1 /* 2 * Copyright 2010-2011 Calxeda, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 #include <linux/module.h> 17 #include <linux/init.h> 18 #include <linux/kernel.h> 19 #include <linux/circ_buf.h> 20 #include <linux/interrupt.h> 21 #include <linux/etherdevice.h> 22 #include <linux/platform_device.h> 23 #include <linux/skbuff.h> 24 #include <linux/ethtool.h> 25 #include <linux/if.h> 26 #include <linux/crc32.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/slab.h> 29 30 /* XGMAC Register definitions */ 31 #define XGMAC_CONTROL 0x00000000 /* MAC Configuration */ 32 #define XGMAC_FRAME_FILTER 0x00000004 /* MAC Frame Filter */ 33 #define XGMAC_FLOW_CTRL 0x00000018 /* MAC Flow Control */ 34 #define XGMAC_VLAN_TAG 0x0000001C /* VLAN Tags */ 35 #define XGMAC_VERSION 0x00000020 /* Version */ 36 #define XGMAC_VLAN_INCL 0x00000024 /* VLAN tag for tx frames */ 37 #define XGMAC_LPI_CTRL 0x00000028 /* LPI Control and Status */ 38 #define XGMAC_LPI_TIMER 0x0000002C /* LPI Timers Control */ 39 #define XGMAC_TX_PACE 0x00000030 /* Transmit Pace and Stretch */ 40 #define XGMAC_VLAN_HASH 0x00000034 /* VLAN Hash Table */ 41 #define XGMAC_DEBUG 0x00000038 /* Debug */ 42 #define XGMAC_INT_STAT 0x0000003C /* Interrupt and Control */ 43 #define XGMAC_ADDR_HIGH(reg) (0x00000040 + ((reg) * 8)) 44 #define XGMAC_ADDR_LOW(reg) (0x00000044 + ((reg) * 8)) 45 #define XGMAC_HASH(n) (0x00000300 + (n) * 4) /* HASH table regs */ 46 #define XGMAC_NUM_HASH 16 47 #define XGMAC_OMR 0x00000400 48 #define XGMAC_REMOTE_WAKE 0x00000700 /* Remote Wake-Up Frm Filter */ 49 #define XGMAC_PMT 0x00000704 /* PMT Control and Status */ 50 #define XGMAC_MMC_CTRL 0x00000800 /* XGMAC MMC Control */ 51 #define XGMAC_MMC_INTR_RX 0x00000804 /* Recieve Interrupt */ 52 #define XGMAC_MMC_INTR_TX 0x00000808 /* Transmit Interrupt */ 53 #define XGMAC_MMC_INTR_MASK_RX 0x0000080c /* Recieve Interrupt Mask */ 54 #define XGMAC_MMC_INTR_MASK_TX 0x00000810 /* Transmit Interrupt Mask */ 55 56 /* Hardware TX Statistics Counters */ 57 #define XGMAC_MMC_TXOCTET_GB_LO 0x00000814 58 #define XGMAC_MMC_TXOCTET_GB_HI 0x00000818 59 #define XGMAC_MMC_TXFRAME_GB_LO 0x0000081C 60 #define XGMAC_MMC_TXFRAME_GB_HI 0x00000820 61 #define XGMAC_MMC_TXBCFRAME_G 0x00000824 62 #define XGMAC_MMC_TXMCFRAME_G 0x0000082C 63 #define XGMAC_MMC_TXUCFRAME_GB 0x00000864 64 #define XGMAC_MMC_TXMCFRAME_GB 0x0000086C 65 #define XGMAC_MMC_TXBCFRAME_GB 0x00000874 66 #define XGMAC_MMC_TXUNDERFLOW 0x0000087C 67 #define XGMAC_MMC_TXOCTET_G_LO 0x00000884 68 #define XGMAC_MMC_TXOCTET_G_HI 0x00000888 69 #define XGMAC_MMC_TXFRAME_G_LO 0x0000088C 70 #define XGMAC_MMC_TXFRAME_G_HI 0x00000890 71 #define XGMAC_MMC_TXPAUSEFRAME 0x00000894 72 #define XGMAC_MMC_TXVLANFRAME 0x0000089C 73 74 /* Hardware RX Statistics Counters */ 75 #define XGMAC_MMC_RXFRAME_GB_LO 0x00000900 76 #define XGMAC_MMC_RXFRAME_GB_HI 0x00000904 77 #define XGMAC_MMC_RXOCTET_GB_LO 0x00000908 78 #define XGMAC_MMC_RXOCTET_GB_HI 0x0000090C 79 #define XGMAC_MMC_RXOCTET_G_LO 0x00000910 80 #define XGMAC_MMC_RXOCTET_G_HI 0x00000914 81 #define XGMAC_MMC_RXBCFRAME_G 0x00000918 82 #define XGMAC_MMC_RXMCFRAME_G 0x00000920 83 #define XGMAC_MMC_RXCRCERR 0x00000928 84 #define XGMAC_MMC_RXRUNT 0x00000930 85 #define XGMAC_MMC_RXJABBER 0x00000934 86 #define XGMAC_MMC_RXUCFRAME_G 0x00000970 87 #define XGMAC_MMC_RXLENGTHERR 0x00000978 88 #define XGMAC_MMC_RXPAUSEFRAME 0x00000988 89 #define XGMAC_MMC_RXOVERFLOW 0x00000990 90 #define XGMAC_MMC_RXVLANFRAME 0x00000998 91 #define XGMAC_MMC_RXWATCHDOG 0x000009a0 92 93 /* DMA Control and Status Registers */ 94 #define XGMAC_DMA_BUS_MODE 0x00000f00 /* Bus Mode */ 95 #define XGMAC_DMA_TX_POLL 0x00000f04 /* Transmit Poll Demand */ 96 #define XGMAC_DMA_RX_POLL 0x00000f08 /* Received Poll Demand */ 97 #define XGMAC_DMA_RX_BASE_ADDR 0x00000f0c /* Receive List Base */ 98 #define XGMAC_DMA_TX_BASE_ADDR 0x00000f10 /* Transmit List Base */ 99 #define XGMAC_DMA_STATUS 0x00000f14 /* Status Register */ 100 #define XGMAC_DMA_CONTROL 0x00000f18 /* Ctrl (Operational Mode) */ 101 #define XGMAC_DMA_INTR_ENA 0x00000f1c /* Interrupt Enable */ 102 #define XGMAC_DMA_MISS_FRAME_CTR 0x00000f20 /* Missed Frame Counter */ 103 #define XGMAC_DMA_RI_WDOG_TIMER 0x00000f24 /* RX Intr Watchdog Timer */ 104 #define XGMAC_DMA_AXI_BUS 0x00000f28 /* AXI Bus Mode */ 105 #define XGMAC_DMA_AXI_STATUS 0x00000f2C /* AXI Status */ 106 #define XGMAC_DMA_HW_FEATURE 0x00000f58 /* Enabled Hardware Features */ 107 108 #define XGMAC_ADDR_AE 0x80000000 109 #define XGMAC_MAX_FILTER_ADDR 31 110 111 /* PMT Control and Status */ 112 #define XGMAC_PMT_POINTER_RESET 0x80000000 113 #define XGMAC_PMT_GLBL_UNICAST 0x00000200 114 #define XGMAC_PMT_WAKEUP_RX_FRM 0x00000040 115 #define XGMAC_PMT_MAGIC_PKT 0x00000020 116 #define XGMAC_PMT_WAKEUP_FRM_EN 0x00000004 117 #define XGMAC_PMT_MAGIC_PKT_EN 0x00000002 118 #define XGMAC_PMT_POWERDOWN 0x00000001 119 120 #define XGMAC_CONTROL_SPD 0x40000000 /* Speed control */ 121 #define XGMAC_CONTROL_SPD_MASK 0x60000000 122 #define XGMAC_CONTROL_SPD_1G 0x60000000 123 #define XGMAC_CONTROL_SPD_2_5G 0x40000000 124 #define XGMAC_CONTROL_SPD_10G 0x00000000 125 #define XGMAC_CONTROL_SARC 0x10000000 /* Source Addr Insert/Replace */ 126 #define XGMAC_CONTROL_SARK_MASK 0x18000000 127 #define XGMAC_CONTROL_CAR 0x04000000 /* CRC Addition/Replacement */ 128 #define XGMAC_CONTROL_CAR_MASK 0x06000000 129 #define XGMAC_CONTROL_DP 0x01000000 /* Disable Padding */ 130 #define XGMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on rx */ 131 #define XGMAC_CONTROL_JD 0x00400000 /* Jabber disable */ 132 #define XGMAC_CONTROL_JE 0x00100000 /* Jumbo frame */ 133 #define XGMAC_CONTROL_LM 0x00001000 /* Loop-back mode */ 134 #define XGMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */ 135 #define XGMAC_CONTROL_ACS 0x00000080 /* Automatic Pad/FCS Strip */ 136 #define XGMAC_CONTROL_DDIC 0x00000010 /* Disable Deficit Idle Count */ 137 #define XGMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */ 138 #define XGMAC_CONTROL_RE 0x00000004 /* Receiver Enable */ 139 140 /* XGMAC Frame Filter defines */ 141 #define XGMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */ 142 #define XGMAC_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */ 143 #define XGMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */ 144 #define XGMAC_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */ 145 #define XGMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */ 146 #define XGMAC_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */ 147 #define XGMAC_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */ 148 #define XGMAC_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */ 149 #define XGMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */ 150 #define XGMAC_FRAME_FILTER_VHF 0x00000800 /* VLAN Hash Filter */ 151 #define XGMAC_FRAME_FILTER_VPF 0x00001000 /* VLAN Perfect Filter */ 152 #define XGMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */ 153 154 /* XGMAC FLOW CTRL defines */ 155 #define XGMAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */ 156 #define XGMAC_FLOW_CTRL_PT_SHIFT 16 157 #define XGMAC_FLOW_CTRL_DZQP 0x00000080 /* Disable Zero-Quanta Phase */ 158 #define XGMAC_FLOW_CTRL_PLT 0x00000020 /* Pause Low Threshhold */ 159 #define XGMAC_FLOW_CTRL_PLT_MASK 0x00000030 /* PLT MASK */ 160 #define XGMAC_FLOW_CTRL_UP 0x00000008 /* Unicast Pause Frame Detect */ 161 #define XGMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */ 162 #define XGMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */ 163 #define XGMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */ 164 165 /* XGMAC_INT_STAT reg */ 166 #define XGMAC_INT_STAT_PMT 0x0080 /* PMT Interrupt Status */ 167 #define XGMAC_INT_STAT_LPI 0x0040 /* LPI Interrupt Status */ 168 169 /* DMA Bus Mode register defines */ 170 #define DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */ 171 #define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */ 172 #define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */ 173 #define DMA_BUS_MODE_ATDS 0x00000080 /* Alternate Descriptor Size */ 174 175 /* Programmable burst length */ 176 #define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */ 177 #define DMA_BUS_MODE_PBL_SHIFT 8 178 #define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */ 179 #define DMA_BUS_MODE_RPBL_MASK 0x003e0000 /* Rx-Programmable Burst Len */ 180 #define DMA_BUS_MODE_RPBL_SHIFT 17 181 #define DMA_BUS_MODE_USP 0x00800000 182 #define DMA_BUS_MODE_8PBL 0x01000000 183 #define DMA_BUS_MODE_AAL 0x02000000 184 185 /* DMA Bus Mode register defines */ 186 #define DMA_BUS_PR_RATIO_MASK 0x0000c000 /* Rx/Tx priority ratio */ 187 #define DMA_BUS_PR_RATIO_SHIFT 14 188 #define DMA_BUS_FB 0x00010000 /* Fixed Burst */ 189 190 /* DMA Control register defines */ 191 #define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */ 192 #define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */ 193 #define DMA_CONTROL_DFF 0x01000000 /* Disable flush of rx frames */ 194 #define DMA_CONTROL_OSF 0x00000004 /* Operate on 2nd tx frame */ 195 196 /* DMA Normal interrupt */ 197 #define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */ 198 #define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */ 199 #define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */ 200 #define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */ 201 #define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */ 202 #define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */ 203 #define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */ 204 #define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */ 205 #define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */ 206 #define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */ 207 #define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */ 208 #define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */ 209 #define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavail */ 210 #define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */ 211 #define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */ 212 213 #define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \ 214 DMA_INTR_ENA_TUE | DMA_INTR_ENA_TIE) 215 216 #define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \ 217 DMA_INTR_ENA_RWE | DMA_INTR_ENA_RSE | \ 218 DMA_INTR_ENA_RUE | DMA_INTR_ENA_UNE | \ 219 DMA_INTR_ENA_OVE | DMA_INTR_ENA_TJE | \ 220 DMA_INTR_ENA_TSE) 221 222 /* DMA default interrupt mask */ 223 #define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL) 224 225 /* DMA Status register defines */ 226 #define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */ 227 #define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */ 228 #define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */ 229 #define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */ 230 #define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */ 231 #define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */ 232 #define DMA_STATUS_TS_SHIFT 20 233 #define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */ 234 #define DMA_STATUS_RS_SHIFT 17 235 #define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */ 236 #define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */ 237 #define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */ 238 #define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */ 239 #define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */ 240 #define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */ 241 #define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */ 242 #define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */ 243 #define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */ 244 #define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */ 245 #define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */ 246 #define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */ 247 #define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavail */ 248 #define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */ 249 #define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */ 250 251 /* Common MAC defines */ 252 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */ 253 #define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */ 254 255 /* XGMAC Operation Mode Register */ 256 #define XGMAC_OMR_TSF 0x00200000 /* TX FIFO Store and Forward */ 257 #define XGMAC_OMR_FTF 0x00100000 /* Flush Transmit FIFO */ 258 #define XGMAC_OMR_TTC 0x00020000 /* Transmit Threshhold Ctrl */ 259 #define XGMAC_OMR_TTC_MASK 0x00030000 260 #define XGMAC_OMR_RFD 0x00006000 /* FC Deactivation Threshhold */ 261 #define XGMAC_OMR_RFD_MASK 0x00007000 /* FC Deact Threshhold MASK */ 262 #define XGMAC_OMR_RFA 0x00000600 /* FC Activation Threshhold */ 263 #define XGMAC_OMR_RFA_MASK 0x00000E00 /* FC Act Threshhold MASK */ 264 #define XGMAC_OMR_EFC 0x00000100 /* Enable Hardware FC */ 265 #define XGMAC_OMR_FEF 0x00000080 /* Forward Error Frames */ 266 #define XGMAC_OMR_DT 0x00000040 /* Drop TCP/IP csum Errors */ 267 #define XGMAC_OMR_RSF 0x00000020 /* RX FIFO Store and Forward */ 268 #define XGMAC_OMR_RTC_256 0x00000018 /* RX Threshhold Ctrl */ 269 #define XGMAC_OMR_RTC_MASK 0x00000018 /* RX Threshhold Ctrl MASK */ 270 271 /* XGMAC HW Features Register */ 272 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* TX Checksum offload */ 273 274 #define XGMAC_MMC_CTRL_CNT_FRZ 0x00000008 275 276 /* XGMAC Descriptor Defines */ 277 #define MAX_DESC_BUF_SZ (0x2000 - 8) 278 279 #define RXDESC_EXT_STATUS 0x00000001 280 #define RXDESC_CRC_ERR 0x00000002 281 #define RXDESC_RX_ERR 0x00000008 282 #define RXDESC_RX_WDOG 0x00000010 283 #define RXDESC_FRAME_TYPE 0x00000020 284 #define RXDESC_GIANT_FRAME 0x00000080 285 #define RXDESC_LAST_SEG 0x00000100 286 #define RXDESC_FIRST_SEG 0x00000200 287 #define RXDESC_VLAN_FRAME 0x00000400 288 #define RXDESC_OVERFLOW_ERR 0x00000800 289 #define RXDESC_LENGTH_ERR 0x00001000 290 #define RXDESC_SA_FILTER_FAIL 0x00002000 291 #define RXDESC_DESCRIPTOR_ERR 0x00004000 292 #define RXDESC_ERROR_SUMMARY 0x00008000 293 #define RXDESC_FRAME_LEN_OFFSET 16 294 #define RXDESC_FRAME_LEN_MASK 0x3fff0000 295 #define RXDESC_DA_FILTER_FAIL 0x40000000 296 297 #define RXDESC1_END_RING 0x00008000 298 299 #define RXDESC_IP_PAYLOAD_MASK 0x00000003 300 #define RXDESC_IP_PAYLOAD_UDP 0x00000001 301 #define RXDESC_IP_PAYLOAD_TCP 0x00000002 302 #define RXDESC_IP_PAYLOAD_ICMP 0x00000003 303 #define RXDESC_IP_HEADER_ERR 0x00000008 304 #define RXDESC_IP_PAYLOAD_ERR 0x00000010 305 #define RXDESC_IPV4_PACKET 0x00000040 306 #define RXDESC_IPV6_PACKET 0x00000080 307 #define TXDESC_UNDERFLOW_ERR 0x00000001 308 #define TXDESC_JABBER_TIMEOUT 0x00000002 309 #define TXDESC_LOCAL_FAULT 0x00000004 310 #define TXDESC_REMOTE_FAULT 0x00000008 311 #define TXDESC_VLAN_FRAME 0x00000010 312 #define TXDESC_FRAME_FLUSHED 0x00000020 313 #define TXDESC_IP_HEADER_ERR 0x00000040 314 #define TXDESC_PAYLOAD_CSUM_ERR 0x00000080 315 #define TXDESC_ERROR_SUMMARY 0x00008000 316 #define TXDESC_SA_CTRL_INSERT 0x00040000 317 #define TXDESC_SA_CTRL_REPLACE 0x00080000 318 #define TXDESC_2ND_ADDR_CHAINED 0x00100000 319 #define TXDESC_END_RING 0x00200000 320 #define TXDESC_CSUM_IP 0x00400000 321 #define TXDESC_CSUM_IP_PAYLD 0x00800000 322 #define TXDESC_CSUM_ALL 0x00C00000 323 #define TXDESC_CRC_EN_REPLACE 0x01000000 324 #define TXDESC_CRC_EN_APPEND 0x02000000 325 #define TXDESC_DISABLE_PAD 0x04000000 326 #define TXDESC_FIRST_SEG 0x10000000 327 #define TXDESC_LAST_SEG 0x20000000 328 #define TXDESC_INTERRUPT 0x40000000 329 330 #define DESC_OWN 0x80000000 331 #define DESC_BUFFER1_SZ_MASK 0x00001fff 332 #define DESC_BUFFER2_SZ_MASK 0x1fff0000 333 #define DESC_BUFFER2_SZ_OFFSET 16 334 335 struct xgmac_dma_desc { 336 __le32 flags; 337 __le32 buf_size; 338 __le32 buf1_addr; /* Buffer 1 Address Pointer */ 339 __le32 buf2_addr; /* Buffer 2 Address Pointer */ 340 __le32 ext_status; 341 __le32 res[3]; 342 }; 343 344 struct xgmac_extra_stats { 345 /* Transmit errors */ 346 unsigned long tx_jabber; 347 unsigned long tx_frame_flushed; 348 unsigned long tx_payload_error; 349 unsigned long tx_ip_header_error; 350 unsigned long tx_local_fault; 351 unsigned long tx_remote_fault; 352 /* Receive errors */ 353 unsigned long rx_watchdog; 354 unsigned long rx_da_filter_fail; 355 unsigned long rx_sa_filter_fail; 356 unsigned long rx_payload_error; 357 unsigned long rx_ip_header_error; 358 /* Tx/Rx IRQ errors */ 359 unsigned long tx_undeflow; 360 unsigned long tx_process_stopped; 361 unsigned long rx_buf_unav; 362 unsigned long rx_process_stopped; 363 unsigned long tx_early; 364 unsigned long fatal_bus_error; 365 }; 366 367 struct xgmac_priv { 368 struct xgmac_dma_desc *dma_rx; 369 struct sk_buff **rx_skbuff; 370 unsigned int rx_tail; 371 unsigned int rx_head; 372 373 struct xgmac_dma_desc *dma_tx; 374 struct sk_buff **tx_skbuff; 375 unsigned int tx_head; 376 unsigned int tx_tail; 377 int tx_irq_cnt; 378 379 void __iomem *base; 380 unsigned int dma_buf_sz; 381 dma_addr_t dma_rx_phy; 382 dma_addr_t dma_tx_phy; 383 384 struct net_device *dev; 385 struct device *device; 386 struct napi_struct napi; 387 388 struct xgmac_extra_stats xstats; 389 390 spinlock_t stats_lock; 391 int pmt_irq; 392 char rx_pause; 393 char tx_pause; 394 int wolopts; 395 }; 396 397 /* XGMAC Configuration Settings */ 398 #define MAX_MTU 9000 399 #define PAUSE_TIME 0x400 400 401 #define DMA_RX_RING_SZ 256 402 #define DMA_TX_RING_SZ 128 403 /* minimum number of free TX descriptors required to wake up TX process */ 404 #define TX_THRESH (DMA_TX_RING_SZ/4) 405 406 /* DMA descriptor ring helpers */ 407 #define dma_ring_incr(n, s) (((n) + 1) & ((s) - 1)) 408 #define dma_ring_space(h, t, s) CIRC_SPACE(h, t, s) 409 #define dma_ring_cnt(h, t, s) CIRC_CNT(h, t, s) 410 411 /* XGMAC Descriptor Access Helpers */ 412 static inline void desc_set_buf_len(struct xgmac_dma_desc *p, u32 buf_sz) 413 { 414 if (buf_sz > MAX_DESC_BUF_SZ) 415 p->buf_size = cpu_to_le32(MAX_DESC_BUF_SZ | 416 (buf_sz - MAX_DESC_BUF_SZ) << DESC_BUFFER2_SZ_OFFSET); 417 else 418 p->buf_size = cpu_to_le32(buf_sz); 419 } 420 421 static inline int desc_get_buf_len(struct xgmac_dma_desc *p) 422 { 423 u32 len = cpu_to_le32(p->flags); 424 return (len & DESC_BUFFER1_SZ_MASK) + 425 ((len & DESC_BUFFER2_SZ_MASK) >> DESC_BUFFER2_SZ_OFFSET); 426 } 427 428 static inline void desc_init_rx_desc(struct xgmac_dma_desc *p, int ring_size, 429 int buf_sz) 430 { 431 struct xgmac_dma_desc *end = p + ring_size - 1; 432 433 memset(p, 0, sizeof(*p) * ring_size); 434 435 for (; p <= end; p++) 436 desc_set_buf_len(p, buf_sz); 437 438 end->buf_size |= cpu_to_le32(RXDESC1_END_RING); 439 } 440 441 static inline void desc_init_tx_desc(struct xgmac_dma_desc *p, u32 ring_size) 442 { 443 memset(p, 0, sizeof(*p) * ring_size); 444 p[ring_size - 1].flags = cpu_to_le32(TXDESC_END_RING); 445 } 446 447 static inline int desc_get_owner(struct xgmac_dma_desc *p) 448 { 449 return le32_to_cpu(p->flags) & DESC_OWN; 450 } 451 452 static inline void desc_set_rx_owner(struct xgmac_dma_desc *p) 453 { 454 /* Clear all fields and set the owner */ 455 p->flags = cpu_to_le32(DESC_OWN); 456 } 457 458 static inline void desc_set_tx_owner(struct xgmac_dma_desc *p, u32 flags) 459 { 460 u32 tmpflags = le32_to_cpu(p->flags); 461 tmpflags &= TXDESC_END_RING; 462 tmpflags |= flags | DESC_OWN; 463 p->flags = cpu_to_le32(tmpflags); 464 } 465 466 static inline int desc_get_tx_ls(struct xgmac_dma_desc *p) 467 { 468 return le32_to_cpu(p->flags) & TXDESC_LAST_SEG; 469 } 470 471 static inline u32 desc_get_buf_addr(struct xgmac_dma_desc *p) 472 { 473 return le32_to_cpu(p->buf1_addr); 474 } 475 476 static inline void desc_set_buf_addr(struct xgmac_dma_desc *p, 477 u32 paddr, int len) 478 { 479 p->buf1_addr = cpu_to_le32(paddr); 480 if (len > MAX_DESC_BUF_SZ) 481 p->buf2_addr = cpu_to_le32(paddr + MAX_DESC_BUF_SZ); 482 } 483 484 static inline void desc_set_buf_addr_and_size(struct xgmac_dma_desc *p, 485 u32 paddr, int len) 486 { 487 desc_set_buf_len(p, len); 488 desc_set_buf_addr(p, paddr, len); 489 } 490 491 static inline int desc_get_rx_frame_len(struct xgmac_dma_desc *p) 492 { 493 u32 data = le32_to_cpu(p->flags); 494 u32 len = (data & RXDESC_FRAME_LEN_MASK) >> RXDESC_FRAME_LEN_OFFSET; 495 if (data & RXDESC_FRAME_TYPE) 496 len -= ETH_FCS_LEN; 497 498 return len; 499 } 500 501 static void xgmac_dma_flush_tx_fifo(void __iomem *ioaddr) 502 { 503 int timeout = 1000; 504 u32 reg = readl(ioaddr + XGMAC_OMR); 505 writel(reg | XGMAC_OMR_FTF, ioaddr + XGMAC_OMR); 506 507 while ((timeout-- > 0) && readl(ioaddr + XGMAC_OMR) & XGMAC_OMR_FTF) 508 udelay(1); 509 } 510 511 static int desc_get_tx_status(struct xgmac_priv *priv, struct xgmac_dma_desc *p) 512 { 513 struct xgmac_extra_stats *x = &priv->xstats; 514 u32 status = le32_to_cpu(p->flags); 515 516 if (!(status & TXDESC_ERROR_SUMMARY)) 517 return 0; 518 519 netdev_dbg(priv->dev, "tx desc error = 0x%08x\n", status); 520 if (status & TXDESC_JABBER_TIMEOUT) 521 x->tx_jabber++; 522 if (status & TXDESC_FRAME_FLUSHED) 523 x->tx_frame_flushed++; 524 if (status & TXDESC_UNDERFLOW_ERR) 525 xgmac_dma_flush_tx_fifo(priv->base); 526 if (status & TXDESC_IP_HEADER_ERR) 527 x->tx_ip_header_error++; 528 if (status & TXDESC_LOCAL_FAULT) 529 x->tx_local_fault++; 530 if (status & TXDESC_REMOTE_FAULT) 531 x->tx_remote_fault++; 532 if (status & TXDESC_PAYLOAD_CSUM_ERR) 533 x->tx_payload_error++; 534 535 return -1; 536 } 537 538 static int desc_get_rx_status(struct xgmac_priv *priv, struct xgmac_dma_desc *p) 539 { 540 struct xgmac_extra_stats *x = &priv->xstats; 541 int ret = CHECKSUM_UNNECESSARY; 542 u32 status = le32_to_cpu(p->flags); 543 u32 ext_status = le32_to_cpu(p->ext_status); 544 545 if (status & RXDESC_DA_FILTER_FAIL) { 546 netdev_dbg(priv->dev, "XGMAC RX : Dest Address filter fail\n"); 547 x->rx_da_filter_fail++; 548 return -1; 549 } 550 551 /* Check if packet has checksum already */ 552 if ((status & RXDESC_FRAME_TYPE) && (status & RXDESC_EXT_STATUS) && 553 !(ext_status & RXDESC_IP_PAYLOAD_MASK)) 554 ret = CHECKSUM_NONE; 555 556 netdev_dbg(priv->dev, "rx status - frame type=%d, csum = %d, ext stat %08x\n", 557 (status & RXDESC_FRAME_TYPE) ? 1 : 0, ret, ext_status); 558 559 if (!(status & RXDESC_ERROR_SUMMARY)) 560 return ret; 561 562 /* Handle any errors */ 563 if (status & (RXDESC_DESCRIPTOR_ERR | RXDESC_OVERFLOW_ERR | 564 RXDESC_GIANT_FRAME | RXDESC_LENGTH_ERR | RXDESC_CRC_ERR)) 565 return -1; 566 567 if (status & RXDESC_EXT_STATUS) { 568 if (ext_status & RXDESC_IP_HEADER_ERR) 569 x->rx_ip_header_error++; 570 if (ext_status & RXDESC_IP_PAYLOAD_ERR) 571 x->rx_payload_error++; 572 netdev_dbg(priv->dev, "IP checksum error - stat %08x\n", 573 ext_status); 574 return CHECKSUM_NONE; 575 } 576 577 return ret; 578 } 579 580 static inline void xgmac_mac_enable(void __iomem *ioaddr) 581 { 582 u32 value = readl(ioaddr + XGMAC_CONTROL); 583 value |= MAC_ENABLE_RX | MAC_ENABLE_TX; 584 writel(value, ioaddr + XGMAC_CONTROL); 585 586 value = readl(ioaddr + XGMAC_DMA_CONTROL); 587 value |= DMA_CONTROL_ST | DMA_CONTROL_SR; 588 writel(value, ioaddr + XGMAC_DMA_CONTROL); 589 } 590 591 static inline void xgmac_mac_disable(void __iomem *ioaddr) 592 { 593 u32 value = readl(ioaddr + XGMAC_DMA_CONTROL); 594 value &= ~(DMA_CONTROL_ST | DMA_CONTROL_SR); 595 writel(value, ioaddr + XGMAC_DMA_CONTROL); 596 597 value = readl(ioaddr + XGMAC_CONTROL); 598 value &= ~(MAC_ENABLE_TX | MAC_ENABLE_RX); 599 writel(value, ioaddr + XGMAC_CONTROL); 600 } 601 602 static void xgmac_set_mac_addr(void __iomem *ioaddr, unsigned char *addr, 603 int num) 604 { 605 u32 data; 606 607 data = (addr[5] << 8) | addr[4] | (num ? XGMAC_ADDR_AE : 0); 608 writel(data, ioaddr + XGMAC_ADDR_HIGH(num)); 609 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; 610 writel(data, ioaddr + XGMAC_ADDR_LOW(num)); 611 } 612 613 static void xgmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 614 int num) 615 { 616 u32 hi_addr, lo_addr; 617 618 /* Read the MAC address from the hardware */ 619 hi_addr = readl(ioaddr + XGMAC_ADDR_HIGH(num)); 620 lo_addr = readl(ioaddr + XGMAC_ADDR_LOW(num)); 621 622 /* Extract the MAC address from the high and low words */ 623 addr[0] = lo_addr & 0xff; 624 addr[1] = (lo_addr >> 8) & 0xff; 625 addr[2] = (lo_addr >> 16) & 0xff; 626 addr[3] = (lo_addr >> 24) & 0xff; 627 addr[4] = hi_addr & 0xff; 628 addr[5] = (hi_addr >> 8) & 0xff; 629 } 630 631 static int xgmac_set_flow_ctrl(struct xgmac_priv *priv, int rx, int tx) 632 { 633 u32 reg; 634 unsigned int flow = 0; 635 636 priv->rx_pause = rx; 637 priv->tx_pause = tx; 638 639 if (rx || tx) { 640 if (rx) 641 flow |= XGMAC_FLOW_CTRL_RFE; 642 if (tx) 643 flow |= XGMAC_FLOW_CTRL_TFE; 644 645 flow |= XGMAC_FLOW_CTRL_PLT | XGMAC_FLOW_CTRL_UP; 646 flow |= (PAUSE_TIME << XGMAC_FLOW_CTRL_PT_SHIFT); 647 648 writel(flow, priv->base + XGMAC_FLOW_CTRL); 649 650 reg = readl(priv->base + XGMAC_OMR); 651 reg |= XGMAC_OMR_EFC; 652 writel(reg, priv->base + XGMAC_OMR); 653 } else { 654 writel(0, priv->base + XGMAC_FLOW_CTRL); 655 656 reg = readl(priv->base + XGMAC_OMR); 657 reg &= ~XGMAC_OMR_EFC; 658 writel(reg, priv->base + XGMAC_OMR); 659 } 660 661 return 0; 662 } 663 664 static void xgmac_rx_refill(struct xgmac_priv *priv) 665 { 666 struct xgmac_dma_desc *p; 667 dma_addr_t paddr; 668 int bufsz = priv->dev->mtu + ETH_HLEN + ETH_FCS_LEN; 669 670 while (dma_ring_space(priv->rx_head, priv->rx_tail, DMA_RX_RING_SZ) > 1) { 671 int entry = priv->rx_head; 672 struct sk_buff *skb; 673 674 p = priv->dma_rx + entry; 675 676 if (priv->rx_skbuff[entry] == NULL) { 677 skb = netdev_alloc_skb_ip_align(priv->dev, bufsz); 678 if (unlikely(skb == NULL)) 679 break; 680 681 priv->rx_skbuff[entry] = skb; 682 paddr = dma_map_single(priv->device, skb->data, 683 bufsz, DMA_FROM_DEVICE); 684 desc_set_buf_addr(p, paddr, priv->dma_buf_sz); 685 } 686 687 netdev_dbg(priv->dev, "rx ring: head %d, tail %d\n", 688 priv->rx_head, priv->rx_tail); 689 690 priv->rx_head = dma_ring_incr(priv->rx_head, DMA_RX_RING_SZ); 691 desc_set_rx_owner(p); 692 } 693 } 694 695 /** 696 * init_xgmac_dma_desc_rings - init the RX/TX descriptor rings 697 * @dev: net device structure 698 * Description: this function initializes the DMA RX/TX descriptors 699 * and allocates the socket buffers. 700 */ 701 static int xgmac_dma_desc_rings_init(struct net_device *dev) 702 { 703 struct xgmac_priv *priv = netdev_priv(dev); 704 unsigned int bfsize; 705 706 /* Set the Buffer size according to the MTU; 707 * The total buffer size including any IP offset must be a multiple 708 * of 8 bytes. 709 */ 710 bfsize = ALIGN(dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN, 8); 711 712 netdev_dbg(priv->dev, "mtu [%d] bfsize [%d]\n", dev->mtu, bfsize); 713 714 priv->rx_skbuff = kzalloc(sizeof(struct sk_buff *) * DMA_RX_RING_SZ, 715 GFP_KERNEL); 716 if (!priv->rx_skbuff) 717 return -ENOMEM; 718 719 priv->dma_rx = dma_alloc_coherent(priv->device, 720 DMA_RX_RING_SZ * 721 sizeof(struct xgmac_dma_desc), 722 &priv->dma_rx_phy, 723 GFP_KERNEL); 724 if (!priv->dma_rx) 725 goto err_dma_rx; 726 727 priv->tx_skbuff = kzalloc(sizeof(struct sk_buff *) * DMA_TX_RING_SZ, 728 GFP_KERNEL); 729 if (!priv->tx_skbuff) 730 goto err_tx_skb; 731 732 priv->dma_tx = dma_alloc_coherent(priv->device, 733 DMA_TX_RING_SZ * 734 sizeof(struct xgmac_dma_desc), 735 &priv->dma_tx_phy, 736 GFP_KERNEL); 737 if (!priv->dma_tx) 738 goto err_dma_tx; 739 740 netdev_dbg(priv->dev, "DMA desc rings: virt addr (Rx %p, " 741 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n", 742 priv->dma_rx, priv->dma_tx, 743 (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy); 744 745 priv->rx_tail = 0; 746 priv->rx_head = 0; 747 priv->dma_buf_sz = bfsize; 748 desc_init_rx_desc(priv->dma_rx, DMA_RX_RING_SZ, priv->dma_buf_sz); 749 xgmac_rx_refill(priv); 750 751 priv->tx_tail = 0; 752 priv->tx_head = 0; 753 desc_init_tx_desc(priv->dma_tx, DMA_TX_RING_SZ); 754 755 writel(priv->dma_tx_phy, priv->base + XGMAC_DMA_TX_BASE_ADDR); 756 writel(priv->dma_rx_phy, priv->base + XGMAC_DMA_RX_BASE_ADDR); 757 758 return 0; 759 760 err_dma_tx: 761 kfree(priv->tx_skbuff); 762 err_tx_skb: 763 dma_free_coherent(priv->device, 764 DMA_RX_RING_SZ * sizeof(struct xgmac_dma_desc), 765 priv->dma_rx, priv->dma_rx_phy); 766 err_dma_rx: 767 kfree(priv->rx_skbuff); 768 return -ENOMEM; 769 } 770 771 static void xgmac_free_rx_skbufs(struct xgmac_priv *priv) 772 { 773 int i; 774 struct xgmac_dma_desc *p; 775 776 if (!priv->rx_skbuff) 777 return; 778 779 for (i = 0; i < DMA_RX_RING_SZ; i++) { 780 if (priv->rx_skbuff[i] == NULL) 781 continue; 782 783 p = priv->dma_rx + i; 784 dma_unmap_single(priv->device, desc_get_buf_addr(p), 785 priv->dma_buf_sz, DMA_FROM_DEVICE); 786 dev_kfree_skb_any(priv->rx_skbuff[i]); 787 priv->rx_skbuff[i] = NULL; 788 } 789 } 790 791 static void xgmac_free_tx_skbufs(struct xgmac_priv *priv) 792 { 793 int i, f; 794 struct xgmac_dma_desc *p; 795 796 if (!priv->tx_skbuff) 797 return; 798 799 for (i = 0; i < DMA_TX_RING_SZ; i++) { 800 if (priv->tx_skbuff[i] == NULL) 801 continue; 802 803 p = priv->dma_tx + i; 804 dma_unmap_single(priv->device, desc_get_buf_addr(p), 805 desc_get_buf_len(p), DMA_TO_DEVICE); 806 807 for (f = 0; f < skb_shinfo(priv->tx_skbuff[i])->nr_frags; f++) { 808 p = priv->dma_tx + i++; 809 dma_unmap_page(priv->device, desc_get_buf_addr(p), 810 desc_get_buf_len(p), DMA_TO_DEVICE); 811 } 812 813 dev_kfree_skb_any(priv->tx_skbuff[i]); 814 priv->tx_skbuff[i] = NULL; 815 } 816 } 817 818 static void xgmac_free_dma_desc_rings(struct xgmac_priv *priv) 819 { 820 /* Release the DMA TX/RX socket buffers */ 821 xgmac_free_rx_skbufs(priv); 822 xgmac_free_tx_skbufs(priv); 823 824 /* Free the consistent memory allocated for descriptor rings */ 825 if (priv->dma_tx) { 826 dma_free_coherent(priv->device, 827 DMA_TX_RING_SZ * sizeof(struct xgmac_dma_desc), 828 priv->dma_tx, priv->dma_tx_phy); 829 priv->dma_tx = NULL; 830 } 831 if (priv->dma_rx) { 832 dma_free_coherent(priv->device, 833 DMA_RX_RING_SZ * sizeof(struct xgmac_dma_desc), 834 priv->dma_rx, priv->dma_rx_phy); 835 priv->dma_rx = NULL; 836 } 837 kfree(priv->rx_skbuff); 838 priv->rx_skbuff = NULL; 839 kfree(priv->tx_skbuff); 840 priv->tx_skbuff = NULL; 841 } 842 843 /** 844 * xgmac_tx: 845 * @priv: private driver structure 846 * Description: it reclaims resources after transmission completes. 847 */ 848 static void xgmac_tx_complete(struct xgmac_priv *priv) 849 { 850 int i; 851 852 while (dma_ring_cnt(priv->tx_head, priv->tx_tail, DMA_TX_RING_SZ)) { 853 unsigned int entry = priv->tx_tail; 854 struct sk_buff *skb = priv->tx_skbuff[entry]; 855 struct xgmac_dma_desc *p = priv->dma_tx + entry; 856 857 /* Check if the descriptor is owned by the DMA. */ 858 if (desc_get_owner(p)) 859 break; 860 861 /* Verify tx error by looking at the last segment */ 862 if (desc_get_tx_ls(p)) 863 desc_get_tx_status(priv, p); 864 865 netdev_dbg(priv->dev, "tx ring: curr %d, dirty %d\n", 866 priv->tx_head, priv->tx_tail); 867 868 dma_unmap_single(priv->device, desc_get_buf_addr(p), 869 desc_get_buf_len(p), DMA_TO_DEVICE); 870 871 priv->tx_skbuff[entry] = NULL; 872 priv->tx_tail = dma_ring_incr(entry, DMA_TX_RING_SZ); 873 874 if (!skb) { 875 continue; 876 } 877 878 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 879 entry = priv->tx_tail = dma_ring_incr(priv->tx_tail, 880 DMA_TX_RING_SZ); 881 p = priv->dma_tx + priv->tx_tail; 882 883 dma_unmap_page(priv->device, desc_get_buf_addr(p), 884 desc_get_buf_len(p), DMA_TO_DEVICE); 885 } 886 887 dev_kfree_skb(skb); 888 } 889 890 if (dma_ring_space(priv->tx_head, priv->tx_tail, DMA_TX_RING_SZ) > 891 MAX_SKB_FRAGS) 892 netif_wake_queue(priv->dev); 893 } 894 895 /** 896 * xgmac_tx_err: 897 * @priv: pointer to the private device structure 898 * Description: it cleans the descriptors and restarts the transmission 899 * in case of errors. 900 */ 901 static void xgmac_tx_err(struct xgmac_priv *priv) 902 { 903 u32 reg, value, inten; 904 905 netif_stop_queue(priv->dev); 906 907 inten = readl(priv->base + XGMAC_DMA_INTR_ENA); 908 writel(0, priv->base + XGMAC_DMA_INTR_ENA); 909 910 reg = readl(priv->base + XGMAC_DMA_CONTROL); 911 writel(reg & ~DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL); 912 do { 913 value = readl(priv->base + XGMAC_DMA_STATUS) & 0x700000; 914 } while (value && (value != 0x600000)); 915 916 xgmac_free_tx_skbufs(priv); 917 desc_init_tx_desc(priv->dma_tx, DMA_TX_RING_SZ); 918 priv->tx_tail = 0; 919 priv->tx_head = 0; 920 writel(priv->dma_tx_phy, priv->base + XGMAC_DMA_TX_BASE_ADDR); 921 writel(reg | DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL); 922 923 writel(DMA_STATUS_TU | DMA_STATUS_TPS | DMA_STATUS_NIS | DMA_STATUS_AIS, 924 priv->base + XGMAC_DMA_STATUS); 925 writel(inten, priv->base + XGMAC_DMA_INTR_ENA); 926 927 netif_wake_queue(priv->dev); 928 } 929 930 static int xgmac_hw_init(struct net_device *dev) 931 { 932 u32 value, ctrl; 933 int limit; 934 struct xgmac_priv *priv = netdev_priv(dev); 935 void __iomem *ioaddr = priv->base; 936 937 /* Save the ctrl register value */ 938 ctrl = readl(ioaddr + XGMAC_CONTROL) & XGMAC_CONTROL_SPD_MASK; 939 940 /* SW reset */ 941 value = DMA_BUS_MODE_SFT_RESET; 942 writel(value, ioaddr + XGMAC_DMA_BUS_MODE); 943 limit = 15000; 944 while (limit-- && 945 (readl(ioaddr + XGMAC_DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)) 946 cpu_relax(); 947 if (limit < 0) 948 return -EBUSY; 949 950 value = (0x10 << DMA_BUS_MODE_PBL_SHIFT) | 951 (0x10 << DMA_BUS_MODE_RPBL_SHIFT) | 952 DMA_BUS_MODE_FB | DMA_BUS_MODE_ATDS | DMA_BUS_MODE_AAL; 953 writel(value, ioaddr + XGMAC_DMA_BUS_MODE); 954 955 /* Enable interrupts */ 956 writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_STATUS); 957 writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_INTR_ENA); 958 959 /* XGMAC requires AXI bus init. This is a 'magic number' for now */ 960 writel(0x0077000E, ioaddr + XGMAC_DMA_AXI_BUS); 961 962 ctrl |= XGMAC_CONTROL_DDIC | XGMAC_CONTROL_JE | XGMAC_CONTROL_ACS | 963 XGMAC_CONTROL_CAR; 964 if (dev->features & NETIF_F_RXCSUM) 965 ctrl |= XGMAC_CONTROL_IPC; 966 writel(ctrl, ioaddr + XGMAC_CONTROL); 967 968 writel(DMA_CONTROL_OSF, ioaddr + XGMAC_DMA_CONTROL); 969 970 /* Set the HW DMA mode and the COE */ 971 writel(XGMAC_OMR_TSF | XGMAC_OMR_RFD | XGMAC_OMR_RFA | 972 XGMAC_OMR_RTC_256, 973 ioaddr + XGMAC_OMR); 974 975 /* Reset the MMC counters */ 976 writel(1, ioaddr + XGMAC_MMC_CTRL); 977 return 0; 978 } 979 980 /** 981 * xgmac_open - open entry point of the driver 982 * @dev : pointer to the device structure. 983 * Description: 984 * This function is the open entry point of the driver. 985 * Return value: 986 * 0 on success and an appropriate (-)ve integer as defined in errno.h 987 * file on failure. 988 */ 989 static int xgmac_open(struct net_device *dev) 990 { 991 int ret; 992 struct xgmac_priv *priv = netdev_priv(dev); 993 void __iomem *ioaddr = priv->base; 994 995 /* Check that the MAC address is valid. If its not, refuse 996 * to bring the device up. The user must specify an 997 * address using the following linux command: 998 * ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx */ 999 if (!is_valid_ether_addr(dev->dev_addr)) { 1000 eth_hw_addr_random(dev); 1001 netdev_dbg(priv->dev, "generated random MAC address %pM\n", 1002 dev->dev_addr); 1003 } 1004 1005 memset(&priv->xstats, 0, sizeof(struct xgmac_extra_stats)); 1006 1007 /* Initialize the XGMAC and descriptors */ 1008 xgmac_hw_init(dev); 1009 xgmac_set_mac_addr(ioaddr, dev->dev_addr, 0); 1010 xgmac_set_flow_ctrl(priv, priv->rx_pause, priv->tx_pause); 1011 1012 ret = xgmac_dma_desc_rings_init(dev); 1013 if (ret < 0) 1014 return ret; 1015 1016 /* Enable the MAC Rx/Tx */ 1017 xgmac_mac_enable(ioaddr); 1018 1019 napi_enable(&priv->napi); 1020 netif_start_queue(dev); 1021 1022 return 0; 1023 } 1024 1025 /** 1026 * xgmac_release - close entry point of the driver 1027 * @dev : device pointer. 1028 * Description: 1029 * This is the stop entry point of the driver. 1030 */ 1031 static int xgmac_stop(struct net_device *dev) 1032 { 1033 struct xgmac_priv *priv = netdev_priv(dev); 1034 1035 netif_stop_queue(dev); 1036 1037 if (readl(priv->base + XGMAC_DMA_INTR_ENA)) 1038 napi_disable(&priv->napi); 1039 1040 writel(0, priv->base + XGMAC_DMA_INTR_ENA); 1041 1042 /* Disable the MAC core */ 1043 xgmac_mac_disable(priv->base); 1044 1045 /* Release and free the Rx/Tx resources */ 1046 xgmac_free_dma_desc_rings(priv); 1047 1048 return 0; 1049 } 1050 1051 /** 1052 * xgmac_xmit: 1053 * @skb : the socket buffer 1054 * @dev : device pointer 1055 * Description : Tx entry point of the driver. 1056 */ 1057 static netdev_tx_t xgmac_xmit(struct sk_buff *skb, struct net_device *dev) 1058 { 1059 struct xgmac_priv *priv = netdev_priv(dev); 1060 unsigned int entry; 1061 int i; 1062 u32 irq_flag; 1063 int nfrags = skb_shinfo(skb)->nr_frags; 1064 struct xgmac_dma_desc *desc, *first; 1065 unsigned int desc_flags; 1066 unsigned int len; 1067 dma_addr_t paddr; 1068 1069 priv->tx_irq_cnt = (priv->tx_irq_cnt + 1) & (DMA_TX_RING_SZ/4 - 1); 1070 irq_flag = priv->tx_irq_cnt ? 0 : TXDESC_INTERRUPT; 1071 1072 desc_flags = (skb->ip_summed == CHECKSUM_PARTIAL) ? 1073 TXDESC_CSUM_ALL : 0; 1074 entry = priv->tx_head; 1075 desc = priv->dma_tx + entry; 1076 first = desc; 1077 1078 len = skb_headlen(skb); 1079 paddr = dma_map_single(priv->device, skb->data, len, DMA_TO_DEVICE); 1080 if (dma_mapping_error(priv->device, paddr)) { 1081 dev_kfree_skb(skb); 1082 return -EIO; 1083 } 1084 priv->tx_skbuff[entry] = skb; 1085 desc_set_buf_addr_and_size(desc, paddr, len); 1086 1087 for (i = 0; i < nfrags; i++) { 1088 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1089 1090 len = frag->size; 1091 1092 paddr = skb_frag_dma_map(priv->device, frag, 0, len, 1093 DMA_TO_DEVICE); 1094 if (dma_mapping_error(priv->device, paddr)) { 1095 dev_kfree_skb(skb); 1096 return -EIO; 1097 } 1098 1099 entry = dma_ring_incr(entry, DMA_TX_RING_SZ); 1100 desc = priv->dma_tx + entry; 1101 priv->tx_skbuff[entry] = NULL; 1102 1103 desc_set_buf_addr_and_size(desc, paddr, len); 1104 if (i < (nfrags - 1)) 1105 desc_set_tx_owner(desc, desc_flags); 1106 } 1107 1108 /* Interrupt on completition only for the latest segment */ 1109 if (desc != first) 1110 desc_set_tx_owner(desc, desc_flags | 1111 TXDESC_LAST_SEG | irq_flag); 1112 else 1113 desc_flags |= TXDESC_LAST_SEG | irq_flag; 1114 1115 /* Set owner on first desc last to avoid race condition */ 1116 wmb(); 1117 desc_set_tx_owner(first, desc_flags | TXDESC_FIRST_SEG); 1118 1119 priv->tx_head = dma_ring_incr(entry, DMA_TX_RING_SZ); 1120 1121 writel(1, priv->base + XGMAC_DMA_TX_POLL); 1122 if (dma_ring_space(priv->tx_head, priv->tx_tail, DMA_TX_RING_SZ) < 1123 MAX_SKB_FRAGS) 1124 netif_stop_queue(dev); 1125 1126 return NETDEV_TX_OK; 1127 } 1128 1129 static int xgmac_rx(struct xgmac_priv *priv, int limit) 1130 { 1131 unsigned int entry; 1132 unsigned int count = 0; 1133 struct xgmac_dma_desc *p; 1134 1135 while (count < limit) { 1136 int ip_checksum; 1137 struct sk_buff *skb; 1138 int frame_len; 1139 1140 entry = priv->rx_tail; 1141 p = priv->dma_rx + entry; 1142 if (desc_get_owner(p)) 1143 break; 1144 1145 count++; 1146 priv->rx_tail = dma_ring_incr(priv->rx_tail, DMA_RX_RING_SZ); 1147 1148 /* read the status of the incoming frame */ 1149 ip_checksum = desc_get_rx_status(priv, p); 1150 if (ip_checksum < 0) 1151 continue; 1152 1153 skb = priv->rx_skbuff[entry]; 1154 if (unlikely(!skb)) { 1155 netdev_err(priv->dev, "Inconsistent Rx descriptor chain\n"); 1156 break; 1157 } 1158 priv->rx_skbuff[entry] = NULL; 1159 1160 frame_len = desc_get_rx_frame_len(p); 1161 netdev_dbg(priv->dev, "RX frame size %d, COE status: %d\n", 1162 frame_len, ip_checksum); 1163 1164 skb_put(skb, frame_len); 1165 dma_unmap_single(priv->device, desc_get_buf_addr(p), 1166 frame_len, DMA_FROM_DEVICE); 1167 1168 skb->protocol = eth_type_trans(skb, priv->dev); 1169 skb->ip_summed = ip_checksum; 1170 if (ip_checksum == CHECKSUM_NONE) 1171 netif_receive_skb(skb); 1172 else 1173 napi_gro_receive(&priv->napi, skb); 1174 } 1175 1176 xgmac_rx_refill(priv); 1177 1178 return count; 1179 } 1180 1181 /** 1182 * xgmac_poll - xgmac poll method (NAPI) 1183 * @napi : pointer to the napi structure. 1184 * @budget : maximum number of packets that the current CPU can receive from 1185 * all interfaces. 1186 * Description : 1187 * This function implements the the reception process. 1188 * Also it runs the TX completion thread 1189 */ 1190 static int xgmac_poll(struct napi_struct *napi, int budget) 1191 { 1192 struct xgmac_priv *priv = container_of(napi, 1193 struct xgmac_priv, napi); 1194 int work_done = 0; 1195 1196 xgmac_tx_complete(priv); 1197 work_done = xgmac_rx(priv, budget); 1198 1199 if (work_done < budget) { 1200 napi_complete(napi); 1201 __raw_writel(DMA_INTR_DEFAULT_MASK, priv->base + XGMAC_DMA_INTR_ENA); 1202 } 1203 return work_done; 1204 } 1205 1206 /** 1207 * xgmac_tx_timeout 1208 * @dev : Pointer to net device structure 1209 * Description: this function is called when a packet transmission fails to 1210 * complete within a reasonable tmrate. The driver will mark the error in the 1211 * netdev structure and arrange for the device to be reset to a sane state 1212 * in order to transmit a new packet. 1213 */ 1214 static void xgmac_tx_timeout(struct net_device *dev) 1215 { 1216 struct xgmac_priv *priv = netdev_priv(dev); 1217 1218 /* Clear Tx resources and restart transmitting again */ 1219 xgmac_tx_err(priv); 1220 } 1221 1222 /** 1223 * xgmac_set_rx_mode - entry point for multicast addressing 1224 * @dev : pointer to the device structure 1225 * Description: 1226 * This function is a driver entry point which gets called by the kernel 1227 * whenever multicast addresses must be enabled/disabled. 1228 * Return value: 1229 * void. 1230 */ 1231 static void xgmac_set_rx_mode(struct net_device *dev) 1232 { 1233 int i; 1234 struct xgmac_priv *priv = netdev_priv(dev); 1235 void __iomem *ioaddr = priv->base; 1236 unsigned int value = 0; 1237 u32 hash_filter[XGMAC_NUM_HASH]; 1238 int reg = 1; 1239 struct netdev_hw_addr *ha; 1240 bool use_hash = false; 1241 1242 netdev_dbg(priv->dev, "# mcasts %d, # unicast %d\n", 1243 netdev_mc_count(dev), netdev_uc_count(dev)); 1244 1245 if (dev->flags & IFF_PROMISC) { 1246 writel(XGMAC_FRAME_FILTER_PR, ioaddr + XGMAC_FRAME_FILTER); 1247 return; 1248 } 1249 1250 memset(hash_filter, 0, sizeof(hash_filter)); 1251 1252 if (netdev_uc_count(dev) > XGMAC_MAX_FILTER_ADDR) { 1253 use_hash = true; 1254 value |= XGMAC_FRAME_FILTER_HUC | XGMAC_FRAME_FILTER_HPF; 1255 } 1256 netdev_for_each_uc_addr(ha, dev) { 1257 if (use_hash) { 1258 u32 bit_nr = ~ether_crc(ETH_ALEN, ha->addr) >> 23; 1259 1260 /* The most significant 4 bits determine the register to 1261 * use (H/L) while the other 5 bits determine the bit 1262 * within the register. */ 1263 hash_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 1264 } else { 1265 xgmac_set_mac_addr(ioaddr, ha->addr, reg); 1266 reg++; 1267 } 1268 } 1269 1270 if (dev->flags & IFF_ALLMULTI) { 1271 value |= XGMAC_FRAME_FILTER_PM; 1272 goto out; 1273 } 1274 1275 if ((netdev_mc_count(dev) + reg - 1) > XGMAC_MAX_FILTER_ADDR) { 1276 use_hash = true; 1277 value |= XGMAC_FRAME_FILTER_HMC | XGMAC_FRAME_FILTER_HPF; 1278 } 1279 netdev_for_each_mc_addr(ha, dev) { 1280 if (use_hash) { 1281 u32 bit_nr = ~ether_crc(ETH_ALEN, ha->addr) >> 23; 1282 1283 /* The most significant 4 bits determine the register to 1284 * use (H/L) while the other 5 bits determine the bit 1285 * within the register. */ 1286 hash_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 1287 } else { 1288 xgmac_set_mac_addr(ioaddr, ha->addr, reg); 1289 reg++; 1290 } 1291 } 1292 1293 out: 1294 for (i = 0; i < XGMAC_NUM_HASH; i++) 1295 writel(hash_filter[i], ioaddr + XGMAC_HASH(i)); 1296 1297 writel(value, ioaddr + XGMAC_FRAME_FILTER); 1298 } 1299 1300 /** 1301 * xgmac_change_mtu - entry point to change MTU size for the device. 1302 * @dev : device pointer. 1303 * @new_mtu : the new MTU size for the device. 1304 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 1305 * to drive packet transmission. Ethernet has an MTU of 1500 octets 1306 * (ETH_DATA_LEN). This value can be changed with ifconfig. 1307 * Return value: 1308 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1309 * file on failure. 1310 */ 1311 static int xgmac_change_mtu(struct net_device *dev, int new_mtu) 1312 { 1313 struct xgmac_priv *priv = netdev_priv(dev); 1314 int old_mtu; 1315 1316 if ((new_mtu < 46) || (new_mtu > MAX_MTU)) { 1317 netdev_err(priv->dev, "invalid MTU, max MTU is: %d\n", MAX_MTU); 1318 return -EINVAL; 1319 } 1320 1321 old_mtu = dev->mtu; 1322 dev->mtu = new_mtu; 1323 1324 /* return early if the buffer sizes will not change */ 1325 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN) 1326 return 0; 1327 if (old_mtu == new_mtu) 1328 return 0; 1329 1330 /* Stop everything, get ready to change the MTU */ 1331 if (!netif_running(dev)) 1332 return 0; 1333 1334 /* Bring the interface down and then back up */ 1335 xgmac_stop(dev); 1336 return xgmac_open(dev); 1337 } 1338 1339 static irqreturn_t xgmac_pmt_interrupt(int irq, void *dev_id) 1340 { 1341 u32 intr_status; 1342 struct net_device *dev = (struct net_device *)dev_id; 1343 struct xgmac_priv *priv = netdev_priv(dev); 1344 void __iomem *ioaddr = priv->base; 1345 1346 intr_status = __raw_readl(ioaddr + XGMAC_INT_STAT); 1347 if (intr_status & XGMAC_INT_STAT_PMT) { 1348 netdev_dbg(priv->dev, "received Magic frame\n"); 1349 /* clear the PMT bits 5 and 6 by reading the PMT */ 1350 readl(ioaddr + XGMAC_PMT); 1351 } 1352 return IRQ_HANDLED; 1353 } 1354 1355 static irqreturn_t xgmac_interrupt(int irq, void *dev_id) 1356 { 1357 u32 intr_status; 1358 bool tx_err = false; 1359 struct net_device *dev = (struct net_device *)dev_id; 1360 struct xgmac_priv *priv = netdev_priv(dev); 1361 struct xgmac_extra_stats *x = &priv->xstats; 1362 1363 /* read the status register (CSR5) */ 1364 intr_status = __raw_readl(priv->base + XGMAC_DMA_STATUS); 1365 intr_status &= __raw_readl(priv->base + XGMAC_DMA_INTR_ENA); 1366 __raw_writel(intr_status, priv->base + XGMAC_DMA_STATUS); 1367 1368 /* It displays the DMA process states (CSR5 register) */ 1369 /* ABNORMAL interrupts */ 1370 if (unlikely(intr_status & DMA_STATUS_AIS)) { 1371 if (intr_status & DMA_STATUS_TJT) { 1372 netdev_err(priv->dev, "transmit jabber\n"); 1373 x->tx_jabber++; 1374 } 1375 if (intr_status & DMA_STATUS_RU) 1376 x->rx_buf_unav++; 1377 if (intr_status & DMA_STATUS_RPS) { 1378 netdev_err(priv->dev, "receive process stopped\n"); 1379 x->rx_process_stopped++; 1380 } 1381 if (intr_status & DMA_STATUS_ETI) { 1382 netdev_err(priv->dev, "transmit early interrupt\n"); 1383 x->tx_early++; 1384 } 1385 if (intr_status & DMA_STATUS_TPS) { 1386 netdev_err(priv->dev, "transmit process stopped\n"); 1387 x->tx_process_stopped++; 1388 tx_err = true; 1389 } 1390 if (intr_status & DMA_STATUS_FBI) { 1391 netdev_err(priv->dev, "fatal bus error\n"); 1392 x->fatal_bus_error++; 1393 tx_err = true; 1394 } 1395 1396 if (tx_err) 1397 xgmac_tx_err(priv); 1398 } 1399 1400 /* TX/RX NORMAL interrupts */ 1401 if (intr_status & (DMA_STATUS_RI | DMA_STATUS_TU | DMA_STATUS_TI)) { 1402 __raw_writel(DMA_INTR_ABNORMAL, priv->base + XGMAC_DMA_INTR_ENA); 1403 napi_schedule(&priv->napi); 1404 } 1405 1406 return IRQ_HANDLED; 1407 } 1408 1409 #ifdef CONFIG_NET_POLL_CONTROLLER 1410 /* Polling receive - used by NETCONSOLE and other diagnostic tools 1411 * to allow network I/O with interrupts disabled. */ 1412 static void xgmac_poll_controller(struct net_device *dev) 1413 { 1414 disable_irq(dev->irq); 1415 xgmac_interrupt(dev->irq, dev); 1416 enable_irq(dev->irq); 1417 } 1418 #endif 1419 1420 static struct rtnl_link_stats64 * 1421 xgmac_get_stats64(struct net_device *dev, 1422 struct rtnl_link_stats64 *storage) 1423 { 1424 struct xgmac_priv *priv = netdev_priv(dev); 1425 void __iomem *base = priv->base; 1426 u32 count; 1427 1428 spin_lock_bh(&priv->stats_lock); 1429 writel(XGMAC_MMC_CTRL_CNT_FRZ, base + XGMAC_MMC_CTRL); 1430 1431 storage->rx_bytes = readl(base + XGMAC_MMC_RXOCTET_G_LO); 1432 storage->rx_bytes |= (u64)(readl(base + XGMAC_MMC_RXOCTET_G_HI)) << 32; 1433 1434 storage->rx_packets = readl(base + XGMAC_MMC_RXFRAME_GB_LO); 1435 storage->multicast = readl(base + XGMAC_MMC_RXMCFRAME_G); 1436 storage->rx_crc_errors = readl(base + XGMAC_MMC_RXCRCERR); 1437 storage->rx_length_errors = readl(base + XGMAC_MMC_RXLENGTHERR); 1438 storage->rx_missed_errors = readl(base + XGMAC_MMC_RXOVERFLOW); 1439 1440 storage->tx_bytes = readl(base + XGMAC_MMC_TXOCTET_G_LO); 1441 storage->tx_bytes |= (u64)(readl(base + XGMAC_MMC_TXOCTET_G_HI)) << 32; 1442 1443 count = readl(base + XGMAC_MMC_TXFRAME_GB_LO); 1444 storage->tx_errors = count - readl(base + XGMAC_MMC_TXFRAME_G_LO); 1445 storage->tx_packets = count; 1446 storage->tx_fifo_errors = readl(base + XGMAC_MMC_TXUNDERFLOW); 1447 1448 writel(0, base + XGMAC_MMC_CTRL); 1449 spin_unlock_bh(&priv->stats_lock); 1450 return storage; 1451 } 1452 1453 static int xgmac_set_mac_address(struct net_device *dev, void *p) 1454 { 1455 struct xgmac_priv *priv = netdev_priv(dev); 1456 void __iomem *ioaddr = priv->base; 1457 struct sockaddr *addr = p; 1458 1459 if (!is_valid_ether_addr(addr->sa_data)) 1460 return -EADDRNOTAVAIL; 1461 1462 dev->addr_assign_type &= ~NET_ADDR_RANDOM; 1463 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 1464 1465 xgmac_set_mac_addr(ioaddr, dev->dev_addr, 0); 1466 1467 return 0; 1468 } 1469 1470 static int xgmac_set_features(struct net_device *dev, netdev_features_t features) 1471 { 1472 u32 ctrl; 1473 struct xgmac_priv *priv = netdev_priv(dev); 1474 void __iomem *ioaddr = priv->base; 1475 u32 changed = dev->features ^ features; 1476 1477 if (!(changed & NETIF_F_RXCSUM)) 1478 return 0; 1479 1480 ctrl = readl(ioaddr + XGMAC_CONTROL); 1481 if (features & NETIF_F_RXCSUM) 1482 ctrl |= XGMAC_CONTROL_IPC; 1483 else 1484 ctrl &= ~XGMAC_CONTROL_IPC; 1485 writel(ctrl, ioaddr + XGMAC_CONTROL); 1486 1487 return 0; 1488 } 1489 1490 static const struct net_device_ops xgmac_netdev_ops = { 1491 .ndo_open = xgmac_open, 1492 .ndo_start_xmit = xgmac_xmit, 1493 .ndo_stop = xgmac_stop, 1494 .ndo_change_mtu = xgmac_change_mtu, 1495 .ndo_set_rx_mode = xgmac_set_rx_mode, 1496 .ndo_tx_timeout = xgmac_tx_timeout, 1497 .ndo_get_stats64 = xgmac_get_stats64, 1498 #ifdef CONFIG_NET_POLL_CONTROLLER 1499 .ndo_poll_controller = xgmac_poll_controller, 1500 #endif 1501 .ndo_set_mac_address = xgmac_set_mac_address, 1502 .ndo_set_features = xgmac_set_features, 1503 }; 1504 1505 static int xgmac_ethtool_getsettings(struct net_device *dev, 1506 struct ethtool_cmd *cmd) 1507 { 1508 cmd->autoneg = 0; 1509 cmd->duplex = DUPLEX_FULL; 1510 ethtool_cmd_speed_set(cmd, 10000); 1511 cmd->supported = 0; 1512 cmd->advertising = 0; 1513 cmd->transceiver = XCVR_INTERNAL; 1514 return 0; 1515 } 1516 1517 static void xgmac_get_pauseparam(struct net_device *netdev, 1518 struct ethtool_pauseparam *pause) 1519 { 1520 struct xgmac_priv *priv = netdev_priv(netdev); 1521 1522 pause->rx_pause = priv->rx_pause; 1523 pause->tx_pause = priv->tx_pause; 1524 } 1525 1526 static int xgmac_set_pauseparam(struct net_device *netdev, 1527 struct ethtool_pauseparam *pause) 1528 { 1529 struct xgmac_priv *priv = netdev_priv(netdev); 1530 1531 if (pause->autoneg) 1532 return -EINVAL; 1533 1534 return xgmac_set_flow_ctrl(priv, pause->rx_pause, pause->tx_pause); 1535 } 1536 1537 struct xgmac_stats { 1538 char stat_string[ETH_GSTRING_LEN]; 1539 int stat_offset; 1540 bool is_reg; 1541 }; 1542 1543 #define XGMAC_STAT(m) \ 1544 { #m, offsetof(struct xgmac_priv, xstats.m), false } 1545 #define XGMAC_HW_STAT(m, reg_offset) \ 1546 { #m, reg_offset, true } 1547 1548 static const struct xgmac_stats xgmac_gstrings_stats[] = { 1549 XGMAC_STAT(tx_frame_flushed), 1550 XGMAC_STAT(tx_payload_error), 1551 XGMAC_STAT(tx_ip_header_error), 1552 XGMAC_STAT(tx_local_fault), 1553 XGMAC_STAT(tx_remote_fault), 1554 XGMAC_STAT(tx_early), 1555 XGMAC_STAT(tx_process_stopped), 1556 XGMAC_STAT(tx_jabber), 1557 XGMAC_STAT(rx_buf_unav), 1558 XGMAC_STAT(rx_process_stopped), 1559 XGMAC_STAT(rx_payload_error), 1560 XGMAC_STAT(rx_ip_header_error), 1561 XGMAC_STAT(rx_da_filter_fail), 1562 XGMAC_STAT(rx_sa_filter_fail), 1563 XGMAC_STAT(fatal_bus_error), 1564 XGMAC_HW_STAT(rx_watchdog, XGMAC_MMC_RXWATCHDOG), 1565 XGMAC_HW_STAT(tx_vlan, XGMAC_MMC_TXVLANFRAME), 1566 XGMAC_HW_STAT(rx_vlan, XGMAC_MMC_RXVLANFRAME), 1567 XGMAC_HW_STAT(tx_pause, XGMAC_MMC_TXPAUSEFRAME), 1568 XGMAC_HW_STAT(rx_pause, XGMAC_MMC_RXPAUSEFRAME), 1569 }; 1570 #define XGMAC_STATS_LEN ARRAY_SIZE(xgmac_gstrings_stats) 1571 1572 static void xgmac_get_ethtool_stats(struct net_device *dev, 1573 struct ethtool_stats *dummy, 1574 u64 *data) 1575 { 1576 struct xgmac_priv *priv = netdev_priv(dev); 1577 void *p = priv; 1578 int i; 1579 1580 for (i = 0; i < XGMAC_STATS_LEN; i++) { 1581 if (xgmac_gstrings_stats[i].is_reg) 1582 *data++ = readl(priv->base + 1583 xgmac_gstrings_stats[i].stat_offset); 1584 else 1585 *data++ = *(u32 *)(p + 1586 xgmac_gstrings_stats[i].stat_offset); 1587 } 1588 } 1589 1590 static int xgmac_get_sset_count(struct net_device *netdev, int sset) 1591 { 1592 switch (sset) { 1593 case ETH_SS_STATS: 1594 return XGMAC_STATS_LEN; 1595 default: 1596 return -EINVAL; 1597 } 1598 } 1599 1600 static void xgmac_get_strings(struct net_device *dev, u32 stringset, 1601 u8 *data) 1602 { 1603 int i; 1604 u8 *p = data; 1605 1606 switch (stringset) { 1607 case ETH_SS_STATS: 1608 for (i = 0; i < XGMAC_STATS_LEN; i++) { 1609 memcpy(p, xgmac_gstrings_stats[i].stat_string, 1610 ETH_GSTRING_LEN); 1611 p += ETH_GSTRING_LEN; 1612 } 1613 break; 1614 default: 1615 WARN_ON(1); 1616 break; 1617 } 1618 } 1619 1620 static void xgmac_get_wol(struct net_device *dev, 1621 struct ethtool_wolinfo *wol) 1622 { 1623 struct xgmac_priv *priv = netdev_priv(dev); 1624 1625 if (device_can_wakeup(priv->device)) { 1626 wol->supported = WAKE_MAGIC | WAKE_UCAST; 1627 wol->wolopts = priv->wolopts; 1628 } 1629 } 1630 1631 static int xgmac_set_wol(struct net_device *dev, 1632 struct ethtool_wolinfo *wol) 1633 { 1634 struct xgmac_priv *priv = netdev_priv(dev); 1635 u32 support = WAKE_MAGIC | WAKE_UCAST; 1636 1637 if (!device_can_wakeup(priv->device)) 1638 return -ENOTSUPP; 1639 1640 if (wol->wolopts & ~support) 1641 return -EINVAL; 1642 1643 priv->wolopts = wol->wolopts; 1644 1645 if (wol->wolopts) { 1646 device_set_wakeup_enable(priv->device, 1); 1647 enable_irq_wake(dev->irq); 1648 } else { 1649 device_set_wakeup_enable(priv->device, 0); 1650 disable_irq_wake(dev->irq); 1651 } 1652 1653 return 0; 1654 } 1655 1656 static const struct ethtool_ops xgmac_ethtool_ops = { 1657 .get_settings = xgmac_ethtool_getsettings, 1658 .get_link = ethtool_op_get_link, 1659 .get_pauseparam = xgmac_get_pauseparam, 1660 .set_pauseparam = xgmac_set_pauseparam, 1661 .get_ethtool_stats = xgmac_get_ethtool_stats, 1662 .get_strings = xgmac_get_strings, 1663 .get_wol = xgmac_get_wol, 1664 .set_wol = xgmac_set_wol, 1665 .get_sset_count = xgmac_get_sset_count, 1666 }; 1667 1668 /** 1669 * xgmac_probe 1670 * @pdev: platform device pointer 1671 * Description: the driver is initialized through platform_device. 1672 */ 1673 static int xgmac_probe(struct platform_device *pdev) 1674 { 1675 int ret = 0; 1676 struct resource *res; 1677 struct net_device *ndev = NULL; 1678 struct xgmac_priv *priv = NULL; 1679 u32 uid; 1680 1681 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1682 if (!res) 1683 return -ENODEV; 1684 1685 if (!request_mem_region(res->start, resource_size(res), pdev->name)) 1686 return -EBUSY; 1687 1688 ndev = alloc_etherdev(sizeof(struct xgmac_priv)); 1689 if (!ndev) { 1690 ret = -ENOMEM; 1691 goto err_alloc; 1692 } 1693 1694 SET_NETDEV_DEV(ndev, &pdev->dev); 1695 priv = netdev_priv(ndev); 1696 platform_set_drvdata(pdev, ndev); 1697 ether_setup(ndev); 1698 ndev->netdev_ops = &xgmac_netdev_ops; 1699 SET_ETHTOOL_OPS(ndev, &xgmac_ethtool_ops); 1700 spin_lock_init(&priv->stats_lock); 1701 1702 priv->device = &pdev->dev; 1703 priv->dev = ndev; 1704 priv->rx_pause = 1; 1705 priv->tx_pause = 1; 1706 1707 priv->base = ioremap(res->start, resource_size(res)); 1708 if (!priv->base) { 1709 netdev_err(ndev, "ioremap failed\n"); 1710 ret = -ENOMEM; 1711 goto err_io; 1712 } 1713 1714 uid = readl(priv->base + XGMAC_VERSION); 1715 netdev_info(ndev, "h/w version is 0x%x\n", uid); 1716 1717 writel(0, priv->base + XGMAC_DMA_INTR_ENA); 1718 ndev->irq = platform_get_irq(pdev, 0); 1719 if (ndev->irq == -ENXIO) { 1720 netdev_err(ndev, "No irq resource\n"); 1721 ret = ndev->irq; 1722 goto err_irq; 1723 } 1724 1725 ret = request_irq(ndev->irq, xgmac_interrupt, 0, 1726 dev_name(&pdev->dev), ndev); 1727 if (ret < 0) { 1728 netdev_err(ndev, "Could not request irq %d - ret %d)\n", 1729 ndev->irq, ret); 1730 goto err_irq; 1731 } 1732 1733 priv->pmt_irq = platform_get_irq(pdev, 1); 1734 if (priv->pmt_irq == -ENXIO) { 1735 netdev_err(ndev, "No pmt irq resource\n"); 1736 ret = priv->pmt_irq; 1737 goto err_pmt_irq; 1738 } 1739 1740 ret = request_irq(priv->pmt_irq, xgmac_pmt_interrupt, 0, 1741 dev_name(&pdev->dev), ndev); 1742 if (ret < 0) { 1743 netdev_err(ndev, "Could not request irq %d - ret %d)\n", 1744 priv->pmt_irq, ret); 1745 goto err_pmt_irq; 1746 } 1747 1748 device_set_wakeup_capable(&pdev->dev, 1); 1749 if (device_can_wakeup(priv->device)) 1750 priv->wolopts = WAKE_MAGIC; /* Magic Frame as default */ 1751 1752 ndev->hw_features = NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_HIGHDMA; 1753 if (readl(priv->base + XGMAC_DMA_HW_FEATURE) & DMA_HW_FEAT_TXCOESEL) 1754 ndev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1755 NETIF_F_RXCSUM; 1756 ndev->features |= ndev->hw_features; 1757 ndev->priv_flags |= IFF_UNICAST_FLT; 1758 1759 /* Get the MAC address */ 1760 xgmac_get_mac_addr(priv->base, ndev->dev_addr, 0); 1761 if (!is_valid_ether_addr(ndev->dev_addr)) 1762 netdev_warn(ndev, "MAC address %pM not valid", 1763 ndev->dev_addr); 1764 1765 netif_napi_add(ndev, &priv->napi, xgmac_poll, 64); 1766 ret = register_netdev(ndev); 1767 if (ret) 1768 goto err_reg; 1769 1770 return 0; 1771 1772 err_reg: 1773 netif_napi_del(&priv->napi); 1774 free_irq(priv->pmt_irq, ndev); 1775 err_pmt_irq: 1776 free_irq(ndev->irq, ndev); 1777 err_irq: 1778 iounmap(priv->base); 1779 err_io: 1780 free_netdev(ndev); 1781 err_alloc: 1782 release_mem_region(res->start, resource_size(res)); 1783 platform_set_drvdata(pdev, NULL); 1784 return ret; 1785 } 1786 1787 /** 1788 * xgmac_dvr_remove 1789 * @pdev: platform device pointer 1790 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 1791 * changes the link status, releases the DMA descriptor rings, 1792 * unregisters the MDIO bus and unmaps the allocated memory. 1793 */ 1794 static int xgmac_remove(struct platform_device *pdev) 1795 { 1796 struct net_device *ndev = platform_get_drvdata(pdev); 1797 struct xgmac_priv *priv = netdev_priv(ndev); 1798 struct resource *res; 1799 1800 xgmac_mac_disable(priv->base); 1801 1802 /* Free the IRQ lines */ 1803 free_irq(ndev->irq, ndev); 1804 free_irq(priv->pmt_irq, ndev); 1805 1806 platform_set_drvdata(pdev, NULL); 1807 unregister_netdev(ndev); 1808 netif_napi_del(&priv->napi); 1809 1810 iounmap(priv->base); 1811 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1812 release_mem_region(res->start, resource_size(res)); 1813 1814 free_netdev(ndev); 1815 1816 return 0; 1817 } 1818 1819 #ifdef CONFIG_PM_SLEEP 1820 static void xgmac_pmt(void __iomem *ioaddr, unsigned long mode) 1821 { 1822 unsigned int pmt = 0; 1823 1824 if (mode & WAKE_MAGIC) 1825 pmt |= XGMAC_PMT_POWERDOWN | XGMAC_PMT_MAGIC_PKT; 1826 if (mode & WAKE_UCAST) 1827 pmt |= XGMAC_PMT_POWERDOWN | XGMAC_PMT_GLBL_UNICAST; 1828 1829 writel(pmt, ioaddr + XGMAC_PMT); 1830 } 1831 1832 static int xgmac_suspend(struct device *dev) 1833 { 1834 struct net_device *ndev = platform_get_drvdata(to_platform_device(dev)); 1835 struct xgmac_priv *priv = netdev_priv(ndev); 1836 u32 value; 1837 1838 if (!ndev || !netif_running(ndev)) 1839 return 0; 1840 1841 netif_device_detach(ndev); 1842 napi_disable(&priv->napi); 1843 writel(0, priv->base + XGMAC_DMA_INTR_ENA); 1844 1845 if (device_may_wakeup(priv->device)) { 1846 /* Stop TX/RX DMA Only */ 1847 value = readl(priv->base + XGMAC_DMA_CONTROL); 1848 value &= ~(DMA_CONTROL_ST | DMA_CONTROL_SR); 1849 writel(value, priv->base + XGMAC_DMA_CONTROL); 1850 1851 xgmac_pmt(priv->base, priv->wolopts); 1852 } else 1853 xgmac_mac_disable(priv->base); 1854 1855 return 0; 1856 } 1857 1858 static int xgmac_resume(struct device *dev) 1859 { 1860 struct net_device *ndev = platform_get_drvdata(to_platform_device(dev)); 1861 struct xgmac_priv *priv = netdev_priv(ndev); 1862 void __iomem *ioaddr = priv->base; 1863 1864 if (!netif_running(ndev)) 1865 return 0; 1866 1867 xgmac_pmt(ioaddr, 0); 1868 1869 /* Enable the MAC and DMA */ 1870 xgmac_mac_enable(ioaddr); 1871 writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_STATUS); 1872 writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_INTR_ENA); 1873 1874 netif_device_attach(ndev); 1875 napi_enable(&priv->napi); 1876 1877 return 0; 1878 } 1879 1880 static SIMPLE_DEV_PM_OPS(xgmac_pm_ops, xgmac_suspend, xgmac_resume); 1881 #define XGMAC_PM_OPS (&xgmac_pm_ops) 1882 #else 1883 #define XGMAC_PM_OPS NULL 1884 #endif /* CONFIG_PM_SLEEP */ 1885 1886 static const struct of_device_id xgmac_of_match[] = { 1887 { .compatible = "calxeda,hb-xgmac", }, 1888 {}, 1889 }; 1890 MODULE_DEVICE_TABLE(of, xgmac_of_match); 1891 1892 static struct platform_driver xgmac_driver = { 1893 .driver = { 1894 .name = "calxedaxgmac", 1895 .of_match_table = xgmac_of_match, 1896 }, 1897 .probe = xgmac_probe, 1898 .remove = xgmac_remove, 1899 .driver.pm = XGMAC_PM_OPS, 1900 }; 1901 1902 module_platform_driver(xgmac_driver); 1903 1904 MODULE_AUTHOR("Calxeda, Inc."); 1905 MODULE_DESCRIPTION("Calxeda 10G XGMAC driver"); 1906 MODULE_LICENSE("GPL v2"); 1907