1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Cadence MACB/GEM Ethernet Controller driver 4 * 5 * Copyright (C) 2004-2006 Atmel Corporation 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 #include <linux/circ_buf.h> 10 #include <linux/clk-provider.h> 11 #include <linux/clk.h> 12 #include <linux/crc32.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/etherdevice.h> 16 #include <linux/firmware/xlnx-zynqmp.h> 17 #include <linux/inetdevice.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/iopoll.h> 22 #include <linux/ip.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/moduleparam.h> 26 #include <linux/netdevice.h> 27 #include <linux/of.h> 28 #include <linux/of_mdio.h> 29 #include <linux/of_net.h> 30 #include <linux/phy/phy.h> 31 #include <linux/phylink.h> 32 #include <linux/platform_device.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/ptp_classify.h> 35 #include <linux/reset.h> 36 #include <linux/slab.h> 37 #include <linux/tcp.h> 38 #include <linux/types.h> 39 #include <linux/udp.h> 40 #include <linux/gcd.h> 41 #include <net/pkt_sched.h> 42 #include "macb.h" 43 44 /* This structure is only used for MACB on SiFive FU540 devices */ 45 struct sifive_fu540_macb_mgmt { 46 void __iomem *reg; 47 unsigned long rate; 48 struct clk_hw hw; 49 }; 50 51 #define MACB_RX_BUFFER_SIZE 128 52 #define RX_BUFFER_MULTIPLE 64 /* bytes */ 53 #define RX_BUFFER_MAX (0xFF * RX_BUFFER_MULTIPLE) /* 16320 bytes */ 54 55 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */ 56 #define MIN_RX_RING_SIZE 64 57 #define MAX_RX_RING_SIZE 8192 58 59 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */ 60 #define MIN_TX_RING_SIZE 64 61 #define MAX_TX_RING_SIZE 4096 62 63 /* level of occupied TX descriptors under which we wake up TX process */ 64 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4) 65 66 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR)) 67 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \ 68 | MACB_BIT(ISR_RLE) \ 69 | MACB_BIT(TXERR)) 70 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \ 71 | MACB_BIT(TXUBR)) 72 73 #define MACB_INT_MISC_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(RXUBR) | \ 74 MACB_BIT(ISR_ROVR) | MACB_BIT(HRESP) | \ 75 GEM_BIT(WOL) | MACB_BIT(WOL)) 76 77 /* Max length of transmit frame must be a multiple of 8 bytes */ 78 #define MACB_TX_LEN_ALIGN 8 79 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1))) 80 /* Limit maximum TX length as per Cadence TSO errata. This is to avoid a 81 * false amba_error in TX path from the DMA assuming there is not enough 82 * space in the SRAM (16KB) even when there is. 83 */ 84 #define GEM_MAX_TX_LEN (unsigned int)(0x3FC0) 85 86 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU 87 #define MACB_NETIF_LSO NETIF_F_TSO 88 89 #define MACB_WOL_ENABLED BIT(0) 90 91 #define HS_SPEED_10000M 4 92 #define MACB_SERDES_RATE_10G 1 93 94 /* Graceful stop timeouts in us. We should allow up to 95 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions) 96 */ 97 #define MACB_HALT_TIMEOUT 14000 98 #define MACB_PM_TIMEOUT 100 /* ms */ 99 100 #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */ 101 102 /* DMA buffer descriptor might be different size 103 * depends on hardware configuration: 104 * 105 * 1. dma address width 32 bits: 106 * word 1: 32 bit address of Data Buffer 107 * word 2: control 108 * 109 * 2. dma address width 64 bits: 110 * word 1: 32 bit address of Data Buffer 111 * word 2: control 112 * word 3: upper 32 bit address of Data Buffer 113 * word 4: unused 114 * 115 * 3. dma address width 32 bits with hardware timestamping: 116 * word 1: 32 bit address of Data Buffer 117 * word 2: control 118 * word 3: timestamp word 1 119 * word 4: timestamp word 2 120 * 121 * 4. dma address width 64 bits with hardware timestamping: 122 * word 1: 32 bit address of Data Buffer 123 * word 2: control 124 * word 3: upper 32 bit address of Data Buffer 125 * word 4: unused 126 * word 5: timestamp word 1 127 * word 6: timestamp word 2 128 */ 129 static unsigned int macb_dma_desc_get_size(struct macb *bp) 130 { 131 unsigned int desc_size = sizeof(struct macb_dma_desc); 132 133 if (macb_dma64(bp)) 134 desc_size += sizeof(struct macb_dma_desc_64); 135 if (macb_dma_ptp(bp)) 136 desc_size += sizeof(struct macb_dma_desc_ptp); 137 138 return desc_size; 139 } 140 141 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx) 142 { 143 return desc_idx * (1 + macb_dma64(bp) + macb_dma_ptp(bp)); 144 } 145 146 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc) 147 { 148 return (struct macb_dma_desc_64 *)((void *)desc 149 + sizeof(struct macb_dma_desc)); 150 } 151 152 /* Ring buffer accessors */ 153 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index) 154 { 155 return index & (bp->tx_ring_size - 1); 156 } 157 158 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue, 159 unsigned int index) 160 { 161 index = macb_tx_ring_wrap(queue->bp, index); 162 index = macb_adj_dma_desc_idx(queue->bp, index); 163 return &queue->tx_ring[index]; 164 } 165 166 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue, 167 unsigned int index) 168 { 169 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)]; 170 } 171 172 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index) 173 { 174 dma_addr_t offset; 175 176 offset = macb_tx_ring_wrap(queue->bp, index) * 177 macb_dma_desc_get_size(queue->bp); 178 179 return queue->tx_ring_dma + offset; 180 } 181 182 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index) 183 { 184 return index & (bp->rx_ring_size - 1); 185 } 186 187 static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index) 188 { 189 index = macb_rx_ring_wrap(queue->bp, index); 190 index = macb_adj_dma_desc_idx(queue->bp, index); 191 return &queue->rx_ring[index]; 192 } 193 194 static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index) 195 { 196 return queue->rx_buffers + queue->bp->rx_buffer_size * 197 macb_rx_ring_wrap(queue->bp, index); 198 } 199 200 /* I/O accessors */ 201 static u32 hw_readl_native(struct macb *bp, int offset) 202 { 203 return __raw_readl(bp->regs + offset); 204 } 205 206 static void hw_writel_native(struct macb *bp, int offset, u32 value) 207 { 208 __raw_writel(value, bp->regs + offset); 209 } 210 211 static u32 hw_readl(struct macb *bp, int offset) 212 { 213 return readl_relaxed(bp->regs + offset); 214 } 215 216 static void hw_writel(struct macb *bp, int offset, u32 value) 217 { 218 writel_relaxed(value, bp->regs + offset); 219 } 220 221 /* Find the CPU endianness by using the loopback bit of NCR register. When the 222 * CPU is in big endian we need to program swapped mode for management 223 * descriptor access. 224 */ 225 static bool hw_is_native_io(void __iomem *addr) 226 { 227 u32 value = MACB_BIT(LLB); 228 229 __raw_writel(value, addr + MACB_NCR); 230 value = __raw_readl(addr + MACB_NCR); 231 232 /* Write 0 back to disable everything */ 233 __raw_writel(0, addr + MACB_NCR); 234 235 return value == MACB_BIT(LLB); 236 } 237 238 static bool hw_is_gem(void __iomem *addr, bool native_io) 239 { 240 u32 id; 241 242 if (native_io) 243 id = __raw_readl(addr + MACB_MID); 244 else 245 id = readl_relaxed(addr + MACB_MID); 246 247 return MACB_BFEXT(IDNUM, id) >= 0x2; 248 } 249 250 static void macb_set_hwaddr(struct macb *bp) 251 { 252 u32 bottom; 253 u16 top; 254 255 bottom = get_unaligned_le32(bp->netdev->dev_addr); 256 macb_or_gem_writel(bp, SA1B, bottom); 257 top = get_unaligned_le16(bp->netdev->dev_addr + 4); 258 macb_or_gem_writel(bp, SA1T, top); 259 260 if (gem_has_ptp(bp)) { 261 gem_writel(bp, RXPTPUNI, bottom); 262 gem_writel(bp, TXPTPUNI, bottom); 263 } 264 265 /* Clear unused address register sets */ 266 macb_or_gem_writel(bp, SA2B, 0); 267 macb_or_gem_writel(bp, SA2T, 0); 268 macb_or_gem_writel(bp, SA3B, 0); 269 macb_or_gem_writel(bp, SA3T, 0); 270 macb_or_gem_writel(bp, SA4B, 0); 271 macb_or_gem_writel(bp, SA4T, 0); 272 } 273 274 static void macb_get_hwaddr(struct macb *bp) 275 { 276 u32 bottom; 277 u16 top; 278 u8 addr[6]; 279 int i; 280 281 /* Check all 4 address register for valid address */ 282 for (i = 0; i < 4; i++) { 283 bottom = macb_or_gem_readl(bp, SA1B + i * 8); 284 top = macb_or_gem_readl(bp, SA1T + i * 8); 285 286 addr[0] = bottom & 0xff; 287 addr[1] = (bottom >> 8) & 0xff; 288 addr[2] = (bottom >> 16) & 0xff; 289 addr[3] = (bottom >> 24) & 0xff; 290 addr[4] = top & 0xff; 291 addr[5] = (top >> 8) & 0xff; 292 293 if (is_valid_ether_addr(addr)) { 294 eth_hw_addr_set(bp->netdev, addr); 295 return; 296 } 297 } 298 299 dev_info(&bp->pdev->dev, "invalid hw address, using random\n"); 300 eth_hw_addr_random(bp->netdev); 301 } 302 303 static int macb_mdio_wait_for_idle(struct macb *bp) 304 { 305 u32 val; 306 307 return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE), 308 1, MACB_MDIO_TIMEOUT); 309 } 310 311 static int macb_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum) 312 { 313 struct macb *bp = bus->priv; 314 int status; 315 316 status = pm_runtime_resume_and_get(&bp->pdev->dev); 317 if (status < 0) 318 goto mdio_pm_exit; 319 320 status = macb_mdio_wait_for_idle(bp); 321 if (status < 0) 322 goto mdio_read_exit; 323 324 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF) 325 | MACB_BF(RW, MACB_MAN_C22_READ) 326 | MACB_BF(PHYA, mii_id) 327 | MACB_BF(REGA, regnum) 328 | MACB_BF(CODE, MACB_MAN_C22_CODE))); 329 330 status = macb_mdio_wait_for_idle(bp); 331 if (status < 0) 332 goto mdio_read_exit; 333 334 status = MACB_BFEXT(DATA, macb_readl(bp, MAN)); 335 336 mdio_read_exit: 337 pm_runtime_put_autosuspend(&bp->pdev->dev); 338 mdio_pm_exit: 339 return status; 340 } 341 342 static int macb_mdio_read_c45(struct mii_bus *bus, int mii_id, int devad, 343 int regnum) 344 { 345 struct macb *bp = bus->priv; 346 int status; 347 348 status = pm_runtime_get_sync(&bp->pdev->dev); 349 if (status < 0) { 350 pm_runtime_put_noidle(&bp->pdev->dev); 351 goto mdio_pm_exit; 352 } 353 354 status = macb_mdio_wait_for_idle(bp); 355 if (status < 0) 356 goto mdio_read_exit; 357 358 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF) 359 | MACB_BF(RW, MACB_MAN_C45_ADDR) 360 | MACB_BF(PHYA, mii_id) 361 | MACB_BF(REGA, devad & 0x1F) 362 | MACB_BF(DATA, regnum & 0xFFFF) 363 | MACB_BF(CODE, MACB_MAN_C45_CODE))); 364 365 status = macb_mdio_wait_for_idle(bp); 366 if (status < 0) 367 goto mdio_read_exit; 368 369 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF) 370 | MACB_BF(RW, MACB_MAN_C45_READ) 371 | MACB_BF(PHYA, mii_id) 372 | MACB_BF(REGA, devad & 0x1F) 373 | MACB_BF(CODE, MACB_MAN_C45_CODE))); 374 375 status = macb_mdio_wait_for_idle(bp); 376 if (status < 0) 377 goto mdio_read_exit; 378 379 status = MACB_BFEXT(DATA, macb_readl(bp, MAN)); 380 381 mdio_read_exit: 382 pm_runtime_put_autosuspend(&bp->pdev->dev); 383 mdio_pm_exit: 384 return status; 385 } 386 387 static int macb_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, 388 u16 value) 389 { 390 struct macb *bp = bus->priv; 391 int status; 392 393 status = pm_runtime_resume_and_get(&bp->pdev->dev); 394 if (status < 0) 395 goto mdio_pm_exit; 396 397 status = macb_mdio_wait_for_idle(bp); 398 if (status < 0) 399 goto mdio_write_exit; 400 401 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF) 402 | MACB_BF(RW, MACB_MAN_C22_WRITE) 403 | MACB_BF(PHYA, mii_id) 404 | MACB_BF(REGA, regnum) 405 | MACB_BF(CODE, MACB_MAN_C22_CODE) 406 | MACB_BF(DATA, value))); 407 408 status = macb_mdio_wait_for_idle(bp); 409 if (status < 0) 410 goto mdio_write_exit; 411 412 mdio_write_exit: 413 pm_runtime_put_autosuspend(&bp->pdev->dev); 414 mdio_pm_exit: 415 return status; 416 } 417 418 static int macb_mdio_write_c45(struct mii_bus *bus, int mii_id, 419 int devad, int regnum, 420 u16 value) 421 { 422 struct macb *bp = bus->priv; 423 int status; 424 425 status = pm_runtime_get_sync(&bp->pdev->dev); 426 if (status < 0) { 427 pm_runtime_put_noidle(&bp->pdev->dev); 428 goto mdio_pm_exit; 429 } 430 431 status = macb_mdio_wait_for_idle(bp); 432 if (status < 0) 433 goto mdio_write_exit; 434 435 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF) 436 | MACB_BF(RW, MACB_MAN_C45_ADDR) 437 | MACB_BF(PHYA, mii_id) 438 | MACB_BF(REGA, devad & 0x1F) 439 | MACB_BF(DATA, regnum & 0xFFFF) 440 | MACB_BF(CODE, MACB_MAN_C45_CODE))); 441 442 status = macb_mdio_wait_for_idle(bp); 443 if (status < 0) 444 goto mdio_write_exit; 445 446 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF) 447 | MACB_BF(RW, MACB_MAN_C45_WRITE) 448 | MACB_BF(PHYA, mii_id) 449 | MACB_BF(REGA, devad & 0x1F) 450 | MACB_BF(CODE, MACB_MAN_C45_CODE) 451 | MACB_BF(DATA, value))); 452 453 status = macb_mdio_wait_for_idle(bp); 454 if (status < 0) 455 goto mdio_write_exit; 456 457 mdio_write_exit: 458 pm_runtime_put_autosuspend(&bp->pdev->dev); 459 mdio_pm_exit: 460 return status; 461 } 462 463 static void macb_init_buffers(struct macb *bp) 464 { 465 struct macb_queue *queue; 466 unsigned int q; 467 468 /* Single register for all queues' high 32 bits. */ 469 if (macb_dma64(bp)) { 470 macb_writel(bp, RBQPH, 471 upper_32_bits(bp->queues[0].rx_ring_dma)); 472 macb_writel(bp, TBQPH, 473 upper_32_bits(bp->queues[0].tx_ring_dma)); 474 } 475 476 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 477 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma)); 478 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma)); 479 } 480 } 481 482 /** 483 * macb_set_tx_clk() - Set a clock to a new frequency 484 * @bp: pointer to struct macb 485 * @speed: New frequency in Hz 486 */ 487 static void macb_set_tx_clk(struct macb *bp, int speed) 488 { 489 long ferr, rate, rate_rounded; 490 491 if (!bp->tx_clk || (bp->caps & MACB_CAPS_CLK_HW_CHG)) 492 return; 493 494 /* In case of MII the PHY is the clock master */ 495 if (bp->phy_interface == PHY_INTERFACE_MODE_MII) 496 return; 497 498 rate = rgmii_clock(speed); 499 if (rate < 0) 500 return; 501 502 rate_rounded = clk_round_rate(bp->tx_clk, rate); 503 if (rate_rounded < 0) 504 return; 505 506 /* RGMII allows 50 ppm frequency error. Test and warn if this limit 507 * is not satisfied. 508 */ 509 ferr = abs(rate_rounded - rate); 510 ferr = DIV_ROUND_UP(ferr, rate / 100000); 511 if (ferr > 5) 512 netdev_warn(bp->netdev, 513 "unable to generate target frequency: %ld Hz\n", 514 rate); 515 516 if (clk_set_rate(bp->tx_clk, rate_rounded)) 517 netdev_err(bp->netdev, "adjusting tx_clk failed.\n"); 518 } 519 520 static void macb_usx_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode, 521 phy_interface_t interface, int speed, 522 int duplex) 523 { 524 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs); 525 u32 config; 526 527 config = gem_readl(bp, USX_CONTROL); 528 config = GEM_BFINS(SERDES_RATE, MACB_SERDES_RATE_10G, config); 529 config = GEM_BFINS(USX_CTRL_SPEED, HS_SPEED_10000M, config); 530 config &= ~(GEM_BIT(TX_SCR_BYPASS) | GEM_BIT(RX_SCR_BYPASS)); 531 config |= GEM_BIT(TX_EN); 532 gem_writel(bp, USX_CONTROL, config); 533 } 534 535 static void macb_usx_pcs_get_state(struct phylink_pcs *pcs, 536 unsigned int neg_mode, 537 struct phylink_link_state *state) 538 { 539 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs); 540 u32 val; 541 542 state->speed = SPEED_10000; 543 state->duplex = 1; 544 state->an_complete = 1; 545 546 val = gem_readl(bp, USX_STATUS); 547 state->link = !!(val & GEM_BIT(USX_BLOCK_LOCK)); 548 val = gem_readl(bp, NCFGR); 549 if (val & GEM_BIT(PAE)) 550 state->pause = MLO_PAUSE_RX; 551 } 552 553 static int macb_usx_pcs_config(struct phylink_pcs *pcs, 554 unsigned int neg_mode, 555 phy_interface_t interface, 556 const unsigned long *advertising, 557 bool permit_pause_to_mac) 558 { 559 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs); 560 561 gem_writel(bp, USX_CONTROL, gem_readl(bp, USX_CONTROL) | 562 GEM_BIT(SIGNAL_OK)); 563 564 return 0; 565 } 566 567 static unsigned int macb_pcs_inband_caps(struct phylink_pcs *pcs, 568 phy_interface_t interface) 569 { 570 return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; 571 } 572 573 static void macb_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, 574 struct phylink_link_state *state) 575 { 576 struct macb *bp = container_of(pcs, struct macb, phylink_sgmii_pcs); 577 u16 bmsr, lpa; 578 579 bmsr = gem_readl(bp, PCSSTS); 580 lpa = gem_readl(bp, PCSANLPBASE); 581 phylink_mii_c22_pcs_decode_state(state, neg_mode, bmsr, lpa); 582 } 583 584 static void macb_pcs_an_restart(struct phylink_pcs *pcs) 585 { 586 /* Not supported */ 587 } 588 589 static int macb_pcs_config(struct phylink_pcs *pcs, 590 unsigned int neg_mode, 591 phy_interface_t interface, 592 const unsigned long *advertising, 593 bool permit_pause_to_mac) 594 { 595 struct macb *bp = container_of(pcs, struct macb, phylink_sgmii_pcs); 596 u32 old, new; 597 598 old = gem_readl(bp, PCSANADV); 599 new = phylink_mii_c22_pcs_encode_advertisement(interface, advertising); 600 if (new != -EINVAL && old != new) 601 gem_writel(bp, PCSANADV, new); 602 603 /* Disable AN if it's not to be used, enable otherwise. 604 * Must be written after PCSSEL is set in NCFGR which is done in 605 * macb_mac_config(), otherwise writes will not take effect. 606 */ 607 old = gem_readl(bp, PCSCNTRL); 608 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) 609 new = old | BMCR_ANENABLE; 610 else 611 new = old & ~BMCR_ANENABLE; 612 if (old != new) 613 gem_writel(bp, PCSCNTRL, new); 614 615 return 0; 616 } 617 618 static const struct phylink_pcs_ops macb_phylink_usx_pcs_ops = { 619 .pcs_get_state = macb_usx_pcs_get_state, 620 .pcs_config = macb_usx_pcs_config, 621 .pcs_link_up = macb_usx_pcs_link_up, 622 }; 623 624 static const struct phylink_pcs_ops macb_phylink_pcs_ops = { 625 .pcs_inband_caps = macb_pcs_inband_caps, 626 .pcs_get_state = macb_pcs_get_state, 627 .pcs_an_restart = macb_pcs_an_restart, 628 .pcs_config = macb_pcs_config, 629 }; 630 631 static bool macb_tx_lpi_set(struct macb *bp, bool enable) 632 { 633 u32 old, ncr; 634 635 lockdep_assert_held(&bp->lock); 636 637 ncr = macb_readl(bp, NCR); 638 old = ncr; 639 if (enable) 640 ncr |= GEM_BIT(TXLPIEN); 641 else 642 ncr &= ~GEM_BIT(TXLPIEN); 643 if (old != ncr) 644 macb_writel(bp, NCR, ncr); 645 646 return old != ncr; 647 } 648 649 static bool macb_tx_all_queues_idle(struct macb *bp) 650 { 651 struct macb_queue *queue; 652 unsigned int q; 653 654 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 655 if (READ_ONCE(queue->tx_head) != READ_ONCE(queue->tx_tail)) 656 return false; 657 } 658 return true; 659 } 660 661 static void macb_tx_lpi_work_fn(struct work_struct *work) 662 { 663 struct macb *bp = container_of(work, struct macb, tx_lpi_work.work); 664 unsigned long flags; 665 666 spin_lock_irqsave(&bp->lock, flags); 667 if (bp->eee_active && macb_tx_all_queues_idle(bp)) 668 macb_tx_lpi_set(bp, true); 669 spin_unlock_irqrestore(&bp->lock, flags); 670 } 671 672 static void macb_tx_lpi_schedule(struct macb *bp) 673 { 674 if (bp->eee_active) 675 mod_delayed_work(system_wq, &bp->tx_lpi_work, 676 usecs_to_jiffies(bp->tx_lpi_timer)); 677 } 678 679 /* Wake from LPI before transmitting. The MAC must deassert TXLPIEN 680 * and wait for the PHY to exit LPI before any frame can be sent. 681 * IEEE 802.3az Tw_sys is ~17us for 1000BASE-T, ~30us for 100BASE-TX; 682 * we use a conservative 50us. 683 */ 684 static void macb_tx_lpi_wake(struct macb *bp) 685 { 686 lockdep_assert_held(&bp->lock); 687 688 if (!bp->eee_active) 689 return; 690 691 if (!macb_tx_lpi_set(bp, false)) 692 return; 693 694 cancel_delayed_work(&bp->tx_lpi_work); 695 udelay(50); 696 } 697 698 static void macb_mac_disable_tx_lpi(struct phylink_config *config) 699 { 700 struct net_device *netdev = to_net_dev(config->dev); 701 struct macb *bp = netdev_priv(netdev); 702 unsigned long flags; 703 704 cancel_delayed_work_sync(&bp->tx_lpi_work); 705 706 spin_lock_irqsave(&bp->lock, flags); 707 bp->eee_active = false; 708 macb_tx_lpi_set(bp, false); 709 spin_unlock_irqrestore(&bp->lock, flags); 710 } 711 712 static int macb_mac_enable_tx_lpi(struct phylink_config *config, u32 timer, 713 bool tx_clk_stop) 714 { 715 struct net_device *netdev = to_net_dev(config->dev); 716 struct macb *bp = netdev_priv(netdev); 717 unsigned long flags; 718 719 spin_lock_irqsave(&bp->lock, flags); 720 bp->tx_lpi_timer = timer; 721 bp->eee_active = true; 722 spin_unlock_irqrestore(&bp->lock, flags); 723 724 /* Defer initial LPI entry by 1 second after link-up per 725 * IEEE 802.3az section 22.7a. 726 */ 727 mod_delayed_work(system_wq, &bp->tx_lpi_work, msecs_to_jiffies(1000)); 728 729 return 0; 730 } 731 732 static void macb_mac_config(struct phylink_config *config, unsigned int mode, 733 const struct phylink_link_state *state) 734 { 735 struct net_device *netdev = to_net_dev(config->dev); 736 struct macb *bp = netdev_priv(netdev); 737 unsigned long flags; 738 u32 old_ctrl, ctrl; 739 u32 old_ncr, ncr; 740 741 spin_lock_irqsave(&bp->lock, flags); 742 743 old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR); 744 old_ncr = ncr = macb_or_gem_readl(bp, NCR); 745 746 if (bp->caps & MACB_CAPS_MACB_IS_EMAC) { 747 if (state->interface == PHY_INTERFACE_MODE_RMII) 748 ctrl |= MACB_BIT(RM9200_RMII); 749 } else if (macb_is_gem(bp)) { 750 ctrl &= ~(GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL)); 751 ncr &= ~GEM_BIT(ENABLE_HS_MAC); 752 753 if (state->interface == PHY_INTERFACE_MODE_SGMII) { 754 ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL); 755 } else if (state->interface == PHY_INTERFACE_MODE_10GBASER) { 756 ctrl |= GEM_BIT(PCSSEL); 757 ncr |= GEM_BIT(ENABLE_HS_MAC); 758 } else if (bp->caps & MACB_CAPS_MIIONRGMII && 759 bp->phy_interface == PHY_INTERFACE_MODE_MII) { 760 ncr |= MACB_BIT(MIIONRGMII); 761 } 762 } 763 764 /* Apply the new configuration, if any */ 765 if (old_ctrl ^ ctrl) 766 macb_or_gem_writel(bp, NCFGR, ctrl); 767 768 if (old_ncr ^ ncr) 769 macb_or_gem_writel(bp, NCR, ncr); 770 771 spin_unlock_irqrestore(&bp->lock, flags); 772 } 773 774 static void macb_mac_link_down(struct phylink_config *config, unsigned int mode, 775 phy_interface_t interface) 776 { 777 struct net_device *netdev = to_net_dev(config->dev); 778 struct macb *bp = netdev_priv(netdev); 779 struct macb_queue *queue; 780 unsigned int q; 781 u32 ctrl; 782 783 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) 784 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) 785 queue_writel(queue, IDR, 786 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP)); 787 788 /* Disable Rx and Tx */ 789 ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE)); 790 macb_writel(bp, NCR, ctrl); 791 792 netif_tx_stop_all_queues(netdev); 793 } 794 795 /* Use juggling algorithm to left rotate tx ring and tx skb array */ 796 static void gem_shuffle_tx_one_ring(struct macb_queue *queue) 797 { 798 unsigned int head, tail, count, ring_size, desc_size; 799 struct macb_tx_skb tx_skb, *skb_curr, *skb_next; 800 struct macb_dma_desc *desc_curr, *desc_next; 801 unsigned int i, cycles, shift, curr, next; 802 struct macb *bp = queue->bp; 803 unsigned char desc[24]; 804 unsigned long flags; 805 806 desc_size = macb_dma_desc_get_size(bp); 807 808 if (WARN_ON_ONCE(desc_size > ARRAY_SIZE(desc))) 809 return; 810 811 spin_lock_irqsave(&queue->tx_ptr_lock, flags); 812 head = queue->tx_head; 813 tail = queue->tx_tail; 814 ring_size = bp->tx_ring_size; 815 count = CIRC_CNT(head, tail, ring_size); 816 817 if (!(tail % ring_size)) 818 goto unlock; 819 820 if (!count) { 821 queue->tx_head = 0; 822 queue->tx_tail = 0; 823 goto unlock; 824 } 825 826 shift = tail % ring_size; 827 cycles = gcd(ring_size, shift); 828 829 for (i = 0; i < cycles; i++) { 830 memcpy(&desc, macb_tx_desc(queue, i), desc_size); 831 memcpy(&tx_skb, macb_tx_skb(queue, i), 832 sizeof(struct macb_tx_skb)); 833 834 curr = i; 835 next = (curr + shift) % ring_size; 836 837 while (next != i) { 838 desc_curr = macb_tx_desc(queue, curr); 839 desc_next = macb_tx_desc(queue, next); 840 841 memcpy(desc_curr, desc_next, desc_size); 842 843 if (next == ring_size - 1) 844 desc_curr->ctrl &= ~MACB_BIT(TX_WRAP); 845 if (curr == ring_size - 1) 846 desc_curr->ctrl |= MACB_BIT(TX_WRAP); 847 848 skb_curr = macb_tx_skb(queue, curr); 849 skb_next = macb_tx_skb(queue, next); 850 memcpy(skb_curr, skb_next, sizeof(struct macb_tx_skb)); 851 852 curr = next; 853 next = (curr + shift) % ring_size; 854 } 855 856 desc_curr = macb_tx_desc(queue, curr); 857 memcpy(desc_curr, &desc, desc_size); 858 if (i == ring_size - 1) 859 desc_curr->ctrl &= ~MACB_BIT(TX_WRAP); 860 if (curr == ring_size - 1) 861 desc_curr->ctrl |= MACB_BIT(TX_WRAP); 862 memcpy(macb_tx_skb(queue, curr), &tx_skb, 863 sizeof(struct macb_tx_skb)); 864 } 865 866 queue->tx_head = count; 867 queue->tx_tail = 0; 868 869 /* Make descriptor updates visible to hardware */ 870 wmb(); 871 872 unlock: 873 spin_unlock_irqrestore(&queue->tx_ptr_lock, flags); 874 } 875 876 /* Rotate the queue so that the tail is at index 0 */ 877 static void gem_shuffle_tx_rings(struct macb *bp) 878 { 879 struct macb_queue *queue; 880 unsigned int q; 881 882 for (q = 0, queue = bp->queues; q < bp->num_queues; q++, queue++) 883 gem_shuffle_tx_one_ring(queue); 884 } 885 886 static void macb_mac_link_up(struct phylink_config *config, 887 struct phy_device *phydev, 888 unsigned int mode, phy_interface_t interface, 889 int speed, int duplex, 890 bool tx_pause, bool rx_pause) 891 { 892 struct net_device *netdev = to_net_dev(config->dev); 893 struct macb *bp = netdev_priv(netdev); 894 struct macb_queue *queue; 895 unsigned long flags; 896 unsigned int q; 897 u32 ctrl; 898 899 spin_lock_irqsave(&bp->lock, flags); 900 901 ctrl = macb_or_gem_readl(bp, NCFGR); 902 903 ctrl &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); 904 905 if (speed == SPEED_100) 906 ctrl |= MACB_BIT(SPD); 907 908 if (duplex) 909 ctrl |= MACB_BIT(FD); 910 911 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) { 912 ctrl &= ~MACB_BIT(PAE); 913 if (macb_is_gem(bp)) { 914 ctrl &= ~GEM_BIT(GBE); 915 916 if (speed == SPEED_1000) 917 ctrl |= GEM_BIT(GBE); 918 } 919 920 if (rx_pause) 921 ctrl |= MACB_BIT(PAE); 922 923 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 924 queue_writel(queue, IER, 925 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP)); 926 } 927 } 928 929 macb_or_gem_writel(bp, NCFGR, ctrl); 930 931 if (bp->phy_interface == PHY_INTERFACE_MODE_10GBASER) 932 gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_10000M, 933 gem_readl(bp, HS_MAC_CONFIG))); 934 935 spin_unlock_irqrestore(&bp->lock, flags); 936 937 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) { 938 macb_set_tx_clk(bp, speed); 939 gem_shuffle_tx_rings(bp); 940 } 941 942 /* Enable Rx and Tx; Enable PTP unicast */ 943 ctrl = macb_readl(bp, NCR); 944 if (gem_has_ptp(bp)) 945 ctrl |= MACB_BIT(PTPUNI); 946 947 macb_writel(bp, NCR, ctrl | MACB_BIT(RE) | MACB_BIT(TE)); 948 949 netif_tx_wake_all_queues(netdev); 950 } 951 952 static struct phylink_pcs *macb_mac_select_pcs(struct phylink_config *config, 953 phy_interface_t interface) 954 { 955 struct net_device *netdev = to_net_dev(config->dev); 956 struct macb *bp = netdev_priv(netdev); 957 958 if (interface == PHY_INTERFACE_MODE_10GBASER) 959 return &bp->phylink_usx_pcs; 960 else if (interface == PHY_INTERFACE_MODE_SGMII) 961 return &bp->phylink_sgmii_pcs; 962 else 963 return NULL; 964 } 965 966 static const struct phylink_mac_ops macb_phylink_ops = { 967 .mac_select_pcs = macb_mac_select_pcs, 968 .mac_config = macb_mac_config, 969 .mac_link_down = macb_mac_link_down, 970 .mac_link_up = macb_mac_link_up, 971 .mac_disable_tx_lpi = macb_mac_disable_tx_lpi, 972 .mac_enable_tx_lpi = macb_mac_enable_tx_lpi, 973 }; 974 975 static bool macb_phy_handle_exists(struct device_node *dn) 976 { 977 dn = of_parse_phandle(dn, "phy-handle", 0); 978 of_node_put(dn); 979 return dn != NULL; 980 } 981 982 static int macb_phylink_connect(struct macb *bp) 983 { 984 struct device_node *dn = bp->pdev->dev.of_node; 985 struct net_device *netdev = bp->netdev; 986 struct phy_device *phydev; 987 int ret; 988 989 if (dn) 990 ret = phylink_of_phy_connect(bp->phylink, dn, 0); 991 992 if (!dn || (ret && !macb_phy_handle_exists(dn))) { 993 phydev = phy_find_first(bp->mii_bus); 994 if (!phydev) { 995 netdev_err(netdev, "no PHY found\n"); 996 return -ENXIO; 997 } 998 999 /* attach the mac to the phy */ 1000 ret = phylink_connect_phy(bp->phylink, phydev); 1001 } 1002 1003 if (ret) { 1004 netdev_err(netdev, "Could not attach PHY (%d)\n", ret); 1005 return ret; 1006 } 1007 1008 phylink_start(bp->phylink); 1009 1010 return 0; 1011 } 1012 1013 static void macb_get_pcs_fixed_state(struct phylink_config *config, 1014 struct phylink_link_state *state) 1015 { 1016 struct net_device *netdev = to_net_dev(config->dev); 1017 struct macb *bp = netdev_priv(netdev); 1018 1019 state->link = (macb_readl(bp, NSR) & MACB_BIT(NSR_LINK)) != 0; 1020 } 1021 1022 /* based on au1000_eth. c*/ 1023 static int macb_mii_probe(struct net_device *netdev) 1024 { 1025 struct macb *bp = netdev_priv(netdev); 1026 1027 bp->phylink_sgmii_pcs.ops = &macb_phylink_pcs_ops; 1028 bp->phylink_usx_pcs.ops = &macb_phylink_usx_pcs_ops; 1029 1030 bp->phylink_config.dev = &netdev->dev; 1031 bp->phylink_config.type = PHYLINK_NETDEV; 1032 bp->phylink_config.mac_managed_pm = true; 1033 1034 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1035 bp->phylink_config.poll_fixed_state = true; 1036 bp->phylink_config.get_fixed_state = macb_get_pcs_fixed_state; 1037 /* The PCSAUTONEG bit in PCSCNTRL is on out of reset. Setting 1038 * default_an_inband to true tells phylink to turn it off only 1039 * if necessary (e.g. a fixed link or a PHY that doesn't support 1040 * inband). 1041 */ 1042 bp->phylink_config.default_an_inband = true; 1043 } 1044 1045 bp->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | 1046 MAC_10 | MAC_100; 1047 1048 __set_bit(PHY_INTERFACE_MODE_MII, 1049 bp->phylink_config.supported_interfaces); 1050 __set_bit(PHY_INTERFACE_MODE_RMII, 1051 bp->phylink_config.supported_interfaces); 1052 1053 /* Determine what modes are supported */ 1054 if (macb_is_gem(bp) && (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)) { 1055 bp->phylink_config.mac_capabilities |= MAC_1000FD; 1056 if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF)) 1057 bp->phylink_config.mac_capabilities |= MAC_1000HD; 1058 1059 __set_bit(PHY_INTERFACE_MODE_GMII, 1060 bp->phylink_config.supported_interfaces); 1061 phy_interface_set_rgmii(bp->phylink_config.supported_interfaces); 1062 1063 if (bp->caps & MACB_CAPS_PCS) 1064 __set_bit(PHY_INTERFACE_MODE_SGMII, 1065 bp->phylink_config.supported_interfaces); 1066 1067 if (bp->caps & MACB_CAPS_HIGH_SPEED) { 1068 __set_bit(PHY_INTERFACE_MODE_10GBASER, 1069 bp->phylink_config.supported_interfaces); 1070 bp->phylink_config.mac_capabilities |= MAC_10000FD; 1071 } 1072 } 1073 1074 /* Configure EEE LPI if supported */ 1075 if (bp->caps & MACB_CAPS_EEE) { 1076 __set_bit(PHY_INTERFACE_MODE_MII, 1077 bp->phylink_config.lpi_interfaces); 1078 __set_bit(PHY_INTERFACE_MODE_GMII, 1079 bp->phylink_config.lpi_interfaces); 1080 phy_interface_set_rgmii(bp->phylink_config.lpi_interfaces); 1081 bp->phylink_config.lpi_capabilities = MAC_100FD | MAC_1000FD; 1082 bp->phylink_config.lpi_timer_default = 250000; 1083 bp->phylink_config.eee_enabled_default = true; 1084 } 1085 1086 bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode, 1087 bp->phy_interface, &macb_phylink_ops); 1088 if (IS_ERR(bp->phylink)) { 1089 netdev_err(netdev, "Could not create a phylink instance (%ld)\n", 1090 PTR_ERR(bp->phylink)); 1091 return PTR_ERR(bp->phylink); 1092 } 1093 1094 return 0; 1095 } 1096 1097 static int macb_mdiobus_register(struct macb *bp, struct device_node *mdio_np) 1098 { 1099 struct device_node *child, *np = bp->pdev->dev.of_node; 1100 1101 /* If we have a child named mdio, probe it instead of looking for PHYs 1102 * directly under the MAC node 1103 */ 1104 if (mdio_np) 1105 return of_mdiobus_register(bp->mii_bus, mdio_np); 1106 1107 /* Only create the PHY from the device tree if at least one PHY is 1108 * described. Otherwise scan the entire MDIO bus. We do this to support 1109 * old device tree that did not follow the best practices and did not 1110 * describe their network PHYs. 1111 */ 1112 for_each_available_child_of_node(np, child) 1113 if (of_mdiobus_child_is_phy(child)) { 1114 /* The loop increments the child refcount, 1115 * decrement it before returning. 1116 */ 1117 of_node_put(child); 1118 1119 return of_mdiobus_register(bp->mii_bus, np); 1120 } 1121 1122 return mdiobus_register(bp->mii_bus); 1123 } 1124 1125 static int macb_mii_init(struct macb *bp) 1126 { 1127 struct device_node *mdio_np, *np = bp->pdev->dev.of_node; 1128 int err = -ENXIO; 1129 1130 /* With fixed-link, we don't need to register the MDIO bus, 1131 * except if we have a child named "mdio" in the device tree. 1132 * In that case, some devices may be attached to the MACB's MDIO bus. 1133 */ 1134 mdio_np = of_get_child_by_name(np, "mdio"); 1135 if (!mdio_np && of_phy_is_fixed_link(np)) 1136 return macb_mii_probe(bp->netdev); 1137 1138 /* Enable management port */ 1139 macb_writel(bp, NCR, MACB_BIT(MPE)); 1140 1141 bp->mii_bus = mdiobus_alloc(); 1142 if (!bp->mii_bus) { 1143 err = -ENOMEM; 1144 goto err_out; 1145 } 1146 1147 bp->mii_bus->name = "MACB_mii_bus"; 1148 bp->mii_bus->read = &macb_mdio_read_c22; 1149 bp->mii_bus->write = &macb_mdio_write_c22; 1150 bp->mii_bus->read_c45 = &macb_mdio_read_c45; 1151 bp->mii_bus->write_c45 = &macb_mdio_write_c45; 1152 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1153 bp->pdev->name, bp->pdev->id); 1154 bp->mii_bus->priv = bp; 1155 bp->mii_bus->parent = &bp->pdev->dev; 1156 1157 dev_set_drvdata(&bp->netdev->dev, bp->mii_bus); 1158 1159 err = macb_mdiobus_register(bp, mdio_np); 1160 if (err) 1161 goto err_out_free_mdiobus; 1162 1163 err = macb_mii_probe(bp->netdev); 1164 if (err) 1165 goto err_out_unregister_bus; 1166 1167 return 0; 1168 1169 err_out_unregister_bus: 1170 mdiobus_unregister(bp->mii_bus); 1171 err_out_free_mdiobus: 1172 mdiobus_free(bp->mii_bus); 1173 err_out: 1174 of_node_put(mdio_np); 1175 1176 return err; 1177 } 1178 1179 static void macb_update_stats(struct macb *bp) 1180 { 1181 u64 *p = &bp->hw_stats.macb.rx_pause_frames; 1182 u64 *end = &bp->hw_stats.macb.tx_pause_frames + 1; 1183 int offset = MACB_PFR; 1184 1185 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4); 1186 1187 for (; p < end; p++, offset += 4) 1188 *p += bp->macb_reg_readl(bp, offset); 1189 } 1190 1191 static int macb_halt_tx(struct macb *bp) 1192 { 1193 u32 status; 1194 1195 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT)); 1196 1197 /* Poll TSR until TGO is cleared or timeout. */ 1198 return read_poll_timeout_atomic(macb_readl, status, 1199 !(status & MACB_BIT(TGO)), 1200 250, MACB_HALT_TIMEOUT, false, 1201 bp, TSR); 1202 } 1203 1204 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb, int budget) 1205 { 1206 if (tx_skb->mapping) { 1207 if (tx_skb->mapped_as_page) 1208 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping, 1209 tx_skb->size, DMA_TO_DEVICE); 1210 else 1211 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, 1212 tx_skb->size, DMA_TO_DEVICE); 1213 tx_skb->mapping = 0; 1214 } 1215 1216 if (tx_skb->skb) { 1217 dev_consume_skb_any(tx_skb->skb); 1218 tx_skb->skb = NULL; 1219 } 1220 } 1221 1222 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr) 1223 { 1224 if (macb_dma64(bp)) { 1225 struct macb_dma_desc_64 *desc_64; 1226 1227 desc_64 = macb_64b_desc(bp, desc); 1228 desc_64->addrh = upper_32_bits(addr); 1229 /* The low bits of RX address contain the RX_USED bit, clearing 1230 * of which allows packet RX. Make sure the high bits are also 1231 * visible to HW at that point. 1232 */ 1233 dma_wmb(); 1234 } 1235 1236 desc->addr = lower_32_bits(addr); 1237 } 1238 1239 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc) 1240 { 1241 dma_addr_t addr = 0; 1242 1243 if (macb_dma64(bp)) { 1244 struct macb_dma_desc_64 *desc_64; 1245 1246 desc_64 = macb_64b_desc(bp, desc); 1247 addr = ((u64)(desc_64->addrh) << 32); 1248 } 1249 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr)); 1250 if (macb_dma_ptp(bp)) 1251 addr &= ~GEM_BIT(DMA_RXVALID); 1252 return addr; 1253 } 1254 1255 static void macb_tx_error_task(struct work_struct *work) 1256 { 1257 struct macb_queue *queue = container_of(work, struct macb_queue, 1258 tx_error_task); 1259 unsigned int q = queue - queue->bp->queues; 1260 struct macb *bp = queue->bp; 1261 struct macb_tx_skb *tx_skb; 1262 struct macb_dma_desc *desc; 1263 bool halt_timeout = false; 1264 struct sk_buff *skb; 1265 unsigned long flags; 1266 unsigned int tail; 1267 u32 packets = 0; 1268 u32 bytes = 0; 1269 1270 netdev_vdbg(bp->netdev, "%s: q = %u, t = %u, h = %u\n", 1271 __func__, q, queue->tx_tail, queue->tx_head); 1272 1273 /* Prevent the queue NAPI TX poll from running, as it calls 1274 * macb_tx_complete(), which in turn may call netif_wake_subqueue(). 1275 * As explained below, we have to halt the transmission before updating 1276 * TBQP registers so we call netif_tx_stop_all_queues() to notify the 1277 * network engine about the macb/gem being halted. 1278 */ 1279 napi_disable(&queue->napi_tx); 1280 spin_lock_irqsave(&bp->lock, flags); 1281 1282 /* Make sure nobody is trying to queue up new packets */ 1283 netif_tx_stop_all_queues(bp->netdev); 1284 1285 /* Stop transmission now 1286 * (in case we have just queued new packets) 1287 * macb/gem must be halted to write TBQP register 1288 */ 1289 if (macb_halt_tx(bp)) { 1290 netdev_err(bp->netdev, "BUG: halt tx timed out\n"); 1291 macb_writel(bp, NCR, macb_readl(bp, NCR) & (~MACB_BIT(TE))); 1292 halt_timeout = true; 1293 } 1294 1295 /* Treat frames in TX queue including the ones that caused the error. 1296 * Free transmit buffers in upper layer. 1297 */ 1298 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) { 1299 u32 ctrl; 1300 1301 desc = macb_tx_desc(queue, tail); 1302 ctrl = desc->ctrl; 1303 tx_skb = macb_tx_skb(queue, tail); 1304 skb = tx_skb->skb; 1305 1306 if (ctrl & MACB_BIT(TX_USED)) { 1307 /* skb is set for the last buffer of the frame */ 1308 while (!skb) { 1309 macb_tx_unmap(bp, tx_skb, 0); 1310 tail++; 1311 tx_skb = macb_tx_skb(queue, tail); 1312 skb = tx_skb->skb; 1313 } 1314 1315 /* ctrl still refers to the first buffer descriptor 1316 * since it's the only one written back by the hardware 1317 */ 1318 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) { 1319 netdev_vdbg(bp->netdev, "txerr skb %u (data %p) TX complete\n", 1320 macb_tx_ring_wrap(bp, tail), 1321 skb->data); 1322 bp->netdev->stats.tx_packets++; 1323 queue->stats.tx_packets++; 1324 packets++; 1325 bp->netdev->stats.tx_bytes += skb->len - tx_skb->fcs_len; 1326 queue->stats.tx_bytes += skb->len - tx_skb->fcs_len; 1327 bytes += skb->len; 1328 } 1329 } else { 1330 /* "Buffers exhausted mid-frame" errors may only happen 1331 * if the driver is buggy, so complain loudly about 1332 * those. Statistics are updated by hardware. 1333 */ 1334 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED)) 1335 netdev_err(bp->netdev, 1336 "BUG: TX buffers exhausted mid-frame\n"); 1337 1338 desc->ctrl = ctrl | MACB_BIT(TX_USED); 1339 } 1340 1341 macb_tx_unmap(bp, tx_skb, 0); 1342 } 1343 1344 netdev_tx_completed_queue(netdev_get_tx_queue(bp->netdev, q), 1345 packets, bytes); 1346 1347 /* Set end of TX queue */ 1348 desc = macb_tx_desc(queue, 0); 1349 macb_set_addr(bp, desc, 0); 1350 desc->ctrl = MACB_BIT(TX_USED); 1351 1352 /* Make descriptor updates visible to hardware */ 1353 wmb(); 1354 1355 /* Reinitialize the TX desc queue */ 1356 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma)); 1357 /* Make TX ring reflect state of hardware */ 1358 queue->tx_head = 0; 1359 queue->tx_tail = 0; 1360 1361 /* Housework before enabling TX IRQ */ 1362 macb_writel(bp, TSR, macb_readl(bp, TSR)); 1363 queue_writel(queue, IER, MACB_TX_INT_FLAGS); 1364 1365 if (halt_timeout) 1366 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TE)); 1367 1368 /* Now we are ready to start transmission again */ 1369 netif_tx_start_all_queues(bp->netdev); 1370 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); 1371 1372 spin_unlock_irqrestore(&bp->lock, flags); 1373 napi_enable(&queue->napi_tx); 1374 } 1375 1376 static bool ptp_one_step_sync(struct sk_buff *skb) 1377 { 1378 struct ptp_header *hdr; 1379 unsigned int ptp_class; 1380 u8 msgtype; 1381 1382 /* No need to parse packet if PTP TS is not involved */ 1383 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) 1384 goto not_oss; 1385 1386 /* Identify and return whether PTP one step sync is being processed */ 1387 ptp_class = ptp_classify_raw(skb); 1388 if (ptp_class == PTP_CLASS_NONE) 1389 goto not_oss; 1390 1391 hdr = ptp_parse_header(skb, ptp_class); 1392 if (!hdr) 1393 goto not_oss; 1394 1395 if (hdr->flag_field[0] & PTP_FLAG_TWOSTEP) 1396 goto not_oss; 1397 1398 msgtype = ptp_get_msgtype(hdr, ptp_class); 1399 if (msgtype == PTP_MSGTYPE_SYNC) 1400 return true; 1401 1402 not_oss: 1403 return false; 1404 } 1405 1406 static int macb_tx_complete(struct macb_queue *queue, int budget) 1407 { 1408 struct macb *bp = queue->bp; 1409 unsigned int q = queue - bp->queues; 1410 unsigned long flags; 1411 unsigned int tail; 1412 unsigned int head; 1413 int packets = 0; 1414 u32 bytes = 0; 1415 1416 spin_lock_irqsave(&queue->tx_ptr_lock, flags); 1417 head = queue->tx_head; 1418 for (tail = queue->tx_tail; tail != head && packets < budget; tail++) { 1419 struct macb_tx_skb *tx_skb; 1420 struct sk_buff *skb; 1421 struct macb_dma_desc *desc; 1422 u32 ctrl; 1423 1424 desc = macb_tx_desc(queue, tail); 1425 1426 /* Make hw descriptor updates visible to CPU */ 1427 rmb(); 1428 1429 ctrl = desc->ctrl; 1430 1431 /* TX_USED bit is only set by hardware on the very first buffer 1432 * descriptor of the transmitted frame. 1433 */ 1434 if (!(ctrl & MACB_BIT(TX_USED))) 1435 break; 1436 1437 /* Process all buffers of the current transmitted frame */ 1438 for (;; tail++) { 1439 tx_skb = macb_tx_skb(queue, tail); 1440 skb = tx_skb->skb; 1441 1442 /* First, update TX stats if needed */ 1443 if (skb) { 1444 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 1445 !ptp_one_step_sync(skb)) 1446 gem_ptp_do_txstamp(bp, skb, desc); 1447 1448 netdev_vdbg(bp->netdev, "skb %u (data %p) TX complete\n", 1449 macb_tx_ring_wrap(bp, tail), 1450 skb->data); 1451 bp->netdev->stats.tx_packets++; 1452 queue->stats.tx_packets++; 1453 bp->netdev->stats.tx_bytes += skb->len - tx_skb->fcs_len; 1454 queue->stats.tx_bytes += skb->len - tx_skb->fcs_len; 1455 packets++; 1456 bytes += skb->len; 1457 } 1458 1459 /* Now we can safely release resources */ 1460 macb_tx_unmap(bp, tx_skb, budget); 1461 1462 /* skb is set only for the last buffer of the frame. 1463 * WARNING: at this point skb has been freed by 1464 * macb_tx_unmap(). 1465 */ 1466 if (skb) 1467 break; 1468 } 1469 } 1470 1471 netdev_tx_completed_queue(netdev_get_tx_queue(bp->netdev, q), 1472 packets, bytes); 1473 1474 queue->tx_tail = tail; 1475 if (__netif_subqueue_stopped(bp->netdev, q) && 1476 CIRC_CNT(queue->tx_head, queue->tx_tail, 1477 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp)) 1478 netif_wake_subqueue(bp->netdev, q); 1479 spin_unlock_irqrestore(&queue->tx_ptr_lock, flags); 1480 1481 if (packets) 1482 macb_tx_lpi_schedule(bp); 1483 1484 return packets; 1485 } 1486 1487 static void gem_rx_refill(struct macb_queue *queue) 1488 { 1489 struct macb *bp = queue->bp; 1490 struct macb_dma_desc *desc; 1491 struct sk_buff *skb; 1492 unsigned int entry; 1493 dma_addr_t paddr; 1494 1495 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail, 1496 bp->rx_ring_size) > 0) { 1497 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head); 1498 1499 /* Make hw descriptor updates visible to CPU */ 1500 rmb(); 1501 1502 desc = macb_rx_desc(queue, entry); 1503 1504 if (!queue->rx_skbuff[entry]) { 1505 /* allocate sk_buff for this free entry in ring */ 1506 skb = netdev_alloc_skb(bp->netdev, bp->rx_buffer_size); 1507 if (unlikely(!skb)) { 1508 netdev_err(bp->netdev, 1509 "Unable to allocate sk_buff\n"); 1510 break; 1511 } 1512 1513 /* now fill corresponding descriptor entry */ 1514 paddr = dma_map_single(&bp->pdev->dev, skb->data, 1515 bp->rx_buffer_size, 1516 DMA_FROM_DEVICE); 1517 if (dma_mapping_error(&bp->pdev->dev, paddr)) { 1518 dev_kfree_skb(skb); 1519 break; 1520 } 1521 1522 queue->rx_skbuff[entry] = skb; 1523 1524 if (entry == bp->rx_ring_size - 1) 1525 paddr |= MACB_BIT(RX_WRAP); 1526 desc->ctrl = 0; 1527 /* Setting addr clears RX_USED and allows reception, 1528 * make sure ctrl is cleared first to avoid a race. 1529 */ 1530 dma_wmb(); 1531 macb_set_addr(bp, desc, paddr); 1532 1533 /* Properly align Ethernet header. 1534 * 1535 * Hardware can add dummy bytes if asked using the RBOF 1536 * field inside the NCFGR register. That feature isn't 1537 * available if hardware is RSC capable. 1538 * 1539 * We cannot fallback to doing the 2-byte shift before 1540 * DMA mapping because the address field does not allow 1541 * setting the low 2/3 bits. 1542 * It is 3 bits if HW_DMA_CAP_PTP, else 2 bits. 1543 */ 1544 if (!(bp->caps & MACB_CAPS_RSC)) 1545 skb_reserve(skb, NET_IP_ALIGN); 1546 } else { 1547 desc->ctrl = 0; 1548 dma_wmb(); 1549 desc->addr &= ~MACB_BIT(RX_USED); 1550 } 1551 queue->rx_prepared_head++; 1552 } 1553 1554 /* Make descriptor updates visible to hardware */ 1555 wmb(); 1556 1557 netdev_vdbg(bp->netdev, "rx ring: queue: %p, prepared head %d, tail %d\n", 1558 queue, queue->rx_prepared_head, queue->rx_tail); 1559 } 1560 1561 /* Mark DMA descriptors from begin up to and not including end as unused */ 1562 static void discard_partial_frame(struct macb_queue *queue, unsigned int begin, 1563 unsigned int end) 1564 { 1565 unsigned int frag; 1566 1567 for (frag = begin; frag != end; frag++) { 1568 struct macb_dma_desc *desc = macb_rx_desc(queue, frag); 1569 1570 desc->addr &= ~MACB_BIT(RX_USED); 1571 } 1572 1573 /* Make descriptor updates visible to hardware */ 1574 wmb(); 1575 1576 /* When this happens, the hardware stats registers for 1577 * whatever caused this is updated, so we don't have to record 1578 * anything. 1579 */ 1580 } 1581 1582 static int gem_rx(struct macb_queue *queue, struct napi_struct *napi, 1583 int budget) 1584 { 1585 struct macb *bp = queue->bp; 1586 struct macb_dma_desc *desc; 1587 struct sk_buff *skb; 1588 unsigned int entry; 1589 unsigned int len; 1590 int count = 0; 1591 1592 while (count < budget) { 1593 u32 ctrl; 1594 dma_addr_t addr; 1595 bool rxused; 1596 1597 entry = macb_rx_ring_wrap(bp, queue->rx_tail); 1598 desc = macb_rx_desc(queue, entry); 1599 1600 /* Make hw descriptor updates visible to CPU */ 1601 rmb(); 1602 1603 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false; 1604 addr = macb_get_addr(bp, desc); 1605 1606 if (!rxused) 1607 break; 1608 1609 /* Ensure ctrl is at least as up-to-date as rxused */ 1610 dma_rmb(); 1611 1612 ctrl = desc->ctrl; 1613 1614 queue->rx_tail++; 1615 count++; 1616 1617 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) { 1618 netdev_err(bp->netdev, 1619 "not whole frame pointed by descriptor\n"); 1620 bp->netdev->stats.rx_dropped++; 1621 queue->stats.rx_dropped++; 1622 break; 1623 } 1624 skb = queue->rx_skbuff[entry]; 1625 if (unlikely(!skb)) { 1626 netdev_err(bp->netdev, 1627 "inconsistent Rx descriptor chain\n"); 1628 bp->netdev->stats.rx_dropped++; 1629 queue->stats.rx_dropped++; 1630 break; 1631 } 1632 /* now everything is ready for receiving packet */ 1633 queue->rx_skbuff[entry] = NULL; 1634 len = ctrl & bp->rx_frm_len_mask; 1635 1636 netdev_vdbg(bp->netdev, "%s %u (len %u)\n", 1637 __func__, entry, len); 1638 1639 skb_put(skb, len); 1640 dma_unmap_single(&bp->pdev->dev, addr, 1641 bp->rx_buffer_size, DMA_FROM_DEVICE); 1642 1643 skb->protocol = eth_type_trans(skb, bp->netdev); 1644 skb_checksum_none_assert(skb); 1645 if (bp->netdev->features & NETIF_F_RXCSUM && 1646 !(bp->netdev->flags & IFF_PROMISC) && 1647 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK) 1648 skb->ip_summed = CHECKSUM_UNNECESSARY; 1649 1650 bp->netdev->stats.rx_packets++; 1651 queue->stats.rx_packets++; 1652 bp->netdev->stats.rx_bytes += skb->len; 1653 queue->stats.rx_bytes += skb->len; 1654 1655 gem_ptp_do_rxstamp(bp, skb, desc); 1656 1657 #if defined(DEBUG) && defined(VERBOSE_DEBUG) 1658 netdev_vdbg(bp->netdev, "received skb of length %u, csum: %08x\n", 1659 skb->len, skb->csum); 1660 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1, 1661 skb_mac_header(skb), 16, true); 1662 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1, 1663 skb->data, 32, true); 1664 #endif 1665 1666 napi_gro_receive(napi, skb); 1667 } 1668 1669 gem_rx_refill(queue); 1670 1671 return count; 1672 } 1673 1674 static int macb_rx_frame(struct macb_queue *queue, struct napi_struct *napi, 1675 unsigned int first_frag, unsigned int last_frag) 1676 { 1677 struct macb *bp = queue->bp; 1678 struct macb_dma_desc *desc; 1679 unsigned int offset; 1680 struct sk_buff *skb; 1681 unsigned int frag; 1682 unsigned int len; 1683 1684 desc = macb_rx_desc(queue, last_frag); 1685 len = desc->ctrl & bp->rx_frm_len_mask; 1686 1687 netdev_vdbg(bp->netdev, "%s frags %u - %u (len %u)\n", 1688 __func__, 1689 macb_rx_ring_wrap(bp, first_frag), 1690 macb_rx_ring_wrap(bp, last_frag), len); 1691 1692 /* The ethernet header starts NET_IP_ALIGN bytes into the 1693 * first buffer. Since the header is 14 bytes, this makes the 1694 * payload word-aligned. 1695 * 1696 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy 1697 * the two padding bytes into the skb so that we avoid hitting 1698 * the slowpath in memcpy(), and pull them off afterwards. 1699 */ 1700 skb = netdev_alloc_skb(bp->netdev, len + NET_IP_ALIGN); 1701 if (!skb) { 1702 bp->netdev->stats.rx_dropped++; 1703 for (frag = first_frag; ; frag++) { 1704 desc = macb_rx_desc(queue, frag); 1705 desc->addr &= ~MACB_BIT(RX_USED); 1706 if (frag == last_frag) 1707 break; 1708 } 1709 1710 /* Make descriptor updates visible to hardware */ 1711 wmb(); 1712 1713 return 1; 1714 } 1715 1716 offset = 0; 1717 len += NET_IP_ALIGN; 1718 skb_checksum_none_assert(skb); 1719 skb_put(skb, len); 1720 1721 for (frag = first_frag; ; frag++) { 1722 unsigned int frag_len = bp->rx_buffer_size; 1723 1724 if (offset + frag_len > len) { 1725 if (unlikely(frag != last_frag)) { 1726 dev_kfree_skb_any(skb); 1727 return -1; 1728 } 1729 frag_len = len - offset; 1730 } 1731 skb_copy_to_linear_data_offset(skb, offset, 1732 macb_rx_buffer(queue, frag), 1733 frag_len); 1734 offset += bp->rx_buffer_size; 1735 desc = macb_rx_desc(queue, frag); 1736 desc->addr &= ~MACB_BIT(RX_USED); 1737 1738 if (frag == last_frag) 1739 break; 1740 } 1741 1742 /* Make descriptor updates visible to hardware */ 1743 wmb(); 1744 1745 __skb_pull(skb, NET_IP_ALIGN); 1746 skb->protocol = eth_type_trans(skb, bp->netdev); 1747 1748 bp->netdev->stats.rx_packets++; 1749 bp->netdev->stats.rx_bytes += skb->len; 1750 netdev_vdbg(bp->netdev, "received skb of length %u, csum: %08x\n", 1751 skb->len, skb->csum); 1752 napi_gro_receive(napi, skb); 1753 1754 return 0; 1755 } 1756 1757 static inline void macb_init_rx_ring(struct macb_queue *queue) 1758 { 1759 struct macb_dma_desc *desc = NULL; 1760 struct macb *bp = queue->bp; 1761 dma_addr_t addr; 1762 int i; 1763 1764 addr = queue->rx_buffers_dma; 1765 for (i = 0; i < bp->rx_ring_size; i++) { 1766 desc = macb_rx_desc(queue, i); 1767 macb_set_addr(bp, desc, addr); 1768 desc->ctrl = 0; 1769 addr += bp->rx_buffer_size; 1770 } 1771 desc->addr |= MACB_BIT(RX_WRAP); 1772 queue->rx_tail = 0; 1773 } 1774 1775 static int macb_rx(struct macb_queue *queue, struct napi_struct *napi, 1776 int budget) 1777 { 1778 struct macb *bp = queue->bp; 1779 bool reset_rx_queue = false; 1780 int first_frag = -1; 1781 unsigned int tail; 1782 int received = 0; 1783 1784 for (tail = queue->rx_tail; budget > 0; tail++) { 1785 struct macb_dma_desc *desc = macb_rx_desc(queue, tail); 1786 u32 ctrl; 1787 1788 /* Make hw descriptor updates visible to CPU */ 1789 rmb(); 1790 1791 if (!(desc->addr & MACB_BIT(RX_USED))) 1792 break; 1793 1794 /* Ensure ctrl is at least as up-to-date as addr */ 1795 dma_rmb(); 1796 1797 ctrl = desc->ctrl; 1798 1799 if (ctrl & MACB_BIT(RX_SOF)) { 1800 if (first_frag != -1) 1801 discard_partial_frame(queue, first_frag, tail); 1802 first_frag = tail; 1803 } 1804 1805 if (ctrl & MACB_BIT(RX_EOF)) { 1806 int dropped; 1807 1808 if (unlikely(first_frag == -1)) { 1809 reset_rx_queue = true; 1810 continue; 1811 } 1812 1813 dropped = macb_rx_frame(queue, napi, first_frag, tail); 1814 first_frag = -1; 1815 if (unlikely(dropped < 0)) { 1816 reset_rx_queue = true; 1817 continue; 1818 } 1819 if (!dropped) { 1820 received++; 1821 budget--; 1822 } 1823 } 1824 } 1825 1826 if (unlikely(reset_rx_queue)) { 1827 unsigned long flags; 1828 u32 ctrl; 1829 1830 netdev_err(bp->netdev, "RX queue corruption: reset it\n"); 1831 1832 spin_lock_irqsave(&bp->lock, flags); 1833 1834 ctrl = macb_readl(bp, NCR); 1835 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE)); 1836 1837 macb_init_rx_ring(queue); 1838 queue_writel(queue, RBQP, queue->rx_ring_dma); 1839 1840 macb_writel(bp, NCR, ctrl | MACB_BIT(RE)); 1841 1842 spin_unlock_irqrestore(&bp->lock, flags); 1843 return received; 1844 } 1845 1846 if (first_frag != -1) 1847 queue->rx_tail = first_frag; 1848 else 1849 queue->rx_tail = tail; 1850 1851 return received; 1852 } 1853 1854 static bool macb_rx_pending(struct macb_queue *queue) 1855 { 1856 struct macb *bp = queue->bp; 1857 struct macb_dma_desc *desc; 1858 unsigned int entry; 1859 1860 entry = macb_rx_ring_wrap(bp, queue->rx_tail); 1861 desc = macb_rx_desc(queue, entry); 1862 1863 /* Make hw descriptor updates visible to CPU */ 1864 rmb(); 1865 1866 return (desc->addr & MACB_BIT(RX_USED)) != 0; 1867 } 1868 1869 static int macb_rx_poll(struct napi_struct *napi, int budget) 1870 { 1871 struct macb_queue *queue = container_of(napi, struct macb_queue, napi_rx); 1872 struct macb *bp = queue->bp; 1873 int work_done; 1874 1875 work_done = bp->macbgem_ops.mog_rx(queue, napi, budget); 1876 1877 netdev_vdbg(bp->netdev, "RX poll: queue = %u, work_done = %d, budget = %d\n", 1878 (unsigned int)(queue - bp->queues), work_done, budget); 1879 1880 if (work_done < budget && napi_complete_done(napi, work_done)) { 1881 queue_writel(queue, IER, bp->rx_intr_mask); 1882 1883 /* Packet completions only seem to propagate to raise 1884 * interrupts when interrupts are enabled at the time, so if 1885 * packets were received while interrupts were disabled, 1886 * they will not cause another interrupt to be generated when 1887 * interrupts are re-enabled. 1888 * Check for this case here to avoid losing a wakeup. This can 1889 * potentially race with the interrupt handler doing the same 1890 * actions if an interrupt is raised just after enabling them, 1891 * but this should be harmless. 1892 */ 1893 if (macb_rx_pending(queue)) { 1894 queue_writel(queue, IDR, bp->rx_intr_mask); 1895 macb_queue_isr_clear(bp, queue, MACB_BIT(RCOMP)); 1896 netdev_vdbg(bp->netdev, "poll: packets pending, reschedule\n"); 1897 napi_schedule(napi); 1898 } 1899 } 1900 1901 /* TODO: Handle errors */ 1902 1903 return work_done; 1904 } 1905 1906 static void macb_tx_restart(struct macb_queue *queue) 1907 { 1908 struct macb *bp = queue->bp; 1909 unsigned int head_idx, tbqp; 1910 unsigned long flags; 1911 1912 spin_lock_irqsave(&queue->tx_ptr_lock, flags); 1913 1914 if (queue->tx_head == queue->tx_tail) 1915 goto out_tx_ptr_unlock; 1916 1917 tbqp = queue_readl(queue, TBQP) / macb_dma_desc_get_size(bp); 1918 tbqp = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, tbqp)); 1919 head_idx = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, queue->tx_head)); 1920 1921 if (tbqp == head_idx) 1922 goto out_tx_ptr_unlock; 1923 1924 spin_lock(&bp->lock); 1925 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); 1926 spin_unlock(&bp->lock); 1927 1928 out_tx_ptr_unlock: 1929 spin_unlock_irqrestore(&queue->tx_ptr_lock, flags); 1930 } 1931 1932 static bool macb_tx_complete_pending(struct macb_queue *queue) 1933 { 1934 bool retval = false; 1935 unsigned long flags; 1936 1937 spin_lock_irqsave(&queue->tx_ptr_lock, flags); 1938 if (queue->tx_head != queue->tx_tail) { 1939 /* Make hw descriptor updates visible to CPU */ 1940 rmb(); 1941 1942 if (macb_tx_desc(queue, queue->tx_tail)->ctrl & MACB_BIT(TX_USED)) 1943 retval = true; 1944 } 1945 spin_unlock_irqrestore(&queue->tx_ptr_lock, flags); 1946 return retval; 1947 } 1948 1949 static int macb_tx_poll(struct napi_struct *napi, int budget) 1950 { 1951 struct macb_queue *queue = container_of(napi, struct macb_queue, napi_tx); 1952 struct macb *bp = queue->bp; 1953 int work_done; 1954 1955 work_done = macb_tx_complete(queue, budget); 1956 1957 rmb(); // ensure txubr_pending is up to date 1958 if (queue->txubr_pending) { 1959 queue->txubr_pending = false; 1960 netdev_vdbg(bp->netdev, "poll: tx restart\n"); 1961 macb_tx_restart(queue); 1962 } 1963 1964 netdev_vdbg(bp->netdev, "TX poll: queue = %u, work_done = %d, budget = %d\n", 1965 (unsigned int)(queue - bp->queues), work_done, budget); 1966 1967 if (work_done < budget && napi_complete_done(napi, work_done)) { 1968 queue_writel(queue, IER, MACB_BIT(TCOMP)); 1969 1970 /* Packet completions only seem to propagate to raise 1971 * interrupts when interrupts are enabled at the time, so if 1972 * packets were sent while interrupts were disabled, 1973 * they will not cause another interrupt to be generated when 1974 * interrupts are re-enabled. 1975 * Check for this case here to avoid losing a wakeup. This can 1976 * potentially race with the interrupt handler doing the same 1977 * actions if an interrupt is raised just after enabling them, 1978 * but this should be harmless. 1979 */ 1980 if (macb_tx_complete_pending(queue)) { 1981 queue_writel(queue, IDR, MACB_BIT(TCOMP)); 1982 macb_queue_isr_clear(bp, queue, MACB_BIT(TCOMP)); 1983 netdev_vdbg(bp->netdev, "TX poll: packets pending, reschedule\n"); 1984 napi_schedule(napi); 1985 } 1986 } 1987 1988 return work_done; 1989 } 1990 1991 static void macb_hresp_error_task(struct work_struct *work) 1992 { 1993 struct macb *bp = from_work(bp, work, hresp_err_bh_work); 1994 struct net_device *netdev = bp->netdev; 1995 struct macb_queue *queue; 1996 unsigned int q; 1997 u32 ctrl; 1998 1999 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 2000 queue_writel(queue, IDR, bp->rx_intr_mask | 2001 MACB_TX_INT_FLAGS | 2002 MACB_BIT(HRESP)); 2003 } 2004 ctrl = macb_readl(bp, NCR); 2005 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE)); 2006 macb_writel(bp, NCR, ctrl); 2007 2008 netif_tx_stop_all_queues(netdev); 2009 netif_carrier_off(netdev); 2010 2011 bp->macbgem_ops.mog_init_rings(bp); 2012 2013 /* Initialize TX and RX buffers */ 2014 macb_init_buffers(bp); 2015 2016 /* Enable interrupts */ 2017 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) 2018 queue_writel(queue, IER, 2019 bp->rx_intr_mask | 2020 MACB_TX_INT_FLAGS | 2021 MACB_BIT(HRESP)); 2022 2023 ctrl |= MACB_BIT(RE) | MACB_BIT(TE); 2024 macb_writel(bp, NCR, ctrl); 2025 2026 netif_carrier_on(netdev); 2027 netif_tx_start_all_queues(netdev); 2028 } 2029 2030 static void macb_wol_interrupt(struct macb_queue *queue, u32 status) 2031 { 2032 struct macb *bp = queue->bp; 2033 2034 queue_writel(queue, IDR, MACB_BIT(WOL)); 2035 macb_writel(bp, WOL, 0); 2036 netdev_vdbg(bp->netdev, "MACB WoL: queue = %u, isr = 0x%08lx\n", 2037 (unsigned int)(queue - bp->queues), 2038 (unsigned long)status); 2039 macb_queue_isr_clear(bp, queue, MACB_BIT(WOL)); 2040 pm_wakeup_event(&bp->pdev->dev, 0); 2041 } 2042 2043 static void gem_wol_interrupt(struct macb_queue *queue, u32 status) 2044 { 2045 struct macb *bp = queue->bp; 2046 2047 queue_writel(queue, IDR, GEM_BIT(WOL)); 2048 gem_writel(bp, WOL, 0); 2049 netdev_vdbg(bp->netdev, "GEM WoL: queue = %u, isr = 0x%08lx\n", 2050 (unsigned int)(queue - bp->queues), 2051 (unsigned long)status); 2052 macb_queue_isr_clear(bp, queue, GEM_BIT(WOL)); 2053 pm_wakeup_event(&bp->pdev->dev, 0); 2054 } 2055 2056 static int macb_interrupt_misc(struct macb_queue *queue, u32 status) 2057 { 2058 struct macb *bp = queue->bp; 2059 struct net_device *netdev; 2060 u32 ctrl; 2061 2062 netdev = bp->netdev; 2063 2064 if (unlikely(status & (MACB_TX_ERR_FLAGS))) { 2065 queue_writel(queue, IDR, MACB_TX_INT_FLAGS); 2066 schedule_work(&queue->tx_error_task); 2067 macb_queue_isr_clear(bp, queue, MACB_TX_ERR_FLAGS); 2068 return -1; 2069 } 2070 2071 /* Link change detection isn't possible with RMII, so we'll 2072 * add that if/when we get our hands on a full-blown MII PHY. 2073 */ 2074 2075 /* There is a hardware issue under heavy load where DMA can 2076 * stop, this causes endless "used buffer descriptor read" 2077 * interrupts but it can be cleared by re-enabling RX. See 2078 * the at91rm9200 manual, section 41.3.1 or the Zynq manual 2079 * section 16.7.4 for details. RXUBR is only enabled for 2080 * these two versions. 2081 */ 2082 if (status & MACB_BIT(RXUBR)) { 2083 ctrl = macb_readl(bp, NCR); 2084 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE)); 2085 wmb(); 2086 macb_writel(bp, NCR, ctrl | MACB_BIT(RE)); 2087 macb_queue_isr_clear(bp, queue, MACB_BIT(RXUBR)); 2088 } 2089 2090 if (status & MACB_BIT(ISR_ROVR)) { 2091 /* We missed at least one packet */ 2092 spin_lock(&bp->stats_lock); 2093 if (macb_is_gem(bp)) 2094 bp->hw_stats.gem.rx_overruns++; 2095 else 2096 bp->hw_stats.macb.rx_overruns++; 2097 spin_unlock(&bp->stats_lock); 2098 macb_queue_isr_clear(bp, queue, MACB_BIT(ISR_ROVR)); 2099 } 2100 2101 if (status & MACB_BIT(HRESP)) { 2102 queue_work(system_bh_wq, &bp->hresp_err_bh_work); 2103 netdev_err(netdev, "DMA bus error: HRESP not OK\n"); 2104 macb_queue_isr_clear(bp, queue, MACB_BIT(HRESP)); 2105 } 2106 2107 if (macb_is_gem(bp)) { 2108 if (status & GEM_BIT(WOL)) 2109 gem_wol_interrupt(queue, status); 2110 } else { 2111 if (status & MACB_BIT(WOL)) 2112 macb_wol_interrupt(queue, status); 2113 } 2114 2115 return 0; 2116 } 2117 2118 static irqreturn_t macb_interrupt(int irq, void *dev_id) 2119 { 2120 struct macb_queue *queue = dev_id; 2121 struct macb *bp = queue->bp; 2122 struct net_device *netdev = bp->netdev; 2123 u32 status; 2124 2125 status = queue_readl(queue, ISR); 2126 2127 if (unlikely(!status)) 2128 return IRQ_NONE; 2129 2130 spin_lock(&bp->lock); 2131 2132 while (status) { 2133 /* close possible race with dev_close */ 2134 if (unlikely(!netif_running(netdev))) { 2135 queue_writel(queue, IDR, -1); 2136 macb_queue_isr_clear(bp, queue, -1); 2137 break; 2138 } 2139 2140 netdev_vdbg(netdev, "queue = %u, isr = 0x%08lx\n", 2141 (unsigned int)(queue - bp->queues), 2142 (unsigned long)status); 2143 2144 if (status & bp->rx_intr_mask) { 2145 /* There's no point taking any more interrupts 2146 * until we have processed the buffers. The 2147 * scheduling call may fail if the poll routine 2148 * is already scheduled, so disable interrupts 2149 * now. 2150 */ 2151 queue_writel(queue, IDR, bp->rx_intr_mask); 2152 macb_queue_isr_clear(bp, queue, MACB_BIT(RCOMP)); 2153 napi_schedule_irqoff(&queue->napi_rx); 2154 } 2155 2156 if (status & (MACB_BIT(TCOMP) | 2157 MACB_BIT(TXUBR))) { 2158 queue_writel(queue, IDR, MACB_BIT(TCOMP)); 2159 macb_queue_isr_clear(bp, queue, MACB_BIT(TCOMP) | 2160 MACB_BIT(TXUBR)); 2161 if (status & MACB_BIT(TXUBR)) { 2162 queue->txubr_pending = true; 2163 wmb(); // ensure softirq can see update 2164 } 2165 2166 napi_schedule_irqoff(&queue->napi_tx); 2167 } 2168 2169 if (unlikely(status & MACB_INT_MISC_FLAGS)) 2170 if (macb_interrupt_misc(queue, status)) 2171 break; 2172 2173 status = queue_readl(queue, ISR); 2174 } 2175 2176 spin_unlock(&bp->lock); 2177 2178 return IRQ_HANDLED; 2179 } 2180 2181 #ifdef CONFIG_NET_POLL_CONTROLLER 2182 /* Polling receive - used by netconsole and other diagnostic tools 2183 * to allow network i/o with interrupts disabled. 2184 */ 2185 static void macb_poll_controller(struct net_device *netdev) 2186 { 2187 struct macb *bp = netdev_priv(netdev); 2188 struct macb_queue *queue; 2189 unsigned long flags; 2190 unsigned int q; 2191 2192 local_irq_save(flags); 2193 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) 2194 macb_interrupt(netdev->irq, queue); 2195 local_irq_restore(flags); 2196 } 2197 #endif 2198 2199 static unsigned int macb_tx_map(struct macb *bp, 2200 struct macb_queue *queue, 2201 struct sk_buff *skb, 2202 unsigned int hdrlen, 2203 u8 fcs_len) 2204 { 2205 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags; 2206 unsigned int len, i, tx_head = queue->tx_head; 2207 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0; 2208 unsigned int eof = 1, mss_mfs = 0; 2209 struct macb_tx_skb *tx_skb = NULL; 2210 struct macb_dma_desc *desc; 2211 unsigned int offset, size; 2212 dma_addr_t mapping; 2213 2214 /* LSO */ 2215 if (skb_shinfo(skb)->gso_size != 0) { 2216 if (ip_hdr(skb)->protocol == IPPROTO_UDP) 2217 /* UDP - UFO */ 2218 lso_ctrl = MACB_LSO_UFO_ENABLE; 2219 else 2220 /* TCP - TSO */ 2221 lso_ctrl = MACB_LSO_TSO_ENABLE; 2222 } 2223 2224 /* First, map non-paged data */ 2225 len = skb_headlen(skb); 2226 2227 /* first buffer length */ 2228 size = hdrlen; 2229 2230 offset = 0; 2231 while (len) { 2232 tx_skb = macb_tx_skb(queue, tx_head); 2233 2234 mapping = dma_map_single(&bp->pdev->dev, 2235 skb->data + offset, 2236 size, DMA_TO_DEVICE); 2237 if (dma_mapping_error(&bp->pdev->dev, mapping)) 2238 goto dma_error; 2239 2240 /* Save info to properly release resources */ 2241 tx_skb->skb = NULL; 2242 tx_skb->mapping = mapping; 2243 tx_skb->size = size; 2244 tx_skb->mapped_as_page = false; 2245 2246 len -= size; 2247 offset += size; 2248 tx_head++; 2249 2250 size = umin(len, bp->max_tx_length); 2251 } 2252 2253 /* Then, map paged data from fragments */ 2254 for (f = 0; f < nr_frags; f++) { 2255 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 2256 2257 len = skb_frag_size(frag); 2258 offset = 0; 2259 while (len) { 2260 size = umin(len, bp->max_tx_length); 2261 tx_skb = macb_tx_skb(queue, tx_head); 2262 2263 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 2264 offset, size, DMA_TO_DEVICE); 2265 if (dma_mapping_error(&bp->pdev->dev, mapping)) 2266 goto dma_error; 2267 2268 /* Save info to properly release resources */ 2269 tx_skb->skb = NULL; 2270 tx_skb->mapping = mapping; 2271 tx_skb->size = size; 2272 tx_skb->mapped_as_page = true; 2273 2274 len -= size; 2275 offset += size; 2276 tx_head++; 2277 } 2278 } 2279 2280 /* Should never happen */ 2281 if (unlikely(!tx_skb)) { 2282 netdev_err(bp->netdev, "BUG! empty skb!\n"); 2283 return 0; 2284 } 2285 2286 /* This is the last buffer of the frame: save socket buffer */ 2287 tx_skb->skb = skb; 2288 tx_skb->fcs_len = fcs_len; 2289 2290 /* Update TX ring: update buffer descriptors in reverse order 2291 * to avoid race condition 2292 */ 2293 2294 /* Set 'TX_USED' bit in buffer descriptor at tx_head position 2295 * to set the end of TX queue 2296 */ 2297 i = tx_head; 2298 ctrl = MACB_BIT(TX_USED); 2299 desc = macb_tx_desc(queue, i); 2300 desc->ctrl = ctrl; 2301 2302 if (lso_ctrl) { 2303 if (lso_ctrl == MACB_LSO_UFO_ENABLE) 2304 /* include header and FCS in value given to h/w */ 2305 mss_mfs = skb_shinfo(skb)->gso_size + 2306 skb_transport_offset(skb) + 2307 ETH_FCS_LEN; 2308 else /* TSO */ { 2309 mss_mfs = skb_shinfo(skb)->gso_size; 2310 /* TCP Sequence Number Source Select 2311 * can be set only for TSO 2312 */ 2313 seq_ctrl = 0; 2314 } 2315 } 2316 2317 do { 2318 i--; 2319 tx_skb = macb_tx_skb(queue, i); 2320 desc = macb_tx_desc(queue, i); 2321 2322 ctrl = (u32)tx_skb->size; 2323 if (eof) { 2324 ctrl |= MACB_BIT(TX_LAST); 2325 eof = 0; 2326 } 2327 if (unlikely(macb_tx_ring_wrap(bp, i) == bp->tx_ring_size - 1)) 2328 ctrl |= MACB_BIT(TX_WRAP); 2329 2330 /* First descriptor is header descriptor */ 2331 if (i == queue->tx_head) { 2332 ctrl |= MACB_BF(TX_LSO, lso_ctrl); 2333 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl); 2334 if ((bp->netdev->features & NETIF_F_HW_CSUM) && 2335 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl && 2336 !ptp_one_step_sync(skb)) 2337 ctrl |= MACB_BIT(TX_NOCRC); 2338 } else 2339 /* Only set MSS/MFS on payload descriptors 2340 * (second or later descriptor) 2341 */ 2342 ctrl |= MACB_BF(MSS_MFS, mss_mfs); 2343 2344 /* Set TX buffer descriptor */ 2345 macb_set_addr(bp, desc, tx_skb->mapping); 2346 /* desc->addr must be visible to hardware before clearing 2347 * 'TX_USED' bit in desc->ctrl. 2348 */ 2349 wmb(); 2350 desc->ctrl = ctrl; 2351 } while (i != queue->tx_head); 2352 2353 queue->tx_head = tx_head; 2354 2355 return 0; 2356 2357 dma_error: 2358 netdev_err(bp->netdev, "TX DMA map failed\n"); 2359 2360 for (i = queue->tx_head; i != tx_head; i++) { 2361 tx_skb = macb_tx_skb(queue, i); 2362 2363 macb_tx_unmap(bp, tx_skb, 0); 2364 } 2365 2366 return -ENOMEM; 2367 } 2368 2369 static netdev_features_t macb_features_check(struct sk_buff *skb, 2370 struct net_device *netdev, 2371 netdev_features_t features) 2372 { 2373 unsigned int nr_frags, f; 2374 unsigned int hdrlen; 2375 2376 /* Validate LSO compatibility */ 2377 2378 /* there is only one buffer or protocol is not UDP */ 2379 if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP)) 2380 return features; 2381 2382 /* length of header */ 2383 hdrlen = skb_transport_offset(skb); 2384 2385 /* For UFO only: 2386 * When software supplies two or more payload buffers all payload buffers 2387 * apart from the last must be a multiple of 8 bytes in size. 2388 */ 2389 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN)) 2390 return features & ~MACB_NETIF_LSO; 2391 2392 nr_frags = skb_shinfo(skb)->nr_frags; 2393 /* No need to check last fragment */ 2394 nr_frags--; 2395 for (f = 0; f < nr_frags; f++) { 2396 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 2397 2398 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN)) 2399 return features & ~MACB_NETIF_LSO; 2400 } 2401 return features; 2402 } 2403 2404 static inline int macb_clear_csum(struct sk_buff *skb) 2405 { 2406 /* no change for packets without checksum offloading */ 2407 if (skb->ip_summed != CHECKSUM_PARTIAL) 2408 return 0; 2409 2410 /* make sure we can modify the header */ 2411 if (unlikely(skb_cow_head(skb, 0))) 2412 return -1; 2413 2414 /* initialize checksum field 2415 * This is required - at least for Zynq, which otherwise calculates 2416 * wrong UDP header checksums for UDP packets with UDP data len <=2 2417 */ 2418 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0; 2419 return 0; 2420 } 2421 2422 /* Returns a negative errno, or the FCS bytes appended (0 or ETH_FCS_LEN). */ 2423 static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *netdev) 2424 { 2425 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb) || 2426 skb_is_nonlinear(*skb); 2427 int padlen = ETH_ZLEN - (*skb)->len; 2428 int tailroom = skb_tailroom(*skb); 2429 struct sk_buff *nskb; 2430 u32 fcs; 2431 2432 if (!(netdev->features & NETIF_F_HW_CSUM) || 2433 !((*skb)->ip_summed != CHECKSUM_PARTIAL) || 2434 skb_shinfo(*skb)->gso_size || ptp_one_step_sync(*skb)) 2435 return 0; 2436 2437 if (padlen <= 0) { 2438 /* FCS could be appeded to tailroom. */ 2439 if (tailroom >= ETH_FCS_LEN) 2440 goto add_fcs; 2441 /* No room for FCS, need to reallocate skb. */ 2442 else 2443 padlen = ETH_FCS_LEN; 2444 } else { 2445 /* Add room for FCS. */ 2446 padlen += ETH_FCS_LEN; 2447 } 2448 2449 if (cloned || tailroom < padlen) { 2450 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC); 2451 if (!nskb) 2452 return -ENOMEM; 2453 2454 dev_consume_skb_any(*skb); 2455 *skb = nskb; 2456 } 2457 2458 if (padlen > ETH_FCS_LEN) 2459 skb_put_zero(*skb, padlen - ETH_FCS_LEN); 2460 2461 add_fcs: 2462 /* set FCS to packet */ 2463 fcs = crc32_le(~0, (*skb)->data, (*skb)->len); 2464 fcs = ~fcs; 2465 2466 skb_put_u8(*skb, fcs & 0xff); 2467 skb_put_u8(*skb, (fcs >> 8) & 0xff); 2468 skb_put_u8(*skb, (fcs >> 16) & 0xff); 2469 skb_put_u8(*skb, (fcs >> 24) & 0xff); 2470 2471 return ETH_FCS_LEN; 2472 } 2473 2474 static netdev_tx_t macb_start_xmit(struct sk_buff *skb, 2475 struct net_device *netdev) 2476 { 2477 struct macb *bp = netdev_priv(netdev); 2478 unsigned int q = skb_get_queue_mapping(skb); 2479 unsigned int desc_cnt, nr_frags, frag_size, f; 2480 struct macb_queue *queue = &bp->queues[q]; 2481 netdev_tx_t ret = NETDEV_TX_OK; 2482 unsigned int hdrlen; 2483 unsigned long flags; 2484 int fcs_len; 2485 bool is_lso; 2486 2487 if (macb_clear_csum(skb)) { 2488 dev_kfree_skb_any(skb); 2489 return ret; 2490 } 2491 2492 fcs_len = macb_pad_and_fcs(&skb, netdev); 2493 if (fcs_len < 0) { 2494 dev_kfree_skb_any(skb); 2495 return ret; 2496 } 2497 2498 if (macb_dma_ptp(bp) && 2499 (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) 2500 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2501 2502 is_lso = (skb_shinfo(skb)->gso_size != 0); 2503 2504 if (is_lso) { 2505 /* length of headers */ 2506 if (ip_hdr(skb)->protocol == IPPROTO_UDP) 2507 /* only queue eth + ip headers separately for UDP */ 2508 hdrlen = skb_transport_offset(skb); 2509 else 2510 hdrlen = skb_tcp_all_headers(skb); 2511 if (skb_headlen(skb) < hdrlen) { 2512 netdev_err(bp->netdev, "Error - LSO headers fragmented!!!\n"); 2513 /* if this is required, would need to copy to single buffer */ 2514 return NETDEV_TX_BUSY; 2515 } 2516 } else 2517 hdrlen = umin(skb_headlen(skb), bp->max_tx_length); 2518 2519 #if defined(DEBUG) && defined(VERBOSE_DEBUG) 2520 netdev_vdbg(bp->netdev, 2521 "start_xmit: queue %u len %u head %p data %p tail %p end %p\n", 2522 q, skb->len, skb->head, skb->data, 2523 skb_tail_pointer(skb), skb_end_pointer(skb)); 2524 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1, 2525 skb->data, 16, true); 2526 #endif 2527 2528 /* Count how many TX buffer descriptors are needed to send this 2529 * socket buffer: skb fragments of jumbo frames may need to be 2530 * split into many buffer descriptors. 2531 */ 2532 if (is_lso && (skb_headlen(skb) > hdrlen)) 2533 /* extra header descriptor if also payload in first buffer */ 2534 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1; 2535 else 2536 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length); 2537 nr_frags = skb_shinfo(skb)->nr_frags; 2538 for (f = 0; f < nr_frags; f++) { 2539 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]); 2540 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length); 2541 } 2542 2543 spin_lock_irqsave(&queue->tx_ptr_lock, flags); 2544 2545 /* This is a hard error, log it. */ 2546 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, 2547 bp->tx_ring_size) < desc_cnt) { 2548 netif_stop_subqueue(netdev, q); 2549 netdev_dbg(netdev, "tx_head = %u, tx_tail = %u\n", 2550 queue->tx_head, queue->tx_tail); 2551 ret = NETDEV_TX_BUSY; 2552 goto unlock; 2553 } 2554 2555 /* Map socket buffer for DMA transfer */ 2556 if (macb_tx_map(bp, queue, skb, hdrlen, fcs_len)) { 2557 dev_kfree_skb_any(skb); 2558 goto unlock; 2559 } 2560 2561 /* Make newly initialized descriptor visible to hardware */ 2562 wmb(); 2563 skb_tx_timestamp(skb); 2564 netdev_tx_sent_queue(netdev_get_tx_queue(bp->netdev, q), 2565 skb->len); 2566 2567 spin_lock(&bp->lock); 2568 macb_tx_lpi_wake(bp); 2569 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); 2570 spin_unlock(&bp->lock); 2571 2572 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1) 2573 netif_stop_subqueue(netdev, q); 2574 2575 unlock: 2576 spin_unlock_irqrestore(&queue->tx_ptr_lock, flags); 2577 2578 return ret; 2579 } 2580 2581 static void macb_init_rx_buffer_size(struct macb *bp, size_t size) 2582 { 2583 if (!macb_is_gem(bp)) { 2584 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE; 2585 } else { 2586 bp->rx_buffer_size = MIN(size, RX_BUFFER_MAX); 2587 2588 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) { 2589 netdev_dbg(bp->netdev, 2590 "RX buffer must be multiple of %d bytes, expanding\n", 2591 RX_BUFFER_MULTIPLE); 2592 bp->rx_buffer_size = 2593 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE); 2594 } 2595 } 2596 2597 netdev_dbg(bp->netdev, "mtu [%u] rx_buffer_size [%zu]\n", 2598 bp->netdev->mtu, bp->rx_buffer_size); 2599 } 2600 2601 static void gem_free_rx_buffers(struct macb *bp) 2602 { 2603 struct sk_buff *skb; 2604 struct macb_dma_desc *desc; 2605 struct macb_queue *queue; 2606 dma_addr_t addr; 2607 unsigned int q; 2608 int i; 2609 2610 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 2611 if (!queue->rx_skbuff) 2612 continue; 2613 2614 for (i = 0; i < bp->rx_ring_size; i++) { 2615 skb = queue->rx_skbuff[i]; 2616 2617 if (!skb) 2618 continue; 2619 2620 desc = macb_rx_desc(queue, i); 2621 addr = macb_get_addr(bp, desc); 2622 2623 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size, 2624 DMA_FROM_DEVICE); 2625 dev_kfree_skb_any(skb); 2626 skb = NULL; 2627 } 2628 2629 kfree(queue->rx_skbuff); 2630 queue->rx_skbuff = NULL; 2631 } 2632 } 2633 2634 static void macb_free_rx_buffers(struct macb *bp) 2635 { 2636 struct macb_queue *queue = &bp->queues[0]; 2637 2638 if (queue->rx_buffers) { 2639 dma_free_coherent(&bp->pdev->dev, 2640 bp->rx_ring_size * bp->rx_buffer_size, 2641 queue->rx_buffers, queue->rx_buffers_dma); 2642 queue->rx_buffers = NULL; 2643 } 2644 } 2645 2646 static unsigned int macb_tx_ring_size_per_queue(struct macb *bp) 2647 { 2648 return macb_dma_desc_get_size(bp) * bp->tx_ring_size + bp->tx_bd_rd_prefetch; 2649 } 2650 2651 static unsigned int macb_rx_ring_size_per_queue(struct macb *bp) 2652 { 2653 return macb_dma_desc_get_size(bp) * bp->rx_ring_size + bp->rx_bd_rd_prefetch; 2654 } 2655 2656 static void macb_free(struct macb *bp) 2657 { 2658 struct device *dev = &bp->pdev->dev; 2659 struct macb_queue *queue; 2660 unsigned int q; 2661 size_t size; 2662 2663 bp->macbgem_ops.mog_free_rx_buffers(bp); 2664 2665 size = bp->num_queues * macb_tx_ring_size_per_queue(bp); 2666 dma_free_coherent(dev, size, bp->queues[0].tx_ring, bp->queues[0].tx_ring_dma); 2667 2668 size = bp->num_queues * macb_rx_ring_size_per_queue(bp); 2669 dma_free_coherent(dev, size, bp->queues[0].rx_ring, bp->queues[0].rx_ring_dma); 2670 2671 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 2672 if (queue->tx_skb) { 2673 unsigned int dropped = 0, tail; 2674 2675 for (tail = queue->tx_tail; tail != queue->tx_head; 2676 tail++) { 2677 if (macb_tx_skb(queue, tail)->skb) 2678 dropped++; 2679 macb_tx_unmap(bp, macb_tx_skb(queue, tail), 0); 2680 } 2681 2682 queue->stats.tx_dropped += dropped; 2683 bp->netdev->stats.tx_dropped += dropped; 2684 2685 kfree(queue->tx_skb); 2686 queue->tx_skb = NULL; 2687 } 2688 2689 queue->tx_head = 0; 2690 queue->tx_tail = 0; 2691 queue->tx_ring = NULL; 2692 queue->rx_ring = NULL; 2693 } 2694 } 2695 2696 static int gem_alloc_rx_buffers(struct macb *bp) 2697 { 2698 struct macb_queue *queue; 2699 unsigned int q; 2700 int size; 2701 2702 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 2703 size = bp->rx_ring_size * sizeof(struct sk_buff *); 2704 queue->rx_skbuff = kzalloc(size, GFP_KERNEL); 2705 if (!queue->rx_skbuff) 2706 return -ENOMEM; 2707 else 2708 netdev_dbg(bp->netdev, 2709 "Allocated %d RX struct sk_buff entries at %p\n", 2710 bp->rx_ring_size, queue->rx_skbuff); 2711 } 2712 return 0; 2713 } 2714 2715 static int macb_alloc_rx_buffers(struct macb *bp) 2716 { 2717 struct macb_queue *queue = &bp->queues[0]; 2718 int size; 2719 2720 size = bp->rx_ring_size * bp->rx_buffer_size; 2721 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size, 2722 &queue->rx_buffers_dma, GFP_KERNEL); 2723 if (!queue->rx_buffers) 2724 return -ENOMEM; 2725 2726 netdev_dbg(bp->netdev, 2727 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n", 2728 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers); 2729 return 0; 2730 } 2731 2732 static int macb_alloc(struct macb *bp) 2733 { 2734 struct device *dev = &bp->pdev->dev; 2735 dma_addr_t tx_dma, rx_dma; 2736 struct macb_queue *queue; 2737 unsigned int q; 2738 void *tx, *rx; 2739 size_t size; 2740 2741 /* 2742 * Upper 32-bits of Tx/Rx DMA descriptor for each queues much match! 2743 * We cannot enforce this guarantee, the best we can do is do a single 2744 * allocation and hope it will land into alloc_pages() that guarantees 2745 * natural alignment of physical addresses. 2746 */ 2747 2748 size = bp->num_queues * macb_tx_ring_size_per_queue(bp); 2749 tx = dma_alloc_coherent(dev, size, &tx_dma, GFP_KERNEL); 2750 if (!tx || upper_32_bits(tx_dma) != upper_32_bits(tx_dma + size - 1)) 2751 goto out_err; 2752 netdev_dbg(bp->netdev, "Allocated %zu bytes for %u TX rings at %08lx (mapped %p)\n", 2753 size, bp->num_queues, (unsigned long)tx_dma, tx); 2754 2755 size = bp->num_queues * macb_rx_ring_size_per_queue(bp); 2756 rx = dma_alloc_coherent(dev, size, &rx_dma, GFP_KERNEL); 2757 if (!rx || upper_32_bits(rx_dma) != upper_32_bits(rx_dma + size - 1)) 2758 goto out_err; 2759 netdev_dbg(bp->netdev, "Allocated %zu bytes for %u RX rings at %08lx (mapped %p)\n", 2760 size, bp->num_queues, (unsigned long)rx_dma, rx); 2761 2762 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 2763 queue->tx_ring = tx + macb_tx_ring_size_per_queue(bp) * q; 2764 queue->tx_ring_dma = tx_dma + macb_tx_ring_size_per_queue(bp) * q; 2765 2766 queue->rx_ring = rx + macb_rx_ring_size_per_queue(bp) * q; 2767 queue->rx_ring_dma = rx_dma + macb_rx_ring_size_per_queue(bp) * q; 2768 2769 size = bp->tx_ring_size * sizeof(struct macb_tx_skb); 2770 queue->tx_skb = kmalloc(size, GFP_KERNEL); 2771 if (!queue->tx_skb) 2772 goto out_err; 2773 } 2774 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp)) 2775 goto out_err; 2776 2777 return 0; 2778 2779 out_err: 2780 macb_free(bp); 2781 return -ENOMEM; 2782 } 2783 2784 static void gem_init_rx_ring(struct macb_queue *queue) 2785 { 2786 queue->rx_tail = 0; 2787 queue->rx_prepared_head = 0; 2788 2789 gem_rx_refill(queue); 2790 } 2791 2792 static void gem_init_rings(struct macb *bp) 2793 { 2794 struct macb_queue *queue; 2795 struct macb_dma_desc *desc = NULL; 2796 unsigned int q; 2797 int i; 2798 2799 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 2800 for (i = 0; i < bp->tx_ring_size; i++) { 2801 desc = macb_tx_desc(queue, i); 2802 macb_set_addr(bp, desc, 0); 2803 desc->ctrl = MACB_BIT(TX_USED); 2804 } 2805 desc->ctrl |= MACB_BIT(TX_WRAP); 2806 queue->tx_head = 0; 2807 queue->tx_tail = 0; 2808 2809 gem_init_rx_ring(queue); 2810 } 2811 } 2812 2813 static void macb_init_rings(struct macb *bp) 2814 { 2815 int i; 2816 struct macb_dma_desc *desc = NULL; 2817 2818 macb_init_rx_ring(&bp->queues[0]); 2819 2820 for (i = 0; i < bp->tx_ring_size; i++) { 2821 desc = macb_tx_desc(&bp->queues[0], i); 2822 macb_set_addr(bp, desc, 0); 2823 desc->ctrl = MACB_BIT(TX_USED); 2824 } 2825 bp->queues[0].tx_head = 0; 2826 bp->queues[0].tx_tail = 0; 2827 desc->ctrl |= MACB_BIT(TX_WRAP); 2828 } 2829 2830 static void macb_reset_hw(struct macb *bp) 2831 { 2832 struct macb_queue *queue; 2833 unsigned int q; 2834 u32 ctrl = macb_readl(bp, NCR); 2835 2836 /* Disable RX and TX (XXX: Should we halt the transmission 2837 * more gracefully?) 2838 */ 2839 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE)); 2840 2841 /* Clear the stats registers (XXX: Update stats first?) */ 2842 ctrl |= MACB_BIT(CLRSTAT); 2843 2844 macb_writel(bp, NCR, ctrl); 2845 2846 /* Clear all status flags */ 2847 macb_writel(bp, TSR, -1); 2848 macb_writel(bp, RSR, -1); 2849 2850 /* Disable RX partial store and forward and reset watermark value */ 2851 gem_writel(bp, PBUFRXCUT, 0); 2852 2853 /* Disable all interrupts */ 2854 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 2855 queue_writel(queue, IDR, -1); 2856 queue_readl(queue, ISR); 2857 macb_queue_isr_clear(bp, queue, -1); 2858 } 2859 } 2860 2861 static u32 gem_mdc_clk_div(struct macb *bp) 2862 { 2863 u32 config; 2864 unsigned long pclk_hz = clk_get_rate(bp->pclk); 2865 2866 if (pclk_hz <= 20000000) 2867 config = GEM_BF(CLK, GEM_CLK_DIV8); 2868 else if (pclk_hz <= 40000000) 2869 config = GEM_BF(CLK, GEM_CLK_DIV16); 2870 else if (pclk_hz <= 80000000) 2871 config = GEM_BF(CLK, GEM_CLK_DIV32); 2872 else if (pclk_hz <= 120000000) 2873 config = GEM_BF(CLK, GEM_CLK_DIV48); 2874 else if (pclk_hz <= 160000000) 2875 config = GEM_BF(CLK, GEM_CLK_DIV64); 2876 else if (pclk_hz <= 240000000) 2877 config = GEM_BF(CLK, GEM_CLK_DIV96); 2878 else if (pclk_hz <= 320000000) 2879 config = GEM_BF(CLK, GEM_CLK_DIV128); 2880 else 2881 config = GEM_BF(CLK, GEM_CLK_DIV224); 2882 2883 return config; 2884 } 2885 2886 static u32 macb_mdc_clk_div(struct macb *bp) 2887 { 2888 u32 config; 2889 unsigned long pclk_hz; 2890 2891 if (macb_is_gem(bp)) 2892 return gem_mdc_clk_div(bp); 2893 2894 pclk_hz = clk_get_rate(bp->pclk); 2895 if (pclk_hz <= 20000000) 2896 config = MACB_BF(CLK, MACB_CLK_DIV8); 2897 else if (pclk_hz <= 40000000) 2898 config = MACB_BF(CLK, MACB_CLK_DIV16); 2899 else if (pclk_hz <= 80000000) 2900 config = MACB_BF(CLK, MACB_CLK_DIV32); 2901 else 2902 config = MACB_BF(CLK, MACB_CLK_DIV64); 2903 2904 return config; 2905 } 2906 2907 /* Get the DMA bus width field of the network configuration register that we 2908 * should program. We find the width from decoding the design configuration 2909 * register to find the maximum supported data bus width. 2910 */ 2911 static u32 macb_dbw(struct macb *bp) 2912 { 2913 if (!macb_is_gem(bp)) 2914 return 0; 2915 2916 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) { 2917 case 4: 2918 return GEM_BF(DBW, GEM_DBW128); 2919 case 2: 2920 return GEM_BF(DBW, GEM_DBW64); 2921 case 1: 2922 default: 2923 return GEM_BF(DBW, GEM_DBW32); 2924 } 2925 } 2926 2927 /* Configure the receive DMA engine 2928 * - use the correct receive buffer size 2929 * - set best burst length for DMA operations 2930 * (if not supported by FIFO, it will fallback to default) 2931 * - set both rx/tx packet buffers to full memory size 2932 * These are configurable parameters for GEM. 2933 */ 2934 static void macb_configure_dma(struct macb *bp) 2935 { 2936 struct macb_queue *queue; 2937 u32 buffer_size; 2938 unsigned int q; 2939 u32 dmacfg; 2940 2941 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE; 2942 if (macb_is_gem(bp)) { 2943 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L); 2944 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 2945 if (q) 2946 queue_writel(queue, RBQS, buffer_size); 2947 else 2948 dmacfg |= GEM_BF(RXBS, buffer_size); 2949 } 2950 if (bp->dma_burst_length) 2951 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg); 2952 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L); 2953 dmacfg &= ~GEM_BIT(ENDIA_PKT); 2954 2955 if (bp->native_io) 2956 dmacfg &= ~GEM_BIT(ENDIA_DESC); 2957 else 2958 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */ 2959 2960 if (bp->netdev->features & NETIF_F_HW_CSUM) 2961 dmacfg |= GEM_BIT(TXCOEN); 2962 else 2963 dmacfg &= ~GEM_BIT(TXCOEN); 2964 2965 dmacfg &= ~GEM_BIT(ADDR64); 2966 if (macb_dma64(bp)) 2967 dmacfg |= GEM_BIT(ADDR64); 2968 if (macb_dma_ptp(bp)) 2969 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT); 2970 netdev_dbg(bp->netdev, "Cadence configure DMA with 0x%08x\n", 2971 dmacfg); 2972 gem_writel(bp, DMACFG, dmacfg); 2973 } 2974 } 2975 2976 static void macb_init_hw(struct macb *bp) 2977 { 2978 u32 config; 2979 2980 macb_reset_hw(bp); 2981 macb_set_hwaddr(bp); 2982 2983 config = macb_mdc_clk_div(bp); 2984 /* Make eth data aligned. 2985 * If RSC capable, that offset is ignored by HW. 2986 */ 2987 if (!(bp->caps & MACB_CAPS_RSC)) 2988 config |= MACB_BF(RBOF, NET_IP_ALIGN); 2989 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */ 2990 if (bp->caps & MACB_CAPS_JUMBO) 2991 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */ 2992 else 2993 config |= MACB_BIT(BIG); /* Receive oversized frames */ 2994 if (bp->netdev->flags & IFF_PROMISC) 2995 config |= MACB_BIT(CAF); /* Copy All Frames */ 2996 else if (macb_is_gem(bp) && bp->netdev->features & NETIF_F_RXCSUM) 2997 config |= GEM_BIT(RXCOEN); 2998 if (!(bp->netdev->flags & IFF_BROADCAST)) 2999 config |= MACB_BIT(NBC); /* No BroadCast */ 3000 config |= macb_dbw(bp); 3001 macb_writel(bp, NCFGR, config); 3002 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len) 3003 gem_writel(bp, JML, bp->jumbo_max_len); 3004 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK; 3005 if (bp->caps & MACB_CAPS_JUMBO) 3006 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK; 3007 3008 macb_configure_dma(bp); 3009 3010 /* Enable RX partial store and forward and set watermark */ 3011 if (bp->rx_watermark) 3012 gem_writel(bp, PBUFRXCUT, (bp->rx_watermark | GEM_BIT(ENCUTTHRU))); 3013 } 3014 3015 /* The hash address register is 64 bits long and takes up two 3016 * locations in the memory map. The least significant bits are stored 3017 * in EMAC_HSL and the most significant bits in EMAC_HSH. 3018 * 3019 * The unicast hash enable and the multicast hash enable bits in the 3020 * network configuration register enable the reception of hash matched 3021 * frames. The destination address is reduced to a 6 bit index into 3022 * the 64 bit hash register using the following hash function. The 3023 * hash function is an exclusive or of every sixth bit of the 3024 * destination address. 3025 * 3026 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] 3027 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] 3028 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] 3029 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] 3030 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] 3031 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] 3032 * 3033 * da[0] represents the least significant bit of the first byte 3034 * received, that is, the multicast/unicast indicator, and da[47] 3035 * represents the most significant bit of the last byte received. If 3036 * the hash index, hi[n], points to a bit that is set in the hash 3037 * register then the frame will be matched according to whether the 3038 * frame is multicast or unicast. A multicast match will be signalled 3039 * if the multicast hash enable bit is set, da[0] is 1 and the hash 3040 * index points to a bit set in the hash register. A unicast match 3041 * will be signalled if the unicast hash enable bit is set, da[0] is 0 3042 * and the hash index points to a bit set in the hash register. To 3043 * receive all multicast frames, the hash register should be set with 3044 * all ones and the multicast hash enable bit should be set in the 3045 * network configuration register. 3046 */ 3047 3048 static inline int hash_bit_value(int bitnr, __u8 *addr) 3049 { 3050 if (addr[bitnr / 8] & (1 << (bitnr % 8))) 3051 return 1; 3052 return 0; 3053 } 3054 3055 /* Return the hash index value for the specified address. */ 3056 static int hash_get_index(__u8 *addr) 3057 { 3058 int i, j, bitval; 3059 int hash_index = 0; 3060 3061 for (j = 0; j < 6; j++) { 3062 for (i = 0, bitval = 0; i < 8; i++) 3063 bitval ^= hash_bit_value(i * 6 + j, addr); 3064 3065 hash_index |= (bitval << j); 3066 } 3067 3068 return hash_index; 3069 } 3070 3071 /* Add multicast addresses to the internal multicast-hash table. */ 3072 static void macb_sethashtable(struct net_device *netdev) 3073 { 3074 struct netdev_hw_addr *ha; 3075 unsigned long mc_filter[2]; 3076 unsigned int bitnr; 3077 struct macb *bp = netdev_priv(netdev); 3078 3079 mc_filter[0] = 0; 3080 mc_filter[1] = 0; 3081 3082 netdev_for_each_mc_addr(ha, netdev) { 3083 bitnr = hash_get_index(ha->addr); 3084 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); 3085 } 3086 3087 macb_or_gem_writel(bp, HRB, mc_filter[0]); 3088 macb_or_gem_writel(bp, HRT, mc_filter[1]); 3089 } 3090 3091 /* Enable/Disable promiscuous and multicast modes. */ 3092 static void macb_set_rx_mode(struct net_device *netdev) 3093 { 3094 unsigned long cfg; 3095 struct macb *bp = netdev_priv(netdev); 3096 3097 cfg = macb_readl(bp, NCFGR); 3098 3099 if (netdev->flags & IFF_PROMISC) { 3100 /* Enable promiscuous mode */ 3101 cfg |= MACB_BIT(CAF); 3102 3103 /* Disable RX checksum offload */ 3104 if (macb_is_gem(bp)) 3105 cfg &= ~GEM_BIT(RXCOEN); 3106 } else { 3107 /* Disable promiscuous mode */ 3108 cfg &= ~MACB_BIT(CAF); 3109 3110 /* Enable RX checksum offload only if requested */ 3111 if (macb_is_gem(bp) && netdev->features & NETIF_F_RXCSUM) 3112 cfg |= GEM_BIT(RXCOEN); 3113 } 3114 3115 if (netdev->flags & IFF_ALLMULTI) { 3116 /* Enable all multicast mode */ 3117 macb_or_gem_writel(bp, HRB, -1); 3118 macb_or_gem_writel(bp, HRT, -1); 3119 cfg |= MACB_BIT(NCFGR_MTI); 3120 } else if (!netdev_mc_empty(netdev)) { 3121 /* Enable specific multicasts */ 3122 macb_sethashtable(netdev); 3123 cfg |= MACB_BIT(NCFGR_MTI); 3124 } else if (netdev->flags & (~IFF_ALLMULTI)) { 3125 /* Disable all multicast mode */ 3126 macb_or_gem_writel(bp, HRB, 0); 3127 macb_or_gem_writel(bp, HRT, 0); 3128 cfg &= ~MACB_BIT(NCFGR_MTI); 3129 } 3130 3131 macb_writel(bp, NCFGR, cfg); 3132 } 3133 3134 static int macb_open(struct net_device *netdev) 3135 { 3136 size_t bufsz = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN; 3137 struct macb *bp = netdev_priv(netdev); 3138 struct macb_queue *queue; 3139 unsigned int q; 3140 int err; 3141 3142 netdev_dbg(bp->netdev, "open\n"); 3143 3144 err = pm_runtime_resume_and_get(&bp->pdev->dev); 3145 if (err < 0) 3146 return err; 3147 3148 /* RX buffers initialization */ 3149 macb_init_rx_buffer_size(bp, bufsz); 3150 3151 err = macb_alloc(bp); 3152 if (err) { 3153 netdev_err(netdev, "Unable to allocate DMA memory (error %d)\n", 3154 err); 3155 goto pm_exit; 3156 } 3157 3158 bp->macbgem_ops.mog_init_rings(bp); 3159 macb_init_buffers(bp); 3160 3161 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 3162 napi_enable(&queue->napi_rx); 3163 napi_enable(&queue->napi_tx); 3164 } 3165 3166 macb_init_hw(bp); 3167 3168 err = phy_set_mode_ext(bp->phy, PHY_MODE_ETHERNET, bp->phy_interface); 3169 if (err) 3170 goto reset_hw; 3171 3172 err = phy_power_on(bp->phy); 3173 if (err) 3174 goto reset_hw; 3175 3176 err = macb_phylink_connect(bp); 3177 if (err) 3178 goto phy_off; 3179 3180 netif_tx_start_all_queues(netdev); 3181 3182 if (bp->ptp_info) 3183 bp->ptp_info->ptp_init(netdev); 3184 3185 return 0; 3186 3187 phy_off: 3188 phy_power_off(bp->phy); 3189 3190 reset_hw: 3191 macb_reset_hw(bp); 3192 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 3193 napi_disable(&queue->napi_rx); 3194 napi_disable(&queue->napi_tx); 3195 } 3196 macb_free(bp); 3197 pm_exit: 3198 pm_runtime_put_sync(&bp->pdev->dev); 3199 return err; 3200 } 3201 3202 static int macb_close(struct net_device *netdev) 3203 { 3204 struct macb *bp = netdev_priv(netdev); 3205 struct macb_queue *queue; 3206 unsigned long flags; 3207 unsigned int q; 3208 3209 netif_tx_stop_all_queues(netdev); 3210 3211 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 3212 napi_disable(&queue->napi_rx); 3213 napi_disable(&queue->napi_tx); 3214 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, q)); 3215 } 3216 3217 cancel_delayed_work_sync(&bp->tx_lpi_work); 3218 3219 phylink_stop(bp->phylink); 3220 phylink_disconnect_phy(bp->phylink); 3221 3222 phy_power_off(bp->phy); 3223 3224 spin_lock_irqsave(&bp->lock, flags); 3225 macb_reset_hw(bp); 3226 netif_carrier_off(netdev); 3227 spin_unlock_irqrestore(&bp->lock, flags); 3228 3229 macb_free(bp); 3230 3231 if (bp->ptp_info) 3232 bp->ptp_info->ptp_remove(netdev); 3233 3234 pm_runtime_put(&bp->pdev->dev); 3235 3236 return 0; 3237 } 3238 3239 static int macb_change_mtu(struct net_device *netdev, int new_mtu) 3240 { 3241 if (netif_running(netdev)) 3242 return -EBUSY; 3243 3244 WRITE_ONCE(netdev->mtu, new_mtu); 3245 3246 return 0; 3247 } 3248 3249 static int macb_set_mac_addr(struct net_device *netdev, void *addr) 3250 { 3251 int err; 3252 3253 err = eth_mac_addr(netdev, addr); 3254 if (err < 0) 3255 return err; 3256 3257 macb_set_hwaddr(netdev_priv(netdev)); 3258 return 0; 3259 } 3260 3261 static void gem_update_stats(struct macb *bp) 3262 { 3263 struct macb_queue *queue; 3264 unsigned int i, q, idx; 3265 unsigned long *stat; 3266 3267 u64 *p = &bp->hw_stats.gem.tx_octets; 3268 3269 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) { 3270 u32 offset = gem_statistics[i].offset; 3271 u64 val = bp->macb_reg_readl(bp, offset); 3272 3273 bp->ethtool_stats[i] += val; 3274 *p += val; 3275 3276 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) { 3277 /* Add GEM_OCTTXH, GEM_OCTRXH */ 3278 val = bp->macb_reg_readl(bp, offset + 4); 3279 bp->ethtool_stats[i] += ((u64)val) << 32; 3280 *p += ((u64)val) << 32; 3281 } 3282 } 3283 3284 idx = GEM_STATS_LEN; 3285 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) 3286 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat) 3287 bp->ethtool_stats[idx++] = *stat; 3288 } 3289 3290 static void gem_get_stats(struct macb *bp, struct rtnl_link_stats64 *nstat) 3291 { 3292 struct gem_stats *hwstat = &bp->hw_stats.gem; 3293 3294 spin_lock_irq(&bp->stats_lock); 3295 if (netif_running(bp->netdev)) 3296 gem_update_stats(bp); 3297 3298 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors + 3299 hwstat->rx_alignment_errors + 3300 hwstat->rx_resource_errors + 3301 hwstat->rx_overruns + 3302 hwstat->rx_oversize_frames + 3303 hwstat->rx_jabbers + 3304 hwstat->rx_undersized_frames + 3305 hwstat->rx_length_field_frame_errors); 3306 nstat->tx_errors = (hwstat->tx_late_collisions + 3307 hwstat->tx_excessive_collisions + 3308 hwstat->tx_underrun + 3309 hwstat->tx_carrier_sense_errors); 3310 nstat->multicast = hwstat->rx_multicast_frames; 3311 nstat->collisions = (hwstat->tx_single_collision_frames + 3312 hwstat->tx_multiple_collision_frames + 3313 hwstat->tx_excessive_collisions); 3314 nstat->rx_length_errors = (hwstat->rx_oversize_frames + 3315 hwstat->rx_jabbers + 3316 hwstat->rx_undersized_frames + 3317 hwstat->rx_length_field_frame_errors); 3318 nstat->rx_over_errors = hwstat->rx_resource_errors; 3319 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors; 3320 nstat->rx_frame_errors = hwstat->rx_alignment_errors; 3321 nstat->rx_fifo_errors = hwstat->rx_overruns; 3322 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions; 3323 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors; 3324 nstat->tx_fifo_errors = hwstat->tx_underrun; 3325 spin_unlock_irq(&bp->stats_lock); 3326 } 3327 3328 static void gem_get_ethtool_stats(struct net_device *netdev, 3329 struct ethtool_stats *stats, u64 *data) 3330 { 3331 struct macb *bp = netdev_priv(netdev); 3332 3333 spin_lock_irq(&bp->stats_lock); 3334 gem_update_stats(bp); 3335 memcpy(data, &bp->ethtool_stats, sizeof(u64) 3336 * (GEM_STATS_LEN + QUEUE_STATS_LEN * bp->num_queues)); 3337 spin_unlock_irq(&bp->stats_lock); 3338 } 3339 3340 static int gem_get_sset_count(struct net_device *netdev, int sset) 3341 { 3342 struct macb *bp = netdev_priv(netdev); 3343 3344 switch (sset) { 3345 case ETH_SS_STATS: 3346 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN; 3347 default: 3348 return -EOPNOTSUPP; 3349 } 3350 } 3351 3352 static void gem_get_ethtool_strings(struct net_device *netdev, u32 sset, u8 *p) 3353 { 3354 struct macb *bp = netdev_priv(netdev); 3355 struct macb_queue *queue; 3356 unsigned int i; 3357 unsigned int q; 3358 3359 switch (sset) { 3360 case ETH_SS_STATS: 3361 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN) 3362 memcpy(p, gem_statistics[i].stat_string, 3363 ETH_GSTRING_LEN); 3364 3365 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 3366 for (i = 0; i < QUEUE_STATS_LEN; i++) 3367 ethtool_sprintf(&p, "q%u_%s", q, queue_statistics[i].stat_string); 3368 } 3369 break; 3370 } 3371 } 3372 3373 static void macb_get_stats(struct net_device *netdev, 3374 struct rtnl_link_stats64 *nstat) 3375 { 3376 struct macb *bp = netdev_priv(netdev); 3377 struct macb_stats *hwstat = &bp->hw_stats.macb; 3378 3379 netdev_stats_to_stats64(nstat, &bp->netdev->stats); 3380 if (macb_is_gem(bp)) { 3381 gem_get_stats(bp, nstat); 3382 return; 3383 } 3384 3385 /* read stats from hardware */ 3386 spin_lock_irq(&bp->stats_lock); 3387 macb_update_stats(bp); 3388 3389 /* Convert HW stats into netdevice stats */ 3390 nstat->rx_errors = (hwstat->rx_fcs_errors + 3391 hwstat->rx_align_errors + 3392 hwstat->rx_resource_errors + 3393 hwstat->rx_overruns + 3394 hwstat->rx_oversize_pkts + 3395 hwstat->rx_jabbers + 3396 hwstat->rx_undersize_pkts + 3397 hwstat->rx_length_mismatch); 3398 nstat->tx_errors = (hwstat->tx_late_cols + 3399 hwstat->tx_excessive_cols + 3400 hwstat->tx_underruns + 3401 hwstat->tx_carrier_errors + 3402 hwstat->sqe_test_errors); 3403 nstat->collisions = (hwstat->tx_single_cols + 3404 hwstat->tx_multiple_cols + 3405 hwstat->tx_excessive_cols); 3406 nstat->rx_length_errors = (hwstat->rx_oversize_pkts + 3407 hwstat->rx_jabbers + 3408 hwstat->rx_undersize_pkts + 3409 hwstat->rx_length_mismatch); 3410 nstat->rx_over_errors = hwstat->rx_resource_errors + 3411 hwstat->rx_overruns; 3412 nstat->rx_crc_errors = hwstat->rx_fcs_errors; 3413 nstat->rx_frame_errors = hwstat->rx_align_errors; 3414 nstat->rx_fifo_errors = hwstat->rx_overruns; 3415 /* XXX: What does "missed" mean? */ 3416 nstat->tx_aborted_errors = hwstat->tx_excessive_cols; 3417 nstat->tx_carrier_errors = hwstat->tx_carrier_errors; 3418 nstat->tx_fifo_errors = hwstat->tx_underruns; 3419 /* Don't know about heartbeat or window errors... */ 3420 spin_unlock_irq(&bp->stats_lock); 3421 } 3422 3423 static void macb_get_pause_stats(struct net_device *netdev, 3424 struct ethtool_pause_stats *pause_stats) 3425 { 3426 struct macb *bp = netdev_priv(netdev); 3427 struct macb_stats *hwstat = &bp->hw_stats.macb; 3428 3429 spin_lock_irq(&bp->stats_lock); 3430 macb_update_stats(bp); 3431 pause_stats->tx_pause_frames = hwstat->tx_pause_frames; 3432 pause_stats->rx_pause_frames = hwstat->rx_pause_frames; 3433 spin_unlock_irq(&bp->stats_lock); 3434 } 3435 3436 static void gem_get_pause_stats(struct net_device *netdev, 3437 struct ethtool_pause_stats *pause_stats) 3438 { 3439 struct macb *bp = netdev_priv(netdev); 3440 struct gem_stats *hwstat = &bp->hw_stats.gem; 3441 3442 spin_lock_irq(&bp->stats_lock); 3443 gem_update_stats(bp); 3444 pause_stats->tx_pause_frames = hwstat->tx_pause_frames; 3445 pause_stats->rx_pause_frames = hwstat->rx_pause_frames; 3446 spin_unlock_irq(&bp->stats_lock); 3447 } 3448 3449 static void macb_get_eth_mac_stats(struct net_device *netdev, 3450 struct ethtool_eth_mac_stats *mac_stats) 3451 { 3452 struct macb *bp = netdev_priv(netdev); 3453 struct macb_stats *hwstat = &bp->hw_stats.macb; 3454 3455 spin_lock_irq(&bp->stats_lock); 3456 macb_update_stats(bp); 3457 mac_stats->FramesTransmittedOK = hwstat->tx_ok; 3458 mac_stats->SingleCollisionFrames = hwstat->tx_single_cols; 3459 mac_stats->MultipleCollisionFrames = hwstat->tx_multiple_cols; 3460 mac_stats->FramesReceivedOK = hwstat->rx_ok; 3461 mac_stats->FrameCheckSequenceErrors = hwstat->rx_fcs_errors; 3462 mac_stats->AlignmentErrors = hwstat->rx_align_errors; 3463 mac_stats->FramesWithDeferredXmissions = hwstat->tx_deferred; 3464 mac_stats->LateCollisions = hwstat->tx_late_cols; 3465 mac_stats->FramesAbortedDueToXSColls = hwstat->tx_excessive_cols; 3466 mac_stats->FramesLostDueToIntMACXmitError = hwstat->tx_underruns; 3467 mac_stats->CarrierSenseErrors = hwstat->tx_carrier_errors; 3468 mac_stats->FramesLostDueToIntMACRcvError = hwstat->rx_overruns; 3469 mac_stats->InRangeLengthErrors = hwstat->rx_length_mismatch; 3470 mac_stats->FrameTooLongErrors = hwstat->rx_oversize_pkts; 3471 spin_unlock_irq(&bp->stats_lock); 3472 } 3473 3474 static void gem_get_eth_mac_stats(struct net_device *netdev, 3475 struct ethtool_eth_mac_stats *mac_stats) 3476 { 3477 struct macb *bp = netdev_priv(netdev); 3478 struct gem_stats *hwstat = &bp->hw_stats.gem; 3479 3480 spin_lock_irq(&bp->stats_lock); 3481 gem_update_stats(bp); 3482 mac_stats->FramesTransmittedOK = hwstat->tx_frames; 3483 mac_stats->SingleCollisionFrames = hwstat->tx_single_collision_frames; 3484 mac_stats->MultipleCollisionFrames = 3485 hwstat->tx_multiple_collision_frames; 3486 mac_stats->FramesReceivedOK = hwstat->rx_frames; 3487 mac_stats->FrameCheckSequenceErrors = 3488 hwstat->rx_frame_check_sequence_errors; 3489 mac_stats->AlignmentErrors = hwstat->rx_alignment_errors; 3490 mac_stats->OctetsTransmittedOK = hwstat->tx_octets; 3491 mac_stats->FramesWithDeferredXmissions = hwstat->tx_deferred_frames; 3492 mac_stats->LateCollisions = hwstat->tx_late_collisions; 3493 mac_stats->FramesAbortedDueToXSColls = hwstat->tx_excessive_collisions; 3494 mac_stats->FramesLostDueToIntMACXmitError = hwstat->tx_underrun; 3495 mac_stats->CarrierSenseErrors = hwstat->tx_carrier_sense_errors; 3496 mac_stats->OctetsReceivedOK = hwstat->rx_octets; 3497 mac_stats->MulticastFramesXmittedOK = hwstat->tx_multicast_frames; 3498 mac_stats->BroadcastFramesXmittedOK = hwstat->tx_broadcast_frames; 3499 mac_stats->MulticastFramesReceivedOK = hwstat->rx_multicast_frames; 3500 mac_stats->BroadcastFramesReceivedOK = hwstat->rx_broadcast_frames; 3501 mac_stats->InRangeLengthErrors = hwstat->rx_length_field_frame_errors; 3502 mac_stats->FrameTooLongErrors = hwstat->rx_oversize_frames; 3503 spin_unlock_irq(&bp->stats_lock); 3504 } 3505 3506 /* TODO: Report SQE test errors when added to phy_stats */ 3507 static void macb_get_eth_phy_stats(struct net_device *netdev, 3508 struct ethtool_eth_phy_stats *phy_stats) 3509 { 3510 struct macb *bp = netdev_priv(netdev); 3511 struct macb_stats *hwstat = &bp->hw_stats.macb; 3512 3513 spin_lock_irq(&bp->stats_lock); 3514 macb_update_stats(bp); 3515 phy_stats->SymbolErrorDuringCarrier = hwstat->rx_symbol_errors; 3516 spin_unlock_irq(&bp->stats_lock); 3517 } 3518 3519 static void gem_get_eth_phy_stats(struct net_device *netdev, 3520 struct ethtool_eth_phy_stats *phy_stats) 3521 { 3522 struct macb *bp = netdev_priv(netdev); 3523 struct gem_stats *hwstat = &bp->hw_stats.gem; 3524 3525 spin_lock_irq(&bp->stats_lock); 3526 gem_update_stats(bp); 3527 phy_stats->SymbolErrorDuringCarrier = hwstat->rx_symbol_errors; 3528 spin_unlock_irq(&bp->stats_lock); 3529 } 3530 3531 static void macb_get_rmon_stats(struct net_device *netdev, 3532 struct ethtool_rmon_stats *rmon_stats, 3533 const struct ethtool_rmon_hist_range **ranges) 3534 { 3535 struct macb *bp = netdev_priv(netdev); 3536 struct macb_stats *hwstat = &bp->hw_stats.macb; 3537 3538 spin_lock_irq(&bp->stats_lock); 3539 macb_update_stats(bp); 3540 rmon_stats->undersize_pkts = hwstat->rx_undersize_pkts; 3541 rmon_stats->oversize_pkts = hwstat->rx_oversize_pkts; 3542 rmon_stats->jabbers = hwstat->rx_jabbers; 3543 spin_unlock_irq(&bp->stats_lock); 3544 } 3545 3546 static const struct ethtool_rmon_hist_range gem_rmon_ranges[] = { 3547 { 64, 64 }, 3548 { 65, 127 }, 3549 { 128, 255 }, 3550 { 256, 511 }, 3551 { 512, 1023 }, 3552 { 1024, 1518 }, 3553 { 1519, 16384 }, 3554 { }, 3555 }; 3556 3557 static void gem_get_rmon_stats(struct net_device *netdev, 3558 struct ethtool_rmon_stats *rmon_stats, 3559 const struct ethtool_rmon_hist_range **ranges) 3560 { 3561 struct macb *bp = netdev_priv(netdev); 3562 struct gem_stats *hwstat = &bp->hw_stats.gem; 3563 3564 spin_lock_irq(&bp->stats_lock); 3565 gem_update_stats(bp); 3566 rmon_stats->undersize_pkts = hwstat->rx_undersized_frames; 3567 rmon_stats->oversize_pkts = hwstat->rx_oversize_frames; 3568 rmon_stats->jabbers = hwstat->rx_jabbers; 3569 rmon_stats->hist[0] = hwstat->rx_64_byte_frames; 3570 rmon_stats->hist[1] = hwstat->rx_65_127_byte_frames; 3571 rmon_stats->hist[2] = hwstat->rx_128_255_byte_frames; 3572 rmon_stats->hist[3] = hwstat->rx_256_511_byte_frames; 3573 rmon_stats->hist[4] = hwstat->rx_512_1023_byte_frames; 3574 rmon_stats->hist[5] = hwstat->rx_1024_1518_byte_frames; 3575 rmon_stats->hist[6] = hwstat->rx_greater_than_1518_byte_frames; 3576 rmon_stats->hist_tx[0] = hwstat->tx_64_byte_frames; 3577 rmon_stats->hist_tx[1] = hwstat->tx_65_127_byte_frames; 3578 rmon_stats->hist_tx[2] = hwstat->tx_128_255_byte_frames; 3579 rmon_stats->hist_tx[3] = hwstat->tx_256_511_byte_frames; 3580 rmon_stats->hist_tx[4] = hwstat->tx_512_1023_byte_frames; 3581 rmon_stats->hist_tx[5] = hwstat->tx_1024_1518_byte_frames; 3582 rmon_stats->hist_tx[6] = hwstat->tx_greater_than_1518_byte_frames; 3583 spin_unlock_irq(&bp->stats_lock); 3584 *ranges = gem_rmon_ranges; 3585 } 3586 3587 static int macb_get_regs_len(struct net_device *netdev) 3588 { 3589 return MACB_GREGS_NBR * sizeof(u32); 3590 } 3591 3592 static void macb_get_regs(struct net_device *netdev, struct ethtool_regs *regs, 3593 void *p) 3594 { 3595 struct macb *bp = netdev_priv(netdev); 3596 unsigned int tail, head; 3597 u32 *regs_buff = p; 3598 3599 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1)) 3600 | MACB_GREGS_VERSION; 3601 3602 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail); 3603 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head); 3604 3605 regs_buff[0] = macb_readl(bp, NCR); 3606 regs_buff[1] = macb_or_gem_readl(bp, NCFGR); 3607 regs_buff[2] = macb_readl(bp, NSR); 3608 regs_buff[3] = macb_readl(bp, TSR); 3609 regs_buff[4] = macb_readl(bp, RBQP); 3610 regs_buff[5] = macb_readl(bp, TBQP); 3611 regs_buff[6] = macb_readl(bp, RSR); 3612 regs_buff[7] = macb_readl(bp, IMR); 3613 3614 regs_buff[8] = tail; 3615 regs_buff[9] = head; 3616 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail); 3617 regs_buff[11] = macb_tx_dma(&bp->queues[0], head); 3618 3619 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) 3620 regs_buff[12] = macb_or_gem_readl(bp, USRIO); 3621 if (macb_is_gem(bp)) 3622 regs_buff[13] = gem_readl(bp, DMACFG); 3623 } 3624 3625 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 3626 { 3627 struct macb *bp = netdev_priv(netdev); 3628 3629 phylink_ethtool_get_wol(bp->phylink, wol); 3630 wol->supported |= (WAKE_MAGIC | WAKE_ARP); 3631 3632 /* Add macb wolopts to phy wolopts */ 3633 wol->wolopts |= bp->wolopts; 3634 } 3635 3636 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 3637 { 3638 struct macb *bp = netdev_priv(netdev); 3639 int ret; 3640 3641 /* Pass the order to phylink layer */ 3642 ret = phylink_ethtool_set_wol(bp->phylink, wol); 3643 /* Don't manage WoL on MAC, if PHY set_wol() fails */ 3644 if (ret && ret != -EOPNOTSUPP) 3645 return ret; 3646 3647 bp->wolopts = (wol->wolopts & WAKE_MAGIC) ? WAKE_MAGIC : 0; 3648 bp->wolopts |= (wol->wolopts & WAKE_ARP) ? WAKE_ARP : 0; 3649 bp->wol = (wol->wolopts) ? MACB_WOL_ENABLED : 0; 3650 3651 device_set_wakeup_enable(&bp->pdev->dev, bp->wol); 3652 3653 return 0; 3654 } 3655 3656 static int macb_get_link_ksettings(struct net_device *netdev, 3657 struct ethtool_link_ksettings *kset) 3658 { 3659 struct macb *bp = netdev_priv(netdev); 3660 3661 return phylink_ethtool_ksettings_get(bp->phylink, kset); 3662 } 3663 3664 static int macb_set_link_ksettings(struct net_device *netdev, 3665 const struct ethtool_link_ksettings *kset) 3666 { 3667 struct macb *bp = netdev_priv(netdev); 3668 3669 return phylink_ethtool_ksettings_set(bp->phylink, kset); 3670 } 3671 3672 static void macb_get_ringparam(struct net_device *netdev, 3673 struct ethtool_ringparam *ring, 3674 struct kernel_ethtool_ringparam *kernel_ring, 3675 struct netlink_ext_ack *extack) 3676 { 3677 struct macb *bp = netdev_priv(netdev); 3678 3679 ring->rx_max_pending = MAX_RX_RING_SIZE; 3680 ring->tx_max_pending = MAX_TX_RING_SIZE; 3681 3682 ring->rx_pending = bp->rx_ring_size; 3683 ring->tx_pending = bp->tx_ring_size; 3684 } 3685 3686 static int macb_set_ringparam(struct net_device *netdev, 3687 struct ethtool_ringparam *ring, 3688 struct kernel_ethtool_ringparam *kernel_ring, 3689 struct netlink_ext_ack *extack) 3690 { 3691 struct macb *bp = netdev_priv(netdev); 3692 u32 new_rx_size, new_tx_size; 3693 unsigned int reset = 0; 3694 3695 if (bp->caps & MACB_CAPS_MACB_IS_EMAC) 3696 return -EOPNOTSUPP; 3697 3698 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 3699 return -EINVAL; 3700 3701 new_rx_size = clamp_t(u32, ring->rx_pending, 3702 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE); 3703 new_rx_size = roundup_pow_of_two(new_rx_size); 3704 3705 new_tx_size = clamp_t(u32, ring->tx_pending, 3706 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE); 3707 new_tx_size = roundup_pow_of_two(new_tx_size); 3708 3709 if ((new_tx_size == bp->tx_ring_size) && 3710 (new_rx_size == bp->rx_ring_size)) { 3711 /* nothing to do */ 3712 return 0; 3713 } 3714 3715 if (netif_running(bp->netdev)) { 3716 reset = 1; 3717 macb_close(bp->netdev); 3718 } 3719 3720 bp->rx_ring_size = new_rx_size; 3721 bp->tx_ring_size = new_tx_size; 3722 3723 if (reset) 3724 macb_open(bp->netdev); 3725 3726 return 0; 3727 } 3728 3729 #ifdef CONFIG_MACB_USE_HWSTAMP 3730 static unsigned int gem_get_tsu_rate(struct macb *bp) 3731 { 3732 struct clk *tsu_clk; 3733 unsigned int tsu_rate; 3734 3735 if (!IS_ERR_OR_NULL(bp->tsu_clk)) { 3736 tsu_rate = clk_get_rate(bp->tsu_clk); 3737 } else { 3738 tsu_clk = bp->pclk; 3739 tsu_rate = clk_get_rate(tsu_clk); 3740 dev_warn(&bp->pdev->dev, "devicetree missing tsu_clk, using pclk as fallback\n"); 3741 } 3742 3743 return tsu_rate; 3744 } 3745 3746 static s32 gem_get_ptp_max_adj(void) 3747 { 3748 return 64000000; 3749 } 3750 3751 static int gem_get_ts_info(struct net_device *netdev, 3752 struct kernel_ethtool_ts_info *info) 3753 { 3754 struct macb *bp = netdev_priv(netdev); 3755 3756 if (!macb_dma_ptp(bp)) { 3757 ethtool_op_get_ts_info(netdev, info); 3758 return 0; 3759 } 3760 3761 info->so_timestamping = 3762 SOF_TIMESTAMPING_TX_SOFTWARE | 3763 SOF_TIMESTAMPING_TX_HARDWARE | 3764 SOF_TIMESTAMPING_RX_HARDWARE | 3765 SOF_TIMESTAMPING_RAW_HARDWARE; 3766 info->tx_types = 3767 (1 << HWTSTAMP_TX_ONESTEP_SYNC) | 3768 (1 << HWTSTAMP_TX_OFF) | 3769 (1 << HWTSTAMP_TX_ON); 3770 info->rx_filters = 3771 (1 << HWTSTAMP_FILTER_NONE) | 3772 (1 << HWTSTAMP_FILTER_ALL); 3773 3774 if (bp->ptp_clock) 3775 info->phc_index = ptp_clock_index(bp->ptp_clock); 3776 3777 return 0; 3778 } 3779 3780 static struct macb_ptp_info gem_ptp_info = { 3781 .ptp_init = gem_ptp_init, 3782 .ptp_remove = gem_ptp_remove, 3783 .get_ptp_max_adj = gem_get_ptp_max_adj, 3784 .get_tsu_rate = gem_get_tsu_rate, 3785 .get_ts_info = gem_get_ts_info, 3786 .get_hwtst = gem_get_hwtst, 3787 .set_hwtst = gem_set_hwtst, 3788 }; 3789 #endif 3790 3791 static int macb_get_ts_info(struct net_device *netdev, 3792 struct kernel_ethtool_ts_info *info) 3793 { 3794 struct macb *bp = netdev_priv(netdev); 3795 3796 if (bp->ptp_info) 3797 return bp->ptp_info->get_ts_info(netdev, info); 3798 3799 return ethtool_op_get_ts_info(netdev, info); 3800 } 3801 3802 static void gem_enable_flow_filters(struct macb *bp, bool enable) 3803 { 3804 struct net_device *netdev = bp->netdev; 3805 struct ethtool_rx_fs_item *item; 3806 u32 t2_scr; 3807 int num_t2_scr; 3808 3809 if (!(netdev->features & NETIF_F_NTUPLE)) 3810 return; 3811 3812 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8)); 3813 3814 list_for_each_entry(item, &bp->rx_fs_list.list, list) { 3815 struct ethtool_rx_flow_spec *fs = &item->fs; 3816 struct ethtool_tcpip4_spec *tp4sp_m; 3817 3818 if (fs->location >= num_t2_scr) 3819 continue; 3820 3821 t2_scr = gem_readl_n(bp, SCRT2, fs->location); 3822 3823 /* enable/disable screener regs for the flow entry */ 3824 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr); 3825 3826 /* only enable fields with no masking */ 3827 tp4sp_m = &(fs->m_u.tcp_ip4_spec); 3828 3829 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF)) 3830 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr); 3831 else 3832 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr); 3833 3834 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF)) 3835 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr); 3836 else 3837 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr); 3838 3839 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF))) 3840 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr); 3841 else 3842 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr); 3843 3844 gem_writel_n(bp, SCRT2, fs->location, t2_scr); 3845 } 3846 } 3847 3848 static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs) 3849 { 3850 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m; 3851 uint16_t index = fs->location; 3852 u32 w0, w1, t2_scr; 3853 bool cmp_a = false; 3854 bool cmp_b = false; 3855 bool cmp_c = false; 3856 3857 if (!macb_is_gem(bp)) 3858 return; 3859 3860 tp4sp_v = &(fs->h_u.tcp_ip4_spec); 3861 tp4sp_m = &(fs->m_u.tcp_ip4_spec); 3862 3863 /* ignore field if any masking set */ 3864 if (tp4sp_m->ip4src == 0xFFFFFFFF) { 3865 /* 1st compare reg - IP source address */ 3866 w0 = 0; 3867 w1 = 0; 3868 w0 = tp4sp_v->ip4src; 3869 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */ 3870 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1); 3871 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1); 3872 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0); 3873 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1); 3874 cmp_a = true; 3875 } 3876 3877 /* ignore field if any masking set */ 3878 if (tp4sp_m->ip4dst == 0xFFFFFFFF) { 3879 /* 2nd compare reg - IP destination address */ 3880 w0 = 0; 3881 w1 = 0; 3882 w0 = tp4sp_v->ip4dst; 3883 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */ 3884 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1); 3885 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1); 3886 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0); 3887 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1); 3888 cmp_b = true; 3889 } 3890 3891 /* ignore both port fields if masking set in both */ 3892 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) { 3893 /* 3rd compare reg - source port, destination port */ 3894 w0 = 0; 3895 w1 = 0; 3896 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1); 3897 if (tp4sp_m->psrc == tp4sp_m->pdst) { 3898 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0); 3899 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0); 3900 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */ 3901 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1); 3902 } else { 3903 /* only one port definition */ 3904 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */ 3905 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0); 3906 if (tp4sp_m->psrc == 0xFFFF) { /* src port */ 3907 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0); 3908 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1); 3909 } else { /* dst port */ 3910 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0); 3911 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1); 3912 } 3913 } 3914 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0); 3915 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1); 3916 cmp_c = true; 3917 } 3918 3919 t2_scr = 0; 3920 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr); 3921 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr); 3922 if (cmp_a) 3923 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr); 3924 if (cmp_b) 3925 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr); 3926 if (cmp_c) 3927 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr); 3928 gem_writel_n(bp, SCRT2, index, t2_scr); 3929 } 3930 3931 static int gem_add_flow_filter(struct net_device *netdev, 3932 struct ethtool_rxnfc *cmd) 3933 { 3934 struct macb *bp = netdev_priv(netdev); 3935 struct ethtool_rx_flow_spec *fs = &cmd->fs; 3936 struct ethtool_rx_fs_item *item, *newfs; 3937 unsigned long flags; 3938 int ret = -EINVAL; 3939 bool added = false; 3940 3941 newfs = kmalloc_obj(*newfs); 3942 if (newfs == NULL) 3943 return -ENOMEM; 3944 memcpy(&newfs->fs, fs, sizeof(newfs->fs)); 3945 3946 netdev_dbg(netdev, 3947 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n", 3948 fs->flow_type, (int)fs->ring_cookie, fs->location, 3949 htonl(fs->h_u.tcp_ip4_spec.ip4src), 3950 htonl(fs->h_u.tcp_ip4_spec.ip4dst), 3951 be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc), 3952 be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst)); 3953 3954 spin_lock_irqsave(&bp->rx_fs_lock, flags); 3955 3956 /* find correct place to add in list */ 3957 list_for_each_entry(item, &bp->rx_fs_list.list, list) { 3958 if (item->fs.location > newfs->fs.location) { 3959 list_add_tail(&newfs->list, &item->list); 3960 added = true; 3961 break; 3962 } else if (item->fs.location == fs->location) { 3963 netdev_err(netdev, "Rule not added: location %d not free!\n", 3964 fs->location); 3965 ret = -EBUSY; 3966 goto err; 3967 } 3968 } 3969 if (!added) 3970 list_add_tail(&newfs->list, &bp->rx_fs_list.list); 3971 3972 gem_prog_cmp_regs(bp, fs); 3973 bp->rx_fs_list.count++; 3974 /* enable filtering if NTUPLE on */ 3975 gem_enable_flow_filters(bp, 1); 3976 3977 spin_unlock_irqrestore(&bp->rx_fs_lock, flags); 3978 return 0; 3979 3980 err: 3981 spin_unlock_irqrestore(&bp->rx_fs_lock, flags); 3982 kfree(newfs); 3983 return ret; 3984 } 3985 3986 static int gem_del_flow_filter(struct net_device *netdev, 3987 struct ethtool_rxnfc *cmd) 3988 { 3989 struct macb *bp = netdev_priv(netdev); 3990 struct ethtool_rx_fs_item *item; 3991 struct ethtool_rx_flow_spec *fs; 3992 unsigned long flags; 3993 3994 spin_lock_irqsave(&bp->rx_fs_lock, flags); 3995 3996 list_for_each_entry(item, &bp->rx_fs_list.list, list) { 3997 if (item->fs.location == cmd->fs.location) { 3998 /* disable screener regs for the flow entry */ 3999 fs = &(item->fs); 4000 netdev_dbg(netdev, 4001 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n", 4002 fs->flow_type, (int)fs->ring_cookie, fs->location, 4003 htonl(fs->h_u.tcp_ip4_spec.ip4src), 4004 htonl(fs->h_u.tcp_ip4_spec.ip4dst), 4005 be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc), 4006 be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst)); 4007 4008 gem_writel_n(bp, SCRT2, fs->location, 0); 4009 4010 list_del(&item->list); 4011 bp->rx_fs_list.count--; 4012 spin_unlock_irqrestore(&bp->rx_fs_lock, flags); 4013 kfree(item); 4014 return 0; 4015 } 4016 } 4017 4018 spin_unlock_irqrestore(&bp->rx_fs_lock, flags); 4019 return -EINVAL; 4020 } 4021 4022 static int gem_get_flow_entry(struct net_device *netdev, 4023 struct ethtool_rxnfc *cmd) 4024 { 4025 struct macb *bp = netdev_priv(netdev); 4026 struct ethtool_rx_fs_item *item; 4027 4028 list_for_each_entry(item, &bp->rx_fs_list.list, list) { 4029 if (item->fs.location == cmd->fs.location) { 4030 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs)); 4031 return 0; 4032 } 4033 } 4034 return -EINVAL; 4035 } 4036 4037 static int gem_get_all_flow_entries(struct net_device *netdev, 4038 struct ethtool_rxnfc *cmd, u32 *rule_locs) 4039 { 4040 struct macb *bp = netdev_priv(netdev); 4041 struct ethtool_rx_fs_item *item; 4042 uint32_t cnt = 0; 4043 4044 list_for_each_entry(item, &bp->rx_fs_list.list, list) { 4045 if (cnt == cmd->rule_cnt) 4046 return -EMSGSIZE; 4047 rule_locs[cnt] = item->fs.location; 4048 cnt++; 4049 } 4050 cmd->data = bp->max_tuples; 4051 cmd->rule_cnt = cnt; 4052 4053 return 0; 4054 } 4055 4056 static u32 gem_get_rx_ring_count(struct net_device *netdev) 4057 { 4058 struct macb *bp = netdev_priv(netdev); 4059 4060 return bp->num_queues; 4061 } 4062 4063 static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd, 4064 u32 *rule_locs) 4065 { 4066 struct macb *bp = netdev_priv(netdev); 4067 int ret = 0; 4068 4069 switch (cmd->cmd) { 4070 case ETHTOOL_GRXCLSRLCNT: 4071 cmd->rule_cnt = bp->rx_fs_list.count; 4072 break; 4073 case ETHTOOL_GRXCLSRULE: 4074 ret = gem_get_flow_entry(netdev, cmd); 4075 break; 4076 case ETHTOOL_GRXCLSRLALL: 4077 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs); 4078 break; 4079 default: 4080 netdev_err(netdev, 4081 "Command parameter %d is not supported\n", cmd->cmd); 4082 ret = -EOPNOTSUPP; 4083 } 4084 4085 return ret; 4086 } 4087 4088 static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd) 4089 { 4090 struct macb *bp = netdev_priv(netdev); 4091 int ret; 4092 4093 if (!(netdev->hw_features & NETIF_F_NTUPLE)) 4094 return -EOPNOTSUPP; 4095 4096 switch (cmd->cmd) { 4097 case ETHTOOL_SRXCLSRLINS: 4098 if ((cmd->fs.location >= bp->max_tuples) 4099 || (cmd->fs.ring_cookie >= bp->num_queues)) { 4100 ret = -EINVAL; 4101 break; 4102 } 4103 ret = gem_add_flow_filter(netdev, cmd); 4104 break; 4105 case ETHTOOL_SRXCLSRLDEL: 4106 ret = gem_del_flow_filter(netdev, cmd); 4107 break; 4108 default: 4109 netdev_err(netdev, 4110 "Command parameter %d is not supported\n", cmd->cmd); 4111 ret = -EOPNOTSUPP; 4112 } 4113 4114 return ret; 4115 } 4116 4117 static const struct ethtool_ops macb_ethtool_ops = { 4118 .get_regs_len = macb_get_regs_len, 4119 .get_regs = macb_get_regs, 4120 .get_link = ethtool_op_get_link, 4121 .get_ts_info = ethtool_op_get_ts_info, 4122 .get_pause_stats = macb_get_pause_stats, 4123 .get_eth_mac_stats = macb_get_eth_mac_stats, 4124 .get_eth_phy_stats = macb_get_eth_phy_stats, 4125 .get_rmon_stats = macb_get_rmon_stats, 4126 .get_wol = macb_get_wol, 4127 .set_wol = macb_set_wol, 4128 .get_link_ksettings = macb_get_link_ksettings, 4129 .set_link_ksettings = macb_set_link_ksettings, 4130 .get_ringparam = macb_get_ringparam, 4131 .set_ringparam = macb_set_ringparam, 4132 }; 4133 4134 static int macb_get_eee(struct net_device *netdev, struct ethtool_keee *eee) 4135 { 4136 struct macb *bp = netdev_priv(netdev); 4137 4138 return phylink_ethtool_get_eee(bp->phylink, eee); 4139 } 4140 4141 static int macb_set_eee(struct net_device *netdev, struct ethtool_keee *eee) 4142 { 4143 struct macb *bp = netdev_priv(netdev); 4144 4145 return phylink_ethtool_set_eee(bp->phylink, eee); 4146 } 4147 4148 static const struct ethtool_ops gem_ethtool_ops = { 4149 .get_regs_len = macb_get_regs_len, 4150 .get_regs = macb_get_regs, 4151 .get_wol = macb_get_wol, 4152 .set_wol = macb_set_wol, 4153 .get_link = ethtool_op_get_link, 4154 .get_ts_info = macb_get_ts_info, 4155 .get_ethtool_stats = gem_get_ethtool_stats, 4156 .get_strings = gem_get_ethtool_strings, 4157 .get_sset_count = gem_get_sset_count, 4158 .get_pause_stats = gem_get_pause_stats, 4159 .get_eth_mac_stats = gem_get_eth_mac_stats, 4160 .get_eth_phy_stats = gem_get_eth_phy_stats, 4161 .get_rmon_stats = gem_get_rmon_stats, 4162 .get_link_ksettings = macb_get_link_ksettings, 4163 .set_link_ksettings = macb_set_link_ksettings, 4164 .get_ringparam = macb_get_ringparam, 4165 .set_ringparam = macb_set_ringparam, 4166 .get_rxnfc = gem_get_rxnfc, 4167 .set_rxnfc = gem_set_rxnfc, 4168 .get_rx_ring_count = gem_get_rx_ring_count, 4169 .nway_reset = phy_ethtool_nway_reset, 4170 .get_eee = macb_get_eee, 4171 .set_eee = macb_set_eee, 4172 }; 4173 4174 static int macb_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 4175 { 4176 struct macb *bp = netdev_priv(netdev); 4177 4178 if (!netif_running(netdev)) 4179 return -EINVAL; 4180 4181 return phylink_mii_ioctl(bp->phylink, rq, cmd); 4182 } 4183 4184 static int macb_hwtstamp_get(struct net_device *netdev, 4185 struct kernel_hwtstamp_config *cfg) 4186 { 4187 struct macb *bp = netdev_priv(netdev); 4188 4189 if (!netif_running(netdev)) 4190 return -EINVAL; 4191 4192 if (!bp->ptp_info) 4193 return -EOPNOTSUPP; 4194 4195 return bp->ptp_info->get_hwtst(netdev, cfg); 4196 } 4197 4198 static int macb_hwtstamp_set(struct net_device *netdev, 4199 struct kernel_hwtstamp_config *cfg, 4200 struct netlink_ext_ack *extack) 4201 { 4202 struct macb *bp = netdev_priv(netdev); 4203 4204 if (!netif_running(netdev)) 4205 return -EINVAL; 4206 4207 if (!bp->ptp_info) 4208 return -EOPNOTSUPP; 4209 4210 return bp->ptp_info->set_hwtst(netdev, cfg, extack); 4211 } 4212 4213 static inline void macb_set_txcsum_feature(struct macb *bp, 4214 netdev_features_t features) 4215 { 4216 u32 val; 4217 4218 if (!macb_is_gem(bp)) 4219 return; 4220 4221 val = gem_readl(bp, DMACFG); 4222 if (features & NETIF_F_HW_CSUM) 4223 val |= GEM_BIT(TXCOEN); 4224 else 4225 val &= ~GEM_BIT(TXCOEN); 4226 4227 gem_writel(bp, DMACFG, val); 4228 } 4229 4230 static inline void macb_set_rxcsum_feature(struct macb *bp, 4231 netdev_features_t features) 4232 { 4233 struct net_device *netdev = bp->netdev; 4234 u32 val; 4235 4236 if (!macb_is_gem(bp)) 4237 return; 4238 4239 val = gem_readl(bp, NCFGR); 4240 if ((features & NETIF_F_RXCSUM) && !(netdev->flags & IFF_PROMISC)) 4241 val |= GEM_BIT(RXCOEN); 4242 else 4243 val &= ~GEM_BIT(RXCOEN); 4244 4245 gem_writel(bp, NCFGR, val); 4246 } 4247 4248 static inline void macb_set_rxflow_feature(struct macb *bp, 4249 netdev_features_t features) 4250 { 4251 if (!macb_is_gem(bp)) 4252 return; 4253 4254 gem_enable_flow_filters(bp, !!(features & NETIF_F_NTUPLE)); 4255 } 4256 4257 static int macb_set_features(struct net_device *netdev, 4258 netdev_features_t features) 4259 { 4260 struct macb *bp = netdev_priv(netdev); 4261 netdev_features_t changed = features ^ netdev->features; 4262 4263 /* TX checksum offload */ 4264 if (changed & NETIF_F_HW_CSUM) 4265 macb_set_txcsum_feature(bp, features); 4266 4267 /* RX checksum offload */ 4268 if (changed & NETIF_F_RXCSUM) 4269 macb_set_rxcsum_feature(bp, features); 4270 4271 /* RX Flow Filters */ 4272 if (changed & NETIF_F_NTUPLE) 4273 macb_set_rxflow_feature(bp, features); 4274 4275 return 0; 4276 } 4277 4278 static void macb_restore_features(struct macb *bp) 4279 { 4280 struct net_device *netdev = bp->netdev; 4281 netdev_features_t features = netdev->features; 4282 struct ethtool_rx_fs_item *item; 4283 4284 /* TX checksum offload */ 4285 macb_set_txcsum_feature(bp, features); 4286 4287 /* RX checksum offload */ 4288 macb_set_rxcsum_feature(bp, features); 4289 4290 /* RX Flow Filters */ 4291 list_for_each_entry(item, &bp->rx_fs_list.list, list) 4292 gem_prog_cmp_regs(bp, &item->fs); 4293 4294 macb_set_rxflow_feature(bp, features); 4295 } 4296 4297 static int macb_taprio_setup_replace(struct net_device *netdev, 4298 struct tc_taprio_qopt_offload *conf) 4299 { 4300 u64 total_on_time = 0, start_time_sec = 0, start_time = conf->base_time; 4301 u32 configured_queues = 0, speed = 0, start_time_nsec; 4302 struct macb_queue_enst_config *enst_queue; 4303 struct tc_taprio_sched_entry *entry; 4304 struct macb *bp = netdev_priv(netdev); 4305 struct ethtool_link_ksettings kset; 4306 struct macb_queue *queue; 4307 u32 queue_mask; 4308 u8 queue_id; 4309 size_t i; 4310 int err; 4311 4312 if (conf->num_entries > bp->num_queues) { 4313 netdev_err(netdev, "Too many TAPRIO entries: %zu > %d queues\n", 4314 conf->num_entries, bp->num_queues); 4315 return -EINVAL; 4316 } 4317 4318 if (conf->base_time < 0) { 4319 netdev_err(netdev, "Invalid base_time: must be 0 or positive, got %lld\n", 4320 conf->base_time); 4321 return -ERANGE; 4322 } 4323 4324 /* Get the current link speed */ 4325 err = phylink_ethtool_ksettings_get(bp->phylink, &kset); 4326 if (unlikely(err)) { 4327 netdev_err(netdev, "Failed to get link settings: %d\n", err); 4328 return err; 4329 } 4330 4331 speed = kset.base.speed; 4332 if (unlikely(speed <= 0)) { 4333 netdev_err(netdev, "Invalid speed: %d\n", speed); 4334 return -EINVAL; 4335 } 4336 4337 enst_queue = kcalloc(conf->num_entries, sizeof(*enst_queue), GFP_KERNEL); 4338 if (unlikely(!enst_queue)) 4339 return -ENOMEM; 4340 4341 /* Pre-validate all entries before making any hardware changes */ 4342 for (i = 0; i < conf->num_entries; i++) { 4343 entry = &conf->entries[i]; 4344 4345 if (entry->command != TC_TAPRIO_CMD_SET_GATES) { 4346 netdev_err(netdev, "Entry %zu: unsupported command %d\n", 4347 i, entry->command); 4348 err = -EOPNOTSUPP; 4349 goto cleanup; 4350 } 4351 4352 /* Validate gate_mask: must be nonzero, single queue, and within range */ 4353 if (!is_power_of_2(entry->gate_mask)) { 4354 netdev_err(netdev, "Entry %zu: gate_mask 0x%x is not a power of 2 (only one queue per entry allowed)\n", 4355 i, entry->gate_mask); 4356 err = -EINVAL; 4357 goto cleanup; 4358 } 4359 4360 /* gate_mask must not select queues outside the valid queues */ 4361 queue_id = order_base_2(entry->gate_mask); 4362 if (queue_id >= bp->num_queues) { 4363 netdev_err(netdev, "Entry %zu: gate_mask 0x%x exceeds queue range (max_queues=%d)\n", 4364 i, entry->gate_mask, bp->num_queues); 4365 err = -EINVAL; 4366 goto cleanup; 4367 } 4368 4369 /* Check for start time limits */ 4370 start_time_sec = start_time; 4371 start_time_nsec = do_div(start_time_sec, NSEC_PER_SEC); 4372 if (start_time_sec > GENMASK(GEM_START_TIME_SEC_SIZE - 1, 0)) { 4373 netdev_err(netdev, "Entry %zu: Start time %llu s exceeds hardware limit\n", 4374 i, start_time_sec); 4375 err = -ERANGE; 4376 goto cleanup; 4377 } 4378 4379 /* Check for on time limit */ 4380 if (entry->interval > enst_max_hw_interval(speed)) { 4381 netdev_err(netdev, "Entry %zu: interval %u ns exceeds hardware limit %llu ns\n", 4382 i, entry->interval, enst_max_hw_interval(speed)); 4383 err = -ERANGE; 4384 goto cleanup; 4385 } 4386 4387 /* Check for off time limit*/ 4388 if ((conf->cycle_time - entry->interval) > enst_max_hw_interval(speed)) { 4389 netdev_err(netdev, "Entry %zu: off_time %llu ns exceeds hardware limit %llu ns\n", 4390 i, conf->cycle_time - entry->interval, 4391 enst_max_hw_interval(speed)); 4392 err = -ERANGE; 4393 goto cleanup; 4394 } 4395 4396 enst_queue[i].queue_id = queue_id; 4397 enst_queue[i].start_time_mask = 4398 (start_time_sec << GEM_START_TIME_SEC_OFFSET) | 4399 start_time_nsec; 4400 enst_queue[i].on_time_bytes = 4401 enst_ns_to_hw_units(entry->interval, speed); 4402 enst_queue[i].off_time_bytes = 4403 enst_ns_to_hw_units(conf->cycle_time - entry->interval, speed); 4404 4405 configured_queues |= entry->gate_mask; 4406 total_on_time += entry->interval; 4407 start_time += entry->interval; 4408 } 4409 4410 /* Check total interval doesn't exceed cycle time */ 4411 if (total_on_time > conf->cycle_time) { 4412 netdev_err(netdev, "Total ON %llu ns exceeds cycle time %llu ns\n", 4413 total_on_time, conf->cycle_time); 4414 err = -EINVAL; 4415 goto cleanup; 4416 } 4417 4418 netdev_dbg(netdev, "TAPRIO setup: %zu entries, base_time=%lld ns, cycle_time=%llu ns\n", 4419 conf->num_entries, conf->base_time, conf->cycle_time); 4420 4421 /* All validations passed - proceed with hardware configuration */ 4422 scoped_guard(spinlock_irqsave, &bp->lock) { 4423 /* Disable ENST queues if running before configuring */ 4424 queue_mask = BIT_U32(bp->num_queues) - 1; 4425 gem_writel(bp, ENST_CONTROL, 4426 queue_mask << GEM_ENST_DISABLE_QUEUE_OFFSET); 4427 4428 for (i = 0; i < conf->num_entries; i++) { 4429 queue = &bp->queues[enst_queue[i].queue_id]; 4430 /* Configure queue timing registers */ 4431 queue_writel(queue, ENST_START_TIME, 4432 enst_queue[i].start_time_mask); 4433 queue_writel(queue, ENST_ON_TIME, 4434 enst_queue[i].on_time_bytes); 4435 queue_writel(queue, ENST_OFF_TIME, 4436 enst_queue[i].off_time_bytes); 4437 } 4438 4439 /* Enable ENST for all configured queues in one write */ 4440 gem_writel(bp, ENST_CONTROL, configured_queues); 4441 } 4442 4443 netdev_info(netdev, "TAPRIO configuration completed successfully: %zu entries, %d queues configured\n", 4444 conf->num_entries, hweight32(configured_queues)); 4445 4446 cleanup: 4447 kfree(enst_queue); 4448 return err; 4449 } 4450 4451 static void macb_taprio_destroy(struct net_device *netdev) 4452 { 4453 struct macb *bp = netdev_priv(netdev); 4454 struct macb_queue *queue; 4455 u32 queue_mask; 4456 unsigned int q; 4457 4458 netdev_reset_tc(netdev); 4459 queue_mask = BIT_U32(bp->num_queues) - 1; 4460 4461 scoped_guard(spinlock_irqsave, &bp->lock) { 4462 /* Single disable command for all queues */ 4463 gem_writel(bp, ENST_CONTROL, 4464 queue_mask << GEM_ENST_DISABLE_QUEUE_OFFSET); 4465 4466 /* Clear all queue ENST registers in batch */ 4467 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 4468 queue_writel(queue, ENST_START_TIME, 0); 4469 queue_writel(queue, ENST_ON_TIME, 0); 4470 queue_writel(queue, ENST_OFF_TIME, 0); 4471 } 4472 } 4473 netdev_info(netdev, "TAPRIO destroy: All gates disabled\n"); 4474 } 4475 4476 static int macb_setup_taprio(struct net_device *netdev, 4477 struct tc_taprio_qopt_offload *taprio) 4478 { 4479 struct macb *bp = netdev_priv(netdev); 4480 int err = 0; 4481 4482 if (unlikely(!(netdev->hw_features & NETIF_F_HW_TC))) 4483 return -EOPNOTSUPP; 4484 4485 /* Check if Device is in runtime suspend */ 4486 if (unlikely(pm_runtime_suspended(&bp->pdev->dev))) { 4487 netdev_err(netdev, "Device is in runtime suspend\n"); 4488 return -EOPNOTSUPP; 4489 } 4490 4491 switch (taprio->cmd) { 4492 case TAPRIO_CMD_REPLACE: 4493 err = macb_taprio_setup_replace(netdev, taprio); 4494 break; 4495 case TAPRIO_CMD_DESTROY: 4496 macb_taprio_destroy(netdev); 4497 break; 4498 default: 4499 err = -EOPNOTSUPP; 4500 } 4501 4502 return err; 4503 } 4504 4505 static int macb_setup_tc(struct net_device *netdev, enum tc_setup_type type, 4506 void *type_data) 4507 { 4508 if (!netdev || !type_data) 4509 return -EINVAL; 4510 4511 switch (type) { 4512 case TC_SETUP_QDISC_TAPRIO: 4513 return macb_setup_taprio(netdev, type_data); 4514 default: 4515 return -EOPNOTSUPP; 4516 } 4517 } 4518 4519 static void macb_tx_timeout(struct net_device *netdev, unsigned int q) 4520 { 4521 struct macb *bp = netdev_priv(netdev); 4522 4523 macb_tx_restart(&bp->queues[q]); 4524 } 4525 4526 static const struct net_device_ops macb_netdev_ops = { 4527 .ndo_open = macb_open, 4528 .ndo_stop = macb_close, 4529 .ndo_start_xmit = macb_start_xmit, 4530 .ndo_set_rx_mode = macb_set_rx_mode, 4531 .ndo_get_stats64 = macb_get_stats, 4532 .ndo_eth_ioctl = macb_ioctl, 4533 .ndo_validate_addr = eth_validate_addr, 4534 .ndo_change_mtu = macb_change_mtu, 4535 .ndo_set_mac_address = macb_set_mac_addr, 4536 #ifdef CONFIG_NET_POLL_CONTROLLER 4537 .ndo_poll_controller = macb_poll_controller, 4538 #endif 4539 .ndo_set_features = macb_set_features, 4540 .ndo_features_check = macb_features_check, 4541 .ndo_hwtstamp_set = macb_hwtstamp_set, 4542 .ndo_hwtstamp_get = macb_hwtstamp_get, 4543 .ndo_setup_tc = macb_setup_tc, 4544 .ndo_tx_timeout = macb_tx_timeout, 4545 }; 4546 4547 /* Configure peripheral capabilities according to device tree 4548 * and integration options used 4549 */ 4550 static void macb_configure_caps(struct macb *bp, 4551 const struct macb_config *dt_conf) 4552 { 4553 u32 dcfg; 4554 4555 bp->caps = dt_conf->caps; 4556 4557 if (!dt_conf->usrio) 4558 bp->caps |= MACB_CAPS_USRIO_DISABLED; 4559 4560 if (hw_is_gem(bp->regs, bp->native_io)) { 4561 bp->caps |= MACB_CAPS_MACB_IS_GEM; 4562 4563 dcfg = gem_readl(bp, DCFG1); 4564 if (GEM_BFEXT(IRQCOR, dcfg) == 0) 4565 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE; 4566 if (GEM_BFEXT(NO_PCS, dcfg) == 0) 4567 bp->caps |= MACB_CAPS_PCS; 4568 if (!(dcfg & GEM_BIT(USERIO))) 4569 bp->caps |= MACB_CAPS_USRIO_DISABLED; 4570 dcfg = gem_readl(bp, DCFG12); 4571 if (GEM_BFEXT(HIGH_SPEED, dcfg) == 1) 4572 bp->caps |= MACB_CAPS_HIGH_SPEED; 4573 dcfg = gem_readl(bp, DCFG2); 4574 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0) 4575 bp->caps |= MACB_CAPS_FIFO_MODE; 4576 if (GEM_BFEXT(PBUF_RSC, gem_readl(bp, DCFG6))) 4577 bp->caps |= MACB_CAPS_RSC; 4578 if (gem_has_ptp(bp)) { 4579 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5))) 4580 dev_err(&bp->pdev->dev, 4581 "GEM doesn't support hardware ptp.\n"); 4582 else { 4583 #ifdef CONFIG_MACB_USE_HWSTAMP 4584 bp->caps |= MACB_CAPS_DMA_PTP; 4585 bp->ptp_info = &gem_ptp_info; 4586 #endif 4587 } 4588 } 4589 } 4590 4591 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps); 4592 } 4593 4594 static int macb_probe_queues(struct device *dev, void __iomem *mem, bool native_io) 4595 { 4596 /* BIT(0) is never set but queue 0 always exists. */ 4597 unsigned int queue_mask = 0x1; 4598 4599 /* Use hw_is_gem() as MACB_CAPS_MACB_IS_GEM is not yet positioned. */ 4600 if (hw_is_gem(mem, native_io)) { 4601 if (native_io) 4602 queue_mask |= __raw_readl(mem + GEM_DCFG6) & 0xFF; 4603 else 4604 queue_mask |= readl_relaxed(mem + GEM_DCFG6) & 0xFF; 4605 4606 if (fls(queue_mask) != ffz(queue_mask)) { 4607 dev_err(dev, "queue mask %#x has a hole\n", queue_mask); 4608 return -EINVAL; 4609 } 4610 } 4611 4612 return hweight32(queue_mask); 4613 } 4614 4615 static void macb_clks_disable(struct clk *pclk, struct clk *hclk, struct clk *tx_clk, 4616 struct clk *rx_clk, struct clk *tsu_clk) 4617 { 4618 struct clk_bulk_data clks[] = { 4619 { .clk = tsu_clk, }, 4620 { .clk = rx_clk, }, 4621 { .clk = pclk, }, 4622 { .clk = hclk, }, 4623 { .clk = tx_clk }, 4624 }; 4625 4626 clk_bulk_disable_unprepare(ARRAY_SIZE(clks), clks); 4627 } 4628 4629 static int macb_clk_init_dflt(struct platform_device *pdev, struct clk **pclk, 4630 struct clk **hclk, struct clk **tx_clk, 4631 struct clk **rx_clk, struct clk **tsu_clk) 4632 { 4633 struct macb_platform_data *pdata; 4634 int err; 4635 4636 pdata = dev_get_platdata(&pdev->dev); 4637 if (pdata) { 4638 *pclk = pdata->pclk; 4639 *hclk = pdata->hclk; 4640 } else { 4641 *pclk = devm_clk_get(&pdev->dev, "pclk"); 4642 *hclk = devm_clk_get(&pdev->dev, "hclk"); 4643 } 4644 4645 if (IS_ERR_OR_NULL(*pclk)) 4646 return dev_err_probe(&pdev->dev, 4647 IS_ERR(*pclk) ? PTR_ERR(*pclk) : -ENODEV, 4648 "failed to get pclk\n"); 4649 4650 if (IS_ERR_OR_NULL(*hclk)) 4651 return dev_err_probe(&pdev->dev, 4652 IS_ERR(*hclk) ? PTR_ERR(*hclk) : -ENODEV, 4653 "failed to get hclk\n"); 4654 4655 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk"); 4656 if (IS_ERR(*tx_clk)) 4657 return PTR_ERR(*tx_clk); 4658 4659 *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk"); 4660 if (IS_ERR(*rx_clk)) 4661 return PTR_ERR(*rx_clk); 4662 4663 *tsu_clk = devm_clk_get_optional(&pdev->dev, "tsu_clk"); 4664 if (IS_ERR(*tsu_clk)) 4665 return PTR_ERR(*tsu_clk); 4666 4667 err = clk_prepare_enable(*pclk); 4668 if (err) { 4669 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err); 4670 return err; 4671 } 4672 4673 err = clk_prepare_enable(*hclk); 4674 if (err) { 4675 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err); 4676 goto err_disable_pclk; 4677 } 4678 4679 err = clk_prepare_enable(*tx_clk); 4680 if (err) { 4681 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err); 4682 goto err_disable_hclk; 4683 } 4684 4685 err = clk_prepare_enable(*rx_clk); 4686 if (err) { 4687 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err); 4688 goto err_disable_txclk; 4689 } 4690 4691 err = clk_prepare_enable(*tsu_clk); 4692 if (err) { 4693 dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err); 4694 goto err_disable_rxclk; 4695 } 4696 4697 return 0; 4698 4699 err_disable_rxclk: 4700 clk_disable_unprepare(*rx_clk); 4701 4702 err_disable_txclk: 4703 clk_disable_unprepare(*tx_clk); 4704 4705 err_disable_hclk: 4706 clk_disable_unprepare(*hclk); 4707 4708 err_disable_pclk: 4709 clk_disable_unprepare(*pclk); 4710 4711 return err; 4712 } 4713 4714 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk, 4715 struct clk **hclk, struct clk **tx_clk, 4716 struct clk **rx_clk, struct clk **tsu_clk, 4717 const struct macb_config *config) 4718 { 4719 if (config->clk_init) 4720 return config->clk_init(pdev, pclk, hclk, tx_clk, rx_clk, 4721 tsu_clk); 4722 else 4723 return macb_clk_init_dflt(pdev, pclk, hclk, tx_clk, rx_clk, 4724 tsu_clk); 4725 } 4726 4727 static int macb_init_dflt(struct platform_device *pdev) 4728 { 4729 struct net_device *netdev = platform_get_drvdata(pdev); 4730 unsigned int hw_q, q; 4731 struct macb *bp = netdev_priv(netdev); 4732 struct macb_queue *queue; 4733 int err; 4734 u32 val, reg; 4735 4736 bp->tx_ring_size = DEFAULT_TX_RING_SIZE; 4737 bp->rx_ring_size = DEFAULT_RX_RING_SIZE; 4738 4739 /* set the queue register mapping once for all: queue0 has a special 4740 * register mapping but we don't want to test the queue index then 4741 * compute the corresponding register offset at run time. 4742 */ 4743 for (hw_q = 0, q = 0; hw_q < bp->num_queues; ++hw_q) { 4744 queue = &bp->queues[q]; 4745 queue->bp = bp; 4746 spin_lock_init(&queue->tx_ptr_lock); 4747 netif_napi_add(netdev, &queue->napi_rx, macb_rx_poll); 4748 netif_napi_add_tx(netdev, &queue->napi_tx, macb_tx_poll); 4749 if (hw_q) { 4750 queue->ISR = GEM_ISR(hw_q - 1); 4751 queue->IER = GEM_IER(hw_q - 1); 4752 queue->IDR = GEM_IDR(hw_q - 1); 4753 queue->IMR = GEM_IMR(hw_q - 1); 4754 queue->TBQP = GEM_TBQP(hw_q - 1); 4755 queue->RBQP = GEM_RBQP(hw_q - 1); 4756 queue->RBQS = GEM_RBQS(hw_q - 1); 4757 } else { 4758 /* queue0 uses legacy registers */ 4759 queue->ISR = MACB_ISR; 4760 queue->IER = MACB_IER; 4761 queue->IDR = MACB_IDR; 4762 queue->IMR = MACB_IMR; 4763 queue->TBQP = MACB_TBQP; 4764 queue->RBQP = MACB_RBQP; 4765 } 4766 4767 queue->ENST_START_TIME = GEM_ENST_START_TIME(hw_q); 4768 queue->ENST_ON_TIME = GEM_ENST_ON_TIME(hw_q); 4769 queue->ENST_OFF_TIME = GEM_ENST_OFF_TIME(hw_q); 4770 4771 /* get irq: here we use the linux queue index, not the hardware 4772 * queue index. the queue irq definitions in the device tree 4773 * must remove the optional gaps that could exist in the 4774 * hardware queue mask. 4775 */ 4776 queue->irq = platform_get_irq(pdev, q); 4777 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt, 4778 IRQF_SHARED, netdev->name, queue); 4779 if (err) { 4780 dev_err(&pdev->dev, 4781 "Unable to request IRQ %d (error %d)\n", 4782 queue->irq, err); 4783 return err; 4784 } 4785 4786 INIT_WORK(&queue->tx_error_task, macb_tx_error_task); 4787 q++; 4788 } 4789 4790 netdev->netdev_ops = &macb_netdev_ops; 4791 4792 /* setup appropriated routines according to adapter type */ 4793 if (macb_is_gem(bp)) { 4794 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers; 4795 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers; 4796 bp->macbgem_ops.mog_init_rings = gem_init_rings; 4797 bp->macbgem_ops.mog_rx = gem_rx; 4798 netdev->ethtool_ops = &gem_ethtool_ops; 4799 } else { 4800 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers; 4801 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers; 4802 bp->macbgem_ops.mog_init_rings = macb_init_rings; 4803 bp->macbgem_ops.mog_rx = macb_rx; 4804 netdev->ethtool_ops = &macb_ethtool_ops; 4805 } 4806 4807 netdev_sw_irq_coalesce_default_on(netdev); 4808 4809 netdev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 4810 4811 /* Set features */ 4812 netdev->hw_features = NETIF_F_SG; 4813 4814 /* Check LSO capability; runtime detection can be overridden by a cap 4815 * flag if the hardware is known to be buggy 4816 */ 4817 if (!(bp->caps & MACB_CAPS_NO_LSO) && 4818 GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6))) 4819 netdev->hw_features |= MACB_NETIF_LSO; 4820 4821 /* Checksum offload is only available on gem with packet buffer */ 4822 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE)) 4823 netdev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM; 4824 if (bp->caps & MACB_CAPS_SG_DISABLED) 4825 netdev->hw_features &= ~NETIF_F_SG; 4826 /* Enable HW_TC if hardware supports QBV */ 4827 if (bp->caps & MACB_CAPS_QBV) 4828 netdev->hw_features |= NETIF_F_HW_TC; 4829 4830 netdev->features = netdev->hw_features; 4831 4832 /* Check RX Flow Filters support. 4833 * Max Rx flows set by availability of screeners & compare regs: 4834 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs 4835 */ 4836 reg = gem_readl(bp, DCFG8); 4837 bp->max_tuples = umin((GEM_BFEXT(SCR2CMP, reg) / 3), 4838 GEM_BFEXT(T2SCR, reg)); 4839 INIT_LIST_HEAD(&bp->rx_fs_list.list); 4840 if (bp->max_tuples > 0) { 4841 /* also needs one ethtype match to check IPv4 */ 4842 if (GEM_BFEXT(SCR2ETH, reg) > 0) { 4843 /* program this reg now */ 4844 reg = 0; 4845 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg); 4846 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg); 4847 /* Filtering is supported in hw but don't enable it in kernel now */ 4848 netdev->hw_features |= NETIF_F_NTUPLE; 4849 /* init Rx flow definitions */ 4850 bp->rx_fs_list.count = 0; 4851 spin_lock_init(&bp->rx_fs_lock); 4852 } else 4853 bp->max_tuples = 0; 4854 } 4855 4856 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) { 4857 val = 0; 4858 if (bp->caps & MACB_CAPS_USRIO_HAS_MII) { 4859 if (phy_interface_mode_is_rgmii(bp->phy_interface)) 4860 val = bp->usrio->rgmii; 4861 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII && 4862 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII)) 4863 val = bp->usrio->rmii; 4864 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII)) 4865 val = bp->usrio->mii; 4866 } 4867 4868 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN) 4869 val |= bp->usrio->clken; 4870 4871 if (bp->caps & MACB_CAPS_USRIO_HAS_REFCLK_SOURCE) { 4872 const char *prop; 4873 bool refclk_ext; 4874 int ret; 4875 4876 /* Default to whatever was set in the match data for 4877 * this device. There's two properties for refclk 4878 * control, but the boolean one is deprecated so is 4879 * a lower priority to check, no device should have 4880 * both. 4881 */ 4882 refclk_ext = bp->usrio->refclk_default_external; 4883 4884 ret = of_property_read_string(pdev->dev.of_node, 4885 "cdns,refclk-source", &prop); 4886 if (!ret) { 4887 if (!strcmp(prop, "external")) 4888 refclk_ext = true; 4889 else 4890 refclk_ext = false; 4891 } else { 4892 ret = of_property_read_bool(pdev->dev.of_node, 4893 "cdns,refclk-ext"); 4894 if (ret) 4895 refclk_ext = true; 4896 } 4897 4898 if (refclk_ext) 4899 val |= bp->usrio->refclk; 4900 } 4901 4902 if (bp->caps & MACB_CAPS_USRIO_HAS_TSUCLK_SOURCE) 4903 val |= bp->usrio->tsu_source; 4904 4905 macb_or_gem_writel(bp, USRIO, val); 4906 } 4907 4908 /* Set MII management clock divider */ 4909 val = macb_mdc_clk_div(bp); 4910 val |= macb_dbw(bp); 4911 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) 4912 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL); 4913 macb_writel(bp, NCFGR, val); 4914 4915 return 0; 4916 } 4917 4918 static int macb_init(struct platform_device *pdev, 4919 const struct macb_config *config) 4920 { 4921 if (config->init) 4922 return config->init(pdev); 4923 else 4924 return macb_init_dflt(pdev); 4925 } 4926 4927 static const struct macb_usrio_config at91_default_usrio = { 4928 .mii = MACB_BIT(MII), 4929 .rmii = MACB_BIT(RMII), 4930 .rgmii = GEM_BIT(RGMII), 4931 .clken = MACB_BIT(CLKEN), 4932 }; 4933 4934 /* 1518 rounded up */ 4935 #define AT91ETHER_MAX_RBUFF_SZ 0x600 4936 /* max number of receive buffers */ 4937 #define AT91ETHER_MAX_RX_DESCR 9 4938 4939 static struct sifive_fu540_macb_mgmt *mgmt; 4940 4941 static int at91ether_alloc_coherent(struct macb *bp) 4942 { 4943 struct macb_queue *queue = &bp->queues[0]; 4944 4945 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, 4946 (AT91ETHER_MAX_RX_DESCR * 4947 macb_dma_desc_get_size(bp)), 4948 &queue->rx_ring_dma, GFP_KERNEL); 4949 if (!queue->rx_ring) 4950 return -ENOMEM; 4951 4952 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, 4953 AT91ETHER_MAX_RX_DESCR * 4954 AT91ETHER_MAX_RBUFF_SZ, 4955 &queue->rx_buffers_dma, 4956 GFP_KERNEL); 4957 if (!queue->rx_buffers) { 4958 dma_free_coherent(&bp->pdev->dev, 4959 AT91ETHER_MAX_RX_DESCR * 4960 macb_dma_desc_get_size(bp), 4961 queue->rx_ring, queue->rx_ring_dma); 4962 queue->rx_ring = NULL; 4963 return -ENOMEM; 4964 } 4965 4966 return 0; 4967 } 4968 4969 static void at91ether_free_coherent(struct macb *bp) 4970 { 4971 struct macb_queue *queue = &bp->queues[0]; 4972 4973 if (queue->rx_ring) { 4974 dma_free_coherent(&bp->pdev->dev, 4975 AT91ETHER_MAX_RX_DESCR * 4976 macb_dma_desc_get_size(bp), 4977 queue->rx_ring, queue->rx_ring_dma); 4978 queue->rx_ring = NULL; 4979 } 4980 4981 if (queue->rx_buffers) { 4982 dma_free_coherent(&bp->pdev->dev, 4983 AT91ETHER_MAX_RX_DESCR * 4984 AT91ETHER_MAX_RBUFF_SZ, 4985 queue->rx_buffers, queue->rx_buffers_dma); 4986 queue->rx_buffers = NULL; 4987 } 4988 } 4989 4990 /* Initialize and start the Receiver and Transmit subsystems */ 4991 static int at91ether_start(struct macb *bp) 4992 { 4993 struct macb_queue *queue = &bp->queues[0]; 4994 struct macb_dma_desc *desc; 4995 dma_addr_t addr; 4996 u32 ctl; 4997 int i, ret; 4998 4999 ret = at91ether_alloc_coherent(bp); 5000 if (ret) 5001 return ret; 5002 5003 addr = queue->rx_buffers_dma; 5004 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) { 5005 desc = macb_rx_desc(queue, i); 5006 macb_set_addr(bp, desc, addr); 5007 desc->ctrl = 0; 5008 addr += AT91ETHER_MAX_RBUFF_SZ; 5009 } 5010 5011 /* Set the Wrap bit on the last descriptor */ 5012 desc->addr |= MACB_BIT(RX_WRAP); 5013 5014 /* Reset buffer index */ 5015 queue->rx_tail = 0; 5016 5017 /* Program address of descriptor list in Rx Buffer Queue register */ 5018 macb_writel(bp, RBQP, queue->rx_ring_dma); 5019 5020 /* Enable Receive and Transmit */ 5021 ctl = macb_readl(bp, NCR); 5022 macb_writel(bp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE)); 5023 5024 /* Enable MAC interrupts */ 5025 macb_writel(bp, IER, MACB_BIT(RCOMP) | 5026 MACB_BIT(RXUBR) | 5027 MACB_BIT(ISR_TUND) | 5028 MACB_BIT(ISR_RLE) | 5029 MACB_BIT(TCOMP) | 5030 MACB_BIT(ISR_ROVR) | 5031 MACB_BIT(HRESP)); 5032 5033 return 0; 5034 } 5035 5036 static void at91ether_stop(struct macb *bp) 5037 { 5038 u32 ctl; 5039 5040 /* Disable MAC interrupts */ 5041 macb_writel(bp, IDR, MACB_BIT(RCOMP) | 5042 MACB_BIT(RXUBR) | 5043 MACB_BIT(ISR_TUND) | 5044 MACB_BIT(ISR_RLE) | 5045 MACB_BIT(TCOMP) | 5046 MACB_BIT(ISR_ROVR) | 5047 MACB_BIT(HRESP)); 5048 5049 /* Disable Receiver and Transmitter */ 5050 ctl = macb_readl(bp, NCR); 5051 macb_writel(bp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE))); 5052 5053 /* Free resources. */ 5054 at91ether_free_coherent(bp); 5055 } 5056 5057 /* Open the ethernet interface */ 5058 static int at91ether_open(struct net_device *netdev) 5059 { 5060 struct macb *bp = netdev_priv(netdev); 5061 u32 ctl; 5062 int ret; 5063 5064 ret = pm_runtime_resume_and_get(&bp->pdev->dev); 5065 if (ret < 0) 5066 return ret; 5067 5068 /* Clear internal statistics */ 5069 ctl = macb_readl(bp, NCR); 5070 macb_writel(bp, NCR, ctl | MACB_BIT(CLRSTAT)); 5071 5072 macb_set_hwaddr(bp); 5073 5074 ret = at91ether_start(bp); 5075 if (ret) 5076 goto pm_exit; 5077 5078 ret = macb_phylink_connect(bp); 5079 if (ret) 5080 goto stop; 5081 5082 netif_start_queue(netdev); 5083 5084 return 0; 5085 5086 stop: 5087 at91ether_stop(bp); 5088 pm_exit: 5089 pm_runtime_put_sync(&bp->pdev->dev); 5090 return ret; 5091 } 5092 5093 /* Close the interface */ 5094 static int at91ether_close(struct net_device *netdev) 5095 { 5096 struct macb *bp = netdev_priv(netdev); 5097 5098 netif_stop_queue(netdev); 5099 5100 phylink_stop(bp->phylink); 5101 phylink_disconnect_phy(bp->phylink); 5102 5103 at91ether_stop(bp); 5104 5105 pm_runtime_put(&bp->pdev->dev); 5106 5107 return 0; 5108 } 5109 5110 /* Transmit packet */ 5111 static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb, 5112 struct net_device *netdev) 5113 { 5114 struct macb *bp = netdev_priv(netdev); 5115 struct device *dev = &bp->pdev->dev; 5116 5117 if (macb_readl(bp, TSR) & MACB_BIT(RM9200_BNQ)) { 5118 int desc = 0; 5119 5120 netif_stop_queue(netdev); 5121 5122 /* Store packet information (to free when Tx completed) */ 5123 bp->rm9200_txq[desc].skb = skb; 5124 bp->rm9200_txq[desc].size = skb->len; 5125 bp->rm9200_txq[desc].mapping = dma_map_single(dev, skb->data, 5126 skb->len, 5127 DMA_TO_DEVICE); 5128 if (dma_mapping_error(dev, bp->rm9200_txq[desc].mapping)) { 5129 dev_kfree_skb_any(skb); 5130 netdev->stats.tx_dropped++; 5131 netdev_err(netdev, "%s: DMA mapping error\n", __func__); 5132 return NETDEV_TX_OK; 5133 } 5134 5135 /* Set address of the data in the Transmit Address register */ 5136 macb_writel(bp, TAR, bp->rm9200_txq[desc].mapping); 5137 /* Set length of the packet in the Transmit Control register */ 5138 macb_writel(bp, TCR, skb->len); 5139 5140 } else { 5141 netdev_err(netdev, "%s called, but device is busy!\n", 5142 __func__); 5143 return NETDEV_TX_BUSY; 5144 } 5145 5146 return NETDEV_TX_OK; 5147 } 5148 5149 /* Extract received frame from buffer descriptors and sent to upper layers. 5150 * (Called from interrupt context) 5151 */ 5152 static void at91ether_rx(struct net_device *netdev) 5153 { 5154 struct macb *bp = netdev_priv(netdev); 5155 struct macb_queue *queue = &bp->queues[0]; 5156 struct macb_dma_desc *desc; 5157 unsigned char *p_recv; 5158 struct sk_buff *skb; 5159 unsigned int pktlen; 5160 5161 desc = macb_rx_desc(queue, queue->rx_tail); 5162 while (desc->addr & MACB_BIT(RX_USED)) { 5163 p_recv = queue->rx_buffers + 5164 queue->rx_tail * AT91ETHER_MAX_RBUFF_SZ; 5165 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl); 5166 skb = netdev_alloc_skb(netdev, pktlen + 2); 5167 if (skb) { 5168 skb_reserve(skb, 2); 5169 skb_put_data(skb, p_recv, pktlen); 5170 5171 skb->protocol = eth_type_trans(skb, netdev); 5172 netdev->stats.rx_packets++; 5173 netdev->stats.rx_bytes += pktlen; 5174 netif_rx(skb); 5175 } else { 5176 netdev->stats.rx_dropped++; 5177 } 5178 5179 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH)) 5180 netdev->stats.multicast++; 5181 5182 /* reset ownership bit */ 5183 desc->addr &= ~MACB_BIT(RX_USED); 5184 5185 /* wrap after last buffer */ 5186 if (queue->rx_tail == AT91ETHER_MAX_RX_DESCR - 1) 5187 queue->rx_tail = 0; 5188 else 5189 queue->rx_tail++; 5190 5191 desc = macb_rx_desc(queue, queue->rx_tail); 5192 } 5193 } 5194 5195 /* MAC interrupt handler */ 5196 static irqreturn_t at91ether_interrupt(int irq, void *dev_id) 5197 { 5198 struct net_device *netdev = dev_id; 5199 struct macb *bp = netdev_priv(netdev); 5200 u32 intstatus, ctl; 5201 unsigned int desc; 5202 5203 /* MAC Interrupt Status register indicates what interrupts are pending. 5204 * It is automatically cleared once read. 5205 */ 5206 intstatus = macb_readl(bp, ISR); 5207 5208 /* Receive complete */ 5209 if (intstatus & MACB_BIT(RCOMP)) 5210 at91ether_rx(netdev); 5211 5212 /* Transmit complete */ 5213 if (intstatus & MACB_BIT(TCOMP)) { 5214 /* The TCOM bit is set even if the transmission failed */ 5215 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE))) 5216 netdev->stats.tx_errors++; 5217 5218 desc = 0; 5219 if (bp->rm9200_txq[desc].skb) { 5220 dev_consume_skb_irq(bp->rm9200_txq[desc].skb); 5221 bp->rm9200_txq[desc].skb = NULL; 5222 dma_unmap_single(&bp->pdev->dev, 5223 bp->rm9200_txq[desc].mapping, 5224 bp->rm9200_txq[desc].size, 5225 DMA_TO_DEVICE); 5226 netdev->stats.tx_packets++; 5227 netdev->stats.tx_bytes += bp->rm9200_txq[desc].size; 5228 } 5229 netif_wake_queue(netdev); 5230 } 5231 5232 /* Work-around for EMAC Errata section 41.3.1 */ 5233 if (intstatus & MACB_BIT(RXUBR)) { 5234 ctl = macb_readl(bp, NCR); 5235 macb_writel(bp, NCR, ctl & ~MACB_BIT(RE)); 5236 wmb(); 5237 macb_writel(bp, NCR, ctl | MACB_BIT(RE)); 5238 } 5239 5240 if (intstatus & MACB_BIT(ISR_ROVR)) 5241 netdev_err(netdev, "ROVR error\n"); 5242 5243 return IRQ_HANDLED; 5244 } 5245 5246 #ifdef CONFIG_NET_POLL_CONTROLLER 5247 static void at91ether_poll_controller(struct net_device *netdev) 5248 { 5249 unsigned long flags; 5250 5251 local_irq_save(flags); 5252 at91ether_interrupt(netdev->irq, netdev); 5253 local_irq_restore(flags); 5254 } 5255 #endif 5256 5257 static const struct net_device_ops at91ether_netdev_ops = { 5258 .ndo_open = at91ether_open, 5259 .ndo_stop = at91ether_close, 5260 .ndo_start_xmit = at91ether_start_xmit, 5261 .ndo_get_stats64 = macb_get_stats, 5262 .ndo_set_rx_mode = macb_set_rx_mode, 5263 .ndo_set_mac_address = eth_mac_addr, 5264 .ndo_eth_ioctl = macb_ioctl, 5265 .ndo_validate_addr = eth_validate_addr, 5266 #ifdef CONFIG_NET_POLL_CONTROLLER 5267 .ndo_poll_controller = at91ether_poll_controller, 5268 #endif 5269 .ndo_hwtstamp_set = macb_hwtstamp_set, 5270 .ndo_hwtstamp_get = macb_hwtstamp_get, 5271 }; 5272 5273 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk, 5274 struct clk **hclk, struct clk **tx_clk, 5275 struct clk **rx_clk, struct clk **tsu_clk) 5276 { 5277 int err; 5278 5279 *hclk = NULL; 5280 *tx_clk = NULL; 5281 *rx_clk = NULL; 5282 *tsu_clk = NULL; 5283 5284 *pclk = devm_clk_get(&pdev->dev, "ether_clk"); 5285 if (IS_ERR(*pclk)) 5286 return PTR_ERR(*pclk); 5287 5288 err = clk_prepare_enable(*pclk); 5289 if (err) { 5290 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err); 5291 return err; 5292 } 5293 5294 return 0; 5295 } 5296 5297 static int at91ether_init(struct platform_device *pdev) 5298 { 5299 struct net_device *netdev = platform_get_drvdata(pdev); 5300 struct macb *bp = netdev_priv(netdev); 5301 int err; 5302 5303 bp->queues[0].bp = bp; 5304 5305 netdev->netdev_ops = &at91ether_netdev_ops; 5306 netdev->ethtool_ops = &macb_ethtool_ops; 5307 5308 err = devm_request_irq(&pdev->dev, netdev->irq, at91ether_interrupt, 5309 0, netdev->name, netdev); 5310 if (err) 5311 return err; 5312 5313 macb_writel(bp, NCR, 0); 5314 5315 macb_writel(bp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG)); 5316 5317 return 0; 5318 } 5319 5320 static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw, 5321 unsigned long parent_rate) 5322 { 5323 return mgmt->rate; 5324 } 5325 5326 static int fu540_macb_tx_determine_rate(struct clk_hw *hw, 5327 struct clk_rate_request *req) 5328 { 5329 if (WARN_ON(req->rate < 2500000)) 5330 req->rate = 2500000; 5331 else if (req->rate == 2500000) 5332 req->rate = 2500000; 5333 else if (WARN_ON(req->rate < 13750000)) 5334 req->rate = 2500000; 5335 else if (WARN_ON(req->rate < 25000000)) 5336 req->rate = 25000000; 5337 else if (req->rate == 25000000) 5338 req->rate = 25000000; 5339 else if (WARN_ON(req->rate < 75000000)) 5340 req->rate = 25000000; 5341 else if (WARN_ON(req->rate < 125000000)) 5342 req->rate = 125000000; 5343 else if (req->rate == 125000000) 5344 req->rate = 125000000; 5345 else if (WARN_ON(req->rate > 125000000)) 5346 req->rate = 125000000; 5347 else 5348 req->rate = 125000000; 5349 5350 return 0; 5351 } 5352 5353 static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate, 5354 unsigned long parent_rate) 5355 { 5356 struct clk_rate_request req; 5357 int ret; 5358 5359 clk_hw_init_rate_request(hw, &req, rate); 5360 ret = fu540_macb_tx_determine_rate(hw, &req); 5361 if (ret != 0) 5362 return ret; 5363 5364 if (req.rate != 125000000) 5365 iowrite32(1, mgmt->reg); 5366 else 5367 iowrite32(0, mgmt->reg); 5368 mgmt->rate = rate; 5369 5370 return 0; 5371 } 5372 5373 static const struct clk_ops fu540_c000_ops = { 5374 .recalc_rate = fu540_macb_tx_recalc_rate, 5375 .determine_rate = fu540_macb_tx_determine_rate, 5376 .set_rate = fu540_macb_tx_set_rate, 5377 }; 5378 5379 static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk, 5380 struct clk **hclk, struct clk **tx_clk, 5381 struct clk **rx_clk, struct clk **tsu_clk) 5382 { 5383 struct clk_init_data init; 5384 int err = 0; 5385 5386 err = macb_clk_init_dflt(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk); 5387 if (err) 5388 return err; 5389 5390 mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL); 5391 if (!mgmt) { 5392 err = -ENOMEM; 5393 goto err_disable_clks; 5394 } 5395 5396 init.name = "sifive-gemgxl-mgmt"; 5397 init.ops = &fu540_c000_ops; 5398 init.flags = 0; 5399 init.num_parents = 0; 5400 5401 mgmt->rate = 0; 5402 mgmt->hw.init = &init; 5403 5404 *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw); 5405 if (IS_ERR(*tx_clk)) { 5406 err = PTR_ERR(*tx_clk); 5407 goto err_disable_clks; 5408 } 5409 5410 err = clk_prepare_enable(*tx_clk); 5411 if (err) { 5412 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err); 5413 *tx_clk = NULL; 5414 goto err_disable_clks; 5415 } else { 5416 dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name); 5417 } 5418 5419 return 0; 5420 5421 err_disable_clks: 5422 macb_clks_disable(*pclk, *hclk, *tx_clk, *rx_clk, *tsu_clk); 5423 5424 return err; 5425 } 5426 5427 static int fu540_c000_init(struct platform_device *pdev) 5428 { 5429 mgmt->reg = devm_platform_ioremap_resource(pdev, 1); 5430 if (IS_ERR(mgmt->reg)) 5431 return PTR_ERR(mgmt->reg); 5432 5433 return macb_init_dflt(pdev); 5434 } 5435 5436 static int init_reset_optional(struct platform_device *pdev) 5437 { 5438 struct net_device *netdev = platform_get_drvdata(pdev); 5439 struct macb *bp = netdev_priv(netdev); 5440 int ret; 5441 5442 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) { 5443 /* Ensure PHY device used in SGMII mode is ready */ 5444 bp->phy = devm_phy_optional_get(&pdev->dev, NULL); 5445 5446 if (IS_ERR(bp->phy)) 5447 return dev_err_probe(&pdev->dev, PTR_ERR(bp->phy), 5448 "failed to get SGMII PHY\n"); 5449 5450 ret = phy_init(bp->phy); 5451 if (ret) 5452 return dev_err_probe(&pdev->dev, ret, 5453 "failed to init SGMII PHY\n"); 5454 5455 ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_SET_GEM_CONFIG); 5456 if (!ret) { 5457 u32 pm_info[2]; 5458 5459 ret = of_property_read_u32_array(pdev->dev.of_node, "power-domains", 5460 pm_info, ARRAY_SIZE(pm_info)); 5461 if (ret) { 5462 dev_err(&pdev->dev, "Failed to read power management information\n"); 5463 goto err_out_phy_exit; 5464 } 5465 ret = zynqmp_pm_set_gem_config(pm_info[1], GEM_CONFIG_FIXED, 0); 5466 if (ret) 5467 goto err_out_phy_exit; 5468 5469 ret = zynqmp_pm_set_gem_config(pm_info[1], GEM_CONFIG_SGMII_MODE, 1); 5470 if (ret) 5471 goto err_out_phy_exit; 5472 } 5473 5474 } 5475 5476 /* Fully reset controller at hardware level if mapped in device tree */ 5477 ret = device_reset_optional(&pdev->dev); 5478 if (ret) { 5479 phy_exit(bp->phy); 5480 return dev_err_probe(&pdev->dev, ret, "failed to reset controller"); 5481 } 5482 5483 ret = macb_init_dflt(pdev); 5484 5485 err_out_phy_exit: 5486 if (ret) 5487 phy_exit(bp->phy); 5488 5489 return ret; 5490 } 5491 5492 static int eyeq5_init(struct platform_device *pdev) 5493 { 5494 struct net_device *netdev = platform_get_drvdata(pdev); 5495 struct macb *bp = netdev_priv(netdev); 5496 struct device *dev = &pdev->dev; 5497 int ret; 5498 5499 bp->phy = devm_phy_get(dev, NULL); 5500 if (IS_ERR(bp->phy)) 5501 return dev_err_probe(dev, PTR_ERR(bp->phy), 5502 "failed to get PHY\n"); 5503 5504 ret = phy_init(bp->phy); 5505 if (ret) 5506 return dev_err_probe(dev, ret, "failed to init PHY\n"); 5507 5508 ret = macb_init_dflt(pdev); 5509 if (ret) 5510 phy_exit(bp->phy); 5511 return ret; 5512 } 5513 5514 static int macb_alloc_tieoff(struct macb *bp) 5515 { 5516 /* Tieoff is a workaround in case HW cannot disable queues, for PM. */ 5517 if (bp->caps & MACB_CAPS_QUEUE_DISABLE) 5518 return 0; 5519 5520 bp->rx_ring_tieoff = dma_alloc_coherent(&bp->pdev->dev, 5521 macb_dma_desc_get_size(bp), 5522 &bp->rx_ring_tieoff_dma, 5523 GFP_KERNEL); 5524 if (!bp->rx_ring_tieoff) 5525 return -ENOMEM; 5526 5527 macb_set_addr(bp, bp->rx_ring_tieoff, 5528 MACB_BIT(RX_WRAP) | MACB_BIT(RX_USED)); 5529 5530 bp->rx_ring_tieoff->ctrl = 0; 5531 5532 return 0; 5533 } 5534 5535 static void macb_free_tieoff(struct macb *bp) 5536 { 5537 if (!bp->rx_ring_tieoff) 5538 return; 5539 5540 dma_free_coherent(&bp->pdev->dev, macb_dma_desc_get_size(bp), 5541 bp->rx_ring_tieoff, 5542 bp->rx_ring_tieoff_dma); 5543 bp->rx_ring_tieoff = NULL; 5544 } 5545 5546 static const struct macb_usrio_config mpfs_usrio = { 5547 .tsu_source = 0, 5548 }; 5549 5550 static const struct macb_usrio_config sama7g5_gem_usrio = { 5551 .mii = 0, 5552 .rmii = 1, 5553 .rgmii = 2, 5554 .refclk = BIT(2), 5555 .refclk_default_external = false, 5556 .hdfctlen = BIT(6), 5557 }; 5558 5559 static const struct macb_usrio_config sama7g5_emac_usrio = { 5560 .mii = 0, 5561 .rmii = 1, 5562 .rgmii = 2, 5563 .refclk = BIT(2), 5564 .refclk_default_external = true, 5565 .hdfctlen = BIT(6), 5566 }; 5567 5568 static const struct macb_config fu540_c000_config = { 5569 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO | 5570 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_USRIO_HAS_MII, 5571 .dma_burst_length = 16, 5572 .clk_init = fu540_c000_clk_init, 5573 .init = fu540_c000_init, 5574 .jumbo_max_len = 10240, 5575 .usrio = &at91_default_usrio, 5576 }; 5577 5578 static const struct macb_config at91sam9260_config = { 5579 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | 5580 MACB_CAPS_USRIO_HAS_MII, 5581 .usrio = &at91_default_usrio, 5582 }; 5583 5584 static const struct macb_config sama5d3macb_config = { 5585 .caps = MACB_CAPS_SG_DISABLED | 5586 MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | 5587 MACB_CAPS_USRIO_HAS_MII, 5588 .usrio = &at91_default_usrio, 5589 }; 5590 5591 static const struct macb_config pc302gem_config = { 5592 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE | 5593 MACB_CAPS_USRIO_HAS_MII, 5594 .dma_burst_length = 16, 5595 .usrio = &at91_default_usrio, 5596 }; 5597 5598 static const struct macb_config sama5d2_config = { 5599 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO | 5600 MACB_CAPS_USRIO_HAS_MII, 5601 .dma_burst_length = 16, 5602 .jumbo_max_len = 10240, 5603 .usrio = &at91_default_usrio, 5604 }; 5605 5606 static const struct macb_config sama5d29_config = { 5607 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_GEM_HAS_PTP | 5608 MACB_CAPS_USRIO_HAS_MII, 5609 .dma_burst_length = 16, 5610 .usrio = &at91_default_usrio, 5611 }; 5612 5613 static const struct macb_config sama5d3_config = { 5614 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE | 5615 MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO | 5616 MACB_CAPS_USRIO_HAS_MII, 5617 .dma_burst_length = 16, 5618 .jumbo_max_len = 10240, 5619 .usrio = &at91_default_usrio, 5620 }; 5621 5622 static const struct macb_config sama5d4_config = { 5623 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | 5624 MACB_CAPS_USRIO_HAS_MII, 5625 .dma_burst_length = 4, 5626 .usrio = &at91_default_usrio, 5627 }; 5628 5629 static const struct macb_config emac_config = { 5630 .caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC | 5631 MACB_CAPS_USRIO_HAS_MII, 5632 .clk_init = at91ether_clk_init, 5633 .init = at91ether_init, 5634 .usrio = &at91_default_usrio, 5635 }; 5636 5637 static const struct macb_config np4_config = { 5638 .caps = MACB_CAPS_USRIO_DISABLED, 5639 }; 5640 5641 static const struct macb_config zynqmp_config = { 5642 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | 5643 MACB_CAPS_JUMBO | 5644 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH | 5645 MACB_CAPS_USRIO_HAS_MII, 5646 .dma_burst_length = 16, 5647 .init = init_reset_optional, 5648 .jumbo_max_len = 10240, 5649 .usrio = &at91_default_usrio, 5650 }; 5651 5652 static const struct macb_config zynq_config = { 5653 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF | 5654 MACB_CAPS_NEEDS_RSTONUBR | 5655 MACB_CAPS_USRIO_HAS_MII, 5656 .dma_burst_length = 16, 5657 .usrio = &at91_default_usrio, 5658 }; 5659 5660 static const struct macb_config mpfs_config = { 5661 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | 5662 MACB_CAPS_JUMBO | 5663 MACB_CAPS_GEM_HAS_PTP | 5664 MACB_CAPS_USRIO_HAS_TSUCLK_SOURCE, 5665 .dma_burst_length = 16, 5666 .init = init_reset_optional, 5667 .usrio = &mpfs_usrio, 5668 .max_tx_length = 4040, /* Cadence Erratum 1686 */ 5669 .jumbo_max_len = 4040, 5670 }; 5671 5672 static const struct macb_config sama7g5_gem_config = { 5673 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG | 5674 MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | 5675 MACB_CAPS_USRIO_HAS_REFCLK_SOURCE | 5676 MACB_CAPS_MIIONRGMII | MACB_CAPS_GEM_HAS_PTP | 5677 MACB_CAPS_USRIO_HAS_MII, 5678 .dma_burst_length = 16, 5679 .usrio = &sama7g5_gem_usrio, 5680 }; 5681 5682 static const struct macb_config sama7g5_emac_config = { 5683 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | 5684 MACB_CAPS_MIIONRGMII | 5685 MACB_CAPS_USRIO_HAS_REFCLK_SOURCE | 5686 MACB_CAPS_GEM_HAS_PTP | 5687 MACB_CAPS_USRIO_HAS_MII, 5688 .dma_burst_length = 16, 5689 .usrio = &sama7g5_emac_usrio, 5690 }; 5691 5692 static const struct macb_config versal_config = { 5693 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO | 5694 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH | 5695 MACB_CAPS_NEED_TSUCLK | MACB_CAPS_QUEUE_DISABLE | 5696 MACB_CAPS_QBV | 5697 MACB_CAPS_USRIO_HAS_MII, 5698 .dma_burst_length = 16, 5699 .init = init_reset_optional, 5700 .jumbo_max_len = 10240, 5701 .usrio = &at91_default_usrio, 5702 }; 5703 5704 static const struct macb_config eyeq5_config = { 5705 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO | 5706 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_QUEUE_DISABLE | 5707 MACB_CAPS_NO_LSO | MACB_CAPS_EEE, 5708 .dma_burst_length = 16, 5709 .init = eyeq5_init, 5710 .jumbo_max_len = 10240, 5711 }; 5712 5713 static const struct macb_config raspberrypi_rp1_config = { 5714 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG | 5715 MACB_CAPS_JUMBO | 5716 MACB_CAPS_GEM_HAS_PTP | 5717 MACB_CAPS_EEE | 5718 MACB_CAPS_USRIO_HAS_MII, 5719 .dma_burst_length = 16, 5720 .usrio = &at91_default_usrio, 5721 .jumbo_max_len = 10240, 5722 }; 5723 5724 static const struct macb_config pic64hpsc_config = { 5725 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO | 5726 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_USRIO_DISABLED, 5727 .dma_burst_length = 16, 5728 .init = init_reset_optional, 5729 .jumbo_max_len = 16383, 5730 }; 5731 5732 static const struct of_device_id macb_dt_ids[] = { 5733 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config }, 5734 { .compatible = "cdns,macb" }, 5735 { .compatible = "cdns,np4-macb", .data = &np4_config }, 5736 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config }, 5737 { .compatible = "cdns,gem", .data = &pc302gem_config }, 5738 { .compatible = "cdns,sam9x60-macb", .data = &at91sam9260_config }, 5739 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config }, 5740 { .compatible = "atmel,sama5d29-gem", .data = &sama5d29_config }, 5741 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config }, 5742 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config }, 5743 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config }, 5744 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config }, 5745 { .compatible = "cdns,emac", .data = &emac_config }, 5746 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config}, /* deprecated */ 5747 { .compatible = "cdns,zynq-gem", .data = &zynq_config }, /* deprecated */ 5748 { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config }, 5749 { .compatible = "microchip,mpfs-macb", .data = &mpfs_config }, 5750 { .compatible = "microchip,pic64hpsc-gem", .data = &pic64hpsc_config}, 5751 { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config }, 5752 { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config }, 5753 { .compatible = "mobileye,eyeq5-gem", .data = &eyeq5_config }, 5754 { .compatible = "raspberrypi,rp1-gem", .data = &raspberrypi_rp1_config }, 5755 { .compatible = "xlnx,zynqmp-gem", .data = &zynqmp_config}, 5756 { .compatible = "xlnx,zynq-gem", .data = &zynq_config }, 5757 { .compatible = "xlnx,versal-gem", .data = &versal_config}, 5758 { /* sentinel */ } 5759 }; 5760 MODULE_DEVICE_TABLE(of, macb_dt_ids); 5761 5762 static const struct macb_config default_gem_config = { 5763 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | 5764 MACB_CAPS_JUMBO | 5765 MACB_CAPS_GEM_HAS_PTP, 5766 .dma_burst_length = 16, 5767 .usrio = &at91_default_usrio, 5768 .jumbo_max_len = 10240, 5769 }; 5770 5771 static int macb_probe(struct platform_device *pdev) 5772 { 5773 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL; 5774 struct device_node *np = pdev->dev.of_node; 5775 const struct macb_config *macb_config; 5776 struct clk *tsu_clk = NULL; 5777 phy_interface_t interface; 5778 struct net_device *netdev; 5779 struct resource *regs; 5780 u32 wtrmrk_rst_val; 5781 void __iomem *mem; 5782 struct macb *bp; 5783 int num_queues; 5784 bool native_io; 5785 int err, val; 5786 5787 mem = devm_platform_get_and_ioremap_resource(pdev, 0, ®s); 5788 if (IS_ERR(mem)) 5789 return PTR_ERR(mem); 5790 5791 macb_config = of_device_get_match_data(&pdev->dev); 5792 if (!macb_config) 5793 macb_config = &default_gem_config; 5794 5795 err = macb_clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk, &tsu_clk, 5796 macb_config); 5797 if (err) 5798 return err; 5799 5800 pm_runtime_set_autosuspend_delay(&pdev->dev, MACB_PM_TIMEOUT); 5801 pm_runtime_use_autosuspend(&pdev->dev); 5802 pm_runtime_get_noresume(&pdev->dev); 5803 pm_runtime_set_active(&pdev->dev); 5804 pm_runtime_enable(&pdev->dev); 5805 native_io = hw_is_native_io(mem); 5806 5807 num_queues = macb_probe_queues(&pdev->dev, mem, native_io); 5808 if (num_queues < 0) { 5809 err = num_queues; 5810 goto err_disable_clocks; 5811 } 5812 5813 netdev = alloc_etherdev_mq(sizeof(*bp), num_queues); 5814 if (!netdev) { 5815 err = -ENOMEM; 5816 goto err_disable_clocks; 5817 } 5818 5819 netdev->base_addr = regs->start; 5820 5821 SET_NETDEV_DEV(netdev, &pdev->dev); 5822 5823 bp = netdev_priv(netdev); 5824 bp->pdev = pdev; 5825 bp->netdev = netdev; 5826 bp->regs = mem; 5827 bp->native_io = native_io; 5828 if (native_io) { 5829 bp->macb_reg_readl = hw_readl_native; 5830 bp->macb_reg_writel = hw_writel_native; 5831 } else { 5832 bp->macb_reg_readl = hw_readl; 5833 bp->macb_reg_writel = hw_writel; 5834 } 5835 bp->num_queues = num_queues; 5836 bp->dma_burst_length = macb_config->dma_burst_length; 5837 bp->pclk = pclk; 5838 bp->hclk = hclk; 5839 bp->tx_clk = tx_clk; 5840 bp->rx_clk = rx_clk; 5841 bp->tsu_clk = tsu_clk; 5842 bp->jumbo_max_len = macb_config->jumbo_max_len; 5843 5844 if (!hw_is_gem(bp->regs, bp->native_io)) 5845 bp->max_tx_length = MACB_MAX_TX_LEN; 5846 else if (macb_config->max_tx_length) 5847 bp->max_tx_length = macb_config->max_tx_length; 5848 else 5849 bp->max_tx_length = GEM_MAX_TX_LEN; 5850 5851 bp->wol = 0; 5852 device_set_wakeup_capable(&pdev->dev, 1); 5853 5854 bp->usrio = macb_config->usrio; 5855 5856 if (of_property_read_bool(bp->pdev->dev.of_node, "cdns,timer-adjust") && 5857 IS_ENABLED(CONFIG_MACB_USE_HWSTAMP)) { 5858 dev_err(&pdev->dev, "Timer adjust mode is not supported\n"); 5859 err = -EINVAL; 5860 goto err_out_free_netdev; 5861 } 5862 5863 /* By default we set to partial store and forward mode for zynqmp. 5864 * Disable if not set in devicetree. 5865 */ 5866 if (GEM_BFEXT(PBUF_CUTTHRU, gem_readl(bp, DCFG6))) { 5867 err = of_property_read_u32(bp->pdev->dev.of_node, 5868 "cdns,rx-watermark", 5869 &bp->rx_watermark); 5870 5871 if (!err) { 5872 /* Disable partial store and forward in case of error or 5873 * invalid watermark value 5874 */ 5875 wtrmrk_rst_val = (1 << (GEM_BFEXT(RX_PBUF_ADDR, gem_readl(bp, DCFG2)))) - 1; 5876 if (bp->rx_watermark > wtrmrk_rst_val || !bp->rx_watermark) { 5877 dev_info(&bp->pdev->dev, "Invalid watermark value\n"); 5878 bp->rx_watermark = 0; 5879 } 5880 } 5881 } 5882 spin_lock_init(&bp->lock); 5883 spin_lock_init(&bp->stats_lock); 5884 5885 /* setup capabilities */ 5886 macb_configure_caps(bp, macb_config); 5887 5888 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 5889 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) { 5890 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44)); 5891 if (err) { 5892 dev_err(&pdev->dev, "failed to set DMA mask\n"); 5893 goto err_out_free_netdev; 5894 } 5895 bp->caps |= MACB_CAPS_DMA_64B; 5896 } 5897 #endif 5898 platform_set_drvdata(pdev, netdev); 5899 5900 netdev->irq = platform_get_irq(pdev, 0); 5901 if (netdev->irq < 0) { 5902 err = netdev->irq; 5903 goto err_out_free_netdev; 5904 } 5905 5906 /* MTU range: 68 - 1518 or 10240 */ 5907 netdev->min_mtu = GEM_MTU_MIN_SIZE; 5908 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len) 5909 netdev->max_mtu = MIN(bp->jumbo_max_len, RX_BUFFER_MAX) - 5910 ETH_HLEN - ETH_FCS_LEN; 5911 else 5912 netdev->max_mtu = 1536 - ETH_HLEN - ETH_FCS_LEN; 5913 5914 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) { 5915 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10)); 5916 if (val) 5917 bp->rx_bd_rd_prefetch = (2 << (val - 1)) * 5918 macb_dma_desc_get_size(bp); 5919 5920 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10)); 5921 if (val) 5922 bp->tx_bd_rd_prefetch = (2 << (val - 1)) * 5923 macb_dma_desc_get_size(bp); 5924 } 5925 5926 bp->rx_intr_mask = MACB_RX_INT_FLAGS; 5927 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR) 5928 bp->rx_intr_mask |= MACB_BIT(RXUBR); 5929 5930 err = of_get_ethdev_address(np, bp->netdev); 5931 if (err == -EPROBE_DEFER) 5932 goto err_out_free_netdev; 5933 else if (err) 5934 macb_get_hwaddr(bp); 5935 5936 err = of_get_phy_mode(np, &interface); 5937 if (err) 5938 /* not found in DT, MII by default */ 5939 bp->phy_interface = PHY_INTERFACE_MODE_MII; 5940 else 5941 bp->phy_interface = interface; 5942 5943 /* IP specific init */ 5944 err = macb_init(pdev, macb_config); 5945 if (err) 5946 goto err_out_free_netdev; 5947 5948 err = macb_mii_init(bp); 5949 if (err) 5950 goto err_out_phy_exit; 5951 5952 netif_carrier_off(netdev); 5953 5954 err = macb_alloc_tieoff(bp); 5955 if (err) 5956 goto err_out_unregister_mdio; 5957 5958 err = register_netdev(netdev); 5959 if (err) { 5960 dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); 5961 goto err_out_free_tieoff; 5962 } 5963 5964 INIT_WORK(&bp->hresp_err_bh_work, macb_hresp_error_task); 5965 INIT_DELAYED_WORK(&bp->tx_lpi_work, macb_tx_lpi_work_fn); 5966 5967 netdev_info(netdev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n", 5968 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID), 5969 netdev->base_addr, netdev->irq, netdev->dev_addr); 5970 5971 pm_runtime_put_autosuspend(&bp->pdev->dev); 5972 5973 return 0; 5974 5975 err_out_free_tieoff: 5976 macb_free_tieoff(bp); 5977 5978 err_out_unregister_mdio: 5979 mdiobus_unregister(bp->mii_bus); 5980 mdiobus_free(bp->mii_bus); 5981 5982 err_out_phy_exit: 5983 phy_exit(bp->phy); 5984 5985 err_out_free_netdev: 5986 free_netdev(netdev); 5987 5988 err_disable_clocks: 5989 macb_clks_disable(pclk, hclk, tx_clk, rx_clk, tsu_clk); 5990 pm_runtime_disable(&pdev->dev); 5991 pm_runtime_set_suspended(&pdev->dev); 5992 pm_runtime_dont_use_autosuspend(&pdev->dev); 5993 5994 return err; 5995 } 5996 5997 static void macb_remove(struct platform_device *pdev) 5998 { 5999 struct net_device *netdev; 6000 struct macb *bp; 6001 6002 netdev = platform_get_drvdata(pdev); 6003 6004 if (netdev) { 6005 bp = netdev_priv(netdev); 6006 unregister_netdev(netdev); 6007 macb_free_tieoff(bp); 6008 phy_exit(bp->phy); 6009 mdiobus_unregister(bp->mii_bus); 6010 mdiobus_free(bp->mii_bus); 6011 6012 device_set_wakeup_enable(&bp->pdev->dev, 0); 6013 cancel_delayed_work_sync(&bp->tx_lpi_work); 6014 cancel_work_sync(&bp->hresp_err_bh_work); 6015 pm_runtime_disable(&pdev->dev); 6016 pm_runtime_dont_use_autosuspend(&pdev->dev); 6017 pm_runtime_set_suspended(&pdev->dev); 6018 phylink_destroy(bp->phylink); 6019 free_netdev(netdev); 6020 } 6021 } 6022 6023 static int __maybe_unused macb_suspend(struct device *dev) 6024 { 6025 struct net_device *netdev = dev_get_drvdata(dev); 6026 struct macb *bp = netdev_priv(netdev); 6027 struct in_ifaddr *ifa = NULL; 6028 struct macb_queue *queue; 6029 struct in_device *idev; 6030 unsigned long flags; 6031 u32 tmp, ifa_local; 6032 unsigned int q; 6033 6034 if (!device_may_wakeup(&bp->netdev->dev)) 6035 phy_exit(bp->phy); 6036 6037 if (!netif_running(netdev)) 6038 return 0; 6039 6040 if (bp->wol & MACB_WOL_ENABLED) { 6041 if (bp->wolopts & WAKE_ARP) { 6042 /* Check for IP address in WOL ARP mode */ 6043 rcu_read_lock(); 6044 idev = __in_dev_get_rcu(bp->netdev); 6045 if (idev) 6046 ifa = rcu_dereference(idev->ifa_list); 6047 if (!ifa) { 6048 rcu_read_unlock(); 6049 netdev_err(netdev, "IP address not assigned as required by WoL walk ARP\n"); 6050 return -EOPNOTSUPP; 6051 } 6052 ifa_local = be32_to_cpu(ifa->ifa_local); 6053 rcu_read_unlock(); 6054 } 6055 6056 spin_lock_irqsave(&bp->lock, flags); 6057 6058 /* Disable Tx and Rx engines before disabling the queues, 6059 * this is mandatory as per the IP spec sheet 6060 */ 6061 tmp = macb_readl(bp, NCR); 6062 macb_writel(bp, NCR, tmp & ~(MACB_BIT(TE) | MACB_BIT(RE))); 6063 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 6064 if (!(bp->caps & MACB_CAPS_QUEUE_DISABLE)) 6065 macb_writel(bp, RBQPH, 6066 upper_32_bits(bp->rx_ring_tieoff_dma)); 6067 #endif 6068 for (q = 0, queue = bp->queues; q < bp->num_queues; 6069 ++q, ++queue) { 6070 /* Disable RX queues */ 6071 if (bp->caps & MACB_CAPS_QUEUE_DISABLE) { 6072 queue_writel(queue, RBQP, MACB_BIT(QUEUE_DISABLE)); 6073 } else { 6074 /* Tie off RX queues */ 6075 queue_writel(queue, RBQP, 6076 lower_32_bits(bp->rx_ring_tieoff_dma)); 6077 } 6078 /* Disable all interrupts */ 6079 queue_writel(queue, IDR, -1); 6080 queue_readl(queue, ISR); 6081 macb_queue_isr_clear(bp, queue, -1); 6082 } 6083 /* Enable Receive engine */ 6084 macb_writel(bp, NCR, tmp | MACB_BIT(RE)); 6085 /* Flush all status bits */ 6086 macb_writel(bp, TSR, -1); 6087 macb_writel(bp, RSR, -1); 6088 6089 tmp = (bp->wolopts & WAKE_MAGIC) ? MACB_BIT(MAG) : 0; 6090 if (bp->wolopts & WAKE_ARP) { 6091 tmp |= MACB_BIT(ARP); 6092 /* write IP address into register */ 6093 tmp |= MACB_BFEXT(IP, ifa_local); 6094 } 6095 6096 if (macb_is_gem(bp)) { 6097 queue_writel(bp->queues, IER, GEM_BIT(WOL)); 6098 gem_writel(bp, WOL, tmp); 6099 } else { 6100 queue_writel(bp->queues, IER, MACB_BIT(WOL)); 6101 macb_writel(bp, WOL, tmp); 6102 } 6103 spin_unlock_irqrestore(&bp->lock, flags); 6104 6105 enable_irq_wake(bp->queues[0].irq); 6106 } 6107 6108 netif_device_detach(netdev); 6109 for (q = 0, queue = bp->queues; q < bp->num_queues; 6110 ++q, ++queue) { 6111 napi_disable(&queue->napi_rx); 6112 napi_disable(&queue->napi_tx); 6113 } 6114 6115 if (!(bp->wol & MACB_WOL_ENABLED)) { 6116 rtnl_lock(); 6117 phylink_stop(bp->phylink); 6118 rtnl_unlock(); 6119 spin_lock_irqsave(&bp->lock, flags); 6120 macb_reset_hw(bp); 6121 spin_unlock_irqrestore(&bp->lock, flags); 6122 } 6123 6124 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) 6125 bp->pm_data.usrio = macb_or_gem_readl(bp, USRIO); 6126 6127 if (netdev->hw_features & NETIF_F_NTUPLE) 6128 bp->pm_data.scrt2 = gem_readl_n(bp, ETHT, SCRT2_ETHT); 6129 6130 if (bp->ptp_info) 6131 bp->ptp_info->ptp_remove(netdev); 6132 if (!device_may_wakeup(dev)) 6133 pm_runtime_force_suspend(dev); 6134 6135 return 0; 6136 } 6137 6138 static int __maybe_unused macb_resume(struct device *dev) 6139 { 6140 struct net_device *netdev = dev_get_drvdata(dev); 6141 struct macb *bp = netdev_priv(netdev); 6142 struct macb_queue *queue; 6143 unsigned long flags; 6144 unsigned int q; 6145 6146 if (!device_may_wakeup(&bp->netdev->dev)) 6147 phy_init(bp->phy); 6148 6149 if (!netif_running(netdev)) 6150 return 0; 6151 6152 if (!device_may_wakeup(dev)) 6153 pm_runtime_force_resume(dev); 6154 6155 if (bp->wol & MACB_WOL_ENABLED) { 6156 spin_lock_irqsave(&bp->lock, flags); 6157 /* Disable WoL */ 6158 if (macb_is_gem(bp)) { 6159 queue_writel(bp->queues, IDR, GEM_BIT(WOL)); 6160 gem_writel(bp, WOL, 0); 6161 } else { 6162 queue_writel(bp->queues, IDR, MACB_BIT(WOL)); 6163 macb_writel(bp, WOL, 0); 6164 } 6165 /* Clear ISR on queue 0 */ 6166 queue_readl(bp->queues, ISR); 6167 macb_queue_isr_clear(bp, bp->queues, -1); 6168 spin_unlock_irqrestore(&bp->lock, flags); 6169 6170 disable_irq_wake(bp->queues[0].irq); 6171 6172 /* Now make sure we disable phy before moving 6173 * to common restore path 6174 */ 6175 rtnl_lock(); 6176 phylink_stop(bp->phylink); 6177 rtnl_unlock(); 6178 } 6179 6180 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) 6181 macb_init_buffers(bp); 6182 6183 for (q = 0, queue = bp->queues; q < bp->num_queues; 6184 ++q, ++queue) { 6185 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) { 6186 if (macb_is_gem(bp)) 6187 gem_init_rx_ring(queue); 6188 else 6189 macb_init_rx_ring(queue); 6190 } 6191 6192 napi_enable(&queue->napi_rx); 6193 napi_enable(&queue->napi_tx); 6194 } 6195 6196 if (netdev->hw_features & NETIF_F_NTUPLE) 6197 gem_writel_n(bp, ETHT, SCRT2_ETHT, bp->pm_data.scrt2); 6198 6199 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) 6200 macb_or_gem_writel(bp, USRIO, bp->pm_data.usrio); 6201 6202 macb_writel(bp, NCR, MACB_BIT(MPE)); 6203 macb_init_hw(bp); 6204 macb_set_rx_mode(netdev); 6205 macb_restore_features(bp); 6206 rtnl_lock(); 6207 6208 phylink_start(bp->phylink); 6209 rtnl_unlock(); 6210 6211 netif_device_attach(netdev); 6212 if (bp->ptp_info) 6213 bp->ptp_info->ptp_init(netdev); 6214 6215 return 0; 6216 } 6217 6218 static int __maybe_unused macb_runtime_suspend(struct device *dev) 6219 { 6220 struct net_device *netdev = dev_get_drvdata(dev); 6221 struct macb *bp = netdev_priv(netdev); 6222 6223 if (!(device_may_wakeup(dev))) 6224 macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, bp->rx_clk, bp->tsu_clk); 6225 else if (!(bp->caps & MACB_CAPS_NEED_TSUCLK)) 6226 macb_clks_disable(NULL, NULL, NULL, NULL, bp->tsu_clk); 6227 6228 return 0; 6229 } 6230 6231 static int __maybe_unused macb_runtime_resume(struct device *dev) 6232 { 6233 struct net_device *netdev = dev_get_drvdata(dev); 6234 struct macb *bp = netdev_priv(netdev); 6235 6236 if (!(device_may_wakeup(dev))) { 6237 clk_prepare_enable(bp->pclk); 6238 clk_prepare_enable(bp->hclk); 6239 clk_prepare_enable(bp->tx_clk); 6240 clk_prepare_enable(bp->rx_clk); 6241 clk_prepare_enable(bp->tsu_clk); 6242 } else if (!(bp->caps & MACB_CAPS_NEED_TSUCLK)) { 6243 clk_prepare_enable(bp->tsu_clk); 6244 } 6245 6246 return 0; 6247 } 6248 6249 static void macb_shutdown(struct platform_device *pdev) 6250 { 6251 struct net_device *netdev = platform_get_drvdata(pdev); 6252 6253 rtnl_lock(); 6254 6255 if (netif_running(netdev)) 6256 dev_close(netdev); 6257 6258 netif_device_detach(netdev); 6259 6260 rtnl_unlock(); 6261 } 6262 6263 static const struct dev_pm_ops macb_pm_ops = { 6264 SET_SYSTEM_SLEEP_PM_OPS(macb_suspend, macb_resume) 6265 SET_RUNTIME_PM_OPS(macb_runtime_suspend, macb_runtime_resume, NULL) 6266 }; 6267 6268 static struct platform_driver macb_driver = { 6269 .probe = macb_probe, 6270 .remove = macb_remove, 6271 .driver = { 6272 .name = "macb", 6273 .of_match_table = macb_dt_ids, 6274 .pm = &macb_pm_ops, 6275 }, 6276 .shutdown = macb_shutdown, 6277 }; 6278 6279 module_platform_driver(macb_driver); 6280 6281 MODULE_LICENSE("GPL"); 6282 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver"); 6283 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 6284 MODULE_ALIAS("platform:macb"); 6285