1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Atmel MACB Ethernet Controller driver 4 * 5 * Copyright (C) 2004-2006 Atmel Corporation 6 */ 7 #ifndef _MACB_H 8 #define _MACB_H 9 10 #include <linux/clk.h> 11 #include <linux/phylink.h> 12 #include <linux/ptp_clock_kernel.h> 13 #include <linux/net_tstamp.h> 14 #include <linux/interrupt.h> 15 #include <linux/phy/phy.h> 16 #include <linux/workqueue.h> 17 18 #if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) || defined(CONFIG_MACB_USE_HWSTAMP) 19 #define MACB_EXT_DESC 20 #endif 21 22 #define MACB_GREGS_NBR 16 23 #define MACB_GREGS_VERSION 2 24 #define MACB_MAX_QUEUES 8 25 26 /* MACB register offsets */ 27 #define MACB_NCR 0x0000 /* Network Control */ 28 #define MACB_NCFGR 0x0004 /* Network Config */ 29 #define MACB_NSR 0x0008 /* Network Status */ 30 #define MACB_TAR 0x000c /* AT91RM9200 only */ 31 #define MACB_TCR 0x0010 /* AT91RM9200 only */ 32 #define MACB_TSR 0x0014 /* Transmit Status */ 33 #define MACB_RBQP 0x0018 /* RX Q Base Address */ 34 #define MACB_TBQP 0x001c /* TX Q Base Address */ 35 #define MACB_RSR 0x0020 /* Receive Status */ 36 #define MACB_ISR 0x0024 /* Interrupt Status */ 37 #define MACB_IER 0x0028 /* Interrupt Enable */ 38 #define MACB_IDR 0x002c /* Interrupt Disable */ 39 #define MACB_IMR 0x0030 /* Interrupt Mask */ 40 #define MACB_MAN 0x0034 /* PHY Maintenance */ 41 #define MACB_PTR 0x0038 42 #define MACB_PFR 0x003c 43 #define MACB_FTO 0x0040 44 #define MACB_SCF 0x0044 45 #define MACB_MCF 0x0048 46 #define MACB_FRO 0x004c 47 #define MACB_FCSE 0x0050 48 #define MACB_ALE 0x0054 49 #define MACB_DTF 0x0058 50 #define MACB_LCOL 0x005c 51 #define MACB_EXCOL 0x0060 52 #define MACB_TUND 0x0064 53 #define MACB_CSE 0x0068 54 #define MACB_RRE 0x006c 55 #define MACB_ROVR 0x0070 56 #define MACB_RSE 0x0074 57 #define MACB_ELE 0x0078 58 #define MACB_RJA 0x007c 59 #define MACB_USF 0x0080 60 #define MACB_STE 0x0084 61 #define MACB_RLE 0x0088 62 #define MACB_TPF 0x008c 63 #define MACB_HRB 0x0090 64 #define MACB_HRT 0x0094 65 #define MACB_SA1B 0x0098 66 #define MACB_SA1T 0x009c 67 #define MACB_SA2B 0x00a0 68 #define MACB_SA2T 0x00a4 69 #define MACB_SA3B 0x00a8 70 #define MACB_SA3T 0x00ac 71 #define MACB_SA4B 0x00b0 72 #define MACB_SA4T 0x00b4 73 #define MACB_TID 0x00b8 74 #define MACB_TPQ 0x00bc 75 #define MACB_USRIO 0x00c0 76 #define MACB_WOL 0x00c4 77 #define MACB_MID 0x00fc 78 #define MACB_TBQPH 0x04C8 79 #define MACB_RBQPH 0x04D4 80 81 /* GEM register offsets. */ 82 #define GEM_NCR 0x0000 /* Network Control */ 83 #define GEM_NCFGR 0x0004 /* Network Config */ 84 #define GEM_USRIO 0x000c /* User IO */ 85 #define GEM_DMACFG 0x0010 /* DMA Configuration */ 86 #define GEM_PBUFRXCUT 0x0044 /* RX Partial Store and Forward */ 87 #define GEM_JML 0x0048 /* Jumbo Max Length */ 88 #define GEM_HS_MAC_CONFIG 0x0050 /* GEM high speed config */ 89 #define GEM_HRB 0x0080 /* Hash Bottom */ 90 #define GEM_HRT 0x0084 /* Hash Top */ 91 #define GEM_SA1B 0x0088 /* Specific1 Bottom */ 92 #define GEM_SA1T 0x008C /* Specific1 Top */ 93 #define GEM_SA2B 0x0090 /* Specific2 Bottom */ 94 #define GEM_SA2T 0x0094 /* Specific2 Top */ 95 #define GEM_SA3B 0x0098 /* Specific3 Bottom */ 96 #define GEM_SA3T 0x009C /* Specific3 Top */ 97 #define GEM_SA4B 0x00A0 /* Specific4 Bottom */ 98 #define GEM_SA4T 0x00A4 /* Specific4 Top */ 99 #define GEM_WOL 0x00b8 /* Wake on LAN */ 100 #define GEM_RXPTPUNI 0x00D4 /* PTP RX Unicast address */ 101 #define GEM_TXPTPUNI 0x00D8 /* PTP TX Unicast address */ 102 #define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */ 103 #define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */ 104 #define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */ 105 #define GEM_PEFRSH 0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */ 106 #define GEM_OTX 0x0100 /* Octets transmitted */ 107 #define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */ 108 #define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */ 109 #define GEM_TXCNT 0x0108 /* Frames Transmitted counter */ 110 #define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */ 111 #define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */ 112 #define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */ 113 #define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */ 114 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */ 115 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */ 116 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */ 117 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */ 118 #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */ 119 #define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */ 120 #define GEM_TXURUNCNT 0x0134 /* TX under run error counter */ 121 #define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */ 122 #define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */ 123 #define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */ 124 #define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */ 125 #define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */ 126 #define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */ 127 #define GEM_ORX 0x0150 /* Octets received */ 128 #define GEM_OCTRXL 0x0150 /* Octets received [31:0] */ 129 #define GEM_OCTRXH 0x0154 /* Octets received [47:32] */ 130 #define GEM_RXCNT 0x0158 /* Frames Received Counter */ 131 #define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */ 132 #define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */ 133 #define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */ 134 #define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */ 135 #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */ 136 #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */ 137 #define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */ 138 #define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */ 139 #define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */ 140 #define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */ 141 #define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */ 142 #define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */ 143 #define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */ 144 #define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */ 145 #define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */ 146 #define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */ 147 #define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */ 148 #define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */ 149 #define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */ 150 #define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */ 151 #define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */ 152 #define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */ 153 #define GEM_TISUBN 0x01bc /* 1588 Timer Increment Sub-ns */ 154 #define GEM_TSH 0x01c0 /* 1588 Timer Seconds High */ 155 #define GEM_TSL 0x01d0 /* 1588 Timer Seconds Low */ 156 #define GEM_TN 0x01d4 /* 1588 Timer Nanoseconds */ 157 #define GEM_TA 0x01d8 /* 1588 Timer Adjust */ 158 #define GEM_TI 0x01dc /* 1588 Timer Increment */ 159 #define GEM_EFTSL 0x01e0 /* PTP Event Frame Tx Seconds Low */ 160 #define GEM_EFTN 0x01e4 /* PTP Event Frame Tx Nanoseconds */ 161 #define GEM_EFRSL 0x01e8 /* PTP Event Frame Rx Seconds Low */ 162 #define GEM_EFRN 0x01ec /* PTP Event Frame Rx Nanoseconds */ 163 #define GEM_PEFTSL 0x01f0 /* PTP Peer Event Frame Tx Secs Low */ 164 #define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */ 165 #define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */ 166 #define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */ 167 #define GEM_PCSCNTRL 0x0200 /* PCS Control */ 168 #define GEM_PCSSTS 0x0204 /* PCS Status */ 169 #define GEM_PCSPHYTOPID 0x0208 /* PCS PHY Top ID */ 170 #define GEM_PCSPHYBOTID 0x020c /* PCS PHY Bottom ID */ 171 #define GEM_PCSANADV 0x0210 /* PCS AN Advertisement */ 172 #define GEM_PCSANLPBASE 0x0214 /* PCS AN Link Partner Base */ 173 #define GEM_PCSANEXP 0x0218 /* PCS AN Expansion */ 174 #define GEM_PCSANNPTX 0x021c /* PCS AN Next Page TX */ 175 #define GEM_PCSANNPLP 0x0220 /* PCS AN Next Page LP */ 176 #define GEM_PCSANEXTSTS 0x023c /* PCS AN Extended Status */ 177 #define GEM_DCFG1 0x0280 /* Design Config 1 */ 178 #define GEM_DCFG2 0x0284 /* Design Config 2 */ 179 #define GEM_DCFG3 0x0288 /* Design Config 3 */ 180 #define GEM_DCFG4 0x028c /* Design Config 4 */ 181 #define GEM_DCFG5 0x0290 /* Design Config 5 */ 182 #define GEM_DCFG6 0x0294 /* Design Config 6 */ 183 #define GEM_DCFG7 0x0298 /* Design Config 7 */ 184 #define GEM_DCFG8 0x029C /* Design Config 8 */ 185 #define GEM_DCFG10 0x02A4 /* Design Config 10 */ 186 #define GEM_DCFG12 0x02AC /* Design Config 12 */ 187 #define GEM_USX_CONTROL 0x0A80 /* High speed PCS control register */ 188 #define GEM_USX_STATUS 0x0A88 /* High speed PCS status register */ 189 190 #define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */ 191 #define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */ 192 193 /* Screener Type 2 match registers */ 194 #define GEM_SCRT2 0x540 195 196 /* EtherType registers */ 197 #define GEM_ETHT 0x06E0 198 199 /* Type 2 compare registers */ 200 #define GEM_T2CMPW0 0x0700 201 #define GEM_T2CMPW1 0x0704 202 #define T2CMP_OFST(t2idx) (t2idx * 2) 203 204 /* type 2 compare registers 205 * each location requires 3 compare regs 206 */ 207 #define GEM_IP4SRC_CMP(idx) (idx * 3) 208 #define GEM_IP4DST_CMP(idx) (idx * 3 + 1) 209 #define GEM_PORT_CMP(idx) (idx * 3 + 2) 210 211 /* Which screening type 2 EtherType register will be used (0 - 7) */ 212 #define SCRT2_ETHT 0 213 214 #define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2)) 215 #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2)) 216 #define GEM_TBQPH(hw_q) (0x04C8) 217 #define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2)) 218 #define GEM_RBQS(hw_q) (0x04A0 + ((hw_q) << 2)) 219 #define GEM_RBQPH(hw_q) (0x04D4) 220 #define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2)) 221 #define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2)) 222 #define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2)) 223 224 /* Bitfields in NCR */ 225 #define MACB_LB_OFFSET 0 /* reserved */ 226 #define MACB_LB_SIZE 1 227 #define MACB_LLB_OFFSET 1 /* Loop back local */ 228 #define MACB_LLB_SIZE 1 229 #define MACB_RE_OFFSET 2 /* Receive enable */ 230 #define MACB_RE_SIZE 1 231 #define MACB_TE_OFFSET 3 /* Transmit enable */ 232 #define MACB_TE_SIZE 1 233 #define MACB_MPE_OFFSET 4 /* Management port enable */ 234 #define MACB_MPE_SIZE 1 235 #define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */ 236 #define MACB_CLRSTAT_SIZE 1 237 #define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */ 238 #define MACB_INCSTAT_SIZE 1 239 #define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */ 240 #define MACB_WESTAT_SIZE 1 241 #define MACB_BP_OFFSET 8 /* Back pressure */ 242 #define MACB_BP_SIZE 1 243 #define MACB_TSTART_OFFSET 9 /* Start transmission */ 244 #define MACB_TSTART_SIZE 1 245 #define MACB_THALT_OFFSET 10 /* Transmit halt */ 246 #define MACB_THALT_SIZE 1 247 #define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */ 248 #define MACB_NCR_TPF_SIZE 1 249 #define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */ 250 #define MACB_TZQ_SIZE 1 251 #define MACB_SRTSM_OFFSET 15 /* Store Receive Timestamp to Memory */ 252 #define MACB_PTPUNI_OFFSET 20 /* PTP Unicast packet enable */ 253 #define MACB_PTPUNI_SIZE 1 254 #define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */ 255 #define MACB_OSSMODE_SIZE 1 256 #define MACB_MIIONRGMII_OFFSET 28 /* MII Usage on RGMII Interface */ 257 #define MACB_MIIONRGMII_SIZE 1 258 259 /* Bitfields in NCFGR */ 260 #define MACB_SPD_OFFSET 0 /* Speed */ 261 #define MACB_SPD_SIZE 1 262 #define MACB_FD_OFFSET 1 /* Full duplex */ 263 #define MACB_FD_SIZE 1 264 #define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */ 265 #define MACB_BIT_RATE_SIZE 1 266 #define MACB_JFRAME_OFFSET 3 /* reserved */ 267 #define MACB_JFRAME_SIZE 1 268 #define MACB_CAF_OFFSET 4 /* Copy all frames */ 269 #define MACB_CAF_SIZE 1 270 #define MACB_NBC_OFFSET 5 /* No broadcast */ 271 #define MACB_NBC_SIZE 1 272 #define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */ 273 #define MACB_NCFGR_MTI_SIZE 1 274 #define MACB_UNI_OFFSET 7 /* Unicast hash enable */ 275 #define MACB_UNI_SIZE 1 276 #define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */ 277 #define MACB_BIG_SIZE 1 278 #define MACB_EAE_OFFSET 9 /* External address match enable */ 279 #define MACB_EAE_SIZE 1 280 #define MACB_CLK_OFFSET 10 281 #define MACB_CLK_SIZE 2 282 #define MACB_RTY_OFFSET 12 /* Retry test */ 283 #define MACB_RTY_SIZE 1 284 #define MACB_PAE_OFFSET 13 /* Pause enable */ 285 #define MACB_PAE_SIZE 1 286 #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */ 287 #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */ 288 #define MACB_RBOF_OFFSET 14 /* Receive buffer offset */ 289 #define MACB_RBOF_SIZE 2 290 #define MACB_RLCE_OFFSET 16 /* Length field error frame discard */ 291 #define MACB_RLCE_SIZE 1 292 #define MACB_DRFCS_OFFSET 17 /* FCS remove */ 293 #define MACB_DRFCS_SIZE 1 294 #define MACB_EFRHD_OFFSET 18 295 #define MACB_EFRHD_SIZE 1 296 #define MACB_IRXFCS_OFFSET 19 297 #define MACB_IRXFCS_SIZE 1 298 299 /* GEM specific NCR bitfields. */ 300 #define GEM_ENABLE_HS_MAC_OFFSET 31 301 #define GEM_ENABLE_HS_MAC_SIZE 1 302 303 /* GEM specific NCFGR bitfields. */ 304 #define GEM_FD_OFFSET 1 /* Full duplex */ 305 #define GEM_FD_SIZE 1 306 #define GEM_GBE_OFFSET 10 /* Gigabit mode enable */ 307 #define GEM_GBE_SIZE 1 308 #define GEM_PCSSEL_OFFSET 11 309 #define GEM_PCSSEL_SIZE 1 310 #define GEM_PAE_OFFSET 13 /* Pause enable */ 311 #define GEM_PAE_SIZE 1 312 #define GEM_CLK_OFFSET 18 /* MDC clock division */ 313 #define GEM_CLK_SIZE 3 314 #define GEM_DBW_OFFSET 21 /* Data bus width */ 315 #define GEM_DBW_SIZE 2 316 #define GEM_RXCOEN_OFFSET 24 317 #define GEM_RXCOEN_SIZE 1 318 #define GEM_SGMIIEN_OFFSET 27 319 #define GEM_SGMIIEN_SIZE 1 320 321 322 /* Constants for data bus width. */ 323 #define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */ 324 #define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */ 325 #define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */ 326 327 /* Bitfields in DMACFG. */ 328 #define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */ 329 #define GEM_FBLDO_SIZE 5 330 #define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */ 331 #define GEM_ENDIA_DESC_SIZE 1 332 #define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */ 333 #define GEM_ENDIA_PKT_SIZE 1 334 #define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */ 335 #define GEM_RXBMS_SIZE 2 336 #define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */ 337 #define GEM_TXPBMS_SIZE 1 338 #define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */ 339 #define GEM_TXCOEN_SIZE 1 340 #define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */ 341 #define GEM_RXBS_SIZE 8 342 #define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */ 343 #define GEM_DDRP_SIZE 1 344 #define GEM_RXEXT_OFFSET 28 /* RX extended Buffer Descriptor mode */ 345 #define GEM_RXEXT_SIZE 1 346 #define GEM_TXEXT_OFFSET 29 /* TX extended Buffer Descriptor mode */ 347 #define GEM_TXEXT_SIZE 1 348 #define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */ 349 #define GEM_ADDR64_SIZE 1 350 351 352 /* Bitfields in PBUFRXCUT */ 353 #define GEM_ENCUTTHRU_OFFSET 31 /* Enable RX partial store and forward */ 354 #define GEM_ENCUTTHRU_SIZE 1 355 356 /* Bitfields in NSR */ 357 #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */ 358 #define MACB_NSR_LINK_SIZE 1 359 #define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */ 360 #define MACB_MDIO_SIZE 1 361 #define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */ 362 #define MACB_IDLE_SIZE 1 363 364 /* Bitfields in TSR */ 365 #define MACB_UBR_OFFSET 0 /* Used bit read */ 366 #define MACB_UBR_SIZE 1 367 #define MACB_COL_OFFSET 1 /* Collision occurred */ 368 #define MACB_COL_SIZE 1 369 #define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */ 370 #define MACB_TSR_RLE_SIZE 1 371 #define MACB_TGO_OFFSET 3 /* Transmit go */ 372 #define MACB_TGO_SIZE 1 373 #define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */ 374 #define MACB_BEX_SIZE 1 375 #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */ 376 #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */ 377 #define MACB_COMP_OFFSET 5 /* Trnasmit complete */ 378 #define MACB_COMP_SIZE 1 379 #define MACB_UND_OFFSET 6 /* Trnasmit under run */ 380 #define MACB_UND_SIZE 1 381 382 /* Bitfields in RSR */ 383 #define MACB_BNA_OFFSET 0 /* Buffer not available */ 384 #define MACB_BNA_SIZE 1 385 #define MACB_REC_OFFSET 1 /* Frame received */ 386 #define MACB_REC_SIZE 1 387 #define MACB_OVR_OFFSET 2 /* Receive overrun */ 388 #define MACB_OVR_SIZE 1 389 390 /* Bitfields in ISR/IER/IDR/IMR */ 391 #define MACB_MFD_OFFSET 0 /* Management frame sent */ 392 #define MACB_MFD_SIZE 1 393 #define MACB_RCOMP_OFFSET 1 /* Receive complete */ 394 #define MACB_RCOMP_SIZE 1 395 #define MACB_RXUBR_OFFSET 2 /* RX used bit read */ 396 #define MACB_RXUBR_SIZE 1 397 #define MACB_TXUBR_OFFSET 3 /* TX used bit read */ 398 #define MACB_TXUBR_SIZE 1 399 #define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */ 400 #define MACB_ISR_TUND_SIZE 1 401 #define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */ 402 #define MACB_ISR_RLE_SIZE 1 403 #define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */ 404 #define MACB_TXERR_SIZE 1 405 #define MACB_RM9200_TBRE_OFFSET 6 /* EN may send new frame interrupt (RM9200) */ 406 #define MACB_RM9200_TBRE_SIZE 1 407 #define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */ 408 #define MACB_TCOMP_SIZE 1 409 #define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */ 410 #define MACB_ISR_LINK_SIZE 1 411 #define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */ 412 #define MACB_ISR_ROVR_SIZE 1 413 #define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */ 414 #define MACB_HRESP_SIZE 1 415 #define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */ 416 #define MACB_PFR_SIZE 1 417 #define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */ 418 #define MACB_PTZ_SIZE 1 419 #define MACB_WOL_OFFSET 14 /* Enable wake-on-lan interrupt */ 420 #define MACB_WOL_SIZE 1 421 #define MACB_DRQFR_OFFSET 18 /* PTP Delay Request Frame Received */ 422 #define MACB_DRQFR_SIZE 1 423 #define MACB_SFR_OFFSET 19 /* PTP Sync Frame Received */ 424 #define MACB_SFR_SIZE 1 425 #define MACB_DRQFT_OFFSET 20 /* PTP Delay Request Frame Transmitted */ 426 #define MACB_DRQFT_SIZE 1 427 #define MACB_SFT_OFFSET 21 /* PTP Sync Frame Transmitted */ 428 #define MACB_SFT_SIZE 1 429 #define MACB_PDRQFR_OFFSET 22 /* PDelay Request Frame Received */ 430 #define MACB_PDRQFR_SIZE 1 431 #define MACB_PDRSFR_OFFSET 23 /* PDelay Response Frame Received */ 432 #define MACB_PDRSFR_SIZE 1 433 #define MACB_PDRQFT_OFFSET 24 /* PDelay Request Frame Transmitted */ 434 #define MACB_PDRQFT_SIZE 1 435 #define MACB_PDRSFT_OFFSET 25 /* PDelay Response Frame Transmitted */ 436 #define MACB_PDRSFT_SIZE 1 437 #define MACB_SRI_OFFSET 26 /* TSU Seconds Register Increment */ 438 #define MACB_SRI_SIZE 1 439 #define GEM_WOL_OFFSET 28 /* Enable wake-on-lan interrupt */ 440 #define GEM_WOL_SIZE 1 441 442 /* Timer increment fields */ 443 #define MACB_TI_CNS_OFFSET 0 444 #define MACB_TI_CNS_SIZE 8 445 #define MACB_TI_ACNS_OFFSET 8 446 #define MACB_TI_ACNS_SIZE 8 447 #define MACB_TI_NIT_OFFSET 16 448 #define MACB_TI_NIT_SIZE 8 449 450 /* Bitfields in MAN */ 451 #define MACB_DATA_OFFSET 0 /* data */ 452 #define MACB_DATA_SIZE 16 453 #define MACB_CODE_OFFSET 16 /* Must be written to 10 */ 454 #define MACB_CODE_SIZE 2 455 #define MACB_REGA_OFFSET 18 /* Register address */ 456 #define MACB_REGA_SIZE 5 457 #define MACB_PHYA_OFFSET 23 /* PHY address */ 458 #define MACB_PHYA_SIZE 5 459 #define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */ 460 #define MACB_RW_SIZE 2 461 #define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */ 462 #define MACB_SOF_SIZE 2 463 464 /* Bitfields in USRIO (AVR32) */ 465 #define MACB_MII_OFFSET 0 466 #define MACB_MII_SIZE 1 467 #define MACB_EAM_OFFSET 1 468 #define MACB_EAM_SIZE 1 469 #define MACB_TX_PAUSE_OFFSET 2 470 #define MACB_TX_PAUSE_SIZE 1 471 #define MACB_TX_PAUSE_ZERO_OFFSET 3 472 #define MACB_TX_PAUSE_ZERO_SIZE 1 473 474 /* Bitfields in USRIO (AT91) */ 475 #define MACB_RMII_OFFSET 0 476 #define MACB_RMII_SIZE 1 477 #define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */ 478 #define GEM_RGMII_SIZE 1 479 #define MACB_CLKEN_OFFSET 1 480 #define MACB_CLKEN_SIZE 1 481 482 /* Bitfields in WOL */ 483 #define MACB_IP_OFFSET 0 484 #define MACB_IP_SIZE 16 485 #define MACB_MAG_OFFSET 16 486 #define MACB_MAG_SIZE 1 487 #define MACB_ARP_OFFSET 17 488 #define MACB_ARP_SIZE 1 489 #define MACB_SA1_OFFSET 18 490 #define MACB_SA1_SIZE 1 491 #define MACB_WOL_MTI_OFFSET 19 492 #define MACB_WOL_MTI_SIZE 1 493 494 /* Bitfields in MID */ 495 #define MACB_IDNUM_OFFSET 16 496 #define MACB_IDNUM_SIZE 12 497 #define MACB_REV_OFFSET 0 498 #define MACB_REV_SIZE 16 499 500 /* Bitfield in HS_MAC_CONFIG */ 501 #define GEM_HS_MAC_SPEED_OFFSET 0 502 #define GEM_HS_MAC_SPEED_SIZE 3 503 504 /* Bitfields in PCSCNTRL */ 505 #define GEM_PCSAUTONEG_OFFSET 12 506 #define GEM_PCSAUTONEG_SIZE 1 507 508 /* Bitfields in DCFG1. */ 509 #define GEM_IRQCOR_OFFSET 23 510 #define GEM_IRQCOR_SIZE 1 511 #define GEM_DBWDEF_OFFSET 25 512 #define GEM_DBWDEF_SIZE 3 513 #define GEM_NO_PCS_OFFSET 0 514 #define GEM_NO_PCS_SIZE 1 515 516 /* Bitfields in DCFG2. */ 517 #define GEM_RX_PKT_BUFF_OFFSET 20 518 #define GEM_RX_PKT_BUFF_SIZE 1 519 #define GEM_TX_PKT_BUFF_OFFSET 21 520 #define GEM_TX_PKT_BUFF_SIZE 1 521 522 #define GEM_RX_PBUF_ADDR_OFFSET 22 523 #define GEM_RX_PBUF_ADDR_SIZE 4 524 525 /* Bitfields in DCFG5. */ 526 #define GEM_TSU_OFFSET 8 527 #define GEM_TSU_SIZE 1 528 529 /* Bitfields in DCFG6. */ 530 #define GEM_PBUF_LSO_OFFSET 27 531 #define GEM_PBUF_LSO_SIZE 1 532 #define GEM_PBUF_CUTTHRU_OFFSET 25 533 #define GEM_PBUF_CUTTHRU_SIZE 1 534 #define GEM_DAW64_OFFSET 23 535 #define GEM_DAW64_SIZE 1 536 537 /* Bitfields in DCFG8. */ 538 #define GEM_T1SCR_OFFSET 24 539 #define GEM_T1SCR_SIZE 8 540 #define GEM_T2SCR_OFFSET 16 541 #define GEM_T2SCR_SIZE 8 542 #define GEM_SCR2ETH_OFFSET 8 543 #define GEM_SCR2ETH_SIZE 8 544 #define GEM_SCR2CMP_OFFSET 0 545 #define GEM_SCR2CMP_SIZE 8 546 547 /* Bitfields in DCFG10 */ 548 #define GEM_TXBD_RDBUFF_OFFSET 12 549 #define GEM_TXBD_RDBUFF_SIZE 4 550 #define GEM_RXBD_RDBUFF_OFFSET 8 551 #define GEM_RXBD_RDBUFF_SIZE 4 552 553 /* Bitfields in DCFG12. */ 554 #define GEM_HIGH_SPEED_OFFSET 26 555 #define GEM_HIGH_SPEED_SIZE 1 556 557 /* Bitfields in USX_CONTROL. */ 558 #define GEM_USX_CTRL_SPEED_OFFSET 14 559 #define GEM_USX_CTRL_SPEED_SIZE 3 560 #define GEM_SERDES_RATE_OFFSET 12 561 #define GEM_SERDES_RATE_SIZE 2 562 #define GEM_RX_SCR_BYPASS_OFFSET 9 563 #define GEM_RX_SCR_BYPASS_SIZE 1 564 #define GEM_TX_SCR_BYPASS_OFFSET 8 565 #define GEM_TX_SCR_BYPASS_SIZE 1 566 #define GEM_TX_EN_OFFSET 1 567 #define GEM_TX_EN_SIZE 1 568 #define GEM_SIGNAL_OK_OFFSET 0 569 #define GEM_SIGNAL_OK_SIZE 1 570 571 /* Bitfields in USX_STATUS. */ 572 #define GEM_USX_BLOCK_LOCK_OFFSET 0 573 #define GEM_USX_BLOCK_LOCK_SIZE 1 574 575 /* Bitfields in TISUBN */ 576 #define GEM_SUBNSINCR_OFFSET 0 577 #define GEM_SUBNSINCRL_OFFSET 24 578 #define GEM_SUBNSINCRL_SIZE 8 579 #define GEM_SUBNSINCRH_OFFSET 0 580 #define GEM_SUBNSINCRH_SIZE 16 581 #define GEM_SUBNSINCR_SIZE 24 582 583 /* Bitfields in TI */ 584 #define GEM_NSINCR_OFFSET 0 585 #define GEM_NSINCR_SIZE 8 586 587 /* Bitfields in TSH */ 588 #define GEM_TSH_OFFSET 0 /* TSU timer value (s). MSB [47:32] of seconds timer count */ 589 #define GEM_TSH_SIZE 16 590 591 /* Bitfields in TSL */ 592 #define GEM_TSL_OFFSET 0 /* TSU timer value (s). LSB [31:0] of seconds timer count */ 593 #define GEM_TSL_SIZE 32 594 595 /* Bitfields in TN */ 596 #define GEM_TN_OFFSET 0 /* TSU timer value (ns) */ 597 #define GEM_TN_SIZE 30 598 599 /* Bitfields in TXBDCTRL */ 600 #define GEM_TXTSMODE_OFFSET 4 /* TX Descriptor Timestamp Insertion mode */ 601 #define GEM_TXTSMODE_SIZE 2 602 603 /* Bitfields in RXBDCTRL */ 604 #define GEM_RXTSMODE_OFFSET 4 /* RX Descriptor Timestamp Insertion mode */ 605 #define GEM_RXTSMODE_SIZE 2 606 607 /* Bitfields in SCRT2 */ 608 #define GEM_QUEUE_OFFSET 0 /* Queue Number */ 609 #define GEM_QUEUE_SIZE 4 610 #define GEM_VLANPR_OFFSET 4 /* VLAN Priority */ 611 #define GEM_VLANPR_SIZE 3 612 #define GEM_VLANEN_OFFSET 8 /* VLAN Enable */ 613 #define GEM_VLANEN_SIZE 1 614 #define GEM_ETHT2IDX_OFFSET 9 /* Index to screener type 2 EtherType register */ 615 #define GEM_ETHT2IDX_SIZE 3 616 #define GEM_ETHTEN_OFFSET 12 /* EtherType Enable */ 617 #define GEM_ETHTEN_SIZE 1 618 #define GEM_CMPA_OFFSET 13 /* Compare A - Index to screener type 2 Compare register */ 619 #define GEM_CMPA_SIZE 5 620 #define GEM_CMPAEN_OFFSET 18 /* Compare A Enable */ 621 #define GEM_CMPAEN_SIZE 1 622 #define GEM_CMPB_OFFSET 19 /* Compare B - Index to screener type 2 Compare register */ 623 #define GEM_CMPB_SIZE 5 624 #define GEM_CMPBEN_OFFSET 24 /* Compare B Enable */ 625 #define GEM_CMPBEN_SIZE 1 626 #define GEM_CMPC_OFFSET 25 /* Compare C - Index to screener type 2 Compare register */ 627 #define GEM_CMPC_SIZE 5 628 #define GEM_CMPCEN_OFFSET 30 /* Compare C Enable */ 629 #define GEM_CMPCEN_SIZE 1 630 631 /* Bitfields in ETHT */ 632 #define GEM_ETHTCMP_OFFSET 0 /* EtherType compare value */ 633 #define GEM_ETHTCMP_SIZE 16 634 635 /* Bitfields in T2CMPW0 */ 636 #define GEM_T2CMP_OFFSET 16 /* 0xFFFF0000 compare value */ 637 #define GEM_T2CMP_SIZE 16 638 #define GEM_T2MASK_OFFSET 0 /* 0x0000FFFF compare value or mask */ 639 #define GEM_T2MASK_SIZE 16 640 641 /* Bitfields in T2CMPW1 */ 642 #define GEM_T2DISMSK_OFFSET 9 /* disable mask */ 643 #define GEM_T2DISMSK_SIZE 1 644 #define GEM_T2CMPOFST_OFFSET 7 /* compare offset */ 645 #define GEM_T2CMPOFST_SIZE 2 646 #define GEM_T2OFST_OFFSET 0 /* offset value */ 647 #define GEM_T2OFST_SIZE 7 648 649 /* Bitfields in queue pointer registers */ 650 #define MACB_QUEUE_DISABLE_OFFSET 0 /* disable queue */ 651 #define MACB_QUEUE_DISABLE_SIZE 1 652 653 /* Offset for screener type 2 compare values (T2CMPOFST). 654 * Note the offset is applied after the specified point, 655 * e.g. GEM_T2COMPOFST_ETYPE denotes the EtherType field, so an offset 656 * of 12 bytes from this would be the source IP address in an IP header 657 */ 658 #define GEM_T2COMPOFST_SOF 0 659 #define GEM_T2COMPOFST_ETYPE 1 660 #define GEM_T2COMPOFST_IPHDR 2 661 #define GEM_T2COMPOFST_TCPUDP 3 662 663 /* offset from EtherType to IP address */ 664 #define ETYPE_SRCIP_OFFSET 12 665 #define ETYPE_DSTIP_OFFSET 16 666 667 /* offset from IP header to port */ 668 #define IPHDR_SRCPORT_OFFSET 0 669 #define IPHDR_DSTPORT_OFFSET 2 670 671 /* Transmit DMA buffer descriptor Word 1 */ 672 #define GEM_DMA_TXVALID_OFFSET 23 /* timestamp has been captured in the Buffer Descriptor */ 673 #define GEM_DMA_TXVALID_SIZE 1 674 675 /* Receive DMA buffer descriptor Word 0 */ 676 #define GEM_DMA_RXVALID_OFFSET 2 /* indicates a valid timestamp in the Buffer Descriptor */ 677 #define GEM_DMA_RXVALID_SIZE 1 678 679 /* DMA buffer descriptor Word 2 (32 bit addressing) or Word 4 (64 bit addressing) */ 680 #define GEM_DMA_SECL_OFFSET 30 /* Timestamp seconds[1:0] */ 681 #define GEM_DMA_SECL_SIZE 2 682 #define GEM_DMA_NSEC_OFFSET 0 /* Timestamp nanosecs [29:0] */ 683 #define GEM_DMA_NSEC_SIZE 30 684 685 /* DMA buffer descriptor Word 3 (32 bit addressing) or Word 5 (64 bit addressing) */ 686 687 /* New hardware supports 12 bit precision of timestamp in DMA buffer descriptor. 688 * Old hardware supports only 6 bit precision but it is enough for PTP. 689 * Less accuracy is used always instead of checking hardware version. 690 */ 691 #define GEM_DMA_SECH_OFFSET 0 /* Timestamp seconds[5:2] */ 692 #define GEM_DMA_SECH_SIZE 4 693 #define GEM_DMA_SEC_WIDTH (GEM_DMA_SECH_SIZE + GEM_DMA_SECL_SIZE) 694 #define GEM_DMA_SEC_TOP (1 << GEM_DMA_SEC_WIDTH) 695 #define GEM_DMA_SEC_MASK (GEM_DMA_SEC_TOP - 1) 696 697 /* Bitfields in ADJ */ 698 #define GEM_ADDSUB_OFFSET 31 699 #define GEM_ADDSUB_SIZE 1 700 /* Constants for CLK */ 701 #define MACB_CLK_DIV8 0 702 #define MACB_CLK_DIV16 1 703 #define MACB_CLK_DIV32 2 704 #define MACB_CLK_DIV64 3 705 706 /* GEM specific constants for CLK. */ 707 #define GEM_CLK_DIV8 0 708 #define GEM_CLK_DIV16 1 709 #define GEM_CLK_DIV32 2 710 #define GEM_CLK_DIV48 3 711 #define GEM_CLK_DIV64 4 712 #define GEM_CLK_DIV96 5 713 #define GEM_CLK_DIV128 6 714 #define GEM_CLK_DIV224 7 715 716 /* Constants for MAN register */ 717 #define MACB_MAN_C22_SOF 1 718 #define MACB_MAN_C22_WRITE 1 719 #define MACB_MAN_C22_READ 2 720 #define MACB_MAN_C22_CODE 2 721 722 #define MACB_MAN_C45_SOF 0 723 #define MACB_MAN_C45_ADDR 0 724 #define MACB_MAN_C45_WRITE 1 725 #define MACB_MAN_C45_POST_READ_INCR 2 726 #define MACB_MAN_C45_READ 3 727 #define MACB_MAN_C45_CODE 2 728 729 /* Capability mask bits */ 730 #define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001 731 #define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002 732 #define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004 733 #define MACB_CAPS_NO_GIGABIT_HALF 0x00000008 734 #define MACB_CAPS_USRIO_DISABLED 0x00000010 735 #define MACB_CAPS_JUMBO 0x00000020 736 #define MACB_CAPS_GEM_HAS_PTP 0x00000040 737 #define MACB_CAPS_BD_RD_PREFETCH 0x00000080 738 #define MACB_CAPS_NEEDS_RSTONUBR 0x00000100 739 #define MACB_CAPS_MIIONRGMII 0x00000200 740 #define MACB_CAPS_NEED_TSUCLK 0x00000400 741 #define MACB_CAPS_QUEUE_DISABLE 0x00000800 742 #define MACB_CAPS_PCS 0x01000000 743 #define MACB_CAPS_HIGH_SPEED 0x02000000 744 #define MACB_CAPS_CLK_HW_CHG 0x04000000 745 #define MACB_CAPS_MACB_IS_EMAC 0x08000000 746 #define MACB_CAPS_FIFO_MODE 0x10000000 747 #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000 748 #define MACB_CAPS_SG_DISABLED 0x40000000 749 #define MACB_CAPS_MACB_IS_GEM 0x80000000 750 751 /* LSO settings */ 752 #define MACB_LSO_UFO_ENABLE 0x01 753 #define MACB_LSO_TSO_ENABLE 0x02 754 755 /* Bit manipulation macros */ 756 #define MACB_BIT(name) \ 757 (1 << MACB_##name##_OFFSET) 758 #define MACB_BF(name,value) \ 759 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ 760 << MACB_##name##_OFFSET) 761 #define MACB_BFEXT(name,value)\ 762 (((value) >> MACB_##name##_OFFSET) \ 763 & ((1 << MACB_##name##_SIZE) - 1)) 764 #define MACB_BFINS(name,value,old) \ 765 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ 766 << MACB_##name##_OFFSET)) \ 767 | MACB_BF(name,value)) 768 769 #define GEM_BIT(name) \ 770 (1 << GEM_##name##_OFFSET) 771 #define GEM_BF(name, value) \ 772 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \ 773 << GEM_##name##_OFFSET) 774 #define GEM_BFEXT(name, value)\ 775 (((value) >> GEM_##name##_OFFSET) \ 776 & ((1 << GEM_##name##_SIZE) - 1)) 777 #define GEM_BFINS(name, value, old) \ 778 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \ 779 << GEM_##name##_OFFSET)) \ 780 | GEM_BF(name, value)) 781 782 /* Register access macros */ 783 #define macb_readl(port, reg) (port)->macb_reg_readl((port), MACB_##reg) 784 #define macb_writel(port, reg, value) (port)->macb_reg_writel((port), MACB_##reg, (value)) 785 #define gem_readl(port, reg) (port)->macb_reg_readl((port), GEM_##reg) 786 #define gem_writel(port, reg, value) (port)->macb_reg_writel((port), GEM_##reg, (value)) 787 #define queue_readl(queue, reg) (queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg) 788 #define queue_writel(queue, reg, value) (queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (value)) 789 #define gem_readl_n(port, reg, idx) (port)->macb_reg_readl((port), GEM_##reg + idx * 4) 790 #define gem_writel_n(port, reg, idx, value) (port)->macb_reg_writel((port), GEM_##reg + idx * 4, (value)) 791 792 /* Conditional GEM/MACB macros. These perform the operation to the correct 793 * register dependent on whether the device is a GEM or a MACB. For registers 794 * and bitfields that are common across both devices, use macb_{read,write}l 795 * to avoid the cost of the conditional. 796 */ 797 #define macb_or_gem_writel(__bp, __reg, __value) \ 798 ({ \ 799 if (macb_is_gem((__bp))) \ 800 gem_writel((__bp), __reg, __value); \ 801 else \ 802 macb_writel((__bp), __reg, __value); \ 803 }) 804 805 #define macb_or_gem_readl(__bp, __reg) \ 806 ({ \ 807 u32 __v; \ 808 if (macb_is_gem((__bp))) \ 809 __v = gem_readl((__bp), __reg); \ 810 else \ 811 __v = macb_readl((__bp), __reg); \ 812 __v; \ 813 }) 814 815 #define MACB_READ_NSR(bp) macb_readl(bp, NSR) 816 817 /* struct macb_dma_desc - Hardware DMA descriptor 818 * @addr: DMA address of data buffer 819 * @ctrl: Control and status bits 820 */ 821 struct macb_dma_desc { 822 u32 addr; 823 u32 ctrl; 824 }; 825 826 #ifdef MACB_EXT_DESC 827 #define HW_DMA_CAP_32B 0 828 #define HW_DMA_CAP_64B (1 << 0) 829 #define HW_DMA_CAP_PTP (1 << 1) 830 #define HW_DMA_CAP_64B_PTP (HW_DMA_CAP_64B | HW_DMA_CAP_PTP) 831 832 struct macb_dma_desc_64 { 833 u32 addrh; 834 u32 resvd; 835 }; 836 837 struct macb_dma_desc_ptp { 838 u32 ts_1; 839 u32 ts_2; 840 }; 841 #endif 842 843 /* DMA descriptor bitfields */ 844 #define MACB_RX_USED_OFFSET 0 845 #define MACB_RX_USED_SIZE 1 846 #define MACB_RX_WRAP_OFFSET 1 847 #define MACB_RX_WRAP_SIZE 1 848 #define MACB_RX_WADDR_OFFSET 2 849 #define MACB_RX_WADDR_SIZE 30 850 851 #define MACB_RX_FRMLEN_OFFSET 0 852 #define MACB_RX_FRMLEN_SIZE 12 853 #define MACB_RX_OFFSET_OFFSET 12 854 #define MACB_RX_OFFSET_SIZE 2 855 #define MACB_RX_SOF_OFFSET 14 856 #define MACB_RX_SOF_SIZE 1 857 #define MACB_RX_EOF_OFFSET 15 858 #define MACB_RX_EOF_SIZE 1 859 #define MACB_RX_CFI_OFFSET 16 860 #define MACB_RX_CFI_SIZE 1 861 #define MACB_RX_VLAN_PRI_OFFSET 17 862 #define MACB_RX_VLAN_PRI_SIZE 3 863 #define MACB_RX_PRI_TAG_OFFSET 20 864 #define MACB_RX_PRI_TAG_SIZE 1 865 #define MACB_RX_VLAN_TAG_OFFSET 21 866 #define MACB_RX_VLAN_TAG_SIZE 1 867 #define MACB_RX_TYPEID_MATCH_OFFSET 22 868 #define MACB_RX_TYPEID_MATCH_SIZE 1 869 #define MACB_RX_SA4_MATCH_OFFSET 23 870 #define MACB_RX_SA4_MATCH_SIZE 1 871 #define MACB_RX_SA3_MATCH_OFFSET 24 872 #define MACB_RX_SA3_MATCH_SIZE 1 873 #define MACB_RX_SA2_MATCH_OFFSET 25 874 #define MACB_RX_SA2_MATCH_SIZE 1 875 #define MACB_RX_SA1_MATCH_OFFSET 26 876 #define MACB_RX_SA1_MATCH_SIZE 1 877 #define MACB_RX_EXT_MATCH_OFFSET 28 878 #define MACB_RX_EXT_MATCH_SIZE 1 879 #define MACB_RX_UHASH_MATCH_OFFSET 29 880 #define MACB_RX_UHASH_MATCH_SIZE 1 881 #define MACB_RX_MHASH_MATCH_OFFSET 30 882 #define MACB_RX_MHASH_MATCH_SIZE 1 883 #define MACB_RX_BROADCAST_OFFSET 31 884 #define MACB_RX_BROADCAST_SIZE 1 885 886 #define MACB_RX_FRMLEN_MASK 0xFFF 887 #define MACB_RX_JFRMLEN_MASK 0x3FFF 888 889 /* RX checksum offload disabled: bit 24 clear in NCFGR */ 890 #define GEM_RX_TYPEID_MATCH_OFFSET 22 891 #define GEM_RX_TYPEID_MATCH_SIZE 2 892 893 /* RX checksum offload enabled: bit 24 set in NCFGR */ 894 #define GEM_RX_CSUM_OFFSET 22 895 #define GEM_RX_CSUM_SIZE 2 896 897 #define MACB_TX_FRMLEN_OFFSET 0 898 #define MACB_TX_FRMLEN_SIZE 11 899 #define MACB_TX_LAST_OFFSET 15 900 #define MACB_TX_LAST_SIZE 1 901 #define MACB_TX_NOCRC_OFFSET 16 902 #define MACB_TX_NOCRC_SIZE 1 903 #define MACB_MSS_MFS_OFFSET 16 904 #define MACB_MSS_MFS_SIZE 14 905 #define MACB_TX_LSO_OFFSET 17 906 #define MACB_TX_LSO_SIZE 2 907 #define MACB_TX_TCP_SEQ_SRC_OFFSET 19 908 #define MACB_TX_TCP_SEQ_SRC_SIZE 1 909 #define MACB_TX_BUF_EXHAUSTED_OFFSET 27 910 #define MACB_TX_BUF_EXHAUSTED_SIZE 1 911 #define MACB_TX_UNDERRUN_OFFSET 28 912 #define MACB_TX_UNDERRUN_SIZE 1 913 #define MACB_TX_ERROR_OFFSET 29 914 #define MACB_TX_ERROR_SIZE 1 915 #define MACB_TX_WRAP_OFFSET 30 916 #define MACB_TX_WRAP_SIZE 1 917 #define MACB_TX_USED_OFFSET 31 918 #define MACB_TX_USED_SIZE 1 919 920 #define GEM_TX_FRMLEN_OFFSET 0 921 #define GEM_TX_FRMLEN_SIZE 14 922 923 /* Buffer descriptor constants */ 924 #define GEM_RX_CSUM_NONE 0 925 #define GEM_RX_CSUM_IP_ONLY 1 926 #define GEM_RX_CSUM_IP_TCP 2 927 #define GEM_RX_CSUM_IP_UDP 3 928 929 /* limit RX checksum offload to TCP and UDP packets */ 930 #define GEM_RX_CSUM_CHECKED_MASK 2 931 932 /* Scaled PPM fraction */ 933 #define PPM_FRACTION 16 934 935 /* struct macb_tx_skb - data about an skb which is being transmitted 936 * @skb: skb currently being transmitted, only set for the last buffer 937 * of the frame 938 * @mapping: DMA address of the skb's fragment buffer 939 * @size: size of the DMA mapped buffer 940 * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(), 941 * false when buffer was mapped with dma_map_single() 942 */ 943 struct macb_tx_skb { 944 struct sk_buff *skb; 945 dma_addr_t mapping; 946 size_t size; 947 bool mapped_as_page; 948 }; 949 950 /* Hardware-collected statistics. Used when updating the network 951 * device stats by a periodic timer. 952 */ 953 struct macb_stats { 954 u32 rx_pause_frames; 955 u32 tx_ok; 956 u32 tx_single_cols; 957 u32 tx_multiple_cols; 958 u32 rx_ok; 959 u32 rx_fcs_errors; 960 u32 rx_align_errors; 961 u32 tx_deferred; 962 u32 tx_late_cols; 963 u32 tx_excessive_cols; 964 u32 tx_underruns; 965 u32 tx_carrier_errors; 966 u32 rx_resource_errors; 967 u32 rx_overruns; 968 u32 rx_symbol_errors; 969 u32 rx_oversize_pkts; 970 u32 rx_jabbers; 971 u32 rx_undersize_pkts; 972 u32 sqe_test_errors; 973 u32 rx_length_mismatch; 974 u32 tx_pause_frames; 975 }; 976 977 struct gem_stats { 978 u32 tx_octets_31_0; 979 u32 tx_octets_47_32; 980 u32 tx_frames; 981 u32 tx_broadcast_frames; 982 u32 tx_multicast_frames; 983 u32 tx_pause_frames; 984 u32 tx_64_byte_frames; 985 u32 tx_65_127_byte_frames; 986 u32 tx_128_255_byte_frames; 987 u32 tx_256_511_byte_frames; 988 u32 tx_512_1023_byte_frames; 989 u32 tx_1024_1518_byte_frames; 990 u32 tx_greater_than_1518_byte_frames; 991 u32 tx_underrun; 992 u32 tx_single_collision_frames; 993 u32 tx_multiple_collision_frames; 994 u32 tx_excessive_collisions; 995 u32 tx_late_collisions; 996 u32 tx_deferred_frames; 997 u32 tx_carrier_sense_errors; 998 u32 rx_octets_31_0; 999 u32 rx_octets_47_32; 1000 u32 rx_frames; 1001 u32 rx_broadcast_frames; 1002 u32 rx_multicast_frames; 1003 u32 rx_pause_frames; 1004 u32 rx_64_byte_frames; 1005 u32 rx_65_127_byte_frames; 1006 u32 rx_128_255_byte_frames; 1007 u32 rx_256_511_byte_frames; 1008 u32 rx_512_1023_byte_frames; 1009 u32 rx_1024_1518_byte_frames; 1010 u32 rx_greater_than_1518_byte_frames; 1011 u32 rx_undersized_frames; 1012 u32 rx_oversize_frames; 1013 u32 rx_jabbers; 1014 u32 rx_frame_check_sequence_errors; 1015 u32 rx_length_field_frame_errors; 1016 u32 rx_symbol_errors; 1017 u32 rx_alignment_errors; 1018 u32 rx_resource_errors; 1019 u32 rx_overruns; 1020 u32 rx_ip_header_checksum_errors; 1021 u32 rx_tcp_checksum_errors; 1022 u32 rx_udp_checksum_errors; 1023 }; 1024 1025 /* Describes the name and offset of an individual statistic register, as 1026 * returned by `ethtool -S`. Also describes which net_device_stats statistics 1027 * this register should contribute to. 1028 */ 1029 struct gem_statistic { 1030 char stat_string[ETH_GSTRING_LEN]; 1031 int offset; 1032 u32 stat_bits; 1033 }; 1034 1035 /* Bitfield defs for net_device_stat statistics */ 1036 #define GEM_NDS_RXERR_OFFSET 0 1037 #define GEM_NDS_RXLENERR_OFFSET 1 1038 #define GEM_NDS_RXOVERERR_OFFSET 2 1039 #define GEM_NDS_RXCRCERR_OFFSET 3 1040 #define GEM_NDS_RXFRAMEERR_OFFSET 4 1041 #define GEM_NDS_RXFIFOERR_OFFSET 5 1042 #define GEM_NDS_TXERR_OFFSET 6 1043 #define GEM_NDS_TXABORTEDERR_OFFSET 7 1044 #define GEM_NDS_TXCARRIERERR_OFFSET 8 1045 #define GEM_NDS_TXFIFOERR_OFFSET 9 1046 #define GEM_NDS_COLLISIONS_OFFSET 10 1047 1048 #define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0) 1049 #define GEM_STAT_TITLE_BITS(name, title, bits) { \ 1050 .stat_string = title, \ 1051 .offset = GEM_##name, \ 1052 .stat_bits = bits \ 1053 } 1054 1055 /* list of gem statistic registers. The names MUST match the 1056 * corresponding GEM_* definitions. 1057 */ 1058 static const struct gem_statistic gem_statistics[] = { 1059 GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */ 1060 GEM_STAT_TITLE(TXCNT, "tx_frames"), 1061 GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"), 1062 GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"), 1063 GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"), 1064 GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"), 1065 GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"), 1066 GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"), 1067 GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"), 1068 GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"), 1069 GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"), 1070 GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"), 1071 GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun", 1072 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)), 1073 GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames", 1074 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), 1075 GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames", 1076 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), 1077 GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions", 1078 GEM_BIT(NDS_TXERR)| 1079 GEM_BIT(NDS_TXABORTEDERR)| 1080 GEM_BIT(NDS_COLLISIONS)), 1081 GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions", 1082 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), 1083 GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"), 1084 GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors", 1085 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), 1086 GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */ 1087 GEM_STAT_TITLE(RXCNT, "rx_frames"), 1088 GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"), 1089 GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"), 1090 GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"), 1091 GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"), 1092 GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"), 1093 GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"), 1094 GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"), 1095 GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"), 1096 GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"), 1097 GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"), 1098 GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames", 1099 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)), 1100 GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames", 1101 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)), 1102 GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers", 1103 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)), 1104 GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors", 1105 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)), 1106 GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors", 1107 GEM_BIT(NDS_RXERR)), 1108 GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors", 1109 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)), 1110 GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors", 1111 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)), 1112 GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors", 1113 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)), 1114 GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns", 1115 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)), 1116 GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors", 1117 GEM_BIT(NDS_RXERR)), 1118 GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors", 1119 GEM_BIT(NDS_RXERR)), 1120 GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors", 1121 GEM_BIT(NDS_RXERR)), 1122 }; 1123 1124 #define GEM_STATS_LEN ARRAY_SIZE(gem_statistics) 1125 1126 #define QUEUE_STAT_TITLE(title) { \ 1127 .stat_string = title, \ 1128 } 1129 1130 /* per queue statistics, each should be unsigned long type */ 1131 struct queue_stats { 1132 union { 1133 unsigned long first; 1134 unsigned long rx_packets; 1135 }; 1136 unsigned long rx_bytes; 1137 unsigned long rx_dropped; 1138 unsigned long tx_packets; 1139 unsigned long tx_bytes; 1140 unsigned long tx_dropped; 1141 }; 1142 1143 static const struct gem_statistic queue_statistics[] = { 1144 QUEUE_STAT_TITLE("rx_packets"), 1145 QUEUE_STAT_TITLE("rx_bytes"), 1146 QUEUE_STAT_TITLE("rx_dropped"), 1147 QUEUE_STAT_TITLE("tx_packets"), 1148 QUEUE_STAT_TITLE("tx_bytes"), 1149 QUEUE_STAT_TITLE("tx_dropped"), 1150 }; 1151 1152 #define QUEUE_STATS_LEN ARRAY_SIZE(queue_statistics) 1153 1154 struct macb; 1155 struct macb_queue; 1156 1157 struct macb_or_gem_ops { 1158 int (*mog_alloc_rx_buffers)(struct macb *bp); 1159 void (*mog_free_rx_buffers)(struct macb *bp); 1160 void (*mog_init_rings)(struct macb *bp); 1161 int (*mog_rx)(struct macb_queue *queue, struct napi_struct *napi, 1162 int budget); 1163 }; 1164 1165 /* MACB-PTP interface: adapt to platform needs. */ 1166 struct macb_ptp_info { 1167 void (*ptp_init)(struct net_device *ndev); 1168 void (*ptp_remove)(struct net_device *ndev); 1169 s32 (*get_ptp_max_adj)(void); 1170 unsigned int (*get_tsu_rate)(struct macb *bp); 1171 int (*get_ts_info)(struct net_device *dev, 1172 struct kernel_ethtool_ts_info *info); 1173 int (*get_hwtst)(struct net_device *netdev, 1174 struct kernel_hwtstamp_config *tstamp_config); 1175 int (*set_hwtst)(struct net_device *netdev, 1176 struct kernel_hwtstamp_config *tstamp_config, 1177 struct netlink_ext_ack *extack); 1178 }; 1179 1180 struct macb_pm_data { 1181 u32 scrt2; 1182 u32 usrio; 1183 }; 1184 1185 struct macb_usrio_config { 1186 u32 mii; 1187 u32 rmii; 1188 u32 rgmii; 1189 u32 refclk; 1190 u32 hdfctlen; 1191 }; 1192 1193 struct macb_config { 1194 u32 caps; 1195 unsigned int dma_burst_length; 1196 int (*clk_init)(struct platform_device *pdev, struct clk **pclk, 1197 struct clk **hclk, struct clk **tx_clk, 1198 struct clk **rx_clk, struct clk **tsu_clk); 1199 int (*init)(struct platform_device *pdev); 1200 unsigned int max_tx_length; 1201 int jumbo_max_len; 1202 const struct macb_usrio_config *usrio; 1203 }; 1204 1205 struct tsu_incr { 1206 u32 sub_ns; 1207 u32 ns; 1208 }; 1209 1210 struct macb_queue { 1211 struct macb *bp; 1212 int irq; 1213 1214 unsigned int ISR; 1215 unsigned int IER; 1216 unsigned int IDR; 1217 unsigned int IMR; 1218 unsigned int TBQP; 1219 unsigned int TBQPH; 1220 unsigned int RBQS; 1221 unsigned int RBQP; 1222 unsigned int RBQPH; 1223 1224 /* Lock to protect tx_head and tx_tail */ 1225 spinlock_t tx_ptr_lock; 1226 unsigned int tx_head, tx_tail; 1227 struct macb_dma_desc *tx_ring; 1228 struct macb_tx_skb *tx_skb; 1229 dma_addr_t tx_ring_dma; 1230 struct work_struct tx_error_task; 1231 bool txubr_pending; 1232 struct napi_struct napi_tx; 1233 1234 dma_addr_t rx_ring_dma; 1235 dma_addr_t rx_buffers_dma; 1236 unsigned int rx_tail; 1237 unsigned int rx_prepared_head; 1238 struct macb_dma_desc *rx_ring; 1239 struct sk_buff **rx_skbuff; 1240 void *rx_buffers; 1241 struct napi_struct napi_rx; 1242 struct queue_stats stats; 1243 }; 1244 1245 struct ethtool_rx_fs_item { 1246 struct ethtool_rx_flow_spec fs; 1247 struct list_head list; 1248 }; 1249 1250 struct ethtool_rx_fs_list { 1251 struct list_head list; 1252 unsigned int count; 1253 }; 1254 1255 struct macb { 1256 void __iomem *regs; 1257 bool native_io; 1258 1259 /* hardware IO accessors */ 1260 u32 (*macb_reg_readl)(struct macb *bp, int offset); 1261 void (*macb_reg_writel)(struct macb *bp, int offset, u32 value); 1262 1263 struct macb_dma_desc *rx_ring_tieoff; 1264 dma_addr_t rx_ring_tieoff_dma; 1265 size_t rx_buffer_size; 1266 1267 unsigned int rx_ring_size; 1268 unsigned int tx_ring_size; 1269 1270 unsigned int num_queues; 1271 unsigned int queue_mask; 1272 struct macb_queue queues[MACB_MAX_QUEUES]; 1273 1274 spinlock_t lock; 1275 struct platform_device *pdev; 1276 struct clk *pclk; 1277 struct clk *hclk; 1278 struct clk *tx_clk; 1279 struct clk *rx_clk; 1280 struct clk *tsu_clk; 1281 struct net_device *dev; 1282 union { 1283 struct macb_stats macb; 1284 struct gem_stats gem; 1285 } hw_stats; 1286 1287 struct macb_or_gem_ops macbgem_ops; 1288 1289 struct mii_bus *mii_bus; 1290 struct phylink *phylink; 1291 struct phylink_config phylink_config; 1292 struct phylink_pcs phylink_usx_pcs; 1293 struct phylink_pcs phylink_sgmii_pcs; 1294 1295 u32 caps; 1296 unsigned int dma_burst_length; 1297 1298 phy_interface_t phy_interface; 1299 1300 /* AT91RM9200 transmit queue (1 on wire + 1 queued) */ 1301 struct macb_tx_skb rm9200_txq[2]; 1302 unsigned int max_tx_length; 1303 1304 u64 ethtool_stats[GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES]; 1305 1306 unsigned int rx_frm_len_mask; 1307 unsigned int jumbo_max_len; 1308 1309 u32 wol; 1310 u32 wolopts; 1311 1312 /* holds value of rx watermark value for pbuf_rxcutthru register */ 1313 u32 rx_watermark; 1314 1315 struct macb_ptp_info *ptp_info; /* macb-ptp interface */ 1316 1317 struct phy *sgmii_phy; /* for ZynqMP SGMII mode */ 1318 1319 #ifdef MACB_EXT_DESC 1320 uint8_t hw_dma_cap; 1321 #endif 1322 spinlock_t tsu_clk_lock; /* gem tsu clock locking */ 1323 unsigned int tsu_rate; 1324 struct ptp_clock *ptp_clock; 1325 struct ptp_clock_info ptp_clock_info; 1326 struct tsu_incr tsu_incr; 1327 struct kernel_hwtstamp_config tstamp_config; 1328 1329 /* RX queue filer rule set*/ 1330 struct ethtool_rx_fs_list rx_fs_list; 1331 spinlock_t rx_fs_lock; 1332 unsigned int max_tuples; 1333 1334 struct work_struct hresp_err_bh_work; 1335 1336 int rx_bd_rd_prefetch; 1337 int tx_bd_rd_prefetch; 1338 1339 u32 rx_intr_mask; 1340 1341 struct macb_pm_data pm_data; 1342 const struct macb_usrio_config *usrio; 1343 }; 1344 1345 #ifdef CONFIG_MACB_USE_HWSTAMP 1346 #define GEM_TSEC_SIZE (GEM_TSH_SIZE + GEM_TSL_SIZE) 1347 #define TSU_SEC_MAX_VAL (((u64)1 << GEM_TSEC_SIZE) - 1) 1348 #define TSU_NSEC_MAX_VAL ((1 << GEM_TN_SIZE) - 1) 1349 1350 enum macb_bd_control { 1351 TSTAMP_DISABLED, 1352 TSTAMP_FRAME_PTP_EVENT_ONLY, 1353 TSTAMP_ALL_PTP_FRAMES, 1354 TSTAMP_ALL_FRAMES, 1355 }; 1356 1357 void gem_ptp_init(struct net_device *ndev); 1358 void gem_ptp_remove(struct net_device *ndev); 1359 void gem_ptp_txstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc); 1360 void gem_ptp_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc); 1361 static inline void gem_ptp_do_txstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) 1362 { 1363 if (bp->tstamp_config.tx_type == TSTAMP_DISABLED) 1364 return; 1365 1366 gem_ptp_txstamp(bp, skb, desc); 1367 } 1368 1369 static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) 1370 { 1371 if (bp->tstamp_config.rx_filter == TSTAMP_DISABLED) 1372 return; 1373 1374 gem_ptp_rxstamp(bp, skb, desc); 1375 } 1376 1377 int gem_get_hwtst(struct net_device *dev, 1378 struct kernel_hwtstamp_config *tstamp_config); 1379 int gem_set_hwtst(struct net_device *dev, 1380 struct kernel_hwtstamp_config *tstamp_config, 1381 struct netlink_ext_ack *extack); 1382 #else 1383 static inline void gem_ptp_init(struct net_device *ndev) { } 1384 static inline void gem_ptp_remove(struct net_device *ndev) { } 1385 1386 static inline void gem_ptp_do_txstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) { } 1387 static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) { } 1388 #endif 1389 1390 static inline bool macb_is_gem(struct macb *bp) 1391 { 1392 return !!(bp->caps & MACB_CAPS_MACB_IS_GEM); 1393 } 1394 1395 static inline bool gem_has_ptp(struct macb *bp) 1396 { 1397 return IS_ENABLED(CONFIG_MACB_USE_HWSTAMP) && (bp->caps & MACB_CAPS_GEM_HAS_PTP); 1398 } 1399 1400 /** 1401 * struct macb_platform_data - platform data for MACB Ethernet used for PCI registration 1402 * @pclk: platform clock 1403 * @hclk: AHB clock 1404 */ 1405 struct macb_platform_data { 1406 struct clk *pclk; 1407 struct clk *hclk; 1408 }; 1409 1410 #endif /* _MACB_H */ 1411