19f2f381fSJeff Kirsher /* 29f2f381fSJeff Kirsher * Atmel MACB Ethernet Controller driver 39f2f381fSJeff Kirsher * 49f2f381fSJeff Kirsher * Copyright (C) 2004-2006 Atmel Corporation 59f2f381fSJeff Kirsher * 69f2f381fSJeff Kirsher * This program is free software; you can redistribute it and/or modify 79f2f381fSJeff Kirsher * it under the terms of the GNU General Public License version 2 as 89f2f381fSJeff Kirsher * published by the Free Software Foundation. 99f2f381fSJeff Kirsher */ 109f2f381fSJeff Kirsher #ifndef _MACB_H 119f2f381fSJeff Kirsher #define _MACB_H 129f2f381fSJeff Kirsher 13fc182b85SRussell King #include <linux/phy.h> 14ab91f0a9SRafal Ozieblo #include <linux/ptp_clock_kernel.h> 15ab91f0a9SRafal Ozieblo #include <linux/net_tstamp.h> 16fc182b85SRussell King 177b429614SRafal Ozieblo #if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) || defined(CONFIG_MACB_USE_HWSTAMP) 187b429614SRafal Ozieblo #define MACB_EXT_DESC 197b429614SRafal Ozieblo #endif 207b429614SRafal Ozieblo 21d1d1b53dSNicolas Ferre #define MACB_GREGS_NBR 16 227c39994fSNicolas Ferre #define MACB_GREGS_VERSION 2 2302c958ddSCyrille Pitchen #define MACB_MAX_QUEUES 8 24d1d1b53dSNicolas Ferre 259f2f381fSJeff Kirsher /* MACB register offsets */ 265c2fa0f6SXander Huff #define MACB_NCR 0x0000 /* Network Control */ 275c2fa0f6SXander Huff #define MACB_NCFGR 0x0004 /* Network Config */ 285c2fa0f6SXander Huff #define MACB_NSR 0x0008 /* Network Status */ 291fd3ca4eSJoachim Eastwood #define MACB_TAR 0x000c /* AT91RM9200 only */ 301fd3ca4eSJoachim Eastwood #define MACB_TCR 0x0010 /* AT91RM9200 only */ 315c2fa0f6SXander Huff #define MACB_TSR 0x0014 /* Transmit Status */ 325c2fa0f6SXander Huff #define MACB_RBQP 0x0018 /* RX Q Base Address */ 335c2fa0f6SXander Huff #define MACB_TBQP 0x001c /* TX Q Base Address */ 345c2fa0f6SXander Huff #define MACB_RSR 0x0020 /* Receive Status */ 355c2fa0f6SXander Huff #define MACB_ISR 0x0024 /* Interrupt Status */ 365c2fa0f6SXander Huff #define MACB_IER 0x0028 /* Interrupt Enable */ 375c2fa0f6SXander Huff #define MACB_IDR 0x002c /* Interrupt Disable */ 385c2fa0f6SXander Huff #define MACB_IMR 0x0030 /* Interrupt Mask */ 395c2fa0f6SXander Huff #define MACB_MAN 0x0034 /* PHY Maintenance */ 409f2f381fSJeff Kirsher #define MACB_PTR 0x0038 419f2f381fSJeff Kirsher #define MACB_PFR 0x003c 429f2f381fSJeff Kirsher #define MACB_FTO 0x0040 439f2f381fSJeff Kirsher #define MACB_SCF 0x0044 449f2f381fSJeff Kirsher #define MACB_MCF 0x0048 459f2f381fSJeff Kirsher #define MACB_FRO 0x004c 469f2f381fSJeff Kirsher #define MACB_FCSE 0x0050 479f2f381fSJeff Kirsher #define MACB_ALE 0x0054 489f2f381fSJeff Kirsher #define MACB_DTF 0x0058 499f2f381fSJeff Kirsher #define MACB_LCOL 0x005c 509f2f381fSJeff Kirsher #define MACB_EXCOL 0x0060 519f2f381fSJeff Kirsher #define MACB_TUND 0x0064 529f2f381fSJeff Kirsher #define MACB_CSE 0x0068 539f2f381fSJeff Kirsher #define MACB_RRE 0x006c 549f2f381fSJeff Kirsher #define MACB_ROVR 0x0070 559f2f381fSJeff Kirsher #define MACB_RSE 0x0074 569f2f381fSJeff Kirsher #define MACB_ELE 0x0078 579f2f381fSJeff Kirsher #define MACB_RJA 0x007c 589f2f381fSJeff Kirsher #define MACB_USF 0x0080 599f2f381fSJeff Kirsher #define MACB_STE 0x0084 609f2f381fSJeff Kirsher #define MACB_RLE 0x0088 619f2f381fSJeff Kirsher #define MACB_TPF 0x008c 629f2f381fSJeff Kirsher #define MACB_HRB 0x0090 639f2f381fSJeff Kirsher #define MACB_HRT 0x0094 649f2f381fSJeff Kirsher #define MACB_SA1B 0x0098 659f2f381fSJeff Kirsher #define MACB_SA1T 0x009c 669f2f381fSJeff Kirsher #define MACB_SA2B 0x00a0 679f2f381fSJeff Kirsher #define MACB_SA2T 0x00a4 689f2f381fSJeff Kirsher #define MACB_SA3B 0x00a8 699f2f381fSJeff Kirsher #define MACB_SA3T 0x00ac 709f2f381fSJeff Kirsher #define MACB_SA4B 0x00b0 719f2f381fSJeff Kirsher #define MACB_SA4T 0x00b4 729f2f381fSJeff Kirsher #define MACB_TID 0x00b8 739f2f381fSJeff Kirsher #define MACB_TPQ 0x00bc 749f2f381fSJeff Kirsher #define MACB_USRIO 0x00c0 759f2f381fSJeff Kirsher #define MACB_WOL 0x00c4 76f75ba50bSJamie Iles #define MACB_MID 0x00fc 77fff8019aSHarini Katakam #define MACB_TBQPH 0x04C8 78fff8019aSHarini Katakam #define MACB_RBQPH 0x04D4 79f75ba50bSJamie Iles 80f75ba50bSJamie Iles /* GEM register offsets. */ 815c2fa0f6SXander Huff #define GEM_NCFGR 0x0004 /* Network Config */ 825c2fa0f6SXander Huff #define GEM_USRIO 0x000c /* User IO */ 835c2fa0f6SXander Huff #define GEM_DMACFG 0x0010 /* DMA Configuration */ 8498b5a0f4SHarini Katakam #define GEM_JML 0x0048 /* Jumbo Max Length */ 855c2fa0f6SXander Huff #define GEM_HRB 0x0080 /* Hash Bottom */ 865c2fa0f6SXander Huff #define GEM_HRT 0x0084 /* Hash Top */ 875c2fa0f6SXander Huff #define GEM_SA1B 0x0088 /* Specific1 Bottom */ 885c2fa0f6SXander Huff #define GEM_SA1T 0x008C /* Specific1 Top */ 895c2fa0f6SXander Huff #define GEM_SA2B 0x0090 /* Specific2 Bottom */ 905c2fa0f6SXander Huff #define GEM_SA2T 0x0094 /* Specific2 Top */ 915c2fa0f6SXander Huff #define GEM_SA3B 0x0098 /* Specific3 Bottom */ 925c2fa0f6SXander Huff #define GEM_SA3T 0x009C /* Specific3 Top */ 935c2fa0f6SXander Huff #define GEM_SA4B 0x00A0 /* Specific4 Bottom */ 945c2fa0f6SXander Huff #define GEM_SA4T 0x00A4 /* Specific4 Top */ 95ab91f0a9SRafal Ozieblo #define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */ 96ab91f0a9SRafal Ozieblo #define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */ 97ab91f0a9SRafal Ozieblo #define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */ 98ab91f0a9SRafal Ozieblo #define GEM_PEFRSH 0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */ 995c2fa0f6SXander Huff #define GEM_OTX 0x0100 /* Octets transmitted */ 1006f79eed8SXander Huff #define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */ 1016f79eed8SXander Huff #define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */ 1026f79eed8SXander Huff #define GEM_TXCNT 0x0108 /* Frames Transmitted counter */ 1036f79eed8SXander Huff #define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */ 1046f79eed8SXander Huff #define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */ 1056f79eed8SXander Huff #define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */ 1066f79eed8SXander Huff #define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */ 1076f79eed8SXander Huff #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */ 1086f79eed8SXander Huff #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */ 1096f79eed8SXander Huff #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */ 1106f79eed8SXander Huff #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */ 1116f79eed8SXander Huff #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */ 1126f79eed8SXander Huff #define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */ 1136f79eed8SXander Huff #define GEM_TXURUNCNT 0x0134 /* TX under run error counter */ 1146f79eed8SXander Huff #define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */ 1156f79eed8SXander Huff #define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */ 1166f79eed8SXander Huff #define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */ 1176f79eed8SXander Huff #define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */ 1186f79eed8SXander Huff #define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */ 1196f79eed8SXander Huff #define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */ 1203ff13f1cSXander Huff #define GEM_ORX 0x0150 /* Octets received */ 1216f79eed8SXander Huff #define GEM_OCTRXL 0x0150 /* Octets received [31:0] */ 1226f79eed8SXander Huff #define GEM_OCTRXH 0x0154 /* Octets received [47:32] */ 1236f79eed8SXander Huff #define GEM_RXCNT 0x0158 /* Frames Received Counter */ 1246f79eed8SXander Huff #define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */ 1256f79eed8SXander Huff #define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */ 1266f79eed8SXander Huff #define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */ 1276f79eed8SXander Huff #define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */ 1286f79eed8SXander Huff #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */ 1296f79eed8SXander Huff #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */ 1306f79eed8SXander Huff #define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */ 1316f79eed8SXander Huff #define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */ 1326f79eed8SXander Huff #define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */ 1336f79eed8SXander Huff #define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */ 1346f79eed8SXander Huff #define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */ 1356f79eed8SXander Huff #define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */ 1366f79eed8SXander Huff #define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */ 1376f79eed8SXander Huff #define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */ 1386f79eed8SXander Huff #define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */ 1396f79eed8SXander Huff #define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */ 1406f79eed8SXander Huff #define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */ 1416f79eed8SXander Huff #define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */ 1426f79eed8SXander Huff #define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */ 1436f79eed8SXander Huff #define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */ 1446f79eed8SXander Huff #define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */ 1456f79eed8SXander Huff #define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */ 146c2594d80SAndrei.Pistirica@microchip.com #define GEM_TISUBN 0x01bc /* 1588 Timer Increment Sub-ns */ 147c2594d80SAndrei.Pistirica@microchip.com #define GEM_TSH 0x01c0 /* 1588 Timer Seconds High */ 148c2594d80SAndrei.Pistirica@microchip.com #define GEM_TSL 0x01d0 /* 1588 Timer Seconds Low */ 149c2594d80SAndrei.Pistirica@microchip.com #define GEM_TN 0x01d4 /* 1588 Timer Nanoseconds */ 150c2594d80SAndrei.Pistirica@microchip.com #define GEM_TA 0x01d8 /* 1588 Timer Adjust */ 151c2594d80SAndrei.Pistirica@microchip.com #define GEM_TI 0x01dc /* 1588 Timer Increment */ 152c2594d80SAndrei.Pistirica@microchip.com #define GEM_EFTSL 0x01e0 /* PTP Event Frame Tx Seconds Low */ 153c2594d80SAndrei.Pistirica@microchip.com #define GEM_EFTN 0x01e4 /* PTP Event Frame Tx Nanoseconds */ 154c2594d80SAndrei.Pistirica@microchip.com #define GEM_EFRSL 0x01e8 /* PTP Event Frame Rx Seconds Low */ 155c2594d80SAndrei.Pistirica@microchip.com #define GEM_EFRN 0x01ec /* PTP Event Frame Rx Nanoseconds */ 156c2594d80SAndrei.Pistirica@microchip.com #define GEM_PEFTSL 0x01f0 /* PTP Peer Event Frame Tx Secs Low */ 157c2594d80SAndrei.Pistirica@microchip.com #define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */ 158c2594d80SAndrei.Pistirica@microchip.com #define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */ 159c2594d80SAndrei.Pistirica@microchip.com #define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */ 1605c2fa0f6SXander Huff #define GEM_DCFG1 0x0280 /* Design Config 1 */ 1615c2fa0f6SXander Huff #define GEM_DCFG2 0x0284 /* Design Config 2 */ 1625c2fa0f6SXander Huff #define GEM_DCFG3 0x0288 /* Design Config 3 */ 1635c2fa0f6SXander Huff #define GEM_DCFG4 0x028c /* Design Config 4 */ 1645c2fa0f6SXander Huff #define GEM_DCFG5 0x0290 /* Design Config 5 */ 1655c2fa0f6SXander Huff #define GEM_DCFG6 0x0294 /* Design Config 6 */ 1665c2fa0f6SXander Huff #define GEM_DCFG7 0x0298 /* Design Config 7 */ 1679f2f381fSJeff Kirsher 168ab91f0a9SRafal Ozieblo #define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */ 169ab91f0a9SRafal Ozieblo #define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */ 170ab91f0a9SRafal Ozieblo 17102c958ddSCyrille Pitchen #define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2)) 17202c958ddSCyrille Pitchen #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2)) 173fff8019aSHarini Katakam #define GEM_TBQPH(hw_q) (0x04C8) 17402c958ddSCyrille Pitchen #define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2)) 175*ae1f2a56SRafal Ozieblo #define GEM_RBQS(hw_q) (0x04A0 + ((hw_q) << 2)) 176*ae1f2a56SRafal Ozieblo #define GEM_RBQPH(hw_q) (0x04D4) 17702c958ddSCyrille Pitchen #define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2)) 17802c958ddSCyrille Pitchen #define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2)) 17902c958ddSCyrille Pitchen #define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2)) 18002c958ddSCyrille Pitchen 1819f2f381fSJeff Kirsher /* Bitfields in NCR */ 1825c2fa0f6SXander Huff #define MACB_LB_OFFSET 0 /* reserved */ 1839f2f381fSJeff Kirsher #define MACB_LB_SIZE 1 1845c2fa0f6SXander Huff #define MACB_LLB_OFFSET 1 /* Loop back local */ 1859f2f381fSJeff Kirsher #define MACB_LLB_SIZE 1 1865c2fa0f6SXander Huff #define MACB_RE_OFFSET 2 /* Receive enable */ 1879f2f381fSJeff Kirsher #define MACB_RE_SIZE 1 1885c2fa0f6SXander Huff #define MACB_TE_OFFSET 3 /* Transmit enable */ 1899f2f381fSJeff Kirsher #define MACB_TE_SIZE 1 1905c2fa0f6SXander Huff #define MACB_MPE_OFFSET 4 /* Management port enable */ 1919f2f381fSJeff Kirsher #define MACB_MPE_SIZE 1 1925c2fa0f6SXander Huff #define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */ 1939f2f381fSJeff Kirsher #define MACB_CLRSTAT_SIZE 1 1945c2fa0f6SXander Huff #define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */ 1959f2f381fSJeff Kirsher #define MACB_INCSTAT_SIZE 1 1965c2fa0f6SXander Huff #define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */ 1979f2f381fSJeff Kirsher #define MACB_WESTAT_SIZE 1 1985c2fa0f6SXander Huff #define MACB_BP_OFFSET 8 /* Back pressure */ 1999f2f381fSJeff Kirsher #define MACB_BP_SIZE 1 2005c2fa0f6SXander Huff #define MACB_TSTART_OFFSET 9 /* Start transmission */ 2019f2f381fSJeff Kirsher #define MACB_TSTART_SIZE 1 2025c2fa0f6SXander Huff #define MACB_THALT_OFFSET 10 /* Transmit halt */ 2039f2f381fSJeff Kirsher #define MACB_THALT_SIZE 1 2045c2fa0f6SXander Huff #define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */ 2059f2f381fSJeff Kirsher #define MACB_NCR_TPF_SIZE 1 2066f79eed8SXander Huff #define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */ 2079f2f381fSJeff Kirsher #define MACB_TZQ_SIZE 1 208c2594d80SAndrei.Pistirica@microchip.com #define MACB_SRTSM_OFFSET 15 209ab91f0a9SRafal Ozieblo #define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */ 210ab91f0a9SRafal Ozieblo #define MACB_OSSMODE_SIZE 1 2119f2f381fSJeff Kirsher 2129f2f381fSJeff Kirsher /* Bitfields in NCFGR */ 2135c2fa0f6SXander Huff #define MACB_SPD_OFFSET 0 /* Speed */ 2149f2f381fSJeff Kirsher #define MACB_SPD_SIZE 1 2155c2fa0f6SXander Huff #define MACB_FD_OFFSET 1 /* Full duplex */ 2169f2f381fSJeff Kirsher #define MACB_FD_SIZE 1 2175c2fa0f6SXander Huff #define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */ 2189f2f381fSJeff Kirsher #define MACB_BIT_RATE_SIZE 1 2195c2fa0f6SXander Huff #define MACB_JFRAME_OFFSET 3 /* reserved */ 2209f2f381fSJeff Kirsher #define MACB_JFRAME_SIZE 1 2215c2fa0f6SXander Huff #define MACB_CAF_OFFSET 4 /* Copy all frames */ 2229f2f381fSJeff Kirsher #define MACB_CAF_SIZE 1 2235c2fa0f6SXander Huff #define MACB_NBC_OFFSET 5 /* No broadcast */ 2249f2f381fSJeff Kirsher #define MACB_NBC_SIZE 1 2255c2fa0f6SXander Huff #define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */ 2269f2f381fSJeff Kirsher #define MACB_NCFGR_MTI_SIZE 1 2275c2fa0f6SXander Huff #define MACB_UNI_OFFSET 7 /* Unicast hash enable */ 2289f2f381fSJeff Kirsher #define MACB_UNI_SIZE 1 2295c2fa0f6SXander Huff #define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */ 2309f2f381fSJeff Kirsher #define MACB_BIG_SIZE 1 2316f79eed8SXander Huff #define MACB_EAE_OFFSET 9 /* External address match enable */ 2329f2f381fSJeff Kirsher #define MACB_EAE_SIZE 1 2339f2f381fSJeff Kirsher #define MACB_CLK_OFFSET 10 2349f2f381fSJeff Kirsher #define MACB_CLK_SIZE 2 2355c2fa0f6SXander Huff #define MACB_RTY_OFFSET 12 /* Retry test */ 2369f2f381fSJeff Kirsher #define MACB_RTY_SIZE 1 2375c2fa0f6SXander Huff #define MACB_PAE_OFFSET 13 /* Pause enable */ 2389f2f381fSJeff Kirsher #define MACB_PAE_SIZE 1 2391fd3ca4eSJoachim Eastwood #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */ 2401fd3ca4eSJoachim Eastwood #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */ 2415c2fa0f6SXander Huff #define MACB_RBOF_OFFSET 14 /* Receive buffer offset */ 2429f2f381fSJeff Kirsher #define MACB_RBOF_SIZE 2 2436f79eed8SXander Huff #define MACB_RLCE_OFFSET 16 /* Length field error frame discard */ 2449f2f381fSJeff Kirsher #define MACB_RLCE_SIZE 1 2455c2fa0f6SXander Huff #define MACB_DRFCS_OFFSET 17 /* FCS remove */ 2469f2f381fSJeff Kirsher #define MACB_DRFCS_SIZE 1 2479f2f381fSJeff Kirsher #define MACB_EFRHD_OFFSET 18 2489f2f381fSJeff Kirsher #define MACB_EFRHD_SIZE 1 2499f2f381fSJeff Kirsher #define MACB_IRXFCS_OFFSET 19 2509f2f381fSJeff Kirsher #define MACB_IRXFCS_SIZE 1 2519f2f381fSJeff Kirsher 25270c9f3d4SJamie Iles /* GEM specific NCFGR bitfields. */ 2535c2fa0f6SXander Huff #define GEM_GBE_OFFSET 10 /* Gigabit mode enable */ 254140b7552SPatrice Vilchez #define GEM_GBE_SIZE 1 255022be25cSPunnaiah Choudary Kalluri #define GEM_PCSSEL_OFFSET 11 256022be25cSPunnaiah Choudary Kalluri #define GEM_PCSSEL_SIZE 1 2575c2fa0f6SXander Huff #define GEM_CLK_OFFSET 18 /* MDC clock division */ 25870c9f3d4SJamie Iles #define GEM_CLK_SIZE 3 2595c2fa0f6SXander Huff #define GEM_DBW_OFFSET 21 /* Data bus width */ 260757a03c6SJamie Iles #define GEM_DBW_SIZE 2 261924ec53cSCyrille Pitchen #define GEM_RXCOEN_OFFSET 24 262924ec53cSCyrille Pitchen #define GEM_RXCOEN_SIZE 1 263022be25cSPunnaiah Choudary Kalluri #define GEM_SGMIIEN_OFFSET 27 264022be25cSPunnaiah Choudary Kalluri #define GEM_SGMIIEN_SIZE 1 265022be25cSPunnaiah Choudary Kalluri 266757a03c6SJamie Iles 267757a03c6SJamie Iles /* Constants for data bus width. */ 2686f79eed8SXander Huff #define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */ 2696f79eed8SXander Huff #define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */ 2706f79eed8SXander Huff #define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */ 271757a03c6SJamie Iles 2720116da4fSJamie Iles /* Bitfields in DMACFG. */ 2736f79eed8SXander Huff #define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */ 274b3e3bd71SNicolas Ferre #define GEM_FBLDO_SIZE 5 275a50dad35SArun Chandran #define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */ 276ea373041SArun Chandran #define GEM_ENDIA_DESC_SIZE 1 277a50dad35SArun Chandran #define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */ 278ea373041SArun Chandran #define GEM_ENDIA_PKT_SIZE 1 2796f79eed8SXander Huff #define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */ 280b3e3bd71SNicolas Ferre #define GEM_RXBMS_SIZE 2 2816f79eed8SXander Huff #define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */ 282b3e3bd71SNicolas Ferre #define GEM_TXPBMS_SIZE 1 2836f79eed8SXander Huff #define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */ 284b3e3bd71SNicolas Ferre #define GEM_TXCOEN_SIZE 1 2856f79eed8SXander Huff #define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */ 2860116da4fSJamie Iles #define GEM_RXBS_SIZE 8 2875c2fa0f6SXander Huff #define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */ 288b3e3bd71SNicolas Ferre #define GEM_DDRP_SIZE 1 2897b429614SRafal Ozieblo #define GEM_RXEXT_OFFSET 28 /* RX extended Buffer Descriptor mode */ 2907b429614SRafal Ozieblo #define GEM_RXEXT_SIZE 1 2917b429614SRafal Ozieblo #define GEM_TXEXT_OFFSET 29 /* TX extended Buffer Descriptor mode */ 2927b429614SRafal Ozieblo #define GEM_TXEXT_SIZE 1 293fff8019aSHarini Katakam #define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */ 294fff8019aSHarini Katakam #define GEM_ADDR64_SIZE 1 295b3e3bd71SNicolas Ferre 2960116da4fSJamie Iles 2979f2f381fSJeff Kirsher /* Bitfields in NSR */ 2985c2fa0f6SXander Huff #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */ 2999f2f381fSJeff Kirsher #define MACB_NSR_LINK_SIZE 1 3006f79eed8SXander Huff #define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */ 3019f2f381fSJeff Kirsher #define MACB_MDIO_SIZE 1 3026f79eed8SXander Huff #define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */ 3039f2f381fSJeff Kirsher #define MACB_IDLE_SIZE 1 3049f2f381fSJeff Kirsher 3059f2f381fSJeff Kirsher /* Bitfields in TSR */ 3065c2fa0f6SXander Huff #define MACB_UBR_OFFSET 0 /* Used bit read */ 3079f2f381fSJeff Kirsher #define MACB_UBR_SIZE 1 3085c2fa0f6SXander Huff #define MACB_COL_OFFSET 1 /* Collision occurred */ 3099f2f381fSJeff Kirsher #define MACB_COL_SIZE 1 3105c2fa0f6SXander Huff #define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */ 3119f2f381fSJeff Kirsher #define MACB_TSR_RLE_SIZE 1 3125c2fa0f6SXander Huff #define MACB_TGO_OFFSET 3 /* Transmit go */ 3139f2f381fSJeff Kirsher #define MACB_TGO_SIZE 1 3146f79eed8SXander Huff #define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */ 3159f2f381fSJeff Kirsher #define MACB_BEX_SIZE 1 3161fd3ca4eSJoachim Eastwood #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */ 3171fd3ca4eSJoachim Eastwood #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */ 3185c2fa0f6SXander Huff #define MACB_COMP_OFFSET 5 /* Trnasmit complete */ 3199f2f381fSJeff Kirsher #define MACB_COMP_SIZE 1 3205c2fa0f6SXander Huff #define MACB_UND_OFFSET 6 /* Trnasmit under run */ 3219f2f381fSJeff Kirsher #define MACB_UND_SIZE 1 3229f2f381fSJeff Kirsher 3239f2f381fSJeff Kirsher /* Bitfields in RSR */ 3245c2fa0f6SXander Huff #define MACB_BNA_OFFSET 0 /* Buffer not available */ 3259f2f381fSJeff Kirsher #define MACB_BNA_SIZE 1 3265c2fa0f6SXander Huff #define MACB_REC_OFFSET 1 /* Frame received */ 3279f2f381fSJeff Kirsher #define MACB_REC_SIZE 1 3285c2fa0f6SXander Huff #define MACB_OVR_OFFSET 2 /* Receive overrun */ 3299f2f381fSJeff Kirsher #define MACB_OVR_SIZE 1 3309f2f381fSJeff Kirsher 3319f2f381fSJeff Kirsher /* Bitfields in ISR/IER/IDR/IMR */ 3325c2fa0f6SXander Huff #define MACB_MFD_OFFSET 0 /* Management frame sent */ 3339f2f381fSJeff Kirsher #define MACB_MFD_SIZE 1 3345c2fa0f6SXander Huff #define MACB_RCOMP_OFFSET 1 /* Receive complete */ 3359f2f381fSJeff Kirsher #define MACB_RCOMP_SIZE 1 3365c2fa0f6SXander Huff #define MACB_RXUBR_OFFSET 2 /* RX used bit read */ 3379f2f381fSJeff Kirsher #define MACB_RXUBR_SIZE 1 3385c2fa0f6SXander Huff #define MACB_TXUBR_OFFSET 3 /* TX used bit read */ 3399f2f381fSJeff Kirsher #define MACB_TXUBR_SIZE 1 3406f79eed8SXander Huff #define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */ 3419f2f381fSJeff Kirsher #define MACB_ISR_TUND_SIZE 1 3426f79eed8SXander Huff #define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */ 3439f2f381fSJeff Kirsher #define MACB_ISR_RLE_SIZE 1 3446f79eed8SXander Huff #define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */ 3459f2f381fSJeff Kirsher #define MACB_TXERR_SIZE 1 3466f79eed8SXander Huff #define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */ 3479f2f381fSJeff Kirsher #define MACB_TCOMP_SIZE 1 3486f79eed8SXander Huff #define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */ 3499f2f381fSJeff Kirsher #define MACB_ISR_LINK_SIZE 1 3506f79eed8SXander Huff #define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */ 3519f2f381fSJeff Kirsher #define MACB_ISR_ROVR_SIZE 1 3526f79eed8SXander Huff #define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */ 3539f2f381fSJeff Kirsher #define MACB_HRESP_SIZE 1 3546f79eed8SXander Huff #define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */ 3559f2f381fSJeff Kirsher #define MACB_PFR_SIZE 1 3566f79eed8SXander Huff #define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */ 3579f2f381fSJeff Kirsher #define MACB_PTZ_SIZE 1 3583e2a5e15SSergio Prado #define MACB_WOL_OFFSET 14 /* Enable wake-on-lan interrupt */ 3593e2a5e15SSergio Prado #define MACB_WOL_SIZE 1 360c2594d80SAndrei.Pistirica@microchip.com #define MACB_DRQFR_OFFSET 18 /* PTP Delay Request Frame Received */ 361c2594d80SAndrei.Pistirica@microchip.com #define MACB_DRQFR_SIZE 1 362c2594d80SAndrei.Pistirica@microchip.com #define MACB_SFR_OFFSET 19 /* PTP Sync Frame Received */ 363c2594d80SAndrei.Pistirica@microchip.com #define MACB_SFR_SIZE 1 364c2594d80SAndrei.Pistirica@microchip.com #define MACB_DRQFT_OFFSET 20 /* PTP Delay Request Frame Transmitted */ 365c2594d80SAndrei.Pistirica@microchip.com #define MACB_DRQFT_SIZE 1 366c2594d80SAndrei.Pistirica@microchip.com #define MACB_SFT_OFFSET 21 /* PTP Sync Frame Transmitted */ 367c2594d80SAndrei.Pistirica@microchip.com #define MACB_SFT_SIZE 1 368c2594d80SAndrei.Pistirica@microchip.com #define MACB_PDRQFR_OFFSET 22 /* PDelay Request Frame Received */ 369c2594d80SAndrei.Pistirica@microchip.com #define MACB_PDRQFR_SIZE 1 370c2594d80SAndrei.Pistirica@microchip.com #define MACB_PDRSFR_OFFSET 23 /* PDelay Response Frame Received */ 371c2594d80SAndrei.Pistirica@microchip.com #define MACB_PDRSFR_SIZE 1 372c2594d80SAndrei.Pistirica@microchip.com #define MACB_PDRQFT_OFFSET 24 /* PDelay Request Frame Transmitted */ 373c2594d80SAndrei.Pistirica@microchip.com #define MACB_PDRQFT_SIZE 1 374c2594d80SAndrei.Pistirica@microchip.com #define MACB_PDRSFT_OFFSET 25 /* PDelay Response Frame Transmitted */ 375c2594d80SAndrei.Pistirica@microchip.com #define MACB_PDRSFT_SIZE 1 376c2594d80SAndrei.Pistirica@microchip.com #define MACB_SRI_OFFSET 26 /* TSU Seconds Register Increment */ 377c2594d80SAndrei.Pistirica@microchip.com #define MACB_SRI_SIZE 1 378c2594d80SAndrei.Pistirica@microchip.com 379c2594d80SAndrei.Pistirica@microchip.com /* Timer increment fields */ 380c2594d80SAndrei.Pistirica@microchip.com #define MACB_TI_CNS_OFFSET 0 381c2594d80SAndrei.Pistirica@microchip.com #define MACB_TI_CNS_SIZE 8 382c2594d80SAndrei.Pistirica@microchip.com #define MACB_TI_ACNS_OFFSET 8 383c2594d80SAndrei.Pistirica@microchip.com #define MACB_TI_ACNS_SIZE 8 384c2594d80SAndrei.Pistirica@microchip.com #define MACB_TI_NIT_OFFSET 16 385c2594d80SAndrei.Pistirica@microchip.com #define MACB_TI_NIT_SIZE 8 3869f2f381fSJeff Kirsher 3879f2f381fSJeff Kirsher /* Bitfields in MAN */ 3885c2fa0f6SXander Huff #define MACB_DATA_OFFSET 0 /* data */ 3899f2f381fSJeff Kirsher #define MACB_DATA_SIZE 16 3905c2fa0f6SXander Huff #define MACB_CODE_OFFSET 16 /* Must be written to 10 */ 3919f2f381fSJeff Kirsher #define MACB_CODE_SIZE 2 3925c2fa0f6SXander Huff #define MACB_REGA_OFFSET 18 /* Register address */ 3939f2f381fSJeff Kirsher #define MACB_REGA_SIZE 5 3945c2fa0f6SXander Huff #define MACB_PHYA_OFFSET 23 /* PHY address */ 3959f2f381fSJeff Kirsher #define MACB_PHYA_SIZE 5 3966f79eed8SXander Huff #define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */ 3979f2f381fSJeff Kirsher #define MACB_RW_SIZE 2 3986f79eed8SXander Huff #define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */ 3999f2f381fSJeff Kirsher #define MACB_SOF_SIZE 2 4009f2f381fSJeff Kirsher 4019f2f381fSJeff Kirsher /* Bitfields in USRIO (AVR32) */ 4029f2f381fSJeff Kirsher #define MACB_MII_OFFSET 0 4039f2f381fSJeff Kirsher #define MACB_MII_SIZE 1 4049f2f381fSJeff Kirsher #define MACB_EAM_OFFSET 1 4059f2f381fSJeff Kirsher #define MACB_EAM_SIZE 1 4069f2f381fSJeff Kirsher #define MACB_TX_PAUSE_OFFSET 2 4079f2f381fSJeff Kirsher #define MACB_TX_PAUSE_SIZE 1 4089f2f381fSJeff Kirsher #define MACB_TX_PAUSE_ZERO_OFFSET 3 4099f2f381fSJeff Kirsher #define MACB_TX_PAUSE_ZERO_SIZE 1 4109f2f381fSJeff Kirsher 4119f2f381fSJeff Kirsher /* Bitfields in USRIO (AT91) */ 4129f2f381fSJeff Kirsher #define MACB_RMII_OFFSET 0 4139f2f381fSJeff Kirsher #define MACB_RMII_SIZE 1 414140b7552SPatrice Vilchez #define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */ 415140b7552SPatrice Vilchez #define GEM_RGMII_SIZE 1 4169f2f381fSJeff Kirsher #define MACB_CLKEN_OFFSET 1 4179f2f381fSJeff Kirsher #define MACB_CLKEN_SIZE 1 4189f2f381fSJeff Kirsher 4199f2f381fSJeff Kirsher /* Bitfields in WOL */ 4209f2f381fSJeff Kirsher #define MACB_IP_OFFSET 0 4219f2f381fSJeff Kirsher #define MACB_IP_SIZE 16 4229f2f381fSJeff Kirsher #define MACB_MAG_OFFSET 16 4239f2f381fSJeff Kirsher #define MACB_MAG_SIZE 1 4249f2f381fSJeff Kirsher #define MACB_ARP_OFFSET 17 4259f2f381fSJeff Kirsher #define MACB_ARP_SIZE 1 4269f2f381fSJeff Kirsher #define MACB_SA1_OFFSET 18 4279f2f381fSJeff Kirsher #define MACB_SA1_SIZE 1 4289f2f381fSJeff Kirsher #define MACB_WOL_MTI_OFFSET 19 4299f2f381fSJeff Kirsher #define MACB_WOL_MTI_SIZE 1 4309f2f381fSJeff Kirsher 431f75ba50bSJamie Iles /* Bitfields in MID */ 432f75ba50bSJamie Iles #define MACB_IDNUM_OFFSET 16 433d941bebfSPunnaiah Choudary Kalluri #define MACB_IDNUM_SIZE 12 434f75ba50bSJamie Iles #define MACB_REV_OFFSET 0 435f75ba50bSJamie Iles #define MACB_REV_SIZE 16 436f75ba50bSJamie Iles 437757a03c6SJamie Iles /* Bitfields in DCFG1. */ 438581df9e1SNicolas Ferre #define GEM_IRQCOR_OFFSET 23 439581df9e1SNicolas Ferre #define GEM_IRQCOR_SIZE 1 440757a03c6SJamie Iles #define GEM_DBWDEF_OFFSET 25 441757a03c6SJamie Iles #define GEM_DBWDEF_SIZE 3 442757a03c6SJamie Iles 443e175587fSNicolas Ferre /* Bitfields in DCFG2. */ 444e175587fSNicolas Ferre #define GEM_RX_PKT_BUFF_OFFSET 20 445e175587fSNicolas Ferre #define GEM_RX_PKT_BUFF_SIZE 1 446e175587fSNicolas Ferre #define GEM_TX_PKT_BUFF_OFFSET 21 447e175587fSNicolas Ferre #define GEM_TX_PKT_BUFF_SIZE 1 448e175587fSNicolas Ferre 4497b429614SRafal Ozieblo 4507b429614SRafal Ozieblo /* Bitfields in DCFG5. */ 4517b429614SRafal Ozieblo #define GEM_TSU_OFFSET 8 4527b429614SRafal Ozieblo #define GEM_TSU_SIZE 1 4537b429614SRafal Ozieblo 4541629dd4fSRafal Ozieblo /* Bitfields in DCFG6. */ 4551629dd4fSRafal Ozieblo #define GEM_PBUF_LSO_OFFSET 27 4561629dd4fSRafal Ozieblo #define GEM_PBUF_LSO_SIZE 1 457dc97a89eSRafal Ozieblo #define GEM_DAW64_OFFSET 23 458dc97a89eSRafal Ozieblo #define GEM_DAW64_SIZE 1 4591629dd4fSRafal Ozieblo 460c2594d80SAndrei.Pistirica@microchip.com /* Bitfields in TISUBN */ 461c2594d80SAndrei.Pistirica@microchip.com #define GEM_SUBNSINCR_OFFSET 0 462c2594d80SAndrei.Pistirica@microchip.com #define GEM_SUBNSINCR_SIZE 16 463c2594d80SAndrei.Pistirica@microchip.com 464c2594d80SAndrei.Pistirica@microchip.com /* Bitfields in TI */ 465c2594d80SAndrei.Pistirica@microchip.com #define GEM_NSINCR_OFFSET 0 466c2594d80SAndrei.Pistirica@microchip.com #define GEM_NSINCR_SIZE 8 467c2594d80SAndrei.Pistirica@microchip.com 468ab91f0a9SRafal Ozieblo /* Bitfields in TSH */ 469ab91f0a9SRafal Ozieblo #define GEM_TSH_OFFSET 0 /* TSU timer value (s). MSB [47:32] of seconds timer count */ 470ab91f0a9SRafal Ozieblo #define GEM_TSH_SIZE 16 471ab91f0a9SRafal Ozieblo 472ab91f0a9SRafal Ozieblo /* Bitfields in TSL */ 473ab91f0a9SRafal Ozieblo #define GEM_TSL_OFFSET 0 /* TSU timer value (s). LSB [31:0] of seconds timer count */ 474ab91f0a9SRafal Ozieblo #define GEM_TSL_SIZE 32 475ab91f0a9SRafal Ozieblo 476ab91f0a9SRafal Ozieblo /* Bitfields in TN */ 477ab91f0a9SRafal Ozieblo #define GEM_TN_OFFSET 0 /* TSU timer value (ns) */ 478ab91f0a9SRafal Ozieblo #define GEM_TN_SIZE 30 479ab91f0a9SRafal Ozieblo 480ab91f0a9SRafal Ozieblo /* Bitfields in TXBDCTRL */ 481ab91f0a9SRafal Ozieblo #define GEM_TXTSMODE_OFFSET 4 /* TX Descriptor Timestamp Insertion mode */ 482ab91f0a9SRafal Ozieblo #define GEM_TXTSMODE_SIZE 2 483ab91f0a9SRafal Ozieblo 484ab91f0a9SRafal Ozieblo /* Bitfields in RXBDCTRL */ 485ab91f0a9SRafal Ozieblo #define GEM_RXTSMODE_OFFSET 4 /* RX Descriptor Timestamp Insertion mode */ 486ab91f0a9SRafal Ozieblo #define GEM_RXTSMODE_SIZE 2 487ab91f0a9SRafal Ozieblo 488ab91f0a9SRafal Ozieblo /* Transmit DMA buffer descriptor Word 1 */ 489ab91f0a9SRafal Ozieblo #define GEM_DMA_TXVALID_OFFSET 23 /* timestamp has been captured in the Buffer Descriptor */ 490ab91f0a9SRafal Ozieblo #define GEM_DMA_TXVALID_SIZE 1 491ab91f0a9SRafal Ozieblo 492ab91f0a9SRafal Ozieblo /* Receive DMA buffer descriptor Word 0 */ 493ab91f0a9SRafal Ozieblo #define GEM_DMA_RXVALID_OFFSET 2 /* indicates a valid timestamp in the Buffer Descriptor */ 494ab91f0a9SRafal Ozieblo #define GEM_DMA_RXVALID_SIZE 1 495ab91f0a9SRafal Ozieblo 496ab91f0a9SRafal Ozieblo /* DMA buffer descriptor Word 2 (32 bit addressing) or Word 4 (64 bit addressing) */ 497ab91f0a9SRafal Ozieblo #define GEM_DMA_SECL_OFFSET 30 /* Timestamp seconds[1:0] */ 498ab91f0a9SRafal Ozieblo #define GEM_DMA_SECL_SIZE 2 499ab91f0a9SRafal Ozieblo #define GEM_DMA_NSEC_OFFSET 0 /* Timestamp nanosecs [29:0] */ 500ab91f0a9SRafal Ozieblo #define GEM_DMA_NSEC_SIZE 30 501ab91f0a9SRafal Ozieblo 502ab91f0a9SRafal Ozieblo /* DMA buffer descriptor Word 3 (32 bit addressing) or Word 5 (64 bit addressing) */ 503ab91f0a9SRafal Ozieblo 504ab91f0a9SRafal Ozieblo /* New hardware supports 12 bit precision of timestamp in DMA buffer descriptor. 505ab91f0a9SRafal Ozieblo * Old hardware supports only 6 bit precision but it is enough for PTP. 506ab91f0a9SRafal Ozieblo * Less accuracy is used always instead of checking hardware version. 507ab91f0a9SRafal Ozieblo */ 508ab91f0a9SRafal Ozieblo #define GEM_DMA_SECH_OFFSET 0 /* Timestamp seconds[5:2] */ 509ab91f0a9SRafal Ozieblo #define GEM_DMA_SECH_SIZE 4 510ab91f0a9SRafal Ozieblo #define GEM_DMA_SEC_WIDTH (GEM_DMA_SECH_SIZE + GEM_DMA_SECL_SIZE) 511ab91f0a9SRafal Ozieblo #define GEM_DMA_SEC_TOP (1 << GEM_DMA_SEC_WIDTH) 512ab91f0a9SRafal Ozieblo #define GEM_DMA_SEC_MASK (GEM_DMA_SEC_TOP - 1) 513ab91f0a9SRafal Ozieblo 514c2594d80SAndrei.Pistirica@microchip.com /* Bitfields in ADJ */ 515c2594d80SAndrei.Pistirica@microchip.com #define GEM_ADDSUB_OFFSET 31 516c2594d80SAndrei.Pistirica@microchip.com #define GEM_ADDSUB_SIZE 1 5179f2f381fSJeff Kirsher /* Constants for CLK */ 5189f2f381fSJeff Kirsher #define MACB_CLK_DIV8 0 5199f2f381fSJeff Kirsher #define MACB_CLK_DIV16 1 5209f2f381fSJeff Kirsher #define MACB_CLK_DIV32 2 5219f2f381fSJeff Kirsher #define MACB_CLK_DIV64 3 5229f2f381fSJeff Kirsher 52370c9f3d4SJamie Iles /* GEM specific constants for CLK. */ 52470c9f3d4SJamie Iles #define GEM_CLK_DIV8 0 52570c9f3d4SJamie Iles #define GEM_CLK_DIV16 1 52670c9f3d4SJamie Iles #define GEM_CLK_DIV32 2 52770c9f3d4SJamie Iles #define GEM_CLK_DIV48 3 52870c9f3d4SJamie Iles #define GEM_CLK_DIV64 4 52970c9f3d4SJamie Iles #define GEM_CLK_DIV96 5 53070c9f3d4SJamie Iles 5319f2f381fSJeff Kirsher /* Constants for MAN register */ 5329f2f381fSJeff Kirsher #define MACB_MAN_SOF 1 5339f2f381fSJeff Kirsher #define MACB_MAN_WRITE 1 5349f2f381fSJeff Kirsher #define MACB_MAN_READ 2 5359f2f381fSJeff Kirsher #define MACB_MAN_CODE 2 5369f2f381fSJeff Kirsher 537581df9e1SNicolas Ferre /* Capability mask bits */ 538e175587fSNicolas Ferre #define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001 539a8487489SBoris BREZILLON #define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002 5406bdaa5e9SNicolas Ferre #define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004 541222ca8e0SNathan Sullivan #define MACB_CAPS_NO_GIGABIT_HALF 0x00000008 542ce721a70SNeil Armstrong #define MACB_CAPS_USRIO_DISABLED 0x00000010 543c5181895SHarini Katakam #define MACB_CAPS_JUMBO 0x00000020 544c2594d80SAndrei.Pistirica@microchip.com #define MACB_CAPS_GEM_HAS_PTP 0x00000040 545e175587fSNicolas Ferre #define MACB_CAPS_FIFO_MODE 0x10000000 546e175587fSNicolas Ferre #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000 547a4c35ed3SCyrille Pitchen #define MACB_CAPS_SG_DISABLED 0x40000000 548e175587fSNicolas Ferre #define MACB_CAPS_MACB_IS_GEM 0x80000000 549581df9e1SNicolas Ferre 5501629dd4fSRafal Ozieblo /* LSO settings */ 5511629dd4fSRafal Ozieblo #define MACB_LSO_UFO_ENABLE 0x01 5521629dd4fSRafal Ozieblo #define MACB_LSO_TSO_ENABLE 0x02 5531629dd4fSRafal Ozieblo 5549f2f381fSJeff Kirsher /* Bit manipulation macros */ 5559f2f381fSJeff Kirsher #define MACB_BIT(name) \ 5569f2f381fSJeff Kirsher (1 << MACB_##name##_OFFSET) 5579f2f381fSJeff Kirsher #define MACB_BF(name,value) \ 5589f2f381fSJeff Kirsher (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ 5599f2f381fSJeff Kirsher << MACB_##name##_OFFSET) 5609f2f381fSJeff Kirsher #define MACB_BFEXT(name,value)\ 5619f2f381fSJeff Kirsher (((value) >> MACB_##name##_OFFSET) \ 5629f2f381fSJeff Kirsher & ((1 << MACB_##name##_SIZE) - 1)) 5639f2f381fSJeff Kirsher #define MACB_BFINS(name,value,old) \ 5649f2f381fSJeff Kirsher (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ 5659f2f381fSJeff Kirsher << MACB_##name##_OFFSET)) \ 5669f2f381fSJeff Kirsher | MACB_BF(name,value)) 5679f2f381fSJeff Kirsher 568f75ba50bSJamie Iles #define GEM_BIT(name) \ 569f75ba50bSJamie Iles (1 << GEM_##name##_OFFSET) 570f75ba50bSJamie Iles #define GEM_BF(name, value) \ 571f75ba50bSJamie Iles (((value) & ((1 << GEM_##name##_SIZE) - 1)) \ 572f75ba50bSJamie Iles << GEM_##name##_OFFSET) 573f75ba50bSJamie Iles #define GEM_BFEXT(name, value)\ 574f75ba50bSJamie Iles (((value) >> GEM_##name##_OFFSET) \ 575f75ba50bSJamie Iles & ((1 << GEM_##name##_SIZE) - 1)) 576f75ba50bSJamie Iles #define GEM_BFINS(name, value, old) \ 577f75ba50bSJamie Iles (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \ 578f75ba50bSJamie Iles << GEM_##name##_OFFSET)) \ 579f75ba50bSJamie Iles | GEM_BF(name, value)) 580f75ba50bSJamie Iles 5819f2f381fSJeff Kirsher /* Register access macros */ 5827a6e0706SDavid S. Miller #define macb_readl(port, reg) (port)->macb_reg_readl((port), MACB_##reg) 5837a6e0706SDavid S. Miller #define macb_writel(port, reg, value) (port)->macb_reg_writel((port), MACB_##reg, (value)) 5847a6e0706SDavid S. Miller #define gem_readl(port, reg) (port)->macb_reg_readl((port), GEM_##reg) 5857a6e0706SDavid S. Miller #define gem_writel(port, reg, value) (port)->macb_reg_writel((port), GEM_##reg, (value)) 5867a6e0706SDavid S. Miller #define queue_readl(queue, reg) (queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg) 5877a6e0706SDavid S. Miller #define queue_writel(queue, reg, value) (queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (value)) 588f75ba50bSJamie Iles 589ab91f0a9SRafal Ozieblo #define PTP_TS_BUFFER_SIZE 128 /* must be power of 2 */ 590ab91f0a9SRafal Ozieblo 5916f79eed8SXander Huff /* Conditional GEM/MACB macros. These perform the operation to the correct 592f75ba50bSJamie Iles * register dependent on whether the device is a GEM or a MACB. For registers 593f75ba50bSJamie Iles * and bitfields that are common across both devices, use macb_{read,write}l 594f75ba50bSJamie Iles * to avoid the cost of the conditional. 595f75ba50bSJamie Iles */ 596f75ba50bSJamie Iles #define macb_or_gem_writel(__bp, __reg, __value) \ 597f75ba50bSJamie Iles ({ \ 598f75ba50bSJamie Iles if (macb_is_gem((__bp))) \ 599f75ba50bSJamie Iles gem_writel((__bp), __reg, __value); \ 600f75ba50bSJamie Iles else \ 601f75ba50bSJamie Iles macb_writel((__bp), __reg, __value); \ 602f75ba50bSJamie Iles }) 603f75ba50bSJamie Iles 604f75ba50bSJamie Iles #define macb_or_gem_readl(__bp, __reg) \ 605f75ba50bSJamie Iles ({ \ 606f75ba50bSJamie Iles u32 __v; \ 607f75ba50bSJamie Iles if (macb_is_gem((__bp))) \ 608f75ba50bSJamie Iles __v = gem_readl((__bp), __reg); \ 609f75ba50bSJamie Iles else \ 610f75ba50bSJamie Iles __v = macb_readl((__bp), __reg); \ 611f75ba50bSJamie Iles __v; \ 612f75ba50bSJamie Iles }) 6139f2f381fSJeff Kirsher 6146f79eed8SXander Huff /* struct macb_dma_desc - Hardware DMA descriptor 61555054a16SHavard Skinnemoen * @addr: DMA address of data buffer 61655054a16SHavard Skinnemoen * @ctrl: Control and status bits 61755054a16SHavard Skinnemoen */ 61855054a16SHavard Skinnemoen struct macb_dma_desc { 6199f2f381fSJeff Kirsher u32 addr; 6209f2f381fSJeff Kirsher u32 ctrl; 621dc97a89eSRafal Ozieblo }; 622dc97a89eSRafal Ozieblo 6237b429614SRafal Ozieblo #ifdef MACB_EXT_DESC 6247b429614SRafal Ozieblo #define HW_DMA_CAP_32B 0 6257b429614SRafal Ozieblo #define HW_DMA_CAP_64B (1 << 0) 6267b429614SRafal Ozieblo #define HW_DMA_CAP_PTP (1 << 1) 6277b429614SRafal Ozieblo #define HW_DMA_CAP_64B_PTP (HW_DMA_CAP_64B | HW_DMA_CAP_PTP) 628dc97a89eSRafal Ozieblo 629dc97a89eSRafal Ozieblo struct macb_dma_desc_64 { 630fff8019aSHarini Katakam u32 addrh; 631fff8019aSHarini Katakam u32 resvd; 6329f2f381fSJeff Kirsher }; 6337b429614SRafal Ozieblo 6347b429614SRafal Ozieblo struct macb_dma_desc_ptp { 6357b429614SRafal Ozieblo u32 ts_1; 6367b429614SRafal Ozieblo u32 ts_2; 6377b429614SRafal Ozieblo }; 638ab91f0a9SRafal Ozieblo 639ab91f0a9SRafal Ozieblo struct gem_tx_ts { 640ab91f0a9SRafal Ozieblo struct sk_buff *skb; 641ab91f0a9SRafal Ozieblo struct macb_dma_desc_ptp desc_ptp; 642ab91f0a9SRafal Ozieblo }; 643dc97a89eSRafal Ozieblo #endif 6449f2f381fSJeff Kirsher 6459f2f381fSJeff Kirsher /* DMA descriptor bitfields */ 6469f2f381fSJeff Kirsher #define MACB_RX_USED_OFFSET 0 6479f2f381fSJeff Kirsher #define MACB_RX_USED_SIZE 1 6489f2f381fSJeff Kirsher #define MACB_RX_WRAP_OFFSET 1 6499f2f381fSJeff Kirsher #define MACB_RX_WRAP_SIZE 1 6509f2f381fSJeff Kirsher #define MACB_RX_WADDR_OFFSET 2 6519f2f381fSJeff Kirsher #define MACB_RX_WADDR_SIZE 30 6529f2f381fSJeff Kirsher 6539f2f381fSJeff Kirsher #define MACB_RX_FRMLEN_OFFSET 0 6549f2f381fSJeff Kirsher #define MACB_RX_FRMLEN_SIZE 12 6559f2f381fSJeff Kirsher #define MACB_RX_OFFSET_OFFSET 12 6569f2f381fSJeff Kirsher #define MACB_RX_OFFSET_SIZE 2 6579f2f381fSJeff Kirsher #define MACB_RX_SOF_OFFSET 14 6589f2f381fSJeff Kirsher #define MACB_RX_SOF_SIZE 1 6599f2f381fSJeff Kirsher #define MACB_RX_EOF_OFFSET 15 6609f2f381fSJeff Kirsher #define MACB_RX_EOF_SIZE 1 6619f2f381fSJeff Kirsher #define MACB_RX_CFI_OFFSET 16 6629f2f381fSJeff Kirsher #define MACB_RX_CFI_SIZE 1 6639f2f381fSJeff Kirsher #define MACB_RX_VLAN_PRI_OFFSET 17 6649f2f381fSJeff Kirsher #define MACB_RX_VLAN_PRI_SIZE 3 6659f2f381fSJeff Kirsher #define MACB_RX_PRI_TAG_OFFSET 20 6669f2f381fSJeff Kirsher #define MACB_RX_PRI_TAG_SIZE 1 6679f2f381fSJeff Kirsher #define MACB_RX_VLAN_TAG_OFFSET 21 6689f2f381fSJeff Kirsher #define MACB_RX_VLAN_TAG_SIZE 1 6699f2f381fSJeff Kirsher #define MACB_RX_TYPEID_MATCH_OFFSET 22 6709f2f381fSJeff Kirsher #define MACB_RX_TYPEID_MATCH_SIZE 1 6719f2f381fSJeff Kirsher #define MACB_RX_SA4_MATCH_OFFSET 23 6729f2f381fSJeff Kirsher #define MACB_RX_SA4_MATCH_SIZE 1 6739f2f381fSJeff Kirsher #define MACB_RX_SA3_MATCH_OFFSET 24 6749f2f381fSJeff Kirsher #define MACB_RX_SA3_MATCH_SIZE 1 6759f2f381fSJeff Kirsher #define MACB_RX_SA2_MATCH_OFFSET 25 6769f2f381fSJeff Kirsher #define MACB_RX_SA2_MATCH_SIZE 1 6779f2f381fSJeff Kirsher #define MACB_RX_SA1_MATCH_OFFSET 26 6789f2f381fSJeff Kirsher #define MACB_RX_SA1_MATCH_SIZE 1 6799f2f381fSJeff Kirsher #define MACB_RX_EXT_MATCH_OFFSET 28 6809f2f381fSJeff Kirsher #define MACB_RX_EXT_MATCH_SIZE 1 6819f2f381fSJeff Kirsher #define MACB_RX_UHASH_MATCH_OFFSET 29 6829f2f381fSJeff Kirsher #define MACB_RX_UHASH_MATCH_SIZE 1 6839f2f381fSJeff Kirsher #define MACB_RX_MHASH_MATCH_OFFSET 30 6849f2f381fSJeff Kirsher #define MACB_RX_MHASH_MATCH_SIZE 1 6859f2f381fSJeff Kirsher #define MACB_RX_BROADCAST_OFFSET 31 6869f2f381fSJeff Kirsher #define MACB_RX_BROADCAST_SIZE 1 6879f2f381fSJeff Kirsher 68898b5a0f4SHarini Katakam #define MACB_RX_FRMLEN_MASK 0xFFF 68998b5a0f4SHarini Katakam #define MACB_RX_JFRMLEN_MASK 0x3FFF 69098b5a0f4SHarini Katakam 691924ec53cSCyrille Pitchen /* RX checksum offload disabled: bit 24 clear in NCFGR */ 692924ec53cSCyrille Pitchen #define GEM_RX_TYPEID_MATCH_OFFSET 22 693924ec53cSCyrille Pitchen #define GEM_RX_TYPEID_MATCH_SIZE 2 694924ec53cSCyrille Pitchen 695924ec53cSCyrille Pitchen /* RX checksum offload enabled: bit 24 set in NCFGR */ 696924ec53cSCyrille Pitchen #define GEM_RX_CSUM_OFFSET 22 697924ec53cSCyrille Pitchen #define GEM_RX_CSUM_SIZE 2 698924ec53cSCyrille Pitchen 6999f2f381fSJeff Kirsher #define MACB_TX_FRMLEN_OFFSET 0 7009f2f381fSJeff Kirsher #define MACB_TX_FRMLEN_SIZE 11 7019f2f381fSJeff Kirsher #define MACB_TX_LAST_OFFSET 15 7029f2f381fSJeff Kirsher #define MACB_TX_LAST_SIZE 1 7039f2f381fSJeff Kirsher #define MACB_TX_NOCRC_OFFSET 16 7049f2f381fSJeff Kirsher #define MACB_TX_NOCRC_SIZE 1 7051629dd4fSRafal Ozieblo #define MACB_MSS_MFS_OFFSET 16 7061629dd4fSRafal Ozieblo #define MACB_MSS_MFS_SIZE 14 7071629dd4fSRafal Ozieblo #define MACB_TX_LSO_OFFSET 17 7081629dd4fSRafal Ozieblo #define MACB_TX_LSO_SIZE 2 7091629dd4fSRafal Ozieblo #define MACB_TX_TCP_SEQ_SRC_OFFSET 19 7101629dd4fSRafal Ozieblo #define MACB_TX_TCP_SEQ_SRC_SIZE 1 7119f2f381fSJeff Kirsher #define MACB_TX_BUF_EXHAUSTED_OFFSET 27 7129f2f381fSJeff Kirsher #define MACB_TX_BUF_EXHAUSTED_SIZE 1 7139f2f381fSJeff Kirsher #define MACB_TX_UNDERRUN_OFFSET 28 7149f2f381fSJeff Kirsher #define MACB_TX_UNDERRUN_SIZE 1 7159f2f381fSJeff Kirsher #define MACB_TX_ERROR_OFFSET 29 7169f2f381fSJeff Kirsher #define MACB_TX_ERROR_SIZE 1 7179f2f381fSJeff Kirsher #define MACB_TX_WRAP_OFFSET 30 7189f2f381fSJeff Kirsher #define MACB_TX_WRAP_SIZE 1 7199f2f381fSJeff Kirsher #define MACB_TX_USED_OFFSET 31 7209f2f381fSJeff Kirsher #define MACB_TX_USED_SIZE 1 7219f2f381fSJeff Kirsher 722a4c35ed3SCyrille Pitchen #define GEM_TX_FRMLEN_OFFSET 0 723a4c35ed3SCyrille Pitchen #define GEM_TX_FRMLEN_SIZE 14 724a4c35ed3SCyrille Pitchen 725924ec53cSCyrille Pitchen /* Buffer descriptor constants */ 726924ec53cSCyrille Pitchen #define GEM_RX_CSUM_NONE 0 727924ec53cSCyrille Pitchen #define GEM_RX_CSUM_IP_ONLY 1 728924ec53cSCyrille Pitchen #define GEM_RX_CSUM_IP_TCP 2 729924ec53cSCyrille Pitchen #define GEM_RX_CSUM_IP_UDP 3 730924ec53cSCyrille Pitchen 731924ec53cSCyrille Pitchen /* limit RX checksum offload to TCP and UDP packets */ 732924ec53cSCyrille Pitchen #define GEM_RX_CSUM_CHECKED_MASK 2 733924ec53cSCyrille Pitchen 7346f79eed8SXander Huff /* struct macb_tx_skb - data about an skb which is being transmitted 735a4c35ed3SCyrille Pitchen * @skb: skb currently being transmitted, only set for the last buffer 736a4c35ed3SCyrille Pitchen * of the frame 737a4c35ed3SCyrille Pitchen * @mapping: DMA address of the skb's fragment buffer 738a4c35ed3SCyrille Pitchen * @size: size of the DMA mapped buffer 739a4c35ed3SCyrille Pitchen * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(), 740a4c35ed3SCyrille Pitchen * false when buffer was mapped with dma_map_single() 74155054a16SHavard Skinnemoen */ 74255054a16SHavard Skinnemoen struct macb_tx_skb { 7439f2f381fSJeff Kirsher struct sk_buff *skb; 7449f2f381fSJeff Kirsher dma_addr_t mapping; 745a4c35ed3SCyrille Pitchen size_t size; 746a4c35ed3SCyrille Pitchen bool mapped_as_page; 7479f2f381fSJeff Kirsher }; 7489f2f381fSJeff Kirsher 7496f79eed8SXander Huff /* Hardware-collected statistics. Used when updating the network 7509f2f381fSJeff Kirsher * device stats by a periodic timer. 7519f2f381fSJeff Kirsher */ 7529f2f381fSJeff Kirsher struct macb_stats { 7539f2f381fSJeff Kirsher u32 rx_pause_frames; 7549f2f381fSJeff Kirsher u32 tx_ok; 7559f2f381fSJeff Kirsher u32 tx_single_cols; 7569f2f381fSJeff Kirsher u32 tx_multiple_cols; 7579f2f381fSJeff Kirsher u32 rx_ok; 7589f2f381fSJeff Kirsher u32 rx_fcs_errors; 7599f2f381fSJeff Kirsher u32 rx_align_errors; 7609f2f381fSJeff Kirsher u32 tx_deferred; 7619f2f381fSJeff Kirsher u32 tx_late_cols; 7629f2f381fSJeff Kirsher u32 tx_excessive_cols; 7639f2f381fSJeff Kirsher u32 tx_underruns; 7649f2f381fSJeff Kirsher u32 tx_carrier_errors; 7659f2f381fSJeff Kirsher u32 rx_resource_errors; 7669f2f381fSJeff Kirsher u32 rx_overruns; 7679f2f381fSJeff Kirsher u32 rx_symbol_errors; 7689f2f381fSJeff Kirsher u32 rx_oversize_pkts; 7699f2f381fSJeff Kirsher u32 rx_jabbers; 7709f2f381fSJeff Kirsher u32 rx_undersize_pkts; 7719f2f381fSJeff Kirsher u32 sqe_test_errors; 7729f2f381fSJeff Kirsher u32 rx_length_mismatch; 7739f2f381fSJeff Kirsher u32 tx_pause_frames; 7749f2f381fSJeff Kirsher }; 7759f2f381fSJeff Kirsher 776a494ed8eSJamie Iles struct gem_stats { 777a494ed8eSJamie Iles u32 tx_octets_31_0; 778a494ed8eSJamie Iles u32 tx_octets_47_32; 779a494ed8eSJamie Iles u32 tx_frames; 780a494ed8eSJamie Iles u32 tx_broadcast_frames; 781a494ed8eSJamie Iles u32 tx_multicast_frames; 782a494ed8eSJamie Iles u32 tx_pause_frames; 783a494ed8eSJamie Iles u32 tx_64_byte_frames; 784a494ed8eSJamie Iles u32 tx_65_127_byte_frames; 785a494ed8eSJamie Iles u32 tx_128_255_byte_frames; 786a494ed8eSJamie Iles u32 tx_256_511_byte_frames; 787a494ed8eSJamie Iles u32 tx_512_1023_byte_frames; 788a494ed8eSJamie Iles u32 tx_1024_1518_byte_frames; 789a494ed8eSJamie Iles u32 tx_greater_than_1518_byte_frames; 790a494ed8eSJamie Iles u32 tx_underrun; 791a494ed8eSJamie Iles u32 tx_single_collision_frames; 792a494ed8eSJamie Iles u32 tx_multiple_collision_frames; 793a494ed8eSJamie Iles u32 tx_excessive_collisions; 794a494ed8eSJamie Iles u32 tx_late_collisions; 795a494ed8eSJamie Iles u32 tx_deferred_frames; 796a494ed8eSJamie Iles u32 tx_carrier_sense_errors; 797a494ed8eSJamie Iles u32 rx_octets_31_0; 798a494ed8eSJamie Iles u32 rx_octets_47_32; 799a494ed8eSJamie Iles u32 rx_frames; 800a494ed8eSJamie Iles u32 rx_broadcast_frames; 801a494ed8eSJamie Iles u32 rx_multicast_frames; 802a494ed8eSJamie Iles u32 rx_pause_frames; 803a494ed8eSJamie Iles u32 rx_64_byte_frames; 804a494ed8eSJamie Iles u32 rx_65_127_byte_frames; 805a494ed8eSJamie Iles u32 rx_128_255_byte_frames; 806a494ed8eSJamie Iles u32 rx_256_511_byte_frames; 807a494ed8eSJamie Iles u32 rx_512_1023_byte_frames; 808a494ed8eSJamie Iles u32 rx_1024_1518_byte_frames; 809a494ed8eSJamie Iles u32 rx_greater_than_1518_byte_frames; 810a494ed8eSJamie Iles u32 rx_undersized_frames; 811a494ed8eSJamie Iles u32 rx_oversize_frames; 812a494ed8eSJamie Iles u32 rx_jabbers; 813a494ed8eSJamie Iles u32 rx_frame_check_sequence_errors; 814a494ed8eSJamie Iles u32 rx_length_field_frame_errors; 815a494ed8eSJamie Iles u32 rx_symbol_errors; 816a494ed8eSJamie Iles u32 rx_alignment_errors; 817a494ed8eSJamie Iles u32 rx_resource_errors; 818a494ed8eSJamie Iles u32 rx_overruns; 819a494ed8eSJamie Iles u32 rx_ip_header_checksum_errors; 820a494ed8eSJamie Iles u32 rx_tcp_checksum_errors; 821a494ed8eSJamie Iles u32 rx_udp_checksum_errors; 822a494ed8eSJamie Iles }; 823a494ed8eSJamie Iles 8243ff13f1cSXander Huff /* Describes the name and offset of an individual statistic register, as 8253ff13f1cSXander Huff * returned by `ethtool -S`. Also describes which net_device_stats statistics 8263ff13f1cSXander Huff * this register should contribute to. 8273ff13f1cSXander Huff */ 8283ff13f1cSXander Huff struct gem_statistic { 8293ff13f1cSXander Huff char stat_string[ETH_GSTRING_LEN]; 8303ff13f1cSXander Huff int offset; 8313ff13f1cSXander Huff u32 stat_bits; 8323ff13f1cSXander Huff }; 8333ff13f1cSXander Huff 8343ff13f1cSXander Huff /* Bitfield defs for net_device_stat statistics */ 8353ff13f1cSXander Huff #define GEM_NDS_RXERR_OFFSET 0 8363ff13f1cSXander Huff #define GEM_NDS_RXLENERR_OFFSET 1 8373ff13f1cSXander Huff #define GEM_NDS_RXOVERERR_OFFSET 2 8383ff13f1cSXander Huff #define GEM_NDS_RXCRCERR_OFFSET 3 8393ff13f1cSXander Huff #define GEM_NDS_RXFRAMEERR_OFFSET 4 8403ff13f1cSXander Huff #define GEM_NDS_RXFIFOERR_OFFSET 5 8413ff13f1cSXander Huff #define GEM_NDS_TXERR_OFFSET 6 8423ff13f1cSXander Huff #define GEM_NDS_TXABORTEDERR_OFFSET 7 8433ff13f1cSXander Huff #define GEM_NDS_TXCARRIERERR_OFFSET 8 8443ff13f1cSXander Huff #define GEM_NDS_TXFIFOERR_OFFSET 9 8453ff13f1cSXander Huff #define GEM_NDS_COLLISIONS_OFFSET 10 8463ff13f1cSXander Huff 8473ff13f1cSXander Huff #define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0) 8483ff13f1cSXander Huff #define GEM_STAT_TITLE_BITS(name, title, bits) { \ 8493ff13f1cSXander Huff .stat_string = title, \ 8503ff13f1cSXander Huff .offset = GEM_##name, \ 8513ff13f1cSXander Huff .stat_bits = bits \ 8523ff13f1cSXander Huff } 8533ff13f1cSXander Huff 8543ff13f1cSXander Huff /* list of gem statistic registers. The names MUST match the 8553ff13f1cSXander Huff * corresponding GEM_* definitions. 8563ff13f1cSXander Huff */ 8573ff13f1cSXander Huff static const struct gem_statistic gem_statistics[] = { 8583ff13f1cSXander Huff GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */ 8593ff13f1cSXander Huff GEM_STAT_TITLE(TXCNT, "tx_frames"), 8603ff13f1cSXander Huff GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"), 8613ff13f1cSXander Huff GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"), 8623ff13f1cSXander Huff GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"), 8633ff13f1cSXander Huff GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"), 8643ff13f1cSXander Huff GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"), 8653ff13f1cSXander Huff GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"), 8663ff13f1cSXander Huff GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"), 8673ff13f1cSXander Huff GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"), 8683ff13f1cSXander Huff GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"), 8693ff13f1cSXander Huff GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"), 8703ff13f1cSXander Huff GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun", 8713ff13f1cSXander Huff GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)), 8723ff13f1cSXander Huff GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames", 8733ff13f1cSXander Huff GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), 8743ff13f1cSXander Huff GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames", 8753ff13f1cSXander Huff GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), 8763ff13f1cSXander Huff GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions", 8773ff13f1cSXander Huff GEM_BIT(NDS_TXERR)| 8783ff13f1cSXander Huff GEM_BIT(NDS_TXABORTEDERR)| 8793ff13f1cSXander Huff GEM_BIT(NDS_COLLISIONS)), 8803ff13f1cSXander Huff GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions", 8813ff13f1cSXander Huff GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), 8823ff13f1cSXander Huff GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"), 8833ff13f1cSXander Huff GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors", 8843ff13f1cSXander Huff GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), 8853ff13f1cSXander Huff GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */ 8863ff13f1cSXander Huff GEM_STAT_TITLE(RXCNT, "rx_frames"), 8873ff13f1cSXander Huff GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"), 8883ff13f1cSXander Huff GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"), 8893ff13f1cSXander Huff GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"), 8903ff13f1cSXander Huff GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"), 8913ff13f1cSXander Huff GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"), 8923ff13f1cSXander Huff GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"), 8933ff13f1cSXander Huff GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"), 8943ff13f1cSXander Huff GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"), 8953ff13f1cSXander Huff GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"), 8963ff13f1cSXander Huff GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"), 8973ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames", 8983ff13f1cSXander Huff GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)), 8993ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames", 9003ff13f1cSXander Huff GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)), 9013ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers", 9023ff13f1cSXander Huff GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)), 9033ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors", 9043ff13f1cSXander Huff GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)), 9053ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors", 9063ff13f1cSXander Huff GEM_BIT(NDS_RXERR)), 9073ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors", 9083ff13f1cSXander Huff GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)), 9093ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors", 9103ff13f1cSXander Huff GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)), 9113ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors", 9123ff13f1cSXander Huff GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)), 9133ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns", 9143ff13f1cSXander Huff GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)), 9153ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors", 9163ff13f1cSXander Huff GEM_BIT(NDS_RXERR)), 9173ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors", 9183ff13f1cSXander Huff GEM_BIT(NDS_RXERR)), 9193ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors", 9203ff13f1cSXander Huff GEM_BIT(NDS_RXERR)), 9213ff13f1cSXander Huff }; 9223ff13f1cSXander Huff 9233ff13f1cSXander Huff #define GEM_STATS_LEN ARRAY_SIZE(gem_statistics) 9243ff13f1cSXander Huff 9254df95131SNicolas Ferre struct macb; 926*ae1f2a56SRafal Ozieblo struct macb_queue; 9274df95131SNicolas Ferre 9284df95131SNicolas Ferre struct macb_or_gem_ops { 9294df95131SNicolas Ferre int (*mog_alloc_rx_buffers)(struct macb *bp); 9304df95131SNicolas Ferre void (*mog_free_rx_buffers)(struct macb *bp); 9314df95131SNicolas Ferre void (*mog_init_rings)(struct macb *bp); 932*ae1f2a56SRafal Ozieblo int (*mog_rx)(struct macb_queue *queue, int budget); 9334df95131SNicolas Ferre }; 9344df95131SNicolas Ferre 935c2594d80SAndrei.Pistirica@microchip.com /* MACB-PTP interface: adapt to platform needs. */ 936c2594d80SAndrei.Pistirica@microchip.com struct macb_ptp_info { 937c2594d80SAndrei.Pistirica@microchip.com void (*ptp_init)(struct net_device *ndev); 938c2594d80SAndrei.Pistirica@microchip.com void (*ptp_remove)(struct net_device *ndev); 939c2594d80SAndrei.Pistirica@microchip.com s32 (*get_ptp_max_adj)(void); 940c2594d80SAndrei.Pistirica@microchip.com unsigned int (*get_tsu_rate)(struct macb *bp); 941c2594d80SAndrei.Pistirica@microchip.com int (*get_ts_info)(struct net_device *dev, 942c2594d80SAndrei.Pistirica@microchip.com struct ethtool_ts_info *info); 943c2594d80SAndrei.Pistirica@microchip.com int (*get_hwtst)(struct net_device *netdev, 944c2594d80SAndrei.Pistirica@microchip.com struct ifreq *ifr); 945c2594d80SAndrei.Pistirica@microchip.com int (*set_hwtst)(struct net_device *netdev, 946c2594d80SAndrei.Pistirica@microchip.com struct ifreq *ifr, int cmd); 947c2594d80SAndrei.Pistirica@microchip.com }; 948c2594d80SAndrei.Pistirica@microchip.com 949e175587fSNicolas Ferre struct macb_config { 950e175587fSNicolas Ferre u32 caps; 951e175587fSNicolas Ferre unsigned int dma_burst_length; 952c69618b3SNicolas Ferre int (*clk_init)(struct platform_device *pdev, struct clk **pclk, 953aead88bdSshubhrajyoti.datta@xilinx.com struct clk **hclk, struct clk **tx_clk, 954aead88bdSshubhrajyoti.datta@xilinx.com struct clk **rx_clk); 955421d9df0SCyrille Pitchen int (*init)(struct platform_device *pdev); 95698b5a0f4SHarini Katakam int jumbo_max_len; 957e175587fSNicolas Ferre }; 958e175587fSNicolas Ferre 959ab91f0a9SRafal Ozieblo struct tsu_incr { 960ab91f0a9SRafal Ozieblo u32 sub_ns; 961ab91f0a9SRafal Ozieblo u32 ns; 962ab91f0a9SRafal Ozieblo }; 963ab91f0a9SRafal Ozieblo 96402c958ddSCyrille Pitchen struct macb_queue { 96502c958ddSCyrille Pitchen struct macb *bp; 96602c958ddSCyrille Pitchen int irq; 96702c958ddSCyrille Pitchen 96802c958ddSCyrille Pitchen unsigned int ISR; 96902c958ddSCyrille Pitchen unsigned int IER; 97002c958ddSCyrille Pitchen unsigned int IDR; 97102c958ddSCyrille Pitchen unsigned int IMR; 97202c958ddSCyrille Pitchen unsigned int TBQP; 973fff8019aSHarini Katakam unsigned int TBQPH; 974*ae1f2a56SRafal Ozieblo unsigned int RBQS; 975*ae1f2a56SRafal Ozieblo unsigned int RBQP; 976*ae1f2a56SRafal Ozieblo unsigned int RBQPH; 97702c958ddSCyrille Pitchen 97802c958ddSCyrille Pitchen unsigned int tx_head, tx_tail; 97902c958ddSCyrille Pitchen struct macb_dma_desc *tx_ring; 98002c958ddSCyrille Pitchen struct macb_tx_skb *tx_skb; 98102c958ddSCyrille Pitchen dma_addr_t tx_ring_dma; 98202c958ddSCyrille Pitchen struct work_struct tx_error_task; 983ab91f0a9SRafal Ozieblo 984*ae1f2a56SRafal Ozieblo dma_addr_t rx_ring_dma; 985*ae1f2a56SRafal Ozieblo dma_addr_t rx_buffers_dma; 986*ae1f2a56SRafal Ozieblo unsigned int rx_tail; 987*ae1f2a56SRafal Ozieblo unsigned int rx_prepared_head; 988*ae1f2a56SRafal Ozieblo struct macb_dma_desc *rx_ring; 989*ae1f2a56SRafal Ozieblo struct sk_buff **rx_skbuff; 990*ae1f2a56SRafal Ozieblo void *rx_buffers; 991*ae1f2a56SRafal Ozieblo struct napi_struct napi; 992*ae1f2a56SRafal Ozieblo 993ab91f0a9SRafal Ozieblo #ifdef CONFIG_MACB_USE_HWSTAMP 994ab91f0a9SRafal Ozieblo struct work_struct tx_ts_task; 995ab91f0a9SRafal Ozieblo unsigned int tx_ts_head, tx_ts_tail; 996ab91f0a9SRafal Ozieblo struct gem_tx_ts tx_timestamps[PTP_TS_BUFFER_SIZE]; 997ab91f0a9SRafal Ozieblo #endif 99802c958ddSCyrille Pitchen }; 99902c958ddSCyrille Pitchen 10009f2f381fSJeff Kirsher struct macb { 10019f2f381fSJeff Kirsher void __iomem *regs; 1002f2ce8a9eSAndy Shevchenko bool native_io; 1003f2ce8a9eSAndy Shevchenko 1004f2ce8a9eSAndy Shevchenko /* hardware IO accessors */ 10057a6e0706SDavid S. Miller u32 (*macb_reg_readl)(struct macb *bp, int offset); 10067a6e0706SDavid S. Miller void (*macb_reg_writel)(struct macb *bp, int offset, u32 value); 10079f2f381fSJeff Kirsher 10081b44791aSNicolas Ferre size_t rx_buffer_size; 10099f2f381fSJeff Kirsher 1010b410d13eSZach Brown unsigned int rx_ring_size; 1011b410d13eSZach Brown unsigned int tx_ring_size; 1012b410d13eSZach Brown 101302c958ddSCyrille Pitchen unsigned int num_queues; 1014bfa0914aSNicolas Ferre unsigned int queue_mask; 101502c958ddSCyrille Pitchen struct macb_queue queues[MACB_MAX_QUEUES]; 10169f2f381fSJeff Kirsher 10179f2f381fSJeff Kirsher spinlock_t lock; 10189f2f381fSJeff Kirsher struct platform_device *pdev; 10199f2f381fSJeff Kirsher struct clk *pclk; 10209f2f381fSJeff Kirsher struct clk *hclk; 1021e1824dfeSSoren Brinkmann struct clk *tx_clk; 1022aead88bdSshubhrajyoti.datta@xilinx.com struct clk *rx_clk; 10239f2f381fSJeff Kirsher struct net_device *dev; 1024a494ed8eSJamie Iles union { 1025a494ed8eSJamie Iles struct macb_stats macb; 1026a494ed8eSJamie Iles struct gem_stats gem; 1027a494ed8eSJamie Iles } hw_stats; 10289f2f381fSJeff Kirsher 10294df95131SNicolas Ferre struct macb_or_gem_ops macbgem_ops; 10304df95131SNicolas Ferre 10319f2f381fSJeff Kirsher struct mii_bus *mii_bus; 1032dacdbb4dSMichael Grzeschik struct device_node *phy_node; 10338bcbf82fSAndy Shevchenko int link; 10348bcbf82fSAndy Shevchenko int speed; 10358bcbf82fSAndy Shevchenko int duplex; 1036fb97a846SJean-Christophe PLAGNIOL-VILLARD 1037581df9e1SNicolas Ferre u32 caps; 1038e175587fSNicolas Ferre unsigned int dma_burst_length; 1039581df9e1SNicolas Ferre 1040fb97a846SJean-Christophe PLAGNIOL-VILLARD phy_interface_t phy_interface; 10415833e052SGregory CLEMENT struct gpio_desc *reset_gpio; 1042b85008b7SJoachim Eastwood 10434dda6f6dSJoachim Eastwood /* AT91RM9200 transmit */ 1044b85008b7SJoachim Eastwood struct sk_buff *skb; /* holds skb until xmit interrupt completes */ 1045b85008b7SJoachim Eastwood dma_addr_t skb_physaddr; /* phys addr from pci_map_single */ 1046b85008b7SJoachim Eastwood int skb_length; /* saved skb length for pci_unmap_single */ 1047a4c35ed3SCyrille Pitchen unsigned int max_tx_length; 10483ff13f1cSXander Huff 10493ff13f1cSXander Huff u64 ethtool_stats[GEM_STATS_LEN]; 105098b5a0f4SHarini Katakam 105198b5a0f4SHarini Katakam unsigned int rx_frm_len_mask; 105298b5a0f4SHarini Katakam unsigned int jumbo_max_len; 10533e2a5e15SSergio Prado 10543e2a5e15SSergio Prado u32 wol; 1055c2594d80SAndrei.Pistirica@microchip.com 1056c2594d80SAndrei.Pistirica@microchip.com struct macb_ptp_info *ptp_info; /* macb-ptp interface */ 10577b429614SRafal Ozieblo #ifdef MACB_EXT_DESC 10587b429614SRafal Ozieblo uint8_t hw_dma_cap; 1059dc97a89eSRafal Ozieblo #endif 1060ab91f0a9SRafal Ozieblo spinlock_t tsu_clk_lock; /* gem tsu clock locking */ 1061ab91f0a9SRafal Ozieblo unsigned int tsu_rate; 1062ab91f0a9SRafal Ozieblo struct ptp_clock *ptp_clock; 1063ab91f0a9SRafal Ozieblo struct ptp_clock_info ptp_clock_info; 1064ab91f0a9SRafal Ozieblo struct tsu_incr tsu_incr; 1065ab91f0a9SRafal Ozieblo struct hwtstamp_config tstamp_config; 10669f2f381fSJeff Kirsher }; 10679f2f381fSJeff Kirsher 1068ab91f0a9SRafal Ozieblo #ifdef CONFIG_MACB_USE_HWSTAMP 1069ab91f0a9SRafal Ozieblo #define GEM_TSEC_SIZE (GEM_TSH_SIZE + GEM_TSL_SIZE) 1070ab91f0a9SRafal Ozieblo #define TSU_SEC_MAX_VAL (((u64)1 << GEM_TSEC_SIZE) - 1) 1071ab91f0a9SRafal Ozieblo #define TSU_NSEC_MAX_VAL ((1 << GEM_TN_SIZE) - 1) 1072ab91f0a9SRafal Ozieblo 1073ab91f0a9SRafal Ozieblo enum macb_bd_control { 1074ab91f0a9SRafal Ozieblo TSTAMP_DISABLED, 1075ab91f0a9SRafal Ozieblo TSTAMP_FRAME_PTP_EVENT_ONLY, 1076ab91f0a9SRafal Ozieblo TSTAMP_ALL_PTP_FRAMES, 1077ab91f0a9SRafal Ozieblo TSTAMP_ALL_FRAMES, 1078ab91f0a9SRafal Ozieblo }; 1079ab91f0a9SRafal Ozieblo 1080ab91f0a9SRafal Ozieblo void gem_ptp_init(struct net_device *ndev); 1081ab91f0a9SRafal Ozieblo void gem_ptp_remove(struct net_device *ndev); 1082ab91f0a9SRafal Ozieblo int gem_ptp_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *des); 1083ab91f0a9SRafal Ozieblo void gem_ptp_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc); 1084ab91f0a9SRafal Ozieblo static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc) 1085ab91f0a9SRafal Ozieblo { 1086ab91f0a9SRafal Ozieblo if (queue->bp->tstamp_config.tx_type == TSTAMP_DISABLED) 1087ab91f0a9SRafal Ozieblo return -ENOTSUPP; 1088ab91f0a9SRafal Ozieblo 1089ab91f0a9SRafal Ozieblo return gem_ptp_txstamp(queue, skb, desc); 1090ab91f0a9SRafal Ozieblo } 1091ab91f0a9SRafal Ozieblo 1092ab91f0a9SRafal Ozieblo static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) 1093ab91f0a9SRafal Ozieblo { 1094ab91f0a9SRafal Ozieblo if (bp->tstamp_config.rx_filter == TSTAMP_DISABLED) 1095ab91f0a9SRafal Ozieblo return; 1096ab91f0a9SRafal Ozieblo 1097ab91f0a9SRafal Ozieblo gem_ptp_rxstamp(bp, skb, desc); 1098ab91f0a9SRafal Ozieblo } 1099ab91f0a9SRafal Ozieblo int gem_get_hwtst(struct net_device *dev, struct ifreq *rq); 1100ab91f0a9SRafal Ozieblo int gem_set_hwtst(struct net_device *dev, struct ifreq *ifr, int cmd); 1101ab91f0a9SRafal Ozieblo #else 1102ab91f0a9SRafal Ozieblo static inline void gem_ptp_init(struct net_device *ndev) { } 1103ab91f0a9SRafal Ozieblo static inline void gem_ptp_remove(struct net_device *ndev) { } 1104ab91f0a9SRafal Ozieblo 1105ab91f0a9SRafal Ozieblo static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc) 1106ab91f0a9SRafal Ozieblo { 1107ab91f0a9SRafal Ozieblo return -1; 1108ab91f0a9SRafal Ozieblo } 1109ab91f0a9SRafal Ozieblo 1110ab91f0a9SRafal Ozieblo static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) { } 1111ab91f0a9SRafal Ozieblo #endif 1112ab91f0a9SRafal Ozieblo 1113f75ba50bSJamie Iles static inline bool macb_is_gem(struct macb *bp) 1114f75ba50bSJamie Iles { 1115e175587fSNicolas Ferre return !!(bp->caps & MACB_CAPS_MACB_IS_GEM); 1116f75ba50bSJamie Iles } 1117f75ba50bSJamie Iles 1118c2594d80SAndrei.Pistirica@microchip.com static inline bool gem_has_ptp(struct macb *bp) 1119c2594d80SAndrei.Pistirica@microchip.com { 1120c2594d80SAndrei.Pistirica@microchip.com return !!(bp->caps & MACB_CAPS_GEM_HAS_PTP); 1121c2594d80SAndrei.Pistirica@microchip.com } 1122c2594d80SAndrei.Pistirica@microchip.com 11239f2f381fSJeff Kirsher #endif /* _MACB_H */ 1124