19f2f381fSJeff Kirsher /* 29f2f381fSJeff Kirsher * Atmel MACB Ethernet Controller driver 39f2f381fSJeff Kirsher * 49f2f381fSJeff Kirsher * Copyright (C) 2004-2006 Atmel Corporation 59f2f381fSJeff Kirsher * 69f2f381fSJeff Kirsher * This program is free software; you can redistribute it and/or modify 79f2f381fSJeff Kirsher * it under the terms of the GNU General Public License version 2 as 89f2f381fSJeff Kirsher * published by the Free Software Foundation. 99f2f381fSJeff Kirsher */ 109f2f381fSJeff Kirsher #ifndef _MACB_H 119f2f381fSJeff Kirsher #define _MACB_H 129f2f381fSJeff Kirsher 13d1d1b53dSNicolas Ferre #define MACB_GREGS_NBR 16 14*7c39994fSNicolas Ferre #define MACB_GREGS_VERSION 2 1502c958ddSCyrille Pitchen #define MACB_MAX_QUEUES 8 16d1d1b53dSNicolas Ferre 179f2f381fSJeff Kirsher /* MACB register offsets */ 185c2fa0f6SXander Huff #define MACB_NCR 0x0000 /* Network Control */ 195c2fa0f6SXander Huff #define MACB_NCFGR 0x0004 /* Network Config */ 205c2fa0f6SXander Huff #define MACB_NSR 0x0008 /* Network Status */ 211fd3ca4eSJoachim Eastwood #define MACB_TAR 0x000c /* AT91RM9200 only */ 221fd3ca4eSJoachim Eastwood #define MACB_TCR 0x0010 /* AT91RM9200 only */ 235c2fa0f6SXander Huff #define MACB_TSR 0x0014 /* Transmit Status */ 245c2fa0f6SXander Huff #define MACB_RBQP 0x0018 /* RX Q Base Address */ 255c2fa0f6SXander Huff #define MACB_TBQP 0x001c /* TX Q Base Address */ 265c2fa0f6SXander Huff #define MACB_RSR 0x0020 /* Receive Status */ 275c2fa0f6SXander Huff #define MACB_ISR 0x0024 /* Interrupt Status */ 285c2fa0f6SXander Huff #define MACB_IER 0x0028 /* Interrupt Enable */ 295c2fa0f6SXander Huff #define MACB_IDR 0x002c /* Interrupt Disable */ 305c2fa0f6SXander Huff #define MACB_IMR 0x0030 /* Interrupt Mask */ 315c2fa0f6SXander Huff #define MACB_MAN 0x0034 /* PHY Maintenance */ 329f2f381fSJeff Kirsher #define MACB_PTR 0x0038 339f2f381fSJeff Kirsher #define MACB_PFR 0x003c 349f2f381fSJeff Kirsher #define MACB_FTO 0x0040 359f2f381fSJeff Kirsher #define MACB_SCF 0x0044 369f2f381fSJeff Kirsher #define MACB_MCF 0x0048 379f2f381fSJeff Kirsher #define MACB_FRO 0x004c 389f2f381fSJeff Kirsher #define MACB_FCSE 0x0050 399f2f381fSJeff Kirsher #define MACB_ALE 0x0054 409f2f381fSJeff Kirsher #define MACB_DTF 0x0058 419f2f381fSJeff Kirsher #define MACB_LCOL 0x005c 429f2f381fSJeff Kirsher #define MACB_EXCOL 0x0060 439f2f381fSJeff Kirsher #define MACB_TUND 0x0064 449f2f381fSJeff Kirsher #define MACB_CSE 0x0068 459f2f381fSJeff Kirsher #define MACB_RRE 0x006c 469f2f381fSJeff Kirsher #define MACB_ROVR 0x0070 479f2f381fSJeff Kirsher #define MACB_RSE 0x0074 489f2f381fSJeff Kirsher #define MACB_ELE 0x0078 499f2f381fSJeff Kirsher #define MACB_RJA 0x007c 509f2f381fSJeff Kirsher #define MACB_USF 0x0080 519f2f381fSJeff Kirsher #define MACB_STE 0x0084 529f2f381fSJeff Kirsher #define MACB_RLE 0x0088 539f2f381fSJeff Kirsher #define MACB_TPF 0x008c 549f2f381fSJeff Kirsher #define MACB_HRB 0x0090 559f2f381fSJeff Kirsher #define MACB_HRT 0x0094 569f2f381fSJeff Kirsher #define MACB_SA1B 0x0098 579f2f381fSJeff Kirsher #define MACB_SA1T 0x009c 589f2f381fSJeff Kirsher #define MACB_SA2B 0x00a0 599f2f381fSJeff Kirsher #define MACB_SA2T 0x00a4 609f2f381fSJeff Kirsher #define MACB_SA3B 0x00a8 619f2f381fSJeff Kirsher #define MACB_SA3T 0x00ac 629f2f381fSJeff Kirsher #define MACB_SA4B 0x00b0 639f2f381fSJeff Kirsher #define MACB_SA4T 0x00b4 649f2f381fSJeff Kirsher #define MACB_TID 0x00b8 659f2f381fSJeff Kirsher #define MACB_TPQ 0x00bc 669f2f381fSJeff Kirsher #define MACB_USRIO 0x00c0 679f2f381fSJeff Kirsher #define MACB_WOL 0x00c4 68f75ba50bSJamie Iles #define MACB_MID 0x00fc 69f75ba50bSJamie Iles 70f75ba50bSJamie Iles /* GEM register offsets. */ 715c2fa0f6SXander Huff #define GEM_NCFGR 0x0004 /* Network Config */ 725c2fa0f6SXander Huff #define GEM_USRIO 0x000c /* User IO */ 735c2fa0f6SXander Huff #define GEM_DMACFG 0x0010 /* DMA Configuration */ 745c2fa0f6SXander Huff #define GEM_HRB 0x0080 /* Hash Bottom */ 755c2fa0f6SXander Huff #define GEM_HRT 0x0084 /* Hash Top */ 765c2fa0f6SXander Huff #define GEM_SA1B 0x0088 /* Specific1 Bottom */ 775c2fa0f6SXander Huff #define GEM_SA1T 0x008C /* Specific1 Top */ 785c2fa0f6SXander Huff #define GEM_SA2B 0x0090 /* Specific2 Bottom */ 795c2fa0f6SXander Huff #define GEM_SA2T 0x0094 /* Specific2 Top */ 805c2fa0f6SXander Huff #define GEM_SA3B 0x0098 /* Specific3 Bottom */ 815c2fa0f6SXander Huff #define GEM_SA3T 0x009C /* Specific3 Top */ 825c2fa0f6SXander Huff #define GEM_SA4B 0x00A0 /* Specific4 Bottom */ 835c2fa0f6SXander Huff #define GEM_SA4T 0x00A4 /* Specific4 Top */ 845c2fa0f6SXander Huff #define GEM_OTX 0x0100 /* Octets transmitted */ 856f79eed8SXander Huff #define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */ 866f79eed8SXander Huff #define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */ 876f79eed8SXander Huff #define GEM_TXCNT 0x0108 /* Frames Transmitted counter */ 886f79eed8SXander Huff #define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */ 896f79eed8SXander Huff #define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */ 906f79eed8SXander Huff #define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */ 916f79eed8SXander Huff #define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */ 926f79eed8SXander Huff #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */ 936f79eed8SXander Huff #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */ 946f79eed8SXander Huff #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */ 956f79eed8SXander Huff #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */ 966f79eed8SXander Huff #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */ 976f79eed8SXander Huff #define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */ 986f79eed8SXander Huff #define GEM_TXURUNCNT 0x0134 /* TX under run error counter */ 996f79eed8SXander Huff #define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */ 1006f79eed8SXander Huff #define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */ 1016f79eed8SXander Huff #define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */ 1026f79eed8SXander Huff #define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */ 1036f79eed8SXander Huff #define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */ 1046f79eed8SXander Huff #define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */ 1053ff13f1cSXander Huff #define GEM_ORX 0x0150 /* Octets received */ 1066f79eed8SXander Huff #define GEM_OCTRXL 0x0150 /* Octets received [31:0] */ 1076f79eed8SXander Huff #define GEM_OCTRXH 0x0154 /* Octets received [47:32] */ 1086f79eed8SXander Huff #define GEM_RXCNT 0x0158 /* Frames Received Counter */ 1096f79eed8SXander Huff #define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */ 1106f79eed8SXander Huff #define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */ 1116f79eed8SXander Huff #define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */ 1126f79eed8SXander Huff #define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */ 1136f79eed8SXander Huff #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */ 1146f79eed8SXander Huff #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */ 1156f79eed8SXander Huff #define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */ 1166f79eed8SXander Huff #define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */ 1176f79eed8SXander Huff #define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */ 1186f79eed8SXander Huff #define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */ 1196f79eed8SXander Huff #define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */ 1206f79eed8SXander Huff #define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */ 1216f79eed8SXander Huff #define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */ 1226f79eed8SXander Huff #define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */ 1236f79eed8SXander Huff #define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */ 1246f79eed8SXander Huff #define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */ 1256f79eed8SXander Huff #define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */ 1266f79eed8SXander Huff #define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */ 1276f79eed8SXander Huff #define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */ 1286f79eed8SXander Huff #define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */ 1296f79eed8SXander Huff #define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */ 1306f79eed8SXander Huff #define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */ 1315c2fa0f6SXander Huff #define GEM_DCFG1 0x0280 /* Design Config 1 */ 1325c2fa0f6SXander Huff #define GEM_DCFG2 0x0284 /* Design Config 2 */ 1335c2fa0f6SXander Huff #define GEM_DCFG3 0x0288 /* Design Config 3 */ 1345c2fa0f6SXander Huff #define GEM_DCFG4 0x028c /* Design Config 4 */ 1355c2fa0f6SXander Huff #define GEM_DCFG5 0x0290 /* Design Config 5 */ 1365c2fa0f6SXander Huff #define GEM_DCFG6 0x0294 /* Design Config 6 */ 1375c2fa0f6SXander Huff #define GEM_DCFG7 0x0298 /* Design Config 7 */ 1389f2f381fSJeff Kirsher 13902c958ddSCyrille Pitchen #define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2)) 14002c958ddSCyrille Pitchen #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2)) 14102c958ddSCyrille Pitchen #define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2)) 14202c958ddSCyrille Pitchen #define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2)) 14302c958ddSCyrille Pitchen #define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2)) 14402c958ddSCyrille Pitchen #define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2)) 14502c958ddSCyrille Pitchen 1469f2f381fSJeff Kirsher /* Bitfields in NCR */ 1475c2fa0f6SXander Huff #define MACB_LB_OFFSET 0 /* reserved */ 1489f2f381fSJeff Kirsher #define MACB_LB_SIZE 1 1495c2fa0f6SXander Huff #define MACB_LLB_OFFSET 1 /* Loop back local */ 1509f2f381fSJeff Kirsher #define MACB_LLB_SIZE 1 1515c2fa0f6SXander Huff #define MACB_RE_OFFSET 2 /* Receive enable */ 1529f2f381fSJeff Kirsher #define MACB_RE_SIZE 1 1535c2fa0f6SXander Huff #define MACB_TE_OFFSET 3 /* Transmit enable */ 1549f2f381fSJeff Kirsher #define MACB_TE_SIZE 1 1555c2fa0f6SXander Huff #define MACB_MPE_OFFSET 4 /* Management port enable */ 1569f2f381fSJeff Kirsher #define MACB_MPE_SIZE 1 1575c2fa0f6SXander Huff #define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */ 1589f2f381fSJeff Kirsher #define MACB_CLRSTAT_SIZE 1 1595c2fa0f6SXander Huff #define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */ 1609f2f381fSJeff Kirsher #define MACB_INCSTAT_SIZE 1 1615c2fa0f6SXander Huff #define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */ 1629f2f381fSJeff Kirsher #define MACB_WESTAT_SIZE 1 1635c2fa0f6SXander Huff #define MACB_BP_OFFSET 8 /* Back pressure */ 1649f2f381fSJeff Kirsher #define MACB_BP_SIZE 1 1655c2fa0f6SXander Huff #define MACB_TSTART_OFFSET 9 /* Start transmission */ 1669f2f381fSJeff Kirsher #define MACB_TSTART_SIZE 1 1675c2fa0f6SXander Huff #define MACB_THALT_OFFSET 10 /* Transmit halt */ 1689f2f381fSJeff Kirsher #define MACB_THALT_SIZE 1 1695c2fa0f6SXander Huff #define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */ 1709f2f381fSJeff Kirsher #define MACB_NCR_TPF_SIZE 1 1716f79eed8SXander Huff #define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */ 1729f2f381fSJeff Kirsher #define MACB_TZQ_SIZE 1 1739f2f381fSJeff Kirsher 1749f2f381fSJeff Kirsher /* Bitfields in NCFGR */ 1755c2fa0f6SXander Huff #define MACB_SPD_OFFSET 0 /* Speed */ 1769f2f381fSJeff Kirsher #define MACB_SPD_SIZE 1 1775c2fa0f6SXander Huff #define MACB_FD_OFFSET 1 /* Full duplex */ 1789f2f381fSJeff Kirsher #define MACB_FD_SIZE 1 1795c2fa0f6SXander Huff #define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */ 1809f2f381fSJeff Kirsher #define MACB_BIT_RATE_SIZE 1 1815c2fa0f6SXander Huff #define MACB_JFRAME_OFFSET 3 /* reserved */ 1829f2f381fSJeff Kirsher #define MACB_JFRAME_SIZE 1 1835c2fa0f6SXander Huff #define MACB_CAF_OFFSET 4 /* Copy all frames */ 1849f2f381fSJeff Kirsher #define MACB_CAF_SIZE 1 1855c2fa0f6SXander Huff #define MACB_NBC_OFFSET 5 /* No broadcast */ 1869f2f381fSJeff Kirsher #define MACB_NBC_SIZE 1 1875c2fa0f6SXander Huff #define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */ 1889f2f381fSJeff Kirsher #define MACB_NCFGR_MTI_SIZE 1 1895c2fa0f6SXander Huff #define MACB_UNI_OFFSET 7 /* Unicast hash enable */ 1909f2f381fSJeff Kirsher #define MACB_UNI_SIZE 1 1915c2fa0f6SXander Huff #define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */ 1929f2f381fSJeff Kirsher #define MACB_BIG_SIZE 1 1936f79eed8SXander Huff #define MACB_EAE_OFFSET 9 /* External address match enable */ 1949f2f381fSJeff Kirsher #define MACB_EAE_SIZE 1 1959f2f381fSJeff Kirsher #define MACB_CLK_OFFSET 10 1969f2f381fSJeff Kirsher #define MACB_CLK_SIZE 2 1975c2fa0f6SXander Huff #define MACB_RTY_OFFSET 12 /* Retry test */ 1989f2f381fSJeff Kirsher #define MACB_RTY_SIZE 1 1995c2fa0f6SXander Huff #define MACB_PAE_OFFSET 13 /* Pause enable */ 2009f2f381fSJeff Kirsher #define MACB_PAE_SIZE 1 2011fd3ca4eSJoachim Eastwood #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */ 2021fd3ca4eSJoachim Eastwood #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */ 2035c2fa0f6SXander Huff #define MACB_RBOF_OFFSET 14 /* Receive buffer offset */ 2049f2f381fSJeff Kirsher #define MACB_RBOF_SIZE 2 2056f79eed8SXander Huff #define MACB_RLCE_OFFSET 16 /* Length field error frame discard */ 2069f2f381fSJeff Kirsher #define MACB_RLCE_SIZE 1 2075c2fa0f6SXander Huff #define MACB_DRFCS_OFFSET 17 /* FCS remove */ 2089f2f381fSJeff Kirsher #define MACB_DRFCS_SIZE 1 2099f2f381fSJeff Kirsher #define MACB_EFRHD_OFFSET 18 2109f2f381fSJeff Kirsher #define MACB_EFRHD_SIZE 1 2119f2f381fSJeff Kirsher #define MACB_IRXFCS_OFFSET 19 2129f2f381fSJeff Kirsher #define MACB_IRXFCS_SIZE 1 2139f2f381fSJeff Kirsher 21470c9f3d4SJamie Iles /* GEM specific NCFGR bitfields. */ 2155c2fa0f6SXander Huff #define GEM_GBE_OFFSET 10 /* Gigabit mode enable */ 216140b7552SPatrice Vilchez #define GEM_GBE_SIZE 1 2175c2fa0f6SXander Huff #define GEM_CLK_OFFSET 18 /* MDC clock division */ 21870c9f3d4SJamie Iles #define GEM_CLK_SIZE 3 2195c2fa0f6SXander Huff #define GEM_DBW_OFFSET 21 /* Data bus width */ 220757a03c6SJamie Iles #define GEM_DBW_SIZE 2 221924ec53cSCyrille Pitchen #define GEM_RXCOEN_OFFSET 24 222924ec53cSCyrille Pitchen #define GEM_RXCOEN_SIZE 1 223757a03c6SJamie Iles 224757a03c6SJamie Iles /* Constants for data bus width. */ 2256f79eed8SXander Huff #define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */ 2266f79eed8SXander Huff #define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */ 2276f79eed8SXander Huff #define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */ 228757a03c6SJamie Iles 2290116da4fSJamie Iles /* Bitfields in DMACFG. */ 2306f79eed8SXander Huff #define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */ 231b3e3bd71SNicolas Ferre #define GEM_FBLDO_SIZE 5 232a50dad35SArun Chandran #define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */ 233ea373041SArun Chandran #define GEM_ENDIA_DESC_SIZE 1 234a50dad35SArun Chandran #define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */ 235ea373041SArun Chandran #define GEM_ENDIA_PKT_SIZE 1 2366f79eed8SXander Huff #define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */ 237b3e3bd71SNicolas Ferre #define GEM_RXBMS_SIZE 2 2386f79eed8SXander Huff #define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */ 239b3e3bd71SNicolas Ferre #define GEM_TXPBMS_SIZE 1 2406f79eed8SXander Huff #define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */ 241b3e3bd71SNicolas Ferre #define GEM_TXCOEN_SIZE 1 2426f79eed8SXander Huff #define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */ 2430116da4fSJamie Iles #define GEM_RXBS_SIZE 8 2445c2fa0f6SXander Huff #define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */ 245b3e3bd71SNicolas Ferre #define GEM_DDRP_SIZE 1 246b3e3bd71SNicolas Ferre 2470116da4fSJamie Iles 2489f2f381fSJeff Kirsher /* Bitfields in NSR */ 2495c2fa0f6SXander Huff #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */ 2509f2f381fSJeff Kirsher #define MACB_NSR_LINK_SIZE 1 2516f79eed8SXander Huff #define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */ 2529f2f381fSJeff Kirsher #define MACB_MDIO_SIZE 1 2536f79eed8SXander Huff #define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */ 2549f2f381fSJeff Kirsher #define MACB_IDLE_SIZE 1 2559f2f381fSJeff Kirsher 2569f2f381fSJeff Kirsher /* Bitfields in TSR */ 2575c2fa0f6SXander Huff #define MACB_UBR_OFFSET 0 /* Used bit read */ 2589f2f381fSJeff Kirsher #define MACB_UBR_SIZE 1 2595c2fa0f6SXander Huff #define MACB_COL_OFFSET 1 /* Collision occurred */ 2609f2f381fSJeff Kirsher #define MACB_COL_SIZE 1 2615c2fa0f6SXander Huff #define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */ 2629f2f381fSJeff Kirsher #define MACB_TSR_RLE_SIZE 1 2635c2fa0f6SXander Huff #define MACB_TGO_OFFSET 3 /* Transmit go */ 2649f2f381fSJeff Kirsher #define MACB_TGO_SIZE 1 2656f79eed8SXander Huff #define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */ 2669f2f381fSJeff Kirsher #define MACB_BEX_SIZE 1 2671fd3ca4eSJoachim Eastwood #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */ 2681fd3ca4eSJoachim Eastwood #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */ 2695c2fa0f6SXander Huff #define MACB_COMP_OFFSET 5 /* Trnasmit complete */ 2709f2f381fSJeff Kirsher #define MACB_COMP_SIZE 1 2715c2fa0f6SXander Huff #define MACB_UND_OFFSET 6 /* Trnasmit under run */ 2729f2f381fSJeff Kirsher #define MACB_UND_SIZE 1 2739f2f381fSJeff Kirsher 2749f2f381fSJeff Kirsher /* Bitfields in RSR */ 2755c2fa0f6SXander Huff #define MACB_BNA_OFFSET 0 /* Buffer not available */ 2769f2f381fSJeff Kirsher #define MACB_BNA_SIZE 1 2775c2fa0f6SXander Huff #define MACB_REC_OFFSET 1 /* Frame received */ 2789f2f381fSJeff Kirsher #define MACB_REC_SIZE 1 2795c2fa0f6SXander Huff #define MACB_OVR_OFFSET 2 /* Receive overrun */ 2809f2f381fSJeff Kirsher #define MACB_OVR_SIZE 1 2819f2f381fSJeff Kirsher 2829f2f381fSJeff Kirsher /* Bitfields in ISR/IER/IDR/IMR */ 2835c2fa0f6SXander Huff #define MACB_MFD_OFFSET 0 /* Management frame sent */ 2849f2f381fSJeff Kirsher #define MACB_MFD_SIZE 1 2855c2fa0f6SXander Huff #define MACB_RCOMP_OFFSET 1 /* Receive complete */ 2869f2f381fSJeff Kirsher #define MACB_RCOMP_SIZE 1 2875c2fa0f6SXander Huff #define MACB_RXUBR_OFFSET 2 /* RX used bit read */ 2889f2f381fSJeff Kirsher #define MACB_RXUBR_SIZE 1 2895c2fa0f6SXander Huff #define MACB_TXUBR_OFFSET 3 /* TX used bit read */ 2909f2f381fSJeff Kirsher #define MACB_TXUBR_SIZE 1 2916f79eed8SXander Huff #define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */ 2929f2f381fSJeff Kirsher #define MACB_ISR_TUND_SIZE 1 2936f79eed8SXander Huff #define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */ 2949f2f381fSJeff Kirsher #define MACB_ISR_RLE_SIZE 1 2956f79eed8SXander Huff #define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */ 2969f2f381fSJeff Kirsher #define MACB_TXERR_SIZE 1 2976f79eed8SXander Huff #define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */ 2989f2f381fSJeff Kirsher #define MACB_TCOMP_SIZE 1 2996f79eed8SXander Huff #define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */ 3009f2f381fSJeff Kirsher #define MACB_ISR_LINK_SIZE 1 3016f79eed8SXander Huff #define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */ 3029f2f381fSJeff Kirsher #define MACB_ISR_ROVR_SIZE 1 3036f79eed8SXander Huff #define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */ 3049f2f381fSJeff Kirsher #define MACB_HRESP_SIZE 1 3056f79eed8SXander Huff #define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */ 3069f2f381fSJeff Kirsher #define MACB_PFR_SIZE 1 3076f79eed8SXander Huff #define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */ 3089f2f381fSJeff Kirsher #define MACB_PTZ_SIZE 1 3099f2f381fSJeff Kirsher 3109f2f381fSJeff Kirsher /* Bitfields in MAN */ 3115c2fa0f6SXander Huff #define MACB_DATA_OFFSET 0 /* data */ 3129f2f381fSJeff Kirsher #define MACB_DATA_SIZE 16 3135c2fa0f6SXander Huff #define MACB_CODE_OFFSET 16 /* Must be written to 10 */ 3149f2f381fSJeff Kirsher #define MACB_CODE_SIZE 2 3155c2fa0f6SXander Huff #define MACB_REGA_OFFSET 18 /* Register address */ 3169f2f381fSJeff Kirsher #define MACB_REGA_SIZE 5 3175c2fa0f6SXander Huff #define MACB_PHYA_OFFSET 23 /* PHY address */ 3189f2f381fSJeff Kirsher #define MACB_PHYA_SIZE 5 3196f79eed8SXander Huff #define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */ 3209f2f381fSJeff Kirsher #define MACB_RW_SIZE 2 3216f79eed8SXander Huff #define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */ 3229f2f381fSJeff Kirsher #define MACB_SOF_SIZE 2 3239f2f381fSJeff Kirsher 3249f2f381fSJeff Kirsher /* Bitfields in USRIO (AVR32) */ 3259f2f381fSJeff Kirsher #define MACB_MII_OFFSET 0 3269f2f381fSJeff Kirsher #define MACB_MII_SIZE 1 3279f2f381fSJeff Kirsher #define MACB_EAM_OFFSET 1 3289f2f381fSJeff Kirsher #define MACB_EAM_SIZE 1 3299f2f381fSJeff Kirsher #define MACB_TX_PAUSE_OFFSET 2 3309f2f381fSJeff Kirsher #define MACB_TX_PAUSE_SIZE 1 3319f2f381fSJeff Kirsher #define MACB_TX_PAUSE_ZERO_OFFSET 3 3329f2f381fSJeff Kirsher #define MACB_TX_PAUSE_ZERO_SIZE 1 3339f2f381fSJeff Kirsher 3349f2f381fSJeff Kirsher /* Bitfields in USRIO (AT91) */ 3359f2f381fSJeff Kirsher #define MACB_RMII_OFFSET 0 3369f2f381fSJeff Kirsher #define MACB_RMII_SIZE 1 337140b7552SPatrice Vilchez #define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */ 338140b7552SPatrice Vilchez #define GEM_RGMII_SIZE 1 3399f2f381fSJeff Kirsher #define MACB_CLKEN_OFFSET 1 3409f2f381fSJeff Kirsher #define MACB_CLKEN_SIZE 1 3419f2f381fSJeff Kirsher 3429f2f381fSJeff Kirsher /* Bitfields in WOL */ 3439f2f381fSJeff Kirsher #define MACB_IP_OFFSET 0 3449f2f381fSJeff Kirsher #define MACB_IP_SIZE 16 3459f2f381fSJeff Kirsher #define MACB_MAG_OFFSET 16 3469f2f381fSJeff Kirsher #define MACB_MAG_SIZE 1 3479f2f381fSJeff Kirsher #define MACB_ARP_OFFSET 17 3489f2f381fSJeff Kirsher #define MACB_ARP_SIZE 1 3499f2f381fSJeff Kirsher #define MACB_SA1_OFFSET 18 3509f2f381fSJeff Kirsher #define MACB_SA1_SIZE 1 3519f2f381fSJeff Kirsher #define MACB_WOL_MTI_OFFSET 19 3529f2f381fSJeff Kirsher #define MACB_WOL_MTI_SIZE 1 3539f2f381fSJeff Kirsher 354f75ba50bSJamie Iles /* Bitfields in MID */ 355f75ba50bSJamie Iles #define MACB_IDNUM_OFFSET 16 356d941bebfSPunnaiah Choudary Kalluri #define MACB_IDNUM_SIZE 12 357f75ba50bSJamie Iles #define MACB_REV_OFFSET 0 358f75ba50bSJamie Iles #define MACB_REV_SIZE 16 359f75ba50bSJamie Iles 360757a03c6SJamie Iles /* Bitfields in DCFG1. */ 361581df9e1SNicolas Ferre #define GEM_IRQCOR_OFFSET 23 362581df9e1SNicolas Ferre #define GEM_IRQCOR_SIZE 1 363757a03c6SJamie Iles #define GEM_DBWDEF_OFFSET 25 364757a03c6SJamie Iles #define GEM_DBWDEF_SIZE 3 365757a03c6SJamie Iles 366e175587fSNicolas Ferre /* Bitfields in DCFG2. */ 367e175587fSNicolas Ferre #define GEM_RX_PKT_BUFF_OFFSET 20 368e175587fSNicolas Ferre #define GEM_RX_PKT_BUFF_SIZE 1 369e175587fSNicolas Ferre #define GEM_TX_PKT_BUFF_OFFSET 21 370e175587fSNicolas Ferre #define GEM_TX_PKT_BUFF_SIZE 1 371e175587fSNicolas Ferre 3729f2f381fSJeff Kirsher /* Constants for CLK */ 3739f2f381fSJeff Kirsher #define MACB_CLK_DIV8 0 3749f2f381fSJeff Kirsher #define MACB_CLK_DIV16 1 3759f2f381fSJeff Kirsher #define MACB_CLK_DIV32 2 3769f2f381fSJeff Kirsher #define MACB_CLK_DIV64 3 3779f2f381fSJeff Kirsher 37870c9f3d4SJamie Iles /* GEM specific constants for CLK. */ 37970c9f3d4SJamie Iles #define GEM_CLK_DIV8 0 38070c9f3d4SJamie Iles #define GEM_CLK_DIV16 1 38170c9f3d4SJamie Iles #define GEM_CLK_DIV32 2 38270c9f3d4SJamie Iles #define GEM_CLK_DIV48 3 38370c9f3d4SJamie Iles #define GEM_CLK_DIV64 4 38470c9f3d4SJamie Iles #define GEM_CLK_DIV96 5 38570c9f3d4SJamie Iles 3869f2f381fSJeff Kirsher /* Constants for MAN register */ 3879f2f381fSJeff Kirsher #define MACB_MAN_SOF 1 3889f2f381fSJeff Kirsher #define MACB_MAN_WRITE 1 3899f2f381fSJeff Kirsher #define MACB_MAN_READ 2 3909f2f381fSJeff Kirsher #define MACB_MAN_CODE 2 3919f2f381fSJeff Kirsher 392581df9e1SNicolas Ferre /* Capability mask bits */ 393e175587fSNicolas Ferre #define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001 394a8487489SBoris BREZILLON #define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002 395a8487489SBoris BREZILLON #define MACB_CAPS_USRIO_DEFAULT_IS_MII 0x00000004 396e175587fSNicolas Ferre #define MACB_CAPS_FIFO_MODE 0x10000000 397e175587fSNicolas Ferre #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000 398a4c35ed3SCyrille Pitchen #define MACB_CAPS_SG_DISABLED 0x40000000 399e175587fSNicolas Ferre #define MACB_CAPS_MACB_IS_GEM 0x80000000 400581df9e1SNicolas Ferre 4019f2f381fSJeff Kirsher /* Bit manipulation macros */ 4029f2f381fSJeff Kirsher #define MACB_BIT(name) \ 4039f2f381fSJeff Kirsher (1 << MACB_##name##_OFFSET) 4049f2f381fSJeff Kirsher #define MACB_BF(name,value) \ 4059f2f381fSJeff Kirsher (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ 4069f2f381fSJeff Kirsher << MACB_##name##_OFFSET) 4079f2f381fSJeff Kirsher #define MACB_BFEXT(name,value)\ 4089f2f381fSJeff Kirsher (((value) >> MACB_##name##_OFFSET) \ 4099f2f381fSJeff Kirsher & ((1 << MACB_##name##_SIZE) - 1)) 4109f2f381fSJeff Kirsher #define MACB_BFINS(name,value,old) \ 4119f2f381fSJeff Kirsher (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ 4129f2f381fSJeff Kirsher << MACB_##name##_OFFSET)) \ 4139f2f381fSJeff Kirsher | MACB_BF(name,value)) 4149f2f381fSJeff Kirsher 415f75ba50bSJamie Iles #define GEM_BIT(name) \ 416f75ba50bSJamie Iles (1 << GEM_##name##_OFFSET) 417f75ba50bSJamie Iles #define GEM_BF(name, value) \ 418f75ba50bSJamie Iles (((value) & ((1 << GEM_##name##_SIZE) - 1)) \ 419f75ba50bSJamie Iles << GEM_##name##_OFFSET) 420f75ba50bSJamie Iles #define GEM_BFEXT(name, value)\ 421f75ba50bSJamie Iles (((value) >> GEM_##name##_OFFSET) \ 422f75ba50bSJamie Iles & ((1 << GEM_##name##_SIZE) - 1)) 423f75ba50bSJamie Iles #define GEM_BFINS(name, value, old) \ 424f75ba50bSJamie Iles (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \ 425f75ba50bSJamie Iles << GEM_##name##_OFFSET)) \ 426f75ba50bSJamie Iles | GEM_BF(name, value)) 427f75ba50bSJamie Iles 4289f2f381fSJeff Kirsher /* Register access macros */ 4299f2f381fSJeff Kirsher #define macb_readl(port,reg) \ 430a50dad35SArun Chandran readl_relaxed((port)->regs + MACB_##reg) 4319f2f381fSJeff Kirsher #define macb_writel(port,reg,value) \ 432a50dad35SArun Chandran writel_relaxed((value), (port)->regs + MACB_##reg) 433f75ba50bSJamie Iles #define gem_readl(port, reg) \ 434a50dad35SArun Chandran readl_relaxed((port)->regs + GEM_##reg) 435f75ba50bSJamie Iles #define gem_writel(port, reg, value) \ 436a50dad35SArun Chandran writel_relaxed((value), (port)->regs + GEM_##reg) 43702c958ddSCyrille Pitchen #define queue_readl(queue, reg) \ 438a50dad35SArun Chandran readl_relaxed((queue)->bp->regs + (queue)->reg) 43902c958ddSCyrille Pitchen #define queue_writel(queue, reg, value) \ 440a50dad35SArun Chandran writel_relaxed((value), (queue)->bp->regs + (queue)->reg) 441f75ba50bSJamie Iles 4426f79eed8SXander Huff /* Conditional GEM/MACB macros. These perform the operation to the correct 443f75ba50bSJamie Iles * register dependent on whether the device is a GEM or a MACB. For registers 444f75ba50bSJamie Iles * and bitfields that are common across both devices, use macb_{read,write}l 445f75ba50bSJamie Iles * to avoid the cost of the conditional. 446f75ba50bSJamie Iles */ 447f75ba50bSJamie Iles #define macb_or_gem_writel(__bp, __reg, __value) \ 448f75ba50bSJamie Iles ({ \ 449f75ba50bSJamie Iles if (macb_is_gem((__bp))) \ 450f75ba50bSJamie Iles gem_writel((__bp), __reg, __value); \ 451f75ba50bSJamie Iles else \ 452f75ba50bSJamie Iles macb_writel((__bp), __reg, __value); \ 453f75ba50bSJamie Iles }) 454f75ba50bSJamie Iles 455f75ba50bSJamie Iles #define macb_or_gem_readl(__bp, __reg) \ 456f75ba50bSJamie Iles ({ \ 457f75ba50bSJamie Iles u32 __v; \ 458f75ba50bSJamie Iles if (macb_is_gem((__bp))) \ 459f75ba50bSJamie Iles __v = gem_readl((__bp), __reg); \ 460f75ba50bSJamie Iles else \ 461f75ba50bSJamie Iles __v = macb_readl((__bp), __reg); \ 462f75ba50bSJamie Iles __v; \ 463f75ba50bSJamie Iles }) 4649f2f381fSJeff Kirsher 4656f79eed8SXander Huff /* struct macb_dma_desc - Hardware DMA descriptor 46655054a16SHavard Skinnemoen * @addr: DMA address of data buffer 46755054a16SHavard Skinnemoen * @ctrl: Control and status bits 46855054a16SHavard Skinnemoen */ 46955054a16SHavard Skinnemoen struct macb_dma_desc { 4709f2f381fSJeff Kirsher u32 addr; 4719f2f381fSJeff Kirsher u32 ctrl; 4729f2f381fSJeff Kirsher }; 4739f2f381fSJeff Kirsher 4749f2f381fSJeff Kirsher /* DMA descriptor bitfields */ 4759f2f381fSJeff Kirsher #define MACB_RX_USED_OFFSET 0 4769f2f381fSJeff Kirsher #define MACB_RX_USED_SIZE 1 4779f2f381fSJeff Kirsher #define MACB_RX_WRAP_OFFSET 1 4789f2f381fSJeff Kirsher #define MACB_RX_WRAP_SIZE 1 4799f2f381fSJeff Kirsher #define MACB_RX_WADDR_OFFSET 2 4809f2f381fSJeff Kirsher #define MACB_RX_WADDR_SIZE 30 4819f2f381fSJeff Kirsher 4829f2f381fSJeff Kirsher #define MACB_RX_FRMLEN_OFFSET 0 4839f2f381fSJeff Kirsher #define MACB_RX_FRMLEN_SIZE 12 4849f2f381fSJeff Kirsher #define MACB_RX_OFFSET_OFFSET 12 4859f2f381fSJeff Kirsher #define MACB_RX_OFFSET_SIZE 2 4869f2f381fSJeff Kirsher #define MACB_RX_SOF_OFFSET 14 4879f2f381fSJeff Kirsher #define MACB_RX_SOF_SIZE 1 4889f2f381fSJeff Kirsher #define MACB_RX_EOF_OFFSET 15 4899f2f381fSJeff Kirsher #define MACB_RX_EOF_SIZE 1 4909f2f381fSJeff Kirsher #define MACB_RX_CFI_OFFSET 16 4919f2f381fSJeff Kirsher #define MACB_RX_CFI_SIZE 1 4929f2f381fSJeff Kirsher #define MACB_RX_VLAN_PRI_OFFSET 17 4939f2f381fSJeff Kirsher #define MACB_RX_VLAN_PRI_SIZE 3 4949f2f381fSJeff Kirsher #define MACB_RX_PRI_TAG_OFFSET 20 4959f2f381fSJeff Kirsher #define MACB_RX_PRI_TAG_SIZE 1 4969f2f381fSJeff Kirsher #define MACB_RX_VLAN_TAG_OFFSET 21 4979f2f381fSJeff Kirsher #define MACB_RX_VLAN_TAG_SIZE 1 4989f2f381fSJeff Kirsher #define MACB_RX_TYPEID_MATCH_OFFSET 22 4999f2f381fSJeff Kirsher #define MACB_RX_TYPEID_MATCH_SIZE 1 5009f2f381fSJeff Kirsher #define MACB_RX_SA4_MATCH_OFFSET 23 5019f2f381fSJeff Kirsher #define MACB_RX_SA4_MATCH_SIZE 1 5029f2f381fSJeff Kirsher #define MACB_RX_SA3_MATCH_OFFSET 24 5039f2f381fSJeff Kirsher #define MACB_RX_SA3_MATCH_SIZE 1 5049f2f381fSJeff Kirsher #define MACB_RX_SA2_MATCH_OFFSET 25 5059f2f381fSJeff Kirsher #define MACB_RX_SA2_MATCH_SIZE 1 5069f2f381fSJeff Kirsher #define MACB_RX_SA1_MATCH_OFFSET 26 5079f2f381fSJeff Kirsher #define MACB_RX_SA1_MATCH_SIZE 1 5089f2f381fSJeff Kirsher #define MACB_RX_EXT_MATCH_OFFSET 28 5099f2f381fSJeff Kirsher #define MACB_RX_EXT_MATCH_SIZE 1 5109f2f381fSJeff Kirsher #define MACB_RX_UHASH_MATCH_OFFSET 29 5119f2f381fSJeff Kirsher #define MACB_RX_UHASH_MATCH_SIZE 1 5129f2f381fSJeff Kirsher #define MACB_RX_MHASH_MATCH_OFFSET 30 5139f2f381fSJeff Kirsher #define MACB_RX_MHASH_MATCH_SIZE 1 5149f2f381fSJeff Kirsher #define MACB_RX_BROADCAST_OFFSET 31 5159f2f381fSJeff Kirsher #define MACB_RX_BROADCAST_SIZE 1 5169f2f381fSJeff Kirsher 517924ec53cSCyrille Pitchen /* RX checksum offload disabled: bit 24 clear in NCFGR */ 518924ec53cSCyrille Pitchen #define GEM_RX_TYPEID_MATCH_OFFSET 22 519924ec53cSCyrille Pitchen #define GEM_RX_TYPEID_MATCH_SIZE 2 520924ec53cSCyrille Pitchen 521924ec53cSCyrille Pitchen /* RX checksum offload enabled: bit 24 set in NCFGR */ 522924ec53cSCyrille Pitchen #define GEM_RX_CSUM_OFFSET 22 523924ec53cSCyrille Pitchen #define GEM_RX_CSUM_SIZE 2 524924ec53cSCyrille Pitchen 5259f2f381fSJeff Kirsher #define MACB_TX_FRMLEN_OFFSET 0 5269f2f381fSJeff Kirsher #define MACB_TX_FRMLEN_SIZE 11 5279f2f381fSJeff Kirsher #define MACB_TX_LAST_OFFSET 15 5289f2f381fSJeff Kirsher #define MACB_TX_LAST_SIZE 1 5299f2f381fSJeff Kirsher #define MACB_TX_NOCRC_OFFSET 16 5309f2f381fSJeff Kirsher #define MACB_TX_NOCRC_SIZE 1 5319f2f381fSJeff Kirsher #define MACB_TX_BUF_EXHAUSTED_OFFSET 27 5329f2f381fSJeff Kirsher #define MACB_TX_BUF_EXHAUSTED_SIZE 1 5339f2f381fSJeff Kirsher #define MACB_TX_UNDERRUN_OFFSET 28 5349f2f381fSJeff Kirsher #define MACB_TX_UNDERRUN_SIZE 1 5359f2f381fSJeff Kirsher #define MACB_TX_ERROR_OFFSET 29 5369f2f381fSJeff Kirsher #define MACB_TX_ERROR_SIZE 1 5379f2f381fSJeff Kirsher #define MACB_TX_WRAP_OFFSET 30 5389f2f381fSJeff Kirsher #define MACB_TX_WRAP_SIZE 1 5399f2f381fSJeff Kirsher #define MACB_TX_USED_OFFSET 31 5409f2f381fSJeff Kirsher #define MACB_TX_USED_SIZE 1 5419f2f381fSJeff Kirsher 542a4c35ed3SCyrille Pitchen #define GEM_TX_FRMLEN_OFFSET 0 543a4c35ed3SCyrille Pitchen #define GEM_TX_FRMLEN_SIZE 14 544a4c35ed3SCyrille Pitchen 545924ec53cSCyrille Pitchen /* Buffer descriptor constants */ 546924ec53cSCyrille Pitchen #define GEM_RX_CSUM_NONE 0 547924ec53cSCyrille Pitchen #define GEM_RX_CSUM_IP_ONLY 1 548924ec53cSCyrille Pitchen #define GEM_RX_CSUM_IP_TCP 2 549924ec53cSCyrille Pitchen #define GEM_RX_CSUM_IP_UDP 3 550924ec53cSCyrille Pitchen 551924ec53cSCyrille Pitchen /* limit RX checksum offload to TCP and UDP packets */ 552924ec53cSCyrille Pitchen #define GEM_RX_CSUM_CHECKED_MASK 2 553924ec53cSCyrille Pitchen 5546f79eed8SXander Huff /* struct macb_tx_skb - data about an skb which is being transmitted 555a4c35ed3SCyrille Pitchen * @skb: skb currently being transmitted, only set for the last buffer 556a4c35ed3SCyrille Pitchen * of the frame 557a4c35ed3SCyrille Pitchen * @mapping: DMA address of the skb's fragment buffer 558a4c35ed3SCyrille Pitchen * @size: size of the DMA mapped buffer 559a4c35ed3SCyrille Pitchen * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(), 560a4c35ed3SCyrille Pitchen * false when buffer was mapped with dma_map_single() 56155054a16SHavard Skinnemoen */ 56255054a16SHavard Skinnemoen struct macb_tx_skb { 5639f2f381fSJeff Kirsher struct sk_buff *skb; 5649f2f381fSJeff Kirsher dma_addr_t mapping; 565a4c35ed3SCyrille Pitchen size_t size; 566a4c35ed3SCyrille Pitchen bool mapped_as_page; 5679f2f381fSJeff Kirsher }; 5689f2f381fSJeff Kirsher 5696f79eed8SXander Huff /* Hardware-collected statistics. Used when updating the network 5709f2f381fSJeff Kirsher * device stats by a periodic timer. 5719f2f381fSJeff Kirsher */ 5729f2f381fSJeff Kirsher struct macb_stats { 5739f2f381fSJeff Kirsher u32 rx_pause_frames; 5749f2f381fSJeff Kirsher u32 tx_ok; 5759f2f381fSJeff Kirsher u32 tx_single_cols; 5769f2f381fSJeff Kirsher u32 tx_multiple_cols; 5779f2f381fSJeff Kirsher u32 rx_ok; 5789f2f381fSJeff Kirsher u32 rx_fcs_errors; 5799f2f381fSJeff Kirsher u32 rx_align_errors; 5809f2f381fSJeff Kirsher u32 tx_deferred; 5819f2f381fSJeff Kirsher u32 tx_late_cols; 5829f2f381fSJeff Kirsher u32 tx_excessive_cols; 5839f2f381fSJeff Kirsher u32 tx_underruns; 5849f2f381fSJeff Kirsher u32 tx_carrier_errors; 5859f2f381fSJeff Kirsher u32 rx_resource_errors; 5869f2f381fSJeff Kirsher u32 rx_overruns; 5879f2f381fSJeff Kirsher u32 rx_symbol_errors; 5889f2f381fSJeff Kirsher u32 rx_oversize_pkts; 5899f2f381fSJeff Kirsher u32 rx_jabbers; 5909f2f381fSJeff Kirsher u32 rx_undersize_pkts; 5919f2f381fSJeff Kirsher u32 sqe_test_errors; 5929f2f381fSJeff Kirsher u32 rx_length_mismatch; 5939f2f381fSJeff Kirsher u32 tx_pause_frames; 5949f2f381fSJeff Kirsher }; 5959f2f381fSJeff Kirsher 596a494ed8eSJamie Iles struct gem_stats { 597a494ed8eSJamie Iles u32 tx_octets_31_0; 598a494ed8eSJamie Iles u32 tx_octets_47_32; 599a494ed8eSJamie Iles u32 tx_frames; 600a494ed8eSJamie Iles u32 tx_broadcast_frames; 601a494ed8eSJamie Iles u32 tx_multicast_frames; 602a494ed8eSJamie Iles u32 tx_pause_frames; 603a494ed8eSJamie Iles u32 tx_64_byte_frames; 604a494ed8eSJamie Iles u32 tx_65_127_byte_frames; 605a494ed8eSJamie Iles u32 tx_128_255_byte_frames; 606a494ed8eSJamie Iles u32 tx_256_511_byte_frames; 607a494ed8eSJamie Iles u32 tx_512_1023_byte_frames; 608a494ed8eSJamie Iles u32 tx_1024_1518_byte_frames; 609a494ed8eSJamie Iles u32 tx_greater_than_1518_byte_frames; 610a494ed8eSJamie Iles u32 tx_underrun; 611a494ed8eSJamie Iles u32 tx_single_collision_frames; 612a494ed8eSJamie Iles u32 tx_multiple_collision_frames; 613a494ed8eSJamie Iles u32 tx_excessive_collisions; 614a494ed8eSJamie Iles u32 tx_late_collisions; 615a494ed8eSJamie Iles u32 tx_deferred_frames; 616a494ed8eSJamie Iles u32 tx_carrier_sense_errors; 617a494ed8eSJamie Iles u32 rx_octets_31_0; 618a494ed8eSJamie Iles u32 rx_octets_47_32; 619a494ed8eSJamie Iles u32 rx_frames; 620a494ed8eSJamie Iles u32 rx_broadcast_frames; 621a494ed8eSJamie Iles u32 rx_multicast_frames; 622a494ed8eSJamie Iles u32 rx_pause_frames; 623a494ed8eSJamie Iles u32 rx_64_byte_frames; 624a494ed8eSJamie Iles u32 rx_65_127_byte_frames; 625a494ed8eSJamie Iles u32 rx_128_255_byte_frames; 626a494ed8eSJamie Iles u32 rx_256_511_byte_frames; 627a494ed8eSJamie Iles u32 rx_512_1023_byte_frames; 628a494ed8eSJamie Iles u32 rx_1024_1518_byte_frames; 629a494ed8eSJamie Iles u32 rx_greater_than_1518_byte_frames; 630a494ed8eSJamie Iles u32 rx_undersized_frames; 631a494ed8eSJamie Iles u32 rx_oversize_frames; 632a494ed8eSJamie Iles u32 rx_jabbers; 633a494ed8eSJamie Iles u32 rx_frame_check_sequence_errors; 634a494ed8eSJamie Iles u32 rx_length_field_frame_errors; 635a494ed8eSJamie Iles u32 rx_symbol_errors; 636a494ed8eSJamie Iles u32 rx_alignment_errors; 637a494ed8eSJamie Iles u32 rx_resource_errors; 638a494ed8eSJamie Iles u32 rx_overruns; 639a494ed8eSJamie Iles u32 rx_ip_header_checksum_errors; 640a494ed8eSJamie Iles u32 rx_tcp_checksum_errors; 641a494ed8eSJamie Iles u32 rx_udp_checksum_errors; 642a494ed8eSJamie Iles }; 643a494ed8eSJamie Iles 6443ff13f1cSXander Huff /* Describes the name and offset of an individual statistic register, as 6453ff13f1cSXander Huff * returned by `ethtool -S`. Also describes which net_device_stats statistics 6463ff13f1cSXander Huff * this register should contribute to. 6473ff13f1cSXander Huff */ 6483ff13f1cSXander Huff struct gem_statistic { 6493ff13f1cSXander Huff char stat_string[ETH_GSTRING_LEN]; 6503ff13f1cSXander Huff int offset; 6513ff13f1cSXander Huff u32 stat_bits; 6523ff13f1cSXander Huff }; 6533ff13f1cSXander Huff 6543ff13f1cSXander Huff /* Bitfield defs for net_device_stat statistics */ 6553ff13f1cSXander Huff #define GEM_NDS_RXERR_OFFSET 0 6563ff13f1cSXander Huff #define GEM_NDS_RXLENERR_OFFSET 1 6573ff13f1cSXander Huff #define GEM_NDS_RXOVERERR_OFFSET 2 6583ff13f1cSXander Huff #define GEM_NDS_RXCRCERR_OFFSET 3 6593ff13f1cSXander Huff #define GEM_NDS_RXFRAMEERR_OFFSET 4 6603ff13f1cSXander Huff #define GEM_NDS_RXFIFOERR_OFFSET 5 6613ff13f1cSXander Huff #define GEM_NDS_TXERR_OFFSET 6 6623ff13f1cSXander Huff #define GEM_NDS_TXABORTEDERR_OFFSET 7 6633ff13f1cSXander Huff #define GEM_NDS_TXCARRIERERR_OFFSET 8 6643ff13f1cSXander Huff #define GEM_NDS_TXFIFOERR_OFFSET 9 6653ff13f1cSXander Huff #define GEM_NDS_COLLISIONS_OFFSET 10 6663ff13f1cSXander Huff 6673ff13f1cSXander Huff #define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0) 6683ff13f1cSXander Huff #define GEM_STAT_TITLE_BITS(name, title, bits) { \ 6693ff13f1cSXander Huff .stat_string = title, \ 6703ff13f1cSXander Huff .offset = GEM_##name, \ 6713ff13f1cSXander Huff .stat_bits = bits \ 6723ff13f1cSXander Huff } 6733ff13f1cSXander Huff 6743ff13f1cSXander Huff /* list of gem statistic registers. The names MUST match the 6753ff13f1cSXander Huff * corresponding GEM_* definitions. 6763ff13f1cSXander Huff */ 6773ff13f1cSXander Huff static const struct gem_statistic gem_statistics[] = { 6783ff13f1cSXander Huff GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */ 6793ff13f1cSXander Huff GEM_STAT_TITLE(TXCNT, "tx_frames"), 6803ff13f1cSXander Huff GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"), 6813ff13f1cSXander Huff GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"), 6823ff13f1cSXander Huff GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"), 6833ff13f1cSXander Huff GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"), 6843ff13f1cSXander Huff GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"), 6853ff13f1cSXander Huff GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"), 6863ff13f1cSXander Huff GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"), 6873ff13f1cSXander Huff GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"), 6883ff13f1cSXander Huff GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"), 6893ff13f1cSXander Huff GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"), 6903ff13f1cSXander Huff GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun", 6913ff13f1cSXander Huff GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)), 6923ff13f1cSXander Huff GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames", 6933ff13f1cSXander Huff GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), 6943ff13f1cSXander Huff GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames", 6953ff13f1cSXander Huff GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), 6963ff13f1cSXander Huff GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions", 6973ff13f1cSXander Huff GEM_BIT(NDS_TXERR)| 6983ff13f1cSXander Huff GEM_BIT(NDS_TXABORTEDERR)| 6993ff13f1cSXander Huff GEM_BIT(NDS_COLLISIONS)), 7003ff13f1cSXander Huff GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions", 7013ff13f1cSXander Huff GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), 7023ff13f1cSXander Huff GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"), 7033ff13f1cSXander Huff GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors", 7043ff13f1cSXander Huff GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), 7053ff13f1cSXander Huff GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */ 7063ff13f1cSXander Huff GEM_STAT_TITLE(RXCNT, "rx_frames"), 7073ff13f1cSXander Huff GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"), 7083ff13f1cSXander Huff GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"), 7093ff13f1cSXander Huff GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"), 7103ff13f1cSXander Huff GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"), 7113ff13f1cSXander Huff GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"), 7123ff13f1cSXander Huff GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"), 7133ff13f1cSXander Huff GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"), 7143ff13f1cSXander Huff GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"), 7153ff13f1cSXander Huff GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"), 7163ff13f1cSXander Huff GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"), 7173ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames", 7183ff13f1cSXander Huff GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)), 7193ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames", 7203ff13f1cSXander Huff GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)), 7213ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers", 7223ff13f1cSXander Huff GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)), 7233ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors", 7243ff13f1cSXander Huff GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)), 7253ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors", 7263ff13f1cSXander Huff GEM_BIT(NDS_RXERR)), 7273ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors", 7283ff13f1cSXander Huff GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)), 7293ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors", 7303ff13f1cSXander Huff GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)), 7313ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors", 7323ff13f1cSXander Huff GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)), 7333ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns", 7343ff13f1cSXander Huff GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)), 7353ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors", 7363ff13f1cSXander Huff GEM_BIT(NDS_RXERR)), 7373ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors", 7383ff13f1cSXander Huff GEM_BIT(NDS_RXERR)), 7393ff13f1cSXander Huff GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors", 7403ff13f1cSXander Huff GEM_BIT(NDS_RXERR)), 7413ff13f1cSXander Huff }; 7423ff13f1cSXander Huff 7433ff13f1cSXander Huff #define GEM_STATS_LEN ARRAY_SIZE(gem_statistics) 7443ff13f1cSXander Huff 7454df95131SNicolas Ferre struct macb; 7464df95131SNicolas Ferre 7474df95131SNicolas Ferre struct macb_or_gem_ops { 7484df95131SNicolas Ferre int (*mog_alloc_rx_buffers)(struct macb *bp); 7494df95131SNicolas Ferre void (*mog_free_rx_buffers)(struct macb *bp); 7504df95131SNicolas Ferre void (*mog_init_rings)(struct macb *bp); 7514df95131SNicolas Ferre int (*mog_rx)(struct macb *bp, int budget); 7524df95131SNicolas Ferre }; 7534df95131SNicolas Ferre 754e175587fSNicolas Ferre struct macb_config { 755e175587fSNicolas Ferre u32 caps; 756e175587fSNicolas Ferre unsigned int dma_burst_length; 757c69618b3SNicolas Ferre int (*clk_init)(struct platform_device *pdev, struct clk **pclk, 758c69618b3SNicolas Ferre struct clk **hclk, struct clk **tx_clk); 759421d9df0SCyrille Pitchen int (*init)(struct platform_device *pdev); 760e175587fSNicolas Ferre }; 761e175587fSNicolas Ferre 76202c958ddSCyrille Pitchen struct macb_queue { 76302c958ddSCyrille Pitchen struct macb *bp; 76402c958ddSCyrille Pitchen int irq; 76502c958ddSCyrille Pitchen 76602c958ddSCyrille Pitchen unsigned int ISR; 76702c958ddSCyrille Pitchen unsigned int IER; 76802c958ddSCyrille Pitchen unsigned int IDR; 76902c958ddSCyrille Pitchen unsigned int IMR; 77002c958ddSCyrille Pitchen unsigned int TBQP; 77102c958ddSCyrille Pitchen 77202c958ddSCyrille Pitchen unsigned int tx_head, tx_tail; 77302c958ddSCyrille Pitchen struct macb_dma_desc *tx_ring; 77402c958ddSCyrille Pitchen struct macb_tx_skb *tx_skb; 77502c958ddSCyrille Pitchen dma_addr_t tx_ring_dma; 77602c958ddSCyrille Pitchen struct work_struct tx_error_task; 77702c958ddSCyrille Pitchen }; 77802c958ddSCyrille Pitchen 7799f2f381fSJeff Kirsher struct macb { 7809f2f381fSJeff Kirsher void __iomem *regs; 7819f2f381fSJeff Kirsher 7829f2f381fSJeff Kirsher unsigned int rx_tail; 7834df95131SNicolas Ferre unsigned int rx_prepared_head; 78455054a16SHavard Skinnemoen struct macb_dma_desc *rx_ring; 7854df95131SNicolas Ferre struct sk_buff **rx_skbuff; 7869f2f381fSJeff Kirsher void *rx_buffers; 7871b44791aSNicolas Ferre size_t rx_buffer_size; 7889f2f381fSJeff Kirsher 78902c958ddSCyrille Pitchen unsigned int num_queues; 790bfa0914aSNicolas Ferre unsigned int queue_mask; 79102c958ddSCyrille Pitchen struct macb_queue queues[MACB_MAX_QUEUES]; 7929f2f381fSJeff Kirsher 7939f2f381fSJeff Kirsher spinlock_t lock; 7949f2f381fSJeff Kirsher struct platform_device *pdev; 7959f2f381fSJeff Kirsher struct clk *pclk; 7969f2f381fSJeff Kirsher struct clk *hclk; 797e1824dfeSSoren Brinkmann struct clk *tx_clk; 7989f2f381fSJeff Kirsher struct net_device *dev; 7999f2f381fSJeff Kirsher struct napi_struct napi; 8009f2f381fSJeff Kirsher struct net_device_stats stats; 801a494ed8eSJamie Iles union { 802a494ed8eSJamie Iles struct macb_stats macb; 803a494ed8eSJamie Iles struct gem_stats gem; 804a494ed8eSJamie Iles } hw_stats; 8059f2f381fSJeff Kirsher 8069f2f381fSJeff Kirsher dma_addr_t rx_ring_dma; 8079f2f381fSJeff Kirsher dma_addr_t rx_buffers_dma; 8089f2f381fSJeff Kirsher 8094df95131SNicolas Ferre struct macb_or_gem_ops macbgem_ops; 8104df95131SNicolas Ferre 8119f2f381fSJeff Kirsher struct mii_bus *mii_bus; 8129f2f381fSJeff Kirsher struct phy_device *phy_dev; 8139f2f381fSJeff Kirsher unsigned int link; 8149f2f381fSJeff Kirsher unsigned int speed; 8159f2f381fSJeff Kirsher unsigned int duplex; 816fb97a846SJean-Christophe PLAGNIOL-VILLARD 817581df9e1SNicolas Ferre u32 caps; 818e175587fSNicolas Ferre unsigned int dma_burst_length; 819581df9e1SNicolas Ferre 820fb97a846SJean-Christophe PLAGNIOL-VILLARD phy_interface_t phy_interface; 821b85008b7SJoachim Eastwood 8224dda6f6dSJoachim Eastwood /* AT91RM9200 transmit */ 823b85008b7SJoachim Eastwood struct sk_buff *skb; /* holds skb until xmit interrupt completes */ 824b85008b7SJoachim Eastwood dma_addr_t skb_physaddr; /* phys addr from pci_map_single */ 825b85008b7SJoachim Eastwood int skb_length; /* saved skb length for pci_unmap_single */ 826a4c35ed3SCyrille Pitchen unsigned int max_tx_length; 8273ff13f1cSXander Huff 8283ff13f1cSXander Huff u64 ethtool_stats[GEM_STATS_LEN]; 8299f2f381fSJeff Kirsher }; 8309f2f381fSJeff Kirsher 831f75ba50bSJamie Iles static inline bool macb_is_gem(struct macb *bp) 832f75ba50bSJamie Iles { 833e175587fSNicolas Ferre return !!(bp->caps & MACB_CAPS_MACB_IS_GEM); 834f75ba50bSJamie Iles } 835f75ba50bSJamie Iles 8369f2f381fSJeff Kirsher #endif /* _MACB_H */ 837