1 /* 2 * Linux network driver for Brocade Converged Network Adapter. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License (GPL) Version 2 as 6 * published by the Free Software Foundation 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 11 * General Public License for more details. 12 */ 13 /* 14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. 15 * All rights reserved 16 * www.brocade.com 17 */ 18 #ifndef __BNAD_H__ 19 #define __BNAD_H__ 20 21 #include <linux/rtnetlink.h> 22 #include <linux/workqueue.h> 23 #include <linux/ipv6.h> 24 #include <linux/etherdevice.h> 25 #include <linux/mutex.h> 26 #include <linux/firmware.h> 27 #include <linux/if_vlan.h> 28 29 /* Fix for IA64 */ 30 #include <asm/checksum.h> 31 #include <net/ip6_checksum.h> 32 33 #include <net/ip.h> 34 #include <net/tcp.h> 35 36 #include "bna.h" 37 38 #define BNAD_TXQ_DEPTH 2048 39 #define BNAD_RXQ_DEPTH 2048 40 41 #define BNAD_MAX_TX 1 42 #define BNAD_MAX_TXQ_PER_TX 8 /* 8 priority queues */ 43 #define BNAD_TXQ_NUM 1 44 45 #define BNAD_MAX_RX 1 46 #define BNAD_MAX_RXP_PER_RX 16 47 #define BNAD_MAX_RXQ_PER_RXP 2 48 49 /* 50 * Control structure pointed to ccb->ctrl, which 51 * determines the NAPI / LRO behavior CCB 52 * There is 1:1 corres. between ccb & ctrl 53 */ 54 struct bnad_rx_ctrl { 55 struct bna_ccb *ccb; 56 struct bnad *bnad; 57 unsigned long flags; 58 struct napi_struct napi; 59 u64 rx_intr_ctr; 60 u64 rx_poll_ctr; 61 u64 rx_schedule; 62 u64 rx_keep_poll; 63 u64 rx_complete; 64 }; 65 66 #define BNAD_RXMODE_PROMISC_DEFAULT BNA_RXMODE_PROMISC 67 68 /* 69 * GLOBAL #defines (CONSTANTS) 70 */ 71 #define BNAD_NAME "bna" 72 #define BNAD_NAME_LEN 64 73 74 #define BNAD_VERSION "3.0.2.2" 75 76 #define BNAD_MAILBOX_MSIX_INDEX 0 77 #define BNAD_MAILBOX_MSIX_VECTORS 1 78 #define BNAD_INTX_TX_IB_BITMASK 0x1 79 #define BNAD_INTX_RX_IB_BITMASK 0x2 80 81 #define BNAD_STATS_TIMER_FREQ 1000 /* in msecs */ 82 #define BNAD_DIM_TIMER_FREQ 1000 /* in msecs */ 83 84 #define BNAD_IOCETH_TIMEOUT 10000 85 86 #define BNAD_MAX_Q_DEPTH 0x10000 87 #define BNAD_MIN_Q_DEPTH 0x200 88 89 #define BNAD_MAX_RXQ_DEPTH (BNAD_MAX_Q_DEPTH / bnad_rxqs_per_cq) 90 /* keeping MAX TX and RX Q depth equal */ 91 #define BNAD_MAX_TXQ_DEPTH BNAD_MAX_RXQ_DEPTH 92 93 #define BNAD_JUMBO_MTU 9000 94 95 #define BNAD_NETIF_WAKE_THRESHOLD 8 96 97 #define BNAD_RXQ_REFILL_THRESHOLD_SHIFT 3 98 99 /* Bit positions for tcb->flags */ 100 #define BNAD_TXQ_FREE_SENT 0 101 #define BNAD_TXQ_TX_STARTED 1 102 103 /* Bit positions for rcb->flags */ 104 #define BNAD_RXQ_REFILL 0 105 #define BNAD_RXQ_STARTED 1 106 #define BNAD_RXQ_POST_OK 2 107 108 /* Resource limits */ 109 #define BNAD_NUM_TXQ (bnad->num_tx * bnad->num_txq_per_tx) 110 #define BNAD_NUM_RXP (bnad->num_rx * bnad->num_rxp_per_rx) 111 112 /* 113 * DATA STRUCTURES 114 */ 115 116 /* enums */ 117 enum bnad_intr_source { 118 BNAD_INTR_TX = 1, 119 BNAD_INTR_RX = 2 120 }; 121 122 enum bnad_link_state { 123 BNAD_LS_DOWN = 0, 124 BNAD_LS_UP = 1 125 }; 126 127 struct bnad_completion { 128 struct completion ioc_comp; 129 struct completion ucast_comp; 130 struct completion mcast_comp; 131 struct completion tx_comp; 132 struct completion rx_comp; 133 struct completion stats_comp; 134 struct completion enet_comp; 135 struct completion mtu_comp; 136 137 u8 ioc_comp_status; 138 u8 ucast_comp_status; 139 u8 mcast_comp_status; 140 u8 tx_comp_status; 141 u8 rx_comp_status; 142 u8 stats_comp_status; 143 u8 port_comp_status; 144 u8 mtu_comp_status; 145 }; 146 147 /* Tx Rx Control Stats */ 148 struct bnad_drv_stats { 149 u64 netif_queue_stop; 150 u64 netif_queue_wakeup; 151 u64 netif_queue_stopped; 152 u64 tso4; 153 u64 tso6; 154 u64 tso_err; 155 u64 tcpcsum_offload; 156 u64 udpcsum_offload; 157 u64 csum_help; 158 u64 tx_skb_too_short; 159 u64 tx_skb_stopping; 160 u64 tx_skb_max_vectors; 161 u64 tx_skb_mss_too_long; 162 u64 tx_skb_tso_too_short; 163 u64 tx_skb_tso_prepare; 164 u64 tx_skb_non_tso_too_long; 165 u64 tx_skb_tcp_hdr; 166 u64 tx_skb_udp_hdr; 167 u64 tx_skb_csum_err; 168 u64 tx_skb_headlen_too_long; 169 u64 tx_skb_headlen_zero; 170 u64 tx_skb_frag_zero; 171 u64 tx_skb_len_mismatch; 172 173 u64 hw_stats_updates; 174 u64 netif_rx_dropped; 175 176 u64 link_toggle; 177 u64 cee_toggle; 178 179 u64 rxp_info_alloc_failed; 180 u64 mbox_intr_disabled; 181 u64 mbox_intr_enabled; 182 u64 tx_unmap_q_alloc_failed; 183 u64 rx_unmap_q_alloc_failed; 184 185 u64 rxbuf_alloc_failed; 186 }; 187 188 /* Complete driver stats */ 189 struct bnad_stats { 190 struct bnad_drv_stats drv_stats; 191 struct bna_stats *bna_stats; 192 }; 193 194 /* Tx / Rx Resources */ 195 struct bnad_tx_res_info { 196 struct bna_res_info res_info[BNA_TX_RES_T_MAX]; 197 }; 198 199 struct bnad_rx_res_info { 200 struct bna_res_info res_info[BNA_RX_RES_T_MAX]; 201 }; 202 203 struct bnad_tx_info { 204 struct bna_tx *tx; /* 1:1 between tx_info & tx */ 205 struct bna_tcb *tcb[BNAD_MAX_TXQ_PER_TX]; 206 u32 tx_id; 207 } ____cacheline_aligned; 208 209 struct bnad_rx_info { 210 struct bna_rx *rx; /* 1:1 between rx_info & rx */ 211 212 struct bnad_rx_ctrl rx_ctrl[BNAD_MAX_RXP_PER_RX]; 213 u32 rx_id; 214 } ____cacheline_aligned; 215 216 /* Unmap queues for Tx / Rx cleanup */ 217 struct bnad_skb_unmap { 218 struct sk_buff *skb; 219 DEFINE_DMA_UNMAP_ADDR(dma_addr); 220 }; 221 222 struct bnad_unmap_q { 223 u32 producer_index; 224 u32 consumer_index; 225 u32 q_depth; 226 /* This should be the last one */ 227 struct bnad_skb_unmap unmap_array[1]; 228 }; 229 230 /* Bit mask values for bnad->cfg_flags */ 231 #define BNAD_CF_DIM_ENABLED 0x01 /* DIM */ 232 #define BNAD_CF_PROMISC 0x02 233 #define BNAD_CF_ALLMULTI 0x04 234 #define BNAD_CF_MSIX 0x08 /* If in MSIx mode */ 235 236 /* Defines for run_flags bit-mask */ 237 /* Set, tested & cleared using xxx_bit() functions */ 238 /* Values indicated bit positions */ 239 #define BNAD_RF_CEE_RUNNING 0 240 #define BNAD_RF_MTU_SET 1 241 #define BNAD_RF_MBOX_IRQ_DISABLED 2 242 #define BNAD_RF_NETDEV_REGISTERED 3 243 #define BNAD_RF_DIM_TIMER_RUNNING 4 244 #define BNAD_RF_STATS_TIMER_RUNNING 5 245 #define BNAD_RF_TX_PRIO_SET 6 246 247 248 /* Define for Fast Path flags */ 249 /* Defined as bit positions */ 250 #define BNAD_FP_IN_RX_PATH 0 251 252 struct bnad { 253 struct net_device *netdev; 254 255 /* Data path */ 256 struct bnad_tx_info tx_info[BNAD_MAX_TX]; 257 struct bnad_rx_info rx_info[BNAD_MAX_RX]; 258 259 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 260 /* 261 * These q numbers are global only because 262 * they are used to calculate MSIx vectors. 263 * Actually the exact # of queues are per Tx/Rx 264 * object. 265 */ 266 u32 num_tx; 267 u32 num_rx; 268 u32 num_txq_per_tx; 269 u32 num_rxp_per_rx; 270 271 u32 txq_depth; 272 u32 rxq_depth; 273 274 u8 tx_coalescing_timeo; 275 u8 rx_coalescing_timeo; 276 277 struct bna_rx_config rx_config[BNAD_MAX_RX]; 278 struct bna_tx_config tx_config[BNAD_MAX_TX]; 279 280 void __iomem *bar0; /* BAR0 address */ 281 282 struct bna bna; 283 284 u32 cfg_flags; 285 unsigned long run_flags; 286 287 struct pci_dev *pcidev; 288 u64 mmio_start; 289 u64 mmio_len; 290 291 u32 msix_num; 292 struct msix_entry *msix_table; 293 294 struct mutex conf_mutex; 295 spinlock_t bna_lock ____cacheline_aligned; 296 297 /* Timers */ 298 struct timer_list ioc_timer; 299 struct timer_list dim_timer; 300 struct timer_list stats_timer; 301 302 /* Control path resources, memory & irq */ 303 struct bna_res_info res_info[BNA_RES_T_MAX]; 304 struct bna_res_info mod_res_info[BNA_MOD_RES_T_MAX]; 305 struct bnad_tx_res_info tx_res_info[BNAD_MAX_TX]; 306 struct bnad_rx_res_info rx_res_info[BNAD_MAX_RX]; 307 308 struct bnad_completion bnad_completions; 309 310 /* Burnt in MAC address */ 311 mac_t perm_addr; 312 313 struct tasklet_struct tx_free_tasklet; 314 315 /* Statistics */ 316 struct bnad_stats stats; 317 318 struct bnad_diag *diag; 319 320 char adapter_name[BNAD_NAME_LEN]; 321 char port_name[BNAD_NAME_LEN]; 322 char mbox_irq_name[BNAD_NAME_LEN]; 323 }; 324 325 /* 326 * EXTERN VARIABLES 327 */ 328 extern struct firmware *bfi_fw; 329 extern u32 bnad_rxqs_per_cq; 330 331 /* 332 * EXTERN PROTOTYPES 333 */ 334 extern u32 *cna_get_firmware_buf(struct pci_dev *pdev); 335 /* Netdev entry point prototypes */ 336 extern void bnad_set_rx_mode(struct net_device *netdev); 337 extern struct net_device_stats *bnad_get_netdev_stats( 338 struct net_device *netdev); 339 extern int bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr); 340 extern int bnad_enable_default_bcast(struct bnad *bnad); 341 extern void bnad_restore_vlans(struct bnad *bnad, u32 rx_id); 342 extern void bnad_set_ethtool_ops(struct net_device *netdev); 343 344 /* Configuration & setup */ 345 extern void bnad_tx_coalescing_timeo_set(struct bnad *bnad); 346 extern void bnad_rx_coalescing_timeo_set(struct bnad *bnad); 347 348 extern int bnad_setup_rx(struct bnad *bnad, u32 rx_id); 349 extern int bnad_setup_tx(struct bnad *bnad, u32 tx_id); 350 extern void bnad_cleanup_tx(struct bnad *bnad, u32 tx_id); 351 extern void bnad_cleanup_rx(struct bnad *bnad, u32 rx_id); 352 353 /* Timer start/stop protos */ 354 extern void bnad_dim_timer_start(struct bnad *bnad); 355 356 /* Statistics */ 357 extern void bnad_netdev_qstats_fill(struct bnad *bnad, 358 struct rtnl_link_stats64 *stats); 359 extern void bnad_netdev_hwstats_fill(struct bnad *bnad, 360 struct rtnl_link_stats64 *stats); 361 362 /** 363 * MACROS 364 */ 365 /* To set & get the stats counters */ 366 #define BNAD_UPDATE_CTR(_bnad, _ctr) \ 367 (((_bnad)->stats.drv_stats._ctr)++) 368 369 #define BNAD_GET_CTR(_bnad, _ctr) ((_bnad)->stats.drv_stats._ctr) 370 371 #define bnad_enable_rx_irq_unsafe(_ccb) \ 372 { \ 373 if (likely(test_bit(BNAD_RXQ_STARTED, &(_ccb)->rcb[0]->flags))) {\ 374 bna_ib_coalescing_timer_set((_ccb)->i_dbell, \ 375 (_ccb)->rx_coalescing_timeo); \ 376 bna_ib_ack((_ccb)->i_dbell, 0); \ 377 } \ 378 } 379 380 #endif /* __BNAD_H__ */ 381