1 /* 2 * Linux network driver for Brocade Converged Network Adapter. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License (GPL) Version 2 as 6 * published by the Free Software Foundation 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 11 * General Public License for more details. 12 */ 13 /* 14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. 15 * All rights reserved 16 * www.brocade.com 17 */ 18 #include <linux/bitops.h> 19 #include <linux/netdevice.h> 20 #include <linux/skbuff.h> 21 #include <linux/etherdevice.h> 22 #include <linux/in.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_vlan.h> 25 #include <linux/if_ether.h> 26 #include <linux/ip.h> 27 #include <linux/prefetch.h> 28 #include <linux/module.h> 29 30 #include "bnad.h" 31 #include "bna.h" 32 #include "cna.h" 33 34 static DEFINE_MUTEX(bnad_fwimg_mutex); 35 36 /* 37 * Module params 38 */ 39 static uint bnad_msix_disable; 40 module_param(bnad_msix_disable, uint, 0444); 41 MODULE_PARM_DESC(bnad_msix_disable, "Disable MSIX mode"); 42 43 static uint bnad_ioc_auto_recover = 1; 44 module_param(bnad_ioc_auto_recover, uint, 0444); 45 MODULE_PARM_DESC(bnad_ioc_auto_recover, "Enable / Disable auto recovery"); 46 47 static uint bna_debugfs_enable = 1; 48 module_param(bna_debugfs_enable, uint, S_IRUGO | S_IWUSR); 49 MODULE_PARM_DESC(bna_debugfs_enable, "Enables debugfs feature, default=1," 50 " Range[false:0|true:1]"); 51 52 /* 53 * Global variables 54 */ 55 u32 bnad_rxqs_per_cq = 2; 56 static u32 bna_id; 57 static struct mutex bnad_list_mutex; 58 static LIST_HEAD(bnad_list); 59 static const u8 bnad_bcast_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 60 61 /* 62 * Local MACROS 63 */ 64 #define BNAD_GET_MBOX_IRQ(_bnad) \ 65 (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \ 66 ((_bnad)->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector) : \ 67 ((_bnad)->pcidev->irq)) 68 69 #define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _size) \ 70 do { \ 71 (_res_info)->res_type = BNA_RES_T_MEM; \ 72 (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \ 73 (_res_info)->res_u.mem_info.num = (_num); \ 74 (_res_info)->res_u.mem_info.len = (_size); \ 75 } while (0) 76 77 static void 78 bnad_add_to_list(struct bnad *bnad) 79 { 80 mutex_lock(&bnad_list_mutex); 81 list_add_tail(&bnad->list_entry, &bnad_list); 82 bnad->id = bna_id++; 83 mutex_unlock(&bnad_list_mutex); 84 } 85 86 static void 87 bnad_remove_from_list(struct bnad *bnad) 88 { 89 mutex_lock(&bnad_list_mutex); 90 list_del(&bnad->list_entry); 91 mutex_unlock(&bnad_list_mutex); 92 } 93 94 /* 95 * Reinitialize completions in CQ, once Rx is taken down 96 */ 97 static void 98 bnad_cq_cleanup(struct bnad *bnad, struct bna_ccb *ccb) 99 { 100 struct bna_cq_entry *cmpl; 101 int i; 102 103 for (i = 0; i < ccb->q_depth; i++) { 104 cmpl = &((struct bna_cq_entry *)ccb->sw_q)[i]; 105 cmpl->valid = 0; 106 } 107 } 108 109 /* Tx Datapath functions */ 110 111 112 /* Caller should ensure that the entry at unmap_q[index] is valid */ 113 static u32 114 bnad_tx_buff_unmap(struct bnad *bnad, 115 struct bnad_tx_unmap *unmap_q, 116 u32 q_depth, u32 index) 117 { 118 struct bnad_tx_unmap *unmap; 119 struct sk_buff *skb; 120 int vector, nvecs; 121 122 unmap = &unmap_q[index]; 123 nvecs = unmap->nvecs; 124 125 skb = unmap->skb; 126 unmap->skb = NULL; 127 unmap->nvecs = 0; 128 dma_unmap_single(&bnad->pcidev->dev, 129 dma_unmap_addr(&unmap->vectors[0], dma_addr), 130 skb_headlen(skb), DMA_TO_DEVICE); 131 dma_unmap_addr_set(&unmap->vectors[0], dma_addr, 0); 132 nvecs--; 133 134 vector = 0; 135 while (nvecs) { 136 vector++; 137 if (vector == BFI_TX_MAX_VECTORS_PER_WI) { 138 vector = 0; 139 BNA_QE_INDX_INC(index, q_depth); 140 unmap = &unmap_q[index]; 141 } 142 143 dma_unmap_page(&bnad->pcidev->dev, 144 dma_unmap_addr(&unmap->vectors[vector], dma_addr), 145 skb_shinfo(skb)->frags[nvecs].size, DMA_TO_DEVICE); 146 dma_unmap_addr_set(&unmap->vectors[vector], dma_addr, 0); 147 nvecs--; 148 } 149 150 BNA_QE_INDX_INC(index, q_depth); 151 152 return index; 153 } 154 155 /* 156 * Frees all pending Tx Bufs 157 * At this point no activity is expected on the Q, 158 * so DMA unmap & freeing is fine. 159 */ 160 static void 161 bnad_txq_cleanup(struct bnad *bnad, struct bna_tcb *tcb) 162 { 163 struct bnad_tx_unmap *unmap_q = tcb->unmap_q; 164 struct sk_buff *skb; 165 int i; 166 167 for (i = 0; i < tcb->q_depth; i++) { 168 skb = unmap_q[i].skb; 169 if (!skb) 170 continue; 171 bnad_tx_buff_unmap(bnad, unmap_q, tcb->q_depth, i); 172 173 dev_kfree_skb_any(skb); 174 } 175 } 176 177 /* 178 * bnad_txcmpl_process : Frees the Tx bufs on Tx completion 179 * Can be called in a) Interrupt context 180 * b) Sending context 181 */ 182 static u32 183 bnad_txcmpl_process(struct bnad *bnad, struct bna_tcb *tcb) 184 { 185 u32 sent_packets = 0, sent_bytes = 0; 186 u32 wis, unmap_wis, hw_cons, cons, q_depth; 187 struct bnad_tx_unmap *unmap_q = tcb->unmap_q; 188 struct bnad_tx_unmap *unmap; 189 struct sk_buff *skb; 190 191 /* Just return if TX is stopped */ 192 if (!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) 193 return 0; 194 195 hw_cons = *(tcb->hw_consumer_index); 196 cons = tcb->consumer_index; 197 q_depth = tcb->q_depth; 198 199 wis = BNA_Q_INDEX_CHANGE(cons, hw_cons, q_depth); 200 BUG_ON(!(wis <= BNA_QE_IN_USE_CNT(tcb, tcb->q_depth))); 201 202 while (wis) { 203 unmap = &unmap_q[cons]; 204 205 skb = unmap->skb; 206 207 sent_packets++; 208 sent_bytes += skb->len; 209 210 unmap_wis = BNA_TXQ_WI_NEEDED(unmap->nvecs); 211 wis -= unmap_wis; 212 213 cons = bnad_tx_buff_unmap(bnad, unmap_q, q_depth, cons); 214 dev_kfree_skb_any(skb); 215 } 216 217 /* Update consumer pointers. */ 218 tcb->consumer_index = hw_cons; 219 220 tcb->txq->tx_packets += sent_packets; 221 tcb->txq->tx_bytes += sent_bytes; 222 223 return sent_packets; 224 } 225 226 static u32 227 bnad_tx_complete(struct bnad *bnad, struct bna_tcb *tcb) 228 { 229 struct net_device *netdev = bnad->netdev; 230 u32 sent = 0; 231 232 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) 233 return 0; 234 235 sent = bnad_txcmpl_process(bnad, tcb); 236 if (sent) { 237 if (netif_queue_stopped(netdev) && 238 netif_carrier_ok(netdev) && 239 BNA_QE_FREE_CNT(tcb, tcb->q_depth) >= 240 BNAD_NETIF_WAKE_THRESHOLD) { 241 if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) { 242 netif_wake_queue(netdev); 243 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup); 244 } 245 } 246 } 247 248 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) 249 bna_ib_ack(tcb->i_dbell, sent); 250 251 smp_mb__before_clear_bit(); 252 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags); 253 254 return sent; 255 } 256 257 /* MSIX Tx Completion Handler */ 258 static irqreturn_t 259 bnad_msix_tx(int irq, void *data) 260 { 261 struct bna_tcb *tcb = (struct bna_tcb *)data; 262 struct bnad *bnad = tcb->bnad; 263 264 bnad_tx_complete(bnad, tcb); 265 266 return IRQ_HANDLED; 267 } 268 269 static inline void 270 bnad_rxq_alloc_uninit(struct bnad *bnad, struct bna_rcb *rcb) 271 { 272 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q; 273 274 unmap_q->reuse_pi = -1; 275 unmap_q->alloc_order = -1; 276 unmap_q->map_size = 0; 277 unmap_q->type = BNAD_RXBUF_NONE; 278 } 279 280 /* Default is page-based allocation. Multi-buffer support - TBD */ 281 static int 282 bnad_rxq_alloc_init(struct bnad *bnad, struct bna_rcb *rcb) 283 { 284 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q; 285 int mtu, order; 286 287 bnad_rxq_alloc_uninit(bnad, rcb); 288 289 mtu = bna_enet_mtu_get(&bnad->bna.enet); 290 order = get_order(mtu); 291 292 if (bna_is_small_rxq(rcb->id)) { 293 unmap_q->alloc_order = 0; 294 unmap_q->map_size = rcb->rxq->buffer_size; 295 } else { 296 unmap_q->alloc_order = order; 297 unmap_q->map_size = 298 (rcb->rxq->buffer_size > 2048) ? 299 PAGE_SIZE << order : 2048; 300 } 301 302 BUG_ON(((PAGE_SIZE << order) % unmap_q->map_size)); 303 304 unmap_q->type = BNAD_RXBUF_PAGE; 305 306 return 0; 307 } 308 309 static inline void 310 bnad_rxq_cleanup_page(struct bnad *bnad, struct bnad_rx_unmap *unmap) 311 { 312 if (!unmap->page) 313 return; 314 315 dma_unmap_page(&bnad->pcidev->dev, 316 dma_unmap_addr(&unmap->vector, dma_addr), 317 unmap->vector.len, DMA_FROM_DEVICE); 318 put_page(unmap->page); 319 unmap->page = NULL; 320 dma_unmap_addr_set(&unmap->vector, dma_addr, 0); 321 unmap->vector.len = 0; 322 } 323 324 static inline void 325 bnad_rxq_cleanup_skb(struct bnad *bnad, struct bnad_rx_unmap *unmap) 326 { 327 if (!unmap->skb) 328 return; 329 330 dma_unmap_single(&bnad->pcidev->dev, 331 dma_unmap_addr(&unmap->vector, dma_addr), 332 unmap->vector.len, DMA_FROM_DEVICE); 333 dev_kfree_skb_any(unmap->skb); 334 unmap->skb = NULL; 335 dma_unmap_addr_set(&unmap->vector, dma_addr, 0); 336 unmap->vector.len = 0; 337 } 338 339 static void 340 bnad_rxq_cleanup(struct bnad *bnad, struct bna_rcb *rcb) 341 { 342 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q; 343 int i; 344 345 for (i = 0; i < rcb->q_depth; i++) { 346 struct bnad_rx_unmap *unmap = &unmap_q->unmap[i]; 347 348 if (BNAD_RXBUF_IS_PAGE(unmap_q->type)) 349 bnad_rxq_cleanup_page(bnad, unmap); 350 else 351 bnad_rxq_cleanup_skb(bnad, unmap); 352 } 353 bnad_rxq_alloc_uninit(bnad, rcb); 354 } 355 356 static u32 357 bnad_rxq_refill_page(struct bnad *bnad, struct bna_rcb *rcb, u32 nalloc) 358 { 359 u32 alloced, prod, q_depth; 360 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q; 361 struct bnad_rx_unmap *unmap, *prev; 362 struct bna_rxq_entry *rxent; 363 struct page *page; 364 u32 page_offset, alloc_size; 365 dma_addr_t dma_addr; 366 367 prod = rcb->producer_index; 368 q_depth = rcb->q_depth; 369 370 alloc_size = PAGE_SIZE << unmap_q->alloc_order; 371 alloced = 0; 372 373 while (nalloc--) { 374 unmap = &unmap_q->unmap[prod]; 375 376 if (unmap_q->reuse_pi < 0) { 377 page = alloc_pages(GFP_ATOMIC | __GFP_COMP, 378 unmap_q->alloc_order); 379 page_offset = 0; 380 } else { 381 prev = &unmap_q->unmap[unmap_q->reuse_pi]; 382 page = prev->page; 383 page_offset = prev->page_offset + unmap_q->map_size; 384 get_page(page); 385 } 386 387 if (unlikely(!page)) { 388 BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed); 389 rcb->rxq->rxbuf_alloc_failed++; 390 goto finishing; 391 } 392 393 dma_addr = dma_map_page(&bnad->pcidev->dev, page, page_offset, 394 unmap_q->map_size, DMA_FROM_DEVICE); 395 396 unmap->page = page; 397 unmap->page_offset = page_offset; 398 dma_unmap_addr_set(&unmap->vector, dma_addr, dma_addr); 399 unmap->vector.len = unmap_q->map_size; 400 page_offset += unmap_q->map_size; 401 402 if (page_offset < alloc_size) 403 unmap_q->reuse_pi = prod; 404 else 405 unmap_q->reuse_pi = -1; 406 407 rxent = &((struct bna_rxq_entry *)rcb->sw_q)[prod]; 408 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr); 409 BNA_QE_INDX_INC(prod, q_depth); 410 alloced++; 411 } 412 413 finishing: 414 if (likely(alloced)) { 415 rcb->producer_index = prod; 416 smp_mb(); 417 if (likely(test_bit(BNAD_RXQ_POST_OK, &rcb->flags))) 418 bna_rxq_prod_indx_doorbell(rcb); 419 } 420 421 return alloced; 422 } 423 424 static u32 425 bnad_rxq_refill_skb(struct bnad *bnad, struct bna_rcb *rcb, u32 nalloc) 426 { 427 u32 alloced, prod, q_depth, buff_sz; 428 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q; 429 struct bnad_rx_unmap *unmap; 430 struct bna_rxq_entry *rxent; 431 struct sk_buff *skb; 432 dma_addr_t dma_addr; 433 434 buff_sz = rcb->rxq->buffer_size; 435 prod = rcb->producer_index; 436 q_depth = rcb->q_depth; 437 438 alloced = 0; 439 while (nalloc--) { 440 unmap = &unmap_q->unmap[prod]; 441 442 skb = netdev_alloc_skb_ip_align(bnad->netdev, buff_sz); 443 444 if (unlikely(!skb)) { 445 BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed); 446 rcb->rxq->rxbuf_alloc_failed++; 447 goto finishing; 448 } 449 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data, 450 buff_sz, DMA_FROM_DEVICE); 451 452 unmap->skb = skb; 453 dma_unmap_addr_set(&unmap->vector, dma_addr, dma_addr); 454 unmap->vector.len = buff_sz; 455 456 rxent = &((struct bna_rxq_entry *)rcb->sw_q)[prod]; 457 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr); 458 BNA_QE_INDX_INC(prod, q_depth); 459 alloced++; 460 } 461 462 finishing: 463 if (likely(alloced)) { 464 rcb->producer_index = prod; 465 smp_mb(); 466 if (likely(test_bit(BNAD_RXQ_POST_OK, &rcb->flags))) 467 bna_rxq_prod_indx_doorbell(rcb); 468 } 469 470 return alloced; 471 } 472 473 static inline void 474 bnad_rxq_post(struct bnad *bnad, struct bna_rcb *rcb) 475 { 476 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q; 477 u32 to_alloc; 478 479 to_alloc = BNA_QE_FREE_CNT(rcb, rcb->q_depth); 480 if (!(to_alloc >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)) 481 return; 482 483 if (BNAD_RXBUF_IS_PAGE(unmap_q->type)) 484 bnad_rxq_refill_page(bnad, rcb, to_alloc); 485 else 486 bnad_rxq_refill_skb(bnad, rcb, to_alloc); 487 } 488 489 #define flags_cksum_prot_mask (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \ 490 BNA_CQ_EF_IPV6 | \ 491 BNA_CQ_EF_TCP | BNA_CQ_EF_UDP | \ 492 BNA_CQ_EF_L4_CKSUM_OK) 493 494 #define flags_tcp4 (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \ 495 BNA_CQ_EF_TCP | BNA_CQ_EF_L4_CKSUM_OK) 496 #define flags_tcp6 (BNA_CQ_EF_IPV6 | \ 497 BNA_CQ_EF_TCP | BNA_CQ_EF_L4_CKSUM_OK) 498 #define flags_udp4 (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \ 499 BNA_CQ_EF_UDP | BNA_CQ_EF_L4_CKSUM_OK) 500 #define flags_udp6 (BNA_CQ_EF_IPV6 | \ 501 BNA_CQ_EF_UDP | BNA_CQ_EF_L4_CKSUM_OK) 502 503 static inline struct sk_buff * 504 bnad_cq_prepare_skb(struct bnad_rx_ctrl *rx_ctrl, 505 struct bnad_rx_unmap_q *unmap_q, 506 struct bnad_rx_unmap *unmap, 507 u32 length, u32 flags) 508 { 509 struct bnad *bnad = rx_ctrl->bnad; 510 struct sk_buff *skb; 511 512 if (BNAD_RXBUF_IS_PAGE(unmap_q->type)) { 513 skb = napi_get_frags(&rx_ctrl->napi); 514 if (unlikely(!skb)) 515 return NULL; 516 517 dma_unmap_page(&bnad->pcidev->dev, 518 dma_unmap_addr(&unmap->vector, dma_addr), 519 unmap->vector.len, DMA_FROM_DEVICE); 520 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, 521 unmap->page, unmap->page_offset, length); 522 skb->len += length; 523 skb->data_len += length; 524 skb->truesize += length; 525 526 unmap->page = NULL; 527 unmap->vector.len = 0; 528 529 return skb; 530 } 531 532 skb = unmap->skb; 533 BUG_ON(!skb); 534 535 dma_unmap_single(&bnad->pcidev->dev, 536 dma_unmap_addr(&unmap->vector, dma_addr), 537 unmap->vector.len, DMA_FROM_DEVICE); 538 539 skb_put(skb, length); 540 541 skb->protocol = eth_type_trans(skb, bnad->netdev); 542 543 unmap->skb = NULL; 544 unmap->vector.len = 0; 545 return skb; 546 } 547 548 static u32 549 bnad_cq_process(struct bnad *bnad, struct bna_ccb *ccb, int budget) 550 { 551 struct bna_cq_entry *cq, *cmpl; 552 struct bna_rcb *rcb = NULL; 553 struct bnad_rx_unmap_q *unmap_q; 554 struct bnad_rx_unmap *unmap; 555 struct sk_buff *skb; 556 struct bna_pkt_rate *pkt_rt = &ccb->pkt_rate; 557 struct bnad_rx_ctrl *rx_ctrl = ccb->ctrl; 558 u32 packets = 0, length = 0, flags, masked_flags; 559 560 prefetch(bnad->netdev); 561 562 cq = ccb->sw_q; 563 cmpl = &cq[ccb->producer_index]; 564 565 while (cmpl->valid && (packets < budget)) { 566 packets++; 567 flags = ntohl(cmpl->flags); 568 length = ntohs(cmpl->length); 569 BNA_UPDATE_PKT_CNT(pkt_rt, ntohs(cmpl->length)); 570 571 if (bna_is_small_rxq(cmpl->rxq_id)) 572 rcb = ccb->rcb[1]; 573 else 574 rcb = ccb->rcb[0]; 575 576 unmap_q = rcb->unmap_q; 577 unmap = &unmap_q->unmap[rcb->consumer_index]; 578 579 if (unlikely(flags & (BNA_CQ_EF_MAC_ERROR | 580 BNA_CQ_EF_FCS_ERROR | 581 BNA_CQ_EF_TOO_LONG))) { 582 if (BNAD_RXBUF_IS_PAGE(unmap_q->type)) 583 bnad_rxq_cleanup_page(bnad, unmap); 584 else 585 bnad_rxq_cleanup_skb(bnad, unmap); 586 587 rcb->rxq->rx_packets_with_error++; 588 goto next; 589 } 590 591 skb = bnad_cq_prepare_skb(ccb->ctrl, unmap_q, unmap, 592 length, flags); 593 594 if (unlikely(!skb)) 595 break; 596 597 masked_flags = flags & flags_cksum_prot_mask; 598 599 if (likely 600 ((bnad->netdev->features & NETIF_F_RXCSUM) && 601 ((masked_flags == flags_tcp4) || 602 (masked_flags == flags_udp4) || 603 (masked_flags == flags_tcp6) || 604 (masked_flags == flags_udp6)))) 605 skb->ip_summed = CHECKSUM_UNNECESSARY; 606 else 607 skb_checksum_none_assert(skb); 608 609 rcb->rxq->rx_packets++; 610 rcb->rxq->rx_bytes += length; 611 612 if (flags & BNA_CQ_EF_VLAN) 613 __vlan_hwaccel_put_tag(skb, ntohs(cmpl->vlan_tag)); 614 615 if (BNAD_RXBUF_IS_PAGE(unmap_q->type)) 616 napi_gro_frags(&rx_ctrl->napi); 617 else 618 netif_receive_skb(skb); 619 620 next: 621 cmpl->valid = 0; 622 BNA_QE_INDX_INC(rcb->consumer_index, rcb->q_depth); 623 BNA_QE_INDX_INC(ccb->producer_index, ccb->q_depth); 624 cmpl = &cq[ccb->producer_index]; 625 } 626 627 napi_gro_flush(&rx_ctrl->napi, false); 628 if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags))) 629 bna_ib_ack_disable_irq(ccb->i_dbell, packets); 630 631 bnad_rxq_post(bnad, ccb->rcb[0]); 632 if (ccb->rcb[1]) 633 bnad_rxq_post(bnad, ccb->rcb[1]); 634 635 return packets; 636 } 637 638 static void 639 bnad_netif_rx_schedule_poll(struct bnad *bnad, struct bna_ccb *ccb) 640 { 641 struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl); 642 struct napi_struct *napi = &rx_ctrl->napi; 643 644 if (likely(napi_schedule_prep(napi))) { 645 __napi_schedule(napi); 646 rx_ctrl->rx_schedule++; 647 } 648 } 649 650 /* MSIX Rx Path Handler */ 651 static irqreturn_t 652 bnad_msix_rx(int irq, void *data) 653 { 654 struct bna_ccb *ccb = (struct bna_ccb *)data; 655 656 if (ccb) { 657 ((struct bnad_rx_ctrl *)(ccb->ctrl))->rx_intr_ctr++; 658 bnad_netif_rx_schedule_poll(ccb->bnad, ccb); 659 } 660 661 return IRQ_HANDLED; 662 } 663 664 /* Interrupt handlers */ 665 666 /* Mbox Interrupt Handlers */ 667 static irqreturn_t 668 bnad_msix_mbox_handler(int irq, void *data) 669 { 670 u32 intr_status; 671 unsigned long flags; 672 struct bnad *bnad = (struct bnad *)data; 673 674 spin_lock_irqsave(&bnad->bna_lock, flags); 675 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))) { 676 spin_unlock_irqrestore(&bnad->bna_lock, flags); 677 return IRQ_HANDLED; 678 } 679 680 bna_intr_status_get(&bnad->bna, intr_status); 681 682 if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status)) 683 bna_mbox_handler(&bnad->bna, intr_status); 684 685 spin_unlock_irqrestore(&bnad->bna_lock, flags); 686 687 return IRQ_HANDLED; 688 } 689 690 static irqreturn_t 691 bnad_isr(int irq, void *data) 692 { 693 int i, j; 694 u32 intr_status; 695 unsigned long flags; 696 struct bnad *bnad = (struct bnad *)data; 697 struct bnad_rx_info *rx_info; 698 struct bnad_rx_ctrl *rx_ctrl; 699 struct bna_tcb *tcb = NULL; 700 701 spin_lock_irqsave(&bnad->bna_lock, flags); 702 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))) { 703 spin_unlock_irqrestore(&bnad->bna_lock, flags); 704 return IRQ_NONE; 705 } 706 707 bna_intr_status_get(&bnad->bna, intr_status); 708 709 if (unlikely(!intr_status)) { 710 spin_unlock_irqrestore(&bnad->bna_lock, flags); 711 return IRQ_NONE; 712 } 713 714 if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status)) 715 bna_mbox_handler(&bnad->bna, intr_status); 716 717 spin_unlock_irqrestore(&bnad->bna_lock, flags); 718 719 if (!BNA_IS_INTX_DATA_INTR(intr_status)) 720 return IRQ_HANDLED; 721 722 /* Process data interrupts */ 723 /* Tx processing */ 724 for (i = 0; i < bnad->num_tx; i++) { 725 for (j = 0; j < bnad->num_txq_per_tx; j++) { 726 tcb = bnad->tx_info[i].tcb[j]; 727 if (tcb && test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) 728 bnad_tx_complete(bnad, bnad->tx_info[i].tcb[j]); 729 } 730 } 731 /* Rx processing */ 732 for (i = 0; i < bnad->num_rx; i++) { 733 rx_info = &bnad->rx_info[i]; 734 if (!rx_info->rx) 735 continue; 736 for (j = 0; j < bnad->num_rxp_per_rx; j++) { 737 rx_ctrl = &rx_info->rx_ctrl[j]; 738 if (rx_ctrl->ccb) 739 bnad_netif_rx_schedule_poll(bnad, 740 rx_ctrl->ccb); 741 } 742 } 743 return IRQ_HANDLED; 744 } 745 746 /* 747 * Called in interrupt / callback context 748 * with bna_lock held, so cfg_flags access is OK 749 */ 750 static void 751 bnad_enable_mbox_irq(struct bnad *bnad) 752 { 753 clear_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags); 754 755 BNAD_UPDATE_CTR(bnad, mbox_intr_enabled); 756 } 757 758 /* 759 * Called with bnad->bna_lock held b'cos of 760 * bnad->cfg_flags access. 761 */ 762 static void 763 bnad_disable_mbox_irq(struct bnad *bnad) 764 { 765 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags); 766 767 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled); 768 } 769 770 static void 771 bnad_set_netdev_perm_addr(struct bnad *bnad) 772 { 773 struct net_device *netdev = bnad->netdev; 774 775 memcpy(netdev->perm_addr, &bnad->perm_addr, netdev->addr_len); 776 if (is_zero_ether_addr(netdev->dev_addr)) 777 memcpy(netdev->dev_addr, &bnad->perm_addr, netdev->addr_len); 778 } 779 780 /* Control Path Handlers */ 781 782 /* Callbacks */ 783 void 784 bnad_cb_mbox_intr_enable(struct bnad *bnad) 785 { 786 bnad_enable_mbox_irq(bnad); 787 } 788 789 void 790 bnad_cb_mbox_intr_disable(struct bnad *bnad) 791 { 792 bnad_disable_mbox_irq(bnad); 793 } 794 795 void 796 bnad_cb_ioceth_ready(struct bnad *bnad) 797 { 798 bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS; 799 complete(&bnad->bnad_completions.ioc_comp); 800 } 801 802 void 803 bnad_cb_ioceth_failed(struct bnad *bnad) 804 { 805 bnad->bnad_completions.ioc_comp_status = BNA_CB_FAIL; 806 complete(&bnad->bnad_completions.ioc_comp); 807 } 808 809 void 810 bnad_cb_ioceth_disabled(struct bnad *bnad) 811 { 812 bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS; 813 complete(&bnad->bnad_completions.ioc_comp); 814 } 815 816 static void 817 bnad_cb_enet_disabled(void *arg) 818 { 819 struct bnad *bnad = (struct bnad *)arg; 820 821 netif_carrier_off(bnad->netdev); 822 complete(&bnad->bnad_completions.enet_comp); 823 } 824 825 void 826 bnad_cb_ethport_link_status(struct bnad *bnad, 827 enum bna_link_status link_status) 828 { 829 bool link_up = false; 830 831 link_up = (link_status == BNA_LINK_UP) || (link_status == BNA_CEE_UP); 832 833 if (link_status == BNA_CEE_UP) { 834 if (!test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) 835 BNAD_UPDATE_CTR(bnad, cee_toggle); 836 set_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags); 837 } else { 838 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) 839 BNAD_UPDATE_CTR(bnad, cee_toggle); 840 clear_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags); 841 } 842 843 if (link_up) { 844 if (!netif_carrier_ok(bnad->netdev)) { 845 uint tx_id, tcb_id; 846 printk(KERN_WARNING "bna: %s link up\n", 847 bnad->netdev->name); 848 netif_carrier_on(bnad->netdev); 849 BNAD_UPDATE_CTR(bnad, link_toggle); 850 for (tx_id = 0; tx_id < bnad->num_tx; tx_id++) { 851 for (tcb_id = 0; tcb_id < bnad->num_txq_per_tx; 852 tcb_id++) { 853 struct bna_tcb *tcb = 854 bnad->tx_info[tx_id].tcb[tcb_id]; 855 u32 txq_id; 856 if (!tcb) 857 continue; 858 859 txq_id = tcb->id; 860 861 if (test_bit(BNAD_TXQ_TX_STARTED, 862 &tcb->flags)) { 863 /* 864 * Force an immediate 865 * Transmit Schedule */ 866 printk(KERN_INFO "bna: %s %d " 867 "TXQ_STARTED\n", 868 bnad->netdev->name, 869 txq_id); 870 netif_wake_subqueue( 871 bnad->netdev, 872 txq_id); 873 BNAD_UPDATE_CTR(bnad, 874 netif_queue_wakeup); 875 } else { 876 netif_stop_subqueue( 877 bnad->netdev, 878 txq_id); 879 BNAD_UPDATE_CTR(bnad, 880 netif_queue_stop); 881 } 882 } 883 } 884 } 885 } else { 886 if (netif_carrier_ok(bnad->netdev)) { 887 printk(KERN_WARNING "bna: %s link down\n", 888 bnad->netdev->name); 889 netif_carrier_off(bnad->netdev); 890 BNAD_UPDATE_CTR(bnad, link_toggle); 891 } 892 } 893 } 894 895 static void 896 bnad_cb_tx_disabled(void *arg, struct bna_tx *tx) 897 { 898 struct bnad *bnad = (struct bnad *)arg; 899 900 complete(&bnad->bnad_completions.tx_comp); 901 } 902 903 static void 904 bnad_cb_tcb_setup(struct bnad *bnad, struct bna_tcb *tcb) 905 { 906 struct bnad_tx_info *tx_info = 907 (struct bnad_tx_info *)tcb->txq->tx->priv; 908 909 tcb->priv = tcb; 910 tx_info->tcb[tcb->id] = tcb; 911 } 912 913 static void 914 bnad_cb_tcb_destroy(struct bnad *bnad, struct bna_tcb *tcb) 915 { 916 struct bnad_tx_info *tx_info = 917 (struct bnad_tx_info *)tcb->txq->tx->priv; 918 919 tx_info->tcb[tcb->id] = NULL; 920 tcb->priv = NULL; 921 } 922 923 static void 924 bnad_cb_ccb_setup(struct bnad *bnad, struct bna_ccb *ccb) 925 { 926 struct bnad_rx_info *rx_info = 927 (struct bnad_rx_info *)ccb->cq->rx->priv; 928 929 rx_info->rx_ctrl[ccb->id].ccb = ccb; 930 ccb->ctrl = &rx_info->rx_ctrl[ccb->id]; 931 } 932 933 static void 934 bnad_cb_ccb_destroy(struct bnad *bnad, struct bna_ccb *ccb) 935 { 936 struct bnad_rx_info *rx_info = 937 (struct bnad_rx_info *)ccb->cq->rx->priv; 938 939 rx_info->rx_ctrl[ccb->id].ccb = NULL; 940 } 941 942 static void 943 bnad_cb_tx_stall(struct bnad *bnad, struct bna_tx *tx) 944 { 945 struct bnad_tx_info *tx_info = 946 (struct bnad_tx_info *)tx->priv; 947 struct bna_tcb *tcb; 948 u32 txq_id; 949 int i; 950 951 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) { 952 tcb = tx_info->tcb[i]; 953 if (!tcb) 954 continue; 955 txq_id = tcb->id; 956 clear_bit(BNAD_TXQ_TX_STARTED, &tcb->flags); 957 netif_stop_subqueue(bnad->netdev, txq_id); 958 printk(KERN_INFO "bna: %s %d TXQ_STOPPED\n", 959 bnad->netdev->name, txq_id); 960 } 961 } 962 963 static void 964 bnad_cb_tx_resume(struct bnad *bnad, struct bna_tx *tx) 965 { 966 struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv; 967 struct bna_tcb *tcb; 968 u32 txq_id; 969 int i; 970 971 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) { 972 tcb = tx_info->tcb[i]; 973 if (!tcb) 974 continue; 975 txq_id = tcb->id; 976 977 BUG_ON(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)); 978 set_bit(BNAD_TXQ_TX_STARTED, &tcb->flags); 979 BUG_ON(*(tcb->hw_consumer_index) != 0); 980 981 if (netif_carrier_ok(bnad->netdev)) { 982 printk(KERN_INFO "bna: %s %d TXQ_STARTED\n", 983 bnad->netdev->name, txq_id); 984 netif_wake_subqueue(bnad->netdev, txq_id); 985 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup); 986 } 987 } 988 989 /* 990 * Workaround for first ioceth enable failure & we 991 * get a 0 MAC address. We try to get the MAC address 992 * again here. 993 */ 994 if (is_zero_ether_addr(&bnad->perm_addr.mac[0])) { 995 bna_enet_perm_mac_get(&bnad->bna.enet, &bnad->perm_addr); 996 bnad_set_netdev_perm_addr(bnad); 997 } 998 } 999 1000 /* 1001 * Free all TxQs buffers and then notify TX_E_CLEANUP_DONE to Tx fsm. 1002 */ 1003 static void 1004 bnad_tx_cleanup(struct delayed_work *work) 1005 { 1006 struct bnad_tx_info *tx_info = 1007 container_of(work, struct bnad_tx_info, tx_cleanup_work); 1008 struct bnad *bnad = NULL; 1009 struct bna_tcb *tcb; 1010 unsigned long flags; 1011 u32 i, pending = 0; 1012 1013 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) { 1014 tcb = tx_info->tcb[i]; 1015 if (!tcb) 1016 continue; 1017 1018 bnad = tcb->bnad; 1019 1020 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) { 1021 pending++; 1022 continue; 1023 } 1024 1025 bnad_txq_cleanup(bnad, tcb); 1026 1027 smp_mb__before_clear_bit(); 1028 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags); 1029 } 1030 1031 if (pending) { 1032 queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work, 1033 msecs_to_jiffies(1)); 1034 return; 1035 } 1036 1037 spin_lock_irqsave(&bnad->bna_lock, flags); 1038 bna_tx_cleanup_complete(tx_info->tx); 1039 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1040 } 1041 1042 static void 1043 bnad_cb_tx_cleanup(struct bnad *bnad, struct bna_tx *tx) 1044 { 1045 struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv; 1046 struct bna_tcb *tcb; 1047 int i; 1048 1049 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) { 1050 tcb = tx_info->tcb[i]; 1051 if (!tcb) 1052 continue; 1053 } 1054 1055 queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work, 0); 1056 } 1057 1058 static void 1059 bnad_cb_rx_stall(struct bnad *bnad, struct bna_rx *rx) 1060 { 1061 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv; 1062 struct bna_ccb *ccb; 1063 struct bnad_rx_ctrl *rx_ctrl; 1064 int i; 1065 1066 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) { 1067 rx_ctrl = &rx_info->rx_ctrl[i]; 1068 ccb = rx_ctrl->ccb; 1069 if (!ccb) 1070 continue; 1071 1072 clear_bit(BNAD_RXQ_POST_OK, &ccb->rcb[0]->flags); 1073 1074 if (ccb->rcb[1]) 1075 clear_bit(BNAD_RXQ_POST_OK, &ccb->rcb[1]->flags); 1076 } 1077 } 1078 1079 /* 1080 * Free all RxQs buffers and then notify RX_E_CLEANUP_DONE to Rx fsm. 1081 */ 1082 static void 1083 bnad_rx_cleanup(void *work) 1084 { 1085 struct bnad_rx_info *rx_info = 1086 container_of(work, struct bnad_rx_info, rx_cleanup_work); 1087 struct bnad_rx_ctrl *rx_ctrl; 1088 struct bnad *bnad = NULL; 1089 unsigned long flags; 1090 u32 i; 1091 1092 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) { 1093 rx_ctrl = &rx_info->rx_ctrl[i]; 1094 1095 if (!rx_ctrl->ccb) 1096 continue; 1097 1098 bnad = rx_ctrl->ccb->bnad; 1099 1100 /* 1101 * Wait till the poll handler has exited 1102 * and nothing can be scheduled anymore 1103 */ 1104 napi_disable(&rx_ctrl->napi); 1105 1106 bnad_cq_cleanup(bnad, rx_ctrl->ccb); 1107 bnad_rxq_cleanup(bnad, rx_ctrl->ccb->rcb[0]); 1108 if (rx_ctrl->ccb->rcb[1]) 1109 bnad_rxq_cleanup(bnad, rx_ctrl->ccb->rcb[1]); 1110 } 1111 1112 spin_lock_irqsave(&bnad->bna_lock, flags); 1113 bna_rx_cleanup_complete(rx_info->rx); 1114 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1115 } 1116 1117 static void 1118 bnad_cb_rx_cleanup(struct bnad *bnad, struct bna_rx *rx) 1119 { 1120 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv; 1121 struct bna_ccb *ccb; 1122 struct bnad_rx_ctrl *rx_ctrl; 1123 int i; 1124 1125 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) { 1126 rx_ctrl = &rx_info->rx_ctrl[i]; 1127 ccb = rx_ctrl->ccb; 1128 if (!ccb) 1129 continue; 1130 1131 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags); 1132 1133 if (ccb->rcb[1]) 1134 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[1]->flags); 1135 } 1136 1137 queue_work(bnad->work_q, &rx_info->rx_cleanup_work); 1138 } 1139 1140 static void 1141 bnad_cb_rx_post(struct bnad *bnad, struct bna_rx *rx) 1142 { 1143 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv; 1144 struct bna_ccb *ccb; 1145 struct bna_rcb *rcb; 1146 struct bnad_rx_ctrl *rx_ctrl; 1147 int i, j; 1148 1149 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) { 1150 rx_ctrl = &rx_info->rx_ctrl[i]; 1151 ccb = rx_ctrl->ccb; 1152 if (!ccb) 1153 continue; 1154 1155 napi_enable(&rx_ctrl->napi); 1156 1157 for (j = 0; j < BNAD_MAX_RXQ_PER_RXP; j++) { 1158 rcb = ccb->rcb[j]; 1159 if (!rcb) 1160 continue; 1161 1162 bnad_rxq_alloc_init(bnad, rcb); 1163 set_bit(BNAD_RXQ_STARTED, &rcb->flags); 1164 set_bit(BNAD_RXQ_POST_OK, &rcb->flags); 1165 bnad_rxq_post(bnad, rcb); 1166 } 1167 } 1168 } 1169 1170 static void 1171 bnad_cb_rx_disabled(void *arg, struct bna_rx *rx) 1172 { 1173 struct bnad *bnad = (struct bnad *)arg; 1174 1175 complete(&bnad->bnad_completions.rx_comp); 1176 } 1177 1178 static void 1179 bnad_cb_rx_mcast_add(struct bnad *bnad, struct bna_rx *rx) 1180 { 1181 bnad->bnad_completions.mcast_comp_status = BNA_CB_SUCCESS; 1182 complete(&bnad->bnad_completions.mcast_comp); 1183 } 1184 1185 void 1186 bnad_cb_stats_get(struct bnad *bnad, enum bna_cb_status status, 1187 struct bna_stats *stats) 1188 { 1189 if (status == BNA_CB_SUCCESS) 1190 BNAD_UPDATE_CTR(bnad, hw_stats_updates); 1191 1192 if (!netif_running(bnad->netdev) || 1193 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) 1194 return; 1195 1196 mod_timer(&bnad->stats_timer, 1197 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ)); 1198 } 1199 1200 static void 1201 bnad_cb_enet_mtu_set(struct bnad *bnad) 1202 { 1203 bnad->bnad_completions.mtu_comp_status = BNA_CB_SUCCESS; 1204 complete(&bnad->bnad_completions.mtu_comp); 1205 } 1206 1207 void 1208 bnad_cb_completion(void *arg, enum bfa_status status) 1209 { 1210 struct bnad_iocmd_comp *iocmd_comp = 1211 (struct bnad_iocmd_comp *)arg; 1212 1213 iocmd_comp->comp_status = (u32) status; 1214 complete(&iocmd_comp->comp); 1215 } 1216 1217 /* Resource allocation, free functions */ 1218 1219 static void 1220 bnad_mem_free(struct bnad *bnad, 1221 struct bna_mem_info *mem_info) 1222 { 1223 int i; 1224 dma_addr_t dma_pa; 1225 1226 if (mem_info->mdl == NULL) 1227 return; 1228 1229 for (i = 0; i < mem_info->num; i++) { 1230 if (mem_info->mdl[i].kva != NULL) { 1231 if (mem_info->mem_type == BNA_MEM_T_DMA) { 1232 BNA_GET_DMA_ADDR(&(mem_info->mdl[i].dma), 1233 dma_pa); 1234 dma_free_coherent(&bnad->pcidev->dev, 1235 mem_info->mdl[i].len, 1236 mem_info->mdl[i].kva, dma_pa); 1237 } else 1238 kfree(mem_info->mdl[i].kva); 1239 } 1240 } 1241 kfree(mem_info->mdl); 1242 mem_info->mdl = NULL; 1243 } 1244 1245 static int 1246 bnad_mem_alloc(struct bnad *bnad, 1247 struct bna_mem_info *mem_info) 1248 { 1249 int i; 1250 dma_addr_t dma_pa; 1251 1252 if ((mem_info->num == 0) || (mem_info->len == 0)) { 1253 mem_info->mdl = NULL; 1254 return 0; 1255 } 1256 1257 mem_info->mdl = kcalloc(mem_info->num, sizeof(struct bna_mem_descr), 1258 GFP_KERNEL); 1259 if (mem_info->mdl == NULL) 1260 return -ENOMEM; 1261 1262 if (mem_info->mem_type == BNA_MEM_T_DMA) { 1263 for (i = 0; i < mem_info->num; i++) { 1264 mem_info->mdl[i].len = mem_info->len; 1265 mem_info->mdl[i].kva = 1266 dma_alloc_coherent(&bnad->pcidev->dev, 1267 mem_info->len, &dma_pa, 1268 GFP_KERNEL); 1269 1270 if (mem_info->mdl[i].kva == NULL) 1271 goto err_return; 1272 1273 BNA_SET_DMA_ADDR(dma_pa, 1274 &(mem_info->mdl[i].dma)); 1275 } 1276 } else { 1277 for (i = 0; i < mem_info->num; i++) { 1278 mem_info->mdl[i].len = mem_info->len; 1279 mem_info->mdl[i].kva = kzalloc(mem_info->len, 1280 GFP_KERNEL); 1281 if (mem_info->mdl[i].kva == NULL) 1282 goto err_return; 1283 } 1284 } 1285 1286 return 0; 1287 1288 err_return: 1289 bnad_mem_free(bnad, mem_info); 1290 return -ENOMEM; 1291 } 1292 1293 /* Free IRQ for Mailbox */ 1294 static void 1295 bnad_mbox_irq_free(struct bnad *bnad) 1296 { 1297 int irq; 1298 unsigned long flags; 1299 1300 spin_lock_irqsave(&bnad->bna_lock, flags); 1301 bnad_disable_mbox_irq(bnad); 1302 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1303 1304 irq = BNAD_GET_MBOX_IRQ(bnad); 1305 free_irq(irq, bnad); 1306 } 1307 1308 /* 1309 * Allocates IRQ for Mailbox, but keep it disabled 1310 * This will be enabled once we get the mbox enable callback 1311 * from bna 1312 */ 1313 static int 1314 bnad_mbox_irq_alloc(struct bnad *bnad) 1315 { 1316 int err = 0; 1317 unsigned long irq_flags, flags; 1318 u32 irq; 1319 irq_handler_t irq_handler; 1320 1321 spin_lock_irqsave(&bnad->bna_lock, flags); 1322 if (bnad->cfg_flags & BNAD_CF_MSIX) { 1323 irq_handler = (irq_handler_t)bnad_msix_mbox_handler; 1324 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector; 1325 irq_flags = 0; 1326 } else { 1327 irq_handler = (irq_handler_t)bnad_isr; 1328 irq = bnad->pcidev->irq; 1329 irq_flags = IRQF_SHARED; 1330 } 1331 1332 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1333 sprintf(bnad->mbox_irq_name, "%s", BNAD_NAME); 1334 1335 /* 1336 * Set the Mbox IRQ disable flag, so that the IRQ handler 1337 * called from request_irq() for SHARED IRQs do not execute 1338 */ 1339 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags); 1340 1341 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled); 1342 1343 err = request_irq(irq, irq_handler, irq_flags, 1344 bnad->mbox_irq_name, bnad); 1345 1346 return err; 1347 } 1348 1349 static void 1350 bnad_txrx_irq_free(struct bnad *bnad, struct bna_intr_info *intr_info) 1351 { 1352 kfree(intr_info->idl); 1353 intr_info->idl = NULL; 1354 } 1355 1356 /* Allocates Interrupt Descriptor List for MSIX/INT-X vectors */ 1357 static int 1358 bnad_txrx_irq_alloc(struct bnad *bnad, enum bnad_intr_source src, 1359 u32 txrx_id, struct bna_intr_info *intr_info) 1360 { 1361 int i, vector_start = 0; 1362 u32 cfg_flags; 1363 unsigned long flags; 1364 1365 spin_lock_irqsave(&bnad->bna_lock, flags); 1366 cfg_flags = bnad->cfg_flags; 1367 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1368 1369 if (cfg_flags & BNAD_CF_MSIX) { 1370 intr_info->intr_type = BNA_INTR_T_MSIX; 1371 intr_info->idl = kcalloc(intr_info->num, 1372 sizeof(struct bna_intr_descr), 1373 GFP_KERNEL); 1374 if (!intr_info->idl) 1375 return -ENOMEM; 1376 1377 switch (src) { 1378 case BNAD_INTR_TX: 1379 vector_start = BNAD_MAILBOX_MSIX_VECTORS + txrx_id; 1380 break; 1381 1382 case BNAD_INTR_RX: 1383 vector_start = BNAD_MAILBOX_MSIX_VECTORS + 1384 (bnad->num_tx * bnad->num_txq_per_tx) + 1385 txrx_id; 1386 break; 1387 1388 default: 1389 BUG(); 1390 } 1391 1392 for (i = 0; i < intr_info->num; i++) 1393 intr_info->idl[i].vector = vector_start + i; 1394 } else { 1395 intr_info->intr_type = BNA_INTR_T_INTX; 1396 intr_info->num = 1; 1397 intr_info->idl = kcalloc(intr_info->num, 1398 sizeof(struct bna_intr_descr), 1399 GFP_KERNEL); 1400 if (!intr_info->idl) 1401 return -ENOMEM; 1402 1403 switch (src) { 1404 case BNAD_INTR_TX: 1405 intr_info->idl[0].vector = BNAD_INTX_TX_IB_BITMASK; 1406 break; 1407 1408 case BNAD_INTR_RX: 1409 intr_info->idl[0].vector = BNAD_INTX_RX_IB_BITMASK; 1410 break; 1411 } 1412 } 1413 return 0; 1414 } 1415 1416 /* NOTE: Should be called for MSIX only 1417 * Unregisters Tx MSIX vector(s) from the kernel 1418 */ 1419 static void 1420 bnad_tx_msix_unregister(struct bnad *bnad, struct bnad_tx_info *tx_info, 1421 int num_txqs) 1422 { 1423 int i; 1424 int vector_num; 1425 1426 for (i = 0; i < num_txqs; i++) { 1427 if (tx_info->tcb[i] == NULL) 1428 continue; 1429 1430 vector_num = tx_info->tcb[i]->intr_vector; 1431 free_irq(bnad->msix_table[vector_num].vector, tx_info->tcb[i]); 1432 } 1433 } 1434 1435 /* NOTE: Should be called for MSIX only 1436 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel 1437 */ 1438 static int 1439 bnad_tx_msix_register(struct bnad *bnad, struct bnad_tx_info *tx_info, 1440 u32 tx_id, int num_txqs) 1441 { 1442 int i; 1443 int err; 1444 int vector_num; 1445 1446 for (i = 0; i < num_txqs; i++) { 1447 vector_num = tx_info->tcb[i]->intr_vector; 1448 sprintf(tx_info->tcb[i]->name, "%s TXQ %d", bnad->netdev->name, 1449 tx_id + tx_info->tcb[i]->id); 1450 err = request_irq(bnad->msix_table[vector_num].vector, 1451 (irq_handler_t)bnad_msix_tx, 0, 1452 tx_info->tcb[i]->name, 1453 tx_info->tcb[i]); 1454 if (err) 1455 goto err_return; 1456 } 1457 1458 return 0; 1459 1460 err_return: 1461 if (i > 0) 1462 bnad_tx_msix_unregister(bnad, tx_info, (i - 1)); 1463 return -1; 1464 } 1465 1466 /* NOTE: Should be called for MSIX only 1467 * Unregisters Rx MSIX vector(s) from the kernel 1468 */ 1469 static void 1470 bnad_rx_msix_unregister(struct bnad *bnad, struct bnad_rx_info *rx_info, 1471 int num_rxps) 1472 { 1473 int i; 1474 int vector_num; 1475 1476 for (i = 0; i < num_rxps; i++) { 1477 if (rx_info->rx_ctrl[i].ccb == NULL) 1478 continue; 1479 1480 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector; 1481 free_irq(bnad->msix_table[vector_num].vector, 1482 rx_info->rx_ctrl[i].ccb); 1483 } 1484 } 1485 1486 /* NOTE: Should be called for MSIX only 1487 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel 1488 */ 1489 static int 1490 bnad_rx_msix_register(struct bnad *bnad, struct bnad_rx_info *rx_info, 1491 u32 rx_id, int num_rxps) 1492 { 1493 int i; 1494 int err; 1495 int vector_num; 1496 1497 for (i = 0; i < num_rxps; i++) { 1498 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector; 1499 sprintf(rx_info->rx_ctrl[i].ccb->name, "%s CQ %d", 1500 bnad->netdev->name, 1501 rx_id + rx_info->rx_ctrl[i].ccb->id); 1502 err = request_irq(bnad->msix_table[vector_num].vector, 1503 (irq_handler_t)bnad_msix_rx, 0, 1504 rx_info->rx_ctrl[i].ccb->name, 1505 rx_info->rx_ctrl[i].ccb); 1506 if (err) 1507 goto err_return; 1508 } 1509 1510 return 0; 1511 1512 err_return: 1513 if (i > 0) 1514 bnad_rx_msix_unregister(bnad, rx_info, (i - 1)); 1515 return -1; 1516 } 1517 1518 /* Free Tx object Resources */ 1519 static void 1520 bnad_tx_res_free(struct bnad *bnad, struct bna_res_info *res_info) 1521 { 1522 int i; 1523 1524 for (i = 0; i < BNA_TX_RES_T_MAX; i++) { 1525 if (res_info[i].res_type == BNA_RES_T_MEM) 1526 bnad_mem_free(bnad, &res_info[i].res_u.mem_info); 1527 else if (res_info[i].res_type == BNA_RES_T_INTR) 1528 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info); 1529 } 1530 } 1531 1532 /* Allocates memory and interrupt resources for Tx object */ 1533 static int 1534 bnad_tx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info, 1535 u32 tx_id) 1536 { 1537 int i, err = 0; 1538 1539 for (i = 0; i < BNA_TX_RES_T_MAX; i++) { 1540 if (res_info[i].res_type == BNA_RES_T_MEM) 1541 err = bnad_mem_alloc(bnad, 1542 &res_info[i].res_u.mem_info); 1543 else if (res_info[i].res_type == BNA_RES_T_INTR) 1544 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_TX, tx_id, 1545 &res_info[i].res_u.intr_info); 1546 if (err) 1547 goto err_return; 1548 } 1549 return 0; 1550 1551 err_return: 1552 bnad_tx_res_free(bnad, res_info); 1553 return err; 1554 } 1555 1556 /* Free Rx object Resources */ 1557 static void 1558 bnad_rx_res_free(struct bnad *bnad, struct bna_res_info *res_info) 1559 { 1560 int i; 1561 1562 for (i = 0; i < BNA_RX_RES_T_MAX; i++) { 1563 if (res_info[i].res_type == BNA_RES_T_MEM) 1564 bnad_mem_free(bnad, &res_info[i].res_u.mem_info); 1565 else if (res_info[i].res_type == BNA_RES_T_INTR) 1566 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info); 1567 } 1568 } 1569 1570 /* Allocates memory and interrupt resources for Rx object */ 1571 static int 1572 bnad_rx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info, 1573 uint rx_id) 1574 { 1575 int i, err = 0; 1576 1577 /* All memory needs to be allocated before setup_ccbs */ 1578 for (i = 0; i < BNA_RX_RES_T_MAX; i++) { 1579 if (res_info[i].res_type == BNA_RES_T_MEM) 1580 err = bnad_mem_alloc(bnad, 1581 &res_info[i].res_u.mem_info); 1582 else if (res_info[i].res_type == BNA_RES_T_INTR) 1583 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_RX, rx_id, 1584 &res_info[i].res_u.intr_info); 1585 if (err) 1586 goto err_return; 1587 } 1588 return 0; 1589 1590 err_return: 1591 bnad_rx_res_free(bnad, res_info); 1592 return err; 1593 } 1594 1595 /* Timer callbacks */ 1596 /* a) IOC timer */ 1597 static void 1598 bnad_ioc_timeout(unsigned long data) 1599 { 1600 struct bnad *bnad = (struct bnad *)data; 1601 unsigned long flags; 1602 1603 spin_lock_irqsave(&bnad->bna_lock, flags); 1604 bfa_nw_ioc_timeout((void *) &bnad->bna.ioceth.ioc); 1605 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1606 } 1607 1608 static void 1609 bnad_ioc_hb_check(unsigned long data) 1610 { 1611 struct bnad *bnad = (struct bnad *)data; 1612 unsigned long flags; 1613 1614 spin_lock_irqsave(&bnad->bna_lock, flags); 1615 bfa_nw_ioc_hb_check((void *) &bnad->bna.ioceth.ioc); 1616 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1617 } 1618 1619 static void 1620 bnad_iocpf_timeout(unsigned long data) 1621 { 1622 struct bnad *bnad = (struct bnad *)data; 1623 unsigned long flags; 1624 1625 spin_lock_irqsave(&bnad->bna_lock, flags); 1626 bfa_nw_iocpf_timeout((void *) &bnad->bna.ioceth.ioc); 1627 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1628 } 1629 1630 static void 1631 bnad_iocpf_sem_timeout(unsigned long data) 1632 { 1633 struct bnad *bnad = (struct bnad *)data; 1634 unsigned long flags; 1635 1636 spin_lock_irqsave(&bnad->bna_lock, flags); 1637 bfa_nw_iocpf_sem_timeout((void *) &bnad->bna.ioceth.ioc); 1638 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1639 } 1640 1641 /* 1642 * All timer routines use bnad->bna_lock to protect against 1643 * the following race, which may occur in case of no locking: 1644 * Time CPU m CPU n 1645 * 0 1 = test_bit 1646 * 1 clear_bit 1647 * 2 del_timer_sync 1648 * 3 mod_timer 1649 */ 1650 1651 /* b) Dynamic Interrupt Moderation Timer */ 1652 static void 1653 bnad_dim_timeout(unsigned long data) 1654 { 1655 struct bnad *bnad = (struct bnad *)data; 1656 struct bnad_rx_info *rx_info; 1657 struct bnad_rx_ctrl *rx_ctrl; 1658 int i, j; 1659 unsigned long flags; 1660 1661 if (!netif_carrier_ok(bnad->netdev)) 1662 return; 1663 1664 spin_lock_irqsave(&bnad->bna_lock, flags); 1665 for (i = 0; i < bnad->num_rx; i++) { 1666 rx_info = &bnad->rx_info[i]; 1667 if (!rx_info->rx) 1668 continue; 1669 for (j = 0; j < bnad->num_rxp_per_rx; j++) { 1670 rx_ctrl = &rx_info->rx_ctrl[j]; 1671 if (!rx_ctrl->ccb) 1672 continue; 1673 bna_rx_dim_update(rx_ctrl->ccb); 1674 } 1675 } 1676 1677 /* Check for BNAD_CF_DIM_ENABLED, does not eleminate a race */ 1678 if (test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) 1679 mod_timer(&bnad->dim_timer, 1680 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ)); 1681 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1682 } 1683 1684 /* c) Statistics Timer */ 1685 static void 1686 bnad_stats_timeout(unsigned long data) 1687 { 1688 struct bnad *bnad = (struct bnad *)data; 1689 unsigned long flags; 1690 1691 if (!netif_running(bnad->netdev) || 1692 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) 1693 return; 1694 1695 spin_lock_irqsave(&bnad->bna_lock, flags); 1696 bna_hw_stats_get(&bnad->bna); 1697 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1698 } 1699 1700 /* 1701 * Set up timer for DIM 1702 * Called with bnad->bna_lock held 1703 */ 1704 void 1705 bnad_dim_timer_start(struct bnad *bnad) 1706 { 1707 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED && 1708 !test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) { 1709 setup_timer(&bnad->dim_timer, bnad_dim_timeout, 1710 (unsigned long)bnad); 1711 set_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags); 1712 mod_timer(&bnad->dim_timer, 1713 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ)); 1714 } 1715 } 1716 1717 /* 1718 * Set up timer for statistics 1719 * Called with mutex_lock(&bnad->conf_mutex) held 1720 */ 1721 static void 1722 bnad_stats_timer_start(struct bnad *bnad) 1723 { 1724 unsigned long flags; 1725 1726 spin_lock_irqsave(&bnad->bna_lock, flags); 1727 if (!test_and_set_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) { 1728 setup_timer(&bnad->stats_timer, bnad_stats_timeout, 1729 (unsigned long)bnad); 1730 mod_timer(&bnad->stats_timer, 1731 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ)); 1732 } 1733 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1734 } 1735 1736 /* 1737 * Stops the stats timer 1738 * Called with mutex_lock(&bnad->conf_mutex) held 1739 */ 1740 static void 1741 bnad_stats_timer_stop(struct bnad *bnad) 1742 { 1743 int to_del = 0; 1744 unsigned long flags; 1745 1746 spin_lock_irqsave(&bnad->bna_lock, flags); 1747 if (test_and_clear_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) 1748 to_del = 1; 1749 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1750 if (to_del) 1751 del_timer_sync(&bnad->stats_timer); 1752 } 1753 1754 /* Utilities */ 1755 1756 static void 1757 bnad_netdev_mc_list_get(struct net_device *netdev, u8 *mc_list) 1758 { 1759 int i = 1; /* Index 0 has broadcast address */ 1760 struct netdev_hw_addr *mc_addr; 1761 1762 netdev_for_each_mc_addr(mc_addr, netdev) { 1763 memcpy(&mc_list[i * ETH_ALEN], &mc_addr->addr[0], 1764 ETH_ALEN); 1765 i++; 1766 } 1767 } 1768 1769 static int 1770 bnad_napi_poll_rx(struct napi_struct *napi, int budget) 1771 { 1772 struct bnad_rx_ctrl *rx_ctrl = 1773 container_of(napi, struct bnad_rx_ctrl, napi); 1774 struct bnad *bnad = rx_ctrl->bnad; 1775 int rcvd = 0; 1776 1777 rx_ctrl->rx_poll_ctr++; 1778 1779 if (!netif_carrier_ok(bnad->netdev)) 1780 goto poll_exit; 1781 1782 rcvd = bnad_cq_process(bnad, rx_ctrl->ccb, budget); 1783 if (rcvd >= budget) 1784 return rcvd; 1785 1786 poll_exit: 1787 napi_complete(napi); 1788 1789 rx_ctrl->rx_complete++; 1790 1791 if (rx_ctrl->ccb) 1792 bnad_enable_rx_irq_unsafe(rx_ctrl->ccb); 1793 1794 return rcvd; 1795 } 1796 1797 #define BNAD_NAPI_POLL_QUOTA 64 1798 static void 1799 bnad_napi_add(struct bnad *bnad, u32 rx_id) 1800 { 1801 struct bnad_rx_ctrl *rx_ctrl; 1802 int i; 1803 1804 /* Initialize & enable NAPI */ 1805 for (i = 0; i < bnad->num_rxp_per_rx; i++) { 1806 rx_ctrl = &bnad->rx_info[rx_id].rx_ctrl[i]; 1807 netif_napi_add(bnad->netdev, &rx_ctrl->napi, 1808 bnad_napi_poll_rx, BNAD_NAPI_POLL_QUOTA); 1809 } 1810 } 1811 1812 static void 1813 bnad_napi_delete(struct bnad *bnad, u32 rx_id) 1814 { 1815 int i; 1816 1817 /* First disable and then clean up */ 1818 for (i = 0; i < bnad->num_rxp_per_rx; i++) 1819 netif_napi_del(&bnad->rx_info[rx_id].rx_ctrl[i].napi); 1820 } 1821 1822 /* Should be held with conf_lock held */ 1823 void 1824 bnad_destroy_tx(struct bnad *bnad, u32 tx_id) 1825 { 1826 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id]; 1827 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0]; 1828 unsigned long flags; 1829 1830 if (!tx_info->tx) 1831 return; 1832 1833 init_completion(&bnad->bnad_completions.tx_comp); 1834 spin_lock_irqsave(&bnad->bna_lock, flags); 1835 bna_tx_disable(tx_info->tx, BNA_HARD_CLEANUP, bnad_cb_tx_disabled); 1836 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1837 wait_for_completion(&bnad->bnad_completions.tx_comp); 1838 1839 if (tx_info->tcb[0]->intr_type == BNA_INTR_T_MSIX) 1840 bnad_tx_msix_unregister(bnad, tx_info, 1841 bnad->num_txq_per_tx); 1842 1843 spin_lock_irqsave(&bnad->bna_lock, flags); 1844 bna_tx_destroy(tx_info->tx); 1845 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1846 1847 tx_info->tx = NULL; 1848 tx_info->tx_id = 0; 1849 1850 bnad_tx_res_free(bnad, res_info); 1851 } 1852 1853 /* Should be held with conf_lock held */ 1854 int 1855 bnad_setup_tx(struct bnad *bnad, u32 tx_id) 1856 { 1857 int err; 1858 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id]; 1859 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0]; 1860 struct bna_intr_info *intr_info = 1861 &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info; 1862 struct bna_tx_config *tx_config = &bnad->tx_config[tx_id]; 1863 static const struct bna_tx_event_cbfn tx_cbfn = { 1864 .tcb_setup_cbfn = bnad_cb_tcb_setup, 1865 .tcb_destroy_cbfn = bnad_cb_tcb_destroy, 1866 .tx_stall_cbfn = bnad_cb_tx_stall, 1867 .tx_resume_cbfn = bnad_cb_tx_resume, 1868 .tx_cleanup_cbfn = bnad_cb_tx_cleanup, 1869 }; 1870 1871 struct bna_tx *tx; 1872 unsigned long flags; 1873 1874 tx_info->tx_id = tx_id; 1875 1876 /* Initialize the Tx object configuration */ 1877 tx_config->num_txq = bnad->num_txq_per_tx; 1878 tx_config->txq_depth = bnad->txq_depth; 1879 tx_config->tx_type = BNA_TX_T_REGULAR; 1880 tx_config->coalescing_timeo = bnad->tx_coalescing_timeo; 1881 1882 /* Get BNA's resource requirement for one tx object */ 1883 spin_lock_irqsave(&bnad->bna_lock, flags); 1884 bna_tx_res_req(bnad->num_txq_per_tx, 1885 bnad->txq_depth, res_info); 1886 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1887 1888 /* Fill Unmap Q memory requirements */ 1889 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_TX_RES_MEM_T_UNMAPQ], 1890 bnad->num_txq_per_tx, (sizeof(struct bnad_tx_unmap) * 1891 bnad->txq_depth)); 1892 1893 /* Allocate resources */ 1894 err = bnad_tx_res_alloc(bnad, res_info, tx_id); 1895 if (err) 1896 return err; 1897 1898 /* Ask BNA to create one Tx object, supplying required resources */ 1899 spin_lock_irqsave(&bnad->bna_lock, flags); 1900 tx = bna_tx_create(&bnad->bna, bnad, tx_config, &tx_cbfn, res_info, 1901 tx_info); 1902 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1903 if (!tx) 1904 goto err_return; 1905 tx_info->tx = tx; 1906 1907 INIT_DELAYED_WORK(&tx_info->tx_cleanup_work, 1908 (work_func_t)bnad_tx_cleanup); 1909 1910 /* Register ISR for the Tx object */ 1911 if (intr_info->intr_type == BNA_INTR_T_MSIX) { 1912 err = bnad_tx_msix_register(bnad, tx_info, 1913 tx_id, bnad->num_txq_per_tx); 1914 if (err) 1915 goto err_return; 1916 } 1917 1918 spin_lock_irqsave(&bnad->bna_lock, flags); 1919 bna_tx_enable(tx); 1920 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1921 1922 return 0; 1923 1924 err_return: 1925 bnad_tx_res_free(bnad, res_info); 1926 return err; 1927 } 1928 1929 /* Setup the rx config for bna_rx_create */ 1930 /* bnad decides the configuration */ 1931 static void 1932 bnad_init_rx_config(struct bnad *bnad, struct bna_rx_config *rx_config) 1933 { 1934 rx_config->rx_type = BNA_RX_T_REGULAR; 1935 rx_config->num_paths = bnad->num_rxp_per_rx; 1936 rx_config->coalescing_timeo = bnad->rx_coalescing_timeo; 1937 1938 if (bnad->num_rxp_per_rx > 1) { 1939 rx_config->rss_status = BNA_STATUS_T_ENABLED; 1940 rx_config->rss_config.hash_type = 1941 (BFI_ENET_RSS_IPV6 | 1942 BFI_ENET_RSS_IPV6_TCP | 1943 BFI_ENET_RSS_IPV4 | 1944 BFI_ENET_RSS_IPV4_TCP); 1945 rx_config->rss_config.hash_mask = 1946 bnad->num_rxp_per_rx - 1; 1947 get_random_bytes(rx_config->rss_config.toeplitz_hash_key, 1948 sizeof(rx_config->rss_config.toeplitz_hash_key)); 1949 } else { 1950 rx_config->rss_status = BNA_STATUS_T_DISABLED; 1951 memset(&rx_config->rss_config, 0, 1952 sizeof(rx_config->rss_config)); 1953 } 1954 rx_config->rxp_type = BNA_RXP_SLR; 1955 rx_config->q_depth = bnad->rxq_depth; 1956 1957 rx_config->small_buff_size = BFI_SMALL_RXBUF_SIZE; 1958 1959 rx_config->vlan_strip_status = BNA_STATUS_T_ENABLED; 1960 } 1961 1962 static void 1963 bnad_rx_ctrl_init(struct bnad *bnad, u32 rx_id) 1964 { 1965 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id]; 1966 int i; 1967 1968 for (i = 0; i < bnad->num_rxp_per_rx; i++) 1969 rx_info->rx_ctrl[i].bnad = bnad; 1970 } 1971 1972 /* Called with mutex_lock(&bnad->conf_mutex) held */ 1973 void 1974 bnad_destroy_rx(struct bnad *bnad, u32 rx_id) 1975 { 1976 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id]; 1977 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id]; 1978 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0]; 1979 unsigned long flags; 1980 int to_del = 0; 1981 1982 if (!rx_info->rx) 1983 return; 1984 1985 if (0 == rx_id) { 1986 spin_lock_irqsave(&bnad->bna_lock, flags); 1987 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED && 1988 test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) { 1989 clear_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags); 1990 to_del = 1; 1991 } 1992 spin_unlock_irqrestore(&bnad->bna_lock, flags); 1993 if (to_del) 1994 del_timer_sync(&bnad->dim_timer); 1995 } 1996 1997 init_completion(&bnad->bnad_completions.rx_comp); 1998 spin_lock_irqsave(&bnad->bna_lock, flags); 1999 bna_rx_disable(rx_info->rx, BNA_HARD_CLEANUP, bnad_cb_rx_disabled); 2000 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2001 wait_for_completion(&bnad->bnad_completions.rx_comp); 2002 2003 if (rx_info->rx_ctrl[0].ccb->intr_type == BNA_INTR_T_MSIX) 2004 bnad_rx_msix_unregister(bnad, rx_info, rx_config->num_paths); 2005 2006 bnad_napi_delete(bnad, rx_id); 2007 2008 spin_lock_irqsave(&bnad->bna_lock, flags); 2009 bna_rx_destroy(rx_info->rx); 2010 2011 rx_info->rx = NULL; 2012 rx_info->rx_id = 0; 2013 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2014 2015 bnad_rx_res_free(bnad, res_info); 2016 } 2017 2018 /* Called with mutex_lock(&bnad->conf_mutex) held */ 2019 int 2020 bnad_setup_rx(struct bnad *bnad, u32 rx_id) 2021 { 2022 int err; 2023 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id]; 2024 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0]; 2025 struct bna_intr_info *intr_info = 2026 &res_info[BNA_RX_RES_T_INTR].res_u.intr_info; 2027 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id]; 2028 static const struct bna_rx_event_cbfn rx_cbfn = { 2029 .rcb_setup_cbfn = NULL, 2030 .rcb_destroy_cbfn = NULL, 2031 .ccb_setup_cbfn = bnad_cb_ccb_setup, 2032 .ccb_destroy_cbfn = bnad_cb_ccb_destroy, 2033 .rx_stall_cbfn = bnad_cb_rx_stall, 2034 .rx_cleanup_cbfn = bnad_cb_rx_cleanup, 2035 .rx_post_cbfn = bnad_cb_rx_post, 2036 }; 2037 struct bna_rx *rx; 2038 unsigned long flags; 2039 2040 rx_info->rx_id = rx_id; 2041 2042 /* Initialize the Rx object configuration */ 2043 bnad_init_rx_config(bnad, rx_config); 2044 2045 /* Get BNA's resource requirement for one Rx object */ 2046 spin_lock_irqsave(&bnad->bna_lock, flags); 2047 bna_rx_res_req(rx_config, res_info); 2048 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2049 2050 /* Fill Unmap Q memory requirements */ 2051 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_RX_RES_MEM_T_UNMAPQ], 2052 rx_config->num_paths + 2053 ((rx_config->rxp_type == BNA_RXP_SINGLE) ? 2054 0 : rx_config->num_paths), 2055 ((bnad->rxq_depth * sizeof(struct bnad_rx_unmap)) + 2056 sizeof(struct bnad_rx_unmap_q))); 2057 2058 /* Allocate resource */ 2059 err = bnad_rx_res_alloc(bnad, res_info, rx_id); 2060 if (err) 2061 return err; 2062 2063 bnad_rx_ctrl_init(bnad, rx_id); 2064 2065 /* Ask BNA to create one Rx object, supplying required resources */ 2066 spin_lock_irqsave(&bnad->bna_lock, flags); 2067 rx = bna_rx_create(&bnad->bna, bnad, rx_config, &rx_cbfn, res_info, 2068 rx_info); 2069 if (!rx) { 2070 err = -ENOMEM; 2071 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2072 goto err_return; 2073 } 2074 rx_info->rx = rx; 2075 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2076 2077 INIT_WORK(&rx_info->rx_cleanup_work, 2078 (work_func_t)(bnad_rx_cleanup)); 2079 2080 /* 2081 * Init NAPI, so that state is set to NAPI_STATE_SCHED, 2082 * so that IRQ handler cannot schedule NAPI at this point. 2083 */ 2084 bnad_napi_add(bnad, rx_id); 2085 2086 /* Register ISR for the Rx object */ 2087 if (intr_info->intr_type == BNA_INTR_T_MSIX) { 2088 err = bnad_rx_msix_register(bnad, rx_info, rx_id, 2089 rx_config->num_paths); 2090 if (err) 2091 goto err_return; 2092 } 2093 2094 spin_lock_irqsave(&bnad->bna_lock, flags); 2095 if (0 == rx_id) { 2096 /* Set up Dynamic Interrupt Moderation Vector */ 2097 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED) 2098 bna_rx_dim_reconfig(&bnad->bna, bna_napi_dim_vector); 2099 2100 /* Enable VLAN filtering only on the default Rx */ 2101 bna_rx_vlanfilter_enable(rx); 2102 2103 /* Start the DIM timer */ 2104 bnad_dim_timer_start(bnad); 2105 } 2106 2107 bna_rx_enable(rx); 2108 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2109 2110 return 0; 2111 2112 err_return: 2113 bnad_destroy_rx(bnad, rx_id); 2114 return err; 2115 } 2116 2117 /* Called with conf_lock & bnad->bna_lock held */ 2118 void 2119 bnad_tx_coalescing_timeo_set(struct bnad *bnad) 2120 { 2121 struct bnad_tx_info *tx_info; 2122 2123 tx_info = &bnad->tx_info[0]; 2124 if (!tx_info->tx) 2125 return; 2126 2127 bna_tx_coalescing_timeo_set(tx_info->tx, bnad->tx_coalescing_timeo); 2128 } 2129 2130 /* Called with conf_lock & bnad->bna_lock held */ 2131 void 2132 bnad_rx_coalescing_timeo_set(struct bnad *bnad) 2133 { 2134 struct bnad_rx_info *rx_info; 2135 int i; 2136 2137 for (i = 0; i < bnad->num_rx; i++) { 2138 rx_info = &bnad->rx_info[i]; 2139 if (!rx_info->rx) 2140 continue; 2141 bna_rx_coalescing_timeo_set(rx_info->rx, 2142 bnad->rx_coalescing_timeo); 2143 } 2144 } 2145 2146 /* 2147 * Called with bnad->bna_lock held 2148 */ 2149 int 2150 bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr) 2151 { 2152 int ret; 2153 2154 if (!is_valid_ether_addr(mac_addr)) 2155 return -EADDRNOTAVAIL; 2156 2157 /* If datapath is down, pretend everything went through */ 2158 if (!bnad->rx_info[0].rx) 2159 return 0; 2160 2161 ret = bna_rx_ucast_set(bnad->rx_info[0].rx, mac_addr, NULL); 2162 if (ret != BNA_CB_SUCCESS) 2163 return -EADDRNOTAVAIL; 2164 2165 return 0; 2166 } 2167 2168 /* Should be called with conf_lock held */ 2169 int 2170 bnad_enable_default_bcast(struct bnad *bnad) 2171 { 2172 struct bnad_rx_info *rx_info = &bnad->rx_info[0]; 2173 int ret; 2174 unsigned long flags; 2175 2176 init_completion(&bnad->bnad_completions.mcast_comp); 2177 2178 spin_lock_irqsave(&bnad->bna_lock, flags); 2179 ret = bna_rx_mcast_add(rx_info->rx, (u8 *)bnad_bcast_addr, 2180 bnad_cb_rx_mcast_add); 2181 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2182 2183 if (ret == BNA_CB_SUCCESS) 2184 wait_for_completion(&bnad->bnad_completions.mcast_comp); 2185 else 2186 return -ENODEV; 2187 2188 if (bnad->bnad_completions.mcast_comp_status != BNA_CB_SUCCESS) 2189 return -ENODEV; 2190 2191 return 0; 2192 } 2193 2194 /* Called with mutex_lock(&bnad->conf_mutex) held */ 2195 void 2196 bnad_restore_vlans(struct bnad *bnad, u32 rx_id) 2197 { 2198 u16 vid; 2199 unsigned long flags; 2200 2201 for_each_set_bit(vid, bnad->active_vlans, VLAN_N_VID) { 2202 spin_lock_irqsave(&bnad->bna_lock, flags); 2203 bna_rx_vlan_add(bnad->rx_info[rx_id].rx, vid); 2204 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2205 } 2206 } 2207 2208 /* Statistics utilities */ 2209 void 2210 bnad_netdev_qstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats) 2211 { 2212 int i, j; 2213 2214 for (i = 0; i < bnad->num_rx; i++) { 2215 for (j = 0; j < bnad->num_rxp_per_rx; j++) { 2216 if (bnad->rx_info[i].rx_ctrl[j].ccb) { 2217 stats->rx_packets += bnad->rx_info[i]. 2218 rx_ctrl[j].ccb->rcb[0]->rxq->rx_packets; 2219 stats->rx_bytes += bnad->rx_info[i]. 2220 rx_ctrl[j].ccb->rcb[0]->rxq->rx_bytes; 2221 if (bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1] && 2222 bnad->rx_info[i].rx_ctrl[j].ccb-> 2223 rcb[1]->rxq) { 2224 stats->rx_packets += 2225 bnad->rx_info[i].rx_ctrl[j]. 2226 ccb->rcb[1]->rxq->rx_packets; 2227 stats->rx_bytes += 2228 bnad->rx_info[i].rx_ctrl[j]. 2229 ccb->rcb[1]->rxq->rx_bytes; 2230 } 2231 } 2232 } 2233 } 2234 for (i = 0; i < bnad->num_tx; i++) { 2235 for (j = 0; j < bnad->num_txq_per_tx; j++) { 2236 if (bnad->tx_info[i].tcb[j]) { 2237 stats->tx_packets += 2238 bnad->tx_info[i].tcb[j]->txq->tx_packets; 2239 stats->tx_bytes += 2240 bnad->tx_info[i].tcb[j]->txq->tx_bytes; 2241 } 2242 } 2243 } 2244 } 2245 2246 /* 2247 * Must be called with the bna_lock held. 2248 */ 2249 void 2250 bnad_netdev_hwstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats) 2251 { 2252 struct bfi_enet_stats_mac *mac_stats; 2253 u32 bmap; 2254 int i; 2255 2256 mac_stats = &bnad->stats.bna_stats->hw_stats.mac_stats; 2257 stats->rx_errors = 2258 mac_stats->rx_fcs_error + mac_stats->rx_alignment_error + 2259 mac_stats->rx_frame_length_error + mac_stats->rx_code_error + 2260 mac_stats->rx_undersize; 2261 stats->tx_errors = mac_stats->tx_fcs_error + 2262 mac_stats->tx_undersize; 2263 stats->rx_dropped = mac_stats->rx_drop; 2264 stats->tx_dropped = mac_stats->tx_drop; 2265 stats->multicast = mac_stats->rx_multicast; 2266 stats->collisions = mac_stats->tx_total_collision; 2267 2268 stats->rx_length_errors = mac_stats->rx_frame_length_error; 2269 2270 /* receive ring buffer overflow ?? */ 2271 2272 stats->rx_crc_errors = mac_stats->rx_fcs_error; 2273 stats->rx_frame_errors = mac_stats->rx_alignment_error; 2274 /* recv'r fifo overrun */ 2275 bmap = bna_rx_rid_mask(&bnad->bna); 2276 for (i = 0; bmap; i++) { 2277 if (bmap & 1) { 2278 stats->rx_fifo_errors += 2279 bnad->stats.bna_stats-> 2280 hw_stats.rxf_stats[i].frame_drops; 2281 break; 2282 } 2283 bmap >>= 1; 2284 } 2285 } 2286 2287 static void 2288 bnad_mbox_irq_sync(struct bnad *bnad) 2289 { 2290 u32 irq; 2291 unsigned long flags; 2292 2293 spin_lock_irqsave(&bnad->bna_lock, flags); 2294 if (bnad->cfg_flags & BNAD_CF_MSIX) 2295 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector; 2296 else 2297 irq = bnad->pcidev->irq; 2298 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2299 2300 synchronize_irq(irq); 2301 } 2302 2303 /* Utility used by bnad_start_xmit, for doing TSO */ 2304 static int 2305 bnad_tso_prepare(struct bnad *bnad, struct sk_buff *skb) 2306 { 2307 int err; 2308 2309 if (skb_header_cloned(skb)) { 2310 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); 2311 if (err) { 2312 BNAD_UPDATE_CTR(bnad, tso_err); 2313 return err; 2314 } 2315 } 2316 2317 /* 2318 * For TSO, the TCP checksum field is seeded with pseudo-header sum 2319 * excluding the length field. 2320 */ 2321 if (skb->protocol == htons(ETH_P_IP)) { 2322 struct iphdr *iph = ip_hdr(skb); 2323 2324 /* Do we really need these? */ 2325 iph->tot_len = 0; 2326 iph->check = 0; 2327 2328 tcp_hdr(skb)->check = 2329 ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0, 2330 IPPROTO_TCP, 0); 2331 BNAD_UPDATE_CTR(bnad, tso4); 2332 } else { 2333 struct ipv6hdr *ipv6h = ipv6_hdr(skb); 2334 2335 ipv6h->payload_len = 0; 2336 tcp_hdr(skb)->check = 2337 ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, 0, 2338 IPPROTO_TCP, 0); 2339 BNAD_UPDATE_CTR(bnad, tso6); 2340 } 2341 2342 return 0; 2343 } 2344 2345 /* 2346 * Initialize Q numbers depending on Rx Paths 2347 * Called with bnad->bna_lock held, because of cfg_flags 2348 * access. 2349 */ 2350 static void 2351 bnad_q_num_init(struct bnad *bnad) 2352 { 2353 int rxps; 2354 2355 rxps = min((uint)num_online_cpus(), 2356 (uint)(BNAD_MAX_RX * BNAD_MAX_RXP_PER_RX)); 2357 2358 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) 2359 rxps = 1; /* INTx */ 2360 2361 bnad->num_rx = 1; 2362 bnad->num_tx = 1; 2363 bnad->num_rxp_per_rx = rxps; 2364 bnad->num_txq_per_tx = BNAD_TXQ_NUM; 2365 } 2366 2367 /* 2368 * Adjusts the Q numbers, given a number of msix vectors 2369 * Give preference to RSS as opposed to Tx priority Queues, 2370 * in such a case, just use 1 Tx Q 2371 * Called with bnad->bna_lock held b'cos of cfg_flags access 2372 */ 2373 static void 2374 bnad_q_num_adjust(struct bnad *bnad, int msix_vectors, int temp) 2375 { 2376 bnad->num_txq_per_tx = 1; 2377 if ((msix_vectors >= (bnad->num_tx * bnad->num_txq_per_tx) + 2378 bnad_rxqs_per_cq + BNAD_MAILBOX_MSIX_VECTORS) && 2379 (bnad->cfg_flags & BNAD_CF_MSIX)) { 2380 bnad->num_rxp_per_rx = msix_vectors - 2381 (bnad->num_tx * bnad->num_txq_per_tx) - 2382 BNAD_MAILBOX_MSIX_VECTORS; 2383 } else 2384 bnad->num_rxp_per_rx = 1; 2385 } 2386 2387 /* Enable / disable ioceth */ 2388 static int 2389 bnad_ioceth_disable(struct bnad *bnad) 2390 { 2391 unsigned long flags; 2392 int err = 0; 2393 2394 spin_lock_irqsave(&bnad->bna_lock, flags); 2395 init_completion(&bnad->bnad_completions.ioc_comp); 2396 bna_ioceth_disable(&bnad->bna.ioceth, BNA_HARD_CLEANUP); 2397 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2398 2399 wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp, 2400 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT)); 2401 2402 err = bnad->bnad_completions.ioc_comp_status; 2403 return err; 2404 } 2405 2406 static int 2407 bnad_ioceth_enable(struct bnad *bnad) 2408 { 2409 int err = 0; 2410 unsigned long flags; 2411 2412 spin_lock_irqsave(&bnad->bna_lock, flags); 2413 init_completion(&bnad->bnad_completions.ioc_comp); 2414 bnad->bnad_completions.ioc_comp_status = BNA_CB_WAITING; 2415 bna_ioceth_enable(&bnad->bna.ioceth); 2416 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2417 2418 wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp, 2419 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT)); 2420 2421 err = bnad->bnad_completions.ioc_comp_status; 2422 2423 return err; 2424 } 2425 2426 /* Free BNA resources */ 2427 static void 2428 bnad_res_free(struct bnad *bnad, struct bna_res_info *res_info, 2429 u32 res_val_max) 2430 { 2431 int i; 2432 2433 for (i = 0; i < res_val_max; i++) 2434 bnad_mem_free(bnad, &res_info[i].res_u.mem_info); 2435 } 2436 2437 /* Allocates memory and interrupt resources for BNA */ 2438 static int 2439 bnad_res_alloc(struct bnad *bnad, struct bna_res_info *res_info, 2440 u32 res_val_max) 2441 { 2442 int i, err; 2443 2444 for (i = 0; i < res_val_max; i++) { 2445 err = bnad_mem_alloc(bnad, &res_info[i].res_u.mem_info); 2446 if (err) 2447 goto err_return; 2448 } 2449 return 0; 2450 2451 err_return: 2452 bnad_res_free(bnad, res_info, res_val_max); 2453 return err; 2454 } 2455 2456 /* Interrupt enable / disable */ 2457 static void 2458 bnad_enable_msix(struct bnad *bnad) 2459 { 2460 int i, ret; 2461 unsigned long flags; 2462 2463 spin_lock_irqsave(&bnad->bna_lock, flags); 2464 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) { 2465 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2466 return; 2467 } 2468 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2469 2470 if (bnad->msix_table) 2471 return; 2472 2473 bnad->msix_table = 2474 kcalloc(bnad->msix_num, sizeof(struct msix_entry), GFP_KERNEL); 2475 2476 if (!bnad->msix_table) 2477 goto intx_mode; 2478 2479 for (i = 0; i < bnad->msix_num; i++) 2480 bnad->msix_table[i].entry = i; 2481 2482 ret = pci_enable_msix(bnad->pcidev, bnad->msix_table, bnad->msix_num); 2483 if (ret > 0) { 2484 /* Not enough MSI-X vectors. */ 2485 pr_warn("BNA: %d MSI-X vectors allocated < %d requested\n", 2486 ret, bnad->msix_num); 2487 2488 spin_lock_irqsave(&bnad->bna_lock, flags); 2489 /* ret = #of vectors that we got */ 2490 bnad_q_num_adjust(bnad, (ret - BNAD_MAILBOX_MSIX_VECTORS) / 2, 2491 (ret - BNAD_MAILBOX_MSIX_VECTORS) / 2); 2492 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2493 2494 bnad->msix_num = BNAD_NUM_TXQ + BNAD_NUM_RXP + 2495 BNAD_MAILBOX_MSIX_VECTORS; 2496 2497 if (bnad->msix_num > ret) 2498 goto intx_mode; 2499 2500 /* Try once more with adjusted numbers */ 2501 /* If this fails, fall back to INTx */ 2502 ret = pci_enable_msix(bnad->pcidev, bnad->msix_table, 2503 bnad->msix_num); 2504 if (ret) 2505 goto intx_mode; 2506 2507 } else if (ret < 0) 2508 goto intx_mode; 2509 2510 pci_intx(bnad->pcidev, 0); 2511 2512 return; 2513 2514 intx_mode: 2515 pr_warn("BNA: MSI-X enable failed - operating in INTx mode\n"); 2516 2517 kfree(bnad->msix_table); 2518 bnad->msix_table = NULL; 2519 bnad->msix_num = 0; 2520 spin_lock_irqsave(&bnad->bna_lock, flags); 2521 bnad->cfg_flags &= ~BNAD_CF_MSIX; 2522 bnad_q_num_init(bnad); 2523 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2524 } 2525 2526 static void 2527 bnad_disable_msix(struct bnad *bnad) 2528 { 2529 u32 cfg_flags; 2530 unsigned long flags; 2531 2532 spin_lock_irqsave(&bnad->bna_lock, flags); 2533 cfg_flags = bnad->cfg_flags; 2534 if (bnad->cfg_flags & BNAD_CF_MSIX) 2535 bnad->cfg_flags &= ~BNAD_CF_MSIX; 2536 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2537 2538 if (cfg_flags & BNAD_CF_MSIX) { 2539 pci_disable_msix(bnad->pcidev); 2540 kfree(bnad->msix_table); 2541 bnad->msix_table = NULL; 2542 } 2543 } 2544 2545 /* Netdev entry points */ 2546 static int 2547 bnad_open(struct net_device *netdev) 2548 { 2549 int err; 2550 struct bnad *bnad = netdev_priv(netdev); 2551 struct bna_pause_config pause_config; 2552 int mtu; 2553 unsigned long flags; 2554 2555 mutex_lock(&bnad->conf_mutex); 2556 2557 /* Tx */ 2558 err = bnad_setup_tx(bnad, 0); 2559 if (err) 2560 goto err_return; 2561 2562 /* Rx */ 2563 err = bnad_setup_rx(bnad, 0); 2564 if (err) 2565 goto cleanup_tx; 2566 2567 /* Port */ 2568 pause_config.tx_pause = 0; 2569 pause_config.rx_pause = 0; 2570 2571 mtu = ETH_HLEN + VLAN_HLEN + bnad->netdev->mtu + ETH_FCS_LEN; 2572 2573 spin_lock_irqsave(&bnad->bna_lock, flags); 2574 bna_enet_mtu_set(&bnad->bna.enet, mtu, NULL); 2575 bna_enet_pause_config(&bnad->bna.enet, &pause_config, NULL); 2576 bna_enet_enable(&bnad->bna.enet); 2577 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2578 2579 /* Enable broadcast */ 2580 bnad_enable_default_bcast(bnad); 2581 2582 /* Restore VLANs, if any */ 2583 bnad_restore_vlans(bnad, 0); 2584 2585 /* Set the UCAST address */ 2586 spin_lock_irqsave(&bnad->bna_lock, flags); 2587 bnad_mac_addr_set_locked(bnad, netdev->dev_addr); 2588 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2589 2590 /* Start the stats timer */ 2591 bnad_stats_timer_start(bnad); 2592 2593 mutex_unlock(&bnad->conf_mutex); 2594 2595 return 0; 2596 2597 cleanup_tx: 2598 bnad_destroy_tx(bnad, 0); 2599 2600 err_return: 2601 mutex_unlock(&bnad->conf_mutex); 2602 return err; 2603 } 2604 2605 static int 2606 bnad_stop(struct net_device *netdev) 2607 { 2608 struct bnad *bnad = netdev_priv(netdev); 2609 unsigned long flags; 2610 2611 mutex_lock(&bnad->conf_mutex); 2612 2613 /* Stop the stats timer */ 2614 bnad_stats_timer_stop(bnad); 2615 2616 init_completion(&bnad->bnad_completions.enet_comp); 2617 2618 spin_lock_irqsave(&bnad->bna_lock, flags); 2619 bna_enet_disable(&bnad->bna.enet, BNA_HARD_CLEANUP, 2620 bnad_cb_enet_disabled); 2621 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2622 2623 wait_for_completion(&bnad->bnad_completions.enet_comp); 2624 2625 bnad_destroy_tx(bnad, 0); 2626 bnad_destroy_rx(bnad, 0); 2627 2628 /* Synchronize mailbox IRQ */ 2629 bnad_mbox_irq_sync(bnad); 2630 2631 mutex_unlock(&bnad->conf_mutex); 2632 2633 return 0; 2634 } 2635 2636 /* TX */ 2637 /* Returns 0 for success */ 2638 static int 2639 bnad_txq_wi_prepare(struct bnad *bnad, struct bna_tcb *tcb, 2640 struct sk_buff *skb, struct bna_txq_entry *txqent) 2641 { 2642 u16 flags = 0; 2643 u32 gso_size; 2644 u16 vlan_tag = 0; 2645 2646 if (vlan_tx_tag_present(skb)) { 2647 vlan_tag = (u16)vlan_tx_tag_get(skb); 2648 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN); 2649 } 2650 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) { 2651 vlan_tag = ((tcb->priority & 0x7) << VLAN_PRIO_SHIFT) 2652 | (vlan_tag & 0x1fff); 2653 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN); 2654 } 2655 txqent->hdr.wi.vlan_tag = htons(vlan_tag); 2656 2657 if (skb_is_gso(skb)) { 2658 gso_size = skb_shinfo(skb)->gso_size; 2659 if (unlikely(gso_size > bnad->netdev->mtu)) { 2660 BNAD_UPDATE_CTR(bnad, tx_skb_mss_too_long); 2661 return -EINVAL; 2662 } 2663 if (unlikely((gso_size + skb_transport_offset(skb) + 2664 tcp_hdrlen(skb)) >= skb->len)) { 2665 txqent->hdr.wi.opcode = 2666 __constant_htons(BNA_TXQ_WI_SEND); 2667 txqent->hdr.wi.lso_mss = 0; 2668 BNAD_UPDATE_CTR(bnad, tx_skb_tso_too_short); 2669 } else { 2670 txqent->hdr.wi.opcode = 2671 __constant_htons(BNA_TXQ_WI_SEND_LSO); 2672 txqent->hdr.wi.lso_mss = htons(gso_size); 2673 } 2674 2675 if (bnad_tso_prepare(bnad, skb)) { 2676 BNAD_UPDATE_CTR(bnad, tx_skb_tso_prepare); 2677 return -EINVAL; 2678 } 2679 2680 flags |= (BNA_TXQ_WI_CF_IP_CKSUM | BNA_TXQ_WI_CF_TCP_CKSUM); 2681 txqent->hdr.wi.l4_hdr_size_n_offset = 2682 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET( 2683 tcp_hdrlen(skb) >> 2, skb_transport_offset(skb))); 2684 } else { 2685 txqent->hdr.wi.opcode = __constant_htons(BNA_TXQ_WI_SEND); 2686 txqent->hdr.wi.lso_mss = 0; 2687 2688 if (unlikely(skb->len > (bnad->netdev->mtu + ETH_HLEN))) { 2689 BNAD_UPDATE_CTR(bnad, tx_skb_non_tso_too_long); 2690 return -EINVAL; 2691 } 2692 2693 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2694 u8 proto = 0; 2695 2696 if (skb->protocol == __constant_htons(ETH_P_IP)) 2697 proto = ip_hdr(skb)->protocol; 2698 #ifdef NETIF_F_IPV6_CSUM 2699 else if (skb->protocol == 2700 __constant_htons(ETH_P_IPV6)) { 2701 /* nexthdr may not be TCP immediately. */ 2702 proto = ipv6_hdr(skb)->nexthdr; 2703 } 2704 #endif 2705 if (proto == IPPROTO_TCP) { 2706 flags |= BNA_TXQ_WI_CF_TCP_CKSUM; 2707 txqent->hdr.wi.l4_hdr_size_n_offset = 2708 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET 2709 (0, skb_transport_offset(skb))); 2710 2711 BNAD_UPDATE_CTR(bnad, tcpcsum_offload); 2712 2713 if (unlikely(skb_headlen(skb) < 2714 skb_transport_offset(skb) + 2715 tcp_hdrlen(skb))) { 2716 BNAD_UPDATE_CTR(bnad, tx_skb_tcp_hdr); 2717 return -EINVAL; 2718 } 2719 } else if (proto == IPPROTO_UDP) { 2720 flags |= BNA_TXQ_WI_CF_UDP_CKSUM; 2721 txqent->hdr.wi.l4_hdr_size_n_offset = 2722 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET 2723 (0, skb_transport_offset(skb))); 2724 2725 BNAD_UPDATE_CTR(bnad, udpcsum_offload); 2726 if (unlikely(skb_headlen(skb) < 2727 skb_transport_offset(skb) + 2728 sizeof(struct udphdr))) { 2729 BNAD_UPDATE_CTR(bnad, tx_skb_udp_hdr); 2730 return -EINVAL; 2731 } 2732 } else { 2733 2734 BNAD_UPDATE_CTR(bnad, tx_skb_csum_err); 2735 return -EINVAL; 2736 } 2737 } else 2738 txqent->hdr.wi.l4_hdr_size_n_offset = 0; 2739 } 2740 2741 txqent->hdr.wi.flags = htons(flags); 2742 txqent->hdr.wi.frame_length = htonl(skb->len); 2743 2744 return 0; 2745 } 2746 2747 /* 2748 * bnad_start_xmit : Netdev entry point for Transmit 2749 * Called under lock held by net_device 2750 */ 2751 static netdev_tx_t 2752 bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev) 2753 { 2754 struct bnad *bnad = netdev_priv(netdev); 2755 u32 txq_id = 0; 2756 struct bna_tcb *tcb = NULL; 2757 struct bnad_tx_unmap *unmap_q, *unmap, *head_unmap; 2758 u32 prod, q_depth, vect_id; 2759 u32 wis, vectors, len; 2760 int i; 2761 dma_addr_t dma_addr; 2762 struct bna_txq_entry *txqent; 2763 2764 len = skb_headlen(skb); 2765 2766 /* Sanity checks for the skb */ 2767 2768 if (unlikely(skb->len <= ETH_HLEN)) { 2769 dev_kfree_skb(skb); 2770 BNAD_UPDATE_CTR(bnad, tx_skb_too_short); 2771 return NETDEV_TX_OK; 2772 } 2773 if (unlikely(len > BFI_TX_MAX_DATA_PER_VECTOR)) { 2774 dev_kfree_skb(skb); 2775 BNAD_UPDATE_CTR(bnad, tx_skb_headlen_zero); 2776 return NETDEV_TX_OK; 2777 } 2778 if (unlikely(len == 0)) { 2779 dev_kfree_skb(skb); 2780 BNAD_UPDATE_CTR(bnad, tx_skb_headlen_zero); 2781 return NETDEV_TX_OK; 2782 } 2783 2784 tcb = bnad->tx_info[0].tcb[txq_id]; 2785 q_depth = tcb->q_depth; 2786 prod = tcb->producer_index; 2787 2788 unmap_q = tcb->unmap_q; 2789 2790 /* 2791 * Takes care of the Tx that is scheduled between clearing the flag 2792 * and the netif_tx_stop_all_queues() call. 2793 */ 2794 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) { 2795 dev_kfree_skb(skb); 2796 BNAD_UPDATE_CTR(bnad, tx_skb_stopping); 2797 return NETDEV_TX_OK; 2798 } 2799 2800 vectors = 1 + skb_shinfo(skb)->nr_frags; 2801 wis = BNA_TXQ_WI_NEEDED(vectors); /* 4 vectors per work item */ 2802 2803 if (unlikely(vectors > BFI_TX_MAX_VECTORS_PER_PKT)) { 2804 dev_kfree_skb(skb); 2805 BNAD_UPDATE_CTR(bnad, tx_skb_max_vectors); 2806 return NETDEV_TX_OK; 2807 } 2808 2809 /* Check for available TxQ resources */ 2810 if (unlikely(wis > BNA_QE_FREE_CNT(tcb, q_depth))) { 2811 if ((*tcb->hw_consumer_index != tcb->consumer_index) && 2812 !test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) { 2813 u32 sent; 2814 sent = bnad_txcmpl_process(bnad, tcb); 2815 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) 2816 bna_ib_ack(tcb->i_dbell, sent); 2817 smp_mb__before_clear_bit(); 2818 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags); 2819 } else { 2820 netif_stop_queue(netdev); 2821 BNAD_UPDATE_CTR(bnad, netif_queue_stop); 2822 } 2823 2824 smp_mb(); 2825 /* 2826 * Check again to deal with race condition between 2827 * netif_stop_queue here, and netif_wake_queue in 2828 * interrupt handler which is not inside netif tx lock. 2829 */ 2830 if (likely(wis > BNA_QE_FREE_CNT(tcb, q_depth))) { 2831 BNAD_UPDATE_CTR(bnad, netif_queue_stop); 2832 return NETDEV_TX_BUSY; 2833 } else { 2834 netif_wake_queue(netdev); 2835 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup); 2836 } 2837 } 2838 2839 txqent = &((struct bna_txq_entry *)tcb->sw_q)[prod]; 2840 head_unmap = &unmap_q[prod]; 2841 2842 /* Program the opcode, flags, frame_len, num_vectors in WI */ 2843 if (bnad_txq_wi_prepare(bnad, tcb, skb, txqent)) { 2844 dev_kfree_skb(skb); 2845 return NETDEV_TX_OK; 2846 } 2847 txqent->hdr.wi.reserved = 0; 2848 txqent->hdr.wi.num_vectors = vectors; 2849 2850 head_unmap->skb = skb; 2851 head_unmap->nvecs = 0; 2852 2853 /* Program the vectors */ 2854 unmap = head_unmap; 2855 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data, 2856 len, DMA_TO_DEVICE); 2857 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[0].host_addr); 2858 txqent->vector[0].length = htons(len); 2859 dma_unmap_addr_set(&unmap->vectors[0], dma_addr, dma_addr); 2860 head_unmap->nvecs++; 2861 2862 for (i = 0, vect_id = 0; i < vectors - 1; i++) { 2863 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 2864 u16 size = skb_frag_size(frag); 2865 2866 if (unlikely(size == 0)) { 2867 /* Undo the changes starting at tcb->producer_index */ 2868 bnad_tx_buff_unmap(bnad, unmap_q, q_depth, 2869 tcb->producer_index); 2870 dev_kfree_skb(skb); 2871 BNAD_UPDATE_CTR(bnad, tx_skb_frag_zero); 2872 return NETDEV_TX_OK; 2873 } 2874 2875 len += size; 2876 2877 vect_id++; 2878 if (vect_id == BFI_TX_MAX_VECTORS_PER_WI) { 2879 vect_id = 0; 2880 BNA_QE_INDX_INC(prod, q_depth); 2881 txqent = &((struct bna_txq_entry *)tcb->sw_q)[prod]; 2882 txqent->hdr.wi_ext.opcode = 2883 __constant_htons(BNA_TXQ_WI_EXTENSION); 2884 unmap = &unmap_q[prod]; 2885 } 2886 2887 dma_addr = skb_frag_dma_map(&bnad->pcidev->dev, frag, 2888 0, size, DMA_TO_DEVICE); 2889 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr); 2890 txqent->vector[vect_id].length = htons(size); 2891 dma_unmap_addr_set(&unmap->vectors[vect_id], dma_addr, 2892 dma_addr); 2893 head_unmap->nvecs++; 2894 } 2895 2896 if (unlikely(len != skb->len)) { 2897 /* Undo the changes starting at tcb->producer_index */ 2898 bnad_tx_buff_unmap(bnad, unmap_q, q_depth, tcb->producer_index); 2899 dev_kfree_skb(skb); 2900 BNAD_UPDATE_CTR(bnad, tx_skb_len_mismatch); 2901 return NETDEV_TX_OK; 2902 } 2903 2904 BNA_QE_INDX_INC(prod, q_depth); 2905 tcb->producer_index = prod; 2906 2907 smp_mb(); 2908 2909 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) 2910 return NETDEV_TX_OK; 2911 2912 bna_txq_prod_indx_doorbell(tcb); 2913 smp_mb(); 2914 2915 return NETDEV_TX_OK; 2916 } 2917 2918 /* 2919 * Used spin_lock to synchronize reading of stats structures, which 2920 * is written by BNA under the same lock. 2921 */ 2922 static struct rtnl_link_stats64 * 2923 bnad_get_stats64(struct net_device *netdev, struct rtnl_link_stats64 *stats) 2924 { 2925 struct bnad *bnad = netdev_priv(netdev); 2926 unsigned long flags; 2927 2928 spin_lock_irqsave(&bnad->bna_lock, flags); 2929 2930 bnad_netdev_qstats_fill(bnad, stats); 2931 bnad_netdev_hwstats_fill(bnad, stats); 2932 2933 spin_unlock_irqrestore(&bnad->bna_lock, flags); 2934 2935 return stats; 2936 } 2937 2938 void 2939 bnad_set_rx_mode(struct net_device *netdev) 2940 { 2941 struct bnad *bnad = netdev_priv(netdev); 2942 u32 new_mask, valid_mask; 2943 unsigned long flags; 2944 2945 spin_lock_irqsave(&bnad->bna_lock, flags); 2946 2947 new_mask = valid_mask = 0; 2948 2949 if (netdev->flags & IFF_PROMISC) { 2950 if (!(bnad->cfg_flags & BNAD_CF_PROMISC)) { 2951 new_mask = BNAD_RXMODE_PROMISC_DEFAULT; 2952 valid_mask = BNAD_RXMODE_PROMISC_DEFAULT; 2953 bnad->cfg_flags |= BNAD_CF_PROMISC; 2954 } 2955 } else { 2956 if (bnad->cfg_flags & BNAD_CF_PROMISC) { 2957 new_mask = ~BNAD_RXMODE_PROMISC_DEFAULT; 2958 valid_mask = BNAD_RXMODE_PROMISC_DEFAULT; 2959 bnad->cfg_flags &= ~BNAD_CF_PROMISC; 2960 } 2961 } 2962 2963 if (netdev->flags & IFF_ALLMULTI) { 2964 if (!(bnad->cfg_flags & BNAD_CF_ALLMULTI)) { 2965 new_mask |= BNA_RXMODE_ALLMULTI; 2966 valid_mask |= BNA_RXMODE_ALLMULTI; 2967 bnad->cfg_flags |= BNAD_CF_ALLMULTI; 2968 } 2969 } else { 2970 if (bnad->cfg_flags & BNAD_CF_ALLMULTI) { 2971 new_mask &= ~BNA_RXMODE_ALLMULTI; 2972 valid_mask |= BNA_RXMODE_ALLMULTI; 2973 bnad->cfg_flags &= ~BNAD_CF_ALLMULTI; 2974 } 2975 } 2976 2977 if (bnad->rx_info[0].rx == NULL) 2978 goto unlock; 2979 2980 bna_rx_mode_set(bnad->rx_info[0].rx, new_mask, valid_mask, NULL); 2981 2982 if (!netdev_mc_empty(netdev)) { 2983 u8 *mcaddr_list; 2984 int mc_count = netdev_mc_count(netdev); 2985 2986 /* Index 0 holds the broadcast address */ 2987 mcaddr_list = 2988 kzalloc((mc_count + 1) * ETH_ALEN, 2989 GFP_ATOMIC); 2990 if (!mcaddr_list) 2991 goto unlock; 2992 2993 memcpy(&mcaddr_list[0], &bnad_bcast_addr[0], ETH_ALEN); 2994 2995 /* Copy rest of the MC addresses */ 2996 bnad_netdev_mc_list_get(netdev, mcaddr_list); 2997 2998 bna_rx_mcast_listset(bnad->rx_info[0].rx, mc_count + 1, 2999 mcaddr_list, NULL); 3000 3001 /* Should we enable BNAD_CF_ALLMULTI for err != 0 ? */ 3002 kfree(mcaddr_list); 3003 } 3004 unlock: 3005 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3006 } 3007 3008 /* 3009 * bna_lock is used to sync writes to netdev->addr 3010 * conf_lock cannot be used since this call may be made 3011 * in a non-blocking context. 3012 */ 3013 static int 3014 bnad_set_mac_address(struct net_device *netdev, void *mac_addr) 3015 { 3016 int err; 3017 struct bnad *bnad = netdev_priv(netdev); 3018 struct sockaddr *sa = (struct sockaddr *)mac_addr; 3019 unsigned long flags; 3020 3021 spin_lock_irqsave(&bnad->bna_lock, flags); 3022 3023 err = bnad_mac_addr_set_locked(bnad, sa->sa_data); 3024 3025 if (!err) 3026 memcpy(netdev->dev_addr, sa->sa_data, netdev->addr_len); 3027 3028 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3029 3030 return err; 3031 } 3032 3033 static int 3034 bnad_mtu_set(struct bnad *bnad, int mtu) 3035 { 3036 unsigned long flags; 3037 3038 init_completion(&bnad->bnad_completions.mtu_comp); 3039 3040 spin_lock_irqsave(&bnad->bna_lock, flags); 3041 bna_enet_mtu_set(&bnad->bna.enet, mtu, bnad_cb_enet_mtu_set); 3042 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3043 3044 wait_for_completion(&bnad->bnad_completions.mtu_comp); 3045 3046 return bnad->bnad_completions.mtu_comp_status; 3047 } 3048 3049 static int 3050 bnad_change_mtu(struct net_device *netdev, int new_mtu) 3051 { 3052 int err, mtu = netdev->mtu; 3053 struct bnad *bnad = netdev_priv(netdev); 3054 3055 if (new_mtu + ETH_HLEN < ETH_ZLEN || new_mtu > BNAD_JUMBO_MTU) 3056 return -EINVAL; 3057 3058 mutex_lock(&bnad->conf_mutex); 3059 3060 netdev->mtu = new_mtu; 3061 3062 mtu = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN; 3063 err = bnad_mtu_set(bnad, mtu); 3064 if (err) 3065 err = -EBUSY; 3066 3067 mutex_unlock(&bnad->conf_mutex); 3068 return err; 3069 } 3070 3071 static int 3072 bnad_vlan_rx_add_vid(struct net_device *netdev, 3073 unsigned short vid) 3074 { 3075 struct bnad *bnad = netdev_priv(netdev); 3076 unsigned long flags; 3077 3078 if (!bnad->rx_info[0].rx) 3079 return 0; 3080 3081 mutex_lock(&bnad->conf_mutex); 3082 3083 spin_lock_irqsave(&bnad->bna_lock, flags); 3084 bna_rx_vlan_add(bnad->rx_info[0].rx, vid); 3085 set_bit(vid, bnad->active_vlans); 3086 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3087 3088 mutex_unlock(&bnad->conf_mutex); 3089 3090 return 0; 3091 } 3092 3093 static int 3094 bnad_vlan_rx_kill_vid(struct net_device *netdev, 3095 unsigned short vid) 3096 { 3097 struct bnad *bnad = netdev_priv(netdev); 3098 unsigned long flags; 3099 3100 if (!bnad->rx_info[0].rx) 3101 return 0; 3102 3103 mutex_lock(&bnad->conf_mutex); 3104 3105 spin_lock_irqsave(&bnad->bna_lock, flags); 3106 clear_bit(vid, bnad->active_vlans); 3107 bna_rx_vlan_del(bnad->rx_info[0].rx, vid); 3108 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3109 3110 mutex_unlock(&bnad->conf_mutex); 3111 3112 return 0; 3113 } 3114 3115 #ifdef CONFIG_NET_POLL_CONTROLLER 3116 static void 3117 bnad_netpoll(struct net_device *netdev) 3118 { 3119 struct bnad *bnad = netdev_priv(netdev); 3120 struct bnad_rx_info *rx_info; 3121 struct bnad_rx_ctrl *rx_ctrl; 3122 u32 curr_mask; 3123 int i, j; 3124 3125 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) { 3126 bna_intx_disable(&bnad->bna, curr_mask); 3127 bnad_isr(bnad->pcidev->irq, netdev); 3128 bna_intx_enable(&bnad->bna, curr_mask); 3129 } else { 3130 /* 3131 * Tx processing may happen in sending context, so no need 3132 * to explicitly process completions here 3133 */ 3134 3135 /* Rx processing */ 3136 for (i = 0; i < bnad->num_rx; i++) { 3137 rx_info = &bnad->rx_info[i]; 3138 if (!rx_info->rx) 3139 continue; 3140 for (j = 0; j < bnad->num_rxp_per_rx; j++) { 3141 rx_ctrl = &rx_info->rx_ctrl[j]; 3142 if (rx_ctrl->ccb) 3143 bnad_netif_rx_schedule_poll(bnad, 3144 rx_ctrl->ccb); 3145 } 3146 } 3147 } 3148 } 3149 #endif 3150 3151 static const struct net_device_ops bnad_netdev_ops = { 3152 .ndo_open = bnad_open, 3153 .ndo_stop = bnad_stop, 3154 .ndo_start_xmit = bnad_start_xmit, 3155 .ndo_get_stats64 = bnad_get_stats64, 3156 .ndo_set_rx_mode = bnad_set_rx_mode, 3157 .ndo_validate_addr = eth_validate_addr, 3158 .ndo_set_mac_address = bnad_set_mac_address, 3159 .ndo_change_mtu = bnad_change_mtu, 3160 .ndo_vlan_rx_add_vid = bnad_vlan_rx_add_vid, 3161 .ndo_vlan_rx_kill_vid = bnad_vlan_rx_kill_vid, 3162 #ifdef CONFIG_NET_POLL_CONTROLLER 3163 .ndo_poll_controller = bnad_netpoll 3164 #endif 3165 }; 3166 3167 static void 3168 bnad_netdev_init(struct bnad *bnad, bool using_dac) 3169 { 3170 struct net_device *netdev = bnad->netdev; 3171 3172 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM | 3173 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 3174 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_VLAN_TX; 3175 3176 netdev->vlan_features = NETIF_F_SG | NETIF_F_HIGHDMA | 3177 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 3178 NETIF_F_TSO | NETIF_F_TSO6; 3179 3180 netdev->features |= netdev->hw_features | 3181 NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER; 3182 3183 if (using_dac) 3184 netdev->features |= NETIF_F_HIGHDMA; 3185 3186 netdev->mem_start = bnad->mmio_start; 3187 netdev->mem_end = bnad->mmio_start + bnad->mmio_len - 1; 3188 3189 netdev->netdev_ops = &bnad_netdev_ops; 3190 bnad_set_ethtool_ops(netdev); 3191 } 3192 3193 /* 3194 * 1. Initialize the bnad structure 3195 * 2. Setup netdev pointer in pci_dev 3196 * 3. Initialize no. of TxQ & CQs & MSIX vectors 3197 * 4. Initialize work queue. 3198 */ 3199 static int 3200 bnad_init(struct bnad *bnad, 3201 struct pci_dev *pdev, struct net_device *netdev) 3202 { 3203 unsigned long flags; 3204 3205 SET_NETDEV_DEV(netdev, &pdev->dev); 3206 pci_set_drvdata(pdev, netdev); 3207 3208 bnad->netdev = netdev; 3209 bnad->pcidev = pdev; 3210 bnad->mmio_start = pci_resource_start(pdev, 0); 3211 bnad->mmio_len = pci_resource_len(pdev, 0); 3212 bnad->bar0 = ioremap_nocache(bnad->mmio_start, bnad->mmio_len); 3213 if (!bnad->bar0) { 3214 dev_err(&pdev->dev, "ioremap for bar0 failed\n"); 3215 pci_set_drvdata(pdev, NULL); 3216 return -ENOMEM; 3217 } 3218 pr_info("bar0 mapped to %p, len %llu\n", bnad->bar0, 3219 (unsigned long long) bnad->mmio_len); 3220 3221 spin_lock_irqsave(&bnad->bna_lock, flags); 3222 if (!bnad_msix_disable) 3223 bnad->cfg_flags = BNAD_CF_MSIX; 3224 3225 bnad->cfg_flags |= BNAD_CF_DIM_ENABLED; 3226 3227 bnad_q_num_init(bnad); 3228 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3229 3230 bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx) + 3231 (bnad->num_rx * bnad->num_rxp_per_rx) + 3232 BNAD_MAILBOX_MSIX_VECTORS; 3233 3234 bnad->txq_depth = BNAD_TXQ_DEPTH; 3235 bnad->rxq_depth = BNAD_RXQ_DEPTH; 3236 3237 bnad->tx_coalescing_timeo = BFI_TX_COALESCING_TIMEO; 3238 bnad->rx_coalescing_timeo = BFI_RX_COALESCING_TIMEO; 3239 3240 sprintf(bnad->wq_name, "%s_wq_%d", BNAD_NAME, bnad->id); 3241 bnad->work_q = create_singlethread_workqueue(bnad->wq_name); 3242 3243 if (!bnad->work_q) 3244 return -ENOMEM; 3245 3246 return 0; 3247 } 3248 3249 /* 3250 * Must be called after bnad_pci_uninit() 3251 * so that iounmap() and pci_set_drvdata(NULL) 3252 * happens only after PCI uninitialization. 3253 */ 3254 static void 3255 bnad_uninit(struct bnad *bnad) 3256 { 3257 if (bnad->work_q) { 3258 flush_workqueue(bnad->work_q); 3259 destroy_workqueue(bnad->work_q); 3260 bnad->work_q = NULL; 3261 } 3262 3263 if (bnad->bar0) 3264 iounmap(bnad->bar0); 3265 pci_set_drvdata(bnad->pcidev, NULL); 3266 } 3267 3268 /* 3269 * Initialize locks 3270 a) Per ioceth mutes used for serializing configuration 3271 changes from OS interface 3272 b) spin lock used to protect bna state machine 3273 */ 3274 static void 3275 bnad_lock_init(struct bnad *bnad) 3276 { 3277 spin_lock_init(&bnad->bna_lock); 3278 mutex_init(&bnad->conf_mutex); 3279 mutex_init(&bnad_list_mutex); 3280 } 3281 3282 static void 3283 bnad_lock_uninit(struct bnad *bnad) 3284 { 3285 mutex_destroy(&bnad->conf_mutex); 3286 mutex_destroy(&bnad_list_mutex); 3287 } 3288 3289 /* PCI Initialization */ 3290 static int 3291 bnad_pci_init(struct bnad *bnad, 3292 struct pci_dev *pdev, bool *using_dac) 3293 { 3294 int err; 3295 3296 err = pci_enable_device(pdev); 3297 if (err) 3298 return err; 3299 err = pci_request_regions(pdev, BNAD_NAME); 3300 if (err) 3301 goto disable_device; 3302 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) && 3303 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { 3304 *using_dac = true; 3305 } else { 3306 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 3307 if (err) { 3308 err = dma_set_coherent_mask(&pdev->dev, 3309 DMA_BIT_MASK(32)); 3310 if (err) 3311 goto release_regions; 3312 } 3313 *using_dac = false; 3314 } 3315 pci_set_master(pdev); 3316 return 0; 3317 3318 release_regions: 3319 pci_release_regions(pdev); 3320 disable_device: 3321 pci_disable_device(pdev); 3322 3323 return err; 3324 } 3325 3326 static void 3327 bnad_pci_uninit(struct pci_dev *pdev) 3328 { 3329 pci_release_regions(pdev); 3330 pci_disable_device(pdev); 3331 } 3332 3333 static int 3334 bnad_pci_probe(struct pci_dev *pdev, 3335 const struct pci_device_id *pcidev_id) 3336 { 3337 bool using_dac; 3338 int err; 3339 struct bnad *bnad; 3340 struct bna *bna; 3341 struct net_device *netdev; 3342 struct bfa_pcidev pcidev_info; 3343 unsigned long flags; 3344 3345 pr_info("bnad_pci_probe : (0x%p, 0x%p) PCI Func : (%d)\n", 3346 pdev, pcidev_id, PCI_FUNC(pdev->devfn)); 3347 3348 mutex_lock(&bnad_fwimg_mutex); 3349 if (!cna_get_firmware_buf(pdev)) { 3350 mutex_unlock(&bnad_fwimg_mutex); 3351 pr_warn("Failed to load Firmware Image!\n"); 3352 return -ENODEV; 3353 } 3354 mutex_unlock(&bnad_fwimg_mutex); 3355 3356 /* 3357 * Allocates sizeof(struct net_device + struct bnad) 3358 * bnad = netdev->priv 3359 */ 3360 netdev = alloc_etherdev(sizeof(struct bnad)); 3361 if (!netdev) { 3362 err = -ENOMEM; 3363 return err; 3364 } 3365 bnad = netdev_priv(netdev); 3366 bnad_lock_init(bnad); 3367 bnad_add_to_list(bnad); 3368 3369 mutex_lock(&bnad->conf_mutex); 3370 /* 3371 * PCI initialization 3372 * Output : using_dac = 1 for 64 bit DMA 3373 * = 0 for 32 bit DMA 3374 */ 3375 using_dac = false; 3376 err = bnad_pci_init(bnad, pdev, &using_dac); 3377 if (err) 3378 goto unlock_mutex; 3379 3380 /* 3381 * Initialize bnad structure 3382 * Setup relation between pci_dev & netdev 3383 */ 3384 err = bnad_init(bnad, pdev, netdev); 3385 if (err) 3386 goto pci_uninit; 3387 3388 /* Initialize netdev structure, set up ethtool ops */ 3389 bnad_netdev_init(bnad, using_dac); 3390 3391 /* Set link to down state */ 3392 netif_carrier_off(netdev); 3393 3394 /* Setup the debugfs node for this bfad */ 3395 if (bna_debugfs_enable) 3396 bnad_debugfs_init(bnad); 3397 3398 /* Get resource requirement form bna */ 3399 spin_lock_irqsave(&bnad->bna_lock, flags); 3400 bna_res_req(&bnad->res_info[0]); 3401 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3402 3403 /* Allocate resources from bna */ 3404 err = bnad_res_alloc(bnad, &bnad->res_info[0], BNA_RES_T_MAX); 3405 if (err) 3406 goto drv_uninit; 3407 3408 bna = &bnad->bna; 3409 3410 /* Setup pcidev_info for bna_init() */ 3411 pcidev_info.pci_slot = PCI_SLOT(bnad->pcidev->devfn); 3412 pcidev_info.pci_func = PCI_FUNC(bnad->pcidev->devfn); 3413 pcidev_info.device_id = bnad->pcidev->device; 3414 pcidev_info.pci_bar_kva = bnad->bar0; 3415 3416 spin_lock_irqsave(&bnad->bna_lock, flags); 3417 bna_init(bna, bnad, &pcidev_info, &bnad->res_info[0]); 3418 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3419 3420 bnad->stats.bna_stats = &bna->stats; 3421 3422 bnad_enable_msix(bnad); 3423 err = bnad_mbox_irq_alloc(bnad); 3424 if (err) 3425 goto res_free; 3426 3427 /* Set up timers */ 3428 setup_timer(&bnad->bna.ioceth.ioc.ioc_timer, bnad_ioc_timeout, 3429 ((unsigned long)bnad)); 3430 setup_timer(&bnad->bna.ioceth.ioc.hb_timer, bnad_ioc_hb_check, 3431 ((unsigned long)bnad)); 3432 setup_timer(&bnad->bna.ioceth.ioc.iocpf_timer, bnad_iocpf_timeout, 3433 ((unsigned long)bnad)); 3434 setup_timer(&bnad->bna.ioceth.ioc.sem_timer, bnad_iocpf_sem_timeout, 3435 ((unsigned long)bnad)); 3436 3437 /* Now start the timer before calling IOC */ 3438 mod_timer(&bnad->bna.ioceth.ioc.iocpf_timer, 3439 jiffies + msecs_to_jiffies(BNA_IOC_TIMER_FREQ)); 3440 3441 /* 3442 * Start the chip 3443 * If the call back comes with error, we bail out. 3444 * This is a catastrophic error. 3445 */ 3446 err = bnad_ioceth_enable(bnad); 3447 if (err) { 3448 pr_err("BNA: Initialization failed err=%d\n", 3449 err); 3450 goto probe_success; 3451 } 3452 3453 spin_lock_irqsave(&bnad->bna_lock, flags); 3454 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) || 3455 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1)) { 3456 bnad_q_num_adjust(bnad, bna_attr(bna)->num_txq - 1, 3457 bna_attr(bna)->num_rxp - 1); 3458 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) || 3459 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1)) 3460 err = -EIO; 3461 } 3462 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3463 if (err) 3464 goto disable_ioceth; 3465 3466 spin_lock_irqsave(&bnad->bna_lock, flags); 3467 bna_mod_res_req(&bnad->bna, &bnad->mod_res_info[0]); 3468 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3469 3470 err = bnad_res_alloc(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX); 3471 if (err) { 3472 err = -EIO; 3473 goto disable_ioceth; 3474 } 3475 3476 spin_lock_irqsave(&bnad->bna_lock, flags); 3477 bna_mod_init(&bnad->bna, &bnad->mod_res_info[0]); 3478 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3479 3480 /* Get the burnt-in mac */ 3481 spin_lock_irqsave(&bnad->bna_lock, flags); 3482 bna_enet_perm_mac_get(&bna->enet, &bnad->perm_addr); 3483 bnad_set_netdev_perm_addr(bnad); 3484 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3485 3486 mutex_unlock(&bnad->conf_mutex); 3487 3488 /* Finally, reguister with net_device layer */ 3489 err = register_netdev(netdev); 3490 if (err) { 3491 pr_err("BNA : Registering with netdev failed\n"); 3492 goto probe_uninit; 3493 } 3494 set_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags); 3495 3496 return 0; 3497 3498 probe_success: 3499 mutex_unlock(&bnad->conf_mutex); 3500 return 0; 3501 3502 probe_uninit: 3503 mutex_lock(&bnad->conf_mutex); 3504 bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX); 3505 disable_ioceth: 3506 bnad_ioceth_disable(bnad); 3507 del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer); 3508 del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer); 3509 del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer); 3510 spin_lock_irqsave(&bnad->bna_lock, flags); 3511 bna_uninit(bna); 3512 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3513 bnad_mbox_irq_free(bnad); 3514 bnad_disable_msix(bnad); 3515 res_free: 3516 bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX); 3517 drv_uninit: 3518 /* Remove the debugfs node for this bnad */ 3519 kfree(bnad->regdata); 3520 bnad_debugfs_uninit(bnad); 3521 bnad_uninit(bnad); 3522 pci_uninit: 3523 bnad_pci_uninit(pdev); 3524 unlock_mutex: 3525 mutex_unlock(&bnad->conf_mutex); 3526 bnad_remove_from_list(bnad); 3527 bnad_lock_uninit(bnad); 3528 free_netdev(netdev); 3529 return err; 3530 } 3531 3532 static void 3533 bnad_pci_remove(struct pci_dev *pdev) 3534 { 3535 struct net_device *netdev = pci_get_drvdata(pdev); 3536 struct bnad *bnad; 3537 struct bna *bna; 3538 unsigned long flags; 3539 3540 if (!netdev) 3541 return; 3542 3543 pr_info("%s bnad_pci_remove\n", netdev->name); 3544 bnad = netdev_priv(netdev); 3545 bna = &bnad->bna; 3546 3547 if (test_and_clear_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags)) 3548 unregister_netdev(netdev); 3549 3550 mutex_lock(&bnad->conf_mutex); 3551 bnad_ioceth_disable(bnad); 3552 del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer); 3553 del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer); 3554 del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer); 3555 spin_lock_irqsave(&bnad->bna_lock, flags); 3556 bna_uninit(bna); 3557 spin_unlock_irqrestore(&bnad->bna_lock, flags); 3558 3559 bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX); 3560 bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX); 3561 bnad_mbox_irq_free(bnad); 3562 bnad_disable_msix(bnad); 3563 bnad_pci_uninit(pdev); 3564 mutex_unlock(&bnad->conf_mutex); 3565 bnad_remove_from_list(bnad); 3566 bnad_lock_uninit(bnad); 3567 /* Remove the debugfs node for this bnad */ 3568 kfree(bnad->regdata); 3569 bnad_debugfs_uninit(bnad); 3570 bnad_uninit(bnad); 3571 free_netdev(netdev); 3572 } 3573 3574 static DEFINE_PCI_DEVICE_TABLE(bnad_pci_id_table) = { 3575 { 3576 PCI_DEVICE(PCI_VENDOR_ID_BROCADE, 3577 PCI_DEVICE_ID_BROCADE_CT), 3578 .class = PCI_CLASS_NETWORK_ETHERNET << 8, 3579 .class_mask = 0xffff00 3580 }, 3581 { 3582 PCI_DEVICE(PCI_VENDOR_ID_BROCADE, 3583 BFA_PCI_DEVICE_ID_CT2), 3584 .class = PCI_CLASS_NETWORK_ETHERNET << 8, 3585 .class_mask = 0xffff00 3586 }, 3587 {0, }, 3588 }; 3589 3590 MODULE_DEVICE_TABLE(pci, bnad_pci_id_table); 3591 3592 static struct pci_driver bnad_pci_driver = { 3593 .name = BNAD_NAME, 3594 .id_table = bnad_pci_id_table, 3595 .probe = bnad_pci_probe, 3596 .remove = bnad_pci_remove, 3597 }; 3598 3599 static int __init 3600 bnad_module_init(void) 3601 { 3602 int err; 3603 3604 pr_info("Brocade 10G Ethernet driver - version: %s\n", 3605 BNAD_VERSION); 3606 3607 bfa_nw_ioc_auto_recover(bnad_ioc_auto_recover); 3608 3609 err = pci_register_driver(&bnad_pci_driver); 3610 if (err < 0) { 3611 pr_err("bna : PCI registration failed in module init " 3612 "(%d)\n", err); 3613 return err; 3614 } 3615 3616 return 0; 3617 } 3618 3619 static void __exit 3620 bnad_module_exit(void) 3621 { 3622 pci_unregister_driver(&bnad_pci_driver); 3623 release_firmware(bfi_fw); 3624 } 3625 3626 module_init(bnad_module_init); 3627 module_exit(bnad_module_exit); 3628 3629 MODULE_AUTHOR("Brocade"); 3630 MODULE_LICENSE("GPL"); 3631 MODULE_DESCRIPTION("Brocade 10G PCIe Ethernet driver"); 3632 MODULE_VERSION(BNAD_VERSION); 3633 MODULE_FIRMWARE(CNA_FW_FILE_CT); 3634 MODULE_FIRMWARE(CNA_FW_FILE_CT2); 3635