1 /* 2 * Broadcom GENET MDIO routines 3 * 4 * Copyright (c) 2014 Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 12 #include <linux/types.h> 13 #include <linux/delay.h> 14 #include <linux/wait.h> 15 #include <linux/mii.h> 16 #include <linux/ethtool.h> 17 #include <linux/bitops.h> 18 #include <linux/netdevice.h> 19 #include <linux/platform_device.h> 20 #include <linux/phy.h> 21 #include <linux/phy_fixed.h> 22 #include <linux/brcmphy.h> 23 #include <linux/of.h> 24 #include <linux/of_net.h> 25 #include <linux/of_mdio.h> 26 #include <linux/platform_data/bcmgenet.h> 27 28 #include "bcmgenet.h" 29 30 /* read a value from the MII */ 31 static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location) 32 { 33 int ret; 34 struct net_device *dev = bus->priv; 35 struct bcmgenet_priv *priv = netdev_priv(dev); 36 u32 reg; 37 38 bcmgenet_umac_writel(priv, (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) | 39 (location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD); 40 /* Start MDIO transaction*/ 41 reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD); 42 reg |= MDIO_START_BUSY; 43 bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD); 44 wait_event_timeout(priv->wq, 45 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) 46 & MDIO_START_BUSY), 47 HZ / 100); 48 ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD); 49 50 /* Some broken devices are known not to release the line during 51 * turn-around, e.g: Broadcom BCM53125 external switches, so check for 52 * that condition here and ignore the MDIO controller read failure 53 * indication. 54 */ 55 if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (ret & MDIO_READ_FAIL)) 56 return -EIO; 57 58 return ret & 0xffff; 59 } 60 61 /* write a value to the MII */ 62 static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id, 63 int location, u16 val) 64 { 65 struct net_device *dev = bus->priv; 66 struct bcmgenet_priv *priv = netdev_priv(dev); 67 u32 reg; 68 69 bcmgenet_umac_writel(priv, (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) | 70 (location << MDIO_REG_SHIFT) | (0xffff & val)), 71 UMAC_MDIO_CMD); 72 reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD); 73 reg |= MDIO_START_BUSY; 74 bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD); 75 wait_event_timeout(priv->wq, 76 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) & 77 MDIO_START_BUSY), 78 HZ / 100); 79 80 return 0; 81 } 82 83 /* setup netdev link state when PHY link status change and 84 * update UMAC and RGMII block when link up 85 */ 86 void bcmgenet_mii_setup(struct net_device *dev) 87 { 88 struct bcmgenet_priv *priv = netdev_priv(dev); 89 struct phy_device *phydev = priv->phydev; 90 u32 reg, cmd_bits = 0; 91 bool status_changed = false; 92 93 if (priv->old_link != phydev->link) { 94 status_changed = true; 95 priv->old_link = phydev->link; 96 } 97 98 if (phydev->link) { 99 /* check speed/duplex/pause changes */ 100 if (priv->old_speed != phydev->speed) { 101 status_changed = true; 102 priv->old_speed = phydev->speed; 103 } 104 105 if (priv->old_duplex != phydev->duplex) { 106 status_changed = true; 107 priv->old_duplex = phydev->duplex; 108 } 109 110 if (priv->old_pause != phydev->pause) { 111 status_changed = true; 112 priv->old_pause = phydev->pause; 113 } 114 115 /* done if nothing has changed */ 116 if (!status_changed) 117 return; 118 119 /* speed */ 120 if (phydev->speed == SPEED_1000) 121 cmd_bits = UMAC_SPEED_1000; 122 else if (phydev->speed == SPEED_100) 123 cmd_bits = UMAC_SPEED_100; 124 else 125 cmd_bits = UMAC_SPEED_10; 126 cmd_bits <<= CMD_SPEED_SHIFT; 127 128 /* duplex */ 129 if (phydev->duplex != DUPLEX_FULL) 130 cmd_bits |= CMD_HD_EN; 131 132 /* pause capability */ 133 if (!phydev->pause) 134 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; 135 136 /* 137 * Program UMAC and RGMII block based on established 138 * link speed, duplex, and pause. The speed set in 139 * umac->cmd tell RGMII block which clock to use for 140 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps). 141 * Receive clock is provided by the PHY. 142 */ 143 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 144 reg &= ~OOB_DISABLE; 145 reg |= RGMII_LINK; 146 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 147 148 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 149 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | 150 CMD_HD_EN | 151 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE); 152 reg |= cmd_bits; 153 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 154 } else { 155 /* done if nothing has changed */ 156 if (!status_changed) 157 return; 158 159 /* needed for MoCA fixed PHY to reflect correct link status */ 160 netif_carrier_off(dev); 161 } 162 163 phy_print_status(phydev); 164 } 165 166 167 static int bcmgenet_fixed_phy_link_update(struct net_device *dev, 168 struct fixed_phy_status *status) 169 { 170 if (dev && dev->phydev && status) 171 status->link = dev->phydev->link; 172 173 return 0; 174 } 175 176 /* Perform a voluntary PHY software reset, since the EPHY is very finicky about 177 * not doing it and will start corrupting packets 178 */ 179 void bcmgenet_mii_reset(struct net_device *dev) 180 { 181 struct bcmgenet_priv *priv = netdev_priv(dev); 182 183 if (GENET_IS_V4(priv)) 184 return; 185 186 if (priv->phydev) { 187 phy_init_hw(priv->phydev); 188 phy_start_aneg(priv->phydev); 189 } 190 } 191 192 void bcmgenet_phy_power_set(struct net_device *dev, bool enable) 193 { 194 struct bcmgenet_priv *priv = netdev_priv(dev); 195 u32 reg = 0; 196 197 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */ 198 if (!GENET_IS_V4(priv)) 199 return; 200 201 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL); 202 if (enable) { 203 reg &= ~EXT_CK25_DIS; 204 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 205 mdelay(1); 206 207 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN); 208 reg |= EXT_GPHY_RESET; 209 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 210 mdelay(1); 211 212 reg &= ~EXT_GPHY_RESET; 213 } else { 214 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | EXT_GPHY_RESET; 215 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 216 mdelay(1); 217 reg |= EXT_CK25_DIS; 218 } 219 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 220 udelay(60); 221 } 222 223 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv) 224 { 225 u32 reg; 226 227 /* Speed settings are set in bcmgenet_mii_setup() */ 228 reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL); 229 reg |= LED_ACT_SOURCE_MAC; 230 bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL); 231 232 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 233 fixed_phy_set_link_update(priv->phydev, 234 bcmgenet_fixed_phy_link_update); 235 } 236 237 int bcmgenet_mii_config(struct net_device *dev) 238 { 239 struct bcmgenet_priv *priv = netdev_priv(dev); 240 struct phy_device *phydev = priv->phydev; 241 struct device *kdev = &priv->pdev->dev; 242 const char *phy_name = NULL; 243 u32 id_mode_dis = 0; 244 u32 port_ctrl; 245 u32 reg; 246 247 priv->ext_phy = !priv->internal_phy && 248 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA); 249 250 if (priv->internal_phy) 251 priv->phy_interface = PHY_INTERFACE_MODE_NA; 252 253 switch (priv->phy_interface) { 254 case PHY_INTERFACE_MODE_NA: 255 case PHY_INTERFACE_MODE_MOCA: 256 /* Irrespective of the actually configured PHY speed (100 or 257 * 1000) GENETv4 only has an internal GPHY so we will just end 258 * up masking the Gigabit features from what we support, not 259 * switching to the EPHY 260 */ 261 if (GENET_IS_V4(priv)) 262 port_ctrl = PORT_MODE_INT_GPHY; 263 else 264 port_ctrl = PORT_MODE_INT_EPHY; 265 266 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 267 268 if (priv->internal_phy) { 269 phy_name = "internal PHY"; 270 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 271 phy_name = "MoCA"; 272 bcmgenet_moca_phy_setup(priv); 273 } 274 break; 275 276 case PHY_INTERFACE_MODE_MII: 277 phy_name = "external MII"; 278 phydev->supported &= PHY_BASIC_FEATURES; 279 bcmgenet_sys_writel(priv, 280 PORT_MODE_EXT_EPHY, SYS_PORT_CTRL); 281 break; 282 283 case PHY_INTERFACE_MODE_REVMII: 284 phy_name = "external RvMII"; 285 /* of_mdiobus_register took care of reading the 'max-speed' 286 * PHY property for us, effectively limiting the PHY supported 287 * capabilities, use that knowledge to also configure the 288 * Reverse MII interface correctly. 289 */ 290 if ((priv->phydev->supported & PHY_BASIC_FEATURES) == 291 PHY_BASIC_FEATURES) 292 port_ctrl = PORT_MODE_EXT_RVMII_25; 293 else 294 port_ctrl = PORT_MODE_EXT_RVMII_50; 295 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 296 break; 297 298 case PHY_INTERFACE_MODE_RGMII: 299 /* RGMII_NO_ID: TXC transitions at the same time as TXD 300 * (requires PCB or receiver-side delay) 301 * RGMII: Add 2ns delay on TXC (90 degree shift) 302 * 303 * ID is implicitly disabled for 100Mbps (RG)MII operation. 304 */ 305 id_mode_dis = BIT(16); 306 /* fall through */ 307 case PHY_INTERFACE_MODE_RGMII_TXID: 308 if (id_mode_dis) 309 phy_name = "external RGMII (no delay)"; 310 else 311 phy_name = "external RGMII (TX delay)"; 312 bcmgenet_sys_writel(priv, 313 PORT_MODE_EXT_GPHY, SYS_PORT_CTRL); 314 break; 315 default: 316 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface); 317 return -EINVAL; 318 } 319 320 /* This is an external PHY (xMII), so we need to enable the RGMII 321 * block for the interface to work 322 */ 323 if (priv->ext_phy) { 324 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 325 reg |= RGMII_MODE_EN | id_mode_dis; 326 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 327 } 328 329 dev_info_once(kdev, "configuring instance for %s\n", phy_name); 330 331 return 0; 332 } 333 334 int bcmgenet_mii_probe(struct net_device *dev) 335 { 336 struct bcmgenet_priv *priv = netdev_priv(dev); 337 struct device_node *dn = priv->pdev->dev.of_node; 338 struct phy_device *phydev; 339 u32 phy_flags; 340 int ret; 341 342 /* Communicate the integrated PHY revision */ 343 phy_flags = priv->gphy_rev; 344 345 /* Initialize link state variables that bcmgenet_mii_setup() uses */ 346 priv->old_link = -1; 347 priv->old_speed = -1; 348 priv->old_duplex = -1; 349 priv->old_pause = -1; 350 351 if (dn) { 352 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup, 353 phy_flags, priv->phy_interface); 354 if (!phydev) { 355 pr_err("could not attach to PHY\n"); 356 return -ENODEV; 357 } 358 } else { 359 phydev = priv->phydev; 360 phydev->dev_flags = phy_flags; 361 362 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup, 363 priv->phy_interface); 364 if (ret) { 365 pr_err("could not attach to PHY\n"); 366 return -ENODEV; 367 } 368 } 369 370 priv->phydev = phydev; 371 372 /* Configure port multiplexer based on what the probed PHY device since 373 * reading the 'max-speed' property determines the maximum supported 374 * PHY speed which is needed for bcmgenet_mii_config() to configure 375 * things appropriately. 376 */ 377 ret = bcmgenet_mii_config(dev); 378 if (ret) { 379 phy_disconnect(priv->phydev); 380 return ret; 381 } 382 383 phydev->advertising = phydev->supported; 384 385 /* The internal PHY has its link interrupts routed to the 386 * Ethernet MAC ISRs 387 */ 388 if (priv->internal_phy) 389 priv->phydev->irq = PHY_IGNORE_INTERRUPT; 390 391 return 0; 392 } 393 394 /* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with 395 * their internal MDIO management controller making them fail to successfully 396 * be read from or written to for the first transaction. We insert a dummy 397 * BMSR read here to make sure that phy_get_device() and get_phy_id() can 398 * correctly read the PHY MII_PHYSID1/2 registers and successfully register a 399 * PHY device for this peripheral. 400 * 401 * Once the PHY driver is registered, we can workaround subsequent reads from 402 * there (e.g: during system-wide power management). 403 * 404 * bus->reset is invoked before mdiobus_scan during mdiobus_register and is 405 * therefore the right location to stick that workaround. Since we do not want 406 * to read from non-existing PHYs, we either use bus->phy_mask or do a manual 407 * Device Tree scan to limit the search area. 408 */ 409 static int bcmgenet_mii_bus_reset(struct mii_bus *bus) 410 { 411 struct net_device *dev = bus->priv; 412 struct bcmgenet_priv *priv = netdev_priv(dev); 413 struct device_node *np = priv->mdio_dn; 414 struct device_node *child = NULL; 415 u32 read_mask = 0; 416 int addr = 0; 417 418 if (!np) { 419 read_mask = 1 << priv->phy_addr; 420 } else { 421 for_each_available_child_of_node(np, child) { 422 addr = of_mdio_parse_addr(&dev->dev, child); 423 if (addr < 0) 424 continue; 425 426 read_mask |= 1 << addr; 427 } 428 } 429 430 for (addr = 0; addr < PHY_MAX_ADDR; addr++) { 431 if (read_mask & 1 << addr) { 432 dev_dbg(&dev->dev, "Workaround for PHY @ %d\n", addr); 433 mdiobus_read(bus, addr, MII_BMSR); 434 } 435 } 436 437 return 0; 438 } 439 440 static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv) 441 { 442 struct mii_bus *bus; 443 444 if (priv->mii_bus) 445 return 0; 446 447 priv->mii_bus = mdiobus_alloc(); 448 if (!priv->mii_bus) { 449 pr_err("failed to allocate\n"); 450 return -ENOMEM; 451 } 452 453 bus = priv->mii_bus; 454 bus->priv = priv->dev; 455 bus->name = "bcmgenet MII bus"; 456 bus->parent = &priv->pdev->dev; 457 bus->read = bcmgenet_mii_read; 458 bus->write = bcmgenet_mii_write; 459 bus->reset = bcmgenet_mii_bus_reset; 460 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", 461 priv->pdev->name, priv->pdev->id); 462 463 return 0; 464 } 465 466 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv) 467 { 468 struct device_node *dn = priv->pdev->dev.of_node; 469 struct device *kdev = &priv->pdev->dev; 470 const char *phy_mode_str = NULL; 471 struct phy_device *phydev = NULL; 472 char *compat; 473 int phy_mode; 474 int ret; 475 476 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version); 477 if (!compat) 478 return -ENOMEM; 479 480 priv->mdio_dn = of_find_compatible_node(dn, NULL, compat); 481 kfree(compat); 482 if (!priv->mdio_dn) { 483 dev_err(kdev, "unable to find MDIO bus node\n"); 484 return -ENODEV; 485 } 486 487 ret = of_mdiobus_register(priv->mii_bus, priv->mdio_dn); 488 if (ret) { 489 dev_err(kdev, "failed to register MDIO bus\n"); 490 return ret; 491 } 492 493 /* Fetch the PHY phandle */ 494 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0); 495 496 /* In the case of a fixed PHY, the DT node associated 497 * to the PHY is the Ethernet MAC DT node. 498 */ 499 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) { 500 ret = of_phy_register_fixed_link(dn); 501 if (ret) 502 return ret; 503 504 priv->phy_dn = of_node_get(dn); 505 } 506 507 /* Get the link mode */ 508 phy_mode = of_get_phy_mode(dn); 509 priv->phy_interface = phy_mode; 510 511 /* We need to specifically look up whether this PHY interface is internal 512 * or not *before* we even try to probe the PHY driver over MDIO as we 513 * may have shut down the internal PHY for power saving purposes. 514 */ 515 if (phy_mode < 0) { 516 ret = of_property_read_string(dn, "phy-mode", &phy_mode_str); 517 if (ret < 0) { 518 dev_err(kdev, "invalid PHY mode property\n"); 519 return ret; 520 } 521 522 priv->phy_interface = PHY_INTERFACE_MODE_NA; 523 if (!strcasecmp(phy_mode_str, "internal")) 524 priv->internal_phy = true; 525 } 526 527 /* Make sure we initialize MoCA PHYs with a link down */ 528 if (phy_mode == PHY_INTERFACE_MODE_MOCA) { 529 phydev = of_phy_find_device(dn); 530 if (phydev) { 531 phydev->link = 0; 532 put_device(&phydev->mdio.dev); 533 } 534 } 535 536 return 0; 537 } 538 539 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv) 540 { 541 struct device *kdev = &priv->pdev->dev; 542 struct bcmgenet_platform_data *pd = kdev->platform_data; 543 struct mii_bus *mdio = priv->mii_bus; 544 struct phy_device *phydev; 545 int ret; 546 547 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 548 /* 549 * Internal or external PHY with MDIO access 550 */ 551 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) 552 mdio->phy_mask = ~(1 << pd->phy_address); 553 else 554 mdio->phy_mask = 0; 555 556 ret = mdiobus_register(mdio); 557 if (ret) { 558 dev_err(kdev, "failed to register MDIO bus\n"); 559 return ret; 560 } 561 562 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) 563 phydev = mdiobus_get_phy(mdio, pd->phy_address); 564 else 565 phydev = phy_find_first(mdio); 566 567 if (!phydev) { 568 dev_err(kdev, "failed to register PHY device\n"); 569 mdiobus_unregister(mdio); 570 return -ENODEV; 571 } 572 } else { 573 /* 574 * MoCA port or no MDIO access. 575 * Use fixed PHY to represent the link layer. 576 */ 577 struct fixed_phy_status fphy_status = { 578 .link = 1, 579 .speed = pd->phy_speed, 580 .duplex = pd->phy_duplex, 581 .pause = 0, 582 .asym_pause = 0, 583 }; 584 585 phydev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL); 586 if (!phydev || IS_ERR(phydev)) { 587 dev_err(kdev, "failed to register fixed PHY device\n"); 588 return -ENODEV; 589 } 590 591 /* Make sure we initialize MoCA PHYs with a link down */ 592 phydev->link = 0; 593 594 } 595 596 priv->phydev = phydev; 597 priv->phy_interface = pd->phy_interface; 598 599 return 0; 600 } 601 602 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv) 603 { 604 struct device_node *dn = priv->pdev->dev.of_node; 605 606 if (dn) 607 return bcmgenet_mii_of_init(priv); 608 else 609 return bcmgenet_mii_pd_init(priv); 610 } 611 612 int bcmgenet_mii_init(struct net_device *dev) 613 { 614 struct bcmgenet_priv *priv = netdev_priv(dev); 615 struct device_node *dn = priv->pdev->dev.of_node; 616 int ret; 617 618 ret = bcmgenet_mii_alloc(priv); 619 if (ret) 620 return ret; 621 622 ret = bcmgenet_mii_bus_init(priv); 623 if (ret) 624 goto out; 625 626 return 0; 627 628 out: 629 if (of_phy_is_fixed_link(dn)) 630 of_phy_deregister_fixed_link(dn); 631 of_node_put(priv->phy_dn); 632 mdiobus_unregister(priv->mii_bus); 633 mdiobus_free(priv->mii_bus); 634 return ret; 635 } 636 637 void bcmgenet_mii_exit(struct net_device *dev) 638 { 639 struct bcmgenet_priv *priv = netdev_priv(dev); 640 struct device_node *dn = priv->pdev->dev.of_node; 641 642 if (of_phy_is_fixed_link(dn)) 643 of_phy_deregister_fixed_link(dn); 644 of_node_put(priv->phy_dn); 645 mdiobus_unregister(priv->mii_bus); 646 mdiobus_free(priv->mii_bus); 647 } 648