1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Broadcom GENET MDIO routines 4 * 5 * Copyright (c) 2014-2017 Broadcom 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/types.h> 10 #include <linux/delay.h> 11 #include <linux/wait.h> 12 #include <linux/mii.h> 13 #include <linux/ethtool.h> 14 #include <linux/bitops.h> 15 #include <linux/netdevice.h> 16 #include <linux/platform_device.h> 17 #include <linux/phy.h> 18 #include <linux/phy_fixed.h> 19 #include <linux/brcmphy.h> 20 #include <linux/of.h> 21 #include <linux/of_net.h> 22 #include <linux/of_mdio.h> 23 #include <linux/platform_data/bcmgenet.h> 24 #include <linux/platform_data/mdio-bcm-unimac.h> 25 26 #include "bcmgenet.h" 27 28 static void bcmgenet_mac_config(struct net_device *dev) 29 { 30 struct bcmgenet_priv *priv = netdev_priv(dev); 31 struct phy_device *phydev = dev->phydev; 32 u32 reg, cmd_bits = 0; 33 34 /* speed */ 35 if (phydev->speed == SPEED_1000) 36 cmd_bits = CMD_SPEED_1000; 37 else if (phydev->speed == SPEED_100) 38 cmd_bits = CMD_SPEED_100; 39 else 40 cmd_bits = CMD_SPEED_10; 41 cmd_bits <<= CMD_SPEED_SHIFT; 42 43 /* duplex */ 44 if (phydev->duplex != DUPLEX_FULL) { 45 cmd_bits |= CMD_HD_EN | 46 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; 47 } else { 48 /* pause capability defaults to Symmetric */ 49 if (priv->autoneg_pause) { 50 bool tx_pause = 0, rx_pause = 0; 51 52 if (phydev->autoneg) 53 phy_get_pause(phydev, &tx_pause, &rx_pause); 54 55 if (!tx_pause) 56 cmd_bits |= CMD_TX_PAUSE_IGNORE; 57 if (!rx_pause) 58 cmd_bits |= CMD_RX_PAUSE_IGNORE; 59 } 60 61 /* Manual override */ 62 if (!priv->rx_pause) 63 cmd_bits |= CMD_RX_PAUSE_IGNORE; 64 if (!priv->tx_pause) 65 cmd_bits |= CMD_TX_PAUSE_IGNORE; 66 } 67 68 /* Program UMAC and RGMII block based on established 69 * link speed, duplex, and pause. The speed set in 70 * umac->cmd tell RGMII block which clock to use for 71 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps). 72 * Receive clock is provided by the PHY. 73 */ 74 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 75 reg |= RGMII_LINK; 76 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 77 78 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 79 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | 80 CMD_HD_EN | 81 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE); 82 reg |= cmd_bits; 83 if (reg & CMD_SW_RESET) { 84 reg &= ~CMD_SW_RESET; 85 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 86 udelay(2); 87 reg |= CMD_TX_EN | CMD_RX_EN; 88 } 89 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 90 } 91 92 /* setup netdev link state when PHY link status change and 93 * update UMAC and RGMII block when link up 94 */ 95 void bcmgenet_mii_setup(struct net_device *dev) 96 { 97 struct bcmgenet_priv *priv = netdev_priv(dev); 98 struct phy_device *phydev = dev->phydev; 99 u32 reg; 100 101 if (phydev->link) { 102 bcmgenet_mac_config(dev); 103 } else { 104 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 105 reg &= ~RGMII_LINK; 106 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 107 } 108 109 phy_print_status(phydev); 110 } 111 112 113 static int bcmgenet_fixed_phy_link_update(struct net_device *dev, 114 struct fixed_phy_status *status) 115 { 116 struct bcmgenet_priv *priv; 117 u32 reg; 118 119 if (dev && dev->phydev && status) { 120 priv = netdev_priv(dev); 121 reg = bcmgenet_umac_readl(priv, UMAC_MODE); 122 status->link = !!(reg & MODE_LINK_STATUS); 123 } 124 125 return 0; 126 } 127 128 void bcmgenet_phy_pause_set(struct net_device *dev, bool rx, bool tx) 129 { 130 struct phy_device *phydev = dev->phydev; 131 132 linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->advertising, rx); 133 linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->advertising, 134 rx | tx); 135 phy_start_aneg(phydev); 136 137 mutex_lock(&phydev->lock); 138 if (phydev->link) 139 bcmgenet_mac_config(dev); 140 mutex_unlock(&phydev->lock); 141 } 142 143 void bcmgenet_phy_power_set(struct net_device *dev, bool enable) 144 { 145 struct bcmgenet_priv *priv = netdev_priv(dev); 146 u32 reg = 0; 147 148 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */ 149 if (GENET_IS_V4(priv) || priv->ephy_16nm) { 150 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL); 151 if (enable) { 152 reg &= ~EXT_CK25_DIS; 153 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 154 mdelay(1); 155 156 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | 157 EXT_CFG_IDDQ_GLOBAL_PWR); 158 reg |= EXT_GPHY_RESET; 159 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 160 mdelay(1); 161 162 reg &= ~EXT_GPHY_RESET; 163 } else { 164 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | 165 EXT_GPHY_RESET | EXT_CFG_IDDQ_GLOBAL_PWR; 166 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 167 mdelay(1); 168 reg |= EXT_CK25_DIS; 169 } 170 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 171 udelay(60); 172 } else { 173 mdelay(1); 174 } 175 } 176 177 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv) 178 { 179 u32 reg; 180 181 if (!GENET_IS_V5(priv)) { 182 /* Speed settings are set in bcmgenet_mii_setup() */ 183 reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL); 184 reg |= LED_ACT_SOURCE_MAC; 185 bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL); 186 } 187 188 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 189 fixed_phy_set_link_update(priv->dev->phydev, 190 bcmgenet_fixed_phy_link_update); 191 } 192 193 int bcmgenet_mii_config(struct net_device *dev, bool init) 194 { 195 struct bcmgenet_priv *priv = netdev_priv(dev); 196 struct phy_device *phydev = dev->phydev; 197 struct device *kdev = &priv->pdev->dev; 198 const char *phy_name = NULL; 199 u32 id_mode_dis = 0; 200 u32 port_ctrl; 201 u32 reg; 202 203 switch (priv->phy_interface) { 204 case PHY_INTERFACE_MODE_INTERNAL: 205 phy_name = "internal PHY"; 206 fallthrough; 207 case PHY_INTERFACE_MODE_MOCA: 208 /* Irrespective of the actually configured PHY speed (100 or 209 * 1000) GENETv4 only has an internal GPHY so we will just end 210 * up masking the Gigabit features from what we support, not 211 * switching to the EPHY 212 */ 213 if (GENET_IS_V4(priv)) 214 port_ctrl = PORT_MODE_INT_GPHY; 215 else 216 port_ctrl = PORT_MODE_INT_EPHY; 217 218 if (!phy_name) { 219 phy_name = "MoCA"; 220 bcmgenet_moca_phy_setup(priv); 221 } 222 break; 223 224 case PHY_INTERFACE_MODE_MII: 225 phy_name = "external MII"; 226 phy_set_max_speed(phydev, SPEED_100); 227 port_ctrl = PORT_MODE_EXT_EPHY; 228 break; 229 230 case PHY_INTERFACE_MODE_REVMII: 231 phy_name = "external RvMII"; 232 /* of_mdiobus_register took care of reading the 'max-speed' 233 * PHY property for us, effectively limiting the PHY supported 234 * capabilities, use that knowledge to also configure the 235 * Reverse MII interface correctly. 236 */ 237 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 238 dev->phydev->supported)) 239 port_ctrl = PORT_MODE_EXT_RVMII_50; 240 else 241 port_ctrl = PORT_MODE_EXT_RVMII_25; 242 break; 243 244 case PHY_INTERFACE_MODE_RGMII: 245 /* RGMII_NO_ID: TXC transitions at the same time as TXD 246 * (requires PCB or receiver-side delay) 247 * 248 * ID is implicitly disabled for 100Mbps (RG)MII operation. 249 */ 250 phy_name = "external RGMII (no delay)"; 251 id_mode_dis = BIT(16); 252 port_ctrl = PORT_MODE_EXT_GPHY; 253 break; 254 255 case PHY_INTERFACE_MODE_RGMII_TXID: 256 /* RGMII_TXID: Add 2ns delay on TXC (90 degree shift) */ 257 phy_name = "external RGMII (TX delay)"; 258 port_ctrl = PORT_MODE_EXT_GPHY; 259 break; 260 261 case PHY_INTERFACE_MODE_RGMII_RXID: 262 phy_name = "external RGMII (RX delay)"; 263 port_ctrl = PORT_MODE_EXT_GPHY; 264 break; 265 default: 266 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface); 267 return -EINVAL; 268 } 269 270 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 271 272 priv->ext_phy = !priv->internal_phy && 273 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA); 274 275 /* This is an external PHY (xMII), so we need to enable the RGMII 276 * block for the interface to work, unconditionally clear the 277 * Out-of-band disable since we do not need it. 278 */ 279 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 280 reg &= ~OOB_DISABLE; 281 if (priv->ext_phy) { 282 reg &= ~ID_MODE_DIS; 283 reg |= id_mode_dis; 284 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv)) 285 reg |= RGMII_MODE_EN_V123; 286 else 287 reg |= RGMII_MODE_EN; 288 } 289 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 290 291 if (init) 292 dev_info(kdev, "configuring instance for %s\n", phy_name); 293 294 return 0; 295 } 296 297 int bcmgenet_mii_probe(struct net_device *dev) 298 { 299 struct bcmgenet_priv *priv = netdev_priv(dev); 300 struct device *kdev = &priv->pdev->dev; 301 struct device_node *dn = kdev->of_node; 302 phy_interface_t phy_iface = priv->phy_interface; 303 struct phy_device *phydev; 304 u32 phy_flags = PHY_BRCM_AUTO_PWRDWN_ENABLE | 305 PHY_BRCM_DIS_TXCRXC_NOENRGY | 306 PHY_BRCM_IDDQ_SUSPEND; 307 int ret; 308 309 /* Communicate the integrated PHY revision */ 310 if (priv->internal_phy) 311 phy_flags = priv->gphy_rev; 312 313 /* This is an ugly quirk but we have not been correctly interpreting 314 * the phy_interface values and we have done that across different 315 * drivers, so at least we are consistent in our mistakes. 316 * 317 * When the Generic PHY driver is in use either the PHY has been 318 * strapped or programmed correctly by the boot loader so we should 319 * stick to our incorrect interpretation since we have validated it. 320 * 321 * Now when a dedicated PHY driver is in use, we need to reverse the 322 * meaning of the phy_interface_mode values to something that the PHY 323 * driver will interpret and act on such that we have two mistakes 324 * canceling themselves so to speak. We only do this for the two 325 * modes that GENET driver officially supports on Broadcom STB chips: 326 * PHY_INTERFACE_MODE_RGMII and PHY_INTERFACE_MODE_RGMII_TXID. Other 327 * modes are not *officially* supported with the boot loader and the 328 * scripted environment generating Device Tree blobs for those 329 * platforms. 330 * 331 * Note that internal PHY, MoCA and fixed-link configurations are not 332 * affected because they use different phy_interface_t values or the 333 * Generic PHY driver. 334 */ 335 switch (priv->phy_interface) { 336 case PHY_INTERFACE_MODE_RGMII: 337 phy_iface = PHY_INTERFACE_MODE_RGMII_ID; 338 break; 339 case PHY_INTERFACE_MODE_RGMII_TXID: 340 phy_iface = PHY_INTERFACE_MODE_RGMII_RXID; 341 break; 342 default: 343 break; 344 } 345 346 if (dn) { 347 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup, 348 phy_flags, phy_iface); 349 if (!phydev) { 350 pr_err("could not attach to PHY\n"); 351 return -ENODEV; 352 } 353 } else { 354 if (has_acpi_companion(kdev)) { 355 char mdio_bus_id[MII_BUS_ID_SIZE]; 356 struct mii_bus *unimacbus; 357 358 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d", 359 UNIMAC_MDIO_DRV_NAME, priv->pdev->id); 360 361 unimacbus = mdio_find_bus(mdio_bus_id); 362 if (!unimacbus) { 363 pr_err("Unable to find mii\n"); 364 return -ENODEV; 365 } 366 phydev = phy_find_first(unimacbus); 367 put_device(&unimacbus->dev); 368 if (!phydev) { 369 pr_err("Unable to find PHY\n"); 370 return -ENODEV; 371 } 372 } else { 373 phydev = dev->phydev; 374 } 375 phydev->dev_flags = phy_flags; 376 377 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup, 378 phy_iface); 379 if (ret) { 380 pr_err("could not attach to PHY\n"); 381 return -ENODEV; 382 } 383 } 384 385 /* Configure port multiplexer based on what the probed PHY device since 386 * reading the 'max-speed' property determines the maximum supported 387 * PHY speed which is needed for bcmgenet_mii_config() to configure 388 * things appropriately. 389 */ 390 ret = bcmgenet_mii_config(dev, true); 391 if (ret) { 392 phy_disconnect(dev->phydev); 393 return ret; 394 } 395 396 /* The internal PHY has its link interrupts routed to the 397 * Ethernet MAC ISRs. On GENETv5 there is a hardware issue 398 * that prevents the signaling of link UP interrupts when 399 * the link operates at 10Mbps, so fallback to polling for 400 * those versions of GENET. 401 */ 402 if (priv->internal_phy && !GENET_IS_V5(priv)) 403 dev->phydev->irq = PHY_MAC_INTERRUPT; 404 405 /* Indicate that the MAC is responsible for PHY PM */ 406 dev->phydev->mac_managed_pm = true; 407 408 return 0; 409 } 410 411 static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv) 412 { 413 struct device_node *dn = priv->pdev->dev.of_node; 414 struct device *kdev = &priv->pdev->dev; 415 char *compat; 416 417 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version); 418 if (!compat) 419 return NULL; 420 421 priv->mdio_dn = of_get_compatible_child(dn, compat); 422 kfree(compat); 423 if (!priv->mdio_dn) { 424 dev_err(kdev, "unable to find MDIO bus node\n"); 425 return NULL; 426 } 427 428 return priv->mdio_dn; 429 } 430 431 static void bcmgenet_mii_pdata_init(struct bcmgenet_priv *priv, 432 struct unimac_mdio_pdata *ppd) 433 { 434 struct device *kdev = &priv->pdev->dev; 435 struct bcmgenet_platform_data *pd = kdev->platform_data; 436 437 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 438 /* 439 * Internal or external PHY with MDIO access 440 */ 441 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) 442 ppd->phy_mask = 1 << pd->phy_address; 443 else 444 ppd->phy_mask = 0; 445 } 446 } 447 448 static int bcmgenet_mii_wait(void *wait_func_data) 449 { 450 struct bcmgenet_priv *priv = wait_func_data; 451 452 wait_event_timeout(priv->wq, 453 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) 454 & MDIO_START_BUSY), 455 HZ / 100); 456 return 0; 457 } 458 459 static int bcmgenet_mii_register(struct bcmgenet_priv *priv) 460 { 461 struct platform_device *pdev = priv->pdev; 462 struct bcmgenet_platform_data *pdata = pdev->dev.platform_data; 463 struct device_node *dn = pdev->dev.of_node; 464 struct unimac_mdio_pdata ppd; 465 struct platform_device *ppdev; 466 struct resource *pres, res; 467 int id, ret; 468 469 pres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 470 if (!pres) { 471 dev_err(&pdev->dev, "Invalid resource\n"); 472 return -EINVAL; 473 } 474 memset(&res, 0, sizeof(res)); 475 memset(&ppd, 0, sizeof(ppd)); 476 477 ppd.wait_func = bcmgenet_mii_wait; 478 ppd.wait_func_data = priv; 479 ppd.bus_name = "bcmgenet MII bus"; 480 481 /* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD 482 * and is 2 * 32-bits word long, 8 bytes total. 483 */ 484 res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD; 485 res.end = res.start + 8; 486 res.flags = IORESOURCE_MEM; 487 488 if (dn) 489 id = of_alias_get_id(dn, "eth"); 490 else 491 id = pdev->id; 492 493 ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id); 494 if (!ppdev) 495 return -ENOMEM; 496 497 /* Retain this platform_device pointer for later cleanup */ 498 priv->mii_pdev = ppdev; 499 ppdev->dev.parent = &pdev->dev; 500 if (dn) 501 ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv); 502 else if (pdata) 503 bcmgenet_mii_pdata_init(priv, &ppd); 504 else 505 ppd.phy_mask = ~0; 506 507 ret = platform_device_add_resources(ppdev, &res, 1); 508 if (ret) 509 goto out; 510 511 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd)); 512 if (ret) 513 goto out; 514 515 ret = platform_device_add(ppdev); 516 if (ret) 517 goto out; 518 519 return 0; 520 out: 521 platform_device_put(ppdev); 522 return ret; 523 } 524 525 static int bcmgenet_phy_interface_init(struct bcmgenet_priv *priv) 526 { 527 struct device *kdev = &priv->pdev->dev; 528 int phy_mode = device_get_phy_mode(kdev); 529 530 if (phy_mode < 0) { 531 dev_err(kdev, "invalid PHY mode property\n"); 532 return phy_mode; 533 } 534 535 priv->phy_interface = phy_mode; 536 537 /* We need to specifically look up whether this PHY interface is 538 * internal or not *before* we even try to probe the PHY driver 539 * over MDIO as we may have shut down the internal PHY for power 540 * saving purposes. 541 */ 542 if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL) 543 priv->internal_phy = true; 544 545 return 0; 546 } 547 548 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv) 549 { 550 struct device_node *dn = priv->pdev->dev.of_node; 551 struct phy_device *phydev; 552 int ret; 553 554 /* Fetch the PHY phandle */ 555 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0); 556 557 /* In the case of a fixed PHY, the DT node associated 558 * to the PHY is the Ethernet MAC DT node. 559 */ 560 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) { 561 ret = of_phy_register_fixed_link(dn); 562 if (ret) 563 return ret; 564 565 priv->phy_dn = of_node_get(dn); 566 } 567 568 /* Get the link mode */ 569 ret = bcmgenet_phy_interface_init(priv); 570 if (ret) 571 return ret; 572 573 /* Make sure we initialize MoCA PHYs with a link down */ 574 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 575 phydev = of_phy_find_device(dn); 576 if (phydev) { 577 phydev->link = 0; 578 put_device(&phydev->mdio.dev); 579 } 580 } 581 582 return 0; 583 } 584 585 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv) 586 { 587 struct device *kdev = &priv->pdev->dev; 588 struct bcmgenet_platform_data *pd = kdev->platform_data; 589 char phy_name[MII_BUS_ID_SIZE + 3]; 590 char mdio_bus_id[MII_BUS_ID_SIZE]; 591 struct phy_device *phydev; 592 593 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d", 594 UNIMAC_MDIO_DRV_NAME, priv->pdev->id); 595 596 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 597 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, 598 mdio_bus_id, pd->phy_address); 599 600 /* 601 * Internal or external PHY with MDIO access 602 */ 603 phydev = phy_attach(priv->dev, phy_name, pd->phy_interface); 604 if (IS_ERR(phydev)) { 605 dev_err(kdev, "failed to register PHY device\n"); 606 return PTR_ERR(phydev); 607 } 608 } else { 609 /* 610 * MoCA port or no MDIO access. 611 * Use fixed PHY to represent the link layer. 612 */ 613 struct fixed_phy_status fphy_status = { 614 .link = 1, 615 .speed = pd->phy_speed, 616 .duplex = pd->phy_duplex, 617 .pause = 0, 618 .asym_pause = 0, 619 }; 620 621 phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL); 622 if (!phydev || IS_ERR(phydev)) { 623 dev_err(kdev, "failed to register fixed PHY device\n"); 624 return -ENODEV; 625 } 626 627 /* Make sure we initialize MoCA PHYs with a link down */ 628 phydev->link = 0; 629 630 } 631 632 priv->phy_interface = pd->phy_interface; 633 634 return 0; 635 } 636 637 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv) 638 { 639 struct device *kdev = &priv->pdev->dev; 640 struct device_node *dn = kdev->of_node; 641 642 if (dn) 643 return bcmgenet_mii_of_init(priv); 644 else if (has_acpi_companion(kdev)) 645 return bcmgenet_phy_interface_init(priv); 646 else 647 return bcmgenet_mii_pd_init(priv); 648 } 649 650 int bcmgenet_mii_init(struct net_device *dev) 651 { 652 struct bcmgenet_priv *priv = netdev_priv(dev); 653 int ret; 654 655 ret = bcmgenet_mii_register(priv); 656 if (ret) 657 return ret; 658 659 ret = bcmgenet_mii_bus_init(priv); 660 if (ret) 661 goto out; 662 663 return 0; 664 665 out: 666 bcmgenet_mii_exit(dev); 667 return ret; 668 } 669 670 void bcmgenet_mii_exit(struct net_device *dev) 671 { 672 struct bcmgenet_priv *priv = netdev_priv(dev); 673 struct device_node *dn = priv->pdev->dev.of_node; 674 675 if (of_phy_is_fixed_link(dn)) 676 of_phy_deregister_fixed_link(dn); 677 of_node_put(priv->phy_dn); 678 platform_device_unregister(priv->mii_pdev); 679 } 680