1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Broadcom GENET MDIO routines 4 * 5 * Copyright (c) 2014-2017 Broadcom 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/types.h> 10 #include <linux/delay.h> 11 #include <linux/wait.h> 12 #include <linux/mii.h> 13 #include <linux/ethtool.h> 14 #include <linux/bitops.h> 15 #include <linux/netdevice.h> 16 #include <linux/platform_device.h> 17 #include <linux/phy.h> 18 #include <linux/phy_fixed.h> 19 #include <linux/brcmphy.h> 20 #include <linux/of.h> 21 #include <linux/of_net.h> 22 #include <linux/of_mdio.h> 23 #include <linux/platform_data/bcmgenet.h> 24 #include <linux/platform_data/mdio-bcm-unimac.h> 25 26 #include "bcmgenet.h" 27 28 static void bcmgenet_mac_config(struct net_device *dev) 29 { 30 struct bcmgenet_priv *priv = netdev_priv(dev); 31 struct phy_device *phydev = dev->phydev; 32 u32 reg, cmd_bits = 0; 33 34 /* speed */ 35 if (phydev->speed == SPEED_1000) 36 cmd_bits = CMD_SPEED_1000; 37 else if (phydev->speed == SPEED_100) 38 cmd_bits = CMD_SPEED_100; 39 else 40 cmd_bits = CMD_SPEED_10; 41 cmd_bits <<= CMD_SPEED_SHIFT; 42 43 /* duplex */ 44 if (phydev->duplex != DUPLEX_FULL) { 45 cmd_bits |= CMD_HD_EN | 46 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; 47 } else { 48 /* pause capability defaults to Symmetric */ 49 if (priv->autoneg_pause) { 50 bool tx_pause = 0, rx_pause = 0; 51 52 if (phydev->autoneg) 53 phy_get_pause(phydev, &tx_pause, &rx_pause); 54 55 if (!tx_pause) 56 cmd_bits |= CMD_TX_PAUSE_IGNORE; 57 if (!rx_pause) 58 cmd_bits |= CMD_RX_PAUSE_IGNORE; 59 } 60 61 /* Manual override */ 62 if (!priv->rx_pause) 63 cmd_bits |= CMD_RX_PAUSE_IGNORE; 64 if (!priv->tx_pause) 65 cmd_bits |= CMD_TX_PAUSE_IGNORE; 66 } 67 68 /* Program UMAC and RGMII block based on established 69 * link speed, duplex, and pause. The speed set in 70 * umac->cmd tell RGMII block which clock to use for 71 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps). 72 * Receive clock is provided by the PHY. 73 */ 74 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 75 reg &= ~OOB_DISABLE; 76 reg |= RGMII_LINK; 77 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 78 79 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 80 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | 81 CMD_HD_EN | 82 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE); 83 reg |= cmd_bits; 84 if (reg & CMD_SW_RESET) { 85 reg &= ~CMD_SW_RESET; 86 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 87 udelay(2); 88 reg |= CMD_TX_EN | CMD_RX_EN; 89 } 90 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 91 } 92 93 /* setup netdev link state when PHY link status change and 94 * update UMAC and RGMII block when link up 95 */ 96 void bcmgenet_mii_setup(struct net_device *dev) 97 { 98 struct phy_device *phydev = dev->phydev; 99 100 if (phydev->link) 101 bcmgenet_mac_config(dev); 102 phy_print_status(phydev); 103 } 104 105 106 static int bcmgenet_fixed_phy_link_update(struct net_device *dev, 107 struct fixed_phy_status *status) 108 { 109 struct bcmgenet_priv *priv; 110 u32 reg; 111 112 if (dev && dev->phydev && status) { 113 priv = netdev_priv(dev); 114 reg = bcmgenet_umac_readl(priv, UMAC_MODE); 115 status->link = !!(reg & MODE_LINK_STATUS); 116 } 117 118 return 0; 119 } 120 121 void bcmgenet_phy_pause_set(struct net_device *dev, bool rx, bool tx) 122 { 123 struct phy_device *phydev = dev->phydev; 124 125 linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->advertising, rx); 126 linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->advertising, 127 rx | tx); 128 phy_start_aneg(phydev); 129 130 mutex_lock(&phydev->lock); 131 if (phydev->link) 132 bcmgenet_mac_config(dev); 133 mutex_unlock(&phydev->lock); 134 } 135 136 void bcmgenet_phy_power_set(struct net_device *dev, bool enable) 137 { 138 struct bcmgenet_priv *priv = netdev_priv(dev); 139 u32 reg = 0; 140 141 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */ 142 if (GENET_IS_V4(priv)) { 143 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL); 144 if (enable) { 145 reg &= ~EXT_CK25_DIS; 146 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 147 mdelay(1); 148 149 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN); 150 reg |= EXT_GPHY_RESET; 151 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 152 mdelay(1); 153 154 reg &= ~EXT_GPHY_RESET; 155 } else { 156 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | 157 EXT_GPHY_RESET; 158 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 159 mdelay(1); 160 reg |= EXT_CK25_DIS; 161 } 162 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 163 udelay(60); 164 } else { 165 mdelay(1); 166 } 167 } 168 169 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv) 170 { 171 u32 reg; 172 173 if (!GENET_IS_V5(priv)) { 174 /* Speed settings are set in bcmgenet_mii_setup() */ 175 reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL); 176 reg |= LED_ACT_SOURCE_MAC; 177 bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL); 178 } 179 180 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 181 fixed_phy_set_link_update(priv->dev->phydev, 182 bcmgenet_fixed_phy_link_update); 183 } 184 185 int bcmgenet_mii_config(struct net_device *dev, bool init) 186 { 187 struct bcmgenet_priv *priv = netdev_priv(dev); 188 struct phy_device *phydev = dev->phydev; 189 struct device *kdev = &priv->pdev->dev; 190 const char *phy_name = NULL; 191 u32 id_mode_dis = 0; 192 u32 port_ctrl; 193 u32 reg; 194 195 switch (priv->phy_interface) { 196 case PHY_INTERFACE_MODE_INTERNAL: 197 phy_name = "internal PHY"; 198 fallthrough; 199 case PHY_INTERFACE_MODE_MOCA: 200 /* Irrespective of the actually configured PHY speed (100 or 201 * 1000) GENETv4 only has an internal GPHY so we will just end 202 * up masking the Gigabit features from what we support, not 203 * switching to the EPHY 204 */ 205 if (GENET_IS_V4(priv)) 206 port_ctrl = PORT_MODE_INT_GPHY; 207 else 208 port_ctrl = PORT_MODE_INT_EPHY; 209 210 if (!phy_name) { 211 phy_name = "MoCA"; 212 bcmgenet_moca_phy_setup(priv); 213 } 214 break; 215 216 case PHY_INTERFACE_MODE_MII: 217 phy_name = "external MII"; 218 phy_set_max_speed(phydev, SPEED_100); 219 port_ctrl = PORT_MODE_EXT_EPHY; 220 break; 221 222 case PHY_INTERFACE_MODE_REVMII: 223 phy_name = "external RvMII"; 224 /* of_mdiobus_register took care of reading the 'max-speed' 225 * PHY property for us, effectively limiting the PHY supported 226 * capabilities, use that knowledge to also configure the 227 * Reverse MII interface correctly. 228 */ 229 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 230 dev->phydev->supported)) 231 port_ctrl = PORT_MODE_EXT_RVMII_50; 232 else 233 port_ctrl = PORT_MODE_EXT_RVMII_25; 234 break; 235 236 case PHY_INTERFACE_MODE_RGMII: 237 /* RGMII_NO_ID: TXC transitions at the same time as TXD 238 * (requires PCB or receiver-side delay) 239 * 240 * ID is implicitly disabled for 100Mbps (RG)MII operation. 241 */ 242 phy_name = "external RGMII (no delay)"; 243 id_mode_dis = BIT(16); 244 port_ctrl = PORT_MODE_EXT_GPHY; 245 break; 246 247 case PHY_INTERFACE_MODE_RGMII_TXID: 248 /* RGMII_TXID: Add 2ns delay on TXC (90 degree shift) */ 249 phy_name = "external RGMII (TX delay)"; 250 port_ctrl = PORT_MODE_EXT_GPHY; 251 break; 252 253 case PHY_INTERFACE_MODE_RGMII_RXID: 254 phy_name = "external RGMII (RX delay)"; 255 port_ctrl = PORT_MODE_EXT_GPHY; 256 break; 257 default: 258 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface); 259 return -EINVAL; 260 } 261 262 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 263 264 priv->ext_phy = !priv->internal_phy && 265 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA); 266 267 /* This is an external PHY (xMII), so we need to enable the RGMII 268 * block for the interface to work 269 */ 270 if (priv->ext_phy) { 271 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 272 reg &= ~ID_MODE_DIS; 273 reg |= id_mode_dis; 274 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv)) 275 reg |= RGMII_MODE_EN_V123; 276 else 277 reg |= RGMII_MODE_EN; 278 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 279 } 280 281 if (init) 282 dev_info(kdev, "configuring instance for %s\n", phy_name); 283 284 return 0; 285 } 286 287 int bcmgenet_mii_probe(struct net_device *dev) 288 { 289 struct bcmgenet_priv *priv = netdev_priv(dev); 290 struct device *kdev = &priv->pdev->dev; 291 struct device_node *dn = kdev->of_node; 292 phy_interface_t phy_iface = priv->phy_interface; 293 struct phy_device *phydev; 294 u32 phy_flags = PHY_BRCM_AUTO_PWRDWN_ENABLE | 295 PHY_BRCM_DIS_TXCRXC_NOENRGY | 296 PHY_BRCM_IDDQ_SUSPEND; 297 int ret; 298 299 /* Communicate the integrated PHY revision */ 300 if (priv->internal_phy) 301 phy_flags = priv->gphy_rev; 302 303 /* This is an ugly quirk but we have not been correctly interpreting 304 * the phy_interface values and we have done that across different 305 * drivers, so at least we are consistent in our mistakes. 306 * 307 * When the Generic PHY driver is in use either the PHY has been 308 * strapped or programmed correctly by the boot loader so we should 309 * stick to our incorrect interpretation since we have validated it. 310 * 311 * Now when a dedicated PHY driver is in use, we need to reverse the 312 * meaning of the phy_interface_mode values to something that the PHY 313 * driver will interpret and act on such that we have two mistakes 314 * canceling themselves so to speak. We only do this for the two 315 * modes that GENET driver officially supports on Broadcom STB chips: 316 * PHY_INTERFACE_MODE_RGMII and PHY_INTERFACE_MODE_RGMII_TXID. Other 317 * modes are not *officially* supported with the boot loader and the 318 * scripted environment generating Device Tree blobs for those 319 * platforms. 320 * 321 * Note that internal PHY, MoCA and fixed-link configurations are not 322 * affected because they use different phy_interface_t values or the 323 * Generic PHY driver. 324 */ 325 switch (priv->phy_interface) { 326 case PHY_INTERFACE_MODE_RGMII: 327 phy_iface = PHY_INTERFACE_MODE_RGMII_ID; 328 break; 329 case PHY_INTERFACE_MODE_RGMII_TXID: 330 phy_iface = PHY_INTERFACE_MODE_RGMII_RXID; 331 break; 332 default: 333 break; 334 } 335 336 if (dn) { 337 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup, 338 phy_flags, phy_iface); 339 if (!phydev) { 340 pr_err("could not attach to PHY\n"); 341 return -ENODEV; 342 } 343 } else { 344 if (has_acpi_companion(kdev)) { 345 char mdio_bus_id[MII_BUS_ID_SIZE]; 346 struct mii_bus *unimacbus; 347 348 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d", 349 UNIMAC_MDIO_DRV_NAME, priv->pdev->id); 350 351 unimacbus = mdio_find_bus(mdio_bus_id); 352 if (!unimacbus) { 353 pr_err("Unable to find mii\n"); 354 return -ENODEV; 355 } 356 phydev = phy_find_first(unimacbus); 357 put_device(&unimacbus->dev); 358 if (!phydev) { 359 pr_err("Unable to find PHY\n"); 360 return -ENODEV; 361 } 362 } else { 363 phydev = dev->phydev; 364 } 365 phydev->dev_flags = phy_flags; 366 367 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup, 368 phy_iface); 369 if (ret) { 370 pr_err("could not attach to PHY\n"); 371 return -ENODEV; 372 } 373 } 374 375 /* Configure port multiplexer based on what the probed PHY device since 376 * reading the 'max-speed' property determines the maximum supported 377 * PHY speed which is needed for bcmgenet_mii_config() to configure 378 * things appropriately. 379 */ 380 ret = bcmgenet_mii_config(dev, true); 381 if (ret) { 382 phy_disconnect(dev->phydev); 383 return ret; 384 } 385 386 /* The internal PHY has its link interrupts routed to the 387 * Ethernet MAC ISRs. On GENETv5 there is a hardware issue 388 * that prevents the signaling of link UP interrupts when 389 * the link operates at 10Mbps, so fallback to polling for 390 * those versions of GENET. 391 */ 392 if (priv->internal_phy && !GENET_IS_V5(priv)) 393 dev->phydev->irq = PHY_MAC_INTERRUPT; 394 395 return 0; 396 } 397 398 static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv) 399 { 400 struct device_node *dn = priv->pdev->dev.of_node; 401 struct device *kdev = &priv->pdev->dev; 402 char *compat; 403 404 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version); 405 if (!compat) 406 return NULL; 407 408 priv->mdio_dn = of_get_compatible_child(dn, compat); 409 kfree(compat); 410 if (!priv->mdio_dn) { 411 dev_err(kdev, "unable to find MDIO bus node\n"); 412 return NULL; 413 } 414 415 return priv->mdio_dn; 416 } 417 418 static void bcmgenet_mii_pdata_init(struct bcmgenet_priv *priv, 419 struct unimac_mdio_pdata *ppd) 420 { 421 struct device *kdev = &priv->pdev->dev; 422 struct bcmgenet_platform_data *pd = kdev->platform_data; 423 424 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 425 /* 426 * Internal or external PHY with MDIO access 427 */ 428 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) 429 ppd->phy_mask = 1 << pd->phy_address; 430 else 431 ppd->phy_mask = 0; 432 } 433 } 434 435 static int bcmgenet_mii_wait(void *wait_func_data) 436 { 437 struct bcmgenet_priv *priv = wait_func_data; 438 439 wait_event_timeout(priv->wq, 440 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) 441 & MDIO_START_BUSY), 442 HZ / 100); 443 return 0; 444 } 445 446 static int bcmgenet_mii_register(struct bcmgenet_priv *priv) 447 { 448 struct platform_device *pdev = priv->pdev; 449 struct bcmgenet_platform_data *pdata = pdev->dev.platform_data; 450 struct device_node *dn = pdev->dev.of_node; 451 struct unimac_mdio_pdata ppd; 452 struct platform_device *ppdev; 453 struct resource *pres, res; 454 int id, ret; 455 456 pres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 457 if (!pres) { 458 dev_err(&pdev->dev, "Invalid resource\n"); 459 return -EINVAL; 460 } 461 memset(&res, 0, sizeof(res)); 462 memset(&ppd, 0, sizeof(ppd)); 463 464 ppd.wait_func = bcmgenet_mii_wait; 465 ppd.wait_func_data = priv; 466 ppd.bus_name = "bcmgenet MII bus"; 467 468 /* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD 469 * and is 2 * 32-bits word long, 8 bytes total. 470 */ 471 res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD; 472 res.end = res.start + 8; 473 res.flags = IORESOURCE_MEM; 474 475 if (dn) 476 id = of_alias_get_id(dn, "eth"); 477 else 478 id = pdev->id; 479 480 ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id); 481 if (!ppdev) 482 return -ENOMEM; 483 484 /* Retain this platform_device pointer for later cleanup */ 485 priv->mii_pdev = ppdev; 486 ppdev->dev.parent = &pdev->dev; 487 if (dn) 488 ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv); 489 else if (pdata) 490 bcmgenet_mii_pdata_init(priv, &ppd); 491 else 492 ppd.phy_mask = ~0; 493 494 ret = platform_device_add_resources(ppdev, &res, 1); 495 if (ret) 496 goto out; 497 498 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd)); 499 if (ret) 500 goto out; 501 502 ret = platform_device_add(ppdev); 503 if (ret) 504 goto out; 505 506 return 0; 507 out: 508 platform_device_put(ppdev); 509 return ret; 510 } 511 512 static int bcmgenet_phy_interface_init(struct bcmgenet_priv *priv) 513 { 514 struct device *kdev = &priv->pdev->dev; 515 int phy_mode = device_get_phy_mode(kdev); 516 517 if (phy_mode < 0) { 518 dev_err(kdev, "invalid PHY mode property\n"); 519 return phy_mode; 520 } 521 522 priv->phy_interface = phy_mode; 523 524 /* We need to specifically look up whether this PHY interface is 525 * internal or not *before* we even try to probe the PHY driver 526 * over MDIO as we may have shut down the internal PHY for power 527 * saving purposes. 528 */ 529 if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL) 530 priv->internal_phy = true; 531 532 return 0; 533 } 534 535 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv) 536 { 537 struct device_node *dn = priv->pdev->dev.of_node; 538 struct phy_device *phydev; 539 int ret; 540 541 /* Fetch the PHY phandle */ 542 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0); 543 544 /* In the case of a fixed PHY, the DT node associated 545 * to the PHY is the Ethernet MAC DT node. 546 */ 547 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) { 548 ret = of_phy_register_fixed_link(dn); 549 if (ret) 550 return ret; 551 552 priv->phy_dn = of_node_get(dn); 553 } 554 555 /* Get the link mode */ 556 ret = bcmgenet_phy_interface_init(priv); 557 if (ret) 558 return ret; 559 560 /* Make sure we initialize MoCA PHYs with a link down */ 561 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 562 phydev = of_phy_find_device(dn); 563 if (phydev) { 564 phydev->link = 0; 565 put_device(&phydev->mdio.dev); 566 } 567 } 568 569 return 0; 570 } 571 572 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv) 573 { 574 struct device *kdev = &priv->pdev->dev; 575 struct bcmgenet_platform_data *pd = kdev->platform_data; 576 char phy_name[MII_BUS_ID_SIZE + 3]; 577 char mdio_bus_id[MII_BUS_ID_SIZE]; 578 struct phy_device *phydev; 579 580 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d", 581 UNIMAC_MDIO_DRV_NAME, priv->pdev->id); 582 583 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 584 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, 585 mdio_bus_id, pd->phy_address); 586 587 /* 588 * Internal or external PHY with MDIO access 589 */ 590 phydev = phy_attach(priv->dev, phy_name, pd->phy_interface); 591 if (!phydev) { 592 dev_err(kdev, "failed to register PHY device\n"); 593 return -ENODEV; 594 } 595 } else { 596 /* 597 * MoCA port or no MDIO access. 598 * Use fixed PHY to represent the link layer. 599 */ 600 struct fixed_phy_status fphy_status = { 601 .link = 1, 602 .speed = pd->phy_speed, 603 .duplex = pd->phy_duplex, 604 .pause = 0, 605 .asym_pause = 0, 606 }; 607 608 phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL); 609 if (!phydev || IS_ERR(phydev)) { 610 dev_err(kdev, "failed to register fixed PHY device\n"); 611 return -ENODEV; 612 } 613 614 /* Make sure we initialize MoCA PHYs with a link down */ 615 phydev->link = 0; 616 617 } 618 619 priv->phy_interface = pd->phy_interface; 620 621 return 0; 622 } 623 624 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv) 625 { 626 struct device *kdev = &priv->pdev->dev; 627 struct device_node *dn = kdev->of_node; 628 629 if (dn) 630 return bcmgenet_mii_of_init(priv); 631 else if (has_acpi_companion(kdev)) 632 return bcmgenet_phy_interface_init(priv); 633 else 634 return bcmgenet_mii_pd_init(priv); 635 } 636 637 int bcmgenet_mii_init(struct net_device *dev) 638 { 639 struct bcmgenet_priv *priv = netdev_priv(dev); 640 int ret; 641 642 ret = bcmgenet_mii_register(priv); 643 if (ret) 644 return ret; 645 646 ret = bcmgenet_mii_bus_init(priv); 647 if (ret) 648 goto out; 649 650 return 0; 651 652 out: 653 bcmgenet_mii_exit(dev); 654 return ret; 655 } 656 657 void bcmgenet_mii_exit(struct net_device *dev) 658 { 659 struct bcmgenet_priv *priv = netdev_priv(dev); 660 struct device_node *dn = priv->pdev->dev.of_node; 661 662 if (of_phy_is_fixed_link(dn)) 663 of_phy_deregister_fixed_link(dn); 664 of_node_put(priv->phy_dn); 665 platform_device_unregister(priv->mii_pdev); 666 } 667