1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Broadcom GENET MDIO routines 4 * 5 * Copyright (c) 2014-2017 Broadcom 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/types.h> 10 #include <linux/delay.h> 11 #include <linux/wait.h> 12 #include <linux/mii.h> 13 #include <linux/ethtool.h> 14 #include <linux/bitops.h> 15 #include <linux/netdevice.h> 16 #include <linux/platform_device.h> 17 #include <linux/phy.h> 18 #include <linux/phy_fixed.h> 19 #include <linux/brcmphy.h> 20 #include <linux/of.h> 21 #include <linux/of_net.h> 22 #include <linux/of_mdio.h> 23 #include <linux/platform_data/bcmgenet.h> 24 #include <linux/platform_data/mdio-bcm-unimac.h> 25 26 #include "bcmgenet.h" 27 28 /* setup netdev link state when PHY link status change and 29 * update UMAC and RGMII block when link up 30 */ 31 void bcmgenet_mii_setup(struct net_device *dev) 32 { 33 struct bcmgenet_priv *priv = netdev_priv(dev); 34 struct phy_device *phydev = dev->phydev; 35 u32 reg, cmd_bits = 0; 36 bool status_changed = false; 37 38 if (priv->old_link != phydev->link) { 39 status_changed = true; 40 priv->old_link = phydev->link; 41 } 42 43 if (phydev->link) { 44 /* check speed/duplex/pause changes */ 45 if (priv->old_speed != phydev->speed) { 46 status_changed = true; 47 priv->old_speed = phydev->speed; 48 } 49 50 if (priv->old_duplex != phydev->duplex) { 51 status_changed = true; 52 priv->old_duplex = phydev->duplex; 53 } 54 55 if (priv->old_pause != phydev->pause) { 56 status_changed = true; 57 priv->old_pause = phydev->pause; 58 } 59 60 /* done if nothing has changed */ 61 if (!status_changed) 62 return; 63 64 /* speed */ 65 if (phydev->speed == SPEED_1000) 66 cmd_bits = UMAC_SPEED_1000; 67 else if (phydev->speed == SPEED_100) 68 cmd_bits = UMAC_SPEED_100; 69 else 70 cmd_bits = UMAC_SPEED_10; 71 cmd_bits <<= CMD_SPEED_SHIFT; 72 73 /* duplex */ 74 if (phydev->duplex != DUPLEX_FULL) 75 cmd_bits |= CMD_HD_EN; 76 77 /* pause capability */ 78 if (!phydev->pause) 79 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; 80 81 /* 82 * Program UMAC and RGMII block based on established 83 * link speed, duplex, and pause. The speed set in 84 * umac->cmd tell RGMII block which clock to use for 85 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps). 86 * Receive clock is provided by the PHY. 87 */ 88 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 89 reg &= ~OOB_DISABLE; 90 reg |= RGMII_LINK; 91 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 92 93 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 94 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | 95 CMD_HD_EN | 96 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE); 97 reg |= cmd_bits; 98 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 99 } else { 100 /* done if nothing has changed */ 101 if (!status_changed) 102 return; 103 104 /* needed for MoCA fixed PHY to reflect correct link status */ 105 netif_carrier_off(dev); 106 } 107 108 phy_print_status(phydev); 109 } 110 111 112 static int bcmgenet_fixed_phy_link_update(struct net_device *dev, 113 struct fixed_phy_status *status) 114 { 115 struct bcmgenet_priv *priv; 116 u32 reg; 117 118 if (dev && dev->phydev && status) { 119 priv = netdev_priv(dev); 120 reg = bcmgenet_umac_readl(priv, UMAC_MODE); 121 status->link = !!(reg & MODE_LINK_STATUS); 122 } 123 124 return 0; 125 } 126 127 void bcmgenet_phy_power_set(struct net_device *dev, bool enable) 128 { 129 struct bcmgenet_priv *priv = netdev_priv(dev); 130 u32 reg = 0; 131 132 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */ 133 if (GENET_IS_V4(priv)) { 134 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL); 135 if (enable) { 136 reg &= ~EXT_CK25_DIS; 137 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 138 mdelay(1); 139 140 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN); 141 reg |= EXT_GPHY_RESET; 142 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 143 mdelay(1); 144 145 reg &= ~EXT_GPHY_RESET; 146 } else { 147 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | 148 EXT_GPHY_RESET; 149 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 150 mdelay(1); 151 reg |= EXT_CK25_DIS; 152 } 153 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 154 udelay(60); 155 } else { 156 mdelay(1); 157 } 158 } 159 160 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv) 161 { 162 u32 reg; 163 164 if (!GENET_IS_V5(priv)) { 165 /* Speed settings are set in bcmgenet_mii_setup() */ 166 reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL); 167 reg |= LED_ACT_SOURCE_MAC; 168 bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL); 169 } 170 171 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 172 fixed_phy_set_link_update(priv->dev->phydev, 173 bcmgenet_fixed_phy_link_update); 174 } 175 176 int bcmgenet_mii_config(struct net_device *dev, bool init) 177 { 178 struct bcmgenet_priv *priv = netdev_priv(dev); 179 struct phy_device *phydev = dev->phydev; 180 struct device *kdev = &priv->pdev->dev; 181 const char *phy_name = NULL; 182 u32 id_mode_dis = 0; 183 u32 port_ctrl; 184 int bmcr = -1; 185 int ret; 186 u32 reg; 187 188 /* MAC clocking workaround during reset of umac state machines */ 189 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 190 if (reg & CMD_SW_RESET) { 191 /* An MII PHY must be isolated to prevent TXC contention */ 192 if (priv->phy_interface == PHY_INTERFACE_MODE_MII) { 193 ret = phy_read(phydev, MII_BMCR); 194 if (ret >= 0) { 195 bmcr = ret; 196 ret = phy_write(phydev, MII_BMCR, 197 bmcr | BMCR_ISOLATE); 198 } 199 if (ret) { 200 netdev_err(dev, "failed to isolate PHY\n"); 201 return ret; 202 } 203 } 204 /* Switch MAC clocking to RGMII generated clock */ 205 bcmgenet_sys_writel(priv, PORT_MODE_EXT_GPHY, SYS_PORT_CTRL); 206 /* Ensure 5 clks with Rx disabled 207 * followed by 5 clks with Reset asserted 208 */ 209 udelay(4); 210 reg &= ~(CMD_SW_RESET | CMD_LCL_LOOP_EN); 211 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 212 /* Ensure 5 more clocks before Rx is enabled */ 213 udelay(2); 214 } 215 216 switch (priv->phy_interface) { 217 case PHY_INTERFACE_MODE_INTERNAL: 218 phy_name = "internal PHY"; 219 /* fall through */ 220 case PHY_INTERFACE_MODE_MOCA: 221 /* Irrespective of the actually configured PHY speed (100 or 222 * 1000) GENETv4 only has an internal GPHY so we will just end 223 * up masking the Gigabit features from what we support, not 224 * switching to the EPHY 225 */ 226 if (GENET_IS_V4(priv)) 227 port_ctrl = PORT_MODE_INT_GPHY; 228 else 229 port_ctrl = PORT_MODE_INT_EPHY; 230 231 if (!phy_name) { 232 phy_name = "MoCA"; 233 bcmgenet_moca_phy_setup(priv); 234 } 235 break; 236 237 case PHY_INTERFACE_MODE_MII: 238 phy_name = "external MII"; 239 phy_set_max_speed(phydev, SPEED_100); 240 port_ctrl = PORT_MODE_EXT_EPHY; 241 break; 242 243 case PHY_INTERFACE_MODE_REVMII: 244 phy_name = "external RvMII"; 245 /* of_mdiobus_register took care of reading the 'max-speed' 246 * PHY property for us, effectively limiting the PHY supported 247 * capabilities, use that knowledge to also configure the 248 * Reverse MII interface correctly. 249 */ 250 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 251 dev->phydev->supported)) 252 port_ctrl = PORT_MODE_EXT_RVMII_50; 253 else 254 port_ctrl = PORT_MODE_EXT_RVMII_25; 255 break; 256 257 case PHY_INTERFACE_MODE_RGMII: 258 /* RGMII_NO_ID: TXC transitions at the same time as TXD 259 * (requires PCB or receiver-side delay) 260 * 261 * ID is implicitly disabled for 100Mbps (RG)MII operation. 262 */ 263 phy_name = "external RGMII (no delay)"; 264 id_mode_dis = BIT(16); 265 port_ctrl = PORT_MODE_EXT_GPHY; 266 break; 267 268 case PHY_INTERFACE_MODE_RGMII_TXID: 269 /* RGMII_TXID: Add 2ns delay on TXC (90 degree shift) */ 270 phy_name = "external RGMII (TX delay)"; 271 port_ctrl = PORT_MODE_EXT_GPHY; 272 break; 273 274 case PHY_INTERFACE_MODE_RGMII_RXID: 275 phy_name = "external RGMII (RX delay)"; 276 port_ctrl = PORT_MODE_EXT_GPHY; 277 break; 278 default: 279 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface); 280 return -EINVAL; 281 } 282 283 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 284 285 /* Restore the MII PHY after isolation */ 286 if (bmcr >= 0) 287 phy_write(phydev, MII_BMCR, bmcr); 288 289 priv->ext_phy = !priv->internal_phy && 290 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA); 291 292 /* This is an external PHY (xMII), so we need to enable the RGMII 293 * block for the interface to work 294 */ 295 if (priv->ext_phy) { 296 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 297 reg &= ~ID_MODE_DIS; 298 reg |= id_mode_dis; 299 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv)) 300 reg |= RGMII_MODE_EN_V123; 301 else 302 reg |= RGMII_MODE_EN; 303 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 304 } 305 306 if (init) 307 dev_info(kdev, "configuring instance for %s\n", phy_name); 308 309 return 0; 310 } 311 312 int bcmgenet_mii_probe(struct net_device *dev) 313 { 314 struct bcmgenet_priv *priv = netdev_priv(dev); 315 struct device *kdev = &priv->pdev->dev; 316 struct device_node *dn = kdev->of_node; 317 struct phy_device *phydev; 318 u32 phy_flags = 0; 319 int ret; 320 321 /* Communicate the integrated PHY revision */ 322 if (priv->internal_phy) 323 phy_flags = priv->gphy_rev; 324 325 /* Initialize link state variables that bcmgenet_mii_setup() uses */ 326 priv->old_link = -1; 327 priv->old_speed = -1; 328 priv->old_duplex = -1; 329 priv->old_pause = -1; 330 331 if (dn) { 332 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup, 333 phy_flags, priv->phy_interface); 334 if (!phydev) { 335 pr_err("could not attach to PHY\n"); 336 return -ENODEV; 337 } 338 } else { 339 if (has_acpi_companion(kdev)) { 340 char mdio_bus_id[MII_BUS_ID_SIZE]; 341 struct mii_bus *unimacbus; 342 343 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d", 344 UNIMAC_MDIO_DRV_NAME, priv->pdev->id); 345 346 unimacbus = mdio_find_bus(mdio_bus_id); 347 if (!unimacbus) { 348 pr_err("Unable to find mii\n"); 349 return -ENODEV; 350 } 351 phydev = phy_find_first(unimacbus); 352 put_device(&unimacbus->dev); 353 if (!phydev) { 354 pr_err("Unable to find PHY\n"); 355 return -ENODEV; 356 } 357 } else { 358 phydev = dev->phydev; 359 } 360 phydev->dev_flags = phy_flags; 361 362 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup, 363 priv->phy_interface); 364 if (ret) { 365 pr_err("could not attach to PHY\n"); 366 return -ENODEV; 367 } 368 } 369 370 /* Configure port multiplexer based on what the probed PHY device since 371 * reading the 'max-speed' property determines the maximum supported 372 * PHY speed which is needed for bcmgenet_mii_config() to configure 373 * things appropriately. 374 */ 375 ret = bcmgenet_mii_config(dev, true); 376 if (ret) { 377 phy_disconnect(dev->phydev); 378 return ret; 379 } 380 381 linkmode_copy(phydev->advertising, phydev->supported); 382 383 /* The internal PHY has its link interrupts routed to the 384 * Ethernet MAC ISRs. On GENETv5 there is a hardware issue 385 * that prevents the signaling of link UP interrupts when 386 * the link operates at 10Mbps, so fallback to polling for 387 * those versions of GENET. 388 */ 389 if (priv->internal_phy && !GENET_IS_V5(priv)) 390 dev->phydev->irq = PHY_IGNORE_INTERRUPT; 391 392 return 0; 393 } 394 395 static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv) 396 { 397 struct device_node *dn = priv->pdev->dev.of_node; 398 struct device *kdev = &priv->pdev->dev; 399 char *compat; 400 401 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version); 402 if (!compat) 403 return NULL; 404 405 priv->mdio_dn = of_get_compatible_child(dn, compat); 406 kfree(compat); 407 if (!priv->mdio_dn) { 408 dev_err(kdev, "unable to find MDIO bus node\n"); 409 return NULL; 410 } 411 412 return priv->mdio_dn; 413 } 414 415 static void bcmgenet_mii_pdata_init(struct bcmgenet_priv *priv, 416 struct unimac_mdio_pdata *ppd) 417 { 418 struct device *kdev = &priv->pdev->dev; 419 struct bcmgenet_platform_data *pd = kdev->platform_data; 420 421 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 422 /* 423 * Internal or external PHY with MDIO access 424 */ 425 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) 426 ppd->phy_mask = 1 << pd->phy_address; 427 else 428 ppd->phy_mask = 0; 429 } 430 } 431 432 static int bcmgenet_mii_wait(void *wait_func_data) 433 { 434 struct bcmgenet_priv *priv = wait_func_data; 435 436 wait_event_timeout(priv->wq, 437 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) 438 & MDIO_START_BUSY), 439 HZ / 100); 440 return 0; 441 } 442 443 static int bcmgenet_mii_register(struct bcmgenet_priv *priv) 444 { 445 struct platform_device *pdev = priv->pdev; 446 struct bcmgenet_platform_data *pdata = pdev->dev.platform_data; 447 struct device_node *dn = pdev->dev.of_node; 448 struct unimac_mdio_pdata ppd; 449 struct platform_device *ppdev; 450 struct resource *pres, res; 451 int id, ret; 452 453 pres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 454 memset(&res, 0, sizeof(res)); 455 memset(&ppd, 0, sizeof(ppd)); 456 457 ppd.wait_func = bcmgenet_mii_wait; 458 ppd.wait_func_data = priv; 459 ppd.bus_name = "bcmgenet MII bus"; 460 461 /* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD 462 * and is 2 * 32-bits word long, 8 bytes total. 463 */ 464 res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD; 465 res.end = res.start + 8; 466 res.flags = IORESOURCE_MEM; 467 468 if (dn) 469 id = of_alias_get_id(dn, "eth"); 470 else 471 id = pdev->id; 472 473 ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id); 474 if (!ppdev) 475 return -ENOMEM; 476 477 /* Retain this platform_device pointer for later cleanup */ 478 priv->mii_pdev = ppdev; 479 ppdev->dev.parent = &pdev->dev; 480 if (dn) 481 ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv); 482 else if (pdata) 483 bcmgenet_mii_pdata_init(priv, &ppd); 484 else 485 ppd.phy_mask = ~0; 486 487 ret = platform_device_add_resources(ppdev, &res, 1); 488 if (ret) 489 goto out; 490 491 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd)); 492 if (ret) 493 goto out; 494 495 ret = platform_device_add(ppdev); 496 if (ret) 497 goto out; 498 499 return 0; 500 out: 501 platform_device_put(ppdev); 502 return ret; 503 } 504 505 static int bcmgenet_phy_interface_init(struct bcmgenet_priv *priv) 506 { 507 struct device *kdev = &priv->pdev->dev; 508 int phy_mode = device_get_phy_mode(kdev); 509 510 if (phy_mode < 0) { 511 dev_err(kdev, "invalid PHY mode property\n"); 512 return phy_mode; 513 } 514 515 priv->phy_interface = phy_mode; 516 517 /* We need to specifically look up whether this PHY interface is 518 * internal or not *before* we even try to probe the PHY driver 519 * over MDIO as we may have shut down the internal PHY for power 520 * saving purposes. 521 */ 522 if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL) 523 priv->internal_phy = true; 524 525 return 0; 526 } 527 528 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv) 529 { 530 struct device_node *dn = priv->pdev->dev.of_node; 531 struct phy_device *phydev; 532 int ret; 533 534 /* Fetch the PHY phandle */ 535 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0); 536 537 /* In the case of a fixed PHY, the DT node associated 538 * to the PHY is the Ethernet MAC DT node. 539 */ 540 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) { 541 ret = of_phy_register_fixed_link(dn); 542 if (ret) 543 return ret; 544 545 priv->phy_dn = of_node_get(dn); 546 } 547 548 /* Get the link mode */ 549 ret = bcmgenet_phy_interface_init(priv); 550 if (ret) 551 return ret; 552 553 /* Make sure we initialize MoCA PHYs with a link down */ 554 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 555 phydev = of_phy_find_device(dn); 556 if (phydev) { 557 phydev->link = 0; 558 put_device(&phydev->mdio.dev); 559 } 560 } 561 562 return 0; 563 } 564 565 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv) 566 { 567 struct device *kdev = &priv->pdev->dev; 568 struct bcmgenet_platform_data *pd = kdev->platform_data; 569 char phy_name[MII_BUS_ID_SIZE + 3]; 570 char mdio_bus_id[MII_BUS_ID_SIZE]; 571 struct phy_device *phydev; 572 573 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d", 574 UNIMAC_MDIO_DRV_NAME, priv->pdev->id); 575 576 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 577 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, 578 mdio_bus_id, pd->phy_address); 579 580 /* 581 * Internal or external PHY with MDIO access 582 */ 583 phydev = phy_attach(priv->dev, phy_name, pd->phy_interface); 584 if (!phydev) { 585 dev_err(kdev, "failed to register PHY device\n"); 586 return -ENODEV; 587 } 588 } else { 589 /* 590 * MoCA port or no MDIO access. 591 * Use fixed PHY to represent the link layer. 592 */ 593 struct fixed_phy_status fphy_status = { 594 .link = 1, 595 .speed = pd->phy_speed, 596 .duplex = pd->phy_duplex, 597 .pause = 0, 598 .asym_pause = 0, 599 }; 600 601 phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL); 602 if (!phydev || IS_ERR(phydev)) { 603 dev_err(kdev, "failed to register fixed PHY device\n"); 604 return -ENODEV; 605 } 606 607 /* Make sure we initialize MoCA PHYs with a link down */ 608 phydev->link = 0; 609 610 } 611 612 priv->phy_interface = pd->phy_interface; 613 614 return 0; 615 } 616 617 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv) 618 { 619 struct device *kdev = &priv->pdev->dev; 620 struct device_node *dn = kdev->of_node; 621 622 if (dn) 623 return bcmgenet_mii_of_init(priv); 624 else if (has_acpi_companion(kdev)) 625 return bcmgenet_phy_interface_init(priv); 626 else 627 return bcmgenet_mii_pd_init(priv); 628 } 629 630 int bcmgenet_mii_init(struct net_device *dev) 631 { 632 struct bcmgenet_priv *priv = netdev_priv(dev); 633 int ret; 634 635 ret = bcmgenet_mii_register(priv); 636 if (ret) 637 return ret; 638 639 ret = bcmgenet_mii_bus_init(priv); 640 if (ret) 641 goto out; 642 643 return 0; 644 645 out: 646 bcmgenet_mii_exit(dev); 647 return ret; 648 } 649 650 void bcmgenet_mii_exit(struct net_device *dev) 651 { 652 struct bcmgenet_priv *priv = netdev_priv(dev); 653 struct device_node *dn = priv->pdev->dev.of_node; 654 655 if (of_phy_is_fixed_link(dn)) 656 of_phy_deregister_fixed_link(dn); 657 of_node_put(priv->phy_dn); 658 platform_device_unregister(priv->mii_pdev); 659 } 660