1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Broadcom GENET (Gigabit Ethernet) controller driver 4 * 5 * Copyright (c) 2014-2019 Broadcom 6 */ 7 8 #define pr_fmt(fmt) "bcmgenet: " fmt 9 10 #include <linux/acpi.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/sched.h> 14 #include <linux/types.h> 15 #include <linux/fcntl.h> 16 #include <linux/interrupt.h> 17 #include <linux/string.h> 18 #include <linux/if_ether.h> 19 #include <linux/init.h> 20 #include <linux/errno.h> 21 #include <linux/delay.h> 22 #include <linux/platform_device.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/pm.h> 25 #include <linux/clk.h> 26 #include <linux/of.h> 27 #include <linux/of_address.h> 28 #include <linux/of_irq.h> 29 #include <linux/of_net.h> 30 #include <linux/of_platform.h> 31 #include <net/arp.h> 32 33 #include <linux/mii.h> 34 #include <linux/ethtool.h> 35 #include <linux/netdevice.h> 36 #include <linux/inetdevice.h> 37 #include <linux/etherdevice.h> 38 #include <linux/skbuff.h> 39 #include <linux/in.h> 40 #include <linux/ip.h> 41 #include <linux/ipv6.h> 42 #include <linux/phy.h> 43 #include <linux/platform_data/bcmgenet.h> 44 45 #include <asm/unaligned.h> 46 47 #include "bcmgenet.h" 48 49 /* Maximum number of hardware queues, downsized if needed */ 50 #define GENET_MAX_MQ_CNT 4 51 52 /* Default highest priority queue for multi queue support */ 53 #define GENET_Q0_PRIORITY 0 54 55 #define GENET_Q16_RX_BD_CNT \ 56 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q) 57 #define GENET_Q16_TX_BD_CNT \ 58 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q) 59 60 #define RX_BUF_LENGTH 2048 61 #define SKB_ALIGNMENT 32 62 63 /* Tx/Rx DMA register offset, skip 256 descriptors */ 64 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd) 65 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32)) 66 67 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \ 68 TOTAL_DESC * DMA_DESC_SIZE) 69 70 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \ 71 TOTAL_DESC * DMA_DESC_SIZE) 72 73 static inline void bcmgenet_writel(u32 value, void __iomem *offset) 74 { 75 /* MIPS chips strapped for BE will automagically configure the 76 * peripheral registers for CPU-native byte order. 77 */ 78 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 79 __raw_writel(value, offset); 80 else 81 writel_relaxed(value, offset); 82 } 83 84 static inline u32 bcmgenet_readl(void __iomem *offset) 85 { 86 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 87 return __raw_readl(offset); 88 else 89 return readl_relaxed(offset); 90 } 91 92 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv, 93 void __iomem *d, u32 value) 94 { 95 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS); 96 } 97 98 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv, 99 void __iomem *d) 100 { 101 return bcmgenet_readl(d + DMA_DESC_LENGTH_STATUS); 102 } 103 104 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv, 105 void __iomem *d, 106 dma_addr_t addr) 107 { 108 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO); 109 110 /* Register writes to GISB bus can take couple hundred nanoseconds 111 * and are done for each packet, save these expensive writes unless 112 * the platform is explicitly configured for 64-bits/LPAE. 113 */ 114 #ifdef CONFIG_PHYS_ADDR_T_64BIT 115 if (priv->hw_params->flags & GENET_HAS_40BITS) 116 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI); 117 #endif 118 } 119 120 /* Combined address + length/status setter */ 121 static inline void dmadesc_set(struct bcmgenet_priv *priv, 122 void __iomem *d, dma_addr_t addr, u32 val) 123 { 124 dmadesc_set_addr(priv, d, addr); 125 dmadesc_set_length_status(priv, d, val); 126 } 127 128 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv, 129 void __iomem *d) 130 { 131 dma_addr_t addr; 132 133 addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO); 134 135 /* Register writes to GISB bus can take couple hundred nanoseconds 136 * and are done for each packet, save these expensive writes unless 137 * the platform is explicitly configured for 64-bits/LPAE. 138 */ 139 #ifdef CONFIG_PHYS_ADDR_T_64BIT 140 if (priv->hw_params->flags & GENET_HAS_40BITS) 141 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32; 142 #endif 143 return addr; 144 } 145 146 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x" 147 148 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ 149 NETIF_MSG_LINK) 150 151 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv) 152 { 153 if (GENET_IS_V1(priv)) 154 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1); 155 else 156 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL); 157 } 158 159 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 160 { 161 if (GENET_IS_V1(priv)) 162 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1); 163 else 164 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL); 165 } 166 167 /* These macros are defined to deal with register map change 168 * between GENET1.1 and GENET2. Only those currently being used 169 * by driver are defined. 170 */ 171 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv) 172 { 173 if (GENET_IS_V1(priv)) 174 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1); 175 else 176 return bcmgenet_readl(priv->base + 177 priv->hw_params->tbuf_offset + TBUF_CTRL); 178 } 179 180 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 181 { 182 if (GENET_IS_V1(priv)) 183 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1); 184 else 185 bcmgenet_writel(val, priv->base + 186 priv->hw_params->tbuf_offset + TBUF_CTRL); 187 } 188 189 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv) 190 { 191 if (GENET_IS_V1(priv)) 192 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1); 193 else 194 return bcmgenet_readl(priv->base + 195 priv->hw_params->tbuf_offset + TBUF_BP_MC); 196 } 197 198 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val) 199 { 200 if (GENET_IS_V1(priv)) 201 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1); 202 else 203 bcmgenet_writel(val, priv->base + 204 priv->hw_params->tbuf_offset + TBUF_BP_MC); 205 } 206 207 /* RX/TX DMA register accessors */ 208 enum dma_reg { 209 DMA_RING_CFG = 0, 210 DMA_CTRL, 211 DMA_STATUS, 212 DMA_SCB_BURST_SIZE, 213 DMA_ARB_CTRL, 214 DMA_PRIORITY_0, 215 DMA_PRIORITY_1, 216 DMA_PRIORITY_2, 217 DMA_INDEX2RING_0, 218 DMA_INDEX2RING_1, 219 DMA_INDEX2RING_2, 220 DMA_INDEX2RING_3, 221 DMA_INDEX2RING_4, 222 DMA_INDEX2RING_5, 223 DMA_INDEX2RING_6, 224 DMA_INDEX2RING_7, 225 DMA_RING0_TIMEOUT, 226 DMA_RING1_TIMEOUT, 227 DMA_RING2_TIMEOUT, 228 DMA_RING3_TIMEOUT, 229 DMA_RING4_TIMEOUT, 230 DMA_RING5_TIMEOUT, 231 DMA_RING6_TIMEOUT, 232 DMA_RING7_TIMEOUT, 233 DMA_RING8_TIMEOUT, 234 DMA_RING9_TIMEOUT, 235 DMA_RING10_TIMEOUT, 236 DMA_RING11_TIMEOUT, 237 DMA_RING12_TIMEOUT, 238 DMA_RING13_TIMEOUT, 239 DMA_RING14_TIMEOUT, 240 DMA_RING15_TIMEOUT, 241 DMA_RING16_TIMEOUT, 242 }; 243 244 static const u8 bcmgenet_dma_regs_v3plus[] = { 245 [DMA_RING_CFG] = 0x00, 246 [DMA_CTRL] = 0x04, 247 [DMA_STATUS] = 0x08, 248 [DMA_SCB_BURST_SIZE] = 0x0C, 249 [DMA_ARB_CTRL] = 0x2C, 250 [DMA_PRIORITY_0] = 0x30, 251 [DMA_PRIORITY_1] = 0x34, 252 [DMA_PRIORITY_2] = 0x38, 253 [DMA_RING0_TIMEOUT] = 0x2C, 254 [DMA_RING1_TIMEOUT] = 0x30, 255 [DMA_RING2_TIMEOUT] = 0x34, 256 [DMA_RING3_TIMEOUT] = 0x38, 257 [DMA_RING4_TIMEOUT] = 0x3c, 258 [DMA_RING5_TIMEOUT] = 0x40, 259 [DMA_RING6_TIMEOUT] = 0x44, 260 [DMA_RING7_TIMEOUT] = 0x48, 261 [DMA_RING8_TIMEOUT] = 0x4c, 262 [DMA_RING9_TIMEOUT] = 0x50, 263 [DMA_RING10_TIMEOUT] = 0x54, 264 [DMA_RING11_TIMEOUT] = 0x58, 265 [DMA_RING12_TIMEOUT] = 0x5c, 266 [DMA_RING13_TIMEOUT] = 0x60, 267 [DMA_RING14_TIMEOUT] = 0x64, 268 [DMA_RING15_TIMEOUT] = 0x68, 269 [DMA_RING16_TIMEOUT] = 0x6C, 270 [DMA_INDEX2RING_0] = 0x70, 271 [DMA_INDEX2RING_1] = 0x74, 272 [DMA_INDEX2RING_2] = 0x78, 273 [DMA_INDEX2RING_3] = 0x7C, 274 [DMA_INDEX2RING_4] = 0x80, 275 [DMA_INDEX2RING_5] = 0x84, 276 [DMA_INDEX2RING_6] = 0x88, 277 [DMA_INDEX2RING_7] = 0x8C, 278 }; 279 280 static const u8 bcmgenet_dma_regs_v2[] = { 281 [DMA_RING_CFG] = 0x00, 282 [DMA_CTRL] = 0x04, 283 [DMA_STATUS] = 0x08, 284 [DMA_SCB_BURST_SIZE] = 0x0C, 285 [DMA_ARB_CTRL] = 0x30, 286 [DMA_PRIORITY_0] = 0x34, 287 [DMA_PRIORITY_1] = 0x38, 288 [DMA_PRIORITY_2] = 0x3C, 289 [DMA_RING0_TIMEOUT] = 0x2C, 290 [DMA_RING1_TIMEOUT] = 0x30, 291 [DMA_RING2_TIMEOUT] = 0x34, 292 [DMA_RING3_TIMEOUT] = 0x38, 293 [DMA_RING4_TIMEOUT] = 0x3c, 294 [DMA_RING5_TIMEOUT] = 0x40, 295 [DMA_RING6_TIMEOUT] = 0x44, 296 [DMA_RING7_TIMEOUT] = 0x48, 297 [DMA_RING8_TIMEOUT] = 0x4c, 298 [DMA_RING9_TIMEOUT] = 0x50, 299 [DMA_RING10_TIMEOUT] = 0x54, 300 [DMA_RING11_TIMEOUT] = 0x58, 301 [DMA_RING12_TIMEOUT] = 0x5c, 302 [DMA_RING13_TIMEOUT] = 0x60, 303 [DMA_RING14_TIMEOUT] = 0x64, 304 [DMA_RING15_TIMEOUT] = 0x68, 305 [DMA_RING16_TIMEOUT] = 0x6C, 306 }; 307 308 static const u8 bcmgenet_dma_regs_v1[] = { 309 [DMA_CTRL] = 0x00, 310 [DMA_STATUS] = 0x04, 311 [DMA_SCB_BURST_SIZE] = 0x0C, 312 [DMA_ARB_CTRL] = 0x30, 313 [DMA_PRIORITY_0] = 0x34, 314 [DMA_PRIORITY_1] = 0x38, 315 [DMA_PRIORITY_2] = 0x3C, 316 [DMA_RING0_TIMEOUT] = 0x2C, 317 [DMA_RING1_TIMEOUT] = 0x30, 318 [DMA_RING2_TIMEOUT] = 0x34, 319 [DMA_RING3_TIMEOUT] = 0x38, 320 [DMA_RING4_TIMEOUT] = 0x3c, 321 [DMA_RING5_TIMEOUT] = 0x40, 322 [DMA_RING6_TIMEOUT] = 0x44, 323 [DMA_RING7_TIMEOUT] = 0x48, 324 [DMA_RING8_TIMEOUT] = 0x4c, 325 [DMA_RING9_TIMEOUT] = 0x50, 326 [DMA_RING10_TIMEOUT] = 0x54, 327 [DMA_RING11_TIMEOUT] = 0x58, 328 [DMA_RING12_TIMEOUT] = 0x5c, 329 [DMA_RING13_TIMEOUT] = 0x60, 330 [DMA_RING14_TIMEOUT] = 0x64, 331 [DMA_RING15_TIMEOUT] = 0x68, 332 [DMA_RING16_TIMEOUT] = 0x6C, 333 }; 334 335 /* Set at runtime once bcmgenet version is known */ 336 static const u8 *bcmgenet_dma_regs; 337 338 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev) 339 { 340 return netdev_priv(dev_get_drvdata(dev)); 341 } 342 343 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv, 344 enum dma_reg r) 345 { 346 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 347 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 348 } 349 350 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv, 351 u32 val, enum dma_reg r) 352 { 353 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 354 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 355 } 356 357 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv, 358 enum dma_reg r) 359 { 360 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 361 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 362 } 363 364 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv, 365 u32 val, enum dma_reg r) 366 { 367 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 368 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 369 } 370 371 /* RDMA/TDMA ring registers and accessors 372 * we merge the common fields and just prefix with T/D the registers 373 * having different meaning depending on the direction 374 */ 375 enum dma_ring_reg { 376 TDMA_READ_PTR = 0, 377 RDMA_WRITE_PTR = TDMA_READ_PTR, 378 TDMA_READ_PTR_HI, 379 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI, 380 TDMA_CONS_INDEX, 381 RDMA_PROD_INDEX = TDMA_CONS_INDEX, 382 TDMA_PROD_INDEX, 383 RDMA_CONS_INDEX = TDMA_PROD_INDEX, 384 DMA_RING_BUF_SIZE, 385 DMA_START_ADDR, 386 DMA_START_ADDR_HI, 387 DMA_END_ADDR, 388 DMA_END_ADDR_HI, 389 DMA_MBUF_DONE_THRESH, 390 TDMA_FLOW_PERIOD, 391 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD, 392 TDMA_WRITE_PTR, 393 RDMA_READ_PTR = TDMA_WRITE_PTR, 394 TDMA_WRITE_PTR_HI, 395 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI 396 }; 397 398 /* GENET v4 supports 40-bits pointer addressing 399 * for obvious reasons the LO and HI word parts 400 * are contiguous, but this offsets the other 401 * registers. 402 */ 403 static const u8 genet_dma_ring_regs_v4[] = { 404 [TDMA_READ_PTR] = 0x00, 405 [TDMA_READ_PTR_HI] = 0x04, 406 [TDMA_CONS_INDEX] = 0x08, 407 [TDMA_PROD_INDEX] = 0x0C, 408 [DMA_RING_BUF_SIZE] = 0x10, 409 [DMA_START_ADDR] = 0x14, 410 [DMA_START_ADDR_HI] = 0x18, 411 [DMA_END_ADDR] = 0x1C, 412 [DMA_END_ADDR_HI] = 0x20, 413 [DMA_MBUF_DONE_THRESH] = 0x24, 414 [TDMA_FLOW_PERIOD] = 0x28, 415 [TDMA_WRITE_PTR] = 0x2C, 416 [TDMA_WRITE_PTR_HI] = 0x30, 417 }; 418 419 static const u8 genet_dma_ring_regs_v123[] = { 420 [TDMA_READ_PTR] = 0x00, 421 [TDMA_CONS_INDEX] = 0x04, 422 [TDMA_PROD_INDEX] = 0x08, 423 [DMA_RING_BUF_SIZE] = 0x0C, 424 [DMA_START_ADDR] = 0x10, 425 [DMA_END_ADDR] = 0x14, 426 [DMA_MBUF_DONE_THRESH] = 0x18, 427 [TDMA_FLOW_PERIOD] = 0x1C, 428 [TDMA_WRITE_PTR] = 0x20, 429 }; 430 431 /* Set at runtime once GENET version is known */ 432 static const u8 *genet_dma_ring_regs; 433 434 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv, 435 unsigned int ring, 436 enum dma_ring_reg r) 437 { 438 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 439 (DMA_RING_SIZE * ring) + 440 genet_dma_ring_regs[r]); 441 } 442 443 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv, 444 unsigned int ring, u32 val, 445 enum dma_ring_reg r) 446 { 447 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 448 (DMA_RING_SIZE * ring) + 449 genet_dma_ring_regs[r]); 450 } 451 452 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv, 453 unsigned int ring, 454 enum dma_ring_reg r) 455 { 456 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 457 (DMA_RING_SIZE * ring) + 458 genet_dma_ring_regs[r]); 459 } 460 461 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv, 462 unsigned int ring, u32 val, 463 enum dma_ring_reg r) 464 { 465 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 466 (DMA_RING_SIZE * ring) + 467 genet_dma_ring_regs[r]); 468 } 469 470 static int bcmgenet_begin(struct net_device *dev) 471 { 472 struct bcmgenet_priv *priv = netdev_priv(dev); 473 474 /* Turn on the clock */ 475 return clk_prepare_enable(priv->clk); 476 } 477 478 static void bcmgenet_complete(struct net_device *dev) 479 { 480 struct bcmgenet_priv *priv = netdev_priv(dev); 481 482 /* Turn off the clock */ 483 clk_disable_unprepare(priv->clk); 484 } 485 486 static int bcmgenet_get_link_ksettings(struct net_device *dev, 487 struct ethtool_link_ksettings *cmd) 488 { 489 if (!netif_running(dev)) 490 return -EINVAL; 491 492 if (!dev->phydev) 493 return -ENODEV; 494 495 phy_ethtool_ksettings_get(dev->phydev, cmd); 496 497 return 0; 498 } 499 500 static int bcmgenet_set_link_ksettings(struct net_device *dev, 501 const struct ethtool_link_ksettings *cmd) 502 { 503 if (!netif_running(dev)) 504 return -EINVAL; 505 506 if (!dev->phydev) 507 return -ENODEV; 508 509 return phy_ethtool_ksettings_set(dev->phydev, cmd); 510 } 511 512 static void bcmgenet_set_rx_csum(struct net_device *dev, 513 netdev_features_t wanted) 514 { 515 struct bcmgenet_priv *priv = netdev_priv(dev); 516 u32 rbuf_chk_ctrl; 517 bool rx_csum_en; 518 519 rx_csum_en = !!(wanted & NETIF_F_RXCSUM); 520 521 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL); 522 523 /* enable rx checksumming */ 524 if (rx_csum_en) 525 rbuf_chk_ctrl |= RBUF_RXCHK_EN | RBUF_L3_PARSE_DIS; 526 else 527 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN; 528 priv->desc_rxchk_en = rx_csum_en; 529 530 /* If UniMAC forwards CRC, we need to skip over it to get 531 * a valid CHK bit to be set in the per-packet status word 532 */ 533 if (rx_csum_en && priv->crc_fwd_en) 534 rbuf_chk_ctrl |= RBUF_SKIP_FCS; 535 else 536 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS; 537 538 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL); 539 } 540 541 static void bcmgenet_set_tx_csum(struct net_device *dev, 542 netdev_features_t wanted) 543 { 544 struct bcmgenet_priv *priv = netdev_priv(dev); 545 bool desc_64b_en; 546 u32 tbuf_ctrl, rbuf_ctrl; 547 548 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv); 549 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 550 551 desc_64b_en = !!(wanted & NETIF_F_HW_CSUM); 552 553 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */ 554 if (desc_64b_en) { 555 tbuf_ctrl |= RBUF_64B_EN; 556 rbuf_ctrl |= RBUF_64B_EN; 557 } else { 558 tbuf_ctrl &= ~RBUF_64B_EN; 559 rbuf_ctrl &= ~RBUF_64B_EN; 560 } 561 priv->desc_64b_en = desc_64b_en; 562 563 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl); 564 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL); 565 } 566 567 static int bcmgenet_set_features(struct net_device *dev, 568 netdev_features_t features) 569 { 570 struct bcmgenet_priv *priv = netdev_priv(dev); 571 u32 reg; 572 int ret; 573 574 ret = clk_prepare_enable(priv->clk); 575 if (ret) 576 return ret; 577 578 /* Make sure we reflect the value of CRC_CMD_FWD */ 579 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 580 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD); 581 582 bcmgenet_set_tx_csum(dev, features); 583 bcmgenet_set_rx_csum(dev, features); 584 585 clk_disable_unprepare(priv->clk); 586 587 return ret; 588 } 589 590 static u32 bcmgenet_get_msglevel(struct net_device *dev) 591 { 592 struct bcmgenet_priv *priv = netdev_priv(dev); 593 594 return priv->msg_enable; 595 } 596 597 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level) 598 { 599 struct bcmgenet_priv *priv = netdev_priv(dev); 600 601 priv->msg_enable = level; 602 } 603 604 static int bcmgenet_get_coalesce(struct net_device *dev, 605 struct ethtool_coalesce *ec) 606 { 607 struct bcmgenet_priv *priv = netdev_priv(dev); 608 struct bcmgenet_rx_ring *ring; 609 unsigned int i; 610 611 ec->tx_max_coalesced_frames = 612 bcmgenet_tdma_ring_readl(priv, DESC_INDEX, 613 DMA_MBUF_DONE_THRESH); 614 ec->rx_max_coalesced_frames = 615 bcmgenet_rdma_ring_readl(priv, DESC_INDEX, 616 DMA_MBUF_DONE_THRESH); 617 ec->rx_coalesce_usecs = 618 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000; 619 620 for (i = 0; i < priv->hw_params->rx_queues; i++) { 621 ring = &priv->rx_rings[i]; 622 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim; 623 } 624 ring = &priv->rx_rings[DESC_INDEX]; 625 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim; 626 627 return 0; 628 } 629 630 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring, 631 u32 usecs, u32 pkts) 632 { 633 struct bcmgenet_priv *priv = ring->priv; 634 unsigned int i = ring->index; 635 u32 reg; 636 637 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH); 638 639 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i); 640 reg &= ~DMA_TIMEOUT_MASK; 641 reg |= DIV_ROUND_UP(usecs * 1000, 8192); 642 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i); 643 } 644 645 static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring, 646 struct ethtool_coalesce *ec) 647 { 648 struct dim_cq_moder moder; 649 u32 usecs, pkts; 650 651 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs; 652 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames; 653 usecs = ring->rx_coalesce_usecs; 654 pkts = ring->rx_max_coalesced_frames; 655 656 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) { 657 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode); 658 usecs = moder.usec; 659 pkts = moder.pkts; 660 } 661 662 ring->dim.use_dim = ec->use_adaptive_rx_coalesce; 663 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 664 } 665 666 static int bcmgenet_set_coalesce(struct net_device *dev, 667 struct ethtool_coalesce *ec) 668 { 669 struct bcmgenet_priv *priv = netdev_priv(dev); 670 unsigned int i; 671 672 /* Base system clock is 125Mhz, DMA timeout is this reference clock 673 * divided by 1024, which yields roughly 8.192us, our maximum value 674 * has to fit in the DMA_TIMEOUT_MASK (16 bits) 675 */ 676 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 677 ec->tx_max_coalesced_frames == 0 || 678 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 679 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1) 680 return -EINVAL; 681 682 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0) 683 return -EINVAL; 684 685 /* GENET TDMA hardware does not support a configurable timeout, but will 686 * always generate an interrupt either after MBDONE packets have been 687 * transmitted, or when the ring is empty. 688 */ 689 if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high || 690 ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low || 691 ec->use_adaptive_tx_coalesce) 692 return -EOPNOTSUPP; 693 694 /* Program all TX queues with the same values, as there is no 695 * ethtool knob to do coalescing on a per-queue basis 696 */ 697 for (i = 0; i < priv->hw_params->tx_queues; i++) 698 bcmgenet_tdma_ring_writel(priv, i, 699 ec->tx_max_coalesced_frames, 700 DMA_MBUF_DONE_THRESH); 701 bcmgenet_tdma_ring_writel(priv, DESC_INDEX, 702 ec->tx_max_coalesced_frames, 703 DMA_MBUF_DONE_THRESH); 704 705 for (i = 0; i < priv->hw_params->rx_queues; i++) 706 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec); 707 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[DESC_INDEX], ec); 708 709 return 0; 710 } 711 712 /* standard ethtool support functions. */ 713 enum bcmgenet_stat_type { 714 BCMGENET_STAT_NETDEV = -1, 715 BCMGENET_STAT_MIB_RX, 716 BCMGENET_STAT_MIB_TX, 717 BCMGENET_STAT_RUNT, 718 BCMGENET_STAT_MISC, 719 BCMGENET_STAT_SOFT, 720 }; 721 722 struct bcmgenet_stats { 723 char stat_string[ETH_GSTRING_LEN]; 724 int stat_sizeof; 725 int stat_offset; 726 enum bcmgenet_stat_type type; 727 /* reg offset from UMAC base for misc counters */ 728 u16 reg_offset; 729 }; 730 731 #define STAT_NETDEV(m) { \ 732 .stat_string = __stringify(m), \ 733 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \ 734 .stat_offset = offsetof(struct net_device_stats, m), \ 735 .type = BCMGENET_STAT_NETDEV, \ 736 } 737 738 #define STAT_GENET_MIB(str, m, _type) { \ 739 .stat_string = str, \ 740 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 741 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 742 .type = _type, \ 743 } 744 745 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX) 746 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX) 747 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT) 748 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT) 749 750 #define STAT_GENET_MISC(str, m, offset) { \ 751 .stat_string = str, \ 752 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 753 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 754 .type = BCMGENET_STAT_MISC, \ 755 .reg_offset = offset, \ 756 } 757 758 #define STAT_GENET_Q(num) \ 759 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \ 760 tx_rings[num].packets), \ 761 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \ 762 tx_rings[num].bytes), \ 763 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \ 764 rx_rings[num].bytes), \ 765 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \ 766 rx_rings[num].packets), \ 767 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \ 768 rx_rings[num].errors), \ 769 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \ 770 rx_rings[num].dropped) 771 772 /* There is a 0xC gap between the end of RX and beginning of TX stats and then 773 * between the end of TX stats and the beginning of the RX RUNT 774 */ 775 #define BCMGENET_STAT_OFFSET 0xc 776 777 /* Hardware counters must be kept in sync because the order/offset 778 * is important here (order in structure declaration = order in hardware) 779 */ 780 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = { 781 /* general stats */ 782 STAT_NETDEV(rx_packets), 783 STAT_NETDEV(tx_packets), 784 STAT_NETDEV(rx_bytes), 785 STAT_NETDEV(tx_bytes), 786 STAT_NETDEV(rx_errors), 787 STAT_NETDEV(tx_errors), 788 STAT_NETDEV(rx_dropped), 789 STAT_NETDEV(tx_dropped), 790 STAT_NETDEV(multicast), 791 /* UniMAC RSV counters */ 792 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), 793 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), 794 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), 795 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), 796 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), 797 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), 798 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), 799 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), 800 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), 801 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), 802 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt), 803 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes), 804 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca), 805 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca), 806 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs), 807 STAT_GENET_MIB_RX("rx_control", mib.rx.cf), 808 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf), 809 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo), 810 STAT_GENET_MIB_RX("rx_align", mib.rx.aln), 811 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr), 812 STAT_GENET_MIB_RX("rx_code", mib.rx.cde), 813 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr), 814 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr), 815 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr), 816 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue), 817 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok), 818 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc), 819 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp), 820 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc), 821 /* UniMAC TSV counters */ 822 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), 823 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), 824 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), 825 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), 826 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), 827 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), 828 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), 829 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), 830 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), 831 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), 832 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts), 833 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca), 834 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca), 835 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf), 836 STAT_GENET_MIB_TX("tx_control", mib.tx.cf), 837 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs), 838 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr), 839 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf), 840 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf), 841 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl), 842 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl), 843 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl), 844 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl), 845 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg), 846 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl), 847 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr), 848 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes), 849 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok), 850 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc), 851 /* UniMAC RUNT counters */ 852 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt), 853 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), 854 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), 855 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes), 856 /* Misc UniMAC counters */ 857 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, 858 UMAC_RBUF_OVFL_CNT_V1), 859 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, 860 UMAC_RBUF_ERR_CNT_V1), 861 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT), 862 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), 863 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed), 864 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed), 865 STAT_GENET_SOFT_MIB("tx_realloc_tsb", mib.tx_realloc_tsb), 866 STAT_GENET_SOFT_MIB("tx_realloc_tsb_failed", 867 mib.tx_realloc_tsb_failed), 868 /* Per TX queues */ 869 STAT_GENET_Q(0), 870 STAT_GENET_Q(1), 871 STAT_GENET_Q(2), 872 STAT_GENET_Q(3), 873 STAT_GENET_Q(16), 874 }; 875 876 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats) 877 878 static void bcmgenet_get_drvinfo(struct net_device *dev, 879 struct ethtool_drvinfo *info) 880 { 881 strlcpy(info->driver, "bcmgenet", sizeof(info->driver)); 882 strlcpy(info->version, "v2.0", sizeof(info->version)); 883 } 884 885 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set) 886 { 887 switch (string_set) { 888 case ETH_SS_STATS: 889 return BCMGENET_STATS_LEN; 890 default: 891 return -EOPNOTSUPP; 892 } 893 } 894 895 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset, 896 u8 *data) 897 { 898 int i; 899 900 switch (stringset) { 901 case ETH_SS_STATS: 902 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 903 memcpy(data + i * ETH_GSTRING_LEN, 904 bcmgenet_gstrings_stats[i].stat_string, 905 ETH_GSTRING_LEN); 906 } 907 break; 908 } 909 } 910 911 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset) 912 { 913 u16 new_offset; 914 u32 val; 915 916 switch (offset) { 917 case UMAC_RBUF_OVFL_CNT_V1: 918 if (GENET_IS_V2(priv)) 919 new_offset = RBUF_OVFL_CNT_V2; 920 else 921 new_offset = RBUF_OVFL_CNT_V3PLUS; 922 923 val = bcmgenet_rbuf_readl(priv, new_offset); 924 /* clear if overflowed */ 925 if (val == ~0) 926 bcmgenet_rbuf_writel(priv, 0, new_offset); 927 break; 928 case UMAC_RBUF_ERR_CNT_V1: 929 if (GENET_IS_V2(priv)) 930 new_offset = RBUF_ERR_CNT_V2; 931 else 932 new_offset = RBUF_ERR_CNT_V3PLUS; 933 934 val = bcmgenet_rbuf_readl(priv, new_offset); 935 /* clear if overflowed */ 936 if (val == ~0) 937 bcmgenet_rbuf_writel(priv, 0, new_offset); 938 break; 939 default: 940 val = bcmgenet_umac_readl(priv, offset); 941 /* clear if overflowed */ 942 if (val == ~0) 943 bcmgenet_umac_writel(priv, 0, offset); 944 break; 945 } 946 947 return val; 948 } 949 950 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv) 951 { 952 int i, j = 0; 953 954 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 955 const struct bcmgenet_stats *s; 956 u8 offset = 0; 957 u32 val = 0; 958 char *p; 959 960 s = &bcmgenet_gstrings_stats[i]; 961 switch (s->type) { 962 case BCMGENET_STAT_NETDEV: 963 case BCMGENET_STAT_SOFT: 964 continue; 965 case BCMGENET_STAT_RUNT: 966 offset += BCMGENET_STAT_OFFSET; 967 /* fall through */ 968 case BCMGENET_STAT_MIB_TX: 969 offset += BCMGENET_STAT_OFFSET; 970 /* fall through */ 971 case BCMGENET_STAT_MIB_RX: 972 val = bcmgenet_umac_readl(priv, 973 UMAC_MIB_START + j + offset); 974 offset = 0; /* Reset Offset */ 975 break; 976 case BCMGENET_STAT_MISC: 977 if (GENET_IS_V1(priv)) { 978 val = bcmgenet_umac_readl(priv, s->reg_offset); 979 /* clear if overflowed */ 980 if (val == ~0) 981 bcmgenet_umac_writel(priv, 0, 982 s->reg_offset); 983 } else { 984 val = bcmgenet_update_stat_misc(priv, 985 s->reg_offset); 986 } 987 break; 988 } 989 990 j += s->stat_sizeof; 991 p = (char *)priv + s->stat_offset; 992 *(u32 *)p = val; 993 } 994 } 995 996 static void bcmgenet_get_ethtool_stats(struct net_device *dev, 997 struct ethtool_stats *stats, 998 u64 *data) 999 { 1000 struct bcmgenet_priv *priv = netdev_priv(dev); 1001 int i; 1002 1003 if (netif_running(dev)) 1004 bcmgenet_update_mib_counters(priv); 1005 1006 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1007 const struct bcmgenet_stats *s; 1008 char *p; 1009 1010 s = &bcmgenet_gstrings_stats[i]; 1011 if (s->type == BCMGENET_STAT_NETDEV) 1012 p = (char *)&dev->stats; 1013 else 1014 p = (char *)priv; 1015 p += s->stat_offset; 1016 if (sizeof(unsigned long) != sizeof(u32) && 1017 s->stat_sizeof == sizeof(unsigned long)) 1018 data[i] = *(unsigned long *)p; 1019 else 1020 data[i] = *(u32 *)p; 1021 } 1022 } 1023 1024 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable) 1025 { 1026 struct bcmgenet_priv *priv = netdev_priv(dev); 1027 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL; 1028 u32 reg; 1029 1030 if (enable && !priv->clk_eee_enabled) { 1031 clk_prepare_enable(priv->clk_eee); 1032 priv->clk_eee_enabled = true; 1033 } 1034 1035 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL); 1036 if (enable) 1037 reg |= EEE_EN; 1038 else 1039 reg &= ~EEE_EN; 1040 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL); 1041 1042 /* Enable EEE and switch to a 27Mhz clock automatically */ 1043 reg = bcmgenet_readl(priv->base + off); 1044 if (enable) 1045 reg |= TBUF_EEE_EN | TBUF_PM_EN; 1046 else 1047 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN); 1048 bcmgenet_writel(reg, priv->base + off); 1049 1050 /* Do the same for thing for RBUF */ 1051 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL); 1052 if (enable) 1053 reg |= RBUF_EEE_EN | RBUF_PM_EN; 1054 else 1055 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN); 1056 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL); 1057 1058 if (!enable && priv->clk_eee_enabled) { 1059 clk_disable_unprepare(priv->clk_eee); 1060 priv->clk_eee_enabled = false; 1061 } 1062 1063 priv->eee.eee_enabled = enable; 1064 priv->eee.eee_active = enable; 1065 } 1066 1067 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e) 1068 { 1069 struct bcmgenet_priv *priv = netdev_priv(dev); 1070 struct ethtool_eee *p = &priv->eee; 1071 1072 if (GENET_IS_V1(priv)) 1073 return -EOPNOTSUPP; 1074 1075 if (!dev->phydev) 1076 return -ENODEV; 1077 1078 e->eee_enabled = p->eee_enabled; 1079 e->eee_active = p->eee_active; 1080 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER); 1081 1082 return phy_ethtool_get_eee(dev->phydev, e); 1083 } 1084 1085 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e) 1086 { 1087 struct bcmgenet_priv *priv = netdev_priv(dev); 1088 struct ethtool_eee *p = &priv->eee; 1089 int ret = 0; 1090 1091 if (GENET_IS_V1(priv)) 1092 return -EOPNOTSUPP; 1093 1094 if (!dev->phydev) 1095 return -ENODEV; 1096 1097 p->eee_enabled = e->eee_enabled; 1098 1099 if (!p->eee_enabled) { 1100 bcmgenet_eee_enable_set(dev, false); 1101 } else { 1102 ret = phy_init_eee(dev->phydev, 0); 1103 if (ret) { 1104 netif_err(priv, hw, dev, "EEE initialization failed\n"); 1105 return ret; 1106 } 1107 1108 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER); 1109 bcmgenet_eee_enable_set(dev, true); 1110 } 1111 1112 return phy_ethtool_set_eee(dev->phydev, e); 1113 } 1114 1115 /* standard ethtool support functions. */ 1116 static const struct ethtool_ops bcmgenet_ethtool_ops = { 1117 .begin = bcmgenet_begin, 1118 .complete = bcmgenet_complete, 1119 .get_strings = bcmgenet_get_strings, 1120 .get_sset_count = bcmgenet_get_sset_count, 1121 .get_ethtool_stats = bcmgenet_get_ethtool_stats, 1122 .get_drvinfo = bcmgenet_get_drvinfo, 1123 .get_link = ethtool_op_get_link, 1124 .get_msglevel = bcmgenet_get_msglevel, 1125 .set_msglevel = bcmgenet_set_msglevel, 1126 .get_wol = bcmgenet_get_wol, 1127 .set_wol = bcmgenet_set_wol, 1128 .get_eee = bcmgenet_get_eee, 1129 .set_eee = bcmgenet_set_eee, 1130 .nway_reset = phy_ethtool_nway_reset, 1131 .get_coalesce = bcmgenet_get_coalesce, 1132 .set_coalesce = bcmgenet_set_coalesce, 1133 .get_link_ksettings = bcmgenet_get_link_ksettings, 1134 .set_link_ksettings = bcmgenet_set_link_ksettings, 1135 .get_ts_info = ethtool_op_get_ts_info, 1136 }; 1137 1138 /* Power down the unimac, based on mode. */ 1139 static int bcmgenet_power_down(struct bcmgenet_priv *priv, 1140 enum bcmgenet_power_mode mode) 1141 { 1142 int ret = 0; 1143 u32 reg; 1144 1145 switch (mode) { 1146 case GENET_POWER_CABLE_SENSE: 1147 phy_detach(priv->dev->phydev); 1148 break; 1149 1150 case GENET_POWER_WOL_MAGIC: 1151 ret = bcmgenet_wol_power_down_cfg(priv, mode); 1152 break; 1153 1154 case GENET_POWER_PASSIVE: 1155 /* Power down LED */ 1156 if (priv->hw_params->flags & GENET_HAS_EXT) { 1157 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1158 if (GENET_IS_V5(priv)) 1159 reg |= EXT_PWR_DOWN_PHY_EN | 1160 EXT_PWR_DOWN_PHY_RD | 1161 EXT_PWR_DOWN_PHY_SD | 1162 EXT_PWR_DOWN_PHY_RX | 1163 EXT_PWR_DOWN_PHY_TX | 1164 EXT_IDDQ_GLBL_PWR; 1165 else 1166 reg |= EXT_PWR_DOWN_PHY; 1167 1168 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1169 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1170 1171 bcmgenet_phy_power_set(priv->dev, false); 1172 } 1173 break; 1174 default: 1175 break; 1176 } 1177 1178 return ret; 1179 } 1180 1181 static void bcmgenet_power_up(struct bcmgenet_priv *priv, 1182 enum bcmgenet_power_mode mode) 1183 { 1184 u32 reg; 1185 1186 if (!(priv->hw_params->flags & GENET_HAS_EXT)) 1187 return; 1188 1189 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1190 1191 switch (mode) { 1192 case GENET_POWER_PASSIVE: 1193 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1194 if (GENET_IS_V5(priv)) { 1195 reg &= ~(EXT_PWR_DOWN_PHY_EN | 1196 EXT_PWR_DOWN_PHY_RD | 1197 EXT_PWR_DOWN_PHY_SD | 1198 EXT_PWR_DOWN_PHY_RX | 1199 EXT_PWR_DOWN_PHY_TX | 1200 EXT_IDDQ_GLBL_PWR); 1201 reg |= EXT_PHY_RESET; 1202 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1203 mdelay(1); 1204 1205 reg &= ~EXT_PHY_RESET; 1206 } else { 1207 reg &= ~EXT_PWR_DOWN_PHY; 1208 reg |= EXT_PWR_DN_EN_LD; 1209 } 1210 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1211 bcmgenet_phy_power_set(priv->dev, true); 1212 break; 1213 1214 case GENET_POWER_CABLE_SENSE: 1215 /* enable APD */ 1216 if (!GENET_IS_V5(priv)) { 1217 reg |= EXT_PWR_DN_EN_LD; 1218 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1219 } 1220 break; 1221 case GENET_POWER_WOL_MAGIC: 1222 bcmgenet_wol_power_up_cfg(priv, mode); 1223 return; 1224 default: 1225 break; 1226 } 1227 } 1228 1229 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv, 1230 struct bcmgenet_tx_ring *ring) 1231 { 1232 struct enet_cb *tx_cb_ptr; 1233 1234 tx_cb_ptr = ring->cbs; 1235 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1236 1237 /* Advancing local write pointer */ 1238 if (ring->write_ptr == ring->end_ptr) 1239 ring->write_ptr = ring->cb_ptr; 1240 else 1241 ring->write_ptr++; 1242 1243 return tx_cb_ptr; 1244 } 1245 1246 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv, 1247 struct bcmgenet_tx_ring *ring) 1248 { 1249 struct enet_cb *tx_cb_ptr; 1250 1251 tx_cb_ptr = ring->cbs; 1252 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1253 1254 /* Rewinding local write pointer */ 1255 if (ring->write_ptr == ring->cb_ptr) 1256 ring->write_ptr = ring->end_ptr; 1257 else 1258 ring->write_ptr--; 1259 1260 return tx_cb_ptr; 1261 } 1262 1263 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring) 1264 { 1265 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 1266 INTRL2_CPU_MASK_SET); 1267 } 1268 1269 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring) 1270 { 1271 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 1272 INTRL2_CPU_MASK_CLEAR); 1273 } 1274 1275 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring) 1276 { 1277 bcmgenet_intrl2_1_writel(ring->priv, 1278 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1279 INTRL2_CPU_MASK_SET); 1280 } 1281 1282 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring) 1283 { 1284 bcmgenet_intrl2_1_writel(ring->priv, 1285 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1286 INTRL2_CPU_MASK_CLEAR); 1287 } 1288 1289 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring) 1290 { 1291 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1292 INTRL2_CPU_MASK_SET); 1293 } 1294 1295 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring) 1296 { 1297 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1298 INTRL2_CPU_MASK_CLEAR); 1299 } 1300 1301 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring) 1302 { 1303 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1304 INTRL2_CPU_MASK_CLEAR); 1305 } 1306 1307 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring) 1308 { 1309 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1310 INTRL2_CPU_MASK_SET); 1311 } 1312 1313 /* Simple helper to free a transmit control block's resources 1314 * Returns an skb when the last transmit control block associated with the 1315 * skb is freed. The skb should be freed by the caller if necessary. 1316 */ 1317 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev, 1318 struct enet_cb *cb) 1319 { 1320 struct sk_buff *skb; 1321 1322 skb = cb->skb; 1323 1324 if (skb) { 1325 cb->skb = NULL; 1326 if (cb == GENET_CB(skb)->first_cb) 1327 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1328 dma_unmap_len(cb, dma_len), 1329 DMA_TO_DEVICE); 1330 else 1331 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr), 1332 dma_unmap_len(cb, dma_len), 1333 DMA_TO_DEVICE); 1334 dma_unmap_addr_set(cb, dma_addr, 0); 1335 1336 if (cb == GENET_CB(skb)->last_cb) 1337 return skb; 1338 1339 } else if (dma_unmap_addr(cb, dma_addr)) { 1340 dma_unmap_page(dev, 1341 dma_unmap_addr(cb, dma_addr), 1342 dma_unmap_len(cb, dma_len), 1343 DMA_TO_DEVICE); 1344 dma_unmap_addr_set(cb, dma_addr, 0); 1345 } 1346 1347 return NULL; 1348 } 1349 1350 /* Simple helper to free a receive control block's resources */ 1351 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev, 1352 struct enet_cb *cb) 1353 { 1354 struct sk_buff *skb; 1355 1356 skb = cb->skb; 1357 cb->skb = NULL; 1358 1359 if (dma_unmap_addr(cb, dma_addr)) { 1360 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1361 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE); 1362 dma_unmap_addr_set(cb, dma_addr, 0); 1363 } 1364 1365 return skb; 1366 } 1367 1368 /* Unlocked version of the reclaim routine */ 1369 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev, 1370 struct bcmgenet_tx_ring *ring) 1371 { 1372 struct bcmgenet_priv *priv = netdev_priv(dev); 1373 unsigned int txbds_processed = 0; 1374 unsigned int bytes_compl = 0; 1375 unsigned int pkts_compl = 0; 1376 unsigned int txbds_ready; 1377 unsigned int c_index; 1378 struct sk_buff *skb; 1379 1380 /* Clear status before servicing to reduce spurious interrupts */ 1381 if (ring->index == DESC_INDEX) 1382 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE, 1383 INTRL2_CPU_CLEAR); 1384 else 1385 bcmgenet_intrl2_1_writel(priv, (1 << ring->index), 1386 INTRL2_CPU_CLEAR); 1387 1388 /* Compute how many buffers are transmitted since last xmit call */ 1389 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX) 1390 & DMA_C_INDEX_MASK; 1391 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK; 1392 1393 netif_dbg(priv, tx_done, dev, 1394 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n", 1395 __func__, ring->index, ring->c_index, c_index, txbds_ready); 1396 1397 /* Reclaim transmitted buffers */ 1398 while (txbds_processed < txbds_ready) { 1399 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, 1400 &priv->tx_cbs[ring->clean_ptr]); 1401 if (skb) { 1402 pkts_compl++; 1403 bytes_compl += GENET_CB(skb)->bytes_sent; 1404 dev_consume_skb_any(skb); 1405 } 1406 1407 txbds_processed++; 1408 if (likely(ring->clean_ptr < ring->end_ptr)) 1409 ring->clean_ptr++; 1410 else 1411 ring->clean_ptr = ring->cb_ptr; 1412 } 1413 1414 ring->free_bds += txbds_processed; 1415 ring->c_index = c_index; 1416 1417 ring->packets += pkts_compl; 1418 ring->bytes += bytes_compl; 1419 1420 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue), 1421 pkts_compl, bytes_compl); 1422 1423 return txbds_processed; 1424 } 1425 1426 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev, 1427 struct bcmgenet_tx_ring *ring) 1428 { 1429 unsigned int released; 1430 1431 spin_lock_bh(&ring->lock); 1432 released = __bcmgenet_tx_reclaim(dev, ring); 1433 spin_unlock_bh(&ring->lock); 1434 1435 return released; 1436 } 1437 1438 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget) 1439 { 1440 struct bcmgenet_tx_ring *ring = 1441 container_of(napi, struct bcmgenet_tx_ring, napi); 1442 unsigned int work_done = 0; 1443 struct netdev_queue *txq; 1444 1445 spin_lock(&ring->lock); 1446 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring); 1447 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) { 1448 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue); 1449 netif_tx_wake_queue(txq); 1450 } 1451 spin_unlock(&ring->lock); 1452 1453 if (work_done == 0) { 1454 napi_complete(napi); 1455 ring->int_enable(ring); 1456 1457 return 0; 1458 } 1459 1460 return budget; 1461 } 1462 1463 static void bcmgenet_tx_reclaim_all(struct net_device *dev) 1464 { 1465 struct bcmgenet_priv *priv = netdev_priv(dev); 1466 int i; 1467 1468 if (netif_is_multiqueue(dev)) { 1469 for (i = 0; i < priv->hw_params->tx_queues; i++) 1470 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]); 1471 } 1472 1473 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]); 1474 } 1475 1476 /* Reallocate the SKB to put enough headroom in front of it and insert 1477 * the transmit checksum offsets in the descriptors 1478 */ 1479 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev, 1480 struct sk_buff *skb) 1481 { 1482 struct bcmgenet_priv *priv = netdev_priv(dev); 1483 struct status_64 *status = NULL; 1484 struct sk_buff *new_skb; 1485 u16 offset; 1486 u8 ip_proto; 1487 __be16 ip_ver; 1488 u32 tx_csum_info; 1489 1490 if (unlikely(skb_headroom(skb) < sizeof(*status))) { 1491 /* If 64 byte status block enabled, must make sure skb has 1492 * enough headroom for us to insert 64B status block. 1493 */ 1494 new_skb = skb_realloc_headroom(skb, sizeof(*status)); 1495 if (!new_skb) { 1496 dev_kfree_skb_any(skb); 1497 priv->mib.tx_realloc_tsb_failed++; 1498 dev->stats.tx_dropped++; 1499 return NULL; 1500 } 1501 dev_consume_skb_any(skb); 1502 skb = new_skb; 1503 priv->mib.tx_realloc_tsb++; 1504 } 1505 1506 skb_push(skb, sizeof(*status)); 1507 status = (struct status_64 *)skb->data; 1508 1509 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1510 ip_ver = skb->protocol; 1511 switch (ip_ver) { 1512 case htons(ETH_P_IP): 1513 ip_proto = ip_hdr(skb)->protocol; 1514 break; 1515 case htons(ETH_P_IPV6): 1516 ip_proto = ipv6_hdr(skb)->nexthdr; 1517 break; 1518 default: 1519 /* don't use UDP flag */ 1520 ip_proto = 0; 1521 break; 1522 } 1523 1524 offset = skb_checksum_start_offset(skb) - sizeof(*status); 1525 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) | 1526 (offset + skb->csum_offset) | 1527 STATUS_TX_CSUM_LV; 1528 1529 /* Set the special UDP flag for UDP */ 1530 if (ip_proto == IPPROTO_UDP) 1531 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP; 1532 1533 status->tx_csum_info = tx_csum_info; 1534 } 1535 1536 return skb; 1537 } 1538 1539 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev) 1540 { 1541 struct bcmgenet_priv *priv = netdev_priv(dev); 1542 struct device *kdev = &priv->pdev->dev; 1543 struct bcmgenet_tx_ring *ring = NULL; 1544 struct enet_cb *tx_cb_ptr; 1545 struct netdev_queue *txq; 1546 int nr_frags, index; 1547 dma_addr_t mapping; 1548 unsigned int size; 1549 skb_frag_t *frag; 1550 u32 len_stat; 1551 int ret; 1552 int i; 1553 1554 index = skb_get_queue_mapping(skb); 1555 /* Mapping strategy: 1556 * queue_mapping = 0, unclassified, packet xmited through ring16 1557 * queue_mapping = 1, goes to ring 0. (highest priority queue 1558 * queue_mapping = 2, goes to ring 1. 1559 * queue_mapping = 3, goes to ring 2. 1560 * queue_mapping = 4, goes to ring 3. 1561 */ 1562 if (index == 0) 1563 index = DESC_INDEX; 1564 else 1565 index -= 1; 1566 1567 ring = &priv->tx_rings[index]; 1568 txq = netdev_get_tx_queue(dev, ring->queue); 1569 1570 nr_frags = skb_shinfo(skb)->nr_frags; 1571 1572 spin_lock(&ring->lock); 1573 if (ring->free_bds <= (nr_frags + 1)) { 1574 if (!netif_tx_queue_stopped(txq)) { 1575 netif_tx_stop_queue(txq); 1576 netdev_err(dev, 1577 "%s: tx ring %d full when queue %d awake\n", 1578 __func__, index, ring->queue); 1579 } 1580 ret = NETDEV_TX_BUSY; 1581 goto out; 1582 } 1583 1584 if (skb_padto(skb, ETH_ZLEN)) { 1585 ret = NETDEV_TX_OK; 1586 goto out; 1587 } 1588 1589 /* Retain how many bytes will be sent on the wire, without TSB inserted 1590 * by transmit checksum offload 1591 */ 1592 GENET_CB(skb)->bytes_sent = skb->len; 1593 1594 /* set the SKB transmit checksum */ 1595 if (priv->desc_64b_en) { 1596 skb = bcmgenet_put_tx_csum(dev, skb); 1597 if (!skb) { 1598 ret = NETDEV_TX_OK; 1599 goto out; 1600 } 1601 } 1602 1603 for (i = 0; i <= nr_frags; i++) { 1604 tx_cb_ptr = bcmgenet_get_txcb(priv, ring); 1605 1606 BUG_ON(!tx_cb_ptr); 1607 1608 if (!i) { 1609 /* Transmit single SKB or head of fragment list */ 1610 GENET_CB(skb)->first_cb = tx_cb_ptr; 1611 size = skb_headlen(skb); 1612 mapping = dma_map_single(kdev, skb->data, size, 1613 DMA_TO_DEVICE); 1614 } else { 1615 /* xmit fragment */ 1616 frag = &skb_shinfo(skb)->frags[i - 1]; 1617 size = skb_frag_size(frag); 1618 mapping = skb_frag_dma_map(kdev, frag, 0, size, 1619 DMA_TO_DEVICE); 1620 } 1621 1622 ret = dma_mapping_error(kdev, mapping); 1623 if (ret) { 1624 priv->mib.tx_dma_failed++; 1625 netif_err(priv, tx_err, dev, "Tx DMA map failed\n"); 1626 ret = NETDEV_TX_OK; 1627 goto out_unmap_frags; 1628 } 1629 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); 1630 dma_unmap_len_set(tx_cb_ptr, dma_len, size); 1631 1632 tx_cb_ptr->skb = skb; 1633 1634 len_stat = (size << DMA_BUFLENGTH_SHIFT) | 1635 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT); 1636 1637 if (!i) { 1638 len_stat |= DMA_TX_APPEND_CRC | DMA_SOP; 1639 if (skb->ip_summed == CHECKSUM_PARTIAL) 1640 len_stat |= DMA_TX_DO_CSUM; 1641 } 1642 if (i == nr_frags) 1643 len_stat |= DMA_EOP; 1644 1645 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat); 1646 } 1647 1648 GENET_CB(skb)->last_cb = tx_cb_ptr; 1649 skb_tx_timestamp(skb); 1650 1651 /* Decrement total BD count and advance our write pointer */ 1652 ring->free_bds -= nr_frags + 1; 1653 ring->prod_index += nr_frags + 1; 1654 ring->prod_index &= DMA_P_INDEX_MASK; 1655 1656 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent); 1657 1658 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) 1659 netif_tx_stop_queue(txq); 1660 1661 if (!netdev_xmit_more() || netif_xmit_stopped(txq)) 1662 /* Packets are ready, update producer index */ 1663 bcmgenet_tdma_ring_writel(priv, ring->index, 1664 ring->prod_index, TDMA_PROD_INDEX); 1665 out: 1666 spin_unlock(&ring->lock); 1667 1668 return ret; 1669 1670 out_unmap_frags: 1671 /* Back up for failed control block mapping */ 1672 bcmgenet_put_txcb(priv, ring); 1673 1674 /* Unmap successfully mapped control blocks */ 1675 while (i-- > 0) { 1676 tx_cb_ptr = bcmgenet_put_txcb(priv, ring); 1677 bcmgenet_free_tx_cb(kdev, tx_cb_ptr); 1678 } 1679 1680 dev_kfree_skb(skb); 1681 goto out; 1682 } 1683 1684 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv, 1685 struct enet_cb *cb) 1686 { 1687 struct device *kdev = &priv->pdev->dev; 1688 struct sk_buff *skb; 1689 struct sk_buff *rx_skb; 1690 dma_addr_t mapping; 1691 1692 /* Allocate a new Rx skb */ 1693 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT); 1694 if (!skb) { 1695 priv->mib.alloc_rx_buff_failed++; 1696 netif_err(priv, rx_err, priv->dev, 1697 "%s: Rx skb allocation failed\n", __func__); 1698 return NULL; 1699 } 1700 1701 /* DMA-map the new Rx skb */ 1702 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len, 1703 DMA_FROM_DEVICE); 1704 if (dma_mapping_error(kdev, mapping)) { 1705 priv->mib.rx_dma_failed++; 1706 dev_kfree_skb_any(skb); 1707 netif_err(priv, rx_err, priv->dev, 1708 "%s: Rx skb DMA mapping failed\n", __func__); 1709 return NULL; 1710 } 1711 1712 /* Grab the current Rx skb from the ring and DMA-unmap it */ 1713 rx_skb = bcmgenet_free_rx_cb(kdev, cb); 1714 1715 /* Put the new Rx skb on the ring */ 1716 cb->skb = skb; 1717 dma_unmap_addr_set(cb, dma_addr, mapping); 1718 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len); 1719 dmadesc_set_addr(priv, cb->bd_addr, mapping); 1720 1721 /* Return the current Rx skb to caller */ 1722 return rx_skb; 1723 } 1724 1725 /* bcmgenet_desc_rx - descriptor based rx process. 1726 * this could be called from bottom half, or from NAPI polling method. 1727 */ 1728 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring, 1729 unsigned int budget) 1730 { 1731 struct bcmgenet_priv *priv = ring->priv; 1732 struct net_device *dev = priv->dev; 1733 struct enet_cb *cb; 1734 struct sk_buff *skb; 1735 u32 dma_length_status; 1736 unsigned long dma_flag; 1737 int len; 1738 unsigned int rxpktprocessed = 0, rxpkttoprocess; 1739 unsigned int bytes_processed = 0; 1740 unsigned int p_index, mask; 1741 unsigned int discards; 1742 1743 /* Clear status before servicing to reduce spurious interrupts */ 1744 if (ring->index == DESC_INDEX) { 1745 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE, 1746 INTRL2_CPU_CLEAR); 1747 } else { 1748 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index); 1749 bcmgenet_intrl2_1_writel(priv, 1750 mask, 1751 INTRL2_CPU_CLEAR); 1752 } 1753 1754 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX); 1755 1756 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) & 1757 DMA_P_INDEX_DISCARD_CNT_MASK; 1758 if (discards > ring->old_discards) { 1759 discards = discards - ring->old_discards; 1760 ring->errors += discards; 1761 ring->old_discards += discards; 1762 1763 /* Clear HW register when we reach 75% of maximum 0xFFFF */ 1764 if (ring->old_discards >= 0xC000) { 1765 ring->old_discards = 0; 1766 bcmgenet_rdma_ring_writel(priv, ring->index, 0, 1767 RDMA_PROD_INDEX); 1768 } 1769 } 1770 1771 p_index &= DMA_P_INDEX_MASK; 1772 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK; 1773 1774 netif_dbg(priv, rx_status, dev, 1775 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess); 1776 1777 while ((rxpktprocessed < rxpkttoprocess) && 1778 (rxpktprocessed < budget)) { 1779 cb = &priv->rx_cbs[ring->read_ptr]; 1780 skb = bcmgenet_rx_refill(priv, cb); 1781 1782 if (unlikely(!skb)) { 1783 ring->dropped++; 1784 goto next; 1785 } 1786 1787 if (!priv->desc_64b_en) { 1788 dma_length_status = 1789 dmadesc_get_length_status(priv, cb->bd_addr); 1790 } else { 1791 struct status_64 *status; 1792 __be16 rx_csum; 1793 1794 status = (struct status_64 *)skb->data; 1795 dma_length_status = status->length_status; 1796 rx_csum = (__force __be16)(status->rx_csum & 0xffff); 1797 if (priv->desc_rxchk_en) { 1798 skb->csum = (__force __wsum)ntohs(rx_csum); 1799 skb->ip_summed = CHECKSUM_COMPLETE; 1800 } 1801 } 1802 1803 /* DMA flags and length are still valid no matter how 1804 * we got the Receive Status Vector (64B RSB or register) 1805 */ 1806 dma_flag = dma_length_status & 0xffff; 1807 len = dma_length_status >> DMA_BUFLENGTH_SHIFT; 1808 1809 netif_dbg(priv, rx_status, dev, 1810 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n", 1811 __func__, p_index, ring->c_index, 1812 ring->read_ptr, dma_length_status); 1813 1814 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) { 1815 netif_err(priv, rx_status, dev, 1816 "dropping fragmented packet!\n"); 1817 ring->errors++; 1818 dev_kfree_skb_any(skb); 1819 goto next; 1820 } 1821 1822 /* report errors */ 1823 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR | 1824 DMA_RX_OV | 1825 DMA_RX_NO | 1826 DMA_RX_LG | 1827 DMA_RX_RXER))) { 1828 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n", 1829 (unsigned int)dma_flag); 1830 if (dma_flag & DMA_RX_CRC_ERROR) 1831 dev->stats.rx_crc_errors++; 1832 if (dma_flag & DMA_RX_OV) 1833 dev->stats.rx_over_errors++; 1834 if (dma_flag & DMA_RX_NO) 1835 dev->stats.rx_frame_errors++; 1836 if (dma_flag & DMA_RX_LG) 1837 dev->stats.rx_length_errors++; 1838 dev->stats.rx_errors++; 1839 dev_kfree_skb_any(skb); 1840 goto next; 1841 } /* error packet */ 1842 1843 skb_put(skb, len); 1844 if (priv->desc_64b_en) { 1845 skb_pull(skb, 64); 1846 len -= 64; 1847 } 1848 1849 /* remove hardware 2bytes added for IP alignment */ 1850 skb_pull(skb, 2); 1851 len -= 2; 1852 1853 if (priv->crc_fwd_en) { 1854 skb_trim(skb, len - ETH_FCS_LEN); 1855 len -= ETH_FCS_LEN; 1856 } 1857 1858 bytes_processed += len; 1859 1860 /*Finish setting up the received SKB and send it to the kernel*/ 1861 skb->protocol = eth_type_trans(skb, priv->dev); 1862 ring->packets++; 1863 ring->bytes += len; 1864 if (dma_flag & DMA_RX_MULT) 1865 dev->stats.multicast++; 1866 1867 /* Notify kernel */ 1868 napi_gro_receive(&ring->napi, skb); 1869 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n"); 1870 1871 next: 1872 rxpktprocessed++; 1873 if (likely(ring->read_ptr < ring->end_ptr)) 1874 ring->read_ptr++; 1875 else 1876 ring->read_ptr = ring->cb_ptr; 1877 1878 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK; 1879 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX); 1880 } 1881 1882 ring->dim.bytes = bytes_processed; 1883 ring->dim.packets = rxpktprocessed; 1884 1885 return rxpktprocessed; 1886 } 1887 1888 /* Rx NAPI polling method */ 1889 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget) 1890 { 1891 struct bcmgenet_rx_ring *ring = container_of(napi, 1892 struct bcmgenet_rx_ring, napi); 1893 struct dim_sample dim_sample = {}; 1894 unsigned int work_done; 1895 1896 work_done = bcmgenet_desc_rx(ring, budget); 1897 1898 if (work_done < budget) { 1899 napi_complete_done(napi, work_done); 1900 ring->int_enable(ring); 1901 } 1902 1903 if (ring->dim.use_dim) { 1904 dim_update_sample(ring->dim.event_ctr, ring->dim.packets, 1905 ring->dim.bytes, &dim_sample); 1906 net_dim(&ring->dim.dim, dim_sample); 1907 } 1908 1909 return work_done; 1910 } 1911 1912 static void bcmgenet_dim_work(struct work_struct *work) 1913 { 1914 struct dim *dim = container_of(work, struct dim, work); 1915 struct bcmgenet_net_dim *ndim = 1916 container_of(dim, struct bcmgenet_net_dim, dim); 1917 struct bcmgenet_rx_ring *ring = 1918 container_of(ndim, struct bcmgenet_rx_ring, dim); 1919 struct dim_cq_moder cur_profile = 1920 net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 1921 1922 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts); 1923 dim->state = DIM_START_MEASURE; 1924 } 1925 1926 /* Assign skb to RX DMA descriptor. */ 1927 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv, 1928 struct bcmgenet_rx_ring *ring) 1929 { 1930 struct enet_cb *cb; 1931 struct sk_buff *skb; 1932 int i; 1933 1934 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 1935 1936 /* loop here for each buffer needing assign */ 1937 for (i = 0; i < ring->size; i++) { 1938 cb = ring->cbs + i; 1939 skb = bcmgenet_rx_refill(priv, cb); 1940 if (skb) 1941 dev_consume_skb_any(skb); 1942 if (!cb->skb) 1943 return -ENOMEM; 1944 } 1945 1946 return 0; 1947 } 1948 1949 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv) 1950 { 1951 struct sk_buff *skb; 1952 struct enet_cb *cb; 1953 int i; 1954 1955 for (i = 0; i < priv->num_rx_bds; i++) { 1956 cb = &priv->rx_cbs[i]; 1957 1958 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb); 1959 if (skb) 1960 dev_consume_skb_any(skb); 1961 } 1962 } 1963 1964 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable) 1965 { 1966 u32 reg; 1967 1968 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 1969 if (enable) 1970 reg |= mask; 1971 else 1972 reg &= ~mask; 1973 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 1974 1975 /* UniMAC stops on a packet boundary, wait for a full-size packet 1976 * to be processed 1977 */ 1978 if (enable == 0) 1979 usleep_range(1000, 2000); 1980 } 1981 1982 static void reset_umac(struct bcmgenet_priv *priv) 1983 { 1984 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */ 1985 bcmgenet_rbuf_ctrl_set(priv, 0); 1986 udelay(10); 1987 1988 /* disable MAC while updating its registers */ 1989 bcmgenet_umac_writel(priv, 0, UMAC_CMD); 1990 1991 /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */ 1992 bcmgenet_umac_writel(priv, CMD_SW_RESET | CMD_LCL_LOOP_EN, UMAC_CMD); 1993 } 1994 1995 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv) 1996 { 1997 /* Mask all interrupts.*/ 1998 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 1999 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 2000 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 2001 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 2002 } 2003 2004 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv) 2005 { 2006 u32 int0_enable = 0; 2007 2008 /* Monitor cable plug/unplugged event for internal PHY, external PHY 2009 * and MoCA PHY 2010 */ 2011 if (priv->internal_phy) { 2012 int0_enable |= UMAC_IRQ_LINK_EVENT; 2013 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv)) 2014 int0_enable |= UMAC_IRQ_PHY_DET_R; 2015 } else if (priv->ext_phy) { 2016 int0_enable |= UMAC_IRQ_LINK_EVENT; 2017 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2018 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 2019 int0_enable |= UMAC_IRQ_LINK_EVENT; 2020 } 2021 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2022 } 2023 2024 static void init_umac(struct bcmgenet_priv *priv) 2025 { 2026 struct device *kdev = &priv->pdev->dev; 2027 u32 reg; 2028 u32 int0_enable = 0; 2029 2030 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n"); 2031 2032 reset_umac(priv); 2033 2034 /* clear tx/rx counter */ 2035 bcmgenet_umac_writel(priv, 2036 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, 2037 UMAC_MIB_CTRL); 2038 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL); 2039 2040 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 2041 2042 /* init rx registers, enable ip header optimization */ 2043 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 2044 reg |= RBUF_ALIGN_2B; 2045 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL); 2046 2047 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) 2048 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL); 2049 2050 bcmgenet_intr_disable(priv); 2051 2052 /* Configure backpressure vectors for MoCA */ 2053 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2054 reg = bcmgenet_bp_mc_get(priv); 2055 reg |= BIT(priv->hw_params->bp_in_en_shift); 2056 2057 /* bp_mask: back pressure mask */ 2058 if (netif_is_multiqueue(priv->dev)) 2059 reg |= priv->hw_params->bp_in_mask; 2060 else 2061 reg &= ~priv->hw_params->bp_in_mask; 2062 bcmgenet_bp_mc_set(priv, reg); 2063 } 2064 2065 /* Enable MDIO interrupts on GENET v3+ */ 2066 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR) 2067 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR); 2068 2069 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2070 2071 dev_dbg(kdev, "done init umac\n"); 2072 } 2073 2074 static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring, 2075 void (*cb)(struct work_struct *work)) 2076 { 2077 struct bcmgenet_net_dim *dim = &ring->dim; 2078 2079 INIT_WORK(&dim->dim.work, cb); 2080 dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2081 dim->event_ctr = 0; 2082 dim->packets = 0; 2083 dim->bytes = 0; 2084 } 2085 2086 static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring) 2087 { 2088 struct bcmgenet_net_dim *dim = &ring->dim; 2089 struct dim_cq_moder moder; 2090 u32 usecs, pkts; 2091 2092 usecs = ring->rx_coalesce_usecs; 2093 pkts = ring->rx_max_coalesced_frames; 2094 2095 /* If DIM was enabled, re-apply default parameters */ 2096 if (dim->use_dim) { 2097 moder = net_dim_get_def_rx_moderation(dim->dim.mode); 2098 usecs = moder.usec; 2099 pkts = moder.pkts; 2100 } 2101 2102 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 2103 } 2104 2105 /* Initialize a Tx ring along with corresponding hardware registers */ 2106 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv, 2107 unsigned int index, unsigned int size, 2108 unsigned int start_ptr, unsigned int end_ptr) 2109 { 2110 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index]; 2111 u32 words_per_bd = WORDS_PER_BD(priv); 2112 u32 flow_period_val = 0; 2113 2114 spin_lock_init(&ring->lock); 2115 ring->priv = priv; 2116 ring->index = index; 2117 if (index == DESC_INDEX) { 2118 ring->queue = 0; 2119 ring->int_enable = bcmgenet_tx_ring16_int_enable; 2120 ring->int_disable = bcmgenet_tx_ring16_int_disable; 2121 } else { 2122 ring->queue = index + 1; 2123 ring->int_enable = bcmgenet_tx_ring_int_enable; 2124 ring->int_disable = bcmgenet_tx_ring_int_disable; 2125 } 2126 ring->cbs = priv->tx_cbs + start_ptr; 2127 ring->size = size; 2128 ring->clean_ptr = start_ptr; 2129 ring->c_index = 0; 2130 ring->free_bds = size; 2131 ring->write_ptr = start_ptr; 2132 ring->cb_ptr = start_ptr; 2133 ring->end_ptr = end_ptr - 1; 2134 ring->prod_index = 0; 2135 2136 /* Set flow period for ring != 16 */ 2137 if (index != DESC_INDEX) 2138 flow_period_val = ENET_MAX_MTU_SIZE << 16; 2139 2140 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX); 2141 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX); 2142 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); 2143 /* Disable rate control for now */ 2144 bcmgenet_tdma_ring_writel(priv, index, flow_period_val, 2145 TDMA_FLOW_PERIOD); 2146 bcmgenet_tdma_ring_writel(priv, index, 2147 ((size << DMA_RING_SIZE_SHIFT) | 2148 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2149 2150 /* Set start and end address, read and write pointers */ 2151 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2152 DMA_START_ADDR); 2153 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2154 TDMA_READ_PTR); 2155 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2156 TDMA_WRITE_PTR); 2157 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2158 DMA_END_ADDR); 2159 2160 /* Initialize Tx NAPI */ 2161 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 2162 NAPI_POLL_WEIGHT); 2163 } 2164 2165 /* Initialize a RDMA ring */ 2166 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv, 2167 unsigned int index, unsigned int size, 2168 unsigned int start_ptr, unsigned int end_ptr) 2169 { 2170 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index]; 2171 u32 words_per_bd = WORDS_PER_BD(priv); 2172 int ret; 2173 2174 ring->priv = priv; 2175 ring->index = index; 2176 if (index == DESC_INDEX) { 2177 ring->int_enable = bcmgenet_rx_ring16_int_enable; 2178 ring->int_disable = bcmgenet_rx_ring16_int_disable; 2179 } else { 2180 ring->int_enable = bcmgenet_rx_ring_int_enable; 2181 ring->int_disable = bcmgenet_rx_ring_int_disable; 2182 } 2183 ring->cbs = priv->rx_cbs + start_ptr; 2184 ring->size = size; 2185 ring->c_index = 0; 2186 ring->read_ptr = start_ptr; 2187 ring->cb_ptr = start_ptr; 2188 ring->end_ptr = end_ptr - 1; 2189 2190 ret = bcmgenet_alloc_rx_buffers(priv, ring); 2191 if (ret) 2192 return ret; 2193 2194 bcmgenet_init_dim(ring, bcmgenet_dim_work); 2195 bcmgenet_init_rx_coalesce(ring); 2196 2197 /* Initialize Rx NAPI */ 2198 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 2199 NAPI_POLL_WEIGHT); 2200 2201 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX); 2202 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX); 2203 bcmgenet_rdma_ring_writel(priv, index, 2204 ((size << DMA_RING_SIZE_SHIFT) | 2205 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2206 bcmgenet_rdma_ring_writel(priv, index, 2207 (DMA_FC_THRESH_LO << 2208 DMA_XOFF_THRESHOLD_SHIFT) | 2209 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH); 2210 2211 /* Set start and end address, read and write pointers */ 2212 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2213 DMA_START_ADDR); 2214 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2215 RDMA_READ_PTR); 2216 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2217 RDMA_WRITE_PTR); 2218 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2219 DMA_END_ADDR); 2220 2221 return ret; 2222 } 2223 2224 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv) 2225 { 2226 unsigned int i; 2227 struct bcmgenet_tx_ring *ring; 2228 2229 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2230 ring = &priv->tx_rings[i]; 2231 napi_enable(&ring->napi); 2232 ring->int_enable(ring); 2233 } 2234 2235 ring = &priv->tx_rings[DESC_INDEX]; 2236 napi_enable(&ring->napi); 2237 ring->int_enable(ring); 2238 } 2239 2240 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv) 2241 { 2242 unsigned int i; 2243 struct bcmgenet_tx_ring *ring; 2244 2245 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2246 ring = &priv->tx_rings[i]; 2247 napi_disable(&ring->napi); 2248 } 2249 2250 ring = &priv->tx_rings[DESC_INDEX]; 2251 napi_disable(&ring->napi); 2252 } 2253 2254 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv) 2255 { 2256 unsigned int i; 2257 struct bcmgenet_tx_ring *ring; 2258 2259 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2260 ring = &priv->tx_rings[i]; 2261 netif_napi_del(&ring->napi); 2262 } 2263 2264 ring = &priv->tx_rings[DESC_INDEX]; 2265 netif_napi_del(&ring->napi); 2266 } 2267 2268 /* Initialize Tx queues 2269 * 2270 * Queues 0-3 are priority-based, each one has 32 descriptors, 2271 * with queue 0 being the highest priority queue. 2272 * 2273 * Queue 16 is the default Tx queue with 2274 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors. 2275 * 2276 * The transmit control block pool is then partitioned as follows: 2277 * - Tx queue 0 uses tx_cbs[0..31] 2278 * - Tx queue 1 uses tx_cbs[32..63] 2279 * - Tx queue 2 uses tx_cbs[64..95] 2280 * - Tx queue 3 uses tx_cbs[96..127] 2281 * - Tx queue 16 uses tx_cbs[128..255] 2282 */ 2283 static void bcmgenet_init_tx_queues(struct net_device *dev) 2284 { 2285 struct bcmgenet_priv *priv = netdev_priv(dev); 2286 u32 i, dma_enable; 2287 u32 dma_ctrl, ring_cfg; 2288 u32 dma_priority[3] = {0, 0, 0}; 2289 2290 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL); 2291 dma_enable = dma_ctrl & DMA_EN; 2292 dma_ctrl &= ~DMA_EN; 2293 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2294 2295 dma_ctrl = 0; 2296 ring_cfg = 0; 2297 2298 /* Enable strict priority arbiter mode */ 2299 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL); 2300 2301 /* Initialize Tx priority queues */ 2302 for (i = 0; i < priv->hw_params->tx_queues; i++) { 2303 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q, 2304 i * priv->hw_params->tx_bds_per_q, 2305 (i + 1) * priv->hw_params->tx_bds_per_q); 2306 ring_cfg |= (1 << i); 2307 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2308 dma_priority[DMA_PRIO_REG_INDEX(i)] |= 2309 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i)); 2310 } 2311 2312 /* Initialize Tx default queue 16 */ 2313 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT, 2314 priv->hw_params->tx_queues * 2315 priv->hw_params->tx_bds_per_q, 2316 TOTAL_DESC); 2317 ring_cfg |= (1 << DESC_INDEX); 2318 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2319 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |= 2320 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 2321 DMA_PRIO_REG_SHIFT(DESC_INDEX)); 2322 2323 /* Set Tx queue priorities */ 2324 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0); 2325 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1); 2326 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2); 2327 2328 /* Enable Tx queues */ 2329 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG); 2330 2331 /* Enable Tx DMA */ 2332 if (dma_enable) 2333 dma_ctrl |= DMA_EN; 2334 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2335 } 2336 2337 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv) 2338 { 2339 unsigned int i; 2340 struct bcmgenet_rx_ring *ring; 2341 2342 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2343 ring = &priv->rx_rings[i]; 2344 napi_enable(&ring->napi); 2345 ring->int_enable(ring); 2346 } 2347 2348 ring = &priv->rx_rings[DESC_INDEX]; 2349 napi_enable(&ring->napi); 2350 ring->int_enable(ring); 2351 } 2352 2353 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv) 2354 { 2355 unsigned int i; 2356 struct bcmgenet_rx_ring *ring; 2357 2358 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2359 ring = &priv->rx_rings[i]; 2360 napi_disable(&ring->napi); 2361 cancel_work_sync(&ring->dim.dim.work); 2362 } 2363 2364 ring = &priv->rx_rings[DESC_INDEX]; 2365 napi_disable(&ring->napi); 2366 cancel_work_sync(&ring->dim.dim.work); 2367 } 2368 2369 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv) 2370 { 2371 unsigned int i; 2372 struct bcmgenet_rx_ring *ring; 2373 2374 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2375 ring = &priv->rx_rings[i]; 2376 netif_napi_del(&ring->napi); 2377 } 2378 2379 ring = &priv->rx_rings[DESC_INDEX]; 2380 netif_napi_del(&ring->napi); 2381 } 2382 2383 /* Initialize Rx queues 2384 * 2385 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be 2386 * used to direct traffic to these queues. 2387 * 2388 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors. 2389 */ 2390 static int bcmgenet_init_rx_queues(struct net_device *dev) 2391 { 2392 struct bcmgenet_priv *priv = netdev_priv(dev); 2393 u32 i; 2394 u32 dma_enable; 2395 u32 dma_ctrl; 2396 u32 ring_cfg; 2397 int ret; 2398 2399 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL); 2400 dma_enable = dma_ctrl & DMA_EN; 2401 dma_ctrl &= ~DMA_EN; 2402 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2403 2404 dma_ctrl = 0; 2405 ring_cfg = 0; 2406 2407 /* Initialize Rx priority queues */ 2408 for (i = 0; i < priv->hw_params->rx_queues; i++) { 2409 ret = bcmgenet_init_rx_ring(priv, i, 2410 priv->hw_params->rx_bds_per_q, 2411 i * priv->hw_params->rx_bds_per_q, 2412 (i + 1) * 2413 priv->hw_params->rx_bds_per_q); 2414 if (ret) 2415 return ret; 2416 2417 ring_cfg |= (1 << i); 2418 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2419 } 2420 2421 /* Initialize Rx default queue 16 */ 2422 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT, 2423 priv->hw_params->rx_queues * 2424 priv->hw_params->rx_bds_per_q, 2425 TOTAL_DESC); 2426 if (ret) 2427 return ret; 2428 2429 ring_cfg |= (1 << DESC_INDEX); 2430 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2431 2432 /* Enable rings */ 2433 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG); 2434 2435 /* Configure ring as descriptor ring and re-enable DMA if enabled */ 2436 if (dma_enable) 2437 dma_ctrl |= DMA_EN; 2438 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2439 2440 return 0; 2441 } 2442 2443 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv) 2444 { 2445 int ret = 0; 2446 int timeout = 0; 2447 u32 reg; 2448 u32 dma_ctrl; 2449 int i; 2450 2451 /* Disable TDMA to stop add more frames in TX DMA */ 2452 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2453 reg &= ~DMA_EN; 2454 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2455 2456 /* Check TDMA status register to confirm TDMA is disabled */ 2457 while (timeout++ < DMA_TIMEOUT_VAL) { 2458 reg = bcmgenet_tdma_readl(priv, DMA_STATUS); 2459 if (reg & DMA_DISABLED) 2460 break; 2461 2462 udelay(1); 2463 } 2464 2465 if (timeout == DMA_TIMEOUT_VAL) { 2466 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n"); 2467 ret = -ETIMEDOUT; 2468 } 2469 2470 /* Wait 10ms for packet drain in both tx and rx dma */ 2471 usleep_range(10000, 20000); 2472 2473 /* Disable RDMA */ 2474 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2475 reg &= ~DMA_EN; 2476 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2477 2478 timeout = 0; 2479 /* Check RDMA status register to confirm RDMA is disabled */ 2480 while (timeout++ < DMA_TIMEOUT_VAL) { 2481 reg = bcmgenet_rdma_readl(priv, DMA_STATUS); 2482 if (reg & DMA_DISABLED) 2483 break; 2484 2485 udelay(1); 2486 } 2487 2488 if (timeout == DMA_TIMEOUT_VAL) { 2489 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n"); 2490 ret = -ETIMEDOUT; 2491 } 2492 2493 dma_ctrl = 0; 2494 for (i = 0; i < priv->hw_params->rx_queues; i++) 2495 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2496 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2497 reg &= ~dma_ctrl; 2498 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2499 2500 dma_ctrl = 0; 2501 for (i = 0; i < priv->hw_params->tx_queues; i++) 2502 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2503 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2504 reg &= ~dma_ctrl; 2505 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2506 2507 return ret; 2508 } 2509 2510 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv) 2511 { 2512 struct netdev_queue *txq; 2513 int i; 2514 2515 bcmgenet_fini_rx_napi(priv); 2516 bcmgenet_fini_tx_napi(priv); 2517 2518 for (i = 0; i < priv->num_tx_bds; i++) 2519 dev_kfree_skb(bcmgenet_free_tx_cb(&priv->pdev->dev, 2520 priv->tx_cbs + i)); 2521 2522 for (i = 0; i < priv->hw_params->tx_queues; i++) { 2523 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue); 2524 netdev_tx_reset_queue(txq); 2525 } 2526 2527 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue); 2528 netdev_tx_reset_queue(txq); 2529 2530 bcmgenet_free_rx_buffers(priv); 2531 kfree(priv->rx_cbs); 2532 kfree(priv->tx_cbs); 2533 } 2534 2535 /* init_edma: Initialize DMA control register */ 2536 static int bcmgenet_init_dma(struct bcmgenet_priv *priv) 2537 { 2538 int ret; 2539 unsigned int i; 2540 struct enet_cb *cb; 2541 2542 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 2543 2544 /* Initialize common Rx ring structures */ 2545 priv->rx_bds = priv->base + priv->hw_params->rdma_offset; 2546 priv->num_rx_bds = TOTAL_DESC; 2547 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb), 2548 GFP_KERNEL); 2549 if (!priv->rx_cbs) 2550 return -ENOMEM; 2551 2552 for (i = 0; i < priv->num_rx_bds; i++) { 2553 cb = priv->rx_cbs + i; 2554 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE; 2555 } 2556 2557 /* Initialize common TX ring structures */ 2558 priv->tx_bds = priv->base + priv->hw_params->tdma_offset; 2559 priv->num_tx_bds = TOTAL_DESC; 2560 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb), 2561 GFP_KERNEL); 2562 if (!priv->tx_cbs) { 2563 kfree(priv->rx_cbs); 2564 return -ENOMEM; 2565 } 2566 2567 for (i = 0; i < priv->num_tx_bds; i++) { 2568 cb = priv->tx_cbs + i; 2569 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE; 2570 } 2571 2572 /* Init rDma */ 2573 bcmgenet_rdma_writel(priv, priv->dma_max_burst_length, 2574 DMA_SCB_BURST_SIZE); 2575 2576 /* Initialize Rx queues */ 2577 ret = bcmgenet_init_rx_queues(priv->dev); 2578 if (ret) { 2579 netdev_err(priv->dev, "failed to initialize Rx queues\n"); 2580 bcmgenet_free_rx_buffers(priv); 2581 kfree(priv->rx_cbs); 2582 kfree(priv->tx_cbs); 2583 return ret; 2584 } 2585 2586 /* Init tDma */ 2587 bcmgenet_tdma_writel(priv, priv->dma_max_burst_length, 2588 DMA_SCB_BURST_SIZE); 2589 2590 /* Initialize Tx queues */ 2591 bcmgenet_init_tx_queues(priv->dev); 2592 2593 return 0; 2594 } 2595 2596 /* Interrupt bottom half */ 2597 static void bcmgenet_irq_task(struct work_struct *work) 2598 { 2599 unsigned int status; 2600 struct bcmgenet_priv *priv = container_of( 2601 work, struct bcmgenet_priv, bcmgenet_irq_work); 2602 2603 netif_dbg(priv, intr, priv->dev, "%s\n", __func__); 2604 2605 spin_lock_irq(&priv->lock); 2606 status = priv->irq0_stat; 2607 priv->irq0_stat = 0; 2608 spin_unlock_irq(&priv->lock); 2609 2610 if (status & UMAC_IRQ_PHY_DET_R && 2611 priv->dev->phydev->autoneg != AUTONEG_ENABLE) { 2612 phy_init_hw(priv->dev->phydev); 2613 genphy_config_aneg(priv->dev->phydev); 2614 } 2615 2616 /* Link UP/DOWN event */ 2617 if (status & UMAC_IRQ_LINK_EVENT) 2618 phy_mac_interrupt(priv->dev->phydev); 2619 2620 } 2621 2622 /* bcmgenet_isr1: handle Rx and Tx priority queues */ 2623 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id) 2624 { 2625 struct bcmgenet_priv *priv = dev_id; 2626 struct bcmgenet_rx_ring *rx_ring; 2627 struct bcmgenet_tx_ring *tx_ring; 2628 unsigned int index, status; 2629 2630 /* Read irq status */ 2631 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) & 2632 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 2633 2634 /* clear interrupts */ 2635 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR); 2636 2637 netif_dbg(priv, intr, priv->dev, 2638 "%s: IRQ=0x%x\n", __func__, status); 2639 2640 /* Check Rx priority queue interrupts */ 2641 for (index = 0; index < priv->hw_params->rx_queues; index++) { 2642 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index))) 2643 continue; 2644 2645 rx_ring = &priv->rx_rings[index]; 2646 rx_ring->dim.event_ctr++; 2647 2648 if (likely(napi_schedule_prep(&rx_ring->napi))) { 2649 rx_ring->int_disable(rx_ring); 2650 __napi_schedule_irqoff(&rx_ring->napi); 2651 } 2652 } 2653 2654 /* Check Tx priority queue interrupts */ 2655 for (index = 0; index < priv->hw_params->tx_queues; index++) { 2656 if (!(status & BIT(index))) 2657 continue; 2658 2659 tx_ring = &priv->tx_rings[index]; 2660 2661 if (likely(napi_schedule_prep(&tx_ring->napi))) { 2662 tx_ring->int_disable(tx_ring); 2663 __napi_schedule_irqoff(&tx_ring->napi); 2664 } 2665 } 2666 2667 return IRQ_HANDLED; 2668 } 2669 2670 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */ 2671 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id) 2672 { 2673 struct bcmgenet_priv *priv = dev_id; 2674 struct bcmgenet_rx_ring *rx_ring; 2675 struct bcmgenet_tx_ring *tx_ring; 2676 unsigned int status; 2677 unsigned long flags; 2678 2679 /* Read irq status */ 2680 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) & 2681 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 2682 2683 /* clear interrupts */ 2684 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR); 2685 2686 netif_dbg(priv, intr, priv->dev, 2687 "IRQ=0x%x\n", status); 2688 2689 if (status & UMAC_IRQ_RXDMA_DONE) { 2690 rx_ring = &priv->rx_rings[DESC_INDEX]; 2691 rx_ring->dim.event_ctr++; 2692 2693 if (likely(napi_schedule_prep(&rx_ring->napi))) { 2694 rx_ring->int_disable(rx_ring); 2695 __napi_schedule_irqoff(&rx_ring->napi); 2696 } 2697 } 2698 2699 if (status & UMAC_IRQ_TXDMA_DONE) { 2700 tx_ring = &priv->tx_rings[DESC_INDEX]; 2701 2702 if (likely(napi_schedule_prep(&tx_ring->napi))) { 2703 tx_ring->int_disable(tx_ring); 2704 __napi_schedule_irqoff(&tx_ring->napi); 2705 } 2706 } 2707 2708 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) && 2709 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) { 2710 wake_up(&priv->wq); 2711 } 2712 2713 /* all other interested interrupts handled in bottom half */ 2714 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R); 2715 if (status) { 2716 /* Save irq status for bottom-half processing. */ 2717 spin_lock_irqsave(&priv->lock, flags); 2718 priv->irq0_stat |= status; 2719 spin_unlock_irqrestore(&priv->lock, flags); 2720 2721 schedule_work(&priv->bcmgenet_irq_work); 2722 } 2723 2724 return IRQ_HANDLED; 2725 } 2726 2727 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id) 2728 { 2729 struct bcmgenet_priv *priv = dev_id; 2730 2731 pm_wakeup_event(&priv->pdev->dev, 0); 2732 2733 return IRQ_HANDLED; 2734 } 2735 2736 #ifdef CONFIG_NET_POLL_CONTROLLER 2737 static void bcmgenet_poll_controller(struct net_device *dev) 2738 { 2739 struct bcmgenet_priv *priv = netdev_priv(dev); 2740 2741 /* Invoke the main RX/TX interrupt handler */ 2742 disable_irq(priv->irq0); 2743 bcmgenet_isr0(priv->irq0, priv); 2744 enable_irq(priv->irq0); 2745 2746 /* And the interrupt handler for RX/TX priority queues */ 2747 disable_irq(priv->irq1); 2748 bcmgenet_isr1(priv->irq1, priv); 2749 enable_irq(priv->irq1); 2750 } 2751 #endif 2752 2753 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv) 2754 { 2755 u32 reg; 2756 2757 reg = bcmgenet_rbuf_ctrl_get(priv); 2758 reg |= BIT(1); 2759 bcmgenet_rbuf_ctrl_set(priv, reg); 2760 udelay(10); 2761 2762 reg &= ~BIT(1); 2763 bcmgenet_rbuf_ctrl_set(priv, reg); 2764 udelay(10); 2765 } 2766 2767 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv, 2768 unsigned char *addr) 2769 { 2770 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) | 2771 (addr[2] << 8) | addr[3], UMAC_MAC0); 2772 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1); 2773 } 2774 2775 static void bcmgenet_get_hw_addr(struct bcmgenet_priv *priv, 2776 unsigned char *addr) 2777 { 2778 u32 addr_tmp; 2779 2780 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC0); 2781 addr[0] = addr_tmp >> 24; 2782 addr[1] = (addr_tmp >> 16) & 0xff; 2783 addr[2] = (addr_tmp >> 8) & 0xff; 2784 addr[3] = addr_tmp & 0xff; 2785 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC1); 2786 addr[4] = (addr_tmp >> 8) & 0xff; 2787 addr[5] = addr_tmp & 0xff; 2788 } 2789 2790 /* Returns a reusable dma control register value */ 2791 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv) 2792 { 2793 u32 reg; 2794 u32 dma_ctrl; 2795 2796 /* disable DMA */ 2797 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN; 2798 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2799 reg &= ~dma_ctrl; 2800 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2801 2802 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2803 reg &= ~dma_ctrl; 2804 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2805 2806 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH); 2807 udelay(10); 2808 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH); 2809 2810 return dma_ctrl; 2811 } 2812 2813 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl) 2814 { 2815 u32 reg; 2816 2817 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2818 reg |= dma_ctrl; 2819 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2820 2821 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2822 reg |= dma_ctrl; 2823 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2824 } 2825 2826 /* bcmgenet_hfb_clear 2827 * 2828 * Clear Hardware Filter Block and disable all filtering. 2829 */ 2830 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv) 2831 { 2832 u32 i; 2833 2834 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL); 2835 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS); 2836 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4); 2837 2838 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++) 2839 bcmgenet_rdma_writel(priv, 0x0, i); 2840 2841 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++) 2842 bcmgenet_hfb_reg_writel(priv, 0x0, 2843 HFB_FLT_LEN_V3PLUS + i * sizeof(u32)); 2844 2845 for (i = 0; i < priv->hw_params->hfb_filter_cnt * 2846 priv->hw_params->hfb_filter_size; i++) 2847 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32)); 2848 } 2849 2850 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv) 2851 { 2852 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) 2853 return; 2854 2855 bcmgenet_hfb_clear(priv); 2856 } 2857 2858 static void bcmgenet_netif_start(struct net_device *dev) 2859 { 2860 struct bcmgenet_priv *priv = netdev_priv(dev); 2861 2862 /* Start the network engine */ 2863 bcmgenet_enable_rx_napi(priv); 2864 2865 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true); 2866 2867 bcmgenet_enable_tx_napi(priv); 2868 2869 /* Monitor link interrupts now */ 2870 bcmgenet_link_intr_enable(priv); 2871 2872 phy_start(dev->phydev); 2873 } 2874 2875 static int bcmgenet_open(struct net_device *dev) 2876 { 2877 struct bcmgenet_priv *priv = netdev_priv(dev); 2878 unsigned long dma_ctrl; 2879 u32 reg; 2880 int ret; 2881 2882 netif_dbg(priv, ifup, dev, "bcmgenet_open\n"); 2883 2884 /* Turn on the clock */ 2885 clk_prepare_enable(priv->clk); 2886 2887 /* If this is an internal GPHY, power it back on now, before UniMAC is 2888 * brought out of reset as absolutely no UniMAC activity is allowed 2889 */ 2890 if (priv->internal_phy) 2891 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 2892 2893 /* take MAC out of reset */ 2894 bcmgenet_umac_reset(priv); 2895 2896 init_umac(priv); 2897 2898 /* Apply features again in case we changed them while interface was 2899 * down 2900 */ 2901 bcmgenet_set_features(dev, dev->features); 2902 2903 bcmgenet_set_hw_addr(priv, dev->dev_addr); 2904 2905 if (priv->internal_phy) { 2906 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 2907 reg |= EXT_ENERGY_DET_MASK; 2908 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 2909 } 2910 2911 /* Disable RX/TX DMA and flush TX queues */ 2912 dma_ctrl = bcmgenet_dma_disable(priv); 2913 2914 /* Reinitialize TDMA and RDMA and SW housekeeping */ 2915 ret = bcmgenet_init_dma(priv); 2916 if (ret) { 2917 netdev_err(dev, "failed to initialize DMA\n"); 2918 goto err_clk_disable; 2919 } 2920 2921 /* Always enable ring 16 - descriptor ring */ 2922 bcmgenet_enable_dma(priv, dma_ctrl); 2923 2924 /* HFB init */ 2925 bcmgenet_hfb_init(priv); 2926 2927 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED, 2928 dev->name, priv); 2929 if (ret < 0) { 2930 netdev_err(dev, "can't request IRQ %d\n", priv->irq0); 2931 goto err_fini_dma; 2932 } 2933 2934 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED, 2935 dev->name, priv); 2936 if (ret < 0) { 2937 netdev_err(dev, "can't request IRQ %d\n", priv->irq1); 2938 goto err_irq0; 2939 } 2940 2941 ret = bcmgenet_mii_probe(dev); 2942 if (ret) { 2943 netdev_err(dev, "failed to connect to PHY\n"); 2944 goto err_irq1; 2945 } 2946 2947 bcmgenet_netif_start(dev); 2948 2949 netif_tx_start_all_queues(dev); 2950 2951 return 0; 2952 2953 err_irq1: 2954 free_irq(priv->irq1, priv); 2955 err_irq0: 2956 free_irq(priv->irq0, priv); 2957 err_fini_dma: 2958 bcmgenet_dma_teardown(priv); 2959 bcmgenet_fini_dma(priv); 2960 err_clk_disable: 2961 if (priv->internal_phy) 2962 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 2963 clk_disable_unprepare(priv->clk); 2964 return ret; 2965 } 2966 2967 static void bcmgenet_netif_stop(struct net_device *dev) 2968 { 2969 struct bcmgenet_priv *priv = netdev_priv(dev); 2970 2971 bcmgenet_disable_tx_napi(priv); 2972 netif_tx_disable(dev); 2973 2974 /* Disable MAC receive */ 2975 umac_enable_set(priv, CMD_RX_EN, false); 2976 2977 bcmgenet_dma_teardown(priv); 2978 2979 /* Disable MAC transmit. TX DMA disabled must be done before this */ 2980 umac_enable_set(priv, CMD_TX_EN, false); 2981 2982 phy_stop(dev->phydev); 2983 bcmgenet_disable_rx_napi(priv); 2984 bcmgenet_intr_disable(priv); 2985 2986 /* Wait for pending work items to complete. Since interrupts are 2987 * disabled no new work will be scheduled. 2988 */ 2989 cancel_work_sync(&priv->bcmgenet_irq_work); 2990 2991 priv->old_link = -1; 2992 priv->old_speed = -1; 2993 priv->old_duplex = -1; 2994 priv->old_pause = -1; 2995 2996 /* tx reclaim */ 2997 bcmgenet_tx_reclaim_all(dev); 2998 bcmgenet_fini_dma(priv); 2999 } 3000 3001 static int bcmgenet_close(struct net_device *dev) 3002 { 3003 struct bcmgenet_priv *priv = netdev_priv(dev); 3004 int ret = 0; 3005 3006 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n"); 3007 3008 bcmgenet_netif_stop(dev); 3009 3010 /* Really kill the PHY state machine and disconnect from it */ 3011 phy_disconnect(dev->phydev); 3012 3013 free_irq(priv->irq0, priv); 3014 free_irq(priv->irq1, priv); 3015 3016 if (priv->internal_phy) 3017 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3018 3019 clk_disable_unprepare(priv->clk); 3020 3021 return ret; 3022 } 3023 3024 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring) 3025 { 3026 struct bcmgenet_priv *priv = ring->priv; 3027 u32 p_index, c_index, intsts, intmsk; 3028 struct netdev_queue *txq; 3029 unsigned int free_bds; 3030 bool txq_stopped; 3031 3032 if (!netif_msg_tx_err(priv)) 3033 return; 3034 3035 txq = netdev_get_tx_queue(priv->dev, ring->queue); 3036 3037 spin_lock(&ring->lock); 3038 if (ring->index == DESC_INDEX) { 3039 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 3040 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE; 3041 } else { 3042 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 3043 intmsk = 1 << ring->index; 3044 } 3045 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX); 3046 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX); 3047 txq_stopped = netif_tx_queue_stopped(txq); 3048 free_bds = ring->free_bds; 3049 spin_unlock(&ring->lock); 3050 3051 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n" 3052 "TX queue status: %s, interrupts: %s\n" 3053 "(sw)free_bds: %d (sw)size: %d\n" 3054 "(sw)p_index: %d (hw)p_index: %d\n" 3055 "(sw)c_index: %d (hw)c_index: %d\n" 3056 "(sw)clean_p: %d (sw)write_p: %d\n" 3057 "(sw)cb_ptr: %d (sw)end_ptr: %d\n", 3058 ring->index, ring->queue, 3059 txq_stopped ? "stopped" : "active", 3060 intsts & intmsk ? "enabled" : "disabled", 3061 free_bds, ring->size, 3062 ring->prod_index, p_index & DMA_P_INDEX_MASK, 3063 ring->c_index, c_index & DMA_C_INDEX_MASK, 3064 ring->clean_ptr, ring->write_ptr, 3065 ring->cb_ptr, ring->end_ptr); 3066 } 3067 3068 static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue) 3069 { 3070 struct bcmgenet_priv *priv = netdev_priv(dev); 3071 u32 int0_enable = 0; 3072 u32 int1_enable = 0; 3073 unsigned int q; 3074 3075 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n"); 3076 3077 for (q = 0; q < priv->hw_params->tx_queues; q++) 3078 bcmgenet_dump_tx_queue(&priv->tx_rings[q]); 3079 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]); 3080 3081 bcmgenet_tx_reclaim_all(dev); 3082 3083 for (q = 0; q < priv->hw_params->tx_queues; q++) 3084 int1_enable |= (1 << q); 3085 3086 int0_enable = UMAC_IRQ_TXDMA_DONE; 3087 3088 /* Re-enable TX interrupts if disabled */ 3089 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 3090 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); 3091 3092 netif_trans_update(dev); 3093 3094 dev->stats.tx_errors++; 3095 3096 netif_tx_wake_all_queues(dev); 3097 } 3098 3099 #define MAX_MDF_FILTER 17 3100 3101 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv, 3102 unsigned char *addr, 3103 int *i) 3104 { 3105 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1], 3106 UMAC_MDF_ADDR + (*i * 4)); 3107 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 | 3108 addr[4] << 8 | addr[5], 3109 UMAC_MDF_ADDR + ((*i + 1) * 4)); 3110 *i += 2; 3111 } 3112 3113 static void bcmgenet_set_rx_mode(struct net_device *dev) 3114 { 3115 struct bcmgenet_priv *priv = netdev_priv(dev); 3116 struct netdev_hw_addr *ha; 3117 int i, nfilter; 3118 u32 reg; 3119 3120 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags); 3121 3122 /* Number of filters needed */ 3123 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2; 3124 3125 /* 3126 * Turn on promicuous mode for three scenarios 3127 * 1. IFF_PROMISC flag is set 3128 * 2. IFF_ALLMULTI flag is set 3129 * 3. The number of filters needed exceeds the number filters 3130 * supported by the hardware. 3131 */ 3132 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 3133 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) || 3134 (nfilter > MAX_MDF_FILTER)) { 3135 reg |= CMD_PROMISC; 3136 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3137 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL); 3138 return; 3139 } else { 3140 reg &= ~CMD_PROMISC; 3141 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3142 } 3143 3144 /* update MDF filter */ 3145 i = 0; 3146 /* Broadcast */ 3147 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i); 3148 /* my own address.*/ 3149 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i); 3150 3151 /* Unicast */ 3152 netdev_for_each_uc_addr(ha, dev) 3153 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3154 3155 /* Multicast */ 3156 netdev_for_each_mc_addr(ha, dev) 3157 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3158 3159 /* Enable filters */ 3160 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter); 3161 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL); 3162 } 3163 3164 /* Set the hardware MAC address. */ 3165 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p) 3166 { 3167 struct sockaddr *addr = p; 3168 3169 /* Setting the MAC address at the hardware level is not possible 3170 * without disabling the UniMAC RX/TX enable bits. 3171 */ 3172 if (netif_running(dev)) 3173 return -EBUSY; 3174 3175 ether_addr_copy(dev->dev_addr, addr->sa_data); 3176 3177 return 0; 3178 } 3179 3180 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev) 3181 { 3182 struct bcmgenet_priv *priv = netdev_priv(dev); 3183 unsigned long tx_bytes = 0, tx_packets = 0; 3184 unsigned long rx_bytes = 0, rx_packets = 0; 3185 unsigned long rx_errors = 0, rx_dropped = 0; 3186 struct bcmgenet_tx_ring *tx_ring; 3187 struct bcmgenet_rx_ring *rx_ring; 3188 unsigned int q; 3189 3190 for (q = 0; q < priv->hw_params->tx_queues; q++) { 3191 tx_ring = &priv->tx_rings[q]; 3192 tx_bytes += tx_ring->bytes; 3193 tx_packets += tx_ring->packets; 3194 } 3195 tx_ring = &priv->tx_rings[DESC_INDEX]; 3196 tx_bytes += tx_ring->bytes; 3197 tx_packets += tx_ring->packets; 3198 3199 for (q = 0; q < priv->hw_params->rx_queues; q++) { 3200 rx_ring = &priv->rx_rings[q]; 3201 3202 rx_bytes += rx_ring->bytes; 3203 rx_packets += rx_ring->packets; 3204 rx_errors += rx_ring->errors; 3205 rx_dropped += rx_ring->dropped; 3206 } 3207 rx_ring = &priv->rx_rings[DESC_INDEX]; 3208 rx_bytes += rx_ring->bytes; 3209 rx_packets += rx_ring->packets; 3210 rx_errors += rx_ring->errors; 3211 rx_dropped += rx_ring->dropped; 3212 3213 dev->stats.tx_bytes = tx_bytes; 3214 dev->stats.tx_packets = tx_packets; 3215 dev->stats.rx_bytes = rx_bytes; 3216 dev->stats.rx_packets = rx_packets; 3217 dev->stats.rx_errors = rx_errors; 3218 dev->stats.rx_missed_errors = rx_errors; 3219 return &dev->stats; 3220 } 3221 3222 static const struct net_device_ops bcmgenet_netdev_ops = { 3223 .ndo_open = bcmgenet_open, 3224 .ndo_stop = bcmgenet_close, 3225 .ndo_start_xmit = bcmgenet_xmit, 3226 .ndo_tx_timeout = bcmgenet_timeout, 3227 .ndo_set_rx_mode = bcmgenet_set_rx_mode, 3228 .ndo_set_mac_address = bcmgenet_set_mac_addr, 3229 .ndo_do_ioctl = phy_do_ioctl_running, 3230 .ndo_set_features = bcmgenet_set_features, 3231 #ifdef CONFIG_NET_POLL_CONTROLLER 3232 .ndo_poll_controller = bcmgenet_poll_controller, 3233 #endif 3234 .ndo_get_stats = bcmgenet_get_stats, 3235 }; 3236 3237 /* Array of GENET hardware parameters/characteristics */ 3238 static struct bcmgenet_hw_params bcmgenet_hw_params[] = { 3239 [GENET_V1] = { 3240 .tx_queues = 0, 3241 .tx_bds_per_q = 0, 3242 .rx_queues = 0, 3243 .rx_bds_per_q = 0, 3244 .bp_in_en_shift = 16, 3245 .bp_in_mask = 0xffff, 3246 .hfb_filter_cnt = 16, 3247 .qtag_mask = 0x1F, 3248 .hfb_offset = 0x1000, 3249 .rdma_offset = 0x2000, 3250 .tdma_offset = 0x3000, 3251 .words_per_bd = 2, 3252 }, 3253 [GENET_V2] = { 3254 .tx_queues = 4, 3255 .tx_bds_per_q = 32, 3256 .rx_queues = 0, 3257 .rx_bds_per_q = 0, 3258 .bp_in_en_shift = 16, 3259 .bp_in_mask = 0xffff, 3260 .hfb_filter_cnt = 16, 3261 .qtag_mask = 0x1F, 3262 .tbuf_offset = 0x0600, 3263 .hfb_offset = 0x1000, 3264 .hfb_reg_offset = 0x2000, 3265 .rdma_offset = 0x3000, 3266 .tdma_offset = 0x4000, 3267 .words_per_bd = 2, 3268 .flags = GENET_HAS_EXT, 3269 }, 3270 [GENET_V3] = { 3271 .tx_queues = 4, 3272 .tx_bds_per_q = 32, 3273 .rx_queues = 0, 3274 .rx_bds_per_q = 0, 3275 .bp_in_en_shift = 17, 3276 .bp_in_mask = 0x1ffff, 3277 .hfb_filter_cnt = 48, 3278 .hfb_filter_size = 128, 3279 .qtag_mask = 0x3F, 3280 .tbuf_offset = 0x0600, 3281 .hfb_offset = 0x8000, 3282 .hfb_reg_offset = 0xfc00, 3283 .rdma_offset = 0x10000, 3284 .tdma_offset = 0x11000, 3285 .words_per_bd = 2, 3286 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR | 3287 GENET_HAS_MOCA_LINK_DET, 3288 }, 3289 [GENET_V4] = { 3290 .tx_queues = 4, 3291 .tx_bds_per_q = 32, 3292 .rx_queues = 0, 3293 .rx_bds_per_q = 0, 3294 .bp_in_en_shift = 17, 3295 .bp_in_mask = 0x1ffff, 3296 .hfb_filter_cnt = 48, 3297 .hfb_filter_size = 128, 3298 .qtag_mask = 0x3F, 3299 .tbuf_offset = 0x0600, 3300 .hfb_offset = 0x8000, 3301 .hfb_reg_offset = 0xfc00, 3302 .rdma_offset = 0x2000, 3303 .tdma_offset = 0x4000, 3304 .words_per_bd = 3, 3305 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3306 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3307 }, 3308 [GENET_V5] = { 3309 .tx_queues = 4, 3310 .tx_bds_per_q = 32, 3311 .rx_queues = 0, 3312 .rx_bds_per_q = 0, 3313 .bp_in_en_shift = 17, 3314 .bp_in_mask = 0x1ffff, 3315 .hfb_filter_cnt = 48, 3316 .hfb_filter_size = 128, 3317 .qtag_mask = 0x3F, 3318 .tbuf_offset = 0x0600, 3319 .hfb_offset = 0x8000, 3320 .hfb_reg_offset = 0xfc00, 3321 .rdma_offset = 0x2000, 3322 .tdma_offset = 0x4000, 3323 .words_per_bd = 3, 3324 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3325 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3326 }, 3327 }; 3328 3329 /* Infer hardware parameters from the detected GENET version */ 3330 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv) 3331 { 3332 struct bcmgenet_hw_params *params; 3333 u32 reg; 3334 u8 major; 3335 u16 gphy_rev; 3336 3337 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) { 3338 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3339 genet_dma_ring_regs = genet_dma_ring_regs_v4; 3340 } else if (GENET_IS_V3(priv)) { 3341 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3342 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3343 } else if (GENET_IS_V2(priv)) { 3344 bcmgenet_dma_regs = bcmgenet_dma_regs_v2; 3345 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3346 } else if (GENET_IS_V1(priv)) { 3347 bcmgenet_dma_regs = bcmgenet_dma_regs_v1; 3348 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3349 } 3350 3351 /* enum genet_version starts at 1 */ 3352 priv->hw_params = &bcmgenet_hw_params[priv->version]; 3353 params = priv->hw_params; 3354 3355 /* Read GENET HW version */ 3356 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL); 3357 major = (reg >> 24 & 0x0f); 3358 if (major == 6) 3359 major = 5; 3360 else if (major == 5) 3361 major = 4; 3362 else if (major == 0) 3363 major = 1; 3364 if (major != priv->version) { 3365 dev_err(&priv->pdev->dev, 3366 "GENET version mismatch, got: %d, configured for: %d\n", 3367 major, priv->version); 3368 } 3369 3370 /* Print the GENET core version */ 3371 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT, 3372 major, (reg >> 16) & 0x0f, reg & 0xffff); 3373 3374 /* Store the integrated PHY revision for the MDIO probing function 3375 * to pass this information to the PHY driver. The PHY driver expects 3376 * to find the PHY major revision in bits 15:8 while the GENET register 3377 * stores that information in bits 7:0, account for that. 3378 * 3379 * On newer chips, starting with PHY revision G0, a new scheme is 3380 * deployed similar to the Starfighter 2 switch with GPHY major 3381 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0 3382 * is reserved as well as special value 0x01ff, we have a small 3383 * heuristic to check for the new GPHY revision and re-arrange things 3384 * so the GPHY driver is happy. 3385 */ 3386 gphy_rev = reg & 0xffff; 3387 3388 if (GENET_IS_V5(priv)) { 3389 /* The EPHY revision should come from the MDIO registers of 3390 * the PHY not from GENET. 3391 */ 3392 if (gphy_rev != 0) { 3393 pr_warn("GENET is reporting EPHY revision: 0x%04x\n", 3394 gphy_rev); 3395 } 3396 /* This is reserved so should require special treatment */ 3397 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) { 3398 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev); 3399 return; 3400 /* This is the good old scheme, just GPHY major, no minor nor patch */ 3401 } else if ((gphy_rev & 0xf0) != 0) { 3402 priv->gphy_rev = gphy_rev << 8; 3403 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */ 3404 } else if ((gphy_rev & 0xff00) != 0) { 3405 priv->gphy_rev = gphy_rev; 3406 } 3407 3408 #ifdef CONFIG_PHYS_ADDR_T_64BIT 3409 if (!(params->flags & GENET_HAS_40BITS)) 3410 pr_warn("GENET does not support 40-bits PA\n"); 3411 #endif 3412 3413 pr_debug("Configuration for version: %d\n" 3414 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n" 3415 "BP << en: %2d, BP msk: 0x%05x\n" 3416 "HFB count: %2d, QTAQ msk: 0x%05x\n" 3417 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n" 3418 "RDMA: 0x%05x, TDMA: 0x%05x\n" 3419 "Words/BD: %d\n", 3420 priv->version, 3421 params->tx_queues, params->tx_bds_per_q, 3422 params->rx_queues, params->rx_bds_per_q, 3423 params->bp_in_en_shift, params->bp_in_mask, 3424 params->hfb_filter_cnt, params->qtag_mask, 3425 params->tbuf_offset, params->hfb_offset, 3426 params->hfb_reg_offset, 3427 params->rdma_offset, params->tdma_offset, 3428 params->words_per_bd); 3429 } 3430 3431 struct bcmgenet_plat_data { 3432 enum bcmgenet_version version; 3433 u32 dma_max_burst_length; 3434 }; 3435 3436 static const struct bcmgenet_plat_data v1_plat_data = { 3437 .version = GENET_V1, 3438 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3439 }; 3440 3441 static const struct bcmgenet_plat_data v2_plat_data = { 3442 .version = GENET_V2, 3443 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3444 }; 3445 3446 static const struct bcmgenet_plat_data v3_plat_data = { 3447 .version = GENET_V3, 3448 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3449 }; 3450 3451 static const struct bcmgenet_plat_data v4_plat_data = { 3452 .version = GENET_V4, 3453 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3454 }; 3455 3456 static const struct bcmgenet_plat_data v5_plat_data = { 3457 .version = GENET_V5, 3458 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3459 }; 3460 3461 static const struct bcmgenet_plat_data bcm2711_plat_data = { 3462 .version = GENET_V5, 3463 .dma_max_burst_length = 0x08, 3464 }; 3465 3466 static const struct of_device_id bcmgenet_match[] = { 3467 { .compatible = "brcm,genet-v1", .data = &v1_plat_data }, 3468 { .compatible = "brcm,genet-v2", .data = &v2_plat_data }, 3469 { .compatible = "brcm,genet-v3", .data = &v3_plat_data }, 3470 { .compatible = "brcm,genet-v4", .data = &v4_plat_data }, 3471 { .compatible = "brcm,genet-v5", .data = &v5_plat_data }, 3472 { .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data }, 3473 { }, 3474 }; 3475 MODULE_DEVICE_TABLE(of, bcmgenet_match); 3476 3477 static int bcmgenet_probe(struct platform_device *pdev) 3478 { 3479 struct bcmgenet_platform_data *pd = pdev->dev.platform_data; 3480 struct device_node *dn = pdev->dev.of_node; 3481 const struct of_device_id *of_id = NULL; 3482 const struct bcmgenet_plat_data *pdata; 3483 struct bcmgenet_priv *priv; 3484 struct net_device *dev; 3485 unsigned int i; 3486 int err = -EIO; 3487 3488 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */ 3489 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 3490 GENET_MAX_MQ_CNT + 1); 3491 if (!dev) { 3492 dev_err(&pdev->dev, "can't allocate net device\n"); 3493 return -ENOMEM; 3494 } 3495 3496 if (dn) { 3497 of_id = of_match_node(bcmgenet_match, dn); 3498 if (!of_id) 3499 return -EINVAL; 3500 } 3501 3502 priv = netdev_priv(dev); 3503 priv->irq0 = platform_get_irq(pdev, 0); 3504 if (priv->irq0 < 0) { 3505 err = priv->irq0; 3506 goto err; 3507 } 3508 priv->irq1 = platform_get_irq(pdev, 1); 3509 if (priv->irq1 < 0) { 3510 err = priv->irq1; 3511 goto err; 3512 } 3513 priv->wol_irq = platform_get_irq_optional(pdev, 2); 3514 3515 priv->base = devm_platform_ioremap_resource(pdev, 0); 3516 if (IS_ERR(priv->base)) { 3517 err = PTR_ERR(priv->base); 3518 goto err; 3519 } 3520 3521 spin_lock_init(&priv->lock); 3522 3523 SET_NETDEV_DEV(dev, &pdev->dev); 3524 dev_set_drvdata(&pdev->dev, dev); 3525 dev->watchdog_timeo = 2 * HZ; 3526 dev->ethtool_ops = &bcmgenet_ethtool_ops; 3527 dev->netdev_ops = &bcmgenet_netdev_ops; 3528 3529 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT); 3530 3531 /* Set default features */ 3532 dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_CSUM | 3533 NETIF_F_RXCSUM; 3534 dev->hw_features |= dev->features; 3535 dev->vlan_features |= dev->features; 3536 3537 /* Request the WOL interrupt and advertise suspend if available */ 3538 priv->wol_irq_disabled = true; 3539 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0, 3540 dev->name, priv); 3541 if (!err) 3542 device_set_wakeup_capable(&pdev->dev, 1); 3543 3544 /* Set the needed headroom to account for any possible 3545 * features enabling/disabling at runtime 3546 */ 3547 dev->needed_headroom += 64; 3548 3549 netdev_boot_setup_check(dev); 3550 3551 priv->dev = dev; 3552 priv->pdev = pdev; 3553 3554 pdata = device_get_match_data(&pdev->dev); 3555 if (pdata) { 3556 priv->version = pdata->version; 3557 priv->dma_max_burst_length = pdata->dma_max_burst_length; 3558 } else { 3559 priv->version = pd->genet_version; 3560 priv->dma_max_burst_length = DMA_MAX_BURST_LENGTH; 3561 } 3562 3563 priv->clk = devm_clk_get(&priv->pdev->dev, "enet"); 3564 if (IS_ERR(priv->clk)) { 3565 dev_dbg(&priv->pdev->dev, "failed to get enet clock\n"); 3566 priv->clk = NULL; 3567 } 3568 3569 clk_prepare_enable(priv->clk); 3570 3571 bcmgenet_set_hw_params(priv); 3572 3573 err = -EIO; 3574 if (priv->hw_params->flags & GENET_HAS_40BITS) 3575 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); 3576 if (err) 3577 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3578 if (err) 3579 goto err; 3580 3581 /* Mii wait queue */ 3582 init_waitqueue_head(&priv->wq); 3583 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */ 3584 priv->rx_buf_len = RX_BUF_LENGTH; 3585 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task); 3586 3587 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol"); 3588 if (IS_ERR(priv->clk_wol)) { 3589 dev_dbg(&priv->pdev->dev, "failed to get enet-wol clock\n"); 3590 priv->clk_wol = NULL; 3591 } 3592 3593 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee"); 3594 if (IS_ERR(priv->clk_eee)) { 3595 dev_dbg(&priv->pdev->dev, "failed to get enet-eee clock\n"); 3596 priv->clk_eee = NULL; 3597 } 3598 3599 /* If this is an internal GPHY, power it on now, before UniMAC is 3600 * brought out of reset as absolutely no UniMAC activity is allowed 3601 */ 3602 if (device_get_phy_mode(&pdev->dev) == PHY_INTERFACE_MODE_INTERNAL) 3603 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 3604 3605 if ((pd) && (!IS_ERR_OR_NULL(pd->mac_address))) 3606 ether_addr_copy(dev->dev_addr, pd->mac_address); 3607 else 3608 if (!device_get_mac_address(&pdev->dev, dev->dev_addr, ETH_ALEN)) 3609 if (has_acpi_companion(&pdev->dev)) 3610 bcmgenet_get_hw_addr(priv, dev->dev_addr); 3611 3612 if (!is_valid_ether_addr(dev->dev_addr)) { 3613 dev_warn(&pdev->dev, "using random Ethernet MAC\n"); 3614 eth_hw_addr_random(dev); 3615 } 3616 3617 reset_umac(priv); 3618 3619 err = bcmgenet_mii_init(dev); 3620 if (err) 3621 goto err_clk_disable; 3622 3623 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues 3624 * just the ring 16 descriptor based TX 3625 */ 3626 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1); 3627 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1); 3628 3629 /* Set default coalescing parameters */ 3630 for (i = 0; i < priv->hw_params->rx_queues; i++) 3631 priv->rx_rings[i].rx_max_coalesced_frames = 1; 3632 priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1; 3633 3634 /* libphy will determine the link state */ 3635 netif_carrier_off(dev); 3636 3637 /* Turn off the main clock, WOL clock is handled separately */ 3638 clk_disable_unprepare(priv->clk); 3639 3640 err = register_netdev(dev); 3641 if (err) 3642 goto err; 3643 3644 return err; 3645 3646 err_clk_disable: 3647 clk_disable_unprepare(priv->clk); 3648 err: 3649 free_netdev(dev); 3650 return err; 3651 } 3652 3653 static int bcmgenet_remove(struct platform_device *pdev) 3654 { 3655 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev); 3656 3657 dev_set_drvdata(&pdev->dev, NULL); 3658 unregister_netdev(priv->dev); 3659 bcmgenet_mii_exit(priv->dev); 3660 free_netdev(priv->dev); 3661 3662 return 0; 3663 } 3664 3665 static void bcmgenet_shutdown(struct platform_device *pdev) 3666 { 3667 bcmgenet_remove(pdev); 3668 } 3669 3670 #ifdef CONFIG_PM_SLEEP 3671 static int bcmgenet_resume(struct device *d) 3672 { 3673 struct net_device *dev = dev_get_drvdata(d); 3674 struct bcmgenet_priv *priv = netdev_priv(dev); 3675 unsigned long dma_ctrl; 3676 int ret; 3677 u32 reg; 3678 3679 if (!netif_running(dev)) 3680 return 0; 3681 3682 /* Turn on the clock */ 3683 ret = clk_prepare_enable(priv->clk); 3684 if (ret) 3685 return ret; 3686 3687 /* If this is an internal GPHY, power it back on now, before UniMAC is 3688 * brought out of reset as absolutely no UniMAC activity is allowed 3689 */ 3690 if (priv->internal_phy) 3691 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 3692 3693 bcmgenet_umac_reset(priv); 3694 3695 init_umac(priv); 3696 3697 /* From WOL-enabled suspend, switch to regular clock */ 3698 if (priv->wolopts) 3699 clk_disable_unprepare(priv->clk_wol); 3700 3701 phy_init_hw(dev->phydev); 3702 3703 /* Speed settings must be restored */ 3704 genphy_config_aneg(dev->phydev); 3705 bcmgenet_mii_config(priv->dev, false); 3706 3707 /* Restore enabled features */ 3708 bcmgenet_set_features(dev, dev->features); 3709 3710 bcmgenet_set_hw_addr(priv, dev->dev_addr); 3711 3712 if (priv->internal_phy) { 3713 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 3714 reg |= EXT_ENERGY_DET_MASK; 3715 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 3716 } 3717 3718 if (priv->wolopts) 3719 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC); 3720 3721 /* Disable RX/TX DMA and flush TX queues */ 3722 dma_ctrl = bcmgenet_dma_disable(priv); 3723 3724 /* Reinitialize TDMA and RDMA and SW housekeeping */ 3725 ret = bcmgenet_init_dma(priv); 3726 if (ret) { 3727 netdev_err(dev, "failed to initialize DMA\n"); 3728 goto out_clk_disable; 3729 } 3730 3731 /* Always enable ring 16 - descriptor ring */ 3732 bcmgenet_enable_dma(priv, dma_ctrl); 3733 3734 if (!device_may_wakeup(d)) 3735 phy_resume(dev->phydev); 3736 3737 if (priv->eee.eee_enabled) 3738 bcmgenet_eee_enable_set(dev, true); 3739 3740 bcmgenet_netif_start(dev); 3741 3742 netif_device_attach(dev); 3743 3744 return 0; 3745 3746 out_clk_disable: 3747 if (priv->internal_phy) 3748 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3749 clk_disable_unprepare(priv->clk); 3750 return ret; 3751 } 3752 3753 static int bcmgenet_suspend(struct device *d) 3754 { 3755 struct net_device *dev = dev_get_drvdata(d); 3756 struct bcmgenet_priv *priv = netdev_priv(dev); 3757 int ret = 0; 3758 3759 if (!netif_running(dev)) 3760 return 0; 3761 3762 netif_device_detach(dev); 3763 3764 bcmgenet_netif_stop(dev); 3765 3766 if (!device_may_wakeup(d)) 3767 phy_suspend(dev->phydev); 3768 3769 /* Prepare the device for Wake-on-LAN and switch to the slow clock */ 3770 if (device_may_wakeup(d) && priv->wolopts) { 3771 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC); 3772 clk_prepare_enable(priv->clk_wol); 3773 } else if (priv->internal_phy) { 3774 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3775 } 3776 3777 /* Turn off the clocks */ 3778 clk_disable_unprepare(priv->clk); 3779 3780 if (ret) 3781 bcmgenet_resume(d); 3782 3783 return ret; 3784 } 3785 #endif /* CONFIG_PM_SLEEP */ 3786 3787 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume); 3788 3789 static const struct acpi_device_id genet_acpi_match[] = { 3790 { "BCM6E4E", (kernel_ulong_t)&bcm2711_plat_data }, 3791 { }, 3792 }; 3793 MODULE_DEVICE_TABLE(acpi, genet_acpi_match); 3794 3795 static struct platform_driver bcmgenet_driver = { 3796 .probe = bcmgenet_probe, 3797 .remove = bcmgenet_remove, 3798 .shutdown = bcmgenet_shutdown, 3799 .driver = { 3800 .name = "bcmgenet", 3801 .of_match_table = bcmgenet_match, 3802 .pm = &bcmgenet_pm_ops, 3803 .acpi_match_table = ACPI_PTR(genet_acpi_match), 3804 }, 3805 }; 3806 module_platform_driver(bcmgenet_driver); 3807 3808 MODULE_AUTHOR("Broadcom Corporation"); 3809 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver"); 3810 MODULE_ALIAS("platform:bcmgenet"); 3811 MODULE_LICENSE("GPL"); 3812