1ae5c42f0SMichael Chan /* Broadcom NetXtreme-C/E network driver. 2ae5c42f0SMichael Chan * 3ae5c42f0SMichael Chan * Copyright (c) 2021 Broadcom Inc. 4ae5c42f0SMichael Chan * 5ae5c42f0SMichael Chan * This program is free software; you can redistribute it and/or modify 6ae5c42f0SMichael Chan * it under the terms of the GNU General Public License as published by 7ae5c42f0SMichael Chan * the Free Software Foundation. 8ae5c42f0SMichael Chan */ 9ae5c42f0SMichael Chan 10ae5c42f0SMichael Chan #ifndef BNXT_PTP_H 11ae5c42f0SMichael Chan #define BNXT_PTP_H 12ae5c42f0SMichael Chan 13228ea8c1SEdwin Peer #include <linux/ptp_clock_kernel.h> 14228ea8c1SEdwin Peer #include <linux/timecounter.h> 15228ea8c1SEdwin Peer 1692529df7SMichael Chan #define BNXT_PTP_GRC_WIN 6 1792529df7SMichael Chan #define BNXT_PTP_GRC_WIN_BASE 0x6000 18118612d5SMichael Chan 19118612d5SMichael Chan #define BNXT_MAX_PHC_DRIFT 31000000 20118612d5SMichael Chan #define BNXT_LO_TIMER_MASK 0x0000ffffffffUL 21118612d5SMichael Chan #define BNXT_HI_TIMER_MASK 0xffff00000000UL 22118612d5SMichael Chan 23118612d5SMichael Chan #define BNXT_PTP_QTS_TIMEOUT 1000 24118612d5SMichael Chan #define BNXT_PTP_QTS_TX_ENABLES (PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID | \ 259e266807SMichael Chan PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT | \ 269e266807SMichael Chan PORT_TS_QUERY_REQ_ENABLES_PTP_HDR_OFFSET) 27118612d5SMichael Chan 28caf3eedbSPavan Chebbi struct pps_pin { 299e518f25SPavan Chebbi u8 event; 30caf3eedbSPavan Chebbi u8 usage; 319e518f25SPavan Chebbi u8 state; 32caf3eedbSPavan Chebbi }; 33caf3eedbSPavan Chebbi 349e518f25SPavan Chebbi #define TSIO_PIN_VALID(pin) ((pin) < (BNXT_MAX_TSIO_PINS)) 359e518f25SPavan Chebbi 36099fdedaSPavan Chebbi #define EVENT_DATA2_PPS_EVENT_TYPE(data2) \ 37099fdedaSPavan Chebbi ((data2) & ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE) 38099fdedaSPavan Chebbi 39099fdedaSPavan Chebbi #define EVENT_DATA2_PPS_PIN_NUM(data2) \ 40099fdedaSPavan Chebbi (((data2) & \ 41099fdedaSPavan Chebbi ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK) >>\ 42099fdedaSPavan Chebbi ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT) 43099fdedaSPavan Chebbi 44099fdedaSPavan Chebbi #define BNXT_DATA2_UPPER_MSK \ 45099fdedaSPavan Chebbi ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK 46099fdedaSPavan Chebbi 47099fdedaSPavan Chebbi #define BNXT_DATA2_UPPER_SFT \ 48099fdedaSPavan Chebbi (32 - \ 49099fdedaSPavan Chebbi ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT) 50099fdedaSPavan Chebbi 51099fdedaSPavan Chebbi #define BNXT_DATA1_LOWER_MSK \ 52099fdedaSPavan Chebbi ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK 53099fdedaSPavan Chebbi 54099fdedaSPavan Chebbi #define BNXT_DATA1_LOWER_SFT \ 55099fdedaSPavan Chebbi ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT 56099fdedaSPavan Chebbi 57099fdedaSPavan Chebbi #define EVENT_PPS_TS(data2, data1) \ 58099fdedaSPavan Chebbi (((u64)((data2) & BNXT_DATA2_UPPER_MSK) << BNXT_DATA2_UPPER_SFT) |\ 59099fdedaSPavan Chebbi (((data1) & BNXT_DATA1_LOWER_MSK) >> BNXT_DATA1_LOWER_SFT)) 60099fdedaSPavan Chebbi 61caf3eedbSPavan Chebbi #define BNXT_PPS_PIN_DISABLE 0 62caf3eedbSPavan Chebbi #define BNXT_PPS_PIN_ENABLE 1 63caf3eedbSPavan Chebbi #define BNXT_PPS_PIN_NONE 0 64caf3eedbSPavan Chebbi #define BNXT_PPS_PIN_PPS_IN 1 65caf3eedbSPavan Chebbi #define BNXT_PPS_PIN_PPS_OUT 2 66caf3eedbSPavan Chebbi #define BNXT_PPS_PIN_SYNC_IN 3 67caf3eedbSPavan Chebbi #define BNXT_PPS_PIN_SYNC_OUT 4 68caf3eedbSPavan Chebbi 69caf3eedbSPavan Chebbi #define BNXT_PPS_EVENT_INTERNAL 1 70caf3eedbSPavan Chebbi #define BNXT_PPS_EVENT_EXTERNAL 2 71caf3eedbSPavan Chebbi 72caf3eedbSPavan Chebbi struct bnxt_pps { 73caf3eedbSPavan Chebbi u8 num_pins; 74caf3eedbSPavan Chebbi #define BNXT_MAX_TSIO_PINS 4 75caf3eedbSPavan Chebbi struct pps_pin pins[BNXT_MAX_TSIO_PINS]; 76caf3eedbSPavan Chebbi }; 77caf3eedbSPavan Chebbi 78ae5c42f0SMichael Chan struct bnxt_ptp_cfg { 79ae5c42f0SMichael Chan struct ptp_clock_info ptp_info; 80ae5c42f0SMichael Chan struct ptp_clock *ptp_clock; 81ae5c42f0SMichael Chan struct cyclecounter cc; 82ae5c42f0SMichael Chan struct timecounter tc; 83caf3eedbSPavan Chebbi struct bnxt_pps pps_info; 84ae5c42f0SMichael Chan /* serialize timecounter access */ 85ae5c42f0SMichael Chan spinlock_t ptp_lock; 86ae5c42f0SMichael Chan struct sk_buff *tx_skb; 87ae5c42f0SMichael Chan u64 current_time; 88ae5c42f0SMichael Chan u64 old_time; 89ae5c42f0SMichael Chan unsigned long next_period; 9089bc7f45SMichael Chan unsigned long next_overflow_check; 9189bc7f45SMichael Chan /* 48-bit PHC overflows in 78 hours. Check overflow every 19 hours. */ 9289bc7f45SMichael Chan #define BNXT_PHC_OVERFLOW_PERIOD (19 * 3600 * HZ) 9389bc7f45SMichael Chan 94ae5c42f0SMichael Chan u16 tx_seqid; 959e266807SMichael Chan u16 tx_hdr_off; 96ae5c42f0SMichael Chan struct bnxt *bp; 97ae5c42f0SMichael Chan atomic_t tx_avail; 98ae5c42f0SMichael Chan #define BNXT_MAX_TX_TS 1 99ae5c42f0SMichael Chan u16 rxctl; 100ae5c42f0SMichael Chan #define BNXT_PTP_MSG_SYNC (1 << 0) 101ae5c42f0SMichael Chan #define BNXT_PTP_MSG_DELAY_REQ (1 << 1) 102ae5c42f0SMichael Chan #define BNXT_PTP_MSG_PDELAY_REQ (1 << 2) 103ae5c42f0SMichael Chan #define BNXT_PTP_MSG_PDELAY_RESP (1 << 3) 104ae5c42f0SMichael Chan #define BNXT_PTP_MSG_FOLLOW_UP (1 << 8) 105ae5c42f0SMichael Chan #define BNXT_PTP_MSG_DELAY_RESP (1 << 9) 106ae5c42f0SMichael Chan #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP (1 << 10) 107ae5c42f0SMichael Chan #define BNXT_PTP_MSG_ANNOUNCE (1 << 11) 108ae5c42f0SMichael Chan #define BNXT_PTP_MSG_SIGNALING (1 << 12) 109ae5c42f0SMichael Chan #define BNXT_PTP_MSG_MANAGEMENT (1 << 13) 110ae5c42f0SMichael Chan #define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \ 111ae5c42f0SMichael Chan BNXT_PTP_MSG_DELAY_REQ | \ 112ae5c42f0SMichael Chan BNXT_PTP_MSG_PDELAY_REQ | \ 113ae5c42f0SMichael Chan BNXT_PTP_MSG_PDELAY_RESP) 114ae5c42f0SMichael Chan u8 tx_tstamp_en:1; 115ae5c42f0SMichael Chan int rx_filter; 116ae5c42f0SMichael Chan 117ae5c42f0SMichael Chan u32 refclk_regs[2]; 118ae5c42f0SMichael Chan u32 refclk_mapped_regs[2]; 119ae5c42f0SMichael Chan }; 120118612d5SMichael Chan 1217f5515d1SPavan Chebbi #if BITS_PER_LONG == 32 1227f5515d1SPavan Chebbi #define BNXT_READ_TIME64(ptp, dst, src) \ 1237f5515d1SPavan Chebbi do { \ 1247f5515d1SPavan Chebbi spin_lock_bh(&(ptp)->ptp_lock); \ 1257f5515d1SPavan Chebbi (dst) = (src); \ 1267f5515d1SPavan Chebbi spin_unlock_bh(&(ptp)->ptp_lock); \ 1277f5515d1SPavan Chebbi } while (0) 1287f5515d1SPavan Chebbi #else 1297f5515d1SPavan Chebbi #define BNXT_READ_TIME64(ptp, dst, src) \ 1307f5515d1SPavan Chebbi ((dst) = READ_ONCE(src)) 1317f5515d1SPavan Chebbi #endif 1327f5515d1SPavan Chebbi 1339e266807SMichael Chan int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off); 134099fdedaSPavan Chebbi void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2); 1359e518f25SPavan Chebbi void bnxt_ptp_reapply_pps(struct bnxt *bp); 136118612d5SMichael Chan int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr); 137118612d5SMichael Chan int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr); 13883bb623cSPavan Chebbi int bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb); 1397f5515d1SPavan Chebbi int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts); 140*24ac1ecdSPavan Chebbi void bnxt_ptp_rtc_timecounter_init(struct bnxt_ptp_cfg *ptp, u64 ns); 141*24ac1ecdSPavan Chebbi int bnxt_ptp_init_rtc(struct bnxt *bp, bool phc_cfg); 142*24ac1ecdSPavan Chebbi int bnxt_ptp_init(struct bnxt *bp, bool phc_cfg); 143118612d5SMichael Chan void bnxt_ptp_clear(struct bnxt *bp); 144ae5c42f0SMichael Chan #endif 145