1ae5c42f0SMichael Chan /* Broadcom NetXtreme-C/E network driver. 2ae5c42f0SMichael Chan * 3ae5c42f0SMichael Chan * Copyright (c) 2021 Broadcom Inc. 4ae5c42f0SMichael Chan * 5ae5c42f0SMichael Chan * This program is free software; you can redistribute it and/or modify 6ae5c42f0SMichael Chan * it under the terms of the GNU General Public License as published by 7ae5c42f0SMichael Chan * the Free Software Foundation. 8ae5c42f0SMichael Chan */ 9ae5c42f0SMichael Chan 10ae5c42f0SMichael Chan #ifndef BNXT_PTP_H 11ae5c42f0SMichael Chan #define BNXT_PTP_H 12ae5c42f0SMichael Chan 13228ea8c1SEdwin Peer #include <linux/ptp_clock_kernel.h> 14228ea8c1SEdwin Peer #include <linux/timecounter.h> 15228ea8c1SEdwin Peer 1692529df7SMichael Chan #define BNXT_PTP_GRC_WIN 6 1792529df7SMichael Chan #define BNXT_PTP_GRC_WIN_BASE 0x6000 18118612d5SMichael Chan 19118612d5SMichael Chan #define BNXT_MAX_PHC_DRIFT 31000000 2085036aeeSPavan Chebbi #define BNXT_CYCLES_SHIFT 23 2185036aeeSPavan Chebbi #define BNXT_DEVCLK_FREQ 1000000 22118612d5SMichael Chan #define BNXT_LO_TIMER_MASK 0x0000ffffffffUL 23118612d5SMichael Chan #define BNXT_HI_TIMER_MASK 0xffff00000000UL 24118612d5SMichael Chan 2560404164SPavan Chebbi #define BNXT_PTP_DFLT_TX_TMO 1000 /* ms */ 26118612d5SMichael Chan #define BNXT_PTP_QTS_TIMEOUT 1000 2738155539SVadim Fedorenko #define BNXT_PTP_QTS_MAX_TMO_US 65535U 28118612d5SMichael Chan #define BNXT_PTP_QTS_TX_ENABLES (PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID | \ 299e266807SMichael Chan PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT | \ 309e266807SMichael Chan PORT_TS_QUERY_REQ_ENABLES_PTP_HDR_OFFSET) 31118612d5SMichael Chan 32caf3eedbSPavan Chebbi struct pps_pin { 339e518f25SPavan Chebbi u8 event; 34caf3eedbSPavan Chebbi u8 usage; 359e518f25SPavan Chebbi u8 state; 36caf3eedbSPavan Chebbi }; 37caf3eedbSPavan Chebbi 38dcf50006SDamien Le Moal #define TSIO_PIN_VALID(pin) ((pin) >= 0 && (pin) < (BNXT_MAX_TSIO_PINS)) 399e518f25SPavan Chebbi 40099fdedaSPavan Chebbi #define EVENT_DATA2_PPS_EVENT_TYPE(data2) \ 41099fdedaSPavan Chebbi ((data2) & ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE) 42099fdedaSPavan Chebbi 43099fdedaSPavan Chebbi #define EVENT_DATA2_PPS_PIN_NUM(data2) \ 44099fdedaSPavan Chebbi (((data2) & \ 45099fdedaSPavan Chebbi ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK) >>\ 46099fdedaSPavan Chebbi ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT) 47099fdedaSPavan Chebbi 48099fdedaSPavan Chebbi #define BNXT_DATA2_UPPER_MSK \ 49099fdedaSPavan Chebbi ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK 50099fdedaSPavan Chebbi 51099fdedaSPavan Chebbi #define BNXT_DATA2_UPPER_SFT \ 52099fdedaSPavan Chebbi (32 - \ 53099fdedaSPavan Chebbi ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT) 54099fdedaSPavan Chebbi 55099fdedaSPavan Chebbi #define BNXT_DATA1_LOWER_MSK \ 56099fdedaSPavan Chebbi ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK 57099fdedaSPavan Chebbi 58099fdedaSPavan Chebbi #define BNXT_DATA1_LOWER_SFT \ 59099fdedaSPavan Chebbi ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT 60099fdedaSPavan Chebbi 61099fdedaSPavan Chebbi #define EVENT_PPS_TS(data2, data1) \ 62099fdedaSPavan Chebbi (((u64)((data2) & BNXT_DATA2_UPPER_MSK) << BNXT_DATA2_UPPER_SFT) |\ 63099fdedaSPavan Chebbi (((data1) & BNXT_DATA1_LOWER_MSK) >> BNXT_DATA1_LOWER_SFT)) 64099fdedaSPavan Chebbi 65caf3eedbSPavan Chebbi #define BNXT_PPS_PIN_DISABLE 0 66caf3eedbSPavan Chebbi #define BNXT_PPS_PIN_ENABLE 1 67caf3eedbSPavan Chebbi #define BNXT_PPS_PIN_NONE 0 68caf3eedbSPavan Chebbi #define BNXT_PPS_PIN_PPS_IN 1 69caf3eedbSPavan Chebbi #define BNXT_PPS_PIN_PPS_OUT 2 70caf3eedbSPavan Chebbi #define BNXT_PPS_PIN_SYNC_IN 3 71caf3eedbSPavan Chebbi #define BNXT_PPS_PIN_SYNC_OUT 4 72caf3eedbSPavan Chebbi 73caf3eedbSPavan Chebbi #define BNXT_PPS_EVENT_INTERNAL 1 74caf3eedbSPavan Chebbi #define BNXT_PPS_EVENT_EXTERNAL 2 75caf3eedbSPavan Chebbi 76caf3eedbSPavan Chebbi struct bnxt_pps { 77caf3eedbSPavan Chebbi u8 num_pins; 78caf3eedbSPavan Chebbi #define BNXT_MAX_TSIO_PINS 4 79caf3eedbSPavan Chebbi struct pps_pin pins[BNXT_MAX_TSIO_PINS]; 80caf3eedbSPavan Chebbi }; 81caf3eedbSPavan Chebbi 82165f8769SVadim Fedorenko struct bnxt_ptp_stats { 83165f8769SVadim Fedorenko u64 ts_pkts; 84165f8769SVadim Fedorenko u64 ts_lost; 85165f8769SVadim Fedorenko atomic64_t ts_err; 86165f8769SVadim Fedorenko }; 87165f8769SVadim Fedorenko 888aa2a79eSPavan Chebbi #define BNXT_MAX_TX_TS 4 898aa2a79eSPavan Chebbi #define NEXT_TXTS(idx) (((idx) + 1) & (BNXT_MAX_TX_TS - 1)) 908aa2a79eSPavan Chebbi 9192595a0cSPavan Chebbi struct bnxt_ptp_tx_req { 9292595a0cSPavan Chebbi struct sk_buff *tx_skb; 9392595a0cSPavan Chebbi u16 tx_seqid; 9492595a0cSPavan Chebbi u16 tx_hdr_off; 9592595a0cSPavan Chebbi unsigned long abs_txts_tmo; 9692595a0cSPavan Chebbi }; 9792595a0cSPavan Chebbi 98ae5c42f0SMichael Chan struct bnxt_ptp_cfg { 99ae5c42f0SMichael Chan struct ptp_clock_info ptp_info; 100ae5c42f0SMichael Chan struct ptp_clock *ptp_clock; 101ae5c42f0SMichael Chan struct cyclecounter cc; 102ae5c42f0SMichael Chan struct timecounter tc; 103caf3eedbSPavan Chebbi struct bnxt_pps pps_info; 104ae5c42f0SMichael Chan /* serialize timecounter access */ 105ae5c42f0SMichael Chan spinlock_t ptp_lock; 1068aa2a79eSPavan Chebbi /* serialize ts tx request queuing */ 1078aa2a79eSPavan Chebbi spinlock_t ptp_tx_lock; 108ae5c42f0SMichael Chan u64 current_time; 109ae5c42f0SMichael Chan u64 old_time; 110ae5c42f0SMichael Chan unsigned long next_period; 11189bc7f45SMichael Chan unsigned long next_overflow_check; 11285036aeeSPavan Chebbi u32 cmult; 11385036aeeSPavan Chebbi /* a 23b shift cyclecounter will overflow in ~36 mins. Check overflow every 18 mins. */ 11485036aeeSPavan Chebbi #define BNXT_PHC_OVERFLOW_PERIOD (18 * 60 * HZ) 11589bc7f45SMichael Chan 1168aa2a79eSPavan Chebbi struct bnxt_ptp_tx_req txts_req[BNXT_MAX_TX_TS]; 11792595a0cSPavan Chebbi 118ae5c42f0SMichael Chan struct bnxt *bp; 119*06033839SPavan Chebbi u32 tx_avail; 120ae5c42f0SMichael Chan u16 rxctl; 121ae5c42f0SMichael Chan #define BNXT_PTP_MSG_SYNC (1 << 0) 122ae5c42f0SMichael Chan #define BNXT_PTP_MSG_DELAY_REQ (1 << 1) 123ae5c42f0SMichael Chan #define BNXT_PTP_MSG_PDELAY_REQ (1 << 2) 124ae5c42f0SMichael Chan #define BNXT_PTP_MSG_PDELAY_RESP (1 << 3) 125ae5c42f0SMichael Chan #define BNXT_PTP_MSG_FOLLOW_UP (1 << 8) 126ae5c42f0SMichael Chan #define BNXT_PTP_MSG_DELAY_RESP (1 << 9) 127ae5c42f0SMichael Chan #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP (1 << 10) 128ae5c42f0SMichael Chan #define BNXT_PTP_MSG_ANNOUNCE (1 << 11) 129ae5c42f0SMichael Chan #define BNXT_PTP_MSG_SIGNALING (1 << 12) 130ae5c42f0SMichael Chan #define BNXT_PTP_MSG_MANAGEMENT (1 << 13) 131ae5c42f0SMichael Chan #define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \ 132ae5c42f0SMichael Chan BNXT_PTP_MSG_DELAY_REQ | \ 133ae5c42f0SMichael Chan BNXT_PTP_MSG_PDELAY_REQ | \ 134ae5c42f0SMichael Chan BNXT_PTP_MSG_PDELAY_RESP) 135ae5c42f0SMichael Chan u8 tx_tstamp_en:1; 136ae5c42f0SMichael Chan int rx_filter; 13711862689SPavan Chebbi u32 tstamp_filters; 138ae5c42f0SMichael Chan 139ae5c42f0SMichael Chan u32 refclk_regs[2]; 140ae5c42f0SMichael Chan u32 refclk_mapped_regs[2]; 14160404164SPavan Chebbi u32 txts_tmo; 1428aa2a79eSPavan Chebbi u16 txts_prod; 1438aa2a79eSPavan Chebbi u16 txts_cons; 144165f8769SVadim Fedorenko 145165f8769SVadim Fedorenko struct bnxt_ptp_stats stats; 146ae5c42f0SMichael Chan }; 147118612d5SMichael Chan 1487f5515d1SPavan Chebbi #if BITS_PER_LONG == 32 1497f5515d1SPavan Chebbi #define BNXT_READ_TIME64(ptp, dst, src) \ 1507f5515d1SPavan Chebbi do { \ 1517f5515d1SPavan Chebbi spin_lock_bh(&(ptp)->ptp_lock); \ 1527f5515d1SPavan Chebbi (dst) = (src); \ 1537f5515d1SPavan Chebbi spin_unlock_bh(&(ptp)->ptp_lock); \ 1547f5515d1SPavan Chebbi } while (0) 1557f5515d1SPavan Chebbi #else 1567f5515d1SPavan Chebbi #define BNXT_READ_TIME64(ptp, dst, src) \ 1577f5515d1SPavan Chebbi ((dst) = READ_ONCE(src)) 1587f5515d1SPavan Chebbi #endif 1597f5515d1SPavan Chebbi 160*06033839SPavan Chebbi #define BNXT_PTP_INC_TX_AVAIL(ptp) \ 161*06033839SPavan Chebbi do { \ 162*06033839SPavan Chebbi spin_lock_bh(&(ptp)->ptp_tx_lock); \ 163*06033839SPavan Chebbi (ptp)->tx_avail++; \ 164*06033839SPavan Chebbi spin_unlock_bh(&(ptp)->ptp_tx_lock); \ 165*06033839SPavan Chebbi } while (0) 166*06033839SPavan Chebbi 1679e266807SMichael Chan int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off); 168e7b0afb6SPavan Chebbi void bnxt_ptp_update_current_time(struct bnxt *bp); 169099fdedaSPavan Chebbi void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2); 17084793a49SPavan Chebbi int bnxt_ptp_cfg_tstamp_filters(struct bnxt *bp); 1719e518f25SPavan Chebbi void bnxt_ptp_reapply_pps(struct bnxt *bp); 172118612d5SMichael Chan int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr); 173118612d5SMichael Chan int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr); 174*06033839SPavan Chebbi int bnxt_ptp_get_txts_prod(struct bnxt_ptp_cfg *ptp, u16 *prod); 1758aa2a79eSPavan Chebbi void bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb, u16 prod); 1767f5515d1SPavan Chebbi int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts); 1771d294b4fSMichael Chan void bnxt_tx_ts_cmp(struct bnxt *bp, struct bnxt_napi *bnapi, 1781d294b4fSMichael Chan struct tx_ts_cmp *tscmp); 17924ac1ecdSPavan Chebbi void bnxt_ptp_rtc_timecounter_init(struct bnxt_ptp_cfg *ptp, u64 ns); 18024ac1ecdSPavan Chebbi int bnxt_ptp_init_rtc(struct bnxt *bp, bool phc_cfg); 18124ac1ecdSPavan Chebbi int bnxt_ptp_init(struct bnxt *bp, bool phc_cfg); 182118612d5SMichael Chan void bnxt_ptp_clear(struct bnxt *bp); 183ae5c42f0SMichael Chan #endif 184