1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2021 Broadcom Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 #include <linux/kernel.h> 10 #include <linux/errno.h> 11 #include <linux/pci.h> 12 #include <linux/netdevice.h> 13 #include <linux/etherdevice.h> 14 #include <linux/net_tstamp.h> 15 #include <linux/timekeeping.h> 16 #include <linux/ptp_classify.h> 17 #include <linux/clocksource.h> 18 #include <linux/bnxt/hsi.h> 19 #include "bnxt.h" 20 #include "bnxt_hwrm.h" 21 #include "bnxt_ptp.h" 22 23 static int bnxt_ptp_cfg_settime(struct bnxt *bp, u64 time) 24 { 25 struct hwrm_func_ptp_cfg_input *req; 26 int rc; 27 28 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG); 29 if (rc) 30 return rc; 31 32 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME); 33 req->ptp_set_time = cpu_to_le64(time); 34 return hwrm_req_send(bp, req); 35 } 36 37 int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off) 38 { 39 unsigned int ptp_class; 40 struct ptp_header *hdr; 41 42 ptp_class = ptp_classify_raw(skb); 43 44 switch (ptp_class & PTP_CLASS_VMASK) { 45 case PTP_CLASS_V1: 46 case PTP_CLASS_V2: 47 hdr = ptp_parse_header(skb, ptp_class); 48 if (!hdr) 49 return -EINVAL; 50 51 *hdr_off = (u8 *)hdr - skb->data; 52 *seq_id = ntohs(hdr->sequence_id); 53 return 0; 54 default: 55 return -ERANGE; 56 } 57 } 58 59 static int bnxt_ptp_settime(struct ptp_clock_info *ptp_info, 60 const struct timespec64 *ts) 61 { 62 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 63 ptp_info); 64 u64 ns = timespec64_to_ns(ts); 65 unsigned long flags; 66 67 if (BNXT_PTP_USE_RTC(ptp->bp)) 68 return bnxt_ptp_cfg_settime(ptp->bp, ns); 69 70 write_seqlock_irqsave(&ptp->ptp_lock, flags); 71 timecounter_init(&ptp->tc, &ptp->cc, ns); 72 write_sequnlock_irqrestore(&ptp->ptp_lock, flags); 73 return 0; 74 } 75 76 /* Caller holds ptp_lock */ 77 static int __bnxt_refclk_read(struct bnxt *bp, struct ptp_system_timestamp *sts, 78 u64 *ns) 79 { 80 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 81 u32 high_before, high_now, low; 82 83 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 84 return -EIO; 85 86 high_before = readl(bp->bar0 + ptp->refclk_mapped_regs[1]); 87 ptp_read_system_prets(sts); 88 low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]); 89 ptp_read_system_postts(sts); 90 high_now = readl(bp->bar0 + ptp->refclk_mapped_regs[1]); 91 if (high_now != high_before) { 92 ptp_read_system_prets(sts); 93 low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]); 94 ptp_read_system_postts(sts); 95 } 96 *ns = ((u64)high_now << 32) | low; 97 98 return 0; 99 } 100 101 static int bnxt_refclk_read(struct bnxt *bp, struct ptp_system_timestamp *sts, 102 u64 *ns) 103 { 104 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 105 unsigned long flags; 106 int rc; 107 108 /* We have to serialize reg access and FW reset */ 109 read_seqlock_excl_irqsave(&ptp->ptp_lock, flags); 110 rc = __bnxt_refclk_read(bp, sts, ns); 111 read_sequnlock_excl_irqrestore(&ptp->ptp_lock, flags); 112 return rc; 113 } 114 115 static int bnxt_refclk_read_low(struct bnxt *bp, struct ptp_system_timestamp *sts, 116 u32 *low) 117 { 118 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 119 unsigned long flags; 120 121 /* We have to serialize reg access and FW reset */ 122 read_seqlock_excl_irqsave(&ptp->ptp_lock, flags); 123 124 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 125 read_sequnlock_excl_irqrestore(&ptp->ptp_lock, flags); 126 return -EIO; 127 } 128 129 ptp_read_system_prets(sts); 130 *low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]); 131 ptp_read_system_postts(sts); 132 133 read_sequnlock_excl_irqrestore(&ptp->ptp_lock, flags); 134 return 0; 135 } 136 137 static void bnxt_ptp_get_current_time(struct bnxt *bp) 138 { 139 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 140 141 if (!ptp) 142 return; 143 WRITE_ONCE(ptp->old_time, ptp->current_time >> BNXT_HI_TIMER_SHIFT); 144 bnxt_refclk_read(bp, NULL, &ptp->current_time); 145 } 146 147 static int bnxt_hwrm_port_ts_query(struct bnxt *bp, u32 flags, u64 *ts, 148 u32 txts_tmo, int slot) 149 { 150 struct hwrm_port_ts_query_output *resp; 151 struct hwrm_port_ts_query_input *req; 152 int rc; 153 154 rc = hwrm_req_init(bp, req, HWRM_PORT_TS_QUERY); 155 if (rc) 156 return rc; 157 158 req->flags = cpu_to_le32(flags); 159 if ((flags & PORT_TS_QUERY_REQ_FLAGS_PATH) == 160 PORT_TS_QUERY_REQ_FLAGS_PATH_TX) { 161 struct bnxt_ptp_tx_req *txts_req = &bp->ptp_cfg->txts_req[slot]; 162 u32 tmo_us = txts_tmo * 1000; 163 164 req->enables = cpu_to_le16(BNXT_PTP_QTS_TX_ENABLES); 165 req->ptp_seq_id = cpu_to_le32(txts_req->tx_seqid); 166 req->ptp_hdr_offset = cpu_to_le16(txts_req->tx_hdr_off); 167 if (!tmo_us) 168 tmo_us = BNXT_PTP_QTS_TIMEOUT; 169 tmo_us = min(tmo_us, BNXT_PTP_QTS_MAX_TMO_US); 170 req->ts_req_timeout = cpu_to_le16(tmo_us); 171 } 172 resp = hwrm_req_hold(bp, req); 173 174 rc = hwrm_req_send_silent(bp, req); 175 if (!rc) 176 *ts = le64_to_cpu(resp->ptp_msg_ts); 177 hwrm_req_drop(bp, req); 178 return rc; 179 } 180 181 static int bnxt_ptp_gettimex(struct ptp_clock_info *ptp_info, 182 struct timespec64 *ts, 183 struct ptp_system_timestamp *sts) 184 { 185 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 186 ptp_info); 187 u64 ns, cycles; 188 u32 low; 189 int rc; 190 191 rc = bnxt_refclk_read_low(ptp->bp, sts, &low); 192 if (rc) 193 return rc; 194 195 cycles = bnxt_extend_cycles_32b_to_48b(ptp, low); 196 ns = bnxt_timecounter_cyc2time(ptp, cycles); 197 *ts = ns_to_timespec64(ns); 198 199 return 0; 200 } 201 202 void bnxt_ptp_update_current_time(struct bnxt *bp) 203 { 204 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 205 206 bnxt_refclk_read(ptp->bp, NULL, &ptp->current_time); 207 WRITE_ONCE(ptp->old_time, ptp->current_time >> BNXT_HI_TIMER_SHIFT); 208 } 209 210 static int bnxt_ptp_adjphc(struct bnxt_ptp_cfg *ptp, s64 delta) 211 { 212 struct hwrm_port_mac_cfg_input *req; 213 int rc; 214 215 rc = hwrm_req_init(ptp->bp, req, HWRM_PORT_MAC_CFG); 216 if (rc) 217 return rc; 218 219 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE); 220 req->ptp_adj_phase = cpu_to_le64(delta); 221 222 rc = hwrm_req_send(ptp->bp, req); 223 if (rc) { 224 netdev_err(ptp->bp->dev, "ptp adjphc failed. rc = %x\n", rc); 225 } else { 226 bnxt_ptp_update_current_time(ptp->bp); 227 } 228 229 return rc; 230 } 231 232 static int bnxt_ptp_adjtime(struct ptp_clock_info *ptp_info, s64 delta) 233 { 234 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 235 ptp_info); 236 unsigned long flags; 237 238 if (BNXT_PTP_USE_RTC(ptp->bp)) 239 return bnxt_ptp_adjphc(ptp, delta); 240 241 write_seqlock_irqsave(&ptp->ptp_lock, flags); 242 timecounter_adjtime(&ptp->tc, delta); 243 write_sequnlock_irqrestore(&ptp->ptp_lock, flags); 244 return 0; 245 } 246 247 static int bnxt_ptp_adjfine_rtc(struct bnxt *bp, long scaled_ppm) 248 { 249 s32 ppb = scaled_ppm_to_ppb(scaled_ppm); 250 struct hwrm_port_mac_cfg_input *req; 251 int rc; 252 253 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 254 if (rc) 255 return rc; 256 257 req->ptp_freq_adj_ppb = cpu_to_le32(ppb); 258 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB); 259 rc = hwrm_req_send(bp, req); 260 if (rc) 261 netdev_err(bp->dev, 262 "ptp adjfine failed. rc = %d\n", rc); 263 return rc; 264 } 265 266 static int bnxt_ptp_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm) 267 { 268 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 269 ptp_info); 270 struct bnxt *bp = ptp->bp; 271 unsigned long flags; 272 273 if (!BNXT_MH(bp)) 274 return bnxt_ptp_adjfine_rtc(bp, scaled_ppm); 275 276 write_seqlock_irqsave(&ptp->ptp_lock, flags); 277 timecounter_read(&ptp->tc); 278 ptp->cc.mult = adjust_by_scaled_ppm(ptp->cmult, scaled_ppm); 279 write_sequnlock_irqrestore(&ptp->ptp_lock, flags); 280 return 0; 281 } 282 283 void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2) 284 { 285 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 286 struct ptp_clock_event event; 287 u64 ns, pps_ts; 288 289 pps_ts = EVENT_PPS_TS(data2, data1); 290 ns = bnxt_timecounter_cyc2time(ptp, pps_ts); 291 292 switch (EVENT_DATA2_PPS_EVENT_TYPE(data2)) { 293 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL: 294 event.pps_times.ts_real = ns_to_timespec64(ns); 295 event.type = PTP_CLOCK_PPSUSR; 296 event.index = EVENT_DATA2_PPS_PIN_NUM(data2); 297 break; 298 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL: 299 event.timestamp = ns; 300 event.type = PTP_CLOCK_EXTTS; 301 event.index = EVENT_DATA2_PPS_PIN_NUM(data2); 302 break; 303 } 304 305 ptp_clock_event(bp->ptp_cfg->ptp_clock, &event); 306 } 307 308 static int bnxt_ptp_cfg_pin(struct bnxt *bp, u8 pin, u8 usage) 309 { 310 struct hwrm_func_ptp_pin_cfg_input *req; 311 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 312 u8 state = usage != BNXT_PPS_PIN_NONE; 313 u8 *pin_state, *pin_usg; 314 u32 enables; 315 int rc; 316 317 if (!TSIO_PIN_VALID(pin)) { 318 netdev_err(ptp->bp->dev, "1PPS: Invalid pin. Check pin-function configuration\n"); 319 return -EOPNOTSUPP; 320 } 321 322 rc = hwrm_req_init(ptp->bp, req, HWRM_FUNC_PTP_PIN_CFG); 323 if (rc) 324 return rc; 325 326 enables = (FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE | 327 FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE) << (pin * 2); 328 req->enables = cpu_to_le32(enables); 329 330 pin_state = &req->pin0_state; 331 pin_usg = &req->pin0_usage; 332 333 *(pin_state + (pin * 2)) = state; 334 *(pin_usg + (pin * 2)) = usage; 335 336 rc = hwrm_req_send(ptp->bp, req); 337 if (rc) 338 return rc; 339 340 ptp->pps_info.pins[pin].usage = usage; 341 ptp->pps_info.pins[pin].state = state; 342 343 return 0; 344 } 345 346 static int bnxt_ptp_cfg_event(struct bnxt *bp, u8 event) 347 { 348 struct hwrm_func_ptp_cfg_input *req; 349 int rc; 350 351 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG); 352 if (rc) 353 return rc; 354 355 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT); 356 req->ptp_pps_event = event; 357 return hwrm_req_send(bp, req); 358 } 359 360 int bnxt_ptp_cfg_tstamp_filters(struct bnxt *bp) 361 { 362 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 363 struct hwrm_port_mac_cfg_input *req; 364 int rc; 365 366 if (!ptp || !ptp->tstamp_filters) 367 return -EIO; 368 369 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 370 if (rc) 371 goto out; 372 373 if (!(bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) && (ptp->tstamp_filters & 374 (PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE | 375 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE))) { 376 ptp->tstamp_filters &= ~(PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE | 377 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE); 378 netdev_warn(bp->dev, "Unsupported FW for all RX pkts timestamp filter\n"); 379 } 380 381 req->flags = cpu_to_le32(ptp->tstamp_filters); 382 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE); 383 req->rx_ts_capture_ptp_msg_type = cpu_to_le16(ptp->rxctl); 384 385 rc = hwrm_req_send(bp, req); 386 if (!rc) { 387 bp->ptp_all_rx_tstamp = !!(ptp->tstamp_filters & 388 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE); 389 return 0; 390 } 391 ptp->tstamp_filters = 0; 392 out: 393 bp->ptp_all_rx_tstamp = 0; 394 netdev_warn(bp->dev, "Failed to configure HW packet timestamp filters\n"); 395 return rc; 396 } 397 398 void bnxt_ptp_reapply_pps(struct bnxt *bp) 399 { 400 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 401 struct bnxt_pps *pps; 402 u32 pin = 0; 403 int rc; 404 405 if (!ptp || !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) || 406 !(ptp->ptp_info.pin_config)) 407 return; 408 pps = &ptp->pps_info; 409 for (pin = 0; pin < BNXT_MAX_TSIO_PINS; pin++) { 410 if (pps->pins[pin].state) { 411 rc = bnxt_ptp_cfg_pin(bp, pin, pps->pins[pin].usage); 412 if (!rc && pps->pins[pin].event) 413 rc = bnxt_ptp_cfg_event(bp, 414 pps->pins[pin].event); 415 if (rc) 416 netdev_err(bp->dev, "1PPS: Failed to configure pin%d\n", 417 pin); 418 } 419 } 420 } 421 422 static int bnxt_ptp_perout_cfg(struct bnxt_ptp_cfg *ptp, 423 struct ptp_clock_request *rq) 424 { 425 struct hwrm_func_ptp_cfg_input *req; 426 struct bnxt *bp = ptp->bp; 427 struct timespec64 ts; 428 u64 target_ns; 429 u16 enables; 430 int rc; 431 432 ts.tv_sec = rq->perout.start.sec; 433 ts.tv_nsec = rq->perout.start.nsec; 434 target_ns = timespec64_to_ns(&ts); 435 436 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG); 437 if (rc) 438 return rc; 439 440 enables = FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD | 441 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP | 442 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE; 443 req->enables = cpu_to_le16(enables); 444 req->ptp_pps_event = 0; 445 req->ptp_freq_adj_dll_source = 0; 446 req->ptp_freq_adj_dll_phase = 0; 447 req->ptp_freq_adj_ext_period = cpu_to_le32(NSEC_PER_SEC); 448 req->ptp_freq_adj_ext_up = 0; 449 req->ptp_freq_adj_ext_phase_lower = 450 cpu_to_le32(lower_32_bits(target_ns)); 451 req->ptp_freq_adj_ext_phase_upper = 452 cpu_to_le32(upper_32_bits(target_ns)); 453 454 return hwrm_req_send(bp, req); 455 } 456 457 static int bnxt_ptp_enable(struct ptp_clock_info *ptp_info, 458 struct ptp_clock_request *rq, int on) 459 { 460 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 461 ptp_info); 462 struct bnxt *bp = ptp->bp; 463 int pin_id; 464 int rc; 465 466 switch (rq->type) { 467 case PTP_CLK_REQ_EXTTS: 468 /* Configure an External PPS IN */ 469 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_EXTTS, 470 rq->extts.index); 471 if (!TSIO_PIN_VALID(pin_id)) 472 return -EOPNOTSUPP; 473 if (!on) 474 break; 475 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_IN); 476 if (rc) 477 return rc; 478 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_EXTERNAL); 479 if (!rc) 480 ptp->pps_info.pins[pin_id].event = BNXT_PPS_EVENT_EXTERNAL; 481 return rc; 482 case PTP_CLK_REQ_PEROUT: 483 /* Configure a Periodic PPS OUT */ 484 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_PEROUT, 485 rq->perout.index); 486 if (!TSIO_PIN_VALID(pin_id)) 487 return -EOPNOTSUPP; 488 if (!on) 489 break; 490 491 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_OUT); 492 if (!rc) 493 rc = bnxt_ptp_perout_cfg(ptp, rq); 494 495 return rc; 496 case PTP_CLK_REQ_PPS: 497 /* Configure PHC PPS IN */ 498 pin_id = 0; 499 if (!on) 500 break; 501 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_IN); 502 if (rc) 503 return rc; 504 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_INTERNAL); 505 if (!rc) 506 ptp->pps_info.pins[pin_id].event = BNXT_PPS_EVENT_INTERNAL; 507 return rc; 508 default: 509 netdev_err(ptp->bp->dev, "Unrecognized PIN function\n"); 510 return -EOPNOTSUPP; 511 } 512 513 return bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_NONE); 514 } 515 516 static int bnxt_hwrm_ptp_cfg(struct bnxt *bp) 517 { 518 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 519 u32 flags = 0; 520 521 switch (ptp->rx_filter) { 522 case HWTSTAMP_FILTER_ALL: 523 flags = PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE; 524 break; 525 case HWTSTAMP_FILTER_NONE: 526 flags = PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE; 527 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) 528 flags |= PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE; 529 break; 530 case HWTSTAMP_FILTER_PTP_V2_EVENT: 531 case HWTSTAMP_FILTER_PTP_V2_SYNC: 532 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 533 flags = PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE; 534 break; 535 } 536 537 if (ptp->tx_tstamp_en) 538 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE; 539 else 540 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE; 541 542 ptp->tstamp_filters = flags; 543 544 return bnxt_ptp_cfg_tstamp_filters(bp); 545 } 546 547 int bnxt_hwtstamp_set(struct net_device *dev, 548 struct kernel_hwtstamp_config *stmpconf, 549 struct netlink_ext_ack *extack) 550 { 551 struct bnxt *bp = netdev_priv(dev); 552 struct bnxt_ptp_cfg *ptp; 553 u16 old_rxctl; 554 int old_rx_filter, rc; 555 u8 old_tx_tstamp_en; 556 557 ptp = bp->ptp_cfg; 558 if (!ptp) 559 return -EOPNOTSUPP; 560 561 if (stmpconf->tx_type != HWTSTAMP_TX_ON && 562 stmpconf->tx_type != HWTSTAMP_TX_OFF) 563 return -ERANGE; 564 565 old_rx_filter = ptp->rx_filter; 566 old_rxctl = ptp->rxctl; 567 old_tx_tstamp_en = ptp->tx_tstamp_en; 568 switch (stmpconf->rx_filter) { 569 case HWTSTAMP_FILTER_NONE: 570 ptp->rxctl = 0; 571 ptp->rx_filter = HWTSTAMP_FILTER_NONE; 572 break; 573 case HWTSTAMP_FILTER_ALL: 574 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) { 575 ptp->rx_filter = HWTSTAMP_FILTER_ALL; 576 break; 577 } 578 return -EOPNOTSUPP; 579 case HWTSTAMP_FILTER_PTP_V2_EVENT: 580 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 581 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 582 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 583 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 584 break; 585 case HWTSTAMP_FILTER_PTP_V2_SYNC: 586 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 587 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 588 ptp->rxctl = BNXT_PTP_MSG_SYNC; 589 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 590 break; 591 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 592 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 593 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 594 ptp->rxctl = BNXT_PTP_MSG_DELAY_REQ; 595 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 596 break; 597 default: 598 return -ERANGE; 599 } 600 601 if (stmpconf->tx_type == HWTSTAMP_TX_ON) 602 ptp->tx_tstamp_en = 1; 603 else 604 ptp->tx_tstamp_en = 0; 605 606 rc = bnxt_hwrm_ptp_cfg(bp); 607 if (rc) 608 goto ts_set_err; 609 610 stmpconf->rx_filter = ptp->rx_filter; 611 return 0; 612 613 ts_set_err: 614 ptp->rx_filter = old_rx_filter; 615 ptp->rxctl = old_rxctl; 616 ptp->tx_tstamp_en = old_tx_tstamp_en; 617 return rc; 618 } 619 620 int bnxt_hwtstamp_get(struct net_device *dev, 621 struct kernel_hwtstamp_config *stmpconf) 622 { 623 struct bnxt *bp = netdev_priv(dev); 624 struct bnxt_ptp_cfg *ptp; 625 626 ptp = bp->ptp_cfg; 627 if (!ptp) 628 return -EOPNOTSUPP; 629 630 stmpconf->flags = 0; 631 stmpconf->tx_type = ptp->tx_tstamp_en ? HWTSTAMP_TX_ON 632 : HWTSTAMP_TX_OFF; 633 634 stmpconf->rx_filter = ptp->rx_filter; 635 return 0; 636 } 637 638 static int bnxt_map_regs(struct bnxt *bp, u32 *reg_arr, int count, int reg_win) 639 { 640 u32 reg_base = *reg_arr & BNXT_GRC_BASE_MASK; 641 u32 win_off; 642 int i; 643 644 for (i = 0; i < count; i++) { 645 if ((reg_arr[i] & BNXT_GRC_BASE_MASK) != reg_base) 646 return -ERANGE; 647 } 648 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 649 writel(reg_base, bp->bar0 + win_off); 650 return 0; 651 } 652 653 static int bnxt_map_ptp_regs(struct bnxt *bp) 654 { 655 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 656 u32 *reg_arr; 657 int rc, i; 658 659 reg_arr = ptp->refclk_regs; 660 if (BNXT_CHIP_P5(bp)) { 661 rc = bnxt_map_regs(bp, reg_arr, 2, BNXT_PTP_GRC_WIN); 662 if (rc) 663 return rc; 664 for (i = 0; i < 2; i++) 665 ptp->refclk_mapped_regs[i] = BNXT_PTP_GRC_WIN_BASE + 666 (ptp->refclk_regs[i] & BNXT_GRC_OFFSET_MASK); 667 return 0; 668 } 669 if (bp->flags & BNXT_FLAG_CHIP_P7) { 670 for (i = 0; i < 2; i++) { 671 if (reg_arr[i] & BNXT_GRC_BASE_MASK) 672 return -EINVAL; 673 ptp->refclk_mapped_regs[i] = reg_arr[i]; 674 } 675 return 0; 676 } 677 return -ENODEV; 678 } 679 680 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 681 { 682 writel(0, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 683 (BNXT_PTP_GRC_WIN - 1) * 4); 684 } 685 686 static u64 bnxt_cc_read(struct cyclecounter *cc) 687 { 688 struct bnxt_ptp_cfg *ptp = container_of(cc, struct bnxt_ptp_cfg, cc); 689 u64 ns = 0; 690 691 __bnxt_refclk_read(ptp->bp, NULL, &ns); 692 return ns; 693 } 694 695 static int bnxt_stamp_tx_skb(struct bnxt *bp, int slot) 696 { 697 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 698 struct skb_shared_hwtstamps timestamp; 699 struct bnxt_ptp_tx_req *txts_req; 700 unsigned long now = jiffies; 701 u64 ts = 0, ns = 0; 702 u32 tmo = 0; 703 int rc; 704 705 txts_req = &ptp->txts_req[slot]; 706 /* make sure bnxt_get_tx_ts_p5() has updated abs_txts_tmo */ 707 smp_rmb(); 708 if (!time_after_eq(now, txts_req->abs_txts_tmo)) 709 tmo = jiffies_to_msecs(txts_req->abs_txts_tmo - now); 710 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_PATH_TX, &ts, 711 tmo, slot); 712 if (!rc) { 713 memset(×tamp, 0, sizeof(timestamp)); 714 ns = bnxt_timecounter_cyc2time(ptp, ts); 715 timestamp.hwtstamp = ns_to_ktime(ns); 716 skb_tstamp_tx(txts_req->tx_skb, ×tamp); 717 ptp->stats.ts_pkts++; 718 } else { 719 if (!time_after_eq(jiffies, txts_req->abs_txts_tmo)) 720 return -EAGAIN; 721 722 ptp->stats.ts_lost++; 723 netdev_warn_once(bp->dev, 724 "TS query for TX timer failed rc = %x\n", rc); 725 } 726 727 dev_kfree_skb_any(txts_req->tx_skb); 728 txts_req->tx_skb = NULL; 729 730 return 0; 731 } 732 733 static long bnxt_ptp_ts_aux_work(struct ptp_clock_info *ptp_info) 734 { 735 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 736 ptp_info); 737 unsigned long now = jiffies; 738 struct bnxt *bp = ptp->bp; 739 u16 cons = ptp->txts_cons; 740 unsigned long flags; 741 u32 num_requests; 742 int rc = 0; 743 744 num_requests = BNXT_MAX_TX_TS - READ_ONCE(ptp->tx_avail); 745 while (num_requests--) { 746 if (IS_ERR(ptp->txts_req[cons].tx_skb)) 747 goto next_slot; 748 if (!ptp->txts_req[cons].tx_skb) 749 break; 750 rc = bnxt_stamp_tx_skb(bp, cons); 751 if (rc == -EAGAIN) 752 break; 753 next_slot: 754 BNXT_PTP_INC_TX_AVAIL(ptp); 755 cons = NEXT_TXTS(cons); 756 } 757 ptp->txts_cons = cons; 758 759 if (!time_after_eq(now, ptp->next_period)) { 760 if (rc == -EAGAIN) 761 return 0; 762 return ptp->next_period - now; 763 } 764 765 bnxt_ptp_get_current_time(bp); 766 ptp->next_period = now + HZ; 767 if (time_after_eq(now, ptp->next_overflow_check)) { 768 write_seqlock_irqsave(&ptp->ptp_lock, flags); 769 timecounter_read(&ptp->tc); 770 write_sequnlock_irqrestore(&ptp->ptp_lock, flags); 771 ptp->next_overflow_check = now + BNXT_PHC_OVERFLOW_PERIOD; 772 } 773 if (rc == -EAGAIN) 774 return 0; 775 return HZ; 776 } 777 778 void bnxt_ptp_free_txts_skbs(struct bnxt_ptp_cfg *ptp) 779 { 780 struct bnxt_ptp_tx_req *txts_req; 781 u16 cons = ptp->txts_cons; 782 783 /* make sure ptp aux worker finished with 784 * possible BNXT_STATE_OPEN set 785 */ 786 ptp_cancel_worker_sync(ptp->ptp_clock); 787 788 ptp->tx_avail = BNXT_MAX_TX_TS; 789 while (cons != ptp->txts_prod) { 790 txts_req = &ptp->txts_req[cons]; 791 if (!IS_ERR_OR_NULL(txts_req->tx_skb)) 792 dev_kfree_skb_any(txts_req->tx_skb); 793 cons = NEXT_TXTS(cons); 794 } 795 ptp->txts_cons = cons; 796 ptp_schedule_worker(ptp->ptp_clock, 0); 797 } 798 799 int bnxt_ptp_get_txts_prod(struct bnxt_ptp_cfg *ptp, u16 *prod) 800 { 801 spin_lock_bh(&ptp->ptp_tx_lock); 802 if (ptp->tx_avail) { 803 *prod = ptp->txts_prod; 804 ptp->txts_prod = NEXT_TXTS(*prod); 805 ptp->tx_avail--; 806 spin_unlock_bh(&ptp->ptp_tx_lock); 807 return 0; 808 } 809 spin_unlock_bh(&ptp->ptp_tx_lock); 810 atomic64_inc(&ptp->stats.ts_err); 811 return -ENOSPC; 812 } 813 814 void bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb, u16 prod) 815 { 816 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 817 struct bnxt_ptp_tx_req *txts_req; 818 819 txts_req = &ptp->txts_req[prod]; 820 txts_req->abs_txts_tmo = jiffies + msecs_to_jiffies(ptp->txts_tmo); 821 /* make sure abs_txts_tmo is written first */ 822 smp_wmb(); 823 txts_req->tx_skb = skb; 824 ptp_schedule_worker(ptp->ptp_clock, 0); 825 } 826 827 int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts) 828 { 829 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 830 831 if (!ptp) 832 return -ENODEV; 833 834 *ts = bnxt_extend_cycles_32b_to_48b(ptp, pkt_ts); 835 836 return 0; 837 } 838 839 void bnxt_tx_ts_cmp(struct bnxt *bp, struct bnxt_napi *bnapi, 840 struct tx_ts_cmp *tscmp) 841 { 842 struct skb_shared_hwtstamps timestamp = {}; 843 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 844 u32 opaque = tscmp->tx_ts_cmp_opaque; 845 struct bnxt_tx_ring_info *txr; 846 struct bnxt_sw_tx_bd *tx_buf; 847 u64 ts, ns; 848 u16 cons; 849 850 txr = bnapi->tx_ring[TX_OPAQUE_RING(opaque)]; 851 ts = BNXT_GET_TX_TS_48B_NS(tscmp); 852 cons = TX_OPAQUE_IDX(opaque); 853 tx_buf = &txr->tx_buf_ring[RING_TX(bp, cons)]; 854 if (tx_buf->is_ts_pkt) { 855 if (BNXT_TX_TS_ERR(tscmp)) { 856 netdev_err(bp->dev, 857 "timestamp completion error 0x%x 0x%x\n", 858 le32_to_cpu(tscmp->tx_ts_cmp_flags_type), 859 le32_to_cpu(tscmp->tx_ts_cmp_errors_v)); 860 } else { 861 ns = bnxt_timecounter_cyc2time(ptp, ts); 862 timestamp.hwtstamp = ns_to_ktime(ns); 863 skb_tstamp_tx(tx_buf->skb, ×tamp); 864 } 865 tx_buf->is_ts_pkt = 0; 866 } 867 } 868 869 #ifdef CONFIG_X86 870 static int bnxt_phc_get_syncdevicetime(ktime_t *device, 871 struct system_counterval_t *system, 872 void *ctx) 873 { 874 struct bnxt_ptp_cfg *ptp = (struct bnxt_ptp_cfg *)ctx; 875 struct hwrm_func_ptp_ts_query_output *resp; 876 struct hwrm_func_ptp_ts_query_input *req; 877 struct bnxt *bp = ptp->bp; 878 u64 ptm_local_ts; 879 int rc; 880 881 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_TS_QUERY); 882 if (rc) 883 return rc; 884 req->flags = cpu_to_le32(FUNC_PTP_TS_QUERY_REQ_FLAGS_PTM_TIME); 885 resp = hwrm_req_hold(bp, req); 886 rc = hwrm_req_send(bp, req); 887 if (rc) { 888 hwrm_req_drop(bp, req); 889 return rc; 890 } 891 ptm_local_ts = le64_to_cpu(resp->ptm_local_ts); 892 *device = ns_to_ktime(bnxt_timecounter_cyc2time(ptp, ptm_local_ts)); 893 /* ptm_system_ts is 64-bit */ 894 system->cycles = le64_to_cpu(resp->ptm_system_ts); 895 system->cs_id = CSID_X86_ART; 896 system->use_nsecs = true; 897 898 hwrm_req_drop(bp, req); 899 900 return 0; 901 } 902 903 static int bnxt_ptp_getcrosststamp(struct ptp_clock_info *ptp_info, 904 struct system_device_crosststamp *xtstamp) 905 { 906 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 907 ptp_info); 908 909 return get_device_system_crosststamp(bnxt_phc_get_syncdevicetime, 910 ptp, NULL, xtstamp); 911 } 912 #endif /* CONFIG_X86 */ 913 914 static const struct ptp_clock_info bnxt_ptp_caps = { 915 .owner = THIS_MODULE, 916 .name = "bnxt clock", 917 .max_adj = BNXT_MAX_PHC_DRIFT, 918 .n_alarm = 0, 919 .n_ext_ts = 0, 920 .n_per_out = 0, 921 .n_pins = 0, 922 .pps = 0, 923 .adjfine = bnxt_ptp_adjfine, 924 .adjtime = bnxt_ptp_adjtime, 925 .do_aux_work = bnxt_ptp_ts_aux_work, 926 .gettimex64 = bnxt_ptp_gettimex, 927 .settime64 = bnxt_ptp_settime, 928 .enable = bnxt_ptp_enable, 929 }; 930 931 static int bnxt_ptp_verify(struct ptp_clock_info *ptp_info, unsigned int pin, 932 enum ptp_pin_function func, unsigned int chan) 933 { 934 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 935 ptp_info); 936 /* Allow only PPS pin function configuration */ 937 if (ptp->pps_info.pins[pin].usage <= BNXT_PPS_PIN_PPS_OUT && 938 func != PTP_PF_PHYSYNC) 939 return 0; 940 else 941 return -EOPNOTSUPP; 942 } 943 944 static int bnxt_ptp_pps_init(struct bnxt *bp) 945 { 946 struct hwrm_func_ptp_pin_qcfg_output *resp; 947 struct hwrm_func_ptp_pin_qcfg_input *req; 948 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 949 struct ptp_clock_info *ptp_info; 950 struct bnxt_pps *pps_info; 951 u8 *pin_usg; 952 u32 i, rc; 953 954 /* Query current/default PIN CFG */ 955 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_PIN_QCFG); 956 if (rc) 957 return rc; 958 959 resp = hwrm_req_hold(bp, req); 960 rc = hwrm_req_send(bp, req); 961 if (rc || !resp->num_pins) { 962 hwrm_req_drop(bp, req); 963 return -EOPNOTSUPP; 964 } 965 966 ptp_info = &ptp->ptp_info; 967 pps_info = &ptp->pps_info; 968 pps_info->num_pins = resp->num_pins; 969 ptp_info->n_pins = pps_info->num_pins; 970 ptp_info->pin_config = kzalloc_objs(*ptp_info->pin_config, 971 ptp_info->n_pins); 972 if (!ptp_info->pin_config) { 973 hwrm_req_drop(bp, req); 974 return -ENOMEM; 975 } 976 977 /* Report the TSIO capability to kernel */ 978 pin_usg = &resp->pin0_usage; 979 for (i = 0; i < pps_info->num_pins; i++, pin_usg++) { 980 snprintf(ptp_info->pin_config[i].name, 981 sizeof(ptp_info->pin_config[i].name), "bnxt_pps%d", i); 982 ptp_info->pin_config[i].index = i; 983 if (*pin_usg == BNXT_PPS_PIN_PPS_IN) 984 ptp_info->pin_config[i].func = PTP_PF_EXTTS; 985 else if (*pin_usg == BNXT_PPS_PIN_PPS_OUT) 986 ptp_info->pin_config[i].func = PTP_PF_PEROUT; 987 else 988 ptp_info->pin_config[i].func = PTP_PF_NONE; 989 990 pps_info->pins[i].usage = *pin_usg; 991 } 992 hwrm_req_drop(bp, req); 993 994 /* Only 1 each of ext_ts and per_out pins is available in HW */ 995 ptp_info->n_ext_ts = 1; 996 ptp_info->n_per_out = 1; 997 ptp_info->pps = 1; 998 ptp_info->verify = bnxt_ptp_verify; 999 ptp_info->supported_extts_flags = PTP_RISING_EDGE | PTP_STRICT_FLAGS; 1000 ptp_info->supported_perout_flags = PTP_PEROUT_DUTY_CYCLE; 1001 1002 return 0; 1003 } 1004 1005 static bool bnxt_pps_config_ok(struct bnxt *bp) 1006 { 1007 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 1008 1009 return !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) == !ptp->ptp_info.pin_config; 1010 } 1011 1012 static void bnxt_ptp_timecounter_init(struct bnxt *bp, bool init_tc) 1013 { 1014 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 1015 unsigned long flags; 1016 1017 if (!ptp->ptp_clock) { 1018 memset(&ptp->cc, 0, sizeof(ptp->cc)); 1019 ptp->cc.read = bnxt_cc_read; 1020 ptp->cc.mask = CYCLECOUNTER_MASK(48); 1021 if (BNXT_MH(bp)) { 1022 /* Use timecounter based non-real time mode */ 1023 ptp->cc.shift = BNXT_CYCLES_SHIFT; 1024 ptp->cc.mult = clocksource_khz2mult(BNXT_DEVCLK_FREQ, ptp->cc.shift); 1025 ptp->cmult = ptp->cc.mult; 1026 } else { 1027 ptp->cc.shift = 0; 1028 ptp->cc.mult = 1; 1029 } 1030 ptp->next_overflow_check = jiffies + BNXT_PHC_OVERFLOW_PERIOD; 1031 } 1032 if (init_tc) { 1033 write_seqlock_irqsave(&ptp->ptp_lock, flags); 1034 timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real())); 1035 write_sequnlock_irqrestore(&ptp->ptp_lock, flags); 1036 } 1037 } 1038 1039 /* Caller holds ptp_lock */ 1040 void bnxt_ptp_rtc_timecounter_init(struct bnxt_ptp_cfg *ptp, u64 ns) 1041 { 1042 timecounter_init(&ptp->tc, &ptp->cc, ns); 1043 /* For RTC, cycle_last must be in sync with the timecounter value. */ 1044 ptp->tc.cycle_last = ns & ptp->cc.mask; 1045 } 1046 1047 int bnxt_ptp_init_rtc(struct bnxt *bp, bool phc_cfg) 1048 { 1049 struct timespec64 tsp; 1050 unsigned long flags; 1051 u64 ns; 1052 int rc; 1053 1054 if (!bp->ptp_cfg || !BNXT_PTP_USE_RTC(bp)) 1055 return -ENODEV; 1056 1057 if (!phc_cfg) { 1058 ktime_get_real_ts64(&tsp); 1059 ns = timespec64_to_ns(&tsp); 1060 rc = bnxt_ptp_cfg_settime(bp, ns); 1061 if (rc) 1062 return rc; 1063 } else { 1064 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME, 1065 &ns, 0, 0); 1066 if (rc) 1067 return rc; 1068 } 1069 write_seqlock_irqsave(&bp->ptp_cfg->ptp_lock, flags); 1070 bnxt_ptp_rtc_timecounter_init(bp->ptp_cfg, ns); 1071 write_sequnlock_irqrestore(&bp->ptp_cfg->ptp_lock, flags); 1072 1073 return 0; 1074 } 1075 1076 static void bnxt_ptp_free(struct bnxt *bp) 1077 { 1078 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 1079 1080 if (ptp->ptp_clock) { 1081 ptp_clock_unregister(ptp->ptp_clock); 1082 ptp->ptp_clock = NULL; 1083 } 1084 kfree(ptp->ptp_info.pin_config); 1085 ptp->ptp_info.pin_config = NULL; 1086 } 1087 1088 int bnxt_ptp_init(struct bnxt *bp) 1089 { 1090 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 1091 int rc; 1092 1093 if (!ptp) 1094 return 0; 1095 1096 rc = bnxt_map_ptp_regs(bp); 1097 if (rc) 1098 return rc; 1099 1100 if (ptp->ptp_clock && bnxt_pps_config_ok(bp)) 1101 return 0; 1102 1103 bnxt_ptp_free(bp); 1104 1105 WRITE_ONCE(ptp->tx_avail, BNXT_MAX_TX_TS); 1106 seqlock_init(&ptp->ptp_lock); 1107 spin_lock_init(&ptp->ptp_tx_lock); 1108 1109 if (BNXT_PTP_USE_RTC(bp)) { 1110 bnxt_ptp_timecounter_init(bp, false); 1111 rc = bnxt_ptp_init_rtc(bp, ptp->rtc_configured); 1112 if (rc) 1113 goto out; 1114 } else { 1115 bnxt_ptp_timecounter_init(bp, true); 1116 bnxt_ptp_adjfine_rtc(bp, 0); 1117 } 1118 bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, true); 1119 1120 ptp->ptp_info = bnxt_ptp_caps; 1121 if ((bp->fw_cap & BNXT_FW_CAP_PTP_PPS)) { 1122 if (bnxt_ptp_pps_init(bp)) 1123 netdev_err(bp->dev, "1pps not initialized, continuing without 1pps support\n"); 1124 } 1125 #ifdef CONFIG_X86 1126 if ((bp->fw_cap & BNXT_FW_CAP_PTP_PTM) && pcie_ptm_enabled(bp->pdev) && 1127 boot_cpu_has(X86_FEATURE_ART)) 1128 ptp->ptp_info.getcrosststamp = bnxt_ptp_getcrosststamp; 1129 #endif /* CONFIG_X86 */ 1130 1131 ptp->ptp_clock = ptp_clock_register(&ptp->ptp_info, &bp->pdev->dev); 1132 if (IS_ERR(ptp->ptp_clock)) { 1133 int err = PTR_ERR(ptp->ptp_clock); 1134 1135 ptp->ptp_clock = NULL; 1136 rc = err; 1137 goto out; 1138 } 1139 1140 ptp->stats.ts_pkts = 0; 1141 ptp->stats.ts_lost = 0; 1142 atomic64_set(&ptp->stats.ts_err, 0); 1143 1144 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) { 1145 bnxt_refclk_read(bp, NULL, &ptp->current_time); 1146 WRITE_ONCE(ptp->old_time, ptp->current_time >> BNXT_HI_TIMER_SHIFT); 1147 ptp_schedule_worker(ptp->ptp_clock, 0); 1148 } 1149 ptp->txts_tmo = BNXT_PTP_DFLT_TX_TMO; 1150 return 0; 1151 1152 out: 1153 bnxt_ptp_free(bp); 1154 bnxt_unmap_ptp_regs(bp); 1155 return rc; 1156 } 1157 1158 void bnxt_ptp_clear(struct bnxt *bp) 1159 { 1160 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 1161 1162 if (!ptp) 1163 return; 1164 1165 if (ptp->ptp_clock) 1166 ptp_clock_unregister(ptp->ptp_clock); 1167 1168 ptp->ptp_clock = NULL; 1169 kfree(ptp->ptp_info.pin_config); 1170 ptp->ptp_info.pin_config = NULL; 1171 1172 bnxt_unmap_ptp_regs(bp); 1173 } 1174