1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2021 Broadcom Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 #include <linux/kernel.h> 10 #include <linux/errno.h> 11 #include <linux/pci.h> 12 #include <linux/netdevice.h> 13 #include <linux/etherdevice.h> 14 #include <linux/ptp_clock_kernel.h> 15 #include <linux/net_tstamp.h> 16 #include <linux/timecounter.h> 17 #include <linux/timekeeping.h> 18 #include <linux/ptp_classify.h> 19 #include "bnxt_hsi.h" 20 #include "bnxt.h" 21 #include "bnxt_ptp.h" 22 23 int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off) 24 { 25 unsigned int ptp_class; 26 struct ptp_header *hdr; 27 28 ptp_class = ptp_classify_raw(skb); 29 30 switch (ptp_class & PTP_CLASS_VMASK) { 31 case PTP_CLASS_V1: 32 case PTP_CLASS_V2: 33 hdr = ptp_parse_header(skb, ptp_class); 34 if (!hdr) 35 return -EINVAL; 36 37 *hdr_off = (u8 *)hdr - skb->data; 38 *seq_id = ntohs(hdr->sequence_id); 39 return 0; 40 default: 41 return -ERANGE; 42 } 43 } 44 45 static int bnxt_ptp_settime(struct ptp_clock_info *ptp_info, 46 const struct timespec64 *ts) 47 { 48 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 49 ptp_info); 50 u64 ns = timespec64_to_ns(ts); 51 52 spin_lock_bh(&ptp->ptp_lock); 53 timecounter_init(&ptp->tc, &ptp->cc, ns); 54 spin_unlock_bh(&ptp->ptp_lock); 55 return 0; 56 } 57 58 /* Caller holds ptp_lock */ 59 static int bnxt_refclk_read(struct bnxt *bp, struct ptp_system_timestamp *sts, 60 u64 *ns) 61 { 62 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 63 64 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 65 return -EIO; 66 67 ptp_read_system_prets(sts); 68 *ns = readl(bp->bar0 + ptp->refclk_mapped_regs[0]); 69 ptp_read_system_postts(sts); 70 *ns |= (u64)readl(bp->bar0 + ptp->refclk_mapped_regs[1]) << 32; 71 return 0; 72 } 73 74 static void bnxt_ptp_get_current_time(struct bnxt *bp) 75 { 76 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 77 78 if (!ptp) 79 return; 80 spin_lock_bh(&ptp->ptp_lock); 81 WRITE_ONCE(ptp->old_time, ptp->current_time); 82 bnxt_refclk_read(bp, NULL, &ptp->current_time); 83 spin_unlock_bh(&ptp->ptp_lock); 84 } 85 86 static int bnxt_hwrm_port_ts_query(struct bnxt *bp, u32 flags, u64 *ts) 87 { 88 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr; 89 struct hwrm_port_ts_query_input req = {0}; 90 int rc; 91 92 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_TS_QUERY, -1, -1); 93 req.flags = cpu_to_le32(flags); 94 if ((flags & PORT_TS_QUERY_REQ_FLAGS_PATH) == 95 PORT_TS_QUERY_REQ_FLAGS_PATH_TX) { 96 req.enables = cpu_to_le16(BNXT_PTP_QTS_TX_ENABLES); 97 req.ptp_seq_id = cpu_to_le32(bp->ptp_cfg->tx_seqid); 98 req.ptp_hdr_offset = cpu_to_le16(bp->ptp_cfg->tx_hdr_off); 99 req.ts_req_timeout = cpu_to_le16(BNXT_PTP_QTS_TIMEOUT); 100 } 101 mutex_lock(&bp->hwrm_cmd_lock); 102 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 103 if (!rc) 104 *ts = le64_to_cpu(resp->ptp_msg_ts); 105 mutex_unlock(&bp->hwrm_cmd_lock); 106 return rc; 107 } 108 109 static int bnxt_ptp_gettimex(struct ptp_clock_info *ptp_info, 110 struct timespec64 *ts, 111 struct ptp_system_timestamp *sts) 112 { 113 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 114 ptp_info); 115 u64 ns, cycles; 116 int rc; 117 118 spin_lock_bh(&ptp->ptp_lock); 119 rc = bnxt_refclk_read(ptp->bp, sts, &cycles); 120 if (rc) { 121 spin_unlock_bh(&ptp->ptp_lock); 122 return rc; 123 } 124 ns = timecounter_cyc2time(&ptp->tc, cycles); 125 spin_unlock_bh(&ptp->ptp_lock); 126 *ts = ns_to_timespec64(ns); 127 128 return 0; 129 } 130 131 static int bnxt_ptp_adjtime(struct ptp_clock_info *ptp_info, s64 delta) 132 { 133 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 134 ptp_info); 135 136 spin_lock_bh(&ptp->ptp_lock); 137 timecounter_adjtime(&ptp->tc, delta); 138 spin_unlock_bh(&ptp->ptp_lock); 139 return 0; 140 } 141 142 static int bnxt_ptp_adjfreq(struct ptp_clock_info *ptp_info, s32 ppb) 143 { 144 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 145 ptp_info); 146 struct hwrm_port_mac_cfg_input req = {0}; 147 struct bnxt *bp = ptp->bp; 148 int rc; 149 150 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_MAC_CFG, -1, -1); 151 req.ptp_freq_adj_ppb = cpu_to_le32(ppb); 152 req.enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB); 153 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 154 if (rc) 155 netdev_err(ptp->bp->dev, 156 "ptp adjfreq failed. rc = %d\n", rc); 157 return rc; 158 } 159 160 void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2) 161 { 162 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 163 struct ptp_clock_event event; 164 u64 ns, pps_ts; 165 166 pps_ts = EVENT_PPS_TS(data2, data1); 167 spin_lock_bh(&ptp->ptp_lock); 168 ns = timecounter_cyc2time(&ptp->tc, pps_ts); 169 spin_unlock_bh(&ptp->ptp_lock); 170 171 switch (EVENT_DATA2_PPS_EVENT_TYPE(data2)) { 172 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL: 173 event.pps_times.ts_real = ns_to_timespec64(ns); 174 event.type = PTP_CLOCK_PPSUSR; 175 event.index = EVENT_DATA2_PPS_PIN_NUM(data2); 176 break; 177 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL: 178 event.timestamp = ns; 179 event.type = PTP_CLOCK_EXTTS; 180 event.index = EVENT_DATA2_PPS_PIN_NUM(data2); 181 break; 182 } 183 184 ptp_clock_event(bp->ptp_cfg->ptp_clock, &event); 185 } 186 187 static int bnxt_ptp_cfg_pin(struct bnxt *bp, u8 pin, u8 usage) 188 { 189 struct hwrm_func_ptp_pin_cfg_input req = {0}; 190 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 191 u8 state = usage != BNXT_PPS_PIN_NONE; 192 u8 *pin_state, *pin_usg; 193 u32 enables; 194 int rc; 195 196 if (!TSIO_PIN_VALID(pin)) { 197 netdev_err(ptp->bp->dev, "1PPS: Invalid pin. Check pin-function configuration\n"); 198 return -EOPNOTSUPP; 199 } 200 201 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_PTP_PIN_CFG, -1, -1); 202 enables = (FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE | 203 FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE) << (pin * 2); 204 req.enables = cpu_to_le32(enables); 205 206 pin_state = &req.pin0_state; 207 pin_usg = &req.pin0_usage; 208 209 *(pin_state + (pin * 2)) = state; 210 *(pin_usg + (pin * 2)) = usage; 211 212 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 213 if (rc) 214 return rc; 215 216 ptp->pps_info.pins[pin].usage = usage; 217 ptp->pps_info.pins[pin].state = state; 218 219 return 0; 220 } 221 222 static int bnxt_ptp_cfg_event(struct bnxt *bp, u8 event) 223 { 224 struct hwrm_func_ptp_cfg_input req = {0}; 225 226 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_PTP_CFG, -1, -1); 227 req.enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT); 228 req.ptp_pps_event = event; 229 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 230 } 231 232 void bnxt_ptp_reapply_pps(struct bnxt *bp) 233 { 234 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 235 struct bnxt_pps *pps; 236 u32 pin = 0; 237 int rc; 238 239 if (!ptp || !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) || 240 !(ptp->ptp_info.pin_config)) 241 return; 242 pps = &ptp->pps_info; 243 for (pin = 0; pin < BNXT_MAX_TSIO_PINS; pin++) { 244 if (pps->pins[pin].state) { 245 rc = bnxt_ptp_cfg_pin(bp, pin, pps->pins[pin].usage); 246 if (!rc && pps->pins[pin].event) 247 rc = bnxt_ptp_cfg_event(bp, 248 pps->pins[pin].event); 249 if (rc) 250 netdev_err(bp->dev, "1PPS: Failed to configure pin%d\n", 251 pin); 252 } 253 } 254 } 255 256 static int bnxt_get_target_cycles(struct bnxt_ptp_cfg *ptp, u64 target_ns, 257 u64 *cycles_delta) 258 { 259 u64 cycles_now; 260 u64 nsec_now, nsec_delta; 261 int rc; 262 263 spin_lock_bh(&ptp->ptp_lock); 264 rc = bnxt_refclk_read(ptp->bp, NULL, &cycles_now); 265 if (rc) { 266 spin_unlock_bh(&ptp->ptp_lock); 267 return rc; 268 } 269 nsec_now = timecounter_cyc2time(&ptp->tc, cycles_now); 270 spin_unlock_bh(&ptp->ptp_lock); 271 272 nsec_delta = target_ns - nsec_now; 273 *cycles_delta = div64_u64(nsec_delta << ptp->cc.shift, ptp->cc.mult); 274 return 0; 275 } 276 277 static int bnxt_ptp_perout_cfg(struct bnxt_ptp_cfg *ptp, 278 struct ptp_clock_request *rq) 279 { 280 struct hwrm_func_ptp_cfg_input req = {0}; 281 struct bnxt *bp = ptp->bp; 282 struct timespec64 ts; 283 u64 target_ns, delta; 284 u16 enables; 285 int rc; 286 287 ts.tv_sec = rq->perout.start.sec; 288 ts.tv_nsec = rq->perout.start.nsec; 289 target_ns = timespec64_to_ns(&ts); 290 291 rc = bnxt_get_target_cycles(ptp, target_ns, &delta); 292 if (rc) 293 return rc; 294 295 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_PTP_CFG, -1, -1); 296 297 enables = FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD | 298 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP | 299 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE; 300 req.enables = cpu_to_le16(enables); 301 req.ptp_pps_event = 0; 302 req.ptp_freq_adj_dll_source = 0; 303 req.ptp_freq_adj_dll_phase = 0; 304 req.ptp_freq_adj_ext_period = cpu_to_le32(NSEC_PER_SEC); 305 req.ptp_freq_adj_ext_up = 0; 306 req.ptp_freq_adj_ext_phase_lower = cpu_to_le32(delta); 307 308 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 309 } 310 311 static int bnxt_ptp_enable(struct ptp_clock_info *ptp_info, 312 struct ptp_clock_request *rq, int on) 313 { 314 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 315 ptp_info); 316 struct bnxt *bp = ptp->bp; 317 u8 pin_id; 318 int rc; 319 320 switch (rq->type) { 321 case PTP_CLK_REQ_EXTTS: 322 /* Configure an External PPS IN */ 323 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_EXTTS, 324 rq->extts.index); 325 if (!on) 326 break; 327 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_IN); 328 if (rc) 329 return rc; 330 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_EXTERNAL); 331 if (!rc) 332 ptp->pps_info.pins[pin_id].event = BNXT_PPS_EVENT_EXTERNAL; 333 return rc; 334 case PTP_CLK_REQ_PEROUT: 335 /* Configure a Periodic PPS OUT */ 336 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_PEROUT, 337 rq->perout.index); 338 if (!on) 339 break; 340 341 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_OUT); 342 if (!rc) 343 rc = bnxt_ptp_perout_cfg(ptp, rq); 344 345 return rc; 346 case PTP_CLK_REQ_PPS: 347 /* Configure PHC PPS IN */ 348 rc = bnxt_ptp_cfg_pin(bp, 0, BNXT_PPS_PIN_PPS_IN); 349 if (rc) 350 return rc; 351 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_INTERNAL); 352 if (!rc) 353 ptp->pps_info.pins[0].event = BNXT_PPS_EVENT_INTERNAL; 354 return rc; 355 default: 356 netdev_err(ptp->bp->dev, "Unrecognized PIN function\n"); 357 return -EOPNOTSUPP; 358 } 359 360 return bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_NONE); 361 } 362 363 static int bnxt_hwrm_ptp_cfg(struct bnxt *bp) 364 { 365 struct hwrm_port_mac_cfg_input req = {0}; 366 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 367 u32 flags = 0; 368 369 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_MAC_CFG, -1, -1); 370 if (ptp->rx_filter) 371 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE; 372 else 373 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE; 374 if (ptp->tx_tstamp_en) 375 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE; 376 else 377 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE; 378 req.flags = cpu_to_le32(flags); 379 req.enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE); 380 req.rx_ts_capture_ptp_msg_type = cpu_to_le16(ptp->rxctl); 381 382 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 383 } 384 385 int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 386 { 387 struct bnxt *bp = netdev_priv(dev); 388 struct hwtstamp_config stmpconf; 389 struct bnxt_ptp_cfg *ptp; 390 u16 old_rxctl; 391 int old_rx_filter, rc; 392 u8 old_tx_tstamp_en; 393 394 ptp = bp->ptp_cfg; 395 if (!ptp) 396 return -EOPNOTSUPP; 397 398 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf))) 399 return -EFAULT; 400 401 if (stmpconf.flags) 402 return -EINVAL; 403 404 if (stmpconf.tx_type != HWTSTAMP_TX_ON && 405 stmpconf.tx_type != HWTSTAMP_TX_OFF) 406 return -ERANGE; 407 408 old_rx_filter = ptp->rx_filter; 409 old_rxctl = ptp->rxctl; 410 old_tx_tstamp_en = ptp->tx_tstamp_en; 411 switch (stmpconf.rx_filter) { 412 case HWTSTAMP_FILTER_NONE: 413 ptp->rxctl = 0; 414 ptp->rx_filter = HWTSTAMP_FILTER_NONE; 415 break; 416 case HWTSTAMP_FILTER_PTP_V2_EVENT: 417 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 418 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 419 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 420 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 421 break; 422 case HWTSTAMP_FILTER_PTP_V2_SYNC: 423 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 424 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 425 ptp->rxctl = BNXT_PTP_MSG_SYNC; 426 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 427 break; 428 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 429 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 430 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 431 ptp->rxctl = BNXT_PTP_MSG_DELAY_REQ; 432 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 433 break; 434 default: 435 return -ERANGE; 436 } 437 438 if (stmpconf.tx_type == HWTSTAMP_TX_ON) 439 ptp->tx_tstamp_en = 1; 440 else 441 ptp->tx_tstamp_en = 0; 442 443 rc = bnxt_hwrm_ptp_cfg(bp); 444 if (rc) 445 goto ts_set_err; 446 447 stmpconf.rx_filter = ptp->rx_filter; 448 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? 449 -EFAULT : 0; 450 451 ts_set_err: 452 ptp->rx_filter = old_rx_filter; 453 ptp->rxctl = old_rxctl; 454 ptp->tx_tstamp_en = old_tx_tstamp_en; 455 return rc; 456 } 457 458 int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 459 { 460 struct bnxt *bp = netdev_priv(dev); 461 struct hwtstamp_config stmpconf; 462 struct bnxt_ptp_cfg *ptp; 463 464 ptp = bp->ptp_cfg; 465 if (!ptp) 466 return -EOPNOTSUPP; 467 468 stmpconf.flags = 0; 469 stmpconf.tx_type = ptp->tx_tstamp_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 470 471 stmpconf.rx_filter = ptp->rx_filter; 472 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? 473 -EFAULT : 0; 474 } 475 476 static int bnxt_map_regs(struct bnxt *bp, u32 *reg_arr, int count, int reg_win) 477 { 478 u32 reg_base = *reg_arr & BNXT_GRC_BASE_MASK; 479 u32 win_off; 480 int i; 481 482 for (i = 0; i < count; i++) { 483 if ((reg_arr[i] & BNXT_GRC_BASE_MASK) != reg_base) 484 return -ERANGE; 485 } 486 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 487 writel(reg_base, bp->bar0 + win_off); 488 return 0; 489 } 490 491 static int bnxt_map_ptp_regs(struct bnxt *bp) 492 { 493 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 494 u32 *reg_arr; 495 int rc, i; 496 497 reg_arr = ptp->refclk_regs; 498 if (bp->flags & BNXT_FLAG_CHIP_P5) { 499 rc = bnxt_map_regs(bp, reg_arr, 2, BNXT_PTP_GRC_WIN); 500 if (rc) 501 return rc; 502 for (i = 0; i < 2; i++) 503 ptp->refclk_mapped_regs[i] = BNXT_PTP_GRC_WIN_BASE + 504 (ptp->refclk_regs[i] & BNXT_GRC_OFFSET_MASK); 505 return 0; 506 } 507 return -ENODEV; 508 } 509 510 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 511 { 512 writel(0, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 513 (BNXT_PTP_GRC_WIN - 1) * 4); 514 } 515 516 static u64 bnxt_cc_read(const struct cyclecounter *cc) 517 { 518 struct bnxt_ptp_cfg *ptp = container_of(cc, struct bnxt_ptp_cfg, cc); 519 u64 ns = 0; 520 521 bnxt_refclk_read(ptp->bp, NULL, &ns); 522 return ns; 523 } 524 525 static void bnxt_stamp_tx_skb(struct bnxt *bp, struct sk_buff *skb) 526 { 527 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 528 struct skb_shared_hwtstamps timestamp; 529 u64 ts = 0, ns = 0; 530 int rc; 531 532 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_PATH_TX, &ts); 533 if (!rc) { 534 memset(×tamp, 0, sizeof(timestamp)); 535 spin_lock_bh(&ptp->ptp_lock); 536 ns = timecounter_cyc2time(&ptp->tc, ts); 537 spin_unlock_bh(&ptp->ptp_lock); 538 timestamp.hwtstamp = ns_to_ktime(ns); 539 skb_tstamp_tx(ptp->tx_skb, ×tamp); 540 } else { 541 netdev_err(bp->dev, "TS query for TX timer failed rc = %x\n", 542 rc); 543 } 544 545 dev_kfree_skb_any(ptp->tx_skb); 546 ptp->tx_skb = NULL; 547 atomic_inc(&ptp->tx_avail); 548 } 549 550 static long bnxt_ptp_ts_aux_work(struct ptp_clock_info *ptp_info) 551 { 552 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 553 ptp_info); 554 unsigned long now = jiffies; 555 struct bnxt *bp = ptp->bp; 556 557 if (ptp->tx_skb) 558 bnxt_stamp_tx_skb(bp, ptp->tx_skb); 559 560 if (!time_after_eq(now, ptp->next_period)) 561 return ptp->next_period - now; 562 563 bnxt_ptp_get_current_time(bp); 564 ptp->next_period = now + HZ; 565 if (time_after_eq(now, ptp->next_overflow_check)) { 566 spin_lock_bh(&ptp->ptp_lock); 567 timecounter_read(&ptp->tc); 568 spin_unlock_bh(&ptp->ptp_lock); 569 ptp->next_overflow_check = now + BNXT_PHC_OVERFLOW_PERIOD; 570 } 571 return HZ; 572 } 573 574 int bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb) 575 { 576 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 577 578 if (ptp->tx_skb) { 579 netdev_err(bp->dev, "deferring skb:one SKB is still outstanding\n"); 580 return -EBUSY; 581 } 582 ptp->tx_skb = skb; 583 ptp_schedule_worker(ptp->ptp_clock, 0); 584 return 0; 585 } 586 587 int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts) 588 { 589 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 590 u64 time; 591 592 if (!ptp) 593 return -ENODEV; 594 595 BNXT_READ_TIME64(ptp, time, ptp->old_time); 596 *ts = (time & BNXT_HI_TIMER_MASK) | pkt_ts; 597 if (pkt_ts < (time & BNXT_LO_TIMER_MASK)) 598 *ts += BNXT_LO_TIMER_MASK + 1; 599 600 return 0; 601 } 602 603 static const struct ptp_clock_info bnxt_ptp_caps = { 604 .owner = THIS_MODULE, 605 .name = "bnxt clock", 606 .max_adj = BNXT_MAX_PHC_DRIFT, 607 .n_alarm = 0, 608 .n_ext_ts = 0, 609 .n_per_out = 0, 610 .n_pins = 0, 611 .pps = 0, 612 .adjfreq = bnxt_ptp_adjfreq, 613 .adjtime = bnxt_ptp_adjtime, 614 .do_aux_work = bnxt_ptp_ts_aux_work, 615 .gettimex64 = bnxt_ptp_gettimex, 616 .settime64 = bnxt_ptp_settime, 617 .enable = bnxt_ptp_enable, 618 }; 619 620 static int bnxt_ptp_verify(struct ptp_clock_info *ptp_info, unsigned int pin, 621 enum ptp_pin_function func, unsigned int chan) 622 { 623 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 624 ptp_info); 625 /* Allow only PPS pin function configuration */ 626 if (ptp->pps_info.pins[pin].usage <= BNXT_PPS_PIN_PPS_OUT && 627 func != PTP_PF_PHYSYNC) 628 return 0; 629 else 630 return -EOPNOTSUPP; 631 } 632 633 /* bp->hwrm_cmd_lock held by the caller */ 634 static int bnxt_ptp_pps_init(struct bnxt *bp) 635 { 636 struct hwrm_func_ptp_pin_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 637 struct hwrm_func_ptp_pin_qcfg_input req = {0}; 638 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 639 struct ptp_clock_info *ptp_info; 640 struct bnxt_pps *pps_info; 641 u8 *pin_usg; 642 u32 i, rc; 643 644 /* Query current/default PIN CFG */ 645 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_PTP_PIN_QCFG, -1, -1); 646 647 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 648 if (rc || !resp->num_pins) 649 return -EOPNOTSUPP; 650 651 ptp_info = &ptp->ptp_info; 652 pps_info = &ptp->pps_info; 653 pps_info->num_pins = resp->num_pins; 654 ptp_info->n_pins = pps_info->num_pins; 655 ptp_info->pin_config = kcalloc(ptp_info->n_pins, 656 sizeof(*ptp_info->pin_config), 657 GFP_KERNEL); 658 if (!ptp_info->pin_config) 659 return -ENOMEM; 660 661 /* Report the TSIO capability to kernel */ 662 pin_usg = &resp->pin0_usage; 663 for (i = 0; i < pps_info->num_pins; i++, pin_usg++) { 664 snprintf(ptp_info->pin_config[i].name, 665 sizeof(ptp_info->pin_config[i].name), "bnxt_pps%d", i); 666 ptp_info->pin_config[i].index = i; 667 ptp_info->pin_config[i].chan = i; 668 if (*pin_usg == BNXT_PPS_PIN_PPS_IN) 669 ptp_info->pin_config[i].func = PTP_PF_EXTTS; 670 else if (*pin_usg == BNXT_PPS_PIN_PPS_OUT) 671 ptp_info->pin_config[i].func = PTP_PF_PEROUT; 672 else 673 ptp_info->pin_config[i].func = PTP_PF_NONE; 674 675 pps_info->pins[i].usage = *pin_usg; 676 } 677 678 /* Only 1 each of ext_ts and per_out pins is available in HW */ 679 ptp_info->n_ext_ts = 1; 680 ptp_info->n_per_out = 1; 681 ptp_info->pps = 1; 682 ptp_info->verify = bnxt_ptp_verify; 683 684 return 0; 685 } 686 687 static bool bnxt_pps_config_ok(struct bnxt *bp) 688 { 689 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 690 691 return !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) == !ptp->ptp_info.pin_config; 692 } 693 694 int bnxt_ptp_init(struct bnxt *bp) 695 { 696 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 697 int rc; 698 699 if (!ptp) 700 return 0; 701 702 rc = bnxt_map_ptp_regs(bp); 703 if (rc) 704 return rc; 705 706 if (ptp->ptp_clock && bnxt_pps_config_ok(bp)) 707 return 0; 708 709 if (ptp->ptp_clock) { 710 ptp_clock_unregister(ptp->ptp_clock); 711 ptp->ptp_clock = NULL; 712 kfree(ptp->ptp_info.pin_config); 713 ptp->ptp_info.pin_config = NULL; 714 } 715 atomic_set(&ptp->tx_avail, BNXT_MAX_TX_TS); 716 spin_lock_init(&ptp->ptp_lock); 717 718 memset(&ptp->cc, 0, sizeof(ptp->cc)); 719 ptp->cc.read = bnxt_cc_read; 720 ptp->cc.mask = CYCLECOUNTER_MASK(48); 721 ptp->cc.shift = 0; 722 ptp->cc.mult = 1; 723 724 ptp->next_overflow_check = jiffies + BNXT_PHC_OVERFLOW_PERIOD; 725 timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real())); 726 727 ptp->ptp_info = bnxt_ptp_caps; 728 if ((bp->fw_cap & BNXT_FW_CAP_PTP_PPS)) { 729 if (bnxt_ptp_pps_init(bp)) 730 netdev_err(bp->dev, "1pps not initialized, continuing without 1pps support\n"); 731 } 732 ptp->ptp_clock = ptp_clock_register(&ptp->ptp_info, &bp->pdev->dev); 733 if (IS_ERR(ptp->ptp_clock)) { 734 int err = PTR_ERR(ptp->ptp_clock); 735 736 ptp->ptp_clock = NULL; 737 bnxt_unmap_ptp_regs(bp); 738 return err; 739 } 740 if (bp->flags & BNXT_FLAG_CHIP_P5) { 741 spin_lock_bh(&ptp->ptp_lock); 742 bnxt_refclk_read(bp, NULL, &ptp->current_time); 743 WRITE_ONCE(ptp->old_time, ptp->current_time); 744 spin_unlock_bh(&ptp->ptp_lock); 745 ptp_schedule_worker(ptp->ptp_clock, 0); 746 } 747 return 0; 748 } 749 750 void bnxt_ptp_clear(struct bnxt *bp) 751 { 752 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 753 754 if (!ptp) 755 return; 756 757 if (ptp->ptp_clock) 758 ptp_clock_unregister(ptp->ptp_clock); 759 760 ptp->ptp_clock = NULL; 761 kfree(ptp->ptp_info.pin_config); 762 ptp->ptp_info.pin_config = NULL; 763 764 if (ptp->tx_skb) { 765 dev_kfree_skb_any(ptp->tx_skb); 766 ptp->tx_skb = NULL; 767 } 768 bnxt_unmap_ptp_regs(bp); 769 } 770