1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2021 Broadcom Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 #include <linux/kernel.h> 10 #include <linux/errno.h> 11 #include <linux/pci.h> 12 #include <linux/netdevice.h> 13 #include <linux/etherdevice.h> 14 #include <linux/net_tstamp.h> 15 #include <linux/timekeeping.h> 16 #include <linux/ptp_classify.h> 17 #include <linux/clocksource.h> 18 #include "bnxt_hsi.h" 19 #include "bnxt.h" 20 #include "bnxt_hwrm.h" 21 #include "bnxt_ptp.h" 22 23 static int bnxt_ptp_cfg_settime(struct bnxt *bp, u64 time) 24 { 25 struct hwrm_func_ptp_cfg_input *req; 26 int rc; 27 28 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG); 29 if (rc) 30 return rc; 31 32 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME); 33 req->ptp_set_time = cpu_to_le64(time); 34 return hwrm_req_send(bp, req); 35 } 36 37 int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off) 38 { 39 unsigned int ptp_class; 40 struct ptp_header *hdr; 41 42 ptp_class = ptp_classify_raw(skb); 43 44 switch (ptp_class & PTP_CLASS_VMASK) { 45 case PTP_CLASS_V1: 46 case PTP_CLASS_V2: 47 hdr = ptp_parse_header(skb, ptp_class); 48 if (!hdr) 49 return -EINVAL; 50 51 *hdr_off = (u8 *)hdr - skb->data; 52 *seq_id = ntohs(hdr->sequence_id); 53 return 0; 54 default: 55 return -ERANGE; 56 } 57 } 58 59 static int bnxt_ptp_settime(struct ptp_clock_info *ptp_info, 60 const struct timespec64 *ts) 61 { 62 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 63 ptp_info); 64 u64 ns = timespec64_to_ns(ts); 65 unsigned long flags; 66 67 if (BNXT_PTP_USE_RTC(ptp->bp)) 68 return bnxt_ptp_cfg_settime(ptp->bp, ns); 69 70 write_seqlock_irqsave(&ptp->ptp_lock, flags); 71 timecounter_init(&ptp->tc, &ptp->cc, ns); 72 write_sequnlock_irqrestore(&ptp->ptp_lock, flags); 73 return 0; 74 } 75 76 /* Caller holds ptp_lock */ 77 static int __bnxt_refclk_read(struct bnxt *bp, struct ptp_system_timestamp *sts, 78 u64 *ns) 79 { 80 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 81 u32 high_before, high_now, low; 82 83 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 84 return -EIO; 85 86 high_before = readl(bp->bar0 + ptp->refclk_mapped_regs[1]); 87 ptp_read_system_prets(sts); 88 low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]); 89 ptp_read_system_postts(sts); 90 high_now = readl(bp->bar0 + ptp->refclk_mapped_regs[1]); 91 if (high_now != high_before) { 92 ptp_read_system_prets(sts); 93 low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]); 94 ptp_read_system_postts(sts); 95 } 96 *ns = ((u64)high_now << 32) | low; 97 98 return 0; 99 } 100 101 static int bnxt_refclk_read(struct bnxt *bp, struct ptp_system_timestamp *sts, 102 u64 *ns) 103 { 104 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 105 unsigned long flags; 106 int rc; 107 108 /* We have to serialize reg access and FW reset */ 109 read_seqlock_excl_irqsave(&ptp->ptp_lock, flags); 110 rc = __bnxt_refclk_read(bp, sts, ns); 111 read_sequnlock_excl_irqrestore(&ptp->ptp_lock, flags); 112 return rc; 113 } 114 115 static void bnxt_ptp_get_current_time(struct bnxt *bp) 116 { 117 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 118 119 if (!ptp) 120 return; 121 WRITE_ONCE(ptp->old_time, ptp->current_time >> BNXT_HI_TIMER_SHIFT); 122 bnxt_refclk_read(bp, NULL, &ptp->current_time); 123 } 124 125 static int bnxt_hwrm_port_ts_query(struct bnxt *bp, u32 flags, u64 *ts, 126 u32 txts_tmo, int slot) 127 { 128 struct hwrm_port_ts_query_output *resp; 129 struct hwrm_port_ts_query_input *req; 130 int rc; 131 132 rc = hwrm_req_init(bp, req, HWRM_PORT_TS_QUERY); 133 if (rc) 134 return rc; 135 136 req->flags = cpu_to_le32(flags); 137 if ((flags & PORT_TS_QUERY_REQ_FLAGS_PATH) == 138 PORT_TS_QUERY_REQ_FLAGS_PATH_TX) { 139 struct bnxt_ptp_tx_req *txts_req = &bp->ptp_cfg->txts_req[slot]; 140 u32 tmo_us = txts_tmo * 1000; 141 142 req->enables = cpu_to_le16(BNXT_PTP_QTS_TX_ENABLES); 143 req->ptp_seq_id = cpu_to_le32(txts_req->tx_seqid); 144 req->ptp_hdr_offset = cpu_to_le16(txts_req->tx_hdr_off); 145 if (!tmo_us) 146 tmo_us = BNXT_PTP_QTS_TIMEOUT; 147 tmo_us = min(tmo_us, BNXT_PTP_QTS_MAX_TMO_US); 148 req->ts_req_timeout = cpu_to_le16(tmo_us); 149 } 150 resp = hwrm_req_hold(bp, req); 151 152 rc = hwrm_req_send_silent(bp, req); 153 if (!rc) 154 *ts = le64_to_cpu(resp->ptp_msg_ts); 155 hwrm_req_drop(bp, req); 156 return rc; 157 } 158 159 static int bnxt_ptp_gettimex(struct ptp_clock_info *ptp_info, 160 struct timespec64 *ts, 161 struct ptp_system_timestamp *sts) 162 { 163 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 164 ptp_info); 165 u64 ns, cycles; 166 int rc; 167 168 rc = bnxt_refclk_read(ptp->bp, sts, &cycles); 169 if (rc) 170 return rc; 171 172 ns = bnxt_timecounter_cyc2time(ptp, cycles); 173 *ts = ns_to_timespec64(ns); 174 175 return 0; 176 } 177 178 void bnxt_ptp_update_current_time(struct bnxt *bp) 179 { 180 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 181 182 bnxt_refclk_read(ptp->bp, NULL, &ptp->current_time); 183 WRITE_ONCE(ptp->old_time, ptp->current_time >> BNXT_HI_TIMER_SHIFT); 184 } 185 186 static int bnxt_ptp_adjphc(struct bnxt_ptp_cfg *ptp, s64 delta) 187 { 188 struct hwrm_port_mac_cfg_input *req; 189 int rc; 190 191 rc = hwrm_req_init(ptp->bp, req, HWRM_PORT_MAC_CFG); 192 if (rc) 193 return rc; 194 195 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE); 196 req->ptp_adj_phase = cpu_to_le64(delta); 197 198 rc = hwrm_req_send(ptp->bp, req); 199 if (rc) { 200 netdev_err(ptp->bp->dev, "ptp adjphc failed. rc = %x\n", rc); 201 } else { 202 bnxt_ptp_update_current_time(ptp->bp); 203 } 204 205 return rc; 206 } 207 208 static int bnxt_ptp_adjtime(struct ptp_clock_info *ptp_info, s64 delta) 209 { 210 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 211 ptp_info); 212 unsigned long flags; 213 214 if (BNXT_PTP_USE_RTC(ptp->bp)) 215 return bnxt_ptp_adjphc(ptp, delta); 216 217 write_seqlock_irqsave(&ptp->ptp_lock, flags); 218 timecounter_adjtime(&ptp->tc, delta); 219 write_sequnlock_irqrestore(&ptp->ptp_lock, flags); 220 return 0; 221 } 222 223 static int bnxt_ptp_adjfine_rtc(struct bnxt *bp, long scaled_ppm) 224 { 225 s32 ppb = scaled_ppm_to_ppb(scaled_ppm); 226 struct hwrm_port_mac_cfg_input *req; 227 int rc; 228 229 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 230 if (rc) 231 return rc; 232 233 req->ptp_freq_adj_ppb = cpu_to_le32(ppb); 234 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB); 235 rc = hwrm_req_send(bp, req); 236 if (rc) 237 netdev_err(bp->dev, 238 "ptp adjfine failed. rc = %d\n", rc); 239 return rc; 240 } 241 242 static int bnxt_ptp_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm) 243 { 244 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 245 ptp_info); 246 struct bnxt *bp = ptp->bp; 247 unsigned long flags; 248 249 if (!BNXT_MH(bp)) 250 return bnxt_ptp_adjfine_rtc(bp, scaled_ppm); 251 252 write_seqlock_irqsave(&ptp->ptp_lock, flags); 253 timecounter_read(&ptp->tc); 254 ptp->cc.mult = adjust_by_scaled_ppm(ptp->cmult, scaled_ppm); 255 write_sequnlock_irqrestore(&ptp->ptp_lock, flags); 256 return 0; 257 } 258 259 void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2) 260 { 261 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 262 struct ptp_clock_event event; 263 u64 ns, pps_ts; 264 265 pps_ts = EVENT_PPS_TS(data2, data1); 266 ns = bnxt_timecounter_cyc2time(ptp, pps_ts); 267 268 switch (EVENT_DATA2_PPS_EVENT_TYPE(data2)) { 269 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL: 270 event.pps_times.ts_real = ns_to_timespec64(ns); 271 event.type = PTP_CLOCK_PPSUSR; 272 event.index = EVENT_DATA2_PPS_PIN_NUM(data2); 273 break; 274 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL: 275 event.timestamp = ns; 276 event.type = PTP_CLOCK_EXTTS; 277 event.index = EVENT_DATA2_PPS_PIN_NUM(data2); 278 break; 279 } 280 281 ptp_clock_event(bp->ptp_cfg->ptp_clock, &event); 282 } 283 284 static int bnxt_ptp_cfg_pin(struct bnxt *bp, u8 pin, u8 usage) 285 { 286 struct hwrm_func_ptp_pin_cfg_input *req; 287 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 288 u8 state = usage != BNXT_PPS_PIN_NONE; 289 u8 *pin_state, *pin_usg; 290 u32 enables; 291 int rc; 292 293 if (!TSIO_PIN_VALID(pin)) { 294 netdev_err(ptp->bp->dev, "1PPS: Invalid pin. Check pin-function configuration\n"); 295 return -EOPNOTSUPP; 296 } 297 298 rc = hwrm_req_init(ptp->bp, req, HWRM_FUNC_PTP_PIN_CFG); 299 if (rc) 300 return rc; 301 302 enables = (FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE | 303 FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE) << (pin * 2); 304 req->enables = cpu_to_le32(enables); 305 306 pin_state = &req->pin0_state; 307 pin_usg = &req->pin0_usage; 308 309 *(pin_state + (pin * 2)) = state; 310 *(pin_usg + (pin * 2)) = usage; 311 312 rc = hwrm_req_send(ptp->bp, req); 313 if (rc) 314 return rc; 315 316 ptp->pps_info.pins[pin].usage = usage; 317 ptp->pps_info.pins[pin].state = state; 318 319 return 0; 320 } 321 322 static int bnxt_ptp_cfg_event(struct bnxt *bp, u8 event) 323 { 324 struct hwrm_func_ptp_cfg_input *req; 325 int rc; 326 327 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG); 328 if (rc) 329 return rc; 330 331 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT); 332 req->ptp_pps_event = event; 333 return hwrm_req_send(bp, req); 334 } 335 336 int bnxt_ptp_cfg_tstamp_filters(struct bnxt *bp) 337 { 338 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 339 struct hwrm_port_mac_cfg_input *req; 340 int rc; 341 342 if (!ptp || !ptp->tstamp_filters) 343 return -EIO; 344 345 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 346 if (rc) 347 goto out; 348 349 if (!(bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) && (ptp->tstamp_filters & 350 (PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE | 351 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE))) { 352 ptp->tstamp_filters &= ~(PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE | 353 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE); 354 netdev_warn(bp->dev, "Unsupported FW for all RX pkts timestamp filter\n"); 355 } 356 357 req->flags = cpu_to_le32(ptp->tstamp_filters); 358 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE); 359 req->rx_ts_capture_ptp_msg_type = cpu_to_le16(ptp->rxctl); 360 361 rc = hwrm_req_send(bp, req); 362 if (!rc) { 363 bp->ptp_all_rx_tstamp = !!(ptp->tstamp_filters & 364 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE); 365 return 0; 366 } 367 ptp->tstamp_filters = 0; 368 out: 369 bp->ptp_all_rx_tstamp = 0; 370 netdev_warn(bp->dev, "Failed to configure HW packet timestamp filters\n"); 371 return rc; 372 } 373 374 void bnxt_ptp_reapply_pps(struct bnxt *bp) 375 { 376 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 377 struct bnxt_pps *pps; 378 u32 pin = 0; 379 int rc; 380 381 if (!ptp || !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) || 382 !(ptp->ptp_info.pin_config)) 383 return; 384 pps = &ptp->pps_info; 385 for (pin = 0; pin < BNXT_MAX_TSIO_PINS; pin++) { 386 if (pps->pins[pin].state) { 387 rc = bnxt_ptp_cfg_pin(bp, pin, pps->pins[pin].usage); 388 if (!rc && pps->pins[pin].event) 389 rc = bnxt_ptp_cfg_event(bp, 390 pps->pins[pin].event); 391 if (rc) 392 netdev_err(bp->dev, "1PPS: Failed to configure pin%d\n", 393 pin); 394 } 395 } 396 } 397 398 static int bnxt_get_target_cycles(struct bnxt_ptp_cfg *ptp, u64 target_ns, 399 u64 *cycles_delta) 400 { 401 u64 cycles_now; 402 u64 nsec_now, nsec_delta; 403 int rc; 404 405 rc = bnxt_refclk_read(ptp->bp, NULL, &cycles_now); 406 if (rc) 407 return rc; 408 409 nsec_now = bnxt_timecounter_cyc2time(ptp, cycles_now); 410 411 nsec_delta = target_ns - nsec_now; 412 *cycles_delta = div64_u64(nsec_delta << ptp->cc.shift, ptp->cc.mult); 413 return 0; 414 } 415 416 static int bnxt_ptp_perout_cfg(struct bnxt_ptp_cfg *ptp, 417 struct ptp_clock_request *rq) 418 { 419 struct hwrm_func_ptp_cfg_input *req; 420 struct bnxt *bp = ptp->bp; 421 struct timespec64 ts; 422 u64 target_ns, delta; 423 u16 enables; 424 int rc; 425 426 ts.tv_sec = rq->perout.start.sec; 427 ts.tv_nsec = rq->perout.start.nsec; 428 target_ns = timespec64_to_ns(&ts); 429 430 rc = bnxt_get_target_cycles(ptp, target_ns, &delta); 431 if (rc) 432 return rc; 433 434 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG); 435 if (rc) 436 return rc; 437 438 enables = FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD | 439 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP | 440 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE; 441 req->enables = cpu_to_le16(enables); 442 req->ptp_pps_event = 0; 443 req->ptp_freq_adj_dll_source = 0; 444 req->ptp_freq_adj_dll_phase = 0; 445 req->ptp_freq_adj_ext_period = cpu_to_le32(NSEC_PER_SEC); 446 req->ptp_freq_adj_ext_up = 0; 447 req->ptp_freq_adj_ext_phase_lower = cpu_to_le32(delta); 448 449 return hwrm_req_send(bp, req); 450 } 451 452 static int bnxt_ptp_enable(struct ptp_clock_info *ptp_info, 453 struct ptp_clock_request *rq, int on) 454 { 455 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 456 ptp_info); 457 struct bnxt *bp = ptp->bp; 458 int pin_id; 459 int rc; 460 461 switch (rq->type) { 462 case PTP_CLK_REQ_EXTTS: 463 /* Configure an External PPS IN */ 464 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_EXTTS, 465 rq->extts.index); 466 if (!TSIO_PIN_VALID(pin_id)) 467 return -EOPNOTSUPP; 468 if (!on) 469 break; 470 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_IN); 471 if (rc) 472 return rc; 473 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_EXTERNAL); 474 if (!rc) 475 ptp->pps_info.pins[pin_id].event = BNXT_PPS_EVENT_EXTERNAL; 476 return rc; 477 case PTP_CLK_REQ_PEROUT: 478 /* Configure a Periodic PPS OUT */ 479 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_PEROUT, 480 rq->perout.index); 481 if (!TSIO_PIN_VALID(pin_id)) 482 return -EOPNOTSUPP; 483 if (!on) 484 break; 485 486 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_OUT); 487 if (!rc) 488 rc = bnxt_ptp_perout_cfg(ptp, rq); 489 490 return rc; 491 case PTP_CLK_REQ_PPS: 492 /* Configure PHC PPS IN */ 493 rc = bnxt_ptp_cfg_pin(bp, 0, BNXT_PPS_PIN_PPS_IN); 494 if (rc) 495 return rc; 496 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_INTERNAL); 497 if (!rc) 498 ptp->pps_info.pins[0].event = BNXT_PPS_EVENT_INTERNAL; 499 return rc; 500 default: 501 netdev_err(ptp->bp->dev, "Unrecognized PIN function\n"); 502 return -EOPNOTSUPP; 503 } 504 505 return bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_NONE); 506 } 507 508 static int bnxt_hwrm_ptp_cfg(struct bnxt *bp) 509 { 510 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 511 u32 flags = 0; 512 513 switch (ptp->rx_filter) { 514 case HWTSTAMP_FILTER_ALL: 515 flags = PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE; 516 break; 517 case HWTSTAMP_FILTER_NONE: 518 flags = PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE; 519 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) 520 flags |= PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE; 521 break; 522 case HWTSTAMP_FILTER_PTP_V2_EVENT: 523 case HWTSTAMP_FILTER_PTP_V2_SYNC: 524 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 525 flags = PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE; 526 break; 527 } 528 529 if (ptp->tx_tstamp_en) 530 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE; 531 else 532 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE; 533 534 ptp->tstamp_filters = flags; 535 536 return bnxt_ptp_cfg_tstamp_filters(bp); 537 } 538 539 int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 540 { 541 struct bnxt *bp = netdev_priv(dev); 542 struct hwtstamp_config stmpconf; 543 struct bnxt_ptp_cfg *ptp; 544 u16 old_rxctl; 545 int old_rx_filter, rc; 546 u8 old_tx_tstamp_en; 547 548 ptp = bp->ptp_cfg; 549 if (!ptp) 550 return -EOPNOTSUPP; 551 552 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf))) 553 return -EFAULT; 554 555 if (stmpconf.tx_type != HWTSTAMP_TX_ON && 556 stmpconf.tx_type != HWTSTAMP_TX_OFF) 557 return -ERANGE; 558 559 old_rx_filter = ptp->rx_filter; 560 old_rxctl = ptp->rxctl; 561 old_tx_tstamp_en = ptp->tx_tstamp_en; 562 switch (stmpconf.rx_filter) { 563 case HWTSTAMP_FILTER_NONE: 564 ptp->rxctl = 0; 565 ptp->rx_filter = HWTSTAMP_FILTER_NONE; 566 break; 567 case HWTSTAMP_FILTER_ALL: 568 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) { 569 ptp->rx_filter = HWTSTAMP_FILTER_ALL; 570 break; 571 } 572 return -EOPNOTSUPP; 573 case HWTSTAMP_FILTER_PTP_V2_EVENT: 574 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 575 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 576 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 577 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 578 break; 579 case HWTSTAMP_FILTER_PTP_V2_SYNC: 580 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 581 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 582 ptp->rxctl = BNXT_PTP_MSG_SYNC; 583 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 584 break; 585 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 586 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 587 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 588 ptp->rxctl = BNXT_PTP_MSG_DELAY_REQ; 589 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 590 break; 591 default: 592 return -ERANGE; 593 } 594 595 if (stmpconf.tx_type == HWTSTAMP_TX_ON) 596 ptp->tx_tstamp_en = 1; 597 else 598 ptp->tx_tstamp_en = 0; 599 600 rc = bnxt_hwrm_ptp_cfg(bp); 601 if (rc) 602 goto ts_set_err; 603 604 stmpconf.rx_filter = ptp->rx_filter; 605 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? 606 -EFAULT : 0; 607 608 ts_set_err: 609 ptp->rx_filter = old_rx_filter; 610 ptp->rxctl = old_rxctl; 611 ptp->tx_tstamp_en = old_tx_tstamp_en; 612 return rc; 613 } 614 615 int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 616 { 617 struct bnxt *bp = netdev_priv(dev); 618 struct hwtstamp_config stmpconf; 619 struct bnxt_ptp_cfg *ptp; 620 621 ptp = bp->ptp_cfg; 622 if (!ptp) 623 return -EOPNOTSUPP; 624 625 stmpconf.flags = 0; 626 stmpconf.tx_type = ptp->tx_tstamp_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 627 628 stmpconf.rx_filter = ptp->rx_filter; 629 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? 630 -EFAULT : 0; 631 } 632 633 static int bnxt_map_regs(struct bnxt *bp, u32 *reg_arr, int count, int reg_win) 634 { 635 u32 reg_base = *reg_arr & BNXT_GRC_BASE_MASK; 636 u32 win_off; 637 int i; 638 639 for (i = 0; i < count; i++) { 640 if ((reg_arr[i] & BNXT_GRC_BASE_MASK) != reg_base) 641 return -ERANGE; 642 } 643 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 644 writel(reg_base, bp->bar0 + win_off); 645 return 0; 646 } 647 648 static int bnxt_map_ptp_regs(struct bnxt *bp) 649 { 650 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 651 u32 *reg_arr; 652 int rc, i; 653 654 reg_arr = ptp->refclk_regs; 655 if (BNXT_CHIP_P5(bp)) { 656 rc = bnxt_map_regs(bp, reg_arr, 2, BNXT_PTP_GRC_WIN); 657 if (rc) 658 return rc; 659 for (i = 0; i < 2; i++) 660 ptp->refclk_mapped_regs[i] = BNXT_PTP_GRC_WIN_BASE + 661 (ptp->refclk_regs[i] & BNXT_GRC_OFFSET_MASK); 662 return 0; 663 } 664 if (bp->flags & BNXT_FLAG_CHIP_P7) { 665 for (i = 0; i < 2; i++) { 666 if (reg_arr[i] & BNXT_GRC_BASE_MASK) 667 return -EINVAL; 668 ptp->refclk_mapped_regs[i] = reg_arr[i]; 669 } 670 return 0; 671 } 672 return -ENODEV; 673 } 674 675 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 676 { 677 writel(0, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 678 (BNXT_PTP_GRC_WIN - 1) * 4); 679 } 680 681 static u64 bnxt_cc_read(const struct cyclecounter *cc) 682 { 683 struct bnxt_ptp_cfg *ptp = container_of(cc, struct bnxt_ptp_cfg, cc); 684 u64 ns = 0; 685 686 __bnxt_refclk_read(ptp->bp, NULL, &ns); 687 return ns; 688 } 689 690 static int bnxt_stamp_tx_skb(struct bnxt *bp, int slot) 691 { 692 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 693 struct skb_shared_hwtstamps timestamp; 694 struct bnxt_ptp_tx_req *txts_req; 695 unsigned long now = jiffies; 696 u64 ts = 0, ns = 0; 697 u32 tmo = 0; 698 int rc; 699 700 txts_req = &ptp->txts_req[slot]; 701 /* make sure bnxt_get_tx_ts_p5() has updated abs_txts_tmo */ 702 smp_rmb(); 703 if (!time_after_eq(now, txts_req->abs_txts_tmo)) 704 tmo = jiffies_to_msecs(txts_req->abs_txts_tmo - now); 705 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_PATH_TX, &ts, 706 tmo, slot); 707 if (!rc) { 708 memset(×tamp, 0, sizeof(timestamp)); 709 ns = bnxt_timecounter_cyc2time(ptp, ts); 710 timestamp.hwtstamp = ns_to_ktime(ns); 711 skb_tstamp_tx(txts_req->tx_skb, ×tamp); 712 ptp->stats.ts_pkts++; 713 } else { 714 if (!time_after_eq(jiffies, txts_req->abs_txts_tmo)) 715 return -EAGAIN; 716 717 ptp->stats.ts_lost++; 718 netdev_warn_once(bp->dev, 719 "TS query for TX timer failed rc = %x\n", rc); 720 } 721 722 dev_kfree_skb_any(txts_req->tx_skb); 723 txts_req->tx_skb = NULL; 724 725 return 0; 726 } 727 728 static long bnxt_ptp_ts_aux_work(struct ptp_clock_info *ptp_info) 729 { 730 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 731 ptp_info); 732 unsigned long now = jiffies; 733 struct bnxt *bp = ptp->bp; 734 u16 cons = ptp->txts_cons; 735 unsigned long flags; 736 u32 num_requests; 737 int rc = 0; 738 739 num_requests = BNXT_MAX_TX_TS - READ_ONCE(ptp->tx_avail); 740 while (num_requests--) { 741 if (IS_ERR(ptp->txts_req[cons].tx_skb)) 742 goto next_slot; 743 if (!ptp->txts_req[cons].tx_skb) 744 break; 745 rc = bnxt_stamp_tx_skb(bp, cons); 746 if (rc == -EAGAIN) 747 break; 748 next_slot: 749 BNXT_PTP_INC_TX_AVAIL(ptp); 750 cons = NEXT_TXTS(cons); 751 } 752 ptp->txts_cons = cons; 753 754 if (!time_after_eq(now, ptp->next_period)) { 755 if (rc == -EAGAIN) 756 return 0; 757 return ptp->next_period - now; 758 } 759 760 bnxt_ptp_get_current_time(bp); 761 ptp->next_period = now + HZ; 762 if (time_after_eq(now, ptp->next_overflow_check)) { 763 write_seqlock_irqsave(&ptp->ptp_lock, flags); 764 timecounter_read(&ptp->tc); 765 write_sequnlock_irqrestore(&ptp->ptp_lock, flags); 766 ptp->next_overflow_check = now + BNXT_PHC_OVERFLOW_PERIOD; 767 } 768 if (rc == -EAGAIN) 769 return 0; 770 return HZ; 771 } 772 773 int bnxt_ptp_get_txts_prod(struct bnxt_ptp_cfg *ptp, u16 *prod) 774 { 775 spin_lock_bh(&ptp->ptp_tx_lock); 776 if (ptp->tx_avail) { 777 *prod = ptp->txts_prod; 778 ptp->txts_prod = NEXT_TXTS(*prod); 779 ptp->tx_avail--; 780 spin_unlock_bh(&ptp->ptp_tx_lock); 781 return 0; 782 } 783 spin_unlock_bh(&ptp->ptp_tx_lock); 784 atomic64_inc(&ptp->stats.ts_err); 785 return -ENOSPC; 786 } 787 788 void bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb, u16 prod) 789 { 790 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 791 struct bnxt_ptp_tx_req *txts_req; 792 793 txts_req = &ptp->txts_req[prod]; 794 txts_req->abs_txts_tmo = jiffies + msecs_to_jiffies(ptp->txts_tmo); 795 /* make sure abs_txts_tmo is written first */ 796 smp_wmb(); 797 txts_req->tx_skb = skb; 798 ptp_schedule_worker(ptp->ptp_clock, 0); 799 } 800 801 int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts) 802 { 803 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 804 u64 time; 805 806 if (!ptp) 807 return -ENODEV; 808 809 time = (u64)READ_ONCE(ptp->old_time) << BNXT_HI_TIMER_SHIFT; 810 *ts = (time & BNXT_HI_TIMER_MASK) | pkt_ts; 811 if (pkt_ts < (time & BNXT_LO_TIMER_MASK)) 812 *ts += BNXT_LO_TIMER_MASK + 1; 813 814 return 0; 815 } 816 817 void bnxt_tx_ts_cmp(struct bnxt *bp, struct bnxt_napi *bnapi, 818 struct tx_ts_cmp *tscmp) 819 { 820 struct skb_shared_hwtstamps timestamp = {}; 821 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 822 u32 opaque = tscmp->tx_ts_cmp_opaque; 823 struct bnxt_tx_ring_info *txr; 824 struct bnxt_sw_tx_bd *tx_buf; 825 u64 ts, ns; 826 u16 cons; 827 828 txr = bnapi->tx_ring[TX_OPAQUE_RING(opaque)]; 829 ts = BNXT_GET_TX_TS_48B_NS(tscmp); 830 cons = TX_OPAQUE_IDX(opaque); 831 tx_buf = &txr->tx_buf_ring[RING_TX(bp, cons)]; 832 if (tx_buf->is_ts_pkt) { 833 if (BNXT_TX_TS_ERR(tscmp)) { 834 netdev_err(bp->dev, 835 "timestamp completion error 0x%x 0x%x\n", 836 le32_to_cpu(tscmp->tx_ts_cmp_flags_type), 837 le32_to_cpu(tscmp->tx_ts_cmp_errors_v)); 838 } else { 839 ns = bnxt_timecounter_cyc2time(ptp, ts); 840 timestamp.hwtstamp = ns_to_ktime(ns); 841 skb_tstamp_tx(tx_buf->skb, ×tamp); 842 } 843 tx_buf->is_ts_pkt = 0; 844 } 845 } 846 847 static const struct ptp_clock_info bnxt_ptp_caps = { 848 .owner = THIS_MODULE, 849 .name = "bnxt clock", 850 .max_adj = BNXT_MAX_PHC_DRIFT, 851 .n_alarm = 0, 852 .n_ext_ts = 0, 853 .n_per_out = 0, 854 .n_pins = 0, 855 .pps = 0, 856 .adjfine = bnxt_ptp_adjfine, 857 .adjtime = bnxt_ptp_adjtime, 858 .do_aux_work = bnxt_ptp_ts_aux_work, 859 .gettimex64 = bnxt_ptp_gettimex, 860 .settime64 = bnxt_ptp_settime, 861 .enable = bnxt_ptp_enable, 862 }; 863 864 static int bnxt_ptp_verify(struct ptp_clock_info *ptp_info, unsigned int pin, 865 enum ptp_pin_function func, unsigned int chan) 866 { 867 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 868 ptp_info); 869 /* Allow only PPS pin function configuration */ 870 if (ptp->pps_info.pins[pin].usage <= BNXT_PPS_PIN_PPS_OUT && 871 func != PTP_PF_PHYSYNC) 872 return 0; 873 else 874 return -EOPNOTSUPP; 875 } 876 877 static int bnxt_ptp_pps_init(struct bnxt *bp) 878 { 879 struct hwrm_func_ptp_pin_qcfg_output *resp; 880 struct hwrm_func_ptp_pin_qcfg_input *req; 881 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 882 struct ptp_clock_info *ptp_info; 883 struct bnxt_pps *pps_info; 884 u8 *pin_usg; 885 u32 i, rc; 886 887 /* Query current/default PIN CFG */ 888 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_PIN_QCFG); 889 if (rc) 890 return rc; 891 892 resp = hwrm_req_hold(bp, req); 893 rc = hwrm_req_send(bp, req); 894 if (rc || !resp->num_pins) { 895 hwrm_req_drop(bp, req); 896 return -EOPNOTSUPP; 897 } 898 899 ptp_info = &ptp->ptp_info; 900 pps_info = &ptp->pps_info; 901 pps_info->num_pins = resp->num_pins; 902 ptp_info->n_pins = pps_info->num_pins; 903 ptp_info->pin_config = kcalloc(ptp_info->n_pins, 904 sizeof(*ptp_info->pin_config), 905 GFP_KERNEL); 906 if (!ptp_info->pin_config) { 907 hwrm_req_drop(bp, req); 908 return -ENOMEM; 909 } 910 911 /* Report the TSIO capability to kernel */ 912 pin_usg = &resp->pin0_usage; 913 for (i = 0; i < pps_info->num_pins; i++, pin_usg++) { 914 snprintf(ptp_info->pin_config[i].name, 915 sizeof(ptp_info->pin_config[i].name), "bnxt_pps%d", i); 916 ptp_info->pin_config[i].index = i; 917 ptp_info->pin_config[i].chan = i; 918 if (*pin_usg == BNXT_PPS_PIN_PPS_IN) 919 ptp_info->pin_config[i].func = PTP_PF_EXTTS; 920 else if (*pin_usg == BNXT_PPS_PIN_PPS_OUT) 921 ptp_info->pin_config[i].func = PTP_PF_PEROUT; 922 else 923 ptp_info->pin_config[i].func = PTP_PF_NONE; 924 925 pps_info->pins[i].usage = *pin_usg; 926 } 927 hwrm_req_drop(bp, req); 928 929 /* Only 1 each of ext_ts and per_out pins is available in HW */ 930 ptp_info->n_ext_ts = 1; 931 ptp_info->n_per_out = 1; 932 ptp_info->pps = 1; 933 ptp_info->verify = bnxt_ptp_verify; 934 935 return 0; 936 } 937 938 static bool bnxt_pps_config_ok(struct bnxt *bp) 939 { 940 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 941 942 return !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) == !ptp->ptp_info.pin_config; 943 } 944 945 static void bnxt_ptp_timecounter_init(struct bnxt *bp, bool init_tc) 946 { 947 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 948 unsigned long flags; 949 950 if (!ptp->ptp_clock) { 951 memset(&ptp->cc, 0, sizeof(ptp->cc)); 952 ptp->cc.read = bnxt_cc_read; 953 ptp->cc.mask = CYCLECOUNTER_MASK(48); 954 if (BNXT_MH(bp)) { 955 /* Use timecounter based non-real time mode */ 956 ptp->cc.shift = BNXT_CYCLES_SHIFT; 957 ptp->cc.mult = clocksource_khz2mult(BNXT_DEVCLK_FREQ, ptp->cc.shift); 958 ptp->cmult = ptp->cc.mult; 959 } else { 960 ptp->cc.shift = 0; 961 ptp->cc.mult = 1; 962 } 963 ptp->next_overflow_check = jiffies + BNXT_PHC_OVERFLOW_PERIOD; 964 } 965 if (init_tc) { 966 write_seqlock_irqsave(&ptp->ptp_lock, flags); 967 timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real())); 968 write_sequnlock_irqrestore(&ptp->ptp_lock, flags); 969 } 970 } 971 972 /* Caller holds ptp_lock */ 973 void bnxt_ptp_rtc_timecounter_init(struct bnxt_ptp_cfg *ptp, u64 ns) 974 { 975 timecounter_init(&ptp->tc, &ptp->cc, ns); 976 /* For RTC, cycle_last must be in sync with the timecounter value. */ 977 ptp->tc.cycle_last = ns & ptp->cc.mask; 978 } 979 980 int bnxt_ptp_init_rtc(struct bnxt *bp, bool phc_cfg) 981 { 982 struct timespec64 tsp; 983 unsigned long flags; 984 u64 ns; 985 int rc; 986 987 if (!bp->ptp_cfg || !BNXT_PTP_USE_RTC(bp)) 988 return -ENODEV; 989 990 if (!phc_cfg) { 991 ktime_get_real_ts64(&tsp); 992 ns = timespec64_to_ns(&tsp); 993 rc = bnxt_ptp_cfg_settime(bp, ns); 994 if (rc) 995 return rc; 996 } else { 997 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME, 998 &ns, 0, 0); 999 if (rc) 1000 return rc; 1001 } 1002 write_seqlock_irqsave(&bp->ptp_cfg->ptp_lock, flags); 1003 bnxt_ptp_rtc_timecounter_init(bp->ptp_cfg, ns); 1004 write_sequnlock_irqrestore(&bp->ptp_cfg->ptp_lock, flags); 1005 1006 return 0; 1007 } 1008 1009 static void bnxt_ptp_free(struct bnxt *bp) 1010 { 1011 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 1012 1013 if (ptp->ptp_clock) { 1014 ptp_clock_unregister(ptp->ptp_clock); 1015 ptp->ptp_clock = NULL; 1016 kfree(ptp->ptp_info.pin_config); 1017 ptp->ptp_info.pin_config = NULL; 1018 } 1019 } 1020 1021 int bnxt_ptp_init(struct bnxt *bp, bool phc_cfg) 1022 { 1023 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 1024 int rc; 1025 1026 if (!ptp) 1027 return 0; 1028 1029 rc = bnxt_map_ptp_regs(bp); 1030 if (rc) 1031 return rc; 1032 1033 if (ptp->ptp_clock && bnxt_pps_config_ok(bp)) 1034 return 0; 1035 1036 bnxt_ptp_free(bp); 1037 1038 WRITE_ONCE(ptp->tx_avail, BNXT_MAX_TX_TS); 1039 seqlock_init(&ptp->ptp_lock); 1040 spin_lock_init(&ptp->ptp_tx_lock); 1041 1042 if (BNXT_PTP_USE_RTC(bp)) { 1043 bnxt_ptp_timecounter_init(bp, false); 1044 rc = bnxt_ptp_init_rtc(bp, phc_cfg); 1045 if (rc) 1046 goto out; 1047 } else { 1048 bnxt_ptp_timecounter_init(bp, true); 1049 bnxt_ptp_adjfine_rtc(bp, 0); 1050 } 1051 bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, true); 1052 1053 ptp->ptp_info = bnxt_ptp_caps; 1054 if ((bp->fw_cap & BNXT_FW_CAP_PTP_PPS)) { 1055 if (bnxt_ptp_pps_init(bp)) 1056 netdev_err(bp->dev, "1pps not initialized, continuing without 1pps support\n"); 1057 } 1058 ptp->ptp_clock = ptp_clock_register(&ptp->ptp_info, &bp->pdev->dev); 1059 if (IS_ERR(ptp->ptp_clock)) { 1060 int err = PTR_ERR(ptp->ptp_clock); 1061 1062 ptp->ptp_clock = NULL; 1063 rc = err; 1064 goto out; 1065 } 1066 1067 ptp->stats.ts_pkts = 0; 1068 ptp->stats.ts_lost = 0; 1069 atomic64_set(&ptp->stats.ts_err, 0); 1070 1071 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) { 1072 bnxt_refclk_read(bp, NULL, &ptp->current_time); 1073 WRITE_ONCE(ptp->old_time, ptp->current_time >> BNXT_HI_TIMER_SHIFT); 1074 ptp_schedule_worker(ptp->ptp_clock, 0); 1075 } 1076 ptp->txts_tmo = BNXT_PTP_DFLT_TX_TMO; 1077 return 0; 1078 1079 out: 1080 bnxt_ptp_free(bp); 1081 bnxt_unmap_ptp_regs(bp); 1082 return rc; 1083 } 1084 1085 void bnxt_ptp_clear(struct bnxt *bp) 1086 { 1087 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 1088 int i; 1089 1090 if (!ptp) 1091 return; 1092 1093 if (ptp->ptp_clock) 1094 ptp_clock_unregister(ptp->ptp_clock); 1095 1096 ptp->ptp_clock = NULL; 1097 kfree(ptp->ptp_info.pin_config); 1098 ptp->ptp_info.pin_config = NULL; 1099 1100 for (i = 0; i < BNXT_MAX_TX_TS; i++) { 1101 if (ptp->txts_req[i].tx_skb) { 1102 dev_kfree_skb_any(ptp->txts_req[i].tx_skb); 1103 ptp->txts_req[i].tx_skb = NULL; 1104 } 1105 } 1106 1107 bnxt_unmap_ptp_regs(bp); 1108 } 1109