1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2021 Broadcom Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 #include <linux/kernel.h> 10 #include <linux/errno.h> 11 #include <linux/pci.h> 12 #include <linux/netdevice.h> 13 #include <linux/etherdevice.h> 14 #include <linux/net_tstamp.h> 15 #include <linux/timekeeping.h> 16 #include <linux/ptp_classify.h> 17 #include <linux/clocksource.h> 18 #include "bnxt_hsi.h" 19 #include "bnxt.h" 20 #include "bnxt_hwrm.h" 21 #include "bnxt_ptp.h" 22 23 static int bnxt_ptp_cfg_settime(struct bnxt *bp, u64 time) 24 { 25 struct hwrm_func_ptp_cfg_input *req; 26 int rc; 27 28 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG); 29 if (rc) 30 return rc; 31 32 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME); 33 req->ptp_set_time = cpu_to_le64(time); 34 return hwrm_req_send(bp, req); 35 } 36 37 int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off) 38 { 39 unsigned int ptp_class; 40 struct ptp_header *hdr; 41 42 ptp_class = ptp_classify_raw(skb); 43 44 switch (ptp_class & PTP_CLASS_VMASK) { 45 case PTP_CLASS_V1: 46 case PTP_CLASS_V2: 47 hdr = ptp_parse_header(skb, ptp_class); 48 if (!hdr) 49 return -EINVAL; 50 51 *hdr_off = (u8 *)hdr - skb->data; 52 *seq_id = ntohs(hdr->sequence_id); 53 return 0; 54 default: 55 return -ERANGE; 56 } 57 } 58 59 static int bnxt_ptp_settime(struct ptp_clock_info *ptp_info, 60 const struct timespec64 *ts) 61 { 62 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 63 ptp_info); 64 u64 ns = timespec64_to_ns(ts); 65 66 if (BNXT_PTP_USE_RTC(ptp->bp)) 67 return bnxt_ptp_cfg_settime(ptp->bp, ns); 68 69 spin_lock_bh(&ptp->ptp_lock); 70 timecounter_init(&ptp->tc, &ptp->cc, ns); 71 spin_unlock_bh(&ptp->ptp_lock); 72 return 0; 73 } 74 75 /* Caller holds ptp_lock */ 76 static int bnxt_refclk_read(struct bnxt *bp, struct ptp_system_timestamp *sts, 77 u64 *ns) 78 { 79 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 80 u32 high_before, high_now, low; 81 82 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 83 return -EIO; 84 85 high_before = readl(bp->bar0 + ptp->refclk_mapped_regs[1]); 86 ptp_read_system_prets(sts); 87 low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]); 88 ptp_read_system_postts(sts); 89 high_now = readl(bp->bar0 + ptp->refclk_mapped_regs[1]); 90 if (high_now != high_before) { 91 ptp_read_system_prets(sts); 92 low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]); 93 ptp_read_system_postts(sts); 94 } 95 *ns = ((u64)high_now << 32) | low; 96 97 return 0; 98 } 99 100 static void bnxt_ptp_get_current_time(struct bnxt *bp) 101 { 102 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 103 104 if (!ptp) 105 return; 106 spin_lock_bh(&ptp->ptp_lock); 107 WRITE_ONCE(ptp->old_time, ptp->current_time); 108 bnxt_refclk_read(bp, NULL, &ptp->current_time); 109 spin_unlock_bh(&ptp->ptp_lock); 110 } 111 112 static int bnxt_hwrm_port_ts_query(struct bnxt *bp, u32 flags, u64 *ts, 113 u32 txts_tmo) 114 { 115 struct hwrm_port_ts_query_output *resp; 116 struct hwrm_port_ts_query_input *req; 117 int rc; 118 119 rc = hwrm_req_init(bp, req, HWRM_PORT_TS_QUERY); 120 if (rc) 121 return rc; 122 123 req->flags = cpu_to_le32(flags); 124 if ((flags & PORT_TS_QUERY_REQ_FLAGS_PATH) == 125 PORT_TS_QUERY_REQ_FLAGS_PATH_TX) { 126 u32 tmo_us = txts_tmo * 1000; 127 128 req->enables = cpu_to_le16(BNXT_PTP_QTS_TX_ENABLES); 129 req->ptp_seq_id = cpu_to_le32(bp->ptp_cfg->tx_seqid); 130 req->ptp_hdr_offset = cpu_to_le16(bp->ptp_cfg->tx_hdr_off); 131 if (!tmo_us) 132 tmo_us = BNXT_PTP_QTS_TIMEOUT; 133 tmo_us = min(tmo_us, BNXT_PTP_QTS_MAX_TMO_US); 134 req->ts_req_timeout = cpu_to_le16(tmo_us); 135 } 136 resp = hwrm_req_hold(bp, req); 137 138 rc = hwrm_req_send_silent(bp, req); 139 if (!rc) 140 *ts = le64_to_cpu(resp->ptp_msg_ts); 141 hwrm_req_drop(bp, req); 142 return rc; 143 } 144 145 static int bnxt_ptp_gettimex(struct ptp_clock_info *ptp_info, 146 struct timespec64 *ts, 147 struct ptp_system_timestamp *sts) 148 { 149 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 150 ptp_info); 151 u64 ns, cycles; 152 int rc; 153 154 spin_lock_bh(&ptp->ptp_lock); 155 rc = bnxt_refclk_read(ptp->bp, sts, &cycles); 156 if (rc) { 157 spin_unlock_bh(&ptp->ptp_lock); 158 return rc; 159 } 160 ns = timecounter_cyc2time(&ptp->tc, cycles); 161 spin_unlock_bh(&ptp->ptp_lock); 162 *ts = ns_to_timespec64(ns); 163 164 return 0; 165 } 166 167 /* Caller holds ptp_lock */ 168 void bnxt_ptp_update_current_time(struct bnxt *bp) 169 { 170 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 171 172 bnxt_refclk_read(ptp->bp, NULL, &ptp->current_time); 173 WRITE_ONCE(ptp->old_time, ptp->current_time); 174 } 175 176 static int bnxt_ptp_adjphc(struct bnxt_ptp_cfg *ptp, s64 delta) 177 { 178 struct hwrm_port_mac_cfg_input *req; 179 int rc; 180 181 rc = hwrm_req_init(ptp->bp, req, HWRM_PORT_MAC_CFG); 182 if (rc) 183 return rc; 184 185 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE); 186 req->ptp_adj_phase = cpu_to_le64(delta); 187 188 rc = hwrm_req_send(ptp->bp, req); 189 if (rc) { 190 netdev_err(ptp->bp->dev, "ptp adjphc failed. rc = %x\n", rc); 191 } else { 192 spin_lock_bh(&ptp->ptp_lock); 193 bnxt_ptp_update_current_time(ptp->bp); 194 spin_unlock_bh(&ptp->ptp_lock); 195 } 196 197 return rc; 198 } 199 200 static int bnxt_ptp_adjtime(struct ptp_clock_info *ptp_info, s64 delta) 201 { 202 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 203 ptp_info); 204 205 if (BNXT_PTP_USE_RTC(ptp->bp)) 206 return bnxt_ptp_adjphc(ptp, delta); 207 208 spin_lock_bh(&ptp->ptp_lock); 209 timecounter_adjtime(&ptp->tc, delta); 210 spin_unlock_bh(&ptp->ptp_lock); 211 return 0; 212 } 213 214 static int bnxt_ptp_adjfine_rtc(struct bnxt *bp, long scaled_ppm) 215 { 216 s32 ppb = scaled_ppm_to_ppb(scaled_ppm); 217 struct hwrm_port_mac_cfg_input *req; 218 int rc; 219 220 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 221 if (rc) 222 return rc; 223 224 req->ptp_freq_adj_ppb = cpu_to_le32(ppb); 225 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB); 226 rc = hwrm_req_send(bp, req); 227 if (rc) 228 netdev_err(bp->dev, 229 "ptp adjfine failed. rc = %d\n", rc); 230 return rc; 231 } 232 233 static int bnxt_ptp_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm) 234 { 235 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 236 ptp_info); 237 struct bnxt *bp = ptp->bp; 238 239 if (!BNXT_MH(bp)) 240 return bnxt_ptp_adjfine_rtc(bp, scaled_ppm); 241 242 spin_lock_bh(&ptp->ptp_lock); 243 timecounter_read(&ptp->tc); 244 ptp->cc.mult = adjust_by_scaled_ppm(ptp->cmult, scaled_ppm); 245 spin_unlock_bh(&ptp->ptp_lock); 246 return 0; 247 } 248 249 void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2) 250 { 251 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 252 struct ptp_clock_event event; 253 u64 ns, pps_ts; 254 255 pps_ts = EVENT_PPS_TS(data2, data1); 256 spin_lock_bh(&ptp->ptp_lock); 257 ns = timecounter_cyc2time(&ptp->tc, pps_ts); 258 spin_unlock_bh(&ptp->ptp_lock); 259 260 switch (EVENT_DATA2_PPS_EVENT_TYPE(data2)) { 261 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL: 262 event.pps_times.ts_real = ns_to_timespec64(ns); 263 event.type = PTP_CLOCK_PPSUSR; 264 event.index = EVENT_DATA2_PPS_PIN_NUM(data2); 265 break; 266 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL: 267 event.timestamp = ns; 268 event.type = PTP_CLOCK_EXTTS; 269 event.index = EVENT_DATA2_PPS_PIN_NUM(data2); 270 break; 271 } 272 273 ptp_clock_event(bp->ptp_cfg->ptp_clock, &event); 274 } 275 276 static int bnxt_ptp_cfg_pin(struct bnxt *bp, u8 pin, u8 usage) 277 { 278 struct hwrm_func_ptp_pin_cfg_input *req; 279 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 280 u8 state = usage != BNXT_PPS_PIN_NONE; 281 u8 *pin_state, *pin_usg; 282 u32 enables; 283 int rc; 284 285 if (!TSIO_PIN_VALID(pin)) { 286 netdev_err(ptp->bp->dev, "1PPS: Invalid pin. Check pin-function configuration\n"); 287 return -EOPNOTSUPP; 288 } 289 290 rc = hwrm_req_init(ptp->bp, req, HWRM_FUNC_PTP_PIN_CFG); 291 if (rc) 292 return rc; 293 294 enables = (FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE | 295 FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE) << (pin * 2); 296 req->enables = cpu_to_le32(enables); 297 298 pin_state = &req->pin0_state; 299 pin_usg = &req->pin0_usage; 300 301 *(pin_state + (pin * 2)) = state; 302 *(pin_usg + (pin * 2)) = usage; 303 304 rc = hwrm_req_send(ptp->bp, req); 305 if (rc) 306 return rc; 307 308 ptp->pps_info.pins[pin].usage = usage; 309 ptp->pps_info.pins[pin].state = state; 310 311 return 0; 312 } 313 314 static int bnxt_ptp_cfg_event(struct bnxt *bp, u8 event) 315 { 316 struct hwrm_func_ptp_cfg_input *req; 317 int rc; 318 319 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG); 320 if (rc) 321 return rc; 322 323 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT); 324 req->ptp_pps_event = event; 325 return hwrm_req_send(bp, req); 326 } 327 328 int bnxt_ptp_cfg_tstamp_filters(struct bnxt *bp) 329 { 330 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 331 struct hwrm_port_mac_cfg_input *req; 332 int rc; 333 334 if (!ptp || !ptp->tstamp_filters) 335 return -EIO; 336 337 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 338 if (rc) 339 goto out; 340 341 if (!(bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) && (ptp->tstamp_filters & 342 (PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE | 343 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE))) { 344 ptp->tstamp_filters &= ~(PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE | 345 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE); 346 netdev_warn(bp->dev, "Unsupported FW for all RX pkts timestamp filter\n"); 347 } 348 349 req->flags = cpu_to_le32(ptp->tstamp_filters); 350 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE); 351 req->rx_ts_capture_ptp_msg_type = cpu_to_le16(ptp->rxctl); 352 353 rc = hwrm_req_send(bp, req); 354 if (!rc) { 355 bp->ptp_all_rx_tstamp = !!(ptp->tstamp_filters & 356 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE); 357 return 0; 358 } 359 ptp->tstamp_filters = 0; 360 out: 361 bp->ptp_all_rx_tstamp = 0; 362 netdev_warn(bp->dev, "Failed to configure HW packet timestamp filters\n"); 363 return rc; 364 } 365 366 void bnxt_ptp_reapply_pps(struct bnxt *bp) 367 { 368 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 369 struct bnxt_pps *pps; 370 u32 pin = 0; 371 int rc; 372 373 if (!ptp || !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) || 374 !(ptp->ptp_info.pin_config)) 375 return; 376 pps = &ptp->pps_info; 377 for (pin = 0; pin < BNXT_MAX_TSIO_PINS; pin++) { 378 if (pps->pins[pin].state) { 379 rc = bnxt_ptp_cfg_pin(bp, pin, pps->pins[pin].usage); 380 if (!rc && pps->pins[pin].event) 381 rc = bnxt_ptp_cfg_event(bp, 382 pps->pins[pin].event); 383 if (rc) 384 netdev_err(bp->dev, "1PPS: Failed to configure pin%d\n", 385 pin); 386 } 387 } 388 } 389 390 static int bnxt_get_target_cycles(struct bnxt_ptp_cfg *ptp, u64 target_ns, 391 u64 *cycles_delta) 392 { 393 u64 cycles_now; 394 u64 nsec_now, nsec_delta; 395 int rc; 396 397 spin_lock_bh(&ptp->ptp_lock); 398 rc = bnxt_refclk_read(ptp->bp, NULL, &cycles_now); 399 if (rc) { 400 spin_unlock_bh(&ptp->ptp_lock); 401 return rc; 402 } 403 nsec_now = timecounter_cyc2time(&ptp->tc, cycles_now); 404 spin_unlock_bh(&ptp->ptp_lock); 405 406 nsec_delta = target_ns - nsec_now; 407 *cycles_delta = div64_u64(nsec_delta << ptp->cc.shift, ptp->cc.mult); 408 return 0; 409 } 410 411 static int bnxt_ptp_perout_cfg(struct bnxt_ptp_cfg *ptp, 412 struct ptp_clock_request *rq) 413 { 414 struct hwrm_func_ptp_cfg_input *req; 415 struct bnxt *bp = ptp->bp; 416 struct timespec64 ts; 417 u64 target_ns, delta; 418 u16 enables; 419 int rc; 420 421 ts.tv_sec = rq->perout.start.sec; 422 ts.tv_nsec = rq->perout.start.nsec; 423 target_ns = timespec64_to_ns(&ts); 424 425 rc = bnxt_get_target_cycles(ptp, target_ns, &delta); 426 if (rc) 427 return rc; 428 429 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG); 430 if (rc) 431 return rc; 432 433 enables = FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD | 434 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP | 435 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE; 436 req->enables = cpu_to_le16(enables); 437 req->ptp_pps_event = 0; 438 req->ptp_freq_adj_dll_source = 0; 439 req->ptp_freq_adj_dll_phase = 0; 440 req->ptp_freq_adj_ext_period = cpu_to_le32(NSEC_PER_SEC); 441 req->ptp_freq_adj_ext_up = 0; 442 req->ptp_freq_adj_ext_phase_lower = cpu_to_le32(delta); 443 444 return hwrm_req_send(bp, req); 445 } 446 447 static int bnxt_ptp_enable(struct ptp_clock_info *ptp_info, 448 struct ptp_clock_request *rq, int on) 449 { 450 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 451 ptp_info); 452 struct bnxt *bp = ptp->bp; 453 int pin_id; 454 int rc; 455 456 switch (rq->type) { 457 case PTP_CLK_REQ_EXTTS: 458 /* Configure an External PPS IN */ 459 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_EXTTS, 460 rq->extts.index); 461 if (!TSIO_PIN_VALID(pin_id)) 462 return -EOPNOTSUPP; 463 if (!on) 464 break; 465 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_IN); 466 if (rc) 467 return rc; 468 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_EXTERNAL); 469 if (!rc) 470 ptp->pps_info.pins[pin_id].event = BNXT_PPS_EVENT_EXTERNAL; 471 return rc; 472 case PTP_CLK_REQ_PEROUT: 473 /* Configure a Periodic PPS OUT */ 474 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_PEROUT, 475 rq->perout.index); 476 if (!TSIO_PIN_VALID(pin_id)) 477 return -EOPNOTSUPP; 478 if (!on) 479 break; 480 481 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_OUT); 482 if (!rc) 483 rc = bnxt_ptp_perout_cfg(ptp, rq); 484 485 return rc; 486 case PTP_CLK_REQ_PPS: 487 /* Configure PHC PPS IN */ 488 rc = bnxt_ptp_cfg_pin(bp, 0, BNXT_PPS_PIN_PPS_IN); 489 if (rc) 490 return rc; 491 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_INTERNAL); 492 if (!rc) 493 ptp->pps_info.pins[0].event = BNXT_PPS_EVENT_INTERNAL; 494 return rc; 495 default: 496 netdev_err(ptp->bp->dev, "Unrecognized PIN function\n"); 497 return -EOPNOTSUPP; 498 } 499 500 return bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_NONE); 501 } 502 503 static int bnxt_hwrm_ptp_cfg(struct bnxt *bp) 504 { 505 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 506 u32 flags = 0; 507 508 switch (ptp->rx_filter) { 509 case HWTSTAMP_FILTER_ALL: 510 flags = PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE; 511 break; 512 case HWTSTAMP_FILTER_NONE: 513 flags = PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE; 514 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) 515 flags |= PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE; 516 break; 517 case HWTSTAMP_FILTER_PTP_V2_EVENT: 518 case HWTSTAMP_FILTER_PTP_V2_SYNC: 519 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 520 flags = PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE; 521 break; 522 } 523 524 if (ptp->tx_tstamp_en) 525 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE; 526 else 527 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE; 528 529 ptp->tstamp_filters = flags; 530 531 return bnxt_ptp_cfg_tstamp_filters(bp); 532 } 533 534 int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 535 { 536 struct bnxt *bp = netdev_priv(dev); 537 struct hwtstamp_config stmpconf; 538 struct bnxt_ptp_cfg *ptp; 539 u16 old_rxctl; 540 int old_rx_filter, rc; 541 u8 old_tx_tstamp_en; 542 543 ptp = bp->ptp_cfg; 544 if (!ptp) 545 return -EOPNOTSUPP; 546 547 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf))) 548 return -EFAULT; 549 550 if (stmpconf.tx_type != HWTSTAMP_TX_ON && 551 stmpconf.tx_type != HWTSTAMP_TX_OFF) 552 return -ERANGE; 553 554 old_rx_filter = ptp->rx_filter; 555 old_rxctl = ptp->rxctl; 556 old_tx_tstamp_en = ptp->tx_tstamp_en; 557 switch (stmpconf.rx_filter) { 558 case HWTSTAMP_FILTER_NONE: 559 ptp->rxctl = 0; 560 ptp->rx_filter = HWTSTAMP_FILTER_NONE; 561 break; 562 case HWTSTAMP_FILTER_ALL: 563 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) { 564 ptp->rx_filter = HWTSTAMP_FILTER_ALL; 565 break; 566 } 567 return -EOPNOTSUPP; 568 case HWTSTAMP_FILTER_PTP_V2_EVENT: 569 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 570 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 571 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 572 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 573 break; 574 case HWTSTAMP_FILTER_PTP_V2_SYNC: 575 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 576 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 577 ptp->rxctl = BNXT_PTP_MSG_SYNC; 578 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 579 break; 580 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 581 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 582 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 583 ptp->rxctl = BNXT_PTP_MSG_DELAY_REQ; 584 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 585 break; 586 default: 587 return -ERANGE; 588 } 589 590 if (stmpconf.tx_type == HWTSTAMP_TX_ON) 591 ptp->tx_tstamp_en = 1; 592 else 593 ptp->tx_tstamp_en = 0; 594 595 rc = bnxt_hwrm_ptp_cfg(bp); 596 if (rc) 597 goto ts_set_err; 598 599 stmpconf.rx_filter = ptp->rx_filter; 600 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? 601 -EFAULT : 0; 602 603 ts_set_err: 604 ptp->rx_filter = old_rx_filter; 605 ptp->rxctl = old_rxctl; 606 ptp->tx_tstamp_en = old_tx_tstamp_en; 607 return rc; 608 } 609 610 int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 611 { 612 struct bnxt *bp = netdev_priv(dev); 613 struct hwtstamp_config stmpconf; 614 struct bnxt_ptp_cfg *ptp; 615 616 ptp = bp->ptp_cfg; 617 if (!ptp) 618 return -EOPNOTSUPP; 619 620 stmpconf.flags = 0; 621 stmpconf.tx_type = ptp->tx_tstamp_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 622 623 stmpconf.rx_filter = ptp->rx_filter; 624 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? 625 -EFAULT : 0; 626 } 627 628 static int bnxt_map_regs(struct bnxt *bp, u32 *reg_arr, int count, int reg_win) 629 { 630 u32 reg_base = *reg_arr & BNXT_GRC_BASE_MASK; 631 u32 win_off; 632 int i; 633 634 for (i = 0; i < count; i++) { 635 if ((reg_arr[i] & BNXT_GRC_BASE_MASK) != reg_base) 636 return -ERANGE; 637 } 638 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 639 writel(reg_base, bp->bar0 + win_off); 640 return 0; 641 } 642 643 static int bnxt_map_ptp_regs(struct bnxt *bp) 644 { 645 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 646 u32 *reg_arr; 647 int rc, i; 648 649 reg_arr = ptp->refclk_regs; 650 if (BNXT_CHIP_P5(bp)) { 651 rc = bnxt_map_regs(bp, reg_arr, 2, BNXT_PTP_GRC_WIN); 652 if (rc) 653 return rc; 654 for (i = 0; i < 2; i++) 655 ptp->refclk_mapped_regs[i] = BNXT_PTP_GRC_WIN_BASE + 656 (ptp->refclk_regs[i] & BNXT_GRC_OFFSET_MASK); 657 return 0; 658 } 659 return -ENODEV; 660 } 661 662 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 663 { 664 writel(0, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 665 (BNXT_PTP_GRC_WIN - 1) * 4); 666 } 667 668 static u64 bnxt_cc_read(const struct cyclecounter *cc) 669 { 670 struct bnxt_ptp_cfg *ptp = container_of(cc, struct bnxt_ptp_cfg, cc); 671 u64 ns = 0; 672 673 bnxt_refclk_read(ptp->bp, NULL, &ns); 674 return ns; 675 } 676 677 static void bnxt_stamp_tx_skb(struct bnxt *bp, struct sk_buff *skb) 678 { 679 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 680 struct skb_shared_hwtstamps timestamp; 681 unsigned long now = jiffies; 682 u64 ts = 0, ns = 0; 683 u32 tmo = 0; 684 int rc; 685 686 if (!ptp->txts_pending) 687 ptp->abs_txts_tmo = now + msecs_to_jiffies(ptp->txts_tmo); 688 if (!time_after_eq(now, ptp->abs_txts_tmo)) 689 tmo = jiffies_to_msecs(ptp->abs_txts_tmo - now); 690 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_PATH_TX, &ts, 691 tmo); 692 if (!rc) { 693 memset(×tamp, 0, sizeof(timestamp)); 694 spin_lock_bh(&ptp->ptp_lock); 695 ns = timecounter_cyc2time(&ptp->tc, ts); 696 spin_unlock_bh(&ptp->ptp_lock); 697 timestamp.hwtstamp = ns_to_ktime(ns); 698 skb_tstamp_tx(ptp->tx_skb, ×tamp); 699 } else { 700 if (!time_after_eq(jiffies, ptp->abs_txts_tmo)) { 701 ptp->txts_pending = true; 702 return; 703 } 704 netdev_warn_once(bp->dev, 705 "TS query for TX timer failed rc = %x\n", rc); 706 } 707 708 dev_kfree_skb_any(ptp->tx_skb); 709 ptp->tx_skb = NULL; 710 atomic_inc(&ptp->tx_avail); 711 ptp->txts_pending = false; 712 } 713 714 static long bnxt_ptp_ts_aux_work(struct ptp_clock_info *ptp_info) 715 { 716 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 717 ptp_info); 718 unsigned long now = jiffies; 719 struct bnxt *bp = ptp->bp; 720 721 if (ptp->tx_skb) 722 bnxt_stamp_tx_skb(bp, ptp->tx_skb); 723 724 if (!time_after_eq(now, ptp->next_period)) 725 return ptp->next_period - now; 726 727 bnxt_ptp_get_current_time(bp); 728 ptp->next_period = now + HZ; 729 if (time_after_eq(now, ptp->next_overflow_check)) { 730 spin_lock_bh(&ptp->ptp_lock); 731 timecounter_read(&ptp->tc); 732 spin_unlock_bh(&ptp->ptp_lock); 733 ptp->next_overflow_check = now + BNXT_PHC_OVERFLOW_PERIOD; 734 } 735 if (ptp->txts_pending) 736 return 0; 737 return HZ; 738 } 739 740 int bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb) 741 { 742 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 743 744 if (ptp->tx_skb) { 745 netdev_err(bp->dev, "deferring skb:one SKB is still outstanding\n"); 746 return -EBUSY; 747 } 748 ptp->tx_skb = skb; 749 ptp_schedule_worker(ptp->ptp_clock, 0); 750 return 0; 751 } 752 753 int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts) 754 { 755 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 756 u64 time; 757 758 if (!ptp) 759 return -ENODEV; 760 761 BNXT_READ_TIME64(ptp, time, ptp->old_time); 762 *ts = (time & BNXT_HI_TIMER_MASK) | pkt_ts; 763 if (pkt_ts < (time & BNXT_LO_TIMER_MASK)) 764 *ts += BNXT_LO_TIMER_MASK + 1; 765 766 return 0; 767 } 768 769 static const struct ptp_clock_info bnxt_ptp_caps = { 770 .owner = THIS_MODULE, 771 .name = "bnxt clock", 772 .max_adj = BNXT_MAX_PHC_DRIFT, 773 .n_alarm = 0, 774 .n_ext_ts = 0, 775 .n_per_out = 0, 776 .n_pins = 0, 777 .pps = 0, 778 .adjfine = bnxt_ptp_adjfine, 779 .adjtime = bnxt_ptp_adjtime, 780 .do_aux_work = bnxt_ptp_ts_aux_work, 781 .gettimex64 = bnxt_ptp_gettimex, 782 .settime64 = bnxt_ptp_settime, 783 .enable = bnxt_ptp_enable, 784 }; 785 786 static int bnxt_ptp_verify(struct ptp_clock_info *ptp_info, unsigned int pin, 787 enum ptp_pin_function func, unsigned int chan) 788 { 789 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 790 ptp_info); 791 /* Allow only PPS pin function configuration */ 792 if (ptp->pps_info.pins[pin].usage <= BNXT_PPS_PIN_PPS_OUT && 793 func != PTP_PF_PHYSYNC) 794 return 0; 795 else 796 return -EOPNOTSUPP; 797 } 798 799 static int bnxt_ptp_pps_init(struct bnxt *bp) 800 { 801 struct hwrm_func_ptp_pin_qcfg_output *resp; 802 struct hwrm_func_ptp_pin_qcfg_input *req; 803 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 804 struct ptp_clock_info *ptp_info; 805 struct bnxt_pps *pps_info; 806 u8 *pin_usg; 807 u32 i, rc; 808 809 /* Query current/default PIN CFG */ 810 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_PIN_QCFG); 811 if (rc) 812 return rc; 813 814 resp = hwrm_req_hold(bp, req); 815 rc = hwrm_req_send(bp, req); 816 if (rc || !resp->num_pins) { 817 hwrm_req_drop(bp, req); 818 return -EOPNOTSUPP; 819 } 820 821 ptp_info = &ptp->ptp_info; 822 pps_info = &ptp->pps_info; 823 pps_info->num_pins = resp->num_pins; 824 ptp_info->n_pins = pps_info->num_pins; 825 ptp_info->pin_config = kcalloc(ptp_info->n_pins, 826 sizeof(*ptp_info->pin_config), 827 GFP_KERNEL); 828 if (!ptp_info->pin_config) { 829 hwrm_req_drop(bp, req); 830 return -ENOMEM; 831 } 832 833 /* Report the TSIO capability to kernel */ 834 pin_usg = &resp->pin0_usage; 835 for (i = 0; i < pps_info->num_pins; i++, pin_usg++) { 836 snprintf(ptp_info->pin_config[i].name, 837 sizeof(ptp_info->pin_config[i].name), "bnxt_pps%d", i); 838 ptp_info->pin_config[i].index = i; 839 ptp_info->pin_config[i].chan = i; 840 if (*pin_usg == BNXT_PPS_PIN_PPS_IN) 841 ptp_info->pin_config[i].func = PTP_PF_EXTTS; 842 else if (*pin_usg == BNXT_PPS_PIN_PPS_OUT) 843 ptp_info->pin_config[i].func = PTP_PF_PEROUT; 844 else 845 ptp_info->pin_config[i].func = PTP_PF_NONE; 846 847 pps_info->pins[i].usage = *pin_usg; 848 } 849 hwrm_req_drop(bp, req); 850 851 /* Only 1 each of ext_ts and per_out pins is available in HW */ 852 ptp_info->n_ext_ts = 1; 853 ptp_info->n_per_out = 1; 854 ptp_info->pps = 1; 855 ptp_info->verify = bnxt_ptp_verify; 856 857 return 0; 858 } 859 860 static bool bnxt_pps_config_ok(struct bnxt *bp) 861 { 862 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 863 864 return !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) == !ptp->ptp_info.pin_config; 865 } 866 867 static void bnxt_ptp_timecounter_init(struct bnxt *bp, bool init_tc) 868 { 869 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 870 871 if (!ptp->ptp_clock) { 872 memset(&ptp->cc, 0, sizeof(ptp->cc)); 873 ptp->cc.read = bnxt_cc_read; 874 ptp->cc.mask = CYCLECOUNTER_MASK(48); 875 if (BNXT_MH(bp)) { 876 /* Use timecounter based non-real time mode */ 877 ptp->cc.shift = BNXT_CYCLES_SHIFT; 878 ptp->cc.mult = clocksource_khz2mult(BNXT_DEVCLK_FREQ, ptp->cc.shift); 879 ptp->cmult = ptp->cc.mult; 880 } else { 881 ptp->cc.shift = 0; 882 ptp->cc.mult = 1; 883 } 884 ptp->next_overflow_check = jiffies + BNXT_PHC_OVERFLOW_PERIOD; 885 } 886 if (init_tc) 887 timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real())); 888 } 889 890 /* Caller holds ptp_lock */ 891 void bnxt_ptp_rtc_timecounter_init(struct bnxt_ptp_cfg *ptp, u64 ns) 892 { 893 timecounter_init(&ptp->tc, &ptp->cc, ns); 894 /* For RTC, cycle_last must be in sync with the timecounter value. */ 895 ptp->tc.cycle_last = ns & ptp->cc.mask; 896 } 897 898 int bnxt_ptp_init_rtc(struct bnxt *bp, bool phc_cfg) 899 { 900 struct timespec64 tsp; 901 u64 ns; 902 int rc; 903 904 if (!bp->ptp_cfg || !BNXT_PTP_USE_RTC(bp)) 905 return -ENODEV; 906 907 if (!phc_cfg) { 908 ktime_get_real_ts64(&tsp); 909 ns = timespec64_to_ns(&tsp); 910 rc = bnxt_ptp_cfg_settime(bp, ns); 911 if (rc) 912 return rc; 913 } else { 914 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME, 915 &ns, 0); 916 if (rc) 917 return rc; 918 } 919 spin_lock_bh(&bp->ptp_cfg->ptp_lock); 920 bnxt_ptp_rtc_timecounter_init(bp->ptp_cfg, ns); 921 spin_unlock_bh(&bp->ptp_cfg->ptp_lock); 922 923 return 0; 924 } 925 926 static void bnxt_ptp_free(struct bnxt *bp) 927 { 928 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 929 930 if (ptp->ptp_clock) { 931 ptp_clock_unregister(ptp->ptp_clock); 932 ptp->ptp_clock = NULL; 933 kfree(ptp->ptp_info.pin_config); 934 ptp->ptp_info.pin_config = NULL; 935 } 936 } 937 938 int bnxt_ptp_init(struct bnxt *bp, bool phc_cfg) 939 { 940 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 941 int rc; 942 943 if (!ptp) 944 return 0; 945 946 rc = bnxt_map_ptp_regs(bp); 947 if (rc) 948 return rc; 949 950 if (ptp->ptp_clock && bnxt_pps_config_ok(bp)) 951 return 0; 952 953 bnxt_ptp_free(bp); 954 955 atomic_set(&ptp->tx_avail, BNXT_MAX_TX_TS); 956 spin_lock_init(&ptp->ptp_lock); 957 958 if (BNXT_PTP_USE_RTC(bp)) { 959 bnxt_ptp_timecounter_init(bp, false); 960 rc = bnxt_ptp_init_rtc(bp, phc_cfg); 961 if (rc) 962 goto out; 963 } else { 964 bnxt_ptp_timecounter_init(bp, true); 965 bnxt_ptp_adjfine_rtc(bp, 0); 966 } 967 bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, true); 968 969 ptp->ptp_info = bnxt_ptp_caps; 970 if ((bp->fw_cap & BNXT_FW_CAP_PTP_PPS)) { 971 if (bnxt_ptp_pps_init(bp)) 972 netdev_err(bp->dev, "1pps not initialized, continuing without 1pps support\n"); 973 } 974 ptp->ptp_clock = ptp_clock_register(&ptp->ptp_info, &bp->pdev->dev); 975 if (IS_ERR(ptp->ptp_clock)) { 976 int err = PTR_ERR(ptp->ptp_clock); 977 978 ptp->ptp_clock = NULL; 979 rc = err; 980 goto out; 981 } 982 if (BNXT_CHIP_P5(bp)) { 983 spin_lock_bh(&ptp->ptp_lock); 984 bnxt_refclk_read(bp, NULL, &ptp->current_time); 985 WRITE_ONCE(ptp->old_time, ptp->current_time); 986 spin_unlock_bh(&ptp->ptp_lock); 987 ptp_schedule_worker(ptp->ptp_clock, 0); 988 } 989 ptp->txts_tmo = BNXT_PTP_DFLT_TX_TMO; 990 return 0; 991 992 out: 993 bnxt_ptp_free(bp); 994 bnxt_unmap_ptp_regs(bp); 995 return rc; 996 } 997 998 void bnxt_ptp_clear(struct bnxt *bp) 999 { 1000 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 1001 1002 if (!ptp) 1003 return; 1004 1005 if (ptp->ptp_clock) 1006 ptp_clock_unregister(ptp->ptp_clock); 1007 1008 ptp->ptp_clock = NULL; 1009 kfree(ptp->ptp_info.pin_config); 1010 ptp->ptp_info.pin_config = NULL; 1011 1012 if (ptp->tx_skb) { 1013 dev_kfree_skb_any(ptp->tx_skb); 1014 ptp->tx_skb = NULL; 1015 } 1016 bnxt_unmap_ptp_regs(bp); 1017 } 1018