1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2014-2018 Broadcom Limited 5 * Copyright (c) 2018-2023 Broadcom Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * DO NOT MODIFY!!! This file is automatically generated. 12 */ 13 14 #ifndef _BNXT_HSI_H_ 15 #define _BNXT_HSI_H_ 16 17 /* hwrm_cmd_hdr (size:128b/16B) */ 18 struct hwrm_cmd_hdr { 19 __le16 req_type; 20 __le16 cmpl_ring; 21 __le16 seq_id; 22 __le16 target_id; 23 __le64 resp_addr; 24 }; 25 26 /* hwrm_resp_hdr (size:64b/8B) */ 27 struct hwrm_resp_hdr { 28 __le16 error_code; 29 __le16 req_type; 30 __le16 seq_id; 31 __le16 resp_len; 32 }; 33 34 #define CMD_DISCR_TLV_ENCAP 0x8000UL 35 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 36 37 38 #define TLV_TYPE_HWRM_REQUEST 0x1UL 39 #define TLV_TYPE_HWRM_RESPONSE 0x2UL 40 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 41 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 42 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 43 #define TLV_TYPE_QUERY_ROCE_CC_GEN2 0x6UL 44 #define TLV_TYPE_MODIFY_ROCE_CC_GEN2 0x7UL 45 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL 46 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 47 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 48 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 49 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL 50 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL 51 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 52 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL 53 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL 54 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 55 56 57 /* tlv (size:64b/8B) */ 58 struct tlv { 59 __le16 cmd_discr; 60 u8 reserved_8b; 61 u8 flags; 62 #define TLV_FLAGS_MORE 0x1UL 63 #define TLV_FLAGS_MORE_LAST 0x0UL 64 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 65 #define TLV_FLAGS_REQUIRED 0x2UL 66 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 67 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 68 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 69 __le16 tlv_type; 70 __le16 length; 71 }; 72 73 /* input (size:128b/16B) */ 74 struct input { 75 __le16 req_type; 76 __le16 cmpl_ring; 77 __le16 seq_id; 78 __le16 target_id; 79 __le64 resp_addr; 80 }; 81 82 /* output (size:64b/8B) */ 83 struct output { 84 __le16 error_code; 85 __le16 req_type; 86 __le16 seq_id; 87 __le16 resp_len; 88 }; 89 90 /* hwrm_short_input (size:128b/16B) */ 91 struct hwrm_short_input { 92 __le16 req_type; 93 __le16 signature; 94 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 95 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 96 __le16 target_id; 97 #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL 98 #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL 99 #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS 100 __le16 size; 101 __le64 req_addr; 102 }; 103 104 /* cmd_nums (size:64b/8B) */ 105 struct cmd_nums { 106 __le16 req_type; 107 #define HWRM_VER_GET 0x0UL 108 #define HWRM_FUNC_ECHO_RESPONSE 0xbUL 109 #define HWRM_ERROR_RECOVERY_QCFG 0xcUL 110 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 111 #define HWRM_FUNC_BUF_UNRGTR 0xeUL 112 #define HWRM_FUNC_VF_CFG 0xfUL 113 #define HWRM_RESERVED1 0x10UL 114 #define HWRM_FUNC_RESET 0x11UL 115 #define HWRM_FUNC_GETFID 0x12UL 116 #define HWRM_FUNC_VF_ALLOC 0x13UL 117 #define HWRM_FUNC_VF_FREE 0x14UL 118 #define HWRM_FUNC_QCAPS 0x15UL 119 #define HWRM_FUNC_QCFG 0x16UL 120 #define HWRM_FUNC_CFG 0x17UL 121 #define HWRM_FUNC_QSTATS 0x18UL 122 #define HWRM_FUNC_CLR_STATS 0x19UL 123 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 124 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 125 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 126 #define HWRM_FUNC_DRV_RGTR 0x1dUL 127 #define HWRM_FUNC_DRV_QVER 0x1eUL 128 #define HWRM_FUNC_BUF_RGTR 0x1fUL 129 #define HWRM_PORT_PHY_CFG 0x20UL 130 #define HWRM_PORT_MAC_CFG 0x21UL 131 #define HWRM_PORT_TS_QUERY 0x22UL 132 #define HWRM_PORT_QSTATS 0x23UL 133 #define HWRM_PORT_LPBK_QSTATS 0x24UL 134 #define HWRM_PORT_CLR_STATS 0x25UL 135 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 136 #define HWRM_PORT_PHY_QCFG 0x27UL 137 #define HWRM_PORT_MAC_QCFG 0x28UL 138 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 139 #define HWRM_PORT_PHY_QCAPS 0x2aUL 140 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 141 #define HWRM_PORT_PHY_I2C_READ 0x2cUL 142 #define HWRM_PORT_LED_CFG 0x2dUL 143 #define HWRM_PORT_LED_QCFG 0x2eUL 144 #define HWRM_PORT_LED_QCAPS 0x2fUL 145 #define HWRM_QUEUE_QPORTCFG 0x30UL 146 #define HWRM_QUEUE_QCFG 0x31UL 147 #define HWRM_QUEUE_CFG 0x32UL 148 #define HWRM_FUNC_VLAN_CFG 0x33UL 149 #define HWRM_FUNC_VLAN_QCFG 0x34UL 150 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 151 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 152 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 153 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 154 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 155 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 156 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 157 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 158 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 159 #define HWRM_VNIC_ALLOC 0x40UL 160 #define HWRM_VNIC_FREE 0x41UL 161 #define HWRM_VNIC_CFG 0x42UL 162 #define HWRM_VNIC_QCFG 0x43UL 163 #define HWRM_VNIC_TPA_CFG 0x44UL 164 #define HWRM_VNIC_TPA_QCFG 0x45UL 165 #define HWRM_VNIC_RSS_CFG 0x46UL 166 #define HWRM_VNIC_RSS_QCFG 0x47UL 167 #define HWRM_VNIC_PLCMODES_CFG 0x48UL 168 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 169 #define HWRM_VNIC_QCAPS 0x4aUL 170 #define HWRM_VNIC_UPDATE 0x4bUL 171 #define HWRM_RING_ALLOC 0x50UL 172 #define HWRM_RING_FREE 0x51UL 173 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 174 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 175 #define HWRM_RING_AGGINT_QCAPS 0x54UL 176 #define HWRM_RING_SCHQ_ALLOC 0x55UL 177 #define HWRM_RING_SCHQ_CFG 0x56UL 178 #define HWRM_RING_SCHQ_FREE 0x57UL 179 #define HWRM_RING_RESET 0x5eUL 180 #define HWRM_RING_GRP_ALLOC 0x60UL 181 #define HWRM_RING_GRP_FREE 0x61UL 182 #define HWRM_RING_CFG 0x62UL 183 #define HWRM_RING_QCFG 0x63UL 184 #define HWRM_RESERVED5 0x64UL 185 #define HWRM_RESERVED6 0x65UL 186 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 187 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 188 #define HWRM_QUEUE_MPLS_QCAPS 0x80UL 189 #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL 190 #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL 191 #define HWRM_QUEUE_VLANPRI_QCAPS 0x83UL 192 #define HWRM_QUEUE_VLANPRI2PRI_QCFG 0x84UL 193 #define HWRM_QUEUE_VLANPRI2PRI_CFG 0x85UL 194 #define HWRM_QUEUE_GLOBAL_CFG 0x86UL 195 #define HWRM_QUEUE_GLOBAL_QCFG 0x87UL 196 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG 0x88UL 197 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG 0x89UL 198 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG 0x8aUL 199 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG 0x8bUL 200 #define HWRM_QUEUE_QCAPS 0x8cUL 201 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_QCFG 0x8dUL 202 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG 0x8eUL 203 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_QCFG 0x8fUL 204 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 205 #define HWRM_CFA_L2_FILTER_FREE 0x91UL 206 #define HWRM_CFA_L2_FILTER_CFG 0x92UL 207 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 208 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 209 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 210 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 211 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 212 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 213 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 214 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 215 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 216 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 217 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 218 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 219 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 220 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 221 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 222 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG 0xa3UL 223 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 224 #define HWRM_STAT_CTX_ALLOC 0xb0UL 225 #define HWRM_STAT_CTX_FREE 0xb1UL 226 #define HWRM_STAT_CTX_QUERY 0xb2UL 227 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 228 #define HWRM_PORT_QSTATS_EXT 0xb4UL 229 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL 230 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL 231 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL 232 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL 233 #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL 234 #define HWRM_RESERVED7 0xbaUL 235 #define HWRM_PORT_TX_FIR_CFG 0xbbUL 236 #define HWRM_PORT_TX_FIR_QCFG 0xbcUL 237 #define HWRM_PORT_ECN_QSTATS 0xbdUL 238 #define HWRM_FW_LIVEPATCH_QUERY 0xbeUL 239 #define HWRM_FW_LIVEPATCH 0xbfUL 240 #define HWRM_FW_RESET 0xc0UL 241 #define HWRM_FW_QSTATUS 0xc1UL 242 #define HWRM_FW_HEALTH_CHECK 0xc2UL 243 #define HWRM_FW_SYNC 0xc3UL 244 #define HWRM_FW_STATE_QCAPS 0xc4UL 245 #define HWRM_FW_STATE_QUIESCE 0xc5UL 246 #define HWRM_FW_STATE_BACKUP 0xc6UL 247 #define HWRM_FW_STATE_RESTORE 0xc7UL 248 #define HWRM_FW_SET_TIME 0xc8UL 249 #define HWRM_FW_GET_TIME 0xc9UL 250 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 251 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 252 #define HWRM_FW_IPC_MAILBOX 0xccUL 253 #define HWRM_FW_ECN_CFG 0xcdUL 254 #define HWRM_FW_ECN_QCFG 0xceUL 255 #define HWRM_FW_SECURE_CFG 0xcfUL 256 #define HWRM_EXEC_FWD_RESP 0xd0UL 257 #define HWRM_REJECT_FWD_RESP 0xd1UL 258 #define HWRM_FWD_RESP 0xd2UL 259 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 260 #define HWRM_OEM_CMD 0xd4UL 261 #define HWRM_PORT_PRBS_TEST 0xd5UL 262 #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL 263 #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL 264 #define HWRM_FW_STATE_UNQUIESCE 0xd8UL 265 #define HWRM_PORT_DSC_DUMP 0xd9UL 266 #define HWRM_PORT_EP_TX_QCFG 0xdaUL 267 #define HWRM_PORT_EP_TX_CFG 0xdbUL 268 #define HWRM_PORT_CFG 0xdcUL 269 #define HWRM_PORT_QCFG 0xddUL 270 #define HWRM_PORT_MAC_QCAPS 0xdfUL 271 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 272 #define HWRM_REG_POWER_QUERY 0xe1UL 273 #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL 274 #define HWRM_REG_POWER_HISTOGRAM 0xe3UL 275 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 276 #define HWRM_WOL_FILTER_FREE 0xf1UL 277 #define HWRM_WOL_FILTER_QCFG 0xf2UL 278 #define HWRM_WOL_REASON_QCFG 0xf3UL 279 #define HWRM_CFA_METER_QCAPS 0xf4UL 280 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 281 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 282 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 283 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 284 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 285 #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL 286 #define HWRM_CFA_VFR_ALLOC 0xfdUL 287 #define HWRM_CFA_VFR_FREE 0xfeUL 288 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 289 #define HWRM_CFA_VF_PAIR_FREE 0x101UL 290 #define HWRM_CFA_VF_PAIR_INFO 0x102UL 291 #define HWRM_CFA_FLOW_ALLOC 0x103UL 292 #define HWRM_CFA_FLOW_FREE 0x104UL 293 #define HWRM_CFA_FLOW_FLUSH 0x105UL 294 #define HWRM_CFA_FLOW_STATS 0x106UL 295 #define HWRM_CFA_FLOW_INFO 0x107UL 296 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 297 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 298 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 299 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 300 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 301 #define HWRM_CFA_PAIR_ALLOC 0x10dUL 302 #define HWRM_CFA_PAIR_FREE 0x10eUL 303 #define HWRM_CFA_PAIR_INFO 0x10fUL 304 #define HWRM_FW_IPC_MSG 0x110UL 305 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 306 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 307 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL 308 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL 309 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL 310 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL 311 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL 312 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL 313 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL 314 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL 315 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL 316 #define HWRM_CFA_COUNTER_CFG 0x11cUL 317 #define HWRM_CFA_COUNTER_QCFG 0x11dUL 318 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL 319 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL 320 #define HWRM_CFA_EEM_QCAPS 0x120UL 321 #define HWRM_CFA_EEM_CFG 0x121UL 322 #define HWRM_CFA_EEM_QCFG 0x122UL 323 #define HWRM_CFA_EEM_OP 0x123UL 324 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL 325 #define HWRM_CFA_TFLIB 0x125UL 326 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR 0x126UL 327 #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR 0x127UL 328 #define HWRM_CFA_TLS_FILTER_ALLOC 0x128UL 329 #define HWRM_CFA_TLS_FILTER_FREE 0x129UL 330 #define HWRM_CFA_RELEASE_AFM_FUNC 0x12aUL 331 #define HWRM_ENGINE_CKV_STATUS 0x12eUL 332 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 333 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 334 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 335 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 336 #define HWRM_ENGINE_CKV_FLUSH 0x133UL 337 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 338 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 339 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL 340 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL 341 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 342 #define HWRM_ENGINE_QG_QUERY 0x13dUL 343 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 344 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 345 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 346 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 347 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 348 #define HWRM_ENGINE_QG_METER_BIND 0x143UL 349 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 350 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 351 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 352 #define HWRM_ENGINE_SG_QUERY 0x147UL 353 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 354 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 355 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 356 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 357 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 358 #define HWRM_ENGINE_STATS_CONFIG 0x155UL 359 #define HWRM_ENGINE_STATS_CLEAR 0x156UL 360 #define HWRM_ENGINE_STATS_QUERY 0x157UL 361 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL 362 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 363 #define HWRM_ENGINE_RQ_FREE 0x15fUL 364 #define HWRM_ENGINE_CQ_ALLOC 0x160UL 365 #define HWRM_ENGINE_CQ_FREE 0x161UL 366 #define HWRM_ENGINE_NQ_ALLOC 0x162UL 367 #define HWRM_ENGINE_NQ_FREE 0x163UL 368 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 369 #define HWRM_ENGINE_FUNC_QCFG 0x165UL 370 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 371 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 372 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 373 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 374 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 375 #define HWRM_FUNC_VF_BW_CFG 0x195UL 376 #define HWRM_FUNC_VF_BW_QCFG 0x196UL 377 #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL 378 #define HWRM_FUNC_QSTATS_EXT 0x198UL 379 #define HWRM_STAT_EXT_CTX_QUERY 0x199UL 380 #define HWRM_FUNC_SPD_CFG 0x19aUL 381 #define HWRM_FUNC_SPD_QCFG 0x19bUL 382 #define HWRM_FUNC_PTP_PIN_QCFG 0x19cUL 383 #define HWRM_FUNC_PTP_PIN_CFG 0x19dUL 384 #define HWRM_FUNC_PTP_CFG 0x19eUL 385 #define HWRM_FUNC_PTP_TS_QUERY 0x19fUL 386 #define HWRM_FUNC_PTP_EXT_CFG 0x1a0UL 387 #define HWRM_FUNC_PTP_EXT_QCFG 0x1a1UL 388 #define HWRM_FUNC_KEY_CTX_ALLOC 0x1a2UL 389 #define HWRM_FUNC_BACKING_STORE_CFG_V2 0x1a3UL 390 #define HWRM_FUNC_BACKING_STORE_QCFG_V2 0x1a4UL 391 #define HWRM_FUNC_DBR_PACING_CFG 0x1a5UL 392 #define HWRM_FUNC_DBR_PACING_QCFG 0x1a6UL 393 #define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT 0x1a7UL 394 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2 0x1a8UL 395 #define HWRM_FUNC_DBR_PACING_NQLIST_QUERY 0x1a9UL 396 #define HWRM_FUNC_DBR_RECOVERY_COMPLETED 0x1aaUL 397 #define HWRM_FUNC_SYNCE_CFG 0x1abUL 398 #define HWRM_FUNC_SYNCE_QCFG 0x1acUL 399 #define HWRM_FUNC_KEY_CTX_FREE 0x1adUL 400 #define HWRM_FUNC_LAG_MODE_CFG 0x1aeUL 401 #define HWRM_FUNC_LAG_MODE_QCFG 0x1afUL 402 #define HWRM_FUNC_LAG_CREATE 0x1b0UL 403 #define HWRM_FUNC_LAG_UPDATE 0x1b1UL 404 #define HWRM_FUNC_LAG_FREE 0x1b2UL 405 #define HWRM_FUNC_LAG_QCFG 0x1b3UL 406 #define HWRM_SELFTEST_QLIST 0x200UL 407 #define HWRM_SELFTEST_EXEC 0x201UL 408 #define HWRM_SELFTEST_IRQ 0x202UL 409 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 410 #define HWRM_PCIE_QSTATS 0x204UL 411 #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL 412 #define HWRM_MFG_TIMERS_QUERY 0x206UL 413 #define HWRM_MFG_OTP_CFG 0x207UL 414 #define HWRM_MFG_OTP_QCFG 0x208UL 415 #define HWRM_MFG_HDMA_TEST 0x209UL 416 #define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL 417 #define HWRM_MFG_FRU_EEPROM_READ 0x20bUL 418 #define HWRM_MFG_SOC_IMAGE 0x20cUL 419 #define HWRM_MFG_SOC_QSTATUS 0x20dUL 420 #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE 0x20eUL 421 #define HWRM_MFG_PARAM_CRITICAL_DATA_READ 0x20fUL 422 #define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH 0x210UL 423 #define HWRM_MFG_PRVSN_EXPORT_CSR 0x211UL 424 #define HWRM_MFG_PRVSN_IMPORT_CERT 0x212UL 425 #define HWRM_MFG_PRVSN_GET_STATE 0x213UL 426 #define HWRM_MFG_GET_NVM_MEASUREMENT 0x214UL 427 #define HWRM_MFG_PSOC_QSTATUS 0x215UL 428 #define HWRM_MFG_SELFTEST_QLIST 0x216UL 429 #define HWRM_MFG_SELFTEST_EXEC 0x217UL 430 #define HWRM_STAT_GENERIC_QSTATS 0x218UL 431 #define HWRM_MFG_PRVSN_EXPORT_CERT 0x219UL 432 #define HWRM_STAT_DB_ERROR_QSTATS 0x21aUL 433 #define HWRM_UDCC_QCAPS 0x258UL 434 #define HWRM_UDCC_CFG 0x259UL 435 #define HWRM_UDCC_QCFG 0x25aUL 436 #define HWRM_UDCC_SESSION_CFG 0x25bUL 437 #define HWRM_UDCC_SESSION_QCFG 0x25cUL 438 #define HWRM_UDCC_SESSION_QUERY 0x25dUL 439 #define HWRM_UDCC_COMP_CFG 0x25eUL 440 #define HWRM_UDCC_COMP_QCFG 0x25fUL 441 #define HWRM_UDCC_COMP_QUERY 0x260UL 442 #define HWRM_TF 0x2bcUL 443 #define HWRM_TF_VERSION_GET 0x2bdUL 444 #define HWRM_TF_SESSION_OPEN 0x2c6UL 445 #define HWRM_TF_SESSION_REGISTER 0x2c8UL 446 #define HWRM_TF_SESSION_UNREGISTER 0x2c9UL 447 #define HWRM_TF_SESSION_CLOSE 0x2caUL 448 #define HWRM_TF_SESSION_QCFG 0x2cbUL 449 #define HWRM_TF_SESSION_RESC_QCAPS 0x2ccUL 450 #define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL 451 #define HWRM_TF_SESSION_RESC_FREE 0x2ceUL 452 #define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL 453 #define HWRM_TF_SESSION_RESC_INFO 0x2d0UL 454 #define HWRM_TF_SESSION_HOTUP_STATE_SET 0x2d1UL 455 #define HWRM_TF_SESSION_HOTUP_STATE_GET 0x2d2UL 456 #define HWRM_TF_TBL_TYPE_GET 0x2daUL 457 #define HWRM_TF_TBL_TYPE_SET 0x2dbUL 458 #define HWRM_TF_TBL_TYPE_BULK_GET 0x2dcUL 459 #define HWRM_TF_EM_INSERT 0x2eaUL 460 #define HWRM_TF_EM_DELETE 0x2ebUL 461 #define HWRM_TF_EM_HASH_INSERT 0x2ecUL 462 #define HWRM_TF_EM_MOVE 0x2edUL 463 #define HWRM_TF_TCAM_SET 0x2f8UL 464 #define HWRM_TF_TCAM_GET 0x2f9UL 465 #define HWRM_TF_TCAM_MOVE 0x2faUL 466 #define HWRM_TF_TCAM_FREE 0x2fbUL 467 #define HWRM_TF_GLOBAL_CFG_SET 0x2fcUL 468 #define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL 469 #define HWRM_TF_IF_TBL_SET 0x2feUL 470 #define HWRM_TF_IF_TBL_GET 0x2ffUL 471 #define HWRM_TF_RESC_USAGE_SET 0x300UL 472 #define HWRM_TF_RESC_USAGE_QUERY 0x301UL 473 #define HWRM_TF_TBL_TYPE_ALLOC 0x302UL 474 #define HWRM_TF_TBL_TYPE_FREE 0x303UL 475 #define HWRM_TFC_TBL_SCOPE_QCAPS 0x380UL 476 #define HWRM_TFC_TBL_SCOPE_ID_ALLOC 0x381UL 477 #define HWRM_TFC_TBL_SCOPE_CONFIG 0x382UL 478 #define HWRM_TFC_TBL_SCOPE_DECONFIG 0x383UL 479 #define HWRM_TFC_TBL_SCOPE_FID_ADD 0x384UL 480 #define HWRM_TFC_TBL_SCOPE_FID_REM 0x385UL 481 #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC 0x386UL 482 #define HWRM_TFC_TBL_SCOPE_POOL_FREE 0x387UL 483 #define HWRM_TFC_SESSION_ID_ALLOC 0x388UL 484 #define HWRM_TFC_SESSION_FID_ADD 0x389UL 485 #define HWRM_TFC_SESSION_FID_REM 0x38aUL 486 #define HWRM_TFC_IDENT_ALLOC 0x38bUL 487 #define HWRM_TFC_IDENT_FREE 0x38cUL 488 #define HWRM_TFC_IDX_TBL_ALLOC 0x38dUL 489 #define HWRM_TFC_IDX_TBL_ALLOC_SET 0x38eUL 490 #define HWRM_TFC_IDX_TBL_SET 0x38fUL 491 #define HWRM_TFC_IDX_TBL_GET 0x390UL 492 #define HWRM_TFC_IDX_TBL_FREE 0x391UL 493 #define HWRM_TFC_GLOBAL_ID_ALLOC 0x392UL 494 #define HWRM_TFC_TCAM_SET 0x393UL 495 #define HWRM_TFC_TCAM_GET 0x394UL 496 #define HWRM_TFC_TCAM_ALLOC 0x395UL 497 #define HWRM_TFC_TCAM_ALLOC_SET 0x396UL 498 #define HWRM_TFC_TCAM_FREE 0x397UL 499 #define HWRM_TFC_IF_TBL_SET 0x398UL 500 #define HWRM_TFC_IF_TBL_GET 0x399UL 501 #define HWRM_TFC_TBL_SCOPE_CONFIG_GET 0x39aUL 502 #define HWRM_TFC_RESC_USAGE_QUERY 0x39bUL 503 #define HWRM_SV 0x400UL 504 #define HWRM_DBG_READ_DIRECT 0xff10UL 505 #define HWRM_DBG_READ_INDIRECT 0xff11UL 506 #define HWRM_DBG_WRITE_DIRECT 0xff12UL 507 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 508 #define HWRM_DBG_DUMP 0xff14UL 509 #define HWRM_DBG_ERASE_NVM 0xff15UL 510 #define HWRM_DBG_CFG 0xff16UL 511 #define HWRM_DBG_COREDUMP_LIST 0xff17UL 512 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 513 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 514 #define HWRM_DBG_FW_CLI 0xff1aUL 515 #define HWRM_DBG_I2C_CMD 0xff1bUL 516 #define HWRM_DBG_RING_INFO_GET 0xff1cUL 517 #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL 518 #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL 519 #define HWRM_DBG_DRV_TRACE 0xff1fUL 520 #define HWRM_DBG_QCAPS 0xff20UL 521 #define HWRM_DBG_QCFG 0xff21UL 522 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL 523 #define HWRM_DBG_USEQ_ALLOC 0xff23UL 524 #define HWRM_DBG_USEQ_FREE 0xff24UL 525 #define HWRM_DBG_USEQ_FLUSH 0xff25UL 526 #define HWRM_DBG_USEQ_QCAPS 0xff26UL 527 #define HWRM_DBG_USEQ_CW_CFG 0xff27UL 528 #define HWRM_DBG_USEQ_SCHED_CFG 0xff28UL 529 #define HWRM_DBG_USEQ_RUN 0xff29UL 530 #define HWRM_DBG_USEQ_DELIVERY_REQ 0xff2aUL 531 #define HWRM_DBG_USEQ_RESP_HDR 0xff2bUL 532 #define HWRM_NVM_GET_VPD_FIELD_INFO 0xffeaUL 533 #define HWRM_NVM_SET_VPD_FIELD_INFO 0xffebUL 534 #define HWRM_NVM_DEFRAG 0xffecUL 535 #define HWRM_NVM_REQ_ARBITRATION 0xffedUL 536 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 537 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 538 #define HWRM_NVM_FLUSH 0xfff0UL 539 #define HWRM_NVM_GET_VARIABLE 0xfff1UL 540 #define HWRM_NVM_SET_VARIABLE 0xfff2UL 541 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 542 #define HWRM_NVM_MODIFY 0xfff4UL 543 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 544 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 545 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 546 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 547 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 548 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 549 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 550 #define HWRM_NVM_RAW_DUMP 0xfffcUL 551 #define HWRM_NVM_READ 0xfffdUL 552 #define HWRM_NVM_WRITE 0xfffeUL 553 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 554 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 555 __le16 unused_0[3]; 556 }; 557 558 /* ret_codes (size:64b/8B) */ 559 struct ret_codes { 560 __le16 error_code; 561 #define HWRM_ERR_CODE_SUCCESS 0x0UL 562 #define HWRM_ERR_CODE_FAIL 0x1UL 563 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 564 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 565 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 566 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 567 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 568 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 569 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 570 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 571 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL 572 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL 573 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL 574 #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL 575 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL 576 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 577 #define HWRM_ERR_CODE_BUSY 0x10UL 578 #define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL 579 #define HWRM_ERR_CODE_PF_UNAVAILABLE 0x12UL 580 #define HWRM_ERR_CODE_ENTITY_NOT_PRESENT 0x13UL 581 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 582 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 583 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 584 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 585 __le16 unused_0[3]; 586 }; 587 588 /* hwrm_err_output (size:128b/16B) */ 589 struct hwrm_err_output { 590 __le16 error_code; 591 __le16 req_type; 592 __le16 seq_id; 593 __le16 resp_len; 594 __le32 opaque_0; 595 __le16 opaque_1; 596 u8 cmd_err; 597 u8 valid; 598 }; 599 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 600 #define HWRM_MAX_REQ_LEN 128 601 #define HWRM_MAX_RESP_LEN 704 602 #define HW_HASH_INDEX_SIZE 0x80 603 #define HW_HASH_KEY_SIZE 40 604 #define HWRM_RESP_VALID_KEY 1 605 #define HWRM_TARGET_ID_BONO 0xFFF8 606 #define HWRM_TARGET_ID_KONG 0xFFF9 607 #define HWRM_TARGET_ID_APE 0xFFFA 608 #define HWRM_TARGET_ID_TOOLS 0xFFFD 609 #define HWRM_VERSION_MAJOR 1 610 #define HWRM_VERSION_MINOR 10 611 #define HWRM_VERSION_UPDATE 3 612 #define HWRM_VERSION_RSVD 39 613 #define HWRM_VERSION_STR "1.10.3.39" 614 615 /* hwrm_ver_get_input (size:192b/24B) */ 616 struct hwrm_ver_get_input { 617 __le16 req_type; 618 __le16 cmpl_ring; 619 __le16 seq_id; 620 __le16 target_id; 621 __le64 resp_addr; 622 u8 hwrm_intf_maj; 623 u8 hwrm_intf_min; 624 u8 hwrm_intf_upd; 625 u8 unused_0[5]; 626 }; 627 628 /* hwrm_ver_get_output (size:1408b/176B) */ 629 struct hwrm_ver_get_output { 630 __le16 error_code; 631 __le16 req_type; 632 __le16 seq_id; 633 __le16 resp_len; 634 u8 hwrm_intf_maj_8b; 635 u8 hwrm_intf_min_8b; 636 u8 hwrm_intf_upd_8b; 637 u8 hwrm_intf_rsvd_8b; 638 u8 hwrm_fw_maj_8b; 639 u8 hwrm_fw_min_8b; 640 u8 hwrm_fw_bld_8b; 641 u8 hwrm_fw_rsvd_8b; 642 u8 mgmt_fw_maj_8b; 643 u8 mgmt_fw_min_8b; 644 u8 mgmt_fw_bld_8b; 645 u8 mgmt_fw_rsvd_8b; 646 u8 netctrl_fw_maj_8b; 647 u8 netctrl_fw_min_8b; 648 u8 netctrl_fw_bld_8b; 649 u8 netctrl_fw_rsvd_8b; 650 __le32 dev_caps_cfg; 651 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 652 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 653 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 654 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 655 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 656 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 657 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 658 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 659 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 660 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL 661 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL 662 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL 663 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL 664 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL 665 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL 666 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE 0x8000UL 667 u8 roce_fw_maj_8b; 668 u8 roce_fw_min_8b; 669 u8 roce_fw_bld_8b; 670 u8 roce_fw_rsvd_8b; 671 char hwrm_fw_name[16]; 672 char mgmt_fw_name[16]; 673 char netctrl_fw_name[16]; 674 char active_pkg_name[16]; 675 char roce_fw_name[16]; 676 __le16 chip_num; 677 u8 chip_rev; 678 u8 chip_metal; 679 u8 chip_bond_id; 680 u8 chip_platform_type; 681 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 682 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 683 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 684 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 685 __le16 max_req_win_len; 686 __le16 max_resp_len; 687 __le16 def_req_timeout; 688 u8 flags; 689 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 690 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 691 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY_BACKING_STORE 0x4UL 692 u8 unused_0[2]; 693 u8 always_1; 694 __le16 hwrm_intf_major; 695 __le16 hwrm_intf_minor; 696 __le16 hwrm_intf_build; 697 __le16 hwrm_intf_patch; 698 __le16 hwrm_fw_major; 699 __le16 hwrm_fw_minor; 700 __le16 hwrm_fw_build; 701 __le16 hwrm_fw_patch; 702 __le16 mgmt_fw_major; 703 __le16 mgmt_fw_minor; 704 __le16 mgmt_fw_build; 705 __le16 mgmt_fw_patch; 706 __le16 netctrl_fw_major; 707 __le16 netctrl_fw_minor; 708 __le16 netctrl_fw_build; 709 __le16 netctrl_fw_patch; 710 __le16 roce_fw_major; 711 __le16 roce_fw_minor; 712 __le16 roce_fw_build; 713 __le16 roce_fw_patch; 714 __le16 max_ext_req_len; 715 __le16 max_req_timeout; 716 u8 unused_1[3]; 717 u8 valid; 718 }; 719 720 /* eject_cmpl (size:128b/16B) */ 721 struct eject_cmpl { 722 __le16 type; 723 #define EJECT_CMPL_TYPE_MASK 0x3fUL 724 #define EJECT_CMPL_TYPE_SFT 0 725 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 726 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 727 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL 728 #define EJECT_CMPL_FLAGS_SFT 6 729 #define EJECT_CMPL_FLAGS_ERROR 0x40UL 730 __le16 len; 731 __le32 opaque; 732 __le16 v; 733 #define EJECT_CMPL_V 0x1UL 734 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL 735 #define EJECT_CMPL_ERRORS_SFT 1 736 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL 737 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 738 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1) 739 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1) 740 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1) 741 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1) 742 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH 743 __le16 reserved16; 744 __le32 unused_2; 745 }; 746 747 /* hwrm_cmpl (size:128b/16B) */ 748 struct hwrm_cmpl { 749 __le16 type; 750 #define CMPL_TYPE_MASK 0x3fUL 751 #define CMPL_TYPE_SFT 0 752 #define CMPL_TYPE_HWRM_DONE 0x20UL 753 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 754 __le16 sequence_id; 755 __le32 unused_1; 756 __le32 v; 757 #define CMPL_V 0x1UL 758 __le32 unused_3; 759 }; 760 761 /* hwrm_fwd_req_cmpl (size:128b/16B) */ 762 struct hwrm_fwd_req_cmpl { 763 __le16 req_len_type; 764 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 765 #define FWD_REQ_CMPL_TYPE_SFT 0 766 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 767 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 768 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 769 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 770 __le16 source_id; 771 __le32 unused0; 772 __le32 req_buf_addr_v[2]; 773 #define FWD_REQ_CMPL_V 0x1UL 774 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 775 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 776 }; 777 778 /* hwrm_fwd_resp_cmpl (size:128b/16B) */ 779 struct hwrm_fwd_resp_cmpl { 780 __le16 type; 781 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 782 #define FWD_RESP_CMPL_TYPE_SFT 0 783 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 784 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 785 __le16 source_id; 786 __le16 resp_len; 787 __le16 unused_1; 788 __le32 resp_buf_addr_v[2]; 789 #define FWD_RESP_CMPL_V 0x1UL 790 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 791 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 792 }; 793 794 /* hwrm_async_event_cmpl (size:128b/16B) */ 795 struct hwrm_async_event_cmpl { 796 __le16 type; 797 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 798 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 799 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 800 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 801 __le16 event_id; 802 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 803 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 804 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 805 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 806 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 807 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 808 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 809 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 810 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 811 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL 812 #define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG 0xaUL 813 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 814 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 815 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 816 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 817 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 818 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 819 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 820 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 821 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 822 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 823 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 824 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 825 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL 826 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 827 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 828 #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL 829 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL 830 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL 831 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL 832 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL 833 #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL 834 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL 835 #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL 836 #define ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST 0x42UL 837 #define ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE 0x43UL 838 #define ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP 0x44UL 839 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT 0x45UL 840 #define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD 0x46UL 841 #define ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE 0x47UL 842 #define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE 0x48UL 843 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR 0x49UL 844 #define ASYNC_EVENT_CMPL_EVENT_ID_CTX_ERROR 0x4aUL 845 #define ASYNC_EVENT_CMPL_EVENT_ID_UDCC_SESSION_CHANGE 0x4bUL 846 #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x4cUL 847 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 848 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 849 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 850 __le32 event_data2; 851 u8 opaque_v; 852 #define ASYNC_EVENT_CMPL_V 0x1UL 853 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 854 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 855 u8 timestamp_lo; 856 __le16 timestamp_hi; 857 __le32 event_data1; 858 }; 859 860 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 861 struct hwrm_async_event_cmpl_link_status_change { 862 __le16 type; 863 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 864 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 865 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 866 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 867 __le16 event_id; 868 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 869 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 870 __le32 event_data2; 871 u8 opaque_v; 872 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 873 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 874 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 875 u8 timestamp_lo; 876 __le16 timestamp_hi; 877 __le32 event_data1; 878 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 879 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 880 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 881 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 882 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 883 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 884 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 885 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 886 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 887 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 888 }; 889 890 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 891 struct hwrm_async_event_cmpl_port_conn_not_allowed { 892 __le16 type; 893 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 894 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 895 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 896 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 897 __le16 event_id; 898 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 899 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 900 __le32 event_data2; 901 u8 opaque_v; 902 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 903 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 904 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 905 u8 timestamp_lo; 906 __le16 timestamp_hi; 907 __le32 event_data1; 908 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 909 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 910 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 911 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 912 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 913 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 914 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 915 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 916 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 917 }; 918 919 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 920 struct hwrm_async_event_cmpl_link_speed_cfg_change { 921 __le16 type; 922 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 923 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 924 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 925 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 926 __le16 event_id; 927 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 928 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 929 __le32 event_data2; 930 u8 opaque_v; 931 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 932 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 933 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 934 u8 timestamp_lo; 935 __le16 timestamp_hi; 936 __le32 event_data1; 937 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 938 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 939 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 940 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 941 }; 942 943 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ 944 struct hwrm_async_event_cmpl_reset_notify { 945 __le16 type; 946 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL 947 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 948 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 949 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 950 __le16 event_id; 951 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 952 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 953 __le32 event_data2; 954 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK 0xffffUL 955 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0 956 u8 opaque_v; 957 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 958 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL 959 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 960 u8 timestamp_lo; 961 __le16 timestamp_hi; 962 __le32 event_data1; 963 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL 964 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0 965 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL 966 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL 967 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 968 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL 969 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8 970 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 971 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 972 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 973 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET (0x4UL << 8) 974 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION (0x5UL << 8) 975 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION 976 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 977 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 978 }; 979 980 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ 981 struct hwrm_async_event_cmpl_error_recovery { 982 __le16 type; 983 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL 984 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 985 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 986 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 987 __le16 event_id; 988 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL 989 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 990 __le32 event_data2; 991 u8 opaque_v; 992 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL 993 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL 994 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 995 u8 timestamp_lo; 996 __le16 timestamp_hi; 997 __le32 event_data1; 998 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL 999 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0 1000 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL 1001 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL 1002 }; 1003 1004 /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */ 1005 struct hwrm_async_event_cmpl_ring_monitor_msg { 1006 __le16 type; 1007 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK 0x3fUL 1008 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0 1009 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1010 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 1011 __le16 event_id; 1012 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL 1013 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 1014 __le32 event_data2; 1015 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL 1016 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0 1017 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX 0x0UL 1018 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX 0x1UL 1019 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 0x2UL 1020 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 1021 u8 opaque_v; 1022 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V 0x1UL 1023 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL 1024 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1 1025 u8 timestamp_lo; 1026 __le16 timestamp_hi; 1027 __le32 event_data1; 1028 }; 1029 1030 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 1031 struct hwrm_async_event_cmpl_vf_cfg_change { 1032 __le16 type; 1033 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 1034 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 1035 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1036 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 1037 __le16 event_id; 1038 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 1039 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 1040 __le32 event_data2; 1041 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK 0xffffUL 1042 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0 1043 u8 opaque_v; 1044 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 1045 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 1046 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 1047 u8 timestamp_lo; 1048 __le16 timestamp_hi; 1049 __le32 event_data1; 1050 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 1051 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 1052 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 1053 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 1054 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 1055 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TF_OWNERSHIP_RELEASE 0x20UL 1056 }; 1057 1058 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ 1059 struct hwrm_async_event_cmpl_default_vnic_change { 1060 __le16 type; 1061 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL 1062 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0 1063 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1064 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 1065 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL 1066 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6 1067 __le16 event_id; 1068 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL 1069 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 1070 __le32 event_data2; 1071 u8 opaque_v; 1072 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL 1073 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL 1074 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1 1075 u8 timestamp_lo; 1076 __le16 timestamp_hi; 1077 __le32 event_data1; 1078 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL 1079 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0 1080 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL 1081 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL 1082 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 1083 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL 1084 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2 1085 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL 1086 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10 1087 }; 1088 1089 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ 1090 struct hwrm_async_event_cmpl_hw_flow_aged { 1091 __le16 type; 1092 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL 1093 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 1094 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1095 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 1096 __le16 event_id; 1097 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL 1098 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 1099 __le32 event_data2; 1100 u8 opaque_v; 1101 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL 1102 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL 1103 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 1104 u8 timestamp_lo; 1105 __le16 timestamp_hi; 1106 __le32 event_data1; 1107 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL 1108 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0 1109 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL 1110 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31) 1111 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31) 1112 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX 1113 }; 1114 1115 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ 1116 struct hwrm_async_event_cmpl_eem_cache_flush_req { 1117 __le16 type; 1118 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL 1119 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0 1120 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1121 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 1122 __le16 event_id; 1123 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 1124 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 1125 __le32 event_data2; 1126 u8 opaque_v; 1127 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL 1128 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL 1129 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 1130 u8 timestamp_lo; 1131 __le16 timestamp_hi; 1132 __le32 event_data1; 1133 }; 1134 1135 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ 1136 struct hwrm_async_event_cmpl_eem_cache_flush_done { 1137 __le16 type; 1138 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL 1139 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0 1140 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1141 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 1142 __le16 event_id; 1143 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 1144 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 1145 __le32 event_data2; 1146 u8 opaque_v; 1147 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL 1148 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL 1149 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 1150 u8 timestamp_lo; 1151 __le16 timestamp_hi; 1152 __le32 event_data1; 1153 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL 1154 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0 1155 }; 1156 1157 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ 1158 struct hwrm_async_event_cmpl_deferred_response { 1159 __le16 type; 1160 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK 0x3fUL 1161 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0 1162 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1163 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 1164 __le16 event_id; 1165 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL 1166 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 1167 __le32 event_data2; 1168 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL 1169 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0 1170 u8 opaque_v; 1171 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V 0x1UL 1172 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL 1173 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1 1174 u8 timestamp_lo; 1175 __le16 timestamp_hi; 1176 __le32 event_data1; 1177 }; 1178 1179 /* hwrm_async_event_cmpl_echo_request (size:128b/16B) */ 1180 struct hwrm_async_event_cmpl_echo_request { 1181 __le16 type; 1182 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK 0x3fUL 1183 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0 1184 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1185 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 1186 __le16 event_id; 1187 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 0x42UL 1188 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 1189 __le32 event_data2; 1190 u8 opaque_v; 1191 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_V 0x1UL 1192 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK 0xfeUL 1193 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1 1194 u8 timestamp_lo; 1195 __le16 timestamp_hi; 1196 __le32 event_data1; 1197 }; 1198 1199 /* hwrm_async_event_cmpl_phc_update (size:128b/16B) */ 1200 struct hwrm_async_event_cmpl_phc_update { 1201 __le16 type; 1202 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_MASK 0x3fUL 1203 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_SFT 0 1204 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1205 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT 1206 __le16 event_id; 1207 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 0x43UL 1208 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 1209 __le32 event_data2; 1210 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_MASK 0xffffUL 1211 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_SFT 0 1212 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_MASK 0xffff0000UL 1213 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_SFT 16 1214 u8 opaque_v; 1215 #define ASYNC_EVENT_CMPL_PHC_UPDATE_V 0x1UL 1216 #define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_MASK 0xfeUL 1217 #define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_SFT 1 1218 u8 timestamp_lo; 1219 __le16 timestamp_hi; 1220 __le32 event_data1; 1221 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK 0xfUL 1222 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT 0 1223 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_MASTER 0x1UL 1224 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_SECONDARY 0x2UL 1225 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_FAILOVER 0x3UL 1226 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE 0x4UL 1227 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE 1228 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK 0xffff0UL 1229 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT 4 1230 }; 1231 1232 /* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */ 1233 struct hwrm_async_event_cmpl_pps_timestamp { 1234 __le16 type; 1235 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK 0x3fUL 1236 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0 1237 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1238 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 1239 __le16 event_id; 1240 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 0x44UL 1241 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 1242 __le32 event_data2; 1243 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE 0x1UL 1244 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL 0x0UL 1245 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 0x1UL 1246 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 1247 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK 0xeUL 1248 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT 1 1249 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK 0xffff0UL 1250 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT 4 1251 u8 opaque_v; 1252 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V 0x1UL 1253 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK 0xfeUL 1254 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1 1255 u8 timestamp_lo; 1256 __le16 timestamp_hi; 1257 __le32 event_data1; 1258 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK 0xffffffffUL 1259 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT 0 1260 }; 1261 1262 /* hwrm_async_event_cmpl_error_report (size:128b/16B) */ 1263 struct hwrm_async_event_cmpl_error_report { 1264 __le16 type; 1265 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK 0x3fUL 1266 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0 1267 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1268 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 1269 __le16 event_id; 1270 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 0x45UL 1271 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 1272 __le32 event_data2; 1273 u8 opaque_v; 1274 #define ASYNC_EVENT_CMPL_ERROR_REPORT_V 0x1UL 1275 #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK 0xfeUL 1276 #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1 1277 u8 timestamp_lo; 1278 __le16 timestamp_hi; 1279 __le32 event_data1; 1280 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1281 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0 1282 }; 1283 1284 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */ 1285 struct hwrm_async_event_cmpl_hwrm_error { 1286 __le16 type; 1287 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL 1288 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 1289 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1290 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 1291 __le16 event_id; 1292 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL 1293 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 1294 __le32 event_data2; 1295 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL 1296 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 1297 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL 1298 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL 1299 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL 1300 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 1301 u8 opaque_v; 1302 #define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL 1303 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL 1304 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 1305 u8 timestamp_lo; 1306 __le16 timestamp_hi; 1307 __le32 event_data1; 1308 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL 1309 }; 1310 1311 /* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */ 1312 struct hwrm_async_event_cmpl_error_report_base { 1313 __le16 type; 1314 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK 0x3fUL 1315 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0 1316 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1317 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 1318 __le16 event_id; 1319 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 0x45UL 1320 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 1321 __le32 event_data2; 1322 u8 opaque_v; 1323 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V 0x1UL 1324 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK 0xfeUL 1325 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1 1326 u8 timestamp_lo; 1327 __le16 timestamp_hi; 1328 __le32 event_data1; 1329 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1330 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT 0 1331 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED 0x0UL 1332 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 1333 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 1334 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM 0x3UL 1335 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL 1336 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD 0x5UL 1337 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 0x6UL 1338 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 1339 }; 1340 1341 /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ 1342 struct hwrm_async_event_cmpl_error_report_pause_storm { 1343 __le16 type; 1344 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK 0x3fUL 1345 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT 0 1346 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1347 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 1348 __le16 event_id; 1349 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 0x45UL 1350 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 1351 __le32 event_data2; 1352 u8 opaque_v; 1353 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V 0x1UL 1354 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK 0xfeUL 1355 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1 1356 u8 timestamp_lo; 1357 __le16 timestamp_hi; 1358 __le32 event_data1; 1359 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1360 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT 0 1361 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 1362 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 1363 }; 1364 1365 /* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */ 1366 struct hwrm_async_event_cmpl_error_report_invalid_signal { 1367 __le16 type; 1368 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK 0x3fUL 1369 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT 0 1370 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1371 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 1372 __le16 event_id; 1373 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 0x45UL 1374 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 1375 __le32 event_data2; 1376 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK 0xffUL 1377 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT 0 1378 u8 opaque_v; 1379 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V 0x1UL 1380 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK 0xfeUL 1381 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1 1382 u8 timestamp_lo; 1383 __le16 timestamp_hi; 1384 __le32 event_data1; 1385 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1386 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT 0 1387 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 1388 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 1389 }; 1390 1391 /* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */ 1392 struct hwrm_async_event_cmpl_error_report_nvm { 1393 __le16 type; 1394 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK 0x3fUL 1395 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0 1396 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1397 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 1398 __le16 event_id; 1399 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 0x45UL 1400 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 1401 __le32 event_data2; 1402 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK 0xffffffffUL 1403 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT 0 1404 u8 opaque_v; 1405 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V 0x1UL 1406 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK 0xfeUL 1407 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1 1408 u8 timestamp_lo; 1409 __le16 timestamp_hi; 1410 __le32 event_data1; 1411 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1412 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT 0 1413 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 0x3UL 1414 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 1415 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK 0xff00UL 1416 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT 8 1417 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE (0x1UL << 8) 1418 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE (0x2UL << 8) 1419 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE 1420 }; 1421 1422 /* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */ 1423 struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold { 1424 __le16 type; 1425 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK 0x3fUL 1426 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT 0 1427 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1428 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT 1429 __le16 event_id; 1430 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT 0x45UL 1431 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT 1432 __le32 event_data2; 1433 u8 opaque_v; 1434 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V 0x1UL 1435 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK 0xfeUL 1436 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT 1 1437 u8 timestamp_lo; 1438 __le16 timestamp_hi; 1439 __le32 event_data1; 1440 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1441 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT 0 1442 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL 1443 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 1444 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK 0xffffff00UL 1445 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT 8 1446 }; 1447 1448 /* hwrm_async_event_cmpl_error_report_thermal (size:128b/16B) */ 1449 struct hwrm_async_event_cmpl_error_report_thermal { 1450 __le16 type; 1451 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_MASK 0x3fUL 1452 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_SFT 0 1453 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1454 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT 1455 __le16 event_id; 1456 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT 0x45UL 1457 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT 1458 __le32 event_data2; 1459 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK 0xffUL 1460 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_SFT 0 1461 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_MASK 0xff00UL 1462 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_SFT 8 1463 u8 opaque_v; 1464 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_V 0x1UL 1465 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_MASK 0xfeUL 1466 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_SFT 1 1467 u8 timestamp_lo; 1468 __le16 timestamp_hi; 1469 __le32 event_data1; 1470 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1471 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_SFT 0 1472 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT 0x5UL 1473 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT 1474 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_MASK 0x700UL 1475 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SFT 8 1476 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_WARN (0x0UL << 8) 1477 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_CRITICAL (0x1UL << 8) 1478 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_FATAL (0x2UL << 8) 1479 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN (0x3UL << 8) 1480 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN 1481 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR 0x800UL 1482 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_DECREASING (0x0UL << 11) 1483 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING (0x1UL << 11) 1484 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING 1485 }; 1486 1487 /* hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported (size:128b/16B) */ 1488 struct hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported { 1489 __le16 type; 1490 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_MASK 0x3fUL 1491 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_SFT 0 1492 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1493 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT 1494 __le16 event_id; 1495 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT 0x45UL 1496 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT 1497 __le32 event_data2; 1498 u8 opaque_v; 1499 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_V 0x1UL 1500 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_MASK 0xfeUL 1501 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_SFT 1 1502 u8 timestamp_lo; 1503 __le16 timestamp_hi; 1504 __le32 event_data1; 1505 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1506 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_SFT 0 1507 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 0x6UL 1508 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 1509 }; 1510 1511 /* hwrm_func_reset_input (size:192b/24B) */ 1512 struct hwrm_func_reset_input { 1513 __le16 req_type; 1514 __le16 cmpl_ring; 1515 __le16 seq_id; 1516 __le16 target_id; 1517 __le64 resp_addr; 1518 __le32 enables; 1519 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 1520 __le16 vf_id; 1521 u8 func_reset_level; 1522 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 1523 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 1524 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 1525 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 1526 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 1527 u8 unused_0; 1528 }; 1529 1530 /* hwrm_func_reset_output (size:128b/16B) */ 1531 struct hwrm_func_reset_output { 1532 __le16 error_code; 1533 __le16 req_type; 1534 __le16 seq_id; 1535 __le16 resp_len; 1536 u8 unused_0[7]; 1537 u8 valid; 1538 }; 1539 1540 /* hwrm_func_getfid_input (size:192b/24B) */ 1541 struct hwrm_func_getfid_input { 1542 __le16 req_type; 1543 __le16 cmpl_ring; 1544 __le16 seq_id; 1545 __le16 target_id; 1546 __le64 resp_addr; 1547 __le32 enables; 1548 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 1549 __le16 pci_id; 1550 u8 unused_0[2]; 1551 }; 1552 1553 /* hwrm_func_getfid_output (size:128b/16B) */ 1554 struct hwrm_func_getfid_output { 1555 __le16 error_code; 1556 __le16 req_type; 1557 __le16 seq_id; 1558 __le16 resp_len; 1559 __le16 fid; 1560 u8 unused_0[5]; 1561 u8 valid; 1562 }; 1563 1564 /* hwrm_func_vf_alloc_input (size:192b/24B) */ 1565 struct hwrm_func_vf_alloc_input { 1566 __le16 req_type; 1567 __le16 cmpl_ring; 1568 __le16 seq_id; 1569 __le16 target_id; 1570 __le64 resp_addr; 1571 __le32 enables; 1572 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 1573 __le16 first_vf_id; 1574 __le16 num_vfs; 1575 }; 1576 1577 /* hwrm_func_vf_alloc_output (size:128b/16B) */ 1578 struct hwrm_func_vf_alloc_output { 1579 __le16 error_code; 1580 __le16 req_type; 1581 __le16 seq_id; 1582 __le16 resp_len; 1583 __le16 first_vf_id; 1584 u8 unused_0[5]; 1585 u8 valid; 1586 }; 1587 1588 /* hwrm_func_vf_free_input (size:192b/24B) */ 1589 struct hwrm_func_vf_free_input { 1590 __le16 req_type; 1591 __le16 cmpl_ring; 1592 __le16 seq_id; 1593 __le16 target_id; 1594 __le64 resp_addr; 1595 __le32 enables; 1596 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 1597 __le16 first_vf_id; 1598 __le16 num_vfs; 1599 }; 1600 1601 /* hwrm_func_vf_free_output (size:128b/16B) */ 1602 struct hwrm_func_vf_free_output { 1603 __le16 error_code; 1604 __le16 req_type; 1605 __le16 seq_id; 1606 __le16 resp_len; 1607 u8 unused_0[7]; 1608 u8 valid; 1609 }; 1610 1611 /* hwrm_func_vf_cfg_input (size:576b/72B) */ 1612 struct hwrm_func_vf_cfg_input { 1613 __le16 req_type; 1614 __le16 cmpl_ring; 1615 __le16 seq_id; 1616 __le16 target_id; 1617 __le64 resp_addr; 1618 __le32 enables; 1619 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 1620 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 1621 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 1622 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 1623 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 1624 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 1625 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 1626 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 1627 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 1628 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 1629 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 1630 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 1631 #define FUNC_VF_CFG_REQ_ENABLES_NUM_KTLS_TX_KEY_CTXS 0x1000UL 1632 #define FUNC_VF_CFG_REQ_ENABLES_NUM_KTLS_RX_KEY_CTXS 0x2000UL 1633 #define FUNC_VF_CFG_REQ_ENABLES_NUM_QUIC_TX_KEY_CTXS 0x4000UL 1634 #define FUNC_VF_CFG_REQ_ENABLES_NUM_QUIC_RX_KEY_CTXS 0x8000UL 1635 __le16 mtu; 1636 __le16 guest_vlan; 1637 __le16 async_event_cr; 1638 u8 dflt_mac_addr[6]; 1639 __le32 flags; 1640 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 1641 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 1642 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 1643 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 1644 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 1645 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 1646 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 1647 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 1648 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x100UL 1649 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x200UL 1650 __le16 num_rsscos_ctxs; 1651 __le16 num_cmpl_rings; 1652 __le16 num_tx_rings; 1653 __le16 num_rx_rings; 1654 __le16 num_l2_ctxs; 1655 __le16 num_vnics; 1656 __le16 num_stat_ctxs; 1657 __le16 num_hw_ring_grps; 1658 __le32 num_ktls_tx_key_ctxs; 1659 __le32 num_ktls_rx_key_ctxs; 1660 __le16 num_msix; 1661 u8 unused[2]; 1662 __le32 num_quic_tx_key_ctxs; 1663 __le32 num_quic_rx_key_ctxs; 1664 }; 1665 1666 /* hwrm_func_vf_cfg_output (size:128b/16B) */ 1667 struct hwrm_func_vf_cfg_output { 1668 __le16 error_code; 1669 __le16 req_type; 1670 __le16 seq_id; 1671 __le16 resp_len; 1672 u8 unused_0[7]; 1673 u8 valid; 1674 }; 1675 1676 /* hwrm_func_qcaps_input (size:192b/24B) */ 1677 struct hwrm_func_qcaps_input { 1678 __le16 req_type; 1679 __le16 cmpl_ring; 1680 __le16 seq_id; 1681 __le16 target_id; 1682 __le64 resp_addr; 1683 __le16 fid; 1684 u8 unused_0[6]; 1685 }; 1686 1687 /* hwrm_func_qcaps_output (size:1088b/136B) */ 1688 struct hwrm_func_qcaps_output { 1689 __le16 error_code; 1690 __le16 req_type; 1691 __le16 seq_id; 1692 __le16 resp_len; 1693 __le16 fid; 1694 __le16 port_id; 1695 __le32 flags; 1696 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1697 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 1698 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1699 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1700 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1701 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1702 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1703 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1704 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1705 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1706 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 1707 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 1708 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 1709 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 1710 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 1711 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 1712 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 1713 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 1714 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 1715 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 1716 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 1717 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL 1718 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL 1719 #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL 1720 #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL 1721 #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL 1722 #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL 1723 #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL 1724 #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL 1725 #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL 1726 #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL 1727 #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL 1728 u8 mac_address[6]; 1729 __le16 max_rsscos_ctx; 1730 __le16 max_cmpl_rings; 1731 __le16 max_tx_rings; 1732 __le16 max_rx_rings; 1733 __le16 max_l2_ctxs; 1734 __le16 max_vnics; 1735 __le16 first_vf_id; 1736 __le16 max_vfs; 1737 __le16 max_stat_ctx; 1738 __le32 max_encap_records; 1739 __le32 max_decap_records; 1740 __le32 max_tx_em_flows; 1741 __le32 max_tx_wm_flows; 1742 __le32 max_rx_em_flows; 1743 __le32 max_rx_wm_flows; 1744 __le32 max_mcast_filters; 1745 __le32 max_flow_id; 1746 __le32 max_hw_ring_grps; 1747 __le16 max_sp_tx_rings; 1748 __le16 max_msix_vfs; 1749 __le32 flags_ext; 1750 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL 1751 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL 1752 #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL 1753 #define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT 0x8UL 1754 #define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT 0x10UL 1755 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL 1756 #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL 1757 #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL 1758 #define FUNC_QCAPS_RESP_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED 0x100UL 1759 #define FUNC_QCAPS_RESP_FLAGS_EXT_SOC_SPD_SUPPORTED 0x200UL 1760 #define FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED 0x400UL 1761 #define FUNC_QCAPS_RESP_FLAGS_EXT_FAST_RESET_CAPABLE 0x800UL 1762 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_METADATA_CFG_CAPABLE 0x1000UL 1763 #define FUNC_QCAPS_RESP_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED 0x2000UL 1764 #define FUNC_QCAPS_RESP_FLAGS_EXT_BD_METADATA_SUPPORTED 0x4000UL 1765 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECHO_REQUEST_SUPPORTED 0x8000UL 1766 #define FUNC_QCAPS_RESP_FLAGS_EXT_NPAR_1_2_SUPPORTED 0x10000UL 1767 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PTM_SUPPORTED 0x20000UL 1768 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED 0x40000UL 1769 #define FUNC_QCAPS_RESP_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED 0x80000UL 1770 #define FUNC_QCAPS_RESP_FLAGS_EXT_PARTITION_BW_SUPPORTED 0x100000UL 1771 #define FUNC_QCAPS_RESP_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED 0x200000UL 1772 #define FUNC_QCAPS_RESP_FLAGS_EXT_KTLS_SUPPORTED 0x400000UL 1773 #define FUNC_QCAPS_RESP_FLAGS_EXT_EP_RATE_CONTROL 0x800000UL 1774 #define FUNC_QCAPS_RESP_FLAGS_EXT_MIN_BW_SUPPORTED 0x1000000UL 1775 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_COAL_CMPL_CAP 0x2000000UL 1776 #define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_SUPPORTED 0x4000000UL 1777 #define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_REQUIRED 0x8000000UL 1778 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED 0x10000000UL 1779 #define FUNC_QCAPS_RESP_FLAGS_EXT_DBR_PACING_SUPPORTED 0x20000000UL 1780 #define FUNC_QCAPS_RESP_FLAGS_EXT_HW_DBR_DROP_RECOV_SUPPORTED 0x40000000UL 1781 #define FUNC_QCAPS_RESP_FLAGS_EXT_DISABLE_CQ_OVERFLOW_DETECTION_SUPPORTED 0x80000000UL 1782 u8 max_schqs; 1783 u8 mpc_chnls_cap; 1784 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL 1785 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE 0x2UL 1786 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA 0x4UL 1787 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA 0x8UL 1788 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE 0x10UL 1789 __le16 max_key_ctxs_alloc; 1790 __le32 flags_ext2; 1791 #define FUNC_QCAPS_RESP_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED 0x1UL 1792 #define FUNC_QCAPS_RESP_FLAGS_EXT2_QUIC_SUPPORTED 0x2UL 1793 #define FUNC_QCAPS_RESP_FLAGS_EXT2_KDNET_SUPPORTED 0x4UL 1794 #define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED 0x8UL 1795 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED 0x10UL 1796 #define FUNC_QCAPS_RESP_FLAGS_EXT2_GENERIC_STATS_SUPPORTED 0x20UL 1797 #define FUNC_QCAPS_RESP_FLAGS_EXT2_UDP_GSO_SUPPORTED 0x40UL 1798 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SYNCE_SUPPORTED 0x80UL 1799 #define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED 0x100UL 1800 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TX_PKT_TS_CMPL_SUPPORTED 0x200UL 1801 #define FUNC_QCAPS_RESP_FLAGS_EXT2_HW_LAG_SUPPORTED 0x400UL 1802 #define FUNC_QCAPS_RESP_FLAGS_EXT2_ON_CHIP_CTX_SUPPORTED 0x800UL 1803 #define FUNC_QCAPS_RESP_FLAGS_EXT2_STEERING_TAG_SUPPORTED 0x1000UL 1804 #define FUNC_QCAPS_RESP_FLAGS_EXT2_ENHANCED_VF_SCALE_SUPPORTED 0x2000UL 1805 #define FUNC_QCAPS_RESP_FLAGS_EXT2_KEY_XID_PARTITION_SUPPORTED 0x4000UL 1806 #define FUNC_QCAPS_RESP_FLAGS_EXT2_CONCURRENT_KTLS_QUIC_SUPPORTED 0x8000UL 1807 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_CROSS_TC_CAP_SUPPORTED 0x10000UL 1808 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_PER_TC_CAP_SUPPORTED 0x20000UL 1809 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_PER_TC_RESERVATION_SUPPORTED 0x40000UL 1810 #define FUNC_QCAPS_RESP_FLAGS_EXT2_DB_ERROR_STATS_SUPPORTED 0x80000UL 1811 #define FUNC_QCAPS_RESP_FLAGS_EXT2_ROCE_VF_RESOURCE_MGMT_SUPPORTED 0x100000UL 1812 #define FUNC_QCAPS_RESP_FLAGS_EXT2_UDCC_SUPPORTED 0x200000UL 1813 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TIMED_TX_SO_TXTIME_SUPPORTED 0x400000UL 1814 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_MAX_RESOURCE_LIMITS_SUPPORTED 0x800000UL 1815 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TF_INGRESS_NIC_FLOW_SUPPORTED 0x1000000UL 1816 #define FUNC_QCAPS_RESP_FLAGS_EXT2_LPBK_STATS_SUPPORTED 0x2000000UL 1817 __le16 tunnel_disable_flag; 1818 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN 0x1UL 1819 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NGE 0x2UL 1820 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NVGRE 0x4UL 1821 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_L2GRE 0x8UL 1822 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_GRE 0x10UL 1823 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP 0x20UL 1824 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_MPLS 0x40UL 1825 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE 0x80UL 1826 __le16 xid_partition_cap; 1827 #define FUNC_QCAPS_RESP_XID_PARTITION_CAP_TX_CK 0x1UL 1828 #define FUNC_QCAPS_RESP_XID_PARTITION_CAP_RX_CK 0x2UL 1829 u8 device_serial_number[8]; 1830 __le16 ctxs_per_partition; 1831 u8 unused_2[2]; 1832 __le32 roce_vf_max_av; 1833 __le32 roce_vf_max_cq; 1834 __le32 roce_vf_max_mrw; 1835 __le32 roce_vf_max_qp; 1836 __le32 roce_vf_max_srq; 1837 __le32 roce_vf_max_gid; 1838 u8 unused_3[3]; 1839 u8 valid; 1840 }; 1841 1842 /* hwrm_func_qcfg_input (size:192b/24B) */ 1843 struct hwrm_func_qcfg_input { 1844 __le16 req_type; 1845 __le16 cmpl_ring; 1846 __le16 seq_id; 1847 __le16 target_id; 1848 __le64 resp_addr; 1849 __le16 fid; 1850 u8 unused_0[6]; 1851 }; 1852 1853 /* hwrm_func_qcfg_output (size:1280b/160B) */ 1854 struct hwrm_func_qcfg_output { 1855 __le16 error_code; 1856 __le16 req_type; 1857 __le16 seq_id; 1858 __le16 resp_len; 1859 __le16 fid; 1860 __le16 port_id; 1861 __le16 vlan; 1862 __le16 flags; 1863 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1864 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1865 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 1866 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 1867 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 1868 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 1869 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 1870 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL 1871 #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL 1872 #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL 1873 #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL 1874 #define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL 1875 #define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED 0x1000UL 1876 #define FUNC_QCFG_RESP_FLAGS_MULTI_ROOT 0x2000UL 1877 #define FUNC_QCFG_RESP_FLAGS_ENABLE_RDMA_SRIOV 0x4000UL 1878 #define FUNC_QCFG_RESP_FLAGS_ROCE_VNIC_ID_VALID 0x8000UL 1879 u8 mac_address[6]; 1880 __le16 pci_id; 1881 __le16 alloc_rsscos_ctx; 1882 __le16 alloc_cmpl_rings; 1883 __le16 alloc_tx_rings; 1884 __le16 alloc_rx_rings; 1885 __le16 alloc_l2_ctx; 1886 __le16 alloc_vnics; 1887 __le16 admin_mtu; 1888 __le16 mru; 1889 __le16 stat_ctx_id; 1890 u8 port_partition_type; 1891 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1892 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1893 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1894 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1895 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 1896 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_2 0x5UL 1897 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 1898 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 1899 u8 port_pf_cnt; 1900 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 1901 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 1902 __le16 dflt_vnic_id; 1903 __le16 max_mtu_configured; 1904 __le32 min_bw; 1905 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1906 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 1907 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 1908 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 1909 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 1910 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 1911 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1912 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 1913 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1914 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1915 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1916 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1917 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1918 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1919 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 1920 __le32 max_bw; 1921 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1922 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 1923 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 1924 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 1925 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 1926 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 1927 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1928 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 1929 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1930 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1931 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1932 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1933 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1934 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1935 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 1936 u8 evb_mode; 1937 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 1938 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 1939 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 1940 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 1941 u8 options; 1942 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1943 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 1944 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1945 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1946 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 1947 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1948 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 1949 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1950 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1951 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1952 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 1953 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 1954 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 1955 __le16 alloc_vfs; 1956 __le32 alloc_mcast_filters; 1957 __le32 alloc_hw_ring_grps; 1958 __le16 alloc_sp_tx_rings; 1959 __le16 alloc_stat_ctx; 1960 __le16 alloc_msix; 1961 __le16 registered_vfs; 1962 __le16 l2_doorbell_bar_size_kb; 1963 u8 active_endpoints; 1964 u8 always_1; 1965 __le32 reset_addr_poll; 1966 __le16 legacy_l2_db_size_kb; 1967 __le16 svif_info; 1968 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL 1969 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0 1970 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL 1971 u8 mpc_chnls; 1972 #define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED 0x1UL 1973 #define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED 0x2UL 1974 #define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL 1975 #define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL 1976 #define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL 1977 u8 db_page_size; 1978 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_4KB 0x0UL 1979 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_8KB 0x1UL 1980 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_16KB 0x2UL 1981 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_32KB 0x3UL 1982 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_64KB 0x4UL 1983 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_128KB 0x5UL 1984 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_256KB 0x6UL 1985 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_512KB 0x7UL 1986 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_1MB 0x8UL 1987 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_2MB 0x9UL 1988 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB 0xaUL 1989 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_LAST FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB 1990 __le16 roce_vnic_id; 1991 __le32 partition_min_bw; 1992 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1993 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_SFT 0 1994 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE 0x10000000UL 1995 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 1996 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 1997 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES 1998 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1999 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 2000 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2001 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 2002 __le32 partition_max_bw; 2003 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2004 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_SFT 0 2005 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE 0x10000000UL 2006 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 2007 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 2008 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES 2009 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2010 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 2011 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2012 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 2013 __le16 host_mtu; 2014 u8 unused_3[2]; 2015 u8 unused_4[2]; 2016 u8 port_kdnet_mode; 2017 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_DISABLED 0x0UL 2018 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED 0x1UL 2019 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_LAST FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED 2020 u8 kdnet_pcie_function; 2021 __le16 port_kdnet_fid; 2022 u8 unused_5[2]; 2023 __le32 num_ktls_tx_key_ctxs; 2024 __le32 num_ktls_rx_key_ctxs; 2025 u8 lag_id; 2026 u8 parif; 2027 u8 fw_lag_id; 2028 u8 unused_6; 2029 __le32 num_quic_tx_key_ctxs; 2030 __le32 num_quic_rx_key_ctxs; 2031 __le32 roce_max_av_per_vf; 2032 __le32 roce_max_cq_per_vf; 2033 __le32 roce_max_mrw_per_vf; 2034 __le32 roce_max_qp_per_vf; 2035 __le32 roce_max_srq_per_vf; 2036 __le32 roce_max_gid_per_vf; 2037 __le16 xid_partition_cfg; 2038 #define FUNC_QCFG_RESP_XID_PARTITION_CFG_TX_CK 0x1UL 2039 #define FUNC_QCFG_RESP_XID_PARTITION_CFG_RX_CK 0x2UL 2040 u8 unused_7; 2041 u8 valid; 2042 }; 2043 2044 /* hwrm_func_cfg_input (size:1280b/160B) */ 2045 struct hwrm_func_cfg_input { 2046 __le16 req_type; 2047 __le16 cmpl_ring; 2048 __le16 seq_id; 2049 __le16 target_id; 2050 __le64 resp_addr; 2051 __le16 fid; 2052 __le16 num_msix; 2053 __le32 flags; 2054 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 2055 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 2056 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 2057 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 2058 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 2059 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 2060 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 2061 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 2062 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 2063 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 2064 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 2065 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 2066 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 2067 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 2068 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 2069 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 2070 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 2071 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL 2072 #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL 2073 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL 2074 #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL 2075 #define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS 0x4000000UL 2076 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x8000000UL 2077 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL 2078 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_ENABLE 0x20000000UL 2079 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_DISABLE 0x40000000UL 2080 __le32 enables; 2081 #define FUNC_CFG_REQ_ENABLES_ADMIN_MTU 0x1UL 2082 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 2083 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 2084 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 2085 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 2086 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 2087 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 2088 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 2089 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 2090 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 2091 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 2092 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 2093 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 2094 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 2095 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 2096 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 2097 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 2098 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 2099 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 2100 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 2101 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 2102 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 2103 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 2104 #define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL 2105 #define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL 2106 #define FUNC_CFG_REQ_ENABLES_MPC_CHNLS 0x2000000UL 2107 #define FUNC_CFG_REQ_ENABLES_PARTITION_MIN_BW 0x4000000UL 2108 #define FUNC_CFG_REQ_ENABLES_PARTITION_MAX_BW 0x8000000UL 2109 #define FUNC_CFG_REQ_ENABLES_TPID 0x10000000UL 2110 #define FUNC_CFG_REQ_ENABLES_HOST_MTU 0x20000000UL 2111 #define FUNC_CFG_REQ_ENABLES_KTLS_TX_KEY_CTXS 0x40000000UL 2112 #define FUNC_CFG_REQ_ENABLES_KTLS_RX_KEY_CTXS 0x80000000UL 2113 __le16 admin_mtu; 2114 __le16 mru; 2115 __le16 num_rsscos_ctxs; 2116 __le16 num_cmpl_rings; 2117 __le16 num_tx_rings; 2118 __le16 num_rx_rings; 2119 __le16 num_l2_ctxs; 2120 __le16 num_vnics; 2121 __le16 num_stat_ctxs; 2122 __le16 num_hw_ring_grps; 2123 u8 dflt_mac_addr[6]; 2124 __le16 dflt_vlan; 2125 __be32 dflt_ip_addr[4]; 2126 __le32 min_bw; 2127 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2128 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 2129 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 2130 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 2131 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 2132 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 2133 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2134 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 2135 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2136 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2137 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2138 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2139 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2140 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2141 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 2142 __le32 max_bw; 2143 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2144 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 2145 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 2146 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 2147 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 2148 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 2149 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2150 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 2151 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2152 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2153 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2154 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2155 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2156 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2157 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 2158 __le16 async_event_cr; 2159 u8 vlan_antispoof_mode; 2160 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 2161 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 2162 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 2163 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 2164 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 2165 u8 allowed_vlan_pris; 2166 u8 evb_mode; 2167 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 2168 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 2169 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 2170 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 2171 u8 options; 2172 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 2173 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 2174 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 2175 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 2176 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 2177 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 2178 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 2179 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 2180 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 2181 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 2182 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 2183 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 2184 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 2185 __le16 num_mcast_filters; 2186 __le16 schq_id; 2187 __le16 mpc_chnls; 2188 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE 0x1UL 2189 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE 0x2UL 2190 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE 0x4UL 2191 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE 0x8UL 2192 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE 0x10UL 2193 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE 0x20UL 2194 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE 0x40UL 2195 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE 0x80UL 2196 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE 0x100UL 2197 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE 0x200UL 2198 __le32 partition_min_bw; 2199 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2200 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_SFT 0 2201 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE 0x10000000UL 2202 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 2203 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 2204 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES 2205 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2206 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 2207 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2208 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 2209 __le32 partition_max_bw; 2210 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2211 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_SFT 0 2212 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE 0x10000000UL 2213 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 2214 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 2215 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES 2216 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2217 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 2218 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2219 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 2220 __be16 tpid; 2221 __le16 host_mtu; 2222 __le32 flags2; 2223 #define FUNC_CFG_REQ_FLAGS2_KTLS_KEY_CTX_ASSETS_TEST 0x1UL 2224 #define FUNC_CFG_REQ_FLAGS2_QUIC_KEY_CTX_ASSETS_TEST 0x2UL 2225 __le32 enables2; 2226 #define FUNC_CFG_REQ_ENABLES2_KDNET 0x1UL 2227 #define FUNC_CFG_REQ_ENABLES2_DB_PAGE_SIZE 0x2UL 2228 #define FUNC_CFG_REQ_ENABLES2_QUIC_TX_KEY_CTXS 0x4UL 2229 #define FUNC_CFG_REQ_ENABLES2_QUIC_RX_KEY_CTXS 0x8UL 2230 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_AV_PER_VF 0x10UL 2231 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_CQ_PER_VF 0x20UL 2232 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_MRW_PER_VF 0x40UL 2233 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_QP_PER_VF 0x80UL 2234 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_SRQ_PER_VF 0x100UL 2235 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_GID_PER_VF 0x200UL 2236 #define FUNC_CFG_REQ_ENABLES2_XID_PARTITION_CFG 0x400UL 2237 u8 port_kdnet_mode; 2238 #define FUNC_CFG_REQ_PORT_KDNET_MODE_DISABLED 0x0UL 2239 #define FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED 0x1UL 2240 #define FUNC_CFG_REQ_PORT_KDNET_MODE_LAST FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED 2241 u8 db_page_size; 2242 #define FUNC_CFG_REQ_DB_PAGE_SIZE_4KB 0x0UL 2243 #define FUNC_CFG_REQ_DB_PAGE_SIZE_8KB 0x1UL 2244 #define FUNC_CFG_REQ_DB_PAGE_SIZE_16KB 0x2UL 2245 #define FUNC_CFG_REQ_DB_PAGE_SIZE_32KB 0x3UL 2246 #define FUNC_CFG_REQ_DB_PAGE_SIZE_64KB 0x4UL 2247 #define FUNC_CFG_REQ_DB_PAGE_SIZE_128KB 0x5UL 2248 #define FUNC_CFG_REQ_DB_PAGE_SIZE_256KB 0x6UL 2249 #define FUNC_CFG_REQ_DB_PAGE_SIZE_512KB 0x7UL 2250 #define FUNC_CFG_REQ_DB_PAGE_SIZE_1MB 0x8UL 2251 #define FUNC_CFG_REQ_DB_PAGE_SIZE_2MB 0x9UL 2252 #define FUNC_CFG_REQ_DB_PAGE_SIZE_4MB 0xaUL 2253 #define FUNC_CFG_REQ_DB_PAGE_SIZE_LAST FUNC_CFG_REQ_DB_PAGE_SIZE_4MB 2254 u8 unused_1[2]; 2255 __le32 num_ktls_tx_key_ctxs; 2256 __le32 num_ktls_rx_key_ctxs; 2257 __le32 num_quic_tx_key_ctxs; 2258 __le32 num_quic_rx_key_ctxs; 2259 __le32 roce_max_av_per_vf; 2260 __le32 roce_max_cq_per_vf; 2261 __le32 roce_max_mrw_per_vf; 2262 __le32 roce_max_qp_per_vf; 2263 __le32 roce_max_srq_per_vf; 2264 __le32 roce_max_gid_per_vf; 2265 __le16 xid_partition_cfg; 2266 #define FUNC_CFG_REQ_XID_PARTITION_CFG_TX_CK 0x1UL 2267 #define FUNC_CFG_REQ_XID_PARTITION_CFG_RX_CK 0x2UL 2268 __le16 unused_2; 2269 }; 2270 2271 /* hwrm_func_cfg_output (size:128b/16B) */ 2272 struct hwrm_func_cfg_output { 2273 __le16 error_code; 2274 __le16 req_type; 2275 __le16 seq_id; 2276 __le16 resp_len; 2277 u8 unused_0[7]; 2278 u8 valid; 2279 }; 2280 2281 /* hwrm_func_cfg_cmd_err (size:64b/8B) */ 2282 struct hwrm_func_cfg_cmd_err { 2283 u8 code; 2284 #define FUNC_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 2285 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_RANGE 0x1UL 2286 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_MORE_THAN_MAX 0x2UL 2287 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_UNSUPPORTED 0x3UL 2288 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT 0x4UL 2289 #define FUNC_CFG_CMD_ERR_CODE_LAST FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT 2290 u8 unused_0[7]; 2291 }; 2292 2293 /* hwrm_func_qstats_input (size:192b/24B) */ 2294 struct hwrm_func_qstats_input { 2295 __le16 req_type; 2296 __le16 cmpl_ring; 2297 __le16 seq_id; 2298 __le16 target_id; 2299 __le64 resp_addr; 2300 __le16 fid; 2301 u8 flags; 2302 #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL 2303 #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL 2304 #define FUNC_QSTATS_REQ_FLAGS_L2_ONLY 0x4UL 2305 u8 unused_0[5]; 2306 }; 2307 2308 /* hwrm_func_qstats_output (size:1408b/176B) */ 2309 struct hwrm_func_qstats_output { 2310 __le16 error_code; 2311 __le16 req_type; 2312 __le16 seq_id; 2313 __le16 resp_len; 2314 __le64 tx_ucast_pkts; 2315 __le64 tx_mcast_pkts; 2316 __le64 tx_bcast_pkts; 2317 __le64 tx_discard_pkts; 2318 __le64 tx_drop_pkts; 2319 __le64 tx_ucast_bytes; 2320 __le64 tx_mcast_bytes; 2321 __le64 tx_bcast_bytes; 2322 __le64 rx_ucast_pkts; 2323 __le64 rx_mcast_pkts; 2324 __le64 rx_bcast_pkts; 2325 __le64 rx_discard_pkts; 2326 __le64 rx_drop_pkts; 2327 __le64 rx_ucast_bytes; 2328 __le64 rx_mcast_bytes; 2329 __le64 rx_bcast_bytes; 2330 __le64 rx_agg_pkts; 2331 __le64 rx_agg_bytes; 2332 __le64 rx_agg_events; 2333 __le64 rx_agg_aborts; 2334 u8 clear_seq; 2335 u8 unused_0[6]; 2336 u8 valid; 2337 }; 2338 2339 /* hwrm_func_qstats_ext_input (size:256b/32B) */ 2340 struct hwrm_func_qstats_ext_input { 2341 __le16 req_type; 2342 __le16 cmpl_ring; 2343 __le16 seq_id; 2344 __le16 target_id; 2345 __le64 resp_addr; 2346 __le16 fid; 2347 u8 flags; 2348 #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL 2349 #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL 2350 u8 unused_0[1]; 2351 __le32 enables; 2352 #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL 2353 __le16 schq_id; 2354 __le16 traffic_class; 2355 u8 unused_1[4]; 2356 }; 2357 2358 /* hwrm_func_qstats_ext_output (size:1536b/192B) */ 2359 struct hwrm_func_qstats_ext_output { 2360 __le16 error_code; 2361 __le16 req_type; 2362 __le16 seq_id; 2363 __le16 resp_len; 2364 __le64 rx_ucast_pkts; 2365 __le64 rx_mcast_pkts; 2366 __le64 rx_bcast_pkts; 2367 __le64 rx_discard_pkts; 2368 __le64 rx_error_pkts; 2369 __le64 rx_ucast_bytes; 2370 __le64 rx_mcast_bytes; 2371 __le64 rx_bcast_bytes; 2372 __le64 tx_ucast_pkts; 2373 __le64 tx_mcast_pkts; 2374 __le64 tx_bcast_pkts; 2375 __le64 tx_error_pkts; 2376 __le64 tx_discard_pkts; 2377 __le64 tx_ucast_bytes; 2378 __le64 tx_mcast_bytes; 2379 __le64 tx_bcast_bytes; 2380 __le64 rx_tpa_eligible_pkt; 2381 __le64 rx_tpa_eligible_bytes; 2382 __le64 rx_tpa_pkt; 2383 __le64 rx_tpa_bytes; 2384 __le64 rx_tpa_errors; 2385 __le64 rx_tpa_events; 2386 u8 unused_0[7]; 2387 u8 valid; 2388 }; 2389 2390 /* hwrm_func_clr_stats_input (size:192b/24B) */ 2391 struct hwrm_func_clr_stats_input { 2392 __le16 req_type; 2393 __le16 cmpl_ring; 2394 __le16 seq_id; 2395 __le16 target_id; 2396 __le64 resp_addr; 2397 __le16 fid; 2398 u8 unused_0[6]; 2399 }; 2400 2401 /* hwrm_func_clr_stats_output (size:128b/16B) */ 2402 struct hwrm_func_clr_stats_output { 2403 __le16 error_code; 2404 __le16 req_type; 2405 __le16 seq_id; 2406 __le16 resp_len; 2407 u8 unused_0[7]; 2408 u8 valid; 2409 }; 2410 2411 /* hwrm_func_vf_resc_free_input (size:192b/24B) */ 2412 struct hwrm_func_vf_resc_free_input { 2413 __le16 req_type; 2414 __le16 cmpl_ring; 2415 __le16 seq_id; 2416 __le16 target_id; 2417 __le64 resp_addr; 2418 __le16 vf_id; 2419 u8 unused_0[6]; 2420 }; 2421 2422 /* hwrm_func_vf_resc_free_output (size:128b/16B) */ 2423 struct hwrm_func_vf_resc_free_output { 2424 __le16 error_code; 2425 __le16 req_type; 2426 __le16 seq_id; 2427 __le16 resp_len; 2428 u8 unused_0[7]; 2429 u8 valid; 2430 }; 2431 2432 /* hwrm_func_drv_rgtr_input (size:896b/112B) */ 2433 struct hwrm_func_drv_rgtr_input { 2434 __le16 req_type; 2435 __le16 cmpl_ring; 2436 __le16 seq_id; 2437 __le16 target_id; 2438 __le64 resp_addr; 2439 __le32 flags; 2440 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 2441 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 2442 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 2443 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 2444 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 2445 #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL 2446 #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL 2447 #define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT 0x80UL 2448 #define FUNC_DRV_RGTR_REQ_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT 0x100UL 2449 #define FUNC_DRV_RGTR_REQ_FLAGS_NPAR_1_2_SUPPORT 0x200UL 2450 #define FUNC_DRV_RGTR_REQ_FLAGS_ASYM_QUEUE_CFG_SUPPORT 0x400UL 2451 #define FUNC_DRV_RGTR_REQ_FLAGS_TF_INGRESS_NIC_FLOW_MODE 0x800UL 2452 __le32 enables; 2453 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 2454 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 2455 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 2456 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 2457 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 2458 __le16 os_type; 2459 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 2460 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 2461 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 2462 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 2463 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 2464 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 2465 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 2466 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 2467 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 2468 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 2469 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 2470 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 2471 u8 ver_maj_8b; 2472 u8 ver_min_8b; 2473 u8 ver_upd_8b; 2474 u8 unused_0[3]; 2475 __le32 timestamp; 2476 u8 unused_1[4]; 2477 __le32 vf_req_fwd[8]; 2478 __le32 async_event_fwd[8]; 2479 __le16 ver_maj; 2480 __le16 ver_min; 2481 __le16 ver_upd; 2482 __le16 ver_patch; 2483 }; 2484 2485 /* hwrm_func_drv_rgtr_output (size:128b/16B) */ 2486 struct hwrm_func_drv_rgtr_output { 2487 __le16 error_code; 2488 __le16 req_type; 2489 __le16 seq_id; 2490 __le16 resp_len; 2491 __le32 flags; 2492 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 2493 u8 unused_0[3]; 2494 u8 valid; 2495 }; 2496 2497 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 2498 struct hwrm_func_drv_unrgtr_input { 2499 __le16 req_type; 2500 __le16 cmpl_ring; 2501 __le16 seq_id; 2502 __le16 target_id; 2503 __le64 resp_addr; 2504 __le32 flags; 2505 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 2506 u8 unused_0[4]; 2507 }; 2508 2509 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 2510 struct hwrm_func_drv_unrgtr_output { 2511 __le16 error_code; 2512 __le16 req_type; 2513 __le16 seq_id; 2514 __le16 resp_len; 2515 u8 unused_0[7]; 2516 u8 valid; 2517 }; 2518 2519 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 2520 struct hwrm_func_buf_rgtr_input { 2521 __le16 req_type; 2522 __le16 cmpl_ring; 2523 __le16 seq_id; 2524 __le16 target_id; 2525 __le64 resp_addr; 2526 __le32 enables; 2527 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 2528 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 2529 __le16 vf_id; 2530 __le16 req_buf_num_pages; 2531 __le16 req_buf_page_size; 2532 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 2533 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 2534 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 2535 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 2536 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 2537 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 2538 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 2539 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 2540 __le16 req_buf_len; 2541 __le16 resp_buf_len; 2542 u8 unused_0[2]; 2543 __le64 req_buf_page_addr0; 2544 __le64 req_buf_page_addr1; 2545 __le64 req_buf_page_addr2; 2546 __le64 req_buf_page_addr3; 2547 __le64 req_buf_page_addr4; 2548 __le64 req_buf_page_addr5; 2549 __le64 req_buf_page_addr6; 2550 __le64 req_buf_page_addr7; 2551 __le64 req_buf_page_addr8; 2552 __le64 req_buf_page_addr9; 2553 __le64 error_buf_addr; 2554 __le64 resp_buf_addr; 2555 }; 2556 2557 /* hwrm_func_buf_rgtr_output (size:128b/16B) */ 2558 struct hwrm_func_buf_rgtr_output { 2559 __le16 error_code; 2560 __le16 req_type; 2561 __le16 seq_id; 2562 __le16 resp_len; 2563 u8 unused_0[7]; 2564 u8 valid; 2565 }; 2566 2567 /* hwrm_func_drv_qver_input (size:192b/24B) */ 2568 struct hwrm_func_drv_qver_input { 2569 __le16 req_type; 2570 __le16 cmpl_ring; 2571 __le16 seq_id; 2572 __le16 target_id; 2573 __le64 resp_addr; 2574 __le32 reserved; 2575 __le16 fid; 2576 u8 driver_type; 2577 #define FUNC_DRV_QVER_REQ_DRIVER_TYPE_L2 0x0UL 2578 #define FUNC_DRV_QVER_REQ_DRIVER_TYPE_ROCE 0x1UL 2579 #define FUNC_DRV_QVER_REQ_DRIVER_TYPE_LAST FUNC_DRV_QVER_REQ_DRIVER_TYPE_ROCE 2580 u8 unused_0; 2581 }; 2582 2583 /* hwrm_func_drv_qver_output (size:256b/32B) */ 2584 struct hwrm_func_drv_qver_output { 2585 __le16 error_code; 2586 __le16 req_type; 2587 __le16 seq_id; 2588 __le16 resp_len; 2589 __le16 os_type; 2590 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 2591 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 2592 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 2593 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 2594 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 2595 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 2596 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 2597 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 2598 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 2599 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 2600 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 2601 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 2602 u8 ver_maj_8b; 2603 u8 ver_min_8b; 2604 u8 ver_upd_8b; 2605 u8 unused_0[3]; 2606 __le16 ver_maj; 2607 __le16 ver_min; 2608 __le16 ver_upd; 2609 __le16 ver_patch; 2610 u8 unused_1[7]; 2611 u8 valid; 2612 }; 2613 2614 /* hwrm_func_resource_qcaps_input (size:192b/24B) */ 2615 struct hwrm_func_resource_qcaps_input { 2616 __le16 req_type; 2617 __le16 cmpl_ring; 2618 __le16 seq_id; 2619 __le16 target_id; 2620 __le64 resp_addr; 2621 __le16 fid; 2622 u8 unused_0[6]; 2623 }; 2624 2625 /* hwrm_func_resource_qcaps_output (size:704b/88B) */ 2626 struct hwrm_func_resource_qcaps_output { 2627 __le16 error_code; 2628 __le16 req_type; 2629 __le16 seq_id; 2630 __le16 resp_len; 2631 __le16 max_vfs; 2632 __le16 max_msix; 2633 __le16 vf_reservation_strategy; 2634 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 2635 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 2636 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 2637 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 2638 __le16 min_rsscos_ctx; 2639 __le16 max_rsscos_ctx; 2640 __le16 min_cmpl_rings; 2641 __le16 max_cmpl_rings; 2642 __le16 min_tx_rings; 2643 __le16 max_tx_rings; 2644 __le16 min_rx_rings; 2645 __le16 max_rx_rings; 2646 __le16 min_l2_ctxs; 2647 __le16 max_l2_ctxs; 2648 __le16 min_vnics; 2649 __le16 max_vnics; 2650 __le16 min_stat_ctx; 2651 __le16 max_stat_ctx; 2652 __le16 min_hw_ring_grps; 2653 __le16 max_hw_ring_grps; 2654 __le16 max_tx_scheduler_inputs; 2655 __le16 flags; 2656 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 2657 __le16 min_msix; 2658 __le32 min_ktls_tx_key_ctxs; 2659 __le32 max_ktls_tx_key_ctxs; 2660 __le32 min_ktls_rx_key_ctxs; 2661 __le32 max_ktls_rx_key_ctxs; 2662 __le32 min_quic_tx_key_ctxs; 2663 __le32 max_quic_tx_key_ctxs; 2664 __le32 min_quic_rx_key_ctxs; 2665 __le32 max_quic_rx_key_ctxs; 2666 u8 unused_0[3]; 2667 u8 valid; 2668 }; 2669 2670 /* hwrm_func_vf_resource_cfg_input (size:704b/88B) */ 2671 struct hwrm_func_vf_resource_cfg_input { 2672 __le16 req_type; 2673 __le16 cmpl_ring; 2674 __le16 seq_id; 2675 __le16 target_id; 2676 __le64 resp_addr; 2677 __le16 vf_id; 2678 __le16 max_msix; 2679 __le16 min_rsscos_ctx; 2680 __le16 max_rsscos_ctx; 2681 __le16 min_cmpl_rings; 2682 __le16 max_cmpl_rings; 2683 __le16 min_tx_rings; 2684 __le16 max_tx_rings; 2685 __le16 min_rx_rings; 2686 __le16 max_rx_rings; 2687 __le16 min_l2_ctxs; 2688 __le16 max_l2_ctxs; 2689 __le16 min_vnics; 2690 __le16 max_vnics; 2691 __le16 min_stat_ctx; 2692 __le16 max_stat_ctx; 2693 __le16 min_hw_ring_grps; 2694 __le16 max_hw_ring_grps; 2695 __le16 flags; 2696 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 2697 __le16 min_msix; 2698 __le32 min_ktls_tx_key_ctxs; 2699 __le32 max_ktls_tx_key_ctxs; 2700 __le32 min_ktls_rx_key_ctxs; 2701 __le32 max_ktls_rx_key_ctxs; 2702 __le32 min_quic_tx_key_ctxs; 2703 __le32 max_quic_tx_key_ctxs; 2704 __le32 min_quic_rx_key_ctxs; 2705 __le32 max_quic_rx_key_ctxs; 2706 }; 2707 2708 /* hwrm_func_vf_resource_cfg_output (size:384b/48B) */ 2709 struct hwrm_func_vf_resource_cfg_output { 2710 __le16 error_code; 2711 __le16 req_type; 2712 __le16 seq_id; 2713 __le16 resp_len; 2714 __le16 reserved_rsscos_ctx; 2715 __le16 reserved_cmpl_rings; 2716 __le16 reserved_tx_rings; 2717 __le16 reserved_rx_rings; 2718 __le16 reserved_l2_ctxs; 2719 __le16 reserved_vnics; 2720 __le16 reserved_stat_ctx; 2721 __le16 reserved_hw_ring_grps; 2722 __le32 reserved_ktls_tx_key_ctxs; 2723 __le32 reserved_ktls_rx_key_ctxs; 2724 __le32 reserved_quic_tx_key_ctxs; 2725 __le32 reserved_quic_rx_key_ctxs; 2726 u8 unused_0[7]; 2727 u8 valid; 2728 }; 2729 2730 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 2731 struct hwrm_func_backing_store_qcaps_input { 2732 __le16 req_type; 2733 __le16 cmpl_ring; 2734 __le16 seq_id; 2735 __le16 target_id; 2736 __le64 resp_addr; 2737 }; 2738 2739 /* hwrm_func_backing_store_qcaps_output (size:832b/104B) */ 2740 struct hwrm_func_backing_store_qcaps_output { 2741 __le16 error_code; 2742 __le16 req_type; 2743 __le16 seq_id; 2744 __le16 resp_len; 2745 __le32 qp_max_entries; 2746 __le16 qp_min_qp1_entries; 2747 __le16 qp_max_l2_entries; 2748 __le16 qp_entry_size; 2749 __le16 srq_max_l2_entries; 2750 __le32 srq_max_entries; 2751 __le16 srq_entry_size; 2752 __le16 cq_max_l2_entries; 2753 __le32 cq_max_entries; 2754 __le16 cq_entry_size; 2755 __le16 vnic_max_vnic_entries; 2756 __le16 vnic_max_ring_table_entries; 2757 __le16 vnic_entry_size; 2758 __le32 stat_max_entries; 2759 __le16 stat_entry_size; 2760 __le16 tqm_entry_size; 2761 __le32 tqm_min_entries_per_ring; 2762 __le32 tqm_max_entries_per_ring; 2763 __le32 mrav_max_entries; 2764 __le16 mrav_entry_size; 2765 __le16 tim_entry_size; 2766 __le32 tim_max_entries; 2767 __le16 mrav_num_entries_units; 2768 u8 tqm_entries_multiple; 2769 u8 ctx_kind_initializer; 2770 __le16 ctx_init_mask; 2771 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_QP 0x1UL 2772 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_SRQ 0x2UL 2773 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_CQ 0x4UL 2774 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_VNIC 0x8UL 2775 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_STAT 0x10UL 2776 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_MRAV 0x20UL 2777 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_TKC 0x40UL 2778 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_RKC 0x80UL 2779 u8 qp_init_offset; 2780 u8 srq_init_offset; 2781 u8 cq_init_offset; 2782 u8 vnic_init_offset; 2783 u8 tqm_fp_rings_count; 2784 u8 stat_init_offset; 2785 u8 mrav_init_offset; 2786 u8 tqm_fp_rings_count_ext; 2787 u8 tkc_init_offset; 2788 u8 rkc_init_offset; 2789 __le16 tkc_entry_size; 2790 __le16 rkc_entry_size; 2791 __le32 tkc_max_entries; 2792 __le32 rkc_max_entries; 2793 __le16 fast_qpmd_qp_num_entries; 2794 u8 rsvd1[5]; 2795 u8 valid; 2796 }; 2797 2798 /* tqm_fp_ring_cfg (size:128b/16B) */ 2799 struct tqm_fp_ring_cfg { 2800 u8 tqm_ring_pg_size_tqm_ring_lvl; 2801 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK 0xfUL 2802 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0 2803 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 0x0UL 2804 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 0x1UL 2805 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 0x2UL 2806 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 2807 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK 0xf0UL 2808 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4 2809 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2810 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2811 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2812 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2813 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2814 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2815 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G 2816 u8 unused[3]; 2817 __le32 tqm_ring_num_entries; 2818 __le64 tqm_ring_page_dir; 2819 }; 2820 2821 /* hwrm_func_backing_store_cfg_input (size:2688b/336B) */ 2822 struct hwrm_func_backing_store_cfg_input { 2823 __le16 req_type; 2824 __le16 cmpl_ring; 2825 __le16 seq_id; 2826 __le16 target_id; 2827 __le64 resp_addr; 2828 __le32 flags; 2829 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 2830 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL 2831 __le32 enables; 2832 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 2833 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 2834 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 2835 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 2836 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 2837 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 2838 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 2839 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 2840 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 2841 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 2842 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 2843 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 2844 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 2845 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 2846 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 2847 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 2848 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING8 0x10000UL 2849 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING9 0x20000UL 2850 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING10 0x40000UL 2851 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TKC 0x80000UL 2852 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_RKC 0x100000UL 2853 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP_FAST_QPMD 0x200000UL 2854 u8 qpc_pg_size_qpc_lvl; 2855 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 2856 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 2857 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 2858 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 2859 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 2860 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 2861 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 2862 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 2863 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 2864 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 2865 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 2866 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 2867 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 2868 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 2869 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 2870 u8 srq_pg_size_srq_lvl; 2871 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 2872 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 2873 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 2874 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 2875 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 2876 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 2877 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 2878 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 2879 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 2880 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 2881 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 2882 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 2883 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 2884 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 2885 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 2886 u8 cq_pg_size_cq_lvl; 2887 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 2888 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 2889 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 2890 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 2891 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 2892 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 2893 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 2894 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 2895 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 2896 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 2897 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 2898 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 2899 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 2900 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 2901 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 2902 u8 vnic_pg_size_vnic_lvl; 2903 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 2904 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 2905 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 2906 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 2907 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 2908 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 2909 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 2910 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 2911 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 2912 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 2913 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 2914 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 2915 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 2916 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 2917 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 2918 u8 stat_pg_size_stat_lvl; 2919 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 2920 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 2921 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 2922 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 2923 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 2924 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 2925 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 2926 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 2927 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 2928 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 2929 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 2930 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 2931 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 2932 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 2933 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 2934 u8 tqm_sp_pg_size_tqm_sp_lvl; 2935 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 2936 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 2937 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 2938 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 2939 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 2940 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 2941 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 2942 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 2943 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 2944 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 2945 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 2946 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 2947 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 2948 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 2949 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 2950 u8 tqm_ring0_pg_size_tqm_ring0_lvl; 2951 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 2952 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 2953 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 2954 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 2955 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 2956 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 2957 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 2958 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 2959 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 2960 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 2961 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 2962 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 2963 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 2964 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 2965 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 2966 u8 tqm_ring1_pg_size_tqm_ring1_lvl; 2967 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 2968 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 2969 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 2970 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 2971 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 2972 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 2973 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 2974 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 2975 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 2976 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 2977 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 2978 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 2979 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 2980 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 2981 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 2982 u8 tqm_ring2_pg_size_tqm_ring2_lvl; 2983 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 2984 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 2985 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 2986 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 2987 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 2988 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 2989 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 2990 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 2991 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 2992 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 2993 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 2994 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 2995 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 2996 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 2997 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 2998 u8 tqm_ring3_pg_size_tqm_ring3_lvl; 2999 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 3000 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 3001 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 3002 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 3003 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 3004 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 3005 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 3006 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 3007 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 3008 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 3009 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 3010 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 3011 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 3012 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 3013 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 3014 u8 tqm_ring4_pg_size_tqm_ring4_lvl; 3015 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 3016 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 3017 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 3018 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 3019 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 3020 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 3021 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 3022 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 3023 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 3024 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 3025 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 3026 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 3027 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 3028 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 3029 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 3030 u8 tqm_ring5_pg_size_tqm_ring5_lvl; 3031 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 3032 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 3033 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 3034 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 3035 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 3036 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 3037 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 3038 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 3039 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 3040 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 3041 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 3042 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 3043 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 3044 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 3045 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 3046 u8 tqm_ring6_pg_size_tqm_ring6_lvl; 3047 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 3048 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 3049 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 3050 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 3051 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 3052 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 3053 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 3054 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 3055 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 3056 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 3057 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 3058 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 3059 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 3060 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 3061 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 3062 u8 tqm_ring7_pg_size_tqm_ring7_lvl; 3063 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 3064 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 3065 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 3066 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 3067 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 3068 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 3069 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 3070 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 3071 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 3072 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 3073 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 3074 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 3075 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 3076 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 3077 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 3078 u8 mrav_pg_size_mrav_lvl; 3079 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 3080 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 3081 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 3082 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL 3083 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 3084 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 3085 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 3086 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 3087 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 3088 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 3089 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 3090 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 3091 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 3092 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 3093 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 3094 u8 tim_pg_size_tim_lvl; 3095 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 3096 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 3097 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 3098 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 3099 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 3100 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 3101 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 3102 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 3103 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 3104 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 3105 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 3106 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 3107 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 3108 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 3109 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 3110 __le64 qpc_page_dir; 3111 __le64 srq_page_dir; 3112 __le64 cq_page_dir; 3113 __le64 vnic_page_dir; 3114 __le64 stat_page_dir; 3115 __le64 tqm_sp_page_dir; 3116 __le64 tqm_ring0_page_dir; 3117 __le64 tqm_ring1_page_dir; 3118 __le64 tqm_ring2_page_dir; 3119 __le64 tqm_ring3_page_dir; 3120 __le64 tqm_ring4_page_dir; 3121 __le64 tqm_ring5_page_dir; 3122 __le64 tqm_ring6_page_dir; 3123 __le64 tqm_ring7_page_dir; 3124 __le64 mrav_page_dir; 3125 __le64 tim_page_dir; 3126 __le32 qp_num_entries; 3127 __le32 srq_num_entries; 3128 __le32 cq_num_entries; 3129 __le32 stat_num_entries; 3130 __le32 tqm_sp_num_entries; 3131 __le32 tqm_ring0_num_entries; 3132 __le32 tqm_ring1_num_entries; 3133 __le32 tqm_ring2_num_entries; 3134 __le32 tqm_ring3_num_entries; 3135 __le32 tqm_ring4_num_entries; 3136 __le32 tqm_ring5_num_entries; 3137 __le32 tqm_ring6_num_entries; 3138 __le32 tqm_ring7_num_entries; 3139 __le32 mrav_num_entries; 3140 __le32 tim_num_entries; 3141 __le16 qp_num_qp1_entries; 3142 __le16 qp_num_l2_entries; 3143 __le16 qp_entry_size; 3144 __le16 srq_num_l2_entries; 3145 __le16 srq_entry_size; 3146 __le16 cq_num_l2_entries; 3147 __le16 cq_entry_size; 3148 __le16 vnic_num_vnic_entries; 3149 __le16 vnic_num_ring_table_entries; 3150 __le16 vnic_entry_size; 3151 __le16 stat_entry_size; 3152 __le16 tqm_entry_size; 3153 __le16 mrav_entry_size; 3154 __le16 tim_entry_size; 3155 u8 tqm_ring8_pg_size_tqm_ring_lvl; 3156 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_MASK 0xfUL 3157 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_SFT 0 3158 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_0 0x0UL 3159 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_1 0x1UL 3160 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 0x2UL 3161 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 3162 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_MASK 0xf0UL 3163 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_SFT 4 3164 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 3165 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 3166 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 3167 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 3168 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 3169 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 3170 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G 3171 u8 ring8_unused[3]; 3172 __le32 tqm_ring8_num_entries; 3173 __le64 tqm_ring8_page_dir; 3174 u8 tqm_ring9_pg_size_tqm_ring_lvl; 3175 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_MASK 0xfUL 3176 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_SFT 0 3177 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_0 0x0UL 3178 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_1 0x1UL 3179 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 0x2UL 3180 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 3181 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_MASK 0xf0UL 3182 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_SFT 4 3183 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 3184 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 3185 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 3186 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 3187 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 3188 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 3189 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G 3190 u8 ring9_unused[3]; 3191 __le32 tqm_ring9_num_entries; 3192 __le64 tqm_ring9_page_dir; 3193 u8 tqm_ring10_pg_size_tqm_ring_lvl; 3194 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_MASK 0xfUL 3195 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_SFT 0 3196 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_0 0x0UL 3197 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_1 0x1UL 3198 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 0x2UL 3199 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 3200 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_MASK 0xf0UL 3201 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_SFT 4 3202 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 3203 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 3204 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 3205 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 3206 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 3207 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 3208 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G 3209 u8 ring10_unused[3]; 3210 __le32 tqm_ring10_num_entries; 3211 __le64 tqm_ring10_page_dir; 3212 __le32 tkc_num_entries; 3213 __le32 rkc_num_entries; 3214 __le64 tkc_page_dir; 3215 __le64 rkc_page_dir; 3216 __le16 tkc_entry_size; 3217 __le16 rkc_entry_size; 3218 u8 tkc_pg_size_tkc_lvl; 3219 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_MASK 0xfUL 3220 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_SFT 0 3221 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_0 0x0UL 3222 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_1 0x1UL 3223 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 0x2UL 3224 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 3225 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_MASK 0xf0UL 3226 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_SFT 4 3227 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_4K (0x0UL << 4) 3228 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8K (0x1UL << 4) 3229 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_64K (0x2UL << 4) 3230 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_2M (0x3UL << 4) 3231 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8M (0x4UL << 4) 3232 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G (0x5UL << 4) 3233 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G 3234 u8 rkc_pg_size_rkc_lvl; 3235 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_MASK 0xfUL 3236 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_SFT 0 3237 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_0 0x0UL 3238 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_1 0x1UL 3239 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 0x2UL 3240 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 3241 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_MASK 0xf0UL 3242 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_SFT 4 3243 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_4K (0x0UL << 4) 3244 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8K (0x1UL << 4) 3245 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_64K (0x2UL << 4) 3246 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_2M (0x3UL << 4) 3247 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8M (0x4UL << 4) 3248 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G (0x5UL << 4) 3249 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G 3250 __le16 qp_num_fast_qpmd_entries; 3251 }; 3252 3253 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 3254 struct hwrm_func_backing_store_cfg_output { 3255 __le16 error_code; 3256 __le16 req_type; 3257 __le16 seq_id; 3258 __le16 resp_len; 3259 u8 unused_0[7]; 3260 u8 valid; 3261 }; 3262 3263 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */ 3264 struct hwrm_error_recovery_qcfg_input { 3265 __le16 req_type; 3266 __le16 cmpl_ring; 3267 __le16 seq_id; 3268 __le16 target_id; 3269 __le64 resp_addr; 3270 u8 unused_0[8]; 3271 }; 3272 3273 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ 3274 struct hwrm_error_recovery_qcfg_output { 3275 __le16 error_code; 3276 __le16 req_type; 3277 __le16 seq_id; 3278 __le16 resp_len; 3279 __le32 flags; 3280 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL 3281 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL 3282 __le32 driver_polling_freq; 3283 __le32 master_func_wait_period; 3284 __le32 normal_func_wait_period; 3285 __le32 master_func_wait_period_after_reset; 3286 __le32 max_bailout_time_after_reset; 3287 __le32 fw_health_status_reg; 3288 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL 3289 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0 3290 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3291 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL 3292 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL 3293 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL 3294 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 3295 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL 3296 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2 3297 __le32 fw_heartbeat_reg; 3298 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL 3299 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0 3300 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3301 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL 3302 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL 3303 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL 3304 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 3305 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL 3306 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2 3307 __le32 fw_reset_cnt_reg; 3308 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL 3309 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0 3310 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3311 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL 3312 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL 3313 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL 3314 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 3315 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL 3316 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2 3317 __le32 reset_inprogress_reg; 3318 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL 3319 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0 3320 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3321 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL 3322 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL 3323 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL 3324 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 3325 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL 3326 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2 3327 __le32 reset_inprogress_reg_mask; 3328 u8 unused_0[3]; 3329 u8 reg_array_cnt; 3330 __le32 reset_reg[16]; 3331 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL 3332 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0 3333 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3334 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL 3335 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL 3336 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL 3337 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 3338 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL 3339 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2 3340 __le32 reset_reg_val[16]; 3341 u8 delay_after_reset[16]; 3342 __le32 err_recovery_cnt_reg; 3343 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL 3344 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0 3345 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3346 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL 3347 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL 3348 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL 3349 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 3350 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL 3351 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2 3352 u8 unused_1[3]; 3353 u8 valid; 3354 }; 3355 3356 /* hwrm_func_echo_response_input (size:192b/24B) */ 3357 struct hwrm_func_echo_response_input { 3358 __le16 req_type; 3359 __le16 cmpl_ring; 3360 __le16 seq_id; 3361 __le16 target_id; 3362 __le64 resp_addr; 3363 __le32 event_data1; 3364 __le32 event_data2; 3365 }; 3366 3367 /* hwrm_func_echo_response_output (size:128b/16B) */ 3368 struct hwrm_func_echo_response_output { 3369 __le16 error_code; 3370 __le16 req_type; 3371 __le16 seq_id; 3372 __le16 resp_len; 3373 u8 unused_0[7]; 3374 u8 valid; 3375 }; 3376 3377 /* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */ 3378 struct hwrm_func_ptp_pin_qcfg_input { 3379 __le16 req_type; 3380 __le16 cmpl_ring; 3381 __le16 seq_id; 3382 __le16 target_id; 3383 __le64 resp_addr; 3384 u8 unused_0[8]; 3385 }; 3386 3387 /* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */ 3388 struct hwrm_func_ptp_pin_qcfg_output { 3389 __le16 error_code; 3390 __le16 req_type; 3391 __le16 seq_id; 3392 __le16 resp_len; 3393 u8 num_pins; 3394 u8 state; 3395 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN0_ENABLED 0x1UL 3396 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN1_ENABLED 0x2UL 3397 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN2_ENABLED 0x4UL 3398 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN3_ENABLED 0x8UL 3399 u8 pin0_usage; 3400 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_NONE 0x0UL 3401 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_IN 0x1UL 3402 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_OUT 0x2UL 3403 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_IN 0x3UL 3404 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 0x4UL 3405 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 3406 u8 pin1_usage; 3407 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_NONE 0x0UL 3408 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_IN 0x1UL 3409 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_OUT 0x2UL 3410 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_IN 0x3UL 3411 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 0x4UL 3412 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 3413 u8 pin2_usage; 3414 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_NONE 0x0UL 3415 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_IN 0x1UL 3416 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_OUT 0x2UL 3417 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_IN 0x3UL 3418 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 0x4UL 3419 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3420 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3421 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3422 u8 pin3_usage; 3423 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_NONE 0x0UL 3424 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_IN 0x1UL 3425 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_OUT 0x2UL 3426 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_IN 0x3UL 3427 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 0x4UL 3428 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3429 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3430 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3431 u8 unused_0; 3432 u8 valid; 3433 }; 3434 3435 /* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */ 3436 struct hwrm_func_ptp_pin_cfg_input { 3437 __le16 req_type; 3438 __le16 cmpl_ring; 3439 __le16 seq_id; 3440 __le16 target_id; 3441 __le64 resp_addr; 3442 __le32 enables; 3443 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE 0x1UL 3444 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE 0x2UL 3445 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_STATE 0x4UL 3446 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_USAGE 0x8UL 3447 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_STATE 0x10UL 3448 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_USAGE 0x20UL 3449 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_STATE 0x40UL 3450 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_USAGE 0x80UL 3451 u8 pin0_state; 3452 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_DISABLED 0x0UL 3453 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 0x1UL 3454 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 3455 u8 pin0_usage; 3456 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_NONE 0x0UL 3457 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_IN 0x1UL 3458 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_OUT 0x2UL 3459 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_IN 0x3UL 3460 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 0x4UL 3461 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 3462 u8 pin1_state; 3463 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_DISABLED 0x0UL 3464 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 0x1UL 3465 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 3466 u8 pin1_usage; 3467 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_NONE 0x0UL 3468 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_IN 0x1UL 3469 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_OUT 0x2UL 3470 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_IN 0x3UL 3471 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 0x4UL 3472 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 3473 u8 pin2_state; 3474 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_DISABLED 0x0UL 3475 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 0x1UL 3476 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 3477 u8 pin2_usage; 3478 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_NONE 0x0UL 3479 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_IN 0x1UL 3480 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_OUT 0x2UL 3481 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_IN 0x3UL 3482 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 0x4UL 3483 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3484 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3485 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3486 u8 pin3_state; 3487 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_DISABLED 0x0UL 3488 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 0x1UL 3489 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 3490 u8 pin3_usage; 3491 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_NONE 0x0UL 3492 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_IN 0x1UL 3493 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_OUT 0x2UL 3494 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_IN 0x3UL 3495 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 0x4UL 3496 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3497 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3498 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3499 u8 unused_0[4]; 3500 }; 3501 3502 /* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */ 3503 struct hwrm_func_ptp_pin_cfg_output { 3504 __le16 error_code; 3505 __le16 req_type; 3506 __le16 seq_id; 3507 __le16 resp_len; 3508 u8 unused_0[7]; 3509 u8 valid; 3510 }; 3511 3512 /* hwrm_func_ptp_cfg_input (size:384b/48B) */ 3513 struct hwrm_func_ptp_cfg_input { 3514 __le16 req_type; 3515 __le16 cmpl_ring; 3516 __le16 seq_id; 3517 __le16 target_id; 3518 __le64 resp_addr; 3519 __le16 enables; 3520 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT 0x1UL 3521 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE 0x2UL 3522 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_PHASE 0x4UL 3523 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD 0x8UL 3524 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP 0x10UL 3525 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE 0x20UL 3526 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME 0x40UL 3527 u8 ptp_pps_event; 3528 #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_INTERNAL 0x1UL 3529 #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_EXTERNAL 0x2UL 3530 u8 ptp_freq_adj_dll_source; 3531 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_NONE 0x0UL 3532 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 0x1UL 3533 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 0x2UL 3534 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 0x3UL 3535 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 0x4UL 3536 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 0x5UL 3537 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 0x6UL 3538 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 0x7UL 3539 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 0x8UL 3540 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 0xffUL 3541 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 3542 u8 ptp_freq_adj_dll_phase; 3543 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_NONE 0x0UL 3544 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_4K 0x1UL 3545 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_8K 0x2UL 3546 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M 0x3UL 3547 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_25M 0x4UL 3548 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_25M 3549 u8 unused_0[3]; 3550 __le32 ptp_freq_adj_ext_period; 3551 __le32 ptp_freq_adj_ext_up; 3552 __le32 ptp_freq_adj_ext_phase_lower; 3553 __le32 ptp_freq_adj_ext_phase_upper; 3554 __le64 ptp_set_time; 3555 }; 3556 3557 /* hwrm_func_ptp_cfg_output (size:128b/16B) */ 3558 struct hwrm_func_ptp_cfg_output { 3559 __le16 error_code; 3560 __le16 req_type; 3561 __le16 seq_id; 3562 __le16 resp_len; 3563 u8 unused_0[7]; 3564 u8 valid; 3565 }; 3566 3567 /* hwrm_func_ptp_ts_query_input (size:192b/24B) */ 3568 struct hwrm_func_ptp_ts_query_input { 3569 __le16 req_type; 3570 __le16 cmpl_ring; 3571 __le16 seq_id; 3572 __le16 target_id; 3573 __le64 resp_addr; 3574 __le32 flags; 3575 #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PPS_TIME 0x1UL 3576 #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PTM_TIME 0x2UL 3577 u8 unused_0[4]; 3578 }; 3579 3580 /* hwrm_func_ptp_ts_query_output (size:320b/40B) */ 3581 struct hwrm_func_ptp_ts_query_output { 3582 __le16 error_code; 3583 __le16 req_type; 3584 __le16 seq_id; 3585 __le16 resp_len; 3586 __le64 pps_event_ts; 3587 __le64 ptm_local_ts; 3588 __le64 ptm_system_ts; 3589 __le32 ptm_link_delay; 3590 u8 unused_0[3]; 3591 u8 valid; 3592 }; 3593 3594 /* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */ 3595 struct hwrm_func_ptp_ext_cfg_input { 3596 __le16 req_type; 3597 __le16 cmpl_ring; 3598 __le16 seq_id; 3599 __le16 target_id; 3600 __le64 resp_addr; 3601 __le16 enables; 3602 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_MASTER_FID 0x1UL 3603 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_FID 0x2UL 3604 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_MODE 0x4UL 3605 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_FAILOVER_TIMER 0x8UL 3606 __le16 phc_master_fid; 3607 __le16 phc_sec_fid; 3608 u8 phc_sec_mode; 3609 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_SWITCH 0x0UL 3610 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_ALL 0x1UL 3611 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY 0x2UL 3612 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_LAST FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY 3613 u8 unused_0; 3614 __le32 failover_timer; 3615 u8 unused_1[4]; 3616 }; 3617 3618 /* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */ 3619 struct hwrm_func_ptp_ext_cfg_output { 3620 __le16 error_code; 3621 __le16 req_type; 3622 __le16 seq_id; 3623 __le16 resp_len; 3624 u8 unused_0[7]; 3625 u8 valid; 3626 }; 3627 3628 /* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */ 3629 struct hwrm_func_ptp_ext_qcfg_input { 3630 __le16 req_type; 3631 __le16 cmpl_ring; 3632 __le16 seq_id; 3633 __le16 target_id; 3634 __le64 resp_addr; 3635 u8 unused_0[8]; 3636 }; 3637 3638 /* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */ 3639 struct hwrm_func_ptp_ext_qcfg_output { 3640 __le16 error_code; 3641 __le16 req_type; 3642 __le16 seq_id; 3643 __le16 resp_len; 3644 __le16 phc_master_fid; 3645 __le16 phc_sec_fid; 3646 __le16 phc_active_fid0; 3647 __le16 phc_active_fid1; 3648 __le32 last_failover_event; 3649 __le16 from_fid; 3650 __le16 to_fid; 3651 u8 unused_0[7]; 3652 u8 valid; 3653 }; 3654 3655 /* hwrm_func_backing_store_cfg_v2_input (size:448b/56B) */ 3656 struct hwrm_func_backing_store_cfg_v2_input { 3657 __le16 req_type; 3658 __le16 cmpl_ring; 3659 __le16 seq_id; 3660 __le16 target_id; 3661 __le64 resp_addr; 3662 __le16 type; 3663 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QP 0x0UL 3664 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ 0x1UL 3665 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ 0x2UL 3666 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_VNIC 0x3UL 3667 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_STAT 0x4UL 3668 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3669 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3670 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MRAV 0xeUL 3671 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TIM 0xfUL 3672 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3673 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3674 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3675 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3676 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3677 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 3678 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_XID_PARTITION 0x1dUL 3679 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRT_TRACE 0x1eUL 3680 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRT2_TRACE 0x1fUL 3681 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CRT_TRACE 0x20UL 3682 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CRT2_TRACE 0x21UL 3683 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RIGP0_TRACE 0x22UL 3684 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL 3685 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL 3686 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 0xffffUL 3687 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 3688 __le16 instance; 3689 __le32 flags; 3690 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_PREBOOT_MODE 0x1UL 3691 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_CFG_ALL_DONE 0x2UL 3692 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_EXTEND 0x4UL 3693 __le64 page_dir; 3694 __le32 num_entries; 3695 __le16 entry_size; 3696 u8 page_size_pbl_level; 3697 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_MASK 0xfUL 3698 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_SFT 0 3699 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_0 0x0UL 3700 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_1 0x1UL 3701 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2 0x2UL 3702 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2 3703 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_MASK 0xf0UL 3704 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_SFT 4 3705 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_4K (0x0UL << 4) 3706 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8K (0x1UL << 4) 3707 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_64K (0x2UL << 4) 3708 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_2M (0x3UL << 4) 3709 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8M (0x4UL << 4) 3710 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G (0x5UL << 4) 3711 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G 3712 u8 subtype_valid_cnt; 3713 __le32 split_entry_0; 3714 __le32 split_entry_1; 3715 __le32 split_entry_2; 3716 __le32 split_entry_3; 3717 }; 3718 3719 /* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */ 3720 struct hwrm_func_backing_store_cfg_v2_output { 3721 __le16 error_code; 3722 __le16 req_type; 3723 __le16 seq_id; 3724 __le16 resp_len; 3725 u8 rsvd0[7]; 3726 u8 valid; 3727 }; 3728 3729 /* hwrm_func_backing_store_qcfg_v2_input (size:192b/24B) */ 3730 struct hwrm_func_backing_store_qcfg_v2_input { 3731 __le16 req_type; 3732 __le16 cmpl_ring; 3733 __le16 seq_id; 3734 __le16 target_id; 3735 __le64 resp_addr; 3736 __le16 type; 3737 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QP 0x0UL 3738 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ 0x1UL 3739 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ 0x2UL 3740 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_VNIC 0x3UL 3741 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_STAT 0x4UL 3742 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3743 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3744 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MRAV 0xeUL 3745 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TIM 0xfUL 3746 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TX_CK 0x13UL 3747 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RX_CK 0x14UL 3748 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3749 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3750 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3751 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3752 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3753 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 3754 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_XID_PARTITION_TABLE 0x1dUL 3755 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRT_TRACE 0x1eUL 3756 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRT2_TRACE 0x1fUL 3757 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CRT_TRACE 0x20UL 3758 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CRT2_TRACE 0x21UL 3759 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RIGP0_TRACE 0x22UL 3760 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL 3761 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL 3762 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 0xffffUL 3763 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 3764 __le16 instance; 3765 u8 rsvd[4]; 3766 }; 3767 3768 /* hwrm_func_backing_store_qcfg_v2_output (size:448b/56B) */ 3769 struct hwrm_func_backing_store_qcfg_v2_output { 3770 __le16 error_code; 3771 __le16 req_type; 3772 __le16 seq_id; 3773 __le16 resp_len; 3774 __le16 type; 3775 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QP 0x0UL 3776 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRQ 0x1UL 3777 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CQ 0x2UL 3778 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_VNIC 0x3UL 3779 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_STAT 0x4UL 3780 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SP_TQM_RING 0x5UL 3781 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_FP_TQM_RING 0x6UL 3782 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MRAV 0xeUL 3783 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TIM 0xfUL 3784 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MP_TQM_RING 0x15UL 3785 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TBL_SCOPE 0x1cUL 3786 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_XID_PARTITION 0x1dUL 3787 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRT_TRACE 0x1eUL 3788 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRT2_TRACE 0x1fUL 3789 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CRT_TRACE 0x20UL 3790 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CRT2_TRACE 0x21UL 3791 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RIGP0_TRACE 0x22UL 3792 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_L2_HWRM_TRACE 0x23UL 3793 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_ROCE_HWRM_TRACE 0x24UL 3794 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 0xffffUL 3795 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 3796 __le16 instance; 3797 __le32 flags; 3798 __le64 page_dir; 3799 __le32 num_entries; 3800 u8 page_size_pbl_level; 3801 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_MASK 0xfUL 3802 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_SFT 0 3803 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_0 0x0UL 3804 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_1 0x1UL 3805 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2 0x2UL 3806 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2 3807 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_MASK 0xf0UL 3808 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_SFT 4 3809 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_4K (0x0UL << 4) 3810 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8K (0x1UL << 4) 3811 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_64K (0x2UL << 4) 3812 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_2M (0x3UL << 4) 3813 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8M (0x4UL << 4) 3814 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G (0x5UL << 4) 3815 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G 3816 u8 subtype_valid_cnt; 3817 u8 rsvd[2]; 3818 __le32 split_entry_0; 3819 __le32 split_entry_1; 3820 __le32 split_entry_2; 3821 __le32 split_entry_3; 3822 u8 rsvd2[7]; 3823 u8 valid; 3824 }; 3825 3826 /* qpc_split_entries (size:128b/16B) */ 3827 struct qpc_split_entries { 3828 __le32 qp_num_l2_entries; 3829 __le32 qp_num_qp1_entries; 3830 __le32 qp_num_fast_qpmd_entries; 3831 __le32 rsvd; 3832 }; 3833 3834 /* srq_split_entries (size:128b/16B) */ 3835 struct srq_split_entries { 3836 __le32 srq_num_l2_entries; 3837 __le32 rsvd; 3838 __le32 rsvd2[2]; 3839 }; 3840 3841 /* cq_split_entries (size:128b/16B) */ 3842 struct cq_split_entries { 3843 __le32 cq_num_l2_entries; 3844 __le32 rsvd; 3845 __le32 rsvd2[2]; 3846 }; 3847 3848 /* vnic_split_entries (size:128b/16B) */ 3849 struct vnic_split_entries { 3850 __le32 vnic_num_vnic_entries; 3851 __le32 rsvd; 3852 __le32 rsvd2[2]; 3853 }; 3854 3855 /* mrav_split_entries (size:128b/16B) */ 3856 struct mrav_split_entries { 3857 __le32 mrav_num_av_entries; 3858 __le32 rsvd; 3859 __le32 rsvd2[2]; 3860 }; 3861 3862 /* ts_split_entries (size:128b/16B) */ 3863 struct ts_split_entries { 3864 __le32 region_num_entries; 3865 u8 tsid; 3866 u8 lkup_static_bkt_cnt_exp[2]; 3867 u8 rsvd; 3868 __le32 rsvd2[2]; 3869 }; 3870 3871 /* hwrm_func_backing_store_qcaps_v2_input (size:192b/24B) */ 3872 struct hwrm_func_backing_store_qcaps_v2_input { 3873 __le16 req_type; 3874 __le16 cmpl_ring; 3875 __le16 seq_id; 3876 __le16 target_id; 3877 __le64 resp_addr; 3878 __le16 type; 3879 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP 0x0UL 3880 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ 0x1UL 3881 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ 0x2UL 3882 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC 0x3UL 3883 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT 0x4UL 3884 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3885 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3886 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV 0xeUL 3887 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM 0xfUL 3888 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3889 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3890 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3891 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3892 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3893 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 3894 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_XID_PARTITION 0x1dUL 3895 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT_TRACE 0x1eUL 3896 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT2_TRACE 0x1fUL 3897 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT_TRACE 0x20UL 3898 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT2_TRACE 0x21UL 3899 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP0_TRACE 0x22UL 3900 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL 3901 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL 3902 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 0xffffUL 3903 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 3904 u8 rsvd[6]; 3905 }; 3906 3907 /* hwrm_func_backing_store_qcaps_v2_output (size:448b/56B) */ 3908 struct hwrm_func_backing_store_qcaps_v2_output { 3909 __le16 error_code; 3910 __le16 req_type; 3911 __le16 seq_id; 3912 __le16 resp_len; 3913 __le16 type; 3914 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QP 0x0UL 3915 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ 0x1UL 3916 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ 0x2UL 3917 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_VNIC 0x3UL 3918 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_STAT 0x4UL 3919 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SP_TQM_RING 0x5UL 3920 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_FP_TQM_RING 0x6UL 3921 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MRAV 0xeUL 3922 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TIM 0xfUL 3923 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MP_TQM_RING 0x15UL 3924 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SQ_DB_SHADOW 0x16UL 3925 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RQ_DB_SHADOW 0x17UL 3926 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ_DB_SHADOW 0x18UL 3927 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ_DB_SHADOW 0x19UL 3928 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TBL_SCOPE 0x1cUL 3929 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_XID_PARTITION 0x1dUL 3930 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRT_TRACE 0x1eUL 3931 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRT2_TRACE 0x1fUL 3932 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CRT_TRACE 0x20UL 3933 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CRT2_TRACE 0x21UL 3934 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RIGP0_TRACE 0x22UL 3935 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_L2_HWRM_TRACE 0x23UL 3936 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_ROCE_HWRM_TRACE 0x24UL 3937 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 0xffffUL 3938 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 3939 __le16 entry_size; 3940 __le32 flags; 3941 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ENABLE_CTX_KIND_INIT 0x1UL 3942 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID 0x2UL 3943 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_DRIVER_MANAGED_MEMORY 0x4UL 3944 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ROCE_QP_PSEUDO_STATIC_ALLOC 0x8UL 3945 __le32 instance_bit_map; 3946 u8 ctx_init_value; 3947 u8 ctx_init_offset; 3948 u8 entry_multiple; 3949 u8 rsvd; 3950 __le32 max_num_entries; 3951 __le32 min_num_entries; 3952 __le16 next_valid_type; 3953 u8 subtype_valid_cnt; 3954 u8 exact_cnt_bit_map; 3955 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_0_EXACT 0x1UL 3956 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_1_EXACT 0x2UL 3957 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_2_EXACT 0x4UL 3958 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_3_EXACT 0x8UL 3959 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_UNUSED_MASK 0xf0UL 3960 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_UNUSED_SFT 4 3961 __le32 split_entry_0; 3962 __le32 split_entry_1; 3963 __le32 split_entry_2; 3964 __le32 split_entry_3; 3965 u8 rsvd3[3]; 3966 u8 valid; 3967 }; 3968 3969 /* hwrm_func_dbr_pacing_qcfg_input (size:128b/16B) */ 3970 struct hwrm_func_dbr_pacing_qcfg_input { 3971 __le16 req_type; 3972 __le16 cmpl_ring; 3973 __le16 seq_id; 3974 __le16 target_id; 3975 __le64 resp_addr; 3976 }; 3977 3978 /* hwrm_func_dbr_pacing_qcfg_output (size:512b/64B) */ 3979 struct hwrm_func_dbr_pacing_qcfg_output { 3980 __le16 error_code; 3981 __le16 req_type; 3982 __le16 seq_id; 3983 __le16 resp_len; 3984 u8 flags; 3985 #define FUNC_DBR_PACING_QCFG_RESP_FLAGS_DBR_NQ_EVENT_ENABLED 0x1UL 3986 u8 unused_0[7]; 3987 __le32 dbr_stat_db_fifo_reg; 3988 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK 0x3UL 3989 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_SFT 0 3990 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3991 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC 0x1UL 3992 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR0 0x2UL 3993 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1 0x3UL 3994 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_LAST FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1 3995 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_MASK 0xfffffffcUL 3996 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SFT 2 3997 __le32 dbr_stat_db_fifo_reg_watermark_mask; 3998 u8 dbr_stat_db_fifo_reg_watermark_shift; 3999 u8 unused_1[3]; 4000 __le32 dbr_stat_db_fifo_reg_fifo_room_mask; 4001 u8 dbr_stat_db_fifo_reg_fifo_room_shift; 4002 u8 unused_2[3]; 4003 __le32 dbr_throttling_aeq_arm_reg; 4004 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_MASK 0x3UL 4005 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_SFT 0 4006 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_PCIE_CFG 0x0UL 4007 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_GRC 0x1UL 4008 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR0 0x2UL 4009 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1 0x3UL 4010 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_LAST FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1 4011 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_MASK 0xfffffffcUL 4012 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SFT 2 4013 u8 dbr_throttling_aeq_arm_reg_val; 4014 u8 unused_3[3]; 4015 __le32 dbr_stat_db_max_fifo_depth; 4016 __le32 primary_nq_id; 4017 __le32 pacing_threshold; 4018 u8 unused_4[7]; 4019 u8 valid; 4020 }; 4021 4022 /* hwrm_func_drv_if_change_input (size:192b/24B) */ 4023 struct hwrm_func_drv_if_change_input { 4024 __le16 req_type; 4025 __le16 cmpl_ring; 4026 __le16 seq_id; 4027 __le16 target_id; 4028 __le64 resp_addr; 4029 __le32 flags; 4030 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 4031 __le32 unused; 4032 }; 4033 4034 /* hwrm_func_drv_if_change_output (size:128b/16B) */ 4035 struct hwrm_func_drv_if_change_output { 4036 __le16 error_code; 4037 __le16 req_type; 4038 __le16 seq_id; 4039 __le16 resp_len; 4040 __le32 flags; 4041 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 4042 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 4043 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_CAPS_CHANGE 0x4UL 4044 u8 unused_0[3]; 4045 u8 valid; 4046 }; 4047 4048 /* hwrm_port_phy_cfg_input (size:512b/64B) */ 4049 struct hwrm_port_phy_cfg_input { 4050 __le16 req_type; 4051 __le16 cmpl_ring; 4052 __le16 seq_id; 4053 __le16 target_id; 4054 __le64 resp_addr; 4055 __le32 flags; 4056 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 4057 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 4058 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 4059 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 4060 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 4061 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 4062 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 4063 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 4064 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 4065 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 4066 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 4067 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 4068 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 4069 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 4070 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 4071 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL 4072 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL 4073 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL 4074 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL 4075 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL 4076 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL 4077 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL 4078 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL 4079 __le32 enables; 4080 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 4081 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 4082 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 4083 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 4084 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 4085 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 4086 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 4087 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 4088 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 4089 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 4090 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 4091 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL 4092 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL 4093 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2 0x2000UL 4094 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEEDS2_MASK 0x4000UL 4095 __le16 port_id; 4096 __le16 force_link_speed; 4097 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 4098 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 4099 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 4100 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 4101 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 4102 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 4103 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 4104 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 4105 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 4106 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 4107 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 4108 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 4109 u8 auto_mode; 4110 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 4111 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 4112 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 4113 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 4114 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 4115 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 4116 u8 auto_duplex; 4117 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 4118 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 4119 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 4120 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 4121 u8 auto_pause; 4122 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 4123 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 4124 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 4125 u8 mgmt_flag; 4126 #define PORT_PHY_CFG_REQ_MGMT_FLAG_LINK_RELEASE 0x1UL 4127 #define PORT_PHY_CFG_REQ_MGMT_FLAG_MGMT_VALID 0x80UL 4128 __le16 auto_link_speed; 4129 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 4130 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 4131 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 4132 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 4133 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 4134 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 4135 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 4136 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 4137 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 4138 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 4139 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 4140 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 4141 __le16 auto_link_speed_mask; 4142 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 4143 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 4144 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 4145 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 4146 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 4147 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 4148 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 4149 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 4150 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 4151 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 4152 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 4153 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 4154 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 4155 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 4156 u8 wirespeed; 4157 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 4158 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 4159 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 4160 u8 lpbk; 4161 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 4162 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 4163 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 4164 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 4165 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 4166 u8 force_pause; 4167 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 4168 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 4169 u8 unused_1; 4170 __le32 preemphasis; 4171 __le16 eee_link_speed_mask; 4172 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 4173 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 4174 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 4175 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 4176 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 4177 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 4178 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 4179 __le16 force_pam4_link_speed; 4180 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 4181 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 4182 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 4183 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 4184 __le32 tx_lpi_timer; 4185 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 4186 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 4187 __le16 auto_link_pam4_speed_mask; 4188 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL 4189 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL 4190 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL 4191 __le16 force_link_speeds2; 4192 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_1GB 0xaUL 4193 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_10GB 0x64UL 4194 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_25GB 0xfaUL 4195 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_40GB 0x190UL 4196 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB 0x1f4UL 4197 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB 0x3e8UL 4198 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56 0x1f5UL 4199 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56 0x3e9UL 4200 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56 0x7d1UL 4201 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56 0xfa1UL 4202 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL 4203 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL 4204 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL 4205 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112 4206 __le16 auto_link_speeds2_mask; 4207 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_1GB 0x1UL 4208 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_10GB 0x2UL 4209 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_25GB 0x4UL 4210 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_40GB 0x8UL 4211 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB 0x10UL 4212 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB 0x20UL 4213 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB_PAM4_56 0x40UL 4214 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_56 0x80UL 4215 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_56 0x100UL 4216 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_56 0x200UL 4217 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_112 0x400UL 4218 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_112 0x800UL 4219 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_112 0x1000UL 4220 u8 unused_2[6]; 4221 }; 4222 4223 /* hwrm_port_phy_cfg_output (size:128b/16B) */ 4224 struct hwrm_port_phy_cfg_output { 4225 __le16 error_code; 4226 __le16 req_type; 4227 __le16 seq_id; 4228 __le16 resp_len; 4229 u8 unused_0[7]; 4230 u8 valid; 4231 }; 4232 4233 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 4234 struct hwrm_port_phy_cfg_cmd_err { 4235 u8 code; 4236 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 4237 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 4238 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 4239 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 4240 u8 unused_0[7]; 4241 }; 4242 4243 /* hwrm_port_phy_qcfg_input (size:192b/24B) */ 4244 struct hwrm_port_phy_qcfg_input { 4245 __le16 req_type; 4246 __le16 cmpl_ring; 4247 __le16 seq_id; 4248 __le16 target_id; 4249 __le64 resp_addr; 4250 __le16 port_id; 4251 u8 unused_0[6]; 4252 }; 4253 4254 /* hwrm_port_phy_qcfg_output (size:832b/104B) */ 4255 struct hwrm_port_phy_qcfg_output { 4256 __le16 error_code; 4257 __le16 req_type; 4258 __le16 seq_id; 4259 __le16 resp_len; 4260 u8 link; 4261 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 4262 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 4263 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 4264 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 4265 u8 active_fec_signal_mode; 4266 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL 4267 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0 4268 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL 4269 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL 4270 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112 0x2UL 4271 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112 4272 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL 4273 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4 4274 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4) 4275 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4) 4276 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4) 4277 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4) 4278 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4) 4279 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4) 4280 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4) 4281 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE 4282 __le16 link_speed; 4283 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 4284 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 4285 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 4286 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 4287 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 4288 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 4289 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 4290 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 4291 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 4292 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 4293 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 4294 #define PORT_PHY_QCFG_RESP_LINK_SPEED_400GB 0xfa0UL 4295 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 4296 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 4297 u8 duplex_cfg; 4298 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 4299 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 4300 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 4301 u8 pause; 4302 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 4303 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 4304 __le16 support_speeds; 4305 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 4306 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 4307 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 4308 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 4309 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 4310 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 4311 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 4312 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 4313 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 4314 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 4315 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 4316 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 4317 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 4318 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 4319 __le16 force_link_speed; 4320 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 4321 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 4322 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 4323 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 4324 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 4325 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 4326 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 4327 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 4328 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 4329 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 4330 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 4331 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 4332 u8 auto_mode; 4333 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 4334 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 4335 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 4336 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 4337 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 4338 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 4339 u8 auto_pause; 4340 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 4341 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 4342 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 4343 __le16 auto_link_speed; 4344 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 4345 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 4346 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 4347 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 4348 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 4349 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 4350 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 4351 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 4352 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 4353 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 4354 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 4355 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 4356 __le16 auto_link_speed_mask; 4357 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 4358 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 4359 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 4360 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 4361 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 4362 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 4363 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 4364 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 4365 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 4366 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 4367 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 4368 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 4369 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 4370 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 4371 u8 wirespeed; 4372 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 4373 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 4374 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 4375 u8 lpbk; 4376 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 4377 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 4378 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 4379 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 4380 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 4381 u8 force_pause; 4382 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 4383 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 4384 u8 module_status; 4385 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 4386 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 4387 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 4388 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 4389 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 4390 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL 4391 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 4392 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 4393 __le32 preemphasis; 4394 u8 phy_maj; 4395 u8 phy_min; 4396 u8 phy_bld; 4397 u8 phy_type; 4398 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 4399 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 4400 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 4401 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 4402 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 4403 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 4404 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 4405 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 4406 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 4407 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 4408 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 4409 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 4410 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 4411 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 4412 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 4413 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 4414 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 4415 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 4416 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 4417 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 4418 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 4419 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 4420 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 4421 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 4422 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 4423 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 4424 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 4425 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 4426 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 4427 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 4428 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 4429 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 4430 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR 0x20UL 4431 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR 0x21UL 4432 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR 0x22UL 4433 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER 0x23UL 4434 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2 0x24UL 4435 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2 0x25UL 4436 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2 0x26UL 4437 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2 0x27UL 4438 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR 0x28UL 4439 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR 0x29UL 4440 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR 0x2aUL 4441 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER 0x2bUL 4442 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2 0x2cUL 4443 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2 0x2dUL 4444 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2 0x2eUL 4445 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2 0x2fUL 4446 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8 0x30UL 4447 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8 0x31UL 4448 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8 0x32UL 4449 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8 0x33UL 4450 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4 0x34UL 4451 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4 0x35UL 4452 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4 0x36UL 4453 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4 0x37UL 4454 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4 4455 u8 media_type; 4456 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 4457 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 4458 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 4459 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 4460 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 4461 u8 xcvr_pkg_type; 4462 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 4463 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 4464 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 4465 u8 eee_config_phy_addr; 4466 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 4467 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 4468 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 4469 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 4470 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 4471 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 4472 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 4473 u8 parallel_detect; 4474 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 4475 __le16 link_partner_adv_speeds; 4476 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 4477 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 4478 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 4479 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 4480 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 4481 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 4482 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 4483 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 4484 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 4485 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 4486 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 4487 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 4488 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 4489 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 4490 u8 link_partner_adv_auto_mode; 4491 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 4492 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 4493 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 4494 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 4495 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 4496 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 4497 u8 link_partner_adv_pause; 4498 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 4499 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 4500 __le16 adv_eee_link_speed_mask; 4501 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 4502 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 4503 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 4504 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 4505 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 4506 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 4507 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 4508 __le16 link_partner_adv_eee_link_speed_mask; 4509 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 4510 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 4511 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 4512 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 4513 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 4514 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 4515 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 4516 __le32 xcvr_identifier_type_tx_lpi_timer; 4517 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 4518 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 4519 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 4520 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 4521 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 4522 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 4523 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 4524 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 4525 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 4526 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPDD (0x18UL << 24) 4527 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP112 (0x1eUL << 24) 4528 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFPDD (0x1fUL << 24) 4529 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_CSFP (0x20UL << 24) 4530 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_CSFP 4531 __le16 fec_cfg; 4532 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 4533 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 4534 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 4535 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 4536 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 4537 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 4538 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 4539 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL 4540 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL 4541 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL 4542 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL 4543 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL 4544 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL 4545 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL 4546 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL 4547 u8 duplex_state; 4548 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 4549 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 4550 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 4551 u8 option_flags; 4552 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 4553 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN 0x2UL 4554 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SPEEDS2_SUPPORTED 0x4UL 4555 char phy_vendor_name[16]; 4556 char phy_vendor_partnumber[16]; 4557 __le16 support_pam4_speeds; 4558 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL 4559 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL 4560 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL 4561 __le16 force_pam4_link_speed; 4562 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 4563 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 4564 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 4565 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 4566 __le16 auto_pam4_link_speed_mask; 4567 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL 4568 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL 4569 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL 4570 u8 link_partner_pam4_adv_speeds; 4571 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL 4572 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL 4573 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL 4574 u8 link_down_reason; 4575 #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF 0x1UL 4576 __le16 support_speeds2; 4577 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB 0x1UL 4578 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB 0x2UL 4579 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_25GB 0x4UL 4580 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_40GB 0x8UL 4581 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB 0x10UL 4582 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB 0x20UL 4583 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB_PAM4_56 0x40UL 4584 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_56 0x80UL 4585 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_56 0x100UL 4586 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_56 0x200UL 4587 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_112 0x400UL 4588 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_112 0x800UL 4589 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_112 0x1000UL 4590 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_800GB_PAM4_112 0x2000UL 4591 __le16 force_link_speeds2; 4592 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_1GB 0xaUL 4593 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_10GB 0x64UL 4594 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_25GB 0xfaUL 4595 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_40GB 0x190UL 4596 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB 0x1f4UL 4597 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB 0x3e8UL 4598 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB_PAM4_56 0x1f5UL 4599 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_56 0x3e9UL 4600 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_56 0x7d1UL 4601 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_56 0xfa1UL 4602 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL 4603 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL 4604 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL 4605 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112 0x1f42UL 4606 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112 4607 __le16 auto_link_speeds2; 4608 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_1GB 0x1UL 4609 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_10GB 0x2UL 4610 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_25GB 0x4UL 4611 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_40GB 0x8UL 4612 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB 0x10UL 4613 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB 0x20UL 4614 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB_PAM4_56 0x40UL 4615 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_56 0x80UL 4616 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_56 0x100UL 4617 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_56 0x200UL 4618 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_112 0x400UL 4619 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_112 0x800UL 4620 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_112 0x1000UL 4621 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_800GB_PAM4_112 0x2000UL 4622 u8 active_lanes; 4623 u8 valid; 4624 }; 4625 4626 /* hwrm_port_mac_cfg_input (size:448b/56B) */ 4627 struct hwrm_port_mac_cfg_input { 4628 __le16 req_type; 4629 __le16 cmpl_ring; 4630 __le16 seq_id; 4631 __le16 target_id; 4632 __le64 resp_addr; 4633 __le32 flags; 4634 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 4635 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 4636 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 4637 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 4638 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 4639 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 4640 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 4641 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 4642 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 4643 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 4644 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 4645 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 4646 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 4647 #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL 4648 #define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE 0x4000UL 4649 #define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE 0x8000UL 4650 __le32 enables; 4651 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 4652 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 4653 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 4654 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 4655 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 4656 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 4657 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 4658 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 4659 #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL 4660 #define PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE 0x400UL 4661 #define PORT_MAC_CFG_REQ_ENABLES_PTP_LOAD_CONTROL 0x800UL 4662 __le16 port_id; 4663 u8 ipg; 4664 u8 lpbk; 4665 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 4666 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 4667 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 4668 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 4669 u8 vlan_pri2cos_map_pri; 4670 u8 reserved1; 4671 u8 tunnel_pri2cos_map_pri; 4672 u8 dscp2pri_map_pri; 4673 __le16 rx_ts_capture_ptp_msg_type; 4674 __le16 tx_ts_capture_ptp_msg_type; 4675 u8 cos_field_cfg; 4676 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 4677 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 4678 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 4679 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 4680 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 4681 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 4682 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 4683 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 4684 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 4685 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 4686 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 4687 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 4688 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 4689 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 4690 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 4691 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 4692 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 4693 u8 unused_0[3]; 4694 __le32 ptp_freq_adj_ppb; 4695 u8 unused_1[3]; 4696 u8 ptp_load_control; 4697 #define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_NONE 0x0UL 4698 #define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_IMMEDIATE 0x1UL 4699 #define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_PPS_EVENT 0x2UL 4700 #define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_LAST PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_PPS_EVENT 4701 __le64 ptp_adj_phase; 4702 }; 4703 4704 /* hwrm_port_mac_cfg_output (size:128b/16B) */ 4705 struct hwrm_port_mac_cfg_output { 4706 __le16 error_code; 4707 __le16 req_type; 4708 __le16 seq_id; 4709 __le16 resp_len; 4710 __le16 mru; 4711 __le16 mtu; 4712 u8 ipg; 4713 u8 lpbk; 4714 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 4715 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 4716 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 4717 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 4718 u8 unused_0; 4719 u8 valid; 4720 }; 4721 4722 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 4723 struct hwrm_port_mac_ptp_qcfg_input { 4724 __le16 req_type; 4725 __le16 cmpl_ring; 4726 __le16 seq_id; 4727 __le16 target_id; 4728 __le64 resp_addr; 4729 __le16 port_id; 4730 u8 unused_0[6]; 4731 }; 4732 4733 /* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */ 4734 struct hwrm_port_mac_ptp_qcfg_output { 4735 __le16 error_code; 4736 __le16 req_type; 4737 __le16 seq_id; 4738 __le16 resp_len; 4739 u8 flags; 4740 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 4741 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL 4742 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL 4743 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK 0x10UL 4744 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_RTC_CONFIGURED 0x20UL 4745 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_64B_PHC_TIME 0x40UL 4746 u8 unused_0[3]; 4747 __le32 rx_ts_reg_off_lower; 4748 __le32 rx_ts_reg_off_upper; 4749 __le32 rx_ts_reg_off_seq_id; 4750 __le32 rx_ts_reg_off_src_id_0; 4751 __le32 rx_ts_reg_off_src_id_1; 4752 __le32 rx_ts_reg_off_src_id_2; 4753 __le32 rx_ts_reg_off_domain_id; 4754 __le32 rx_ts_reg_off_fifo; 4755 __le32 rx_ts_reg_off_fifo_adv; 4756 __le32 rx_ts_reg_off_granularity; 4757 __le32 tx_ts_reg_off_lower; 4758 __le32 tx_ts_reg_off_upper; 4759 __le32 tx_ts_reg_off_seq_id; 4760 __le32 tx_ts_reg_off_fifo; 4761 __le32 tx_ts_reg_off_granularity; 4762 __le32 ts_ref_clock_reg_lower; 4763 __le32 ts_ref_clock_reg_upper; 4764 u8 unused_1[7]; 4765 u8 valid; 4766 }; 4767 4768 /* tx_port_stats (size:3264b/408B) */ 4769 struct tx_port_stats { 4770 __le64 tx_64b_frames; 4771 __le64 tx_65b_127b_frames; 4772 __le64 tx_128b_255b_frames; 4773 __le64 tx_256b_511b_frames; 4774 __le64 tx_512b_1023b_frames; 4775 __le64 tx_1024b_1518b_frames; 4776 __le64 tx_good_vlan_frames; 4777 __le64 tx_1519b_2047b_frames; 4778 __le64 tx_2048b_4095b_frames; 4779 __le64 tx_4096b_9216b_frames; 4780 __le64 tx_9217b_16383b_frames; 4781 __le64 tx_good_frames; 4782 __le64 tx_total_frames; 4783 __le64 tx_ucast_frames; 4784 __le64 tx_mcast_frames; 4785 __le64 tx_bcast_frames; 4786 __le64 tx_pause_frames; 4787 __le64 tx_pfc_frames; 4788 __le64 tx_jabber_frames; 4789 __le64 tx_fcs_err_frames; 4790 __le64 tx_control_frames; 4791 __le64 tx_oversz_frames; 4792 __le64 tx_single_dfrl_frames; 4793 __le64 tx_multi_dfrl_frames; 4794 __le64 tx_single_coll_frames; 4795 __le64 tx_multi_coll_frames; 4796 __le64 tx_late_coll_frames; 4797 __le64 tx_excessive_coll_frames; 4798 __le64 tx_frag_frames; 4799 __le64 tx_err; 4800 __le64 tx_tagged_frames; 4801 __le64 tx_dbl_tagged_frames; 4802 __le64 tx_runt_frames; 4803 __le64 tx_fifo_underruns; 4804 __le64 tx_pfc_ena_frames_pri0; 4805 __le64 tx_pfc_ena_frames_pri1; 4806 __le64 tx_pfc_ena_frames_pri2; 4807 __le64 tx_pfc_ena_frames_pri3; 4808 __le64 tx_pfc_ena_frames_pri4; 4809 __le64 tx_pfc_ena_frames_pri5; 4810 __le64 tx_pfc_ena_frames_pri6; 4811 __le64 tx_pfc_ena_frames_pri7; 4812 __le64 tx_eee_lpi_events; 4813 __le64 tx_eee_lpi_duration; 4814 __le64 tx_llfc_logical_msgs; 4815 __le64 tx_hcfc_msgs; 4816 __le64 tx_total_collisions; 4817 __le64 tx_bytes; 4818 __le64 tx_xthol_frames; 4819 __le64 tx_stat_discard; 4820 __le64 tx_stat_error; 4821 }; 4822 4823 /* rx_port_stats (size:4224b/528B) */ 4824 struct rx_port_stats { 4825 __le64 rx_64b_frames; 4826 __le64 rx_65b_127b_frames; 4827 __le64 rx_128b_255b_frames; 4828 __le64 rx_256b_511b_frames; 4829 __le64 rx_512b_1023b_frames; 4830 __le64 rx_1024b_1518b_frames; 4831 __le64 rx_good_vlan_frames; 4832 __le64 rx_1519b_2047b_frames; 4833 __le64 rx_2048b_4095b_frames; 4834 __le64 rx_4096b_9216b_frames; 4835 __le64 rx_9217b_16383b_frames; 4836 __le64 rx_total_frames; 4837 __le64 rx_ucast_frames; 4838 __le64 rx_mcast_frames; 4839 __le64 rx_bcast_frames; 4840 __le64 rx_fcs_err_frames; 4841 __le64 rx_ctrl_frames; 4842 __le64 rx_pause_frames; 4843 __le64 rx_pfc_frames; 4844 __le64 rx_unsupported_opcode_frames; 4845 __le64 rx_unsupported_da_pausepfc_frames; 4846 __le64 rx_wrong_sa_frames; 4847 __le64 rx_align_err_frames; 4848 __le64 rx_oor_len_frames; 4849 __le64 rx_code_err_frames; 4850 __le64 rx_false_carrier_frames; 4851 __le64 rx_ovrsz_frames; 4852 __le64 rx_jbr_frames; 4853 __le64 rx_mtu_err_frames; 4854 __le64 rx_match_crc_frames; 4855 __le64 rx_promiscuous_frames; 4856 __le64 rx_tagged_frames; 4857 __le64 rx_double_tagged_frames; 4858 __le64 rx_trunc_frames; 4859 __le64 rx_good_frames; 4860 __le64 rx_pfc_xon2xoff_frames_pri0; 4861 __le64 rx_pfc_xon2xoff_frames_pri1; 4862 __le64 rx_pfc_xon2xoff_frames_pri2; 4863 __le64 rx_pfc_xon2xoff_frames_pri3; 4864 __le64 rx_pfc_xon2xoff_frames_pri4; 4865 __le64 rx_pfc_xon2xoff_frames_pri5; 4866 __le64 rx_pfc_xon2xoff_frames_pri6; 4867 __le64 rx_pfc_xon2xoff_frames_pri7; 4868 __le64 rx_pfc_ena_frames_pri0; 4869 __le64 rx_pfc_ena_frames_pri1; 4870 __le64 rx_pfc_ena_frames_pri2; 4871 __le64 rx_pfc_ena_frames_pri3; 4872 __le64 rx_pfc_ena_frames_pri4; 4873 __le64 rx_pfc_ena_frames_pri5; 4874 __le64 rx_pfc_ena_frames_pri6; 4875 __le64 rx_pfc_ena_frames_pri7; 4876 __le64 rx_sch_crc_err_frames; 4877 __le64 rx_undrsz_frames; 4878 __le64 rx_frag_frames; 4879 __le64 rx_eee_lpi_events; 4880 __le64 rx_eee_lpi_duration; 4881 __le64 rx_llfc_physical_msgs; 4882 __le64 rx_llfc_logical_msgs; 4883 __le64 rx_llfc_msgs_with_crc_err; 4884 __le64 rx_hcfc_msgs; 4885 __le64 rx_hcfc_msgs_with_crc_err; 4886 __le64 rx_bytes; 4887 __le64 rx_runt_bytes; 4888 __le64 rx_runt_frames; 4889 __le64 rx_stat_discard; 4890 __le64 rx_stat_err; 4891 }; 4892 4893 /* hwrm_port_qstats_input (size:320b/40B) */ 4894 struct hwrm_port_qstats_input { 4895 __le16 req_type; 4896 __le16 cmpl_ring; 4897 __le16 seq_id; 4898 __le16 target_id; 4899 __le64 resp_addr; 4900 __le16 port_id; 4901 u8 flags; 4902 #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 4903 u8 unused_0[5]; 4904 __le64 tx_stat_host_addr; 4905 __le64 rx_stat_host_addr; 4906 }; 4907 4908 /* hwrm_port_qstats_output (size:128b/16B) */ 4909 struct hwrm_port_qstats_output { 4910 __le16 error_code; 4911 __le16 req_type; 4912 __le16 seq_id; 4913 __le16 resp_len; 4914 __le16 tx_stat_size; 4915 __le16 rx_stat_size; 4916 u8 unused_0[3]; 4917 u8 valid; 4918 }; 4919 4920 /* tx_port_stats_ext (size:2048b/256B) */ 4921 struct tx_port_stats_ext { 4922 __le64 tx_bytes_cos0; 4923 __le64 tx_bytes_cos1; 4924 __le64 tx_bytes_cos2; 4925 __le64 tx_bytes_cos3; 4926 __le64 tx_bytes_cos4; 4927 __le64 tx_bytes_cos5; 4928 __le64 tx_bytes_cos6; 4929 __le64 tx_bytes_cos7; 4930 __le64 tx_packets_cos0; 4931 __le64 tx_packets_cos1; 4932 __le64 tx_packets_cos2; 4933 __le64 tx_packets_cos3; 4934 __le64 tx_packets_cos4; 4935 __le64 tx_packets_cos5; 4936 __le64 tx_packets_cos6; 4937 __le64 tx_packets_cos7; 4938 __le64 pfc_pri0_tx_duration_us; 4939 __le64 pfc_pri0_tx_transitions; 4940 __le64 pfc_pri1_tx_duration_us; 4941 __le64 pfc_pri1_tx_transitions; 4942 __le64 pfc_pri2_tx_duration_us; 4943 __le64 pfc_pri2_tx_transitions; 4944 __le64 pfc_pri3_tx_duration_us; 4945 __le64 pfc_pri3_tx_transitions; 4946 __le64 pfc_pri4_tx_duration_us; 4947 __le64 pfc_pri4_tx_transitions; 4948 __le64 pfc_pri5_tx_duration_us; 4949 __le64 pfc_pri5_tx_transitions; 4950 __le64 pfc_pri6_tx_duration_us; 4951 __le64 pfc_pri6_tx_transitions; 4952 __le64 pfc_pri7_tx_duration_us; 4953 __le64 pfc_pri7_tx_transitions; 4954 }; 4955 4956 /* rx_port_stats_ext (size:3904b/488B) */ 4957 struct rx_port_stats_ext { 4958 __le64 link_down_events; 4959 __le64 continuous_pause_events; 4960 __le64 resume_pause_events; 4961 __le64 continuous_roce_pause_events; 4962 __le64 resume_roce_pause_events; 4963 __le64 rx_bytes_cos0; 4964 __le64 rx_bytes_cos1; 4965 __le64 rx_bytes_cos2; 4966 __le64 rx_bytes_cos3; 4967 __le64 rx_bytes_cos4; 4968 __le64 rx_bytes_cos5; 4969 __le64 rx_bytes_cos6; 4970 __le64 rx_bytes_cos7; 4971 __le64 rx_packets_cos0; 4972 __le64 rx_packets_cos1; 4973 __le64 rx_packets_cos2; 4974 __le64 rx_packets_cos3; 4975 __le64 rx_packets_cos4; 4976 __le64 rx_packets_cos5; 4977 __le64 rx_packets_cos6; 4978 __le64 rx_packets_cos7; 4979 __le64 pfc_pri0_rx_duration_us; 4980 __le64 pfc_pri0_rx_transitions; 4981 __le64 pfc_pri1_rx_duration_us; 4982 __le64 pfc_pri1_rx_transitions; 4983 __le64 pfc_pri2_rx_duration_us; 4984 __le64 pfc_pri2_rx_transitions; 4985 __le64 pfc_pri3_rx_duration_us; 4986 __le64 pfc_pri3_rx_transitions; 4987 __le64 pfc_pri4_rx_duration_us; 4988 __le64 pfc_pri4_rx_transitions; 4989 __le64 pfc_pri5_rx_duration_us; 4990 __le64 pfc_pri5_rx_transitions; 4991 __le64 pfc_pri6_rx_duration_us; 4992 __le64 pfc_pri6_rx_transitions; 4993 __le64 pfc_pri7_rx_duration_us; 4994 __le64 pfc_pri7_rx_transitions; 4995 __le64 rx_bits; 4996 __le64 rx_buffer_passed_threshold; 4997 __le64 rx_pcs_symbol_err; 4998 __le64 rx_corrected_bits; 4999 __le64 rx_discard_bytes_cos0; 5000 __le64 rx_discard_bytes_cos1; 5001 __le64 rx_discard_bytes_cos2; 5002 __le64 rx_discard_bytes_cos3; 5003 __le64 rx_discard_bytes_cos4; 5004 __le64 rx_discard_bytes_cos5; 5005 __le64 rx_discard_bytes_cos6; 5006 __le64 rx_discard_bytes_cos7; 5007 __le64 rx_discard_packets_cos0; 5008 __le64 rx_discard_packets_cos1; 5009 __le64 rx_discard_packets_cos2; 5010 __le64 rx_discard_packets_cos3; 5011 __le64 rx_discard_packets_cos4; 5012 __le64 rx_discard_packets_cos5; 5013 __le64 rx_discard_packets_cos6; 5014 __le64 rx_discard_packets_cos7; 5015 __le64 rx_fec_corrected_blocks; 5016 __le64 rx_fec_uncorrectable_blocks; 5017 __le64 rx_filter_miss; 5018 __le64 rx_fec_symbol_err; 5019 }; 5020 5021 /* hwrm_port_qstats_ext_input (size:320b/40B) */ 5022 struct hwrm_port_qstats_ext_input { 5023 __le16 req_type; 5024 __le16 cmpl_ring; 5025 __le16 seq_id; 5026 __le16 target_id; 5027 __le64 resp_addr; 5028 __le16 port_id; 5029 __le16 tx_stat_size; 5030 __le16 rx_stat_size; 5031 u8 flags; 5032 #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL 5033 u8 unused_0; 5034 __le64 tx_stat_host_addr; 5035 __le64 rx_stat_host_addr; 5036 }; 5037 5038 /* hwrm_port_qstats_ext_output (size:128b/16B) */ 5039 struct hwrm_port_qstats_ext_output { 5040 __le16 error_code; 5041 __le16 req_type; 5042 __le16 seq_id; 5043 __le16 resp_len; 5044 __le16 tx_stat_size; 5045 __le16 rx_stat_size; 5046 __le16 total_active_cos_queues; 5047 u8 flags; 5048 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 5049 u8 valid; 5050 }; 5051 5052 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */ 5053 struct hwrm_port_lpbk_qstats_input { 5054 __le16 req_type; 5055 __le16 cmpl_ring; 5056 __le16 seq_id; 5057 __le16 target_id; 5058 __le64 resp_addr; 5059 }; 5060 5061 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */ 5062 struct hwrm_port_lpbk_qstats_output { 5063 __le16 error_code; 5064 __le16 req_type; 5065 __le16 seq_id; 5066 __le16 resp_len; 5067 __le64 lpbk_ucast_frames; 5068 __le64 lpbk_mcast_frames; 5069 __le64 lpbk_bcast_frames; 5070 __le64 lpbk_ucast_bytes; 5071 __le64 lpbk_mcast_bytes; 5072 __le64 lpbk_bcast_bytes; 5073 __le64 tx_stat_discard; 5074 __le64 tx_stat_error; 5075 __le64 rx_stat_discard; 5076 __le64 rx_stat_error; 5077 u8 unused_0[7]; 5078 u8 valid; 5079 }; 5080 5081 /* hwrm_port_ecn_qstats_input (size:256b/32B) */ 5082 struct hwrm_port_ecn_qstats_input { 5083 __le16 req_type; 5084 __le16 cmpl_ring; 5085 __le16 seq_id; 5086 __le16 target_id; 5087 __le64 resp_addr; 5088 __le16 port_id; 5089 __le16 ecn_stat_buf_size; 5090 u8 flags; 5091 #define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 5092 u8 unused_0[3]; 5093 __le64 ecn_stat_host_addr; 5094 }; 5095 5096 /* hwrm_port_ecn_qstats_output (size:128b/16B) */ 5097 struct hwrm_port_ecn_qstats_output { 5098 __le16 error_code; 5099 __le16 req_type; 5100 __le16 seq_id; 5101 __le16 resp_len; 5102 __le16 ecn_stat_buf_size; 5103 u8 mark_en; 5104 u8 unused_0[4]; 5105 u8 valid; 5106 }; 5107 5108 /* port_stats_ecn (size:512b/64B) */ 5109 struct port_stats_ecn { 5110 __le64 mark_cnt_cos0; 5111 __le64 mark_cnt_cos1; 5112 __le64 mark_cnt_cos2; 5113 __le64 mark_cnt_cos3; 5114 __le64 mark_cnt_cos4; 5115 __le64 mark_cnt_cos5; 5116 __le64 mark_cnt_cos6; 5117 __le64 mark_cnt_cos7; 5118 }; 5119 5120 /* hwrm_port_clr_stats_input (size:192b/24B) */ 5121 struct hwrm_port_clr_stats_input { 5122 __le16 req_type; 5123 __le16 cmpl_ring; 5124 __le16 seq_id; 5125 __le16 target_id; 5126 __le64 resp_addr; 5127 __le16 port_id; 5128 u8 flags; 5129 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 5130 u8 unused_0[5]; 5131 }; 5132 5133 /* hwrm_port_clr_stats_output (size:128b/16B) */ 5134 struct hwrm_port_clr_stats_output { 5135 __le16 error_code; 5136 __le16 req_type; 5137 __le16 seq_id; 5138 __le16 resp_len; 5139 u8 unused_0[7]; 5140 u8 valid; 5141 }; 5142 5143 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ 5144 struct hwrm_port_lpbk_clr_stats_input { 5145 __le16 req_type; 5146 __le16 cmpl_ring; 5147 __le16 seq_id; 5148 __le16 target_id; 5149 __le64 resp_addr; 5150 }; 5151 5152 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 5153 struct hwrm_port_lpbk_clr_stats_output { 5154 __le16 error_code; 5155 __le16 req_type; 5156 __le16 seq_id; 5157 __le16 resp_len; 5158 u8 unused_0[7]; 5159 u8 valid; 5160 }; 5161 5162 /* hwrm_port_ts_query_input (size:320b/40B) */ 5163 struct hwrm_port_ts_query_input { 5164 __le16 req_type; 5165 __le16 cmpl_ring; 5166 __le16 seq_id; 5167 __le16 target_id; 5168 __le64 resp_addr; 5169 __le32 flags; 5170 #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL 5171 #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL 5172 #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL 5173 #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX 5174 #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL 5175 __le16 port_id; 5176 u8 unused_0[2]; 5177 __le16 enables; 5178 #define PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT 0x1UL 5179 #define PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID 0x2UL 5180 #define PORT_TS_QUERY_REQ_ENABLES_PTP_HDR_OFFSET 0x4UL 5181 __le16 ts_req_timeout; 5182 __le32 ptp_seq_id; 5183 __le16 ptp_hdr_offset; 5184 u8 unused_1[6]; 5185 }; 5186 5187 /* hwrm_port_ts_query_output (size:192b/24B) */ 5188 struct hwrm_port_ts_query_output { 5189 __le16 error_code; 5190 __le16 req_type; 5191 __le16 seq_id; 5192 __le16 resp_len; 5193 __le64 ptp_msg_ts; 5194 __le16 ptp_msg_seqid; 5195 u8 unused_0[5]; 5196 u8 valid; 5197 }; 5198 5199 /* hwrm_port_phy_qcaps_input (size:192b/24B) */ 5200 struct hwrm_port_phy_qcaps_input { 5201 __le16 req_type; 5202 __le16 cmpl_ring; 5203 __le16 seq_id; 5204 __le16 target_id; 5205 __le64 resp_addr; 5206 __le16 port_id; 5207 u8 unused_0[6]; 5208 }; 5209 5210 /* hwrm_port_phy_qcaps_output (size:320b/40B) */ 5211 struct hwrm_port_phy_qcaps_output { 5212 __le16 error_code; 5213 __le16 req_type; 5214 __le16 seq_id; 5215 __le16 resp_len; 5216 u8 flags; 5217 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 5218 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 5219 #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL 5220 #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL 5221 #define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL 5222 #define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x20UL 5223 #define PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN 0x40UL 5224 #define PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS 0x80UL 5225 u8 port_cnt; 5226 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 5227 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 5228 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 5229 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 5230 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 5231 #define PORT_PHY_QCAPS_RESP_PORT_CNT_12 0xcUL 5232 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_12 5233 __le16 supported_speeds_force_mode; 5234 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 5235 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 5236 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 5237 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 5238 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 5239 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 5240 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 5241 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 5242 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 5243 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 5244 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 5245 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 5246 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 5247 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 5248 __le16 supported_speeds_auto_mode; 5249 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 5250 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 5251 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 5252 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 5253 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 5254 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 5255 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 5256 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 5257 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 5258 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 5259 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 5260 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 5261 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 5262 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 5263 __le16 supported_speeds_eee_mode; 5264 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 5265 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 5266 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 5267 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 5268 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 5269 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 5270 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 5271 __le32 tx_lpi_timer_low; 5272 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 5273 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 5274 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 5275 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 5276 __le32 valid_tx_lpi_timer_high; 5277 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 5278 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 5279 #define PORT_PHY_QCAPS_RESP_RSVD_MASK 0xff000000UL 5280 #define PORT_PHY_QCAPS_RESP_RSVD_SFT 24 5281 __le16 supported_pam4_speeds_auto_mode; 5282 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL 5283 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL 5284 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL 5285 __le16 supported_pam4_speeds_force_mode; 5286 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL 5287 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL 5288 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL 5289 __le16 flags2; 5290 #define PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED 0x1UL 5291 #define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED 0x2UL 5292 #define PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED 0x4UL 5293 #define PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED 0x8UL 5294 u8 internal_port_cnt; 5295 u8 unused_0; 5296 __le16 supported_speeds2_force_mode; 5297 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_1GB 0x1UL 5298 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_10GB 0x2UL 5299 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_25GB 0x4UL 5300 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_40GB 0x8UL 5301 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB 0x10UL 5302 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB 0x20UL 5303 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB_PAM4_56 0x40UL 5304 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_56 0x80UL 5305 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_56 0x100UL 5306 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_56 0x200UL 5307 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_112 0x400UL 5308 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_112 0x800UL 5309 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_112 0x1000UL 5310 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_800GB_PAM4_112 0x2000UL 5311 __le16 supported_speeds2_auto_mode; 5312 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_1GB 0x1UL 5313 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_10GB 0x2UL 5314 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_25GB 0x4UL 5315 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_40GB 0x8UL 5316 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB 0x10UL 5317 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB 0x20UL 5318 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB_PAM4_56 0x40UL 5319 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_56 0x80UL 5320 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_56 0x100UL 5321 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_56 0x200UL 5322 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_112 0x400UL 5323 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_112 0x800UL 5324 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_112 0x1000UL 5325 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_800GB_PAM4_112 0x2000UL 5326 u8 unused_1[3]; 5327 u8 valid; 5328 }; 5329 5330 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 5331 struct hwrm_port_phy_i2c_read_input { 5332 __le16 req_type; 5333 __le16 cmpl_ring; 5334 __le16 seq_id; 5335 __le16 target_id; 5336 __le64 resp_addr; 5337 __le32 flags; 5338 __le32 enables; 5339 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 5340 #define PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER 0x2UL 5341 __le16 port_id; 5342 u8 i2c_slave_addr; 5343 u8 bank_number; 5344 __le16 page_number; 5345 __le16 page_offset; 5346 u8 data_length; 5347 u8 unused_1[7]; 5348 }; 5349 5350 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 5351 struct hwrm_port_phy_i2c_read_output { 5352 __le16 error_code; 5353 __le16 req_type; 5354 __le16 seq_id; 5355 __le16 resp_len; 5356 __le32 data[16]; 5357 u8 unused_0[7]; 5358 u8 valid; 5359 }; 5360 5361 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */ 5362 struct hwrm_port_phy_mdio_write_input { 5363 __le16 req_type; 5364 __le16 cmpl_ring; 5365 __le16 seq_id; 5366 __le16 target_id; 5367 __le64 resp_addr; 5368 __le32 unused_0[2]; 5369 __le16 port_id; 5370 u8 phy_addr; 5371 u8 dev_addr; 5372 __le16 reg_addr; 5373 __le16 reg_data; 5374 u8 cl45_mdio; 5375 u8 unused_1[7]; 5376 }; 5377 5378 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */ 5379 struct hwrm_port_phy_mdio_write_output { 5380 __le16 error_code; 5381 __le16 req_type; 5382 __le16 seq_id; 5383 __le16 resp_len; 5384 u8 unused_0[7]; 5385 u8 valid; 5386 }; 5387 5388 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */ 5389 struct hwrm_port_phy_mdio_read_input { 5390 __le16 req_type; 5391 __le16 cmpl_ring; 5392 __le16 seq_id; 5393 __le16 target_id; 5394 __le64 resp_addr; 5395 __le32 unused_0[2]; 5396 __le16 port_id; 5397 u8 phy_addr; 5398 u8 dev_addr; 5399 __le16 reg_addr; 5400 u8 cl45_mdio; 5401 u8 unused_1; 5402 }; 5403 5404 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */ 5405 struct hwrm_port_phy_mdio_read_output { 5406 __le16 error_code; 5407 __le16 req_type; 5408 __le16 seq_id; 5409 __le16 resp_len; 5410 __le16 reg_data; 5411 u8 unused_0[5]; 5412 u8 valid; 5413 }; 5414 5415 /* hwrm_port_led_cfg_input (size:512b/64B) */ 5416 struct hwrm_port_led_cfg_input { 5417 __le16 req_type; 5418 __le16 cmpl_ring; 5419 __le16 seq_id; 5420 __le16 target_id; 5421 __le64 resp_addr; 5422 __le32 enables; 5423 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 5424 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 5425 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 5426 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 5427 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 5428 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 5429 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 5430 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 5431 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 5432 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 5433 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 5434 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 5435 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 5436 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 5437 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 5438 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 5439 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 5440 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 5441 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 5442 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 5443 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 5444 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 5445 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 5446 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 5447 __le16 port_id; 5448 u8 num_leds; 5449 u8 rsvd; 5450 u8 led0_id; 5451 u8 led0_state; 5452 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 5453 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 5454 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 5455 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 5456 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 5457 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 5458 u8 led0_color; 5459 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 5460 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 5461 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 5462 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 5463 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 5464 u8 unused_0; 5465 __le16 led0_blink_on; 5466 __le16 led0_blink_off; 5467 u8 led0_group_id; 5468 u8 rsvd0; 5469 u8 led1_id; 5470 u8 led1_state; 5471 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 5472 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 5473 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 5474 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 5475 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 5476 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 5477 u8 led1_color; 5478 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 5479 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 5480 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 5481 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 5482 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 5483 u8 unused_1; 5484 __le16 led1_blink_on; 5485 __le16 led1_blink_off; 5486 u8 led1_group_id; 5487 u8 rsvd1; 5488 u8 led2_id; 5489 u8 led2_state; 5490 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 5491 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 5492 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 5493 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 5494 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 5495 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 5496 u8 led2_color; 5497 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 5498 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 5499 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 5500 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 5501 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 5502 u8 unused_2; 5503 __le16 led2_blink_on; 5504 __le16 led2_blink_off; 5505 u8 led2_group_id; 5506 u8 rsvd2; 5507 u8 led3_id; 5508 u8 led3_state; 5509 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 5510 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 5511 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 5512 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 5513 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 5514 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 5515 u8 led3_color; 5516 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 5517 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 5518 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 5519 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 5520 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 5521 u8 unused_3; 5522 __le16 led3_blink_on; 5523 __le16 led3_blink_off; 5524 u8 led3_group_id; 5525 u8 rsvd3; 5526 }; 5527 5528 /* hwrm_port_led_cfg_output (size:128b/16B) */ 5529 struct hwrm_port_led_cfg_output { 5530 __le16 error_code; 5531 __le16 req_type; 5532 __le16 seq_id; 5533 __le16 resp_len; 5534 u8 unused_0[7]; 5535 u8 valid; 5536 }; 5537 5538 /* hwrm_port_led_qcfg_input (size:192b/24B) */ 5539 struct hwrm_port_led_qcfg_input { 5540 __le16 req_type; 5541 __le16 cmpl_ring; 5542 __le16 seq_id; 5543 __le16 target_id; 5544 __le64 resp_addr; 5545 __le16 port_id; 5546 u8 unused_0[6]; 5547 }; 5548 5549 /* hwrm_port_led_qcfg_output (size:448b/56B) */ 5550 struct hwrm_port_led_qcfg_output { 5551 __le16 error_code; 5552 __le16 req_type; 5553 __le16 seq_id; 5554 __le16 resp_len; 5555 u8 num_leds; 5556 u8 led0_id; 5557 u8 led0_type; 5558 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 5559 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 5560 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 5561 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 5562 u8 led0_state; 5563 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 5564 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 5565 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 5566 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 5567 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 5568 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 5569 u8 led0_color; 5570 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 5571 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 5572 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 5573 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 5574 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 5575 u8 unused_0; 5576 __le16 led0_blink_on; 5577 __le16 led0_blink_off; 5578 u8 led0_group_id; 5579 u8 led1_id; 5580 u8 led1_type; 5581 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 5582 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 5583 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 5584 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 5585 u8 led1_state; 5586 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 5587 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 5588 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 5589 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 5590 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 5591 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 5592 u8 led1_color; 5593 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 5594 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 5595 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 5596 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 5597 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 5598 u8 unused_1; 5599 __le16 led1_blink_on; 5600 __le16 led1_blink_off; 5601 u8 led1_group_id; 5602 u8 led2_id; 5603 u8 led2_type; 5604 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 5605 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 5606 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 5607 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 5608 u8 led2_state; 5609 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 5610 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 5611 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 5612 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 5613 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 5614 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 5615 u8 led2_color; 5616 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 5617 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 5618 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 5619 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 5620 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 5621 u8 unused_2; 5622 __le16 led2_blink_on; 5623 __le16 led2_blink_off; 5624 u8 led2_group_id; 5625 u8 led3_id; 5626 u8 led3_type; 5627 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 5628 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 5629 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 5630 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 5631 u8 led3_state; 5632 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 5633 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 5634 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 5635 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 5636 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 5637 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 5638 u8 led3_color; 5639 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 5640 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 5641 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 5642 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 5643 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 5644 u8 unused_3; 5645 __le16 led3_blink_on; 5646 __le16 led3_blink_off; 5647 u8 led3_group_id; 5648 u8 unused_4[6]; 5649 u8 valid; 5650 }; 5651 5652 /* hwrm_port_led_qcaps_input (size:192b/24B) */ 5653 struct hwrm_port_led_qcaps_input { 5654 __le16 req_type; 5655 __le16 cmpl_ring; 5656 __le16 seq_id; 5657 __le16 target_id; 5658 __le64 resp_addr; 5659 __le16 port_id; 5660 u8 unused_0[6]; 5661 }; 5662 5663 /* hwrm_port_led_qcaps_output (size:384b/48B) */ 5664 struct hwrm_port_led_qcaps_output { 5665 __le16 error_code; 5666 __le16 req_type; 5667 __le16 seq_id; 5668 __le16 resp_len; 5669 u8 num_leds; 5670 u8 unused[3]; 5671 u8 led0_id; 5672 u8 led0_type; 5673 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 5674 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 5675 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 5676 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 5677 u8 led0_group_id; 5678 u8 unused_0; 5679 __le16 led0_state_caps; 5680 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 5681 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 5682 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 5683 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5684 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5685 __le16 led0_color_caps; 5686 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 5687 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5688 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5689 u8 led1_id; 5690 u8 led1_type; 5691 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 5692 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 5693 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 5694 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 5695 u8 led1_group_id; 5696 u8 unused_1; 5697 __le16 led1_state_caps; 5698 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 5699 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 5700 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 5701 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5702 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5703 __le16 led1_color_caps; 5704 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 5705 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5706 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5707 u8 led2_id; 5708 u8 led2_type; 5709 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 5710 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 5711 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 5712 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 5713 u8 led2_group_id; 5714 u8 unused_2; 5715 __le16 led2_state_caps; 5716 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 5717 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 5718 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 5719 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5720 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5721 __le16 led2_color_caps; 5722 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 5723 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5724 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5725 u8 led3_id; 5726 u8 led3_type; 5727 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 5728 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 5729 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 5730 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 5731 u8 led3_group_id; 5732 u8 unused_3; 5733 __le16 led3_state_caps; 5734 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 5735 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 5736 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 5737 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5738 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5739 __le16 led3_color_caps; 5740 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 5741 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5742 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5743 u8 unused_4[3]; 5744 u8 valid; 5745 }; 5746 5747 /* hwrm_port_mac_qcaps_input (size:192b/24B) */ 5748 struct hwrm_port_mac_qcaps_input { 5749 __le16 req_type; 5750 __le16 cmpl_ring; 5751 __le16 seq_id; 5752 __le16 target_id; 5753 __le64 resp_addr; 5754 __le16 port_id; 5755 u8 unused_0[6]; 5756 }; 5757 5758 /* hwrm_port_mac_qcaps_output (size:128b/16B) */ 5759 struct hwrm_port_mac_qcaps_output { 5760 __le16 error_code; 5761 __le16 req_type; 5762 __le16 seq_id; 5763 __le16 resp_len; 5764 u8 flags; 5765 #define PORT_MAC_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x1UL 5766 #define PORT_MAC_QCAPS_RESP_FLAGS_REMOTE_LPBK_SUPPORTED 0x2UL 5767 u8 unused_0[6]; 5768 u8 valid; 5769 }; 5770 5771 /* hwrm_queue_qportcfg_input (size:192b/24B) */ 5772 struct hwrm_queue_qportcfg_input { 5773 __le16 req_type; 5774 __le16 cmpl_ring; 5775 __le16 seq_id; 5776 __le16 target_id; 5777 __le64 resp_addr; 5778 __le32 flags; 5779 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 5780 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 5781 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 5782 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 5783 __le16 port_id; 5784 u8 drv_qmap_cap; 5785 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 5786 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 5787 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 5788 u8 unused_0; 5789 }; 5790 5791 /* hwrm_queue_qportcfg_output (size:1344b/168B) */ 5792 struct hwrm_queue_qportcfg_output { 5793 __le16 error_code; 5794 __le16 req_type; 5795 __le16 seq_id; 5796 __le16 resp_len; 5797 u8 max_configurable_queues; 5798 u8 max_configurable_lossless_queues; 5799 u8 queue_cfg_allowed; 5800 u8 queue_cfg_info; 5801 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 5802 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_USE_PROFILE_TYPE 0x2UL 5803 u8 queue_pfcenable_cfg_allowed; 5804 u8 queue_pri2cos_cfg_allowed; 5805 u8 queue_cos2bw_cfg_allowed; 5806 u8 queue_id0; 5807 u8 queue_id0_service_profile; 5808 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 5809 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 5810 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5811 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5812 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5813 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 5814 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 5815 u8 queue_id1; 5816 u8 queue_id1_service_profile; 5817 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 5818 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 5819 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5820 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5821 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5822 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 5823 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 5824 u8 queue_id2; 5825 u8 queue_id2_service_profile; 5826 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 5827 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 5828 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5829 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5830 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5831 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 5832 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 5833 u8 queue_id3; 5834 u8 queue_id3_service_profile; 5835 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 5836 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 5837 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5838 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5839 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5840 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 5841 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 5842 u8 queue_id4; 5843 u8 queue_id4_service_profile; 5844 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 5845 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 5846 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5847 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5848 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5849 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 5850 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 5851 u8 queue_id5; 5852 u8 queue_id5_service_profile; 5853 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 5854 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 5855 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5856 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5857 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5858 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 5859 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 5860 u8 queue_id6; 5861 u8 queue_id6_service_profile; 5862 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 5863 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 5864 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5865 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5866 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5867 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 5868 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 5869 u8 queue_id7; 5870 u8 queue_id7_service_profile; 5871 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 5872 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 5873 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5874 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5875 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5876 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 5877 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 5878 u8 queue_id0_service_profile_type; 5879 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5880 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC 0x2UL 5881 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP 0x4UL 5882 char qid0_name[16]; 5883 char qid1_name[16]; 5884 char qid2_name[16]; 5885 char qid3_name[16]; 5886 char qid4_name[16]; 5887 char qid5_name[16]; 5888 char qid6_name[16]; 5889 char qid7_name[16]; 5890 u8 queue_id1_service_profile_type; 5891 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5892 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC 0x2UL 5893 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP 0x4UL 5894 u8 queue_id2_service_profile_type; 5895 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5896 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC 0x2UL 5897 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP 0x4UL 5898 u8 queue_id3_service_profile_type; 5899 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5900 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC 0x2UL 5901 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP 0x4UL 5902 u8 queue_id4_service_profile_type; 5903 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5904 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC 0x2UL 5905 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP 0x4UL 5906 u8 queue_id5_service_profile_type; 5907 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5908 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC 0x2UL 5909 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP 0x4UL 5910 u8 queue_id6_service_profile_type; 5911 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5912 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC 0x2UL 5913 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP 0x4UL 5914 u8 queue_id7_service_profile_type; 5915 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5916 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC 0x2UL 5917 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP 0x4UL 5918 u8 valid; 5919 }; 5920 5921 /* hwrm_queue_qcfg_input (size:192b/24B) */ 5922 struct hwrm_queue_qcfg_input { 5923 __le16 req_type; 5924 __le16 cmpl_ring; 5925 __le16 seq_id; 5926 __le16 target_id; 5927 __le64 resp_addr; 5928 __le32 flags; 5929 #define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL 5930 #define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL 5931 #define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL 5932 #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX 5933 __le32 queue_id; 5934 }; 5935 5936 /* hwrm_queue_qcfg_output (size:128b/16B) */ 5937 struct hwrm_queue_qcfg_output { 5938 __le16 error_code; 5939 __le16 req_type; 5940 __le16 seq_id; 5941 __le16 resp_len; 5942 __le32 queue_len; 5943 u8 service_profile; 5944 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL 5945 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL 5946 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL 5947 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 5948 u8 queue_cfg_info; 5949 #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 5950 u8 unused_0; 5951 u8 valid; 5952 }; 5953 5954 /* hwrm_queue_cfg_input (size:320b/40B) */ 5955 struct hwrm_queue_cfg_input { 5956 __le16 req_type; 5957 __le16 cmpl_ring; 5958 __le16 seq_id; 5959 __le16 target_id; 5960 __le64 resp_addr; 5961 __le32 flags; 5962 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 5963 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 5964 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 5965 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 5966 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 5967 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 5968 __le32 enables; 5969 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 5970 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 5971 __le32 queue_id; 5972 __le32 dflt_len; 5973 u8 service_profile; 5974 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 5975 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 5976 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 5977 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 5978 u8 unused_0[7]; 5979 }; 5980 5981 /* hwrm_queue_cfg_output (size:128b/16B) */ 5982 struct hwrm_queue_cfg_output { 5983 __le16 error_code; 5984 __le16 req_type; 5985 __le16 seq_id; 5986 __le16 resp_len; 5987 u8 unused_0[7]; 5988 u8 valid; 5989 }; 5990 5991 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 5992 struct hwrm_queue_pfcenable_qcfg_input { 5993 __le16 req_type; 5994 __le16 cmpl_ring; 5995 __le16 seq_id; 5996 __le16 target_id; 5997 __le64 resp_addr; 5998 __le16 port_id; 5999 u8 unused_0[6]; 6000 }; 6001 6002 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 6003 struct hwrm_queue_pfcenable_qcfg_output { 6004 __le16 error_code; 6005 __le16 req_type; 6006 __le16 seq_id; 6007 __le16 resp_len; 6008 __le32 flags; 6009 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 6010 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 6011 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 6012 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 6013 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 6014 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 6015 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 6016 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 6017 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 6018 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 6019 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 6020 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 6021 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 6022 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 6023 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 6024 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 6025 u8 unused_0[3]; 6026 u8 valid; 6027 }; 6028 6029 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 6030 struct hwrm_queue_pfcenable_cfg_input { 6031 __le16 req_type; 6032 __le16 cmpl_ring; 6033 __le16 seq_id; 6034 __le16 target_id; 6035 __le64 resp_addr; 6036 __le32 flags; 6037 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 6038 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 6039 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 6040 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 6041 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 6042 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 6043 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 6044 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 6045 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 6046 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 6047 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 6048 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 6049 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 6050 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 6051 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 6052 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 6053 __le16 port_id; 6054 u8 unused_0[2]; 6055 }; 6056 6057 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 6058 struct hwrm_queue_pfcenable_cfg_output { 6059 __le16 error_code; 6060 __le16 req_type; 6061 __le16 seq_id; 6062 __le16 resp_len; 6063 u8 unused_0[7]; 6064 u8 valid; 6065 }; 6066 6067 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 6068 struct hwrm_queue_pri2cos_qcfg_input { 6069 __le16 req_type; 6070 __le16 cmpl_ring; 6071 __le16 seq_id; 6072 __le16 target_id; 6073 __le64 resp_addr; 6074 __le32 flags; 6075 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 6076 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 6077 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 6078 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 6079 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 6080 u8 port_id; 6081 u8 unused_0[3]; 6082 }; 6083 6084 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 6085 struct hwrm_queue_pri2cos_qcfg_output { 6086 __le16 error_code; 6087 __le16 req_type; 6088 __le16 seq_id; 6089 __le16 resp_len; 6090 u8 pri0_cos_queue_id; 6091 u8 pri1_cos_queue_id; 6092 u8 pri2_cos_queue_id; 6093 u8 pri3_cos_queue_id; 6094 u8 pri4_cos_queue_id; 6095 u8 pri5_cos_queue_id; 6096 u8 pri6_cos_queue_id; 6097 u8 pri7_cos_queue_id; 6098 u8 queue_cfg_info; 6099 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 6100 u8 unused_0[6]; 6101 u8 valid; 6102 }; 6103 6104 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 6105 struct hwrm_queue_pri2cos_cfg_input { 6106 __le16 req_type; 6107 __le16 cmpl_ring; 6108 __le16 seq_id; 6109 __le16 target_id; 6110 __le64 resp_addr; 6111 __le32 flags; 6112 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 6113 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 6114 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 6115 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 6116 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 6117 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 6118 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 6119 __le32 enables; 6120 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 6121 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 6122 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 6123 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 6124 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 6125 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 6126 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 6127 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 6128 u8 port_id; 6129 u8 pri0_cos_queue_id; 6130 u8 pri1_cos_queue_id; 6131 u8 pri2_cos_queue_id; 6132 u8 pri3_cos_queue_id; 6133 u8 pri4_cos_queue_id; 6134 u8 pri5_cos_queue_id; 6135 u8 pri6_cos_queue_id; 6136 u8 pri7_cos_queue_id; 6137 u8 unused_0[7]; 6138 }; 6139 6140 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 6141 struct hwrm_queue_pri2cos_cfg_output { 6142 __le16 error_code; 6143 __le16 req_type; 6144 __le16 seq_id; 6145 __le16 resp_len; 6146 u8 unused_0[7]; 6147 u8 valid; 6148 }; 6149 6150 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 6151 struct hwrm_queue_cos2bw_qcfg_input { 6152 __le16 req_type; 6153 __le16 cmpl_ring; 6154 __le16 seq_id; 6155 __le16 target_id; 6156 __le64 resp_addr; 6157 __le16 port_id; 6158 u8 unused_0[6]; 6159 }; 6160 6161 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 6162 struct hwrm_queue_cos2bw_qcfg_output { 6163 __le16 error_code; 6164 __le16 req_type; 6165 __le16 seq_id; 6166 __le16 resp_len; 6167 u8 queue_id0; 6168 u8 unused_0; 6169 __le16 unused_1; 6170 __le32 queue_id0_min_bw; 6171 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6172 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 6173 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 6174 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 6175 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 6176 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 6177 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6178 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 6179 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6180 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6181 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6182 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6183 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6184 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6185 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 6186 __le32 queue_id0_max_bw; 6187 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6188 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 6189 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 6190 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 6191 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 6192 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 6193 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6194 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 6195 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6196 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6197 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6198 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6199 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6200 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6201 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 6202 u8 queue_id0_tsa_assign; 6203 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 6204 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 6205 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6206 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 6207 u8 queue_id0_pri_lvl; 6208 u8 queue_id0_bw_weight; 6209 struct { 6210 u8 queue_id; 6211 __le32 queue_id_min_bw; 6212 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6213 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_SFT 0 6214 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE 0x10000000UL 6215 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BITS (0x0UL << 28) 6216 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BYTES (0x1UL << 28) 6217 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BYTES 6218 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6219 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_SFT 29 6220 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6221 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6222 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6223 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6224 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6225 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6226 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID 6227 __le32 queue_id_max_bw; 6228 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6229 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_SFT 0 6230 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE 0x10000000UL 6231 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BITS (0x0UL << 28) 6232 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BYTES (0x1UL << 28) 6233 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BYTES 6234 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6235 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_SFT 29 6236 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6237 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6238 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6239 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6240 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6241 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6242 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID 6243 u8 queue_id_tsa_assign; 6244 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_SP 0x0UL 6245 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_ETS 0x1UL 6246 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6247 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_RESERVED_LAST 0xffUL 6248 u8 queue_id_pri_lvl; 6249 u8 queue_id_bw_weight; 6250 } __packed cfg[7]; 6251 u8 unused_2[4]; 6252 u8 valid; 6253 }; 6254 6255 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 6256 struct hwrm_queue_cos2bw_cfg_input { 6257 __le16 req_type; 6258 __le16 cmpl_ring; 6259 __le16 seq_id; 6260 __le16 target_id; 6261 __le64 resp_addr; 6262 __le32 flags; 6263 __le32 enables; 6264 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 6265 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 6266 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 6267 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 6268 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 6269 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 6270 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 6271 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 6272 __le16 port_id; 6273 u8 queue_id0; 6274 u8 unused_0; 6275 __le32 queue_id0_min_bw; 6276 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6277 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 6278 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 6279 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 6280 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 6281 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 6282 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6283 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 6284 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6285 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6286 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6287 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6288 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6289 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6290 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 6291 __le32 queue_id0_max_bw; 6292 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6293 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 6294 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 6295 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 6296 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 6297 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 6298 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6299 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 6300 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6301 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6302 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6303 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6304 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6305 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6306 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 6307 u8 queue_id0_tsa_assign; 6308 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 6309 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 6310 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6311 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 6312 u8 queue_id0_pri_lvl; 6313 u8 queue_id0_bw_weight; 6314 struct { 6315 u8 queue_id; 6316 __le32 queue_id_min_bw; 6317 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6318 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_SFT 0 6319 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE 0x10000000UL 6320 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BITS (0x0UL << 28) 6321 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BYTES (0x1UL << 28) 6322 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BYTES 6323 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6324 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_SFT 29 6325 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6326 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6327 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6328 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6329 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6330 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6331 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID 6332 __le32 queue_id_max_bw; 6333 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6334 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_SFT 0 6335 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE 0x10000000UL 6336 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BITS (0x0UL << 28) 6337 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BYTES (0x1UL << 28) 6338 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BYTES 6339 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6340 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_SFT 29 6341 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6342 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6343 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6344 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6345 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6346 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6347 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID 6348 u8 queue_id_tsa_assign; 6349 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_SP 0x0UL 6350 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_ETS 0x1UL 6351 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6352 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_RESERVED_LAST 0xffUL 6353 u8 queue_id_pri_lvl; 6354 u8 queue_id_bw_weight; 6355 } __packed cfg[7]; 6356 u8 unused_1[5]; 6357 }; 6358 6359 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 6360 struct hwrm_queue_cos2bw_cfg_output { 6361 __le16 error_code; 6362 __le16 req_type; 6363 __le16 seq_id; 6364 __le16 resp_len; 6365 u8 unused_0[7]; 6366 u8 valid; 6367 }; 6368 6369 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 6370 struct hwrm_queue_dscp_qcaps_input { 6371 __le16 req_type; 6372 __le16 cmpl_ring; 6373 __le16 seq_id; 6374 __le16 target_id; 6375 __le64 resp_addr; 6376 u8 port_id; 6377 u8 unused_0[7]; 6378 }; 6379 6380 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 6381 struct hwrm_queue_dscp_qcaps_output { 6382 __le16 error_code; 6383 __le16 req_type; 6384 __le16 seq_id; 6385 __le16 resp_len; 6386 u8 num_dscp_bits; 6387 u8 unused_0; 6388 __le16 max_entries; 6389 u8 unused_1[3]; 6390 u8 valid; 6391 }; 6392 6393 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 6394 struct hwrm_queue_dscp2pri_qcfg_input { 6395 __le16 req_type; 6396 __le16 cmpl_ring; 6397 __le16 seq_id; 6398 __le16 target_id; 6399 __le64 resp_addr; 6400 __le64 dest_data_addr; 6401 u8 port_id; 6402 u8 unused_0; 6403 __le16 dest_data_buffer_size; 6404 u8 unused_1[4]; 6405 }; 6406 6407 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 6408 struct hwrm_queue_dscp2pri_qcfg_output { 6409 __le16 error_code; 6410 __le16 req_type; 6411 __le16 seq_id; 6412 __le16 resp_len; 6413 __le16 entry_cnt; 6414 u8 default_pri; 6415 u8 unused_0[4]; 6416 u8 valid; 6417 }; 6418 6419 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 6420 struct hwrm_queue_dscp2pri_cfg_input { 6421 __le16 req_type; 6422 __le16 cmpl_ring; 6423 __le16 seq_id; 6424 __le16 target_id; 6425 __le64 resp_addr; 6426 __le64 src_data_addr; 6427 __le32 flags; 6428 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 6429 __le32 enables; 6430 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 6431 u8 port_id; 6432 u8 default_pri; 6433 __le16 entry_cnt; 6434 u8 unused_0[4]; 6435 }; 6436 6437 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 6438 struct hwrm_queue_dscp2pri_cfg_output { 6439 __le16 error_code; 6440 __le16 req_type; 6441 __le16 seq_id; 6442 __le16 resp_len; 6443 u8 unused_0[7]; 6444 u8 valid; 6445 }; 6446 6447 /* hwrm_vnic_alloc_input (size:192b/24B) */ 6448 struct hwrm_vnic_alloc_input { 6449 __le16 req_type; 6450 __le16 cmpl_ring; 6451 __le16 seq_id; 6452 __le16 target_id; 6453 __le64 resp_addr; 6454 __le32 flags; 6455 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 6456 #define VNIC_ALLOC_REQ_FLAGS_VIRTIO_NET_FID_VALID 0x2UL 6457 __le16 virtio_net_fid; 6458 u8 unused_0[2]; 6459 }; 6460 6461 /* hwrm_vnic_alloc_output (size:128b/16B) */ 6462 struct hwrm_vnic_alloc_output { 6463 __le16 error_code; 6464 __le16 req_type; 6465 __le16 seq_id; 6466 __le16 resp_len; 6467 __le32 vnic_id; 6468 u8 unused_0[3]; 6469 u8 valid; 6470 }; 6471 6472 /* hwrm_vnic_free_input (size:192b/24B) */ 6473 struct hwrm_vnic_free_input { 6474 __le16 req_type; 6475 __le16 cmpl_ring; 6476 __le16 seq_id; 6477 __le16 target_id; 6478 __le64 resp_addr; 6479 __le32 vnic_id; 6480 u8 unused_0[4]; 6481 }; 6482 6483 /* hwrm_vnic_free_output (size:128b/16B) */ 6484 struct hwrm_vnic_free_output { 6485 __le16 error_code; 6486 __le16 req_type; 6487 __le16 seq_id; 6488 __le16 resp_len; 6489 u8 unused_0[7]; 6490 u8 valid; 6491 }; 6492 6493 /* hwrm_vnic_cfg_input (size:384b/48B) */ 6494 struct hwrm_vnic_cfg_input { 6495 __le16 req_type; 6496 __le16 cmpl_ring; 6497 __le16 seq_id; 6498 __le16 target_id; 6499 __le64 resp_addr; 6500 __le32 flags; 6501 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 6502 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 6503 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 6504 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 6505 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 6506 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 6507 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 6508 #define VNIC_CFG_REQ_FLAGS_PORTCOS_MAPPING_MODE 0x80UL 6509 __le32 enables; 6510 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 6511 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 6512 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 6513 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 6514 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 6515 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 6516 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 6517 #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL 6518 #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL 6519 #define VNIC_CFG_REQ_ENABLES_L2_CQE_MODE 0x200UL 6520 __le16 vnic_id; 6521 __le16 dflt_ring_grp; 6522 __le16 rss_rule; 6523 __le16 cos_rule; 6524 __le16 lb_rule; 6525 __le16 mru; 6526 __le16 default_rx_ring_id; 6527 __le16 default_cmpl_ring_id; 6528 __le16 queue_id; 6529 u8 rx_csum_v2_mode; 6530 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL 6531 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK 0x1UL 6532 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 0x2UL 6533 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 6534 u8 l2_cqe_mode; 6535 #define VNIC_CFG_REQ_L2_CQE_MODE_DEFAULT 0x0UL 6536 #define VNIC_CFG_REQ_L2_CQE_MODE_COMPRESSED 0x1UL 6537 #define VNIC_CFG_REQ_L2_CQE_MODE_MIXED 0x2UL 6538 #define VNIC_CFG_REQ_L2_CQE_MODE_LAST VNIC_CFG_REQ_L2_CQE_MODE_MIXED 6539 u8 unused0[4]; 6540 }; 6541 6542 /* hwrm_vnic_cfg_output (size:128b/16B) */ 6543 struct hwrm_vnic_cfg_output { 6544 __le16 error_code; 6545 __le16 req_type; 6546 __le16 seq_id; 6547 __le16 resp_len; 6548 u8 unused_0[7]; 6549 u8 valid; 6550 }; 6551 6552 /* hwrm_vnic_qcaps_input (size:192b/24B) */ 6553 struct hwrm_vnic_qcaps_input { 6554 __le16 req_type; 6555 __le16 cmpl_ring; 6556 __le16 seq_id; 6557 __le16 target_id; 6558 __le64 resp_addr; 6559 __le32 enables; 6560 u8 unused_0[4]; 6561 }; 6562 6563 /* hwrm_vnic_qcaps_output (size:192b/24B) */ 6564 struct hwrm_vnic_qcaps_output { 6565 __le16 error_code; 6566 __le16 req_type; 6567 __le16 seq_id; 6568 __le16 resp_len; 6569 __le16 mru; 6570 u8 unused_0[2]; 6571 __le32 flags; 6572 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 6573 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 6574 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 6575 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 6576 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 6577 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 6578 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 6579 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 6580 #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL 6581 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL 6582 #define VNIC_QCAPS_RESP_FLAGS_VNIC_STATE_CAP 0x400UL 6583 #define VNIC_QCAPS_RESP_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP 0x800UL 6584 #define VNIC_QCAPS_RESP_FLAGS_METADATA_FORMAT_CAP 0x1000UL 6585 #define VNIC_QCAPS_RESP_FLAGS_RSS_STRICT_HASH_TYPE_CAP 0x2000UL 6586 #define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP 0x4000UL 6587 #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CAP 0x8000UL 6588 #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_XOR_CAP 0x10000UL 6589 #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CHKSM_CAP 0x20000UL 6590 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPV6_FLOW_LABEL_CAP 0x40000UL 6591 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V3_CAP 0x80000UL 6592 #define VNIC_QCAPS_RESP_FLAGS_L2_CQE_MODE_CAP 0x100000UL 6593 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP 0x200000UL 6594 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP 0x400000UL 6595 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP 0x800000UL 6596 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP 0x1000000UL 6597 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP 0x2000000UL 6598 #define VNIC_QCAPS_RESP_FLAGS_PORTCOS_MAPPING_MODE 0x4000000UL 6599 #define VNIC_QCAPS_RESP_FLAGS_RSS_PROF_TCAM_MODE_ENABLED 0x8000000UL 6600 #define VNIC_QCAPS_RESP_FLAGS_VNIC_RSS_HASH_MODE_CAP 0x10000000UL 6601 #define VNIC_QCAPS_RESP_FLAGS_HW_TUNNEL_TPA_CAP 0x20000000UL 6602 __le16 max_aggs_supported; 6603 u8 unused_1[5]; 6604 u8 valid; 6605 }; 6606 6607 /* hwrm_vnic_tpa_cfg_input (size:384b/48B) */ 6608 struct hwrm_vnic_tpa_cfg_input { 6609 __le16 req_type; 6610 __le16 cmpl_ring; 6611 __le16 seq_id; 6612 __le16 target_id; 6613 __le64 resp_addr; 6614 __le32 flags; 6615 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 6616 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 6617 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 6618 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 6619 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 6620 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 6621 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 6622 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 6623 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL 6624 __le32 enables; 6625 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 6626 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 6627 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 6628 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 6629 #define VNIC_TPA_CFG_REQ_ENABLES_TNL_TPA_EN 0x10UL 6630 __le16 vnic_id; 6631 __le16 max_agg_segs; 6632 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 6633 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 6634 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 6635 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 6636 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 6637 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 6638 __le16 max_aggs; 6639 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 6640 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 6641 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 6642 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 6643 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 6644 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 6645 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 6646 u8 unused_0[2]; 6647 __le32 max_agg_timer; 6648 __le32 min_agg_len; 6649 __le32 tnl_tpa_en_bitmap; 6650 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN 0x1UL 6651 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GENEVE 0x2UL 6652 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_NVGRE 0x4UL 6653 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GRE 0x8UL 6654 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_IPV4 0x10UL 6655 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_IPV6 0x20UL 6656 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN_GPE 0x40UL 6657 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN_CUST1 0x80UL 6658 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GRE_CUST1 0x100UL 6659 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR1 0x200UL 6660 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR2 0x400UL 6661 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR3 0x800UL 6662 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR4 0x1000UL 6663 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR5 0x2000UL 6664 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR6 0x4000UL 6665 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR7 0x8000UL 6666 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR8 0x10000UL 6667 u8 unused_1[4]; 6668 }; 6669 6670 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 6671 struct hwrm_vnic_tpa_cfg_output { 6672 __le16 error_code; 6673 __le16 req_type; 6674 __le16 seq_id; 6675 __le16 resp_len; 6676 u8 unused_0[7]; 6677 u8 valid; 6678 }; 6679 6680 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 6681 struct hwrm_vnic_tpa_qcfg_input { 6682 __le16 req_type; 6683 __le16 cmpl_ring; 6684 __le16 seq_id; 6685 __le16 target_id; 6686 __le64 resp_addr; 6687 __le16 vnic_id; 6688 u8 unused_0[6]; 6689 }; 6690 6691 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 6692 struct hwrm_vnic_tpa_qcfg_output { 6693 __le16 error_code; 6694 __le16 req_type; 6695 __le16 seq_id; 6696 __le16 resp_len; 6697 __le32 flags; 6698 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 6699 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 6700 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 6701 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 6702 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 6703 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 6704 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 6705 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 6706 __le16 max_agg_segs; 6707 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 6708 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 6709 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 6710 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 6711 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 6712 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 6713 __le16 max_aggs; 6714 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 6715 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 6716 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 6717 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 6718 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 6719 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 6720 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 6721 __le32 max_agg_timer; 6722 __le32 min_agg_len; 6723 __le32 tnl_tpa_en_bitmap; 6724 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN 0x1UL 6725 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GENEVE 0x2UL 6726 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_NVGRE 0x4UL 6727 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GRE 0x8UL 6728 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_IPV4 0x10UL 6729 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_IPV6 0x20UL 6730 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN_GPE 0x40UL 6731 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN_CUST1 0x80UL 6732 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GRE_CUST1 0x100UL 6733 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR1 0x200UL 6734 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR2 0x400UL 6735 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR3 0x800UL 6736 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR4 0x1000UL 6737 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR5 0x2000UL 6738 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR6 0x4000UL 6739 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR7 0x8000UL 6740 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR8 0x10000UL 6741 u8 unused_0[3]; 6742 u8 valid; 6743 }; 6744 6745 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 6746 struct hwrm_vnic_rss_cfg_input { 6747 __le16 req_type; 6748 __le16 cmpl_ring; 6749 __le16 seq_id; 6750 __le16 target_id; 6751 __le64 resp_addr; 6752 __le32 hash_type; 6753 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 6754 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 6755 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 6756 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 6757 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 6758 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 6759 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL 0x40UL 6760 #define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 0x80UL 6761 #define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4 0x100UL 6762 #define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 0x200UL 6763 #define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6 0x400UL 6764 __le16 vnic_id; 6765 u8 ring_table_pair_index; 6766 u8 hash_mode_flags; 6767 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 6768 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 6769 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 6770 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 6771 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 6772 __le64 ring_grp_tbl_addr; 6773 __le64 hash_key_tbl_addr; 6774 __le16 rss_ctx_idx; 6775 u8 flags; 6776 #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_INCLUDE 0x1UL 6777 #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_EXCLUDE 0x2UL 6778 #define VNIC_RSS_CFG_REQ_FLAGS_IPSEC_HASH_TYPE_CFG_SUPPORT 0x4UL 6779 u8 ring_select_mode; 6780 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ 0x0UL 6781 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_XOR 0x1UL 6782 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL 6783 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_LAST VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 6784 u8 unused_1[4]; 6785 }; 6786 6787 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 6788 struct hwrm_vnic_rss_cfg_output { 6789 __le16 error_code; 6790 __le16 req_type; 6791 __le16 seq_id; 6792 __le16 resp_len; 6793 u8 unused_0[7]; 6794 u8 valid; 6795 }; 6796 6797 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ 6798 struct hwrm_vnic_rss_cfg_cmd_err { 6799 u8 code; 6800 #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 6801 #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL 6802 #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 6803 u8 unused_0[7]; 6804 }; 6805 6806 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */ 6807 struct hwrm_vnic_rss_qcfg_input { 6808 __le16 req_type; 6809 __le16 cmpl_ring; 6810 __le16 seq_id; 6811 __le16 target_id; 6812 __le64 resp_addr; 6813 __le16 rss_ctx_idx; 6814 __le16 vnic_id; 6815 u8 unused_0[4]; 6816 }; 6817 6818 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */ 6819 struct hwrm_vnic_rss_qcfg_output { 6820 __le16 error_code; 6821 __le16 req_type; 6822 __le16 seq_id; 6823 __le16 resp_len; 6824 __le32 hash_type; 6825 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV4 0x1UL 6826 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV4 0x2UL 6827 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV4 0x4UL 6828 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6 0x8UL 6829 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV6 0x10UL 6830 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV6 0x20UL 6831 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6_FLOW_LABEL 0x40UL 6832 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV4 0x80UL 6833 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV4 0x100UL 6834 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV6 0x200UL 6835 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV6 0x400UL 6836 u8 unused_0[4]; 6837 __le32 hash_key[10]; 6838 u8 hash_mode_flags; 6839 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_DEFAULT 0x1UL 6840 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 6841 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 6842 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 6843 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 6844 u8 ring_select_mode; 6845 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ 0x0UL 6846 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_XOR 0x1UL 6847 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL 6848 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_LAST VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 6849 u8 unused_1[5]; 6850 u8 valid; 6851 }; 6852 6853 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 6854 struct hwrm_vnic_plcmodes_cfg_input { 6855 __le16 req_type; 6856 __le16 cmpl_ring; 6857 __le16 seq_id; 6858 __le16 target_id; 6859 __le64 resp_addr; 6860 __le32 flags; 6861 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 6862 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 6863 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 6864 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 6865 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 6866 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 6867 #define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT 0x40UL 6868 __le32 enables; 6869 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 6870 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 6871 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 6872 #define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID 0x8UL 6873 __le32 vnic_id; 6874 __le16 jumbo_thresh; 6875 __le16 hds_offset; 6876 __le16 hds_threshold; 6877 __le16 max_bds; 6878 u8 unused_0[4]; 6879 }; 6880 6881 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 6882 struct hwrm_vnic_plcmodes_cfg_output { 6883 __le16 error_code; 6884 __le16 req_type; 6885 __le16 seq_id; 6886 __le16 resp_len; 6887 u8 unused_0[7]; 6888 u8 valid; 6889 }; 6890 6891 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 6892 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 6893 __le16 req_type; 6894 __le16 cmpl_ring; 6895 __le16 seq_id; 6896 __le16 target_id; 6897 __le64 resp_addr; 6898 }; 6899 6900 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 6901 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 6902 __le16 error_code; 6903 __le16 req_type; 6904 __le16 seq_id; 6905 __le16 resp_len; 6906 __le16 rss_cos_lb_ctx_id; 6907 u8 unused_0[5]; 6908 u8 valid; 6909 }; 6910 6911 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 6912 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 6913 __le16 req_type; 6914 __le16 cmpl_ring; 6915 __le16 seq_id; 6916 __le16 target_id; 6917 __le64 resp_addr; 6918 __le16 rss_cos_lb_ctx_id; 6919 u8 unused_0[6]; 6920 }; 6921 6922 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 6923 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 6924 __le16 error_code; 6925 __le16 req_type; 6926 __le16 seq_id; 6927 __le16 resp_len; 6928 u8 unused_0[7]; 6929 u8 valid; 6930 }; 6931 6932 /* hwrm_ring_alloc_input (size:704b/88B) */ 6933 struct hwrm_ring_alloc_input { 6934 __le16 req_type; 6935 __le16 cmpl_ring; 6936 __le16 seq_id; 6937 __le16 target_id; 6938 __le64 resp_addr; 6939 __le32 enables; 6940 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 6941 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 6942 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 6943 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 6944 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 6945 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 6946 #define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL 6947 #define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL 6948 #define RING_ALLOC_REQ_ENABLES_STEERING_TAG_VALID 0x800UL 6949 u8 ring_type; 6950 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 6951 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 6952 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 6953 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 6954 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 6955 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 6956 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 6957 u8 cmpl_coal_cnt; 6958 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_OFF 0x0UL 6959 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_4 0x1UL 6960 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_8 0x2UL 6961 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_12 0x3UL 6962 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_16 0x4UL 6963 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_24 0x5UL 6964 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_32 0x6UL 6965 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_48 0x7UL 6966 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_64 0x8UL 6967 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_96 0x9UL 6968 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_128 0xaUL 6969 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_192 0xbUL 6970 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_256 0xcUL 6971 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_320 0xdUL 6972 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_384 0xeUL 6973 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 0xfUL 6974 #define RING_ALLOC_REQ_CMPL_COAL_CNT_LAST RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 6975 __le16 flags; 6976 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 6977 #define RING_ALLOC_REQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION 0x2UL 6978 #define RING_ALLOC_REQ_FLAGS_NQ_DBR_PACING 0x4UL 6979 #define RING_ALLOC_REQ_FLAGS_TX_PKT_TS_CMPL_ENABLE 0x8UL 6980 __le64 page_tbl_addr; 6981 __le32 fbo; 6982 u8 page_size; 6983 u8 page_tbl_depth; 6984 __le16 schq_id; 6985 __le32 length; 6986 __le16 logical_id; 6987 __le16 cmpl_ring_id; 6988 __le16 queue_id; 6989 __le16 rx_buf_size; 6990 __le16 rx_ring_id; 6991 __le16 nq_ring_id; 6992 __le16 ring_arb_cfg; 6993 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 6994 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 6995 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 6996 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 6997 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 6998 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 6999 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 7000 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 7001 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 7002 __le16 steering_tag; 7003 __le32 reserved3; 7004 __le32 stat_ctx_id; 7005 __le32 reserved4; 7006 __le32 max_bw; 7007 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 7008 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 7009 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 7010 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 7011 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 7012 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 7013 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 7014 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 7015 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 7016 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 7017 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 7018 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 7019 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 7020 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 7021 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 7022 u8 int_mode; 7023 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 7024 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 7025 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 7026 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 7027 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 7028 u8 mpc_chnls_type; 7029 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE 0x0UL 7030 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE 0x1UL 7031 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA 0x2UL 7032 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL 7033 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL 7034 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 7035 u8 unused_4[2]; 7036 __le64 cq_handle; 7037 }; 7038 7039 /* hwrm_ring_alloc_output (size:128b/16B) */ 7040 struct hwrm_ring_alloc_output { 7041 __le16 error_code; 7042 __le16 req_type; 7043 __le16 seq_id; 7044 __le16 resp_len; 7045 __le16 ring_id; 7046 __le16 logical_ring_id; 7047 u8 push_buffer_index; 7048 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 7049 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 7050 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_LAST RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 7051 u8 unused_0[2]; 7052 u8 valid; 7053 }; 7054 7055 /* hwrm_ring_free_input (size:256b/32B) */ 7056 struct hwrm_ring_free_input { 7057 __le16 req_type; 7058 __le16 cmpl_ring; 7059 __le16 seq_id; 7060 __le16 target_id; 7061 __le64 resp_addr; 7062 u8 ring_type; 7063 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 7064 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 7065 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 7066 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 7067 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 7068 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 7069 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 7070 u8 flags; 7071 #define RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 0x1UL 7072 #define RING_FREE_REQ_FLAGS_LAST RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 7073 __le16 ring_id; 7074 __le32 prod_idx; 7075 __le32 opaque; 7076 __le32 unused_1; 7077 }; 7078 7079 /* hwrm_ring_free_output (size:128b/16B) */ 7080 struct hwrm_ring_free_output { 7081 __le16 error_code; 7082 __le16 req_type; 7083 __le16 seq_id; 7084 __le16 resp_len; 7085 u8 unused_0[7]; 7086 u8 valid; 7087 }; 7088 7089 /* hwrm_ring_reset_input (size:192b/24B) */ 7090 struct hwrm_ring_reset_input { 7091 __le16 req_type; 7092 __le16 cmpl_ring; 7093 __le16 seq_id; 7094 __le16 target_id; 7095 __le64 resp_addr; 7096 u8 ring_type; 7097 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 7098 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 7099 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 7100 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 7101 #define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL 7102 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_RX_RING_GRP 7103 u8 unused_0; 7104 __le16 ring_id; 7105 u8 unused_1[4]; 7106 }; 7107 7108 /* hwrm_ring_reset_output (size:128b/16B) */ 7109 struct hwrm_ring_reset_output { 7110 __le16 error_code; 7111 __le16 req_type; 7112 __le16 seq_id; 7113 __le16 resp_len; 7114 u8 push_buffer_index; 7115 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 7116 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 7117 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_LAST RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 7118 u8 unused_0[3]; 7119 u8 consumer_idx[3]; 7120 u8 valid; 7121 }; 7122 7123 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 7124 struct hwrm_ring_aggint_qcaps_input { 7125 __le16 req_type; 7126 __le16 cmpl_ring; 7127 __le16 seq_id; 7128 __le16 target_id; 7129 __le64 resp_addr; 7130 }; 7131 7132 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 7133 struct hwrm_ring_aggint_qcaps_output { 7134 __le16 error_code; 7135 __le16 req_type; 7136 __le16 seq_id; 7137 __le16 resp_len; 7138 __le32 cmpl_params; 7139 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 7140 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 7141 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 7142 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 7143 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 7144 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 7145 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 7146 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 7147 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 7148 __le32 nq_params; 7149 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 7150 __le16 num_cmpl_dma_aggr_min; 7151 __le16 num_cmpl_dma_aggr_max; 7152 __le16 num_cmpl_dma_aggr_during_int_min; 7153 __le16 num_cmpl_dma_aggr_during_int_max; 7154 __le16 cmpl_aggr_dma_tmr_min; 7155 __le16 cmpl_aggr_dma_tmr_max; 7156 __le16 cmpl_aggr_dma_tmr_during_int_min; 7157 __le16 cmpl_aggr_dma_tmr_during_int_max; 7158 __le16 int_lat_tmr_min_min; 7159 __le16 int_lat_tmr_min_max; 7160 __le16 int_lat_tmr_max_min; 7161 __le16 int_lat_tmr_max_max; 7162 __le16 num_cmpl_aggr_int_min; 7163 __le16 num_cmpl_aggr_int_max; 7164 __le16 timer_units; 7165 u8 unused_0[1]; 7166 u8 valid; 7167 }; 7168 7169 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 7170 struct hwrm_ring_cmpl_ring_qaggint_params_input { 7171 __le16 req_type; 7172 __le16 cmpl_ring; 7173 __le16 seq_id; 7174 __le16 target_id; 7175 __le64 resp_addr; 7176 __le16 ring_id; 7177 __le16 flags; 7178 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL 7179 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0 7180 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 7181 u8 unused_0[4]; 7182 }; 7183 7184 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 7185 struct hwrm_ring_cmpl_ring_qaggint_params_output { 7186 __le16 error_code; 7187 __le16 req_type; 7188 __le16 seq_id; 7189 __le16 resp_len; 7190 __le16 flags; 7191 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 7192 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 7193 __le16 num_cmpl_dma_aggr; 7194 __le16 num_cmpl_dma_aggr_during_int; 7195 __le16 cmpl_aggr_dma_tmr; 7196 __le16 cmpl_aggr_dma_tmr_during_int; 7197 __le16 int_lat_tmr_min; 7198 __le16 int_lat_tmr_max; 7199 __le16 num_cmpl_aggr_int; 7200 u8 unused_0[7]; 7201 u8 valid; 7202 }; 7203 7204 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 7205 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 7206 __le16 req_type; 7207 __le16 cmpl_ring; 7208 __le16 seq_id; 7209 __le16 target_id; 7210 __le64 resp_addr; 7211 __le16 ring_id; 7212 __le16 flags; 7213 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 7214 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 7215 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 7216 __le16 num_cmpl_dma_aggr; 7217 __le16 num_cmpl_dma_aggr_during_int; 7218 __le16 cmpl_aggr_dma_tmr; 7219 __le16 cmpl_aggr_dma_tmr_during_int; 7220 __le16 int_lat_tmr_min; 7221 __le16 int_lat_tmr_max; 7222 __le16 num_cmpl_aggr_int; 7223 __le16 enables; 7224 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 7225 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 7226 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 7227 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 7228 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 7229 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 7230 u8 unused_0[4]; 7231 }; 7232 7233 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 7234 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 7235 __le16 error_code; 7236 __le16 req_type; 7237 __le16 seq_id; 7238 __le16 resp_len; 7239 u8 unused_0[7]; 7240 u8 valid; 7241 }; 7242 7243 /* hwrm_ring_grp_alloc_input (size:192b/24B) */ 7244 struct hwrm_ring_grp_alloc_input { 7245 __le16 req_type; 7246 __le16 cmpl_ring; 7247 __le16 seq_id; 7248 __le16 target_id; 7249 __le64 resp_addr; 7250 __le16 cr; 7251 __le16 rr; 7252 __le16 ar; 7253 __le16 sc; 7254 }; 7255 7256 /* hwrm_ring_grp_alloc_output (size:128b/16B) */ 7257 struct hwrm_ring_grp_alloc_output { 7258 __le16 error_code; 7259 __le16 req_type; 7260 __le16 seq_id; 7261 __le16 resp_len; 7262 __le32 ring_group_id; 7263 u8 unused_0[3]; 7264 u8 valid; 7265 }; 7266 7267 /* hwrm_ring_grp_free_input (size:192b/24B) */ 7268 struct hwrm_ring_grp_free_input { 7269 __le16 req_type; 7270 __le16 cmpl_ring; 7271 __le16 seq_id; 7272 __le16 target_id; 7273 __le64 resp_addr; 7274 __le32 ring_group_id; 7275 u8 unused_0[4]; 7276 }; 7277 7278 /* hwrm_ring_grp_free_output (size:128b/16B) */ 7279 struct hwrm_ring_grp_free_output { 7280 __le16 error_code; 7281 __le16 req_type; 7282 __le16 seq_id; 7283 __le16 resp_len; 7284 u8 unused_0[7]; 7285 u8 valid; 7286 }; 7287 7288 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL 7289 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL 7290 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL 7291 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL 7292 7293 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 7294 struct hwrm_cfa_l2_filter_alloc_input { 7295 __le16 req_type; 7296 __le16 cmpl_ring; 7297 __le16 seq_id; 7298 __le16 target_id; 7299 __le64 resp_addr; 7300 __le32 flags; 7301 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 7302 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 7303 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 7304 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 7305 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 7306 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 7307 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 7308 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 7309 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 7310 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 7311 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 7312 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 7313 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 7314 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL 7315 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL 7316 __le32 enables; 7317 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 7318 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 7319 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 7320 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 7321 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 7322 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 7323 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 7324 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 7325 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 7326 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 7327 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 7328 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 7329 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 7330 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 7331 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 7332 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 7333 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 7334 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL 7335 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL 7336 u8 l2_addr[6]; 7337 u8 num_vlans; 7338 u8 t_num_vlans; 7339 u8 l2_addr_mask[6]; 7340 __le16 l2_ovlan; 7341 __le16 l2_ovlan_mask; 7342 __le16 l2_ivlan; 7343 __le16 l2_ivlan_mask; 7344 u8 unused_1[2]; 7345 u8 t_l2_addr[6]; 7346 u8 unused_2[2]; 7347 u8 t_l2_addr_mask[6]; 7348 __le16 t_l2_ovlan; 7349 __le16 t_l2_ovlan_mask; 7350 __le16 t_l2_ivlan; 7351 __le16 t_l2_ivlan_mask; 7352 u8 src_type; 7353 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 7354 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 7355 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 7356 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 7357 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 7358 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 7359 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 7360 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 7361 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 7362 u8 unused_3; 7363 __le32 src_id; 7364 u8 tunnel_type; 7365 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7366 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7367 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7368 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7369 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7370 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7371 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7372 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7373 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7374 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7375 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7376 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7377 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7378 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 7379 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7380 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7381 u8 unused_4; 7382 __le16 dst_id; 7383 __le16 mirror_vnic_id; 7384 u8 pri_hint; 7385 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 7386 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 7387 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 7388 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 7389 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 7390 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 7391 u8 unused_5; 7392 __le32 unused_6; 7393 __le64 l2_filter_id_hint; 7394 }; 7395 7396 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 7397 struct hwrm_cfa_l2_filter_alloc_output { 7398 __le16 error_code; 7399 __le16 req_type; 7400 __le16 seq_id; 7401 __le16 resp_len; 7402 __le64 l2_filter_id; 7403 __le32 flow_id; 7404 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7405 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7406 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7407 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7408 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7409 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 7410 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7411 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7412 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7413 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7414 u8 unused_0[3]; 7415 u8 valid; 7416 }; 7417 7418 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 7419 struct hwrm_cfa_l2_filter_free_input { 7420 __le16 req_type; 7421 __le16 cmpl_ring; 7422 __le16 seq_id; 7423 __le16 target_id; 7424 __le64 resp_addr; 7425 __le64 l2_filter_id; 7426 }; 7427 7428 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 7429 struct hwrm_cfa_l2_filter_free_output { 7430 __le16 error_code; 7431 __le16 req_type; 7432 __le16 seq_id; 7433 __le16 resp_len; 7434 u8 unused_0[7]; 7435 u8 valid; 7436 }; 7437 7438 /* hwrm_cfa_l2_filter_cfg_input (size:384b/48B) */ 7439 struct hwrm_cfa_l2_filter_cfg_input { 7440 __le16 req_type; 7441 __le16 cmpl_ring; 7442 __le16 seq_id; 7443 __le16 target_id; 7444 __le64 resp_addr; 7445 __le32 flags; 7446 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 7447 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 7448 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 7449 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 7450 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 7451 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 7452 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 7453 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 7454 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 7455 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 7456 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 7457 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_MASK 0x30UL 7458 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_SFT 4 7459 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_NO_UPDATE (0x0UL << 4) 7460 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_BYPASS_LKUP (0x1UL << 4) 7461 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_ENABLE_LKUP (0x2UL << 4) 7462 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_ENABLE_LKUP 7463 __le32 enables; 7464 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 7465 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 7466 #define CFA_L2_FILTER_CFG_REQ_ENABLES_PROF_FUNC 0x4UL 7467 #define CFA_L2_FILTER_CFG_REQ_ENABLES_L2_CONTEXT_ID 0x8UL 7468 __le64 l2_filter_id; 7469 __le32 dst_id; 7470 __le32 new_mirror_vnic_id; 7471 __le32 prof_func; 7472 __le32 l2_context_id; 7473 }; 7474 7475 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 7476 struct hwrm_cfa_l2_filter_cfg_output { 7477 __le16 error_code; 7478 __le16 req_type; 7479 __le16 seq_id; 7480 __le16 resp_len; 7481 u8 unused_0[7]; 7482 u8 valid; 7483 }; 7484 7485 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 7486 struct hwrm_cfa_l2_set_rx_mask_input { 7487 __le16 req_type; 7488 __le16 cmpl_ring; 7489 __le16 seq_id; 7490 __le16 target_id; 7491 __le64 resp_addr; 7492 __le32 vnic_id; 7493 __le32 mask; 7494 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 7495 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 7496 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 7497 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 7498 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 7499 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 7500 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 7501 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 7502 __le64 mc_tbl_addr; 7503 __le32 num_mc_entries; 7504 u8 unused_0[4]; 7505 __le64 vlan_tag_tbl_addr; 7506 __le32 num_vlan_tags; 7507 u8 unused_1[4]; 7508 }; 7509 7510 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 7511 struct hwrm_cfa_l2_set_rx_mask_output { 7512 __le16 error_code; 7513 __le16 req_type; 7514 __le16 seq_id; 7515 __le16 resp_len; 7516 u8 unused_0[7]; 7517 u8 valid; 7518 }; 7519 7520 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 7521 struct hwrm_cfa_l2_set_rx_mask_cmd_err { 7522 u8 code; 7523 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 7524 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 7525 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 7526 u8 unused_0[7]; 7527 }; 7528 7529 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 7530 struct hwrm_cfa_tunnel_filter_alloc_input { 7531 __le16 req_type; 7532 __le16 cmpl_ring; 7533 __le16 seq_id; 7534 __le16 target_id; 7535 __le64 resp_addr; 7536 __le32 flags; 7537 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7538 __le32 enables; 7539 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 7540 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 7541 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 7542 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 7543 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 7544 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 7545 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 7546 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 7547 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 7548 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 7549 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 7550 __le64 l2_filter_id; 7551 u8 l2_addr[6]; 7552 __le16 l2_ivlan; 7553 __le32 l3_addr[4]; 7554 __le32 t_l3_addr[4]; 7555 u8 l3_addr_type; 7556 u8 t_l3_addr_type; 7557 u8 tunnel_type; 7558 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7559 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7560 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7561 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7562 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7563 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7564 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7565 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7566 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7567 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7568 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7569 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7570 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7571 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 7572 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7573 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7574 u8 tunnel_flags; 7575 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 7576 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 7577 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 7578 __le32 vni; 7579 __le32 dst_vnic_id; 7580 __le32 mirror_vnic_id; 7581 }; 7582 7583 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 7584 struct hwrm_cfa_tunnel_filter_alloc_output { 7585 __le16 error_code; 7586 __le16 req_type; 7587 __le16 seq_id; 7588 __le16 resp_len; 7589 __le64 tunnel_filter_id; 7590 __le32 flow_id; 7591 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7592 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7593 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7594 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7595 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7596 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 7597 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7598 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7599 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7600 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7601 u8 unused_0[3]; 7602 u8 valid; 7603 }; 7604 7605 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 7606 struct hwrm_cfa_tunnel_filter_free_input { 7607 __le16 req_type; 7608 __le16 cmpl_ring; 7609 __le16 seq_id; 7610 __le16 target_id; 7611 __le64 resp_addr; 7612 __le64 tunnel_filter_id; 7613 }; 7614 7615 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 7616 struct hwrm_cfa_tunnel_filter_free_output { 7617 __le16 error_code; 7618 __le16 req_type; 7619 __le16 seq_id; 7620 __le16 resp_len; 7621 u8 unused_0[7]; 7622 u8 valid; 7623 }; 7624 7625 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 7626 struct hwrm_vxlan_ipv4_hdr { 7627 u8 ver_hlen; 7628 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 7629 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 7630 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 7631 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 7632 u8 tos; 7633 __be16 ip_id; 7634 __be16 flags_frag_offset; 7635 u8 ttl; 7636 u8 protocol; 7637 __be32 src_ip_addr; 7638 __be32 dest_ip_addr; 7639 }; 7640 7641 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 7642 struct hwrm_vxlan_ipv6_hdr { 7643 __be32 ver_tc_flow_label; 7644 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 7645 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 7646 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 7647 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 7648 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 7649 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 7650 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 7651 __be16 payload_len; 7652 u8 next_hdr; 7653 u8 ttl; 7654 __be32 src_ip_addr[4]; 7655 __be32 dest_ip_addr[4]; 7656 }; 7657 7658 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 7659 struct hwrm_cfa_encap_data_vxlan { 7660 u8 src_mac_addr[6]; 7661 __le16 unused_0; 7662 u8 dst_mac_addr[6]; 7663 u8 num_vlan_tags; 7664 u8 unused_1; 7665 __be16 ovlan_tpid; 7666 __be16 ovlan_tci; 7667 __be16 ivlan_tpid; 7668 __be16 ivlan_tci; 7669 __le32 l3[10]; 7670 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 7671 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 7672 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 7673 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 7674 __be16 src_port; 7675 __be16 dst_port; 7676 __be32 vni; 7677 u8 hdr_rsvd0[3]; 7678 u8 hdr_rsvd1; 7679 u8 hdr_flags; 7680 u8 unused[3]; 7681 }; 7682 7683 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 7684 struct hwrm_cfa_encap_record_alloc_input { 7685 __le16 req_type; 7686 __le16 cmpl_ring; 7687 __le16 seq_id; 7688 __le16 target_id; 7689 __le64 resp_addr; 7690 __le32 flags; 7691 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7692 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL 7693 u8 encap_type; 7694 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 7695 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 7696 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 7697 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 7698 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 7699 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 7700 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 7701 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 7702 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 7703 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 7704 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 7705 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL 7706 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE 0x10UL 7707 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE 7708 u8 unused_0[3]; 7709 __le32 encap_data[20]; 7710 }; 7711 7712 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 7713 struct hwrm_cfa_encap_record_alloc_output { 7714 __le16 error_code; 7715 __le16 req_type; 7716 __le16 seq_id; 7717 __le16 resp_len; 7718 __le32 encap_record_id; 7719 u8 unused_0[3]; 7720 u8 valid; 7721 }; 7722 7723 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 7724 struct hwrm_cfa_encap_record_free_input { 7725 __le16 req_type; 7726 __le16 cmpl_ring; 7727 __le16 seq_id; 7728 __le16 target_id; 7729 __le64 resp_addr; 7730 __le32 encap_record_id; 7731 u8 unused_0[4]; 7732 }; 7733 7734 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 7735 struct hwrm_cfa_encap_record_free_output { 7736 __le16 error_code; 7737 __le16 req_type; 7738 __le16 seq_id; 7739 __le16 resp_len; 7740 u8 unused_0[7]; 7741 u8 valid; 7742 }; 7743 7744 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 7745 struct hwrm_cfa_ntuple_filter_alloc_input { 7746 __le16 req_type; 7747 __le16 cmpl_ring; 7748 __le16 seq_id; 7749 __le16 target_id; 7750 __le64 resp_addr; 7751 __le32 flags; 7752 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7753 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 7754 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 7755 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL 7756 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL 7757 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL 7758 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_NO_L2_CONTEXT 0x40UL 7759 __le32 enables; 7760 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 7761 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 7762 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 7763 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 7764 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 7765 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 7766 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 7767 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 7768 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 7769 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 7770 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 7771 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 7772 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 7773 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 7774 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 7775 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 7776 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 7777 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 7778 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 7779 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL 7780 __le64 l2_filter_id; 7781 u8 src_macaddr[6]; 7782 __be16 ethertype; 7783 u8 ip_addr_type; 7784 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 7785 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 7786 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 7787 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 7788 u8 ip_protocol; 7789 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 7790 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 7791 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 7792 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_ICMP 0x1UL 7793 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_ICMPV6 0x3aUL 7794 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD 0xffUL 7795 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD 7796 __le16 dst_id; 7797 __le16 rfs_ring_tbl_idx; 7798 u8 tunnel_type; 7799 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7800 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7801 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7802 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7803 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7804 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7805 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7806 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7807 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7808 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7809 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7810 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7811 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7812 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 7813 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7814 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7815 u8 pri_hint; 7816 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 7817 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 7818 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 7819 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 7820 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 7821 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 7822 __be32 src_ipaddr[4]; 7823 __be32 src_ipaddr_mask[4]; 7824 __be32 dst_ipaddr[4]; 7825 __be32 dst_ipaddr_mask[4]; 7826 __be16 src_port; 7827 __be16 src_port_mask; 7828 __be16 dst_port; 7829 __be16 dst_port_mask; 7830 __le64 ntuple_filter_id_hint; 7831 }; 7832 7833 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 7834 struct hwrm_cfa_ntuple_filter_alloc_output { 7835 __le16 error_code; 7836 __le16 req_type; 7837 __le16 seq_id; 7838 __le16 resp_len; 7839 __le64 ntuple_filter_id; 7840 __le32 flow_id; 7841 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7842 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7843 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7844 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7845 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7846 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 7847 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7848 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7849 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7850 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7851 u8 unused_0[3]; 7852 u8 valid; 7853 }; 7854 7855 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 7856 struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 7857 u8 code; 7858 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 7859 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 7860 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 7861 u8 unused_0[7]; 7862 }; 7863 7864 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 7865 struct hwrm_cfa_ntuple_filter_free_input { 7866 __le16 req_type; 7867 __le16 cmpl_ring; 7868 __le16 seq_id; 7869 __le16 target_id; 7870 __le64 resp_addr; 7871 __le64 ntuple_filter_id; 7872 }; 7873 7874 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 7875 struct hwrm_cfa_ntuple_filter_free_output { 7876 __le16 error_code; 7877 __le16 req_type; 7878 __le16 seq_id; 7879 __le16 resp_len; 7880 u8 unused_0[7]; 7881 u8 valid; 7882 }; 7883 7884 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 7885 struct hwrm_cfa_ntuple_filter_cfg_input { 7886 __le16 req_type; 7887 __le16 cmpl_ring; 7888 __le16 seq_id; 7889 __le16 target_id; 7890 __le64 resp_addr; 7891 __le32 enables; 7892 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 7893 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 7894 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 7895 __le32 flags; 7896 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL 7897 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL 7898 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_NO_L2_CONTEXT 0x4UL 7899 __le64 ntuple_filter_id; 7900 __le32 new_dst_id; 7901 __le32 new_mirror_vnic_id; 7902 __le16 new_meter_instance_id; 7903 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 7904 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 7905 u8 unused_1[6]; 7906 }; 7907 7908 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 7909 struct hwrm_cfa_ntuple_filter_cfg_output { 7910 __le16 error_code; 7911 __le16 req_type; 7912 __le16 seq_id; 7913 __le16 resp_len; 7914 u8 unused_0[7]; 7915 u8 valid; 7916 }; 7917 7918 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 7919 struct hwrm_cfa_decap_filter_alloc_input { 7920 __le16 req_type; 7921 __le16 cmpl_ring; 7922 __le16 seq_id; 7923 __le16 target_id; 7924 __le64 resp_addr; 7925 __le32 flags; 7926 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 7927 __le32 enables; 7928 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 7929 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 7930 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 7931 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 7932 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 7933 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 7934 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 7935 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 7936 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 7937 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 7938 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 7939 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 7940 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 7941 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 7942 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 7943 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 7944 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 7945 __be32 tunnel_id; 7946 u8 tunnel_type; 7947 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7948 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7949 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7950 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7951 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7952 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7953 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7954 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7955 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7956 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7957 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7958 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7959 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7960 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 7961 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7962 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7963 u8 unused_0; 7964 __le16 unused_1; 7965 u8 src_macaddr[6]; 7966 u8 unused_2[2]; 7967 u8 dst_macaddr[6]; 7968 __be16 ovlan_vid; 7969 __be16 ivlan_vid; 7970 __be16 t_ovlan_vid; 7971 __be16 t_ivlan_vid; 7972 __be16 ethertype; 7973 u8 ip_addr_type; 7974 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 7975 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 7976 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 7977 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 7978 u8 ip_protocol; 7979 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 7980 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 7981 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 7982 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 7983 __le16 unused_3; 7984 __le32 unused_4; 7985 __be32 src_ipaddr[4]; 7986 __be32 dst_ipaddr[4]; 7987 __be16 src_port; 7988 __be16 dst_port; 7989 __le16 dst_id; 7990 __le16 l2_ctxt_ref_id; 7991 }; 7992 7993 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 7994 struct hwrm_cfa_decap_filter_alloc_output { 7995 __le16 error_code; 7996 __le16 req_type; 7997 __le16 seq_id; 7998 __le16 resp_len; 7999 __le32 decap_filter_id; 8000 u8 unused_0[3]; 8001 u8 valid; 8002 }; 8003 8004 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 8005 struct hwrm_cfa_decap_filter_free_input { 8006 __le16 req_type; 8007 __le16 cmpl_ring; 8008 __le16 seq_id; 8009 __le16 target_id; 8010 __le64 resp_addr; 8011 __le32 decap_filter_id; 8012 u8 unused_0[4]; 8013 }; 8014 8015 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 8016 struct hwrm_cfa_decap_filter_free_output { 8017 __le16 error_code; 8018 __le16 req_type; 8019 __le16 seq_id; 8020 __le16 resp_len; 8021 u8 unused_0[7]; 8022 u8 valid; 8023 }; 8024 8025 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 8026 struct hwrm_cfa_flow_alloc_input { 8027 __le16 req_type; 8028 __le16 cmpl_ring; 8029 __le16 seq_id; 8030 __le16 target_id; 8031 __le64 resp_addr; 8032 __le16 flags; 8033 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 8034 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 8035 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 8036 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 8037 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 8038 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 8039 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 8040 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 8041 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 8042 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 8043 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 8044 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 8045 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 8046 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 8047 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 8048 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 8049 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL 8050 __le16 src_fid; 8051 __le32 tunnel_handle; 8052 __le16 action_flags; 8053 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 8054 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 8055 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 8056 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 8057 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 8058 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 8059 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 8060 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 8061 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 8062 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 8063 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 8064 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL 8065 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL 8066 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL 8067 __le16 dst_fid; 8068 __be16 l2_rewrite_vlan_tpid; 8069 __be16 l2_rewrite_vlan_tci; 8070 __le16 act_meter_id; 8071 __le16 ref_flow_handle; 8072 __be16 ethertype; 8073 __be16 outer_vlan_tci; 8074 __be16 dmac[3]; 8075 __be16 inner_vlan_tci; 8076 __be16 smac[3]; 8077 u8 ip_dst_mask_len; 8078 u8 ip_src_mask_len; 8079 __be32 ip_dst[4]; 8080 __be32 ip_src[4]; 8081 __be16 l4_src_port; 8082 __be16 l4_src_port_mask; 8083 __be16 l4_dst_port; 8084 __be16 l4_dst_port_mask; 8085 __be32 nat_ip_address[4]; 8086 __be16 l2_rewrite_dmac[3]; 8087 __be16 nat_port; 8088 __be16 l2_rewrite_smac[3]; 8089 u8 ip_proto; 8090 u8 tunnel_type; 8091 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 8092 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8093 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 8094 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 8095 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 8096 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8097 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 8098 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 8099 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 8100 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8101 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8102 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8103 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8104 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8105 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 8106 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 8107 }; 8108 8109 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 8110 struct hwrm_cfa_flow_alloc_output { 8111 __le16 error_code; 8112 __le16 req_type; 8113 __le16 seq_id; 8114 __le16 resp_len; 8115 __le16 flow_handle; 8116 u8 unused_0[2]; 8117 __le32 flow_id; 8118 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 8119 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 8120 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 8121 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 8122 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 8123 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT 8124 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 8125 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 8126 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 8127 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX 8128 __le64 ext_flow_handle; 8129 __le32 flow_counter_id; 8130 u8 unused_1[3]; 8131 u8 valid; 8132 }; 8133 8134 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ 8135 struct hwrm_cfa_flow_alloc_cmd_err { 8136 u8 code; 8137 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 8138 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL 8139 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL 8140 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL 8141 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL 8142 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL 8143 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL 8144 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL 8145 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 8146 u8 unused_0[7]; 8147 }; 8148 8149 /* hwrm_cfa_flow_free_input (size:256b/32B) */ 8150 struct hwrm_cfa_flow_free_input { 8151 __le16 req_type; 8152 __le16 cmpl_ring; 8153 __le16 seq_id; 8154 __le16 target_id; 8155 __le64 resp_addr; 8156 __le16 flow_handle; 8157 __le16 unused_0; 8158 __le32 flow_counter_id; 8159 __le64 ext_flow_handle; 8160 }; 8161 8162 /* hwrm_cfa_flow_free_output (size:256b/32B) */ 8163 struct hwrm_cfa_flow_free_output { 8164 __le16 error_code; 8165 __le16 req_type; 8166 __le16 seq_id; 8167 __le16 resp_len; 8168 __le64 packet; 8169 __le64 byte; 8170 u8 unused_0[7]; 8171 u8 valid; 8172 }; 8173 8174 /* hwrm_cfa_flow_info_input (size:256b/32B) */ 8175 struct hwrm_cfa_flow_info_input { 8176 __le16 req_type; 8177 __le16 cmpl_ring; 8178 __le16 seq_id; 8179 __le16 target_id; 8180 __le64 resp_addr; 8181 __le16 flow_handle; 8182 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL 8183 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL 8184 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL 8185 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_TX 0x3000UL 8186 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL 8187 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL 8188 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT_RX 0x9000UL 8189 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT_RX 0xa000UL 8190 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_RX 0xb000UL 8191 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX 0xc000UL 8192 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_LAST CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX 8193 u8 unused_0[6]; 8194 __le64 ext_flow_handle; 8195 }; 8196 8197 /* hwrm_cfa_flow_info_output (size:5632b/704B) */ 8198 struct hwrm_cfa_flow_info_output { 8199 __le16 error_code; 8200 __le16 req_type; 8201 __le16 seq_id; 8202 __le16 resp_len; 8203 u8 flags; 8204 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL 8205 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL 8206 u8 profile; 8207 __le16 src_fid; 8208 __le16 dst_fid; 8209 __le16 l2_ctxt_id; 8210 __le64 em_info; 8211 __le64 tcam_info; 8212 __le64 vfp_tcam_info; 8213 __le16 ar_id; 8214 __le16 flow_handle; 8215 __le32 tunnel_handle; 8216 __le16 flow_timer; 8217 u8 unused_0[6]; 8218 __le32 flow_key_data[130]; 8219 __le32 flow_action_info[30]; 8220 u8 unused_1[7]; 8221 u8 valid; 8222 }; 8223 8224 /* hwrm_cfa_flow_stats_input (size:640b/80B) */ 8225 struct hwrm_cfa_flow_stats_input { 8226 __le16 req_type; 8227 __le16 cmpl_ring; 8228 __le16 seq_id; 8229 __le16 target_id; 8230 __le64 resp_addr; 8231 __le16 num_flows; 8232 __le16 flow_handle_0; 8233 __le16 flow_handle_1; 8234 __le16 flow_handle_2; 8235 __le16 flow_handle_3; 8236 __le16 flow_handle_4; 8237 __le16 flow_handle_5; 8238 __le16 flow_handle_6; 8239 __le16 flow_handle_7; 8240 __le16 flow_handle_8; 8241 __le16 flow_handle_9; 8242 u8 unused_0[2]; 8243 __le32 flow_id_0; 8244 __le32 flow_id_1; 8245 __le32 flow_id_2; 8246 __le32 flow_id_3; 8247 __le32 flow_id_4; 8248 __le32 flow_id_5; 8249 __le32 flow_id_6; 8250 __le32 flow_id_7; 8251 __le32 flow_id_8; 8252 __le32 flow_id_9; 8253 }; 8254 8255 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 8256 struct hwrm_cfa_flow_stats_output { 8257 __le16 error_code; 8258 __le16 req_type; 8259 __le16 seq_id; 8260 __le16 resp_len; 8261 __le64 packet_0; 8262 __le64 packet_1; 8263 __le64 packet_2; 8264 __le64 packet_3; 8265 __le64 packet_4; 8266 __le64 packet_5; 8267 __le64 packet_6; 8268 __le64 packet_7; 8269 __le64 packet_8; 8270 __le64 packet_9; 8271 __le64 byte_0; 8272 __le64 byte_1; 8273 __le64 byte_2; 8274 __le64 byte_3; 8275 __le64 byte_4; 8276 __le64 byte_5; 8277 __le64 byte_6; 8278 __le64 byte_7; 8279 __le64 byte_8; 8280 __le64 byte_9; 8281 __le16 flow_hits; 8282 u8 unused_0[5]; 8283 u8 valid; 8284 }; 8285 8286 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 8287 struct hwrm_cfa_vfr_alloc_input { 8288 __le16 req_type; 8289 __le16 cmpl_ring; 8290 __le16 seq_id; 8291 __le16 target_id; 8292 __le64 resp_addr; 8293 __le16 vf_id; 8294 __le16 reserved; 8295 u8 unused_0[4]; 8296 char vfr_name[32]; 8297 }; 8298 8299 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 8300 struct hwrm_cfa_vfr_alloc_output { 8301 __le16 error_code; 8302 __le16 req_type; 8303 __le16 seq_id; 8304 __le16 resp_len; 8305 __le16 rx_cfa_code; 8306 __le16 tx_cfa_action; 8307 u8 unused_0[3]; 8308 u8 valid; 8309 }; 8310 8311 /* hwrm_cfa_vfr_free_input (size:448b/56B) */ 8312 struct hwrm_cfa_vfr_free_input { 8313 __le16 req_type; 8314 __le16 cmpl_ring; 8315 __le16 seq_id; 8316 __le16 target_id; 8317 __le64 resp_addr; 8318 char vfr_name[32]; 8319 __le16 vf_id; 8320 __le16 reserved; 8321 u8 unused_0[4]; 8322 }; 8323 8324 /* hwrm_cfa_vfr_free_output (size:128b/16B) */ 8325 struct hwrm_cfa_vfr_free_output { 8326 __le16 error_code; 8327 __le16 req_type; 8328 __le16 seq_id; 8329 __le16 resp_len; 8330 u8 unused_0[7]; 8331 u8 valid; 8332 }; 8333 8334 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ 8335 struct hwrm_cfa_eem_qcaps_input { 8336 __le16 req_type; 8337 __le16 cmpl_ring; 8338 __le16 seq_id; 8339 __le16 target_id; 8340 __le64 resp_addr; 8341 __le32 flags; 8342 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL 8343 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL 8344 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 8345 __le32 unused_0; 8346 }; 8347 8348 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ 8349 struct hwrm_cfa_eem_qcaps_output { 8350 __le16 error_code; 8351 __le16 req_type; 8352 __le16 seq_id; 8353 __le16 resp_len; 8354 __le32 flags; 8355 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL 8356 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL 8357 #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL 8358 #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL 8359 __le32 unused_0; 8360 __le32 supported; 8361 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL 8362 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL 8363 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL 8364 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL 8365 #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL 8366 __le32 max_entries_supported; 8367 __le16 key_entry_size; 8368 __le16 record_entry_size; 8369 __le16 efc_entry_size; 8370 __le16 fid_entry_size; 8371 u8 unused_1[7]; 8372 u8 valid; 8373 }; 8374 8375 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */ 8376 struct hwrm_cfa_eem_cfg_input { 8377 __le16 req_type; 8378 __le16 cmpl_ring; 8379 __le16 seq_id; 8380 __le16 target_id; 8381 __le64 resp_addr; 8382 __le32 flags; 8383 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL 8384 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL 8385 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 8386 #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL 8387 __le16 group_id; 8388 __le16 unused_0; 8389 __le32 num_entries; 8390 __le32 unused_1; 8391 __le16 key0_ctx_id; 8392 __le16 key1_ctx_id; 8393 __le16 record_ctx_id; 8394 __le16 efc_ctx_id; 8395 __le16 fid_ctx_id; 8396 __le16 unused_2; 8397 __le32 unused_3; 8398 }; 8399 8400 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */ 8401 struct hwrm_cfa_eem_cfg_output { 8402 __le16 error_code; 8403 __le16 req_type; 8404 __le16 seq_id; 8405 __le16 resp_len; 8406 u8 unused_0[7]; 8407 u8 valid; 8408 }; 8409 8410 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ 8411 struct hwrm_cfa_eem_qcfg_input { 8412 __le16 req_type; 8413 __le16 cmpl_ring; 8414 __le16 seq_id; 8415 __le16 target_id; 8416 __le64 resp_addr; 8417 __le32 flags; 8418 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL 8419 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL 8420 __le32 unused_0; 8421 }; 8422 8423 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ 8424 struct hwrm_cfa_eem_qcfg_output { 8425 __le16 error_code; 8426 __le16 req_type; 8427 __le16 seq_id; 8428 __le16 resp_len; 8429 __le32 flags; 8430 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL 8431 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL 8432 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL 8433 __le32 num_entries; 8434 __le16 key0_ctx_id; 8435 __le16 key1_ctx_id; 8436 __le16 record_ctx_id; 8437 __le16 efc_ctx_id; 8438 __le16 fid_ctx_id; 8439 u8 unused_2[5]; 8440 u8 valid; 8441 }; 8442 8443 /* hwrm_cfa_eem_op_input (size:192b/24B) */ 8444 struct hwrm_cfa_eem_op_input { 8445 __le16 req_type; 8446 __le16 cmpl_ring; 8447 __le16 seq_id; 8448 __le16 target_id; 8449 __le64 resp_addr; 8450 __le32 flags; 8451 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL 8452 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL 8453 __le16 unused_0; 8454 __le16 op; 8455 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL 8456 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL 8457 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL 8458 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL 8459 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP 8460 }; 8461 8462 /* hwrm_cfa_eem_op_output (size:128b/16B) */ 8463 struct hwrm_cfa_eem_op_output { 8464 __le16 error_code; 8465 __le16 req_type; 8466 __le16 seq_id; 8467 __le16 resp_len; 8468 u8 unused_0[7]; 8469 u8 valid; 8470 }; 8471 8472 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ 8473 struct hwrm_cfa_adv_flow_mgnt_qcaps_input { 8474 __le16 req_type; 8475 __le16 cmpl_ring; 8476 __le16 seq_id; 8477 __le16 target_id; 8478 __le64 resp_addr; 8479 __le32 unused_0[4]; 8480 }; 8481 8482 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ 8483 struct hwrm_cfa_adv_flow_mgnt_qcaps_output { 8484 __le16 error_code; 8485 __le16 req_type; 8486 __le16 seq_id; 8487 __le16 resp_len; 8488 __le32 flags; 8489 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL 8490 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL 8491 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL 8492 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL 8493 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL 8494 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL 8495 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL 8496 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL 8497 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL 8498 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL 8499 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL 8500 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL 8501 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL 8502 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL 8503 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL 8504 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TRUFLOW_CAPABLE 0x8000UL 8505 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED 0x10000UL 8506 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_LAG_SUPPORTED 0x20000UL 8507 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED 0x40000UL 8508 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NIC_FLOW_STATS_SUPPORTED 0x80000UL 8509 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED 0x100000UL 8510 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V3_SUPPORTED 0x200000UL 8511 u8 unused_0[3]; 8512 u8 valid; 8513 }; 8514 8515 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 8516 struct hwrm_tunnel_dst_port_query_input { 8517 __le16 req_type; 8518 __le16 cmpl_ring; 8519 __le16 seq_id; 8520 __le16 target_id; 8521 __le64 resp_addr; 8522 u8 tunnel_type; 8523 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8524 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8525 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8526 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8527 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8528 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8529 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL 8530 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ECPRI 0xeUL 8531 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_SRV6 0xfUL 8532 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8533 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GRE 0x11UL 8534 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR 0x12UL 8535 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 0x13UL 8536 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 0x14UL 8537 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 0x15UL 8538 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 0x16UL 8539 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 0x17UL 8540 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 0x18UL 8541 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 0x19UL 8542 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 8543 u8 tunnel_next_proto; 8544 u8 unused_0[6]; 8545 }; 8546 8547 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 8548 struct hwrm_tunnel_dst_port_query_output { 8549 __le16 error_code; 8550 __le16 req_type; 8551 __le16 seq_id; 8552 __le16 resp_len; 8553 __le16 tunnel_dst_port_id; 8554 __be16 tunnel_dst_port_val; 8555 u8 upar_in_use; 8556 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR0 0x1UL 8557 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR1 0x2UL 8558 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR2 0x4UL 8559 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR3 0x8UL 8560 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR4 0x10UL 8561 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR5 0x20UL 8562 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR6 0x40UL 8563 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR7 0x80UL 8564 u8 status; 8565 #define TUNNEL_DST_PORT_QUERY_RESP_STATUS_CHIP_LEVEL 0x1UL 8566 #define TUNNEL_DST_PORT_QUERY_RESP_STATUS_FUNC_LEVEL 0x2UL 8567 u8 unused_0; 8568 u8 valid; 8569 }; 8570 8571 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 8572 struct hwrm_tunnel_dst_port_alloc_input { 8573 __le16 req_type; 8574 __le16 cmpl_ring; 8575 __le16 seq_id; 8576 __le16 target_id; 8577 __le64 resp_addr; 8578 u8 tunnel_type; 8579 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8580 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8581 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8582 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8583 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8584 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8585 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL 8586 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ECPRI 0xeUL 8587 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_SRV6 0xfUL 8588 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8589 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GRE 0x11UL 8590 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR 0x12UL 8591 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 0x13UL 8592 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 0x14UL 8593 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 0x15UL 8594 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 0x16UL 8595 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 0x17UL 8596 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 0x18UL 8597 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 0x19UL 8598 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 8599 u8 tunnel_next_proto; 8600 __be16 tunnel_dst_port_val; 8601 u8 unused_0[4]; 8602 }; 8603 8604 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 8605 struct hwrm_tunnel_dst_port_alloc_output { 8606 __le16 error_code; 8607 __le16 req_type; 8608 __le16 seq_id; 8609 __le16 resp_len; 8610 __le16 tunnel_dst_port_id; 8611 u8 error_info; 8612 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_SUCCESS 0x0UL 8613 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ALLOCATED 0x1UL 8614 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_NO_RESOURCE 0x2UL 8615 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ENABLED 0x3UL 8616 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_LAST TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ENABLED 8617 u8 upar_in_use; 8618 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR0 0x1UL 8619 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR1 0x2UL 8620 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR2 0x4UL 8621 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR3 0x8UL 8622 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR4 0x10UL 8623 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR5 0x20UL 8624 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR6 0x40UL 8625 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR7 0x80UL 8626 u8 unused_0[3]; 8627 u8 valid; 8628 }; 8629 8630 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 8631 struct hwrm_tunnel_dst_port_free_input { 8632 __le16 req_type; 8633 __le16 cmpl_ring; 8634 __le16 seq_id; 8635 __le16 target_id; 8636 __le64 resp_addr; 8637 u8 tunnel_type; 8638 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8639 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8640 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8641 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8642 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8643 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8644 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL 8645 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ECPRI 0xeUL 8646 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_SRV6 0xfUL 8647 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8648 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GRE 0x11UL 8649 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR 0x12UL 8650 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 0x13UL 8651 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 0x14UL 8652 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 0x15UL 8653 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 0x16UL 8654 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 0x17UL 8655 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 0x18UL 8656 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 0x19UL 8657 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 8658 u8 tunnel_next_proto; 8659 __le16 tunnel_dst_port_id; 8660 u8 unused_0[4]; 8661 }; 8662 8663 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 8664 struct hwrm_tunnel_dst_port_free_output { 8665 __le16 error_code; 8666 __le16 req_type; 8667 __le16 seq_id; 8668 __le16 resp_len; 8669 u8 error_info; 8670 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_SUCCESS 0x0UL 8671 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_OWNER 0x1UL 8672 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED 0x2UL 8673 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_LAST TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED 8674 u8 unused_1[6]; 8675 u8 valid; 8676 }; 8677 8678 /* ctx_hw_stats (size:1280b/160B) */ 8679 struct ctx_hw_stats { 8680 __le64 rx_ucast_pkts; 8681 __le64 rx_mcast_pkts; 8682 __le64 rx_bcast_pkts; 8683 __le64 rx_discard_pkts; 8684 __le64 rx_error_pkts; 8685 __le64 rx_ucast_bytes; 8686 __le64 rx_mcast_bytes; 8687 __le64 rx_bcast_bytes; 8688 __le64 tx_ucast_pkts; 8689 __le64 tx_mcast_pkts; 8690 __le64 tx_bcast_pkts; 8691 __le64 tx_error_pkts; 8692 __le64 tx_discard_pkts; 8693 __le64 tx_ucast_bytes; 8694 __le64 tx_mcast_bytes; 8695 __le64 tx_bcast_bytes; 8696 __le64 tpa_pkts; 8697 __le64 tpa_bytes; 8698 __le64 tpa_events; 8699 __le64 tpa_aborts; 8700 }; 8701 8702 /* ctx_hw_stats_ext (size:1408b/176B) */ 8703 struct ctx_hw_stats_ext { 8704 __le64 rx_ucast_pkts; 8705 __le64 rx_mcast_pkts; 8706 __le64 rx_bcast_pkts; 8707 __le64 rx_discard_pkts; 8708 __le64 rx_error_pkts; 8709 __le64 rx_ucast_bytes; 8710 __le64 rx_mcast_bytes; 8711 __le64 rx_bcast_bytes; 8712 __le64 tx_ucast_pkts; 8713 __le64 tx_mcast_pkts; 8714 __le64 tx_bcast_pkts; 8715 __le64 tx_error_pkts; 8716 __le64 tx_discard_pkts; 8717 __le64 tx_ucast_bytes; 8718 __le64 tx_mcast_bytes; 8719 __le64 tx_bcast_bytes; 8720 __le64 rx_tpa_eligible_pkt; 8721 __le64 rx_tpa_eligible_bytes; 8722 __le64 rx_tpa_pkt; 8723 __le64 rx_tpa_bytes; 8724 __le64 rx_tpa_errors; 8725 __le64 rx_tpa_events; 8726 }; 8727 8728 /* hwrm_stat_ctx_alloc_input (size:320b/40B) */ 8729 struct hwrm_stat_ctx_alloc_input { 8730 __le16 req_type; 8731 __le16 cmpl_ring; 8732 __le16 seq_id; 8733 __le16 target_id; 8734 __le64 resp_addr; 8735 __le64 stats_dma_addr; 8736 __le32 update_period_ms; 8737 u8 stat_ctx_flags; 8738 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 8739 u8 unused_0; 8740 __le16 stats_dma_length; 8741 __le16 flags; 8742 #define STAT_CTX_ALLOC_REQ_FLAGS_STEERING_TAG_VALID 0x1UL 8743 __le16 steering_tag; 8744 __le32 unused_1; 8745 }; 8746 8747 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 8748 struct hwrm_stat_ctx_alloc_output { 8749 __le16 error_code; 8750 __le16 req_type; 8751 __le16 seq_id; 8752 __le16 resp_len; 8753 __le32 stat_ctx_id; 8754 u8 unused_0[3]; 8755 u8 valid; 8756 }; 8757 8758 /* hwrm_stat_ctx_free_input (size:192b/24B) */ 8759 struct hwrm_stat_ctx_free_input { 8760 __le16 req_type; 8761 __le16 cmpl_ring; 8762 __le16 seq_id; 8763 __le16 target_id; 8764 __le64 resp_addr; 8765 __le32 stat_ctx_id; 8766 u8 unused_0[4]; 8767 }; 8768 8769 /* hwrm_stat_ctx_free_output (size:128b/16B) */ 8770 struct hwrm_stat_ctx_free_output { 8771 __le16 error_code; 8772 __le16 req_type; 8773 __le16 seq_id; 8774 __le16 resp_len; 8775 __le32 stat_ctx_id; 8776 u8 unused_0[3]; 8777 u8 valid; 8778 }; 8779 8780 /* hwrm_stat_ctx_query_input (size:192b/24B) */ 8781 struct hwrm_stat_ctx_query_input { 8782 __le16 req_type; 8783 __le16 cmpl_ring; 8784 __le16 seq_id; 8785 __le16 target_id; 8786 __le64 resp_addr; 8787 __le32 stat_ctx_id; 8788 u8 flags; 8789 #define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 8790 u8 unused_0[3]; 8791 }; 8792 8793 /* hwrm_stat_ctx_query_output (size:1408b/176B) */ 8794 struct hwrm_stat_ctx_query_output { 8795 __le16 error_code; 8796 __le16 req_type; 8797 __le16 seq_id; 8798 __le16 resp_len; 8799 __le64 tx_ucast_pkts; 8800 __le64 tx_mcast_pkts; 8801 __le64 tx_bcast_pkts; 8802 __le64 tx_discard_pkts; 8803 __le64 tx_error_pkts; 8804 __le64 tx_ucast_bytes; 8805 __le64 tx_mcast_bytes; 8806 __le64 tx_bcast_bytes; 8807 __le64 rx_ucast_pkts; 8808 __le64 rx_mcast_pkts; 8809 __le64 rx_bcast_pkts; 8810 __le64 rx_discard_pkts; 8811 __le64 rx_error_pkts; 8812 __le64 rx_ucast_bytes; 8813 __le64 rx_mcast_bytes; 8814 __le64 rx_bcast_bytes; 8815 __le64 rx_agg_pkts; 8816 __le64 rx_agg_bytes; 8817 __le64 rx_agg_events; 8818 __le64 rx_agg_aborts; 8819 u8 unused_0[7]; 8820 u8 valid; 8821 }; 8822 8823 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ 8824 struct hwrm_stat_ext_ctx_query_input { 8825 __le16 req_type; 8826 __le16 cmpl_ring; 8827 __le16 seq_id; 8828 __le16 target_id; 8829 __le64 resp_addr; 8830 __le32 stat_ctx_id; 8831 u8 flags; 8832 #define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 8833 u8 unused_0[3]; 8834 }; 8835 8836 /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */ 8837 struct hwrm_stat_ext_ctx_query_output { 8838 __le16 error_code; 8839 __le16 req_type; 8840 __le16 seq_id; 8841 __le16 resp_len; 8842 __le64 rx_ucast_pkts; 8843 __le64 rx_mcast_pkts; 8844 __le64 rx_bcast_pkts; 8845 __le64 rx_discard_pkts; 8846 __le64 rx_error_pkts; 8847 __le64 rx_ucast_bytes; 8848 __le64 rx_mcast_bytes; 8849 __le64 rx_bcast_bytes; 8850 __le64 tx_ucast_pkts; 8851 __le64 tx_mcast_pkts; 8852 __le64 tx_bcast_pkts; 8853 __le64 tx_error_pkts; 8854 __le64 tx_discard_pkts; 8855 __le64 tx_ucast_bytes; 8856 __le64 tx_mcast_bytes; 8857 __le64 tx_bcast_bytes; 8858 __le64 rx_tpa_eligible_pkt; 8859 __le64 rx_tpa_eligible_bytes; 8860 __le64 rx_tpa_pkt; 8861 __le64 rx_tpa_bytes; 8862 __le64 rx_tpa_errors; 8863 __le64 rx_tpa_events; 8864 u8 unused_0[7]; 8865 u8 valid; 8866 }; 8867 8868 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 8869 struct hwrm_stat_ctx_clr_stats_input { 8870 __le16 req_type; 8871 __le16 cmpl_ring; 8872 __le16 seq_id; 8873 __le16 target_id; 8874 __le64 resp_addr; 8875 __le32 stat_ctx_id; 8876 u8 unused_0[4]; 8877 }; 8878 8879 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 8880 struct hwrm_stat_ctx_clr_stats_output { 8881 __le16 error_code; 8882 __le16 req_type; 8883 __le16 seq_id; 8884 __le16 resp_len; 8885 u8 unused_0[7]; 8886 u8 valid; 8887 }; 8888 8889 /* hwrm_pcie_qstats_input (size:256b/32B) */ 8890 struct hwrm_pcie_qstats_input { 8891 __le16 req_type; 8892 __le16 cmpl_ring; 8893 __le16 seq_id; 8894 __le16 target_id; 8895 __le64 resp_addr; 8896 __le16 pcie_stat_size; 8897 u8 unused_0[6]; 8898 __le64 pcie_stat_host_addr; 8899 }; 8900 8901 /* hwrm_pcie_qstats_output (size:128b/16B) */ 8902 struct hwrm_pcie_qstats_output { 8903 __le16 error_code; 8904 __le16 req_type; 8905 __le16 seq_id; 8906 __le16 resp_len; 8907 __le16 pcie_stat_size; 8908 u8 unused_0[5]; 8909 u8 valid; 8910 }; 8911 8912 /* pcie_ctx_hw_stats (size:768b/96B) */ 8913 struct pcie_ctx_hw_stats { 8914 __le64 pcie_pl_signal_integrity; 8915 __le64 pcie_dl_signal_integrity; 8916 __le64 pcie_tl_signal_integrity; 8917 __le64 pcie_link_integrity; 8918 __le64 pcie_tx_traffic_rate; 8919 __le64 pcie_rx_traffic_rate; 8920 __le64 pcie_tx_dllp_statistics; 8921 __le64 pcie_rx_dllp_statistics; 8922 __le64 pcie_equalization_time; 8923 __le32 pcie_ltssm_histogram[4]; 8924 __le64 pcie_recovery_histogram; 8925 }; 8926 8927 /* hwrm_stat_generic_qstats_input (size:256b/32B) */ 8928 struct hwrm_stat_generic_qstats_input { 8929 __le16 req_type; 8930 __le16 cmpl_ring; 8931 __le16 seq_id; 8932 __le16 target_id; 8933 __le64 resp_addr; 8934 __le16 generic_stat_size; 8935 u8 flags; 8936 #define STAT_GENERIC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 8937 u8 unused_0[5]; 8938 __le64 generic_stat_host_addr; 8939 }; 8940 8941 /* hwrm_stat_generic_qstats_output (size:128b/16B) */ 8942 struct hwrm_stat_generic_qstats_output { 8943 __le16 error_code; 8944 __le16 req_type; 8945 __le16 seq_id; 8946 __le16 resp_len; 8947 __le16 generic_stat_size; 8948 u8 unused_0[5]; 8949 u8 valid; 8950 }; 8951 8952 /* generic_sw_hw_stats (size:1472b/184B) */ 8953 struct generic_sw_hw_stats { 8954 __le64 pcie_statistics_tx_tlp; 8955 __le64 pcie_statistics_rx_tlp; 8956 __le64 pcie_credit_fc_hdr_posted; 8957 __le64 pcie_credit_fc_hdr_nonposted; 8958 __le64 pcie_credit_fc_hdr_cmpl; 8959 __le64 pcie_credit_fc_data_posted; 8960 __le64 pcie_credit_fc_data_nonposted; 8961 __le64 pcie_credit_fc_data_cmpl; 8962 __le64 pcie_credit_fc_tgt_nonposted; 8963 __le64 pcie_credit_fc_tgt_data_posted; 8964 __le64 pcie_credit_fc_tgt_hdr_posted; 8965 __le64 pcie_credit_fc_cmpl_hdr_posted; 8966 __le64 pcie_credit_fc_cmpl_data_posted; 8967 __le64 pcie_cmpl_longest; 8968 __le64 pcie_cmpl_shortest; 8969 __le64 cache_miss_count_cfcq; 8970 __le64 cache_miss_count_cfcs; 8971 __le64 cache_miss_count_cfcc; 8972 __le64 cache_miss_count_cfcm; 8973 __le64 hw_db_recov_dbs_dropped; 8974 __le64 hw_db_recov_drops_serviced; 8975 __le64 hw_db_recov_dbs_recovered; 8976 __le64 hw_db_recov_oo_drop_count; 8977 }; 8978 8979 /* hwrm_fw_reset_input (size:192b/24B) */ 8980 struct hwrm_fw_reset_input { 8981 __le16 req_type; 8982 __le16 cmpl_ring; 8983 __le16 seq_id; 8984 __le16 target_id; 8985 __le64 resp_addr; 8986 u8 embedded_proc_type; 8987 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 8988 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 8989 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 8990 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 8991 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 8992 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 8993 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 8994 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 8995 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL 8996 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 8997 u8 selfrst_status; 8998 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 8999 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 9000 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 9001 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 9002 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 9003 u8 host_idx; 9004 u8 flags; 9005 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL 9006 #define FW_RESET_REQ_FLAGS_FW_ACTIVATION 0x2UL 9007 u8 unused_0[4]; 9008 }; 9009 9010 /* hwrm_fw_reset_output (size:128b/16B) */ 9011 struct hwrm_fw_reset_output { 9012 __le16 error_code; 9013 __le16 req_type; 9014 __le16 seq_id; 9015 __le16 resp_len; 9016 u8 selfrst_status; 9017 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 9018 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 9019 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 9020 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 9021 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 9022 u8 unused_0[6]; 9023 u8 valid; 9024 }; 9025 9026 /* hwrm_fw_qstatus_input (size:192b/24B) */ 9027 struct hwrm_fw_qstatus_input { 9028 __le16 req_type; 9029 __le16 cmpl_ring; 9030 __le16 seq_id; 9031 __le16 target_id; 9032 __le64 resp_addr; 9033 u8 embedded_proc_type; 9034 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 9035 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 9036 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 9037 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 9038 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 9039 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 9040 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 9041 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 9042 u8 unused_0[7]; 9043 }; 9044 9045 /* hwrm_fw_qstatus_output (size:128b/16B) */ 9046 struct hwrm_fw_qstatus_output { 9047 __le16 error_code; 9048 __le16 req_type; 9049 __le16 seq_id; 9050 __le16 resp_len; 9051 u8 selfrst_status; 9052 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 9053 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 9054 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 9055 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL 9056 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 9057 u8 nvm_option_action_status; 9058 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_NONE 0x0UL 9059 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_HOTRESET 0x1UL 9060 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_WARMBOOT 0x2UL 9061 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 0x3UL 9062 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_LAST FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 9063 u8 unused_0[5]; 9064 u8 valid; 9065 }; 9066 9067 /* hwrm_fw_set_time_input (size:256b/32B) */ 9068 struct hwrm_fw_set_time_input { 9069 __le16 req_type; 9070 __le16 cmpl_ring; 9071 __le16 seq_id; 9072 __le16 target_id; 9073 __le64 resp_addr; 9074 __le16 year; 9075 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 9076 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 9077 u8 month; 9078 u8 day; 9079 u8 hour; 9080 u8 minute; 9081 u8 second; 9082 u8 unused_0; 9083 __le16 millisecond; 9084 __le16 zone; 9085 #define FW_SET_TIME_REQ_ZONE_UTC 0 9086 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535 9087 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 9088 u8 unused_1[4]; 9089 }; 9090 9091 /* hwrm_fw_set_time_output (size:128b/16B) */ 9092 struct hwrm_fw_set_time_output { 9093 __le16 error_code; 9094 __le16 req_type; 9095 __le16 seq_id; 9096 __le16 resp_len; 9097 u8 unused_0[7]; 9098 u8 valid; 9099 }; 9100 9101 /* hwrm_struct_hdr (size:128b/16B) */ 9102 struct hwrm_struct_hdr { 9103 __le16 struct_id; 9104 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 9105 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 9106 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 9107 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 9108 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 9109 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 9110 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 9111 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL 9112 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 9113 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 9114 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 9115 #define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL 9116 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 9117 __le16 len; 9118 u8 version; 9119 u8 count; 9120 __le16 subtype; 9121 __le16 next_offset; 9122 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 9123 u8 unused_0[6]; 9124 }; 9125 9126 /* hwrm_struct_data_dcbx_app (size:64b/8B) */ 9127 struct hwrm_struct_data_dcbx_app { 9128 __be16 protocol_id; 9129 u8 protocol_selector; 9130 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 9131 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 9132 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 9133 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 9134 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 9135 u8 priority; 9136 u8 valid; 9137 u8 unused_0[3]; 9138 }; 9139 9140 /* hwrm_fw_set_structured_data_input (size:256b/32B) */ 9141 struct hwrm_fw_set_structured_data_input { 9142 __le16 req_type; 9143 __le16 cmpl_ring; 9144 __le16 seq_id; 9145 __le16 target_id; 9146 __le64 resp_addr; 9147 __le64 src_data_addr; 9148 __le16 data_len; 9149 u8 hdr_cnt; 9150 u8 unused_0[5]; 9151 }; 9152 9153 /* hwrm_fw_set_structured_data_output (size:128b/16B) */ 9154 struct hwrm_fw_set_structured_data_output { 9155 __le16 error_code; 9156 __le16 req_type; 9157 __le16 seq_id; 9158 __le16 resp_len; 9159 u8 unused_0[7]; 9160 u8 valid; 9161 }; 9162 9163 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 9164 struct hwrm_fw_set_structured_data_cmd_err { 9165 u8 code; 9166 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 9167 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 9168 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 9169 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 9170 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 9171 u8 unused_0[7]; 9172 }; 9173 9174 /* hwrm_fw_get_structured_data_input (size:256b/32B) */ 9175 struct hwrm_fw_get_structured_data_input { 9176 __le16 req_type; 9177 __le16 cmpl_ring; 9178 __le16 seq_id; 9179 __le16 target_id; 9180 __le64 resp_addr; 9181 __le64 dest_data_addr; 9182 __le16 data_len; 9183 __le16 structure_id; 9184 __le16 subtype; 9185 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 9186 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 9187 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 9188 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 9189 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 9190 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 9191 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 9192 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 9193 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 9194 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 9195 u8 count; 9196 u8 unused_0; 9197 }; 9198 9199 /* hwrm_fw_get_structured_data_output (size:128b/16B) */ 9200 struct hwrm_fw_get_structured_data_output { 9201 __le16 error_code; 9202 __le16 req_type; 9203 __le16 seq_id; 9204 __le16 resp_len; 9205 u8 hdr_cnt; 9206 u8 unused_0[6]; 9207 u8 valid; 9208 }; 9209 9210 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 9211 struct hwrm_fw_get_structured_data_cmd_err { 9212 u8 code; 9213 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 9214 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 9215 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 9216 u8 unused_0[7]; 9217 }; 9218 9219 /* hwrm_fw_livepatch_query_input (size:192b/24B) */ 9220 struct hwrm_fw_livepatch_query_input { 9221 __le16 req_type; 9222 __le16 cmpl_ring; 9223 __le16 seq_id; 9224 __le16 target_id; 9225 __le64 resp_addr; 9226 u8 fw_target; 9227 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_COMMON_FW 0x1UL 9228 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 0x2UL 9229 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_LAST FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 9230 u8 unused_0[7]; 9231 }; 9232 9233 /* hwrm_fw_livepatch_query_output (size:640b/80B) */ 9234 struct hwrm_fw_livepatch_query_output { 9235 __le16 error_code; 9236 __le16 req_type; 9237 __le16 seq_id; 9238 __le16 resp_len; 9239 char install_ver[32]; 9240 char active_ver[32]; 9241 __le16 status_flags; 9242 #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_INSTALL 0x1UL 9243 #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_ACTIVE 0x2UL 9244 u8 unused_0[5]; 9245 u8 valid; 9246 }; 9247 9248 /* hwrm_fw_livepatch_input (size:256b/32B) */ 9249 struct hwrm_fw_livepatch_input { 9250 __le16 req_type; 9251 __le16 cmpl_ring; 9252 __le16 seq_id; 9253 __le16 target_id; 9254 __le64 resp_addr; 9255 u8 opcode; 9256 #define FW_LIVEPATCH_REQ_OPCODE_ACTIVATE 0x1UL 9257 #define FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 0x2UL 9258 #define FW_LIVEPATCH_REQ_OPCODE_LAST FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 9259 u8 fw_target; 9260 #define FW_LIVEPATCH_REQ_FW_TARGET_COMMON_FW 0x1UL 9261 #define FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 0x2UL 9262 #define FW_LIVEPATCH_REQ_FW_TARGET_LAST FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 9263 u8 loadtype; 9264 #define FW_LIVEPATCH_REQ_LOADTYPE_NVM_INSTALL 0x1UL 9265 #define FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 0x2UL 9266 #define FW_LIVEPATCH_REQ_LOADTYPE_LAST FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 9267 u8 flags; 9268 __le32 patch_len; 9269 __le64 host_addr; 9270 }; 9271 9272 /* hwrm_fw_livepatch_output (size:128b/16B) */ 9273 struct hwrm_fw_livepatch_output { 9274 __le16 error_code; 9275 __le16 req_type; 9276 __le16 seq_id; 9277 __le16 resp_len; 9278 u8 unused_0[7]; 9279 u8 valid; 9280 }; 9281 9282 /* hwrm_fw_livepatch_cmd_err (size:64b/8B) */ 9283 struct hwrm_fw_livepatch_cmd_err { 9284 u8 code; 9285 #define FW_LIVEPATCH_CMD_ERR_CODE_UNKNOWN 0x0UL 9286 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_OPCODE 0x1UL 9287 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_TARGET 0x2UL 9288 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_SUPPORTED 0x3UL 9289 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_INSTALLED 0x4UL 9290 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_PATCHED 0x5UL 9291 #define FW_LIVEPATCH_CMD_ERR_CODE_AUTH_FAIL 0x6UL 9292 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_HEADER 0x7UL 9293 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_SIZE 0x8UL 9294 #define FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 0x9UL 9295 #define FW_LIVEPATCH_CMD_ERR_CODE_LAST FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 9296 u8 unused_0[7]; 9297 }; 9298 9299 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 9300 struct hwrm_exec_fwd_resp_input { 9301 __le16 req_type; 9302 __le16 cmpl_ring; 9303 __le16 seq_id; 9304 __le16 target_id; 9305 __le64 resp_addr; 9306 __le32 encap_request[26]; 9307 __le16 encap_resp_target_id; 9308 u8 unused_0[6]; 9309 }; 9310 9311 /* hwrm_exec_fwd_resp_output (size:128b/16B) */ 9312 struct hwrm_exec_fwd_resp_output { 9313 __le16 error_code; 9314 __le16 req_type; 9315 __le16 seq_id; 9316 __le16 resp_len; 9317 u8 unused_0[7]; 9318 u8 valid; 9319 }; 9320 9321 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 9322 struct hwrm_reject_fwd_resp_input { 9323 __le16 req_type; 9324 __le16 cmpl_ring; 9325 __le16 seq_id; 9326 __le16 target_id; 9327 __le64 resp_addr; 9328 __le32 encap_request[26]; 9329 __le16 encap_resp_target_id; 9330 u8 unused_0[6]; 9331 }; 9332 9333 /* hwrm_reject_fwd_resp_output (size:128b/16B) */ 9334 struct hwrm_reject_fwd_resp_output { 9335 __le16 error_code; 9336 __le16 req_type; 9337 __le16 seq_id; 9338 __le16 resp_len; 9339 u8 unused_0[7]; 9340 u8 valid; 9341 }; 9342 9343 /* hwrm_fwd_resp_input (size:1024b/128B) */ 9344 struct hwrm_fwd_resp_input { 9345 __le16 req_type; 9346 __le16 cmpl_ring; 9347 __le16 seq_id; 9348 __le16 target_id; 9349 __le64 resp_addr; 9350 __le16 encap_resp_target_id; 9351 __le16 encap_resp_cmpl_ring; 9352 __le16 encap_resp_len; 9353 u8 unused_0; 9354 u8 unused_1; 9355 __le64 encap_resp_addr; 9356 __le32 encap_resp[24]; 9357 }; 9358 9359 /* hwrm_fwd_resp_output (size:128b/16B) */ 9360 struct hwrm_fwd_resp_output { 9361 __le16 error_code; 9362 __le16 req_type; 9363 __le16 seq_id; 9364 __le16 resp_len; 9365 u8 unused_0[7]; 9366 u8 valid; 9367 }; 9368 9369 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 9370 struct hwrm_fwd_async_event_cmpl_input { 9371 __le16 req_type; 9372 __le16 cmpl_ring; 9373 __le16 seq_id; 9374 __le16 target_id; 9375 __le64 resp_addr; 9376 __le16 encap_async_event_target_id; 9377 u8 unused_0[6]; 9378 __le32 encap_async_event_cmpl[4]; 9379 }; 9380 9381 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 9382 struct hwrm_fwd_async_event_cmpl_output { 9383 __le16 error_code; 9384 __le16 req_type; 9385 __le16 seq_id; 9386 __le16 resp_len; 9387 u8 unused_0[7]; 9388 u8 valid; 9389 }; 9390 9391 /* hwrm_temp_monitor_query_input (size:128b/16B) */ 9392 struct hwrm_temp_monitor_query_input { 9393 __le16 req_type; 9394 __le16 cmpl_ring; 9395 __le16 seq_id; 9396 __le16 target_id; 9397 __le64 resp_addr; 9398 }; 9399 9400 /* hwrm_temp_monitor_query_output (size:192b/24B) */ 9401 struct hwrm_temp_monitor_query_output { 9402 __le16 error_code; 9403 __le16 req_type; 9404 __le16 seq_id; 9405 __le16 resp_len; 9406 u8 temp; 9407 u8 phy_temp; 9408 u8 om_temp; 9409 u8 flags; 9410 #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL 9411 #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL 9412 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL 9413 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL 9414 #define TEMP_MONITOR_QUERY_RESP_FLAGS_EXT_TEMP_FIELDS_AVAILABLE 0x10UL 9415 #define TEMP_MONITOR_QUERY_RESP_FLAGS_THRESHOLD_VALUES_AVAILABLE 0x20UL 9416 u8 temp2; 9417 u8 phy_temp2; 9418 u8 om_temp2; 9419 u8 warn_threshold; 9420 u8 critical_threshold; 9421 u8 fatal_threshold; 9422 u8 shutdown_threshold; 9423 u8 unused_0[4]; 9424 u8 valid; 9425 }; 9426 9427 /* hwrm_wol_filter_alloc_input (size:512b/64B) */ 9428 struct hwrm_wol_filter_alloc_input { 9429 __le16 req_type; 9430 __le16 cmpl_ring; 9431 __le16 seq_id; 9432 __le16 target_id; 9433 __le64 resp_addr; 9434 __le32 flags; 9435 __le32 enables; 9436 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 9437 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 9438 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 9439 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 9440 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 9441 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 9442 __le16 port_id; 9443 u8 wol_type; 9444 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 9445 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 9446 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 9447 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 9448 u8 unused_0[5]; 9449 u8 mac_address[6]; 9450 __le16 pattern_offset; 9451 __le16 pattern_buf_size; 9452 __le16 pattern_mask_size; 9453 u8 unused_1[4]; 9454 __le64 pattern_buf_addr; 9455 __le64 pattern_mask_addr; 9456 }; 9457 9458 /* hwrm_wol_filter_alloc_output (size:128b/16B) */ 9459 struct hwrm_wol_filter_alloc_output { 9460 __le16 error_code; 9461 __le16 req_type; 9462 __le16 seq_id; 9463 __le16 resp_len; 9464 u8 wol_filter_id; 9465 u8 unused_0[6]; 9466 u8 valid; 9467 }; 9468 9469 /* hwrm_wol_filter_free_input (size:256b/32B) */ 9470 struct hwrm_wol_filter_free_input { 9471 __le16 req_type; 9472 __le16 cmpl_ring; 9473 __le16 seq_id; 9474 __le16 target_id; 9475 __le64 resp_addr; 9476 __le32 flags; 9477 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 9478 __le32 enables; 9479 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 9480 __le16 port_id; 9481 u8 wol_filter_id; 9482 u8 unused_0[5]; 9483 }; 9484 9485 /* hwrm_wol_filter_free_output (size:128b/16B) */ 9486 struct hwrm_wol_filter_free_output { 9487 __le16 error_code; 9488 __le16 req_type; 9489 __le16 seq_id; 9490 __le16 resp_len; 9491 u8 unused_0[7]; 9492 u8 valid; 9493 }; 9494 9495 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 9496 struct hwrm_wol_filter_qcfg_input { 9497 __le16 req_type; 9498 __le16 cmpl_ring; 9499 __le16 seq_id; 9500 __le16 target_id; 9501 __le64 resp_addr; 9502 __le16 port_id; 9503 __le16 handle; 9504 u8 unused_0[4]; 9505 __le64 pattern_buf_addr; 9506 __le16 pattern_buf_size; 9507 u8 unused_1[6]; 9508 __le64 pattern_mask_addr; 9509 __le16 pattern_mask_size; 9510 u8 unused_2[6]; 9511 }; 9512 9513 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 9514 struct hwrm_wol_filter_qcfg_output { 9515 __le16 error_code; 9516 __le16 req_type; 9517 __le16 seq_id; 9518 __le16 resp_len; 9519 __le16 next_handle; 9520 u8 wol_filter_id; 9521 u8 wol_type; 9522 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 9523 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 9524 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 9525 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 9526 __le32 unused_0; 9527 u8 mac_address[6]; 9528 __le16 pattern_offset; 9529 __le16 pattern_size; 9530 __le16 pattern_mask_size; 9531 u8 unused_1[3]; 9532 u8 valid; 9533 }; 9534 9535 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 9536 struct hwrm_wol_reason_qcfg_input { 9537 __le16 req_type; 9538 __le16 cmpl_ring; 9539 __le16 seq_id; 9540 __le16 target_id; 9541 __le64 resp_addr; 9542 __le16 port_id; 9543 u8 unused_0[6]; 9544 __le64 wol_pkt_buf_addr; 9545 __le16 wol_pkt_buf_size; 9546 u8 unused_1[6]; 9547 }; 9548 9549 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 9550 struct hwrm_wol_reason_qcfg_output { 9551 __le16 error_code; 9552 __le16 req_type; 9553 __le16 seq_id; 9554 __le16 resp_len; 9555 u8 wol_filter_id; 9556 u8 wol_reason; 9557 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 9558 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 9559 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 9560 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 9561 u8 wol_pkt_len; 9562 u8 unused_0[4]; 9563 u8 valid; 9564 }; 9565 9566 /* hwrm_dbg_read_direct_input (size:256b/32B) */ 9567 struct hwrm_dbg_read_direct_input { 9568 __le16 req_type; 9569 __le16 cmpl_ring; 9570 __le16 seq_id; 9571 __le16 target_id; 9572 __le64 resp_addr; 9573 __le64 host_dest_addr; 9574 __le32 read_addr; 9575 __le32 read_len32; 9576 }; 9577 9578 /* hwrm_dbg_read_direct_output (size:128b/16B) */ 9579 struct hwrm_dbg_read_direct_output { 9580 __le16 error_code; 9581 __le16 req_type; 9582 __le16 seq_id; 9583 __le16 resp_len; 9584 __le32 crc32; 9585 u8 unused_0[3]; 9586 u8 valid; 9587 }; 9588 9589 /* hwrm_dbg_qcaps_input (size:192b/24B) */ 9590 struct hwrm_dbg_qcaps_input { 9591 __le16 req_type; 9592 __le16 cmpl_ring; 9593 __le16 seq_id; 9594 __le16 target_id; 9595 __le64 resp_addr; 9596 __le16 fid; 9597 u8 unused_0[6]; 9598 }; 9599 9600 /* hwrm_dbg_qcaps_output (size:192b/24B) */ 9601 struct hwrm_dbg_qcaps_output { 9602 __le16 error_code; 9603 __le16 req_type; 9604 __le16 seq_id; 9605 __le16 resp_len; 9606 __le16 fid; 9607 u8 unused_0[2]; 9608 __le32 coredump_component_disable_caps; 9609 #define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM 0x1UL 9610 __le32 flags; 9611 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL 9612 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL 9613 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL 9614 #define DBG_QCAPS_RESP_FLAGS_USEQ 0x8UL 9615 u8 unused_1[3]; 9616 u8 valid; 9617 }; 9618 9619 /* hwrm_dbg_qcfg_input (size:192b/24B) */ 9620 struct hwrm_dbg_qcfg_input { 9621 __le16 req_type; 9622 __le16 cmpl_ring; 9623 __le16 seq_id; 9624 __le16 target_id; 9625 __le64 resp_addr; 9626 __le16 fid; 9627 __le16 flags; 9628 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK 0x3UL 9629 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0 9630 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM 0x0UL 9631 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR 0x1UL 9632 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 0x2UL 9633 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 9634 __le32 coredump_component_disable_flags; 9635 #define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM 0x1UL 9636 }; 9637 9638 /* hwrm_dbg_qcfg_output (size:256b/32B) */ 9639 struct hwrm_dbg_qcfg_output { 9640 __le16 error_code; 9641 __le16 req_type; 9642 __le16 seq_id; 9643 __le16 resp_len; 9644 __le16 fid; 9645 u8 unused_0[2]; 9646 __le32 coredump_size; 9647 __le32 flags; 9648 #define DBG_QCFG_RESP_FLAGS_UART_LOG 0x1UL 9649 #define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY 0x2UL 9650 #define DBG_QCFG_RESP_FLAGS_FW_TRACE 0x4UL 9651 #define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY 0x8UL 9652 #define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY 0x10UL 9653 #define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG 0x20UL 9654 __le16 async_cmpl_ring; 9655 u8 unused_2[2]; 9656 __le32 crashdump_size; 9657 u8 unused_3[3]; 9658 u8 valid; 9659 }; 9660 9661 /* hwrm_dbg_crashdump_medium_cfg_input (size:320b/40B) */ 9662 struct hwrm_dbg_crashdump_medium_cfg_input { 9663 __le16 req_type; 9664 __le16 cmpl_ring; 9665 __le16 seq_id; 9666 __le16 target_id; 9667 __le64 resp_addr; 9668 __le16 output_dest_flags; 9669 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_TYPE_DDR 0x1UL 9670 __le16 pg_size_lvl; 9671 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_MASK 0x3UL 9672 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_SFT 0 9673 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_0 0x0UL 9674 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_1 0x1UL 9675 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2 0x2UL 9676 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2 9677 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_MASK 0x1cUL 9678 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_SFT 2 9679 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_4K (0x0UL << 2) 9680 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8K (0x1UL << 2) 9681 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_64K (0x2UL << 2) 9682 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_2M (0x3UL << 2) 9683 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8M (0x4UL << 2) 9684 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G (0x5UL << 2) 9685 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G 9686 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_MASK 0xffe0UL 9687 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_SFT 5 9688 __le32 size; 9689 __le32 coredump_component_disable_flags; 9690 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_NVRAM 0x1UL 9691 __le32 unused_0; 9692 __le64 pbl; 9693 }; 9694 9695 /* hwrm_dbg_crashdump_medium_cfg_output (size:128b/16B) */ 9696 struct hwrm_dbg_crashdump_medium_cfg_output { 9697 __le16 error_code; 9698 __le16 req_type; 9699 __le16 seq_id; 9700 __le16 resp_len; 9701 u8 unused_1[7]; 9702 u8 valid; 9703 }; 9704 9705 /* coredump_segment_record (size:128b/16B) */ 9706 struct coredump_segment_record { 9707 __le16 component_id; 9708 __le16 segment_id; 9709 __le16 max_instances; 9710 u8 version_hi; 9711 u8 version_low; 9712 u8 seg_flags; 9713 u8 compress_flags; 9714 #define SFLAG_COMPRESSED_ZLIB 0x1UL 9715 u8 unused_0[2]; 9716 __le32 segment_len; 9717 }; 9718 9719 /* hwrm_dbg_coredump_list_input (size:256b/32B) */ 9720 struct hwrm_dbg_coredump_list_input { 9721 __le16 req_type; 9722 __le16 cmpl_ring; 9723 __le16 seq_id; 9724 __le16 target_id; 9725 __le64 resp_addr; 9726 __le64 host_dest_addr; 9727 __le32 host_buf_len; 9728 __le16 seq_no; 9729 u8 flags; 9730 #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL 9731 u8 unused_0[1]; 9732 }; 9733 9734 /* hwrm_dbg_coredump_list_output (size:128b/16B) */ 9735 struct hwrm_dbg_coredump_list_output { 9736 __le16 error_code; 9737 __le16 req_type; 9738 __le16 seq_id; 9739 __le16 resp_len; 9740 u8 flags; 9741 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 9742 u8 unused_0; 9743 __le16 total_segments; 9744 __le16 data_len; 9745 u8 unused_1; 9746 u8 valid; 9747 }; 9748 9749 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 9750 struct hwrm_dbg_coredump_initiate_input { 9751 __le16 req_type; 9752 __le16 cmpl_ring; 9753 __le16 seq_id; 9754 __le16 target_id; 9755 __le64 resp_addr; 9756 __le16 component_id; 9757 __le16 segment_id; 9758 __le16 instance; 9759 __le16 unused_0; 9760 u8 seg_flags; 9761 u8 unused_1[7]; 9762 }; 9763 9764 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 9765 struct hwrm_dbg_coredump_initiate_output { 9766 __le16 error_code; 9767 __le16 req_type; 9768 __le16 seq_id; 9769 __le16 resp_len; 9770 u8 unused_0[7]; 9771 u8 valid; 9772 }; 9773 9774 /* coredump_data_hdr (size:128b/16B) */ 9775 struct coredump_data_hdr { 9776 __le32 address; 9777 __le32 flags_length; 9778 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK 0xffffffUL 9779 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT 0 9780 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS 0x1000000UL 9781 __le32 instance; 9782 __le32 next_offset; 9783 }; 9784 9785 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 9786 struct hwrm_dbg_coredump_retrieve_input { 9787 __le16 req_type; 9788 __le16 cmpl_ring; 9789 __le16 seq_id; 9790 __le16 target_id; 9791 __le64 resp_addr; 9792 __le64 host_dest_addr; 9793 __le32 host_buf_len; 9794 __le32 unused_0; 9795 __le16 component_id; 9796 __le16 segment_id; 9797 __le16 instance; 9798 __le16 unused_1; 9799 u8 seg_flags; 9800 u8 unused_2; 9801 __le16 unused_3; 9802 __le32 unused_4; 9803 __le32 seq_no; 9804 __le32 unused_5; 9805 }; 9806 9807 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 9808 struct hwrm_dbg_coredump_retrieve_output { 9809 __le16 error_code; 9810 __le16 req_type; 9811 __le16 seq_id; 9812 __le16 resp_len; 9813 u8 flags; 9814 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 9815 u8 unused_0; 9816 __le16 data_len; 9817 u8 unused_1[3]; 9818 u8 valid; 9819 }; 9820 9821 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 9822 struct hwrm_dbg_ring_info_get_input { 9823 __le16 req_type; 9824 __le16 cmpl_ring; 9825 __le16 seq_id; 9826 __le16 target_id; 9827 __le64 resp_addr; 9828 u8 ring_type; 9829 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 9830 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 9831 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 9832 #define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 0x3UL 9833 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 9834 u8 unused_0[3]; 9835 __le32 fw_ring_id; 9836 }; 9837 9838 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 9839 struct hwrm_dbg_ring_info_get_output { 9840 __le16 error_code; 9841 __le16 req_type; 9842 __le16 seq_id; 9843 __le16 resp_len; 9844 __le32 producer_index; 9845 __le32 consumer_index; 9846 __le32 cag_vector_ctrl; 9847 __le16 st_tag; 9848 u8 unused_0; 9849 u8 valid; 9850 }; 9851 9852 /* hwrm_nvm_read_input (size:320b/40B) */ 9853 struct hwrm_nvm_read_input { 9854 __le16 req_type; 9855 __le16 cmpl_ring; 9856 __le16 seq_id; 9857 __le16 target_id; 9858 __le64 resp_addr; 9859 __le64 host_dest_addr; 9860 __le16 dir_idx; 9861 u8 unused_0[2]; 9862 __le32 offset; 9863 __le32 len; 9864 u8 unused_1[4]; 9865 }; 9866 9867 /* hwrm_nvm_read_output (size:128b/16B) */ 9868 struct hwrm_nvm_read_output { 9869 __le16 error_code; 9870 __le16 req_type; 9871 __le16 seq_id; 9872 __le16 resp_len; 9873 u8 unused_0[7]; 9874 u8 valid; 9875 }; 9876 9877 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 9878 struct hwrm_nvm_get_dir_entries_input { 9879 __le16 req_type; 9880 __le16 cmpl_ring; 9881 __le16 seq_id; 9882 __le16 target_id; 9883 __le64 resp_addr; 9884 __le64 host_dest_addr; 9885 }; 9886 9887 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 9888 struct hwrm_nvm_get_dir_entries_output { 9889 __le16 error_code; 9890 __le16 req_type; 9891 __le16 seq_id; 9892 __le16 resp_len; 9893 u8 unused_0[7]; 9894 u8 valid; 9895 }; 9896 9897 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 9898 struct hwrm_nvm_get_dir_info_input { 9899 __le16 req_type; 9900 __le16 cmpl_ring; 9901 __le16 seq_id; 9902 __le16 target_id; 9903 __le64 resp_addr; 9904 }; 9905 9906 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 9907 struct hwrm_nvm_get_dir_info_output { 9908 __le16 error_code; 9909 __le16 req_type; 9910 __le16 seq_id; 9911 __le16 resp_len; 9912 __le32 entries; 9913 __le32 entry_length; 9914 u8 unused_0[7]; 9915 u8 valid; 9916 }; 9917 9918 /* hwrm_nvm_write_input (size:448b/56B) */ 9919 struct hwrm_nvm_write_input { 9920 __le16 req_type; 9921 __le16 cmpl_ring; 9922 __le16 seq_id; 9923 __le16 target_id; 9924 __le64 resp_addr; 9925 __le64 host_src_addr; 9926 __le16 dir_type; 9927 __le16 dir_ordinal; 9928 __le16 dir_ext; 9929 __le16 dir_attr; 9930 __le32 dir_data_length; 9931 __le16 option; 9932 __le16 flags; 9933 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 9934 #define NVM_WRITE_REQ_FLAGS_BATCH_MODE 0x2UL 9935 #define NVM_WRITE_REQ_FLAGS_BATCH_LAST 0x4UL 9936 __le32 dir_item_length; 9937 __le32 offset; 9938 __le32 len; 9939 __le32 unused_0; 9940 }; 9941 9942 /* hwrm_nvm_write_output (size:128b/16B) */ 9943 struct hwrm_nvm_write_output { 9944 __le16 error_code; 9945 __le16 req_type; 9946 __le16 seq_id; 9947 __le16 resp_len; 9948 __le32 dir_item_length; 9949 __le16 dir_idx; 9950 u8 unused_0; 9951 u8 valid; 9952 }; 9953 9954 /* hwrm_nvm_write_cmd_err (size:64b/8B) */ 9955 struct hwrm_nvm_write_cmd_err { 9956 u8 code; 9957 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 9958 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 9959 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 9960 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 9961 u8 unused_0[7]; 9962 }; 9963 9964 /* hwrm_nvm_modify_input (size:320b/40B) */ 9965 struct hwrm_nvm_modify_input { 9966 __le16 req_type; 9967 __le16 cmpl_ring; 9968 __le16 seq_id; 9969 __le16 target_id; 9970 __le64 resp_addr; 9971 __le64 host_src_addr; 9972 __le16 dir_idx; 9973 __le16 flags; 9974 #define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL 9975 #define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL 9976 __le32 offset; 9977 __le32 len; 9978 u8 unused_1[4]; 9979 }; 9980 9981 /* hwrm_nvm_modify_output (size:128b/16B) */ 9982 struct hwrm_nvm_modify_output { 9983 __le16 error_code; 9984 __le16 req_type; 9985 __le16 seq_id; 9986 __le16 resp_len; 9987 u8 unused_0[7]; 9988 u8 valid; 9989 }; 9990 9991 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 9992 struct hwrm_nvm_find_dir_entry_input { 9993 __le16 req_type; 9994 __le16 cmpl_ring; 9995 __le16 seq_id; 9996 __le16 target_id; 9997 __le64 resp_addr; 9998 __le32 enables; 9999 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 10000 __le16 dir_idx; 10001 __le16 dir_type; 10002 __le16 dir_ordinal; 10003 __le16 dir_ext; 10004 u8 opt_ordinal; 10005 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 10006 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 10007 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 10008 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 10009 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 10010 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 10011 u8 unused_0[3]; 10012 }; 10013 10014 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 10015 struct hwrm_nvm_find_dir_entry_output { 10016 __le16 error_code; 10017 __le16 req_type; 10018 __le16 seq_id; 10019 __le16 resp_len; 10020 __le32 dir_item_length; 10021 __le32 dir_data_length; 10022 __le32 fw_ver; 10023 __le16 dir_ordinal; 10024 __le16 dir_idx; 10025 u8 unused_0[7]; 10026 u8 valid; 10027 }; 10028 10029 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 10030 struct hwrm_nvm_erase_dir_entry_input { 10031 __le16 req_type; 10032 __le16 cmpl_ring; 10033 __le16 seq_id; 10034 __le16 target_id; 10035 __le64 resp_addr; 10036 __le16 dir_idx; 10037 u8 unused_0[6]; 10038 }; 10039 10040 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 10041 struct hwrm_nvm_erase_dir_entry_output { 10042 __le16 error_code; 10043 __le16 req_type; 10044 __le16 seq_id; 10045 __le16 resp_len; 10046 u8 unused_0[7]; 10047 u8 valid; 10048 }; 10049 10050 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 10051 struct hwrm_nvm_get_dev_info_input { 10052 __le16 req_type; 10053 __le16 cmpl_ring; 10054 __le16 seq_id; 10055 __le16 target_id; 10056 __le64 resp_addr; 10057 }; 10058 10059 /* hwrm_nvm_get_dev_info_output (size:704b/88B) */ 10060 struct hwrm_nvm_get_dev_info_output { 10061 __le16 error_code; 10062 __le16 req_type; 10063 __le16 seq_id; 10064 __le16 resp_len; 10065 __le16 manufacturer_id; 10066 __le16 device_id; 10067 __le32 sector_size; 10068 __le32 nvram_size; 10069 __le32 reserved_size; 10070 __le32 available_size; 10071 u8 nvm_cfg_ver_maj; 10072 u8 nvm_cfg_ver_min; 10073 u8 nvm_cfg_ver_upd; 10074 u8 flags; 10075 #define NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID 0x1UL 10076 char pkg_name[16]; 10077 __le16 hwrm_fw_major; 10078 __le16 hwrm_fw_minor; 10079 __le16 hwrm_fw_build; 10080 __le16 hwrm_fw_patch; 10081 __le16 mgmt_fw_major; 10082 __le16 mgmt_fw_minor; 10083 __le16 mgmt_fw_build; 10084 __le16 mgmt_fw_patch; 10085 __le16 roce_fw_major; 10086 __le16 roce_fw_minor; 10087 __le16 roce_fw_build; 10088 __le16 roce_fw_patch; 10089 __le16 netctrl_fw_major; 10090 __le16 netctrl_fw_minor; 10091 __le16 netctrl_fw_build; 10092 __le16 netctrl_fw_patch; 10093 u8 unused_0[7]; 10094 u8 valid; 10095 }; 10096 10097 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 10098 struct hwrm_nvm_mod_dir_entry_input { 10099 __le16 req_type; 10100 __le16 cmpl_ring; 10101 __le16 seq_id; 10102 __le16 target_id; 10103 __le64 resp_addr; 10104 __le32 enables; 10105 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 10106 __le16 dir_idx; 10107 __le16 dir_ordinal; 10108 __le16 dir_ext; 10109 __le16 dir_attr; 10110 __le32 checksum; 10111 }; 10112 10113 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 10114 struct hwrm_nvm_mod_dir_entry_output { 10115 __le16 error_code; 10116 __le16 req_type; 10117 __le16 seq_id; 10118 __le16 resp_len; 10119 u8 unused_0[7]; 10120 u8 valid; 10121 }; 10122 10123 /* hwrm_nvm_verify_update_input (size:192b/24B) */ 10124 struct hwrm_nvm_verify_update_input { 10125 __le16 req_type; 10126 __le16 cmpl_ring; 10127 __le16 seq_id; 10128 __le16 target_id; 10129 __le64 resp_addr; 10130 __le16 dir_type; 10131 __le16 dir_ordinal; 10132 __le16 dir_ext; 10133 u8 unused_0[2]; 10134 }; 10135 10136 /* hwrm_nvm_verify_update_output (size:128b/16B) */ 10137 struct hwrm_nvm_verify_update_output { 10138 __le16 error_code; 10139 __le16 req_type; 10140 __le16 seq_id; 10141 __le16 resp_len; 10142 u8 unused_0[7]; 10143 u8 valid; 10144 }; 10145 10146 /* hwrm_nvm_install_update_input (size:192b/24B) */ 10147 struct hwrm_nvm_install_update_input { 10148 __le16 req_type; 10149 __le16 cmpl_ring; 10150 __le16 seq_id; 10151 __le16 target_id; 10152 __le64 resp_addr; 10153 __le32 install_type; 10154 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 10155 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 10156 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 10157 __le16 flags; 10158 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 10159 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 10160 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 10161 #define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY 0x8UL 10162 u8 unused_0[2]; 10163 }; 10164 10165 /* hwrm_nvm_install_update_output (size:192b/24B) */ 10166 struct hwrm_nvm_install_update_output { 10167 __le16 error_code; 10168 __le16 req_type; 10169 __le16 seq_id; 10170 __le16 resp_len; 10171 __le64 installed_items; 10172 u8 result; 10173 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 10174 #define NVM_INSTALL_UPDATE_RESP_RESULT_FAILURE 0xffUL 10175 #define NVM_INSTALL_UPDATE_RESP_RESULT_MALLOC_FAILURE 0xfdUL 10176 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER 0xfbUL 10177 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER 0xf3UL 10178 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE 0xf2UL 10179 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER 0xecUL 10180 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE 0xebUL 10181 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM 0xeaUL 10182 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH 0xe9UL 10183 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST 0xe8UL 10184 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER 0xe7UL 10185 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM 0xe6UL 10186 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM 0xe5UL 10187 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH 0xe4UL 10188 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE 0xe1UL 10189 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV 0xceUL 10190 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID 0xcdUL 10191 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR 0xccUL 10192 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID 0xcbUL 10193 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM 0xc5UL 10194 #define NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM 0xc4UL 10195 #define NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM 0xc3UL 10196 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR 0xb9UL 10197 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR 0xb8UL 10198 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR 0xb7UL 10199 #define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND 0xb0UL 10200 #define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED 0xa7UL 10201 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED 10202 u8 problem_item; 10203 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 10204 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 10205 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 10206 u8 reset_required; 10207 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 10208 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 10209 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 10210 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 10211 u8 unused_0[4]; 10212 u8 valid; 10213 }; 10214 10215 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 10216 struct hwrm_nvm_install_update_cmd_err { 10217 u8 code; 10218 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 10219 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 10220 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 10221 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK 0x3UL 10222 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT 0x4UL 10223 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT 10224 u8 unused_0[7]; 10225 }; 10226 10227 /* hwrm_nvm_get_variable_input (size:320b/40B) */ 10228 struct hwrm_nvm_get_variable_input { 10229 __le16 req_type; 10230 __le16 cmpl_ring; 10231 __le16 seq_id; 10232 __le16 target_id; 10233 __le64 resp_addr; 10234 __le64 dest_data_addr; 10235 __le16 data_len; 10236 __le16 option_num; 10237 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 10238 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 10239 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 10240 __le16 dimensions; 10241 __le16 index_0; 10242 __le16 index_1; 10243 __le16 index_2; 10244 __le16 index_3; 10245 u8 flags; 10246 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 10247 u8 unused_0; 10248 }; 10249 10250 /* hwrm_nvm_get_variable_output (size:128b/16B) */ 10251 struct hwrm_nvm_get_variable_output { 10252 __le16 error_code; 10253 __le16 req_type; 10254 __le16 seq_id; 10255 __le16 resp_len; 10256 __le16 data_len; 10257 __le16 option_num; 10258 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 10259 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 10260 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 10261 u8 unused_0[3]; 10262 u8 valid; 10263 }; 10264 10265 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 10266 struct hwrm_nvm_get_variable_cmd_err { 10267 u8 code; 10268 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 10269 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 10270 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 10271 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 10272 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 10273 u8 unused_0[7]; 10274 }; 10275 10276 /* hwrm_nvm_set_variable_input (size:320b/40B) */ 10277 struct hwrm_nvm_set_variable_input { 10278 __le16 req_type; 10279 __le16 cmpl_ring; 10280 __le16 seq_id; 10281 __le16 target_id; 10282 __le64 resp_addr; 10283 __le64 src_data_addr; 10284 __le16 data_len; 10285 __le16 option_num; 10286 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 10287 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 10288 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 10289 __le16 dimensions; 10290 __le16 index_0; 10291 __le16 index_1; 10292 __le16 index_2; 10293 __le16 index_3; 10294 u8 flags; 10295 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 10296 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 10297 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 10298 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 10299 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 10300 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 10301 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 10302 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 10303 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL 10304 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4 10305 #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL 10306 u8 unused_0; 10307 }; 10308 10309 /* hwrm_nvm_set_variable_output (size:128b/16B) */ 10310 struct hwrm_nvm_set_variable_output { 10311 __le16 error_code; 10312 __le16 req_type; 10313 __le16 seq_id; 10314 __le16 resp_len; 10315 u8 unused_0[7]; 10316 u8 valid; 10317 }; 10318 10319 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 10320 struct hwrm_nvm_set_variable_cmd_err { 10321 u8 code; 10322 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 10323 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 10324 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 10325 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 10326 u8 unused_0[7]; 10327 }; 10328 10329 /* hwrm_selftest_qlist_input (size:128b/16B) */ 10330 struct hwrm_selftest_qlist_input { 10331 __le16 req_type; 10332 __le16 cmpl_ring; 10333 __le16 seq_id; 10334 __le16 target_id; 10335 __le64 resp_addr; 10336 }; 10337 10338 /* hwrm_selftest_qlist_output (size:2240b/280B) */ 10339 struct hwrm_selftest_qlist_output { 10340 __le16 error_code; 10341 __le16 req_type; 10342 __le16 seq_id; 10343 __le16 resp_len; 10344 u8 num_tests; 10345 u8 available_tests; 10346 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 10347 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 10348 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 10349 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 10350 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 10351 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 10352 u8 offline_tests; 10353 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 10354 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 10355 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 10356 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 10357 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 10358 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 10359 u8 unused_0; 10360 __le16 test_timeout; 10361 u8 unused_1[2]; 10362 char test_name[8][32]; 10363 u8 eyescope_target_BER_support; 10364 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED 0x0UL 10365 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED 0x1UL 10366 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL 10367 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL 10368 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL 10369 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 10370 u8 unused_2[6]; 10371 u8 valid; 10372 }; 10373 10374 /* hwrm_selftest_exec_input (size:192b/24B) */ 10375 struct hwrm_selftest_exec_input { 10376 __le16 req_type; 10377 __le16 cmpl_ring; 10378 __le16 seq_id; 10379 __le16 target_id; 10380 __le64 resp_addr; 10381 u8 flags; 10382 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 10383 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 10384 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 10385 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 10386 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 10387 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 10388 u8 unused_0[7]; 10389 }; 10390 10391 /* hwrm_selftest_exec_output (size:128b/16B) */ 10392 struct hwrm_selftest_exec_output { 10393 __le16 error_code; 10394 __le16 req_type; 10395 __le16 seq_id; 10396 __le16 resp_len; 10397 u8 requested_tests; 10398 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 10399 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 10400 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 10401 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 10402 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 10403 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 10404 u8 test_success; 10405 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 10406 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 10407 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 10408 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 10409 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 10410 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 10411 u8 unused_0[5]; 10412 u8 valid; 10413 }; 10414 10415 /* hwrm_selftest_irq_input (size:128b/16B) */ 10416 struct hwrm_selftest_irq_input { 10417 __le16 req_type; 10418 __le16 cmpl_ring; 10419 __le16 seq_id; 10420 __le16 target_id; 10421 __le64 resp_addr; 10422 }; 10423 10424 /* hwrm_selftest_irq_output (size:128b/16B) */ 10425 struct hwrm_selftest_irq_output { 10426 __le16 error_code; 10427 __le16 req_type; 10428 __le16 seq_id; 10429 __le16 resp_len; 10430 u8 unused_0[7]; 10431 u8 valid; 10432 }; 10433 10434 /* dbc_dbc (size:64b/8B) */ 10435 struct dbc_dbc { 10436 u32 index; 10437 #define DBC_DBC_INDEX_MASK 0xffffffUL 10438 #define DBC_DBC_INDEX_SFT 0 10439 #define DBC_DBC_EPOCH 0x1000000UL 10440 #define DBC_DBC_TOGGLE_MASK 0x6000000UL 10441 #define DBC_DBC_TOGGLE_SFT 25 10442 u32 type_path_xid; 10443 #define DBC_DBC_XID_MASK 0xfffffUL 10444 #define DBC_DBC_XID_SFT 0 10445 #define DBC_DBC_PATH_MASK 0x3000000UL 10446 #define DBC_DBC_PATH_SFT 24 10447 #define DBC_DBC_PATH_ROCE (0x0UL << 24) 10448 #define DBC_DBC_PATH_L2 (0x1UL << 24) 10449 #define DBC_DBC_PATH_ENGINE (0x2UL << 24) 10450 #define DBC_DBC_PATH_LAST DBC_DBC_PATH_ENGINE 10451 #define DBC_DBC_VALID 0x4000000UL 10452 #define DBC_DBC_DEBUG_TRACE 0x8000000UL 10453 #define DBC_DBC_TYPE_MASK 0xf0000000UL 10454 #define DBC_DBC_TYPE_SFT 28 10455 #define DBC_DBC_TYPE_SQ (0x0UL << 28) 10456 #define DBC_DBC_TYPE_RQ (0x1UL << 28) 10457 #define DBC_DBC_TYPE_SRQ (0x2UL << 28) 10458 #define DBC_DBC_TYPE_SRQ_ARM (0x3UL << 28) 10459 #define DBC_DBC_TYPE_CQ (0x4UL << 28) 10460 #define DBC_DBC_TYPE_CQ_ARMSE (0x5UL << 28) 10461 #define DBC_DBC_TYPE_CQ_ARMALL (0x6UL << 28) 10462 #define DBC_DBC_TYPE_CQ_ARMENA (0x7UL << 28) 10463 #define DBC_DBC_TYPE_SRQ_ARMENA (0x8UL << 28) 10464 #define DBC_DBC_TYPE_CQ_CUTOFF_ACK (0x9UL << 28) 10465 #define DBC_DBC_TYPE_NQ (0xaUL << 28) 10466 #define DBC_DBC_TYPE_NQ_ARM (0xbUL << 28) 10467 #define DBC_DBC_TYPE_NQ_MASK (0xeUL << 28) 10468 #define DBC_DBC_TYPE_NULL (0xfUL << 28) 10469 #define DBC_DBC_TYPE_LAST DBC_DBC_TYPE_NULL 10470 }; 10471 10472 /* db_push_start (size:64b/8B) */ 10473 struct db_push_start { 10474 u64 db; 10475 #define DB_PUSH_START_DB_INDEX_MASK 0xffffffUL 10476 #define DB_PUSH_START_DB_INDEX_SFT 0 10477 #define DB_PUSH_START_DB_PI_LO_MASK 0xff000000UL 10478 #define DB_PUSH_START_DB_PI_LO_SFT 24 10479 #define DB_PUSH_START_DB_XID_MASK 0xfffff00000000ULL 10480 #define DB_PUSH_START_DB_XID_SFT 32 10481 #define DB_PUSH_START_DB_PI_HI_MASK 0xf0000000000000ULL 10482 #define DB_PUSH_START_DB_PI_HI_SFT 52 10483 #define DB_PUSH_START_DB_TYPE_MASK 0xf000000000000000ULL 10484 #define DB_PUSH_START_DB_TYPE_SFT 60 10485 #define DB_PUSH_START_DB_TYPE_PUSH_START (0xcULL << 60) 10486 #define DB_PUSH_START_DB_TYPE_PUSH_END (0xdULL << 60) 10487 #define DB_PUSH_START_DB_TYPE_LAST DB_PUSH_START_DB_TYPE_PUSH_END 10488 }; 10489 10490 /* db_push_end (size:64b/8B) */ 10491 struct db_push_end { 10492 u64 db; 10493 #define DB_PUSH_END_DB_INDEX_MASK 0xffffffUL 10494 #define DB_PUSH_END_DB_INDEX_SFT 0 10495 #define DB_PUSH_END_DB_PI_LO_MASK 0xff000000UL 10496 #define DB_PUSH_END_DB_PI_LO_SFT 24 10497 #define DB_PUSH_END_DB_XID_MASK 0xfffff00000000ULL 10498 #define DB_PUSH_END_DB_XID_SFT 32 10499 #define DB_PUSH_END_DB_PI_HI_MASK 0xf0000000000000ULL 10500 #define DB_PUSH_END_DB_PI_HI_SFT 52 10501 #define DB_PUSH_END_DB_PATH_MASK 0x300000000000000ULL 10502 #define DB_PUSH_END_DB_PATH_SFT 56 10503 #define DB_PUSH_END_DB_PATH_ROCE (0x0ULL << 56) 10504 #define DB_PUSH_END_DB_PATH_L2 (0x1ULL << 56) 10505 #define DB_PUSH_END_DB_PATH_ENGINE (0x2ULL << 56) 10506 #define DB_PUSH_END_DB_PATH_LAST DB_PUSH_END_DB_PATH_ENGINE 10507 #define DB_PUSH_END_DB_DEBUG_TRACE 0x800000000000000ULL 10508 #define DB_PUSH_END_DB_TYPE_MASK 0xf000000000000000ULL 10509 #define DB_PUSH_END_DB_TYPE_SFT 60 10510 #define DB_PUSH_END_DB_TYPE_PUSH_START (0xcULL << 60) 10511 #define DB_PUSH_END_DB_TYPE_PUSH_END (0xdULL << 60) 10512 #define DB_PUSH_END_DB_TYPE_LAST DB_PUSH_END_DB_TYPE_PUSH_END 10513 }; 10514 10515 /* db_push_info (size:64b/8B) */ 10516 struct db_push_info { 10517 u32 push_size_push_index; 10518 #define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL 10519 #define DB_PUSH_INFO_PUSH_INDEX_SFT 0 10520 #define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL 10521 #define DB_PUSH_INFO_PUSH_SIZE_SFT 24 10522 u32 reserved32; 10523 }; 10524 10525 /* fw_status_reg (size:32b/4B) */ 10526 struct fw_status_reg { 10527 u32 fw_status; 10528 #define FW_STATUS_REG_CODE_MASK 0xffffUL 10529 #define FW_STATUS_REG_CODE_SFT 0 10530 #define FW_STATUS_REG_CODE_READY 0x8000UL 10531 #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY 10532 #define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL 10533 #define FW_STATUS_REG_RECOVERABLE 0x20000UL 10534 #define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL 10535 #define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL 10536 #define FW_STATUS_REG_SHUTDOWN 0x100000UL 10537 #define FW_STATUS_REG_CRASHED_NO_MASTER 0x200000UL 10538 #define FW_STATUS_REG_RECOVERING 0x400000UL 10539 #define FW_STATUS_REG_MANU_DEBUG_STATUS 0x800000UL 10540 }; 10541 10542 /* hcomm_status (size:64b/8B) */ 10543 struct hcomm_status { 10544 u32 sig_ver; 10545 #define HCOMM_STATUS_VER_MASK 0xffUL 10546 #define HCOMM_STATUS_VER_SFT 0 10547 #define HCOMM_STATUS_VER_LATEST 0x1UL 10548 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST 10549 #define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL 10550 #define HCOMM_STATUS_SIGNATURE_SFT 8 10551 #define HCOMM_STATUS_SIGNATURE_VAL (0x484353UL << 8) 10552 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL 10553 u32 fw_status_loc; 10554 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK 0x3UL 10555 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 10556 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG 0x0UL 10557 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC 0x1UL 10558 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 0x2UL 10559 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 0x3UL 10560 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 10561 #define HCOMM_STATUS_TRUE_OFFSET_MASK 0xfffffffcUL 10562 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 10563 }; 10564 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL 10565 10566 #endif /* _BNXT_HSI_H_ */ 10567