1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2014-2018 Broadcom Limited 5 * Copyright (c) 2018-2023 Broadcom Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * DO NOT MODIFY!!! This file is automatically generated. 12 */ 13 14 #ifndef _BNXT_HSI_H_ 15 #define _BNXT_HSI_H_ 16 17 /* hwrm_cmd_hdr (size:128b/16B) */ 18 struct hwrm_cmd_hdr { 19 __le16 req_type; 20 __le16 cmpl_ring; 21 __le16 seq_id; 22 __le16 target_id; 23 __le64 resp_addr; 24 }; 25 26 /* hwrm_resp_hdr (size:64b/8B) */ 27 struct hwrm_resp_hdr { 28 __le16 error_code; 29 __le16 req_type; 30 __le16 seq_id; 31 __le16 resp_len; 32 }; 33 34 #define CMD_DISCR_TLV_ENCAP 0x8000UL 35 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 36 37 38 #define TLV_TYPE_HWRM_REQUEST 0x1UL 39 #define TLV_TYPE_HWRM_RESPONSE 0x2UL 40 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 41 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 42 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 43 #define TLV_TYPE_QUERY_ROCE_CC_GEN2 0x6UL 44 #define TLV_TYPE_MODIFY_ROCE_CC_GEN2 0x7UL 45 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL 46 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 47 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 48 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 49 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL 50 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL 51 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 52 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL 53 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL 54 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 55 56 57 /* tlv (size:64b/8B) */ 58 struct tlv { 59 __le16 cmd_discr; 60 u8 reserved_8b; 61 u8 flags; 62 #define TLV_FLAGS_MORE 0x1UL 63 #define TLV_FLAGS_MORE_LAST 0x0UL 64 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 65 #define TLV_FLAGS_REQUIRED 0x2UL 66 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 67 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 68 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 69 __le16 tlv_type; 70 __le16 length; 71 }; 72 73 /* input (size:128b/16B) */ 74 struct input { 75 __le16 req_type; 76 __le16 cmpl_ring; 77 __le16 seq_id; 78 __le16 target_id; 79 __le64 resp_addr; 80 }; 81 82 /* output (size:64b/8B) */ 83 struct output { 84 __le16 error_code; 85 __le16 req_type; 86 __le16 seq_id; 87 __le16 resp_len; 88 }; 89 90 /* hwrm_short_input (size:128b/16B) */ 91 struct hwrm_short_input { 92 __le16 req_type; 93 __le16 signature; 94 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 95 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 96 __le16 target_id; 97 #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL 98 #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL 99 #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS 100 __le16 size; 101 __le64 req_addr; 102 }; 103 104 /* cmd_nums (size:64b/8B) */ 105 struct cmd_nums { 106 __le16 req_type; 107 #define HWRM_VER_GET 0x0UL 108 #define HWRM_FUNC_ECHO_RESPONSE 0xbUL 109 #define HWRM_ERROR_RECOVERY_QCFG 0xcUL 110 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 111 #define HWRM_FUNC_BUF_UNRGTR 0xeUL 112 #define HWRM_FUNC_VF_CFG 0xfUL 113 #define HWRM_RESERVED1 0x10UL 114 #define HWRM_FUNC_RESET 0x11UL 115 #define HWRM_FUNC_GETFID 0x12UL 116 #define HWRM_FUNC_VF_ALLOC 0x13UL 117 #define HWRM_FUNC_VF_FREE 0x14UL 118 #define HWRM_FUNC_QCAPS 0x15UL 119 #define HWRM_FUNC_QCFG 0x16UL 120 #define HWRM_FUNC_CFG 0x17UL 121 #define HWRM_FUNC_QSTATS 0x18UL 122 #define HWRM_FUNC_CLR_STATS 0x19UL 123 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 124 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 125 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 126 #define HWRM_FUNC_DRV_RGTR 0x1dUL 127 #define HWRM_FUNC_DRV_QVER 0x1eUL 128 #define HWRM_FUNC_BUF_RGTR 0x1fUL 129 #define HWRM_PORT_PHY_CFG 0x20UL 130 #define HWRM_PORT_MAC_CFG 0x21UL 131 #define HWRM_PORT_TS_QUERY 0x22UL 132 #define HWRM_PORT_QSTATS 0x23UL 133 #define HWRM_PORT_LPBK_QSTATS 0x24UL 134 #define HWRM_PORT_CLR_STATS 0x25UL 135 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 136 #define HWRM_PORT_PHY_QCFG 0x27UL 137 #define HWRM_PORT_MAC_QCFG 0x28UL 138 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 139 #define HWRM_PORT_PHY_QCAPS 0x2aUL 140 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 141 #define HWRM_PORT_PHY_I2C_READ 0x2cUL 142 #define HWRM_PORT_LED_CFG 0x2dUL 143 #define HWRM_PORT_LED_QCFG 0x2eUL 144 #define HWRM_PORT_LED_QCAPS 0x2fUL 145 #define HWRM_QUEUE_QPORTCFG 0x30UL 146 #define HWRM_QUEUE_QCFG 0x31UL 147 #define HWRM_QUEUE_CFG 0x32UL 148 #define HWRM_FUNC_VLAN_CFG 0x33UL 149 #define HWRM_FUNC_VLAN_QCFG 0x34UL 150 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 151 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 152 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 153 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 154 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 155 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 156 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 157 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 158 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 159 #define HWRM_VNIC_ALLOC 0x40UL 160 #define HWRM_VNIC_FREE 0x41UL 161 #define HWRM_VNIC_CFG 0x42UL 162 #define HWRM_VNIC_QCFG 0x43UL 163 #define HWRM_VNIC_TPA_CFG 0x44UL 164 #define HWRM_VNIC_TPA_QCFG 0x45UL 165 #define HWRM_VNIC_RSS_CFG 0x46UL 166 #define HWRM_VNIC_RSS_QCFG 0x47UL 167 #define HWRM_VNIC_PLCMODES_CFG 0x48UL 168 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 169 #define HWRM_VNIC_QCAPS 0x4aUL 170 #define HWRM_VNIC_UPDATE 0x4bUL 171 #define HWRM_RING_ALLOC 0x50UL 172 #define HWRM_RING_FREE 0x51UL 173 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 174 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 175 #define HWRM_RING_AGGINT_QCAPS 0x54UL 176 #define HWRM_RING_SCHQ_ALLOC 0x55UL 177 #define HWRM_RING_SCHQ_CFG 0x56UL 178 #define HWRM_RING_SCHQ_FREE 0x57UL 179 #define HWRM_RING_RESET 0x5eUL 180 #define HWRM_RING_GRP_ALLOC 0x60UL 181 #define HWRM_RING_GRP_FREE 0x61UL 182 #define HWRM_RING_CFG 0x62UL 183 #define HWRM_RING_QCFG 0x63UL 184 #define HWRM_RESERVED5 0x64UL 185 #define HWRM_RESERVED6 0x65UL 186 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 187 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 188 #define HWRM_QUEUE_MPLS_QCAPS 0x80UL 189 #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL 190 #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL 191 #define HWRM_QUEUE_VLANPRI_QCAPS 0x83UL 192 #define HWRM_QUEUE_VLANPRI2PRI_QCFG 0x84UL 193 #define HWRM_QUEUE_VLANPRI2PRI_CFG 0x85UL 194 #define HWRM_QUEUE_GLOBAL_CFG 0x86UL 195 #define HWRM_QUEUE_GLOBAL_QCFG 0x87UL 196 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG 0x88UL 197 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG 0x89UL 198 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG 0x8aUL 199 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG 0x8bUL 200 #define HWRM_QUEUE_QCAPS 0x8cUL 201 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_QCFG 0x8dUL 202 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG 0x8eUL 203 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_QCFG 0x8fUL 204 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 205 #define HWRM_CFA_L2_FILTER_FREE 0x91UL 206 #define HWRM_CFA_L2_FILTER_CFG 0x92UL 207 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 208 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 209 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 210 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 211 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 212 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 213 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 214 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 215 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 216 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 217 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 218 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 219 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 220 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 221 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 222 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG 0xa3UL 223 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 224 #define HWRM_STAT_CTX_ALLOC 0xb0UL 225 #define HWRM_STAT_CTX_FREE 0xb1UL 226 #define HWRM_STAT_CTX_QUERY 0xb2UL 227 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 228 #define HWRM_PORT_QSTATS_EXT 0xb4UL 229 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL 230 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL 231 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL 232 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL 233 #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL 234 #define HWRM_RESERVED7 0xbaUL 235 #define HWRM_PORT_TX_FIR_CFG 0xbbUL 236 #define HWRM_PORT_TX_FIR_QCFG 0xbcUL 237 #define HWRM_PORT_ECN_QSTATS 0xbdUL 238 #define HWRM_FW_LIVEPATCH_QUERY 0xbeUL 239 #define HWRM_FW_LIVEPATCH 0xbfUL 240 #define HWRM_FW_RESET 0xc0UL 241 #define HWRM_FW_QSTATUS 0xc1UL 242 #define HWRM_FW_HEALTH_CHECK 0xc2UL 243 #define HWRM_FW_SYNC 0xc3UL 244 #define HWRM_FW_STATE_QCAPS 0xc4UL 245 #define HWRM_FW_STATE_QUIESCE 0xc5UL 246 #define HWRM_FW_STATE_BACKUP 0xc6UL 247 #define HWRM_FW_STATE_RESTORE 0xc7UL 248 #define HWRM_FW_SET_TIME 0xc8UL 249 #define HWRM_FW_GET_TIME 0xc9UL 250 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 251 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 252 #define HWRM_FW_IPC_MAILBOX 0xccUL 253 #define HWRM_FW_ECN_CFG 0xcdUL 254 #define HWRM_FW_ECN_QCFG 0xceUL 255 #define HWRM_FW_SECURE_CFG 0xcfUL 256 #define HWRM_EXEC_FWD_RESP 0xd0UL 257 #define HWRM_REJECT_FWD_RESP 0xd1UL 258 #define HWRM_FWD_RESP 0xd2UL 259 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 260 #define HWRM_OEM_CMD 0xd4UL 261 #define HWRM_PORT_PRBS_TEST 0xd5UL 262 #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL 263 #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL 264 #define HWRM_FW_STATE_UNQUIESCE 0xd8UL 265 #define HWRM_PORT_DSC_DUMP 0xd9UL 266 #define HWRM_PORT_EP_TX_QCFG 0xdaUL 267 #define HWRM_PORT_EP_TX_CFG 0xdbUL 268 #define HWRM_PORT_CFG 0xdcUL 269 #define HWRM_PORT_QCFG 0xddUL 270 #define HWRM_PORT_MAC_QCAPS 0xdfUL 271 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 272 #define HWRM_REG_POWER_QUERY 0xe1UL 273 #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL 274 #define HWRM_REG_POWER_HISTOGRAM 0xe3UL 275 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 276 #define HWRM_WOL_FILTER_FREE 0xf1UL 277 #define HWRM_WOL_FILTER_QCFG 0xf2UL 278 #define HWRM_WOL_REASON_QCFG 0xf3UL 279 #define HWRM_CFA_METER_QCAPS 0xf4UL 280 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 281 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 282 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 283 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 284 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 285 #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL 286 #define HWRM_CFA_VFR_ALLOC 0xfdUL 287 #define HWRM_CFA_VFR_FREE 0xfeUL 288 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 289 #define HWRM_CFA_VF_PAIR_FREE 0x101UL 290 #define HWRM_CFA_VF_PAIR_INFO 0x102UL 291 #define HWRM_CFA_FLOW_ALLOC 0x103UL 292 #define HWRM_CFA_FLOW_FREE 0x104UL 293 #define HWRM_CFA_FLOW_FLUSH 0x105UL 294 #define HWRM_CFA_FLOW_STATS 0x106UL 295 #define HWRM_CFA_FLOW_INFO 0x107UL 296 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 297 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 298 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 299 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 300 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 301 #define HWRM_CFA_PAIR_ALLOC 0x10dUL 302 #define HWRM_CFA_PAIR_FREE 0x10eUL 303 #define HWRM_CFA_PAIR_INFO 0x10fUL 304 #define HWRM_FW_IPC_MSG 0x110UL 305 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 306 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 307 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL 308 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL 309 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL 310 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL 311 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL 312 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL 313 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL 314 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL 315 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL 316 #define HWRM_CFA_COUNTER_CFG 0x11cUL 317 #define HWRM_CFA_COUNTER_QCFG 0x11dUL 318 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL 319 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL 320 #define HWRM_CFA_EEM_QCAPS 0x120UL 321 #define HWRM_CFA_EEM_CFG 0x121UL 322 #define HWRM_CFA_EEM_QCFG 0x122UL 323 #define HWRM_CFA_EEM_OP 0x123UL 324 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL 325 #define HWRM_CFA_TFLIB 0x125UL 326 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR 0x126UL 327 #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR 0x127UL 328 #define HWRM_CFA_TLS_FILTER_ALLOC 0x128UL 329 #define HWRM_CFA_TLS_FILTER_FREE 0x129UL 330 #define HWRM_CFA_RELEASE_AFM_FUNC 0x12aUL 331 #define HWRM_ENGINE_CKV_STATUS 0x12eUL 332 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 333 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 334 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 335 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 336 #define HWRM_ENGINE_CKV_FLUSH 0x133UL 337 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 338 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 339 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL 340 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL 341 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 342 #define HWRM_ENGINE_QG_QUERY 0x13dUL 343 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 344 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 345 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 346 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 347 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 348 #define HWRM_ENGINE_QG_METER_BIND 0x143UL 349 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 350 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 351 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 352 #define HWRM_ENGINE_SG_QUERY 0x147UL 353 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 354 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 355 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 356 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 357 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 358 #define HWRM_ENGINE_STATS_CONFIG 0x155UL 359 #define HWRM_ENGINE_STATS_CLEAR 0x156UL 360 #define HWRM_ENGINE_STATS_QUERY 0x157UL 361 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL 362 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 363 #define HWRM_ENGINE_RQ_FREE 0x15fUL 364 #define HWRM_ENGINE_CQ_ALLOC 0x160UL 365 #define HWRM_ENGINE_CQ_FREE 0x161UL 366 #define HWRM_ENGINE_NQ_ALLOC 0x162UL 367 #define HWRM_ENGINE_NQ_FREE 0x163UL 368 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 369 #define HWRM_ENGINE_FUNC_QCFG 0x165UL 370 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 371 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 372 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 373 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 374 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 375 #define HWRM_FUNC_VF_BW_CFG 0x195UL 376 #define HWRM_FUNC_VF_BW_QCFG 0x196UL 377 #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL 378 #define HWRM_FUNC_QSTATS_EXT 0x198UL 379 #define HWRM_STAT_EXT_CTX_QUERY 0x199UL 380 #define HWRM_FUNC_SPD_CFG 0x19aUL 381 #define HWRM_FUNC_SPD_QCFG 0x19bUL 382 #define HWRM_FUNC_PTP_PIN_QCFG 0x19cUL 383 #define HWRM_FUNC_PTP_PIN_CFG 0x19dUL 384 #define HWRM_FUNC_PTP_CFG 0x19eUL 385 #define HWRM_FUNC_PTP_TS_QUERY 0x19fUL 386 #define HWRM_FUNC_PTP_EXT_CFG 0x1a0UL 387 #define HWRM_FUNC_PTP_EXT_QCFG 0x1a1UL 388 #define HWRM_FUNC_KEY_CTX_ALLOC 0x1a2UL 389 #define HWRM_FUNC_BACKING_STORE_CFG_V2 0x1a3UL 390 #define HWRM_FUNC_BACKING_STORE_QCFG_V2 0x1a4UL 391 #define HWRM_FUNC_DBR_PACING_CFG 0x1a5UL 392 #define HWRM_FUNC_DBR_PACING_QCFG 0x1a6UL 393 #define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT 0x1a7UL 394 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2 0x1a8UL 395 #define HWRM_FUNC_DBR_PACING_NQLIST_QUERY 0x1a9UL 396 #define HWRM_FUNC_DBR_RECOVERY_COMPLETED 0x1aaUL 397 #define HWRM_FUNC_SYNCE_CFG 0x1abUL 398 #define HWRM_FUNC_SYNCE_QCFG 0x1acUL 399 #define HWRM_FUNC_KEY_CTX_FREE 0x1adUL 400 #define HWRM_FUNC_LAG_MODE_CFG 0x1aeUL 401 #define HWRM_FUNC_LAG_MODE_QCFG 0x1afUL 402 #define HWRM_FUNC_LAG_CREATE 0x1b0UL 403 #define HWRM_FUNC_LAG_UPDATE 0x1b1UL 404 #define HWRM_FUNC_LAG_FREE 0x1b2UL 405 #define HWRM_FUNC_LAG_QCFG 0x1b3UL 406 #define HWRM_SELFTEST_QLIST 0x200UL 407 #define HWRM_SELFTEST_EXEC 0x201UL 408 #define HWRM_SELFTEST_IRQ 0x202UL 409 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 410 #define HWRM_PCIE_QSTATS 0x204UL 411 #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL 412 #define HWRM_MFG_TIMERS_QUERY 0x206UL 413 #define HWRM_MFG_OTP_CFG 0x207UL 414 #define HWRM_MFG_OTP_QCFG 0x208UL 415 #define HWRM_MFG_HDMA_TEST 0x209UL 416 #define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL 417 #define HWRM_MFG_FRU_EEPROM_READ 0x20bUL 418 #define HWRM_MFG_SOC_IMAGE 0x20cUL 419 #define HWRM_MFG_SOC_QSTATUS 0x20dUL 420 #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE 0x20eUL 421 #define HWRM_MFG_PARAM_CRITICAL_DATA_READ 0x20fUL 422 #define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH 0x210UL 423 #define HWRM_MFG_PRVSN_EXPORT_CSR 0x211UL 424 #define HWRM_MFG_PRVSN_IMPORT_CERT 0x212UL 425 #define HWRM_MFG_PRVSN_GET_STATE 0x213UL 426 #define HWRM_MFG_GET_NVM_MEASUREMENT 0x214UL 427 #define HWRM_MFG_PSOC_QSTATUS 0x215UL 428 #define HWRM_MFG_SELFTEST_QLIST 0x216UL 429 #define HWRM_MFG_SELFTEST_EXEC 0x217UL 430 #define HWRM_STAT_GENERIC_QSTATS 0x218UL 431 #define HWRM_MFG_PRVSN_EXPORT_CERT 0x219UL 432 #define HWRM_STAT_DB_ERROR_QSTATS 0x21aUL 433 #define HWRM_UDCC_QCAPS 0x258UL 434 #define HWRM_UDCC_CFG 0x259UL 435 #define HWRM_UDCC_QCFG 0x25aUL 436 #define HWRM_UDCC_SESSION_CFG 0x25bUL 437 #define HWRM_UDCC_SESSION_QCFG 0x25cUL 438 #define HWRM_UDCC_SESSION_QUERY 0x25dUL 439 #define HWRM_UDCC_COMP_CFG 0x25eUL 440 #define HWRM_UDCC_COMP_QCFG 0x25fUL 441 #define HWRM_UDCC_COMP_QUERY 0x260UL 442 #define HWRM_TF 0x2bcUL 443 #define HWRM_TF_VERSION_GET 0x2bdUL 444 #define HWRM_TF_SESSION_OPEN 0x2c6UL 445 #define HWRM_TF_SESSION_REGISTER 0x2c8UL 446 #define HWRM_TF_SESSION_UNREGISTER 0x2c9UL 447 #define HWRM_TF_SESSION_CLOSE 0x2caUL 448 #define HWRM_TF_SESSION_QCFG 0x2cbUL 449 #define HWRM_TF_SESSION_RESC_QCAPS 0x2ccUL 450 #define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL 451 #define HWRM_TF_SESSION_RESC_FREE 0x2ceUL 452 #define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL 453 #define HWRM_TF_SESSION_RESC_INFO 0x2d0UL 454 #define HWRM_TF_SESSION_HOTUP_STATE_SET 0x2d1UL 455 #define HWRM_TF_SESSION_HOTUP_STATE_GET 0x2d2UL 456 #define HWRM_TF_TBL_TYPE_GET 0x2daUL 457 #define HWRM_TF_TBL_TYPE_SET 0x2dbUL 458 #define HWRM_TF_TBL_TYPE_BULK_GET 0x2dcUL 459 #define HWRM_TF_EM_INSERT 0x2eaUL 460 #define HWRM_TF_EM_DELETE 0x2ebUL 461 #define HWRM_TF_EM_HASH_INSERT 0x2ecUL 462 #define HWRM_TF_EM_MOVE 0x2edUL 463 #define HWRM_TF_TCAM_SET 0x2f8UL 464 #define HWRM_TF_TCAM_GET 0x2f9UL 465 #define HWRM_TF_TCAM_MOVE 0x2faUL 466 #define HWRM_TF_TCAM_FREE 0x2fbUL 467 #define HWRM_TF_GLOBAL_CFG_SET 0x2fcUL 468 #define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL 469 #define HWRM_TF_IF_TBL_SET 0x2feUL 470 #define HWRM_TF_IF_TBL_GET 0x2ffUL 471 #define HWRM_TFC_TBL_SCOPE_QCAPS 0x380UL 472 #define HWRM_TFC_TBL_SCOPE_ID_ALLOC 0x381UL 473 #define HWRM_TFC_TBL_SCOPE_CONFIG 0x382UL 474 #define HWRM_TFC_TBL_SCOPE_DECONFIG 0x383UL 475 #define HWRM_TFC_TBL_SCOPE_FID_ADD 0x384UL 476 #define HWRM_TFC_TBL_SCOPE_FID_REM 0x385UL 477 #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC 0x386UL 478 #define HWRM_TFC_TBL_SCOPE_POOL_FREE 0x387UL 479 #define HWRM_TFC_SESSION_ID_ALLOC 0x388UL 480 #define HWRM_TFC_SESSION_FID_ADD 0x389UL 481 #define HWRM_TFC_SESSION_FID_REM 0x38aUL 482 #define HWRM_TFC_IDENT_ALLOC 0x38bUL 483 #define HWRM_TFC_IDENT_FREE 0x38cUL 484 #define HWRM_TFC_IDX_TBL_ALLOC 0x38dUL 485 #define HWRM_TFC_IDX_TBL_ALLOC_SET 0x38eUL 486 #define HWRM_TFC_IDX_TBL_SET 0x38fUL 487 #define HWRM_TFC_IDX_TBL_GET 0x390UL 488 #define HWRM_TFC_IDX_TBL_FREE 0x391UL 489 #define HWRM_TFC_GLOBAL_ID_ALLOC 0x392UL 490 #define HWRM_TFC_TCAM_SET 0x393UL 491 #define HWRM_TFC_TCAM_GET 0x394UL 492 #define HWRM_TFC_TCAM_ALLOC 0x395UL 493 #define HWRM_TFC_TCAM_ALLOC_SET 0x396UL 494 #define HWRM_TFC_TCAM_FREE 0x397UL 495 #define HWRM_TFC_IF_TBL_SET 0x398UL 496 #define HWRM_TFC_IF_TBL_GET 0x399UL 497 #define HWRM_TFC_TBL_SCOPE_CONFIG_GET 0x39aUL 498 #define HWRM_SV 0x400UL 499 #define HWRM_DBG_READ_DIRECT 0xff10UL 500 #define HWRM_DBG_READ_INDIRECT 0xff11UL 501 #define HWRM_DBG_WRITE_DIRECT 0xff12UL 502 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 503 #define HWRM_DBG_DUMP 0xff14UL 504 #define HWRM_DBG_ERASE_NVM 0xff15UL 505 #define HWRM_DBG_CFG 0xff16UL 506 #define HWRM_DBG_COREDUMP_LIST 0xff17UL 507 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 508 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 509 #define HWRM_DBG_FW_CLI 0xff1aUL 510 #define HWRM_DBG_I2C_CMD 0xff1bUL 511 #define HWRM_DBG_RING_INFO_GET 0xff1cUL 512 #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL 513 #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL 514 #define HWRM_DBG_DRV_TRACE 0xff1fUL 515 #define HWRM_DBG_QCAPS 0xff20UL 516 #define HWRM_DBG_QCFG 0xff21UL 517 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL 518 #define HWRM_DBG_USEQ_ALLOC 0xff23UL 519 #define HWRM_DBG_USEQ_FREE 0xff24UL 520 #define HWRM_DBG_USEQ_FLUSH 0xff25UL 521 #define HWRM_DBG_USEQ_QCAPS 0xff26UL 522 #define HWRM_DBG_USEQ_CW_CFG 0xff27UL 523 #define HWRM_DBG_USEQ_SCHED_CFG 0xff28UL 524 #define HWRM_DBG_USEQ_RUN 0xff29UL 525 #define HWRM_DBG_USEQ_DELIVERY_REQ 0xff2aUL 526 #define HWRM_DBG_USEQ_RESP_HDR 0xff2bUL 527 #define HWRM_NVM_GET_VPD_FIELD_INFO 0xffeaUL 528 #define HWRM_NVM_SET_VPD_FIELD_INFO 0xffebUL 529 #define HWRM_NVM_DEFRAG 0xffecUL 530 #define HWRM_NVM_REQ_ARBITRATION 0xffedUL 531 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 532 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 533 #define HWRM_NVM_FLUSH 0xfff0UL 534 #define HWRM_NVM_GET_VARIABLE 0xfff1UL 535 #define HWRM_NVM_SET_VARIABLE 0xfff2UL 536 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 537 #define HWRM_NVM_MODIFY 0xfff4UL 538 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 539 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 540 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 541 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 542 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 543 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 544 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 545 #define HWRM_NVM_RAW_DUMP 0xfffcUL 546 #define HWRM_NVM_READ 0xfffdUL 547 #define HWRM_NVM_WRITE 0xfffeUL 548 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 549 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 550 __le16 unused_0[3]; 551 }; 552 553 /* ret_codes (size:64b/8B) */ 554 struct ret_codes { 555 __le16 error_code; 556 #define HWRM_ERR_CODE_SUCCESS 0x0UL 557 #define HWRM_ERR_CODE_FAIL 0x1UL 558 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 559 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 560 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 561 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 562 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 563 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 564 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 565 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 566 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL 567 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL 568 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL 569 #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL 570 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL 571 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 572 #define HWRM_ERR_CODE_BUSY 0x10UL 573 #define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL 574 #define HWRM_ERR_CODE_PF_UNAVAILABLE 0x12UL 575 #define HWRM_ERR_CODE_ENTITY_NOT_PRESENT 0x13UL 576 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 577 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 578 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 579 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 580 __le16 unused_0[3]; 581 }; 582 583 /* hwrm_err_output (size:128b/16B) */ 584 struct hwrm_err_output { 585 __le16 error_code; 586 __le16 req_type; 587 __le16 seq_id; 588 __le16 resp_len; 589 __le32 opaque_0; 590 __le16 opaque_1; 591 u8 cmd_err; 592 u8 valid; 593 }; 594 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 595 #define HWRM_MAX_REQ_LEN 128 596 #define HWRM_MAX_RESP_LEN 704 597 #define HW_HASH_INDEX_SIZE 0x80 598 #define HW_HASH_KEY_SIZE 40 599 #define HWRM_RESP_VALID_KEY 1 600 #define HWRM_TARGET_ID_BONO 0xFFF8 601 #define HWRM_TARGET_ID_KONG 0xFFF9 602 #define HWRM_TARGET_ID_APE 0xFFFA 603 #define HWRM_TARGET_ID_TOOLS 0xFFFD 604 #define HWRM_VERSION_MAJOR 1 605 #define HWRM_VERSION_MINOR 10 606 #define HWRM_VERSION_UPDATE 3 607 #define HWRM_VERSION_RSVD 15 608 #define HWRM_VERSION_STR "1.10.3.15" 609 610 /* hwrm_ver_get_input (size:192b/24B) */ 611 struct hwrm_ver_get_input { 612 __le16 req_type; 613 __le16 cmpl_ring; 614 __le16 seq_id; 615 __le16 target_id; 616 __le64 resp_addr; 617 u8 hwrm_intf_maj; 618 u8 hwrm_intf_min; 619 u8 hwrm_intf_upd; 620 u8 unused_0[5]; 621 }; 622 623 /* hwrm_ver_get_output (size:1408b/176B) */ 624 struct hwrm_ver_get_output { 625 __le16 error_code; 626 __le16 req_type; 627 __le16 seq_id; 628 __le16 resp_len; 629 u8 hwrm_intf_maj_8b; 630 u8 hwrm_intf_min_8b; 631 u8 hwrm_intf_upd_8b; 632 u8 hwrm_intf_rsvd_8b; 633 u8 hwrm_fw_maj_8b; 634 u8 hwrm_fw_min_8b; 635 u8 hwrm_fw_bld_8b; 636 u8 hwrm_fw_rsvd_8b; 637 u8 mgmt_fw_maj_8b; 638 u8 mgmt_fw_min_8b; 639 u8 mgmt_fw_bld_8b; 640 u8 mgmt_fw_rsvd_8b; 641 u8 netctrl_fw_maj_8b; 642 u8 netctrl_fw_min_8b; 643 u8 netctrl_fw_bld_8b; 644 u8 netctrl_fw_rsvd_8b; 645 __le32 dev_caps_cfg; 646 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 647 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 648 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 649 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 650 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 651 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 652 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 653 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 654 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 655 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL 656 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL 657 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL 658 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL 659 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL 660 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL 661 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE 0x8000UL 662 u8 roce_fw_maj_8b; 663 u8 roce_fw_min_8b; 664 u8 roce_fw_bld_8b; 665 u8 roce_fw_rsvd_8b; 666 char hwrm_fw_name[16]; 667 char mgmt_fw_name[16]; 668 char netctrl_fw_name[16]; 669 char active_pkg_name[16]; 670 char roce_fw_name[16]; 671 __le16 chip_num; 672 u8 chip_rev; 673 u8 chip_metal; 674 u8 chip_bond_id; 675 u8 chip_platform_type; 676 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 677 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 678 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 679 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 680 __le16 max_req_win_len; 681 __le16 max_resp_len; 682 __le16 def_req_timeout; 683 u8 flags; 684 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 685 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 686 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY_BACKING_STORE 0x4UL 687 u8 unused_0[2]; 688 u8 always_1; 689 __le16 hwrm_intf_major; 690 __le16 hwrm_intf_minor; 691 __le16 hwrm_intf_build; 692 __le16 hwrm_intf_patch; 693 __le16 hwrm_fw_major; 694 __le16 hwrm_fw_minor; 695 __le16 hwrm_fw_build; 696 __le16 hwrm_fw_patch; 697 __le16 mgmt_fw_major; 698 __le16 mgmt_fw_minor; 699 __le16 mgmt_fw_build; 700 __le16 mgmt_fw_patch; 701 __le16 netctrl_fw_major; 702 __le16 netctrl_fw_minor; 703 __le16 netctrl_fw_build; 704 __le16 netctrl_fw_patch; 705 __le16 roce_fw_major; 706 __le16 roce_fw_minor; 707 __le16 roce_fw_build; 708 __le16 roce_fw_patch; 709 __le16 max_ext_req_len; 710 __le16 max_req_timeout; 711 u8 unused_1[3]; 712 u8 valid; 713 }; 714 715 /* eject_cmpl (size:128b/16B) */ 716 struct eject_cmpl { 717 __le16 type; 718 #define EJECT_CMPL_TYPE_MASK 0x3fUL 719 #define EJECT_CMPL_TYPE_SFT 0 720 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 721 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 722 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL 723 #define EJECT_CMPL_FLAGS_SFT 6 724 #define EJECT_CMPL_FLAGS_ERROR 0x40UL 725 __le16 len; 726 __le32 opaque; 727 __le16 v; 728 #define EJECT_CMPL_V 0x1UL 729 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL 730 #define EJECT_CMPL_ERRORS_SFT 1 731 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL 732 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 733 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1) 734 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1) 735 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1) 736 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1) 737 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH 738 __le16 reserved16; 739 __le32 unused_2; 740 }; 741 742 /* hwrm_cmpl (size:128b/16B) */ 743 struct hwrm_cmpl { 744 __le16 type; 745 #define CMPL_TYPE_MASK 0x3fUL 746 #define CMPL_TYPE_SFT 0 747 #define CMPL_TYPE_HWRM_DONE 0x20UL 748 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 749 __le16 sequence_id; 750 __le32 unused_1; 751 __le32 v; 752 #define CMPL_V 0x1UL 753 __le32 unused_3; 754 }; 755 756 /* hwrm_fwd_req_cmpl (size:128b/16B) */ 757 struct hwrm_fwd_req_cmpl { 758 __le16 req_len_type; 759 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 760 #define FWD_REQ_CMPL_TYPE_SFT 0 761 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 762 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 763 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 764 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 765 __le16 source_id; 766 __le32 unused0; 767 __le32 req_buf_addr_v[2]; 768 #define FWD_REQ_CMPL_V 0x1UL 769 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 770 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 771 }; 772 773 /* hwrm_fwd_resp_cmpl (size:128b/16B) */ 774 struct hwrm_fwd_resp_cmpl { 775 __le16 type; 776 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 777 #define FWD_RESP_CMPL_TYPE_SFT 0 778 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 779 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 780 __le16 source_id; 781 __le16 resp_len; 782 __le16 unused_1; 783 __le32 resp_buf_addr_v[2]; 784 #define FWD_RESP_CMPL_V 0x1UL 785 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 786 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 787 }; 788 789 /* hwrm_async_event_cmpl (size:128b/16B) */ 790 struct hwrm_async_event_cmpl { 791 __le16 type; 792 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 793 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 794 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 795 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 796 __le16 event_id; 797 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 798 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 799 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 800 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 801 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 802 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 803 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 804 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 805 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 806 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL 807 #define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG 0xaUL 808 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 809 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 810 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 811 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 812 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 813 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 814 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 815 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 816 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 817 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 818 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 819 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 820 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL 821 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 822 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 823 #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL 824 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL 825 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL 826 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL 827 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL 828 #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL 829 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL 830 #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL 831 #define ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST 0x42UL 832 #define ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE 0x43UL 833 #define ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP 0x44UL 834 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT 0x45UL 835 #define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD 0x46UL 836 #define ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE 0x47UL 837 #define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE 0x48UL 838 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR 0x49UL 839 #define ASYNC_EVENT_CMPL_EVENT_ID_CTX_ERROR 0x4aUL 840 #define ASYNC_EVENT_CMPL_EVENT_ID_UDCC_SESSION_CHANGE 0x4bUL 841 #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x4cUL 842 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 843 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 844 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 845 __le32 event_data2; 846 u8 opaque_v; 847 #define ASYNC_EVENT_CMPL_V 0x1UL 848 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 849 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 850 u8 timestamp_lo; 851 __le16 timestamp_hi; 852 __le32 event_data1; 853 }; 854 855 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 856 struct hwrm_async_event_cmpl_link_status_change { 857 __le16 type; 858 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 859 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 860 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 861 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 862 __le16 event_id; 863 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 864 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 865 __le32 event_data2; 866 u8 opaque_v; 867 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 868 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 869 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 870 u8 timestamp_lo; 871 __le16 timestamp_hi; 872 __le32 event_data1; 873 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 874 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 875 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 876 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 877 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 878 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 879 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 880 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 881 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 882 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 883 }; 884 885 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 886 struct hwrm_async_event_cmpl_port_conn_not_allowed { 887 __le16 type; 888 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 889 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 890 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 891 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 892 __le16 event_id; 893 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 894 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 895 __le32 event_data2; 896 u8 opaque_v; 897 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 898 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 899 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 900 u8 timestamp_lo; 901 __le16 timestamp_hi; 902 __le32 event_data1; 903 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 904 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 905 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 906 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 907 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 908 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 909 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 910 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 911 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 912 }; 913 914 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 915 struct hwrm_async_event_cmpl_link_speed_cfg_change { 916 __le16 type; 917 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 918 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 919 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 920 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 921 __le16 event_id; 922 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 923 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 924 __le32 event_data2; 925 u8 opaque_v; 926 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 927 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 928 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 929 u8 timestamp_lo; 930 __le16 timestamp_hi; 931 __le32 event_data1; 932 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 933 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 934 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 935 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 936 }; 937 938 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ 939 struct hwrm_async_event_cmpl_reset_notify { 940 __le16 type; 941 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL 942 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 943 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 944 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 945 __le16 event_id; 946 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 947 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 948 __le32 event_data2; 949 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK 0xffffUL 950 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0 951 u8 opaque_v; 952 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 953 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL 954 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 955 u8 timestamp_lo; 956 __le16 timestamp_hi; 957 __le32 event_data1; 958 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL 959 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0 960 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL 961 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL 962 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 963 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL 964 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8 965 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 966 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 967 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 968 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET (0x4UL << 8) 969 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION (0x5UL << 8) 970 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION 971 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 972 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 973 }; 974 975 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ 976 struct hwrm_async_event_cmpl_error_recovery { 977 __le16 type; 978 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL 979 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 980 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 981 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 982 __le16 event_id; 983 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL 984 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 985 __le32 event_data2; 986 u8 opaque_v; 987 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL 988 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL 989 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 990 u8 timestamp_lo; 991 __le16 timestamp_hi; 992 __le32 event_data1; 993 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL 994 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0 995 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL 996 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL 997 }; 998 999 /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */ 1000 struct hwrm_async_event_cmpl_ring_monitor_msg { 1001 __le16 type; 1002 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK 0x3fUL 1003 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0 1004 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1005 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 1006 __le16 event_id; 1007 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL 1008 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 1009 __le32 event_data2; 1010 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL 1011 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0 1012 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX 0x0UL 1013 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX 0x1UL 1014 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 0x2UL 1015 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 1016 u8 opaque_v; 1017 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V 0x1UL 1018 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL 1019 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1 1020 u8 timestamp_lo; 1021 __le16 timestamp_hi; 1022 __le32 event_data1; 1023 }; 1024 1025 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 1026 struct hwrm_async_event_cmpl_vf_cfg_change { 1027 __le16 type; 1028 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 1029 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 1030 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1031 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 1032 __le16 event_id; 1033 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 1034 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 1035 __le32 event_data2; 1036 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK 0xffffUL 1037 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0 1038 u8 opaque_v; 1039 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 1040 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 1041 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 1042 u8 timestamp_lo; 1043 __le16 timestamp_hi; 1044 __le32 event_data1; 1045 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 1046 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 1047 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 1048 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 1049 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 1050 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TF_OWNERSHIP_RELEASE 0x20UL 1051 }; 1052 1053 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ 1054 struct hwrm_async_event_cmpl_default_vnic_change { 1055 __le16 type; 1056 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL 1057 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0 1058 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1059 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 1060 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL 1061 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6 1062 __le16 event_id; 1063 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL 1064 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 1065 __le32 event_data2; 1066 u8 opaque_v; 1067 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL 1068 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL 1069 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1 1070 u8 timestamp_lo; 1071 __le16 timestamp_hi; 1072 __le32 event_data1; 1073 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL 1074 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0 1075 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL 1076 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL 1077 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 1078 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL 1079 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2 1080 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL 1081 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10 1082 }; 1083 1084 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ 1085 struct hwrm_async_event_cmpl_hw_flow_aged { 1086 __le16 type; 1087 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL 1088 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 1089 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1090 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 1091 __le16 event_id; 1092 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL 1093 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 1094 __le32 event_data2; 1095 u8 opaque_v; 1096 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL 1097 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL 1098 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 1099 u8 timestamp_lo; 1100 __le16 timestamp_hi; 1101 __le32 event_data1; 1102 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL 1103 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0 1104 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL 1105 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31) 1106 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31) 1107 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX 1108 }; 1109 1110 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ 1111 struct hwrm_async_event_cmpl_eem_cache_flush_req { 1112 __le16 type; 1113 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL 1114 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0 1115 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1116 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 1117 __le16 event_id; 1118 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 1119 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 1120 __le32 event_data2; 1121 u8 opaque_v; 1122 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL 1123 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL 1124 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 1125 u8 timestamp_lo; 1126 __le16 timestamp_hi; 1127 __le32 event_data1; 1128 }; 1129 1130 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ 1131 struct hwrm_async_event_cmpl_eem_cache_flush_done { 1132 __le16 type; 1133 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL 1134 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0 1135 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1136 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 1137 __le16 event_id; 1138 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 1139 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 1140 __le32 event_data2; 1141 u8 opaque_v; 1142 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL 1143 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL 1144 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 1145 u8 timestamp_lo; 1146 __le16 timestamp_hi; 1147 __le32 event_data1; 1148 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL 1149 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0 1150 }; 1151 1152 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ 1153 struct hwrm_async_event_cmpl_deferred_response { 1154 __le16 type; 1155 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK 0x3fUL 1156 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0 1157 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1158 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 1159 __le16 event_id; 1160 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL 1161 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 1162 __le32 event_data2; 1163 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL 1164 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0 1165 u8 opaque_v; 1166 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V 0x1UL 1167 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL 1168 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1 1169 u8 timestamp_lo; 1170 __le16 timestamp_hi; 1171 __le32 event_data1; 1172 }; 1173 1174 /* hwrm_async_event_cmpl_echo_request (size:128b/16B) */ 1175 struct hwrm_async_event_cmpl_echo_request { 1176 __le16 type; 1177 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK 0x3fUL 1178 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0 1179 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1180 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 1181 __le16 event_id; 1182 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 0x42UL 1183 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 1184 __le32 event_data2; 1185 u8 opaque_v; 1186 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_V 0x1UL 1187 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK 0xfeUL 1188 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1 1189 u8 timestamp_lo; 1190 __le16 timestamp_hi; 1191 __le32 event_data1; 1192 }; 1193 1194 /* hwrm_async_event_cmpl_phc_update (size:128b/16B) */ 1195 struct hwrm_async_event_cmpl_phc_update { 1196 __le16 type; 1197 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_MASK 0x3fUL 1198 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_SFT 0 1199 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1200 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT 1201 __le16 event_id; 1202 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 0x43UL 1203 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 1204 __le32 event_data2; 1205 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_MASK 0xffffUL 1206 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_SFT 0 1207 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_MASK 0xffff0000UL 1208 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_SFT 16 1209 u8 opaque_v; 1210 #define ASYNC_EVENT_CMPL_PHC_UPDATE_V 0x1UL 1211 #define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_MASK 0xfeUL 1212 #define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_SFT 1 1213 u8 timestamp_lo; 1214 __le16 timestamp_hi; 1215 __le32 event_data1; 1216 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK 0xfUL 1217 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT 0 1218 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_MASTER 0x1UL 1219 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_SECONDARY 0x2UL 1220 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_FAILOVER 0x3UL 1221 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE 0x4UL 1222 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE 1223 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK 0xffff0UL 1224 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT 4 1225 }; 1226 1227 /* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */ 1228 struct hwrm_async_event_cmpl_pps_timestamp { 1229 __le16 type; 1230 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK 0x3fUL 1231 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0 1232 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1233 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 1234 __le16 event_id; 1235 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 0x44UL 1236 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 1237 __le32 event_data2; 1238 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE 0x1UL 1239 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL 0x0UL 1240 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 0x1UL 1241 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 1242 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK 0xeUL 1243 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT 1 1244 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK 0xffff0UL 1245 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT 4 1246 u8 opaque_v; 1247 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V 0x1UL 1248 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK 0xfeUL 1249 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1 1250 u8 timestamp_lo; 1251 __le16 timestamp_hi; 1252 __le32 event_data1; 1253 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK 0xffffffffUL 1254 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT 0 1255 }; 1256 1257 /* hwrm_async_event_cmpl_error_report (size:128b/16B) */ 1258 struct hwrm_async_event_cmpl_error_report { 1259 __le16 type; 1260 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK 0x3fUL 1261 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0 1262 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1263 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 1264 __le16 event_id; 1265 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 0x45UL 1266 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 1267 __le32 event_data2; 1268 u8 opaque_v; 1269 #define ASYNC_EVENT_CMPL_ERROR_REPORT_V 0x1UL 1270 #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK 0xfeUL 1271 #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1 1272 u8 timestamp_lo; 1273 __le16 timestamp_hi; 1274 __le32 event_data1; 1275 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1276 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0 1277 }; 1278 1279 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */ 1280 struct hwrm_async_event_cmpl_hwrm_error { 1281 __le16 type; 1282 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL 1283 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 1284 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1285 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 1286 __le16 event_id; 1287 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL 1288 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 1289 __le32 event_data2; 1290 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL 1291 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 1292 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL 1293 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL 1294 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL 1295 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 1296 u8 opaque_v; 1297 #define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL 1298 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL 1299 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 1300 u8 timestamp_lo; 1301 __le16 timestamp_hi; 1302 __le32 event_data1; 1303 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL 1304 }; 1305 1306 /* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */ 1307 struct hwrm_async_event_cmpl_error_report_base { 1308 __le16 type; 1309 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK 0x3fUL 1310 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0 1311 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1312 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 1313 __le16 event_id; 1314 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 0x45UL 1315 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 1316 __le32 event_data2; 1317 u8 opaque_v; 1318 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V 0x1UL 1319 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK 0xfeUL 1320 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1 1321 u8 timestamp_lo; 1322 __le16 timestamp_hi; 1323 __le32 event_data1; 1324 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1325 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT 0 1326 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED 0x0UL 1327 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 1328 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 1329 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM 0x3UL 1330 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL 1331 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD 0x5UL 1332 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD 1333 }; 1334 1335 /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ 1336 struct hwrm_async_event_cmpl_error_report_pause_storm { 1337 __le16 type; 1338 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK 0x3fUL 1339 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT 0 1340 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1341 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 1342 __le16 event_id; 1343 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 0x45UL 1344 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 1345 __le32 event_data2; 1346 u8 opaque_v; 1347 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V 0x1UL 1348 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK 0xfeUL 1349 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1 1350 u8 timestamp_lo; 1351 __le16 timestamp_hi; 1352 __le32 event_data1; 1353 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1354 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT 0 1355 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 1356 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 1357 }; 1358 1359 /* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */ 1360 struct hwrm_async_event_cmpl_error_report_invalid_signal { 1361 __le16 type; 1362 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK 0x3fUL 1363 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT 0 1364 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1365 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 1366 __le16 event_id; 1367 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 0x45UL 1368 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 1369 __le32 event_data2; 1370 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK 0xffUL 1371 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT 0 1372 u8 opaque_v; 1373 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V 0x1UL 1374 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK 0xfeUL 1375 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1 1376 u8 timestamp_lo; 1377 __le16 timestamp_hi; 1378 __le32 event_data1; 1379 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1380 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT 0 1381 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 1382 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 1383 }; 1384 1385 /* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */ 1386 struct hwrm_async_event_cmpl_error_report_nvm { 1387 __le16 type; 1388 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK 0x3fUL 1389 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0 1390 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1391 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 1392 __le16 event_id; 1393 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 0x45UL 1394 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 1395 __le32 event_data2; 1396 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK 0xffffffffUL 1397 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT 0 1398 u8 opaque_v; 1399 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V 0x1UL 1400 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK 0xfeUL 1401 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1 1402 u8 timestamp_lo; 1403 __le16 timestamp_hi; 1404 __le32 event_data1; 1405 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1406 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT 0 1407 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 0x3UL 1408 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 1409 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK 0xff00UL 1410 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT 8 1411 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE (0x1UL << 8) 1412 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE (0x2UL << 8) 1413 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE 1414 }; 1415 1416 /* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */ 1417 struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold { 1418 __le16 type; 1419 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK 0x3fUL 1420 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT 0 1421 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1422 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT 1423 __le16 event_id; 1424 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT 0x45UL 1425 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT 1426 __le32 event_data2; 1427 u8 opaque_v; 1428 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V 0x1UL 1429 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK 0xfeUL 1430 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT 1 1431 u8 timestamp_lo; 1432 __le16 timestamp_hi; 1433 __le32 event_data1; 1434 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1435 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT 0 1436 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL 1437 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 1438 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK 0xffffff00UL 1439 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT 8 1440 }; 1441 1442 /* hwrm_async_event_cmpl_error_report_thermal (size:128b/16B) */ 1443 struct hwrm_async_event_cmpl_error_report_thermal { 1444 __le16 type; 1445 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_MASK 0x3fUL 1446 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_SFT 0 1447 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1448 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT 1449 __le16 event_id; 1450 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT 0x45UL 1451 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT 1452 __le32 event_data2; 1453 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK 0xffUL 1454 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_SFT 0 1455 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_MASK 0xff00UL 1456 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_SFT 8 1457 u8 opaque_v; 1458 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_V 0x1UL 1459 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_MASK 0xfeUL 1460 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_SFT 1 1461 u8 timestamp_lo; 1462 __le16 timestamp_hi; 1463 __le32 event_data1; 1464 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1465 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_SFT 0 1466 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT 0x5UL 1467 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT 1468 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_MASK 0x700UL 1469 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SFT 8 1470 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_WARN (0x0UL << 8) 1471 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_CRITICAL (0x1UL << 8) 1472 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_FATAL (0x2UL << 8) 1473 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN (0x3UL << 8) 1474 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN 1475 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR 0x800UL 1476 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_DECREASING (0x0UL << 11) 1477 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING (0x1UL << 11) 1478 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING 1479 }; 1480 1481 /* hwrm_func_reset_input (size:192b/24B) */ 1482 struct hwrm_func_reset_input { 1483 __le16 req_type; 1484 __le16 cmpl_ring; 1485 __le16 seq_id; 1486 __le16 target_id; 1487 __le64 resp_addr; 1488 __le32 enables; 1489 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 1490 __le16 vf_id; 1491 u8 func_reset_level; 1492 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 1493 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 1494 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 1495 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 1496 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 1497 u8 unused_0; 1498 }; 1499 1500 /* hwrm_func_reset_output (size:128b/16B) */ 1501 struct hwrm_func_reset_output { 1502 __le16 error_code; 1503 __le16 req_type; 1504 __le16 seq_id; 1505 __le16 resp_len; 1506 u8 unused_0[7]; 1507 u8 valid; 1508 }; 1509 1510 /* hwrm_func_getfid_input (size:192b/24B) */ 1511 struct hwrm_func_getfid_input { 1512 __le16 req_type; 1513 __le16 cmpl_ring; 1514 __le16 seq_id; 1515 __le16 target_id; 1516 __le64 resp_addr; 1517 __le32 enables; 1518 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 1519 __le16 pci_id; 1520 u8 unused_0[2]; 1521 }; 1522 1523 /* hwrm_func_getfid_output (size:128b/16B) */ 1524 struct hwrm_func_getfid_output { 1525 __le16 error_code; 1526 __le16 req_type; 1527 __le16 seq_id; 1528 __le16 resp_len; 1529 __le16 fid; 1530 u8 unused_0[5]; 1531 u8 valid; 1532 }; 1533 1534 /* hwrm_func_vf_alloc_input (size:192b/24B) */ 1535 struct hwrm_func_vf_alloc_input { 1536 __le16 req_type; 1537 __le16 cmpl_ring; 1538 __le16 seq_id; 1539 __le16 target_id; 1540 __le64 resp_addr; 1541 __le32 enables; 1542 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 1543 __le16 first_vf_id; 1544 __le16 num_vfs; 1545 }; 1546 1547 /* hwrm_func_vf_alloc_output (size:128b/16B) */ 1548 struct hwrm_func_vf_alloc_output { 1549 __le16 error_code; 1550 __le16 req_type; 1551 __le16 seq_id; 1552 __le16 resp_len; 1553 __le16 first_vf_id; 1554 u8 unused_0[5]; 1555 u8 valid; 1556 }; 1557 1558 /* hwrm_func_vf_free_input (size:192b/24B) */ 1559 struct hwrm_func_vf_free_input { 1560 __le16 req_type; 1561 __le16 cmpl_ring; 1562 __le16 seq_id; 1563 __le16 target_id; 1564 __le64 resp_addr; 1565 __le32 enables; 1566 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 1567 __le16 first_vf_id; 1568 __le16 num_vfs; 1569 }; 1570 1571 /* hwrm_func_vf_free_output (size:128b/16B) */ 1572 struct hwrm_func_vf_free_output { 1573 __le16 error_code; 1574 __le16 req_type; 1575 __le16 seq_id; 1576 __le16 resp_len; 1577 u8 unused_0[7]; 1578 u8 valid; 1579 }; 1580 1581 /* hwrm_func_vf_cfg_input (size:576b/72B) */ 1582 struct hwrm_func_vf_cfg_input { 1583 __le16 req_type; 1584 __le16 cmpl_ring; 1585 __le16 seq_id; 1586 __le16 target_id; 1587 __le64 resp_addr; 1588 __le32 enables; 1589 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 1590 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 1591 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 1592 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 1593 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 1594 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 1595 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 1596 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 1597 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 1598 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 1599 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 1600 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 1601 #define FUNC_VF_CFG_REQ_ENABLES_NUM_KTLS_TX_KEY_CTXS 0x1000UL 1602 #define FUNC_VF_CFG_REQ_ENABLES_NUM_KTLS_RX_KEY_CTXS 0x2000UL 1603 #define FUNC_VF_CFG_REQ_ENABLES_NUM_QUIC_TX_KEY_CTXS 0x4000UL 1604 #define FUNC_VF_CFG_REQ_ENABLES_NUM_QUIC_RX_KEY_CTXS 0x8000UL 1605 __le16 mtu; 1606 __le16 guest_vlan; 1607 __le16 async_event_cr; 1608 u8 dflt_mac_addr[6]; 1609 __le32 flags; 1610 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 1611 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 1612 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 1613 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 1614 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 1615 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 1616 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 1617 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 1618 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x100UL 1619 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x200UL 1620 __le16 num_rsscos_ctxs; 1621 __le16 num_cmpl_rings; 1622 __le16 num_tx_rings; 1623 __le16 num_rx_rings; 1624 __le16 num_l2_ctxs; 1625 __le16 num_vnics; 1626 __le16 num_stat_ctxs; 1627 __le16 num_hw_ring_grps; 1628 __le32 num_ktls_tx_key_ctxs; 1629 __le32 num_ktls_rx_key_ctxs; 1630 __le16 num_msix; 1631 u8 unused[2]; 1632 __le32 num_quic_tx_key_ctxs; 1633 __le32 num_quic_rx_key_ctxs; 1634 }; 1635 1636 /* hwrm_func_vf_cfg_output (size:128b/16B) */ 1637 struct hwrm_func_vf_cfg_output { 1638 __le16 error_code; 1639 __le16 req_type; 1640 __le16 seq_id; 1641 __le16 resp_len; 1642 u8 unused_0[7]; 1643 u8 valid; 1644 }; 1645 1646 /* hwrm_func_qcaps_input (size:192b/24B) */ 1647 struct hwrm_func_qcaps_input { 1648 __le16 req_type; 1649 __le16 cmpl_ring; 1650 __le16 seq_id; 1651 __le16 target_id; 1652 __le64 resp_addr; 1653 __le16 fid; 1654 u8 unused_0[6]; 1655 }; 1656 1657 /* hwrm_func_qcaps_output (size:1088b/136B) */ 1658 struct hwrm_func_qcaps_output { 1659 __le16 error_code; 1660 __le16 req_type; 1661 __le16 seq_id; 1662 __le16 resp_len; 1663 __le16 fid; 1664 __le16 port_id; 1665 __le32 flags; 1666 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1667 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 1668 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1669 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1670 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1671 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1672 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1673 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1674 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1675 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1676 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 1677 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 1678 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 1679 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 1680 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 1681 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 1682 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 1683 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 1684 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 1685 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 1686 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 1687 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL 1688 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL 1689 #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL 1690 #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL 1691 #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL 1692 #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL 1693 #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL 1694 #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL 1695 #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL 1696 #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL 1697 #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL 1698 u8 mac_address[6]; 1699 __le16 max_rsscos_ctx; 1700 __le16 max_cmpl_rings; 1701 __le16 max_tx_rings; 1702 __le16 max_rx_rings; 1703 __le16 max_l2_ctxs; 1704 __le16 max_vnics; 1705 __le16 first_vf_id; 1706 __le16 max_vfs; 1707 __le16 max_stat_ctx; 1708 __le32 max_encap_records; 1709 __le32 max_decap_records; 1710 __le32 max_tx_em_flows; 1711 __le32 max_tx_wm_flows; 1712 __le32 max_rx_em_flows; 1713 __le32 max_rx_wm_flows; 1714 __le32 max_mcast_filters; 1715 __le32 max_flow_id; 1716 __le32 max_hw_ring_grps; 1717 __le16 max_sp_tx_rings; 1718 __le16 max_msix_vfs; 1719 __le32 flags_ext; 1720 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL 1721 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL 1722 #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL 1723 #define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT 0x8UL 1724 #define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT 0x10UL 1725 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL 1726 #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL 1727 #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL 1728 #define FUNC_QCAPS_RESP_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED 0x100UL 1729 #define FUNC_QCAPS_RESP_FLAGS_EXT_SOC_SPD_SUPPORTED 0x200UL 1730 #define FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED 0x400UL 1731 #define FUNC_QCAPS_RESP_FLAGS_EXT_FAST_RESET_CAPABLE 0x800UL 1732 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_METADATA_CFG_CAPABLE 0x1000UL 1733 #define FUNC_QCAPS_RESP_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED 0x2000UL 1734 #define FUNC_QCAPS_RESP_FLAGS_EXT_BD_METADATA_SUPPORTED 0x4000UL 1735 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECHO_REQUEST_SUPPORTED 0x8000UL 1736 #define FUNC_QCAPS_RESP_FLAGS_EXT_NPAR_1_2_SUPPORTED 0x10000UL 1737 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PTM_SUPPORTED 0x20000UL 1738 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED 0x40000UL 1739 #define FUNC_QCAPS_RESP_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED 0x80000UL 1740 #define FUNC_QCAPS_RESP_FLAGS_EXT_PARTITION_BW_SUPPORTED 0x100000UL 1741 #define FUNC_QCAPS_RESP_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED 0x200000UL 1742 #define FUNC_QCAPS_RESP_FLAGS_EXT_KTLS_SUPPORTED 0x400000UL 1743 #define FUNC_QCAPS_RESP_FLAGS_EXT_EP_RATE_CONTROL 0x800000UL 1744 #define FUNC_QCAPS_RESP_FLAGS_EXT_MIN_BW_SUPPORTED 0x1000000UL 1745 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_COAL_CMPL_CAP 0x2000000UL 1746 #define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_SUPPORTED 0x4000000UL 1747 #define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_REQUIRED 0x8000000UL 1748 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED 0x10000000UL 1749 #define FUNC_QCAPS_RESP_FLAGS_EXT_DBR_PACING_SUPPORTED 0x20000000UL 1750 #define FUNC_QCAPS_RESP_FLAGS_EXT_HW_DBR_DROP_RECOV_SUPPORTED 0x40000000UL 1751 #define FUNC_QCAPS_RESP_FLAGS_EXT_DISABLE_CQ_OVERFLOW_DETECTION_SUPPORTED 0x80000000UL 1752 u8 max_schqs; 1753 u8 mpc_chnls_cap; 1754 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL 1755 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE 0x2UL 1756 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA 0x4UL 1757 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA 0x8UL 1758 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE 0x10UL 1759 __le16 max_key_ctxs_alloc; 1760 __le32 flags_ext2; 1761 #define FUNC_QCAPS_RESP_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED 0x1UL 1762 #define FUNC_QCAPS_RESP_FLAGS_EXT2_QUIC_SUPPORTED 0x2UL 1763 #define FUNC_QCAPS_RESP_FLAGS_EXT2_KDNET_SUPPORTED 0x4UL 1764 #define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED 0x8UL 1765 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED 0x10UL 1766 #define FUNC_QCAPS_RESP_FLAGS_EXT2_GENERIC_STATS_SUPPORTED 0x20UL 1767 #define FUNC_QCAPS_RESP_FLAGS_EXT2_UDP_GSO_SUPPORTED 0x40UL 1768 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SYNCE_SUPPORTED 0x80UL 1769 #define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED 0x100UL 1770 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TX_PKT_TS_CMPL_SUPPORTED 0x200UL 1771 #define FUNC_QCAPS_RESP_FLAGS_EXT2_HW_LAG_SUPPORTED 0x400UL 1772 #define FUNC_QCAPS_RESP_FLAGS_EXT2_ON_CHIP_CTX_SUPPORTED 0x800UL 1773 #define FUNC_QCAPS_RESP_FLAGS_EXT2_STEERING_TAG_SUPPORTED 0x1000UL 1774 #define FUNC_QCAPS_RESP_FLAGS_EXT2_ENHANCED_VF_SCALE_SUPPORTED 0x2000UL 1775 #define FUNC_QCAPS_RESP_FLAGS_EXT2_KEY_XID_PARTITION_SUPPORTED 0x4000UL 1776 #define FUNC_QCAPS_RESP_FLAGS_EXT2_CONCURRENT_KTLS_QUIC_SUPPORTED 0x8000UL 1777 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_CROSS_TC_CAP_SUPPORTED 0x10000UL 1778 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_PER_TC_CAP_SUPPORTED 0x20000UL 1779 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_PER_TC_RESERVATION_SUPPORTED 0x40000UL 1780 #define FUNC_QCAPS_RESP_FLAGS_EXT2_DB_ERROR_STATS_SUPPORTED 0x80000UL 1781 #define FUNC_QCAPS_RESP_FLAGS_EXT2_ROCE_VF_RESOURCE_MGMT_SUPPORTED 0x100000UL 1782 #define FUNC_QCAPS_RESP_FLAGS_EXT2_UDCC_SUPPORTED 0x200000UL 1783 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TIMED_TX_SO_TXTIME_SUPPORTED 0x400000UL 1784 __le16 tunnel_disable_flag; 1785 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN 0x1UL 1786 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NGE 0x2UL 1787 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NVGRE 0x4UL 1788 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_L2GRE 0x8UL 1789 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_GRE 0x10UL 1790 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP 0x20UL 1791 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_MPLS 0x40UL 1792 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE 0x80UL 1793 __le16 xid_partition_cap; 1794 #define FUNC_QCAPS_RESP_XID_PARTITION_CAP_KTLS_TKC 0x1UL 1795 #define FUNC_QCAPS_RESP_XID_PARTITION_CAP_KTLS_RKC 0x2UL 1796 #define FUNC_QCAPS_RESP_XID_PARTITION_CAP_QUIC_TKC 0x4UL 1797 #define FUNC_QCAPS_RESP_XID_PARTITION_CAP_QUIC_RKC 0x8UL 1798 u8 device_serial_number[8]; 1799 __le16 ctxs_per_partition; 1800 u8 unused_2[2]; 1801 __le32 roce_vf_max_av; 1802 __le32 roce_vf_max_cq; 1803 __le32 roce_vf_max_mrw; 1804 __le32 roce_vf_max_qp; 1805 __le32 roce_vf_max_srq; 1806 __le32 roce_vf_max_gid; 1807 u8 unused_3[3]; 1808 u8 valid; 1809 }; 1810 1811 /* hwrm_func_qcfg_input (size:192b/24B) */ 1812 struct hwrm_func_qcfg_input { 1813 __le16 req_type; 1814 __le16 cmpl_ring; 1815 __le16 seq_id; 1816 __le16 target_id; 1817 __le64 resp_addr; 1818 __le16 fid; 1819 u8 unused_0[6]; 1820 }; 1821 1822 /* hwrm_func_qcfg_output (size:1280b/160B) */ 1823 struct hwrm_func_qcfg_output { 1824 __le16 error_code; 1825 __le16 req_type; 1826 __le16 seq_id; 1827 __le16 resp_len; 1828 __le16 fid; 1829 __le16 port_id; 1830 __le16 vlan; 1831 __le16 flags; 1832 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1833 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1834 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 1835 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 1836 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 1837 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 1838 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 1839 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL 1840 #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL 1841 #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL 1842 #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL 1843 #define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL 1844 #define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED 0x1000UL 1845 #define FUNC_QCFG_RESP_FLAGS_MULTI_ROOT 0x2000UL 1846 #define FUNC_QCFG_RESP_FLAGS_ENABLE_RDMA_SRIOV 0x4000UL 1847 u8 mac_address[6]; 1848 __le16 pci_id; 1849 __le16 alloc_rsscos_ctx; 1850 __le16 alloc_cmpl_rings; 1851 __le16 alloc_tx_rings; 1852 __le16 alloc_rx_rings; 1853 __le16 alloc_l2_ctx; 1854 __le16 alloc_vnics; 1855 __le16 admin_mtu; 1856 __le16 mru; 1857 __le16 stat_ctx_id; 1858 u8 port_partition_type; 1859 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1860 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1861 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1862 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1863 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 1864 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_2 0x5UL 1865 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 1866 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 1867 u8 port_pf_cnt; 1868 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 1869 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 1870 __le16 dflt_vnic_id; 1871 __le16 max_mtu_configured; 1872 __le32 min_bw; 1873 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1874 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 1875 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 1876 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 1877 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 1878 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 1879 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1880 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 1881 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1882 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1883 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1884 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1885 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1886 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1887 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 1888 __le32 max_bw; 1889 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1890 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 1891 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 1892 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 1893 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 1894 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 1895 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1896 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 1897 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1898 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1899 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1900 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1901 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1902 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1903 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 1904 u8 evb_mode; 1905 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 1906 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 1907 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 1908 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 1909 u8 options; 1910 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1911 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 1912 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1913 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1914 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 1915 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1916 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 1917 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1918 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1919 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1920 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 1921 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 1922 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 1923 __le16 alloc_vfs; 1924 __le32 alloc_mcast_filters; 1925 __le32 alloc_hw_ring_grps; 1926 __le16 alloc_sp_tx_rings; 1927 __le16 alloc_stat_ctx; 1928 __le16 alloc_msix; 1929 __le16 registered_vfs; 1930 __le16 l2_doorbell_bar_size_kb; 1931 u8 active_endpoints; 1932 u8 always_1; 1933 __le32 reset_addr_poll; 1934 __le16 legacy_l2_db_size_kb; 1935 __le16 svif_info; 1936 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL 1937 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0 1938 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL 1939 u8 mpc_chnls; 1940 #define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED 0x1UL 1941 #define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED 0x2UL 1942 #define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL 1943 #define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL 1944 #define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL 1945 u8 db_page_size; 1946 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_4KB 0x0UL 1947 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_8KB 0x1UL 1948 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_16KB 0x2UL 1949 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_32KB 0x3UL 1950 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_64KB 0x4UL 1951 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_128KB 0x5UL 1952 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_256KB 0x6UL 1953 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_512KB 0x7UL 1954 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_1MB 0x8UL 1955 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_2MB 0x9UL 1956 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB 0xaUL 1957 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_LAST FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB 1958 u8 unused_2[2]; 1959 __le32 partition_min_bw; 1960 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1961 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_SFT 0 1962 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE 0x10000000UL 1963 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 1964 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 1965 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES 1966 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1967 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 1968 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1969 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 1970 __le32 partition_max_bw; 1971 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1972 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_SFT 0 1973 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE 0x10000000UL 1974 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 1975 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 1976 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES 1977 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1978 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 1979 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1980 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 1981 __le16 host_mtu; 1982 u8 unused_3[2]; 1983 u8 unused_4[2]; 1984 u8 port_kdnet_mode; 1985 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_DISABLED 0x0UL 1986 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED 0x1UL 1987 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_LAST FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED 1988 u8 kdnet_pcie_function; 1989 __le16 port_kdnet_fid; 1990 u8 unused_5[2]; 1991 __le32 num_ktls_tx_key_ctxs; 1992 __le32 num_ktls_rx_key_ctxs; 1993 u8 lag_id; 1994 u8 parif; 1995 u8 fw_lag_id; 1996 u8 unused_6; 1997 __le32 num_quic_tx_key_ctxs; 1998 __le32 num_quic_rx_key_ctxs; 1999 __le32 roce_max_av_per_vf; 2000 __le32 roce_max_cq_per_vf; 2001 __le32 roce_max_mrw_per_vf; 2002 __le32 roce_max_qp_per_vf; 2003 __le32 roce_max_srq_per_vf; 2004 __le32 roce_max_gid_per_vf; 2005 __le16 xid_partition_cfg; 2006 u8 unused_7; 2007 u8 valid; 2008 }; 2009 2010 /* hwrm_func_cfg_input (size:1280b/160B) */ 2011 struct hwrm_func_cfg_input { 2012 __le16 req_type; 2013 __le16 cmpl_ring; 2014 __le16 seq_id; 2015 __le16 target_id; 2016 __le64 resp_addr; 2017 __le16 fid; 2018 __le16 num_msix; 2019 __le32 flags; 2020 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 2021 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 2022 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 2023 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 2024 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 2025 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 2026 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 2027 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 2028 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 2029 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 2030 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 2031 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 2032 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 2033 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 2034 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 2035 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 2036 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 2037 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL 2038 #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL 2039 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL 2040 #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL 2041 #define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS 0x4000000UL 2042 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x8000000UL 2043 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL 2044 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_ENABLE 0x20000000UL 2045 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_DISABLE 0x40000000UL 2046 __le32 enables; 2047 #define FUNC_CFG_REQ_ENABLES_ADMIN_MTU 0x1UL 2048 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 2049 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 2050 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 2051 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 2052 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 2053 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 2054 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 2055 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 2056 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 2057 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 2058 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 2059 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 2060 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 2061 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 2062 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 2063 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 2064 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 2065 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 2066 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 2067 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 2068 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 2069 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 2070 #define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL 2071 #define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL 2072 #define FUNC_CFG_REQ_ENABLES_MPC_CHNLS 0x2000000UL 2073 #define FUNC_CFG_REQ_ENABLES_PARTITION_MIN_BW 0x4000000UL 2074 #define FUNC_CFG_REQ_ENABLES_PARTITION_MAX_BW 0x8000000UL 2075 #define FUNC_CFG_REQ_ENABLES_TPID 0x10000000UL 2076 #define FUNC_CFG_REQ_ENABLES_HOST_MTU 0x20000000UL 2077 #define FUNC_CFG_REQ_ENABLES_KTLS_TX_KEY_CTXS 0x40000000UL 2078 #define FUNC_CFG_REQ_ENABLES_KTLS_RX_KEY_CTXS 0x80000000UL 2079 __le16 admin_mtu; 2080 __le16 mru; 2081 __le16 num_rsscos_ctxs; 2082 __le16 num_cmpl_rings; 2083 __le16 num_tx_rings; 2084 __le16 num_rx_rings; 2085 __le16 num_l2_ctxs; 2086 __le16 num_vnics; 2087 __le16 num_stat_ctxs; 2088 __le16 num_hw_ring_grps; 2089 u8 dflt_mac_addr[6]; 2090 __le16 dflt_vlan; 2091 __be32 dflt_ip_addr[4]; 2092 __le32 min_bw; 2093 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2094 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 2095 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 2096 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 2097 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 2098 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 2099 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2100 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 2101 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2102 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2103 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2104 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2105 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2106 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2107 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 2108 __le32 max_bw; 2109 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2110 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 2111 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 2112 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 2113 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 2114 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 2115 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2116 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 2117 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2118 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2119 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2120 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2121 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2122 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2123 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 2124 __le16 async_event_cr; 2125 u8 vlan_antispoof_mode; 2126 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 2127 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 2128 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 2129 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 2130 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 2131 u8 allowed_vlan_pris; 2132 u8 evb_mode; 2133 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 2134 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 2135 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 2136 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 2137 u8 options; 2138 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 2139 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 2140 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 2141 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 2142 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 2143 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 2144 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 2145 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 2146 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 2147 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 2148 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 2149 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 2150 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 2151 __le16 num_mcast_filters; 2152 __le16 schq_id; 2153 __le16 mpc_chnls; 2154 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE 0x1UL 2155 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE 0x2UL 2156 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE 0x4UL 2157 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE 0x8UL 2158 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE 0x10UL 2159 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE 0x20UL 2160 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE 0x40UL 2161 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE 0x80UL 2162 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE 0x100UL 2163 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE 0x200UL 2164 __le32 partition_min_bw; 2165 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2166 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_SFT 0 2167 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE 0x10000000UL 2168 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 2169 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 2170 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES 2171 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2172 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 2173 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2174 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 2175 __le32 partition_max_bw; 2176 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2177 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_SFT 0 2178 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE 0x10000000UL 2179 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 2180 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 2181 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES 2182 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2183 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 2184 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2185 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 2186 __be16 tpid; 2187 __le16 host_mtu; 2188 __le32 flags2; 2189 #define FUNC_CFG_REQ_FLAGS2_KTLS_KEY_CTX_ASSETS_TEST 0x1UL 2190 #define FUNC_CFG_REQ_FLAGS2_QUIC_KEY_CTX_ASSETS_TEST 0x2UL 2191 __le32 enables2; 2192 #define FUNC_CFG_REQ_ENABLES2_KDNET 0x1UL 2193 #define FUNC_CFG_REQ_ENABLES2_DB_PAGE_SIZE 0x2UL 2194 #define FUNC_CFG_REQ_ENABLES2_QUIC_TX_KEY_CTXS 0x4UL 2195 #define FUNC_CFG_REQ_ENABLES2_QUIC_RX_KEY_CTXS 0x8UL 2196 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_AV_PER_VF 0x10UL 2197 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_CQ_PER_VF 0x20UL 2198 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_MRW_PER_VF 0x40UL 2199 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_QP_PER_VF 0x80UL 2200 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_SRQ_PER_VF 0x100UL 2201 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_GID_PER_VF 0x200UL 2202 #define FUNC_CFG_REQ_ENABLES2_XID_PARTITION_CFG 0x400UL 2203 u8 port_kdnet_mode; 2204 #define FUNC_CFG_REQ_PORT_KDNET_MODE_DISABLED 0x0UL 2205 #define FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED 0x1UL 2206 #define FUNC_CFG_REQ_PORT_KDNET_MODE_LAST FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED 2207 u8 db_page_size; 2208 #define FUNC_CFG_REQ_DB_PAGE_SIZE_4KB 0x0UL 2209 #define FUNC_CFG_REQ_DB_PAGE_SIZE_8KB 0x1UL 2210 #define FUNC_CFG_REQ_DB_PAGE_SIZE_16KB 0x2UL 2211 #define FUNC_CFG_REQ_DB_PAGE_SIZE_32KB 0x3UL 2212 #define FUNC_CFG_REQ_DB_PAGE_SIZE_64KB 0x4UL 2213 #define FUNC_CFG_REQ_DB_PAGE_SIZE_128KB 0x5UL 2214 #define FUNC_CFG_REQ_DB_PAGE_SIZE_256KB 0x6UL 2215 #define FUNC_CFG_REQ_DB_PAGE_SIZE_512KB 0x7UL 2216 #define FUNC_CFG_REQ_DB_PAGE_SIZE_1MB 0x8UL 2217 #define FUNC_CFG_REQ_DB_PAGE_SIZE_2MB 0x9UL 2218 #define FUNC_CFG_REQ_DB_PAGE_SIZE_4MB 0xaUL 2219 #define FUNC_CFG_REQ_DB_PAGE_SIZE_LAST FUNC_CFG_REQ_DB_PAGE_SIZE_4MB 2220 u8 unused_1[2]; 2221 __le32 num_ktls_tx_key_ctxs; 2222 __le32 num_ktls_rx_key_ctxs; 2223 __le32 num_quic_tx_key_ctxs; 2224 __le32 num_quic_rx_key_ctxs; 2225 __le32 roce_max_av_per_vf; 2226 __le32 roce_max_cq_per_vf; 2227 __le32 roce_max_mrw_per_vf; 2228 __le32 roce_max_qp_per_vf; 2229 __le32 roce_max_srq_per_vf; 2230 __le32 roce_max_gid_per_vf; 2231 __le16 xid_partition_cfg; 2232 #define FUNC_CFG_REQ_XID_PARTITION_CFG_KTLS_TKC 0x1UL 2233 #define FUNC_CFG_REQ_XID_PARTITION_CFG_KTLS_RKC 0x2UL 2234 #define FUNC_CFG_REQ_XID_PARTITION_CFG_QUIC_TKC 0x4UL 2235 #define FUNC_CFG_REQ_XID_PARTITION_CFG_QUIC_RKC 0x8UL 2236 __le16 unused_2; 2237 }; 2238 2239 /* hwrm_func_cfg_output (size:128b/16B) */ 2240 struct hwrm_func_cfg_output { 2241 __le16 error_code; 2242 __le16 req_type; 2243 __le16 seq_id; 2244 __le16 resp_len; 2245 u8 unused_0[7]; 2246 u8 valid; 2247 }; 2248 2249 /* hwrm_func_cfg_cmd_err (size:64b/8B) */ 2250 struct hwrm_func_cfg_cmd_err { 2251 u8 code; 2252 #define FUNC_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 2253 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_RANGE 0x1UL 2254 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_MORE_THAN_MAX 0x2UL 2255 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_UNSUPPORTED 0x3UL 2256 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT 0x4UL 2257 #define FUNC_CFG_CMD_ERR_CODE_LAST FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT 2258 u8 unused_0[7]; 2259 }; 2260 2261 /* hwrm_func_qstats_input (size:192b/24B) */ 2262 struct hwrm_func_qstats_input { 2263 __le16 req_type; 2264 __le16 cmpl_ring; 2265 __le16 seq_id; 2266 __le16 target_id; 2267 __le64 resp_addr; 2268 __le16 fid; 2269 u8 flags; 2270 #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL 2271 #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL 2272 #define FUNC_QSTATS_REQ_FLAGS_L2_ONLY 0x4UL 2273 u8 unused_0[5]; 2274 }; 2275 2276 /* hwrm_func_qstats_output (size:1408b/176B) */ 2277 struct hwrm_func_qstats_output { 2278 __le16 error_code; 2279 __le16 req_type; 2280 __le16 seq_id; 2281 __le16 resp_len; 2282 __le64 tx_ucast_pkts; 2283 __le64 tx_mcast_pkts; 2284 __le64 tx_bcast_pkts; 2285 __le64 tx_discard_pkts; 2286 __le64 tx_drop_pkts; 2287 __le64 tx_ucast_bytes; 2288 __le64 tx_mcast_bytes; 2289 __le64 tx_bcast_bytes; 2290 __le64 rx_ucast_pkts; 2291 __le64 rx_mcast_pkts; 2292 __le64 rx_bcast_pkts; 2293 __le64 rx_discard_pkts; 2294 __le64 rx_drop_pkts; 2295 __le64 rx_ucast_bytes; 2296 __le64 rx_mcast_bytes; 2297 __le64 rx_bcast_bytes; 2298 __le64 rx_agg_pkts; 2299 __le64 rx_agg_bytes; 2300 __le64 rx_agg_events; 2301 __le64 rx_agg_aborts; 2302 u8 clear_seq; 2303 u8 unused_0[6]; 2304 u8 valid; 2305 }; 2306 2307 /* hwrm_func_qstats_ext_input (size:256b/32B) */ 2308 struct hwrm_func_qstats_ext_input { 2309 __le16 req_type; 2310 __le16 cmpl_ring; 2311 __le16 seq_id; 2312 __le16 target_id; 2313 __le64 resp_addr; 2314 __le16 fid; 2315 u8 flags; 2316 #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL 2317 #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL 2318 u8 unused_0[1]; 2319 __le32 enables; 2320 #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL 2321 __le16 schq_id; 2322 __le16 traffic_class; 2323 u8 unused_1[4]; 2324 }; 2325 2326 /* hwrm_func_qstats_ext_output (size:1536b/192B) */ 2327 struct hwrm_func_qstats_ext_output { 2328 __le16 error_code; 2329 __le16 req_type; 2330 __le16 seq_id; 2331 __le16 resp_len; 2332 __le64 rx_ucast_pkts; 2333 __le64 rx_mcast_pkts; 2334 __le64 rx_bcast_pkts; 2335 __le64 rx_discard_pkts; 2336 __le64 rx_error_pkts; 2337 __le64 rx_ucast_bytes; 2338 __le64 rx_mcast_bytes; 2339 __le64 rx_bcast_bytes; 2340 __le64 tx_ucast_pkts; 2341 __le64 tx_mcast_pkts; 2342 __le64 tx_bcast_pkts; 2343 __le64 tx_error_pkts; 2344 __le64 tx_discard_pkts; 2345 __le64 tx_ucast_bytes; 2346 __le64 tx_mcast_bytes; 2347 __le64 tx_bcast_bytes; 2348 __le64 rx_tpa_eligible_pkt; 2349 __le64 rx_tpa_eligible_bytes; 2350 __le64 rx_tpa_pkt; 2351 __le64 rx_tpa_bytes; 2352 __le64 rx_tpa_errors; 2353 __le64 rx_tpa_events; 2354 u8 unused_0[7]; 2355 u8 valid; 2356 }; 2357 2358 /* hwrm_func_clr_stats_input (size:192b/24B) */ 2359 struct hwrm_func_clr_stats_input { 2360 __le16 req_type; 2361 __le16 cmpl_ring; 2362 __le16 seq_id; 2363 __le16 target_id; 2364 __le64 resp_addr; 2365 __le16 fid; 2366 u8 unused_0[6]; 2367 }; 2368 2369 /* hwrm_func_clr_stats_output (size:128b/16B) */ 2370 struct hwrm_func_clr_stats_output { 2371 __le16 error_code; 2372 __le16 req_type; 2373 __le16 seq_id; 2374 __le16 resp_len; 2375 u8 unused_0[7]; 2376 u8 valid; 2377 }; 2378 2379 /* hwrm_func_vf_resc_free_input (size:192b/24B) */ 2380 struct hwrm_func_vf_resc_free_input { 2381 __le16 req_type; 2382 __le16 cmpl_ring; 2383 __le16 seq_id; 2384 __le16 target_id; 2385 __le64 resp_addr; 2386 __le16 vf_id; 2387 u8 unused_0[6]; 2388 }; 2389 2390 /* hwrm_func_vf_resc_free_output (size:128b/16B) */ 2391 struct hwrm_func_vf_resc_free_output { 2392 __le16 error_code; 2393 __le16 req_type; 2394 __le16 seq_id; 2395 __le16 resp_len; 2396 u8 unused_0[7]; 2397 u8 valid; 2398 }; 2399 2400 /* hwrm_func_drv_rgtr_input (size:896b/112B) */ 2401 struct hwrm_func_drv_rgtr_input { 2402 __le16 req_type; 2403 __le16 cmpl_ring; 2404 __le16 seq_id; 2405 __le16 target_id; 2406 __le64 resp_addr; 2407 __le32 flags; 2408 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 2409 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 2410 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 2411 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 2412 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 2413 #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL 2414 #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL 2415 #define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT 0x80UL 2416 #define FUNC_DRV_RGTR_REQ_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT 0x100UL 2417 #define FUNC_DRV_RGTR_REQ_FLAGS_NPAR_1_2_SUPPORT 0x200UL 2418 #define FUNC_DRV_RGTR_REQ_FLAGS_ASYM_QUEUE_CFG_SUPPORT 0x400UL 2419 __le32 enables; 2420 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 2421 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 2422 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 2423 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 2424 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 2425 __le16 os_type; 2426 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 2427 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 2428 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 2429 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 2430 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 2431 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 2432 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 2433 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 2434 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 2435 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 2436 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 2437 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 2438 u8 ver_maj_8b; 2439 u8 ver_min_8b; 2440 u8 ver_upd_8b; 2441 u8 unused_0[3]; 2442 __le32 timestamp; 2443 u8 unused_1[4]; 2444 __le32 vf_req_fwd[8]; 2445 __le32 async_event_fwd[8]; 2446 __le16 ver_maj; 2447 __le16 ver_min; 2448 __le16 ver_upd; 2449 __le16 ver_patch; 2450 }; 2451 2452 /* hwrm_func_drv_rgtr_output (size:128b/16B) */ 2453 struct hwrm_func_drv_rgtr_output { 2454 __le16 error_code; 2455 __le16 req_type; 2456 __le16 seq_id; 2457 __le16 resp_len; 2458 __le32 flags; 2459 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 2460 u8 unused_0[3]; 2461 u8 valid; 2462 }; 2463 2464 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 2465 struct hwrm_func_drv_unrgtr_input { 2466 __le16 req_type; 2467 __le16 cmpl_ring; 2468 __le16 seq_id; 2469 __le16 target_id; 2470 __le64 resp_addr; 2471 __le32 flags; 2472 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 2473 u8 unused_0[4]; 2474 }; 2475 2476 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 2477 struct hwrm_func_drv_unrgtr_output { 2478 __le16 error_code; 2479 __le16 req_type; 2480 __le16 seq_id; 2481 __le16 resp_len; 2482 u8 unused_0[7]; 2483 u8 valid; 2484 }; 2485 2486 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 2487 struct hwrm_func_buf_rgtr_input { 2488 __le16 req_type; 2489 __le16 cmpl_ring; 2490 __le16 seq_id; 2491 __le16 target_id; 2492 __le64 resp_addr; 2493 __le32 enables; 2494 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 2495 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 2496 __le16 vf_id; 2497 __le16 req_buf_num_pages; 2498 __le16 req_buf_page_size; 2499 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 2500 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 2501 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 2502 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 2503 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 2504 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 2505 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 2506 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 2507 __le16 req_buf_len; 2508 __le16 resp_buf_len; 2509 u8 unused_0[2]; 2510 __le64 req_buf_page_addr0; 2511 __le64 req_buf_page_addr1; 2512 __le64 req_buf_page_addr2; 2513 __le64 req_buf_page_addr3; 2514 __le64 req_buf_page_addr4; 2515 __le64 req_buf_page_addr5; 2516 __le64 req_buf_page_addr6; 2517 __le64 req_buf_page_addr7; 2518 __le64 req_buf_page_addr8; 2519 __le64 req_buf_page_addr9; 2520 __le64 error_buf_addr; 2521 __le64 resp_buf_addr; 2522 }; 2523 2524 /* hwrm_func_buf_rgtr_output (size:128b/16B) */ 2525 struct hwrm_func_buf_rgtr_output { 2526 __le16 error_code; 2527 __le16 req_type; 2528 __le16 seq_id; 2529 __le16 resp_len; 2530 u8 unused_0[7]; 2531 u8 valid; 2532 }; 2533 2534 /* hwrm_func_drv_qver_input (size:192b/24B) */ 2535 struct hwrm_func_drv_qver_input { 2536 __le16 req_type; 2537 __le16 cmpl_ring; 2538 __le16 seq_id; 2539 __le16 target_id; 2540 __le64 resp_addr; 2541 __le32 reserved; 2542 __le16 fid; 2543 u8 driver_type; 2544 #define FUNC_DRV_QVER_REQ_DRIVER_TYPE_L2 0x0UL 2545 #define FUNC_DRV_QVER_REQ_DRIVER_TYPE_ROCE 0x1UL 2546 #define FUNC_DRV_QVER_REQ_DRIVER_TYPE_LAST FUNC_DRV_QVER_REQ_DRIVER_TYPE_ROCE 2547 u8 unused_0; 2548 }; 2549 2550 /* hwrm_func_drv_qver_output (size:256b/32B) */ 2551 struct hwrm_func_drv_qver_output { 2552 __le16 error_code; 2553 __le16 req_type; 2554 __le16 seq_id; 2555 __le16 resp_len; 2556 __le16 os_type; 2557 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 2558 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 2559 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 2560 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 2561 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 2562 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 2563 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 2564 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 2565 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 2566 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 2567 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 2568 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 2569 u8 ver_maj_8b; 2570 u8 ver_min_8b; 2571 u8 ver_upd_8b; 2572 u8 unused_0[3]; 2573 __le16 ver_maj; 2574 __le16 ver_min; 2575 __le16 ver_upd; 2576 __le16 ver_patch; 2577 u8 unused_1[7]; 2578 u8 valid; 2579 }; 2580 2581 /* hwrm_func_resource_qcaps_input (size:192b/24B) */ 2582 struct hwrm_func_resource_qcaps_input { 2583 __le16 req_type; 2584 __le16 cmpl_ring; 2585 __le16 seq_id; 2586 __le16 target_id; 2587 __le64 resp_addr; 2588 __le16 fid; 2589 u8 unused_0[6]; 2590 }; 2591 2592 /* hwrm_func_resource_qcaps_output (size:704b/88B) */ 2593 struct hwrm_func_resource_qcaps_output { 2594 __le16 error_code; 2595 __le16 req_type; 2596 __le16 seq_id; 2597 __le16 resp_len; 2598 __le16 max_vfs; 2599 __le16 max_msix; 2600 __le16 vf_reservation_strategy; 2601 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 2602 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 2603 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 2604 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 2605 __le16 min_rsscos_ctx; 2606 __le16 max_rsscos_ctx; 2607 __le16 min_cmpl_rings; 2608 __le16 max_cmpl_rings; 2609 __le16 min_tx_rings; 2610 __le16 max_tx_rings; 2611 __le16 min_rx_rings; 2612 __le16 max_rx_rings; 2613 __le16 min_l2_ctxs; 2614 __le16 max_l2_ctxs; 2615 __le16 min_vnics; 2616 __le16 max_vnics; 2617 __le16 min_stat_ctx; 2618 __le16 max_stat_ctx; 2619 __le16 min_hw_ring_grps; 2620 __le16 max_hw_ring_grps; 2621 __le16 max_tx_scheduler_inputs; 2622 __le16 flags; 2623 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 2624 __le16 min_msix; 2625 __le32 min_ktls_tx_key_ctxs; 2626 __le32 max_ktls_tx_key_ctxs; 2627 __le32 min_ktls_rx_key_ctxs; 2628 __le32 max_ktls_rx_key_ctxs; 2629 __le32 min_quic_tx_key_ctxs; 2630 __le32 max_quic_tx_key_ctxs; 2631 __le32 min_quic_rx_key_ctxs; 2632 __le32 max_quic_rx_key_ctxs; 2633 u8 unused_0[3]; 2634 u8 valid; 2635 }; 2636 2637 /* hwrm_func_vf_resource_cfg_input (size:704b/88B) */ 2638 struct hwrm_func_vf_resource_cfg_input { 2639 __le16 req_type; 2640 __le16 cmpl_ring; 2641 __le16 seq_id; 2642 __le16 target_id; 2643 __le64 resp_addr; 2644 __le16 vf_id; 2645 __le16 max_msix; 2646 __le16 min_rsscos_ctx; 2647 __le16 max_rsscos_ctx; 2648 __le16 min_cmpl_rings; 2649 __le16 max_cmpl_rings; 2650 __le16 min_tx_rings; 2651 __le16 max_tx_rings; 2652 __le16 min_rx_rings; 2653 __le16 max_rx_rings; 2654 __le16 min_l2_ctxs; 2655 __le16 max_l2_ctxs; 2656 __le16 min_vnics; 2657 __le16 max_vnics; 2658 __le16 min_stat_ctx; 2659 __le16 max_stat_ctx; 2660 __le16 min_hw_ring_grps; 2661 __le16 max_hw_ring_grps; 2662 __le16 flags; 2663 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 2664 __le16 min_msix; 2665 __le32 min_ktls_tx_key_ctxs; 2666 __le32 max_ktls_tx_key_ctxs; 2667 __le32 min_ktls_rx_key_ctxs; 2668 __le32 max_ktls_rx_key_ctxs; 2669 __le32 min_quic_tx_key_ctxs; 2670 __le32 max_quic_tx_key_ctxs; 2671 __le32 min_quic_rx_key_ctxs; 2672 __le32 max_quic_rx_key_ctxs; 2673 }; 2674 2675 /* hwrm_func_vf_resource_cfg_output (size:384b/48B) */ 2676 struct hwrm_func_vf_resource_cfg_output { 2677 __le16 error_code; 2678 __le16 req_type; 2679 __le16 seq_id; 2680 __le16 resp_len; 2681 __le16 reserved_rsscos_ctx; 2682 __le16 reserved_cmpl_rings; 2683 __le16 reserved_tx_rings; 2684 __le16 reserved_rx_rings; 2685 __le16 reserved_l2_ctxs; 2686 __le16 reserved_vnics; 2687 __le16 reserved_stat_ctx; 2688 __le16 reserved_hw_ring_grps; 2689 __le32 reserved_ktls_tx_key_ctxs; 2690 __le32 reserved_ktls_rx_key_ctxs; 2691 __le32 reserved_quic_tx_key_ctxs; 2692 __le32 reserved_quic_rx_key_ctxs; 2693 u8 unused_0[7]; 2694 u8 valid; 2695 }; 2696 2697 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 2698 struct hwrm_func_backing_store_qcaps_input { 2699 __le16 req_type; 2700 __le16 cmpl_ring; 2701 __le16 seq_id; 2702 __le16 target_id; 2703 __le64 resp_addr; 2704 }; 2705 2706 /* hwrm_func_backing_store_qcaps_output (size:832b/104B) */ 2707 struct hwrm_func_backing_store_qcaps_output { 2708 __le16 error_code; 2709 __le16 req_type; 2710 __le16 seq_id; 2711 __le16 resp_len; 2712 __le32 qp_max_entries; 2713 __le16 qp_min_qp1_entries; 2714 __le16 qp_max_l2_entries; 2715 __le16 qp_entry_size; 2716 __le16 srq_max_l2_entries; 2717 __le32 srq_max_entries; 2718 __le16 srq_entry_size; 2719 __le16 cq_max_l2_entries; 2720 __le32 cq_max_entries; 2721 __le16 cq_entry_size; 2722 __le16 vnic_max_vnic_entries; 2723 __le16 vnic_max_ring_table_entries; 2724 __le16 vnic_entry_size; 2725 __le32 stat_max_entries; 2726 __le16 stat_entry_size; 2727 __le16 tqm_entry_size; 2728 __le32 tqm_min_entries_per_ring; 2729 __le32 tqm_max_entries_per_ring; 2730 __le32 mrav_max_entries; 2731 __le16 mrav_entry_size; 2732 __le16 tim_entry_size; 2733 __le32 tim_max_entries; 2734 __le16 mrav_num_entries_units; 2735 u8 tqm_entries_multiple; 2736 u8 ctx_kind_initializer; 2737 __le16 ctx_init_mask; 2738 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_QP 0x1UL 2739 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_SRQ 0x2UL 2740 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_CQ 0x4UL 2741 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_VNIC 0x8UL 2742 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_STAT 0x10UL 2743 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_MRAV 0x20UL 2744 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_TKC 0x40UL 2745 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_RKC 0x80UL 2746 u8 qp_init_offset; 2747 u8 srq_init_offset; 2748 u8 cq_init_offset; 2749 u8 vnic_init_offset; 2750 u8 tqm_fp_rings_count; 2751 u8 stat_init_offset; 2752 u8 mrav_init_offset; 2753 u8 tqm_fp_rings_count_ext; 2754 u8 tkc_init_offset; 2755 u8 rkc_init_offset; 2756 __le16 tkc_entry_size; 2757 __le16 rkc_entry_size; 2758 __le32 tkc_max_entries; 2759 __le32 rkc_max_entries; 2760 __le16 fast_qpmd_qp_num_entries; 2761 u8 rsvd1[5]; 2762 u8 valid; 2763 }; 2764 2765 /* tqm_fp_ring_cfg (size:128b/16B) */ 2766 struct tqm_fp_ring_cfg { 2767 u8 tqm_ring_pg_size_tqm_ring_lvl; 2768 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK 0xfUL 2769 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0 2770 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 0x0UL 2771 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 0x1UL 2772 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 0x2UL 2773 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 2774 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK 0xf0UL 2775 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4 2776 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2777 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2778 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2779 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2780 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2781 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2782 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G 2783 u8 unused[3]; 2784 __le32 tqm_ring_num_entries; 2785 __le64 tqm_ring_page_dir; 2786 }; 2787 2788 /* hwrm_func_backing_store_cfg_input (size:2688b/336B) */ 2789 struct hwrm_func_backing_store_cfg_input { 2790 __le16 req_type; 2791 __le16 cmpl_ring; 2792 __le16 seq_id; 2793 __le16 target_id; 2794 __le64 resp_addr; 2795 __le32 flags; 2796 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 2797 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL 2798 __le32 enables; 2799 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 2800 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 2801 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 2802 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 2803 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 2804 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 2805 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 2806 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 2807 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 2808 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 2809 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 2810 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 2811 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 2812 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 2813 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 2814 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 2815 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING8 0x10000UL 2816 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING9 0x20000UL 2817 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING10 0x40000UL 2818 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TKC 0x80000UL 2819 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_RKC 0x100000UL 2820 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP_FAST_QPMD 0x200000UL 2821 u8 qpc_pg_size_qpc_lvl; 2822 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 2823 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 2824 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 2825 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 2826 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 2827 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 2828 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 2829 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 2830 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 2831 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 2832 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 2833 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 2834 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 2835 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 2836 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 2837 u8 srq_pg_size_srq_lvl; 2838 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 2839 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 2840 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 2841 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 2842 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 2843 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 2844 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 2845 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 2846 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 2847 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 2848 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 2849 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 2850 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 2851 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 2852 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 2853 u8 cq_pg_size_cq_lvl; 2854 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 2855 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 2856 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 2857 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 2858 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 2859 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 2860 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 2861 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 2862 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 2863 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 2864 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 2865 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 2866 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 2867 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 2868 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 2869 u8 vnic_pg_size_vnic_lvl; 2870 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 2871 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 2872 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 2873 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 2874 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 2875 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 2876 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 2877 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 2878 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 2879 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 2880 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 2881 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 2882 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 2883 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 2884 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 2885 u8 stat_pg_size_stat_lvl; 2886 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 2887 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 2888 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 2889 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 2890 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 2891 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 2892 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 2893 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 2894 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 2895 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 2896 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 2897 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 2898 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 2899 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 2900 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 2901 u8 tqm_sp_pg_size_tqm_sp_lvl; 2902 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 2903 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 2904 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 2905 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 2906 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 2907 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 2908 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 2909 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 2910 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 2911 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 2912 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 2913 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 2914 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 2915 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 2916 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 2917 u8 tqm_ring0_pg_size_tqm_ring0_lvl; 2918 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 2919 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 2920 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 2921 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 2922 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 2923 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 2924 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 2925 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 2926 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 2927 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 2928 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 2929 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 2930 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 2931 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 2932 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 2933 u8 tqm_ring1_pg_size_tqm_ring1_lvl; 2934 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 2935 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 2936 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 2937 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 2938 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 2939 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 2940 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 2941 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 2942 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 2943 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 2944 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 2945 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 2946 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 2947 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 2948 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 2949 u8 tqm_ring2_pg_size_tqm_ring2_lvl; 2950 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 2951 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 2952 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 2953 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 2954 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 2955 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 2956 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 2957 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 2958 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 2959 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 2960 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 2961 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 2962 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 2963 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 2964 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 2965 u8 tqm_ring3_pg_size_tqm_ring3_lvl; 2966 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 2967 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 2968 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 2969 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 2970 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 2971 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 2972 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 2973 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 2974 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 2975 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 2976 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 2977 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 2978 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 2979 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 2980 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 2981 u8 tqm_ring4_pg_size_tqm_ring4_lvl; 2982 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 2983 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 2984 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 2985 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 2986 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 2987 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 2988 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 2989 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 2990 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 2991 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 2992 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 2993 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 2994 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 2995 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 2996 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 2997 u8 tqm_ring5_pg_size_tqm_ring5_lvl; 2998 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 2999 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 3000 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 3001 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 3002 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 3003 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 3004 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 3005 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 3006 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 3007 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 3008 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 3009 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 3010 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 3011 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 3012 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 3013 u8 tqm_ring6_pg_size_tqm_ring6_lvl; 3014 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 3015 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 3016 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 3017 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 3018 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 3019 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 3020 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 3021 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 3022 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 3023 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 3024 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 3025 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 3026 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 3027 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 3028 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 3029 u8 tqm_ring7_pg_size_tqm_ring7_lvl; 3030 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 3031 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 3032 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 3033 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 3034 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 3035 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 3036 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 3037 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 3038 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 3039 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 3040 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 3041 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 3042 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 3043 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 3044 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 3045 u8 mrav_pg_size_mrav_lvl; 3046 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 3047 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 3048 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 3049 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL 3050 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 3051 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 3052 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 3053 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 3054 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 3055 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 3056 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 3057 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 3058 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 3059 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 3060 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 3061 u8 tim_pg_size_tim_lvl; 3062 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 3063 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 3064 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 3065 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 3066 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 3067 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 3068 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 3069 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 3070 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 3071 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 3072 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 3073 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 3074 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 3075 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 3076 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 3077 __le64 qpc_page_dir; 3078 __le64 srq_page_dir; 3079 __le64 cq_page_dir; 3080 __le64 vnic_page_dir; 3081 __le64 stat_page_dir; 3082 __le64 tqm_sp_page_dir; 3083 __le64 tqm_ring0_page_dir; 3084 __le64 tqm_ring1_page_dir; 3085 __le64 tqm_ring2_page_dir; 3086 __le64 tqm_ring3_page_dir; 3087 __le64 tqm_ring4_page_dir; 3088 __le64 tqm_ring5_page_dir; 3089 __le64 tqm_ring6_page_dir; 3090 __le64 tqm_ring7_page_dir; 3091 __le64 mrav_page_dir; 3092 __le64 tim_page_dir; 3093 __le32 qp_num_entries; 3094 __le32 srq_num_entries; 3095 __le32 cq_num_entries; 3096 __le32 stat_num_entries; 3097 __le32 tqm_sp_num_entries; 3098 __le32 tqm_ring0_num_entries; 3099 __le32 tqm_ring1_num_entries; 3100 __le32 tqm_ring2_num_entries; 3101 __le32 tqm_ring3_num_entries; 3102 __le32 tqm_ring4_num_entries; 3103 __le32 tqm_ring5_num_entries; 3104 __le32 tqm_ring6_num_entries; 3105 __le32 tqm_ring7_num_entries; 3106 __le32 mrav_num_entries; 3107 __le32 tim_num_entries; 3108 __le16 qp_num_qp1_entries; 3109 __le16 qp_num_l2_entries; 3110 __le16 qp_entry_size; 3111 __le16 srq_num_l2_entries; 3112 __le16 srq_entry_size; 3113 __le16 cq_num_l2_entries; 3114 __le16 cq_entry_size; 3115 __le16 vnic_num_vnic_entries; 3116 __le16 vnic_num_ring_table_entries; 3117 __le16 vnic_entry_size; 3118 __le16 stat_entry_size; 3119 __le16 tqm_entry_size; 3120 __le16 mrav_entry_size; 3121 __le16 tim_entry_size; 3122 u8 tqm_ring8_pg_size_tqm_ring_lvl; 3123 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_MASK 0xfUL 3124 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_SFT 0 3125 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_0 0x0UL 3126 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_1 0x1UL 3127 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 0x2UL 3128 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 3129 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_MASK 0xf0UL 3130 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_SFT 4 3131 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 3132 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 3133 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 3134 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 3135 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 3136 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 3137 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G 3138 u8 ring8_unused[3]; 3139 __le32 tqm_ring8_num_entries; 3140 __le64 tqm_ring8_page_dir; 3141 u8 tqm_ring9_pg_size_tqm_ring_lvl; 3142 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_MASK 0xfUL 3143 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_SFT 0 3144 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_0 0x0UL 3145 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_1 0x1UL 3146 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 0x2UL 3147 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 3148 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_MASK 0xf0UL 3149 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_SFT 4 3150 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 3151 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 3152 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 3153 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 3154 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 3155 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 3156 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G 3157 u8 ring9_unused[3]; 3158 __le32 tqm_ring9_num_entries; 3159 __le64 tqm_ring9_page_dir; 3160 u8 tqm_ring10_pg_size_tqm_ring_lvl; 3161 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_MASK 0xfUL 3162 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_SFT 0 3163 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_0 0x0UL 3164 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_1 0x1UL 3165 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 0x2UL 3166 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 3167 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_MASK 0xf0UL 3168 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_SFT 4 3169 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 3170 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 3171 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 3172 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 3173 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 3174 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 3175 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G 3176 u8 ring10_unused[3]; 3177 __le32 tqm_ring10_num_entries; 3178 __le64 tqm_ring10_page_dir; 3179 __le32 tkc_num_entries; 3180 __le32 rkc_num_entries; 3181 __le64 tkc_page_dir; 3182 __le64 rkc_page_dir; 3183 __le16 tkc_entry_size; 3184 __le16 rkc_entry_size; 3185 u8 tkc_pg_size_tkc_lvl; 3186 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_MASK 0xfUL 3187 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_SFT 0 3188 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_0 0x0UL 3189 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_1 0x1UL 3190 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 0x2UL 3191 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 3192 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_MASK 0xf0UL 3193 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_SFT 4 3194 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_4K (0x0UL << 4) 3195 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8K (0x1UL << 4) 3196 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_64K (0x2UL << 4) 3197 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_2M (0x3UL << 4) 3198 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8M (0x4UL << 4) 3199 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G (0x5UL << 4) 3200 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G 3201 u8 rkc_pg_size_rkc_lvl; 3202 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_MASK 0xfUL 3203 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_SFT 0 3204 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_0 0x0UL 3205 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_1 0x1UL 3206 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 0x2UL 3207 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 3208 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_MASK 0xf0UL 3209 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_SFT 4 3210 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_4K (0x0UL << 4) 3211 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8K (0x1UL << 4) 3212 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_64K (0x2UL << 4) 3213 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_2M (0x3UL << 4) 3214 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8M (0x4UL << 4) 3215 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G (0x5UL << 4) 3216 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G 3217 __le16 qp_num_fast_qpmd_entries; 3218 }; 3219 3220 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 3221 struct hwrm_func_backing_store_cfg_output { 3222 __le16 error_code; 3223 __le16 req_type; 3224 __le16 seq_id; 3225 __le16 resp_len; 3226 u8 unused_0[7]; 3227 u8 valid; 3228 }; 3229 3230 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */ 3231 struct hwrm_error_recovery_qcfg_input { 3232 __le16 req_type; 3233 __le16 cmpl_ring; 3234 __le16 seq_id; 3235 __le16 target_id; 3236 __le64 resp_addr; 3237 u8 unused_0[8]; 3238 }; 3239 3240 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ 3241 struct hwrm_error_recovery_qcfg_output { 3242 __le16 error_code; 3243 __le16 req_type; 3244 __le16 seq_id; 3245 __le16 resp_len; 3246 __le32 flags; 3247 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL 3248 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL 3249 __le32 driver_polling_freq; 3250 __le32 master_func_wait_period; 3251 __le32 normal_func_wait_period; 3252 __le32 master_func_wait_period_after_reset; 3253 __le32 max_bailout_time_after_reset; 3254 __le32 fw_health_status_reg; 3255 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL 3256 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0 3257 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3258 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL 3259 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL 3260 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL 3261 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 3262 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL 3263 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2 3264 __le32 fw_heartbeat_reg; 3265 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL 3266 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0 3267 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3268 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL 3269 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL 3270 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL 3271 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 3272 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL 3273 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2 3274 __le32 fw_reset_cnt_reg; 3275 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL 3276 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0 3277 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3278 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL 3279 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL 3280 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL 3281 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 3282 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL 3283 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2 3284 __le32 reset_inprogress_reg; 3285 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL 3286 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0 3287 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3288 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL 3289 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL 3290 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL 3291 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 3292 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL 3293 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2 3294 __le32 reset_inprogress_reg_mask; 3295 u8 unused_0[3]; 3296 u8 reg_array_cnt; 3297 __le32 reset_reg[16]; 3298 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL 3299 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0 3300 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3301 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL 3302 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL 3303 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL 3304 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 3305 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL 3306 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2 3307 __le32 reset_reg_val[16]; 3308 u8 delay_after_reset[16]; 3309 __le32 err_recovery_cnt_reg; 3310 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL 3311 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0 3312 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3313 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL 3314 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL 3315 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL 3316 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 3317 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL 3318 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2 3319 u8 unused_1[3]; 3320 u8 valid; 3321 }; 3322 3323 /* hwrm_func_echo_response_input (size:192b/24B) */ 3324 struct hwrm_func_echo_response_input { 3325 __le16 req_type; 3326 __le16 cmpl_ring; 3327 __le16 seq_id; 3328 __le16 target_id; 3329 __le64 resp_addr; 3330 __le32 event_data1; 3331 __le32 event_data2; 3332 }; 3333 3334 /* hwrm_func_echo_response_output (size:128b/16B) */ 3335 struct hwrm_func_echo_response_output { 3336 __le16 error_code; 3337 __le16 req_type; 3338 __le16 seq_id; 3339 __le16 resp_len; 3340 u8 unused_0[7]; 3341 u8 valid; 3342 }; 3343 3344 /* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */ 3345 struct hwrm_func_ptp_pin_qcfg_input { 3346 __le16 req_type; 3347 __le16 cmpl_ring; 3348 __le16 seq_id; 3349 __le16 target_id; 3350 __le64 resp_addr; 3351 u8 unused_0[8]; 3352 }; 3353 3354 /* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */ 3355 struct hwrm_func_ptp_pin_qcfg_output { 3356 __le16 error_code; 3357 __le16 req_type; 3358 __le16 seq_id; 3359 __le16 resp_len; 3360 u8 num_pins; 3361 u8 state; 3362 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN0_ENABLED 0x1UL 3363 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN1_ENABLED 0x2UL 3364 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN2_ENABLED 0x4UL 3365 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN3_ENABLED 0x8UL 3366 u8 pin0_usage; 3367 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_NONE 0x0UL 3368 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_IN 0x1UL 3369 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_OUT 0x2UL 3370 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_IN 0x3UL 3371 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 0x4UL 3372 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 3373 u8 pin1_usage; 3374 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_NONE 0x0UL 3375 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_IN 0x1UL 3376 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_OUT 0x2UL 3377 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_IN 0x3UL 3378 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 0x4UL 3379 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 3380 u8 pin2_usage; 3381 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_NONE 0x0UL 3382 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_IN 0x1UL 3383 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_OUT 0x2UL 3384 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_IN 0x3UL 3385 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 0x4UL 3386 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3387 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3388 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3389 u8 pin3_usage; 3390 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_NONE 0x0UL 3391 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_IN 0x1UL 3392 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_OUT 0x2UL 3393 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_IN 0x3UL 3394 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 0x4UL 3395 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3396 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3397 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3398 u8 unused_0; 3399 u8 valid; 3400 }; 3401 3402 /* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */ 3403 struct hwrm_func_ptp_pin_cfg_input { 3404 __le16 req_type; 3405 __le16 cmpl_ring; 3406 __le16 seq_id; 3407 __le16 target_id; 3408 __le64 resp_addr; 3409 __le32 enables; 3410 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE 0x1UL 3411 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE 0x2UL 3412 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_STATE 0x4UL 3413 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_USAGE 0x8UL 3414 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_STATE 0x10UL 3415 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_USAGE 0x20UL 3416 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_STATE 0x40UL 3417 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_USAGE 0x80UL 3418 u8 pin0_state; 3419 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_DISABLED 0x0UL 3420 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 0x1UL 3421 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 3422 u8 pin0_usage; 3423 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_NONE 0x0UL 3424 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_IN 0x1UL 3425 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_OUT 0x2UL 3426 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_IN 0x3UL 3427 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 0x4UL 3428 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 3429 u8 pin1_state; 3430 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_DISABLED 0x0UL 3431 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 0x1UL 3432 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 3433 u8 pin1_usage; 3434 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_NONE 0x0UL 3435 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_IN 0x1UL 3436 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_OUT 0x2UL 3437 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_IN 0x3UL 3438 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 0x4UL 3439 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 3440 u8 pin2_state; 3441 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_DISABLED 0x0UL 3442 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 0x1UL 3443 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 3444 u8 pin2_usage; 3445 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_NONE 0x0UL 3446 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_IN 0x1UL 3447 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_OUT 0x2UL 3448 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_IN 0x3UL 3449 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 0x4UL 3450 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3451 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3452 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3453 u8 pin3_state; 3454 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_DISABLED 0x0UL 3455 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 0x1UL 3456 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 3457 u8 pin3_usage; 3458 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_NONE 0x0UL 3459 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_IN 0x1UL 3460 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_OUT 0x2UL 3461 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_IN 0x3UL 3462 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 0x4UL 3463 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3464 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3465 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3466 u8 unused_0[4]; 3467 }; 3468 3469 /* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */ 3470 struct hwrm_func_ptp_pin_cfg_output { 3471 __le16 error_code; 3472 __le16 req_type; 3473 __le16 seq_id; 3474 __le16 resp_len; 3475 u8 unused_0[7]; 3476 u8 valid; 3477 }; 3478 3479 /* hwrm_func_ptp_cfg_input (size:384b/48B) */ 3480 struct hwrm_func_ptp_cfg_input { 3481 __le16 req_type; 3482 __le16 cmpl_ring; 3483 __le16 seq_id; 3484 __le16 target_id; 3485 __le64 resp_addr; 3486 __le16 enables; 3487 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT 0x1UL 3488 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE 0x2UL 3489 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_PHASE 0x4UL 3490 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD 0x8UL 3491 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP 0x10UL 3492 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE 0x20UL 3493 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME 0x40UL 3494 u8 ptp_pps_event; 3495 #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_INTERNAL 0x1UL 3496 #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_EXTERNAL 0x2UL 3497 u8 ptp_freq_adj_dll_source; 3498 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_NONE 0x0UL 3499 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 0x1UL 3500 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 0x2UL 3501 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 0x3UL 3502 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 0x4UL 3503 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 0x5UL 3504 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 0x6UL 3505 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 0x7UL 3506 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 0x8UL 3507 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 0xffUL 3508 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 3509 u8 ptp_freq_adj_dll_phase; 3510 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_NONE 0x0UL 3511 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_4K 0x1UL 3512 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_8K 0x2UL 3513 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M 0x3UL 3514 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_25M 0x4UL 3515 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_25M 3516 u8 unused_0[3]; 3517 __le32 ptp_freq_adj_ext_period; 3518 __le32 ptp_freq_adj_ext_up; 3519 __le32 ptp_freq_adj_ext_phase_lower; 3520 __le32 ptp_freq_adj_ext_phase_upper; 3521 __le64 ptp_set_time; 3522 }; 3523 3524 /* hwrm_func_ptp_cfg_output (size:128b/16B) */ 3525 struct hwrm_func_ptp_cfg_output { 3526 __le16 error_code; 3527 __le16 req_type; 3528 __le16 seq_id; 3529 __le16 resp_len; 3530 u8 unused_0[7]; 3531 u8 valid; 3532 }; 3533 3534 /* hwrm_func_ptp_ts_query_input (size:192b/24B) */ 3535 struct hwrm_func_ptp_ts_query_input { 3536 __le16 req_type; 3537 __le16 cmpl_ring; 3538 __le16 seq_id; 3539 __le16 target_id; 3540 __le64 resp_addr; 3541 __le32 flags; 3542 #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PPS_TIME 0x1UL 3543 #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PTM_TIME 0x2UL 3544 u8 unused_0[4]; 3545 }; 3546 3547 /* hwrm_func_ptp_ts_query_output (size:320b/40B) */ 3548 struct hwrm_func_ptp_ts_query_output { 3549 __le16 error_code; 3550 __le16 req_type; 3551 __le16 seq_id; 3552 __le16 resp_len; 3553 __le64 pps_event_ts; 3554 __le64 ptm_local_ts; 3555 __le64 ptm_system_ts; 3556 __le32 ptm_link_delay; 3557 u8 unused_0[3]; 3558 u8 valid; 3559 }; 3560 3561 /* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */ 3562 struct hwrm_func_ptp_ext_cfg_input { 3563 __le16 req_type; 3564 __le16 cmpl_ring; 3565 __le16 seq_id; 3566 __le16 target_id; 3567 __le64 resp_addr; 3568 __le16 enables; 3569 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_MASTER_FID 0x1UL 3570 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_FID 0x2UL 3571 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_MODE 0x4UL 3572 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_FAILOVER_TIMER 0x8UL 3573 __le16 phc_master_fid; 3574 __le16 phc_sec_fid; 3575 u8 phc_sec_mode; 3576 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_SWITCH 0x0UL 3577 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_ALL 0x1UL 3578 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY 0x2UL 3579 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_LAST FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY 3580 u8 unused_0; 3581 __le32 failover_timer; 3582 u8 unused_1[4]; 3583 }; 3584 3585 /* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */ 3586 struct hwrm_func_ptp_ext_cfg_output { 3587 __le16 error_code; 3588 __le16 req_type; 3589 __le16 seq_id; 3590 __le16 resp_len; 3591 u8 unused_0[7]; 3592 u8 valid; 3593 }; 3594 3595 /* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */ 3596 struct hwrm_func_ptp_ext_qcfg_input { 3597 __le16 req_type; 3598 __le16 cmpl_ring; 3599 __le16 seq_id; 3600 __le16 target_id; 3601 __le64 resp_addr; 3602 u8 unused_0[8]; 3603 }; 3604 3605 /* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */ 3606 struct hwrm_func_ptp_ext_qcfg_output { 3607 __le16 error_code; 3608 __le16 req_type; 3609 __le16 seq_id; 3610 __le16 resp_len; 3611 __le16 phc_master_fid; 3612 __le16 phc_sec_fid; 3613 __le16 phc_active_fid0; 3614 __le16 phc_active_fid1; 3615 __le32 last_failover_event; 3616 __le16 from_fid; 3617 __le16 to_fid; 3618 u8 unused_0[7]; 3619 u8 valid; 3620 }; 3621 3622 /* hwrm_func_backing_store_cfg_v2_input (size:448b/56B) */ 3623 struct hwrm_func_backing_store_cfg_v2_input { 3624 __le16 req_type; 3625 __le16 cmpl_ring; 3626 __le16 seq_id; 3627 __le16 target_id; 3628 __le64 resp_addr; 3629 __le16 type; 3630 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QP 0x0UL 3631 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ 0x1UL 3632 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ 0x2UL 3633 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_VNIC 0x3UL 3634 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_STAT 0x4UL 3635 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3636 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3637 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MRAV 0xeUL 3638 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TIM 0xfUL 3639 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TKC 0x13UL 3640 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RKC 0x14UL 3641 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3642 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3643 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3644 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3645 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3646 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QUIC_TKC 0x1aUL 3647 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QUIC_RKC 0x1bUL 3648 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 3649 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_XID_PARTITION 0x1dUL 3650 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 0xffffUL 3651 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 3652 __le16 instance; 3653 __le32 flags; 3654 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_PREBOOT_MODE 0x1UL 3655 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_CFG_ALL_DONE 0x2UL 3656 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_EXTEND 0x4UL 3657 __le64 page_dir; 3658 __le32 num_entries; 3659 __le16 entry_size; 3660 u8 page_size_pbl_level; 3661 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_MASK 0xfUL 3662 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_SFT 0 3663 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_0 0x0UL 3664 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_1 0x1UL 3665 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2 0x2UL 3666 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2 3667 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_MASK 0xf0UL 3668 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_SFT 4 3669 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_4K (0x0UL << 4) 3670 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8K (0x1UL << 4) 3671 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_64K (0x2UL << 4) 3672 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_2M (0x3UL << 4) 3673 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8M (0x4UL << 4) 3674 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G (0x5UL << 4) 3675 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G 3676 u8 subtype_valid_cnt; 3677 __le32 split_entry_0; 3678 __le32 split_entry_1; 3679 __le32 split_entry_2; 3680 __le32 split_entry_3; 3681 }; 3682 3683 /* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */ 3684 struct hwrm_func_backing_store_cfg_v2_output { 3685 __le16 error_code; 3686 __le16 req_type; 3687 __le16 seq_id; 3688 __le16 resp_len; 3689 u8 rsvd0[7]; 3690 u8 valid; 3691 }; 3692 3693 /* hwrm_func_backing_store_qcfg_v2_input (size:192b/24B) */ 3694 struct hwrm_func_backing_store_qcfg_v2_input { 3695 __le16 req_type; 3696 __le16 cmpl_ring; 3697 __le16 seq_id; 3698 __le16 target_id; 3699 __le64 resp_addr; 3700 __le16 type; 3701 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QP 0x0UL 3702 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ 0x1UL 3703 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ 0x2UL 3704 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_VNIC 0x3UL 3705 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_STAT 0x4UL 3706 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3707 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3708 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MRAV 0xeUL 3709 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TIM 0xfUL 3710 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TKC 0x13UL 3711 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RKC 0x14UL 3712 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3713 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3714 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3715 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3716 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3717 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QUIC_TKC 0x1aUL 3718 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QUIC_RKC 0x1bUL 3719 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 3720 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_XID_PARTITION_TABLE 0x1dUL 3721 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 0xffffUL 3722 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 3723 __le16 instance; 3724 u8 rsvd[4]; 3725 }; 3726 3727 /* hwrm_func_backing_store_qcfg_v2_output (size:448b/56B) */ 3728 struct hwrm_func_backing_store_qcfg_v2_output { 3729 __le16 error_code; 3730 __le16 req_type; 3731 __le16 seq_id; 3732 __le16 resp_len; 3733 __le16 type; 3734 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QP 0x0UL 3735 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRQ 0x1UL 3736 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CQ 0x2UL 3737 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_VNIC 0x3UL 3738 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_STAT 0x4UL 3739 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SP_TQM_RING 0x5UL 3740 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_FP_TQM_RING 0x6UL 3741 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MRAV 0xeUL 3742 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TIM 0xfUL 3743 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TKC 0x13UL 3744 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RKC 0x14UL 3745 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MP_TQM_RING 0x15UL 3746 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QUIC_TKC 0x1aUL 3747 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QUIC_RKC 0x1bUL 3748 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TBL_SCOPE 0x1cUL 3749 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_XID_PARTITION 0x1dUL 3750 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 0xffffUL 3751 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 3752 __le16 instance; 3753 __le32 flags; 3754 __le64 page_dir; 3755 __le32 num_entries; 3756 u8 page_size_pbl_level; 3757 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_MASK 0xfUL 3758 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_SFT 0 3759 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_0 0x0UL 3760 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_1 0x1UL 3761 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2 0x2UL 3762 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2 3763 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_MASK 0xf0UL 3764 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_SFT 4 3765 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_4K (0x0UL << 4) 3766 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8K (0x1UL << 4) 3767 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_64K (0x2UL << 4) 3768 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_2M (0x3UL << 4) 3769 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8M (0x4UL << 4) 3770 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G (0x5UL << 4) 3771 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G 3772 u8 subtype_valid_cnt; 3773 u8 rsvd[2]; 3774 __le32 split_entry_0; 3775 __le32 split_entry_1; 3776 __le32 split_entry_2; 3777 __le32 split_entry_3; 3778 u8 rsvd2[7]; 3779 u8 valid; 3780 }; 3781 3782 /* qpc_split_entries (size:128b/16B) */ 3783 struct qpc_split_entries { 3784 __le32 qp_num_l2_entries; 3785 __le32 qp_num_qp1_entries; 3786 __le32 qp_num_fast_qpmd_entries; 3787 __le32 rsvd; 3788 }; 3789 3790 /* srq_split_entries (size:128b/16B) */ 3791 struct srq_split_entries { 3792 __le32 srq_num_l2_entries; 3793 __le32 rsvd; 3794 __le32 rsvd2[2]; 3795 }; 3796 3797 /* cq_split_entries (size:128b/16B) */ 3798 struct cq_split_entries { 3799 __le32 cq_num_l2_entries; 3800 __le32 rsvd; 3801 __le32 rsvd2[2]; 3802 }; 3803 3804 /* vnic_split_entries (size:128b/16B) */ 3805 struct vnic_split_entries { 3806 __le32 vnic_num_vnic_entries; 3807 __le32 rsvd; 3808 __le32 rsvd2[2]; 3809 }; 3810 3811 /* mrav_split_entries (size:128b/16B) */ 3812 struct mrav_split_entries { 3813 __le32 mrav_num_av_entries; 3814 __le32 rsvd; 3815 __le32 rsvd2[2]; 3816 }; 3817 3818 /* ts_split_entries (size:128b/16B) */ 3819 struct ts_split_entries { 3820 __le32 region_num_entries; 3821 u8 tsid; 3822 u8 lkup_static_bkt_cnt_exp[2]; 3823 u8 rsvd; 3824 __le32 rsvd2[2]; 3825 }; 3826 3827 /* hwrm_func_backing_store_qcaps_v2_input (size:192b/24B) */ 3828 struct hwrm_func_backing_store_qcaps_v2_input { 3829 __le16 req_type; 3830 __le16 cmpl_ring; 3831 __le16 seq_id; 3832 __le16 target_id; 3833 __le64 resp_addr; 3834 __le16 type; 3835 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP 0x0UL 3836 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ 0x1UL 3837 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ 0x2UL 3838 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC 0x3UL 3839 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT 0x4UL 3840 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3841 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3842 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV 0xeUL 3843 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM 0xfUL 3844 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_KTLS_TKC 0x13UL 3845 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_KTLS_RKC 0x14UL 3846 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3847 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3848 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3849 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3850 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3851 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_TKC 0x1aUL 3852 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_RKC 0x1bUL 3853 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 3854 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_XID_PARTITION 0x1dUL 3855 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 0xffffUL 3856 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 3857 u8 rsvd[6]; 3858 }; 3859 3860 /* hwrm_func_backing_store_qcaps_v2_output (size:448b/56B) */ 3861 struct hwrm_func_backing_store_qcaps_v2_output { 3862 __le16 error_code; 3863 __le16 req_type; 3864 __le16 seq_id; 3865 __le16 resp_len; 3866 __le16 type; 3867 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QP 0x0UL 3868 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ 0x1UL 3869 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ 0x2UL 3870 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_VNIC 0x3UL 3871 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_STAT 0x4UL 3872 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SP_TQM_RING 0x5UL 3873 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_FP_TQM_RING 0x6UL 3874 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MRAV 0xeUL 3875 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TIM 0xfUL 3876 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_KTLS_TKC 0x13UL 3877 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_KTLS_RKC 0x14UL 3878 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MP_TQM_RING 0x15UL 3879 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SQ_DB_SHADOW 0x16UL 3880 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RQ_DB_SHADOW 0x17UL 3881 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ_DB_SHADOW 0x18UL 3882 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ_DB_SHADOW 0x19UL 3883 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QUIC_TKC 0x1aUL 3884 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QUIC_RKC 0x1bUL 3885 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TBL_SCOPE 0x1cUL 3886 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_XID_PARTITION 0x1dUL 3887 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 0xffffUL 3888 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 3889 __le16 entry_size; 3890 __le32 flags; 3891 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ENABLE_CTX_KIND_INIT 0x1UL 3892 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID 0x2UL 3893 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_DRIVER_MANAGED_MEMORY 0x4UL 3894 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ROCE_QP_PSEUDO_STATIC_ALLOC 0x8UL 3895 __le32 instance_bit_map; 3896 u8 ctx_init_value; 3897 u8 ctx_init_offset; 3898 u8 entry_multiple; 3899 u8 rsvd; 3900 __le32 max_num_entries; 3901 __le32 min_num_entries; 3902 __le16 next_valid_type; 3903 u8 subtype_valid_cnt; 3904 u8 exact_cnt_bit_map; 3905 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_0_EXACT 0x1UL 3906 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_1_EXACT 0x2UL 3907 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_2_EXACT 0x4UL 3908 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_3_EXACT 0x8UL 3909 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_UNUSED_MASK 0xf0UL 3910 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_UNUSED_SFT 4 3911 __le32 split_entry_0; 3912 __le32 split_entry_1; 3913 __le32 split_entry_2; 3914 __le32 split_entry_3; 3915 u8 rsvd3[3]; 3916 u8 valid; 3917 }; 3918 3919 /* hwrm_func_dbr_pacing_qcfg_input (size:128b/16B) */ 3920 struct hwrm_func_dbr_pacing_qcfg_input { 3921 __le16 req_type; 3922 __le16 cmpl_ring; 3923 __le16 seq_id; 3924 __le16 target_id; 3925 __le64 resp_addr; 3926 }; 3927 3928 /* hwrm_func_dbr_pacing_qcfg_output (size:512b/64B) */ 3929 struct hwrm_func_dbr_pacing_qcfg_output { 3930 __le16 error_code; 3931 __le16 req_type; 3932 __le16 seq_id; 3933 __le16 resp_len; 3934 u8 flags; 3935 #define FUNC_DBR_PACING_QCFG_RESP_FLAGS_DBR_NQ_EVENT_ENABLED 0x1UL 3936 u8 unused_0[7]; 3937 __le32 dbr_stat_db_fifo_reg; 3938 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK 0x3UL 3939 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_SFT 0 3940 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3941 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC 0x1UL 3942 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR0 0x2UL 3943 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1 0x3UL 3944 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_LAST FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1 3945 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_MASK 0xfffffffcUL 3946 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SFT 2 3947 __le32 dbr_stat_db_fifo_reg_watermark_mask; 3948 u8 dbr_stat_db_fifo_reg_watermark_shift; 3949 u8 unused_1[3]; 3950 __le32 dbr_stat_db_fifo_reg_fifo_room_mask; 3951 u8 dbr_stat_db_fifo_reg_fifo_room_shift; 3952 u8 unused_2[3]; 3953 __le32 dbr_throttling_aeq_arm_reg; 3954 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_MASK 0x3UL 3955 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_SFT 0 3956 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3957 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_GRC 0x1UL 3958 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR0 0x2UL 3959 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1 0x3UL 3960 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_LAST FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1 3961 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_MASK 0xfffffffcUL 3962 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SFT 2 3963 u8 dbr_throttling_aeq_arm_reg_val; 3964 u8 unused_3[3]; 3965 __le32 dbr_stat_db_max_fifo_depth; 3966 __le32 primary_nq_id; 3967 __le32 pacing_threshold; 3968 u8 unused_4[7]; 3969 u8 valid; 3970 }; 3971 3972 /* hwrm_func_drv_if_change_input (size:192b/24B) */ 3973 struct hwrm_func_drv_if_change_input { 3974 __le16 req_type; 3975 __le16 cmpl_ring; 3976 __le16 seq_id; 3977 __le16 target_id; 3978 __le64 resp_addr; 3979 __le32 flags; 3980 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 3981 __le32 unused; 3982 }; 3983 3984 /* hwrm_func_drv_if_change_output (size:128b/16B) */ 3985 struct hwrm_func_drv_if_change_output { 3986 __le16 error_code; 3987 __le16 req_type; 3988 __le16 seq_id; 3989 __le16 resp_len; 3990 __le32 flags; 3991 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 3992 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 3993 u8 unused_0[3]; 3994 u8 valid; 3995 }; 3996 3997 /* hwrm_port_phy_cfg_input (size:512b/64B) */ 3998 struct hwrm_port_phy_cfg_input { 3999 __le16 req_type; 4000 __le16 cmpl_ring; 4001 __le16 seq_id; 4002 __le16 target_id; 4003 __le64 resp_addr; 4004 __le32 flags; 4005 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 4006 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 4007 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 4008 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 4009 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 4010 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 4011 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 4012 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 4013 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 4014 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 4015 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 4016 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 4017 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 4018 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 4019 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 4020 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL 4021 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL 4022 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL 4023 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL 4024 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL 4025 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL 4026 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL 4027 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL 4028 __le32 enables; 4029 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 4030 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 4031 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 4032 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 4033 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 4034 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 4035 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 4036 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 4037 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 4038 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 4039 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 4040 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL 4041 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL 4042 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2 0x2000UL 4043 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEEDS2_MASK 0x4000UL 4044 __le16 port_id; 4045 __le16 force_link_speed; 4046 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 4047 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 4048 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 4049 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 4050 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 4051 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 4052 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 4053 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 4054 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 4055 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 4056 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 4057 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 4058 u8 auto_mode; 4059 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 4060 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 4061 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 4062 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 4063 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 4064 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 4065 u8 auto_duplex; 4066 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 4067 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 4068 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 4069 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 4070 u8 auto_pause; 4071 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 4072 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 4073 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 4074 u8 mgmt_flag; 4075 #define PORT_PHY_CFG_REQ_MGMT_FLAG_LINK_RELEASE 0x1UL 4076 #define PORT_PHY_CFG_REQ_MGMT_FLAG_MGMT_VALID 0x80UL 4077 __le16 auto_link_speed; 4078 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 4079 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 4080 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 4081 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 4082 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 4083 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 4084 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 4085 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 4086 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 4087 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 4088 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 4089 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 4090 __le16 auto_link_speed_mask; 4091 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 4092 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 4093 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 4094 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 4095 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 4096 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 4097 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 4098 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 4099 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 4100 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 4101 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 4102 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 4103 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 4104 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 4105 u8 wirespeed; 4106 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 4107 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 4108 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 4109 u8 lpbk; 4110 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 4111 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 4112 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 4113 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 4114 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 4115 u8 force_pause; 4116 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 4117 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 4118 u8 unused_1; 4119 __le32 preemphasis; 4120 __le16 eee_link_speed_mask; 4121 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 4122 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 4123 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 4124 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 4125 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 4126 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 4127 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 4128 __le16 force_pam4_link_speed; 4129 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 4130 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 4131 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 4132 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 4133 __le32 tx_lpi_timer; 4134 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 4135 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 4136 __le16 auto_link_pam4_speed_mask; 4137 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL 4138 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL 4139 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL 4140 __le16 force_link_speeds2; 4141 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_1GB 0xaUL 4142 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_10GB 0x64UL 4143 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_25GB 0xfaUL 4144 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_40GB 0x190UL 4145 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB 0x1f4UL 4146 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB 0x3e8UL 4147 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56 0x1f5UL 4148 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56 0x3e9UL 4149 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56 0x7d1UL 4150 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56 0xfa1UL 4151 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL 4152 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL 4153 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL 4154 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112 4155 __le16 auto_link_speeds2_mask; 4156 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_1GB 0x1UL 4157 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_10GB 0x2UL 4158 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_25GB 0x4UL 4159 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_40GB 0x8UL 4160 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB 0x10UL 4161 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB 0x20UL 4162 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB_PAM4_56 0x40UL 4163 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_56 0x80UL 4164 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_56 0x100UL 4165 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_56 0x200UL 4166 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_112 0x400UL 4167 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_112 0x800UL 4168 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_112 0x1000UL 4169 u8 unused_2[6]; 4170 }; 4171 4172 /* hwrm_port_phy_cfg_output (size:128b/16B) */ 4173 struct hwrm_port_phy_cfg_output { 4174 __le16 error_code; 4175 __le16 req_type; 4176 __le16 seq_id; 4177 __le16 resp_len; 4178 u8 unused_0[7]; 4179 u8 valid; 4180 }; 4181 4182 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 4183 struct hwrm_port_phy_cfg_cmd_err { 4184 u8 code; 4185 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 4186 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 4187 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 4188 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 4189 u8 unused_0[7]; 4190 }; 4191 4192 /* hwrm_port_phy_qcfg_input (size:192b/24B) */ 4193 struct hwrm_port_phy_qcfg_input { 4194 __le16 req_type; 4195 __le16 cmpl_ring; 4196 __le16 seq_id; 4197 __le16 target_id; 4198 __le64 resp_addr; 4199 __le16 port_id; 4200 u8 unused_0[6]; 4201 }; 4202 4203 /* hwrm_port_phy_qcfg_output (size:832b/104B) */ 4204 struct hwrm_port_phy_qcfg_output { 4205 __le16 error_code; 4206 __le16 req_type; 4207 __le16 seq_id; 4208 __le16 resp_len; 4209 u8 link; 4210 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 4211 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 4212 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 4213 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 4214 u8 active_fec_signal_mode; 4215 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL 4216 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0 4217 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL 4218 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL 4219 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112 0x2UL 4220 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112 4221 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL 4222 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4 4223 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4) 4224 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4) 4225 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4) 4226 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4) 4227 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4) 4228 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4) 4229 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4) 4230 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE 4231 __le16 link_speed; 4232 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 4233 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 4234 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 4235 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 4236 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 4237 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 4238 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 4239 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 4240 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 4241 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 4242 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 4243 #define PORT_PHY_QCFG_RESP_LINK_SPEED_400GB 0xfa0UL 4244 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 4245 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 4246 u8 duplex_cfg; 4247 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 4248 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 4249 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 4250 u8 pause; 4251 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 4252 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 4253 __le16 support_speeds; 4254 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 4255 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 4256 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 4257 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 4258 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 4259 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 4260 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 4261 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 4262 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 4263 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 4264 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 4265 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 4266 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 4267 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 4268 __le16 force_link_speed; 4269 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 4270 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 4271 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 4272 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 4273 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 4274 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 4275 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 4276 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 4277 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 4278 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 4279 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 4280 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 4281 u8 auto_mode; 4282 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 4283 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 4284 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 4285 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 4286 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 4287 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 4288 u8 auto_pause; 4289 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 4290 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 4291 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 4292 __le16 auto_link_speed; 4293 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 4294 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 4295 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 4296 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 4297 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 4298 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 4299 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 4300 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 4301 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 4302 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 4303 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 4304 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 4305 __le16 auto_link_speed_mask; 4306 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 4307 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 4308 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 4309 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 4310 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 4311 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 4312 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 4313 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 4314 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 4315 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 4316 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 4317 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 4318 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 4319 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 4320 u8 wirespeed; 4321 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 4322 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 4323 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 4324 u8 lpbk; 4325 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 4326 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 4327 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 4328 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 4329 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 4330 u8 force_pause; 4331 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 4332 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 4333 u8 module_status; 4334 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 4335 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 4336 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 4337 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 4338 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 4339 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL 4340 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 4341 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 4342 __le32 preemphasis; 4343 u8 phy_maj; 4344 u8 phy_min; 4345 u8 phy_bld; 4346 u8 phy_type; 4347 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 4348 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 4349 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 4350 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 4351 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 4352 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 4353 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 4354 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 4355 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 4356 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 4357 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 4358 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 4359 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 4360 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 4361 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 4362 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 4363 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 4364 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 4365 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 4366 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 4367 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 4368 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 4369 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 4370 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 4371 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 4372 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 4373 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 4374 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 4375 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 4376 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 4377 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 4378 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 4379 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR 0x20UL 4380 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR 0x21UL 4381 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR 0x22UL 4382 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER 0x23UL 4383 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2 0x24UL 4384 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2 0x25UL 4385 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2 0x26UL 4386 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2 0x27UL 4387 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR 0x28UL 4388 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR 0x29UL 4389 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR 0x2aUL 4390 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER 0x2bUL 4391 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2 0x2cUL 4392 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2 0x2dUL 4393 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2 0x2eUL 4394 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2 0x2fUL 4395 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8 0x30UL 4396 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8 0x31UL 4397 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8 0x32UL 4398 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8 0x33UL 4399 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4 0x34UL 4400 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4 0x35UL 4401 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4 0x36UL 4402 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4 0x37UL 4403 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4 4404 u8 media_type; 4405 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 4406 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 4407 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 4408 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 4409 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 4410 u8 xcvr_pkg_type; 4411 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 4412 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 4413 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 4414 u8 eee_config_phy_addr; 4415 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 4416 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 4417 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 4418 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 4419 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 4420 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 4421 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 4422 u8 parallel_detect; 4423 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 4424 __le16 link_partner_adv_speeds; 4425 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 4426 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 4427 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 4428 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 4429 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 4430 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 4431 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 4432 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 4433 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 4434 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 4435 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 4436 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 4437 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 4438 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 4439 u8 link_partner_adv_auto_mode; 4440 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 4441 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 4442 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 4443 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 4444 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 4445 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 4446 u8 link_partner_adv_pause; 4447 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 4448 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 4449 __le16 adv_eee_link_speed_mask; 4450 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 4451 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 4452 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 4453 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 4454 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 4455 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 4456 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 4457 __le16 link_partner_adv_eee_link_speed_mask; 4458 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 4459 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 4460 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 4461 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 4462 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 4463 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 4464 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 4465 __le32 xcvr_identifier_type_tx_lpi_timer; 4466 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 4467 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 4468 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 4469 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 4470 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 4471 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 4472 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 4473 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 4474 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 4475 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 4476 __le16 fec_cfg; 4477 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 4478 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 4479 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 4480 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 4481 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 4482 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 4483 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 4484 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL 4485 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL 4486 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL 4487 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL 4488 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL 4489 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL 4490 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL 4491 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL 4492 u8 duplex_state; 4493 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 4494 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 4495 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 4496 u8 option_flags; 4497 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 4498 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN 0x2UL 4499 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SPEEDS2_SUPPORTED 0x4UL 4500 char phy_vendor_name[16]; 4501 char phy_vendor_partnumber[16]; 4502 __le16 support_pam4_speeds; 4503 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL 4504 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL 4505 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL 4506 __le16 force_pam4_link_speed; 4507 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 4508 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 4509 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 4510 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 4511 __le16 auto_pam4_link_speed_mask; 4512 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL 4513 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL 4514 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL 4515 u8 link_partner_pam4_adv_speeds; 4516 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL 4517 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL 4518 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL 4519 u8 link_down_reason; 4520 #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF 0x1UL 4521 __le16 support_speeds2; 4522 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB 0x1UL 4523 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB 0x2UL 4524 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_25GB 0x4UL 4525 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_40GB 0x8UL 4526 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB 0x10UL 4527 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB 0x20UL 4528 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB_PAM4_56 0x40UL 4529 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_56 0x80UL 4530 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_56 0x100UL 4531 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_56 0x200UL 4532 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_112 0x400UL 4533 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_112 0x800UL 4534 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_112 0x1000UL 4535 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_800GB_PAM4_112 0x2000UL 4536 __le16 force_link_speeds2; 4537 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_1GB 0xaUL 4538 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_10GB 0x64UL 4539 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_25GB 0xfaUL 4540 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_40GB 0x190UL 4541 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB 0x1f4UL 4542 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB 0x3e8UL 4543 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB_PAM4_56 0x1f5UL 4544 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_56 0x3e9UL 4545 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_56 0x7d1UL 4546 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_56 0xfa1UL 4547 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL 4548 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL 4549 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL 4550 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112 0x1f42UL 4551 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112 4552 __le16 auto_link_speeds2; 4553 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_1GB 0x1UL 4554 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_10GB 0x2UL 4555 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_25GB 0x4UL 4556 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_40GB 0x8UL 4557 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB 0x10UL 4558 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB 0x20UL 4559 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB_PAM4_56 0x40UL 4560 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_56 0x80UL 4561 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_56 0x100UL 4562 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_56 0x200UL 4563 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_112 0x400UL 4564 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_112 0x800UL 4565 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_112 0x1000UL 4566 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_800GB_PAM4_112 0x2000UL 4567 u8 active_lanes; 4568 u8 valid; 4569 }; 4570 4571 /* hwrm_port_mac_cfg_input (size:448b/56B) */ 4572 struct hwrm_port_mac_cfg_input { 4573 __le16 req_type; 4574 __le16 cmpl_ring; 4575 __le16 seq_id; 4576 __le16 target_id; 4577 __le64 resp_addr; 4578 __le32 flags; 4579 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 4580 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 4581 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 4582 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 4583 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 4584 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 4585 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 4586 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 4587 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 4588 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 4589 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 4590 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 4591 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 4592 #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL 4593 #define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE 0x4000UL 4594 #define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE 0x8000UL 4595 __le32 enables; 4596 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 4597 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 4598 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 4599 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 4600 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 4601 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 4602 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 4603 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 4604 #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL 4605 #define PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE 0x400UL 4606 #define PORT_MAC_CFG_REQ_ENABLES_PTP_LOAD_CONTROL 0x800UL 4607 __le16 port_id; 4608 u8 ipg; 4609 u8 lpbk; 4610 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 4611 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 4612 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 4613 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 4614 u8 vlan_pri2cos_map_pri; 4615 u8 reserved1; 4616 u8 tunnel_pri2cos_map_pri; 4617 u8 dscp2pri_map_pri; 4618 __le16 rx_ts_capture_ptp_msg_type; 4619 __le16 tx_ts_capture_ptp_msg_type; 4620 u8 cos_field_cfg; 4621 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 4622 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 4623 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 4624 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 4625 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 4626 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 4627 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 4628 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 4629 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 4630 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 4631 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 4632 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 4633 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 4634 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 4635 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 4636 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 4637 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 4638 u8 unused_0[3]; 4639 __le32 ptp_freq_adj_ppb; 4640 u8 unused_1[3]; 4641 u8 ptp_load_control; 4642 #define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_NONE 0x0UL 4643 #define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_IMMEDIATE 0x1UL 4644 #define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_PPS_EVENT 0x2UL 4645 #define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_LAST PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_PPS_EVENT 4646 __le64 ptp_adj_phase; 4647 }; 4648 4649 /* hwrm_port_mac_cfg_output (size:128b/16B) */ 4650 struct hwrm_port_mac_cfg_output { 4651 __le16 error_code; 4652 __le16 req_type; 4653 __le16 seq_id; 4654 __le16 resp_len; 4655 __le16 mru; 4656 __le16 mtu; 4657 u8 ipg; 4658 u8 lpbk; 4659 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 4660 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 4661 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 4662 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 4663 u8 unused_0; 4664 u8 valid; 4665 }; 4666 4667 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 4668 struct hwrm_port_mac_ptp_qcfg_input { 4669 __le16 req_type; 4670 __le16 cmpl_ring; 4671 __le16 seq_id; 4672 __le16 target_id; 4673 __le64 resp_addr; 4674 __le16 port_id; 4675 u8 unused_0[6]; 4676 }; 4677 4678 /* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */ 4679 struct hwrm_port_mac_ptp_qcfg_output { 4680 __le16 error_code; 4681 __le16 req_type; 4682 __le16 seq_id; 4683 __le16 resp_len; 4684 u8 flags; 4685 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 4686 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL 4687 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL 4688 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK 0x10UL 4689 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_RTC_CONFIGURED 0x20UL 4690 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_64B_PHC_TIME 0x40UL 4691 u8 unused_0[3]; 4692 __le32 rx_ts_reg_off_lower; 4693 __le32 rx_ts_reg_off_upper; 4694 __le32 rx_ts_reg_off_seq_id; 4695 __le32 rx_ts_reg_off_src_id_0; 4696 __le32 rx_ts_reg_off_src_id_1; 4697 __le32 rx_ts_reg_off_src_id_2; 4698 __le32 rx_ts_reg_off_domain_id; 4699 __le32 rx_ts_reg_off_fifo; 4700 __le32 rx_ts_reg_off_fifo_adv; 4701 __le32 rx_ts_reg_off_granularity; 4702 __le32 tx_ts_reg_off_lower; 4703 __le32 tx_ts_reg_off_upper; 4704 __le32 tx_ts_reg_off_seq_id; 4705 __le32 tx_ts_reg_off_fifo; 4706 __le32 tx_ts_reg_off_granularity; 4707 __le32 ts_ref_clock_reg_lower; 4708 __le32 ts_ref_clock_reg_upper; 4709 u8 unused_1[7]; 4710 u8 valid; 4711 }; 4712 4713 /* tx_port_stats (size:3264b/408B) */ 4714 struct tx_port_stats { 4715 __le64 tx_64b_frames; 4716 __le64 tx_65b_127b_frames; 4717 __le64 tx_128b_255b_frames; 4718 __le64 tx_256b_511b_frames; 4719 __le64 tx_512b_1023b_frames; 4720 __le64 tx_1024b_1518b_frames; 4721 __le64 tx_good_vlan_frames; 4722 __le64 tx_1519b_2047b_frames; 4723 __le64 tx_2048b_4095b_frames; 4724 __le64 tx_4096b_9216b_frames; 4725 __le64 tx_9217b_16383b_frames; 4726 __le64 tx_good_frames; 4727 __le64 tx_total_frames; 4728 __le64 tx_ucast_frames; 4729 __le64 tx_mcast_frames; 4730 __le64 tx_bcast_frames; 4731 __le64 tx_pause_frames; 4732 __le64 tx_pfc_frames; 4733 __le64 tx_jabber_frames; 4734 __le64 tx_fcs_err_frames; 4735 __le64 tx_control_frames; 4736 __le64 tx_oversz_frames; 4737 __le64 tx_single_dfrl_frames; 4738 __le64 tx_multi_dfrl_frames; 4739 __le64 tx_single_coll_frames; 4740 __le64 tx_multi_coll_frames; 4741 __le64 tx_late_coll_frames; 4742 __le64 tx_excessive_coll_frames; 4743 __le64 tx_frag_frames; 4744 __le64 tx_err; 4745 __le64 tx_tagged_frames; 4746 __le64 tx_dbl_tagged_frames; 4747 __le64 tx_runt_frames; 4748 __le64 tx_fifo_underruns; 4749 __le64 tx_pfc_ena_frames_pri0; 4750 __le64 tx_pfc_ena_frames_pri1; 4751 __le64 tx_pfc_ena_frames_pri2; 4752 __le64 tx_pfc_ena_frames_pri3; 4753 __le64 tx_pfc_ena_frames_pri4; 4754 __le64 tx_pfc_ena_frames_pri5; 4755 __le64 tx_pfc_ena_frames_pri6; 4756 __le64 tx_pfc_ena_frames_pri7; 4757 __le64 tx_eee_lpi_events; 4758 __le64 tx_eee_lpi_duration; 4759 __le64 tx_llfc_logical_msgs; 4760 __le64 tx_hcfc_msgs; 4761 __le64 tx_total_collisions; 4762 __le64 tx_bytes; 4763 __le64 tx_xthol_frames; 4764 __le64 tx_stat_discard; 4765 __le64 tx_stat_error; 4766 }; 4767 4768 /* rx_port_stats (size:4224b/528B) */ 4769 struct rx_port_stats { 4770 __le64 rx_64b_frames; 4771 __le64 rx_65b_127b_frames; 4772 __le64 rx_128b_255b_frames; 4773 __le64 rx_256b_511b_frames; 4774 __le64 rx_512b_1023b_frames; 4775 __le64 rx_1024b_1518b_frames; 4776 __le64 rx_good_vlan_frames; 4777 __le64 rx_1519b_2047b_frames; 4778 __le64 rx_2048b_4095b_frames; 4779 __le64 rx_4096b_9216b_frames; 4780 __le64 rx_9217b_16383b_frames; 4781 __le64 rx_total_frames; 4782 __le64 rx_ucast_frames; 4783 __le64 rx_mcast_frames; 4784 __le64 rx_bcast_frames; 4785 __le64 rx_fcs_err_frames; 4786 __le64 rx_ctrl_frames; 4787 __le64 rx_pause_frames; 4788 __le64 rx_pfc_frames; 4789 __le64 rx_unsupported_opcode_frames; 4790 __le64 rx_unsupported_da_pausepfc_frames; 4791 __le64 rx_wrong_sa_frames; 4792 __le64 rx_align_err_frames; 4793 __le64 rx_oor_len_frames; 4794 __le64 rx_code_err_frames; 4795 __le64 rx_false_carrier_frames; 4796 __le64 rx_ovrsz_frames; 4797 __le64 rx_jbr_frames; 4798 __le64 rx_mtu_err_frames; 4799 __le64 rx_match_crc_frames; 4800 __le64 rx_promiscuous_frames; 4801 __le64 rx_tagged_frames; 4802 __le64 rx_double_tagged_frames; 4803 __le64 rx_trunc_frames; 4804 __le64 rx_good_frames; 4805 __le64 rx_pfc_xon2xoff_frames_pri0; 4806 __le64 rx_pfc_xon2xoff_frames_pri1; 4807 __le64 rx_pfc_xon2xoff_frames_pri2; 4808 __le64 rx_pfc_xon2xoff_frames_pri3; 4809 __le64 rx_pfc_xon2xoff_frames_pri4; 4810 __le64 rx_pfc_xon2xoff_frames_pri5; 4811 __le64 rx_pfc_xon2xoff_frames_pri6; 4812 __le64 rx_pfc_xon2xoff_frames_pri7; 4813 __le64 rx_pfc_ena_frames_pri0; 4814 __le64 rx_pfc_ena_frames_pri1; 4815 __le64 rx_pfc_ena_frames_pri2; 4816 __le64 rx_pfc_ena_frames_pri3; 4817 __le64 rx_pfc_ena_frames_pri4; 4818 __le64 rx_pfc_ena_frames_pri5; 4819 __le64 rx_pfc_ena_frames_pri6; 4820 __le64 rx_pfc_ena_frames_pri7; 4821 __le64 rx_sch_crc_err_frames; 4822 __le64 rx_undrsz_frames; 4823 __le64 rx_frag_frames; 4824 __le64 rx_eee_lpi_events; 4825 __le64 rx_eee_lpi_duration; 4826 __le64 rx_llfc_physical_msgs; 4827 __le64 rx_llfc_logical_msgs; 4828 __le64 rx_llfc_msgs_with_crc_err; 4829 __le64 rx_hcfc_msgs; 4830 __le64 rx_hcfc_msgs_with_crc_err; 4831 __le64 rx_bytes; 4832 __le64 rx_runt_bytes; 4833 __le64 rx_runt_frames; 4834 __le64 rx_stat_discard; 4835 __le64 rx_stat_err; 4836 }; 4837 4838 /* hwrm_port_qstats_input (size:320b/40B) */ 4839 struct hwrm_port_qstats_input { 4840 __le16 req_type; 4841 __le16 cmpl_ring; 4842 __le16 seq_id; 4843 __le16 target_id; 4844 __le64 resp_addr; 4845 __le16 port_id; 4846 u8 flags; 4847 #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 4848 u8 unused_0[5]; 4849 __le64 tx_stat_host_addr; 4850 __le64 rx_stat_host_addr; 4851 }; 4852 4853 /* hwrm_port_qstats_output (size:128b/16B) */ 4854 struct hwrm_port_qstats_output { 4855 __le16 error_code; 4856 __le16 req_type; 4857 __le16 seq_id; 4858 __le16 resp_len; 4859 __le16 tx_stat_size; 4860 __le16 rx_stat_size; 4861 u8 unused_0[3]; 4862 u8 valid; 4863 }; 4864 4865 /* tx_port_stats_ext (size:2048b/256B) */ 4866 struct tx_port_stats_ext { 4867 __le64 tx_bytes_cos0; 4868 __le64 tx_bytes_cos1; 4869 __le64 tx_bytes_cos2; 4870 __le64 tx_bytes_cos3; 4871 __le64 tx_bytes_cos4; 4872 __le64 tx_bytes_cos5; 4873 __le64 tx_bytes_cos6; 4874 __le64 tx_bytes_cos7; 4875 __le64 tx_packets_cos0; 4876 __le64 tx_packets_cos1; 4877 __le64 tx_packets_cos2; 4878 __le64 tx_packets_cos3; 4879 __le64 tx_packets_cos4; 4880 __le64 tx_packets_cos5; 4881 __le64 tx_packets_cos6; 4882 __le64 tx_packets_cos7; 4883 __le64 pfc_pri0_tx_duration_us; 4884 __le64 pfc_pri0_tx_transitions; 4885 __le64 pfc_pri1_tx_duration_us; 4886 __le64 pfc_pri1_tx_transitions; 4887 __le64 pfc_pri2_tx_duration_us; 4888 __le64 pfc_pri2_tx_transitions; 4889 __le64 pfc_pri3_tx_duration_us; 4890 __le64 pfc_pri3_tx_transitions; 4891 __le64 pfc_pri4_tx_duration_us; 4892 __le64 pfc_pri4_tx_transitions; 4893 __le64 pfc_pri5_tx_duration_us; 4894 __le64 pfc_pri5_tx_transitions; 4895 __le64 pfc_pri6_tx_duration_us; 4896 __le64 pfc_pri6_tx_transitions; 4897 __le64 pfc_pri7_tx_duration_us; 4898 __le64 pfc_pri7_tx_transitions; 4899 }; 4900 4901 /* rx_port_stats_ext (size:3904b/488B) */ 4902 struct rx_port_stats_ext { 4903 __le64 link_down_events; 4904 __le64 continuous_pause_events; 4905 __le64 resume_pause_events; 4906 __le64 continuous_roce_pause_events; 4907 __le64 resume_roce_pause_events; 4908 __le64 rx_bytes_cos0; 4909 __le64 rx_bytes_cos1; 4910 __le64 rx_bytes_cos2; 4911 __le64 rx_bytes_cos3; 4912 __le64 rx_bytes_cos4; 4913 __le64 rx_bytes_cos5; 4914 __le64 rx_bytes_cos6; 4915 __le64 rx_bytes_cos7; 4916 __le64 rx_packets_cos0; 4917 __le64 rx_packets_cos1; 4918 __le64 rx_packets_cos2; 4919 __le64 rx_packets_cos3; 4920 __le64 rx_packets_cos4; 4921 __le64 rx_packets_cos5; 4922 __le64 rx_packets_cos6; 4923 __le64 rx_packets_cos7; 4924 __le64 pfc_pri0_rx_duration_us; 4925 __le64 pfc_pri0_rx_transitions; 4926 __le64 pfc_pri1_rx_duration_us; 4927 __le64 pfc_pri1_rx_transitions; 4928 __le64 pfc_pri2_rx_duration_us; 4929 __le64 pfc_pri2_rx_transitions; 4930 __le64 pfc_pri3_rx_duration_us; 4931 __le64 pfc_pri3_rx_transitions; 4932 __le64 pfc_pri4_rx_duration_us; 4933 __le64 pfc_pri4_rx_transitions; 4934 __le64 pfc_pri5_rx_duration_us; 4935 __le64 pfc_pri5_rx_transitions; 4936 __le64 pfc_pri6_rx_duration_us; 4937 __le64 pfc_pri6_rx_transitions; 4938 __le64 pfc_pri7_rx_duration_us; 4939 __le64 pfc_pri7_rx_transitions; 4940 __le64 rx_bits; 4941 __le64 rx_buffer_passed_threshold; 4942 __le64 rx_pcs_symbol_err; 4943 __le64 rx_corrected_bits; 4944 __le64 rx_discard_bytes_cos0; 4945 __le64 rx_discard_bytes_cos1; 4946 __le64 rx_discard_bytes_cos2; 4947 __le64 rx_discard_bytes_cos3; 4948 __le64 rx_discard_bytes_cos4; 4949 __le64 rx_discard_bytes_cos5; 4950 __le64 rx_discard_bytes_cos6; 4951 __le64 rx_discard_bytes_cos7; 4952 __le64 rx_discard_packets_cos0; 4953 __le64 rx_discard_packets_cos1; 4954 __le64 rx_discard_packets_cos2; 4955 __le64 rx_discard_packets_cos3; 4956 __le64 rx_discard_packets_cos4; 4957 __le64 rx_discard_packets_cos5; 4958 __le64 rx_discard_packets_cos6; 4959 __le64 rx_discard_packets_cos7; 4960 __le64 rx_fec_corrected_blocks; 4961 __le64 rx_fec_uncorrectable_blocks; 4962 __le64 rx_filter_miss; 4963 __le64 rx_fec_symbol_err; 4964 }; 4965 4966 /* hwrm_port_qstats_ext_input (size:320b/40B) */ 4967 struct hwrm_port_qstats_ext_input { 4968 __le16 req_type; 4969 __le16 cmpl_ring; 4970 __le16 seq_id; 4971 __le16 target_id; 4972 __le64 resp_addr; 4973 __le16 port_id; 4974 __le16 tx_stat_size; 4975 __le16 rx_stat_size; 4976 u8 flags; 4977 #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL 4978 u8 unused_0; 4979 __le64 tx_stat_host_addr; 4980 __le64 rx_stat_host_addr; 4981 }; 4982 4983 /* hwrm_port_qstats_ext_output (size:128b/16B) */ 4984 struct hwrm_port_qstats_ext_output { 4985 __le16 error_code; 4986 __le16 req_type; 4987 __le16 seq_id; 4988 __le16 resp_len; 4989 __le16 tx_stat_size; 4990 __le16 rx_stat_size; 4991 __le16 total_active_cos_queues; 4992 u8 flags; 4993 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 4994 u8 valid; 4995 }; 4996 4997 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */ 4998 struct hwrm_port_lpbk_qstats_input { 4999 __le16 req_type; 5000 __le16 cmpl_ring; 5001 __le16 seq_id; 5002 __le16 target_id; 5003 __le64 resp_addr; 5004 }; 5005 5006 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */ 5007 struct hwrm_port_lpbk_qstats_output { 5008 __le16 error_code; 5009 __le16 req_type; 5010 __le16 seq_id; 5011 __le16 resp_len; 5012 __le64 lpbk_ucast_frames; 5013 __le64 lpbk_mcast_frames; 5014 __le64 lpbk_bcast_frames; 5015 __le64 lpbk_ucast_bytes; 5016 __le64 lpbk_mcast_bytes; 5017 __le64 lpbk_bcast_bytes; 5018 __le64 tx_stat_discard; 5019 __le64 tx_stat_error; 5020 __le64 rx_stat_discard; 5021 __le64 rx_stat_error; 5022 u8 unused_0[7]; 5023 u8 valid; 5024 }; 5025 5026 /* hwrm_port_ecn_qstats_input (size:256b/32B) */ 5027 struct hwrm_port_ecn_qstats_input { 5028 __le16 req_type; 5029 __le16 cmpl_ring; 5030 __le16 seq_id; 5031 __le16 target_id; 5032 __le64 resp_addr; 5033 __le16 port_id; 5034 __le16 ecn_stat_buf_size; 5035 u8 flags; 5036 #define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 5037 u8 unused_0[3]; 5038 __le64 ecn_stat_host_addr; 5039 }; 5040 5041 /* hwrm_port_ecn_qstats_output (size:128b/16B) */ 5042 struct hwrm_port_ecn_qstats_output { 5043 __le16 error_code; 5044 __le16 req_type; 5045 __le16 seq_id; 5046 __le16 resp_len; 5047 __le16 ecn_stat_buf_size; 5048 u8 mark_en; 5049 u8 unused_0[4]; 5050 u8 valid; 5051 }; 5052 5053 /* port_stats_ecn (size:512b/64B) */ 5054 struct port_stats_ecn { 5055 __le64 mark_cnt_cos0; 5056 __le64 mark_cnt_cos1; 5057 __le64 mark_cnt_cos2; 5058 __le64 mark_cnt_cos3; 5059 __le64 mark_cnt_cos4; 5060 __le64 mark_cnt_cos5; 5061 __le64 mark_cnt_cos6; 5062 __le64 mark_cnt_cos7; 5063 }; 5064 5065 /* hwrm_port_clr_stats_input (size:192b/24B) */ 5066 struct hwrm_port_clr_stats_input { 5067 __le16 req_type; 5068 __le16 cmpl_ring; 5069 __le16 seq_id; 5070 __le16 target_id; 5071 __le64 resp_addr; 5072 __le16 port_id; 5073 u8 flags; 5074 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 5075 u8 unused_0[5]; 5076 }; 5077 5078 /* hwrm_port_clr_stats_output (size:128b/16B) */ 5079 struct hwrm_port_clr_stats_output { 5080 __le16 error_code; 5081 __le16 req_type; 5082 __le16 seq_id; 5083 __le16 resp_len; 5084 u8 unused_0[7]; 5085 u8 valid; 5086 }; 5087 5088 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ 5089 struct hwrm_port_lpbk_clr_stats_input { 5090 __le16 req_type; 5091 __le16 cmpl_ring; 5092 __le16 seq_id; 5093 __le16 target_id; 5094 __le64 resp_addr; 5095 }; 5096 5097 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 5098 struct hwrm_port_lpbk_clr_stats_output { 5099 __le16 error_code; 5100 __le16 req_type; 5101 __le16 seq_id; 5102 __le16 resp_len; 5103 u8 unused_0[7]; 5104 u8 valid; 5105 }; 5106 5107 /* hwrm_port_ts_query_input (size:320b/40B) */ 5108 struct hwrm_port_ts_query_input { 5109 __le16 req_type; 5110 __le16 cmpl_ring; 5111 __le16 seq_id; 5112 __le16 target_id; 5113 __le64 resp_addr; 5114 __le32 flags; 5115 #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL 5116 #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL 5117 #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL 5118 #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX 5119 #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL 5120 __le16 port_id; 5121 u8 unused_0[2]; 5122 __le16 enables; 5123 #define PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT 0x1UL 5124 #define PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID 0x2UL 5125 #define PORT_TS_QUERY_REQ_ENABLES_PTP_HDR_OFFSET 0x4UL 5126 __le16 ts_req_timeout; 5127 __le32 ptp_seq_id; 5128 __le16 ptp_hdr_offset; 5129 u8 unused_1[6]; 5130 }; 5131 5132 /* hwrm_port_ts_query_output (size:192b/24B) */ 5133 struct hwrm_port_ts_query_output { 5134 __le16 error_code; 5135 __le16 req_type; 5136 __le16 seq_id; 5137 __le16 resp_len; 5138 __le64 ptp_msg_ts; 5139 __le16 ptp_msg_seqid; 5140 u8 unused_0[5]; 5141 u8 valid; 5142 }; 5143 5144 /* hwrm_port_phy_qcaps_input (size:192b/24B) */ 5145 struct hwrm_port_phy_qcaps_input { 5146 __le16 req_type; 5147 __le16 cmpl_ring; 5148 __le16 seq_id; 5149 __le16 target_id; 5150 __le64 resp_addr; 5151 __le16 port_id; 5152 u8 unused_0[6]; 5153 }; 5154 5155 /* hwrm_port_phy_qcaps_output (size:320b/40B) */ 5156 struct hwrm_port_phy_qcaps_output { 5157 __le16 error_code; 5158 __le16 req_type; 5159 __le16 seq_id; 5160 __le16 resp_len; 5161 u8 flags; 5162 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 5163 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 5164 #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL 5165 #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL 5166 #define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL 5167 #define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x20UL 5168 #define PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN 0x40UL 5169 #define PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS 0x80UL 5170 u8 port_cnt; 5171 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 5172 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 5173 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 5174 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 5175 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 5176 #define PORT_PHY_QCAPS_RESP_PORT_CNT_12 0xcUL 5177 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_12 5178 __le16 supported_speeds_force_mode; 5179 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 5180 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 5181 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 5182 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 5183 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 5184 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 5185 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 5186 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 5187 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 5188 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 5189 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 5190 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 5191 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 5192 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 5193 __le16 supported_speeds_auto_mode; 5194 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 5195 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 5196 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 5197 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 5198 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 5199 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 5200 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 5201 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 5202 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 5203 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 5204 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 5205 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 5206 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 5207 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 5208 __le16 supported_speeds_eee_mode; 5209 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 5210 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 5211 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 5212 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 5213 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 5214 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 5215 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 5216 __le32 tx_lpi_timer_low; 5217 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 5218 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 5219 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 5220 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 5221 __le32 valid_tx_lpi_timer_high; 5222 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 5223 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 5224 #define PORT_PHY_QCAPS_RESP_RSVD_MASK 0xff000000UL 5225 #define PORT_PHY_QCAPS_RESP_RSVD_SFT 24 5226 __le16 supported_pam4_speeds_auto_mode; 5227 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL 5228 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL 5229 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL 5230 __le16 supported_pam4_speeds_force_mode; 5231 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL 5232 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL 5233 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL 5234 __le16 flags2; 5235 #define PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED 0x1UL 5236 #define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED 0x2UL 5237 #define PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED 0x4UL 5238 #define PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED 0x8UL 5239 u8 internal_port_cnt; 5240 u8 unused_0; 5241 __le16 supported_speeds2_force_mode; 5242 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_1GB 0x1UL 5243 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_10GB 0x2UL 5244 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_25GB 0x4UL 5245 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_40GB 0x8UL 5246 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB 0x10UL 5247 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB 0x20UL 5248 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB_PAM4_56 0x40UL 5249 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_56 0x80UL 5250 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_56 0x100UL 5251 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_56 0x200UL 5252 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_112 0x400UL 5253 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_112 0x800UL 5254 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_112 0x1000UL 5255 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_800GB_PAM4_112 0x2000UL 5256 __le16 supported_speeds2_auto_mode; 5257 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_1GB 0x1UL 5258 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_10GB 0x2UL 5259 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_25GB 0x4UL 5260 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_40GB 0x8UL 5261 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB 0x10UL 5262 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB 0x20UL 5263 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB_PAM4_56 0x40UL 5264 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_56 0x80UL 5265 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_56 0x100UL 5266 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_56 0x200UL 5267 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_112 0x400UL 5268 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_112 0x800UL 5269 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_112 0x1000UL 5270 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_800GB_PAM4_112 0x2000UL 5271 u8 unused_1[3]; 5272 u8 valid; 5273 }; 5274 5275 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 5276 struct hwrm_port_phy_i2c_read_input { 5277 __le16 req_type; 5278 __le16 cmpl_ring; 5279 __le16 seq_id; 5280 __le16 target_id; 5281 __le64 resp_addr; 5282 __le32 flags; 5283 __le32 enables; 5284 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 5285 #define PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER 0x2UL 5286 __le16 port_id; 5287 u8 i2c_slave_addr; 5288 u8 bank_number; 5289 __le16 page_number; 5290 __le16 page_offset; 5291 u8 data_length; 5292 u8 unused_1[7]; 5293 }; 5294 5295 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 5296 struct hwrm_port_phy_i2c_read_output { 5297 __le16 error_code; 5298 __le16 req_type; 5299 __le16 seq_id; 5300 __le16 resp_len; 5301 __le32 data[16]; 5302 u8 unused_0[7]; 5303 u8 valid; 5304 }; 5305 5306 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */ 5307 struct hwrm_port_phy_mdio_write_input { 5308 __le16 req_type; 5309 __le16 cmpl_ring; 5310 __le16 seq_id; 5311 __le16 target_id; 5312 __le64 resp_addr; 5313 __le32 unused_0[2]; 5314 __le16 port_id; 5315 u8 phy_addr; 5316 u8 dev_addr; 5317 __le16 reg_addr; 5318 __le16 reg_data; 5319 u8 cl45_mdio; 5320 u8 unused_1[7]; 5321 }; 5322 5323 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */ 5324 struct hwrm_port_phy_mdio_write_output { 5325 __le16 error_code; 5326 __le16 req_type; 5327 __le16 seq_id; 5328 __le16 resp_len; 5329 u8 unused_0[7]; 5330 u8 valid; 5331 }; 5332 5333 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */ 5334 struct hwrm_port_phy_mdio_read_input { 5335 __le16 req_type; 5336 __le16 cmpl_ring; 5337 __le16 seq_id; 5338 __le16 target_id; 5339 __le64 resp_addr; 5340 __le32 unused_0[2]; 5341 __le16 port_id; 5342 u8 phy_addr; 5343 u8 dev_addr; 5344 __le16 reg_addr; 5345 u8 cl45_mdio; 5346 u8 unused_1; 5347 }; 5348 5349 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */ 5350 struct hwrm_port_phy_mdio_read_output { 5351 __le16 error_code; 5352 __le16 req_type; 5353 __le16 seq_id; 5354 __le16 resp_len; 5355 __le16 reg_data; 5356 u8 unused_0[5]; 5357 u8 valid; 5358 }; 5359 5360 /* hwrm_port_led_cfg_input (size:512b/64B) */ 5361 struct hwrm_port_led_cfg_input { 5362 __le16 req_type; 5363 __le16 cmpl_ring; 5364 __le16 seq_id; 5365 __le16 target_id; 5366 __le64 resp_addr; 5367 __le32 enables; 5368 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 5369 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 5370 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 5371 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 5372 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 5373 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 5374 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 5375 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 5376 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 5377 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 5378 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 5379 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 5380 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 5381 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 5382 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 5383 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 5384 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 5385 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 5386 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 5387 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 5388 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 5389 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 5390 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 5391 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 5392 __le16 port_id; 5393 u8 num_leds; 5394 u8 rsvd; 5395 u8 led0_id; 5396 u8 led0_state; 5397 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 5398 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 5399 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 5400 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 5401 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 5402 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 5403 u8 led0_color; 5404 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 5405 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 5406 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 5407 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 5408 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 5409 u8 unused_0; 5410 __le16 led0_blink_on; 5411 __le16 led0_blink_off; 5412 u8 led0_group_id; 5413 u8 rsvd0; 5414 u8 led1_id; 5415 u8 led1_state; 5416 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 5417 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 5418 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 5419 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 5420 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 5421 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 5422 u8 led1_color; 5423 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 5424 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 5425 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 5426 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 5427 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 5428 u8 unused_1; 5429 __le16 led1_blink_on; 5430 __le16 led1_blink_off; 5431 u8 led1_group_id; 5432 u8 rsvd1; 5433 u8 led2_id; 5434 u8 led2_state; 5435 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 5436 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 5437 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 5438 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 5439 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 5440 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 5441 u8 led2_color; 5442 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 5443 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 5444 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 5445 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 5446 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 5447 u8 unused_2; 5448 __le16 led2_blink_on; 5449 __le16 led2_blink_off; 5450 u8 led2_group_id; 5451 u8 rsvd2; 5452 u8 led3_id; 5453 u8 led3_state; 5454 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 5455 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 5456 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 5457 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 5458 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 5459 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 5460 u8 led3_color; 5461 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 5462 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 5463 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 5464 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 5465 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 5466 u8 unused_3; 5467 __le16 led3_blink_on; 5468 __le16 led3_blink_off; 5469 u8 led3_group_id; 5470 u8 rsvd3; 5471 }; 5472 5473 /* hwrm_port_led_cfg_output (size:128b/16B) */ 5474 struct hwrm_port_led_cfg_output { 5475 __le16 error_code; 5476 __le16 req_type; 5477 __le16 seq_id; 5478 __le16 resp_len; 5479 u8 unused_0[7]; 5480 u8 valid; 5481 }; 5482 5483 /* hwrm_port_led_qcfg_input (size:192b/24B) */ 5484 struct hwrm_port_led_qcfg_input { 5485 __le16 req_type; 5486 __le16 cmpl_ring; 5487 __le16 seq_id; 5488 __le16 target_id; 5489 __le64 resp_addr; 5490 __le16 port_id; 5491 u8 unused_0[6]; 5492 }; 5493 5494 /* hwrm_port_led_qcfg_output (size:448b/56B) */ 5495 struct hwrm_port_led_qcfg_output { 5496 __le16 error_code; 5497 __le16 req_type; 5498 __le16 seq_id; 5499 __le16 resp_len; 5500 u8 num_leds; 5501 u8 led0_id; 5502 u8 led0_type; 5503 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 5504 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 5505 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 5506 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 5507 u8 led0_state; 5508 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 5509 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 5510 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 5511 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 5512 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 5513 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 5514 u8 led0_color; 5515 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 5516 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 5517 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 5518 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 5519 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 5520 u8 unused_0; 5521 __le16 led0_blink_on; 5522 __le16 led0_blink_off; 5523 u8 led0_group_id; 5524 u8 led1_id; 5525 u8 led1_type; 5526 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 5527 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 5528 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 5529 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 5530 u8 led1_state; 5531 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 5532 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 5533 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 5534 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 5535 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 5536 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 5537 u8 led1_color; 5538 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 5539 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 5540 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 5541 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 5542 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 5543 u8 unused_1; 5544 __le16 led1_blink_on; 5545 __le16 led1_blink_off; 5546 u8 led1_group_id; 5547 u8 led2_id; 5548 u8 led2_type; 5549 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 5550 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 5551 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 5552 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 5553 u8 led2_state; 5554 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 5555 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 5556 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 5557 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 5558 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 5559 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 5560 u8 led2_color; 5561 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 5562 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 5563 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 5564 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 5565 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 5566 u8 unused_2; 5567 __le16 led2_blink_on; 5568 __le16 led2_blink_off; 5569 u8 led2_group_id; 5570 u8 led3_id; 5571 u8 led3_type; 5572 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 5573 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 5574 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 5575 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 5576 u8 led3_state; 5577 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 5578 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 5579 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 5580 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 5581 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 5582 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 5583 u8 led3_color; 5584 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 5585 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 5586 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 5587 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 5588 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 5589 u8 unused_3; 5590 __le16 led3_blink_on; 5591 __le16 led3_blink_off; 5592 u8 led3_group_id; 5593 u8 unused_4[6]; 5594 u8 valid; 5595 }; 5596 5597 /* hwrm_port_led_qcaps_input (size:192b/24B) */ 5598 struct hwrm_port_led_qcaps_input { 5599 __le16 req_type; 5600 __le16 cmpl_ring; 5601 __le16 seq_id; 5602 __le16 target_id; 5603 __le64 resp_addr; 5604 __le16 port_id; 5605 u8 unused_0[6]; 5606 }; 5607 5608 /* hwrm_port_led_qcaps_output (size:384b/48B) */ 5609 struct hwrm_port_led_qcaps_output { 5610 __le16 error_code; 5611 __le16 req_type; 5612 __le16 seq_id; 5613 __le16 resp_len; 5614 u8 num_leds; 5615 u8 unused[3]; 5616 u8 led0_id; 5617 u8 led0_type; 5618 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 5619 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 5620 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 5621 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 5622 u8 led0_group_id; 5623 u8 unused_0; 5624 __le16 led0_state_caps; 5625 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 5626 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 5627 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 5628 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5629 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5630 __le16 led0_color_caps; 5631 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 5632 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5633 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5634 u8 led1_id; 5635 u8 led1_type; 5636 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 5637 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 5638 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 5639 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 5640 u8 led1_group_id; 5641 u8 unused_1; 5642 __le16 led1_state_caps; 5643 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 5644 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 5645 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 5646 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5647 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5648 __le16 led1_color_caps; 5649 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 5650 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5651 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5652 u8 led2_id; 5653 u8 led2_type; 5654 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 5655 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 5656 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 5657 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 5658 u8 led2_group_id; 5659 u8 unused_2; 5660 __le16 led2_state_caps; 5661 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 5662 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 5663 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 5664 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5665 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5666 __le16 led2_color_caps; 5667 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 5668 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5669 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5670 u8 led3_id; 5671 u8 led3_type; 5672 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 5673 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 5674 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 5675 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 5676 u8 led3_group_id; 5677 u8 unused_3; 5678 __le16 led3_state_caps; 5679 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 5680 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 5681 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 5682 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5683 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5684 __le16 led3_color_caps; 5685 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 5686 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5687 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5688 u8 unused_4[3]; 5689 u8 valid; 5690 }; 5691 5692 /* hwrm_port_mac_qcaps_input (size:192b/24B) */ 5693 struct hwrm_port_mac_qcaps_input { 5694 __le16 req_type; 5695 __le16 cmpl_ring; 5696 __le16 seq_id; 5697 __le16 target_id; 5698 __le64 resp_addr; 5699 __le16 port_id; 5700 u8 unused_0[6]; 5701 }; 5702 5703 /* hwrm_port_mac_qcaps_output (size:128b/16B) */ 5704 struct hwrm_port_mac_qcaps_output { 5705 __le16 error_code; 5706 __le16 req_type; 5707 __le16 seq_id; 5708 __le16 resp_len; 5709 u8 flags; 5710 #define PORT_MAC_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x1UL 5711 #define PORT_MAC_QCAPS_RESP_FLAGS_REMOTE_LPBK_SUPPORTED 0x2UL 5712 u8 unused_0[6]; 5713 u8 valid; 5714 }; 5715 5716 /* hwrm_queue_qportcfg_input (size:192b/24B) */ 5717 struct hwrm_queue_qportcfg_input { 5718 __le16 req_type; 5719 __le16 cmpl_ring; 5720 __le16 seq_id; 5721 __le16 target_id; 5722 __le64 resp_addr; 5723 __le32 flags; 5724 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 5725 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 5726 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 5727 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 5728 __le16 port_id; 5729 u8 drv_qmap_cap; 5730 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 5731 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 5732 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 5733 u8 unused_0; 5734 }; 5735 5736 /* hwrm_queue_qportcfg_output (size:1344b/168B) */ 5737 struct hwrm_queue_qportcfg_output { 5738 __le16 error_code; 5739 __le16 req_type; 5740 __le16 seq_id; 5741 __le16 resp_len; 5742 u8 max_configurable_queues; 5743 u8 max_configurable_lossless_queues; 5744 u8 queue_cfg_allowed; 5745 u8 queue_cfg_info; 5746 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 5747 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_USE_PROFILE_TYPE 0x2UL 5748 u8 queue_pfcenable_cfg_allowed; 5749 u8 queue_pri2cos_cfg_allowed; 5750 u8 queue_cos2bw_cfg_allowed; 5751 u8 queue_id0; 5752 u8 queue_id0_service_profile; 5753 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 5754 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 5755 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5756 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5757 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5758 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 5759 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 5760 u8 queue_id1; 5761 u8 queue_id1_service_profile; 5762 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 5763 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 5764 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5765 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5766 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5767 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 5768 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 5769 u8 queue_id2; 5770 u8 queue_id2_service_profile; 5771 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 5772 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 5773 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5774 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5775 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5776 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 5777 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 5778 u8 queue_id3; 5779 u8 queue_id3_service_profile; 5780 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 5781 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 5782 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5783 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5784 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5785 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 5786 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 5787 u8 queue_id4; 5788 u8 queue_id4_service_profile; 5789 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 5790 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 5791 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5792 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5793 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5794 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 5795 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 5796 u8 queue_id5; 5797 u8 queue_id5_service_profile; 5798 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 5799 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 5800 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5801 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5802 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5803 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 5804 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 5805 u8 queue_id6; 5806 u8 queue_id6_service_profile; 5807 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 5808 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 5809 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5810 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5811 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5812 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 5813 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 5814 u8 queue_id7; 5815 u8 queue_id7_service_profile; 5816 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 5817 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 5818 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5819 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5820 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5821 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 5822 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 5823 u8 queue_id0_service_profile_type; 5824 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5825 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC 0x2UL 5826 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP 0x4UL 5827 char qid0_name[16]; 5828 char qid1_name[16]; 5829 char qid2_name[16]; 5830 char qid3_name[16]; 5831 char qid4_name[16]; 5832 char qid5_name[16]; 5833 char qid6_name[16]; 5834 char qid7_name[16]; 5835 u8 queue_id1_service_profile_type; 5836 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5837 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC 0x2UL 5838 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP 0x4UL 5839 u8 queue_id2_service_profile_type; 5840 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5841 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC 0x2UL 5842 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP 0x4UL 5843 u8 queue_id3_service_profile_type; 5844 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5845 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC 0x2UL 5846 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP 0x4UL 5847 u8 queue_id4_service_profile_type; 5848 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5849 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC 0x2UL 5850 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP 0x4UL 5851 u8 queue_id5_service_profile_type; 5852 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5853 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC 0x2UL 5854 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP 0x4UL 5855 u8 queue_id6_service_profile_type; 5856 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5857 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC 0x2UL 5858 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP 0x4UL 5859 u8 queue_id7_service_profile_type; 5860 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5861 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC 0x2UL 5862 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP 0x4UL 5863 u8 valid; 5864 }; 5865 5866 /* hwrm_queue_qcfg_input (size:192b/24B) */ 5867 struct hwrm_queue_qcfg_input { 5868 __le16 req_type; 5869 __le16 cmpl_ring; 5870 __le16 seq_id; 5871 __le16 target_id; 5872 __le64 resp_addr; 5873 __le32 flags; 5874 #define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL 5875 #define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL 5876 #define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL 5877 #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX 5878 __le32 queue_id; 5879 }; 5880 5881 /* hwrm_queue_qcfg_output (size:128b/16B) */ 5882 struct hwrm_queue_qcfg_output { 5883 __le16 error_code; 5884 __le16 req_type; 5885 __le16 seq_id; 5886 __le16 resp_len; 5887 __le32 queue_len; 5888 u8 service_profile; 5889 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL 5890 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL 5891 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL 5892 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 5893 u8 queue_cfg_info; 5894 #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 5895 u8 unused_0; 5896 u8 valid; 5897 }; 5898 5899 /* hwrm_queue_cfg_input (size:320b/40B) */ 5900 struct hwrm_queue_cfg_input { 5901 __le16 req_type; 5902 __le16 cmpl_ring; 5903 __le16 seq_id; 5904 __le16 target_id; 5905 __le64 resp_addr; 5906 __le32 flags; 5907 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 5908 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 5909 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 5910 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 5911 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 5912 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 5913 __le32 enables; 5914 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 5915 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 5916 __le32 queue_id; 5917 __le32 dflt_len; 5918 u8 service_profile; 5919 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 5920 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 5921 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 5922 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 5923 u8 unused_0[7]; 5924 }; 5925 5926 /* hwrm_queue_cfg_output (size:128b/16B) */ 5927 struct hwrm_queue_cfg_output { 5928 __le16 error_code; 5929 __le16 req_type; 5930 __le16 seq_id; 5931 __le16 resp_len; 5932 u8 unused_0[7]; 5933 u8 valid; 5934 }; 5935 5936 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 5937 struct hwrm_queue_pfcenable_qcfg_input { 5938 __le16 req_type; 5939 __le16 cmpl_ring; 5940 __le16 seq_id; 5941 __le16 target_id; 5942 __le64 resp_addr; 5943 __le16 port_id; 5944 u8 unused_0[6]; 5945 }; 5946 5947 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 5948 struct hwrm_queue_pfcenable_qcfg_output { 5949 __le16 error_code; 5950 __le16 req_type; 5951 __le16 seq_id; 5952 __le16 resp_len; 5953 __le32 flags; 5954 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 5955 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 5956 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 5957 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 5958 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 5959 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 5960 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 5961 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 5962 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 5963 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 5964 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 5965 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 5966 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 5967 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 5968 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 5969 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 5970 u8 unused_0[3]; 5971 u8 valid; 5972 }; 5973 5974 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 5975 struct hwrm_queue_pfcenable_cfg_input { 5976 __le16 req_type; 5977 __le16 cmpl_ring; 5978 __le16 seq_id; 5979 __le16 target_id; 5980 __le64 resp_addr; 5981 __le32 flags; 5982 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 5983 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 5984 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 5985 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 5986 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 5987 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 5988 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 5989 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 5990 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 5991 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 5992 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 5993 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 5994 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 5995 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 5996 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 5997 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 5998 __le16 port_id; 5999 u8 unused_0[2]; 6000 }; 6001 6002 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 6003 struct hwrm_queue_pfcenable_cfg_output { 6004 __le16 error_code; 6005 __le16 req_type; 6006 __le16 seq_id; 6007 __le16 resp_len; 6008 u8 unused_0[7]; 6009 u8 valid; 6010 }; 6011 6012 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 6013 struct hwrm_queue_pri2cos_qcfg_input { 6014 __le16 req_type; 6015 __le16 cmpl_ring; 6016 __le16 seq_id; 6017 __le16 target_id; 6018 __le64 resp_addr; 6019 __le32 flags; 6020 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 6021 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 6022 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 6023 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 6024 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 6025 u8 port_id; 6026 u8 unused_0[3]; 6027 }; 6028 6029 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 6030 struct hwrm_queue_pri2cos_qcfg_output { 6031 __le16 error_code; 6032 __le16 req_type; 6033 __le16 seq_id; 6034 __le16 resp_len; 6035 u8 pri0_cos_queue_id; 6036 u8 pri1_cos_queue_id; 6037 u8 pri2_cos_queue_id; 6038 u8 pri3_cos_queue_id; 6039 u8 pri4_cos_queue_id; 6040 u8 pri5_cos_queue_id; 6041 u8 pri6_cos_queue_id; 6042 u8 pri7_cos_queue_id; 6043 u8 queue_cfg_info; 6044 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 6045 u8 unused_0[6]; 6046 u8 valid; 6047 }; 6048 6049 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 6050 struct hwrm_queue_pri2cos_cfg_input { 6051 __le16 req_type; 6052 __le16 cmpl_ring; 6053 __le16 seq_id; 6054 __le16 target_id; 6055 __le64 resp_addr; 6056 __le32 flags; 6057 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 6058 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 6059 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 6060 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 6061 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 6062 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 6063 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 6064 __le32 enables; 6065 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 6066 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 6067 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 6068 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 6069 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 6070 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 6071 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 6072 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 6073 u8 port_id; 6074 u8 pri0_cos_queue_id; 6075 u8 pri1_cos_queue_id; 6076 u8 pri2_cos_queue_id; 6077 u8 pri3_cos_queue_id; 6078 u8 pri4_cos_queue_id; 6079 u8 pri5_cos_queue_id; 6080 u8 pri6_cos_queue_id; 6081 u8 pri7_cos_queue_id; 6082 u8 unused_0[7]; 6083 }; 6084 6085 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 6086 struct hwrm_queue_pri2cos_cfg_output { 6087 __le16 error_code; 6088 __le16 req_type; 6089 __le16 seq_id; 6090 __le16 resp_len; 6091 u8 unused_0[7]; 6092 u8 valid; 6093 }; 6094 6095 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 6096 struct hwrm_queue_cos2bw_qcfg_input { 6097 __le16 req_type; 6098 __le16 cmpl_ring; 6099 __le16 seq_id; 6100 __le16 target_id; 6101 __le64 resp_addr; 6102 __le16 port_id; 6103 u8 unused_0[6]; 6104 }; 6105 6106 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 6107 struct hwrm_queue_cos2bw_qcfg_output { 6108 __le16 error_code; 6109 __le16 req_type; 6110 __le16 seq_id; 6111 __le16 resp_len; 6112 u8 queue_id0; 6113 u8 unused_0; 6114 __le16 unused_1; 6115 __le32 queue_id0_min_bw; 6116 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6117 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 6118 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 6119 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 6120 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 6121 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 6122 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6123 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 6124 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6125 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6126 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6127 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6128 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6129 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6130 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 6131 __le32 queue_id0_max_bw; 6132 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6133 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 6134 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 6135 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 6136 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 6137 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 6138 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6139 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 6140 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6141 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6142 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6143 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6144 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6145 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6146 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 6147 u8 queue_id0_tsa_assign; 6148 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 6149 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 6150 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6151 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 6152 u8 queue_id0_pri_lvl; 6153 u8 queue_id0_bw_weight; 6154 struct { 6155 u8 queue_id; 6156 __le32 queue_id_min_bw; 6157 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6158 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_SFT 0 6159 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE 0x10000000UL 6160 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BITS (0x0UL << 28) 6161 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BYTES (0x1UL << 28) 6162 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BYTES 6163 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6164 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_SFT 29 6165 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6166 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6167 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6168 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6169 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6170 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6171 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID 6172 __le32 queue_id_max_bw; 6173 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6174 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_SFT 0 6175 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE 0x10000000UL 6176 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BITS (0x0UL << 28) 6177 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BYTES (0x1UL << 28) 6178 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BYTES 6179 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6180 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_SFT 29 6181 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6182 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6183 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6184 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6185 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6186 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6187 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID 6188 u8 queue_id_tsa_assign; 6189 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_SP 0x0UL 6190 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_ETS 0x1UL 6191 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6192 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_RESERVED_LAST 0xffUL 6193 u8 queue_id_pri_lvl; 6194 u8 queue_id_bw_weight; 6195 } __packed cfg[7]; 6196 u8 unused_2[4]; 6197 u8 valid; 6198 }; 6199 6200 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 6201 struct hwrm_queue_cos2bw_cfg_input { 6202 __le16 req_type; 6203 __le16 cmpl_ring; 6204 __le16 seq_id; 6205 __le16 target_id; 6206 __le64 resp_addr; 6207 __le32 flags; 6208 __le32 enables; 6209 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 6210 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 6211 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 6212 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 6213 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 6214 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 6215 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 6216 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 6217 __le16 port_id; 6218 u8 queue_id0; 6219 u8 unused_0; 6220 __le32 queue_id0_min_bw; 6221 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6222 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 6223 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 6224 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 6225 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 6226 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 6227 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6228 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 6229 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6230 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6231 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6232 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6233 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6234 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6235 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 6236 __le32 queue_id0_max_bw; 6237 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6238 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 6239 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 6240 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 6241 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 6242 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 6243 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6244 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 6245 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6246 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6247 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6248 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6249 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6250 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6251 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 6252 u8 queue_id0_tsa_assign; 6253 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 6254 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 6255 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6256 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 6257 u8 queue_id0_pri_lvl; 6258 u8 queue_id0_bw_weight; 6259 struct { 6260 u8 queue_id; 6261 __le32 queue_id_min_bw; 6262 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6263 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_SFT 0 6264 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE 0x10000000UL 6265 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BITS (0x0UL << 28) 6266 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BYTES (0x1UL << 28) 6267 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BYTES 6268 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6269 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_SFT 29 6270 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6271 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6272 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6273 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6274 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6275 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6276 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID 6277 __le32 queue_id_max_bw; 6278 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6279 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_SFT 0 6280 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE 0x10000000UL 6281 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BITS (0x0UL << 28) 6282 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BYTES (0x1UL << 28) 6283 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BYTES 6284 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6285 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_SFT 29 6286 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6287 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6288 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6289 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6290 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6291 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6292 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID 6293 u8 queue_id_tsa_assign; 6294 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_SP 0x0UL 6295 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_ETS 0x1UL 6296 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6297 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_RESERVED_LAST 0xffUL 6298 u8 queue_id_pri_lvl; 6299 u8 queue_id_bw_weight; 6300 } __packed cfg[7]; 6301 u8 unused_1[5]; 6302 }; 6303 6304 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 6305 struct hwrm_queue_cos2bw_cfg_output { 6306 __le16 error_code; 6307 __le16 req_type; 6308 __le16 seq_id; 6309 __le16 resp_len; 6310 u8 unused_0[7]; 6311 u8 valid; 6312 }; 6313 6314 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 6315 struct hwrm_queue_dscp_qcaps_input { 6316 __le16 req_type; 6317 __le16 cmpl_ring; 6318 __le16 seq_id; 6319 __le16 target_id; 6320 __le64 resp_addr; 6321 u8 port_id; 6322 u8 unused_0[7]; 6323 }; 6324 6325 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 6326 struct hwrm_queue_dscp_qcaps_output { 6327 __le16 error_code; 6328 __le16 req_type; 6329 __le16 seq_id; 6330 __le16 resp_len; 6331 u8 num_dscp_bits; 6332 u8 unused_0; 6333 __le16 max_entries; 6334 u8 unused_1[3]; 6335 u8 valid; 6336 }; 6337 6338 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 6339 struct hwrm_queue_dscp2pri_qcfg_input { 6340 __le16 req_type; 6341 __le16 cmpl_ring; 6342 __le16 seq_id; 6343 __le16 target_id; 6344 __le64 resp_addr; 6345 __le64 dest_data_addr; 6346 u8 port_id; 6347 u8 unused_0; 6348 __le16 dest_data_buffer_size; 6349 u8 unused_1[4]; 6350 }; 6351 6352 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 6353 struct hwrm_queue_dscp2pri_qcfg_output { 6354 __le16 error_code; 6355 __le16 req_type; 6356 __le16 seq_id; 6357 __le16 resp_len; 6358 __le16 entry_cnt; 6359 u8 default_pri; 6360 u8 unused_0[4]; 6361 u8 valid; 6362 }; 6363 6364 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 6365 struct hwrm_queue_dscp2pri_cfg_input { 6366 __le16 req_type; 6367 __le16 cmpl_ring; 6368 __le16 seq_id; 6369 __le16 target_id; 6370 __le64 resp_addr; 6371 __le64 src_data_addr; 6372 __le32 flags; 6373 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 6374 __le32 enables; 6375 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 6376 u8 port_id; 6377 u8 default_pri; 6378 __le16 entry_cnt; 6379 u8 unused_0[4]; 6380 }; 6381 6382 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 6383 struct hwrm_queue_dscp2pri_cfg_output { 6384 __le16 error_code; 6385 __le16 req_type; 6386 __le16 seq_id; 6387 __le16 resp_len; 6388 u8 unused_0[7]; 6389 u8 valid; 6390 }; 6391 6392 /* hwrm_vnic_alloc_input (size:192b/24B) */ 6393 struct hwrm_vnic_alloc_input { 6394 __le16 req_type; 6395 __le16 cmpl_ring; 6396 __le16 seq_id; 6397 __le16 target_id; 6398 __le64 resp_addr; 6399 __le32 flags; 6400 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 6401 #define VNIC_ALLOC_REQ_FLAGS_VIRTIO_NET_FID_VALID 0x2UL 6402 __le16 virtio_net_fid; 6403 u8 unused_0[2]; 6404 }; 6405 6406 /* hwrm_vnic_alloc_output (size:128b/16B) */ 6407 struct hwrm_vnic_alloc_output { 6408 __le16 error_code; 6409 __le16 req_type; 6410 __le16 seq_id; 6411 __le16 resp_len; 6412 __le32 vnic_id; 6413 u8 unused_0[3]; 6414 u8 valid; 6415 }; 6416 6417 /* hwrm_vnic_free_input (size:192b/24B) */ 6418 struct hwrm_vnic_free_input { 6419 __le16 req_type; 6420 __le16 cmpl_ring; 6421 __le16 seq_id; 6422 __le16 target_id; 6423 __le64 resp_addr; 6424 __le32 vnic_id; 6425 u8 unused_0[4]; 6426 }; 6427 6428 /* hwrm_vnic_free_output (size:128b/16B) */ 6429 struct hwrm_vnic_free_output { 6430 __le16 error_code; 6431 __le16 req_type; 6432 __le16 seq_id; 6433 __le16 resp_len; 6434 u8 unused_0[7]; 6435 u8 valid; 6436 }; 6437 6438 /* hwrm_vnic_cfg_input (size:384b/48B) */ 6439 struct hwrm_vnic_cfg_input { 6440 __le16 req_type; 6441 __le16 cmpl_ring; 6442 __le16 seq_id; 6443 __le16 target_id; 6444 __le64 resp_addr; 6445 __le32 flags; 6446 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 6447 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 6448 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 6449 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 6450 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 6451 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 6452 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 6453 #define VNIC_CFG_REQ_FLAGS_PORTCOS_MAPPING_MODE 0x80UL 6454 __le32 enables; 6455 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 6456 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 6457 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 6458 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 6459 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 6460 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 6461 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 6462 #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL 6463 #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL 6464 #define VNIC_CFG_REQ_ENABLES_L2_CQE_MODE 0x200UL 6465 __le16 vnic_id; 6466 __le16 dflt_ring_grp; 6467 __le16 rss_rule; 6468 __le16 cos_rule; 6469 __le16 lb_rule; 6470 __le16 mru; 6471 __le16 default_rx_ring_id; 6472 __le16 default_cmpl_ring_id; 6473 __le16 queue_id; 6474 u8 rx_csum_v2_mode; 6475 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL 6476 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK 0x1UL 6477 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 0x2UL 6478 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 6479 u8 l2_cqe_mode; 6480 #define VNIC_CFG_REQ_L2_CQE_MODE_DEFAULT 0x0UL 6481 #define VNIC_CFG_REQ_L2_CQE_MODE_COMPRESSED 0x1UL 6482 #define VNIC_CFG_REQ_L2_CQE_MODE_MIXED 0x2UL 6483 #define VNIC_CFG_REQ_L2_CQE_MODE_LAST VNIC_CFG_REQ_L2_CQE_MODE_MIXED 6484 u8 unused0[4]; 6485 }; 6486 6487 /* hwrm_vnic_cfg_output (size:128b/16B) */ 6488 struct hwrm_vnic_cfg_output { 6489 __le16 error_code; 6490 __le16 req_type; 6491 __le16 seq_id; 6492 __le16 resp_len; 6493 u8 unused_0[7]; 6494 u8 valid; 6495 }; 6496 6497 /* hwrm_vnic_qcaps_input (size:192b/24B) */ 6498 struct hwrm_vnic_qcaps_input { 6499 __le16 req_type; 6500 __le16 cmpl_ring; 6501 __le16 seq_id; 6502 __le16 target_id; 6503 __le64 resp_addr; 6504 __le32 enables; 6505 u8 unused_0[4]; 6506 }; 6507 6508 /* hwrm_vnic_qcaps_output (size:192b/24B) */ 6509 struct hwrm_vnic_qcaps_output { 6510 __le16 error_code; 6511 __le16 req_type; 6512 __le16 seq_id; 6513 __le16 resp_len; 6514 __le16 mru; 6515 u8 unused_0[2]; 6516 __le32 flags; 6517 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 6518 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 6519 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 6520 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 6521 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 6522 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 6523 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 6524 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 6525 #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL 6526 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL 6527 #define VNIC_QCAPS_RESP_FLAGS_VNIC_STATE_CAP 0x400UL 6528 #define VNIC_QCAPS_RESP_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP 0x800UL 6529 #define VNIC_QCAPS_RESP_FLAGS_METADATA_FORMAT_CAP 0x1000UL 6530 #define VNIC_QCAPS_RESP_FLAGS_RSS_STRICT_HASH_TYPE_CAP 0x2000UL 6531 #define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP 0x4000UL 6532 #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CAP 0x8000UL 6533 #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_XOR_CAP 0x10000UL 6534 #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CHKSM_CAP 0x20000UL 6535 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPV6_FLOW_LABEL_CAP 0x40000UL 6536 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V3_CAP 0x80000UL 6537 #define VNIC_QCAPS_RESP_FLAGS_L2_CQE_MODE_CAP 0x100000UL 6538 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP 0x200000UL 6539 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP 0x400000UL 6540 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP 0x800000UL 6541 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP 0x1000000UL 6542 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP 0x2000000UL 6543 #define VNIC_QCAPS_RESP_FLAGS_PORTCOS_MAPPING_MODE 0x4000000UL 6544 #define VNIC_QCAPS_RESP_FLAGS_RSS_PROF_TCAM_MODE_ENABLED 0x8000000UL 6545 #define VNIC_QCAPS_RESP_FLAGS_VNIC_RSS_HASH_MODE_CAP 0x10000000UL 6546 #define VNIC_QCAPS_RESP_FLAGS_HW_TUNNEL_TPA_CAP 0x20000000UL 6547 __le16 max_aggs_supported; 6548 u8 unused_1[5]; 6549 u8 valid; 6550 }; 6551 6552 /* hwrm_vnic_tpa_cfg_input (size:384b/48B) */ 6553 struct hwrm_vnic_tpa_cfg_input { 6554 __le16 req_type; 6555 __le16 cmpl_ring; 6556 __le16 seq_id; 6557 __le16 target_id; 6558 __le64 resp_addr; 6559 __le32 flags; 6560 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 6561 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 6562 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 6563 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 6564 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 6565 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 6566 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 6567 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 6568 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL 6569 __le32 enables; 6570 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 6571 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 6572 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 6573 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 6574 #define VNIC_TPA_CFG_REQ_ENABLES_TNL_TPA_EN 0x10UL 6575 __le16 vnic_id; 6576 __le16 max_agg_segs; 6577 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 6578 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 6579 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 6580 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 6581 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 6582 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 6583 __le16 max_aggs; 6584 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 6585 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 6586 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 6587 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 6588 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 6589 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 6590 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 6591 u8 unused_0[2]; 6592 __le32 max_agg_timer; 6593 __le32 min_agg_len; 6594 __le32 tnl_tpa_en_bitmap; 6595 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN 0x1UL 6596 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GENEVE 0x2UL 6597 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_NVGRE 0x4UL 6598 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GRE 0x8UL 6599 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_IPV4 0x10UL 6600 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_IPV6 0x20UL 6601 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN_GPE 0x40UL 6602 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN_CUST1 0x80UL 6603 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GRE_CUST1 0x100UL 6604 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR1 0x200UL 6605 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR2 0x400UL 6606 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR3 0x800UL 6607 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR4 0x1000UL 6608 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR5 0x2000UL 6609 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR6 0x4000UL 6610 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR7 0x8000UL 6611 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR8 0x10000UL 6612 u8 unused_1[4]; 6613 }; 6614 6615 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 6616 struct hwrm_vnic_tpa_cfg_output { 6617 __le16 error_code; 6618 __le16 req_type; 6619 __le16 seq_id; 6620 __le16 resp_len; 6621 u8 unused_0[7]; 6622 u8 valid; 6623 }; 6624 6625 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 6626 struct hwrm_vnic_tpa_qcfg_input { 6627 __le16 req_type; 6628 __le16 cmpl_ring; 6629 __le16 seq_id; 6630 __le16 target_id; 6631 __le64 resp_addr; 6632 __le16 vnic_id; 6633 u8 unused_0[6]; 6634 }; 6635 6636 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 6637 struct hwrm_vnic_tpa_qcfg_output { 6638 __le16 error_code; 6639 __le16 req_type; 6640 __le16 seq_id; 6641 __le16 resp_len; 6642 __le32 flags; 6643 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 6644 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 6645 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 6646 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 6647 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 6648 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 6649 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 6650 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 6651 __le16 max_agg_segs; 6652 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 6653 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 6654 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 6655 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 6656 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 6657 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 6658 __le16 max_aggs; 6659 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 6660 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 6661 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 6662 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 6663 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 6664 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 6665 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 6666 __le32 max_agg_timer; 6667 __le32 min_agg_len; 6668 __le32 tnl_tpa_en_bitmap; 6669 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN 0x1UL 6670 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GENEVE 0x2UL 6671 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_NVGRE 0x4UL 6672 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GRE 0x8UL 6673 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_IPV4 0x10UL 6674 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_IPV6 0x20UL 6675 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN_GPE 0x40UL 6676 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN_CUST1 0x80UL 6677 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GRE_CUST1 0x100UL 6678 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR1 0x200UL 6679 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR2 0x400UL 6680 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR3 0x800UL 6681 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR4 0x1000UL 6682 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR5 0x2000UL 6683 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR6 0x4000UL 6684 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR7 0x8000UL 6685 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR8 0x10000UL 6686 u8 unused_0[3]; 6687 u8 valid; 6688 }; 6689 6690 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 6691 struct hwrm_vnic_rss_cfg_input { 6692 __le16 req_type; 6693 __le16 cmpl_ring; 6694 __le16 seq_id; 6695 __le16 target_id; 6696 __le64 resp_addr; 6697 __le32 hash_type; 6698 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 6699 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 6700 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 6701 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 6702 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 6703 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 6704 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL 0x40UL 6705 #define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 0x80UL 6706 #define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4 0x100UL 6707 #define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 0x200UL 6708 #define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6 0x400UL 6709 __le16 vnic_id; 6710 u8 ring_table_pair_index; 6711 u8 hash_mode_flags; 6712 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 6713 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 6714 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 6715 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 6716 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 6717 __le64 ring_grp_tbl_addr; 6718 __le64 hash_key_tbl_addr; 6719 __le16 rss_ctx_idx; 6720 u8 flags; 6721 #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_INCLUDE 0x1UL 6722 #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_EXCLUDE 0x2UL 6723 #define VNIC_RSS_CFG_REQ_FLAGS_IPSEC_HASH_TYPE_CFG_SUPPORT 0x4UL 6724 u8 ring_select_mode; 6725 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ 0x0UL 6726 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_XOR 0x1UL 6727 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL 6728 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_LAST VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 6729 u8 unused_1[4]; 6730 }; 6731 6732 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 6733 struct hwrm_vnic_rss_cfg_output { 6734 __le16 error_code; 6735 __le16 req_type; 6736 __le16 seq_id; 6737 __le16 resp_len; 6738 u8 unused_0[7]; 6739 u8 valid; 6740 }; 6741 6742 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ 6743 struct hwrm_vnic_rss_cfg_cmd_err { 6744 u8 code; 6745 #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 6746 #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL 6747 #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 6748 u8 unused_0[7]; 6749 }; 6750 6751 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */ 6752 struct hwrm_vnic_rss_qcfg_input { 6753 __le16 req_type; 6754 __le16 cmpl_ring; 6755 __le16 seq_id; 6756 __le16 target_id; 6757 __le64 resp_addr; 6758 __le16 rss_ctx_idx; 6759 __le16 vnic_id; 6760 u8 unused_0[4]; 6761 }; 6762 6763 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */ 6764 struct hwrm_vnic_rss_qcfg_output { 6765 __le16 error_code; 6766 __le16 req_type; 6767 __le16 seq_id; 6768 __le16 resp_len; 6769 __le32 hash_type; 6770 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV4 0x1UL 6771 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV4 0x2UL 6772 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV4 0x4UL 6773 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6 0x8UL 6774 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV6 0x10UL 6775 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV6 0x20UL 6776 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6_FLOW_LABEL 0x40UL 6777 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV4 0x80UL 6778 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV4 0x100UL 6779 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV6 0x200UL 6780 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV6 0x400UL 6781 u8 unused_0[4]; 6782 __le32 hash_key[10]; 6783 u8 hash_mode_flags; 6784 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_DEFAULT 0x1UL 6785 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 6786 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 6787 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 6788 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 6789 u8 ring_select_mode; 6790 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ 0x0UL 6791 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_XOR 0x1UL 6792 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL 6793 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_LAST VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 6794 u8 unused_1[5]; 6795 u8 valid; 6796 }; 6797 6798 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 6799 struct hwrm_vnic_plcmodes_cfg_input { 6800 __le16 req_type; 6801 __le16 cmpl_ring; 6802 __le16 seq_id; 6803 __le16 target_id; 6804 __le64 resp_addr; 6805 __le32 flags; 6806 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 6807 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 6808 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 6809 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 6810 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 6811 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 6812 #define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT 0x40UL 6813 __le32 enables; 6814 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 6815 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 6816 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 6817 #define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID 0x8UL 6818 __le32 vnic_id; 6819 __le16 jumbo_thresh; 6820 __le16 hds_offset; 6821 __le16 hds_threshold; 6822 __le16 max_bds; 6823 u8 unused_0[4]; 6824 }; 6825 6826 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 6827 struct hwrm_vnic_plcmodes_cfg_output { 6828 __le16 error_code; 6829 __le16 req_type; 6830 __le16 seq_id; 6831 __le16 resp_len; 6832 u8 unused_0[7]; 6833 u8 valid; 6834 }; 6835 6836 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 6837 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 6838 __le16 req_type; 6839 __le16 cmpl_ring; 6840 __le16 seq_id; 6841 __le16 target_id; 6842 __le64 resp_addr; 6843 }; 6844 6845 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 6846 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 6847 __le16 error_code; 6848 __le16 req_type; 6849 __le16 seq_id; 6850 __le16 resp_len; 6851 __le16 rss_cos_lb_ctx_id; 6852 u8 unused_0[5]; 6853 u8 valid; 6854 }; 6855 6856 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 6857 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 6858 __le16 req_type; 6859 __le16 cmpl_ring; 6860 __le16 seq_id; 6861 __le16 target_id; 6862 __le64 resp_addr; 6863 __le16 rss_cos_lb_ctx_id; 6864 u8 unused_0[6]; 6865 }; 6866 6867 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 6868 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 6869 __le16 error_code; 6870 __le16 req_type; 6871 __le16 seq_id; 6872 __le16 resp_len; 6873 u8 unused_0[7]; 6874 u8 valid; 6875 }; 6876 6877 /* hwrm_ring_alloc_input (size:704b/88B) */ 6878 struct hwrm_ring_alloc_input { 6879 __le16 req_type; 6880 __le16 cmpl_ring; 6881 __le16 seq_id; 6882 __le16 target_id; 6883 __le64 resp_addr; 6884 __le32 enables; 6885 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 6886 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 6887 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 6888 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 6889 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 6890 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 6891 #define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL 6892 #define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL 6893 #define RING_ALLOC_REQ_ENABLES_STEERING_TAG_VALID 0x800UL 6894 u8 ring_type; 6895 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 6896 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 6897 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 6898 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 6899 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 6900 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 6901 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 6902 u8 cmpl_coal_cnt; 6903 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_OFF 0x0UL 6904 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_4 0x1UL 6905 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_8 0x2UL 6906 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_12 0x3UL 6907 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_16 0x4UL 6908 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_24 0x5UL 6909 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_32 0x6UL 6910 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_48 0x7UL 6911 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_64 0x8UL 6912 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_96 0x9UL 6913 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_128 0xaUL 6914 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_192 0xbUL 6915 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_256 0xcUL 6916 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_320 0xdUL 6917 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_384 0xeUL 6918 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 0xfUL 6919 #define RING_ALLOC_REQ_CMPL_COAL_CNT_LAST RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 6920 __le16 flags; 6921 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 6922 #define RING_ALLOC_REQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION 0x2UL 6923 #define RING_ALLOC_REQ_FLAGS_NQ_DBR_PACING 0x4UL 6924 #define RING_ALLOC_REQ_FLAGS_TX_PKT_TS_CMPL_ENABLE 0x8UL 6925 __le64 page_tbl_addr; 6926 __le32 fbo; 6927 u8 page_size; 6928 u8 page_tbl_depth; 6929 __le16 schq_id; 6930 __le32 length; 6931 __le16 logical_id; 6932 __le16 cmpl_ring_id; 6933 __le16 queue_id; 6934 __le16 rx_buf_size; 6935 __le16 rx_ring_id; 6936 __le16 nq_ring_id; 6937 __le16 ring_arb_cfg; 6938 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 6939 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 6940 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 6941 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 6942 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 6943 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 6944 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 6945 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 6946 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 6947 __le16 steering_tag; 6948 __le32 reserved3; 6949 __le32 stat_ctx_id; 6950 __le32 reserved4; 6951 __le32 max_bw; 6952 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6953 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 6954 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 6955 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 6956 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 6957 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 6958 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6959 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 6960 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6961 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6962 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6963 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6964 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6965 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6966 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 6967 u8 int_mode; 6968 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 6969 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 6970 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 6971 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 6972 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 6973 u8 mpc_chnls_type; 6974 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE 0x0UL 6975 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE 0x1UL 6976 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA 0x2UL 6977 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL 6978 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL 6979 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 6980 u8 unused_4[2]; 6981 __le64 cq_handle; 6982 }; 6983 6984 /* hwrm_ring_alloc_output (size:128b/16B) */ 6985 struct hwrm_ring_alloc_output { 6986 __le16 error_code; 6987 __le16 req_type; 6988 __le16 seq_id; 6989 __le16 resp_len; 6990 __le16 ring_id; 6991 __le16 logical_ring_id; 6992 u8 push_buffer_index; 6993 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 6994 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 6995 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_LAST RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 6996 u8 unused_0[2]; 6997 u8 valid; 6998 }; 6999 7000 /* hwrm_ring_free_input (size:256b/32B) */ 7001 struct hwrm_ring_free_input { 7002 __le16 req_type; 7003 __le16 cmpl_ring; 7004 __le16 seq_id; 7005 __le16 target_id; 7006 __le64 resp_addr; 7007 u8 ring_type; 7008 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 7009 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 7010 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 7011 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 7012 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 7013 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 7014 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 7015 u8 flags; 7016 #define RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 0x1UL 7017 #define RING_FREE_REQ_FLAGS_LAST RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 7018 __le16 ring_id; 7019 __le32 prod_idx; 7020 __le32 opaque; 7021 __le32 unused_1; 7022 }; 7023 7024 /* hwrm_ring_free_output (size:128b/16B) */ 7025 struct hwrm_ring_free_output { 7026 __le16 error_code; 7027 __le16 req_type; 7028 __le16 seq_id; 7029 __le16 resp_len; 7030 u8 unused_0[7]; 7031 u8 valid; 7032 }; 7033 7034 /* hwrm_ring_reset_input (size:192b/24B) */ 7035 struct hwrm_ring_reset_input { 7036 __le16 req_type; 7037 __le16 cmpl_ring; 7038 __le16 seq_id; 7039 __le16 target_id; 7040 __le64 resp_addr; 7041 u8 ring_type; 7042 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 7043 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 7044 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 7045 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 7046 #define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL 7047 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_RX_RING_GRP 7048 u8 unused_0; 7049 __le16 ring_id; 7050 u8 unused_1[4]; 7051 }; 7052 7053 /* hwrm_ring_reset_output (size:128b/16B) */ 7054 struct hwrm_ring_reset_output { 7055 __le16 error_code; 7056 __le16 req_type; 7057 __le16 seq_id; 7058 __le16 resp_len; 7059 u8 push_buffer_index; 7060 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 7061 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 7062 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_LAST RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 7063 u8 unused_0[3]; 7064 u8 consumer_idx[3]; 7065 u8 valid; 7066 }; 7067 7068 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 7069 struct hwrm_ring_aggint_qcaps_input { 7070 __le16 req_type; 7071 __le16 cmpl_ring; 7072 __le16 seq_id; 7073 __le16 target_id; 7074 __le64 resp_addr; 7075 }; 7076 7077 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 7078 struct hwrm_ring_aggint_qcaps_output { 7079 __le16 error_code; 7080 __le16 req_type; 7081 __le16 seq_id; 7082 __le16 resp_len; 7083 __le32 cmpl_params; 7084 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 7085 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 7086 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 7087 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 7088 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 7089 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 7090 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 7091 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 7092 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 7093 __le32 nq_params; 7094 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 7095 __le16 num_cmpl_dma_aggr_min; 7096 __le16 num_cmpl_dma_aggr_max; 7097 __le16 num_cmpl_dma_aggr_during_int_min; 7098 __le16 num_cmpl_dma_aggr_during_int_max; 7099 __le16 cmpl_aggr_dma_tmr_min; 7100 __le16 cmpl_aggr_dma_tmr_max; 7101 __le16 cmpl_aggr_dma_tmr_during_int_min; 7102 __le16 cmpl_aggr_dma_tmr_during_int_max; 7103 __le16 int_lat_tmr_min_min; 7104 __le16 int_lat_tmr_min_max; 7105 __le16 int_lat_tmr_max_min; 7106 __le16 int_lat_tmr_max_max; 7107 __le16 num_cmpl_aggr_int_min; 7108 __le16 num_cmpl_aggr_int_max; 7109 __le16 timer_units; 7110 u8 unused_0[1]; 7111 u8 valid; 7112 }; 7113 7114 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 7115 struct hwrm_ring_cmpl_ring_qaggint_params_input { 7116 __le16 req_type; 7117 __le16 cmpl_ring; 7118 __le16 seq_id; 7119 __le16 target_id; 7120 __le64 resp_addr; 7121 __le16 ring_id; 7122 __le16 flags; 7123 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL 7124 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0 7125 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 7126 u8 unused_0[4]; 7127 }; 7128 7129 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 7130 struct hwrm_ring_cmpl_ring_qaggint_params_output { 7131 __le16 error_code; 7132 __le16 req_type; 7133 __le16 seq_id; 7134 __le16 resp_len; 7135 __le16 flags; 7136 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 7137 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 7138 __le16 num_cmpl_dma_aggr; 7139 __le16 num_cmpl_dma_aggr_during_int; 7140 __le16 cmpl_aggr_dma_tmr; 7141 __le16 cmpl_aggr_dma_tmr_during_int; 7142 __le16 int_lat_tmr_min; 7143 __le16 int_lat_tmr_max; 7144 __le16 num_cmpl_aggr_int; 7145 u8 unused_0[7]; 7146 u8 valid; 7147 }; 7148 7149 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 7150 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 7151 __le16 req_type; 7152 __le16 cmpl_ring; 7153 __le16 seq_id; 7154 __le16 target_id; 7155 __le64 resp_addr; 7156 __le16 ring_id; 7157 __le16 flags; 7158 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 7159 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 7160 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 7161 __le16 num_cmpl_dma_aggr; 7162 __le16 num_cmpl_dma_aggr_during_int; 7163 __le16 cmpl_aggr_dma_tmr; 7164 __le16 cmpl_aggr_dma_tmr_during_int; 7165 __le16 int_lat_tmr_min; 7166 __le16 int_lat_tmr_max; 7167 __le16 num_cmpl_aggr_int; 7168 __le16 enables; 7169 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 7170 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 7171 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 7172 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 7173 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 7174 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 7175 u8 unused_0[4]; 7176 }; 7177 7178 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 7179 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 7180 __le16 error_code; 7181 __le16 req_type; 7182 __le16 seq_id; 7183 __le16 resp_len; 7184 u8 unused_0[7]; 7185 u8 valid; 7186 }; 7187 7188 /* hwrm_ring_grp_alloc_input (size:192b/24B) */ 7189 struct hwrm_ring_grp_alloc_input { 7190 __le16 req_type; 7191 __le16 cmpl_ring; 7192 __le16 seq_id; 7193 __le16 target_id; 7194 __le64 resp_addr; 7195 __le16 cr; 7196 __le16 rr; 7197 __le16 ar; 7198 __le16 sc; 7199 }; 7200 7201 /* hwrm_ring_grp_alloc_output (size:128b/16B) */ 7202 struct hwrm_ring_grp_alloc_output { 7203 __le16 error_code; 7204 __le16 req_type; 7205 __le16 seq_id; 7206 __le16 resp_len; 7207 __le32 ring_group_id; 7208 u8 unused_0[3]; 7209 u8 valid; 7210 }; 7211 7212 /* hwrm_ring_grp_free_input (size:192b/24B) */ 7213 struct hwrm_ring_grp_free_input { 7214 __le16 req_type; 7215 __le16 cmpl_ring; 7216 __le16 seq_id; 7217 __le16 target_id; 7218 __le64 resp_addr; 7219 __le32 ring_group_id; 7220 u8 unused_0[4]; 7221 }; 7222 7223 /* hwrm_ring_grp_free_output (size:128b/16B) */ 7224 struct hwrm_ring_grp_free_output { 7225 __le16 error_code; 7226 __le16 req_type; 7227 __le16 seq_id; 7228 __le16 resp_len; 7229 u8 unused_0[7]; 7230 u8 valid; 7231 }; 7232 7233 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL 7234 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL 7235 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL 7236 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL 7237 7238 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 7239 struct hwrm_cfa_l2_filter_alloc_input { 7240 __le16 req_type; 7241 __le16 cmpl_ring; 7242 __le16 seq_id; 7243 __le16 target_id; 7244 __le64 resp_addr; 7245 __le32 flags; 7246 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 7247 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 7248 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 7249 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 7250 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 7251 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 7252 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 7253 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 7254 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 7255 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 7256 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 7257 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 7258 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 7259 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL 7260 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL 7261 __le32 enables; 7262 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 7263 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 7264 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 7265 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 7266 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 7267 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 7268 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 7269 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 7270 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 7271 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 7272 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 7273 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 7274 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 7275 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 7276 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 7277 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 7278 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 7279 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL 7280 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL 7281 u8 l2_addr[6]; 7282 u8 num_vlans; 7283 u8 t_num_vlans; 7284 u8 l2_addr_mask[6]; 7285 __le16 l2_ovlan; 7286 __le16 l2_ovlan_mask; 7287 __le16 l2_ivlan; 7288 __le16 l2_ivlan_mask; 7289 u8 unused_1[2]; 7290 u8 t_l2_addr[6]; 7291 u8 unused_2[2]; 7292 u8 t_l2_addr_mask[6]; 7293 __le16 t_l2_ovlan; 7294 __le16 t_l2_ovlan_mask; 7295 __le16 t_l2_ivlan; 7296 __le16 t_l2_ivlan_mask; 7297 u8 src_type; 7298 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 7299 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 7300 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 7301 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 7302 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 7303 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 7304 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 7305 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 7306 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 7307 u8 unused_3; 7308 __le32 src_id; 7309 u8 tunnel_type; 7310 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7311 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7312 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7313 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7314 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7315 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7316 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7317 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7318 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7319 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7320 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7321 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7322 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7323 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 7324 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7325 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7326 u8 unused_4; 7327 __le16 dst_id; 7328 __le16 mirror_vnic_id; 7329 u8 pri_hint; 7330 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 7331 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 7332 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 7333 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 7334 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 7335 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 7336 u8 unused_5; 7337 __le32 unused_6; 7338 __le64 l2_filter_id_hint; 7339 }; 7340 7341 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 7342 struct hwrm_cfa_l2_filter_alloc_output { 7343 __le16 error_code; 7344 __le16 req_type; 7345 __le16 seq_id; 7346 __le16 resp_len; 7347 __le64 l2_filter_id; 7348 __le32 flow_id; 7349 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7350 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7351 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7352 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7353 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7354 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 7355 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7356 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7357 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7358 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7359 u8 unused_0[3]; 7360 u8 valid; 7361 }; 7362 7363 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 7364 struct hwrm_cfa_l2_filter_free_input { 7365 __le16 req_type; 7366 __le16 cmpl_ring; 7367 __le16 seq_id; 7368 __le16 target_id; 7369 __le64 resp_addr; 7370 __le64 l2_filter_id; 7371 }; 7372 7373 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 7374 struct hwrm_cfa_l2_filter_free_output { 7375 __le16 error_code; 7376 __le16 req_type; 7377 __le16 seq_id; 7378 __le16 resp_len; 7379 u8 unused_0[7]; 7380 u8 valid; 7381 }; 7382 7383 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ 7384 struct hwrm_cfa_l2_filter_cfg_input { 7385 __le16 req_type; 7386 __le16 cmpl_ring; 7387 __le16 seq_id; 7388 __le16 target_id; 7389 __le64 resp_addr; 7390 __le32 flags; 7391 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 7392 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 7393 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 7394 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 7395 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 7396 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 7397 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 7398 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 7399 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 7400 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 7401 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 7402 __le32 enables; 7403 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 7404 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 7405 __le64 l2_filter_id; 7406 __le32 dst_id; 7407 __le32 new_mirror_vnic_id; 7408 }; 7409 7410 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 7411 struct hwrm_cfa_l2_filter_cfg_output { 7412 __le16 error_code; 7413 __le16 req_type; 7414 __le16 seq_id; 7415 __le16 resp_len; 7416 u8 unused_0[7]; 7417 u8 valid; 7418 }; 7419 7420 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 7421 struct hwrm_cfa_l2_set_rx_mask_input { 7422 __le16 req_type; 7423 __le16 cmpl_ring; 7424 __le16 seq_id; 7425 __le16 target_id; 7426 __le64 resp_addr; 7427 __le32 vnic_id; 7428 __le32 mask; 7429 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 7430 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 7431 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 7432 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 7433 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 7434 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 7435 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 7436 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 7437 __le64 mc_tbl_addr; 7438 __le32 num_mc_entries; 7439 u8 unused_0[4]; 7440 __le64 vlan_tag_tbl_addr; 7441 __le32 num_vlan_tags; 7442 u8 unused_1[4]; 7443 }; 7444 7445 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 7446 struct hwrm_cfa_l2_set_rx_mask_output { 7447 __le16 error_code; 7448 __le16 req_type; 7449 __le16 seq_id; 7450 __le16 resp_len; 7451 u8 unused_0[7]; 7452 u8 valid; 7453 }; 7454 7455 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 7456 struct hwrm_cfa_l2_set_rx_mask_cmd_err { 7457 u8 code; 7458 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 7459 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 7460 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 7461 u8 unused_0[7]; 7462 }; 7463 7464 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 7465 struct hwrm_cfa_tunnel_filter_alloc_input { 7466 __le16 req_type; 7467 __le16 cmpl_ring; 7468 __le16 seq_id; 7469 __le16 target_id; 7470 __le64 resp_addr; 7471 __le32 flags; 7472 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7473 __le32 enables; 7474 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 7475 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 7476 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 7477 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 7478 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 7479 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 7480 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 7481 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 7482 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 7483 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 7484 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 7485 __le64 l2_filter_id; 7486 u8 l2_addr[6]; 7487 __le16 l2_ivlan; 7488 __le32 l3_addr[4]; 7489 __le32 t_l3_addr[4]; 7490 u8 l3_addr_type; 7491 u8 t_l3_addr_type; 7492 u8 tunnel_type; 7493 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7494 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7495 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7496 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7497 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7498 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7499 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7500 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7501 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7502 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7503 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7504 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7505 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7506 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 7507 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7508 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7509 u8 tunnel_flags; 7510 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 7511 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 7512 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 7513 __le32 vni; 7514 __le32 dst_vnic_id; 7515 __le32 mirror_vnic_id; 7516 }; 7517 7518 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 7519 struct hwrm_cfa_tunnel_filter_alloc_output { 7520 __le16 error_code; 7521 __le16 req_type; 7522 __le16 seq_id; 7523 __le16 resp_len; 7524 __le64 tunnel_filter_id; 7525 __le32 flow_id; 7526 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7527 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7528 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7529 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7530 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7531 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 7532 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7533 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7534 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7535 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7536 u8 unused_0[3]; 7537 u8 valid; 7538 }; 7539 7540 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 7541 struct hwrm_cfa_tunnel_filter_free_input { 7542 __le16 req_type; 7543 __le16 cmpl_ring; 7544 __le16 seq_id; 7545 __le16 target_id; 7546 __le64 resp_addr; 7547 __le64 tunnel_filter_id; 7548 }; 7549 7550 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 7551 struct hwrm_cfa_tunnel_filter_free_output { 7552 __le16 error_code; 7553 __le16 req_type; 7554 __le16 seq_id; 7555 __le16 resp_len; 7556 u8 unused_0[7]; 7557 u8 valid; 7558 }; 7559 7560 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 7561 struct hwrm_vxlan_ipv4_hdr { 7562 u8 ver_hlen; 7563 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 7564 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 7565 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 7566 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 7567 u8 tos; 7568 __be16 ip_id; 7569 __be16 flags_frag_offset; 7570 u8 ttl; 7571 u8 protocol; 7572 __be32 src_ip_addr; 7573 __be32 dest_ip_addr; 7574 }; 7575 7576 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 7577 struct hwrm_vxlan_ipv6_hdr { 7578 __be32 ver_tc_flow_label; 7579 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 7580 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 7581 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 7582 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 7583 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 7584 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 7585 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 7586 __be16 payload_len; 7587 u8 next_hdr; 7588 u8 ttl; 7589 __be32 src_ip_addr[4]; 7590 __be32 dest_ip_addr[4]; 7591 }; 7592 7593 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 7594 struct hwrm_cfa_encap_data_vxlan { 7595 u8 src_mac_addr[6]; 7596 __le16 unused_0; 7597 u8 dst_mac_addr[6]; 7598 u8 num_vlan_tags; 7599 u8 unused_1; 7600 __be16 ovlan_tpid; 7601 __be16 ovlan_tci; 7602 __be16 ivlan_tpid; 7603 __be16 ivlan_tci; 7604 __le32 l3[10]; 7605 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 7606 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 7607 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 7608 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 7609 __be16 src_port; 7610 __be16 dst_port; 7611 __be32 vni; 7612 u8 hdr_rsvd0[3]; 7613 u8 hdr_rsvd1; 7614 u8 hdr_flags; 7615 u8 unused[3]; 7616 }; 7617 7618 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 7619 struct hwrm_cfa_encap_record_alloc_input { 7620 __le16 req_type; 7621 __le16 cmpl_ring; 7622 __le16 seq_id; 7623 __le16 target_id; 7624 __le64 resp_addr; 7625 __le32 flags; 7626 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7627 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL 7628 u8 encap_type; 7629 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 7630 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 7631 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 7632 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 7633 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 7634 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 7635 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 7636 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 7637 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 7638 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 7639 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 7640 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL 7641 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE 0x10UL 7642 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE 7643 u8 unused_0[3]; 7644 __le32 encap_data[20]; 7645 }; 7646 7647 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 7648 struct hwrm_cfa_encap_record_alloc_output { 7649 __le16 error_code; 7650 __le16 req_type; 7651 __le16 seq_id; 7652 __le16 resp_len; 7653 __le32 encap_record_id; 7654 u8 unused_0[3]; 7655 u8 valid; 7656 }; 7657 7658 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 7659 struct hwrm_cfa_encap_record_free_input { 7660 __le16 req_type; 7661 __le16 cmpl_ring; 7662 __le16 seq_id; 7663 __le16 target_id; 7664 __le64 resp_addr; 7665 __le32 encap_record_id; 7666 u8 unused_0[4]; 7667 }; 7668 7669 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 7670 struct hwrm_cfa_encap_record_free_output { 7671 __le16 error_code; 7672 __le16 req_type; 7673 __le16 seq_id; 7674 __le16 resp_len; 7675 u8 unused_0[7]; 7676 u8 valid; 7677 }; 7678 7679 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 7680 struct hwrm_cfa_ntuple_filter_alloc_input { 7681 __le16 req_type; 7682 __le16 cmpl_ring; 7683 __le16 seq_id; 7684 __le16 target_id; 7685 __le64 resp_addr; 7686 __le32 flags; 7687 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7688 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 7689 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 7690 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL 7691 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL 7692 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL 7693 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_NO_L2_CONTEXT 0x40UL 7694 __le32 enables; 7695 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 7696 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 7697 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 7698 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 7699 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 7700 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 7701 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 7702 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 7703 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 7704 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 7705 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 7706 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 7707 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 7708 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 7709 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 7710 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 7711 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 7712 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 7713 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 7714 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL 7715 __le64 l2_filter_id; 7716 u8 src_macaddr[6]; 7717 __be16 ethertype; 7718 u8 ip_addr_type; 7719 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 7720 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 7721 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 7722 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 7723 u8 ip_protocol; 7724 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 7725 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 7726 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 7727 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_ICMP 0x1UL 7728 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_ICMPV6 0x3aUL 7729 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD 0xffUL 7730 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD 7731 __le16 dst_id; 7732 __le16 rfs_ring_tbl_idx; 7733 u8 tunnel_type; 7734 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7735 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7736 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7737 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7738 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7739 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7740 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7741 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7742 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7743 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7744 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7745 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7746 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7747 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 7748 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7749 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7750 u8 pri_hint; 7751 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 7752 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 7753 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 7754 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 7755 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 7756 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 7757 __be32 src_ipaddr[4]; 7758 __be32 src_ipaddr_mask[4]; 7759 __be32 dst_ipaddr[4]; 7760 __be32 dst_ipaddr_mask[4]; 7761 __be16 src_port; 7762 __be16 src_port_mask; 7763 __be16 dst_port; 7764 __be16 dst_port_mask; 7765 __le64 ntuple_filter_id_hint; 7766 }; 7767 7768 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 7769 struct hwrm_cfa_ntuple_filter_alloc_output { 7770 __le16 error_code; 7771 __le16 req_type; 7772 __le16 seq_id; 7773 __le16 resp_len; 7774 __le64 ntuple_filter_id; 7775 __le32 flow_id; 7776 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7777 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7778 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7779 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7780 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7781 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 7782 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7783 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7784 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7785 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7786 u8 unused_0[3]; 7787 u8 valid; 7788 }; 7789 7790 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 7791 struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 7792 u8 code; 7793 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 7794 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 7795 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 7796 u8 unused_0[7]; 7797 }; 7798 7799 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 7800 struct hwrm_cfa_ntuple_filter_free_input { 7801 __le16 req_type; 7802 __le16 cmpl_ring; 7803 __le16 seq_id; 7804 __le16 target_id; 7805 __le64 resp_addr; 7806 __le64 ntuple_filter_id; 7807 }; 7808 7809 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 7810 struct hwrm_cfa_ntuple_filter_free_output { 7811 __le16 error_code; 7812 __le16 req_type; 7813 __le16 seq_id; 7814 __le16 resp_len; 7815 u8 unused_0[7]; 7816 u8 valid; 7817 }; 7818 7819 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 7820 struct hwrm_cfa_ntuple_filter_cfg_input { 7821 __le16 req_type; 7822 __le16 cmpl_ring; 7823 __le16 seq_id; 7824 __le16 target_id; 7825 __le64 resp_addr; 7826 __le32 enables; 7827 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 7828 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 7829 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 7830 __le32 flags; 7831 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL 7832 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL 7833 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_NO_L2_CONTEXT 0x4UL 7834 __le64 ntuple_filter_id; 7835 __le32 new_dst_id; 7836 __le32 new_mirror_vnic_id; 7837 __le16 new_meter_instance_id; 7838 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 7839 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 7840 u8 unused_1[6]; 7841 }; 7842 7843 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 7844 struct hwrm_cfa_ntuple_filter_cfg_output { 7845 __le16 error_code; 7846 __le16 req_type; 7847 __le16 seq_id; 7848 __le16 resp_len; 7849 u8 unused_0[7]; 7850 u8 valid; 7851 }; 7852 7853 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 7854 struct hwrm_cfa_decap_filter_alloc_input { 7855 __le16 req_type; 7856 __le16 cmpl_ring; 7857 __le16 seq_id; 7858 __le16 target_id; 7859 __le64 resp_addr; 7860 __le32 flags; 7861 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 7862 __le32 enables; 7863 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 7864 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 7865 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 7866 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 7867 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 7868 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 7869 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 7870 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 7871 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 7872 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 7873 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 7874 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 7875 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 7876 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 7877 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 7878 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 7879 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 7880 __be32 tunnel_id; 7881 u8 tunnel_type; 7882 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7883 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7884 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7885 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7886 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7887 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7888 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7889 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7890 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7891 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7892 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7893 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7894 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7895 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 7896 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7897 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7898 u8 unused_0; 7899 __le16 unused_1; 7900 u8 src_macaddr[6]; 7901 u8 unused_2[2]; 7902 u8 dst_macaddr[6]; 7903 __be16 ovlan_vid; 7904 __be16 ivlan_vid; 7905 __be16 t_ovlan_vid; 7906 __be16 t_ivlan_vid; 7907 __be16 ethertype; 7908 u8 ip_addr_type; 7909 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 7910 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 7911 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 7912 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 7913 u8 ip_protocol; 7914 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 7915 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 7916 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 7917 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 7918 __le16 unused_3; 7919 __le32 unused_4; 7920 __be32 src_ipaddr[4]; 7921 __be32 dst_ipaddr[4]; 7922 __be16 src_port; 7923 __be16 dst_port; 7924 __le16 dst_id; 7925 __le16 l2_ctxt_ref_id; 7926 }; 7927 7928 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 7929 struct hwrm_cfa_decap_filter_alloc_output { 7930 __le16 error_code; 7931 __le16 req_type; 7932 __le16 seq_id; 7933 __le16 resp_len; 7934 __le32 decap_filter_id; 7935 u8 unused_0[3]; 7936 u8 valid; 7937 }; 7938 7939 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 7940 struct hwrm_cfa_decap_filter_free_input { 7941 __le16 req_type; 7942 __le16 cmpl_ring; 7943 __le16 seq_id; 7944 __le16 target_id; 7945 __le64 resp_addr; 7946 __le32 decap_filter_id; 7947 u8 unused_0[4]; 7948 }; 7949 7950 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 7951 struct hwrm_cfa_decap_filter_free_output { 7952 __le16 error_code; 7953 __le16 req_type; 7954 __le16 seq_id; 7955 __le16 resp_len; 7956 u8 unused_0[7]; 7957 u8 valid; 7958 }; 7959 7960 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 7961 struct hwrm_cfa_flow_alloc_input { 7962 __le16 req_type; 7963 __le16 cmpl_ring; 7964 __le16 seq_id; 7965 __le16 target_id; 7966 __le64 resp_addr; 7967 __le16 flags; 7968 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 7969 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 7970 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 7971 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 7972 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 7973 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 7974 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 7975 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 7976 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 7977 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 7978 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 7979 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 7980 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 7981 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 7982 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 7983 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 7984 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL 7985 __le16 src_fid; 7986 __le32 tunnel_handle; 7987 __le16 action_flags; 7988 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 7989 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 7990 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 7991 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 7992 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 7993 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 7994 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 7995 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 7996 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 7997 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 7998 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 7999 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL 8000 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL 8001 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL 8002 __le16 dst_fid; 8003 __be16 l2_rewrite_vlan_tpid; 8004 __be16 l2_rewrite_vlan_tci; 8005 __le16 act_meter_id; 8006 __le16 ref_flow_handle; 8007 __be16 ethertype; 8008 __be16 outer_vlan_tci; 8009 __be16 dmac[3]; 8010 __be16 inner_vlan_tci; 8011 __be16 smac[3]; 8012 u8 ip_dst_mask_len; 8013 u8 ip_src_mask_len; 8014 __be32 ip_dst[4]; 8015 __be32 ip_src[4]; 8016 __be16 l4_src_port; 8017 __be16 l4_src_port_mask; 8018 __be16 l4_dst_port; 8019 __be16 l4_dst_port_mask; 8020 __be32 nat_ip_address[4]; 8021 __be16 l2_rewrite_dmac[3]; 8022 __be16 nat_port; 8023 __be16 l2_rewrite_smac[3]; 8024 u8 ip_proto; 8025 u8 tunnel_type; 8026 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 8027 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8028 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 8029 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 8030 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 8031 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8032 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 8033 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 8034 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 8035 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8036 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8037 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8038 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8039 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8040 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 8041 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 8042 }; 8043 8044 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 8045 struct hwrm_cfa_flow_alloc_output { 8046 __le16 error_code; 8047 __le16 req_type; 8048 __le16 seq_id; 8049 __le16 resp_len; 8050 __le16 flow_handle; 8051 u8 unused_0[2]; 8052 __le32 flow_id; 8053 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 8054 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 8055 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 8056 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 8057 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 8058 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT 8059 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 8060 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 8061 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 8062 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX 8063 __le64 ext_flow_handle; 8064 __le32 flow_counter_id; 8065 u8 unused_1[3]; 8066 u8 valid; 8067 }; 8068 8069 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ 8070 struct hwrm_cfa_flow_alloc_cmd_err { 8071 u8 code; 8072 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 8073 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL 8074 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL 8075 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL 8076 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL 8077 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL 8078 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL 8079 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL 8080 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 8081 u8 unused_0[7]; 8082 }; 8083 8084 /* hwrm_cfa_flow_free_input (size:256b/32B) */ 8085 struct hwrm_cfa_flow_free_input { 8086 __le16 req_type; 8087 __le16 cmpl_ring; 8088 __le16 seq_id; 8089 __le16 target_id; 8090 __le64 resp_addr; 8091 __le16 flow_handle; 8092 __le16 unused_0; 8093 __le32 flow_counter_id; 8094 __le64 ext_flow_handle; 8095 }; 8096 8097 /* hwrm_cfa_flow_free_output (size:256b/32B) */ 8098 struct hwrm_cfa_flow_free_output { 8099 __le16 error_code; 8100 __le16 req_type; 8101 __le16 seq_id; 8102 __le16 resp_len; 8103 __le64 packet; 8104 __le64 byte; 8105 u8 unused_0[7]; 8106 u8 valid; 8107 }; 8108 8109 /* hwrm_cfa_flow_info_input (size:256b/32B) */ 8110 struct hwrm_cfa_flow_info_input { 8111 __le16 req_type; 8112 __le16 cmpl_ring; 8113 __le16 seq_id; 8114 __le16 target_id; 8115 __le64 resp_addr; 8116 __le16 flow_handle; 8117 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL 8118 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL 8119 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL 8120 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_TX 0x3000UL 8121 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL 8122 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL 8123 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT_RX 0x9000UL 8124 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT_RX 0xa000UL 8125 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_RX 0xb000UL 8126 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX 0xc000UL 8127 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_LAST CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX 8128 u8 unused_0[6]; 8129 __le64 ext_flow_handle; 8130 }; 8131 8132 /* hwrm_cfa_flow_info_output (size:5632b/704B) */ 8133 struct hwrm_cfa_flow_info_output { 8134 __le16 error_code; 8135 __le16 req_type; 8136 __le16 seq_id; 8137 __le16 resp_len; 8138 u8 flags; 8139 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL 8140 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL 8141 u8 profile; 8142 __le16 src_fid; 8143 __le16 dst_fid; 8144 __le16 l2_ctxt_id; 8145 __le64 em_info; 8146 __le64 tcam_info; 8147 __le64 vfp_tcam_info; 8148 __le16 ar_id; 8149 __le16 flow_handle; 8150 __le32 tunnel_handle; 8151 __le16 flow_timer; 8152 u8 unused_0[6]; 8153 __le32 flow_key_data[130]; 8154 __le32 flow_action_info[30]; 8155 u8 unused_1[7]; 8156 u8 valid; 8157 }; 8158 8159 /* hwrm_cfa_flow_stats_input (size:640b/80B) */ 8160 struct hwrm_cfa_flow_stats_input { 8161 __le16 req_type; 8162 __le16 cmpl_ring; 8163 __le16 seq_id; 8164 __le16 target_id; 8165 __le64 resp_addr; 8166 __le16 num_flows; 8167 __le16 flow_handle_0; 8168 __le16 flow_handle_1; 8169 __le16 flow_handle_2; 8170 __le16 flow_handle_3; 8171 __le16 flow_handle_4; 8172 __le16 flow_handle_5; 8173 __le16 flow_handle_6; 8174 __le16 flow_handle_7; 8175 __le16 flow_handle_8; 8176 __le16 flow_handle_9; 8177 u8 unused_0[2]; 8178 __le32 flow_id_0; 8179 __le32 flow_id_1; 8180 __le32 flow_id_2; 8181 __le32 flow_id_3; 8182 __le32 flow_id_4; 8183 __le32 flow_id_5; 8184 __le32 flow_id_6; 8185 __le32 flow_id_7; 8186 __le32 flow_id_8; 8187 __le32 flow_id_9; 8188 }; 8189 8190 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 8191 struct hwrm_cfa_flow_stats_output { 8192 __le16 error_code; 8193 __le16 req_type; 8194 __le16 seq_id; 8195 __le16 resp_len; 8196 __le64 packet_0; 8197 __le64 packet_1; 8198 __le64 packet_2; 8199 __le64 packet_3; 8200 __le64 packet_4; 8201 __le64 packet_5; 8202 __le64 packet_6; 8203 __le64 packet_7; 8204 __le64 packet_8; 8205 __le64 packet_9; 8206 __le64 byte_0; 8207 __le64 byte_1; 8208 __le64 byte_2; 8209 __le64 byte_3; 8210 __le64 byte_4; 8211 __le64 byte_5; 8212 __le64 byte_6; 8213 __le64 byte_7; 8214 __le64 byte_8; 8215 __le64 byte_9; 8216 __le16 flow_hits; 8217 u8 unused_0[5]; 8218 u8 valid; 8219 }; 8220 8221 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 8222 struct hwrm_cfa_vfr_alloc_input { 8223 __le16 req_type; 8224 __le16 cmpl_ring; 8225 __le16 seq_id; 8226 __le16 target_id; 8227 __le64 resp_addr; 8228 __le16 vf_id; 8229 __le16 reserved; 8230 u8 unused_0[4]; 8231 char vfr_name[32]; 8232 }; 8233 8234 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 8235 struct hwrm_cfa_vfr_alloc_output { 8236 __le16 error_code; 8237 __le16 req_type; 8238 __le16 seq_id; 8239 __le16 resp_len; 8240 __le16 rx_cfa_code; 8241 __le16 tx_cfa_action; 8242 u8 unused_0[3]; 8243 u8 valid; 8244 }; 8245 8246 /* hwrm_cfa_vfr_free_input (size:448b/56B) */ 8247 struct hwrm_cfa_vfr_free_input { 8248 __le16 req_type; 8249 __le16 cmpl_ring; 8250 __le16 seq_id; 8251 __le16 target_id; 8252 __le64 resp_addr; 8253 char vfr_name[32]; 8254 __le16 vf_id; 8255 __le16 reserved; 8256 u8 unused_0[4]; 8257 }; 8258 8259 /* hwrm_cfa_vfr_free_output (size:128b/16B) */ 8260 struct hwrm_cfa_vfr_free_output { 8261 __le16 error_code; 8262 __le16 req_type; 8263 __le16 seq_id; 8264 __le16 resp_len; 8265 u8 unused_0[7]; 8266 u8 valid; 8267 }; 8268 8269 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ 8270 struct hwrm_cfa_eem_qcaps_input { 8271 __le16 req_type; 8272 __le16 cmpl_ring; 8273 __le16 seq_id; 8274 __le16 target_id; 8275 __le64 resp_addr; 8276 __le32 flags; 8277 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL 8278 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL 8279 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 8280 __le32 unused_0; 8281 }; 8282 8283 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ 8284 struct hwrm_cfa_eem_qcaps_output { 8285 __le16 error_code; 8286 __le16 req_type; 8287 __le16 seq_id; 8288 __le16 resp_len; 8289 __le32 flags; 8290 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL 8291 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL 8292 #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL 8293 #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL 8294 __le32 unused_0; 8295 __le32 supported; 8296 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL 8297 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL 8298 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL 8299 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL 8300 #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL 8301 __le32 max_entries_supported; 8302 __le16 key_entry_size; 8303 __le16 record_entry_size; 8304 __le16 efc_entry_size; 8305 __le16 fid_entry_size; 8306 u8 unused_1[7]; 8307 u8 valid; 8308 }; 8309 8310 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */ 8311 struct hwrm_cfa_eem_cfg_input { 8312 __le16 req_type; 8313 __le16 cmpl_ring; 8314 __le16 seq_id; 8315 __le16 target_id; 8316 __le64 resp_addr; 8317 __le32 flags; 8318 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL 8319 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL 8320 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 8321 #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL 8322 __le16 group_id; 8323 __le16 unused_0; 8324 __le32 num_entries; 8325 __le32 unused_1; 8326 __le16 key0_ctx_id; 8327 __le16 key1_ctx_id; 8328 __le16 record_ctx_id; 8329 __le16 efc_ctx_id; 8330 __le16 fid_ctx_id; 8331 __le16 unused_2; 8332 __le32 unused_3; 8333 }; 8334 8335 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */ 8336 struct hwrm_cfa_eem_cfg_output { 8337 __le16 error_code; 8338 __le16 req_type; 8339 __le16 seq_id; 8340 __le16 resp_len; 8341 u8 unused_0[7]; 8342 u8 valid; 8343 }; 8344 8345 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ 8346 struct hwrm_cfa_eem_qcfg_input { 8347 __le16 req_type; 8348 __le16 cmpl_ring; 8349 __le16 seq_id; 8350 __le16 target_id; 8351 __le64 resp_addr; 8352 __le32 flags; 8353 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL 8354 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL 8355 __le32 unused_0; 8356 }; 8357 8358 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ 8359 struct hwrm_cfa_eem_qcfg_output { 8360 __le16 error_code; 8361 __le16 req_type; 8362 __le16 seq_id; 8363 __le16 resp_len; 8364 __le32 flags; 8365 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL 8366 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL 8367 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL 8368 __le32 num_entries; 8369 __le16 key0_ctx_id; 8370 __le16 key1_ctx_id; 8371 __le16 record_ctx_id; 8372 __le16 efc_ctx_id; 8373 __le16 fid_ctx_id; 8374 u8 unused_2[5]; 8375 u8 valid; 8376 }; 8377 8378 /* hwrm_cfa_eem_op_input (size:192b/24B) */ 8379 struct hwrm_cfa_eem_op_input { 8380 __le16 req_type; 8381 __le16 cmpl_ring; 8382 __le16 seq_id; 8383 __le16 target_id; 8384 __le64 resp_addr; 8385 __le32 flags; 8386 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL 8387 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL 8388 __le16 unused_0; 8389 __le16 op; 8390 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL 8391 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL 8392 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL 8393 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL 8394 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP 8395 }; 8396 8397 /* hwrm_cfa_eem_op_output (size:128b/16B) */ 8398 struct hwrm_cfa_eem_op_output { 8399 __le16 error_code; 8400 __le16 req_type; 8401 __le16 seq_id; 8402 __le16 resp_len; 8403 u8 unused_0[7]; 8404 u8 valid; 8405 }; 8406 8407 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ 8408 struct hwrm_cfa_adv_flow_mgnt_qcaps_input { 8409 __le16 req_type; 8410 __le16 cmpl_ring; 8411 __le16 seq_id; 8412 __le16 target_id; 8413 __le64 resp_addr; 8414 __le32 unused_0[4]; 8415 }; 8416 8417 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ 8418 struct hwrm_cfa_adv_flow_mgnt_qcaps_output { 8419 __le16 error_code; 8420 __le16 req_type; 8421 __le16 seq_id; 8422 __le16 resp_len; 8423 __le32 flags; 8424 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL 8425 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL 8426 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL 8427 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL 8428 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL 8429 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL 8430 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL 8431 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL 8432 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL 8433 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL 8434 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL 8435 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL 8436 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL 8437 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL 8438 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL 8439 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TRUFLOW_CAPABLE 0x8000UL 8440 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED 0x10000UL 8441 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_LAG_SUPPORTED 0x20000UL 8442 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED 0x40000UL 8443 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NIC_FLOW_STATS_SUPPORTED 0x80000UL 8444 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED 0x100000UL 8445 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V3_SUPPORTED 0x200000UL 8446 u8 unused_0[3]; 8447 u8 valid; 8448 }; 8449 8450 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 8451 struct hwrm_tunnel_dst_port_query_input { 8452 __le16 req_type; 8453 __le16 cmpl_ring; 8454 __le16 seq_id; 8455 __le16 target_id; 8456 __le64 resp_addr; 8457 u8 tunnel_type; 8458 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8459 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8460 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8461 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8462 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8463 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8464 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL 8465 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ECPRI 0xeUL 8466 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_SRV6 0xfUL 8467 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8468 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GRE 0x11UL 8469 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GRE 8470 u8 tunnel_next_proto; 8471 u8 unused_0[6]; 8472 }; 8473 8474 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 8475 struct hwrm_tunnel_dst_port_query_output { 8476 __le16 error_code; 8477 __le16 req_type; 8478 __le16 seq_id; 8479 __le16 resp_len; 8480 __le16 tunnel_dst_port_id; 8481 __be16 tunnel_dst_port_val; 8482 u8 upar_in_use; 8483 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR0 0x1UL 8484 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR1 0x2UL 8485 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR2 0x4UL 8486 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR3 0x8UL 8487 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR4 0x10UL 8488 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR5 0x20UL 8489 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR6 0x40UL 8490 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR7 0x80UL 8491 u8 status; 8492 #define TUNNEL_DST_PORT_QUERY_RESP_STATUS_CHIP_LEVEL 0x1UL 8493 #define TUNNEL_DST_PORT_QUERY_RESP_STATUS_FUNC_LEVEL 0x2UL 8494 u8 unused_0; 8495 u8 valid; 8496 }; 8497 8498 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 8499 struct hwrm_tunnel_dst_port_alloc_input { 8500 __le16 req_type; 8501 __le16 cmpl_ring; 8502 __le16 seq_id; 8503 __le16 target_id; 8504 __le64 resp_addr; 8505 u8 tunnel_type; 8506 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8507 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8508 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8509 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8510 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8511 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8512 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL 8513 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ECPRI 0xeUL 8514 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_SRV6 0xfUL 8515 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8516 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GRE 0x11UL 8517 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GRE 8518 u8 tunnel_next_proto; 8519 __be16 tunnel_dst_port_val; 8520 u8 unused_0[4]; 8521 }; 8522 8523 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 8524 struct hwrm_tunnel_dst_port_alloc_output { 8525 __le16 error_code; 8526 __le16 req_type; 8527 __le16 seq_id; 8528 __le16 resp_len; 8529 __le16 tunnel_dst_port_id; 8530 u8 error_info; 8531 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_SUCCESS 0x0UL 8532 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ALLOCATED 0x1UL 8533 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_NO_RESOURCE 0x2UL 8534 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ENABLED 0x3UL 8535 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_LAST TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ENABLED 8536 u8 upar_in_use; 8537 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR0 0x1UL 8538 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR1 0x2UL 8539 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR2 0x4UL 8540 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR3 0x8UL 8541 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR4 0x10UL 8542 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR5 0x20UL 8543 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR6 0x40UL 8544 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR7 0x80UL 8545 u8 unused_0[3]; 8546 u8 valid; 8547 }; 8548 8549 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 8550 struct hwrm_tunnel_dst_port_free_input { 8551 __le16 req_type; 8552 __le16 cmpl_ring; 8553 __le16 seq_id; 8554 __le16 target_id; 8555 __le64 resp_addr; 8556 u8 tunnel_type; 8557 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8558 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8559 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8560 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8561 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8562 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8563 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL 8564 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ECPRI 0xeUL 8565 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_SRV6 0xfUL 8566 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8567 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GRE 0x11UL 8568 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GRE 8569 u8 tunnel_next_proto; 8570 __le16 tunnel_dst_port_id; 8571 u8 unused_0[4]; 8572 }; 8573 8574 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 8575 struct hwrm_tunnel_dst_port_free_output { 8576 __le16 error_code; 8577 __le16 req_type; 8578 __le16 seq_id; 8579 __le16 resp_len; 8580 u8 error_info; 8581 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_SUCCESS 0x0UL 8582 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_OWNER 0x1UL 8583 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED 0x2UL 8584 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_LAST TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED 8585 u8 unused_1[6]; 8586 u8 valid; 8587 }; 8588 8589 /* ctx_hw_stats (size:1280b/160B) */ 8590 struct ctx_hw_stats { 8591 __le64 rx_ucast_pkts; 8592 __le64 rx_mcast_pkts; 8593 __le64 rx_bcast_pkts; 8594 __le64 rx_discard_pkts; 8595 __le64 rx_error_pkts; 8596 __le64 rx_ucast_bytes; 8597 __le64 rx_mcast_bytes; 8598 __le64 rx_bcast_bytes; 8599 __le64 tx_ucast_pkts; 8600 __le64 tx_mcast_pkts; 8601 __le64 tx_bcast_pkts; 8602 __le64 tx_error_pkts; 8603 __le64 tx_discard_pkts; 8604 __le64 tx_ucast_bytes; 8605 __le64 tx_mcast_bytes; 8606 __le64 tx_bcast_bytes; 8607 __le64 tpa_pkts; 8608 __le64 tpa_bytes; 8609 __le64 tpa_events; 8610 __le64 tpa_aborts; 8611 }; 8612 8613 /* ctx_hw_stats_ext (size:1408b/176B) */ 8614 struct ctx_hw_stats_ext { 8615 __le64 rx_ucast_pkts; 8616 __le64 rx_mcast_pkts; 8617 __le64 rx_bcast_pkts; 8618 __le64 rx_discard_pkts; 8619 __le64 rx_error_pkts; 8620 __le64 rx_ucast_bytes; 8621 __le64 rx_mcast_bytes; 8622 __le64 rx_bcast_bytes; 8623 __le64 tx_ucast_pkts; 8624 __le64 tx_mcast_pkts; 8625 __le64 tx_bcast_pkts; 8626 __le64 tx_error_pkts; 8627 __le64 tx_discard_pkts; 8628 __le64 tx_ucast_bytes; 8629 __le64 tx_mcast_bytes; 8630 __le64 tx_bcast_bytes; 8631 __le64 rx_tpa_eligible_pkt; 8632 __le64 rx_tpa_eligible_bytes; 8633 __le64 rx_tpa_pkt; 8634 __le64 rx_tpa_bytes; 8635 __le64 rx_tpa_errors; 8636 __le64 rx_tpa_events; 8637 }; 8638 8639 /* hwrm_stat_ctx_alloc_input (size:320b/40B) */ 8640 struct hwrm_stat_ctx_alloc_input { 8641 __le16 req_type; 8642 __le16 cmpl_ring; 8643 __le16 seq_id; 8644 __le16 target_id; 8645 __le64 resp_addr; 8646 __le64 stats_dma_addr; 8647 __le32 update_period_ms; 8648 u8 stat_ctx_flags; 8649 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 8650 u8 unused_0; 8651 __le16 stats_dma_length; 8652 __le16 flags; 8653 #define STAT_CTX_ALLOC_REQ_FLAGS_STEERING_TAG_VALID 0x1UL 8654 __le16 steering_tag; 8655 __le32 unused_1; 8656 }; 8657 8658 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 8659 struct hwrm_stat_ctx_alloc_output { 8660 __le16 error_code; 8661 __le16 req_type; 8662 __le16 seq_id; 8663 __le16 resp_len; 8664 __le32 stat_ctx_id; 8665 u8 unused_0[3]; 8666 u8 valid; 8667 }; 8668 8669 /* hwrm_stat_ctx_free_input (size:192b/24B) */ 8670 struct hwrm_stat_ctx_free_input { 8671 __le16 req_type; 8672 __le16 cmpl_ring; 8673 __le16 seq_id; 8674 __le16 target_id; 8675 __le64 resp_addr; 8676 __le32 stat_ctx_id; 8677 u8 unused_0[4]; 8678 }; 8679 8680 /* hwrm_stat_ctx_free_output (size:128b/16B) */ 8681 struct hwrm_stat_ctx_free_output { 8682 __le16 error_code; 8683 __le16 req_type; 8684 __le16 seq_id; 8685 __le16 resp_len; 8686 __le32 stat_ctx_id; 8687 u8 unused_0[3]; 8688 u8 valid; 8689 }; 8690 8691 /* hwrm_stat_ctx_query_input (size:192b/24B) */ 8692 struct hwrm_stat_ctx_query_input { 8693 __le16 req_type; 8694 __le16 cmpl_ring; 8695 __le16 seq_id; 8696 __le16 target_id; 8697 __le64 resp_addr; 8698 __le32 stat_ctx_id; 8699 u8 flags; 8700 #define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 8701 u8 unused_0[3]; 8702 }; 8703 8704 /* hwrm_stat_ctx_query_output (size:1408b/176B) */ 8705 struct hwrm_stat_ctx_query_output { 8706 __le16 error_code; 8707 __le16 req_type; 8708 __le16 seq_id; 8709 __le16 resp_len; 8710 __le64 tx_ucast_pkts; 8711 __le64 tx_mcast_pkts; 8712 __le64 tx_bcast_pkts; 8713 __le64 tx_discard_pkts; 8714 __le64 tx_error_pkts; 8715 __le64 tx_ucast_bytes; 8716 __le64 tx_mcast_bytes; 8717 __le64 tx_bcast_bytes; 8718 __le64 rx_ucast_pkts; 8719 __le64 rx_mcast_pkts; 8720 __le64 rx_bcast_pkts; 8721 __le64 rx_discard_pkts; 8722 __le64 rx_error_pkts; 8723 __le64 rx_ucast_bytes; 8724 __le64 rx_mcast_bytes; 8725 __le64 rx_bcast_bytes; 8726 __le64 rx_agg_pkts; 8727 __le64 rx_agg_bytes; 8728 __le64 rx_agg_events; 8729 __le64 rx_agg_aborts; 8730 u8 unused_0[7]; 8731 u8 valid; 8732 }; 8733 8734 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ 8735 struct hwrm_stat_ext_ctx_query_input { 8736 __le16 req_type; 8737 __le16 cmpl_ring; 8738 __le16 seq_id; 8739 __le16 target_id; 8740 __le64 resp_addr; 8741 __le32 stat_ctx_id; 8742 u8 flags; 8743 #define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 8744 u8 unused_0[3]; 8745 }; 8746 8747 /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */ 8748 struct hwrm_stat_ext_ctx_query_output { 8749 __le16 error_code; 8750 __le16 req_type; 8751 __le16 seq_id; 8752 __le16 resp_len; 8753 __le64 rx_ucast_pkts; 8754 __le64 rx_mcast_pkts; 8755 __le64 rx_bcast_pkts; 8756 __le64 rx_discard_pkts; 8757 __le64 rx_error_pkts; 8758 __le64 rx_ucast_bytes; 8759 __le64 rx_mcast_bytes; 8760 __le64 rx_bcast_bytes; 8761 __le64 tx_ucast_pkts; 8762 __le64 tx_mcast_pkts; 8763 __le64 tx_bcast_pkts; 8764 __le64 tx_error_pkts; 8765 __le64 tx_discard_pkts; 8766 __le64 tx_ucast_bytes; 8767 __le64 tx_mcast_bytes; 8768 __le64 tx_bcast_bytes; 8769 __le64 rx_tpa_eligible_pkt; 8770 __le64 rx_tpa_eligible_bytes; 8771 __le64 rx_tpa_pkt; 8772 __le64 rx_tpa_bytes; 8773 __le64 rx_tpa_errors; 8774 __le64 rx_tpa_events; 8775 u8 unused_0[7]; 8776 u8 valid; 8777 }; 8778 8779 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 8780 struct hwrm_stat_ctx_clr_stats_input { 8781 __le16 req_type; 8782 __le16 cmpl_ring; 8783 __le16 seq_id; 8784 __le16 target_id; 8785 __le64 resp_addr; 8786 __le32 stat_ctx_id; 8787 u8 unused_0[4]; 8788 }; 8789 8790 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 8791 struct hwrm_stat_ctx_clr_stats_output { 8792 __le16 error_code; 8793 __le16 req_type; 8794 __le16 seq_id; 8795 __le16 resp_len; 8796 u8 unused_0[7]; 8797 u8 valid; 8798 }; 8799 8800 /* hwrm_pcie_qstats_input (size:256b/32B) */ 8801 struct hwrm_pcie_qstats_input { 8802 __le16 req_type; 8803 __le16 cmpl_ring; 8804 __le16 seq_id; 8805 __le16 target_id; 8806 __le64 resp_addr; 8807 __le16 pcie_stat_size; 8808 u8 unused_0[6]; 8809 __le64 pcie_stat_host_addr; 8810 }; 8811 8812 /* hwrm_pcie_qstats_output (size:128b/16B) */ 8813 struct hwrm_pcie_qstats_output { 8814 __le16 error_code; 8815 __le16 req_type; 8816 __le16 seq_id; 8817 __le16 resp_len; 8818 __le16 pcie_stat_size; 8819 u8 unused_0[5]; 8820 u8 valid; 8821 }; 8822 8823 /* pcie_ctx_hw_stats (size:768b/96B) */ 8824 struct pcie_ctx_hw_stats { 8825 __le64 pcie_pl_signal_integrity; 8826 __le64 pcie_dl_signal_integrity; 8827 __le64 pcie_tl_signal_integrity; 8828 __le64 pcie_link_integrity; 8829 __le64 pcie_tx_traffic_rate; 8830 __le64 pcie_rx_traffic_rate; 8831 __le64 pcie_tx_dllp_statistics; 8832 __le64 pcie_rx_dllp_statistics; 8833 __le64 pcie_equalization_time; 8834 __le32 pcie_ltssm_histogram[4]; 8835 __le64 pcie_recovery_histogram; 8836 }; 8837 8838 /* hwrm_stat_generic_qstats_input (size:256b/32B) */ 8839 struct hwrm_stat_generic_qstats_input { 8840 __le16 req_type; 8841 __le16 cmpl_ring; 8842 __le16 seq_id; 8843 __le16 target_id; 8844 __le64 resp_addr; 8845 __le16 generic_stat_size; 8846 u8 flags; 8847 #define STAT_GENERIC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 8848 u8 unused_0[5]; 8849 __le64 generic_stat_host_addr; 8850 }; 8851 8852 /* hwrm_stat_generic_qstats_output (size:128b/16B) */ 8853 struct hwrm_stat_generic_qstats_output { 8854 __le16 error_code; 8855 __le16 req_type; 8856 __le16 seq_id; 8857 __le16 resp_len; 8858 __le16 generic_stat_size; 8859 u8 unused_0[5]; 8860 u8 valid; 8861 }; 8862 8863 /* generic_sw_hw_stats (size:1408b/176B) */ 8864 struct generic_sw_hw_stats { 8865 __le64 pcie_statistics_tx_tlp; 8866 __le64 pcie_statistics_rx_tlp; 8867 __le64 pcie_credit_fc_hdr_posted; 8868 __le64 pcie_credit_fc_hdr_nonposted; 8869 __le64 pcie_credit_fc_hdr_cmpl; 8870 __le64 pcie_credit_fc_data_posted; 8871 __le64 pcie_credit_fc_data_nonposted; 8872 __le64 pcie_credit_fc_data_cmpl; 8873 __le64 pcie_credit_fc_tgt_nonposted; 8874 __le64 pcie_credit_fc_tgt_data_posted; 8875 __le64 pcie_credit_fc_tgt_hdr_posted; 8876 __le64 pcie_credit_fc_cmpl_hdr_posted; 8877 __le64 pcie_credit_fc_cmpl_data_posted; 8878 __le64 pcie_cmpl_longest; 8879 __le64 pcie_cmpl_shortest; 8880 __le64 cache_miss_count_cfcq; 8881 __le64 cache_miss_count_cfcs; 8882 __le64 cache_miss_count_cfcc; 8883 __le64 cache_miss_count_cfcm; 8884 __le64 hw_db_recov_dbs_dropped; 8885 __le64 hw_db_recov_drops_serviced; 8886 __le64 hw_db_recov_dbs_recovered; 8887 }; 8888 8889 /* hwrm_fw_reset_input (size:192b/24B) */ 8890 struct hwrm_fw_reset_input { 8891 __le16 req_type; 8892 __le16 cmpl_ring; 8893 __le16 seq_id; 8894 __le16 target_id; 8895 __le64 resp_addr; 8896 u8 embedded_proc_type; 8897 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 8898 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 8899 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 8900 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 8901 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 8902 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 8903 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 8904 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 8905 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL 8906 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 8907 u8 selfrst_status; 8908 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 8909 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 8910 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 8911 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 8912 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 8913 u8 host_idx; 8914 u8 flags; 8915 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL 8916 #define FW_RESET_REQ_FLAGS_FW_ACTIVATION 0x2UL 8917 u8 unused_0[4]; 8918 }; 8919 8920 /* hwrm_fw_reset_output (size:128b/16B) */ 8921 struct hwrm_fw_reset_output { 8922 __le16 error_code; 8923 __le16 req_type; 8924 __le16 seq_id; 8925 __le16 resp_len; 8926 u8 selfrst_status; 8927 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 8928 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 8929 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 8930 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 8931 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 8932 u8 unused_0[6]; 8933 u8 valid; 8934 }; 8935 8936 /* hwrm_fw_qstatus_input (size:192b/24B) */ 8937 struct hwrm_fw_qstatus_input { 8938 __le16 req_type; 8939 __le16 cmpl_ring; 8940 __le16 seq_id; 8941 __le16 target_id; 8942 __le64 resp_addr; 8943 u8 embedded_proc_type; 8944 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 8945 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 8946 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 8947 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 8948 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 8949 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 8950 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 8951 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 8952 u8 unused_0[7]; 8953 }; 8954 8955 /* hwrm_fw_qstatus_output (size:128b/16B) */ 8956 struct hwrm_fw_qstatus_output { 8957 __le16 error_code; 8958 __le16 req_type; 8959 __le16 seq_id; 8960 __le16 resp_len; 8961 u8 selfrst_status; 8962 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 8963 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 8964 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 8965 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL 8966 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 8967 u8 nvm_option_action_status; 8968 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_NONE 0x0UL 8969 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_HOTRESET 0x1UL 8970 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_WARMBOOT 0x2UL 8971 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 0x3UL 8972 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_LAST FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 8973 u8 unused_0[5]; 8974 u8 valid; 8975 }; 8976 8977 /* hwrm_fw_set_time_input (size:256b/32B) */ 8978 struct hwrm_fw_set_time_input { 8979 __le16 req_type; 8980 __le16 cmpl_ring; 8981 __le16 seq_id; 8982 __le16 target_id; 8983 __le64 resp_addr; 8984 __le16 year; 8985 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 8986 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 8987 u8 month; 8988 u8 day; 8989 u8 hour; 8990 u8 minute; 8991 u8 second; 8992 u8 unused_0; 8993 __le16 millisecond; 8994 __le16 zone; 8995 #define FW_SET_TIME_REQ_ZONE_UTC 0 8996 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535 8997 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 8998 u8 unused_1[4]; 8999 }; 9000 9001 /* hwrm_fw_set_time_output (size:128b/16B) */ 9002 struct hwrm_fw_set_time_output { 9003 __le16 error_code; 9004 __le16 req_type; 9005 __le16 seq_id; 9006 __le16 resp_len; 9007 u8 unused_0[7]; 9008 u8 valid; 9009 }; 9010 9011 /* hwrm_struct_hdr (size:128b/16B) */ 9012 struct hwrm_struct_hdr { 9013 __le16 struct_id; 9014 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 9015 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 9016 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 9017 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 9018 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 9019 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 9020 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 9021 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL 9022 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 9023 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 9024 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 9025 #define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL 9026 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 9027 __le16 len; 9028 u8 version; 9029 u8 count; 9030 __le16 subtype; 9031 __le16 next_offset; 9032 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 9033 u8 unused_0[6]; 9034 }; 9035 9036 /* hwrm_struct_data_dcbx_app (size:64b/8B) */ 9037 struct hwrm_struct_data_dcbx_app { 9038 __be16 protocol_id; 9039 u8 protocol_selector; 9040 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 9041 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 9042 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 9043 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 9044 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 9045 u8 priority; 9046 u8 valid; 9047 u8 unused_0[3]; 9048 }; 9049 9050 /* hwrm_fw_set_structured_data_input (size:256b/32B) */ 9051 struct hwrm_fw_set_structured_data_input { 9052 __le16 req_type; 9053 __le16 cmpl_ring; 9054 __le16 seq_id; 9055 __le16 target_id; 9056 __le64 resp_addr; 9057 __le64 src_data_addr; 9058 __le16 data_len; 9059 u8 hdr_cnt; 9060 u8 unused_0[5]; 9061 }; 9062 9063 /* hwrm_fw_set_structured_data_output (size:128b/16B) */ 9064 struct hwrm_fw_set_structured_data_output { 9065 __le16 error_code; 9066 __le16 req_type; 9067 __le16 seq_id; 9068 __le16 resp_len; 9069 u8 unused_0[7]; 9070 u8 valid; 9071 }; 9072 9073 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 9074 struct hwrm_fw_set_structured_data_cmd_err { 9075 u8 code; 9076 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 9077 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 9078 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 9079 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 9080 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 9081 u8 unused_0[7]; 9082 }; 9083 9084 /* hwrm_fw_get_structured_data_input (size:256b/32B) */ 9085 struct hwrm_fw_get_structured_data_input { 9086 __le16 req_type; 9087 __le16 cmpl_ring; 9088 __le16 seq_id; 9089 __le16 target_id; 9090 __le64 resp_addr; 9091 __le64 dest_data_addr; 9092 __le16 data_len; 9093 __le16 structure_id; 9094 __le16 subtype; 9095 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 9096 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 9097 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 9098 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 9099 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 9100 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 9101 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 9102 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 9103 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 9104 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 9105 u8 count; 9106 u8 unused_0; 9107 }; 9108 9109 /* hwrm_fw_get_structured_data_output (size:128b/16B) */ 9110 struct hwrm_fw_get_structured_data_output { 9111 __le16 error_code; 9112 __le16 req_type; 9113 __le16 seq_id; 9114 __le16 resp_len; 9115 u8 hdr_cnt; 9116 u8 unused_0[6]; 9117 u8 valid; 9118 }; 9119 9120 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 9121 struct hwrm_fw_get_structured_data_cmd_err { 9122 u8 code; 9123 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 9124 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 9125 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 9126 u8 unused_0[7]; 9127 }; 9128 9129 /* hwrm_fw_livepatch_query_input (size:192b/24B) */ 9130 struct hwrm_fw_livepatch_query_input { 9131 __le16 req_type; 9132 __le16 cmpl_ring; 9133 __le16 seq_id; 9134 __le16 target_id; 9135 __le64 resp_addr; 9136 u8 fw_target; 9137 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_COMMON_FW 0x1UL 9138 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 0x2UL 9139 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_LAST FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 9140 u8 unused_0[7]; 9141 }; 9142 9143 /* hwrm_fw_livepatch_query_output (size:640b/80B) */ 9144 struct hwrm_fw_livepatch_query_output { 9145 __le16 error_code; 9146 __le16 req_type; 9147 __le16 seq_id; 9148 __le16 resp_len; 9149 char install_ver[32]; 9150 char active_ver[32]; 9151 __le16 status_flags; 9152 #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_INSTALL 0x1UL 9153 #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_ACTIVE 0x2UL 9154 u8 unused_0[5]; 9155 u8 valid; 9156 }; 9157 9158 /* hwrm_fw_livepatch_input (size:256b/32B) */ 9159 struct hwrm_fw_livepatch_input { 9160 __le16 req_type; 9161 __le16 cmpl_ring; 9162 __le16 seq_id; 9163 __le16 target_id; 9164 __le64 resp_addr; 9165 u8 opcode; 9166 #define FW_LIVEPATCH_REQ_OPCODE_ACTIVATE 0x1UL 9167 #define FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 0x2UL 9168 #define FW_LIVEPATCH_REQ_OPCODE_LAST FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 9169 u8 fw_target; 9170 #define FW_LIVEPATCH_REQ_FW_TARGET_COMMON_FW 0x1UL 9171 #define FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 0x2UL 9172 #define FW_LIVEPATCH_REQ_FW_TARGET_LAST FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 9173 u8 loadtype; 9174 #define FW_LIVEPATCH_REQ_LOADTYPE_NVM_INSTALL 0x1UL 9175 #define FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 0x2UL 9176 #define FW_LIVEPATCH_REQ_LOADTYPE_LAST FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 9177 u8 flags; 9178 __le32 patch_len; 9179 __le64 host_addr; 9180 }; 9181 9182 /* hwrm_fw_livepatch_output (size:128b/16B) */ 9183 struct hwrm_fw_livepatch_output { 9184 __le16 error_code; 9185 __le16 req_type; 9186 __le16 seq_id; 9187 __le16 resp_len; 9188 u8 unused_0[7]; 9189 u8 valid; 9190 }; 9191 9192 /* hwrm_fw_livepatch_cmd_err (size:64b/8B) */ 9193 struct hwrm_fw_livepatch_cmd_err { 9194 u8 code; 9195 #define FW_LIVEPATCH_CMD_ERR_CODE_UNKNOWN 0x0UL 9196 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_OPCODE 0x1UL 9197 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_TARGET 0x2UL 9198 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_SUPPORTED 0x3UL 9199 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_INSTALLED 0x4UL 9200 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_PATCHED 0x5UL 9201 #define FW_LIVEPATCH_CMD_ERR_CODE_AUTH_FAIL 0x6UL 9202 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_HEADER 0x7UL 9203 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_SIZE 0x8UL 9204 #define FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 0x9UL 9205 #define FW_LIVEPATCH_CMD_ERR_CODE_LAST FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 9206 u8 unused_0[7]; 9207 }; 9208 9209 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 9210 struct hwrm_exec_fwd_resp_input { 9211 __le16 req_type; 9212 __le16 cmpl_ring; 9213 __le16 seq_id; 9214 __le16 target_id; 9215 __le64 resp_addr; 9216 __le32 encap_request[26]; 9217 __le16 encap_resp_target_id; 9218 u8 unused_0[6]; 9219 }; 9220 9221 /* hwrm_exec_fwd_resp_output (size:128b/16B) */ 9222 struct hwrm_exec_fwd_resp_output { 9223 __le16 error_code; 9224 __le16 req_type; 9225 __le16 seq_id; 9226 __le16 resp_len; 9227 u8 unused_0[7]; 9228 u8 valid; 9229 }; 9230 9231 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 9232 struct hwrm_reject_fwd_resp_input { 9233 __le16 req_type; 9234 __le16 cmpl_ring; 9235 __le16 seq_id; 9236 __le16 target_id; 9237 __le64 resp_addr; 9238 __le32 encap_request[26]; 9239 __le16 encap_resp_target_id; 9240 u8 unused_0[6]; 9241 }; 9242 9243 /* hwrm_reject_fwd_resp_output (size:128b/16B) */ 9244 struct hwrm_reject_fwd_resp_output { 9245 __le16 error_code; 9246 __le16 req_type; 9247 __le16 seq_id; 9248 __le16 resp_len; 9249 u8 unused_0[7]; 9250 u8 valid; 9251 }; 9252 9253 /* hwrm_fwd_resp_input (size:1024b/128B) */ 9254 struct hwrm_fwd_resp_input { 9255 __le16 req_type; 9256 __le16 cmpl_ring; 9257 __le16 seq_id; 9258 __le16 target_id; 9259 __le64 resp_addr; 9260 __le16 encap_resp_target_id; 9261 __le16 encap_resp_cmpl_ring; 9262 __le16 encap_resp_len; 9263 u8 unused_0; 9264 u8 unused_1; 9265 __le64 encap_resp_addr; 9266 __le32 encap_resp[24]; 9267 }; 9268 9269 /* hwrm_fwd_resp_output (size:128b/16B) */ 9270 struct hwrm_fwd_resp_output { 9271 __le16 error_code; 9272 __le16 req_type; 9273 __le16 seq_id; 9274 __le16 resp_len; 9275 u8 unused_0[7]; 9276 u8 valid; 9277 }; 9278 9279 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 9280 struct hwrm_fwd_async_event_cmpl_input { 9281 __le16 req_type; 9282 __le16 cmpl_ring; 9283 __le16 seq_id; 9284 __le16 target_id; 9285 __le64 resp_addr; 9286 __le16 encap_async_event_target_id; 9287 u8 unused_0[6]; 9288 __le32 encap_async_event_cmpl[4]; 9289 }; 9290 9291 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 9292 struct hwrm_fwd_async_event_cmpl_output { 9293 __le16 error_code; 9294 __le16 req_type; 9295 __le16 seq_id; 9296 __le16 resp_len; 9297 u8 unused_0[7]; 9298 u8 valid; 9299 }; 9300 9301 /* hwrm_temp_monitor_query_input (size:128b/16B) */ 9302 struct hwrm_temp_monitor_query_input { 9303 __le16 req_type; 9304 __le16 cmpl_ring; 9305 __le16 seq_id; 9306 __le16 target_id; 9307 __le64 resp_addr; 9308 }; 9309 9310 /* hwrm_temp_monitor_query_output (size:192b/24B) */ 9311 struct hwrm_temp_monitor_query_output { 9312 __le16 error_code; 9313 __le16 req_type; 9314 __le16 seq_id; 9315 __le16 resp_len; 9316 u8 temp; 9317 u8 phy_temp; 9318 u8 om_temp; 9319 u8 flags; 9320 #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL 9321 #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL 9322 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL 9323 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL 9324 #define TEMP_MONITOR_QUERY_RESP_FLAGS_EXT_TEMP_FIELDS_AVAILABLE 0x10UL 9325 #define TEMP_MONITOR_QUERY_RESP_FLAGS_THRESHOLD_VALUES_AVAILABLE 0x20UL 9326 u8 temp2; 9327 u8 phy_temp2; 9328 u8 om_temp2; 9329 u8 warn_threshold; 9330 u8 critical_threshold; 9331 u8 fatal_threshold; 9332 u8 shutdown_threshold; 9333 u8 unused_0[4]; 9334 u8 valid; 9335 }; 9336 9337 /* hwrm_wol_filter_alloc_input (size:512b/64B) */ 9338 struct hwrm_wol_filter_alloc_input { 9339 __le16 req_type; 9340 __le16 cmpl_ring; 9341 __le16 seq_id; 9342 __le16 target_id; 9343 __le64 resp_addr; 9344 __le32 flags; 9345 __le32 enables; 9346 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 9347 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 9348 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 9349 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 9350 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 9351 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 9352 __le16 port_id; 9353 u8 wol_type; 9354 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 9355 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 9356 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 9357 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 9358 u8 unused_0[5]; 9359 u8 mac_address[6]; 9360 __le16 pattern_offset; 9361 __le16 pattern_buf_size; 9362 __le16 pattern_mask_size; 9363 u8 unused_1[4]; 9364 __le64 pattern_buf_addr; 9365 __le64 pattern_mask_addr; 9366 }; 9367 9368 /* hwrm_wol_filter_alloc_output (size:128b/16B) */ 9369 struct hwrm_wol_filter_alloc_output { 9370 __le16 error_code; 9371 __le16 req_type; 9372 __le16 seq_id; 9373 __le16 resp_len; 9374 u8 wol_filter_id; 9375 u8 unused_0[6]; 9376 u8 valid; 9377 }; 9378 9379 /* hwrm_wol_filter_free_input (size:256b/32B) */ 9380 struct hwrm_wol_filter_free_input { 9381 __le16 req_type; 9382 __le16 cmpl_ring; 9383 __le16 seq_id; 9384 __le16 target_id; 9385 __le64 resp_addr; 9386 __le32 flags; 9387 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 9388 __le32 enables; 9389 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 9390 __le16 port_id; 9391 u8 wol_filter_id; 9392 u8 unused_0[5]; 9393 }; 9394 9395 /* hwrm_wol_filter_free_output (size:128b/16B) */ 9396 struct hwrm_wol_filter_free_output { 9397 __le16 error_code; 9398 __le16 req_type; 9399 __le16 seq_id; 9400 __le16 resp_len; 9401 u8 unused_0[7]; 9402 u8 valid; 9403 }; 9404 9405 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 9406 struct hwrm_wol_filter_qcfg_input { 9407 __le16 req_type; 9408 __le16 cmpl_ring; 9409 __le16 seq_id; 9410 __le16 target_id; 9411 __le64 resp_addr; 9412 __le16 port_id; 9413 __le16 handle; 9414 u8 unused_0[4]; 9415 __le64 pattern_buf_addr; 9416 __le16 pattern_buf_size; 9417 u8 unused_1[6]; 9418 __le64 pattern_mask_addr; 9419 __le16 pattern_mask_size; 9420 u8 unused_2[6]; 9421 }; 9422 9423 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 9424 struct hwrm_wol_filter_qcfg_output { 9425 __le16 error_code; 9426 __le16 req_type; 9427 __le16 seq_id; 9428 __le16 resp_len; 9429 __le16 next_handle; 9430 u8 wol_filter_id; 9431 u8 wol_type; 9432 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 9433 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 9434 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 9435 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 9436 __le32 unused_0; 9437 u8 mac_address[6]; 9438 __le16 pattern_offset; 9439 __le16 pattern_size; 9440 __le16 pattern_mask_size; 9441 u8 unused_1[3]; 9442 u8 valid; 9443 }; 9444 9445 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 9446 struct hwrm_wol_reason_qcfg_input { 9447 __le16 req_type; 9448 __le16 cmpl_ring; 9449 __le16 seq_id; 9450 __le16 target_id; 9451 __le64 resp_addr; 9452 __le16 port_id; 9453 u8 unused_0[6]; 9454 __le64 wol_pkt_buf_addr; 9455 __le16 wol_pkt_buf_size; 9456 u8 unused_1[6]; 9457 }; 9458 9459 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 9460 struct hwrm_wol_reason_qcfg_output { 9461 __le16 error_code; 9462 __le16 req_type; 9463 __le16 seq_id; 9464 __le16 resp_len; 9465 u8 wol_filter_id; 9466 u8 wol_reason; 9467 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 9468 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 9469 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 9470 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 9471 u8 wol_pkt_len; 9472 u8 unused_0[4]; 9473 u8 valid; 9474 }; 9475 9476 /* hwrm_dbg_read_direct_input (size:256b/32B) */ 9477 struct hwrm_dbg_read_direct_input { 9478 __le16 req_type; 9479 __le16 cmpl_ring; 9480 __le16 seq_id; 9481 __le16 target_id; 9482 __le64 resp_addr; 9483 __le64 host_dest_addr; 9484 __le32 read_addr; 9485 __le32 read_len32; 9486 }; 9487 9488 /* hwrm_dbg_read_direct_output (size:128b/16B) */ 9489 struct hwrm_dbg_read_direct_output { 9490 __le16 error_code; 9491 __le16 req_type; 9492 __le16 seq_id; 9493 __le16 resp_len; 9494 __le32 crc32; 9495 u8 unused_0[3]; 9496 u8 valid; 9497 }; 9498 9499 /* hwrm_dbg_qcaps_input (size:192b/24B) */ 9500 struct hwrm_dbg_qcaps_input { 9501 __le16 req_type; 9502 __le16 cmpl_ring; 9503 __le16 seq_id; 9504 __le16 target_id; 9505 __le64 resp_addr; 9506 __le16 fid; 9507 u8 unused_0[6]; 9508 }; 9509 9510 /* hwrm_dbg_qcaps_output (size:192b/24B) */ 9511 struct hwrm_dbg_qcaps_output { 9512 __le16 error_code; 9513 __le16 req_type; 9514 __le16 seq_id; 9515 __le16 resp_len; 9516 __le16 fid; 9517 u8 unused_0[2]; 9518 __le32 coredump_component_disable_caps; 9519 #define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM 0x1UL 9520 __le32 flags; 9521 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL 9522 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL 9523 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL 9524 #define DBG_QCAPS_RESP_FLAGS_USEQ 0x8UL 9525 u8 unused_1[3]; 9526 u8 valid; 9527 }; 9528 9529 /* hwrm_dbg_qcfg_input (size:192b/24B) */ 9530 struct hwrm_dbg_qcfg_input { 9531 __le16 req_type; 9532 __le16 cmpl_ring; 9533 __le16 seq_id; 9534 __le16 target_id; 9535 __le64 resp_addr; 9536 __le16 fid; 9537 __le16 flags; 9538 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK 0x3UL 9539 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0 9540 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM 0x0UL 9541 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR 0x1UL 9542 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 0x2UL 9543 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 9544 __le32 coredump_component_disable_flags; 9545 #define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM 0x1UL 9546 }; 9547 9548 /* hwrm_dbg_qcfg_output (size:256b/32B) */ 9549 struct hwrm_dbg_qcfg_output { 9550 __le16 error_code; 9551 __le16 req_type; 9552 __le16 seq_id; 9553 __le16 resp_len; 9554 __le16 fid; 9555 u8 unused_0[2]; 9556 __le32 coredump_size; 9557 __le32 flags; 9558 #define DBG_QCFG_RESP_FLAGS_UART_LOG 0x1UL 9559 #define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY 0x2UL 9560 #define DBG_QCFG_RESP_FLAGS_FW_TRACE 0x4UL 9561 #define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY 0x8UL 9562 #define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY 0x10UL 9563 #define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG 0x20UL 9564 __le16 async_cmpl_ring; 9565 u8 unused_2[2]; 9566 __le32 crashdump_size; 9567 u8 unused_3[3]; 9568 u8 valid; 9569 }; 9570 9571 /* hwrm_dbg_crashdump_medium_cfg_input (size:320b/40B) */ 9572 struct hwrm_dbg_crashdump_medium_cfg_input { 9573 __le16 req_type; 9574 __le16 cmpl_ring; 9575 __le16 seq_id; 9576 __le16 target_id; 9577 __le64 resp_addr; 9578 __le16 output_dest_flags; 9579 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_TYPE_DDR 0x1UL 9580 __le16 pg_size_lvl; 9581 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_MASK 0x3UL 9582 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_SFT 0 9583 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_0 0x0UL 9584 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_1 0x1UL 9585 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2 0x2UL 9586 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2 9587 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_MASK 0x1cUL 9588 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_SFT 2 9589 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_4K (0x0UL << 2) 9590 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8K (0x1UL << 2) 9591 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_64K (0x2UL << 2) 9592 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_2M (0x3UL << 2) 9593 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8M (0x4UL << 2) 9594 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G (0x5UL << 2) 9595 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G 9596 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_MASK 0xffe0UL 9597 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_SFT 5 9598 __le32 size; 9599 __le32 coredump_component_disable_flags; 9600 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_NVRAM 0x1UL 9601 __le32 unused_0; 9602 __le64 pbl; 9603 }; 9604 9605 /* hwrm_dbg_crashdump_medium_cfg_output (size:128b/16B) */ 9606 struct hwrm_dbg_crashdump_medium_cfg_output { 9607 __le16 error_code; 9608 __le16 req_type; 9609 __le16 seq_id; 9610 __le16 resp_len; 9611 u8 unused_1[7]; 9612 u8 valid; 9613 }; 9614 9615 /* coredump_segment_record (size:128b/16B) */ 9616 struct coredump_segment_record { 9617 __le16 component_id; 9618 __le16 segment_id; 9619 __le16 max_instances; 9620 u8 version_hi; 9621 u8 version_low; 9622 u8 seg_flags; 9623 u8 compress_flags; 9624 #define SFLAG_COMPRESSED_ZLIB 0x1UL 9625 u8 unused_0[2]; 9626 __le32 segment_len; 9627 }; 9628 9629 /* hwrm_dbg_coredump_list_input (size:256b/32B) */ 9630 struct hwrm_dbg_coredump_list_input { 9631 __le16 req_type; 9632 __le16 cmpl_ring; 9633 __le16 seq_id; 9634 __le16 target_id; 9635 __le64 resp_addr; 9636 __le64 host_dest_addr; 9637 __le32 host_buf_len; 9638 __le16 seq_no; 9639 u8 flags; 9640 #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL 9641 u8 unused_0[1]; 9642 }; 9643 9644 /* hwrm_dbg_coredump_list_output (size:128b/16B) */ 9645 struct hwrm_dbg_coredump_list_output { 9646 __le16 error_code; 9647 __le16 req_type; 9648 __le16 seq_id; 9649 __le16 resp_len; 9650 u8 flags; 9651 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 9652 u8 unused_0; 9653 __le16 total_segments; 9654 __le16 data_len; 9655 u8 unused_1; 9656 u8 valid; 9657 }; 9658 9659 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 9660 struct hwrm_dbg_coredump_initiate_input { 9661 __le16 req_type; 9662 __le16 cmpl_ring; 9663 __le16 seq_id; 9664 __le16 target_id; 9665 __le64 resp_addr; 9666 __le16 component_id; 9667 __le16 segment_id; 9668 __le16 instance; 9669 __le16 unused_0; 9670 u8 seg_flags; 9671 u8 unused_1[7]; 9672 }; 9673 9674 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 9675 struct hwrm_dbg_coredump_initiate_output { 9676 __le16 error_code; 9677 __le16 req_type; 9678 __le16 seq_id; 9679 __le16 resp_len; 9680 u8 unused_0[7]; 9681 u8 valid; 9682 }; 9683 9684 /* coredump_data_hdr (size:128b/16B) */ 9685 struct coredump_data_hdr { 9686 __le32 address; 9687 __le32 flags_length; 9688 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK 0xffffffUL 9689 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT 0 9690 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS 0x1000000UL 9691 __le32 instance; 9692 __le32 next_offset; 9693 }; 9694 9695 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 9696 struct hwrm_dbg_coredump_retrieve_input { 9697 __le16 req_type; 9698 __le16 cmpl_ring; 9699 __le16 seq_id; 9700 __le16 target_id; 9701 __le64 resp_addr; 9702 __le64 host_dest_addr; 9703 __le32 host_buf_len; 9704 __le32 unused_0; 9705 __le16 component_id; 9706 __le16 segment_id; 9707 __le16 instance; 9708 __le16 unused_1; 9709 u8 seg_flags; 9710 u8 unused_2; 9711 __le16 unused_3; 9712 __le32 unused_4; 9713 __le32 seq_no; 9714 __le32 unused_5; 9715 }; 9716 9717 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 9718 struct hwrm_dbg_coredump_retrieve_output { 9719 __le16 error_code; 9720 __le16 req_type; 9721 __le16 seq_id; 9722 __le16 resp_len; 9723 u8 flags; 9724 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 9725 u8 unused_0; 9726 __le16 data_len; 9727 u8 unused_1[3]; 9728 u8 valid; 9729 }; 9730 9731 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 9732 struct hwrm_dbg_ring_info_get_input { 9733 __le16 req_type; 9734 __le16 cmpl_ring; 9735 __le16 seq_id; 9736 __le16 target_id; 9737 __le64 resp_addr; 9738 u8 ring_type; 9739 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 9740 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 9741 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 9742 #define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 0x3UL 9743 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 9744 u8 unused_0[3]; 9745 __le32 fw_ring_id; 9746 }; 9747 9748 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 9749 struct hwrm_dbg_ring_info_get_output { 9750 __le16 error_code; 9751 __le16 req_type; 9752 __le16 seq_id; 9753 __le16 resp_len; 9754 __le32 producer_index; 9755 __le32 consumer_index; 9756 __le32 cag_vector_ctrl; 9757 __le16 st_tag; 9758 u8 unused_0; 9759 u8 valid; 9760 }; 9761 9762 /* hwrm_nvm_read_input (size:320b/40B) */ 9763 struct hwrm_nvm_read_input { 9764 __le16 req_type; 9765 __le16 cmpl_ring; 9766 __le16 seq_id; 9767 __le16 target_id; 9768 __le64 resp_addr; 9769 __le64 host_dest_addr; 9770 __le16 dir_idx; 9771 u8 unused_0[2]; 9772 __le32 offset; 9773 __le32 len; 9774 u8 unused_1[4]; 9775 }; 9776 9777 /* hwrm_nvm_read_output (size:128b/16B) */ 9778 struct hwrm_nvm_read_output { 9779 __le16 error_code; 9780 __le16 req_type; 9781 __le16 seq_id; 9782 __le16 resp_len; 9783 u8 unused_0[7]; 9784 u8 valid; 9785 }; 9786 9787 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 9788 struct hwrm_nvm_get_dir_entries_input { 9789 __le16 req_type; 9790 __le16 cmpl_ring; 9791 __le16 seq_id; 9792 __le16 target_id; 9793 __le64 resp_addr; 9794 __le64 host_dest_addr; 9795 }; 9796 9797 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 9798 struct hwrm_nvm_get_dir_entries_output { 9799 __le16 error_code; 9800 __le16 req_type; 9801 __le16 seq_id; 9802 __le16 resp_len; 9803 u8 unused_0[7]; 9804 u8 valid; 9805 }; 9806 9807 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 9808 struct hwrm_nvm_get_dir_info_input { 9809 __le16 req_type; 9810 __le16 cmpl_ring; 9811 __le16 seq_id; 9812 __le16 target_id; 9813 __le64 resp_addr; 9814 }; 9815 9816 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 9817 struct hwrm_nvm_get_dir_info_output { 9818 __le16 error_code; 9819 __le16 req_type; 9820 __le16 seq_id; 9821 __le16 resp_len; 9822 __le32 entries; 9823 __le32 entry_length; 9824 u8 unused_0[7]; 9825 u8 valid; 9826 }; 9827 9828 /* hwrm_nvm_write_input (size:448b/56B) */ 9829 struct hwrm_nvm_write_input { 9830 __le16 req_type; 9831 __le16 cmpl_ring; 9832 __le16 seq_id; 9833 __le16 target_id; 9834 __le64 resp_addr; 9835 __le64 host_src_addr; 9836 __le16 dir_type; 9837 __le16 dir_ordinal; 9838 __le16 dir_ext; 9839 __le16 dir_attr; 9840 __le32 dir_data_length; 9841 __le16 option; 9842 __le16 flags; 9843 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 9844 #define NVM_WRITE_REQ_FLAGS_BATCH_MODE 0x2UL 9845 #define NVM_WRITE_REQ_FLAGS_BATCH_LAST 0x4UL 9846 __le32 dir_item_length; 9847 __le32 offset; 9848 __le32 len; 9849 __le32 unused_0; 9850 }; 9851 9852 /* hwrm_nvm_write_output (size:128b/16B) */ 9853 struct hwrm_nvm_write_output { 9854 __le16 error_code; 9855 __le16 req_type; 9856 __le16 seq_id; 9857 __le16 resp_len; 9858 __le32 dir_item_length; 9859 __le16 dir_idx; 9860 u8 unused_0; 9861 u8 valid; 9862 }; 9863 9864 /* hwrm_nvm_write_cmd_err (size:64b/8B) */ 9865 struct hwrm_nvm_write_cmd_err { 9866 u8 code; 9867 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 9868 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 9869 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 9870 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 9871 u8 unused_0[7]; 9872 }; 9873 9874 /* hwrm_nvm_modify_input (size:320b/40B) */ 9875 struct hwrm_nvm_modify_input { 9876 __le16 req_type; 9877 __le16 cmpl_ring; 9878 __le16 seq_id; 9879 __le16 target_id; 9880 __le64 resp_addr; 9881 __le64 host_src_addr; 9882 __le16 dir_idx; 9883 __le16 flags; 9884 #define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL 9885 #define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL 9886 __le32 offset; 9887 __le32 len; 9888 u8 unused_1[4]; 9889 }; 9890 9891 /* hwrm_nvm_modify_output (size:128b/16B) */ 9892 struct hwrm_nvm_modify_output { 9893 __le16 error_code; 9894 __le16 req_type; 9895 __le16 seq_id; 9896 __le16 resp_len; 9897 u8 unused_0[7]; 9898 u8 valid; 9899 }; 9900 9901 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 9902 struct hwrm_nvm_find_dir_entry_input { 9903 __le16 req_type; 9904 __le16 cmpl_ring; 9905 __le16 seq_id; 9906 __le16 target_id; 9907 __le64 resp_addr; 9908 __le32 enables; 9909 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 9910 __le16 dir_idx; 9911 __le16 dir_type; 9912 __le16 dir_ordinal; 9913 __le16 dir_ext; 9914 u8 opt_ordinal; 9915 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 9916 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 9917 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 9918 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 9919 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 9920 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 9921 u8 unused_0[3]; 9922 }; 9923 9924 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 9925 struct hwrm_nvm_find_dir_entry_output { 9926 __le16 error_code; 9927 __le16 req_type; 9928 __le16 seq_id; 9929 __le16 resp_len; 9930 __le32 dir_item_length; 9931 __le32 dir_data_length; 9932 __le32 fw_ver; 9933 __le16 dir_ordinal; 9934 __le16 dir_idx; 9935 u8 unused_0[7]; 9936 u8 valid; 9937 }; 9938 9939 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 9940 struct hwrm_nvm_erase_dir_entry_input { 9941 __le16 req_type; 9942 __le16 cmpl_ring; 9943 __le16 seq_id; 9944 __le16 target_id; 9945 __le64 resp_addr; 9946 __le16 dir_idx; 9947 u8 unused_0[6]; 9948 }; 9949 9950 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 9951 struct hwrm_nvm_erase_dir_entry_output { 9952 __le16 error_code; 9953 __le16 req_type; 9954 __le16 seq_id; 9955 __le16 resp_len; 9956 u8 unused_0[7]; 9957 u8 valid; 9958 }; 9959 9960 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 9961 struct hwrm_nvm_get_dev_info_input { 9962 __le16 req_type; 9963 __le16 cmpl_ring; 9964 __le16 seq_id; 9965 __le16 target_id; 9966 __le64 resp_addr; 9967 }; 9968 9969 /* hwrm_nvm_get_dev_info_output (size:704b/88B) */ 9970 struct hwrm_nvm_get_dev_info_output { 9971 __le16 error_code; 9972 __le16 req_type; 9973 __le16 seq_id; 9974 __le16 resp_len; 9975 __le16 manufacturer_id; 9976 __le16 device_id; 9977 __le32 sector_size; 9978 __le32 nvram_size; 9979 __le32 reserved_size; 9980 __le32 available_size; 9981 u8 nvm_cfg_ver_maj; 9982 u8 nvm_cfg_ver_min; 9983 u8 nvm_cfg_ver_upd; 9984 u8 flags; 9985 #define NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID 0x1UL 9986 char pkg_name[16]; 9987 __le16 hwrm_fw_major; 9988 __le16 hwrm_fw_minor; 9989 __le16 hwrm_fw_build; 9990 __le16 hwrm_fw_patch; 9991 __le16 mgmt_fw_major; 9992 __le16 mgmt_fw_minor; 9993 __le16 mgmt_fw_build; 9994 __le16 mgmt_fw_patch; 9995 __le16 roce_fw_major; 9996 __le16 roce_fw_minor; 9997 __le16 roce_fw_build; 9998 __le16 roce_fw_patch; 9999 __le16 netctrl_fw_major; 10000 __le16 netctrl_fw_minor; 10001 __le16 netctrl_fw_build; 10002 __le16 netctrl_fw_patch; 10003 u8 unused_0[7]; 10004 u8 valid; 10005 }; 10006 10007 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 10008 struct hwrm_nvm_mod_dir_entry_input { 10009 __le16 req_type; 10010 __le16 cmpl_ring; 10011 __le16 seq_id; 10012 __le16 target_id; 10013 __le64 resp_addr; 10014 __le32 enables; 10015 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 10016 __le16 dir_idx; 10017 __le16 dir_ordinal; 10018 __le16 dir_ext; 10019 __le16 dir_attr; 10020 __le32 checksum; 10021 }; 10022 10023 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 10024 struct hwrm_nvm_mod_dir_entry_output { 10025 __le16 error_code; 10026 __le16 req_type; 10027 __le16 seq_id; 10028 __le16 resp_len; 10029 u8 unused_0[7]; 10030 u8 valid; 10031 }; 10032 10033 /* hwrm_nvm_verify_update_input (size:192b/24B) */ 10034 struct hwrm_nvm_verify_update_input { 10035 __le16 req_type; 10036 __le16 cmpl_ring; 10037 __le16 seq_id; 10038 __le16 target_id; 10039 __le64 resp_addr; 10040 __le16 dir_type; 10041 __le16 dir_ordinal; 10042 __le16 dir_ext; 10043 u8 unused_0[2]; 10044 }; 10045 10046 /* hwrm_nvm_verify_update_output (size:128b/16B) */ 10047 struct hwrm_nvm_verify_update_output { 10048 __le16 error_code; 10049 __le16 req_type; 10050 __le16 seq_id; 10051 __le16 resp_len; 10052 u8 unused_0[7]; 10053 u8 valid; 10054 }; 10055 10056 /* hwrm_nvm_install_update_input (size:192b/24B) */ 10057 struct hwrm_nvm_install_update_input { 10058 __le16 req_type; 10059 __le16 cmpl_ring; 10060 __le16 seq_id; 10061 __le16 target_id; 10062 __le64 resp_addr; 10063 __le32 install_type; 10064 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 10065 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 10066 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 10067 __le16 flags; 10068 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 10069 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 10070 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 10071 #define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY 0x8UL 10072 u8 unused_0[2]; 10073 }; 10074 10075 /* hwrm_nvm_install_update_output (size:192b/24B) */ 10076 struct hwrm_nvm_install_update_output { 10077 __le16 error_code; 10078 __le16 req_type; 10079 __le16 seq_id; 10080 __le16 resp_len; 10081 __le64 installed_items; 10082 u8 result; 10083 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 10084 #define NVM_INSTALL_UPDATE_RESP_RESULT_FAILURE 0xffUL 10085 #define NVM_INSTALL_UPDATE_RESP_RESULT_MALLOC_FAILURE 0xfdUL 10086 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER 0xfbUL 10087 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER 0xf3UL 10088 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE 0xf2UL 10089 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER 0xecUL 10090 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE 0xebUL 10091 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM 0xeaUL 10092 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH 0xe9UL 10093 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST 0xe8UL 10094 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER 0xe7UL 10095 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM 0xe6UL 10096 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM 0xe5UL 10097 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH 0xe4UL 10098 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE 0xe1UL 10099 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV 0xceUL 10100 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID 0xcdUL 10101 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR 0xccUL 10102 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID 0xcbUL 10103 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM 0xc5UL 10104 #define NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM 0xc4UL 10105 #define NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM 0xc3UL 10106 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR 0xb9UL 10107 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR 0xb8UL 10108 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR 0xb7UL 10109 #define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND 0xb0UL 10110 #define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED 0xa7UL 10111 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED 10112 u8 problem_item; 10113 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 10114 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 10115 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 10116 u8 reset_required; 10117 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 10118 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 10119 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 10120 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 10121 u8 unused_0[4]; 10122 u8 valid; 10123 }; 10124 10125 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 10126 struct hwrm_nvm_install_update_cmd_err { 10127 u8 code; 10128 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 10129 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 10130 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 10131 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK 0x3UL 10132 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT 0x4UL 10133 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT 10134 u8 unused_0[7]; 10135 }; 10136 10137 /* hwrm_nvm_get_variable_input (size:320b/40B) */ 10138 struct hwrm_nvm_get_variable_input { 10139 __le16 req_type; 10140 __le16 cmpl_ring; 10141 __le16 seq_id; 10142 __le16 target_id; 10143 __le64 resp_addr; 10144 __le64 dest_data_addr; 10145 __le16 data_len; 10146 __le16 option_num; 10147 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 10148 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 10149 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 10150 __le16 dimensions; 10151 __le16 index_0; 10152 __le16 index_1; 10153 __le16 index_2; 10154 __le16 index_3; 10155 u8 flags; 10156 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 10157 u8 unused_0; 10158 }; 10159 10160 /* hwrm_nvm_get_variable_output (size:128b/16B) */ 10161 struct hwrm_nvm_get_variable_output { 10162 __le16 error_code; 10163 __le16 req_type; 10164 __le16 seq_id; 10165 __le16 resp_len; 10166 __le16 data_len; 10167 __le16 option_num; 10168 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 10169 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 10170 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 10171 u8 unused_0[3]; 10172 u8 valid; 10173 }; 10174 10175 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 10176 struct hwrm_nvm_get_variable_cmd_err { 10177 u8 code; 10178 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 10179 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 10180 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 10181 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 10182 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 10183 u8 unused_0[7]; 10184 }; 10185 10186 /* hwrm_nvm_set_variable_input (size:320b/40B) */ 10187 struct hwrm_nvm_set_variable_input { 10188 __le16 req_type; 10189 __le16 cmpl_ring; 10190 __le16 seq_id; 10191 __le16 target_id; 10192 __le64 resp_addr; 10193 __le64 src_data_addr; 10194 __le16 data_len; 10195 __le16 option_num; 10196 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 10197 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 10198 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 10199 __le16 dimensions; 10200 __le16 index_0; 10201 __le16 index_1; 10202 __le16 index_2; 10203 __le16 index_3; 10204 u8 flags; 10205 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 10206 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 10207 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 10208 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 10209 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 10210 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 10211 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 10212 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 10213 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL 10214 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4 10215 #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL 10216 u8 unused_0; 10217 }; 10218 10219 /* hwrm_nvm_set_variable_output (size:128b/16B) */ 10220 struct hwrm_nvm_set_variable_output { 10221 __le16 error_code; 10222 __le16 req_type; 10223 __le16 seq_id; 10224 __le16 resp_len; 10225 u8 unused_0[7]; 10226 u8 valid; 10227 }; 10228 10229 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 10230 struct hwrm_nvm_set_variable_cmd_err { 10231 u8 code; 10232 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 10233 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 10234 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 10235 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 10236 u8 unused_0[7]; 10237 }; 10238 10239 /* hwrm_selftest_qlist_input (size:128b/16B) */ 10240 struct hwrm_selftest_qlist_input { 10241 __le16 req_type; 10242 __le16 cmpl_ring; 10243 __le16 seq_id; 10244 __le16 target_id; 10245 __le64 resp_addr; 10246 }; 10247 10248 /* hwrm_selftest_qlist_output (size:2240b/280B) */ 10249 struct hwrm_selftest_qlist_output { 10250 __le16 error_code; 10251 __le16 req_type; 10252 __le16 seq_id; 10253 __le16 resp_len; 10254 u8 num_tests; 10255 u8 available_tests; 10256 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 10257 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 10258 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 10259 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 10260 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 10261 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 10262 u8 offline_tests; 10263 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 10264 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 10265 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 10266 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 10267 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 10268 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 10269 u8 unused_0; 10270 __le16 test_timeout; 10271 u8 unused_1[2]; 10272 char test_name[8][32]; 10273 u8 eyescope_target_BER_support; 10274 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED 0x0UL 10275 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED 0x1UL 10276 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL 10277 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL 10278 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL 10279 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 10280 u8 unused_2[6]; 10281 u8 valid; 10282 }; 10283 10284 /* hwrm_selftest_exec_input (size:192b/24B) */ 10285 struct hwrm_selftest_exec_input { 10286 __le16 req_type; 10287 __le16 cmpl_ring; 10288 __le16 seq_id; 10289 __le16 target_id; 10290 __le64 resp_addr; 10291 u8 flags; 10292 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 10293 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 10294 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 10295 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 10296 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 10297 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 10298 u8 unused_0[7]; 10299 }; 10300 10301 /* hwrm_selftest_exec_output (size:128b/16B) */ 10302 struct hwrm_selftest_exec_output { 10303 __le16 error_code; 10304 __le16 req_type; 10305 __le16 seq_id; 10306 __le16 resp_len; 10307 u8 requested_tests; 10308 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 10309 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 10310 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 10311 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 10312 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 10313 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 10314 u8 test_success; 10315 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 10316 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 10317 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 10318 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 10319 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 10320 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 10321 u8 unused_0[5]; 10322 u8 valid; 10323 }; 10324 10325 /* hwrm_selftest_irq_input (size:128b/16B) */ 10326 struct hwrm_selftest_irq_input { 10327 __le16 req_type; 10328 __le16 cmpl_ring; 10329 __le16 seq_id; 10330 __le16 target_id; 10331 __le64 resp_addr; 10332 }; 10333 10334 /* hwrm_selftest_irq_output (size:128b/16B) */ 10335 struct hwrm_selftest_irq_output { 10336 __le16 error_code; 10337 __le16 req_type; 10338 __le16 seq_id; 10339 __le16 resp_len; 10340 u8 unused_0[7]; 10341 u8 valid; 10342 }; 10343 10344 /* dbc_dbc (size:64b/8B) */ 10345 struct dbc_dbc { 10346 u32 index; 10347 #define DBC_DBC_INDEX_MASK 0xffffffUL 10348 #define DBC_DBC_INDEX_SFT 0 10349 #define DBC_DBC_EPOCH 0x1000000UL 10350 #define DBC_DBC_TOGGLE_MASK 0x6000000UL 10351 #define DBC_DBC_TOGGLE_SFT 25 10352 u32 type_path_xid; 10353 #define DBC_DBC_XID_MASK 0xfffffUL 10354 #define DBC_DBC_XID_SFT 0 10355 #define DBC_DBC_PATH_MASK 0x3000000UL 10356 #define DBC_DBC_PATH_SFT 24 10357 #define DBC_DBC_PATH_ROCE (0x0UL << 24) 10358 #define DBC_DBC_PATH_L2 (0x1UL << 24) 10359 #define DBC_DBC_PATH_ENGINE (0x2UL << 24) 10360 #define DBC_DBC_PATH_LAST DBC_DBC_PATH_ENGINE 10361 #define DBC_DBC_VALID 0x4000000UL 10362 #define DBC_DBC_DEBUG_TRACE 0x8000000UL 10363 #define DBC_DBC_TYPE_MASK 0xf0000000UL 10364 #define DBC_DBC_TYPE_SFT 28 10365 #define DBC_DBC_TYPE_SQ (0x0UL << 28) 10366 #define DBC_DBC_TYPE_RQ (0x1UL << 28) 10367 #define DBC_DBC_TYPE_SRQ (0x2UL << 28) 10368 #define DBC_DBC_TYPE_SRQ_ARM (0x3UL << 28) 10369 #define DBC_DBC_TYPE_CQ (0x4UL << 28) 10370 #define DBC_DBC_TYPE_CQ_ARMSE (0x5UL << 28) 10371 #define DBC_DBC_TYPE_CQ_ARMALL (0x6UL << 28) 10372 #define DBC_DBC_TYPE_CQ_ARMENA (0x7UL << 28) 10373 #define DBC_DBC_TYPE_SRQ_ARMENA (0x8UL << 28) 10374 #define DBC_DBC_TYPE_CQ_CUTOFF_ACK (0x9UL << 28) 10375 #define DBC_DBC_TYPE_NQ (0xaUL << 28) 10376 #define DBC_DBC_TYPE_NQ_ARM (0xbUL << 28) 10377 #define DBC_DBC_TYPE_NQ_MASK (0xeUL << 28) 10378 #define DBC_DBC_TYPE_NULL (0xfUL << 28) 10379 #define DBC_DBC_TYPE_LAST DBC_DBC_TYPE_NULL 10380 }; 10381 10382 /* db_push_start (size:64b/8B) */ 10383 struct db_push_start { 10384 u64 db; 10385 #define DB_PUSH_START_DB_INDEX_MASK 0xffffffUL 10386 #define DB_PUSH_START_DB_INDEX_SFT 0 10387 #define DB_PUSH_START_DB_PI_LO_MASK 0xff000000UL 10388 #define DB_PUSH_START_DB_PI_LO_SFT 24 10389 #define DB_PUSH_START_DB_XID_MASK 0xfffff00000000ULL 10390 #define DB_PUSH_START_DB_XID_SFT 32 10391 #define DB_PUSH_START_DB_PI_HI_MASK 0xf0000000000000ULL 10392 #define DB_PUSH_START_DB_PI_HI_SFT 52 10393 #define DB_PUSH_START_DB_TYPE_MASK 0xf000000000000000ULL 10394 #define DB_PUSH_START_DB_TYPE_SFT 60 10395 #define DB_PUSH_START_DB_TYPE_PUSH_START (0xcULL << 60) 10396 #define DB_PUSH_START_DB_TYPE_PUSH_END (0xdULL << 60) 10397 #define DB_PUSH_START_DB_TYPE_LAST DB_PUSH_START_DB_TYPE_PUSH_END 10398 }; 10399 10400 /* db_push_end (size:64b/8B) */ 10401 struct db_push_end { 10402 u64 db; 10403 #define DB_PUSH_END_DB_INDEX_MASK 0xffffffUL 10404 #define DB_PUSH_END_DB_INDEX_SFT 0 10405 #define DB_PUSH_END_DB_PI_LO_MASK 0xff000000UL 10406 #define DB_PUSH_END_DB_PI_LO_SFT 24 10407 #define DB_PUSH_END_DB_XID_MASK 0xfffff00000000ULL 10408 #define DB_PUSH_END_DB_XID_SFT 32 10409 #define DB_PUSH_END_DB_PI_HI_MASK 0xf0000000000000ULL 10410 #define DB_PUSH_END_DB_PI_HI_SFT 52 10411 #define DB_PUSH_END_DB_PATH_MASK 0x300000000000000ULL 10412 #define DB_PUSH_END_DB_PATH_SFT 56 10413 #define DB_PUSH_END_DB_PATH_ROCE (0x0ULL << 56) 10414 #define DB_PUSH_END_DB_PATH_L2 (0x1ULL << 56) 10415 #define DB_PUSH_END_DB_PATH_ENGINE (0x2ULL << 56) 10416 #define DB_PUSH_END_DB_PATH_LAST DB_PUSH_END_DB_PATH_ENGINE 10417 #define DB_PUSH_END_DB_DEBUG_TRACE 0x800000000000000ULL 10418 #define DB_PUSH_END_DB_TYPE_MASK 0xf000000000000000ULL 10419 #define DB_PUSH_END_DB_TYPE_SFT 60 10420 #define DB_PUSH_END_DB_TYPE_PUSH_START (0xcULL << 60) 10421 #define DB_PUSH_END_DB_TYPE_PUSH_END (0xdULL << 60) 10422 #define DB_PUSH_END_DB_TYPE_LAST DB_PUSH_END_DB_TYPE_PUSH_END 10423 }; 10424 10425 /* db_push_info (size:64b/8B) */ 10426 struct db_push_info { 10427 u32 push_size_push_index; 10428 #define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL 10429 #define DB_PUSH_INFO_PUSH_INDEX_SFT 0 10430 #define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL 10431 #define DB_PUSH_INFO_PUSH_SIZE_SFT 24 10432 u32 reserved32; 10433 }; 10434 10435 /* fw_status_reg (size:32b/4B) */ 10436 struct fw_status_reg { 10437 u32 fw_status; 10438 #define FW_STATUS_REG_CODE_MASK 0xffffUL 10439 #define FW_STATUS_REG_CODE_SFT 0 10440 #define FW_STATUS_REG_CODE_READY 0x8000UL 10441 #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY 10442 #define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL 10443 #define FW_STATUS_REG_RECOVERABLE 0x20000UL 10444 #define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL 10445 #define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL 10446 #define FW_STATUS_REG_SHUTDOWN 0x100000UL 10447 #define FW_STATUS_REG_CRASHED_NO_MASTER 0x200000UL 10448 #define FW_STATUS_REG_RECOVERING 0x400000UL 10449 #define FW_STATUS_REG_MANU_DEBUG_STATUS 0x800000UL 10450 }; 10451 10452 /* hcomm_status (size:64b/8B) */ 10453 struct hcomm_status { 10454 u32 sig_ver; 10455 #define HCOMM_STATUS_VER_MASK 0xffUL 10456 #define HCOMM_STATUS_VER_SFT 0 10457 #define HCOMM_STATUS_VER_LATEST 0x1UL 10458 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST 10459 #define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL 10460 #define HCOMM_STATUS_SIGNATURE_SFT 8 10461 #define HCOMM_STATUS_SIGNATURE_VAL (0x484353UL << 8) 10462 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL 10463 u32 fw_status_loc; 10464 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK 0x3UL 10465 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 10466 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG 0x0UL 10467 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC 0x1UL 10468 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 0x2UL 10469 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 0x3UL 10470 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 10471 #define HCOMM_STATUS_TRUE_OFFSET_MASK 0xfffffffcUL 10472 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 10473 }; 10474 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL 10475 10476 #endif /* _BNXT_HSI_H_ */ 10477