1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2014-2018 Broadcom Limited 5 * Copyright (c) 2018-2022 Broadcom Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * DO NOT MODIFY!!! This file is automatically generated. 12 */ 13 14 #ifndef _BNXT_HSI_H_ 15 #define _BNXT_HSI_H_ 16 17 /* hwrm_cmd_hdr (size:128b/16B) */ 18 struct hwrm_cmd_hdr { 19 __le16 req_type; 20 __le16 cmpl_ring; 21 __le16 seq_id; 22 __le16 target_id; 23 __le64 resp_addr; 24 }; 25 26 /* hwrm_resp_hdr (size:64b/8B) */ 27 struct hwrm_resp_hdr { 28 __le16 error_code; 29 __le16 req_type; 30 __le16 seq_id; 31 __le16 resp_len; 32 }; 33 34 #define CMD_DISCR_TLV_ENCAP 0x8000UL 35 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 36 37 38 #define TLV_TYPE_HWRM_REQUEST 0x1UL 39 #define TLV_TYPE_HWRM_RESPONSE 0x2UL 40 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 41 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 42 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 43 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL 44 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 45 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 46 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 47 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL 48 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL 49 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 50 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL 51 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL 52 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 53 54 55 /* tlv (size:64b/8B) */ 56 struct tlv { 57 __le16 cmd_discr; 58 u8 reserved_8b; 59 u8 flags; 60 #define TLV_FLAGS_MORE 0x1UL 61 #define TLV_FLAGS_MORE_LAST 0x0UL 62 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 63 #define TLV_FLAGS_REQUIRED 0x2UL 64 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 65 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 66 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 67 __le16 tlv_type; 68 __le16 length; 69 }; 70 71 /* input (size:128b/16B) */ 72 struct input { 73 __le16 req_type; 74 __le16 cmpl_ring; 75 __le16 seq_id; 76 __le16 target_id; 77 __le64 resp_addr; 78 }; 79 80 /* output (size:64b/8B) */ 81 struct output { 82 __le16 error_code; 83 __le16 req_type; 84 __le16 seq_id; 85 __le16 resp_len; 86 }; 87 88 /* hwrm_short_input (size:128b/16B) */ 89 struct hwrm_short_input { 90 __le16 req_type; 91 __le16 signature; 92 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 93 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 94 __le16 target_id; 95 #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL 96 #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL 97 #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS 98 __le16 size; 99 __le64 req_addr; 100 }; 101 102 /* cmd_nums (size:64b/8B) */ 103 struct cmd_nums { 104 __le16 req_type; 105 #define HWRM_VER_GET 0x0UL 106 #define HWRM_FUNC_ECHO_RESPONSE 0xbUL 107 #define HWRM_ERROR_RECOVERY_QCFG 0xcUL 108 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 109 #define HWRM_FUNC_BUF_UNRGTR 0xeUL 110 #define HWRM_FUNC_VF_CFG 0xfUL 111 #define HWRM_RESERVED1 0x10UL 112 #define HWRM_FUNC_RESET 0x11UL 113 #define HWRM_FUNC_GETFID 0x12UL 114 #define HWRM_FUNC_VF_ALLOC 0x13UL 115 #define HWRM_FUNC_VF_FREE 0x14UL 116 #define HWRM_FUNC_QCAPS 0x15UL 117 #define HWRM_FUNC_QCFG 0x16UL 118 #define HWRM_FUNC_CFG 0x17UL 119 #define HWRM_FUNC_QSTATS 0x18UL 120 #define HWRM_FUNC_CLR_STATS 0x19UL 121 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 122 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 123 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 124 #define HWRM_FUNC_DRV_RGTR 0x1dUL 125 #define HWRM_FUNC_DRV_QVER 0x1eUL 126 #define HWRM_FUNC_BUF_RGTR 0x1fUL 127 #define HWRM_PORT_PHY_CFG 0x20UL 128 #define HWRM_PORT_MAC_CFG 0x21UL 129 #define HWRM_PORT_TS_QUERY 0x22UL 130 #define HWRM_PORT_QSTATS 0x23UL 131 #define HWRM_PORT_LPBK_QSTATS 0x24UL 132 #define HWRM_PORT_CLR_STATS 0x25UL 133 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 134 #define HWRM_PORT_PHY_QCFG 0x27UL 135 #define HWRM_PORT_MAC_QCFG 0x28UL 136 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 137 #define HWRM_PORT_PHY_QCAPS 0x2aUL 138 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 139 #define HWRM_PORT_PHY_I2C_READ 0x2cUL 140 #define HWRM_PORT_LED_CFG 0x2dUL 141 #define HWRM_PORT_LED_QCFG 0x2eUL 142 #define HWRM_PORT_LED_QCAPS 0x2fUL 143 #define HWRM_QUEUE_QPORTCFG 0x30UL 144 #define HWRM_QUEUE_QCFG 0x31UL 145 #define HWRM_QUEUE_CFG 0x32UL 146 #define HWRM_FUNC_VLAN_CFG 0x33UL 147 #define HWRM_FUNC_VLAN_QCFG 0x34UL 148 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 149 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 150 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 151 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 152 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 153 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 154 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 155 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 156 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 157 #define HWRM_VNIC_ALLOC 0x40UL 158 #define HWRM_VNIC_FREE 0x41UL 159 #define HWRM_VNIC_CFG 0x42UL 160 #define HWRM_VNIC_QCFG 0x43UL 161 #define HWRM_VNIC_TPA_CFG 0x44UL 162 #define HWRM_VNIC_TPA_QCFG 0x45UL 163 #define HWRM_VNIC_RSS_CFG 0x46UL 164 #define HWRM_VNIC_RSS_QCFG 0x47UL 165 #define HWRM_VNIC_PLCMODES_CFG 0x48UL 166 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 167 #define HWRM_VNIC_QCAPS 0x4aUL 168 #define HWRM_VNIC_UPDATE 0x4bUL 169 #define HWRM_RING_ALLOC 0x50UL 170 #define HWRM_RING_FREE 0x51UL 171 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 172 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 173 #define HWRM_RING_AGGINT_QCAPS 0x54UL 174 #define HWRM_RING_SCHQ_ALLOC 0x55UL 175 #define HWRM_RING_SCHQ_CFG 0x56UL 176 #define HWRM_RING_SCHQ_FREE 0x57UL 177 #define HWRM_RING_RESET 0x5eUL 178 #define HWRM_RING_GRP_ALLOC 0x60UL 179 #define HWRM_RING_GRP_FREE 0x61UL 180 #define HWRM_RING_CFG 0x62UL 181 #define HWRM_RING_QCFG 0x63UL 182 #define HWRM_RESERVED5 0x64UL 183 #define HWRM_RESERVED6 0x65UL 184 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 185 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 186 #define HWRM_QUEUE_MPLS_QCAPS 0x80UL 187 #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL 188 #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL 189 #define HWRM_QUEUE_VLANPRI_QCAPS 0x83UL 190 #define HWRM_QUEUE_VLANPRI2PRI_QCFG 0x84UL 191 #define HWRM_QUEUE_VLANPRI2PRI_CFG 0x85UL 192 #define HWRM_QUEUE_GLOBAL_CFG 0x86UL 193 #define HWRM_QUEUE_GLOBAL_QCFG 0x87UL 194 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 195 #define HWRM_CFA_L2_FILTER_FREE 0x91UL 196 #define HWRM_CFA_L2_FILTER_CFG 0x92UL 197 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 198 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 199 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 200 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 201 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 202 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 203 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 204 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 205 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 206 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 207 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 208 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 209 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 210 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 211 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 212 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 213 #define HWRM_STAT_CTX_ALLOC 0xb0UL 214 #define HWRM_STAT_CTX_FREE 0xb1UL 215 #define HWRM_STAT_CTX_QUERY 0xb2UL 216 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 217 #define HWRM_PORT_QSTATS_EXT 0xb4UL 218 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL 219 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL 220 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL 221 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL 222 #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL 223 #define HWRM_RESERVED7 0xbaUL 224 #define HWRM_PORT_TX_FIR_CFG 0xbbUL 225 #define HWRM_PORT_TX_FIR_QCFG 0xbcUL 226 #define HWRM_PORT_ECN_QSTATS 0xbdUL 227 #define HWRM_FW_LIVEPATCH_QUERY 0xbeUL 228 #define HWRM_FW_LIVEPATCH 0xbfUL 229 #define HWRM_FW_RESET 0xc0UL 230 #define HWRM_FW_QSTATUS 0xc1UL 231 #define HWRM_FW_HEALTH_CHECK 0xc2UL 232 #define HWRM_FW_SYNC 0xc3UL 233 #define HWRM_FW_STATE_QCAPS 0xc4UL 234 #define HWRM_FW_STATE_QUIESCE 0xc5UL 235 #define HWRM_FW_STATE_BACKUP 0xc6UL 236 #define HWRM_FW_STATE_RESTORE 0xc7UL 237 #define HWRM_FW_SET_TIME 0xc8UL 238 #define HWRM_FW_GET_TIME 0xc9UL 239 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 240 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 241 #define HWRM_FW_IPC_MAILBOX 0xccUL 242 #define HWRM_FW_ECN_CFG 0xcdUL 243 #define HWRM_FW_ECN_QCFG 0xceUL 244 #define HWRM_FW_SECURE_CFG 0xcfUL 245 #define HWRM_EXEC_FWD_RESP 0xd0UL 246 #define HWRM_REJECT_FWD_RESP 0xd1UL 247 #define HWRM_FWD_RESP 0xd2UL 248 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 249 #define HWRM_OEM_CMD 0xd4UL 250 #define HWRM_PORT_PRBS_TEST 0xd5UL 251 #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL 252 #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL 253 #define HWRM_FW_STATE_UNQUIESCE 0xd8UL 254 #define HWRM_PORT_DSC_DUMP 0xd9UL 255 #define HWRM_PORT_EP_TX_QCFG 0xdaUL 256 #define HWRM_PORT_EP_TX_CFG 0xdbUL 257 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 258 #define HWRM_REG_POWER_QUERY 0xe1UL 259 #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL 260 #define HWRM_REG_POWER_HISTOGRAM 0xe3UL 261 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 262 #define HWRM_WOL_FILTER_FREE 0xf1UL 263 #define HWRM_WOL_FILTER_QCFG 0xf2UL 264 #define HWRM_WOL_REASON_QCFG 0xf3UL 265 #define HWRM_CFA_METER_QCAPS 0xf4UL 266 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 267 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 268 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 269 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 270 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 271 #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL 272 #define HWRM_CFA_VFR_ALLOC 0xfdUL 273 #define HWRM_CFA_VFR_FREE 0xfeUL 274 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 275 #define HWRM_CFA_VF_PAIR_FREE 0x101UL 276 #define HWRM_CFA_VF_PAIR_INFO 0x102UL 277 #define HWRM_CFA_FLOW_ALLOC 0x103UL 278 #define HWRM_CFA_FLOW_FREE 0x104UL 279 #define HWRM_CFA_FLOW_FLUSH 0x105UL 280 #define HWRM_CFA_FLOW_STATS 0x106UL 281 #define HWRM_CFA_FLOW_INFO 0x107UL 282 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 283 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 284 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 285 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 286 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 287 #define HWRM_CFA_PAIR_ALLOC 0x10dUL 288 #define HWRM_CFA_PAIR_FREE 0x10eUL 289 #define HWRM_CFA_PAIR_INFO 0x10fUL 290 #define HWRM_FW_IPC_MSG 0x110UL 291 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 292 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 293 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL 294 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL 295 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL 296 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL 297 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL 298 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL 299 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL 300 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL 301 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL 302 #define HWRM_CFA_COUNTER_CFG 0x11cUL 303 #define HWRM_CFA_COUNTER_QCFG 0x11dUL 304 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL 305 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL 306 #define HWRM_CFA_EEM_QCAPS 0x120UL 307 #define HWRM_CFA_EEM_CFG 0x121UL 308 #define HWRM_CFA_EEM_QCFG 0x122UL 309 #define HWRM_CFA_EEM_OP 0x123UL 310 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL 311 #define HWRM_CFA_TFLIB 0x125UL 312 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR 0x126UL 313 #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR 0x127UL 314 #define HWRM_CFA_TLS_FILTER_ALLOC 0x128UL 315 #define HWRM_CFA_TLS_FILTER_FREE 0x129UL 316 #define HWRM_ENGINE_CKV_STATUS 0x12eUL 317 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 318 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 319 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 320 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 321 #define HWRM_ENGINE_CKV_FLUSH 0x133UL 322 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 323 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 324 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL 325 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL 326 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 327 #define HWRM_ENGINE_QG_QUERY 0x13dUL 328 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 329 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 330 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 331 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 332 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 333 #define HWRM_ENGINE_QG_METER_BIND 0x143UL 334 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 335 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 336 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 337 #define HWRM_ENGINE_SG_QUERY 0x147UL 338 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 339 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 340 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 341 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 342 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 343 #define HWRM_ENGINE_STATS_CONFIG 0x155UL 344 #define HWRM_ENGINE_STATS_CLEAR 0x156UL 345 #define HWRM_ENGINE_STATS_QUERY 0x157UL 346 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL 347 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 348 #define HWRM_ENGINE_RQ_FREE 0x15fUL 349 #define HWRM_ENGINE_CQ_ALLOC 0x160UL 350 #define HWRM_ENGINE_CQ_FREE 0x161UL 351 #define HWRM_ENGINE_NQ_ALLOC 0x162UL 352 #define HWRM_ENGINE_NQ_FREE 0x163UL 353 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 354 #define HWRM_ENGINE_FUNC_QCFG 0x165UL 355 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 356 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 357 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 358 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 359 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 360 #define HWRM_FUNC_VF_BW_CFG 0x195UL 361 #define HWRM_FUNC_VF_BW_QCFG 0x196UL 362 #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL 363 #define HWRM_FUNC_QSTATS_EXT 0x198UL 364 #define HWRM_STAT_EXT_CTX_QUERY 0x199UL 365 #define HWRM_FUNC_SPD_CFG 0x19aUL 366 #define HWRM_FUNC_SPD_QCFG 0x19bUL 367 #define HWRM_FUNC_PTP_PIN_QCFG 0x19cUL 368 #define HWRM_FUNC_PTP_PIN_CFG 0x19dUL 369 #define HWRM_FUNC_PTP_CFG 0x19eUL 370 #define HWRM_FUNC_PTP_TS_QUERY 0x19fUL 371 #define HWRM_FUNC_PTP_EXT_CFG 0x1a0UL 372 #define HWRM_FUNC_PTP_EXT_QCFG 0x1a1UL 373 #define HWRM_FUNC_KEY_CTX_ALLOC 0x1a2UL 374 #define HWRM_FUNC_BACKING_STORE_CFG_V2 0x1a3UL 375 #define HWRM_FUNC_BACKING_STORE_QCFG_V2 0x1a4UL 376 #define HWRM_FUNC_DBR_PACING_CFG 0x1a5UL 377 #define HWRM_FUNC_DBR_PACING_QCFG 0x1a6UL 378 #define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT 0x1a7UL 379 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2 0x1a8UL 380 #define HWRM_FUNC_DBR_PACING_NQLIST_QUERY 0x1a9UL 381 #define HWRM_FUNC_DBR_RECOVERY_COMPLETED 0x1aaUL 382 #define HWRM_SELFTEST_QLIST 0x200UL 383 #define HWRM_SELFTEST_EXEC 0x201UL 384 #define HWRM_SELFTEST_IRQ 0x202UL 385 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 386 #define HWRM_PCIE_QSTATS 0x204UL 387 #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL 388 #define HWRM_MFG_TIMERS_QUERY 0x206UL 389 #define HWRM_MFG_OTP_CFG 0x207UL 390 #define HWRM_MFG_OTP_QCFG 0x208UL 391 #define HWRM_MFG_HDMA_TEST 0x209UL 392 #define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL 393 #define HWRM_MFG_FRU_EEPROM_READ 0x20bUL 394 #define HWRM_MFG_SOC_IMAGE 0x20cUL 395 #define HWRM_MFG_SOC_QSTATUS 0x20dUL 396 #define HWRM_MFG_PARAM_SEEPROM_SYNC 0x20eUL 397 #define HWRM_MFG_PARAM_SEEPROM_READ 0x20fUL 398 #define HWRM_MFG_PARAM_SEEPROM_HEALTH 0x210UL 399 #define HWRM_MFG_PRVSN_EXPORT_CSR 0x211UL 400 #define HWRM_MFG_PRVSN_IMPORT_CERT 0x212UL 401 #define HWRM_MFG_PRVSN_GET_STATE 0x213UL 402 #define HWRM_MFG_GET_NVM_MEASUREMENT 0x214UL 403 #define HWRM_MFG_PSOC_QSTATUS 0x215UL 404 #define HWRM_MFG_SELFTEST_QLIST 0x216UL 405 #define HWRM_MFG_SELFTEST_EXEC 0x217UL 406 #define HWRM_STAT_GENERIC_QSTATS 0x218UL 407 #define HWRM_TF 0x2bcUL 408 #define HWRM_TF_VERSION_GET 0x2bdUL 409 #define HWRM_TF_SESSION_OPEN 0x2c6UL 410 #define HWRM_TF_SESSION_ATTACH 0x2c7UL 411 #define HWRM_TF_SESSION_REGISTER 0x2c8UL 412 #define HWRM_TF_SESSION_UNREGISTER 0x2c9UL 413 #define HWRM_TF_SESSION_CLOSE 0x2caUL 414 #define HWRM_TF_SESSION_QCFG 0x2cbUL 415 #define HWRM_TF_SESSION_RESC_QCAPS 0x2ccUL 416 #define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL 417 #define HWRM_TF_SESSION_RESC_FREE 0x2ceUL 418 #define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL 419 #define HWRM_TF_SESSION_RESC_INFO 0x2d0UL 420 #define HWRM_TF_TBL_TYPE_GET 0x2daUL 421 #define HWRM_TF_TBL_TYPE_SET 0x2dbUL 422 #define HWRM_TF_TBL_TYPE_BULK_GET 0x2dcUL 423 #define HWRM_TF_CTXT_MEM_ALLOC 0x2e2UL 424 #define HWRM_TF_CTXT_MEM_FREE 0x2e3UL 425 #define HWRM_TF_CTXT_MEM_RGTR 0x2e4UL 426 #define HWRM_TF_CTXT_MEM_UNRGTR 0x2e5UL 427 #define HWRM_TF_EXT_EM_QCAPS 0x2e6UL 428 #define HWRM_TF_EXT_EM_OP 0x2e7UL 429 #define HWRM_TF_EXT_EM_CFG 0x2e8UL 430 #define HWRM_TF_EXT_EM_QCFG 0x2e9UL 431 #define HWRM_TF_EM_INSERT 0x2eaUL 432 #define HWRM_TF_EM_DELETE 0x2ebUL 433 #define HWRM_TF_EM_HASH_INSERT 0x2ecUL 434 #define HWRM_TF_EM_MOVE 0x2edUL 435 #define HWRM_TF_TCAM_SET 0x2f8UL 436 #define HWRM_TF_TCAM_GET 0x2f9UL 437 #define HWRM_TF_TCAM_MOVE 0x2faUL 438 #define HWRM_TF_TCAM_FREE 0x2fbUL 439 #define HWRM_TF_GLOBAL_CFG_SET 0x2fcUL 440 #define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL 441 #define HWRM_TF_IF_TBL_SET 0x2feUL 442 #define HWRM_TF_IF_TBL_GET 0x2ffUL 443 #define HWRM_SV 0x400UL 444 #define HWRM_DBG_READ_DIRECT 0xff10UL 445 #define HWRM_DBG_READ_INDIRECT 0xff11UL 446 #define HWRM_DBG_WRITE_DIRECT 0xff12UL 447 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 448 #define HWRM_DBG_DUMP 0xff14UL 449 #define HWRM_DBG_ERASE_NVM 0xff15UL 450 #define HWRM_DBG_CFG 0xff16UL 451 #define HWRM_DBG_COREDUMP_LIST 0xff17UL 452 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 453 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 454 #define HWRM_DBG_FW_CLI 0xff1aUL 455 #define HWRM_DBG_I2C_CMD 0xff1bUL 456 #define HWRM_DBG_RING_INFO_GET 0xff1cUL 457 #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL 458 #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL 459 #define HWRM_DBG_DRV_TRACE 0xff1fUL 460 #define HWRM_DBG_QCAPS 0xff20UL 461 #define HWRM_DBG_QCFG 0xff21UL 462 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL 463 #define HWRM_DBG_USEQ_ALLOC 0xff23UL 464 #define HWRM_DBG_USEQ_FREE 0xff24UL 465 #define HWRM_DBG_USEQ_FLUSH 0xff25UL 466 #define HWRM_DBG_USEQ_QCAPS 0xff26UL 467 #define HWRM_DBG_USEQ_CW_CFG 0xff27UL 468 #define HWRM_DBG_USEQ_SCHED_CFG 0xff28UL 469 #define HWRM_DBG_USEQ_RUN 0xff29UL 470 #define HWRM_DBG_USEQ_DELIVERY_REQ 0xff2aUL 471 #define HWRM_DBG_USEQ_RESP_HDR 0xff2bUL 472 #define HWRM_NVM_DEFRAG 0xffecUL 473 #define HWRM_NVM_REQ_ARBITRATION 0xffedUL 474 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 475 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 476 #define HWRM_NVM_FLUSH 0xfff0UL 477 #define HWRM_NVM_GET_VARIABLE 0xfff1UL 478 #define HWRM_NVM_SET_VARIABLE 0xfff2UL 479 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 480 #define HWRM_NVM_MODIFY 0xfff4UL 481 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 482 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 483 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 484 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 485 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 486 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 487 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 488 #define HWRM_NVM_RAW_DUMP 0xfffcUL 489 #define HWRM_NVM_READ 0xfffdUL 490 #define HWRM_NVM_WRITE 0xfffeUL 491 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 492 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 493 __le16 unused_0[3]; 494 }; 495 496 /* ret_codes (size:64b/8B) */ 497 struct ret_codes { 498 __le16 error_code; 499 #define HWRM_ERR_CODE_SUCCESS 0x0UL 500 #define HWRM_ERR_CODE_FAIL 0x1UL 501 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 502 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 503 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 504 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 505 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 506 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 507 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 508 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 509 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL 510 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL 511 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL 512 #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL 513 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL 514 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 515 #define HWRM_ERR_CODE_BUSY 0x10UL 516 #define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL 517 #define HWRM_ERR_CODE_PF_UNAVAILABLE 0x12UL 518 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 519 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 520 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 521 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 522 __le16 unused_0[3]; 523 }; 524 525 /* hwrm_err_output (size:128b/16B) */ 526 struct hwrm_err_output { 527 __le16 error_code; 528 __le16 req_type; 529 __le16 seq_id; 530 __le16 resp_len; 531 __le32 opaque_0; 532 __le16 opaque_1; 533 u8 cmd_err; 534 u8 valid; 535 }; 536 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 537 #define HWRM_MAX_REQ_LEN 128 538 #define HWRM_MAX_RESP_LEN 704 539 #define HW_HASH_INDEX_SIZE 0x80 540 #define HW_HASH_KEY_SIZE 40 541 #define HWRM_RESP_VALID_KEY 1 542 #define HWRM_TARGET_ID_BONO 0xFFF8 543 #define HWRM_TARGET_ID_KONG 0xFFF9 544 #define HWRM_TARGET_ID_APE 0xFFFA 545 #define HWRM_TARGET_ID_TOOLS 0xFFFD 546 #define HWRM_VERSION_MAJOR 1 547 #define HWRM_VERSION_MINOR 10 548 #define HWRM_VERSION_UPDATE 2 549 #define HWRM_VERSION_RSVD 95 550 #define HWRM_VERSION_STR "1.10.2.95" 551 552 /* hwrm_ver_get_input (size:192b/24B) */ 553 struct hwrm_ver_get_input { 554 __le16 req_type; 555 __le16 cmpl_ring; 556 __le16 seq_id; 557 __le16 target_id; 558 __le64 resp_addr; 559 u8 hwrm_intf_maj; 560 u8 hwrm_intf_min; 561 u8 hwrm_intf_upd; 562 u8 unused_0[5]; 563 }; 564 565 /* hwrm_ver_get_output (size:1408b/176B) */ 566 struct hwrm_ver_get_output { 567 __le16 error_code; 568 __le16 req_type; 569 __le16 seq_id; 570 __le16 resp_len; 571 u8 hwrm_intf_maj_8b; 572 u8 hwrm_intf_min_8b; 573 u8 hwrm_intf_upd_8b; 574 u8 hwrm_intf_rsvd_8b; 575 u8 hwrm_fw_maj_8b; 576 u8 hwrm_fw_min_8b; 577 u8 hwrm_fw_bld_8b; 578 u8 hwrm_fw_rsvd_8b; 579 u8 mgmt_fw_maj_8b; 580 u8 mgmt_fw_min_8b; 581 u8 mgmt_fw_bld_8b; 582 u8 mgmt_fw_rsvd_8b; 583 u8 netctrl_fw_maj_8b; 584 u8 netctrl_fw_min_8b; 585 u8 netctrl_fw_bld_8b; 586 u8 netctrl_fw_rsvd_8b; 587 __le32 dev_caps_cfg; 588 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 589 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 590 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 591 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 592 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 593 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 594 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 595 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 596 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 597 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL 598 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL 599 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL 600 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL 601 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL 602 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL 603 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE 0x8000UL 604 u8 roce_fw_maj_8b; 605 u8 roce_fw_min_8b; 606 u8 roce_fw_bld_8b; 607 u8 roce_fw_rsvd_8b; 608 char hwrm_fw_name[16]; 609 char mgmt_fw_name[16]; 610 char netctrl_fw_name[16]; 611 char active_pkg_name[16]; 612 char roce_fw_name[16]; 613 __le16 chip_num; 614 u8 chip_rev; 615 u8 chip_metal; 616 u8 chip_bond_id; 617 u8 chip_platform_type; 618 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 619 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 620 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 621 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 622 __le16 max_req_win_len; 623 __le16 max_resp_len; 624 __le16 def_req_timeout; 625 u8 flags; 626 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 627 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 628 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY_BACKING_STORE 0x4UL 629 u8 unused_0[2]; 630 u8 always_1; 631 __le16 hwrm_intf_major; 632 __le16 hwrm_intf_minor; 633 __le16 hwrm_intf_build; 634 __le16 hwrm_intf_patch; 635 __le16 hwrm_fw_major; 636 __le16 hwrm_fw_minor; 637 __le16 hwrm_fw_build; 638 __le16 hwrm_fw_patch; 639 __le16 mgmt_fw_major; 640 __le16 mgmt_fw_minor; 641 __le16 mgmt_fw_build; 642 __le16 mgmt_fw_patch; 643 __le16 netctrl_fw_major; 644 __le16 netctrl_fw_minor; 645 __le16 netctrl_fw_build; 646 __le16 netctrl_fw_patch; 647 __le16 roce_fw_major; 648 __le16 roce_fw_minor; 649 __le16 roce_fw_build; 650 __le16 roce_fw_patch; 651 __le16 max_ext_req_len; 652 __le16 max_req_timeout; 653 u8 unused_1[3]; 654 u8 valid; 655 }; 656 657 /* eject_cmpl (size:128b/16B) */ 658 struct eject_cmpl { 659 __le16 type; 660 #define EJECT_CMPL_TYPE_MASK 0x3fUL 661 #define EJECT_CMPL_TYPE_SFT 0 662 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 663 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 664 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL 665 #define EJECT_CMPL_FLAGS_SFT 6 666 #define EJECT_CMPL_FLAGS_ERROR 0x40UL 667 __le16 len; 668 __le32 opaque; 669 __le16 v; 670 #define EJECT_CMPL_V 0x1UL 671 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL 672 #define EJECT_CMPL_ERRORS_SFT 1 673 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL 674 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 675 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1) 676 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1) 677 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1) 678 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1) 679 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH 680 __le16 reserved16; 681 __le32 unused_2; 682 }; 683 684 /* hwrm_cmpl (size:128b/16B) */ 685 struct hwrm_cmpl { 686 __le16 type; 687 #define CMPL_TYPE_MASK 0x3fUL 688 #define CMPL_TYPE_SFT 0 689 #define CMPL_TYPE_HWRM_DONE 0x20UL 690 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 691 __le16 sequence_id; 692 __le32 unused_1; 693 __le32 v; 694 #define CMPL_V 0x1UL 695 __le32 unused_3; 696 }; 697 698 /* hwrm_fwd_req_cmpl (size:128b/16B) */ 699 struct hwrm_fwd_req_cmpl { 700 __le16 req_len_type; 701 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 702 #define FWD_REQ_CMPL_TYPE_SFT 0 703 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 704 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 705 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 706 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 707 __le16 source_id; 708 __le32 unused0; 709 __le32 req_buf_addr_v[2]; 710 #define FWD_REQ_CMPL_V 0x1UL 711 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 712 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 713 }; 714 715 /* hwrm_fwd_resp_cmpl (size:128b/16B) */ 716 struct hwrm_fwd_resp_cmpl { 717 __le16 type; 718 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 719 #define FWD_RESP_CMPL_TYPE_SFT 0 720 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 721 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 722 __le16 source_id; 723 __le16 resp_len; 724 __le16 unused_1; 725 __le32 resp_buf_addr_v[2]; 726 #define FWD_RESP_CMPL_V 0x1UL 727 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 728 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 729 }; 730 731 /* hwrm_async_event_cmpl (size:128b/16B) */ 732 struct hwrm_async_event_cmpl { 733 __le16 type; 734 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 735 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 736 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 737 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 738 __le16 event_id; 739 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 740 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 741 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 742 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 743 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 744 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 745 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 746 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 747 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 748 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL 749 #define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG 0xaUL 750 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 751 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 752 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 753 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 754 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 755 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 756 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 757 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 758 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 759 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 760 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 761 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 762 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL 763 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 764 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 765 #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL 766 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL 767 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL 768 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL 769 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL 770 #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL 771 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL 772 #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL 773 #define ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST 0x42UL 774 #define ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE 0x43UL 775 #define ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP 0x44UL 776 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT 0x45UL 777 #define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD 0x46UL 778 #define ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE 0x47UL 779 #define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE 0x48UL 780 #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x49UL 781 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 782 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 783 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 784 __le32 event_data2; 785 u8 opaque_v; 786 #define ASYNC_EVENT_CMPL_V 0x1UL 787 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 788 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 789 u8 timestamp_lo; 790 __le16 timestamp_hi; 791 __le32 event_data1; 792 }; 793 794 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 795 struct hwrm_async_event_cmpl_link_status_change { 796 __le16 type; 797 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 798 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 799 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 800 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 801 __le16 event_id; 802 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 803 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 804 __le32 event_data2; 805 u8 opaque_v; 806 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 807 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 808 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 809 u8 timestamp_lo; 810 __le16 timestamp_hi; 811 __le32 event_data1; 812 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 813 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 814 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 815 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 816 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 817 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 818 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 819 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 820 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 821 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 822 }; 823 824 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 825 struct hwrm_async_event_cmpl_port_conn_not_allowed { 826 __le16 type; 827 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 828 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 829 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 830 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 831 __le16 event_id; 832 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 833 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 834 __le32 event_data2; 835 u8 opaque_v; 836 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 837 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 838 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 839 u8 timestamp_lo; 840 __le16 timestamp_hi; 841 __le32 event_data1; 842 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 843 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 844 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 845 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 846 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 847 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 848 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 849 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 850 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 851 }; 852 853 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 854 struct hwrm_async_event_cmpl_link_speed_cfg_change { 855 __le16 type; 856 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 857 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 858 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 859 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 860 __le16 event_id; 861 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 862 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 863 __le32 event_data2; 864 u8 opaque_v; 865 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 866 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 867 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 868 u8 timestamp_lo; 869 __le16 timestamp_hi; 870 __le32 event_data1; 871 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 872 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 873 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 874 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 875 }; 876 877 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ 878 struct hwrm_async_event_cmpl_reset_notify { 879 __le16 type; 880 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL 881 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 882 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 883 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 884 __le16 event_id; 885 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 886 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 887 __le32 event_data2; 888 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK 0xffffUL 889 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0 890 u8 opaque_v; 891 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 892 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL 893 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 894 u8 timestamp_lo; 895 __le16 timestamp_hi; 896 __le32 event_data1; 897 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL 898 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0 899 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL 900 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL 901 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 902 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL 903 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8 904 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 905 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 906 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 907 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET (0x4UL << 8) 908 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION (0x5UL << 8) 909 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION 910 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 911 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 912 }; 913 914 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ 915 struct hwrm_async_event_cmpl_error_recovery { 916 __le16 type; 917 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL 918 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 919 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 920 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 921 __le16 event_id; 922 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL 923 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 924 __le32 event_data2; 925 u8 opaque_v; 926 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL 927 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL 928 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 929 u8 timestamp_lo; 930 __le16 timestamp_hi; 931 __le32 event_data1; 932 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL 933 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0 934 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL 935 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL 936 }; 937 938 /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */ 939 struct hwrm_async_event_cmpl_ring_monitor_msg { 940 __le16 type; 941 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK 0x3fUL 942 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0 943 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 0x2eUL 944 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 945 __le16 event_id; 946 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL 947 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 948 __le32 event_data2; 949 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL 950 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0 951 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX 0x0UL 952 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX 0x1UL 953 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 0x2UL 954 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 955 u8 opaque_v; 956 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V 0x1UL 957 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL 958 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1 959 u8 timestamp_lo; 960 __le16 timestamp_hi; 961 __le32 event_data1; 962 }; 963 964 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 965 struct hwrm_async_event_cmpl_vf_cfg_change { 966 __le16 type; 967 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 968 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 969 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 970 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 971 __le16 event_id; 972 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 973 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 974 __le32 event_data2; 975 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK 0xffffUL 976 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0 977 u8 opaque_v; 978 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 979 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 980 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 981 u8 timestamp_lo; 982 __le16 timestamp_hi; 983 __le32 event_data1; 984 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 985 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 986 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 987 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 988 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 989 }; 990 991 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ 992 struct hwrm_async_event_cmpl_default_vnic_change { 993 __le16 type; 994 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL 995 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0 996 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 997 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 998 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL 999 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6 1000 __le16 event_id; 1001 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL 1002 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 1003 __le32 event_data2; 1004 u8 opaque_v; 1005 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL 1006 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL 1007 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1 1008 u8 timestamp_lo; 1009 __le16 timestamp_hi; 1010 __le32 event_data1; 1011 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL 1012 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0 1013 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL 1014 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL 1015 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 1016 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL 1017 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2 1018 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL 1019 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10 1020 }; 1021 1022 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ 1023 struct hwrm_async_event_cmpl_hw_flow_aged { 1024 __le16 type; 1025 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL 1026 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 1027 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1028 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 1029 __le16 event_id; 1030 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL 1031 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 1032 __le32 event_data2; 1033 u8 opaque_v; 1034 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL 1035 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL 1036 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 1037 u8 timestamp_lo; 1038 __le16 timestamp_hi; 1039 __le32 event_data1; 1040 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL 1041 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0 1042 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL 1043 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31) 1044 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31) 1045 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX 1046 }; 1047 1048 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ 1049 struct hwrm_async_event_cmpl_eem_cache_flush_req { 1050 __le16 type; 1051 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL 1052 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0 1053 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1054 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 1055 __le16 event_id; 1056 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 1057 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 1058 __le32 event_data2; 1059 u8 opaque_v; 1060 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL 1061 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL 1062 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 1063 u8 timestamp_lo; 1064 __le16 timestamp_hi; 1065 __le32 event_data1; 1066 }; 1067 1068 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ 1069 struct hwrm_async_event_cmpl_eem_cache_flush_done { 1070 __le16 type; 1071 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL 1072 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0 1073 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1074 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 1075 __le16 event_id; 1076 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 1077 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 1078 __le32 event_data2; 1079 u8 opaque_v; 1080 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL 1081 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL 1082 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 1083 u8 timestamp_lo; 1084 __le16 timestamp_hi; 1085 __le32 event_data1; 1086 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL 1087 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0 1088 }; 1089 1090 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ 1091 struct hwrm_async_event_cmpl_deferred_response { 1092 __le16 type; 1093 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK 0x3fUL 1094 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0 1095 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1096 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 1097 __le16 event_id; 1098 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL 1099 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 1100 __le32 event_data2; 1101 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL 1102 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0 1103 u8 opaque_v; 1104 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V 0x1UL 1105 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL 1106 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1 1107 u8 timestamp_lo; 1108 __le16 timestamp_hi; 1109 __le32 event_data1; 1110 }; 1111 1112 /* hwrm_async_event_cmpl_echo_request (size:128b/16B) */ 1113 struct hwrm_async_event_cmpl_echo_request { 1114 __le16 type; 1115 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK 0x3fUL 1116 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0 1117 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1118 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 1119 __le16 event_id; 1120 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 0x42UL 1121 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 1122 __le32 event_data2; 1123 u8 opaque_v; 1124 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_V 0x1UL 1125 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK 0xfeUL 1126 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1 1127 u8 timestamp_lo; 1128 __le16 timestamp_hi; 1129 __le32 event_data1; 1130 }; 1131 1132 /* hwrm_async_event_cmpl_phc_update (size:128b/16B) */ 1133 struct hwrm_async_event_cmpl_phc_update { 1134 __le16 type; 1135 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_MASK 0x3fUL 1136 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_SFT 0 1137 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1138 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT 1139 __le16 event_id; 1140 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 0x43UL 1141 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 1142 __le32 event_data2; 1143 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_MASK 0xffffUL 1144 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_SFT 0 1145 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_MASK 0xffff0000UL 1146 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_SFT 16 1147 u8 opaque_v; 1148 #define ASYNC_EVENT_CMPL_PHC_UPDATE_V 0x1UL 1149 #define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_MASK 0xfeUL 1150 #define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_SFT 1 1151 u8 timestamp_lo; 1152 __le16 timestamp_hi; 1153 __le32 event_data1; 1154 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK 0xfUL 1155 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT 0 1156 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_MASTER 0x1UL 1157 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_SECONDARY 0x2UL 1158 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_FAILOVER 0x3UL 1159 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE 0x4UL 1160 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE 1161 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK 0xffff0UL 1162 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT 4 1163 }; 1164 1165 /* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */ 1166 struct hwrm_async_event_cmpl_pps_timestamp { 1167 __le16 type; 1168 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK 0x3fUL 1169 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0 1170 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1171 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 1172 __le16 event_id; 1173 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 0x44UL 1174 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 1175 __le32 event_data2; 1176 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE 0x1UL 1177 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL 0x0UL 1178 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 0x1UL 1179 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 1180 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK 0xeUL 1181 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT 1 1182 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK 0xffff0UL 1183 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT 4 1184 u8 opaque_v; 1185 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V 0x1UL 1186 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK 0xfeUL 1187 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1 1188 u8 timestamp_lo; 1189 __le16 timestamp_hi; 1190 __le32 event_data1; 1191 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK 0xffffffffUL 1192 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT 0 1193 }; 1194 1195 /* hwrm_async_event_cmpl_error_report (size:128b/16B) */ 1196 struct hwrm_async_event_cmpl_error_report { 1197 __le16 type; 1198 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK 0x3fUL 1199 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0 1200 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1201 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 1202 __le16 event_id; 1203 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 0x45UL 1204 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 1205 __le32 event_data2; 1206 u8 opaque_v; 1207 #define ASYNC_EVENT_CMPL_ERROR_REPORT_V 0x1UL 1208 #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK 0xfeUL 1209 #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1 1210 u8 timestamp_lo; 1211 __le16 timestamp_hi; 1212 __le32 event_data1; 1213 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1214 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0 1215 }; 1216 1217 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */ 1218 struct hwrm_async_event_cmpl_hwrm_error { 1219 __le16 type; 1220 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL 1221 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 1222 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1223 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 1224 __le16 event_id; 1225 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL 1226 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 1227 __le32 event_data2; 1228 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL 1229 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 1230 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL 1231 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL 1232 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL 1233 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 1234 u8 opaque_v; 1235 #define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL 1236 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL 1237 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 1238 u8 timestamp_lo; 1239 __le16 timestamp_hi; 1240 __le32 event_data1; 1241 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL 1242 }; 1243 1244 /* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */ 1245 struct hwrm_async_event_cmpl_error_report_base { 1246 __le16 type; 1247 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK 0x3fUL 1248 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0 1249 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1250 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 1251 __le16 event_id; 1252 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 0x45UL 1253 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 1254 __le32 event_data2; 1255 u8 opaque_v; 1256 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V 0x1UL 1257 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK 0xfeUL 1258 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1 1259 u8 timestamp_lo; 1260 __le16 timestamp_hi; 1261 __le32 event_data1; 1262 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1263 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT 0 1264 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED 0x0UL 1265 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 1266 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 1267 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM 0x3UL 1268 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL 1269 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD 0x5UL 1270 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD 1271 }; 1272 1273 /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ 1274 struct hwrm_async_event_cmpl_error_report_pause_storm { 1275 __le16 type; 1276 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK 0x3fUL 1277 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT 0 1278 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1279 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 1280 __le16 event_id; 1281 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 0x45UL 1282 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 1283 __le32 event_data2; 1284 u8 opaque_v; 1285 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V 0x1UL 1286 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK 0xfeUL 1287 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1 1288 u8 timestamp_lo; 1289 __le16 timestamp_hi; 1290 __le32 event_data1; 1291 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1292 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT 0 1293 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 1294 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 1295 }; 1296 1297 /* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */ 1298 struct hwrm_async_event_cmpl_error_report_invalid_signal { 1299 __le16 type; 1300 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK 0x3fUL 1301 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT 0 1302 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1303 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 1304 __le16 event_id; 1305 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 0x45UL 1306 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 1307 __le32 event_data2; 1308 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK 0xffUL 1309 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT 0 1310 u8 opaque_v; 1311 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V 0x1UL 1312 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK 0xfeUL 1313 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1 1314 u8 timestamp_lo; 1315 __le16 timestamp_hi; 1316 __le32 event_data1; 1317 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1318 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT 0 1319 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 1320 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 1321 }; 1322 1323 /* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */ 1324 struct hwrm_async_event_cmpl_error_report_nvm { 1325 __le16 type; 1326 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK 0x3fUL 1327 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0 1328 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1329 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 1330 __le16 event_id; 1331 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 0x45UL 1332 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 1333 __le32 event_data2; 1334 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK 0xffffffffUL 1335 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT 0 1336 u8 opaque_v; 1337 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V 0x1UL 1338 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK 0xfeUL 1339 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1 1340 u8 timestamp_lo; 1341 __le16 timestamp_hi; 1342 __le32 event_data1; 1343 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1344 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT 0 1345 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 0x3UL 1346 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 1347 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK 0xff00UL 1348 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT 8 1349 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE (0x1UL << 8) 1350 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE (0x2UL << 8) 1351 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE 1352 }; 1353 1354 /* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */ 1355 struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold { 1356 __le16 type; 1357 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK 0x3fUL 1358 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT 0 1359 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1360 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT 1361 __le16 event_id; 1362 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT 0x45UL 1363 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT 1364 __le32 event_data2; 1365 u8 opaque_v; 1366 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V 0x1UL 1367 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK 0xfeUL 1368 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT 1 1369 u8 timestamp_lo; 1370 __le16 timestamp_hi; 1371 __le32 event_data1; 1372 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1373 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT 0 1374 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL 1375 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 1376 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK 0xffffff00UL 1377 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT 8 1378 }; 1379 1380 /* hwrm_func_reset_input (size:192b/24B) */ 1381 struct hwrm_func_reset_input { 1382 __le16 req_type; 1383 __le16 cmpl_ring; 1384 __le16 seq_id; 1385 __le16 target_id; 1386 __le64 resp_addr; 1387 __le32 enables; 1388 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 1389 __le16 vf_id; 1390 u8 func_reset_level; 1391 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 1392 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 1393 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 1394 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 1395 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 1396 u8 unused_0; 1397 }; 1398 1399 /* hwrm_func_reset_output (size:128b/16B) */ 1400 struct hwrm_func_reset_output { 1401 __le16 error_code; 1402 __le16 req_type; 1403 __le16 seq_id; 1404 __le16 resp_len; 1405 u8 unused_0[7]; 1406 u8 valid; 1407 }; 1408 1409 /* hwrm_func_getfid_input (size:192b/24B) */ 1410 struct hwrm_func_getfid_input { 1411 __le16 req_type; 1412 __le16 cmpl_ring; 1413 __le16 seq_id; 1414 __le16 target_id; 1415 __le64 resp_addr; 1416 __le32 enables; 1417 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 1418 __le16 pci_id; 1419 u8 unused_0[2]; 1420 }; 1421 1422 /* hwrm_func_getfid_output (size:128b/16B) */ 1423 struct hwrm_func_getfid_output { 1424 __le16 error_code; 1425 __le16 req_type; 1426 __le16 seq_id; 1427 __le16 resp_len; 1428 __le16 fid; 1429 u8 unused_0[5]; 1430 u8 valid; 1431 }; 1432 1433 /* hwrm_func_vf_alloc_input (size:192b/24B) */ 1434 struct hwrm_func_vf_alloc_input { 1435 __le16 req_type; 1436 __le16 cmpl_ring; 1437 __le16 seq_id; 1438 __le16 target_id; 1439 __le64 resp_addr; 1440 __le32 enables; 1441 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 1442 __le16 first_vf_id; 1443 __le16 num_vfs; 1444 }; 1445 1446 /* hwrm_func_vf_alloc_output (size:128b/16B) */ 1447 struct hwrm_func_vf_alloc_output { 1448 __le16 error_code; 1449 __le16 req_type; 1450 __le16 seq_id; 1451 __le16 resp_len; 1452 __le16 first_vf_id; 1453 u8 unused_0[5]; 1454 u8 valid; 1455 }; 1456 1457 /* hwrm_func_vf_free_input (size:192b/24B) */ 1458 struct hwrm_func_vf_free_input { 1459 __le16 req_type; 1460 __le16 cmpl_ring; 1461 __le16 seq_id; 1462 __le16 target_id; 1463 __le64 resp_addr; 1464 __le32 enables; 1465 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 1466 __le16 first_vf_id; 1467 __le16 num_vfs; 1468 }; 1469 1470 /* hwrm_func_vf_free_output (size:128b/16B) */ 1471 struct hwrm_func_vf_free_output { 1472 __le16 error_code; 1473 __le16 req_type; 1474 __le16 seq_id; 1475 __le16 resp_len; 1476 u8 unused_0[7]; 1477 u8 valid; 1478 }; 1479 1480 /* hwrm_func_vf_cfg_input (size:448b/56B) */ 1481 struct hwrm_func_vf_cfg_input { 1482 __le16 req_type; 1483 __le16 cmpl_ring; 1484 __le16 seq_id; 1485 __le16 target_id; 1486 __le64 resp_addr; 1487 __le32 enables; 1488 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 1489 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 1490 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 1491 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 1492 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 1493 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 1494 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 1495 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 1496 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 1497 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 1498 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 1499 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 1500 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_KEY_CTXS 0x1000UL 1501 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_KEY_CTXS 0x2000UL 1502 __le16 mtu; 1503 __le16 guest_vlan; 1504 __le16 async_event_cr; 1505 u8 dflt_mac_addr[6]; 1506 __le32 flags; 1507 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 1508 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 1509 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 1510 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 1511 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 1512 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 1513 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 1514 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 1515 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x100UL 1516 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x200UL 1517 __le16 num_rsscos_ctxs; 1518 __le16 num_cmpl_rings; 1519 __le16 num_tx_rings; 1520 __le16 num_rx_rings; 1521 __le16 num_l2_ctxs; 1522 __le16 num_vnics; 1523 __le16 num_stat_ctxs; 1524 __le16 num_hw_ring_grps; 1525 __le16 num_tx_key_ctxs; 1526 __le16 num_rx_key_ctxs; 1527 }; 1528 1529 /* hwrm_func_vf_cfg_output (size:128b/16B) */ 1530 struct hwrm_func_vf_cfg_output { 1531 __le16 error_code; 1532 __le16 req_type; 1533 __le16 seq_id; 1534 __le16 resp_len; 1535 u8 unused_0[7]; 1536 u8 valid; 1537 }; 1538 1539 /* hwrm_func_qcaps_input (size:192b/24B) */ 1540 struct hwrm_func_qcaps_input { 1541 __le16 req_type; 1542 __le16 cmpl_ring; 1543 __le16 seq_id; 1544 __le16 target_id; 1545 __le64 resp_addr; 1546 __le16 fid; 1547 u8 unused_0[6]; 1548 }; 1549 1550 /* hwrm_func_qcaps_output (size:768b/96B) */ 1551 struct hwrm_func_qcaps_output { 1552 __le16 error_code; 1553 __le16 req_type; 1554 __le16 seq_id; 1555 __le16 resp_len; 1556 __le16 fid; 1557 __le16 port_id; 1558 __le32 flags; 1559 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1560 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 1561 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1562 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1563 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1564 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1565 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1566 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1567 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1568 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1569 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 1570 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 1571 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 1572 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 1573 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 1574 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 1575 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 1576 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 1577 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 1578 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 1579 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 1580 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL 1581 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL 1582 #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL 1583 #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL 1584 #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL 1585 #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL 1586 #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL 1587 #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL 1588 #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL 1589 #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL 1590 #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL 1591 u8 mac_address[6]; 1592 __le16 max_rsscos_ctx; 1593 __le16 max_cmpl_rings; 1594 __le16 max_tx_rings; 1595 __le16 max_rx_rings; 1596 __le16 max_l2_ctxs; 1597 __le16 max_vnics; 1598 __le16 first_vf_id; 1599 __le16 max_vfs; 1600 __le16 max_stat_ctx; 1601 __le32 max_encap_records; 1602 __le32 max_decap_records; 1603 __le32 max_tx_em_flows; 1604 __le32 max_tx_wm_flows; 1605 __le32 max_rx_em_flows; 1606 __le32 max_rx_wm_flows; 1607 __le32 max_mcast_filters; 1608 __le32 max_flow_id; 1609 __le32 max_hw_ring_grps; 1610 __le16 max_sp_tx_rings; 1611 __le16 max_msix_vfs; 1612 __le32 flags_ext; 1613 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL 1614 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL 1615 #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL 1616 #define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT 0x8UL 1617 #define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT 0x10UL 1618 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL 1619 #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL 1620 #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL 1621 #define FUNC_QCAPS_RESP_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED 0x100UL 1622 #define FUNC_QCAPS_RESP_FLAGS_EXT_SOC_SPD_SUPPORTED 0x200UL 1623 #define FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED 0x400UL 1624 #define FUNC_QCAPS_RESP_FLAGS_EXT_FAST_RESET_CAPABLE 0x800UL 1625 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_METADATA_CFG_CAPABLE 0x1000UL 1626 #define FUNC_QCAPS_RESP_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED 0x2000UL 1627 #define FUNC_QCAPS_RESP_FLAGS_EXT_BD_METADATA_SUPPORTED 0x4000UL 1628 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECHO_REQUEST_SUPPORTED 0x8000UL 1629 #define FUNC_QCAPS_RESP_FLAGS_EXT_NPAR_1_2_SUPPORTED 0x10000UL 1630 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PTM_SUPPORTED 0x20000UL 1631 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED 0x40000UL 1632 #define FUNC_QCAPS_RESP_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED 0x80000UL 1633 #define FUNC_QCAPS_RESP_FLAGS_EXT_PARTITION_BW_SUPPORTED 0x100000UL 1634 #define FUNC_QCAPS_RESP_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED 0x200000UL 1635 #define FUNC_QCAPS_RESP_FLAGS_EXT_KTLS_SUPPORTED 0x400000UL 1636 #define FUNC_QCAPS_RESP_FLAGS_EXT_EP_RATE_CONTROL 0x800000UL 1637 #define FUNC_QCAPS_RESP_FLAGS_EXT_MIN_BW_SUPPORTED 0x1000000UL 1638 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_COAL_CMPL_CAP 0x2000000UL 1639 #define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_SUPPORTED 0x4000000UL 1640 #define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_REQUIRED 0x8000000UL 1641 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED 0x10000000UL 1642 #define FUNC_QCAPS_RESP_FLAGS_EXT_DBR_PACING_SUPPORTED 0x20000000UL 1643 #define FUNC_QCAPS_RESP_FLAGS_EXT_HW_DBR_DROP_RECOV_SUPPORTED 0x40000000UL 1644 #define FUNC_QCAPS_RESP_FLAGS_EXT_DISABLE_CQ_OVERFLOW_DETECTION_SUPPORTED 0x80000000UL 1645 u8 max_schqs; 1646 u8 mpc_chnls_cap; 1647 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL 1648 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE 0x2UL 1649 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA 0x4UL 1650 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA 0x8UL 1651 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE 0x10UL 1652 __le16 max_key_ctxs_alloc; 1653 __le32 flags_ext2; 1654 #define FUNC_QCAPS_RESP_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED 0x1UL 1655 #define FUNC_QCAPS_RESP_FLAGS_EXT2_QUIC_SUPPORTED 0x2UL 1656 #define FUNC_QCAPS_RESP_FLAGS_EXT2_KDNET_SUPPORTED 0x4UL 1657 #define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED 0x8UL 1658 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED 0x10UL 1659 #define FUNC_QCAPS_RESP_FLAGS_EXT2_GENERIC_STATS_SUPPORTED 0x20UL 1660 __le16 tunnel_disable_flag; 1661 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN 0x1UL 1662 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NGE 0x2UL 1663 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NVGRE 0x4UL 1664 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_L2GRE 0x8UL 1665 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_GRE 0x10UL 1666 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP 0x20UL 1667 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_MPLS 0x40UL 1668 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE 0x80UL 1669 u8 unused_1; 1670 u8 valid; 1671 }; 1672 1673 /* hwrm_func_qcfg_input (size:192b/24B) */ 1674 struct hwrm_func_qcfg_input { 1675 __le16 req_type; 1676 __le16 cmpl_ring; 1677 __le16 seq_id; 1678 __le16 target_id; 1679 __le64 resp_addr; 1680 __le16 fid; 1681 u8 unused_0[6]; 1682 }; 1683 1684 /* hwrm_func_qcfg_output (size:896b/112B) */ 1685 struct hwrm_func_qcfg_output { 1686 __le16 error_code; 1687 __le16 req_type; 1688 __le16 seq_id; 1689 __le16 resp_len; 1690 __le16 fid; 1691 __le16 port_id; 1692 __le16 vlan; 1693 __le16 flags; 1694 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1695 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1696 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 1697 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 1698 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 1699 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 1700 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 1701 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL 1702 #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL 1703 #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL 1704 #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL 1705 #define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL 1706 #define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED 0x1000UL 1707 #define FUNC_QCFG_RESP_FLAGS_MULTI_ROOT 0x2000UL 1708 #define FUNC_QCFG_RESP_FLAGS_ENABLE_RDMA_SRIOV 0x4000UL 1709 u8 mac_address[6]; 1710 __le16 pci_id; 1711 __le16 alloc_rsscos_ctx; 1712 __le16 alloc_cmpl_rings; 1713 __le16 alloc_tx_rings; 1714 __le16 alloc_rx_rings; 1715 __le16 alloc_l2_ctx; 1716 __le16 alloc_vnics; 1717 __le16 admin_mtu; 1718 __le16 mru; 1719 __le16 stat_ctx_id; 1720 u8 port_partition_type; 1721 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1722 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1723 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1724 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1725 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 1726 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_2 0x5UL 1727 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 1728 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 1729 u8 port_pf_cnt; 1730 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 1731 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 1732 __le16 dflt_vnic_id; 1733 __le16 max_mtu_configured; 1734 __le32 min_bw; 1735 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1736 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 1737 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 1738 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 1739 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 1740 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 1741 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1742 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 1743 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1744 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1745 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1746 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1747 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1748 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1749 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 1750 __le32 max_bw; 1751 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1752 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 1753 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 1754 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 1755 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 1756 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 1757 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1758 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 1759 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1760 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1761 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1762 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1763 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1764 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1765 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 1766 u8 evb_mode; 1767 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 1768 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 1769 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 1770 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 1771 u8 options; 1772 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1773 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 1774 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1775 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1776 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 1777 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1778 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 1779 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1780 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1781 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1782 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 1783 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 1784 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 1785 __le16 alloc_vfs; 1786 __le32 alloc_mcast_filters; 1787 __le32 alloc_hw_ring_grps; 1788 __le16 alloc_sp_tx_rings; 1789 __le16 alloc_stat_ctx; 1790 __le16 alloc_msix; 1791 __le16 registered_vfs; 1792 __le16 l2_doorbell_bar_size_kb; 1793 u8 unused_1; 1794 u8 always_1; 1795 __le32 reset_addr_poll; 1796 __le16 legacy_l2_db_size_kb; 1797 __le16 svif_info; 1798 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL 1799 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0 1800 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL 1801 u8 mpc_chnls; 1802 #define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED 0x1UL 1803 #define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED 0x2UL 1804 #define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL 1805 #define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL 1806 #define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL 1807 u8 unused_2[3]; 1808 __le32 partition_min_bw; 1809 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1810 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_SFT 0 1811 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE 0x10000000UL 1812 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 1813 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 1814 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES 1815 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1816 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 1817 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1818 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 1819 __le32 partition_max_bw; 1820 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1821 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_SFT 0 1822 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE 0x10000000UL 1823 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 1824 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 1825 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES 1826 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1827 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 1828 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1829 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 1830 __le16 host_mtu; 1831 __le16 alloc_tx_key_ctxs; 1832 __le16 alloc_rx_key_ctxs; 1833 u8 port_kdnet_mode; 1834 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_DISABLED 0x0UL 1835 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED 0x1UL 1836 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_LAST FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED 1837 u8 kdnet_pcie_function; 1838 __le16 port_kdnet_fid; 1839 u8 unused_3; 1840 u8 valid; 1841 }; 1842 1843 /* hwrm_func_cfg_input (size:960b/120B) */ 1844 struct hwrm_func_cfg_input { 1845 __le16 req_type; 1846 __le16 cmpl_ring; 1847 __le16 seq_id; 1848 __le16 target_id; 1849 __le64 resp_addr; 1850 __le16 fid; 1851 __le16 num_msix; 1852 __le32 flags; 1853 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 1854 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 1855 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 1856 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 1857 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 1858 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 1859 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 1860 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 1861 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 1862 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 1863 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 1864 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 1865 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 1866 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 1867 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 1868 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 1869 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 1870 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL 1871 #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL 1872 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL 1873 #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL 1874 #define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS 0x4000000UL 1875 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x8000000UL 1876 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL 1877 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_ENABLE 0x20000000UL 1878 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_DISABLE 0x40000000UL 1879 __le32 enables; 1880 #define FUNC_CFG_REQ_ENABLES_ADMIN_MTU 0x1UL 1881 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1882 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1883 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1884 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1885 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1886 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1887 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1888 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1889 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1890 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1891 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1892 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1893 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1894 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1895 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1896 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1897 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1898 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1899 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1900 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 1901 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 1902 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 1903 #define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL 1904 #define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL 1905 #define FUNC_CFG_REQ_ENABLES_MPC_CHNLS 0x2000000UL 1906 #define FUNC_CFG_REQ_ENABLES_PARTITION_MIN_BW 0x4000000UL 1907 #define FUNC_CFG_REQ_ENABLES_PARTITION_MAX_BW 0x8000000UL 1908 #define FUNC_CFG_REQ_ENABLES_TPID 0x10000000UL 1909 #define FUNC_CFG_REQ_ENABLES_HOST_MTU 0x20000000UL 1910 #define FUNC_CFG_REQ_ENABLES_TX_KEY_CTXS 0x40000000UL 1911 #define FUNC_CFG_REQ_ENABLES_RX_KEY_CTXS 0x80000000UL 1912 __le16 admin_mtu; 1913 __le16 mru; 1914 __le16 num_rsscos_ctxs; 1915 __le16 num_cmpl_rings; 1916 __le16 num_tx_rings; 1917 __le16 num_rx_rings; 1918 __le16 num_l2_ctxs; 1919 __le16 num_vnics; 1920 __le16 num_stat_ctxs; 1921 __le16 num_hw_ring_grps; 1922 u8 dflt_mac_addr[6]; 1923 __le16 dflt_vlan; 1924 __be32 dflt_ip_addr[4]; 1925 __le32 min_bw; 1926 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1927 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 1928 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 1929 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 1930 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 1931 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 1932 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1933 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 1934 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1935 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1936 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1937 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1938 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1939 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1940 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1941 __le32 max_bw; 1942 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1943 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1944 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1945 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1946 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1947 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1948 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1949 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1950 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1951 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1952 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1953 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1954 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1955 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1956 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1957 __le16 async_event_cr; 1958 u8 vlan_antispoof_mode; 1959 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1960 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1961 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1962 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1963 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 1964 u8 allowed_vlan_pris; 1965 u8 evb_mode; 1966 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1967 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1968 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1969 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 1970 u8 options; 1971 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1972 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 1973 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1974 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1975 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 1976 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1977 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 1978 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1979 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1980 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1981 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 1982 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 1983 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 1984 __le16 num_mcast_filters; 1985 __le16 schq_id; 1986 __le16 mpc_chnls; 1987 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE 0x1UL 1988 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE 0x2UL 1989 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE 0x4UL 1990 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE 0x8UL 1991 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE 0x10UL 1992 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE 0x20UL 1993 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE 0x40UL 1994 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE 0x80UL 1995 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE 0x100UL 1996 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE 0x200UL 1997 __le32 partition_min_bw; 1998 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1999 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_SFT 0 2000 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE 0x10000000UL 2001 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 2002 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 2003 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES 2004 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2005 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 2006 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2007 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 2008 __le32 partition_max_bw; 2009 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2010 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_SFT 0 2011 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE 0x10000000UL 2012 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 2013 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 2014 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES 2015 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2016 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 2017 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2018 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 2019 __be16 tpid; 2020 __le16 host_mtu; 2021 __le16 num_tx_key_ctxs; 2022 __le16 num_rx_key_ctxs; 2023 __le32 enables2; 2024 #define FUNC_CFG_REQ_ENABLES2_KDNET 0x1UL 2025 u8 port_kdnet_mode; 2026 #define FUNC_CFG_REQ_PORT_KDNET_MODE_DISABLED 0x0UL 2027 #define FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED 0x1UL 2028 #define FUNC_CFG_REQ_PORT_KDNET_MODE_LAST FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED 2029 u8 unused_0[7]; 2030 }; 2031 2032 /* hwrm_func_cfg_output (size:128b/16B) */ 2033 struct hwrm_func_cfg_output { 2034 __le16 error_code; 2035 __le16 req_type; 2036 __le16 seq_id; 2037 __le16 resp_len; 2038 u8 unused_0[7]; 2039 u8 valid; 2040 }; 2041 2042 /* hwrm_func_cfg_cmd_err (size:64b/8B) */ 2043 struct hwrm_func_cfg_cmd_err { 2044 u8 code; 2045 #define FUNC_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 2046 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_RANGE 0x1UL 2047 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_MORE_THAN_MAX 0x2UL 2048 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_UNSUPPORTED 0x3UL 2049 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT 0x4UL 2050 #define FUNC_CFG_CMD_ERR_CODE_LAST FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT 2051 u8 unused_0[7]; 2052 }; 2053 2054 /* hwrm_func_qstats_input (size:192b/24B) */ 2055 struct hwrm_func_qstats_input { 2056 __le16 req_type; 2057 __le16 cmpl_ring; 2058 __le16 seq_id; 2059 __le16 target_id; 2060 __le64 resp_addr; 2061 __le16 fid; 2062 u8 flags; 2063 #define FUNC_QSTATS_REQ_FLAGS_UNUSED 0x0UL 2064 #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL 2065 #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL 2066 #define FUNC_QSTATS_REQ_FLAGS_LAST FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 2067 u8 unused_0[5]; 2068 }; 2069 2070 /* hwrm_func_qstats_output (size:1408b/176B) */ 2071 struct hwrm_func_qstats_output { 2072 __le16 error_code; 2073 __le16 req_type; 2074 __le16 seq_id; 2075 __le16 resp_len; 2076 __le64 tx_ucast_pkts; 2077 __le64 tx_mcast_pkts; 2078 __le64 tx_bcast_pkts; 2079 __le64 tx_discard_pkts; 2080 __le64 tx_drop_pkts; 2081 __le64 tx_ucast_bytes; 2082 __le64 tx_mcast_bytes; 2083 __le64 tx_bcast_bytes; 2084 __le64 rx_ucast_pkts; 2085 __le64 rx_mcast_pkts; 2086 __le64 rx_bcast_pkts; 2087 __le64 rx_discard_pkts; 2088 __le64 rx_drop_pkts; 2089 __le64 rx_ucast_bytes; 2090 __le64 rx_mcast_bytes; 2091 __le64 rx_bcast_bytes; 2092 __le64 rx_agg_pkts; 2093 __le64 rx_agg_bytes; 2094 __le64 rx_agg_events; 2095 __le64 rx_agg_aborts; 2096 u8 unused_0[7]; 2097 u8 valid; 2098 }; 2099 2100 /* hwrm_func_qstats_ext_input (size:256b/32B) */ 2101 struct hwrm_func_qstats_ext_input { 2102 __le16 req_type; 2103 __le16 cmpl_ring; 2104 __le16 seq_id; 2105 __le16 target_id; 2106 __le64 resp_addr; 2107 __le16 fid; 2108 u8 flags; 2109 #define FUNC_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 2110 #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL 2111 #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL 2112 #define FUNC_QSTATS_EXT_REQ_FLAGS_LAST FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 2113 u8 unused_0[1]; 2114 __le32 enables; 2115 #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL 2116 __le16 schq_id; 2117 __le16 traffic_class; 2118 u8 unused_1[4]; 2119 }; 2120 2121 /* hwrm_func_qstats_ext_output (size:1536b/192B) */ 2122 struct hwrm_func_qstats_ext_output { 2123 __le16 error_code; 2124 __le16 req_type; 2125 __le16 seq_id; 2126 __le16 resp_len; 2127 __le64 rx_ucast_pkts; 2128 __le64 rx_mcast_pkts; 2129 __le64 rx_bcast_pkts; 2130 __le64 rx_discard_pkts; 2131 __le64 rx_error_pkts; 2132 __le64 rx_ucast_bytes; 2133 __le64 rx_mcast_bytes; 2134 __le64 rx_bcast_bytes; 2135 __le64 tx_ucast_pkts; 2136 __le64 tx_mcast_pkts; 2137 __le64 tx_bcast_pkts; 2138 __le64 tx_error_pkts; 2139 __le64 tx_discard_pkts; 2140 __le64 tx_ucast_bytes; 2141 __le64 tx_mcast_bytes; 2142 __le64 tx_bcast_bytes; 2143 __le64 rx_tpa_eligible_pkt; 2144 __le64 rx_tpa_eligible_bytes; 2145 __le64 rx_tpa_pkt; 2146 __le64 rx_tpa_bytes; 2147 __le64 rx_tpa_errors; 2148 __le64 rx_tpa_events; 2149 u8 unused_0[7]; 2150 u8 valid; 2151 }; 2152 2153 /* hwrm_func_clr_stats_input (size:192b/24B) */ 2154 struct hwrm_func_clr_stats_input { 2155 __le16 req_type; 2156 __le16 cmpl_ring; 2157 __le16 seq_id; 2158 __le16 target_id; 2159 __le64 resp_addr; 2160 __le16 fid; 2161 u8 unused_0[6]; 2162 }; 2163 2164 /* hwrm_func_clr_stats_output (size:128b/16B) */ 2165 struct hwrm_func_clr_stats_output { 2166 __le16 error_code; 2167 __le16 req_type; 2168 __le16 seq_id; 2169 __le16 resp_len; 2170 u8 unused_0[7]; 2171 u8 valid; 2172 }; 2173 2174 /* hwrm_func_vf_resc_free_input (size:192b/24B) */ 2175 struct hwrm_func_vf_resc_free_input { 2176 __le16 req_type; 2177 __le16 cmpl_ring; 2178 __le16 seq_id; 2179 __le16 target_id; 2180 __le64 resp_addr; 2181 __le16 vf_id; 2182 u8 unused_0[6]; 2183 }; 2184 2185 /* hwrm_func_vf_resc_free_output (size:128b/16B) */ 2186 struct hwrm_func_vf_resc_free_output { 2187 __le16 error_code; 2188 __le16 req_type; 2189 __le16 seq_id; 2190 __le16 resp_len; 2191 u8 unused_0[7]; 2192 u8 valid; 2193 }; 2194 2195 /* hwrm_func_drv_rgtr_input (size:896b/112B) */ 2196 struct hwrm_func_drv_rgtr_input { 2197 __le16 req_type; 2198 __le16 cmpl_ring; 2199 __le16 seq_id; 2200 __le16 target_id; 2201 __le64 resp_addr; 2202 __le32 flags; 2203 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 2204 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 2205 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 2206 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 2207 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 2208 #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL 2209 #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL 2210 #define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT 0x80UL 2211 #define FUNC_DRV_RGTR_REQ_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT 0x100UL 2212 #define FUNC_DRV_RGTR_REQ_FLAGS_NPAR_1_2_SUPPORT 0x200UL 2213 __le32 enables; 2214 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 2215 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 2216 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 2217 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 2218 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 2219 __le16 os_type; 2220 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 2221 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 2222 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 2223 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 2224 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 2225 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 2226 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 2227 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 2228 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 2229 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 2230 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 2231 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 2232 u8 ver_maj_8b; 2233 u8 ver_min_8b; 2234 u8 ver_upd_8b; 2235 u8 unused_0[3]; 2236 __le32 timestamp; 2237 u8 unused_1[4]; 2238 __le32 vf_req_fwd[8]; 2239 __le32 async_event_fwd[8]; 2240 __le16 ver_maj; 2241 __le16 ver_min; 2242 __le16 ver_upd; 2243 __le16 ver_patch; 2244 }; 2245 2246 /* hwrm_func_drv_rgtr_output (size:128b/16B) */ 2247 struct hwrm_func_drv_rgtr_output { 2248 __le16 error_code; 2249 __le16 req_type; 2250 __le16 seq_id; 2251 __le16 resp_len; 2252 __le32 flags; 2253 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 2254 u8 unused_0[3]; 2255 u8 valid; 2256 }; 2257 2258 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 2259 struct hwrm_func_drv_unrgtr_input { 2260 __le16 req_type; 2261 __le16 cmpl_ring; 2262 __le16 seq_id; 2263 __le16 target_id; 2264 __le64 resp_addr; 2265 __le32 flags; 2266 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 2267 u8 unused_0[4]; 2268 }; 2269 2270 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 2271 struct hwrm_func_drv_unrgtr_output { 2272 __le16 error_code; 2273 __le16 req_type; 2274 __le16 seq_id; 2275 __le16 resp_len; 2276 u8 unused_0[7]; 2277 u8 valid; 2278 }; 2279 2280 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 2281 struct hwrm_func_buf_rgtr_input { 2282 __le16 req_type; 2283 __le16 cmpl_ring; 2284 __le16 seq_id; 2285 __le16 target_id; 2286 __le64 resp_addr; 2287 __le32 enables; 2288 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 2289 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 2290 __le16 vf_id; 2291 __le16 req_buf_num_pages; 2292 __le16 req_buf_page_size; 2293 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 2294 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 2295 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 2296 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 2297 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 2298 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 2299 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 2300 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 2301 __le16 req_buf_len; 2302 __le16 resp_buf_len; 2303 u8 unused_0[2]; 2304 __le64 req_buf_page_addr0; 2305 __le64 req_buf_page_addr1; 2306 __le64 req_buf_page_addr2; 2307 __le64 req_buf_page_addr3; 2308 __le64 req_buf_page_addr4; 2309 __le64 req_buf_page_addr5; 2310 __le64 req_buf_page_addr6; 2311 __le64 req_buf_page_addr7; 2312 __le64 req_buf_page_addr8; 2313 __le64 req_buf_page_addr9; 2314 __le64 error_buf_addr; 2315 __le64 resp_buf_addr; 2316 }; 2317 2318 /* hwrm_func_buf_rgtr_output (size:128b/16B) */ 2319 struct hwrm_func_buf_rgtr_output { 2320 __le16 error_code; 2321 __le16 req_type; 2322 __le16 seq_id; 2323 __le16 resp_len; 2324 u8 unused_0[7]; 2325 u8 valid; 2326 }; 2327 2328 /* hwrm_func_drv_qver_input (size:192b/24B) */ 2329 struct hwrm_func_drv_qver_input { 2330 __le16 req_type; 2331 __le16 cmpl_ring; 2332 __le16 seq_id; 2333 __le16 target_id; 2334 __le64 resp_addr; 2335 __le32 reserved; 2336 __le16 fid; 2337 u8 unused_0[2]; 2338 }; 2339 2340 /* hwrm_func_drv_qver_output (size:256b/32B) */ 2341 struct hwrm_func_drv_qver_output { 2342 __le16 error_code; 2343 __le16 req_type; 2344 __le16 seq_id; 2345 __le16 resp_len; 2346 __le16 os_type; 2347 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 2348 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 2349 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 2350 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 2351 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 2352 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 2353 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 2354 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 2355 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 2356 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 2357 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 2358 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 2359 u8 ver_maj_8b; 2360 u8 ver_min_8b; 2361 u8 ver_upd_8b; 2362 u8 unused_0[3]; 2363 __le16 ver_maj; 2364 __le16 ver_min; 2365 __le16 ver_upd; 2366 __le16 ver_patch; 2367 u8 unused_1[7]; 2368 u8 valid; 2369 }; 2370 2371 /* hwrm_func_resource_qcaps_input (size:192b/24B) */ 2372 struct hwrm_func_resource_qcaps_input { 2373 __le16 req_type; 2374 __le16 cmpl_ring; 2375 __le16 seq_id; 2376 __le16 target_id; 2377 __le64 resp_addr; 2378 __le16 fid; 2379 u8 unused_0[6]; 2380 }; 2381 2382 /* hwrm_func_resource_qcaps_output (size:512b/64B) */ 2383 struct hwrm_func_resource_qcaps_output { 2384 __le16 error_code; 2385 __le16 req_type; 2386 __le16 seq_id; 2387 __le16 resp_len; 2388 __le16 max_vfs; 2389 __le16 max_msix; 2390 __le16 vf_reservation_strategy; 2391 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 2392 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 2393 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 2394 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 2395 __le16 min_rsscos_ctx; 2396 __le16 max_rsscos_ctx; 2397 __le16 min_cmpl_rings; 2398 __le16 max_cmpl_rings; 2399 __le16 min_tx_rings; 2400 __le16 max_tx_rings; 2401 __le16 min_rx_rings; 2402 __le16 max_rx_rings; 2403 __le16 min_l2_ctxs; 2404 __le16 max_l2_ctxs; 2405 __le16 min_vnics; 2406 __le16 max_vnics; 2407 __le16 min_stat_ctx; 2408 __le16 max_stat_ctx; 2409 __le16 min_hw_ring_grps; 2410 __le16 max_hw_ring_grps; 2411 __le16 max_tx_scheduler_inputs; 2412 __le16 flags; 2413 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 2414 __le16 min_tx_key_ctxs; 2415 __le16 max_tx_key_ctxs; 2416 __le16 min_rx_key_ctxs; 2417 __le16 max_rx_key_ctxs; 2418 u8 unused_0[5]; 2419 u8 valid; 2420 }; 2421 2422 /* hwrm_func_vf_resource_cfg_input (size:512b/64B) */ 2423 struct hwrm_func_vf_resource_cfg_input { 2424 __le16 req_type; 2425 __le16 cmpl_ring; 2426 __le16 seq_id; 2427 __le16 target_id; 2428 __le64 resp_addr; 2429 __le16 vf_id; 2430 __le16 max_msix; 2431 __le16 min_rsscos_ctx; 2432 __le16 max_rsscos_ctx; 2433 __le16 min_cmpl_rings; 2434 __le16 max_cmpl_rings; 2435 __le16 min_tx_rings; 2436 __le16 max_tx_rings; 2437 __le16 min_rx_rings; 2438 __le16 max_rx_rings; 2439 __le16 min_l2_ctxs; 2440 __le16 max_l2_ctxs; 2441 __le16 min_vnics; 2442 __le16 max_vnics; 2443 __le16 min_stat_ctx; 2444 __le16 max_stat_ctx; 2445 __le16 min_hw_ring_grps; 2446 __le16 max_hw_ring_grps; 2447 __le16 flags; 2448 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 2449 __le16 min_tx_key_ctxs; 2450 __le16 max_tx_key_ctxs; 2451 __le16 min_rx_key_ctxs; 2452 __le16 max_rx_key_ctxs; 2453 u8 unused_0[2]; 2454 }; 2455 2456 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ 2457 struct hwrm_func_vf_resource_cfg_output { 2458 __le16 error_code; 2459 __le16 req_type; 2460 __le16 seq_id; 2461 __le16 resp_len; 2462 __le16 reserved_rsscos_ctx; 2463 __le16 reserved_cmpl_rings; 2464 __le16 reserved_tx_rings; 2465 __le16 reserved_rx_rings; 2466 __le16 reserved_l2_ctxs; 2467 __le16 reserved_vnics; 2468 __le16 reserved_stat_ctx; 2469 __le16 reserved_hw_ring_grps; 2470 __le16 reserved_tx_key_ctxs; 2471 __le16 reserved_rx_key_ctxs; 2472 u8 unused_0[3]; 2473 u8 valid; 2474 }; 2475 2476 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 2477 struct hwrm_func_backing_store_qcaps_input { 2478 __le16 req_type; 2479 __le16 cmpl_ring; 2480 __le16 seq_id; 2481 __le16 target_id; 2482 __le64 resp_addr; 2483 }; 2484 2485 /* hwrm_func_backing_store_qcaps_output (size:832b/104B) */ 2486 struct hwrm_func_backing_store_qcaps_output { 2487 __le16 error_code; 2488 __le16 req_type; 2489 __le16 seq_id; 2490 __le16 resp_len; 2491 __le32 qp_max_entries; 2492 __le16 qp_min_qp1_entries; 2493 __le16 qp_max_l2_entries; 2494 __le16 qp_entry_size; 2495 __le16 srq_max_l2_entries; 2496 __le32 srq_max_entries; 2497 __le16 srq_entry_size; 2498 __le16 cq_max_l2_entries; 2499 __le32 cq_max_entries; 2500 __le16 cq_entry_size; 2501 __le16 vnic_max_vnic_entries; 2502 __le16 vnic_max_ring_table_entries; 2503 __le16 vnic_entry_size; 2504 __le32 stat_max_entries; 2505 __le16 stat_entry_size; 2506 __le16 tqm_entry_size; 2507 __le32 tqm_min_entries_per_ring; 2508 __le32 tqm_max_entries_per_ring; 2509 __le32 mrav_max_entries; 2510 __le16 mrav_entry_size; 2511 __le16 tim_entry_size; 2512 __le32 tim_max_entries; 2513 __le16 mrav_num_entries_units; 2514 u8 tqm_entries_multiple; 2515 u8 ctx_kind_initializer; 2516 __le16 ctx_init_mask; 2517 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_QP 0x1UL 2518 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_SRQ 0x2UL 2519 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_CQ 0x4UL 2520 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_VNIC 0x8UL 2521 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_STAT 0x10UL 2522 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_MRAV 0x20UL 2523 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_TKC 0x40UL 2524 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_RKC 0x80UL 2525 u8 qp_init_offset; 2526 u8 srq_init_offset; 2527 u8 cq_init_offset; 2528 u8 vnic_init_offset; 2529 u8 tqm_fp_rings_count; 2530 u8 stat_init_offset; 2531 u8 mrav_init_offset; 2532 u8 tqm_fp_rings_count_ext; 2533 u8 tkc_init_offset; 2534 u8 rkc_init_offset; 2535 __le16 tkc_entry_size; 2536 __le16 rkc_entry_size; 2537 __le32 tkc_max_entries; 2538 __le32 rkc_max_entries; 2539 u8 rsvd1[7]; 2540 u8 valid; 2541 }; 2542 2543 /* tqm_fp_ring_cfg (size:128b/16B) */ 2544 struct tqm_fp_ring_cfg { 2545 u8 tqm_ring_pg_size_tqm_ring_lvl; 2546 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK 0xfUL 2547 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0 2548 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 0x0UL 2549 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 0x1UL 2550 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 0x2UL 2551 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 2552 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK 0xf0UL 2553 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4 2554 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2555 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2556 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2557 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2558 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2559 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2560 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G 2561 u8 unused[3]; 2562 __le32 tqm_ring_num_entries; 2563 __le64 tqm_ring_page_dir; 2564 }; 2565 2566 /* hwrm_func_backing_store_cfg_input (size:2688b/336B) */ 2567 struct hwrm_func_backing_store_cfg_input { 2568 __le16 req_type; 2569 __le16 cmpl_ring; 2570 __le16 seq_id; 2571 __le16 target_id; 2572 __le64 resp_addr; 2573 __le32 flags; 2574 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 2575 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL 2576 __le32 enables; 2577 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 2578 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 2579 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 2580 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 2581 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 2582 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 2583 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 2584 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 2585 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 2586 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 2587 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 2588 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 2589 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 2590 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 2591 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 2592 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 2593 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING8 0x10000UL 2594 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING9 0x20000UL 2595 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING10 0x40000UL 2596 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TKC 0x80000UL 2597 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_RKC 0x100000UL 2598 u8 qpc_pg_size_qpc_lvl; 2599 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 2600 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 2601 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 2602 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 2603 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 2604 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 2605 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 2606 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 2607 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 2608 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 2609 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 2610 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 2611 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 2612 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 2613 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 2614 u8 srq_pg_size_srq_lvl; 2615 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 2616 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 2617 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 2618 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 2619 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 2620 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 2621 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 2622 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 2623 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 2624 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 2625 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 2626 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 2627 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 2628 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 2629 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 2630 u8 cq_pg_size_cq_lvl; 2631 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 2632 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 2633 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 2634 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 2635 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 2636 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 2637 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 2638 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 2639 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 2640 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 2641 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 2642 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 2643 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 2644 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 2645 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 2646 u8 vnic_pg_size_vnic_lvl; 2647 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 2648 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 2649 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 2650 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 2651 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 2652 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 2653 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 2654 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 2655 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 2656 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 2657 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 2658 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 2659 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 2660 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 2661 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 2662 u8 stat_pg_size_stat_lvl; 2663 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 2664 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 2665 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 2666 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 2667 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 2668 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 2669 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 2670 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 2671 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 2672 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 2673 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 2674 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 2675 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 2676 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 2677 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 2678 u8 tqm_sp_pg_size_tqm_sp_lvl; 2679 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 2680 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 2681 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 2682 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 2683 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 2684 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 2685 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 2686 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 2687 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 2688 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 2689 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 2690 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 2691 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 2692 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 2693 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 2694 u8 tqm_ring0_pg_size_tqm_ring0_lvl; 2695 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 2696 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 2697 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 2698 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 2699 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 2700 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 2701 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 2702 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 2703 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 2704 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 2705 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 2706 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 2707 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 2708 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 2709 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 2710 u8 tqm_ring1_pg_size_tqm_ring1_lvl; 2711 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 2712 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 2713 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 2714 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 2715 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 2716 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 2717 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 2718 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 2719 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 2720 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 2721 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 2722 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 2723 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 2724 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 2725 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 2726 u8 tqm_ring2_pg_size_tqm_ring2_lvl; 2727 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 2728 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 2729 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 2730 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 2731 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 2732 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 2733 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 2734 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 2735 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 2736 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 2737 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 2738 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 2739 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 2740 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 2741 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 2742 u8 tqm_ring3_pg_size_tqm_ring3_lvl; 2743 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 2744 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 2745 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 2746 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 2747 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 2748 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 2749 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 2750 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 2751 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 2752 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 2753 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 2754 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 2755 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 2756 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 2757 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 2758 u8 tqm_ring4_pg_size_tqm_ring4_lvl; 2759 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 2760 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 2761 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 2762 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 2763 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 2764 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 2765 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 2766 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 2767 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 2768 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 2769 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 2770 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 2771 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 2772 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 2773 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 2774 u8 tqm_ring5_pg_size_tqm_ring5_lvl; 2775 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 2776 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 2777 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 2778 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 2779 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 2780 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 2781 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 2782 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 2783 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 2784 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 2785 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 2786 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 2787 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 2788 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 2789 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 2790 u8 tqm_ring6_pg_size_tqm_ring6_lvl; 2791 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 2792 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 2793 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 2794 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 2795 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 2796 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 2797 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 2798 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 2799 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 2800 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 2801 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 2802 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 2803 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 2804 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 2805 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 2806 u8 tqm_ring7_pg_size_tqm_ring7_lvl; 2807 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 2808 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 2809 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 2810 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 2811 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 2812 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 2813 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 2814 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 2815 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 2816 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 2817 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 2818 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 2819 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 2820 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 2821 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 2822 u8 mrav_pg_size_mrav_lvl; 2823 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 2824 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 2825 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 2826 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL 2827 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 2828 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 2829 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 2830 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 2831 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 2832 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 2833 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 2834 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 2835 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 2836 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 2837 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 2838 u8 tim_pg_size_tim_lvl; 2839 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 2840 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 2841 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 2842 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 2843 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 2844 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 2845 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 2846 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 2847 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 2848 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 2849 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 2850 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 2851 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 2852 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 2853 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 2854 __le64 qpc_page_dir; 2855 __le64 srq_page_dir; 2856 __le64 cq_page_dir; 2857 __le64 vnic_page_dir; 2858 __le64 stat_page_dir; 2859 __le64 tqm_sp_page_dir; 2860 __le64 tqm_ring0_page_dir; 2861 __le64 tqm_ring1_page_dir; 2862 __le64 tqm_ring2_page_dir; 2863 __le64 tqm_ring3_page_dir; 2864 __le64 tqm_ring4_page_dir; 2865 __le64 tqm_ring5_page_dir; 2866 __le64 tqm_ring6_page_dir; 2867 __le64 tqm_ring7_page_dir; 2868 __le64 mrav_page_dir; 2869 __le64 tim_page_dir; 2870 __le32 qp_num_entries; 2871 __le32 srq_num_entries; 2872 __le32 cq_num_entries; 2873 __le32 stat_num_entries; 2874 __le32 tqm_sp_num_entries; 2875 __le32 tqm_ring0_num_entries; 2876 __le32 tqm_ring1_num_entries; 2877 __le32 tqm_ring2_num_entries; 2878 __le32 tqm_ring3_num_entries; 2879 __le32 tqm_ring4_num_entries; 2880 __le32 tqm_ring5_num_entries; 2881 __le32 tqm_ring6_num_entries; 2882 __le32 tqm_ring7_num_entries; 2883 __le32 mrav_num_entries; 2884 __le32 tim_num_entries; 2885 __le16 qp_num_qp1_entries; 2886 __le16 qp_num_l2_entries; 2887 __le16 qp_entry_size; 2888 __le16 srq_num_l2_entries; 2889 __le16 srq_entry_size; 2890 __le16 cq_num_l2_entries; 2891 __le16 cq_entry_size; 2892 __le16 vnic_num_vnic_entries; 2893 __le16 vnic_num_ring_table_entries; 2894 __le16 vnic_entry_size; 2895 __le16 stat_entry_size; 2896 __le16 tqm_entry_size; 2897 __le16 mrav_entry_size; 2898 __le16 tim_entry_size; 2899 u8 tqm_ring8_pg_size_tqm_ring_lvl; 2900 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_MASK 0xfUL 2901 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_SFT 0 2902 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_0 0x0UL 2903 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_1 0x1UL 2904 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 0x2UL 2905 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 2906 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_MASK 0xf0UL 2907 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_SFT 4 2908 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2909 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2910 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2911 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2912 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2913 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2914 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G 2915 u8 ring8_unused[3]; 2916 __le32 tqm_ring8_num_entries; 2917 __le64 tqm_ring8_page_dir; 2918 u8 tqm_ring9_pg_size_tqm_ring_lvl; 2919 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_MASK 0xfUL 2920 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_SFT 0 2921 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_0 0x0UL 2922 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_1 0x1UL 2923 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 0x2UL 2924 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 2925 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_MASK 0xf0UL 2926 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_SFT 4 2927 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2928 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2929 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2930 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2931 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2932 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2933 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G 2934 u8 ring9_unused[3]; 2935 __le32 tqm_ring9_num_entries; 2936 __le64 tqm_ring9_page_dir; 2937 u8 tqm_ring10_pg_size_tqm_ring_lvl; 2938 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_MASK 0xfUL 2939 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_SFT 0 2940 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_0 0x0UL 2941 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_1 0x1UL 2942 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 0x2UL 2943 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 2944 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_MASK 0xf0UL 2945 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_SFT 4 2946 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2947 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2948 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2949 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2950 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2951 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2952 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G 2953 u8 ring10_unused[3]; 2954 __le32 tqm_ring10_num_entries; 2955 __le64 tqm_ring10_page_dir; 2956 __le32 tkc_num_entries; 2957 __le32 rkc_num_entries; 2958 __le64 tkc_page_dir; 2959 __le64 rkc_page_dir; 2960 __le16 tkc_entry_size; 2961 __le16 rkc_entry_size; 2962 u8 tkc_pg_size_tkc_lvl; 2963 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_MASK 0xfUL 2964 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_SFT 0 2965 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_0 0x0UL 2966 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_1 0x1UL 2967 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 0x2UL 2968 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 2969 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_MASK 0xf0UL 2970 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_SFT 4 2971 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_4K (0x0UL << 4) 2972 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8K (0x1UL << 4) 2973 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_64K (0x2UL << 4) 2974 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_2M (0x3UL << 4) 2975 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8M (0x4UL << 4) 2976 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G (0x5UL << 4) 2977 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G 2978 u8 rkc_pg_size_rkc_lvl; 2979 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_MASK 0xfUL 2980 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_SFT 0 2981 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_0 0x0UL 2982 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_1 0x1UL 2983 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 0x2UL 2984 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 2985 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_MASK 0xf0UL 2986 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_SFT 4 2987 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_4K (0x0UL << 4) 2988 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8K (0x1UL << 4) 2989 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_64K (0x2UL << 4) 2990 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_2M (0x3UL << 4) 2991 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8M (0x4UL << 4) 2992 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G (0x5UL << 4) 2993 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G 2994 u8 rsvd[2]; 2995 }; 2996 2997 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 2998 struct hwrm_func_backing_store_cfg_output { 2999 __le16 error_code; 3000 __le16 req_type; 3001 __le16 seq_id; 3002 __le16 resp_len; 3003 u8 unused_0[7]; 3004 u8 valid; 3005 }; 3006 3007 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */ 3008 struct hwrm_error_recovery_qcfg_input { 3009 __le16 req_type; 3010 __le16 cmpl_ring; 3011 __le16 seq_id; 3012 __le16 target_id; 3013 __le64 resp_addr; 3014 u8 unused_0[8]; 3015 }; 3016 3017 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ 3018 struct hwrm_error_recovery_qcfg_output { 3019 __le16 error_code; 3020 __le16 req_type; 3021 __le16 seq_id; 3022 __le16 resp_len; 3023 __le32 flags; 3024 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL 3025 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL 3026 __le32 driver_polling_freq; 3027 __le32 master_func_wait_period; 3028 __le32 normal_func_wait_period; 3029 __le32 master_func_wait_period_after_reset; 3030 __le32 max_bailout_time_after_reset; 3031 __le32 fw_health_status_reg; 3032 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL 3033 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0 3034 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3035 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL 3036 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL 3037 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL 3038 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 3039 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL 3040 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2 3041 __le32 fw_heartbeat_reg; 3042 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL 3043 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0 3044 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3045 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL 3046 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL 3047 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL 3048 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 3049 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL 3050 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2 3051 __le32 fw_reset_cnt_reg; 3052 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL 3053 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0 3054 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3055 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL 3056 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL 3057 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL 3058 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 3059 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL 3060 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2 3061 __le32 reset_inprogress_reg; 3062 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL 3063 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0 3064 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3065 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL 3066 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL 3067 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL 3068 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 3069 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL 3070 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2 3071 __le32 reset_inprogress_reg_mask; 3072 u8 unused_0[3]; 3073 u8 reg_array_cnt; 3074 __le32 reset_reg[16]; 3075 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL 3076 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0 3077 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3078 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL 3079 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL 3080 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL 3081 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 3082 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL 3083 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2 3084 __le32 reset_reg_val[16]; 3085 u8 delay_after_reset[16]; 3086 __le32 err_recovery_cnt_reg; 3087 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL 3088 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0 3089 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3090 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL 3091 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL 3092 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL 3093 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 3094 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL 3095 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2 3096 u8 unused_1[3]; 3097 u8 valid; 3098 }; 3099 3100 /* hwrm_func_echo_response_input (size:192b/24B) */ 3101 struct hwrm_func_echo_response_input { 3102 __le16 req_type; 3103 __le16 cmpl_ring; 3104 __le16 seq_id; 3105 __le16 target_id; 3106 __le64 resp_addr; 3107 __le32 event_data1; 3108 __le32 event_data2; 3109 }; 3110 3111 /* hwrm_func_echo_response_output (size:128b/16B) */ 3112 struct hwrm_func_echo_response_output { 3113 __le16 error_code; 3114 __le16 req_type; 3115 __le16 seq_id; 3116 __le16 resp_len; 3117 u8 unused_0[7]; 3118 u8 valid; 3119 }; 3120 3121 /* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */ 3122 struct hwrm_func_ptp_pin_qcfg_input { 3123 __le16 req_type; 3124 __le16 cmpl_ring; 3125 __le16 seq_id; 3126 __le16 target_id; 3127 __le64 resp_addr; 3128 u8 unused_0[8]; 3129 }; 3130 3131 /* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */ 3132 struct hwrm_func_ptp_pin_qcfg_output { 3133 __le16 error_code; 3134 __le16 req_type; 3135 __le16 seq_id; 3136 __le16 resp_len; 3137 u8 num_pins; 3138 u8 state; 3139 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN0_ENABLED 0x1UL 3140 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN1_ENABLED 0x2UL 3141 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN2_ENABLED 0x4UL 3142 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN3_ENABLED 0x8UL 3143 u8 pin0_usage; 3144 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_NONE 0x0UL 3145 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_IN 0x1UL 3146 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_OUT 0x2UL 3147 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_IN 0x3UL 3148 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 0x4UL 3149 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 3150 u8 pin1_usage; 3151 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_NONE 0x0UL 3152 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_IN 0x1UL 3153 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_OUT 0x2UL 3154 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_IN 0x3UL 3155 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 0x4UL 3156 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 3157 u8 pin2_usage; 3158 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_NONE 0x0UL 3159 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_IN 0x1UL 3160 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_OUT 0x2UL 3161 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_IN 0x3UL 3162 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 0x4UL 3163 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 3164 u8 pin3_usage; 3165 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_NONE 0x0UL 3166 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_IN 0x1UL 3167 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_OUT 0x2UL 3168 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_IN 0x3UL 3169 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 0x4UL 3170 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 3171 u8 unused_0; 3172 u8 valid; 3173 }; 3174 3175 /* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */ 3176 struct hwrm_func_ptp_pin_cfg_input { 3177 __le16 req_type; 3178 __le16 cmpl_ring; 3179 __le16 seq_id; 3180 __le16 target_id; 3181 __le64 resp_addr; 3182 __le32 enables; 3183 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE 0x1UL 3184 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE 0x2UL 3185 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_STATE 0x4UL 3186 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_USAGE 0x8UL 3187 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_STATE 0x10UL 3188 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_USAGE 0x20UL 3189 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_STATE 0x40UL 3190 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_USAGE 0x80UL 3191 u8 pin0_state; 3192 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_DISABLED 0x0UL 3193 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 0x1UL 3194 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 3195 u8 pin0_usage; 3196 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_NONE 0x0UL 3197 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_IN 0x1UL 3198 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_OUT 0x2UL 3199 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_IN 0x3UL 3200 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 0x4UL 3201 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 3202 u8 pin1_state; 3203 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_DISABLED 0x0UL 3204 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 0x1UL 3205 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 3206 u8 pin1_usage; 3207 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_NONE 0x0UL 3208 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_IN 0x1UL 3209 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_OUT 0x2UL 3210 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_IN 0x3UL 3211 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 0x4UL 3212 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 3213 u8 pin2_state; 3214 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_DISABLED 0x0UL 3215 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 0x1UL 3216 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 3217 u8 pin2_usage; 3218 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_NONE 0x0UL 3219 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_IN 0x1UL 3220 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_OUT 0x2UL 3221 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_IN 0x3UL 3222 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 0x4UL 3223 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 3224 u8 pin3_state; 3225 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_DISABLED 0x0UL 3226 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 0x1UL 3227 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 3228 u8 pin3_usage; 3229 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_NONE 0x0UL 3230 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_IN 0x1UL 3231 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_OUT 0x2UL 3232 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_IN 0x3UL 3233 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 0x4UL 3234 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 3235 u8 unused_0[4]; 3236 }; 3237 3238 /* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */ 3239 struct hwrm_func_ptp_pin_cfg_output { 3240 __le16 error_code; 3241 __le16 req_type; 3242 __le16 seq_id; 3243 __le16 resp_len; 3244 u8 unused_0[7]; 3245 u8 valid; 3246 }; 3247 3248 /* hwrm_func_ptp_cfg_input (size:384b/48B) */ 3249 struct hwrm_func_ptp_cfg_input { 3250 __le16 req_type; 3251 __le16 cmpl_ring; 3252 __le16 seq_id; 3253 __le16 target_id; 3254 __le64 resp_addr; 3255 __le16 enables; 3256 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT 0x1UL 3257 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE 0x2UL 3258 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_PHASE 0x4UL 3259 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD 0x8UL 3260 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP 0x10UL 3261 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE 0x20UL 3262 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME 0x40UL 3263 u8 ptp_pps_event; 3264 #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_INTERNAL 0x1UL 3265 #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_EXTERNAL 0x2UL 3266 u8 ptp_freq_adj_dll_source; 3267 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_NONE 0x0UL 3268 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 0x1UL 3269 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 0x2UL 3270 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 0x3UL 3271 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 0x4UL 3272 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 0x5UL 3273 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 0x6UL 3274 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 0x7UL 3275 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 0x8UL 3276 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 0xffUL 3277 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 3278 u8 ptp_freq_adj_dll_phase; 3279 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_NONE 0x0UL 3280 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_4K 0x1UL 3281 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_8K 0x2UL 3282 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M 0x3UL 3283 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M 3284 u8 unused_0[3]; 3285 __le32 ptp_freq_adj_ext_period; 3286 __le32 ptp_freq_adj_ext_up; 3287 __le32 ptp_freq_adj_ext_phase_lower; 3288 __le32 ptp_freq_adj_ext_phase_upper; 3289 __le64 ptp_set_time; 3290 }; 3291 3292 /* hwrm_func_ptp_cfg_output (size:128b/16B) */ 3293 struct hwrm_func_ptp_cfg_output { 3294 __le16 error_code; 3295 __le16 req_type; 3296 __le16 seq_id; 3297 __le16 resp_len; 3298 u8 unused_0[7]; 3299 u8 valid; 3300 }; 3301 3302 /* hwrm_func_ptp_ts_query_input (size:192b/24B) */ 3303 struct hwrm_func_ptp_ts_query_input { 3304 __le16 req_type; 3305 __le16 cmpl_ring; 3306 __le16 seq_id; 3307 __le16 target_id; 3308 __le64 resp_addr; 3309 __le32 flags; 3310 #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PPS_TIME 0x1UL 3311 #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PTM_TIME 0x2UL 3312 u8 unused_0[4]; 3313 }; 3314 3315 /* hwrm_func_ptp_ts_query_output (size:320b/40B) */ 3316 struct hwrm_func_ptp_ts_query_output { 3317 __le16 error_code; 3318 __le16 req_type; 3319 __le16 seq_id; 3320 __le16 resp_len; 3321 __le64 pps_event_ts; 3322 __le64 ptm_res_local_ts; 3323 __le64 ptm_pmstr_ts; 3324 __le32 ptm_mstr_prop_dly; 3325 u8 unused_0[3]; 3326 u8 valid; 3327 }; 3328 3329 /* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */ 3330 struct hwrm_func_ptp_ext_cfg_input { 3331 __le16 req_type; 3332 __le16 cmpl_ring; 3333 __le16 seq_id; 3334 __le16 target_id; 3335 __le64 resp_addr; 3336 __le16 enables; 3337 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_MASTER_FID 0x1UL 3338 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_FID 0x2UL 3339 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_MODE 0x4UL 3340 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_FAILOVER_TIMER 0x8UL 3341 __le16 phc_master_fid; 3342 __le16 phc_sec_fid; 3343 u8 phc_sec_mode; 3344 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_SWITCH 0x0UL 3345 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_ALL 0x1UL 3346 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY 0x2UL 3347 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_LAST FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY 3348 u8 unused_0; 3349 __le32 failover_timer; 3350 u8 unused_1[4]; 3351 }; 3352 3353 /* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */ 3354 struct hwrm_func_ptp_ext_cfg_output { 3355 __le16 error_code; 3356 __le16 req_type; 3357 __le16 seq_id; 3358 __le16 resp_len; 3359 u8 unused_0[7]; 3360 u8 valid; 3361 }; 3362 3363 /* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */ 3364 struct hwrm_func_ptp_ext_qcfg_input { 3365 __le16 req_type; 3366 __le16 cmpl_ring; 3367 __le16 seq_id; 3368 __le16 target_id; 3369 __le64 resp_addr; 3370 u8 unused_0[8]; 3371 }; 3372 3373 /* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */ 3374 struct hwrm_func_ptp_ext_qcfg_output { 3375 __le16 error_code; 3376 __le16 req_type; 3377 __le16 seq_id; 3378 __le16 resp_len; 3379 __le16 phc_master_fid; 3380 __le16 phc_sec_fid; 3381 __le16 phc_active_fid0; 3382 __le16 phc_active_fid1; 3383 __le32 last_failover_event; 3384 __le16 from_fid; 3385 __le16 to_fid; 3386 u8 unused_0[7]; 3387 u8 valid; 3388 }; 3389 3390 /* hwrm_func_backing_store_cfg_v2_input (size:448b/56B) */ 3391 struct hwrm_func_backing_store_cfg_v2_input { 3392 __le16 req_type; 3393 __le16 cmpl_ring; 3394 __le16 seq_id; 3395 __le16 target_id; 3396 __le64 resp_addr; 3397 __le16 type; 3398 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QP 0x0UL 3399 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ 0x1UL 3400 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ 0x2UL 3401 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_VNIC 0x3UL 3402 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_STAT 0x4UL 3403 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3404 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3405 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MRAV 0xeUL 3406 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TIM 0xfUL 3407 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TKC 0x13UL 3408 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RKC 0x14UL 3409 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3410 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3411 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3412 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3413 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3414 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QUIC_TKC 0x1aUL 3415 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QUIC_RKC 0x1bUL 3416 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 0xffffUL 3417 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 3418 __le16 instance; 3419 __le32 flags; 3420 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_PREBOOT_MODE 0x1UL 3421 __le64 page_dir; 3422 __le32 num_entries; 3423 __le16 entry_size; 3424 u8 page_size_pbl_level; 3425 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_MASK 0xfUL 3426 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_SFT 0 3427 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_0 0x0UL 3428 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_1 0x1UL 3429 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2 0x2UL 3430 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2 3431 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_MASK 0xf0UL 3432 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_SFT 4 3433 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_4K (0x0UL << 4) 3434 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8K (0x1UL << 4) 3435 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_64K (0x2UL << 4) 3436 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_2M (0x3UL << 4) 3437 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8M (0x4UL << 4) 3438 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G (0x5UL << 4) 3439 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G 3440 u8 subtype_valid_cnt; 3441 __le32 split_entry_0; 3442 __le32 split_entry_1; 3443 __le32 split_entry_2; 3444 __le32 split_entry_3; 3445 }; 3446 3447 /* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */ 3448 struct hwrm_func_backing_store_cfg_v2_output { 3449 __le16 error_code; 3450 __le16 req_type; 3451 __le16 seq_id; 3452 __le16 resp_len; 3453 u8 rsvd0[7]; 3454 u8 valid; 3455 }; 3456 3457 /* hwrm_func_backing_store_qcfg_v2_input (size:192b/24B) */ 3458 struct hwrm_func_backing_store_qcfg_v2_input { 3459 __le16 req_type; 3460 __le16 cmpl_ring; 3461 __le16 seq_id; 3462 __le16 target_id; 3463 __le64 resp_addr; 3464 __le16 type; 3465 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QP 0x0UL 3466 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ 0x1UL 3467 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ 0x2UL 3468 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_VNIC 0x3UL 3469 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_STAT 0x4UL 3470 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3471 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3472 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MRAV 0xeUL 3473 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TIM 0xfUL 3474 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TKC 0x13UL 3475 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RKC 0x14UL 3476 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3477 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3478 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3479 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3480 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3481 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QUIC_TKC 0x1aUL 3482 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QUIC_RKC 0x1bUL 3483 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 0xffffUL 3484 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 3485 __le16 instance; 3486 u8 rsvd[4]; 3487 }; 3488 3489 /* hwrm_func_backing_store_qcfg_v2_output (size:448b/56B) */ 3490 struct hwrm_func_backing_store_qcfg_v2_output { 3491 __le16 error_code; 3492 __le16 req_type; 3493 __le16 seq_id; 3494 __le16 resp_len; 3495 __le16 type; 3496 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QP 0x0UL 3497 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRQ 0x1UL 3498 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CQ 0x2UL 3499 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_VNIC 0x3UL 3500 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_STAT 0x4UL 3501 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SP_TQM_RING 0x5UL 3502 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_FP_TQM_RING 0x6UL 3503 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MRAV 0xeUL 3504 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TIM 0xfUL 3505 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TKC 0x13UL 3506 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RKC 0x14UL 3507 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MP_TQM_RING 0x15UL 3508 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QUIC_TKC 0x1aUL 3509 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QUIC_RKC 0x1bUL 3510 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 0xffffUL 3511 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 3512 __le16 instance; 3513 __le32 flags; 3514 __le64 page_dir; 3515 __le32 num_entries; 3516 u8 page_size_pbl_level; 3517 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_MASK 0xfUL 3518 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_SFT 0 3519 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_0 0x0UL 3520 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_1 0x1UL 3521 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2 0x2UL 3522 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2 3523 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_MASK 0xf0UL 3524 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_SFT 4 3525 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_4K (0x0UL << 4) 3526 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8K (0x1UL << 4) 3527 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_64K (0x2UL << 4) 3528 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_2M (0x3UL << 4) 3529 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8M (0x4UL << 4) 3530 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G (0x5UL << 4) 3531 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G 3532 u8 subtype_valid_cnt; 3533 u8 rsvd[2]; 3534 __le32 split_entry_0; 3535 __le32 split_entry_1; 3536 __le32 split_entry_2; 3537 __le32 split_entry_3; 3538 u8 rsvd2[7]; 3539 u8 valid; 3540 }; 3541 3542 /* qpc_split_entries (size:128b/16B) */ 3543 struct qpc_split_entries { 3544 __le32 qp_num_l2_entries; 3545 __le32 qp_num_qp1_entries; 3546 __le32 rsvd[2]; 3547 }; 3548 3549 /* srq_split_entries (size:128b/16B) */ 3550 struct srq_split_entries { 3551 __le32 srq_num_l2_entries; 3552 __le32 rsvd; 3553 __le32 rsvd2[2]; 3554 }; 3555 3556 /* cq_split_entries (size:128b/16B) */ 3557 struct cq_split_entries { 3558 __le32 cq_num_l2_entries; 3559 __le32 rsvd; 3560 __le32 rsvd2[2]; 3561 }; 3562 3563 /* vnic_split_entries (size:128b/16B) */ 3564 struct vnic_split_entries { 3565 __le32 vnic_num_vnic_entries; 3566 __le32 rsvd; 3567 __le32 rsvd2[2]; 3568 }; 3569 3570 /* mrav_split_entries (size:128b/16B) */ 3571 struct mrav_split_entries { 3572 __le32 mrav_num_av_entries; 3573 __le32 rsvd; 3574 __le32 rsvd2[2]; 3575 }; 3576 3577 /* hwrm_func_backing_store_qcaps_v2_input (size:192b/24B) */ 3578 struct hwrm_func_backing_store_qcaps_v2_input { 3579 __le16 req_type; 3580 __le16 cmpl_ring; 3581 __le16 seq_id; 3582 __le16 target_id; 3583 __le64 resp_addr; 3584 __le16 type; 3585 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP 0x0UL 3586 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ 0x1UL 3587 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ 0x2UL 3588 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC 0x3UL 3589 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT 0x4UL 3590 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3591 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3592 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV 0xeUL 3593 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM 0xfUL 3594 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TKC 0x13UL 3595 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RKC 0x14UL 3596 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3597 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3598 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3599 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3600 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3601 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_TKC 0x1aUL 3602 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_RKC 0x1bUL 3603 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 0xffffUL 3604 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 3605 u8 rsvd[6]; 3606 }; 3607 3608 /* hwrm_func_backing_store_qcaps_v2_output (size:448b/56B) */ 3609 struct hwrm_func_backing_store_qcaps_v2_output { 3610 __le16 error_code; 3611 __le16 req_type; 3612 __le16 seq_id; 3613 __le16 resp_len; 3614 __le16 type; 3615 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QP 0x0UL 3616 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ 0x1UL 3617 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ 0x2UL 3618 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_VNIC 0x3UL 3619 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_STAT 0x4UL 3620 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SP_TQM_RING 0x5UL 3621 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_FP_TQM_RING 0x6UL 3622 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MRAV 0xeUL 3623 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TIM 0xfUL 3624 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TKC 0x13UL 3625 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RKC 0x14UL 3626 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MP_TQM_RING 0x15UL 3627 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SQ_DB_SHADOW 0x16UL 3628 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RQ_DB_SHADOW 0x17UL 3629 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ_DB_SHADOW 0x18UL 3630 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ_DB_SHADOW 0x19UL 3631 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QUIC_TKC 0x1aUL 3632 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QUIC_RKC 0x1bUL 3633 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 0xffffUL 3634 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 3635 __le16 entry_size; 3636 __le32 flags; 3637 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ENABLE_CTX_KIND_INIT 0x1UL 3638 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID 0x2UL 3639 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_DRIVER_MANAGED_MEMORY 0x4UL 3640 __le32 instance_bit_map; 3641 u8 ctx_init_value; 3642 u8 ctx_init_offset; 3643 u8 entry_multiple; 3644 u8 rsvd; 3645 __le32 max_num_entries; 3646 __le32 min_num_entries; 3647 __le16 next_valid_type; 3648 u8 subtype_valid_cnt; 3649 u8 rsvd2; 3650 __le32 split_entry_0; 3651 __le32 split_entry_1; 3652 __le32 split_entry_2; 3653 __le32 split_entry_3; 3654 u8 rsvd3[3]; 3655 u8 valid; 3656 }; 3657 3658 /* hwrm_func_drv_if_change_input (size:192b/24B) */ 3659 struct hwrm_func_drv_if_change_input { 3660 __le16 req_type; 3661 __le16 cmpl_ring; 3662 __le16 seq_id; 3663 __le16 target_id; 3664 __le64 resp_addr; 3665 __le32 flags; 3666 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 3667 __le32 unused; 3668 }; 3669 3670 /* hwrm_func_drv_if_change_output (size:128b/16B) */ 3671 struct hwrm_func_drv_if_change_output { 3672 __le16 error_code; 3673 __le16 req_type; 3674 __le16 seq_id; 3675 __le16 resp_len; 3676 __le32 flags; 3677 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 3678 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 3679 u8 unused_0[3]; 3680 u8 valid; 3681 }; 3682 3683 /* hwrm_port_phy_cfg_input (size:448b/56B) */ 3684 struct hwrm_port_phy_cfg_input { 3685 __le16 req_type; 3686 __le16 cmpl_ring; 3687 __le16 seq_id; 3688 __le16 target_id; 3689 __le64 resp_addr; 3690 __le32 flags; 3691 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 3692 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 3693 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 3694 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 3695 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 3696 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 3697 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 3698 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 3699 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 3700 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 3701 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 3702 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 3703 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 3704 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 3705 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 3706 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL 3707 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL 3708 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL 3709 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL 3710 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL 3711 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL 3712 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL 3713 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL 3714 __le32 enables; 3715 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 3716 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 3717 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 3718 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 3719 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 3720 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 3721 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 3722 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 3723 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 3724 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 3725 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 3726 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL 3727 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL 3728 __le16 port_id; 3729 __le16 force_link_speed; 3730 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 3731 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 3732 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 3733 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 3734 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 3735 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 3736 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 3737 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 3738 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 3739 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 3740 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 3741 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 3742 u8 auto_mode; 3743 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 3744 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 3745 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 3746 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 3747 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 3748 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 3749 u8 auto_duplex; 3750 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 3751 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 3752 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 3753 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 3754 u8 auto_pause; 3755 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 3756 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 3757 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 3758 u8 unused_0; 3759 __le16 auto_link_speed; 3760 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 3761 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 3762 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 3763 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 3764 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 3765 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 3766 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 3767 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 3768 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 3769 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 3770 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 3771 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 3772 __le16 auto_link_speed_mask; 3773 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 3774 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 3775 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 3776 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 3777 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 3778 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 3779 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 3780 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 3781 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 3782 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 3783 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 3784 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 3785 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 3786 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 3787 u8 wirespeed; 3788 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 3789 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 3790 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 3791 u8 lpbk; 3792 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 3793 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 3794 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 3795 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 3796 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 3797 u8 force_pause; 3798 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 3799 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 3800 u8 unused_1; 3801 __le32 preemphasis; 3802 __le16 eee_link_speed_mask; 3803 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 3804 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 3805 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 3806 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 3807 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 3808 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 3809 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 3810 __le16 force_pam4_link_speed; 3811 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 3812 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 3813 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 3814 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 3815 __le32 tx_lpi_timer; 3816 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 3817 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 3818 __le16 auto_link_pam4_speed_mask; 3819 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL 3820 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL 3821 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL 3822 u8 unused_2[2]; 3823 }; 3824 3825 /* hwrm_port_phy_cfg_output (size:128b/16B) */ 3826 struct hwrm_port_phy_cfg_output { 3827 __le16 error_code; 3828 __le16 req_type; 3829 __le16 seq_id; 3830 __le16 resp_len; 3831 u8 unused_0[7]; 3832 u8 valid; 3833 }; 3834 3835 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 3836 struct hwrm_port_phy_cfg_cmd_err { 3837 u8 code; 3838 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 3839 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 3840 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 3841 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 3842 u8 unused_0[7]; 3843 }; 3844 3845 /* hwrm_port_phy_qcfg_input (size:192b/24B) */ 3846 struct hwrm_port_phy_qcfg_input { 3847 __le16 req_type; 3848 __le16 cmpl_ring; 3849 __le16 seq_id; 3850 __le16 target_id; 3851 __le64 resp_addr; 3852 __le16 port_id; 3853 u8 unused_0[6]; 3854 }; 3855 3856 /* hwrm_port_phy_qcfg_output (size:768b/96B) */ 3857 struct hwrm_port_phy_qcfg_output { 3858 __le16 error_code; 3859 __le16 req_type; 3860 __le16 seq_id; 3861 __le16 resp_len; 3862 u8 link; 3863 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 3864 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 3865 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 3866 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 3867 u8 active_fec_signal_mode; 3868 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL 3869 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0 3870 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL 3871 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL 3872 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 3873 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL 3874 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4 3875 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4) 3876 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4) 3877 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4) 3878 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4) 3879 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4) 3880 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4) 3881 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4) 3882 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE 3883 __le16 link_speed; 3884 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 3885 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 3886 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 3887 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 3888 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 3889 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 3890 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 3891 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 3892 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 3893 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 3894 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 3895 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 3896 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 3897 u8 duplex_cfg; 3898 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 3899 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 3900 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 3901 u8 pause; 3902 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 3903 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 3904 __le16 support_speeds; 3905 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 3906 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 3907 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 3908 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 3909 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 3910 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 3911 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 3912 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 3913 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 3914 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 3915 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 3916 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 3917 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 3918 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 3919 __le16 force_link_speed; 3920 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 3921 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 3922 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 3923 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 3924 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 3925 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 3926 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 3927 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 3928 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 3929 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 3930 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 3931 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 3932 u8 auto_mode; 3933 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 3934 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 3935 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 3936 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 3937 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 3938 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 3939 u8 auto_pause; 3940 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 3941 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 3942 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 3943 __le16 auto_link_speed; 3944 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 3945 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 3946 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 3947 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 3948 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 3949 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 3950 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 3951 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 3952 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 3953 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 3954 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 3955 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 3956 __le16 auto_link_speed_mask; 3957 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 3958 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 3959 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 3960 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 3961 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 3962 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 3963 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 3964 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 3965 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 3966 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 3967 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 3968 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 3969 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 3970 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 3971 u8 wirespeed; 3972 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 3973 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 3974 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 3975 u8 lpbk; 3976 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 3977 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 3978 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 3979 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 3980 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 3981 u8 force_pause; 3982 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 3983 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 3984 u8 module_status; 3985 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 3986 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 3987 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 3988 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 3989 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 3990 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL 3991 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 3992 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 3993 __le32 preemphasis; 3994 u8 phy_maj; 3995 u8 phy_min; 3996 u8 phy_bld; 3997 u8 phy_type; 3998 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 3999 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 4000 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 4001 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 4002 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 4003 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 4004 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 4005 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 4006 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 4007 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 4008 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 4009 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 4010 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 4011 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 4012 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 4013 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 4014 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 4015 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 4016 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 4017 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 4018 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 4019 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 4020 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 4021 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 4022 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 4023 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 4024 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 4025 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 4026 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 4027 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 4028 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 4029 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 4030 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR 0x20UL 4031 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR 0x21UL 4032 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR 0x22UL 4033 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER 0x23UL 4034 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2 0x24UL 4035 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2 0x25UL 4036 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2 0x26UL 4037 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2 0x27UL 4038 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2 4039 u8 media_type; 4040 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 4041 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 4042 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 4043 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 4044 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 4045 u8 xcvr_pkg_type; 4046 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 4047 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 4048 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 4049 u8 eee_config_phy_addr; 4050 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 4051 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 4052 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 4053 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 4054 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 4055 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 4056 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 4057 u8 parallel_detect; 4058 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 4059 __le16 link_partner_adv_speeds; 4060 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 4061 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 4062 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 4063 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 4064 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 4065 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 4066 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 4067 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 4068 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 4069 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 4070 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 4071 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 4072 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 4073 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 4074 u8 link_partner_adv_auto_mode; 4075 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 4076 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 4077 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 4078 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 4079 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 4080 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 4081 u8 link_partner_adv_pause; 4082 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 4083 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 4084 __le16 adv_eee_link_speed_mask; 4085 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 4086 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 4087 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 4088 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 4089 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 4090 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 4091 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 4092 __le16 link_partner_adv_eee_link_speed_mask; 4093 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 4094 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 4095 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 4096 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 4097 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 4098 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 4099 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 4100 __le32 xcvr_identifier_type_tx_lpi_timer; 4101 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 4102 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 4103 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 4104 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 4105 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 4106 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 4107 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 4108 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 4109 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 4110 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 4111 __le16 fec_cfg; 4112 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 4113 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 4114 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 4115 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 4116 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 4117 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 4118 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 4119 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL 4120 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL 4121 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL 4122 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL 4123 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL 4124 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL 4125 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL 4126 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL 4127 u8 duplex_state; 4128 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 4129 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 4130 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 4131 u8 option_flags; 4132 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 4133 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN 0x2UL 4134 char phy_vendor_name[16]; 4135 char phy_vendor_partnumber[16]; 4136 __le16 support_pam4_speeds; 4137 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL 4138 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL 4139 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL 4140 __le16 force_pam4_link_speed; 4141 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 4142 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 4143 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 4144 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 4145 __le16 auto_pam4_link_speed_mask; 4146 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL 4147 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL 4148 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL 4149 u8 link_partner_pam4_adv_speeds; 4150 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL 4151 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL 4152 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL 4153 u8 valid; 4154 }; 4155 4156 /* hwrm_port_mac_cfg_input (size:448b/56B) */ 4157 struct hwrm_port_mac_cfg_input { 4158 __le16 req_type; 4159 __le16 cmpl_ring; 4160 __le16 seq_id; 4161 __le16 target_id; 4162 __le64 resp_addr; 4163 __le32 flags; 4164 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 4165 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 4166 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 4167 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 4168 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 4169 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 4170 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 4171 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 4172 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 4173 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 4174 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 4175 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 4176 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 4177 #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL 4178 #define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE 0x4000UL 4179 #define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE 0x8000UL 4180 __le32 enables; 4181 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 4182 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 4183 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 4184 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 4185 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 4186 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 4187 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 4188 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 4189 #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL 4190 #define PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE 0x400UL 4191 __le16 port_id; 4192 u8 ipg; 4193 u8 lpbk; 4194 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 4195 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 4196 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 4197 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 4198 u8 vlan_pri2cos_map_pri; 4199 u8 reserved1; 4200 u8 tunnel_pri2cos_map_pri; 4201 u8 dscp2pri_map_pri; 4202 __le16 rx_ts_capture_ptp_msg_type; 4203 __le16 tx_ts_capture_ptp_msg_type; 4204 u8 cos_field_cfg; 4205 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 4206 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 4207 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 4208 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 4209 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 4210 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 4211 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 4212 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 4213 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 4214 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 4215 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 4216 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 4217 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 4218 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 4219 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 4220 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 4221 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 4222 u8 unused_0[3]; 4223 __le32 ptp_freq_adj_ppb; 4224 u8 unused_1[4]; 4225 __le64 ptp_adj_phase; 4226 }; 4227 4228 /* hwrm_port_mac_cfg_output (size:128b/16B) */ 4229 struct hwrm_port_mac_cfg_output { 4230 __le16 error_code; 4231 __le16 req_type; 4232 __le16 seq_id; 4233 __le16 resp_len; 4234 __le16 mru; 4235 __le16 mtu; 4236 u8 ipg; 4237 u8 lpbk; 4238 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 4239 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 4240 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 4241 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 4242 u8 unused_0; 4243 u8 valid; 4244 }; 4245 4246 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 4247 struct hwrm_port_mac_ptp_qcfg_input { 4248 __le16 req_type; 4249 __le16 cmpl_ring; 4250 __le16 seq_id; 4251 __le16 target_id; 4252 __le64 resp_addr; 4253 __le16 port_id; 4254 u8 unused_0[6]; 4255 }; 4256 4257 /* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */ 4258 struct hwrm_port_mac_ptp_qcfg_output { 4259 __le16 error_code; 4260 __le16 req_type; 4261 __le16 seq_id; 4262 __le16 resp_len; 4263 u8 flags; 4264 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 4265 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL 4266 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL 4267 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK 0x10UL 4268 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_RTC_CONFIGURED 0x20UL 4269 u8 unused_0[3]; 4270 __le32 rx_ts_reg_off_lower; 4271 __le32 rx_ts_reg_off_upper; 4272 __le32 rx_ts_reg_off_seq_id; 4273 __le32 rx_ts_reg_off_src_id_0; 4274 __le32 rx_ts_reg_off_src_id_1; 4275 __le32 rx_ts_reg_off_src_id_2; 4276 __le32 rx_ts_reg_off_domain_id; 4277 __le32 rx_ts_reg_off_fifo; 4278 __le32 rx_ts_reg_off_fifo_adv; 4279 __le32 rx_ts_reg_off_granularity; 4280 __le32 tx_ts_reg_off_lower; 4281 __le32 tx_ts_reg_off_upper; 4282 __le32 tx_ts_reg_off_seq_id; 4283 __le32 tx_ts_reg_off_fifo; 4284 __le32 tx_ts_reg_off_granularity; 4285 __le32 ts_ref_clock_reg_lower; 4286 __le32 ts_ref_clock_reg_upper; 4287 u8 unused_1[7]; 4288 u8 valid; 4289 }; 4290 4291 /* tx_port_stats (size:3264b/408B) */ 4292 struct tx_port_stats { 4293 __le64 tx_64b_frames; 4294 __le64 tx_65b_127b_frames; 4295 __le64 tx_128b_255b_frames; 4296 __le64 tx_256b_511b_frames; 4297 __le64 tx_512b_1023b_frames; 4298 __le64 tx_1024b_1518b_frames; 4299 __le64 tx_good_vlan_frames; 4300 __le64 tx_1519b_2047b_frames; 4301 __le64 tx_2048b_4095b_frames; 4302 __le64 tx_4096b_9216b_frames; 4303 __le64 tx_9217b_16383b_frames; 4304 __le64 tx_good_frames; 4305 __le64 tx_total_frames; 4306 __le64 tx_ucast_frames; 4307 __le64 tx_mcast_frames; 4308 __le64 tx_bcast_frames; 4309 __le64 tx_pause_frames; 4310 __le64 tx_pfc_frames; 4311 __le64 tx_jabber_frames; 4312 __le64 tx_fcs_err_frames; 4313 __le64 tx_control_frames; 4314 __le64 tx_oversz_frames; 4315 __le64 tx_single_dfrl_frames; 4316 __le64 tx_multi_dfrl_frames; 4317 __le64 tx_single_coll_frames; 4318 __le64 tx_multi_coll_frames; 4319 __le64 tx_late_coll_frames; 4320 __le64 tx_excessive_coll_frames; 4321 __le64 tx_frag_frames; 4322 __le64 tx_err; 4323 __le64 tx_tagged_frames; 4324 __le64 tx_dbl_tagged_frames; 4325 __le64 tx_runt_frames; 4326 __le64 tx_fifo_underruns; 4327 __le64 tx_pfc_ena_frames_pri0; 4328 __le64 tx_pfc_ena_frames_pri1; 4329 __le64 tx_pfc_ena_frames_pri2; 4330 __le64 tx_pfc_ena_frames_pri3; 4331 __le64 tx_pfc_ena_frames_pri4; 4332 __le64 tx_pfc_ena_frames_pri5; 4333 __le64 tx_pfc_ena_frames_pri6; 4334 __le64 tx_pfc_ena_frames_pri7; 4335 __le64 tx_eee_lpi_events; 4336 __le64 tx_eee_lpi_duration; 4337 __le64 tx_llfc_logical_msgs; 4338 __le64 tx_hcfc_msgs; 4339 __le64 tx_total_collisions; 4340 __le64 tx_bytes; 4341 __le64 tx_xthol_frames; 4342 __le64 tx_stat_discard; 4343 __le64 tx_stat_error; 4344 }; 4345 4346 /* rx_port_stats (size:4224b/528B) */ 4347 struct rx_port_stats { 4348 __le64 rx_64b_frames; 4349 __le64 rx_65b_127b_frames; 4350 __le64 rx_128b_255b_frames; 4351 __le64 rx_256b_511b_frames; 4352 __le64 rx_512b_1023b_frames; 4353 __le64 rx_1024b_1518b_frames; 4354 __le64 rx_good_vlan_frames; 4355 __le64 rx_1519b_2047b_frames; 4356 __le64 rx_2048b_4095b_frames; 4357 __le64 rx_4096b_9216b_frames; 4358 __le64 rx_9217b_16383b_frames; 4359 __le64 rx_total_frames; 4360 __le64 rx_ucast_frames; 4361 __le64 rx_mcast_frames; 4362 __le64 rx_bcast_frames; 4363 __le64 rx_fcs_err_frames; 4364 __le64 rx_ctrl_frames; 4365 __le64 rx_pause_frames; 4366 __le64 rx_pfc_frames; 4367 __le64 rx_unsupported_opcode_frames; 4368 __le64 rx_unsupported_da_pausepfc_frames; 4369 __le64 rx_wrong_sa_frames; 4370 __le64 rx_align_err_frames; 4371 __le64 rx_oor_len_frames; 4372 __le64 rx_code_err_frames; 4373 __le64 rx_false_carrier_frames; 4374 __le64 rx_ovrsz_frames; 4375 __le64 rx_jbr_frames; 4376 __le64 rx_mtu_err_frames; 4377 __le64 rx_match_crc_frames; 4378 __le64 rx_promiscuous_frames; 4379 __le64 rx_tagged_frames; 4380 __le64 rx_double_tagged_frames; 4381 __le64 rx_trunc_frames; 4382 __le64 rx_good_frames; 4383 __le64 rx_pfc_xon2xoff_frames_pri0; 4384 __le64 rx_pfc_xon2xoff_frames_pri1; 4385 __le64 rx_pfc_xon2xoff_frames_pri2; 4386 __le64 rx_pfc_xon2xoff_frames_pri3; 4387 __le64 rx_pfc_xon2xoff_frames_pri4; 4388 __le64 rx_pfc_xon2xoff_frames_pri5; 4389 __le64 rx_pfc_xon2xoff_frames_pri6; 4390 __le64 rx_pfc_xon2xoff_frames_pri7; 4391 __le64 rx_pfc_ena_frames_pri0; 4392 __le64 rx_pfc_ena_frames_pri1; 4393 __le64 rx_pfc_ena_frames_pri2; 4394 __le64 rx_pfc_ena_frames_pri3; 4395 __le64 rx_pfc_ena_frames_pri4; 4396 __le64 rx_pfc_ena_frames_pri5; 4397 __le64 rx_pfc_ena_frames_pri6; 4398 __le64 rx_pfc_ena_frames_pri7; 4399 __le64 rx_sch_crc_err_frames; 4400 __le64 rx_undrsz_frames; 4401 __le64 rx_frag_frames; 4402 __le64 rx_eee_lpi_events; 4403 __le64 rx_eee_lpi_duration; 4404 __le64 rx_llfc_physical_msgs; 4405 __le64 rx_llfc_logical_msgs; 4406 __le64 rx_llfc_msgs_with_crc_err; 4407 __le64 rx_hcfc_msgs; 4408 __le64 rx_hcfc_msgs_with_crc_err; 4409 __le64 rx_bytes; 4410 __le64 rx_runt_bytes; 4411 __le64 rx_runt_frames; 4412 __le64 rx_stat_discard; 4413 __le64 rx_stat_err; 4414 }; 4415 4416 /* hwrm_port_qstats_input (size:320b/40B) */ 4417 struct hwrm_port_qstats_input { 4418 __le16 req_type; 4419 __le16 cmpl_ring; 4420 __le16 seq_id; 4421 __le16 target_id; 4422 __le64 resp_addr; 4423 __le16 port_id; 4424 u8 flags; 4425 #define PORT_QSTATS_REQ_FLAGS_UNUSED 0x0UL 4426 #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 4427 #define PORT_QSTATS_REQ_FLAGS_LAST PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 4428 u8 unused_0[5]; 4429 __le64 tx_stat_host_addr; 4430 __le64 rx_stat_host_addr; 4431 }; 4432 4433 /* hwrm_port_qstats_output (size:128b/16B) */ 4434 struct hwrm_port_qstats_output { 4435 __le16 error_code; 4436 __le16 req_type; 4437 __le16 seq_id; 4438 __le16 resp_len; 4439 __le16 tx_stat_size; 4440 __le16 rx_stat_size; 4441 u8 unused_0[3]; 4442 u8 valid; 4443 }; 4444 4445 /* tx_port_stats_ext (size:2048b/256B) */ 4446 struct tx_port_stats_ext { 4447 __le64 tx_bytes_cos0; 4448 __le64 tx_bytes_cos1; 4449 __le64 tx_bytes_cos2; 4450 __le64 tx_bytes_cos3; 4451 __le64 tx_bytes_cos4; 4452 __le64 tx_bytes_cos5; 4453 __le64 tx_bytes_cos6; 4454 __le64 tx_bytes_cos7; 4455 __le64 tx_packets_cos0; 4456 __le64 tx_packets_cos1; 4457 __le64 tx_packets_cos2; 4458 __le64 tx_packets_cos3; 4459 __le64 tx_packets_cos4; 4460 __le64 tx_packets_cos5; 4461 __le64 tx_packets_cos6; 4462 __le64 tx_packets_cos7; 4463 __le64 pfc_pri0_tx_duration_us; 4464 __le64 pfc_pri0_tx_transitions; 4465 __le64 pfc_pri1_tx_duration_us; 4466 __le64 pfc_pri1_tx_transitions; 4467 __le64 pfc_pri2_tx_duration_us; 4468 __le64 pfc_pri2_tx_transitions; 4469 __le64 pfc_pri3_tx_duration_us; 4470 __le64 pfc_pri3_tx_transitions; 4471 __le64 pfc_pri4_tx_duration_us; 4472 __le64 pfc_pri4_tx_transitions; 4473 __le64 pfc_pri5_tx_duration_us; 4474 __le64 pfc_pri5_tx_transitions; 4475 __le64 pfc_pri6_tx_duration_us; 4476 __le64 pfc_pri6_tx_transitions; 4477 __le64 pfc_pri7_tx_duration_us; 4478 __le64 pfc_pri7_tx_transitions; 4479 }; 4480 4481 /* rx_port_stats_ext (size:3776b/472B) */ 4482 struct rx_port_stats_ext { 4483 __le64 link_down_events; 4484 __le64 continuous_pause_events; 4485 __le64 resume_pause_events; 4486 __le64 continuous_roce_pause_events; 4487 __le64 resume_roce_pause_events; 4488 __le64 rx_bytes_cos0; 4489 __le64 rx_bytes_cos1; 4490 __le64 rx_bytes_cos2; 4491 __le64 rx_bytes_cos3; 4492 __le64 rx_bytes_cos4; 4493 __le64 rx_bytes_cos5; 4494 __le64 rx_bytes_cos6; 4495 __le64 rx_bytes_cos7; 4496 __le64 rx_packets_cos0; 4497 __le64 rx_packets_cos1; 4498 __le64 rx_packets_cos2; 4499 __le64 rx_packets_cos3; 4500 __le64 rx_packets_cos4; 4501 __le64 rx_packets_cos5; 4502 __le64 rx_packets_cos6; 4503 __le64 rx_packets_cos7; 4504 __le64 pfc_pri0_rx_duration_us; 4505 __le64 pfc_pri0_rx_transitions; 4506 __le64 pfc_pri1_rx_duration_us; 4507 __le64 pfc_pri1_rx_transitions; 4508 __le64 pfc_pri2_rx_duration_us; 4509 __le64 pfc_pri2_rx_transitions; 4510 __le64 pfc_pri3_rx_duration_us; 4511 __le64 pfc_pri3_rx_transitions; 4512 __le64 pfc_pri4_rx_duration_us; 4513 __le64 pfc_pri4_rx_transitions; 4514 __le64 pfc_pri5_rx_duration_us; 4515 __le64 pfc_pri5_rx_transitions; 4516 __le64 pfc_pri6_rx_duration_us; 4517 __le64 pfc_pri6_rx_transitions; 4518 __le64 pfc_pri7_rx_duration_us; 4519 __le64 pfc_pri7_rx_transitions; 4520 __le64 rx_bits; 4521 __le64 rx_buffer_passed_threshold; 4522 __le64 rx_pcs_symbol_err; 4523 __le64 rx_corrected_bits; 4524 __le64 rx_discard_bytes_cos0; 4525 __le64 rx_discard_bytes_cos1; 4526 __le64 rx_discard_bytes_cos2; 4527 __le64 rx_discard_bytes_cos3; 4528 __le64 rx_discard_bytes_cos4; 4529 __le64 rx_discard_bytes_cos5; 4530 __le64 rx_discard_bytes_cos6; 4531 __le64 rx_discard_bytes_cos7; 4532 __le64 rx_discard_packets_cos0; 4533 __le64 rx_discard_packets_cos1; 4534 __le64 rx_discard_packets_cos2; 4535 __le64 rx_discard_packets_cos3; 4536 __le64 rx_discard_packets_cos4; 4537 __le64 rx_discard_packets_cos5; 4538 __le64 rx_discard_packets_cos6; 4539 __le64 rx_discard_packets_cos7; 4540 __le64 rx_fec_corrected_blocks; 4541 __le64 rx_fec_uncorrectable_blocks; 4542 }; 4543 4544 /* hwrm_port_qstats_ext_input (size:320b/40B) */ 4545 struct hwrm_port_qstats_ext_input { 4546 __le16 req_type; 4547 __le16 cmpl_ring; 4548 __le16 seq_id; 4549 __le16 target_id; 4550 __le64 resp_addr; 4551 __le16 port_id; 4552 __le16 tx_stat_size; 4553 __le16 rx_stat_size; 4554 u8 flags; 4555 #define PORT_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 4556 #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL 4557 #define PORT_QSTATS_EXT_REQ_FLAGS_LAST PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 4558 u8 unused_0; 4559 __le64 tx_stat_host_addr; 4560 __le64 rx_stat_host_addr; 4561 }; 4562 4563 /* hwrm_port_qstats_ext_output (size:128b/16B) */ 4564 struct hwrm_port_qstats_ext_output { 4565 __le16 error_code; 4566 __le16 req_type; 4567 __le16 seq_id; 4568 __le16 resp_len; 4569 __le16 tx_stat_size; 4570 __le16 rx_stat_size; 4571 __le16 total_active_cos_queues; 4572 u8 flags; 4573 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 4574 u8 valid; 4575 }; 4576 4577 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */ 4578 struct hwrm_port_lpbk_qstats_input { 4579 __le16 req_type; 4580 __le16 cmpl_ring; 4581 __le16 seq_id; 4582 __le16 target_id; 4583 __le64 resp_addr; 4584 }; 4585 4586 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */ 4587 struct hwrm_port_lpbk_qstats_output { 4588 __le16 error_code; 4589 __le16 req_type; 4590 __le16 seq_id; 4591 __le16 resp_len; 4592 __le64 lpbk_ucast_frames; 4593 __le64 lpbk_mcast_frames; 4594 __le64 lpbk_bcast_frames; 4595 __le64 lpbk_ucast_bytes; 4596 __le64 lpbk_mcast_bytes; 4597 __le64 lpbk_bcast_bytes; 4598 __le64 tx_stat_discard; 4599 __le64 tx_stat_error; 4600 __le64 rx_stat_discard; 4601 __le64 rx_stat_error; 4602 u8 unused_0[7]; 4603 u8 valid; 4604 }; 4605 4606 /* hwrm_port_ecn_qstats_input (size:256b/32B) */ 4607 struct hwrm_port_ecn_qstats_input { 4608 __le16 req_type; 4609 __le16 cmpl_ring; 4610 __le16 seq_id; 4611 __le16 target_id; 4612 __le64 resp_addr; 4613 __le16 port_id; 4614 __le16 ecn_stat_buf_size; 4615 u8 flags; 4616 #define PORT_ECN_QSTATS_REQ_FLAGS_UNUSED 0x0UL 4617 #define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 4618 #define PORT_ECN_QSTATS_REQ_FLAGS_LAST PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 4619 u8 unused_0[3]; 4620 __le64 ecn_stat_host_addr; 4621 }; 4622 4623 /* hwrm_port_ecn_qstats_output (size:128b/16B) */ 4624 struct hwrm_port_ecn_qstats_output { 4625 __le16 error_code; 4626 __le16 req_type; 4627 __le16 seq_id; 4628 __le16 resp_len; 4629 __le16 ecn_stat_buf_size; 4630 u8 mark_en; 4631 u8 unused_0[4]; 4632 u8 valid; 4633 }; 4634 4635 /* port_stats_ecn (size:512b/64B) */ 4636 struct port_stats_ecn { 4637 __le64 mark_cnt_cos0; 4638 __le64 mark_cnt_cos1; 4639 __le64 mark_cnt_cos2; 4640 __le64 mark_cnt_cos3; 4641 __le64 mark_cnt_cos4; 4642 __le64 mark_cnt_cos5; 4643 __le64 mark_cnt_cos6; 4644 __le64 mark_cnt_cos7; 4645 }; 4646 4647 /* hwrm_port_clr_stats_input (size:192b/24B) */ 4648 struct hwrm_port_clr_stats_input { 4649 __le16 req_type; 4650 __le16 cmpl_ring; 4651 __le16 seq_id; 4652 __le16 target_id; 4653 __le64 resp_addr; 4654 __le16 port_id; 4655 u8 flags; 4656 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 4657 u8 unused_0[5]; 4658 }; 4659 4660 /* hwrm_port_clr_stats_output (size:128b/16B) */ 4661 struct hwrm_port_clr_stats_output { 4662 __le16 error_code; 4663 __le16 req_type; 4664 __le16 seq_id; 4665 __le16 resp_len; 4666 u8 unused_0[7]; 4667 u8 valid; 4668 }; 4669 4670 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ 4671 struct hwrm_port_lpbk_clr_stats_input { 4672 __le16 req_type; 4673 __le16 cmpl_ring; 4674 __le16 seq_id; 4675 __le16 target_id; 4676 __le64 resp_addr; 4677 }; 4678 4679 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 4680 struct hwrm_port_lpbk_clr_stats_output { 4681 __le16 error_code; 4682 __le16 req_type; 4683 __le16 seq_id; 4684 __le16 resp_len; 4685 u8 unused_0[7]; 4686 u8 valid; 4687 }; 4688 4689 /* hwrm_port_ts_query_input (size:320b/40B) */ 4690 struct hwrm_port_ts_query_input { 4691 __le16 req_type; 4692 __le16 cmpl_ring; 4693 __le16 seq_id; 4694 __le16 target_id; 4695 __le64 resp_addr; 4696 __le32 flags; 4697 #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL 4698 #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL 4699 #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL 4700 #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX 4701 #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL 4702 __le16 port_id; 4703 u8 unused_0[2]; 4704 __le16 enables; 4705 #define PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT 0x1UL 4706 #define PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID 0x2UL 4707 #define PORT_TS_QUERY_REQ_ENABLES_PTP_HDR_OFFSET 0x4UL 4708 __le16 ts_req_timeout; 4709 __le32 ptp_seq_id; 4710 __le16 ptp_hdr_offset; 4711 u8 unused_1[6]; 4712 }; 4713 4714 /* hwrm_port_ts_query_output (size:192b/24B) */ 4715 struct hwrm_port_ts_query_output { 4716 __le16 error_code; 4717 __le16 req_type; 4718 __le16 seq_id; 4719 __le16 resp_len; 4720 __le64 ptp_msg_ts; 4721 __le16 ptp_msg_seqid; 4722 u8 unused_0[5]; 4723 u8 valid; 4724 }; 4725 4726 /* hwrm_port_phy_qcaps_input (size:192b/24B) */ 4727 struct hwrm_port_phy_qcaps_input { 4728 __le16 req_type; 4729 __le16 cmpl_ring; 4730 __le16 seq_id; 4731 __le16 target_id; 4732 __le64 resp_addr; 4733 __le16 port_id; 4734 u8 unused_0[6]; 4735 }; 4736 4737 /* hwrm_port_phy_qcaps_output (size:256b/32B) */ 4738 struct hwrm_port_phy_qcaps_output { 4739 __le16 error_code; 4740 __le16 req_type; 4741 __le16 seq_id; 4742 __le16 resp_len; 4743 u8 flags; 4744 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 4745 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 4746 #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL 4747 #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL 4748 #define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL 4749 #define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x20UL 4750 #define PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN 0x40UL 4751 #define PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS 0x80UL 4752 u8 port_cnt; 4753 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 4754 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 4755 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 4756 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 4757 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 4758 #define PORT_PHY_QCAPS_RESP_PORT_CNT_12 0xcUL 4759 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_12 4760 __le16 supported_speeds_force_mode; 4761 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 4762 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 4763 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 4764 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 4765 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 4766 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 4767 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 4768 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 4769 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 4770 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 4771 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 4772 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 4773 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 4774 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 4775 __le16 supported_speeds_auto_mode; 4776 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 4777 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 4778 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 4779 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 4780 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 4781 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 4782 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 4783 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 4784 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 4785 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 4786 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 4787 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 4788 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 4789 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 4790 __le16 supported_speeds_eee_mode; 4791 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 4792 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 4793 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 4794 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 4795 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 4796 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 4797 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 4798 __le32 tx_lpi_timer_low; 4799 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 4800 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 4801 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 4802 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 4803 __le32 valid_tx_lpi_timer_high; 4804 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 4805 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 4806 #define PORT_PHY_QCAPS_RESP_RSVD_MASK 0xff000000UL 4807 #define PORT_PHY_QCAPS_RESP_RSVD_SFT 24 4808 __le16 supported_pam4_speeds_auto_mode; 4809 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL 4810 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL 4811 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL 4812 __le16 supported_pam4_speeds_force_mode; 4813 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL 4814 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL 4815 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL 4816 __le16 flags2; 4817 #define PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED 0x1UL 4818 #define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED 0x2UL 4819 u8 internal_port_cnt; 4820 u8 valid; 4821 }; 4822 4823 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 4824 struct hwrm_port_phy_i2c_read_input { 4825 __le16 req_type; 4826 __le16 cmpl_ring; 4827 __le16 seq_id; 4828 __le16 target_id; 4829 __le64 resp_addr; 4830 __le32 flags; 4831 __le32 enables; 4832 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 4833 __le16 port_id; 4834 u8 i2c_slave_addr; 4835 u8 unused_0; 4836 __le16 page_number; 4837 __le16 page_offset; 4838 u8 data_length; 4839 u8 unused_1[7]; 4840 }; 4841 4842 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 4843 struct hwrm_port_phy_i2c_read_output { 4844 __le16 error_code; 4845 __le16 req_type; 4846 __le16 seq_id; 4847 __le16 resp_len; 4848 __le32 data[16]; 4849 u8 unused_0[7]; 4850 u8 valid; 4851 }; 4852 4853 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */ 4854 struct hwrm_port_phy_mdio_write_input { 4855 __le16 req_type; 4856 __le16 cmpl_ring; 4857 __le16 seq_id; 4858 __le16 target_id; 4859 __le64 resp_addr; 4860 __le32 unused_0[2]; 4861 __le16 port_id; 4862 u8 phy_addr; 4863 u8 dev_addr; 4864 __le16 reg_addr; 4865 __le16 reg_data; 4866 u8 cl45_mdio; 4867 u8 unused_1[7]; 4868 }; 4869 4870 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */ 4871 struct hwrm_port_phy_mdio_write_output { 4872 __le16 error_code; 4873 __le16 req_type; 4874 __le16 seq_id; 4875 __le16 resp_len; 4876 u8 unused_0[7]; 4877 u8 valid; 4878 }; 4879 4880 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */ 4881 struct hwrm_port_phy_mdio_read_input { 4882 __le16 req_type; 4883 __le16 cmpl_ring; 4884 __le16 seq_id; 4885 __le16 target_id; 4886 __le64 resp_addr; 4887 __le32 unused_0[2]; 4888 __le16 port_id; 4889 u8 phy_addr; 4890 u8 dev_addr; 4891 __le16 reg_addr; 4892 u8 cl45_mdio; 4893 u8 unused_1; 4894 }; 4895 4896 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */ 4897 struct hwrm_port_phy_mdio_read_output { 4898 __le16 error_code; 4899 __le16 req_type; 4900 __le16 seq_id; 4901 __le16 resp_len; 4902 __le16 reg_data; 4903 u8 unused_0[5]; 4904 u8 valid; 4905 }; 4906 4907 /* hwrm_port_led_cfg_input (size:512b/64B) */ 4908 struct hwrm_port_led_cfg_input { 4909 __le16 req_type; 4910 __le16 cmpl_ring; 4911 __le16 seq_id; 4912 __le16 target_id; 4913 __le64 resp_addr; 4914 __le32 enables; 4915 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 4916 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 4917 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 4918 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 4919 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 4920 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 4921 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 4922 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 4923 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 4924 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 4925 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 4926 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 4927 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 4928 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 4929 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 4930 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 4931 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 4932 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 4933 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 4934 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 4935 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 4936 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 4937 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 4938 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 4939 __le16 port_id; 4940 u8 num_leds; 4941 u8 rsvd; 4942 u8 led0_id; 4943 u8 led0_state; 4944 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 4945 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 4946 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 4947 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 4948 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 4949 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 4950 u8 led0_color; 4951 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 4952 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 4953 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 4954 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 4955 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 4956 u8 unused_0; 4957 __le16 led0_blink_on; 4958 __le16 led0_blink_off; 4959 u8 led0_group_id; 4960 u8 rsvd0; 4961 u8 led1_id; 4962 u8 led1_state; 4963 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 4964 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 4965 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 4966 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 4967 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 4968 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 4969 u8 led1_color; 4970 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 4971 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 4972 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 4973 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 4974 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 4975 u8 unused_1; 4976 __le16 led1_blink_on; 4977 __le16 led1_blink_off; 4978 u8 led1_group_id; 4979 u8 rsvd1; 4980 u8 led2_id; 4981 u8 led2_state; 4982 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 4983 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 4984 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 4985 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 4986 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 4987 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 4988 u8 led2_color; 4989 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 4990 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 4991 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 4992 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 4993 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 4994 u8 unused_2; 4995 __le16 led2_blink_on; 4996 __le16 led2_blink_off; 4997 u8 led2_group_id; 4998 u8 rsvd2; 4999 u8 led3_id; 5000 u8 led3_state; 5001 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 5002 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 5003 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 5004 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 5005 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 5006 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 5007 u8 led3_color; 5008 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 5009 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 5010 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 5011 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 5012 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 5013 u8 unused_3; 5014 __le16 led3_blink_on; 5015 __le16 led3_blink_off; 5016 u8 led3_group_id; 5017 u8 rsvd3; 5018 }; 5019 5020 /* hwrm_port_led_cfg_output (size:128b/16B) */ 5021 struct hwrm_port_led_cfg_output { 5022 __le16 error_code; 5023 __le16 req_type; 5024 __le16 seq_id; 5025 __le16 resp_len; 5026 u8 unused_0[7]; 5027 u8 valid; 5028 }; 5029 5030 /* hwrm_port_led_qcfg_input (size:192b/24B) */ 5031 struct hwrm_port_led_qcfg_input { 5032 __le16 req_type; 5033 __le16 cmpl_ring; 5034 __le16 seq_id; 5035 __le16 target_id; 5036 __le64 resp_addr; 5037 __le16 port_id; 5038 u8 unused_0[6]; 5039 }; 5040 5041 /* hwrm_port_led_qcfg_output (size:448b/56B) */ 5042 struct hwrm_port_led_qcfg_output { 5043 __le16 error_code; 5044 __le16 req_type; 5045 __le16 seq_id; 5046 __le16 resp_len; 5047 u8 num_leds; 5048 u8 led0_id; 5049 u8 led0_type; 5050 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 5051 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 5052 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 5053 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 5054 u8 led0_state; 5055 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 5056 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 5057 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 5058 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 5059 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 5060 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 5061 u8 led0_color; 5062 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 5063 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 5064 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 5065 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 5066 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 5067 u8 unused_0; 5068 __le16 led0_blink_on; 5069 __le16 led0_blink_off; 5070 u8 led0_group_id; 5071 u8 led1_id; 5072 u8 led1_type; 5073 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 5074 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 5075 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 5076 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 5077 u8 led1_state; 5078 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 5079 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 5080 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 5081 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 5082 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 5083 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 5084 u8 led1_color; 5085 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 5086 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 5087 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 5088 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 5089 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 5090 u8 unused_1; 5091 __le16 led1_blink_on; 5092 __le16 led1_blink_off; 5093 u8 led1_group_id; 5094 u8 led2_id; 5095 u8 led2_type; 5096 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 5097 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 5098 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 5099 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 5100 u8 led2_state; 5101 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 5102 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 5103 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 5104 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 5105 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 5106 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 5107 u8 led2_color; 5108 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 5109 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 5110 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 5111 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 5112 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 5113 u8 unused_2; 5114 __le16 led2_blink_on; 5115 __le16 led2_blink_off; 5116 u8 led2_group_id; 5117 u8 led3_id; 5118 u8 led3_type; 5119 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 5120 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 5121 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 5122 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 5123 u8 led3_state; 5124 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 5125 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 5126 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 5127 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 5128 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 5129 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 5130 u8 led3_color; 5131 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 5132 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 5133 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 5134 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 5135 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 5136 u8 unused_3; 5137 __le16 led3_blink_on; 5138 __le16 led3_blink_off; 5139 u8 led3_group_id; 5140 u8 unused_4[6]; 5141 u8 valid; 5142 }; 5143 5144 /* hwrm_port_led_qcaps_input (size:192b/24B) */ 5145 struct hwrm_port_led_qcaps_input { 5146 __le16 req_type; 5147 __le16 cmpl_ring; 5148 __le16 seq_id; 5149 __le16 target_id; 5150 __le64 resp_addr; 5151 __le16 port_id; 5152 u8 unused_0[6]; 5153 }; 5154 5155 /* hwrm_port_led_qcaps_output (size:384b/48B) */ 5156 struct hwrm_port_led_qcaps_output { 5157 __le16 error_code; 5158 __le16 req_type; 5159 __le16 seq_id; 5160 __le16 resp_len; 5161 u8 num_leds; 5162 u8 unused[3]; 5163 u8 led0_id; 5164 u8 led0_type; 5165 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 5166 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 5167 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 5168 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 5169 u8 led0_group_id; 5170 u8 unused_0; 5171 __le16 led0_state_caps; 5172 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 5173 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 5174 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 5175 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5176 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5177 __le16 led0_color_caps; 5178 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 5179 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5180 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5181 u8 led1_id; 5182 u8 led1_type; 5183 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 5184 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 5185 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 5186 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 5187 u8 led1_group_id; 5188 u8 unused_1; 5189 __le16 led1_state_caps; 5190 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 5191 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 5192 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 5193 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5194 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5195 __le16 led1_color_caps; 5196 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 5197 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5198 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5199 u8 led2_id; 5200 u8 led2_type; 5201 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 5202 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 5203 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 5204 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 5205 u8 led2_group_id; 5206 u8 unused_2; 5207 __le16 led2_state_caps; 5208 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 5209 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 5210 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 5211 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5212 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5213 __le16 led2_color_caps; 5214 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 5215 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5216 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5217 u8 led3_id; 5218 u8 led3_type; 5219 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 5220 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 5221 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 5222 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 5223 u8 led3_group_id; 5224 u8 unused_3; 5225 __le16 led3_state_caps; 5226 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 5227 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 5228 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 5229 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5230 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5231 __le16 led3_color_caps; 5232 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 5233 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5234 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5235 u8 unused_4[3]; 5236 u8 valid; 5237 }; 5238 5239 /* hwrm_queue_qportcfg_input (size:192b/24B) */ 5240 struct hwrm_queue_qportcfg_input { 5241 __le16 req_type; 5242 __le16 cmpl_ring; 5243 __le16 seq_id; 5244 __le16 target_id; 5245 __le64 resp_addr; 5246 __le32 flags; 5247 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 5248 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 5249 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 5250 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 5251 __le16 port_id; 5252 u8 drv_qmap_cap; 5253 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 5254 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 5255 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 5256 u8 unused_0; 5257 }; 5258 5259 /* hwrm_queue_qportcfg_output (size:1344b/168B) */ 5260 struct hwrm_queue_qportcfg_output { 5261 __le16 error_code; 5262 __le16 req_type; 5263 __le16 seq_id; 5264 __le16 resp_len; 5265 u8 max_configurable_queues; 5266 u8 max_configurable_lossless_queues; 5267 u8 queue_cfg_allowed; 5268 u8 queue_cfg_info; 5269 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 5270 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_USE_PROFILE_TYPE 0x2UL 5271 u8 queue_pfcenable_cfg_allowed; 5272 u8 queue_pri2cos_cfg_allowed; 5273 u8 queue_cos2bw_cfg_allowed; 5274 u8 queue_id0; 5275 u8 queue_id0_service_profile; 5276 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 5277 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 5278 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5279 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5280 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5281 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 5282 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 5283 u8 queue_id1; 5284 u8 queue_id1_service_profile; 5285 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 5286 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 5287 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5288 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5289 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5290 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 5291 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 5292 u8 queue_id2; 5293 u8 queue_id2_service_profile; 5294 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 5295 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 5296 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5297 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5298 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5299 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 5300 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 5301 u8 queue_id3; 5302 u8 queue_id3_service_profile; 5303 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 5304 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 5305 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5306 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5307 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5308 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 5309 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 5310 u8 queue_id4; 5311 u8 queue_id4_service_profile; 5312 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 5313 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 5314 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5315 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5316 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5317 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 5318 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 5319 u8 queue_id5; 5320 u8 queue_id5_service_profile; 5321 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 5322 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 5323 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5324 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5325 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5326 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 5327 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 5328 u8 queue_id6; 5329 u8 queue_id6_service_profile; 5330 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 5331 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 5332 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5333 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5334 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5335 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 5336 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 5337 u8 queue_id7; 5338 u8 queue_id7_service_profile; 5339 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 5340 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 5341 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5342 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5343 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5344 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 5345 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 5346 u8 queue_id0_service_profile_type; 5347 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5348 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC 0x2UL 5349 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP 0x4UL 5350 char qid0_name[16]; 5351 char qid1_name[16]; 5352 char qid2_name[16]; 5353 char qid3_name[16]; 5354 char qid4_name[16]; 5355 char qid5_name[16]; 5356 char qid6_name[16]; 5357 char qid7_name[16]; 5358 u8 queue_id1_service_profile_type; 5359 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5360 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC 0x2UL 5361 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP 0x4UL 5362 u8 queue_id2_service_profile_type; 5363 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5364 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC 0x2UL 5365 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP 0x4UL 5366 u8 queue_id3_service_profile_type; 5367 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5368 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC 0x2UL 5369 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP 0x4UL 5370 u8 queue_id4_service_profile_type; 5371 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5372 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC 0x2UL 5373 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP 0x4UL 5374 u8 queue_id5_service_profile_type; 5375 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5376 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC 0x2UL 5377 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP 0x4UL 5378 u8 queue_id6_service_profile_type; 5379 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5380 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC 0x2UL 5381 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP 0x4UL 5382 u8 queue_id7_service_profile_type; 5383 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5384 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC 0x2UL 5385 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP 0x4UL 5386 u8 valid; 5387 }; 5388 5389 /* hwrm_queue_qcfg_input (size:192b/24B) */ 5390 struct hwrm_queue_qcfg_input { 5391 __le16 req_type; 5392 __le16 cmpl_ring; 5393 __le16 seq_id; 5394 __le16 target_id; 5395 __le64 resp_addr; 5396 __le32 flags; 5397 #define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL 5398 #define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL 5399 #define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL 5400 #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX 5401 __le32 queue_id; 5402 }; 5403 5404 /* hwrm_queue_qcfg_output (size:128b/16B) */ 5405 struct hwrm_queue_qcfg_output { 5406 __le16 error_code; 5407 __le16 req_type; 5408 __le16 seq_id; 5409 __le16 resp_len; 5410 __le32 queue_len; 5411 u8 service_profile; 5412 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL 5413 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL 5414 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL 5415 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 5416 u8 queue_cfg_info; 5417 #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 5418 u8 unused_0; 5419 u8 valid; 5420 }; 5421 5422 /* hwrm_queue_cfg_input (size:320b/40B) */ 5423 struct hwrm_queue_cfg_input { 5424 __le16 req_type; 5425 __le16 cmpl_ring; 5426 __le16 seq_id; 5427 __le16 target_id; 5428 __le64 resp_addr; 5429 __le32 flags; 5430 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 5431 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 5432 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 5433 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 5434 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 5435 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 5436 __le32 enables; 5437 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 5438 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 5439 __le32 queue_id; 5440 __le32 dflt_len; 5441 u8 service_profile; 5442 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 5443 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 5444 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 5445 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 5446 u8 unused_0[7]; 5447 }; 5448 5449 /* hwrm_queue_cfg_output (size:128b/16B) */ 5450 struct hwrm_queue_cfg_output { 5451 __le16 error_code; 5452 __le16 req_type; 5453 __le16 seq_id; 5454 __le16 resp_len; 5455 u8 unused_0[7]; 5456 u8 valid; 5457 }; 5458 5459 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 5460 struct hwrm_queue_pfcenable_qcfg_input { 5461 __le16 req_type; 5462 __le16 cmpl_ring; 5463 __le16 seq_id; 5464 __le16 target_id; 5465 __le64 resp_addr; 5466 __le16 port_id; 5467 u8 unused_0[6]; 5468 }; 5469 5470 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 5471 struct hwrm_queue_pfcenable_qcfg_output { 5472 __le16 error_code; 5473 __le16 req_type; 5474 __le16 seq_id; 5475 __le16 resp_len; 5476 __le32 flags; 5477 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 5478 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 5479 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 5480 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 5481 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 5482 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 5483 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 5484 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 5485 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 5486 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 5487 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 5488 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 5489 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 5490 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 5491 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 5492 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 5493 u8 unused_0[3]; 5494 u8 valid; 5495 }; 5496 5497 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 5498 struct hwrm_queue_pfcenable_cfg_input { 5499 __le16 req_type; 5500 __le16 cmpl_ring; 5501 __le16 seq_id; 5502 __le16 target_id; 5503 __le64 resp_addr; 5504 __le32 flags; 5505 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 5506 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 5507 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 5508 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 5509 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 5510 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 5511 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 5512 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 5513 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 5514 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 5515 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 5516 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 5517 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 5518 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 5519 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 5520 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 5521 __le16 port_id; 5522 u8 unused_0[2]; 5523 }; 5524 5525 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 5526 struct hwrm_queue_pfcenable_cfg_output { 5527 __le16 error_code; 5528 __le16 req_type; 5529 __le16 seq_id; 5530 __le16 resp_len; 5531 u8 unused_0[7]; 5532 u8 valid; 5533 }; 5534 5535 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 5536 struct hwrm_queue_pri2cos_qcfg_input { 5537 __le16 req_type; 5538 __le16 cmpl_ring; 5539 __le16 seq_id; 5540 __le16 target_id; 5541 __le64 resp_addr; 5542 __le32 flags; 5543 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 5544 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 5545 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 5546 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 5547 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 5548 u8 port_id; 5549 u8 unused_0[3]; 5550 }; 5551 5552 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 5553 struct hwrm_queue_pri2cos_qcfg_output { 5554 __le16 error_code; 5555 __le16 req_type; 5556 __le16 seq_id; 5557 __le16 resp_len; 5558 u8 pri0_cos_queue_id; 5559 u8 pri1_cos_queue_id; 5560 u8 pri2_cos_queue_id; 5561 u8 pri3_cos_queue_id; 5562 u8 pri4_cos_queue_id; 5563 u8 pri5_cos_queue_id; 5564 u8 pri6_cos_queue_id; 5565 u8 pri7_cos_queue_id; 5566 u8 queue_cfg_info; 5567 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 5568 u8 unused_0[6]; 5569 u8 valid; 5570 }; 5571 5572 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 5573 struct hwrm_queue_pri2cos_cfg_input { 5574 __le16 req_type; 5575 __le16 cmpl_ring; 5576 __le16 seq_id; 5577 __le16 target_id; 5578 __le64 resp_addr; 5579 __le32 flags; 5580 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 5581 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 5582 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 5583 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 5584 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 5585 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 5586 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 5587 __le32 enables; 5588 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 5589 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 5590 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 5591 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 5592 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 5593 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 5594 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 5595 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 5596 u8 port_id; 5597 u8 pri0_cos_queue_id; 5598 u8 pri1_cos_queue_id; 5599 u8 pri2_cos_queue_id; 5600 u8 pri3_cos_queue_id; 5601 u8 pri4_cos_queue_id; 5602 u8 pri5_cos_queue_id; 5603 u8 pri6_cos_queue_id; 5604 u8 pri7_cos_queue_id; 5605 u8 unused_0[7]; 5606 }; 5607 5608 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 5609 struct hwrm_queue_pri2cos_cfg_output { 5610 __le16 error_code; 5611 __le16 req_type; 5612 __le16 seq_id; 5613 __le16 resp_len; 5614 u8 unused_0[7]; 5615 u8 valid; 5616 }; 5617 5618 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 5619 struct hwrm_queue_cos2bw_qcfg_input { 5620 __le16 req_type; 5621 __le16 cmpl_ring; 5622 __le16 seq_id; 5623 __le16 target_id; 5624 __le64 resp_addr; 5625 __le16 port_id; 5626 u8 unused_0[6]; 5627 }; 5628 5629 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 5630 struct hwrm_queue_cos2bw_qcfg_output { 5631 __le16 error_code; 5632 __le16 req_type; 5633 __le16 seq_id; 5634 __le16 resp_len; 5635 u8 queue_id0; 5636 u8 unused_0; 5637 __le16 unused_1; 5638 __le32 queue_id0_min_bw; 5639 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5640 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 5641 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 5642 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 5643 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 5644 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 5645 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5646 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 5647 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5648 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5649 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5650 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5651 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5652 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5653 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 5654 __le32 queue_id0_max_bw; 5655 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5656 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 5657 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 5658 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 5659 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 5660 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 5661 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5662 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 5663 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5664 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5665 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5666 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5667 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5668 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5669 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 5670 u8 queue_id0_tsa_assign; 5671 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 5672 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 5673 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5674 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 5675 u8 queue_id0_pri_lvl; 5676 u8 queue_id0_bw_weight; 5677 u8 queue_id1; 5678 __le32 queue_id1_min_bw; 5679 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5680 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 5681 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 5682 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 5683 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 5684 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 5685 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5686 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 5687 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5688 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5689 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5690 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5691 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5692 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5693 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 5694 __le32 queue_id1_max_bw; 5695 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5696 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 5697 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 5698 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 5699 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 5700 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 5701 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5702 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 5703 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5704 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5705 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5706 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5707 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5708 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5709 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 5710 u8 queue_id1_tsa_assign; 5711 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 5712 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 5713 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5714 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 5715 u8 queue_id1_pri_lvl; 5716 u8 queue_id1_bw_weight; 5717 u8 queue_id2; 5718 __le32 queue_id2_min_bw; 5719 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5720 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 5721 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 5722 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 5723 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 5724 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 5725 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5726 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 5727 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5728 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5729 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5730 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5731 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5732 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5733 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 5734 __le32 queue_id2_max_bw; 5735 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5736 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 5737 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 5738 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 5739 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 5740 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 5741 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5742 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 5743 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5744 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5745 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5746 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5747 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5748 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5749 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 5750 u8 queue_id2_tsa_assign; 5751 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 5752 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 5753 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5754 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 5755 u8 queue_id2_pri_lvl; 5756 u8 queue_id2_bw_weight; 5757 u8 queue_id3; 5758 __le32 queue_id3_min_bw; 5759 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5760 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 5761 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 5762 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 5763 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 5764 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 5765 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5766 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 5767 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5768 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5769 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5770 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5771 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5772 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5773 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 5774 __le32 queue_id3_max_bw; 5775 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5776 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 5777 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 5778 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 5779 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 5780 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 5781 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5782 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 5783 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5784 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5785 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5786 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5787 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5788 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5789 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 5790 u8 queue_id3_tsa_assign; 5791 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 5792 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 5793 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5794 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 5795 u8 queue_id3_pri_lvl; 5796 u8 queue_id3_bw_weight; 5797 u8 queue_id4; 5798 __le32 queue_id4_min_bw; 5799 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5800 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 5801 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 5802 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 5803 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 5804 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 5805 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5806 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 5807 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5808 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5809 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5810 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5811 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5812 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5813 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 5814 __le32 queue_id4_max_bw; 5815 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5816 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 5817 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 5818 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 5819 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 5820 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 5821 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5822 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 5823 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5824 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5825 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5826 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5827 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5828 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5829 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 5830 u8 queue_id4_tsa_assign; 5831 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 5832 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 5833 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5834 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 5835 u8 queue_id4_pri_lvl; 5836 u8 queue_id4_bw_weight; 5837 u8 queue_id5; 5838 __le32 queue_id5_min_bw; 5839 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5840 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 5841 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 5842 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 5843 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 5844 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 5845 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5846 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 5847 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5848 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5849 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5850 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5851 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5852 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5853 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 5854 __le32 queue_id5_max_bw; 5855 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5856 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 5857 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 5858 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 5859 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 5860 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 5861 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5862 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 5863 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5864 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5865 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5866 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5867 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5868 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5869 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 5870 u8 queue_id5_tsa_assign; 5871 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 5872 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 5873 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5874 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 5875 u8 queue_id5_pri_lvl; 5876 u8 queue_id5_bw_weight; 5877 u8 queue_id6; 5878 __le32 queue_id6_min_bw; 5879 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5880 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 5881 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 5882 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 5883 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 5884 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 5885 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5886 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 5887 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5888 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5889 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5890 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5891 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5892 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5893 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 5894 __le32 queue_id6_max_bw; 5895 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5896 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 5897 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 5898 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 5899 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 5900 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 5901 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5902 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 5903 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5904 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5905 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5906 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5907 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5908 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5909 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 5910 u8 queue_id6_tsa_assign; 5911 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 5912 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 5913 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5914 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 5915 u8 queue_id6_pri_lvl; 5916 u8 queue_id6_bw_weight; 5917 u8 queue_id7; 5918 __le32 queue_id7_min_bw; 5919 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5920 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 5921 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 5922 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 5923 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 5924 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 5925 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5926 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 5927 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5928 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5929 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5930 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5931 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5932 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5933 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 5934 __le32 queue_id7_max_bw; 5935 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5936 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 5937 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 5938 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 5939 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 5940 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 5941 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5942 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 5943 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5944 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5945 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5946 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5947 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5948 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5949 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 5950 u8 queue_id7_tsa_assign; 5951 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 5952 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 5953 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5954 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 5955 u8 queue_id7_pri_lvl; 5956 u8 queue_id7_bw_weight; 5957 u8 unused_2[4]; 5958 u8 valid; 5959 }; 5960 5961 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 5962 struct hwrm_queue_cos2bw_cfg_input { 5963 __le16 req_type; 5964 __le16 cmpl_ring; 5965 __le16 seq_id; 5966 __le16 target_id; 5967 __le64 resp_addr; 5968 __le32 flags; 5969 __le32 enables; 5970 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 5971 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 5972 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 5973 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 5974 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 5975 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 5976 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 5977 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 5978 __le16 port_id; 5979 u8 queue_id0; 5980 u8 unused_0; 5981 __le32 queue_id0_min_bw; 5982 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5983 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 5984 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 5985 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 5986 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 5987 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 5988 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5989 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 5990 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5991 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5992 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5993 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5994 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5995 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5996 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 5997 __le32 queue_id0_max_bw; 5998 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5999 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 6000 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 6001 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 6002 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 6003 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 6004 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6005 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 6006 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6007 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6008 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6009 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6010 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6011 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6012 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 6013 u8 queue_id0_tsa_assign; 6014 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 6015 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 6016 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6017 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 6018 u8 queue_id0_pri_lvl; 6019 u8 queue_id0_bw_weight; 6020 u8 queue_id1; 6021 __le32 queue_id1_min_bw; 6022 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6023 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 6024 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 6025 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 6026 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 6027 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 6028 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6029 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 6030 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6031 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6032 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6033 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6034 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6035 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6036 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 6037 __le32 queue_id1_max_bw; 6038 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6039 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 6040 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 6041 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 6042 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 6043 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 6044 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6045 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 6046 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6047 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6048 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6049 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6050 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6051 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6052 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 6053 u8 queue_id1_tsa_assign; 6054 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 6055 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 6056 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6057 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 6058 u8 queue_id1_pri_lvl; 6059 u8 queue_id1_bw_weight; 6060 u8 queue_id2; 6061 __le32 queue_id2_min_bw; 6062 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6063 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 6064 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 6065 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 6066 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 6067 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 6068 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6069 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 6070 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6071 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6072 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6073 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6074 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6075 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6076 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 6077 __le32 queue_id2_max_bw; 6078 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6079 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 6080 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 6081 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 6082 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 6083 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 6084 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6085 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 6086 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6087 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6088 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6089 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6090 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6091 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6092 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 6093 u8 queue_id2_tsa_assign; 6094 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 6095 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 6096 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6097 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 6098 u8 queue_id2_pri_lvl; 6099 u8 queue_id2_bw_weight; 6100 u8 queue_id3; 6101 __le32 queue_id3_min_bw; 6102 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6103 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 6104 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 6105 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 6106 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 6107 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 6108 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6109 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 6110 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6111 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6112 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6113 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6114 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6115 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6116 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 6117 __le32 queue_id3_max_bw; 6118 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6119 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 6120 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 6121 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 6122 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 6123 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 6124 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6125 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 6126 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6127 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6128 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6129 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6130 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6131 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6132 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 6133 u8 queue_id3_tsa_assign; 6134 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 6135 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 6136 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6137 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 6138 u8 queue_id3_pri_lvl; 6139 u8 queue_id3_bw_weight; 6140 u8 queue_id4; 6141 __le32 queue_id4_min_bw; 6142 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6143 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 6144 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 6145 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 6146 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 6147 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 6148 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6149 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 6150 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6151 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6152 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6153 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6154 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6155 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6156 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 6157 __le32 queue_id4_max_bw; 6158 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6159 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 6160 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 6161 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 6162 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 6163 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 6164 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6165 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 6166 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6167 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6168 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6169 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6170 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6171 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6172 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 6173 u8 queue_id4_tsa_assign; 6174 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 6175 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 6176 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6177 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 6178 u8 queue_id4_pri_lvl; 6179 u8 queue_id4_bw_weight; 6180 u8 queue_id5; 6181 __le32 queue_id5_min_bw; 6182 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6183 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 6184 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 6185 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 6186 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 6187 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 6188 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6189 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 6190 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6191 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6192 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6193 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6194 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6195 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6196 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 6197 __le32 queue_id5_max_bw; 6198 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6199 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 6200 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 6201 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 6202 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 6203 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 6204 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6205 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 6206 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6207 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6208 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6209 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6210 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6211 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6212 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 6213 u8 queue_id5_tsa_assign; 6214 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 6215 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 6216 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6217 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 6218 u8 queue_id5_pri_lvl; 6219 u8 queue_id5_bw_weight; 6220 u8 queue_id6; 6221 __le32 queue_id6_min_bw; 6222 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6223 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 6224 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 6225 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 6226 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 6227 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 6228 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6229 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 6230 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6231 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6232 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6233 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6234 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6235 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6236 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 6237 __le32 queue_id6_max_bw; 6238 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6239 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 6240 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 6241 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 6242 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 6243 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 6244 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6245 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 6246 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6247 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6248 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6249 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6250 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6251 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6252 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 6253 u8 queue_id6_tsa_assign; 6254 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 6255 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 6256 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6257 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 6258 u8 queue_id6_pri_lvl; 6259 u8 queue_id6_bw_weight; 6260 u8 queue_id7; 6261 __le32 queue_id7_min_bw; 6262 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6263 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 6264 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 6265 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 6266 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 6267 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 6268 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6269 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 6270 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6271 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6272 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6273 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6274 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6275 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6276 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 6277 __le32 queue_id7_max_bw; 6278 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6279 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 6280 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 6281 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 6282 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 6283 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 6284 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6285 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 6286 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6287 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6288 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6289 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6290 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6291 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6292 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 6293 u8 queue_id7_tsa_assign; 6294 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 6295 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 6296 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6297 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 6298 u8 queue_id7_pri_lvl; 6299 u8 queue_id7_bw_weight; 6300 u8 unused_1[5]; 6301 }; 6302 6303 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 6304 struct hwrm_queue_cos2bw_cfg_output { 6305 __le16 error_code; 6306 __le16 req_type; 6307 __le16 seq_id; 6308 __le16 resp_len; 6309 u8 unused_0[7]; 6310 u8 valid; 6311 }; 6312 6313 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 6314 struct hwrm_queue_dscp_qcaps_input { 6315 __le16 req_type; 6316 __le16 cmpl_ring; 6317 __le16 seq_id; 6318 __le16 target_id; 6319 __le64 resp_addr; 6320 u8 port_id; 6321 u8 unused_0[7]; 6322 }; 6323 6324 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 6325 struct hwrm_queue_dscp_qcaps_output { 6326 __le16 error_code; 6327 __le16 req_type; 6328 __le16 seq_id; 6329 __le16 resp_len; 6330 u8 num_dscp_bits; 6331 u8 unused_0; 6332 __le16 max_entries; 6333 u8 unused_1[3]; 6334 u8 valid; 6335 }; 6336 6337 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 6338 struct hwrm_queue_dscp2pri_qcfg_input { 6339 __le16 req_type; 6340 __le16 cmpl_ring; 6341 __le16 seq_id; 6342 __le16 target_id; 6343 __le64 resp_addr; 6344 __le64 dest_data_addr; 6345 u8 port_id; 6346 u8 unused_0; 6347 __le16 dest_data_buffer_size; 6348 u8 unused_1[4]; 6349 }; 6350 6351 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 6352 struct hwrm_queue_dscp2pri_qcfg_output { 6353 __le16 error_code; 6354 __le16 req_type; 6355 __le16 seq_id; 6356 __le16 resp_len; 6357 __le16 entry_cnt; 6358 u8 default_pri; 6359 u8 unused_0[4]; 6360 u8 valid; 6361 }; 6362 6363 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 6364 struct hwrm_queue_dscp2pri_cfg_input { 6365 __le16 req_type; 6366 __le16 cmpl_ring; 6367 __le16 seq_id; 6368 __le16 target_id; 6369 __le64 resp_addr; 6370 __le64 src_data_addr; 6371 __le32 flags; 6372 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 6373 __le32 enables; 6374 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 6375 u8 port_id; 6376 u8 default_pri; 6377 __le16 entry_cnt; 6378 u8 unused_0[4]; 6379 }; 6380 6381 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 6382 struct hwrm_queue_dscp2pri_cfg_output { 6383 __le16 error_code; 6384 __le16 req_type; 6385 __le16 seq_id; 6386 __le16 resp_len; 6387 u8 unused_0[7]; 6388 u8 valid; 6389 }; 6390 6391 /* hwrm_vnic_alloc_input (size:192b/24B) */ 6392 struct hwrm_vnic_alloc_input { 6393 __le16 req_type; 6394 __le16 cmpl_ring; 6395 __le16 seq_id; 6396 __le16 target_id; 6397 __le64 resp_addr; 6398 __le32 flags; 6399 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 6400 #define VNIC_ALLOC_REQ_FLAGS_VIRTIO_NET_FID_VALID 0x2UL 6401 __le16 virtio_net_fid; 6402 u8 unused_0[2]; 6403 }; 6404 6405 /* hwrm_vnic_alloc_output (size:128b/16B) */ 6406 struct hwrm_vnic_alloc_output { 6407 __le16 error_code; 6408 __le16 req_type; 6409 __le16 seq_id; 6410 __le16 resp_len; 6411 __le32 vnic_id; 6412 u8 unused_0[3]; 6413 u8 valid; 6414 }; 6415 6416 /* hwrm_vnic_free_input (size:192b/24B) */ 6417 struct hwrm_vnic_free_input { 6418 __le16 req_type; 6419 __le16 cmpl_ring; 6420 __le16 seq_id; 6421 __le16 target_id; 6422 __le64 resp_addr; 6423 __le32 vnic_id; 6424 u8 unused_0[4]; 6425 }; 6426 6427 /* hwrm_vnic_free_output (size:128b/16B) */ 6428 struct hwrm_vnic_free_output { 6429 __le16 error_code; 6430 __le16 req_type; 6431 __le16 seq_id; 6432 __le16 resp_len; 6433 u8 unused_0[7]; 6434 u8 valid; 6435 }; 6436 6437 /* hwrm_vnic_cfg_input (size:384b/48B) */ 6438 struct hwrm_vnic_cfg_input { 6439 __le16 req_type; 6440 __le16 cmpl_ring; 6441 __le16 seq_id; 6442 __le16 target_id; 6443 __le64 resp_addr; 6444 __le32 flags; 6445 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 6446 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 6447 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 6448 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 6449 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 6450 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 6451 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 6452 __le32 enables; 6453 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 6454 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 6455 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 6456 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 6457 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 6458 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 6459 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 6460 #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL 6461 #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL 6462 #define VNIC_CFG_REQ_ENABLES_L2_CQE_MODE 0x200UL 6463 __le16 vnic_id; 6464 __le16 dflt_ring_grp; 6465 __le16 rss_rule; 6466 __le16 cos_rule; 6467 __le16 lb_rule; 6468 __le16 mru; 6469 __le16 default_rx_ring_id; 6470 __le16 default_cmpl_ring_id; 6471 __le16 queue_id; 6472 u8 rx_csum_v2_mode; 6473 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL 6474 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK 0x1UL 6475 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 0x2UL 6476 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 6477 u8 l2_cqe_mode; 6478 #define VNIC_CFG_REQ_L2_CQE_MODE_DEFAULT 0x0UL 6479 #define VNIC_CFG_REQ_L2_CQE_MODE_COMPRESSED 0x1UL 6480 #define VNIC_CFG_REQ_L2_CQE_MODE_MIXED 0x2UL 6481 #define VNIC_CFG_REQ_L2_CQE_MODE_LAST VNIC_CFG_REQ_L2_CQE_MODE_MIXED 6482 u8 unused0[4]; 6483 }; 6484 6485 /* hwrm_vnic_cfg_output (size:128b/16B) */ 6486 struct hwrm_vnic_cfg_output { 6487 __le16 error_code; 6488 __le16 req_type; 6489 __le16 seq_id; 6490 __le16 resp_len; 6491 u8 unused_0[7]; 6492 u8 valid; 6493 }; 6494 6495 /* hwrm_vnic_qcaps_input (size:192b/24B) */ 6496 struct hwrm_vnic_qcaps_input { 6497 __le16 req_type; 6498 __le16 cmpl_ring; 6499 __le16 seq_id; 6500 __le16 target_id; 6501 __le64 resp_addr; 6502 __le32 enables; 6503 u8 unused_0[4]; 6504 }; 6505 6506 /* hwrm_vnic_qcaps_output (size:192b/24B) */ 6507 struct hwrm_vnic_qcaps_output { 6508 __le16 error_code; 6509 __le16 req_type; 6510 __le16 seq_id; 6511 __le16 resp_len; 6512 __le16 mru; 6513 u8 unused_0[2]; 6514 __le32 flags; 6515 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 6516 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 6517 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 6518 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 6519 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 6520 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 6521 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 6522 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 6523 #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL 6524 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL 6525 #define VNIC_QCAPS_RESP_FLAGS_VNIC_STATE_CAP 0x400UL 6526 #define VNIC_QCAPS_RESP_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP 0x800UL 6527 #define VNIC_QCAPS_RESP_FLAGS_METADATA_FORMAT_CAP 0x1000UL 6528 #define VNIC_QCAPS_RESP_FLAGS_RSS_STRICT_HASH_TYPE_CAP 0x2000UL 6529 #define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP 0x4000UL 6530 #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CAP 0x8000UL 6531 #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_XOR_CAP 0x10000UL 6532 #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CHKSM_CAP 0x20000UL 6533 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPV6_FLOW_LABEL_CAP 0x40000UL 6534 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V3_CAP 0x80000UL 6535 #define VNIC_QCAPS_RESP_FLAGS_L2_CQE_MODE_CAP 0x100000UL 6536 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP 0x200000UL 6537 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP 0x400000UL 6538 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP 0x800000UL 6539 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP 0x1000000UL 6540 __le16 max_aggs_supported; 6541 u8 unused_1[5]; 6542 u8 valid; 6543 }; 6544 6545 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ 6546 struct hwrm_vnic_tpa_cfg_input { 6547 __le16 req_type; 6548 __le16 cmpl_ring; 6549 __le16 seq_id; 6550 __le16 target_id; 6551 __le64 resp_addr; 6552 __le32 flags; 6553 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 6554 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 6555 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 6556 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 6557 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 6558 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 6559 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 6560 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 6561 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL 6562 __le32 enables; 6563 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 6564 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 6565 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 6566 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 6567 __le16 vnic_id; 6568 __le16 max_agg_segs; 6569 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 6570 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 6571 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 6572 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 6573 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 6574 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 6575 __le16 max_aggs; 6576 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 6577 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 6578 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 6579 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 6580 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 6581 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 6582 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 6583 u8 unused_0[2]; 6584 __le32 max_agg_timer; 6585 __le32 min_agg_len; 6586 }; 6587 6588 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 6589 struct hwrm_vnic_tpa_cfg_output { 6590 __le16 error_code; 6591 __le16 req_type; 6592 __le16 seq_id; 6593 __le16 resp_len; 6594 u8 unused_0[7]; 6595 u8 valid; 6596 }; 6597 6598 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 6599 struct hwrm_vnic_tpa_qcfg_input { 6600 __le16 req_type; 6601 __le16 cmpl_ring; 6602 __le16 seq_id; 6603 __le16 target_id; 6604 __le64 resp_addr; 6605 __le16 vnic_id; 6606 u8 unused_0[6]; 6607 }; 6608 6609 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 6610 struct hwrm_vnic_tpa_qcfg_output { 6611 __le16 error_code; 6612 __le16 req_type; 6613 __le16 seq_id; 6614 __le16 resp_len; 6615 __le32 flags; 6616 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 6617 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 6618 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 6619 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 6620 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 6621 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 6622 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 6623 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 6624 __le16 max_agg_segs; 6625 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 6626 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 6627 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 6628 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 6629 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 6630 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 6631 __le16 max_aggs; 6632 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 6633 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 6634 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 6635 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 6636 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 6637 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 6638 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 6639 __le32 max_agg_timer; 6640 __le32 min_agg_len; 6641 u8 unused_0[7]; 6642 u8 valid; 6643 }; 6644 6645 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 6646 struct hwrm_vnic_rss_cfg_input { 6647 __le16 req_type; 6648 __le16 cmpl_ring; 6649 __le16 seq_id; 6650 __le16 target_id; 6651 __le64 resp_addr; 6652 __le32 hash_type; 6653 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 6654 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 6655 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 6656 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 6657 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 6658 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 6659 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL 0x40UL 6660 #define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 0x80UL 6661 #define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4 0x100UL 6662 #define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 0x200UL 6663 #define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6 0x400UL 6664 __le16 vnic_id; 6665 u8 ring_table_pair_index; 6666 u8 hash_mode_flags; 6667 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 6668 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 6669 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 6670 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 6671 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 6672 __le64 ring_grp_tbl_addr; 6673 __le64 hash_key_tbl_addr; 6674 __le16 rss_ctx_idx; 6675 u8 flags; 6676 #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_INCLUDE 0x1UL 6677 #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_EXCLUDE 0x2UL 6678 u8 ring_select_mode; 6679 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ 0x0UL 6680 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_XOR 0x1UL 6681 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL 6682 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_LAST VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 6683 u8 unused_1[4]; 6684 }; 6685 6686 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 6687 struct hwrm_vnic_rss_cfg_output { 6688 __le16 error_code; 6689 __le16 req_type; 6690 __le16 seq_id; 6691 __le16 resp_len; 6692 u8 unused_0[7]; 6693 u8 valid; 6694 }; 6695 6696 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ 6697 struct hwrm_vnic_rss_cfg_cmd_err { 6698 u8 code; 6699 #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 6700 #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL 6701 #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 6702 u8 unused_0[7]; 6703 }; 6704 6705 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 6706 struct hwrm_vnic_plcmodes_cfg_input { 6707 __le16 req_type; 6708 __le16 cmpl_ring; 6709 __le16 seq_id; 6710 __le16 target_id; 6711 __le64 resp_addr; 6712 __le32 flags; 6713 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 6714 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 6715 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 6716 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 6717 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 6718 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 6719 #define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT 0x40UL 6720 __le32 enables; 6721 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 6722 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 6723 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 6724 #define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID 0x8UL 6725 __le32 vnic_id; 6726 __le16 jumbo_thresh; 6727 __le16 hds_offset; 6728 __le16 hds_threshold; 6729 __le16 max_bds; 6730 u8 unused_0[4]; 6731 }; 6732 6733 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 6734 struct hwrm_vnic_plcmodes_cfg_output { 6735 __le16 error_code; 6736 __le16 req_type; 6737 __le16 seq_id; 6738 __le16 resp_len; 6739 u8 unused_0[7]; 6740 u8 valid; 6741 }; 6742 6743 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 6744 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 6745 __le16 req_type; 6746 __le16 cmpl_ring; 6747 __le16 seq_id; 6748 __le16 target_id; 6749 __le64 resp_addr; 6750 }; 6751 6752 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 6753 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 6754 __le16 error_code; 6755 __le16 req_type; 6756 __le16 seq_id; 6757 __le16 resp_len; 6758 __le16 rss_cos_lb_ctx_id; 6759 u8 unused_0[5]; 6760 u8 valid; 6761 }; 6762 6763 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 6764 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 6765 __le16 req_type; 6766 __le16 cmpl_ring; 6767 __le16 seq_id; 6768 __le16 target_id; 6769 __le64 resp_addr; 6770 __le16 rss_cos_lb_ctx_id; 6771 u8 unused_0[6]; 6772 }; 6773 6774 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 6775 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 6776 __le16 error_code; 6777 __le16 req_type; 6778 __le16 seq_id; 6779 __le16 resp_len; 6780 u8 unused_0[7]; 6781 u8 valid; 6782 }; 6783 6784 /* hwrm_ring_alloc_input (size:704b/88B) */ 6785 struct hwrm_ring_alloc_input { 6786 __le16 req_type; 6787 __le16 cmpl_ring; 6788 __le16 seq_id; 6789 __le16 target_id; 6790 __le64 resp_addr; 6791 __le32 enables; 6792 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 6793 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 6794 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 6795 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 6796 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 6797 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 6798 #define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL 6799 #define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL 6800 u8 ring_type; 6801 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 6802 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 6803 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 6804 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 6805 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 6806 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 6807 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 6808 u8 cmpl_coal_cnt; 6809 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_OFF 0x0UL 6810 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_4 0x1UL 6811 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_8 0x2UL 6812 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_12 0x3UL 6813 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_16 0x4UL 6814 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_24 0x5UL 6815 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_32 0x6UL 6816 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_48 0x7UL 6817 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_64 0x8UL 6818 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_96 0x9UL 6819 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_128 0xaUL 6820 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_192 0xbUL 6821 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_256 0xcUL 6822 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_320 0xdUL 6823 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_384 0xeUL 6824 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 0xfUL 6825 #define RING_ALLOC_REQ_CMPL_COAL_CNT_LAST RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 6826 __le16 flags; 6827 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 6828 #define RING_ALLOC_REQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION 0x2UL 6829 #define RING_ALLOC_REQ_FLAGS_NQ_DBR_PACING 0x4UL 6830 __le64 page_tbl_addr; 6831 __le32 fbo; 6832 u8 page_size; 6833 u8 page_tbl_depth; 6834 __le16 schq_id; 6835 __le32 length; 6836 __le16 logical_id; 6837 __le16 cmpl_ring_id; 6838 __le16 queue_id; 6839 __le16 rx_buf_size; 6840 __le16 rx_ring_id; 6841 __le16 nq_ring_id; 6842 __le16 ring_arb_cfg; 6843 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 6844 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 6845 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 6846 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 6847 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 6848 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 6849 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 6850 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 6851 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 6852 __le16 unused_3; 6853 __le32 reserved3; 6854 __le32 stat_ctx_id; 6855 __le32 reserved4; 6856 __le32 max_bw; 6857 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6858 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 6859 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 6860 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 6861 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 6862 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 6863 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6864 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 6865 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6866 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6867 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6868 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6869 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6870 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6871 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 6872 u8 int_mode; 6873 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 6874 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 6875 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 6876 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 6877 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 6878 u8 mpc_chnls_type; 6879 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE 0x0UL 6880 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE 0x1UL 6881 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA 0x2UL 6882 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL 6883 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL 6884 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 6885 u8 unused_4[2]; 6886 __le64 cq_handle; 6887 }; 6888 6889 /* hwrm_ring_alloc_output (size:128b/16B) */ 6890 struct hwrm_ring_alloc_output { 6891 __le16 error_code; 6892 __le16 req_type; 6893 __le16 seq_id; 6894 __le16 resp_len; 6895 __le16 ring_id; 6896 __le16 logical_ring_id; 6897 u8 push_buffer_index; 6898 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 6899 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 6900 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_LAST RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 6901 u8 unused_0[2]; 6902 u8 valid; 6903 }; 6904 6905 /* hwrm_ring_free_input (size:256b/32B) */ 6906 struct hwrm_ring_free_input { 6907 __le16 req_type; 6908 __le16 cmpl_ring; 6909 __le16 seq_id; 6910 __le16 target_id; 6911 __le64 resp_addr; 6912 u8 ring_type; 6913 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 6914 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 6915 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 6916 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 6917 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 6918 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 6919 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 6920 u8 flags; 6921 #define RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 0x1UL 6922 #define RING_FREE_REQ_FLAGS_LAST RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 6923 __le16 ring_id; 6924 __le32 prod_idx; 6925 __le32 opaque; 6926 __le32 unused_1; 6927 }; 6928 6929 /* hwrm_ring_free_output (size:128b/16B) */ 6930 struct hwrm_ring_free_output { 6931 __le16 error_code; 6932 __le16 req_type; 6933 __le16 seq_id; 6934 __le16 resp_len; 6935 u8 unused_0[7]; 6936 u8 valid; 6937 }; 6938 6939 /* hwrm_ring_reset_input (size:192b/24B) */ 6940 struct hwrm_ring_reset_input { 6941 __le16 req_type; 6942 __le16 cmpl_ring; 6943 __le16 seq_id; 6944 __le16 target_id; 6945 __le64 resp_addr; 6946 u8 ring_type; 6947 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 6948 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 6949 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 6950 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 6951 #define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL 6952 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_RX_RING_GRP 6953 u8 unused_0; 6954 __le16 ring_id; 6955 u8 unused_1[4]; 6956 }; 6957 6958 /* hwrm_ring_reset_output (size:128b/16B) */ 6959 struct hwrm_ring_reset_output { 6960 __le16 error_code; 6961 __le16 req_type; 6962 __le16 seq_id; 6963 __le16 resp_len; 6964 u8 push_buffer_index; 6965 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 6966 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 6967 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_LAST RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 6968 u8 unused_0[3]; 6969 u8 consumer_idx[3]; 6970 u8 valid; 6971 }; 6972 6973 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 6974 struct hwrm_ring_aggint_qcaps_input { 6975 __le16 req_type; 6976 __le16 cmpl_ring; 6977 __le16 seq_id; 6978 __le16 target_id; 6979 __le64 resp_addr; 6980 }; 6981 6982 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 6983 struct hwrm_ring_aggint_qcaps_output { 6984 __le16 error_code; 6985 __le16 req_type; 6986 __le16 seq_id; 6987 __le16 resp_len; 6988 __le32 cmpl_params; 6989 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 6990 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 6991 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 6992 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 6993 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 6994 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 6995 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 6996 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 6997 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 6998 __le32 nq_params; 6999 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 7000 __le16 num_cmpl_dma_aggr_min; 7001 __le16 num_cmpl_dma_aggr_max; 7002 __le16 num_cmpl_dma_aggr_during_int_min; 7003 __le16 num_cmpl_dma_aggr_during_int_max; 7004 __le16 cmpl_aggr_dma_tmr_min; 7005 __le16 cmpl_aggr_dma_tmr_max; 7006 __le16 cmpl_aggr_dma_tmr_during_int_min; 7007 __le16 cmpl_aggr_dma_tmr_during_int_max; 7008 __le16 int_lat_tmr_min_min; 7009 __le16 int_lat_tmr_min_max; 7010 __le16 int_lat_tmr_max_min; 7011 __le16 int_lat_tmr_max_max; 7012 __le16 num_cmpl_aggr_int_min; 7013 __le16 num_cmpl_aggr_int_max; 7014 __le16 timer_units; 7015 u8 unused_0[1]; 7016 u8 valid; 7017 }; 7018 7019 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 7020 struct hwrm_ring_cmpl_ring_qaggint_params_input { 7021 __le16 req_type; 7022 __le16 cmpl_ring; 7023 __le16 seq_id; 7024 __le16 target_id; 7025 __le64 resp_addr; 7026 __le16 ring_id; 7027 __le16 flags; 7028 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL 7029 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0 7030 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 7031 u8 unused_0[4]; 7032 }; 7033 7034 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 7035 struct hwrm_ring_cmpl_ring_qaggint_params_output { 7036 __le16 error_code; 7037 __le16 req_type; 7038 __le16 seq_id; 7039 __le16 resp_len; 7040 __le16 flags; 7041 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 7042 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 7043 __le16 num_cmpl_dma_aggr; 7044 __le16 num_cmpl_dma_aggr_during_int; 7045 __le16 cmpl_aggr_dma_tmr; 7046 __le16 cmpl_aggr_dma_tmr_during_int; 7047 __le16 int_lat_tmr_min; 7048 __le16 int_lat_tmr_max; 7049 __le16 num_cmpl_aggr_int; 7050 u8 unused_0[7]; 7051 u8 valid; 7052 }; 7053 7054 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 7055 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 7056 __le16 req_type; 7057 __le16 cmpl_ring; 7058 __le16 seq_id; 7059 __le16 target_id; 7060 __le64 resp_addr; 7061 __le16 ring_id; 7062 __le16 flags; 7063 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 7064 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 7065 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 7066 __le16 num_cmpl_dma_aggr; 7067 __le16 num_cmpl_dma_aggr_during_int; 7068 __le16 cmpl_aggr_dma_tmr; 7069 __le16 cmpl_aggr_dma_tmr_during_int; 7070 __le16 int_lat_tmr_min; 7071 __le16 int_lat_tmr_max; 7072 __le16 num_cmpl_aggr_int; 7073 __le16 enables; 7074 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 7075 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 7076 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 7077 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 7078 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 7079 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 7080 u8 unused_0[4]; 7081 }; 7082 7083 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 7084 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 7085 __le16 error_code; 7086 __le16 req_type; 7087 __le16 seq_id; 7088 __le16 resp_len; 7089 u8 unused_0[7]; 7090 u8 valid; 7091 }; 7092 7093 /* hwrm_ring_grp_alloc_input (size:192b/24B) */ 7094 struct hwrm_ring_grp_alloc_input { 7095 __le16 req_type; 7096 __le16 cmpl_ring; 7097 __le16 seq_id; 7098 __le16 target_id; 7099 __le64 resp_addr; 7100 __le16 cr; 7101 __le16 rr; 7102 __le16 ar; 7103 __le16 sc; 7104 }; 7105 7106 /* hwrm_ring_grp_alloc_output (size:128b/16B) */ 7107 struct hwrm_ring_grp_alloc_output { 7108 __le16 error_code; 7109 __le16 req_type; 7110 __le16 seq_id; 7111 __le16 resp_len; 7112 __le32 ring_group_id; 7113 u8 unused_0[3]; 7114 u8 valid; 7115 }; 7116 7117 /* hwrm_ring_grp_free_input (size:192b/24B) */ 7118 struct hwrm_ring_grp_free_input { 7119 __le16 req_type; 7120 __le16 cmpl_ring; 7121 __le16 seq_id; 7122 __le16 target_id; 7123 __le64 resp_addr; 7124 __le32 ring_group_id; 7125 u8 unused_0[4]; 7126 }; 7127 7128 /* hwrm_ring_grp_free_output (size:128b/16B) */ 7129 struct hwrm_ring_grp_free_output { 7130 __le16 error_code; 7131 __le16 req_type; 7132 __le16 seq_id; 7133 __le16 resp_len; 7134 u8 unused_0[7]; 7135 u8 valid; 7136 }; 7137 7138 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL 7139 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL 7140 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL 7141 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL 7142 7143 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 7144 struct hwrm_cfa_l2_filter_alloc_input { 7145 __le16 req_type; 7146 __le16 cmpl_ring; 7147 __le16 seq_id; 7148 __le16 target_id; 7149 __le64 resp_addr; 7150 __le32 flags; 7151 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 7152 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 7153 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 7154 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 7155 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 7156 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 7157 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 7158 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 7159 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 7160 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 7161 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 7162 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 7163 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 7164 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL 7165 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL 7166 __le32 enables; 7167 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 7168 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 7169 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 7170 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 7171 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 7172 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 7173 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 7174 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 7175 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 7176 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 7177 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 7178 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 7179 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 7180 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 7181 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 7182 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 7183 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 7184 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL 7185 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL 7186 u8 l2_addr[6]; 7187 u8 num_vlans; 7188 u8 t_num_vlans; 7189 u8 l2_addr_mask[6]; 7190 __le16 l2_ovlan; 7191 __le16 l2_ovlan_mask; 7192 __le16 l2_ivlan; 7193 __le16 l2_ivlan_mask; 7194 u8 unused_1[2]; 7195 u8 t_l2_addr[6]; 7196 u8 unused_2[2]; 7197 u8 t_l2_addr_mask[6]; 7198 __le16 t_l2_ovlan; 7199 __le16 t_l2_ovlan_mask; 7200 __le16 t_l2_ivlan; 7201 __le16 t_l2_ivlan_mask; 7202 u8 src_type; 7203 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 7204 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 7205 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 7206 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 7207 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 7208 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 7209 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 7210 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 7211 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 7212 u8 unused_3; 7213 __le32 src_id; 7214 u8 tunnel_type; 7215 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7216 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7217 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7218 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7219 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7220 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7221 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7222 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7223 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7224 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7225 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7226 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7227 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7228 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7229 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7230 u8 unused_4; 7231 __le16 dst_id; 7232 __le16 mirror_vnic_id; 7233 u8 pri_hint; 7234 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 7235 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 7236 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 7237 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 7238 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 7239 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 7240 u8 unused_5; 7241 __le32 unused_6; 7242 __le64 l2_filter_id_hint; 7243 }; 7244 7245 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 7246 struct hwrm_cfa_l2_filter_alloc_output { 7247 __le16 error_code; 7248 __le16 req_type; 7249 __le16 seq_id; 7250 __le16 resp_len; 7251 __le64 l2_filter_id; 7252 __le32 flow_id; 7253 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7254 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7255 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7256 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7257 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7258 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 7259 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7260 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7261 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7262 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7263 u8 unused_0[3]; 7264 u8 valid; 7265 }; 7266 7267 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 7268 struct hwrm_cfa_l2_filter_free_input { 7269 __le16 req_type; 7270 __le16 cmpl_ring; 7271 __le16 seq_id; 7272 __le16 target_id; 7273 __le64 resp_addr; 7274 __le64 l2_filter_id; 7275 }; 7276 7277 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 7278 struct hwrm_cfa_l2_filter_free_output { 7279 __le16 error_code; 7280 __le16 req_type; 7281 __le16 seq_id; 7282 __le16 resp_len; 7283 u8 unused_0[7]; 7284 u8 valid; 7285 }; 7286 7287 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ 7288 struct hwrm_cfa_l2_filter_cfg_input { 7289 __le16 req_type; 7290 __le16 cmpl_ring; 7291 __le16 seq_id; 7292 __le16 target_id; 7293 __le64 resp_addr; 7294 __le32 flags; 7295 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 7296 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 7297 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 7298 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 7299 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 7300 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 7301 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 7302 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 7303 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 7304 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 7305 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 7306 __le32 enables; 7307 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 7308 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 7309 __le64 l2_filter_id; 7310 __le32 dst_id; 7311 __le32 new_mirror_vnic_id; 7312 }; 7313 7314 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 7315 struct hwrm_cfa_l2_filter_cfg_output { 7316 __le16 error_code; 7317 __le16 req_type; 7318 __le16 seq_id; 7319 __le16 resp_len; 7320 u8 unused_0[7]; 7321 u8 valid; 7322 }; 7323 7324 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 7325 struct hwrm_cfa_l2_set_rx_mask_input { 7326 __le16 req_type; 7327 __le16 cmpl_ring; 7328 __le16 seq_id; 7329 __le16 target_id; 7330 __le64 resp_addr; 7331 __le32 vnic_id; 7332 __le32 mask; 7333 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 7334 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 7335 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 7336 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 7337 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 7338 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 7339 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 7340 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 7341 __le64 mc_tbl_addr; 7342 __le32 num_mc_entries; 7343 u8 unused_0[4]; 7344 __le64 vlan_tag_tbl_addr; 7345 __le32 num_vlan_tags; 7346 u8 unused_1[4]; 7347 }; 7348 7349 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 7350 struct hwrm_cfa_l2_set_rx_mask_output { 7351 __le16 error_code; 7352 __le16 req_type; 7353 __le16 seq_id; 7354 __le16 resp_len; 7355 u8 unused_0[7]; 7356 u8 valid; 7357 }; 7358 7359 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 7360 struct hwrm_cfa_l2_set_rx_mask_cmd_err { 7361 u8 code; 7362 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 7363 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 7364 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 7365 u8 unused_0[7]; 7366 }; 7367 7368 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 7369 struct hwrm_cfa_tunnel_filter_alloc_input { 7370 __le16 req_type; 7371 __le16 cmpl_ring; 7372 __le16 seq_id; 7373 __le16 target_id; 7374 __le64 resp_addr; 7375 __le32 flags; 7376 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7377 __le32 enables; 7378 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 7379 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 7380 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 7381 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 7382 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 7383 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 7384 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 7385 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 7386 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 7387 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 7388 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 7389 __le64 l2_filter_id; 7390 u8 l2_addr[6]; 7391 __le16 l2_ivlan; 7392 __le32 l3_addr[4]; 7393 __le32 t_l3_addr[4]; 7394 u8 l3_addr_type; 7395 u8 t_l3_addr_type; 7396 u8 tunnel_type; 7397 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7398 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7399 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7400 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7401 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7402 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7403 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7404 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7405 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7406 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7407 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7408 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7409 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7410 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7411 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7412 u8 tunnel_flags; 7413 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 7414 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 7415 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 7416 __le32 vni; 7417 __le32 dst_vnic_id; 7418 __le32 mirror_vnic_id; 7419 }; 7420 7421 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 7422 struct hwrm_cfa_tunnel_filter_alloc_output { 7423 __le16 error_code; 7424 __le16 req_type; 7425 __le16 seq_id; 7426 __le16 resp_len; 7427 __le64 tunnel_filter_id; 7428 __le32 flow_id; 7429 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7430 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7431 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7432 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7433 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7434 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 7435 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7436 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7437 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7438 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7439 u8 unused_0[3]; 7440 u8 valid; 7441 }; 7442 7443 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 7444 struct hwrm_cfa_tunnel_filter_free_input { 7445 __le16 req_type; 7446 __le16 cmpl_ring; 7447 __le16 seq_id; 7448 __le16 target_id; 7449 __le64 resp_addr; 7450 __le64 tunnel_filter_id; 7451 }; 7452 7453 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 7454 struct hwrm_cfa_tunnel_filter_free_output { 7455 __le16 error_code; 7456 __le16 req_type; 7457 __le16 seq_id; 7458 __le16 resp_len; 7459 u8 unused_0[7]; 7460 u8 valid; 7461 }; 7462 7463 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 7464 struct hwrm_vxlan_ipv4_hdr { 7465 u8 ver_hlen; 7466 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 7467 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 7468 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 7469 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 7470 u8 tos; 7471 __be16 ip_id; 7472 __be16 flags_frag_offset; 7473 u8 ttl; 7474 u8 protocol; 7475 __be32 src_ip_addr; 7476 __be32 dest_ip_addr; 7477 }; 7478 7479 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 7480 struct hwrm_vxlan_ipv6_hdr { 7481 __be32 ver_tc_flow_label; 7482 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 7483 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 7484 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 7485 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 7486 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 7487 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 7488 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 7489 __be16 payload_len; 7490 u8 next_hdr; 7491 u8 ttl; 7492 __be32 src_ip_addr[4]; 7493 __be32 dest_ip_addr[4]; 7494 }; 7495 7496 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 7497 struct hwrm_cfa_encap_data_vxlan { 7498 u8 src_mac_addr[6]; 7499 __le16 unused_0; 7500 u8 dst_mac_addr[6]; 7501 u8 num_vlan_tags; 7502 u8 unused_1; 7503 __be16 ovlan_tpid; 7504 __be16 ovlan_tci; 7505 __be16 ivlan_tpid; 7506 __be16 ivlan_tci; 7507 __le32 l3[10]; 7508 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 7509 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 7510 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 7511 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 7512 __be16 src_port; 7513 __be16 dst_port; 7514 __be32 vni; 7515 u8 hdr_rsvd0[3]; 7516 u8 hdr_rsvd1; 7517 u8 hdr_flags; 7518 u8 unused[3]; 7519 }; 7520 7521 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 7522 struct hwrm_cfa_encap_record_alloc_input { 7523 __le16 req_type; 7524 __le16 cmpl_ring; 7525 __le16 seq_id; 7526 __le16 target_id; 7527 __le64 resp_addr; 7528 __le32 flags; 7529 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7530 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL 7531 u8 encap_type; 7532 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 7533 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 7534 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 7535 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 7536 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 7537 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 7538 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 7539 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 7540 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 7541 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 7542 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 7543 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL 7544 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 7545 u8 unused_0[3]; 7546 __le32 encap_data[20]; 7547 }; 7548 7549 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 7550 struct hwrm_cfa_encap_record_alloc_output { 7551 __le16 error_code; 7552 __le16 req_type; 7553 __le16 seq_id; 7554 __le16 resp_len; 7555 __le32 encap_record_id; 7556 u8 unused_0[3]; 7557 u8 valid; 7558 }; 7559 7560 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 7561 struct hwrm_cfa_encap_record_free_input { 7562 __le16 req_type; 7563 __le16 cmpl_ring; 7564 __le16 seq_id; 7565 __le16 target_id; 7566 __le64 resp_addr; 7567 __le32 encap_record_id; 7568 u8 unused_0[4]; 7569 }; 7570 7571 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 7572 struct hwrm_cfa_encap_record_free_output { 7573 __le16 error_code; 7574 __le16 req_type; 7575 __le16 seq_id; 7576 __le16 resp_len; 7577 u8 unused_0[7]; 7578 u8 valid; 7579 }; 7580 7581 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 7582 struct hwrm_cfa_ntuple_filter_alloc_input { 7583 __le16 req_type; 7584 __le16 cmpl_ring; 7585 __le16 seq_id; 7586 __le16 target_id; 7587 __le64 resp_addr; 7588 __le32 flags; 7589 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7590 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 7591 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 7592 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL 7593 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL 7594 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL 7595 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_NO_L2_CONTEXT 0x40UL 7596 __le32 enables; 7597 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 7598 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 7599 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 7600 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 7601 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 7602 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 7603 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 7604 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 7605 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 7606 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 7607 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 7608 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 7609 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 7610 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 7611 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 7612 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 7613 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 7614 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 7615 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 7616 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL 7617 __le64 l2_filter_id; 7618 u8 src_macaddr[6]; 7619 __be16 ethertype; 7620 u8 ip_addr_type; 7621 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 7622 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 7623 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 7624 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 7625 u8 ip_protocol; 7626 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 7627 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 7628 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 7629 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 7630 __le16 dst_id; 7631 __le16 mirror_vnic_id; 7632 u8 tunnel_type; 7633 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7634 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7635 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7636 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7637 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7638 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7639 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7640 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7641 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7642 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7643 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7644 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7645 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7646 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7647 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7648 u8 pri_hint; 7649 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 7650 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 7651 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 7652 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 7653 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 7654 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 7655 __be32 src_ipaddr[4]; 7656 __be32 src_ipaddr_mask[4]; 7657 __be32 dst_ipaddr[4]; 7658 __be32 dst_ipaddr_mask[4]; 7659 __be16 src_port; 7660 __be16 src_port_mask; 7661 __be16 dst_port; 7662 __be16 dst_port_mask; 7663 __le64 ntuple_filter_id_hint; 7664 }; 7665 7666 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 7667 struct hwrm_cfa_ntuple_filter_alloc_output { 7668 __le16 error_code; 7669 __le16 req_type; 7670 __le16 seq_id; 7671 __le16 resp_len; 7672 __le64 ntuple_filter_id; 7673 __le32 flow_id; 7674 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7675 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7676 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7677 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7678 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7679 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 7680 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7681 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7682 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7683 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7684 u8 unused_0[3]; 7685 u8 valid; 7686 }; 7687 7688 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 7689 struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 7690 u8 code; 7691 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 7692 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 7693 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 7694 u8 unused_0[7]; 7695 }; 7696 7697 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 7698 struct hwrm_cfa_ntuple_filter_free_input { 7699 __le16 req_type; 7700 __le16 cmpl_ring; 7701 __le16 seq_id; 7702 __le16 target_id; 7703 __le64 resp_addr; 7704 __le64 ntuple_filter_id; 7705 }; 7706 7707 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 7708 struct hwrm_cfa_ntuple_filter_free_output { 7709 __le16 error_code; 7710 __le16 req_type; 7711 __le16 seq_id; 7712 __le16 resp_len; 7713 u8 unused_0[7]; 7714 u8 valid; 7715 }; 7716 7717 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 7718 struct hwrm_cfa_ntuple_filter_cfg_input { 7719 __le16 req_type; 7720 __le16 cmpl_ring; 7721 __le16 seq_id; 7722 __le16 target_id; 7723 __le64 resp_addr; 7724 __le32 enables; 7725 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 7726 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 7727 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 7728 __le32 flags; 7729 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL 7730 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL 7731 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_NO_L2_CONTEXT 0x4UL 7732 __le64 ntuple_filter_id; 7733 __le32 new_dst_id; 7734 __le32 new_mirror_vnic_id; 7735 __le16 new_meter_instance_id; 7736 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 7737 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 7738 u8 unused_1[6]; 7739 }; 7740 7741 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 7742 struct hwrm_cfa_ntuple_filter_cfg_output { 7743 __le16 error_code; 7744 __le16 req_type; 7745 __le16 seq_id; 7746 __le16 resp_len; 7747 u8 unused_0[7]; 7748 u8 valid; 7749 }; 7750 7751 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 7752 struct hwrm_cfa_decap_filter_alloc_input { 7753 __le16 req_type; 7754 __le16 cmpl_ring; 7755 __le16 seq_id; 7756 __le16 target_id; 7757 __le64 resp_addr; 7758 __le32 flags; 7759 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 7760 __le32 enables; 7761 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 7762 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 7763 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 7764 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 7765 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 7766 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 7767 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 7768 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 7769 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 7770 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 7771 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 7772 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 7773 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 7774 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 7775 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 7776 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 7777 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 7778 __be32 tunnel_id; 7779 u8 tunnel_type; 7780 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7781 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7782 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7783 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7784 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7785 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7786 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7787 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7788 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7789 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7790 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7791 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7792 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7793 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7794 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7795 u8 unused_0; 7796 __le16 unused_1; 7797 u8 src_macaddr[6]; 7798 u8 unused_2[2]; 7799 u8 dst_macaddr[6]; 7800 __be16 ovlan_vid; 7801 __be16 ivlan_vid; 7802 __be16 t_ovlan_vid; 7803 __be16 t_ivlan_vid; 7804 __be16 ethertype; 7805 u8 ip_addr_type; 7806 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 7807 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 7808 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 7809 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 7810 u8 ip_protocol; 7811 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 7812 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 7813 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 7814 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 7815 __le16 unused_3; 7816 __le32 unused_4; 7817 __be32 src_ipaddr[4]; 7818 __be32 dst_ipaddr[4]; 7819 __be16 src_port; 7820 __be16 dst_port; 7821 __le16 dst_id; 7822 __le16 l2_ctxt_ref_id; 7823 }; 7824 7825 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 7826 struct hwrm_cfa_decap_filter_alloc_output { 7827 __le16 error_code; 7828 __le16 req_type; 7829 __le16 seq_id; 7830 __le16 resp_len; 7831 __le32 decap_filter_id; 7832 u8 unused_0[3]; 7833 u8 valid; 7834 }; 7835 7836 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 7837 struct hwrm_cfa_decap_filter_free_input { 7838 __le16 req_type; 7839 __le16 cmpl_ring; 7840 __le16 seq_id; 7841 __le16 target_id; 7842 __le64 resp_addr; 7843 __le32 decap_filter_id; 7844 u8 unused_0[4]; 7845 }; 7846 7847 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 7848 struct hwrm_cfa_decap_filter_free_output { 7849 __le16 error_code; 7850 __le16 req_type; 7851 __le16 seq_id; 7852 __le16 resp_len; 7853 u8 unused_0[7]; 7854 u8 valid; 7855 }; 7856 7857 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 7858 struct hwrm_cfa_flow_alloc_input { 7859 __le16 req_type; 7860 __le16 cmpl_ring; 7861 __le16 seq_id; 7862 __le16 target_id; 7863 __le64 resp_addr; 7864 __le16 flags; 7865 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 7866 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 7867 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 7868 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 7869 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 7870 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 7871 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 7872 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 7873 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 7874 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 7875 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 7876 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 7877 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 7878 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 7879 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 7880 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 7881 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL 7882 __le16 src_fid; 7883 __le32 tunnel_handle; 7884 __le16 action_flags; 7885 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 7886 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 7887 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 7888 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 7889 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 7890 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 7891 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 7892 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 7893 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 7894 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 7895 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 7896 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL 7897 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL 7898 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL 7899 __le16 dst_fid; 7900 __be16 l2_rewrite_vlan_tpid; 7901 __be16 l2_rewrite_vlan_tci; 7902 __le16 act_meter_id; 7903 __le16 ref_flow_handle; 7904 __be16 ethertype; 7905 __be16 outer_vlan_tci; 7906 __be16 dmac[3]; 7907 __be16 inner_vlan_tci; 7908 __be16 smac[3]; 7909 u8 ip_dst_mask_len; 7910 u8 ip_src_mask_len; 7911 __be32 ip_dst[4]; 7912 __be32 ip_src[4]; 7913 __be16 l4_src_port; 7914 __be16 l4_src_port_mask; 7915 __be16 l4_dst_port; 7916 __be16 l4_dst_port_mask; 7917 __be32 nat_ip_address[4]; 7918 __be16 l2_rewrite_dmac[3]; 7919 __be16 nat_port; 7920 __be16 l2_rewrite_smac[3]; 7921 u8 ip_proto; 7922 u8 tunnel_type; 7923 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7924 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7925 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7926 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7927 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7928 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7929 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7930 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7931 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7932 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7933 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7934 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7935 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7936 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7937 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7938 }; 7939 7940 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 7941 struct hwrm_cfa_flow_alloc_output { 7942 __le16 error_code; 7943 __le16 req_type; 7944 __le16 seq_id; 7945 __le16 resp_len; 7946 __le16 flow_handle; 7947 u8 unused_0[2]; 7948 __le32 flow_id; 7949 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7950 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7951 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7952 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7953 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7954 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT 7955 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7956 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7957 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7958 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX 7959 __le64 ext_flow_handle; 7960 __le32 flow_counter_id; 7961 u8 unused_1[3]; 7962 u8 valid; 7963 }; 7964 7965 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ 7966 struct hwrm_cfa_flow_alloc_cmd_err { 7967 u8 code; 7968 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 7969 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL 7970 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL 7971 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL 7972 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL 7973 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL 7974 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL 7975 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL 7976 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 7977 u8 unused_0[7]; 7978 }; 7979 7980 /* hwrm_cfa_flow_free_input (size:256b/32B) */ 7981 struct hwrm_cfa_flow_free_input { 7982 __le16 req_type; 7983 __le16 cmpl_ring; 7984 __le16 seq_id; 7985 __le16 target_id; 7986 __le64 resp_addr; 7987 __le16 flow_handle; 7988 __le16 unused_0; 7989 __le32 flow_counter_id; 7990 __le64 ext_flow_handle; 7991 }; 7992 7993 /* hwrm_cfa_flow_free_output (size:256b/32B) */ 7994 struct hwrm_cfa_flow_free_output { 7995 __le16 error_code; 7996 __le16 req_type; 7997 __le16 seq_id; 7998 __le16 resp_len; 7999 __le64 packet; 8000 __le64 byte; 8001 u8 unused_0[7]; 8002 u8 valid; 8003 }; 8004 8005 /* hwrm_cfa_flow_info_input (size:256b/32B) */ 8006 struct hwrm_cfa_flow_info_input { 8007 __le16 req_type; 8008 __le16 cmpl_ring; 8009 __le16 seq_id; 8010 __le16 target_id; 8011 __le64 resp_addr; 8012 __le16 flow_handle; 8013 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL 8014 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL 8015 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL 8016 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_TX 0x3000UL 8017 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL 8018 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL 8019 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT_RX 0x9000UL 8020 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT_RX 0xa000UL 8021 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_RX 0xb000UL 8022 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX 0xc000UL 8023 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_LAST CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX 8024 u8 unused_0[6]; 8025 __le64 ext_flow_handle; 8026 }; 8027 8028 /* hwrm_cfa_flow_info_output (size:5632b/704B) */ 8029 struct hwrm_cfa_flow_info_output { 8030 __le16 error_code; 8031 __le16 req_type; 8032 __le16 seq_id; 8033 __le16 resp_len; 8034 u8 flags; 8035 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL 8036 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL 8037 u8 profile; 8038 __le16 src_fid; 8039 __le16 dst_fid; 8040 __le16 l2_ctxt_id; 8041 __le64 em_info; 8042 __le64 tcam_info; 8043 __le64 vfp_tcam_info; 8044 __le16 ar_id; 8045 __le16 flow_handle; 8046 __le32 tunnel_handle; 8047 __le16 flow_timer; 8048 u8 unused_0[6]; 8049 __le32 flow_key_data[130]; 8050 __le32 flow_action_info[30]; 8051 u8 unused_1[7]; 8052 u8 valid; 8053 }; 8054 8055 /* hwrm_cfa_flow_stats_input (size:640b/80B) */ 8056 struct hwrm_cfa_flow_stats_input { 8057 __le16 req_type; 8058 __le16 cmpl_ring; 8059 __le16 seq_id; 8060 __le16 target_id; 8061 __le64 resp_addr; 8062 __le16 num_flows; 8063 __le16 flow_handle_0; 8064 __le16 flow_handle_1; 8065 __le16 flow_handle_2; 8066 __le16 flow_handle_3; 8067 __le16 flow_handle_4; 8068 __le16 flow_handle_5; 8069 __le16 flow_handle_6; 8070 __le16 flow_handle_7; 8071 __le16 flow_handle_8; 8072 __le16 flow_handle_9; 8073 u8 unused_0[2]; 8074 __le32 flow_id_0; 8075 __le32 flow_id_1; 8076 __le32 flow_id_2; 8077 __le32 flow_id_3; 8078 __le32 flow_id_4; 8079 __le32 flow_id_5; 8080 __le32 flow_id_6; 8081 __le32 flow_id_7; 8082 __le32 flow_id_8; 8083 __le32 flow_id_9; 8084 }; 8085 8086 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 8087 struct hwrm_cfa_flow_stats_output { 8088 __le16 error_code; 8089 __le16 req_type; 8090 __le16 seq_id; 8091 __le16 resp_len; 8092 __le64 packet_0; 8093 __le64 packet_1; 8094 __le64 packet_2; 8095 __le64 packet_3; 8096 __le64 packet_4; 8097 __le64 packet_5; 8098 __le64 packet_6; 8099 __le64 packet_7; 8100 __le64 packet_8; 8101 __le64 packet_9; 8102 __le64 byte_0; 8103 __le64 byte_1; 8104 __le64 byte_2; 8105 __le64 byte_3; 8106 __le64 byte_4; 8107 __le64 byte_5; 8108 __le64 byte_6; 8109 __le64 byte_7; 8110 __le64 byte_8; 8111 __le64 byte_9; 8112 __le16 flow_hits; 8113 u8 unused_0[5]; 8114 u8 valid; 8115 }; 8116 8117 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 8118 struct hwrm_cfa_vfr_alloc_input { 8119 __le16 req_type; 8120 __le16 cmpl_ring; 8121 __le16 seq_id; 8122 __le16 target_id; 8123 __le64 resp_addr; 8124 __le16 vf_id; 8125 __le16 reserved; 8126 u8 unused_0[4]; 8127 char vfr_name[32]; 8128 }; 8129 8130 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 8131 struct hwrm_cfa_vfr_alloc_output { 8132 __le16 error_code; 8133 __le16 req_type; 8134 __le16 seq_id; 8135 __le16 resp_len; 8136 __le16 rx_cfa_code; 8137 __le16 tx_cfa_action; 8138 u8 unused_0[3]; 8139 u8 valid; 8140 }; 8141 8142 /* hwrm_cfa_vfr_free_input (size:448b/56B) */ 8143 struct hwrm_cfa_vfr_free_input { 8144 __le16 req_type; 8145 __le16 cmpl_ring; 8146 __le16 seq_id; 8147 __le16 target_id; 8148 __le64 resp_addr; 8149 char vfr_name[32]; 8150 __le16 vf_id; 8151 __le16 reserved; 8152 u8 unused_0[4]; 8153 }; 8154 8155 /* hwrm_cfa_vfr_free_output (size:128b/16B) */ 8156 struct hwrm_cfa_vfr_free_output { 8157 __le16 error_code; 8158 __le16 req_type; 8159 __le16 seq_id; 8160 __le16 resp_len; 8161 u8 unused_0[7]; 8162 u8 valid; 8163 }; 8164 8165 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ 8166 struct hwrm_cfa_eem_qcaps_input { 8167 __le16 req_type; 8168 __le16 cmpl_ring; 8169 __le16 seq_id; 8170 __le16 target_id; 8171 __le64 resp_addr; 8172 __le32 flags; 8173 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL 8174 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL 8175 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 8176 __le32 unused_0; 8177 }; 8178 8179 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ 8180 struct hwrm_cfa_eem_qcaps_output { 8181 __le16 error_code; 8182 __le16 req_type; 8183 __le16 seq_id; 8184 __le16 resp_len; 8185 __le32 flags; 8186 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL 8187 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL 8188 #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL 8189 #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL 8190 __le32 unused_0; 8191 __le32 supported; 8192 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL 8193 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL 8194 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL 8195 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL 8196 #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL 8197 __le32 max_entries_supported; 8198 __le16 key_entry_size; 8199 __le16 record_entry_size; 8200 __le16 efc_entry_size; 8201 __le16 fid_entry_size; 8202 u8 unused_1[7]; 8203 u8 valid; 8204 }; 8205 8206 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */ 8207 struct hwrm_cfa_eem_cfg_input { 8208 __le16 req_type; 8209 __le16 cmpl_ring; 8210 __le16 seq_id; 8211 __le16 target_id; 8212 __le64 resp_addr; 8213 __le32 flags; 8214 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL 8215 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL 8216 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 8217 #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL 8218 __le16 group_id; 8219 __le16 unused_0; 8220 __le32 num_entries; 8221 __le32 unused_1; 8222 __le16 key0_ctx_id; 8223 __le16 key1_ctx_id; 8224 __le16 record_ctx_id; 8225 __le16 efc_ctx_id; 8226 __le16 fid_ctx_id; 8227 __le16 unused_2; 8228 __le32 unused_3; 8229 }; 8230 8231 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */ 8232 struct hwrm_cfa_eem_cfg_output { 8233 __le16 error_code; 8234 __le16 req_type; 8235 __le16 seq_id; 8236 __le16 resp_len; 8237 u8 unused_0[7]; 8238 u8 valid; 8239 }; 8240 8241 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ 8242 struct hwrm_cfa_eem_qcfg_input { 8243 __le16 req_type; 8244 __le16 cmpl_ring; 8245 __le16 seq_id; 8246 __le16 target_id; 8247 __le64 resp_addr; 8248 __le32 flags; 8249 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL 8250 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL 8251 __le32 unused_0; 8252 }; 8253 8254 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ 8255 struct hwrm_cfa_eem_qcfg_output { 8256 __le16 error_code; 8257 __le16 req_type; 8258 __le16 seq_id; 8259 __le16 resp_len; 8260 __le32 flags; 8261 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL 8262 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL 8263 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL 8264 __le32 num_entries; 8265 __le16 key0_ctx_id; 8266 __le16 key1_ctx_id; 8267 __le16 record_ctx_id; 8268 __le16 efc_ctx_id; 8269 __le16 fid_ctx_id; 8270 u8 unused_2[5]; 8271 u8 valid; 8272 }; 8273 8274 /* hwrm_cfa_eem_op_input (size:192b/24B) */ 8275 struct hwrm_cfa_eem_op_input { 8276 __le16 req_type; 8277 __le16 cmpl_ring; 8278 __le16 seq_id; 8279 __le16 target_id; 8280 __le64 resp_addr; 8281 __le32 flags; 8282 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL 8283 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL 8284 __le16 unused_0; 8285 __le16 op; 8286 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL 8287 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL 8288 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL 8289 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL 8290 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP 8291 }; 8292 8293 /* hwrm_cfa_eem_op_output (size:128b/16B) */ 8294 struct hwrm_cfa_eem_op_output { 8295 __le16 error_code; 8296 __le16 req_type; 8297 __le16 seq_id; 8298 __le16 resp_len; 8299 u8 unused_0[7]; 8300 u8 valid; 8301 }; 8302 8303 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ 8304 struct hwrm_cfa_adv_flow_mgnt_qcaps_input { 8305 __le16 req_type; 8306 __le16 cmpl_ring; 8307 __le16 seq_id; 8308 __le16 target_id; 8309 __le64 resp_addr; 8310 __le32 unused_0[4]; 8311 }; 8312 8313 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ 8314 struct hwrm_cfa_adv_flow_mgnt_qcaps_output { 8315 __le16 error_code; 8316 __le16 req_type; 8317 __le16 seq_id; 8318 __le16 resp_len; 8319 __le32 flags; 8320 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL 8321 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL 8322 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL 8323 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL 8324 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL 8325 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL 8326 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL 8327 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL 8328 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL 8329 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL 8330 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL 8331 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL 8332 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL 8333 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL 8334 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL 8335 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TRUFLOW_CAPABLE 0x8000UL 8336 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED 0x10000UL 8337 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_LAG_SUPPORTED 0x20000UL 8338 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED 0x40000UL 8339 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NIC_FLOW_STATS_SUPPORTED 0x80000UL 8340 u8 unused_0[3]; 8341 u8 valid; 8342 }; 8343 8344 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 8345 struct hwrm_tunnel_dst_port_query_input { 8346 __le16 req_type; 8347 __le16 cmpl_ring; 8348 __le16 seq_id; 8349 __le16 target_id; 8350 __le64 resp_addr; 8351 u8 tunnel_type; 8352 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8353 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8354 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8355 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8356 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8357 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8358 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 8359 u8 unused_0[7]; 8360 }; 8361 8362 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 8363 struct hwrm_tunnel_dst_port_query_output { 8364 __le16 error_code; 8365 __le16 req_type; 8366 __le16 seq_id; 8367 __le16 resp_len; 8368 __le16 tunnel_dst_port_id; 8369 __be16 tunnel_dst_port_val; 8370 u8 unused_0[3]; 8371 u8 valid; 8372 }; 8373 8374 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 8375 struct hwrm_tunnel_dst_port_alloc_input { 8376 __le16 req_type; 8377 __le16 cmpl_ring; 8378 __le16 seq_id; 8379 __le16 target_id; 8380 __le64 resp_addr; 8381 u8 tunnel_type; 8382 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8383 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8384 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8385 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8386 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8387 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8388 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 8389 u8 unused_0; 8390 __be16 tunnel_dst_port_val; 8391 u8 unused_1[4]; 8392 }; 8393 8394 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 8395 struct hwrm_tunnel_dst_port_alloc_output { 8396 __le16 error_code; 8397 __le16 req_type; 8398 __le16 seq_id; 8399 __le16 resp_len; 8400 __le16 tunnel_dst_port_id; 8401 u8 unused_0[5]; 8402 u8 valid; 8403 }; 8404 8405 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 8406 struct hwrm_tunnel_dst_port_free_input { 8407 __le16 req_type; 8408 __le16 cmpl_ring; 8409 __le16 seq_id; 8410 __le16 target_id; 8411 __le64 resp_addr; 8412 u8 tunnel_type; 8413 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8414 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8415 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8416 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8417 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8418 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8419 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 8420 u8 unused_0; 8421 __le16 tunnel_dst_port_id; 8422 u8 unused_1[4]; 8423 }; 8424 8425 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 8426 struct hwrm_tunnel_dst_port_free_output { 8427 __le16 error_code; 8428 __le16 req_type; 8429 __le16 seq_id; 8430 __le16 resp_len; 8431 u8 unused_1[7]; 8432 u8 valid; 8433 }; 8434 8435 /* ctx_hw_stats (size:1280b/160B) */ 8436 struct ctx_hw_stats { 8437 __le64 rx_ucast_pkts; 8438 __le64 rx_mcast_pkts; 8439 __le64 rx_bcast_pkts; 8440 __le64 rx_discard_pkts; 8441 __le64 rx_error_pkts; 8442 __le64 rx_ucast_bytes; 8443 __le64 rx_mcast_bytes; 8444 __le64 rx_bcast_bytes; 8445 __le64 tx_ucast_pkts; 8446 __le64 tx_mcast_pkts; 8447 __le64 tx_bcast_pkts; 8448 __le64 tx_error_pkts; 8449 __le64 tx_discard_pkts; 8450 __le64 tx_ucast_bytes; 8451 __le64 tx_mcast_bytes; 8452 __le64 tx_bcast_bytes; 8453 __le64 tpa_pkts; 8454 __le64 tpa_bytes; 8455 __le64 tpa_events; 8456 __le64 tpa_aborts; 8457 }; 8458 8459 /* ctx_hw_stats_ext (size:1408b/176B) */ 8460 struct ctx_hw_stats_ext { 8461 __le64 rx_ucast_pkts; 8462 __le64 rx_mcast_pkts; 8463 __le64 rx_bcast_pkts; 8464 __le64 rx_discard_pkts; 8465 __le64 rx_error_pkts; 8466 __le64 rx_ucast_bytes; 8467 __le64 rx_mcast_bytes; 8468 __le64 rx_bcast_bytes; 8469 __le64 tx_ucast_pkts; 8470 __le64 tx_mcast_pkts; 8471 __le64 tx_bcast_pkts; 8472 __le64 tx_error_pkts; 8473 __le64 tx_discard_pkts; 8474 __le64 tx_ucast_bytes; 8475 __le64 tx_mcast_bytes; 8476 __le64 tx_bcast_bytes; 8477 __le64 rx_tpa_eligible_pkt; 8478 __le64 rx_tpa_eligible_bytes; 8479 __le64 rx_tpa_pkt; 8480 __le64 rx_tpa_bytes; 8481 __le64 rx_tpa_errors; 8482 __le64 rx_tpa_events; 8483 }; 8484 8485 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */ 8486 struct hwrm_stat_ctx_alloc_input { 8487 __le16 req_type; 8488 __le16 cmpl_ring; 8489 __le16 seq_id; 8490 __le16 target_id; 8491 __le64 resp_addr; 8492 __le64 stats_dma_addr; 8493 __le32 update_period_ms; 8494 u8 stat_ctx_flags; 8495 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 8496 u8 unused_0; 8497 __le16 stats_dma_length; 8498 }; 8499 8500 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 8501 struct hwrm_stat_ctx_alloc_output { 8502 __le16 error_code; 8503 __le16 req_type; 8504 __le16 seq_id; 8505 __le16 resp_len; 8506 __le32 stat_ctx_id; 8507 u8 unused_0[3]; 8508 u8 valid; 8509 }; 8510 8511 /* hwrm_stat_ctx_free_input (size:192b/24B) */ 8512 struct hwrm_stat_ctx_free_input { 8513 __le16 req_type; 8514 __le16 cmpl_ring; 8515 __le16 seq_id; 8516 __le16 target_id; 8517 __le64 resp_addr; 8518 __le32 stat_ctx_id; 8519 u8 unused_0[4]; 8520 }; 8521 8522 /* hwrm_stat_ctx_free_output (size:128b/16B) */ 8523 struct hwrm_stat_ctx_free_output { 8524 __le16 error_code; 8525 __le16 req_type; 8526 __le16 seq_id; 8527 __le16 resp_len; 8528 __le32 stat_ctx_id; 8529 u8 unused_0[3]; 8530 u8 valid; 8531 }; 8532 8533 /* hwrm_stat_ctx_query_input (size:192b/24B) */ 8534 struct hwrm_stat_ctx_query_input { 8535 __le16 req_type; 8536 __le16 cmpl_ring; 8537 __le16 seq_id; 8538 __le16 target_id; 8539 __le64 resp_addr; 8540 __le32 stat_ctx_id; 8541 u8 flags; 8542 #define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 8543 u8 unused_0[3]; 8544 }; 8545 8546 /* hwrm_stat_ctx_query_output (size:1408b/176B) */ 8547 struct hwrm_stat_ctx_query_output { 8548 __le16 error_code; 8549 __le16 req_type; 8550 __le16 seq_id; 8551 __le16 resp_len; 8552 __le64 tx_ucast_pkts; 8553 __le64 tx_mcast_pkts; 8554 __le64 tx_bcast_pkts; 8555 __le64 tx_discard_pkts; 8556 __le64 tx_error_pkts; 8557 __le64 tx_ucast_bytes; 8558 __le64 tx_mcast_bytes; 8559 __le64 tx_bcast_bytes; 8560 __le64 rx_ucast_pkts; 8561 __le64 rx_mcast_pkts; 8562 __le64 rx_bcast_pkts; 8563 __le64 rx_discard_pkts; 8564 __le64 rx_error_pkts; 8565 __le64 rx_ucast_bytes; 8566 __le64 rx_mcast_bytes; 8567 __le64 rx_bcast_bytes; 8568 __le64 rx_agg_pkts; 8569 __le64 rx_agg_bytes; 8570 __le64 rx_agg_events; 8571 __le64 rx_agg_aborts; 8572 u8 unused_0[7]; 8573 u8 valid; 8574 }; 8575 8576 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ 8577 struct hwrm_stat_ext_ctx_query_input { 8578 __le16 req_type; 8579 __le16 cmpl_ring; 8580 __le16 seq_id; 8581 __le16 target_id; 8582 __le64 resp_addr; 8583 __le32 stat_ctx_id; 8584 u8 flags; 8585 #define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 8586 u8 unused_0[3]; 8587 }; 8588 8589 /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */ 8590 struct hwrm_stat_ext_ctx_query_output { 8591 __le16 error_code; 8592 __le16 req_type; 8593 __le16 seq_id; 8594 __le16 resp_len; 8595 __le64 rx_ucast_pkts; 8596 __le64 rx_mcast_pkts; 8597 __le64 rx_bcast_pkts; 8598 __le64 rx_discard_pkts; 8599 __le64 rx_error_pkts; 8600 __le64 rx_ucast_bytes; 8601 __le64 rx_mcast_bytes; 8602 __le64 rx_bcast_bytes; 8603 __le64 tx_ucast_pkts; 8604 __le64 tx_mcast_pkts; 8605 __le64 tx_bcast_pkts; 8606 __le64 tx_error_pkts; 8607 __le64 tx_discard_pkts; 8608 __le64 tx_ucast_bytes; 8609 __le64 tx_mcast_bytes; 8610 __le64 tx_bcast_bytes; 8611 __le64 rx_tpa_eligible_pkt; 8612 __le64 rx_tpa_eligible_bytes; 8613 __le64 rx_tpa_pkt; 8614 __le64 rx_tpa_bytes; 8615 __le64 rx_tpa_errors; 8616 __le64 rx_tpa_events; 8617 u8 unused_0[7]; 8618 u8 valid; 8619 }; 8620 8621 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 8622 struct hwrm_stat_ctx_clr_stats_input { 8623 __le16 req_type; 8624 __le16 cmpl_ring; 8625 __le16 seq_id; 8626 __le16 target_id; 8627 __le64 resp_addr; 8628 __le32 stat_ctx_id; 8629 u8 unused_0[4]; 8630 }; 8631 8632 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 8633 struct hwrm_stat_ctx_clr_stats_output { 8634 __le16 error_code; 8635 __le16 req_type; 8636 __le16 seq_id; 8637 __le16 resp_len; 8638 u8 unused_0[7]; 8639 u8 valid; 8640 }; 8641 8642 /* hwrm_pcie_qstats_input (size:256b/32B) */ 8643 struct hwrm_pcie_qstats_input { 8644 __le16 req_type; 8645 __le16 cmpl_ring; 8646 __le16 seq_id; 8647 __le16 target_id; 8648 __le64 resp_addr; 8649 __le16 pcie_stat_size; 8650 u8 unused_0[6]; 8651 __le64 pcie_stat_host_addr; 8652 }; 8653 8654 /* hwrm_pcie_qstats_output (size:128b/16B) */ 8655 struct hwrm_pcie_qstats_output { 8656 __le16 error_code; 8657 __le16 req_type; 8658 __le16 seq_id; 8659 __le16 resp_len; 8660 __le16 pcie_stat_size; 8661 u8 unused_0[5]; 8662 u8 valid; 8663 }; 8664 8665 /* pcie_ctx_hw_stats (size:768b/96B) */ 8666 struct pcie_ctx_hw_stats { 8667 __le64 pcie_pl_signal_integrity; 8668 __le64 pcie_dl_signal_integrity; 8669 __le64 pcie_tl_signal_integrity; 8670 __le64 pcie_link_integrity; 8671 __le64 pcie_tx_traffic_rate; 8672 __le64 pcie_rx_traffic_rate; 8673 __le64 pcie_tx_dllp_statistics; 8674 __le64 pcie_rx_dllp_statistics; 8675 __le64 pcie_equalization_time; 8676 __le32 pcie_ltssm_histogram[4]; 8677 __le64 pcie_recovery_histogram; 8678 }; 8679 8680 /* hwrm_stat_generic_qstats_input (size:256b/32B) */ 8681 struct hwrm_stat_generic_qstats_input { 8682 __le16 req_type; 8683 __le16 cmpl_ring; 8684 __le16 seq_id; 8685 __le16 target_id; 8686 __le64 resp_addr; 8687 __le16 generic_stat_size; 8688 u8 flags; 8689 #define STAT_GENERIC_QSTATS_REQ_FLAGS_COUNTER 0x0UL 8690 #define STAT_GENERIC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 8691 #define STAT_GENERIC_QSTATS_REQ_FLAGS_LAST STAT_GENERIC_QSTATS_REQ_FLAGS_COUNTER_MASK 8692 u8 unused_0[5]; 8693 __le64 generic_stat_host_addr; 8694 }; 8695 8696 /* hwrm_stat_generic_qstats_output (size:128b/16B) */ 8697 struct hwrm_stat_generic_qstats_output { 8698 __le16 error_code; 8699 __le16 req_type; 8700 __le16 seq_id; 8701 __le16 resp_len; 8702 __le16 generic_stat_size; 8703 u8 unused_0[5]; 8704 u8 valid; 8705 }; 8706 8707 /* generic_sw_hw_stats (size:1216b/152B) */ 8708 struct generic_sw_hw_stats { 8709 __le64 pcie_statistics_tx_tlp; 8710 __le64 pcie_statistics_rx_tlp; 8711 __le64 pcie_credit_fc_hdr_posted; 8712 __le64 pcie_credit_fc_hdr_nonposted; 8713 __le64 pcie_credit_fc_hdr_cmpl; 8714 __le64 pcie_credit_fc_data_posted; 8715 __le64 pcie_credit_fc_data_nonposted; 8716 __le64 pcie_credit_fc_data_cmpl; 8717 __le64 pcie_credit_fc_tgt_nonposted; 8718 __le64 pcie_credit_fc_tgt_data_posted; 8719 __le64 pcie_credit_fc_tgt_hdr_posted; 8720 __le64 pcie_credit_fc_cmpl_hdr_posted; 8721 __le64 pcie_credit_fc_cmpl_data_posted; 8722 __le64 pcie_cmpl_longest; 8723 __le64 pcie_cmpl_shortest; 8724 __le64 cache_miss_count_cfcq; 8725 __le64 cache_miss_count_cfcs; 8726 __le64 cache_miss_count_cfcc; 8727 __le64 cache_miss_count_cfcm; 8728 }; 8729 8730 /* hwrm_fw_reset_input (size:192b/24B) */ 8731 struct hwrm_fw_reset_input { 8732 __le16 req_type; 8733 __le16 cmpl_ring; 8734 __le16 seq_id; 8735 __le16 target_id; 8736 __le64 resp_addr; 8737 u8 embedded_proc_type; 8738 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 8739 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 8740 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 8741 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 8742 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 8743 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 8744 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 8745 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 8746 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL 8747 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 8748 u8 selfrst_status; 8749 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 8750 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 8751 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 8752 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 8753 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 8754 u8 host_idx; 8755 u8 flags; 8756 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL 8757 #define FW_RESET_REQ_FLAGS_FW_ACTIVATION 0x2UL 8758 u8 unused_0[4]; 8759 }; 8760 8761 /* hwrm_fw_reset_output (size:128b/16B) */ 8762 struct hwrm_fw_reset_output { 8763 __le16 error_code; 8764 __le16 req_type; 8765 __le16 seq_id; 8766 __le16 resp_len; 8767 u8 selfrst_status; 8768 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 8769 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 8770 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 8771 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 8772 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 8773 u8 unused_0[6]; 8774 u8 valid; 8775 }; 8776 8777 /* hwrm_fw_qstatus_input (size:192b/24B) */ 8778 struct hwrm_fw_qstatus_input { 8779 __le16 req_type; 8780 __le16 cmpl_ring; 8781 __le16 seq_id; 8782 __le16 target_id; 8783 __le64 resp_addr; 8784 u8 embedded_proc_type; 8785 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 8786 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 8787 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 8788 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 8789 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 8790 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 8791 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 8792 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 8793 u8 unused_0[7]; 8794 }; 8795 8796 /* hwrm_fw_qstatus_output (size:128b/16B) */ 8797 struct hwrm_fw_qstatus_output { 8798 __le16 error_code; 8799 __le16 req_type; 8800 __le16 seq_id; 8801 __le16 resp_len; 8802 u8 selfrst_status; 8803 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 8804 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 8805 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 8806 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL 8807 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 8808 u8 nvm_option_action_status; 8809 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_NONE 0x0UL 8810 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_HOTRESET 0x1UL 8811 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_WARMBOOT 0x2UL 8812 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 0x3UL 8813 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_LAST FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 8814 u8 unused_0[5]; 8815 u8 valid; 8816 }; 8817 8818 /* hwrm_fw_set_time_input (size:256b/32B) */ 8819 struct hwrm_fw_set_time_input { 8820 __le16 req_type; 8821 __le16 cmpl_ring; 8822 __le16 seq_id; 8823 __le16 target_id; 8824 __le64 resp_addr; 8825 __le16 year; 8826 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 8827 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 8828 u8 month; 8829 u8 day; 8830 u8 hour; 8831 u8 minute; 8832 u8 second; 8833 u8 unused_0; 8834 __le16 millisecond; 8835 __le16 zone; 8836 #define FW_SET_TIME_REQ_ZONE_UTC 0 8837 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535 8838 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 8839 u8 unused_1[4]; 8840 }; 8841 8842 /* hwrm_fw_set_time_output (size:128b/16B) */ 8843 struct hwrm_fw_set_time_output { 8844 __le16 error_code; 8845 __le16 req_type; 8846 __le16 seq_id; 8847 __le16 resp_len; 8848 u8 unused_0[7]; 8849 u8 valid; 8850 }; 8851 8852 /* hwrm_struct_hdr (size:128b/16B) */ 8853 struct hwrm_struct_hdr { 8854 __le16 struct_id; 8855 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 8856 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 8857 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 8858 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 8859 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 8860 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 8861 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 8862 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL 8863 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 8864 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 8865 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 8866 #define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL 8867 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 8868 __le16 len; 8869 u8 version; 8870 u8 count; 8871 __le16 subtype; 8872 __le16 next_offset; 8873 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 8874 u8 unused_0[6]; 8875 }; 8876 8877 /* hwrm_struct_data_dcbx_app (size:64b/8B) */ 8878 struct hwrm_struct_data_dcbx_app { 8879 __be16 protocol_id; 8880 u8 protocol_selector; 8881 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 8882 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 8883 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 8884 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 8885 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 8886 u8 priority; 8887 u8 valid; 8888 u8 unused_0[3]; 8889 }; 8890 8891 /* hwrm_fw_set_structured_data_input (size:256b/32B) */ 8892 struct hwrm_fw_set_structured_data_input { 8893 __le16 req_type; 8894 __le16 cmpl_ring; 8895 __le16 seq_id; 8896 __le16 target_id; 8897 __le64 resp_addr; 8898 __le64 src_data_addr; 8899 __le16 data_len; 8900 u8 hdr_cnt; 8901 u8 unused_0[5]; 8902 }; 8903 8904 /* hwrm_fw_set_structured_data_output (size:128b/16B) */ 8905 struct hwrm_fw_set_structured_data_output { 8906 __le16 error_code; 8907 __le16 req_type; 8908 __le16 seq_id; 8909 __le16 resp_len; 8910 u8 unused_0[7]; 8911 u8 valid; 8912 }; 8913 8914 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 8915 struct hwrm_fw_set_structured_data_cmd_err { 8916 u8 code; 8917 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 8918 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 8919 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 8920 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 8921 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 8922 u8 unused_0[7]; 8923 }; 8924 8925 /* hwrm_fw_get_structured_data_input (size:256b/32B) */ 8926 struct hwrm_fw_get_structured_data_input { 8927 __le16 req_type; 8928 __le16 cmpl_ring; 8929 __le16 seq_id; 8930 __le16 target_id; 8931 __le64 resp_addr; 8932 __le64 dest_data_addr; 8933 __le16 data_len; 8934 __le16 structure_id; 8935 __le16 subtype; 8936 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 8937 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 8938 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 8939 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 8940 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 8941 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 8942 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 8943 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 8944 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 8945 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 8946 u8 count; 8947 u8 unused_0; 8948 }; 8949 8950 /* hwrm_fw_get_structured_data_output (size:128b/16B) */ 8951 struct hwrm_fw_get_structured_data_output { 8952 __le16 error_code; 8953 __le16 req_type; 8954 __le16 seq_id; 8955 __le16 resp_len; 8956 u8 hdr_cnt; 8957 u8 unused_0[6]; 8958 u8 valid; 8959 }; 8960 8961 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 8962 struct hwrm_fw_get_structured_data_cmd_err { 8963 u8 code; 8964 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 8965 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 8966 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 8967 u8 unused_0[7]; 8968 }; 8969 8970 /* hwrm_fw_livepatch_query_input (size:192b/24B) */ 8971 struct hwrm_fw_livepatch_query_input { 8972 __le16 req_type; 8973 __le16 cmpl_ring; 8974 __le16 seq_id; 8975 __le16 target_id; 8976 __le64 resp_addr; 8977 u8 fw_target; 8978 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_COMMON_FW 0x1UL 8979 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 0x2UL 8980 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_LAST FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 8981 u8 unused_0[7]; 8982 }; 8983 8984 /* hwrm_fw_livepatch_query_output (size:640b/80B) */ 8985 struct hwrm_fw_livepatch_query_output { 8986 __le16 error_code; 8987 __le16 req_type; 8988 __le16 seq_id; 8989 __le16 resp_len; 8990 char install_ver[32]; 8991 char active_ver[32]; 8992 __le16 status_flags; 8993 #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_INSTALL 0x1UL 8994 #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_ACTIVE 0x2UL 8995 u8 unused_0[5]; 8996 u8 valid; 8997 }; 8998 8999 /* hwrm_fw_livepatch_input (size:256b/32B) */ 9000 struct hwrm_fw_livepatch_input { 9001 __le16 req_type; 9002 __le16 cmpl_ring; 9003 __le16 seq_id; 9004 __le16 target_id; 9005 __le64 resp_addr; 9006 u8 opcode; 9007 #define FW_LIVEPATCH_REQ_OPCODE_ACTIVATE 0x1UL 9008 #define FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 0x2UL 9009 #define FW_LIVEPATCH_REQ_OPCODE_LAST FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 9010 u8 fw_target; 9011 #define FW_LIVEPATCH_REQ_FW_TARGET_COMMON_FW 0x1UL 9012 #define FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 0x2UL 9013 #define FW_LIVEPATCH_REQ_FW_TARGET_LAST FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 9014 u8 loadtype; 9015 #define FW_LIVEPATCH_REQ_LOADTYPE_NVM_INSTALL 0x1UL 9016 #define FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 0x2UL 9017 #define FW_LIVEPATCH_REQ_LOADTYPE_LAST FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 9018 u8 flags; 9019 __le32 patch_len; 9020 __le64 host_addr; 9021 }; 9022 9023 /* hwrm_fw_livepatch_output (size:128b/16B) */ 9024 struct hwrm_fw_livepatch_output { 9025 __le16 error_code; 9026 __le16 req_type; 9027 __le16 seq_id; 9028 __le16 resp_len; 9029 u8 unused_0[7]; 9030 u8 valid; 9031 }; 9032 9033 /* hwrm_fw_livepatch_cmd_err (size:64b/8B) */ 9034 struct hwrm_fw_livepatch_cmd_err { 9035 u8 code; 9036 #define FW_LIVEPATCH_CMD_ERR_CODE_UNKNOWN 0x0UL 9037 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_OPCODE 0x1UL 9038 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_TARGET 0x2UL 9039 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_SUPPORTED 0x3UL 9040 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_INSTALLED 0x4UL 9041 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_PATCHED 0x5UL 9042 #define FW_LIVEPATCH_CMD_ERR_CODE_AUTH_FAIL 0x6UL 9043 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_HEADER 0x7UL 9044 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_SIZE 0x8UL 9045 #define FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 0x9UL 9046 #define FW_LIVEPATCH_CMD_ERR_CODE_LAST FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 9047 u8 unused_0[7]; 9048 }; 9049 9050 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 9051 struct hwrm_exec_fwd_resp_input { 9052 __le16 req_type; 9053 __le16 cmpl_ring; 9054 __le16 seq_id; 9055 __le16 target_id; 9056 __le64 resp_addr; 9057 __le32 encap_request[26]; 9058 __le16 encap_resp_target_id; 9059 u8 unused_0[6]; 9060 }; 9061 9062 /* hwrm_exec_fwd_resp_output (size:128b/16B) */ 9063 struct hwrm_exec_fwd_resp_output { 9064 __le16 error_code; 9065 __le16 req_type; 9066 __le16 seq_id; 9067 __le16 resp_len; 9068 u8 unused_0[7]; 9069 u8 valid; 9070 }; 9071 9072 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 9073 struct hwrm_reject_fwd_resp_input { 9074 __le16 req_type; 9075 __le16 cmpl_ring; 9076 __le16 seq_id; 9077 __le16 target_id; 9078 __le64 resp_addr; 9079 __le32 encap_request[26]; 9080 __le16 encap_resp_target_id; 9081 u8 unused_0[6]; 9082 }; 9083 9084 /* hwrm_reject_fwd_resp_output (size:128b/16B) */ 9085 struct hwrm_reject_fwd_resp_output { 9086 __le16 error_code; 9087 __le16 req_type; 9088 __le16 seq_id; 9089 __le16 resp_len; 9090 u8 unused_0[7]; 9091 u8 valid; 9092 }; 9093 9094 /* hwrm_fwd_resp_input (size:1024b/128B) */ 9095 struct hwrm_fwd_resp_input { 9096 __le16 req_type; 9097 __le16 cmpl_ring; 9098 __le16 seq_id; 9099 __le16 target_id; 9100 __le64 resp_addr; 9101 __le16 encap_resp_target_id; 9102 __le16 encap_resp_cmpl_ring; 9103 __le16 encap_resp_len; 9104 u8 unused_0; 9105 u8 unused_1; 9106 __le64 encap_resp_addr; 9107 __le32 encap_resp[24]; 9108 }; 9109 9110 /* hwrm_fwd_resp_output (size:128b/16B) */ 9111 struct hwrm_fwd_resp_output { 9112 __le16 error_code; 9113 __le16 req_type; 9114 __le16 seq_id; 9115 __le16 resp_len; 9116 u8 unused_0[7]; 9117 u8 valid; 9118 }; 9119 9120 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 9121 struct hwrm_fwd_async_event_cmpl_input { 9122 __le16 req_type; 9123 __le16 cmpl_ring; 9124 __le16 seq_id; 9125 __le16 target_id; 9126 __le64 resp_addr; 9127 __le16 encap_async_event_target_id; 9128 u8 unused_0[6]; 9129 __le32 encap_async_event_cmpl[4]; 9130 }; 9131 9132 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 9133 struct hwrm_fwd_async_event_cmpl_output { 9134 __le16 error_code; 9135 __le16 req_type; 9136 __le16 seq_id; 9137 __le16 resp_len; 9138 u8 unused_0[7]; 9139 u8 valid; 9140 }; 9141 9142 /* hwrm_temp_monitor_query_input (size:128b/16B) */ 9143 struct hwrm_temp_monitor_query_input { 9144 __le16 req_type; 9145 __le16 cmpl_ring; 9146 __le16 seq_id; 9147 __le16 target_id; 9148 __le64 resp_addr; 9149 }; 9150 9151 /* hwrm_temp_monitor_query_output (size:128b/16B) */ 9152 struct hwrm_temp_monitor_query_output { 9153 __le16 error_code; 9154 __le16 req_type; 9155 __le16 seq_id; 9156 __le16 resp_len; 9157 u8 temp; 9158 u8 phy_temp; 9159 u8 om_temp; 9160 u8 flags; 9161 #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL 9162 #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL 9163 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL 9164 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL 9165 #define TEMP_MONITOR_QUERY_RESP_FLAGS_EXT_TEMP_FIELDS_AVAILABLE 0x10UL 9166 u8 temp2; 9167 u8 phy_temp2; 9168 u8 om_temp2; 9169 u8 valid; 9170 }; 9171 9172 /* hwrm_wol_filter_alloc_input (size:512b/64B) */ 9173 struct hwrm_wol_filter_alloc_input { 9174 __le16 req_type; 9175 __le16 cmpl_ring; 9176 __le16 seq_id; 9177 __le16 target_id; 9178 __le64 resp_addr; 9179 __le32 flags; 9180 __le32 enables; 9181 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 9182 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 9183 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 9184 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 9185 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 9186 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 9187 __le16 port_id; 9188 u8 wol_type; 9189 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 9190 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 9191 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 9192 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 9193 u8 unused_0[5]; 9194 u8 mac_address[6]; 9195 __le16 pattern_offset; 9196 __le16 pattern_buf_size; 9197 __le16 pattern_mask_size; 9198 u8 unused_1[4]; 9199 __le64 pattern_buf_addr; 9200 __le64 pattern_mask_addr; 9201 }; 9202 9203 /* hwrm_wol_filter_alloc_output (size:128b/16B) */ 9204 struct hwrm_wol_filter_alloc_output { 9205 __le16 error_code; 9206 __le16 req_type; 9207 __le16 seq_id; 9208 __le16 resp_len; 9209 u8 wol_filter_id; 9210 u8 unused_0[6]; 9211 u8 valid; 9212 }; 9213 9214 /* hwrm_wol_filter_free_input (size:256b/32B) */ 9215 struct hwrm_wol_filter_free_input { 9216 __le16 req_type; 9217 __le16 cmpl_ring; 9218 __le16 seq_id; 9219 __le16 target_id; 9220 __le64 resp_addr; 9221 __le32 flags; 9222 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 9223 __le32 enables; 9224 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 9225 __le16 port_id; 9226 u8 wol_filter_id; 9227 u8 unused_0[5]; 9228 }; 9229 9230 /* hwrm_wol_filter_free_output (size:128b/16B) */ 9231 struct hwrm_wol_filter_free_output { 9232 __le16 error_code; 9233 __le16 req_type; 9234 __le16 seq_id; 9235 __le16 resp_len; 9236 u8 unused_0[7]; 9237 u8 valid; 9238 }; 9239 9240 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 9241 struct hwrm_wol_filter_qcfg_input { 9242 __le16 req_type; 9243 __le16 cmpl_ring; 9244 __le16 seq_id; 9245 __le16 target_id; 9246 __le64 resp_addr; 9247 __le16 port_id; 9248 __le16 handle; 9249 u8 unused_0[4]; 9250 __le64 pattern_buf_addr; 9251 __le16 pattern_buf_size; 9252 u8 unused_1[6]; 9253 __le64 pattern_mask_addr; 9254 __le16 pattern_mask_size; 9255 u8 unused_2[6]; 9256 }; 9257 9258 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 9259 struct hwrm_wol_filter_qcfg_output { 9260 __le16 error_code; 9261 __le16 req_type; 9262 __le16 seq_id; 9263 __le16 resp_len; 9264 __le16 next_handle; 9265 u8 wol_filter_id; 9266 u8 wol_type; 9267 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 9268 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 9269 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 9270 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 9271 __le32 unused_0; 9272 u8 mac_address[6]; 9273 __le16 pattern_offset; 9274 __le16 pattern_size; 9275 __le16 pattern_mask_size; 9276 u8 unused_1[3]; 9277 u8 valid; 9278 }; 9279 9280 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 9281 struct hwrm_wol_reason_qcfg_input { 9282 __le16 req_type; 9283 __le16 cmpl_ring; 9284 __le16 seq_id; 9285 __le16 target_id; 9286 __le64 resp_addr; 9287 __le16 port_id; 9288 u8 unused_0[6]; 9289 __le64 wol_pkt_buf_addr; 9290 __le16 wol_pkt_buf_size; 9291 u8 unused_1[6]; 9292 }; 9293 9294 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 9295 struct hwrm_wol_reason_qcfg_output { 9296 __le16 error_code; 9297 __le16 req_type; 9298 __le16 seq_id; 9299 __le16 resp_len; 9300 u8 wol_filter_id; 9301 u8 wol_reason; 9302 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 9303 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 9304 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 9305 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 9306 u8 wol_pkt_len; 9307 u8 unused_0[4]; 9308 u8 valid; 9309 }; 9310 9311 /* hwrm_dbg_read_direct_input (size:256b/32B) */ 9312 struct hwrm_dbg_read_direct_input { 9313 __le16 req_type; 9314 __le16 cmpl_ring; 9315 __le16 seq_id; 9316 __le16 target_id; 9317 __le64 resp_addr; 9318 __le64 host_dest_addr; 9319 __le32 read_addr; 9320 __le32 read_len32; 9321 }; 9322 9323 /* hwrm_dbg_read_direct_output (size:128b/16B) */ 9324 struct hwrm_dbg_read_direct_output { 9325 __le16 error_code; 9326 __le16 req_type; 9327 __le16 seq_id; 9328 __le16 resp_len; 9329 __le32 crc32; 9330 u8 unused_0[3]; 9331 u8 valid; 9332 }; 9333 9334 /* hwrm_dbg_qcaps_input (size:192b/24B) */ 9335 struct hwrm_dbg_qcaps_input { 9336 __le16 req_type; 9337 __le16 cmpl_ring; 9338 __le16 seq_id; 9339 __le16 target_id; 9340 __le64 resp_addr; 9341 __le16 fid; 9342 u8 unused_0[6]; 9343 }; 9344 9345 /* hwrm_dbg_qcaps_output (size:192b/24B) */ 9346 struct hwrm_dbg_qcaps_output { 9347 __le16 error_code; 9348 __le16 req_type; 9349 __le16 seq_id; 9350 __le16 resp_len; 9351 __le16 fid; 9352 u8 unused_0[2]; 9353 __le32 coredump_component_disable_caps; 9354 #define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM 0x1UL 9355 __le32 flags; 9356 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL 9357 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL 9358 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL 9359 #define DBG_QCAPS_RESP_FLAGS_USEQ 0x8UL 9360 u8 unused_1[3]; 9361 u8 valid; 9362 }; 9363 9364 /* hwrm_dbg_qcfg_input (size:192b/24B) */ 9365 struct hwrm_dbg_qcfg_input { 9366 __le16 req_type; 9367 __le16 cmpl_ring; 9368 __le16 seq_id; 9369 __le16 target_id; 9370 __le64 resp_addr; 9371 __le16 fid; 9372 __le16 flags; 9373 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK 0x3UL 9374 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0 9375 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM 0x0UL 9376 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR 0x1UL 9377 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 0x2UL 9378 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 9379 __le32 coredump_component_disable_flags; 9380 #define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM 0x1UL 9381 }; 9382 9383 /* hwrm_dbg_qcfg_output (size:256b/32B) */ 9384 struct hwrm_dbg_qcfg_output { 9385 __le16 error_code; 9386 __le16 req_type; 9387 __le16 seq_id; 9388 __le16 resp_len; 9389 __le16 fid; 9390 u8 unused_0[2]; 9391 __le32 coredump_size; 9392 __le32 flags; 9393 #define DBG_QCFG_RESP_FLAGS_UART_LOG 0x1UL 9394 #define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY 0x2UL 9395 #define DBG_QCFG_RESP_FLAGS_FW_TRACE 0x4UL 9396 #define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY 0x8UL 9397 #define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY 0x10UL 9398 #define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG 0x20UL 9399 __le16 async_cmpl_ring; 9400 u8 unused_2[2]; 9401 __le32 crashdump_size; 9402 u8 unused_3[3]; 9403 u8 valid; 9404 }; 9405 9406 /* hwrm_dbg_crashdump_medium_cfg_input (size:320b/40B) */ 9407 struct hwrm_dbg_crashdump_medium_cfg_input { 9408 __le16 req_type; 9409 __le16 cmpl_ring; 9410 __le16 seq_id; 9411 __le16 target_id; 9412 __le64 resp_addr; 9413 __le16 output_dest_flags; 9414 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_TYPE_DDR 0x1UL 9415 __le16 pg_size_lvl; 9416 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_MASK 0x3UL 9417 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_SFT 0 9418 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_0 0x0UL 9419 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_1 0x1UL 9420 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2 0x2UL 9421 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2 9422 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_MASK 0x1cUL 9423 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_SFT 2 9424 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_4K (0x0UL << 2) 9425 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8K (0x1UL << 2) 9426 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_64K (0x2UL << 2) 9427 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_2M (0x3UL << 2) 9428 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8M (0x4UL << 2) 9429 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G (0x5UL << 2) 9430 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G 9431 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_MASK 0xffe0UL 9432 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_SFT 5 9433 __le32 size; 9434 __le32 coredump_component_disable_flags; 9435 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_NVRAM 0x1UL 9436 __le32 unused_0; 9437 __le64 pbl; 9438 }; 9439 9440 /* hwrm_dbg_crashdump_medium_cfg_output (size:128b/16B) */ 9441 struct hwrm_dbg_crashdump_medium_cfg_output { 9442 __le16 error_code; 9443 __le16 req_type; 9444 __le16 seq_id; 9445 __le16 resp_len; 9446 u8 unused_1[7]; 9447 u8 valid; 9448 }; 9449 9450 /* coredump_segment_record (size:128b/16B) */ 9451 struct coredump_segment_record { 9452 __le16 component_id; 9453 __le16 segment_id; 9454 __le16 max_instances; 9455 u8 version_hi; 9456 u8 version_low; 9457 u8 seg_flags; 9458 u8 compress_flags; 9459 #define SFLAG_COMPRESSED_ZLIB 0x1UL 9460 u8 unused_0[2]; 9461 __le32 segment_len; 9462 }; 9463 9464 /* hwrm_dbg_coredump_list_input (size:256b/32B) */ 9465 struct hwrm_dbg_coredump_list_input { 9466 __le16 req_type; 9467 __le16 cmpl_ring; 9468 __le16 seq_id; 9469 __le16 target_id; 9470 __le64 resp_addr; 9471 __le64 host_dest_addr; 9472 __le32 host_buf_len; 9473 __le16 seq_no; 9474 u8 flags; 9475 #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL 9476 u8 unused_0[1]; 9477 }; 9478 9479 /* hwrm_dbg_coredump_list_output (size:128b/16B) */ 9480 struct hwrm_dbg_coredump_list_output { 9481 __le16 error_code; 9482 __le16 req_type; 9483 __le16 seq_id; 9484 __le16 resp_len; 9485 u8 flags; 9486 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 9487 u8 unused_0; 9488 __le16 total_segments; 9489 __le16 data_len; 9490 u8 unused_1; 9491 u8 valid; 9492 }; 9493 9494 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 9495 struct hwrm_dbg_coredump_initiate_input { 9496 __le16 req_type; 9497 __le16 cmpl_ring; 9498 __le16 seq_id; 9499 __le16 target_id; 9500 __le64 resp_addr; 9501 __le16 component_id; 9502 __le16 segment_id; 9503 __le16 instance; 9504 __le16 unused_0; 9505 u8 seg_flags; 9506 u8 unused_1[7]; 9507 }; 9508 9509 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 9510 struct hwrm_dbg_coredump_initiate_output { 9511 __le16 error_code; 9512 __le16 req_type; 9513 __le16 seq_id; 9514 __le16 resp_len; 9515 u8 unused_0[7]; 9516 u8 valid; 9517 }; 9518 9519 /* coredump_data_hdr (size:128b/16B) */ 9520 struct coredump_data_hdr { 9521 __le32 address; 9522 __le32 flags_length; 9523 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK 0xffffffUL 9524 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT 0 9525 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS 0x1000000UL 9526 __le32 instance; 9527 __le32 next_offset; 9528 }; 9529 9530 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 9531 struct hwrm_dbg_coredump_retrieve_input { 9532 __le16 req_type; 9533 __le16 cmpl_ring; 9534 __le16 seq_id; 9535 __le16 target_id; 9536 __le64 resp_addr; 9537 __le64 host_dest_addr; 9538 __le32 host_buf_len; 9539 __le32 unused_0; 9540 __le16 component_id; 9541 __le16 segment_id; 9542 __le16 instance; 9543 __le16 unused_1; 9544 u8 seg_flags; 9545 u8 unused_2; 9546 __le16 unused_3; 9547 __le32 unused_4; 9548 __le32 seq_no; 9549 __le32 unused_5; 9550 }; 9551 9552 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 9553 struct hwrm_dbg_coredump_retrieve_output { 9554 __le16 error_code; 9555 __le16 req_type; 9556 __le16 seq_id; 9557 __le16 resp_len; 9558 u8 flags; 9559 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 9560 u8 unused_0; 9561 __le16 data_len; 9562 u8 unused_1[3]; 9563 u8 valid; 9564 }; 9565 9566 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 9567 struct hwrm_dbg_ring_info_get_input { 9568 __le16 req_type; 9569 __le16 cmpl_ring; 9570 __le16 seq_id; 9571 __le16 target_id; 9572 __le64 resp_addr; 9573 u8 ring_type; 9574 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 9575 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 9576 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 9577 #define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 0x3UL 9578 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 9579 u8 unused_0[3]; 9580 __le32 fw_ring_id; 9581 }; 9582 9583 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 9584 struct hwrm_dbg_ring_info_get_output { 9585 __le16 error_code; 9586 __le16 req_type; 9587 __le16 seq_id; 9588 __le16 resp_len; 9589 __le32 producer_index; 9590 __le32 consumer_index; 9591 __le32 cag_vector_ctrl; 9592 u8 unused_0[3]; 9593 u8 valid; 9594 }; 9595 9596 /* hwrm_nvm_read_input (size:320b/40B) */ 9597 struct hwrm_nvm_read_input { 9598 __le16 req_type; 9599 __le16 cmpl_ring; 9600 __le16 seq_id; 9601 __le16 target_id; 9602 __le64 resp_addr; 9603 __le64 host_dest_addr; 9604 __le16 dir_idx; 9605 u8 unused_0[2]; 9606 __le32 offset; 9607 __le32 len; 9608 u8 unused_1[4]; 9609 }; 9610 9611 /* hwrm_nvm_read_output (size:128b/16B) */ 9612 struct hwrm_nvm_read_output { 9613 __le16 error_code; 9614 __le16 req_type; 9615 __le16 seq_id; 9616 __le16 resp_len; 9617 u8 unused_0[7]; 9618 u8 valid; 9619 }; 9620 9621 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 9622 struct hwrm_nvm_get_dir_entries_input { 9623 __le16 req_type; 9624 __le16 cmpl_ring; 9625 __le16 seq_id; 9626 __le16 target_id; 9627 __le64 resp_addr; 9628 __le64 host_dest_addr; 9629 }; 9630 9631 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 9632 struct hwrm_nvm_get_dir_entries_output { 9633 __le16 error_code; 9634 __le16 req_type; 9635 __le16 seq_id; 9636 __le16 resp_len; 9637 u8 unused_0[7]; 9638 u8 valid; 9639 }; 9640 9641 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 9642 struct hwrm_nvm_get_dir_info_input { 9643 __le16 req_type; 9644 __le16 cmpl_ring; 9645 __le16 seq_id; 9646 __le16 target_id; 9647 __le64 resp_addr; 9648 }; 9649 9650 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 9651 struct hwrm_nvm_get_dir_info_output { 9652 __le16 error_code; 9653 __le16 req_type; 9654 __le16 seq_id; 9655 __le16 resp_len; 9656 __le32 entries; 9657 __le32 entry_length; 9658 u8 unused_0[7]; 9659 u8 valid; 9660 }; 9661 9662 /* hwrm_nvm_write_input (size:448b/56B) */ 9663 struct hwrm_nvm_write_input { 9664 __le16 req_type; 9665 __le16 cmpl_ring; 9666 __le16 seq_id; 9667 __le16 target_id; 9668 __le64 resp_addr; 9669 __le64 host_src_addr; 9670 __le16 dir_type; 9671 __le16 dir_ordinal; 9672 __le16 dir_ext; 9673 __le16 dir_attr; 9674 __le32 dir_data_length; 9675 __le16 option; 9676 __le16 flags; 9677 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 9678 #define NVM_WRITE_REQ_FLAGS_BATCH_MODE 0x2UL 9679 #define NVM_WRITE_REQ_FLAGS_BATCH_LAST 0x4UL 9680 __le32 dir_item_length; 9681 __le32 offset; 9682 __le32 len; 9683 __le32 unused_0; 9684 }; 9685 9686 /* hwrm_nvm_write_output (size:128b/16B) */ 9687 struct hwrm_nvm_write_output { 9688 __le16 error_code; 9689 __le16 req_type; 9690 __le16 seq_id; 9691 __le16 resp_len; 9692 __le32 dir_item_length; 9693 __le16 dir_idx; 9694 u8 unused_0; 9695 u8 valid; 9696 }; 9697 9698 /* hwrm_nvm_write_cmd_err (size:64b/8B) */ 9699 struct hwrm_nvm_write_cmd_err { 9700 u8 code; 9701 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 9702 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 9703 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 9704 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 9705 u8 unused_0[7]; 9706 }; 9707 9708 /* hwrm_nvm_modify_input (size:320b/40B) */ 9709 struct hwrm_nvm_modify_input { 9710 __le16 req_type; 9711 __le16 cmpl_ring; 9712 __le16 seq_id; 9713 __le16 target_id; 9714 __le64 resp_addr; 9715 __le64 host_src_addr; 9716 __le16 dir_idx; 9717 __le16 flags; 9718 #define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL 9719 #define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL 9720 __le32 offset; 9721 __le32 len; 9722 u8 unused_1[4]; 9723 }; 9724 9725 /* hwrm_nvm_modify_output (size:128b/16B) */ 9726 struct hwrm_nvm_modify_output { 9727 __le16 error_code; 9728 __le16 req_type; 9729 __le16 seq_id; 9730 __le16 resp_len; 9731 u8 unused_0[7]; 9732 u8 valid; 9733 }; 9734 9735 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 9736 struct hwrm_nvm_find_dir_entry_input { 9737 __le16 req_type; 9738 __le16 cmpl_ring; 9739 __le16 seq_id; 9740 __le16 target_id; 9741 __le64 resp_addr; 9742 __le32 enables; 9743 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 9744 __le16 dir_idx; 9745 __le16 dir_type; 9746 __le16 dir_ordinal; 9747 __le16 dir_ext; 9748 u8 opt_ordinal; 9749 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 9750 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 9751 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 9752 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 9753 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 9754 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 9755 u8 unused_0[3]; 9756 }; 9757 9758 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 9759 struct hwrm_nvm_find_dir_entry_output { 9760 __le16 error_code; 9761 __le16 req_type; 9762 __le16 seq_id; 9763 __le16 resp_len; 9764 __le32 dir_item_length; 9765 __le32 dir_data_length; 9766 __le32 fw_ver; 9767 __le16 dir_ordinal; 9768 __le16 dir_idx; 9769 u8 unused_0[7]; 9770 u8 valid; 9771 }; 9772 9773 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 9774 struct hwrm_nvm_erase_dir_entry_input { 9775 __le16 req_type; 9776 __le16 cmpl_ring; 9777 __le16 seq_id; 9778 __le16 target_id; 9779 __le64 resp_addr; 9780 __le16 dir_idx; 9781 u8 unused_0[6]; 9782 }; 9783 9784 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 9785 struct hwrm_nvm_erase_dir_entry_output { 9786 __le16 error_code; 9787 __le16 req_type; 9788 __le16 seq_id; 9789 __le16 resp_len; 9790 u8 unused_0[7]; 9791 u8 valid; 9792 }; 9793 9794 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 9795 struct hwrm_nvm_get_dev_info_input { 9796 __le16 req_type; 9797 __le16 cmpl_ring; 9798 __le16 seq_id; 9799 __le16 target_id; 9800 __le64 resp_addr; 9801 }; 9802 9803 /* hwrm_nvm_get_dev_info_output (size:640b/80B) */ 9804 struct hwrm_nvm_get_dev_info_output { 9805 __le16 error_code; 9806 __le16 req_type; 9807 __le16 seq_id; 9808 __le16 resp_len; 9809 __le16 manufacturer_id; 9810 __le16 device_id; 9811 __le32 sector_size; 9812 __le32 nvram_size; 9813 __le32 reserved_size; 9814 __le32 available_size; 9815 u8 nvm_cfg_ver_maj; 9816 u8 nvm_cfg_ver_min; 9817 u8 nvm_cfg_ver_upd; 9818 u8 flags; 9819 #define NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID 0x1UL 9820 char pkg_name[16]; 9821 __le16 hwrm_fw_major; 9822 __le16 hwrm_fw_minor; 9823 __le16 hwrm_fw_build; 9824 __le16 hwrm_fw_patch; 9825 __le16 mgmt_fw_major; 9826 __le16 mgmt_fw_minor; 9827 __le16 mgmt_fw_build; 9828 __le16 mgmt_fw_patch; 9829 __le16 roce_fw_major; 9830 __le16 roce_fw_minor; 9831 __le16 roce_fw_build; 9832 __le16 roce_fw_patch; 9833 u8 unused_0[7]; 9834 u8 valid; 9835 }; 9836 9837 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 9838 struct hwrm_nvm_mod_dir_entry_input { 9839 __le16 req_type; 9840 __le16 cmpl_ring; 9841 __le16 seq_id; 9842 __le16 target_id; 9843 __le64 resp_addr; 9844 __le32 enables; 9845 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 9846 __le16 dir_idx; 9847 __le16 dir_ordinal; 9848 __le16 dir_ext; 9849 __le16 dir_attr; 9850 __le32 checksum; 9851 }; 9852 9853 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 9854 struct hwrm_nvm_mod_dir_entry_output { 9855 __le16 error_code; 9856 __le16 req_type; 9857 __le16 seq_id; 9858 __le16 resp_len; 9859 u8 unused_0[7]; 9860 u8 valid; 9861 }; 9862 9863 /* hwrm_nvm_verify_update_input (size:192b/24B) */ 9864 struct hwrm_nvm_verify_update_input { 9865 __le16 req_type; 9866 __le16 cmpl_ring; 9867 __le16 seq_id; 9868 __le16 target_id; 9869 __le64 resp_addr; 9870 __le16 dir_type; 9871 __le16 dir_ordinal; 9872 __le16 dir_ext; 9873 u8 unused_0[2]; 9874 }; 9875 9876 /* hwrm_nvm_verify_update_output (size:128b/16B) */ 9877 struct hwrm_nvm_verify_update_output { 9878 __le16 error_code; 9879 __le16 req_type; 9880 __le16 seq_id; 9881 __le16 resp_len; 9882 u8 unused_0[7]; 9883 u8 valid; 9884 }; 9885 9886 /* hwrm_nvm_install_update_input (size:192b/24B) */ 9887 struct hwrm_nvm_install_update_input { 9888 __le16 req_type; 9889 __le16 cmpl_ring; 9890 __le16 seq_id; 9891 __le16 target_id; 9892 __le64 resp_addr; 9893 __le32 install_type; 9894 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 9895 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 9896 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 9897 __le16 flags; 9898 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 9899 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 9900 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 9901 #define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY 0x8UL 9902 u8 unused_0[2]; 9903 }; 9904 9905 /* hwrm_nvm_install_update_output (size:192b/24B) */ 9906 struct hwrm_nvm_install_update_output { 9907 __le16 error_code; 9908 __le16 req_type; 9909 __le16 seq_id; 9910 __le16 resp_len; 9911 __le64 installed_items; 9912 u8 result; 9913 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 9914 #define NVM_INSTALL_UPDATE_RESP_RESULT_FAILURE 0xffUL 9915 #define NVM_INSTALL_UPDATE_RESP_RESULT_MALLOC_FAILURE 0xfdUL 9916 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER 0xfbUL 9917 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER 0xf3UL 9918 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE 0xf2UL 9919 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER 0xecUL 9920 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE 0xebUL 9921 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM 0xeaUL 9922 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH 0xe9UL 9923 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST 0xe8UL 9924 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER 0xe7UL 9925 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM 0xe6UL 9926 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM 0xe5UL 9927 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH 0xe4UL 9928 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE 0xe1UL 9929 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV 0xceUL 9930 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID 0xcdUL 9931 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR 0xccUL 9932 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID 0xcbUL 9933 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM 0xc5UL 9934 #define NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM 0xc4UL 9935 #define NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM 0xc3UL 9936 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR 0xb9UL 9937 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR 0xb8UL 9938 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR 0xb7UL 9939 #define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND 0xb0UL 9940 #define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED 0xa7UL 9941 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED 9942 u8 problem_item; 9943 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 9944 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 9945 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 9946 u8 reset_required; 9947 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 9948 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 9949 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 9950 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 9951 u8 unused_0[4]; 9952 u8 valid; 9953 }; 9954 9955 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 9956 struct hwrm_nvm_install_update_cmd_err { 9957 u8 code; 9958 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 9959 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 9960 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 9961 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK 0x3UL 9962 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT 0x4UL 9963 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT 9964 u8 unused_0[7]; 9965 }; 9966 9967 /* hwrm_nvm_get_variable_input (size:320b/40B) */ 9968 struct hwrm_nvm_get_variable_input { 9969 __le16 req_type; 9970 __le16 cmpl_ring; 9971 __le16 seq_id; 9972 __le16 target_id; 9973 __le64 resp_addr; 9974 __le64 dest_data_addr; 9975 __le16 data_len; 9976 __le16 option_num; 9977 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 9978 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 9979 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 9980 __le16 dimensions; 9981 __le16 index_0; 9982 __le16 index_1; 9983 __le16 index_2; 9984 __le16 index_3; 9985 u8 flags; 9986 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 9987 u8 unused_0; 9988 }; 9989 9990 /* hwrm_nvm_get_variable_output (size:128b/16B) */ 9991 struct hwrm_nvm_get_variable_output { 9992 __le16 error_code; 9993 __le16 req_type; 9994 __le16 seq_id; 9995 __le16 resp_len; 9996 __le16 data_len; 9997 __le16 option_num; 9998 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 9999 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 10000 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 10001 u8 unused_0[3]; 10002 u8 valid; 10003 }; 10004 10005 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 10006 struct hwrm_nvm_get_variable_cmd_err { 10007 u8 code; 10008 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 10009 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 10010 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 10011 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 10012 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 10013 u8 unused_0[7]; 10014 }; 10015 10016 /* hwrm_nvm_set_variable_input (size:320b/40B) */ 10017 struct hwrm_nvm_set_variable_input { 10018 __le16 req_type; 10019 __le16 cmpl_ring; 10020 __le16 seq_id; 10021 __le16 target_id; 10022 __le64 resp_addr; 10023 __le64 src_data_addr; 10024 __le16 data_len; 10025 __le16 option_num; 10026 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 10027 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 10028 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 10029 __le16 dimensions; 10030 __le16 index_0; 10031 __le16 index_1; 10032 __le16 index_2; 10033 __le16 index_3; 10034 u8 flags; 10035 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 10036 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 10037 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 10038 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 10039 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 10040 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 10041 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 10042 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 10043 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL 10044 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4 10045 #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL 10046 u8 unused_0; 10047 }; 10048 10049 /* hwrm_nvm_set_variable_output (size:128b/16B) */ 10050 struct hwrm_nvm_set_variable_output { 10051 __le16 error_code; 10052 __le16 req_type; 10053 __le16 seq_id; 10054 __le16 resp_len; 10055 u8 unused_0[7]; 10056 u8 valid; 10057 }; 10058 10059 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 10060 struct hwrm_nvm_set_variable_cmd_err { 10061 u8 code; 10062 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 10063 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 10064 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 10065 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 10066 u8 unused_0[7]; 10067 }; 10068 10069 /* hwrm_selftest_qlist_input (size:128b/16B) */ 10070 struct hwrm_selftest_qlist_input { 10071 __le16 req_type; 10072 __le16 cmpl_ring; 10073 __le16 seq_id; 10074 __le16 target_id; 10075 __le64 resp_addr; 10076 }; 10077 10078 /* hwrm_selftest_qlist_output (size:2240b/280B) */ 10079 struct hwrm_selftest_qlist_output { 10080 __le16 error_code; 10081 __le16 req_type; 10082 __le16 seq_id; 10083 __le16 resp_len; 10084 u8 num_tests; 10085 u8 available_tests; 10086 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 10087 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 10088 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 10089 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 10090 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 10091 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 10092 u8 offline_tests; 10093 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 10094 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 10095 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 10096 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 10097 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 10098 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 10099 u8 unused_0; 10100 __le16 test_timeout; 10101 u8 unused_1[2]; 10102 char test0_name[32]; 10103 char test1_name[32]; 10104 char test2_name[32]; 10105 char test3_name[32]; 10106 char test4_name[32]; 10107 char test5_name[32]; 10108 char test6_name[32]; 10109 char test7_name[32]; 10110 u8 eyescope_target_BER_support; 10111 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED 0x0UL 10112 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED 0x1UL 10113 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL 10114 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL 10115 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL 10116 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 10117 u8 unused_2[6]; 10118 u8 valid; 10119 }; 10120 10121 /* hwrm_selftest_exec_input (size:192b/24B) */ 10122 struct hwrm_selftest_exec_input { 10123 __le16 req_type; 10124 __le16 cmpl_ring; 10125 __le16 seq_id; 10126 __le16 target_id; 10127 __le64 resp_addr; 10128 u8 flags; 10129 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 10130 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 10131 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 10132 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 10133 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 10134 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 10135 u8 unused_0[7]; 10136 }; 10137 10138 /* hwrm_selftest_exec_output (size:128b/16B) */ 10139 struct hwrm_selftest_exec_output { 10140 __le16 error_code; 10141 __le16 req_type; 10142 __le16 seq_id; 10143 __le16 resp_len; 10144 u8 requested_tests; 10145 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 10146 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 10147 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 10148 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 10149 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 10150 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 10151 u8 test_success; 10152 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 10153 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 10154 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 10155 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 10156 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 10157 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 10158 u8 unused_0[5]; 10159 u8 valid; 10160 }; 10161 10162 /* hwrm_selftest_irq_input (size:128b/16B) */ 10163 struct hwrm_selftest_irq_input { 10164 __le16 req_type; 10165 __le16 cmpl_ring; 10166 __le16 seq_id; 10167 __le16 target_id; 10168 __le64 resp_addr; 10169 }; 10170 10171 /* hwrm_selftest_irq_output (size:128b/16B) */ 10172 struct hwrm_selftest_irq_output { 10173 __le16 error_code; 10174 __le16 req_type; 10175 __le16 seq_id; 10176 __le16 resp_len; 10177 u8 unused_0[7]; 10178 u8 valid; 10179 }; 10180 10181 /* db_push_info (size:64b/8B) */ 10182 struct db_push_info { 10183 u32 push_size_push_index; 10184 #define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL 10185 #define DB_PUSH_INFO_PUSH_INDEX_SFT 0 10186 #define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL 10187 #define DB_PUSH_INFO_PUSH_SIZE_SFT 24 10188 u32 reserved32; 10189 }; 10190 10191 /* fw_status_reg (size:32b/4B) */ 10192 struct fw_status_reg { 10193 u32 fw_status; 10194 #define FW_STATUS_REG_CODE_MASK 0xffffUL 10195 #define FW_STATUS_REG_CODE_SFT 0 10196 #define FW_STATUS_REG_CODE_READY 0x8000UL 10197 #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY 10198 #define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL 10199 #define FW_STATUS_REG_RECOVERABLE 0x20000UL 10200 #define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL 10201 #define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL 10202 #define FW_STATUS_REG_SHUTDOWN 0x100000UL 10203 #define FW_STATUS_REG_CRASHED_NO_MASTER 0x200000UL 10204 #define FW_STATUS_REG_RECOVERING 0x400000UL 10205 }; 10206 10207 /* hcomm_status (size:64b/8B) */ 10208 struct hcomm_status { 10209 u32 sig_ver; 10210 #define HCOMM_STATUS_VER_MASK 0xffUL 10211 #define HCOMM_STATUS_VER_SFT 0 10212 #define HCOMM_STATUS_VER_LATEST 0x1UL 10213 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST 10214 #define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL 10215 #define HCOMM_STATUS_SIGNATURE_SFT 8 10216 #define HCOMM_STATUS_SIGNATURE_VAL (0x484353UL << 8) 10217 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL 10218 u32 fw_status_loc; 10219 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK 0x3UL 10220 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 10221 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG 0x0UL 10222 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC 0x1UL 10223 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 0x2UL 10224 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 0x3UL 10225 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 10226 #define HCOMM_STATUS_TRUE_OFFSET_MASK 0xfffffffcUL 10227 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 10228 }; 10229 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL 10230 10231 #endif /* _BNXT_HSI_H_ */ 10232