1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2014-2018 Broadcom Limited 5 * Copyright (c) 2018-2021 Broadcom Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * DO NOT MODIFY!!! This file is automatically generated. 12 */ 13 14 #ifndef _BNXT_HSI_H_ 15 #define _BNXT_HSI_H_ 16 17 /* hwrm_cmd_hdr (size:128b/16B) */ 18 struct hwrm_cmd_hdr { 19 __le16 req_type; 20 __le16 cmpl_ring; 21 __le16 seq_id; 22 __le16 target_id; 23 __le64 resp_addr; 24 }; 25 26 /* hwrm_resp_hdr (size:64b/8B) */ 27 struct hwrm_resp_hdr { 28 __le16 error_code; 29 __le16 req_type; 30 __le16 seq_id; 31 __le16 resp_len; 32 }; 33 34 #define CMD_DISCR_TLV_ENCAP 0x8000UL 35 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 36 37 38 #define TLV_TYPE_HWRM_REQUEST 0x1UL 39 #define TLV_TYPE_HWRM_RESPONSE 0x2UL 40 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 41 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 42 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 43 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL 44 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 45 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 46 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 47 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL 48 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL 49 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 50 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL 51 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL 52 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 53 54 55 /* tlv (size:64b/8B) */ 56 struct tlv { 57 __le16 cmd_discr; 58 u8 reserved_8b; 59 u8 flags; 60 #define TLV_FLAGS_MORE 0x1UL 61 #define TLV_FLAGS_MORE_LAST 0x0UL 62 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 63 #define TLV_FLAGS_REQUIRED 0x2UL 64 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 65 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 66 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 67 __le16 tlv_type; 68 __le16 length; 69 }; 70 71 /* input (size:128b/16B) */ 72 struct input { 73 __le16 req_type; 74 __le16 cmpl_ring; 75 __le16 seq_id; 76 __le16 target_id; 77 __le64 resp_addr; 78 }; 79 80 /* output (size:64b/8B) */ 81 struct output { 82 __le16 error_code; 83 __le16 req_type; 84 __le16 seq_id; 85 __le16 resp_len; 86 }; 87 88 /* hwrm_short_input (size:128b/16B) */ 89 struct hwrm_short_input { 90 __le16 req_type; 91 __le16 signature; 92 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 93 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 94 __le16 target_id; 95 #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL 96 #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL 97 #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS 98 __le16 size; 99 __le64 req_addr; 100 }; 101 102 /* cmd_nums (size:64b/8B) */ 103 struct cmd_nums { 104 __le16 req_type; 105 #define HWRM_VER_GET 0x0UL 106 #define HWRM_FUNC_ECHO_RESPONSE 0xbUL 107 #define HWRM_ERROR_RECOVERY_QCFG 0xcUL 108 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 109 #define HWRM_FUNC_BUF_UNRGTR 0xeUL 110 #define HWRM_FUNC_VF_CFG 0xfUL 111 #define HWRM_RESERVED1 0x10UL 112 #define HWRM_FUNC_RESET 0x11UL 113 #define HWRM_FUNC_GETFID 0x12UL 114 #define HWRM_FUNC_VF_ALLOC 0x13UL 115 #define HWRM_FUNC_VF_FREE 0x14UL 116 #define HWRM_FUNC_QCAPS 0x15UL 117 #define HWRM_FUNC_QCFG 0x16UL 118 #define HWRM_FUNC_CFG 0x17UL 119 #define HWRM_FUNC_QSTATS 0x18UL 120 #define HWRM_FUNC_CLR_STATS 0x19UL 121 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 122 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 123 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 124 #define HWRM_FUNC_DRV_RGTR 0x1dUL 125 #define HWRM_FUNC_DRV_QVER 0x1eUL 126 #define HWRM_FUNC_BUF_RGTR 0x1fUL 127 #define HWRM_PORT_PHY_CFG 0x20UL 128 #define HWRM_PORT_MAC_CFG 0x21UL 129 #define HWRM_PORT_TS_QUERY 0x22UL 130 #define HWRM_PORT_QSTATS 0x23UL 131 #define HWRM_PORT_LPBK_QSTATS 0x24UL 132 #define HWRM_PORT_CLR_STATS 0x25UL 133 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 134 #define HWRM_PORT_PHY_QCFG 0x27UL 135 #define HWRM_PORT_MAC_QCFG 0x28UL 136 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 137 #define HWRM_PORT_PHY_QCAPS 0x2aUL 138 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 139 #define HWRM_PORT_PHY_I2C_READ 0x2cUL 140 #define HWRM_PORT_LED_CFG 0x2dUL 141 #define HWRM_PORT_LED_QCFG 0x2eUL 142 #define HWRM_PORT_LED_QCAPS 0x2fUL 143 #define HWRM_QUEUE_QPORTCFG 0x30UL 144 #define HWRM_QUEUE_QCFG 0x31UL 145 #define HWRM_QUEUE_CFG 0x32UL 146 #define HWRM_FUNC_VLAN_CFG 0x33UL 147 #define HWRM_FUNC_VLAN_QCFG 0x34UL 148 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 149 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 150 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 151 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 152 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 153 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 154 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 155 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 156 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 157 #define HWRM_VNIC_ALLOC 0x40UL 158 #define HWRM_VNIC_FREE 0x41UL 159 #define HWRM_VNIC_CFG 0x42UL 160 #define HWRM_VNIC_QCFG 0x43UL 161 #define HWRM_VNIC_TPA_CFG 0x44UL 162 #define HWRM_VNIC_TPA_QCFG 0x45UL 163 #define HWRM_VNIC_RSS_CFG 0x46UL 164 #define HWRM_VNIC_RSS_QCFG 0x47UL 165 #define HWRM_VNIC_PLCMODES_CFG 0x48UL 166 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 167 #define HWRM_VNIC_QCAPS 0x4aUL 168 #define HWRM_VNIC_UPDATE 0x4bUL 169 #define HWRM_RING_ALLOC 0x50UL 170 #define HWRM_RING_FREE 0x51UL 171 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 172 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 173 #define HWRM_RING_AGGINT_QCAPS 0x54UL 174 #define HWRM_RING_SCHQ_ALLOC 0x55UL 175 #define HWRM_RING_SCHQ_CFG 0x56UL 176 #define HWRM_RING_SCHQ_FREE 0x57UL 177 #define HWRM_RING_RESET 0x5eUL 178 #define HWRM_RING_GRP_ALLOC 0x60UL 179 #define HWRM_RING_GRP_FREE 0x61UL 180 #define HWRM_RING_CFG 0x62UL 181 #define HWRM_RING_QCFG 0x63UL 182 #define HWRM_RESERVED5 0x64UL 183 #define HWRM_RESERVED6 0x65UL 184 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 185 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 186 #define HWRM_QUEUE_MPLS_QCAPS 0x80UL 187 #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL 188 #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL 189 #define HWRM_QUEUE_VLANPRI_QCAPS 0x83UL 190 #define HWRM_QUEUE_VLANPRI2PRI_QCFG 0x84UL 191 #define HWRM_QUEUE_VLANPRI2PRI_CFG 0x85UL 192 #define HWRM_QUEUE_GLOBAL_CFG 0x86UL 193 #define HWRM_QUEUE_GLOBAL_QCFG 0x87UL 194 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 195 #define HWRM_CFA_L2_FILTER_FREE 0x91UL 196 #define HWRM_CFA_L2_FILTER_CFG 0x92UL 197 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 198 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 199 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 200 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 201 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 202 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 203 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 204 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 205 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 206 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 207 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 208 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 209 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 210 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 211 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 212 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 213 #define HWRM_STAT_CTX_ALLOC 0xb0UL 214 #define HWRM_STAT_CTX_FREE 0xb1UL 215 #define HWRM_STAT_CTX_QUERY 0xb2UL 216 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 217 #define HWRM_PORT_QSTATS_EXT 0xb4UL 218 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL 219 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL 220 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL 221 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL 222 #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL 223 #define HWRM_RESERVED7 0xbaUL 224 #define HWRM_PORT_TX_FIR_CFG 0xbbUL 225 #define HWRM_PORT_TX_FIR_QCFG 0xbcUL 226 #define HWRM_PORT_ECN_QSTATS 0xbdUL 227 #define HWRM_FW_LIVEPATCH_QUERY 0xbeUL 228 #define HWRM_FW_LIVEPATCH 0xbfUL 229 #define HWRM_FW_RESET 0xc0UL 230 #define HWRM_FW_QSTATUS 0xc1UL 231 #define HWRM_FW_HEALTH_CHECK 0xc2UL 232 #define HWRM_FW_SYNC 0xc3UL 233 #define HWRM_FW_STATE_QCAPS 0xc4UL 234 #define HWRM_FW_STATE_QUIESCE 0xc5UL 235 #define HWRM_FW_STATE_BACKUP 0xc6UL 236 #define HWRM_FW_STATE_RESTORE 0xc7UL 237 #define HWRM_FW_SET_TIME 0xc8UL 238 #define HWRM_FW_GET_TIME 0xc9UL 239 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 240 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 241 #define HWRM_FW_IPC_MAILBOX 0xccUL 242 #define HWRM_FW_ECN_CFG 0xcdUL 243 #define HWRM_FW_ECN_QCFG 0xceUL 244 #define HWRM_FW_SECURE_CFG 0xcfUL 245 #define HWRM_EXEC_FWD_RESP 0xd0UL 246 #define HWRM_REJECT_FWD_RESP 0xd1UL 247 #define HWRM_FWD_RESP 0xd2UL 248 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 249 #define HWRM_OEM_CMD 0xd4UL 250 #define HWRM_PORT_PRBS_TEST 0xd5UL 251 #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL 252 #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL 253 #define HWRM_FW_STATE_UNQUIESCE 0xd8UL 254 #define HWRM_PORT_DSC_DUMP 0xd9UL 255 #define HWRM_PORT_EP_TX_QCFG 0xdaUL 256 #define HWRM_PORT_EP_TX_CFG 0xdbUL 257 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 258 #define HWRM_REG_POWER_QUERY 0xe1UL 259 #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL 260 #define HWRM_REG_POWER_HISTOGRAM 0xe3UL 261 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 262 #define HWRM_WOL_FILTER_FREE 0xf1UL 263 #define HWRM_WOL_FILTER_QCFG 0xf2UL 264 #define HWRM_WOL_REASON_QCFG 0xf3UL 265 #define HWRM_CFA_METER_QCAPS 0xf4UL 266 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 267 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 268 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 269 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 270 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 271 #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL 272 #define HWRM_CFA_VFR_ALLOC 0xfdUL 273 #define HWRM_CFA_VFR_FREE 0xfeUL 274 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 275 #define HWRM_CFA_VF_PAIR_FREE 0x101UL 276 #define HWRM_CFA_VF_PAIR_INFO 0x102UL 277 #define HWRM_CFA_FLOW_ALLOC 0x103UL 278 #define HWRM_CFA_FLOW_FREE 0x104UL 279 #define HWRM_CFA_FLOW_FLUSH 0x105UL 280 #define HWRM_CFA_FLOW_STATS 0x106UL 281 #define HWRM_CFA_FLOW_INFO 0x107UL 282 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 283 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 284 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 285 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 286 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 287 #define HWRM_CFA_PAIR_ALLOC 0x10dUL 288 #define HWRM_CFA_PAIR_FREE 0x10eUL 289 #define HWRM_CFA_PAIR_INFO 0x10fUL 290 #define HWRM_FW_IPC_MSG 0x110UL 291 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 292 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 293 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL 294 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL 295 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL 296 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL 297 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL 298 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL 299 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL 300 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL 301 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL 302 #define HWRM_CFA_COUNTER_CFG 0x11cUL 303 #define HWRM_CFA_COUNTER_QCFG 0x11dUL 304 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL 305 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL 306 #define HWRM_CFA_EEM_QCAPS 0x120UL 307 #define HWRM_CFA_EEM_CFG 0x121UL 308 #define HWRM_CFA_EEM_QCFG 0x122UL 309 #define HWRM_CFA_EEM_OP 0x123UL 310 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL 311 #define HWRM_CFA_TFLIB 0x125UL 312 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR 0x126UL 313 #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR 0x127UL 314 #define HWRM_ENGINE_CKV_STATUS 0x12eUL 315 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 316 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 317 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 318 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 319 #define HWRM_ENGINE_CKV_FLUSH 0x133UL 320 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 321 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 322 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL 323 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL 324 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 325 #define HWRM_ENGINE_QG_QUERY 0x13dUL 326 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 327 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 328 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 329 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 330 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 331 #define HWRM_ENGINE_QG_METER_BIND 0x143UL 332 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 333 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 334 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 335 #define HWRM_ENGINE_SG_QUERY 0x147UL 336 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 337 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 338 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 339 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 340 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 341 #define HWRM_ENGINE_STATS_CONFIG 0x155UL 342 #define HWRM_ENGINE_STATS_CLEAR 0x156UL 343 #define HWRM_ENGINE_STATS_QUERY 0x157UL 344 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL 345 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 346 #define HWRM_ENGINE_RQ_FREE 0x15fUL 347 #define HWRM_ENGINE_CQ_ALLOC 0x160UL 348 #define HWRM_ENGINE_CQ_FREE 0x161UL 349 #define HWRM_ENGINE_NQ_ALLOC 0x162UL 350 #define HWRM_ENGINE_NQ_FREE 0x163UL 351 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 352 #define HWRM_ENGINE_FUNC_QCFG 0x165UL 353 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 354 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 355 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 356 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 357 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 358 #define HWRM_FUNC_VF_BW_CFG 0x195UL 359 #define HWRM_FUNC_VF_BW_QCFG 0x196UL 360 #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL 361 #define HWRM_FUNC_QSTATS_EXT 0x198UL 362 #define HWRM_STAT_EXT_CTX_QUERY 0x199UL 363 #define HWRM_FUNC_SPD_CFG 0x19aUL 364 #define HWRM_FUNC_SPD_QCFG 0x19bUL 365 #define HWRM_FUNC_PTP_PIN_QCFG 0x19cUL 366 #define HWRM_FUNC_PTP_PIN_CFG 0x19dUL 367 #define HWRM_FUNC_PTP_CFG 0x19eUL 368 #define HWRM_FUNC_PTP_TS_QUERY 0x19fUL 369 #define HWRM_FUNC_PTP_EXT_CFG 0x1a0UL 370 #define HWRM_FUNC_PTP_EXT_QCFG 0x1a1UL 371 #define HWRM_SELFTEST_QLIST 0x200UL 372 #define HWRM_SELFTEST_EXEC 0x201UL 373 #define HWRM_SELFTEST_IRQ 0x202UL 374 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 375 #define HWRM_PCIE_QSTATS 0x204UL 376 #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL 377 #define HWRM_MFG_TIMERS_QUERY 0x206UL 378 #define HWRM_MFG_OTP_CFG 0x207UL 379 #define HWRM_MFG_OTP_QCFG 0x208UL 380 #define HWRM_MFG_HDMA_TEST 0x209UL 381 #define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL 382 #define HWRM_MFG_FRU_EEPROM_READ 0x20bUL 383 #define HWRM_MFG_SOC_IMAGE 0x20cUL 384 #define HWRM_MFG_SOC_QSTATUS 0x20dUL 385 #define HWRM_MFG_PARAM_SEEPROM_SYNC 0x20eUL 386 #define HWRM_MFG_PARAM_SEEPROM_READ 0x20fUL 387 #define HWRM_MFG_PARAM_SEEPROM_HEALTH 0x210UL 388 #define HWRM_MFG_PRVSN_EXPORT_CSR 0x211UL 389 #define HWRM_MFG_PRVSN_IMPORT_CERT 0x212UL 390 #define HWRM_MFG_PRVSN_GET_STATE 0x213UL 391 #define HWRM_MFG_GET_NVM_MEASUREMENT 0x214UL 392 #define HWRM_TF 0x2bcUL 393 #define HWRM_TF_VERSION_GET 0x2bdUL 394 #define HWRM_TF_SESSION_OPEN 0x2c6UL 395 #define HWRM_TF_SESSION_ATTACH 0x2c7UL 396 #define HWRM_TF_SESSION_REGISTER 0x2c8UL 397 #define HWRM_TF_SESSION_UNREGISTER 0x2c9UL 398 #define HWRM_TF_SESSION_CLOSE 0x2caUL 399 #define HWRM_TF_SESSION_QCFG 0x2cbUL 400 #define HWRM_TF_SESSION_RESC_QCAPS 0x2ccUL 401 #define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL 402 #define HWRM_TF_SESSION_RESC_FREE 0x2ceUL 403 #define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL 404 #define HWRM_TF_SESSION_RESC_INFO 0x2d0UL 405 #define HWRM_TF_TBL_TYPE_GET 0x2daUL 406 #define HWRM_TF_TBL_TYPE_SET 0x2dbUL 407 #define HWRM_TF_TBL_TYPE_BULK_GET 0x2dcUL 408 #define HWRM_TF_CTXT_MEM_ALLOC 0x2e2UL 409 #define HWRM_TF_CTXT_MEM_FREE 0x2e3UL 410 #define HWRM_TF_CTXT_MEM_RGTR 0x2e4UL 411 #define HWRM_TF_CTXT_MEM_UNRGTR 0x2e5UL 412 #define HWRM_TF_EXT_EM_QCAPS 0x2e6UL 413 #define HWRM_TF_EXT_EM_OP 0x2e7UL 414 #define HWRM_TF_EXT_EM_CFG 0x2e8UL 415 #define HWRM_TF_EXT_EM_QCFG 0x2e9UL 416 #define HWRM_TF_EM_INSERT 0x2eaUL 417 #define HWRM_TF_EM_DELETE 0x2ebUL 418 #define HWRM_TF_EM_HASH_INSERT 0x2ecUL 419 #define HWRM_TF_EM_MOVE 0x2edUL 420 #define HWRM_TF_TCAM_SET 0x2f8UL 421 #define HWRM_TF_TCAM_GET 0x2f9UL 422 #define HWRM_TF_TCAM_MOVE 0x2faUL 423 #define HWRM_TF_TCAM_FREE 0x2fbUL 424 #define HWRM_TF_GLOBAL_CFG_SET 0x2fcUL 425 #define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL 426 #define HWRM_TF_IF_TBL_SET 0x2feUL 427 #define HWRM_TF_IF_TBL_GET 0x2ffUL 428 #define HWRM_SV 0x400UL 429 #define HWRM_DBG_READ_DIRECT 0xff10UL 430 #define HWRM_DBG_READ_INDIRECT 0xff11UL 431 #define HWRM_DBG_WRITE_DIRECT 0xff12UL 432 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 433 #define HWRM_DBG_DUMP 0xff14UL 434 #define HWRM_DBG_ERASE_NVM 0xff15UL 435 #define HWRM_DBG_CFG 0xff16UL 436 #define HWRM_DBG_COREDUMP_LIST 0xff17UL 437 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 438 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 439 #define HWRM_DBG_FW_CLI 0xff1aUL 440 #define HWRM_DBG_I2C_CMD 0xff1bUL 441 #define HWRM_DBG_RING_INFO_GET 0xff1cUL 442 #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL 443 #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL 444 #define HWRM_DBG_DRV_TRACE 0xff1fUL 445 #define HWRM_DBG_QCAPS 0xff20UL 446 #define HWRM_DBG_QCFG 0xff21UL 447 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL 448 #define HWRM_DBG_USEQ_ALLOC 0xff23UL 449 #define HWRM_DBG_USEQ_FREE 0xff24UL 450 #define HWRM_DBG_USEQ_FLUSH 0xff25UL 451 #define HWRM_DBG_USEQ_QCAPS 0xff26UL 452 #define HWRM_DBG_USEQ_CW_CFG 0xff27UL 453 #define HWRM_DBG_USEQ_SCHED_CFG 0xff28UL 454 #define HWRM_DBG_USEQ_RUN 0xff29UL 455 #define HWRM_DBG_USEQ_DELIVERY_REQ 0xff2aUL 456 #define HWRM_DBG_USEQ_RESP_HDR 0xff2bUL 457 #define HWRM_NVM_DEFRAG 0xffecUL 458 #define HWRM_NVM_REQ_ARBITRATION 0xffedUL 459 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 460 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 461 #define HWRM_NVM_FLUSH 0xfff0UL 462 #define HWRM_NVM_GET_VARIABLE 0xfff1UL 463 #define HWRM_NVM_SET_VARIABLE 0xfff2UL 464 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 465 #define HWRM_NVM_MODIFY 0xfff4UL 466 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 467 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 468 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 469 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 470 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 471 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 472 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 473 #define HWRM_NVM_RAW_DUMP 0xfffcUL 474 #define HWRM_NVM_READ 0xfffdUL 475 #define HWRM_NVM_WRITE 0xfffeUL 476 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 477 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 478 __le16 unused_0[3]; 479 }; 480 481 /* ret_codes (size:64b/8B) */ 482 struct ret_codes { 483 __le16 error_code; 484 #define HWRM_ERR_CODE_SUCCESS 0x0UL 485 #define HWRM_ERR_CODE_FAIL 0x1UL 486 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 487 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 488 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 489 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 490 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 491 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 492 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 493 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 494 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL 495 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL 496 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL 497 #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL 498 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL 499 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 500 #define HWRM_ERR_CODE_BUSY 0x10UL 501 #define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL 502 #define HWRM_ERR_CODE_PF_UNAVAILABLE 0x12UL 503 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 504 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 505 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 506 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 507 __le16 unused_0[3]; 508 }; 509 510 /* hwrm_err_output (size:128b/16B) */ 511 struct hwrm_err_output { 512 __le16 error_code; 513 __le16 req_type; 514 __le16 seq_id; 515 __le16 resp_len; 516 __le32 opaque_0; 517 __le16 opaque_1; 518 u8 cmd_err; 519 u8 valid; 520 }; 521 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 522 #define HWRM_MAX_REQ_LEN 128 523 #define HWRM_MAX_RESP_LEN 704 524 #define HW_HASH_INDEX_SIZE 0x80 525 #define HW_HASH_KEY_SIZE 40 526 #define HWRM_RESP_VALID_KEY 1 527 #define HWRM_TARGET_ID_BONO 0xFFF8 528 #define HWRM_TARGET_ID_KONG 0xFFF9 529 #define HWRM_TARGET_ID_APE 0xFFFA 530 #define HWRM_TARGET_ID_TOOLS 0xFFFD 531 #define HWRM_VERSION_MAJOR 1 532 #define HWRM_VERSION_MINOR 10 533 #define HWRM_VERSION_UPDATE 2 534 #define HWRM_VERSION_RSVD 47 535 #define HWRM_VERSION_STR "1.10.2.47" 536 537 /* hwrm_ver_get_input (size:192b/24B) */ 538 struct hwrm_ver_get_input { 539 __le16 req_type; 540 __le16 cmpl_ring; 541 __le16 seq_id; 542 __le16 target_id; 543 __le64 resp_addr; 544 u8 hwrm_intf_maj; 545 u8 hwrm_intf_min; 546 u8 hwrm_intf_upd; 547 u8 unused_0[5]; 548 }; 549 550 /* hwrm_ver_get_output (size:1408b/176B) */ 551 struct hwrm_ver_get_output { 552 __le16 error_code; 553 __le16 req_type; 554 __le16 seq_id; 555 __le16 resp_len; 556 u8 hwrm_intf_maj_8b; 557 u8 hwrm_intf_min_8b; 558 u8 hwrm_intf_upd_8b; 559 u8 hwrm_intf_rsvd_8b; 560 u8 hwrm_fw_maj_8b; 561 u8 hwrm_fw_min_8b; 562 u8 hwrm_fw_bld_8b; 563 u8 hwrm_fw_rsvd_8b; 564 u8 mgmt_fw_maj_8b; 565 u8 mgmt_fw_min_8b; 566 u8 mgmt_fw_bld_8b; 567 u8 mgmt_fw_rsvd_8b; 568 u8 netctrl_fw_maj_8b; 569 u8 netctrl_fw_min_8b; 570 u8 netctrl_fw_bld_8b; 571 u8 netctrl_fw_rsvd_8b; 572 __le32 dev_caps_cfg; 573 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 574 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 575 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 576 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 577 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 578 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 579 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 580 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 581 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 582 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL 583 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL 584 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL 585 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL 586 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL 587 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL 588 u8 roce_fw_maj_8b; 589 u8 roce_fw_min_8b; 590 u8 roce_fw_bld_8b; 591 u8 roce_fw_rsvd_8b; 592 char hwrm_fw_name[16]; 593 char mgmt_fw_name[16]; 594 char netctrl_fw_name[16]; 595 char active_pkg_name[16]; 596 char roce_fw_name[16]; 597 __le16 chip_num; 598 u8 chip_rev; 599 u8 chip_metal; 600 u8 chip_bond_id; 601 u8 chip_platform_type; 602 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 603 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 604 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 605 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 606 __le16 max_req_win_len; 607 __le16 max_resp_len; 608 __le16 def_req_timeout; 609 u8 flags; 610 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 611 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 612 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY_BACKING_STORE 0x4UL 613 u8 unused_0[2]; 614 u8 always_1; 615 __le16 hwrm_intf_major; 616 __le16 hwrm_intf_minor; 617 __le16 hwrm_intf_build; 618 __le16 hwrm_intf_patch; 619 __le16 hwrm_fw_major; 620 __le16 hwrm_fw_minor; 621 __le16 hwrm_fw_build; 622 __le16 hwrm_fw_patch; 623 __le16 mgmt_fw_major; 624 __le16 mgmt_fw_minor; 625 __le16 mgmt_fw_build; 626 __le16 mgmt_fw_patch; 627 __le16 netctrl_fw_major; 628 __le16 netctrl_fw_minor; 629 __le16 netctrl_fw_build; 630 __le16 netctrl_fw_patch; 631 __le16 roce_fw_major; 632 __le16 roce_fw_minor; 633 __le16 roce_fw_build; 634 __le16 roce_fw_patch; 635 __le16 max_ext_req_len; 636 __le16 max_req_timeout; 637 u8 unused_1[3]; 638 u8 valid; 639 }; 640 641 /* eject_cmpl (size:128b/16B) */ 642 struct eject_cmpl { 643 __le16 type; 644 #define EJECT_CMPL_TYPE_MASK 0x3fUL 645 #define EJECT_CMPL_TYPE_SFT 0 646 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 647 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 648 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL 649 #define EJECT_CMPL_FLAGS_SFT 6 650 #define EJECT_CMPL_FLAGS_ERROR 0x40UL 651 __le16 len; 652 __le32 opaque; 653 __le16 v; 654 #define EJECT_CMPL_V 0x1UL 655 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL 656 #define EJECT_CMPL_ERRORS_SFT 1 657 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL 658 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 659 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1) 660 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1) 661 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1) 662 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1) 663 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH 664 __le16 reserved16; 665 __le32 unused_2; 666 }; 667 668 /* hwrm_cmpl (size:128b/16B) */ 669 struct hwrm_cmpl { 670 __le16 type; 671 #define CMPL_TYPE_MASK 0x3fUL 672 #define CMPL_TYPE_SFT 0 673 #define CMPL_TYPE_HWRM_DONE 0x20UL 674 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 675 __le16 sequence_id; 676 __le32 unused_1; 677 __le32 v; 678 #define CMPL_V 0x1UL 679 __le32 unused_3; 680 }; 681 682 /* hwrm_fwd_req_cmpl (size:128b/16B) */ 683 struct hwrm_fwd_req_cmpl { 684 __le16 req_len_type; 685 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 686 #define FWD_REQ_CMPL_TYPE_SFT 0 687 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 688 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 689 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 690 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 691 __le16 source_id; 692 __le32 unused0; 693 __le32 req_buf_addr_v[2]; 694 #define FWD_REQ_CMPL_V 0x1UL 695 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 696 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 697 }; 698 699 /* hwrm_fwd_resp_cmpl (size:128b/16B) */ 700 struct hwrm_fwd_resp_cmpl { 701 __le16 type; 702 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 703 #define FWD_RESP_CMPL_TYPE_SFT 0 704 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 705 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 706 __le16 source_id; 707 __le16 resp_len; 708 __le16 unused_1; 709 __le32 resp_buf_addr_v[2]; 710 #define FWD_RESP_CMPL_V 0x1UL 711 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 712 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 713 }; 714 715 /* hwrm_async_event_cmpl (size:128b/16B) */ 716 struct hwrm_async_event_cmpl { 717 __le16 type; 718 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 719 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 720 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 721 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 722 __le16 event_id; 723 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 724 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 725 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 726 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 727 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 728 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 729 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 730 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 731 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 732 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL 733 #define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG 0xaUL 734 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 735 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 736 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 737 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 738 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 739 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 740 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 741 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 742 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 743 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 744 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 745 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 746 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL 747 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 748 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 749 #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL 750 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL 751 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL 752 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL 753 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL 754 #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL 755 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL 756 #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL 757 #define ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST 0x42UL 758 #define ASYNC_EVENT_CMPL_EVENT_ID_PHC_MASTER 0x43UL 759 #define ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP 0x44UL 760 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT 0x45UL 761 #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x46UL 762 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 763 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 764 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 765 __le32 event_data2; 766 u8 opaque_v; 767 #define ASYNC_EVENT_CMPL_V 0x1UL 768 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 769 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 770 u8 timestamp_lo; 771 __le16 timestamp_hi; 772 __le32 event_data1; 773 }; 774 775 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 776 struct hwrm_async_event_cmpl_link_status_change { 777 __le16 type; 778 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 779 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 780 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 781 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 782 __le16 event_id; 783 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 784 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 785 __le32 event_data2; 786 u8 opaque_v; 787 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 788 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 789 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 790 u8 timestamp_lo; 791 __le16 timestamp_hi; 792 __le32 event_data1; 793 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 794 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 795 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 796 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 797 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 798 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 799 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 800 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 801 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 802 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 803 }; 804 805 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 806 struct hwrm_async_event_cmpl_port_conn_not_allowed { 807 __le16 type; 808 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 809 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 810 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 811 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 812 __le16 event_id; 813 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 814 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 815 __le32 event_data2; 816 u8 opaque_v; 817 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 818 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 819 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 820 u8 timestamp_lo; 821 __le16 timestamp_hi; 822 __le32 event_data1; 823 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 824 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 825 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 826 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 827 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 828 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 829 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 830 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 831 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 832 }; 833 834 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 835 struct hwrm_async_event_cmpl_link_speed_cfg_change { 836 __le16 type; 837 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 838 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 839 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 840 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 841 __le16 event_id; 842 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 843 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 844 __le32 event_data2; 845 u8 opaque_v; 846 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 847 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 848 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 849 u8 timestamp_lo; 850 __le16 timestamp_hi; 851 __le32 event_data1; 852 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 853 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 854 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 855 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 856 }; 857 858 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ 859 struct hwrm_async_event_cmpl_reset_notify { 860 __le16 type; 861 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL 862 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 863 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 864 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 865 __le16 event_id; 866 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 867 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 868 __le32 event_data2; 869 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK 0xffffUL 870 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0 871 u8 opaque_v; 872 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 873 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL 874 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 875 u8 timestamp_lo; 876 __le16 timestamp_hi; 877 __le32 event_data1; 878 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL 879 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0 880 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL 881 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL 882 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 883 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL 884 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8 885 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 886 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 887 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 888 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET (0x4UL << 8) 889 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET 890 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 891 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 892 }; 893 894 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ 895 struct hwrm_async_event_cmpl_error_recovery { 896 __le16 type; 897 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL 898 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 899 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 900 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 901 __le16 event_id; 902 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL 903 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 904 __le32 event_data2; 905 u8 opaque_v; 906 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL 907 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL 908 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 909 u8 timestamp_lo; 910 __le16 timestamp_hi; 911 __le32 event_data1; 912 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL 913 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0 914 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL 915 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL 916 }; 917 918 /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */ 919 struct hwrm_async_event_cmpl_ring_monitor_msg { 920 __le16 type; 921 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK 0x3fUL 922 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0 923 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 0x2eUL 924 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 925 __le16 event_id; 926 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL 927 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 928 __le32 event_data2; 929 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL 930 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0 931 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX 0x0UL 932 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX 0x1UL 933 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 0x2UL 934 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 935 u8 opaque_v; 936 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V 0x1UL 937 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL 938 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1 939 u8 timestamp_lo; 940 __le16 timestamp_hi; 941 __le32 event_data1; 942 }; 943 944 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 945 struct hwrm_async_event_cmpl_vf_cfg_change { 946 __le16 type; 947 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 948 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 949 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 950 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 951 __le16 event_id; 952 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 953 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 954 __le32 event_data2; 955 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK 0xffffUL 956 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0 957 u8 opaque_v; 958 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 959 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 960 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 961 u8 timestamp_lo; 962 __le16 timestamp_hi; 963 __le32 event_data1; 964 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 965 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 966 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 967 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 968 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 969 }; 970 971 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ 972 struct hwrm_async_event_cmpl_default_vnic_change { 973 __le16 type; 974 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL 975 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0 976 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 977 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 978 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL 979 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6 980 __le16 event_id; 981 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL 982 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 983 __le32 event_data2; 984 u8 opaque_v; 985 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL 986 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL 987 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1 988 u8 timestamp_lo; 989 __le16 timestamp_hi; 990 __le32 event_data1; 991 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL 992 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0 993 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL 994 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL 995 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 996 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL 997 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2 998 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL 999 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10 1000 }; 1001 1002 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ 1003 struct hwrm_async_event_cmpl_hw_flow_aged { 1004 __le16 type; 1005 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL 1006 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 1007 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1008 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 1009 __le16 event_id; 1010 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL 1011 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 1012 __le32 event_data2; 1013 u8 opaque_v; 1014 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL 1015 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL 1016 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 1017 u8 timestamp_lo; 1018 __le16 timestamp_hi; 1019 __le32 event_data1; 1020 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL 1021 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0 1022 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL 1023 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31) 1024 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31) 1025 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX 1026 }; 1027 1028 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ 1029 struct hwrm_async_event_cmpl_eem_cache_flush_req { 1030 __le16 type; 1031 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL 1032 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0 1033 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1034 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 1035 __le16 event_id; 1036 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 1037 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 1038 __le32 event_data2; 1039 u8 opaque_v; 1040 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL 1041 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL 1042 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 1043 u8 timestamp_lo; 1044 __le16 timestamp_hi; 1045 __le32 event_data1; 1046 }; 1047 1048 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ 1049 struct hwrm_async_event_cmpl_eem_cache_flush_done { 1050 __le16 type; 1051 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL 1052 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0 1053 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1054 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 1055 __le16 event_id; 1056 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 1057 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 1058 __le32 event_data2; 1059 u8 opaque_v; 1060 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL 1061 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL 1062 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 1063 u8 timestamp_lo; 1064 __le16 timestamp_hi; 1065 __le32 event_data1; 1066 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL 1067 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0 1068 }; 1069 1070 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ 1071 struct hwrm_async_event_cmpl_deferred_response { 1072 __le16 type; 1073 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK 0x3fUL 1074 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0 1075 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1076 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 1077 __le16 event_id; 1078 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL 1079 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 1080 __le32 event_data2; 1081 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL 1082 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0 1083 u8 opaque_v; 1084 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V 0x1UL 1085 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL 1086 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1 1087 u8 timestamp_lo; 1088 __le16 timestamp_hi; 1089 __le32 event_data1; 1090 }; 1091 1092 /* hwrm_async_event_cmpl_echo_request (size:128b/16B) */ 1093 struct hwrm_async_event_cmpl_echo_request { 1094 __le16 type; 1095 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK 0x3fUL 1096 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0 1097 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1098 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 1099 __le16 event_id; 1100 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 0x42UL 1101 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 1102 __le32 event_data2; 1103 u8 opaque_v; 1104 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_V 0x1UL 1105 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK 0xfeUL 1106 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1 1107 u8 timestamp_lo; 1108 __le16 timestamp_hi; 1109 __le32 event_data1; 1110 }; 1111 1112 /* hwrm_async_event_cmpl_phc_master (size:128b/16B) */ 1113 struct hwrm_async_event_cmpl_phc_master { 1114 __le16 type; 1115 #define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_MASK 0x3fUL 1116 #define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_SFT 0 1117 #define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1118 #define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_LAST ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_HWRM_ASYNC_EVENT 1119 __le16 event_id; 1120 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_PHC_MASTER 0x43UL 1121 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_LAST ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_PHC_MASTER 1122 __le32 event_data2; 1123 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_MASTER_FID_MASK 0xffffUL 1124 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_MASTER_FID_SFT 0 1125 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_SEC_FID_MASK 0xffff0000UL 1126 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_SEC_FID_SFT 16 1127 u8 opaque_v; 1128 #define ASYNC_EVENT_CMPL_PHC_MASTER_V 0x1UL 1129 #define ASYNC_EVENT_CMPL_PHC_MASTER_OPAQUE_MASK 0xfeUL 1130 #define ASYNC_EVENT_CMPL_PHC_MASTER_OPAQUE_SFT 1 1131 u8 timestamp_lo; 1132 __le16 timestamp_hi; 1133 __le32 event_data1; 1134 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_MASK 0xfUL 1135 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_SFT 0 1136 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_MASTER 0x1UL 1137 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_SECONDARY 0x2UL 1138 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_FAILOVER 0x3UL 1139 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_LAST ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_FAILOVER 1140 }; 1141 1142 /* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */ 1143 struct hwrm_async_event_cmpl_pps_timestamp { 1144 __le16 type; 1145 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK 0x3fUL 1146 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0 1147 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1148 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 1149 __le16 event_id; 1150 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 0x44UL 1151 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 1152 __le32 event_data2; 1153 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE 0x1UL 1154 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL 0x0UL 1155 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 0x1UL 1156 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 1157 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK 0xeUL 1158 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT 1 1159 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK 0xffff0UL 1160 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT 4 1161 u8 opaque_v; 1162 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V 0x1UL 1163 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK 0xfeUL 1164 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1 1165 u8 timestamp_lo; 1166 __le16 timestamp_hi; 1167 __le32 event_data1; 1168 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK 0xffffffffUL 1169 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT 0 1170 }; 1171 1172 /* hwrm_async_event_cmpl_error_report (size:128b/16B) */ 1173 struct hwrm_async_event_cmpl_error_report { 1174 __le16 type; 1175 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK 0x3fUL 1176 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0 1177 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1178 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 1179 __le16 event_id; 1180 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 0x45UL 1181 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 1182 __le32 event_data2; 1183 u8 opaque_v; 1184 #define ASYNC_EVENT_CMPL_ERROR_REPORT_V 0x1UL 1185 #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK 0xfeUL 1186 #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1 1187 u8 timestamp_lo; 1188 __le16 timestamp_hi; 1189 __le32 event_data1; 1190 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1191 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0 1192 }; 1193 1194 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */ 1195 struct hwrm_async_event_cmpl_hwrm_error { 1196 __le16 type; 1197 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL 1198 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 1199 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1200 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 1201 __le16 event_id; 1202 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL 1203 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 1204 __le32 event_data2; 1205 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL 1206 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 1207 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL 1208 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL 1209 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL 1210 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 1211 u8 opaque_v; 1212 #define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL 1213 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL 1214 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 1215 u8 timestamp_lo; 1216 __le16 timestamp_hi; 1217 __le32 event_data1; 1218 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL 1219 }; 1220 1221 /* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */ 1222 struct hwrm_async_event_cmpl_error_report_base { 1223 __le16 type; 1224 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK 0x3fUL 1225 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0 1226 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1227 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 1228 __le16 event_id; 1229 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 0x45UL 1230 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 1231 __le32 event_data2; 1232 u8 opaque_v; 1233 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V 0x1UL 1234 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK 0xfeUL 1235 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1 1236 u8 timestamp_lo; 1237 __le16 timestamp_hi; 1238 __le32 event_data1; 1239 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1240 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT 0 1241 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED 0x0UL 1242 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 1243 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 1244 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM 0x3UL 1245 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM 1246 }; 1247 1248 /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ 1249 struct hwrm_async_event_cmpl_error_report_pause_storm { 1250 __le16 type; 1251 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK 0x3fUL 1252 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT 0 1253 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1254 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 1255 __le16 event_id; 1256 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 0x45UL 1257 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 1258 __le32 event_data2; 1259 u8 opaque_v; 1260 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V 0x1UL 1261 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK 0xfeUL 1262 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1 1263 u8 timestamp_lo; 1264 __le16 timestamp_hi; 1265 __le32 event_data1; 1266 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1267 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT 0 1268 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 1269 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 1270 }; 1271 1272 /* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */ 1273 struct hwrm_async_event_cmpl_error_report_invalid_signal { 1274 __le16 type; 1275 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK 0x3fUL 1276 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT 0 1277 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1278 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 1279 __le16 event_id; 1280 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 0x45UL 1281 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 1282 __le32 event_data2; 1283 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK 0xffUL 1284 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT 0 1285 u8 opaque_v; 1286 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V 0x1UL 1287 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK 0xfeUL 1288 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1 1289 u8 timestamp_lo; 1290 __le16 timestamp_hi; 1291 __le32 event_data1; 1292 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1293 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT 0 1294 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 1295 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 1296 }; 1297 1298 /* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */ 1299 struct hwrm_async_event_cmpl_error_report_nvm { 1300 __le16 type; 1301 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK 0x3fUL 1302 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0 1303 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1304 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 1305 __le16 event_id; 1306 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 0x45UL 1307 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 1308 __le32 event_data2; 1309 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK 0xffffffffUL 1310 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT 0 1311 u8 opaque_v; 1312 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V 0x1UL 1313 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK 0xfeUL 1314 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1 1315 u8 timestamp_lo; 1316 __le16 timestamp_hi; 1317 __le32 event_data1; 1318 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1319 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT 0 1320 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 0x3UL 1321 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 1322 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK 0xff00UL 1323 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT 8 1324 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE (0x1UL << 8) 1325 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE (0x2UL << 8) 1326 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE 1327 }; 1328 1329 /* hwrm_func_reset_input (size:192b/24B) */ 1330 struct hwrm_func_reset_input { 1331 __le16 req_type; 1332 __le16 cmpl_ring; 1333 __le16 seq_id; 1334 __le16 target_id; 1335 __le64 resp_addr; 1336 __le32 enables; 1337 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 1338 __le16 vf_id; 1339 u8 func_reset_level; 1340 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 1341 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 1342 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 1343 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 1344 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 1345 u8 unused_0; 1346 }; 1347 1348 /* hwrm_func_reset_output (size:128b/16B) */ 1349 struct hwrm_func_reset_output { 1350 __le16 error_code; 1351 __le16 req_type; 1352 __le16 seq_id; 1353 __le16 resp_len; 1354 u8 unused_0[7]; 1355 u8 valid; 1356 }; 1357 1358 /* hwrm_func_getfid_input (size:192b/24B) */ 1359 struct hwrm_func_getfid_input { 1360 __le16 req_type; 1361 __le16 cmpl_ring; 1362 __le16 seq_id; 1363 __le16 target_id; 1364 __le64 resp_addr; 1365 __le32 enables; 1366 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 1367 __le16 pci_id; 1368 u8 unused_0[2]; 1369 }; 1370 1371 /* hwrm_func_getfid_output (size:128b/16B) */ 1372 struct hwrm_func_getfid_output { 1373 __le16 error_code; 1374 __le16 req_type; 1375 __le16 seq_id; 1376 __le16 resp_len; 1377 __le16 fid; 1378 u8 unused_0[5]; 1379 u8 valid; 1380 }; 1381 1382 /* hwrm_func_vf_alloc_input (size:192b/24B) */ 1383 struct hwrm_func_vf_alloc_input { 1384 __le16 req_type; 1385 __le16 cmpl_ring; 1386 __le16 seq_id; 1387 __le16 target_id; 1388 __le64 resp_addr; 1389 __le32 enables; 1390 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 1391 __le16 first_vf_id; 1392 __le16 num_vfs; 1393 }; 1394 1395 /* hwrm_func_vf_alloc_output (size:128b/16B) */ 1396 struct hwrm_func_vf_alloc_output { 1397 __le16 error_code; 1398 __le16 req_type; 1399 __le16 seq_id; 1400 __le16 resp_len; 1401 __le16 first_vf_id; 1402 u8 unused_0[5]; 1403 u8 valid; 1404 }; 1405 1406 /* hwrm_func_vf_free_input (size:192b/24B) */ 1407 struct hwrm_func_vf_free_input { 1408 __le16 req_type; 1409 __le16 cmpl_ring; 1410 __le16 seq_id; 1411 __le16 target_id; 1412 __le64 resp_addr; 1413 __le32 enables; 1414 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 1415 __le16 first_vf_id; 1416 __le16 num_vfs; 1417 }; 1418 1419 /* hwrm_func_vf_free_output (size:128b/16B) */ 1420 struct hwrm_func_vf_free_output { 1421 __le16 error_code; 1422 __le16 req_type; 1423 __le16 seq_id; 1424 __le16 resp_len; 1425 u8 unused_0[7]; 1426 u8 valid; 1427 }; 1428 1429 /* hwrm_func_vf_cfg_input (size:448b/56B) */ 1430 struct hwrm_func_vf_cfg_input { 1431 __le16 req_type; 1432 __le16 cmpl_ring; 1433 __le16 seq_id; 1434 __le16 target_id; 1435 __le64 resp_addr; 1436 __le32 enables; 1437 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 1438 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 1439 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 1440 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 1441 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 1442 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 1443 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 1444 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 1445 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 1446 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 1447 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 1448 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 1449 __le16 mtu; 1450 __le16 guest_vlan; 1451 __le16 async_event_cr; 1452 u8 dflt_mac_addr[6]; 1453 __le32 flags; 1454 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 1455 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 1456 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 1457 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 1458 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 1459 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 1460 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 1461 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 1462 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x100UL 1463 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x200UL 1464 __le16 num_rsscos_ctxs; 1465 __le16 num_cmpl_rings; 1466 __le16 num_tx_rings; 1467 __le16 num_rx_rings; 1468 __le16 num_l2_ctxs; 1469 __le16 num_vnics; 1470 __le16 num_stat_ctxs; 1471 __le16 num_hw_ring_grps; 1472 u8 unused_0[4]; 1473 }; 1474 1475 /* hwrm_func_vf_cfg_output (size:128b/16B) */ 1476 struct hwrm_func_vf_cfg_output { 1477 __le16 error_code; 1478 __le16 req_type; 1479 __le16 seq_id; 1480 __le16 resp_len; 1481 u8 unused_0[7]; 1482 u8 valid; 1483 }; 1484 1485 /* hwrm_func_qcaps_input (size:192b/24B) */ 1486 struct hwrm_func_qcaps_input { 1487 __le16 req_type; 1488 __le16 cmpl_ring; 1489 __le16 seq_id; 1490 __le16 target_id; 1491 __le64 resp_addr; 1492 __le16 fid; 1493 u8 unused_0[6]; 1494 }; 1495 1496 /* hwrm_func_qcaps_output (size:704b/88B) */ 1497 struct hwrm_func_qcaps_output { 1498 __le16 error_code; 1499 __le16 req_type; 1500 __le16 seq_id; 1501 __le16 resp_len; 1502 __le16 fid; 1503 __le16 port_id; 1504 __le32 flags; 1505 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1506 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 1507 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1508 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1509 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1510 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1511 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1512 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1513 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1514 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1515 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 1516 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 1517 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 1518 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 1519 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 1520 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 1521 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 1522 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 1523 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 1524 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 1525 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 1526 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL 1527 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL 1528 #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL 1529 #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL 1530 #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL 1531 #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL 1532 #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL 1533 #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL 1534 #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL 1535 #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL 1536 #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL 1537 u8 mac_address[6]; 1538 __le16 max_rsscos_ctx; 1539 __le16 max_cmpl_rings; 1540 __le16 max_tx_rings; 1541 __le16 max_rx_rings; 1542 __le16 max_l2_ctxs; 1543 __le16 max_vnics; 1544 __le16 first_vf_id; 1545 __le16 max_vfs; 1546 __le16 max_stat_ctx; 1547 __le32 max_encap_records; 1548 __le32 max_decap_records; 1549 __le32 max_tx_em_flows; 1550 __le32 max_tx_wm_flows; 1551 __le32 max_rx_em_flows; 1552 __le32 max_rx_wm_flows; 1553 __le32 max_mcast_filters; 1554 __le32 max_flow_id; 1555 __le32 max_hw_ring_grps; 1556 __le16 max_sp_tx_rings; 1557 __le16 max_msix_vfs; 1558 __le32 flags_ext; 1559 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL 1560 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL 1561 #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL 1562 #define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT 0x8UL 1563 #define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT 0x10UL 1564 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL 1565 #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL 1566 #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL 1567 #define FUNC_QCAPS_RESP_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED 0x100UL 1568 #define FUNC_QCAPS_RESP_FLAGS_EXT_SOC_SPD_SUPPORTED 0x200UL 1569 #define FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED 0x400UL 1570 #define FUNC_QCAPS_RESP_FLAGS_EXT_FAST_RESET_CAPABLE 0x800UL 1571 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_METADATA_CFG_CAPABLE 0x1000UL 1572 #define FUNC_QCAPS_RESP_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED 0x2000UL 1573 #define FUNC_QCAPS_RESP_FLAGS_EXT_BD_METADATA_SUPPORTED 0x4000UL 1574 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECHO_REQUEST_SUPPORTED 0x8000UL 1575 #define FUNC_QCAPS_RESP_FLAGS_EXT_NPAR_1_2_SUPPORTED 0x10000UL 1576 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PTM_SUPPORTED 0x20000UL 1577 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED 0x40000UL 1578 #define FUNC_QCAPS_RESP_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED 0x80000UL 1579 #define FUNC_QCAPS_RESP_FLAGS_EXT_PARTITION_BW_SUPPORTED 0x100000UL 1580 #define FUNC_QCAPS_RESP_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED 0x200000UL 1581 #define FUNC_QCAPS_RESP_FLAGS_EXT_KTLS_SUPPORTED 0x400000UL 1582 #define FUNC_QCAPS_RESP_FLAGS_EXT_EP_RATE_CONTROL 0x800000UL 1583 u8 max_schqs; 1584 u8 mpc_chnls_cap; 1585 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL 1586 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE 0x2UL 1587 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA 0x4UL 1588 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA 0x8UL 1589 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE 0x10UL 1590 u8 unused_1; 1591 u8 valid; 1592 }; 1593 1594 /* hwrm_func_qcfg_input (size:192b/24B) */ 1595 struct hwrm_func_qcfg_input { 1596 __le16 req_type; 1597 __le16 cmpl_ring; 1598 __le16 seq_id; 1599 __le16 target_id; 1600 __le64 resp_addr; 1601 __le16 fid; 1602 u8 unused_0[6]; 1603 }; 1604 1605 /* hwrm_func_qcfg_output (size:832b/104B) */ 1606 struct hwrm_func_qcfg_output { 1607 __le16 error_code; 1608 __le16 req_type; 1609 __le16 seq_id; 1610 __le16 resp_len; 1611 __le16 fid; 1612 __le16 port_id; 1613 __le16 vlan; 1614 __le16 flags; 1615 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1616 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1617 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 1618 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 1619 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 1620 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 1621 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 1622 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL 1623 #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL 1624 #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL 1625 #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL 1626 #define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL 1627 #define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED 0x1000UL 1628 #define FUNC_QCFG_RESP_FLAGS_MULTI_ROOT 0x2000UL 1629 #define FUNC_QCFG_RESP_FLAGS_ENABLE_RDMA_SRIOV 0x4000UL 1630 u8 mac_address[6]; 1631 __le16 pci_id; 1632 __le16 alloc_rsscos_ctx; 1633 __le16 alloc_cmpl_rings; 1634 __le16 alloc_tx_rings; 1635 __le16 alloc_rx_rings; 1636 __le16 alloc_l2_ctx; 1637 __le16 alloc_vnics; 1638 __le16 admin_mtu; 1639 __le16 mru; 1640 __le16 stat_ctx_id; 1641 u8 port_partition_type; 1642 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1643 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1644 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1645 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1646 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 1647 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_2 0x5UL 1648 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 1649 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 1650 u8 port_pf_cnt; 1651 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 1652 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 1653 __le16 dflt_vnic_id; 1654 __le16 max_mtu_configured; 1655 __le32 min_bw; 1656 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1657 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 1658 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 1659 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 1660 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 1661 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 1662 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1663 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 1664 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1665 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1666 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1667 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1668 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1669 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1670 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 1671 __le32 max_bw; 1672 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1673 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 1674 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 1675 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 1676 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 1677 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 1678 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1679 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 1680 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1681 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1682 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1683 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1684 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1685 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1686 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 1687 u8 evb_mode; 1688 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 1689 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 1690 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 1691 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 1692 u8 options; 1693 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1694 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 1695 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1696 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1697 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 1698 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1699 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 1700 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1701 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1702 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1703 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 1704 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 1705 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 1706 __le16 alloc_vfs; 1707 __le32 alloc_mcast_filters; 1708 __le32 alloc_hw_ring_grps; 1709 __le16 alloc_sp_tx_rings; 1710 __le16 alloc_stat_ctx; 1711 __le16 alloc_msix; 1712 __le16 registered_vfs; 1713 __le16 l2_doorbell_bar_size_kb; 1714 u8 unused_1; 1715 u8 always_1; 1716 __le32 reset_addr_poll; 1717 __le16 legacy_l2_db_size_kb; 1718 __le16 svif_info; 1719 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL 1720 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0 1721 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL 1722 u8 mpc_chnls; 1723 #define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED 0x1UL 1724 #define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED 0x2UL 1725 #define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL 1726 #define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL 1727 #define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL 1728 u8 unused_2[3]; 1729 __le32 partition_min_bw; 1730 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1731 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_SFT 0 1732 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE 0x10000000UL 1733 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 1734 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 1735 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES 1736 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1737 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 1738 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1739 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 1740 __le32 partition_max_bw; 1741 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1742 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_SFT 0 1743 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE 0x10000000UL 1744 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 1745 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 1746 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES 1747 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1748 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 1749 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1750 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 1751 __le16 host_mtu; 1752 u8 unused_3; 1753 u8 valid; 1754 }; 1755 1756 /* hwrm_func_cfg_input (size:832b/104B) */ 1757 struct hwrm_func_cfg_input { 1758 __le16 req_type; 1759 __le16 cmpl_ring; 1760 __le16 seq_id; 1761 __le16 target_id; 1762 __le64 resp_addr; 1763 __le16 fid; 1764 __le16 num_msix; 1765 __le32 flags; 1766 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 1767 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 1768 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 1769 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 1770 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 1771 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 1772 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 1773 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 1774 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 1775 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 1776 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 1777 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 1778 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 1779 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 1780 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 1781 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 1782 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 1783 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL 1784 #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL 1785 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL 1786 #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL 1787 #define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS 0x4000000UL 1788 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x8000000UL 1789 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL 1790 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_ENABLE 0x20000000UL 1791 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_DISABLE 0x40000000UL 1792 __le32 enables; 1793 #define FUNC_CFG_REQ_ENABLES_ADMIN_MTU 0x1UL 1794 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1795 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1796 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1797 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1798 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1799 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1800 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1801 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1802 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1803 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1804 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1805 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1806 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1807 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1808 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1809 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1810 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1811 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1812 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1813 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 1814 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 1815 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 1816 #define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL 1817 #define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL 1818 #define FUNC_CFG_REQ_ENABLES_MPC_CHNLS 0x2000000UL 1819 #define FUNC_CFG_REQ_ENABLES_PARTITION_MIN_BW 0x4000000UL 1820 #define FUNC_CFG_REQ_ENABLES_PARTITION_MAX_BW 0x8000000UL 1821 #define FUNC_CFG_REQ_ENABLES_TPID 0x10000000UL 1822 #define FUNC_CFG_REQ_ENABLES_HOST_MTU 0x20000000UL 1823 __le16 admin_mtu; 1824 __le16 mru; 1825 __le16 num_rsscos_ctxs; 1826 __le16 num_cmpl_rings; 1827 __le16 num_tx_rings; 1828 __le16 num_rx_rings; 1829 __le16 num_l2_ctxs; 1830 __le16 num_vnics; 1831 __le16 num_stat_ctxs; 1832 __le16 num_hw_ring_grps; 1833 u8 dflt_mac_addr[6]; 1834 __le16 dflt_vlan; 1835 __be32 dflt_ip_addr[4]; 1836 __le32 min_bw; 1837 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1838 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 1839 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 1840 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 1841 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 1842 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 1843 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1844 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 1845 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1846 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1847 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1848 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1849 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1850 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1851 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1852 __le32 max_bw; 1853 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1854 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1855 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1856 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1857 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1858 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1859 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1860 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1861 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1862 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1863 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1864 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1865 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1866 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1867 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1868 __le16 async_event_cr; 1869 u8 vlan_antispoof_mode; 1870 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1871 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1872 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1873 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1874 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 1875 u8 allowed_vlan_pris; 1876 u8 evb_mode; 1877 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1878 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1879 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1880 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 1881 u8 options; 1882 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1883 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 1884 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1885 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1886 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 1887 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1888 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 1889 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1890 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1891 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1892 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 1893 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 1894 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 1895 __le16 num_mcast_filters; 1896 __le16 schq_id; 1897 __le16 mpc_chnls; 1898 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE 0x1UL 1899 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE 0x2UL 1900 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE 0x4UL 1901 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE 0x8UL 1902 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE 0x10UL 1903 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE 0x20UL 1904 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE 0x40UL 1905 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE 0x80UL 1906 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE 0x100UL 1907 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE 0x200UL 1908 __le32 partition_min_bw; 1909 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1910 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_SFT 0 1911 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE 0x10000000UL 1912 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 1913 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 1914 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES 1915 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1916 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 1917 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1918 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 1919 __le32 partition_max_bw; 1920 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1921 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_SFT 0 1922 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE 0x10000000UL 1923 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 1924 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 1925 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES 1926 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1927 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 1928 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1929 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 1930 __be16 tpid; 1931 __le16 host_mtu; 1932 }; 1933 1934 /* hwrm_func_cfg_output (size:128b/16B) */ 1935 struct hwrm_func_cfg_output { 1936 __le16 error_code; 1937 __le16 req_type; 1938 __le16 seq_id; 1939 __le16 resp_len; 1940 u8 unused_0[7]; 1941 u8 valid; 1942 }; 1943 1944 /* hwrm_func_qstats_input (size:192b/24B) */ 1945 struct hwrm_func_qstats_input { 1946 __le16 req_type; 1947 __le16 cmpl_ring; 1948 __le16 seq_id; 1949 __le16 target_id; 1950 __le64 resp_addr; 1951 __le16 fid; 1952 u8 flags; 1953 #define FUNC_QSTATS_REQ_FLAGS_UNUSED 0x0UL 1954 #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL 1955 #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL 1956 #define FUNC_QSTATS_REQ_FLAGS_LAST FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 1957 u8 unused_0[5]; 1958 }; 1959 1960 /* hwrm_func_qstats_output (size:1408b/176B) */ 1961 struct hwrm_func_qstats_output { 1962 __le16 error_code; 1963 __le16 req_type; 1964 __le16 seq_id; 1965 __le16 resp_len; 1966 __le64 tx_ucast_pkts; 1967 __le64 tx_mcast_pkts; 1968 __le64 tx_bcast_pkts; 1969 __le64 tx_discard_pkts; 1970 __le64 tx_drop_pkts; 1971 __le64 tx_ucast_bytes; 1972 __le64 tx_mcast_bytes; 1973 __le64 tx_bcast_bytes; 1974 __le64 rx_ucast_pkts; 1975 __le64 rx_mcast_pkts; 1976 __le64 rx_bcast_pkts; 1977 __le64 rx_discard_pkts; 1978 __le64 rx_drop_pkts; 1979 __le64 rx_ucast_bytes; 1980 __le64 rx_mcast_bytes; 1981 __le64 rx_bcast_bytes; 1982 __le64 rx_agg_pkts; 1983 __le64 rx_agg_bytes; 1984 __le64 rx_agg_events; 1985 __le64 rx_agg_aborts; 1986 u8 unused_0[7]; 1987 u8 valid; 1988 }; 1989 1990 /* hwrm_func_qstats_ext_input (size:256b/32B) */ 1991 struct hwrm_func_qstats_ext_input { 1992 __le16 req_type; 1993 __le16 cmpl_ring; 1994 __le16 seq_id; 1995 __le16 target_id; 1996 __le64 resp_addr; 1997 __le16 fid; 1998 u8 flags; 1999 #define FUNC_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 2000 #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL 2001 #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL 2002 #define FUNC_QSTATS_EXT_REQ_FLAGS_LAST FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 2003 u8 unused_0[1]; 2004 __le32 enables; 2005 #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL 2006 __le16 schq_id; 2007 __le16 traffic_class; 2008 u8 unused_1[4]; 2009 }; 2010 2011 /* hwrm_func_qstats_ext_output (size:1536b/192B) */ 2012 struct hwrm_func_qstats_ext_output { 2013 __le16 error_code; 2014 __le16 req_type; 2015 __le16 seq_id; 2016 __le16 resp_len; 2017 __le64 rx_ucast_pkts; 2018 __le64 rx_mcast_pkts; 2019 __le64 rx_bcast_pkts; 2020 __le64 rx_discard_pkts; 2021 __le64 rx_error_pkts; 2022 __le64 rx_ucast_bytes; 2023 __le64 rx_mcast_bytes; 2024 __le64 rx_bcast_bytes; 2025 __le64 tx_ucast_pkts; 2026 __le64 tx_mcast_pkts; 2027 __le64 tx_bcast_pkts; 2028 __le64 tx_error_pkts; 2029 __le64 tx_discard_pkts; 2030 __le64 tx_ucast_bytes; 2031 __le64 tx_mcast_bytes; 2032 __le64 tx_bcast_bytes; 2033 __le64 rx_tpa_eligible_pkt; 2034 __le64 rx_tpa_eligible_bytes; 2035 __le64 rx_tpa_pkt; 2036 __le64 rx_tpa_bytes; 2037 __le64 rx_tpa_errors; 2038 __le64 rx_tpa_events; 2039 u8 unused_0[7]; 2040 u8 valid; 2041 }; 2042 2043 /* hwrm_func_clr_stats_input (size:192b/24B) */ 2044 struct hwrm_func_clr_stats_input { 2045 __le16 req_type; 2046 __le16 cmpl_ring; 2047 __le16 seq_id; 2048 __le16 target_id; 2049 __le64 resp_addr; 2050 __le16 fid; 2051 u8 unused_0[6]; 2052 }; 2053 2054 /* hwrm_func_clr_stats_output (size:128b/16B) */ 2055 struct hwrm_func_clr_stats_output { 2056 __le16 error_code; 2057 __le16 req_type; 2058 __le16 seq_id; 2059 __le16 resp_len; 2060 u8 unused_0[7]; 2061 u8 valid; 2062 }; 2063 2064 /* hwrm_func_vf_resc_free_input (size:192b/24B) */ 2065 struct hwrm_func_vf_resc_free_input { 2066 __le16 req_type; 2067 __le16 cmpl_ring; 2068 __le16 seq_id; 2069 __le16 target_id; 2070 __le64 resp_addr; 2071 __le16 vf_id; 2072 u8 unused_0[6]; 2073 }; 2074 2075 /* hwrm_func_vf_resc_free_output (size:128b/16B) */ 2076 struct hwrm_func_vf_resc_free_output { 2077 __le16 error_code; 2078 __le16 req_type; 2079 __le16 seq_id; 2080 __le16 resp_len; 2081 u8 unused_0[7]; 2082 u8 valid; 2083 }; 2084 2085 /* hwrm_func_drv_rgtr_input (size:896b/112B) */ 2086 struct hwrm_func_drv_rgtr_input { 2087 __le16 req_type; 2088 __le16 cmpl_ring; 2089 __le16 seq_id; 2090 __le16 target_id; 2091 __le64 resp_addr; 2092 __le32 flags; 2093 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 2094 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 2095 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 2096 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 2097 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 2098 #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL 2099 #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL 2100 #define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT 0x80UL 2101 #define FUNC_DRV_RGTR_REQ_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT 0x100UL 2102 __le32 enables; 2103 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 2104 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 2105 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 2106 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 2107 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 2108 __le16 os_type; 2109 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 2110 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 2111 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 2112 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 2113 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 2114 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 2115 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 2116 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 2117 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 2118 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 2119 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 2120 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 2121 u8 ver_maj_8b; 2122 u8 ver_min_8b; 2123 u8 ver_upd_8b; 2124 u8 unused_0[3]; 2125 __le32 timestamp; 2126 u8 unused_1[4]; 2127 __le32 vf_req_fwd[8]; 2128 __le32 async_event_fwd[8]; 2129 __le16 ver_maj; 2130 __le16 ver_min; 2131 __le16 ver_upd; 2132 __le16 ver_patch; 2133 }; 2134 2135 /* hwrm_func_drv_rgtr_output (size:128b/16B) */ 2136 struct hwrm_func_drv_rgtr_output { 2137 __le16 error_code; 2138 __le16 req_type; 2139 __le16 seq_id; 2140 __le16 resp_len; 2141 __le32 flags; 2142 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 2143 u8 unused_0[3]; 2144 u8 valid; 2145 }; 2146 2147 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 2148 struct hwrm_func_drv_unrgtr_input { 2149 __le16 req_type; 2150 __le16 cmpl_ring; 2151 __le16 seq_id; 2152 __le16 target_id; 2153 __le64 resp_addr; 2154 __le32 flags; 2155 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 2156 u8 unused_0[4]; 2157 }; 2158 2159 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 2160 struct hwrm_func_drv_unrgtr_output { 2161 __le16 error_code; 2162 __le16 req_type; 2163 __le16 seq_id; 2164 __le16 resp_len; 2165 u8 unused_0[7]; 2166 u8 valid; 2167 }; 2168 2169 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 2170 struct hwrm_func_buf_rgtr_input { 2171 __le16 req_type; 2172 __le16 cmpl_ring; 2173 __le16 seq_id; 2174 __le16 target_id; 2175 __le64 resp_addr; 2176 __le32 enables; 2177 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 2178 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 2179 __le16 vf_id; 2180 __le16 req_buf_num_pages; 2181 __le16 req_buf_page_size; 2182 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 2183 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 2184 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 2185 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 2186 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 2187 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 2188 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 2189 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 2190 __le16 req_buf_len; 2191 __le16 resp_buf_len; 2192 u8 unused_0[2]; 2193 __le64 req_buf_page_addr0; 2194 __le64 req_buf_page_addr1; 2195 __le64 req_buf_page_addr2; 2196 __le64 req_buf_page_addr3; 2197 __le64 req_buf_page_addr4; 2198 __le64 req_buf_page_addr5; 2199 __le64 req_buf_page_addr6; 2200 __le64 req_buf_page_addr7; 2201 __le64 req_buf_page_addr8; 2202 __le64 req_buf_page_addr9; 2203 __le64 error_buf_addr; 2204 __le64 resp_buf_addr; 2205 }; 2206 2207 /* hwrm_func_buf_rgtr_output (size:128b/16B) */ 2208 struct hwrm_func_buf_rgtr_output { 2209 __le16 error_code; 2210 __le16 req_type; 2211 __le16 seq_id; 2212 __le16 resp_len; 2213 u8 unused_0[7]; 2214 u8 valid; 2215 }; 2216 2217 /* hwrm_func_drv_qver_input (size:192b/24B) */ 2218 struct hwrm_func_drv_qver_input { 2219 __le16 req_type; 2220 __le16 cmpl_ring; 2221 __le16 seq_id; 2222 __le16 target_id; 2223 __le64 resp_addr; 2224 __le32 reserved; 2225 __le16 fid; 2226 u8 unused_0[2]; 2227 }; 2228 2229 /* hwrm_func_drv_qver_output (size:256b/32B) */ 2230 struct hwrm_func_drv_qver_output { 2231 __le16 error_code; 2232 __le16 req_type; 2233 __le16 seq_id; 2234 __le16 resp_len; 2235 __le16 os_type; 2236 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 2237 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 2238 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 2239 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 2240 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 2241 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 2242 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 2243 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 2244 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 2245 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 2246 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 2247 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 2248 u8 ver_maj_8b; 2249 u8 ver_min_8b; 2250 u8 ver_upd_8b; 2251 u8 unused_0[3]; 2252 __le16 ver_maj; 2253 __le16 ver_min; 2254 __le16 ver_upd; 2255 __le16 ver_patch; 2256 u8 unused_1[7]; 2257 u8 valid; 2258 }; 2259 2260 /* hwrm_func_resource_qcaps_input (size:192b/24B) */ 2261 struct hwrm_func_resource_qcaps_input { 2262 __le16 req_type; 2263 __le16 cmpl_ring; 2264 __le16 seq_id; 2265 __le16 target_id; 2266 __le64 resp_addr; 2267 __le16 fid; 2268 u8 unused_0[6]; 2269 }; 2270 2271 /* hwrm_func_resource_qcaps_output (size:448b/56B) */ 2272 struct hwrm_func_resource_qcaps_output { 2273 __le16 error_code; 2274 __le16 req_type; 2275 __le16 seq_id; 2276 __le16 resp_len; 2277 __le16 max_vfs; 2278 __le16 max_msix; 2279 __le16 vf_reservation_strategy; 2280 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 2281 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 2282 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 2283 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 2284 __le16 min_rsscos_ctx; 2285 __le16 max_rsscos_ctx; 2286 __le16 min_cmpl_rings; 2287 __le16 max_cmpl_rings; 2288 __le16 min_tx_rings; 2289 __le16 max_tx_rings; 2290 __le16 min_rx_rings; 2291 __le16 max_rx_rings; 2292 __le16 min_l2_ctxs; 2293 __le16 max_l2_ctxs; 2294 __le16 min_vnics; 2295 __le16 max_vnics; 2296 __le16 min_stat_ctx; 2297 __le16 max_stat_ctx; 2298 __le16 min_hw_ring_grps; 2299 __le16 max_hw_ring_grps; 2300 __le16 max_tx_scheduler_inputs; 2301 __le16 flags; 2302 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 2303 u8 unused_0[5]; 2304 u8 valid; 2305 }; 2306 2307 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ 2308 struct hwrm_func_vf_resource_cfg_input { 2309 __le16 req_type; 2310 __le16 cmpl_ring; 2311 __le16 seq_id; 2312 __le16 target_id; 2313 __le64 resp_addr; 2314 __le16 vf_id; 2315 __le16 max_msix; 2316 __le16 min_rsscos_ctx; 2317 __le16 max_rsscos_ctx; 2318 __le16 min_cmpl_rings; 2319 __le16 max_cmpl_rings; 2320 __le16 min_tx_rings; 2321 __le16 max_tx_rings; 2322 __le16 min_rx_rings; 2323 __le16 max_rx_rings; 2324 __le16 min_l2_ctxs; 2325 __le16 max_l2_ctxs; 2326 __le16 min_vnics; 2327 __le16 max_vnics; 2328 __le16 min_stat_ctx; 2329 __le16 max_stat_ctx; 2330 __le16 min_hw_ring_grps; 2331 __le16 max_hw_ring_grps; 2332 __le16 flags; 2333 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 2334 u8 unused_0[2]; 2335 }; 2336 2337 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ 2338 struct hwrm_func_vf_resource_cfg_output { 2339 __le16 error_code; 2340 __le16 req_type; 2341 __le16 seq_id; 2342 __le16 resp_len; 2343 __le16 reserved_rsscos_ctx; 2344 __le16 reserved_cmpl_rings; 2345 __le16 reserved_tx_rings; 2346 __le16 reserved_rx_rings; 2347 __le16 reserved_l2_ctxs; 2348 __le16 reserved_vnics; 2349 __le16 reserved_stat_ctx; 2350 __le16 reserved_hw_ring_grps; 2351 u8 unused_0[7]; 2352 u8 valid; 2353 }; 2354 2355 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 2356 struct hwrm_func_backing_store_qcaps_input { 2357 __le16 req_type; 2358 __le16 cmpl_ring; 2359 __le16 seq_id; 2360 __le16 target_id; 2361 __le64 resp_addr; 2362 }; 2363 2364 /* hwrm_func_backing_store_qcaps_output (size:832b/104B) */ 2365 struct hwrm_func_backing_store_qcaps_output { 2366 __le16 error_code; 2367 __le16 req_type; 2368 __le16 seq_id; 2369 __le16 resp_len; 2370 __le32 qp_max_entries; 2371 __le16 qp_min_qp1_entries; 2372 __le16 qp_max_l2_entries; 2373 __le16 qp_entry_size; 2374 __le16 srq_max_l2_entries; 2375 __le32 srq_max_entries; 2376 __le16 srq_entry_size; 2377 __le16 cq_max_l2_entries; 2378 __le32 cq_max_entries; 2379 __le16 cq_entry_size; 2380 __le16 vnic_max_vnic_entries; 2381 __le16 vnic_max_ring_table_entries; 2382 __le16 vnic_entry_size; 2383 __le32 stat_max_entries; 2384 __le16 stat_entry_size; 2385 __le16 tqm_entry_size; 2386 __le32 tqm_min_entries_per_ring; 2387 __le32 tqm_max_entries_per_ring; 2388 __le32 mrav_max_entries; 2389 __le16 mrav_entry_size; 2390 __le16 tim_entry_size; 2391 __le32 tim_max_entries; 2392 __le16 mrav_num_entries_units; 2393 u8 tqm_entries_multiple; 2394 u8 ctx_kind_initializer; 2395 __le16 ctx_init_mask; 2396 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_QP 0x1UL 2397 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_SRQ 0x2UL 2398 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_CQ 0x4UL 2399 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_VNIC 0x8UL 2400 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_STAT 0x10UL 2401 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_MRAV 0x20UL 2402 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_TKC 0x40UL 2403 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_RKC 0x80UL 2404 u8 qp_init_offset; 2405 u8 srq_init_offset; 2406 u8 cq_init_offset; 2407 u8 vnic_init_offset; 2408 u8 tqm_fp_rings_count; 2409 u8 stat_init_offset; 2410 u8 mrav_init_offset; 2411 u8 tqm_fp_rings_count_ext; 2412 u8 tkc_init_offset; 2413 u8 rkc_init_offset; 2414 __le16 tkc_entry_size; 2415 __le16 rkc_entry_size; 2416 __le32 tkc_max_entries; 2417 __le32 rkc_max_entries; 2418 u8 rsvd[7]; 2419 u8 valid; 2420 }; 2421 2422 /* tqm_fp_ring_cfg (size:128b/16B) */ 2423 struct tqm_fp_ring_cfg { 2424 u8 tqm_ring_pg_size_tqm_ring_lvl; 2425 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK 0xfUL 2426 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0 2427 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 0x0UL 2428 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 0x1UL 2429 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 0x2UL 2430 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 2431 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK 0xf0UL 2432 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4 2433 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2434 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2435 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2436 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2437 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2438 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2439 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G 2440 u8 unused[3]; 2441 __le32 tqm_ring_num_entries; 2442 __le64 tqm_ring_page_dir; 2443 }; 2444 2445 /* hwrm_func_backing_store_cfg_input (size:2688b/336B) */ 2446 struct hwrm_func_backing_store_cfg_input { 2447 __le16 req_type; 2448 __le16 cmpl_ring; 2449 __le16 seq_id; 2450 __le16 target_id; 2451 __le64 resp_addr; 2452 __le32 flags; 2453 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 2454 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL 2455 __le32 enables; 2456 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 2457 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 2458 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 2459 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 2460 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 2461 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 2462 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 2463 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 2464 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 2465 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 2466 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 2467 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 2468 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 2469 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 2470 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 2471 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 2472 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING8 0x10000UL 2473 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING9 0x20000UL 2474 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING10 0x40000UL 2475 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TKC 0x80000UL 2476 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_RKC 0x100000UL 2477 u8 qpc_pg_size_qpc_lvl; 2478 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 2479 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 2480 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 2481 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 2482 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 2483 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 2484 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 2485 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 2486 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 2487 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 2488 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 2489 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 2490 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 2491 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 2492 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 2493 u8 srq_pg_size_srq_lvl; 2494 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 2495 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 2496 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 2497 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 2498 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 2499 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 2500 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 2501 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 2502 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 2503 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 2504 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 2505 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 2506 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 2507 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 2508 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 2509 u8 cq_pg_size_cq_lvl; 2510 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 2511 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 2512 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 2513 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 2514 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 2515 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 2516 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 2517 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 2518 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 2519 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 2520 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 2521 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 2522 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 2523 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 2524 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 2525 u8 vnic_pg_size_vnic_lvl; 2526 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 2527 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 2528 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 2529 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 2530 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 2531 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 2532 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 2533 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 2534 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 2535 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 2536 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 2537 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 2538 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 2539 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 2540 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 2541 u8 stat_pg_size_stat_lvl; 2542 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 2543 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 2544 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 2545 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 2546 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 2547 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 2548 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 2549 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 2550 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 2551 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 2552 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 2553 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 2554 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 2555 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 2556 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 2557 u8 tqm_sp_pg_size_tqm_sp_lvl; 2558 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 2559 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 2560 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 2561 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 2562 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 2563 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 2564 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 2565 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 2566 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 2567 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 2568 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 2569 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 2570 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 2571 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 2572 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 2573 u8 tqm_ring0_pg_size_tqm_ring0_lvl; 2574 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 2575 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 2576 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 2577 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 2578 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 2579 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 2580 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 2581 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 2582 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 2583 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 2584 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 2585 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 2586 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 2587 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 2588 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 2589 u8 tqm_ring1_pg_size_tqm_ring1_lvl; 2590 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 2591 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 2592 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 2593 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 2594 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 2595 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 2596 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 2597 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 2598 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 2599 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 2600 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 2601 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 2602 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 2603 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 2604 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 2605 u8 tqm_ring2_pg_size_tqm_ring2_lvl; 2606 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 2607 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 2608 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 2609 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 2610 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 2611 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 2612 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 2613 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 2614 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 2615 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 2616 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 2617 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 2618 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 2619 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 2620 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 2621 u8 tqm_ring3_pg_size_tqm_ring3_lvl; 2622 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 2623 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 2624 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 2625 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 2626 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 2627 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 2628 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 2629 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 2630 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 2631 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 2632 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 2633 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 2634 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 2635 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 2636 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 2637 u8 tqm_ring4_pg_size_tqm_ring4_lvl; 2638 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 2639 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 2640 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 2641 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 2642 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 2643 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 2644 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 2645 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 2646 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 2647 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 2648 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 2649 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 2650 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 2651 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 2652 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 2653 u8 tqm_ring5_pg_size_tqm_ring5_lvl; 2654 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 2655 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 2656 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 2657 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 2658 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 2659 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 2660 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 2661 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 2662 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 2663 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 2664 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 2665 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 2666 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 2667 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 2668 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 2669 u8 tqm_ring6_pg_size_tqm_ring6_lvl; 2670 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 2671 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 2672 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 2673 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 2674 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 2675 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 2676 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 2677 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 2678 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 2679 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 2680 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 2681 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 2682 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 2683 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 2684 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 2685 u8 tqm_ring7_pg_size_tqm_ring7_lvl; 2686 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 2687 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 2688 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 2689 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 2690 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 2691 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 2692 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 2693 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 2694 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 2695 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 2696 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 2697 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 2698 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 2699 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 2700 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 2701 u8 mrav_pg_size_mrav_lvl; 2702 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 2703 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 2704 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 2705 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL 2706 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 2707 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 2708 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 2709 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 2710 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 2711 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 2712 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 2713 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 2714 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 2715 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 2716 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 2717 u8 tim_pg_size_tim_lvl; 2718 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 2719 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 2720 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 2721 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 2722 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 2723 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 2724 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 2725 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 2726 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 2727 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 2728 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 2729 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 2730 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 2731 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 2732 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 2733 __le64 qpc_page_dir; 2734 __le64 srq_page_dir; 2735 __le64 cq_page_dir; 2736 __le64 vnic_page_dir; 2737 __le64 stat_page_dir; 2738 __le64 tqm_sp_page_dir; 2739 __le64 tqm_ring0_page_dir; 2740 __le64 tqm_ring1_page_dir; 2741 __le64 tqm_ring2_page_dir; 2742 __le64 tqm_ring3_page_dir; 2743 __le64 tqm_ring4_page_dir; 2744 __le64 tqm_ring5_page_dir; 2745 __le64 tqm_ring6_page_dir; 2746 __le64 tqm_ring7_page_dir; 2747 __le64 mrav_page_dir; 2748 __le64 tim_page_dir; 2749 __le32 qp_num_entries; 2750 __le32 srq_num_entries; 2751 __le32 cq_num_entries; 2752 __le32 stat_num_entries; 2753 __le32 tqm_sp_num_entries; 2754 __le32 tqm_ring0_num_entries; 2755 __le32 tqm_ring1_num_entries; 2756 __le32 tqm_ring2_num_entries; 2757 __le32 tqm_ring3_num_entries; 2758 __le32 tqm_ring4_num_entries; 2759 __le32 tqm_ring5_num_entries; 2760 __le32 tqm_ring6_num_entries; 2761 __le32 tqm_ring7_num_entries; 2762 __le32 mrav_num_entries; 2763 __le32 tim_num_entries; 2764 __le16 qp_num_qp1_entries; 2765 __le16 qp_num_l2_entries; 2766 __le16 qp_entry_size; 2767 __le16 srq_num_l2_entries; 2768 __le16 srq_entry_size; 2769 __le16 cq_num_l2_entries; 2770 __le16 cq_entry_size; 2771 __le16 vnic_num_vnic_entries; 2772 __le16 vnic_num_ring_table_entries; 2773 __le16 vnic_entry_size; 2774 __le16 stat_entry_size; 2775 __le16 tqm_entry_size; 2776 __le16 mrav_entry_size; 2777 __le16 tim_entry_size; 2778 u8 tqm_ring8_pg_size_tqm_ring_lvl; 2779 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_MASK 0xfUL 2780 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_SFT 0 2781 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_0 0x0UL 2782 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_1 0x1UL 2783 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 0x2UL 2784 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 2785 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_MASK 0xf0UL 2786 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_SFT 4 2787 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2788 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2789 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2790 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2791 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2792 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2793 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G 2794 u8 ring8_unused[3]; 2795 __le32 tqm_ring8_num_entries; 2796 __le64 tqm_ring8_page_dir; 2797 u8 tqm_ring9_pg_size_tqm_ring_lvl; 2798 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_MASK 0xfUL 2799 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_SFT 0 2800 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_0 0x0UL 2801 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_1 0x1UL 2802 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 0x2UL 2803 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 2804 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_MASK 0xf0UL 2805 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_SFT 4 2806 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2807 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2808 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2809 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2810 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2811 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2812 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G 2813 u8 ring9_unused[3]; 2814 __le32 tqm_ring9_num_entries; 2815 __le64 tqm_ring9_page_dir; 2816 u8 tqm_ring10_pg_size_tqm_ring_lvl; 2817 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_MASK 0xfUL 2818 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_SFT 0 2819 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_0 0x0UL 2820 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_1 0x1UL 2821 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 0x2UL 2822 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 2823 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_MASK 0xf0UL 2824 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_SFT 4 2825 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2826 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2827 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2828 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2829 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2830 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2831 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G 2832 u8 ring10_unused[3]; 2833 __le32 tqm_ring10_num_entries; 2834 __le64 tqm_ring10_page_dir; 2835 __le32 tkc_num_entries; 2836 __le32 rkc_num_entries; 2837 __le64 tkc_page_dir; 2838 __le64 rkc_page_dir; 2839 __le16 tkc_entry_size; 2840 __le16 rkc_entry_size; 2841 u8 tkc_pg_size_tkc_lvl; 2842 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_MASK 0xfUL 2843 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_SFT 0 2844 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_0 0x0UL 2845 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_1 0x1UL 2846 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 0x2UL 2847 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 2848 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_MASK 0xf0UL 2849 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_SFT 4 2850 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_4K (0x0UL << 4) 2851 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8K (0x1UL << 4) 2852 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_64K (0x2UL << 4) 2853 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_2M (0x3UL << 4) 2854 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8M (0x4UL << 4) 2855 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G (0x5UL << 4) 2856 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G 2857 u8 rkc_pg_size_rkc_lvl; 2858 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_MASK 0xfUL 2859 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_SFT 0 2860 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_0 0x0UL 2861 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_1 0x1UL 2862 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 0x2UL 2863 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 2864 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_MASK 0xf0UL 2865 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_SFT 4 2866 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_4K (0x0UL << 4) 2867 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8K (0x1UL << 4) 2868 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_64K (0x2UL << 4) 2869 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_2M (0x3UL << 4) 2870 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8M (0x4UL << 4) 2871 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G (0x5UL << 4) 2872 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G 2873 u8 rsvd[2]; 2874 }; 2875 2876 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 2877 struct hwrm_func_backing_store_cfg_output { 2878 __le16 error_code; 2879 __le16 req_type; 2880 __le16 seq_id; 2881 __le16 resp_len; 2882 u8 unused_0[7]; 2883 u8 valid; 2884 }; 2885 2886 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */ 2887 struct hwrm_error_recovery_qcfg_input { 2888 __le16 req_type; 2889 __le16 cmpl_ring; 2890 __le16 seq_id; 2891 __le16 target_id; 2892 __le64 resp_addr; 2893 u8 unused_0[8]; 2894 }; 2895 2896 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ 2897 struct hwrm_error_recovery_qcfg_output { 2898 __le16 error_code; 2899 __le16 req_type; 2900 __le16 seq_id; 2901 __le16 resp_len; 2902 __le32 flags; 2903 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL 2904 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL 2905 __le32 driver_polling_freq; 2906 __le32 master_func_wait_period; 2907 __le32 normal_func_wait_period; 2908 __le32 master_func_wait_period_after_reset; 2909 __le32 max_bailout_time_after_reset; 2910 __le32 fw_health_status_reg; 2911 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL 2912 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0 2913 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2914 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL 2915 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL 2916 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL 2917 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 2918 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL 2919 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2 2920 __le32 fw_heartbeat_reg; 2921 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL 2922 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0 2923 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2924 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL 2925 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL 2926 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL 2927 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 2928 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL 2929 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2 2930 __le32 fw_reset_cnt_reg; 2931 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL 2932 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0 2933 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2934 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL 2935 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL 2936 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL 2937 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 2938 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL 2939 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2 2940 __le32 reset_inprogress_reg; 2941 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL 2942 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0 2943 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2944 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL 2945 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL 2946 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL 2947 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 2948 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL 2949 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2 2950 __le32 reset_inprogress_reg_mask; 2951 u8 unused_0[3]; 2952 u8 reg_array_cnt; 2953 __le32 reset_reg[16]; 2954 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL 2955 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0 2956 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2957 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL 2958 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL 2959 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL 2960 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 2961 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL 2962 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2 2963 __le32 reset_reg_val[16]; 2964 u8 delay_after_reset[16]; 2965 __le32 err_recovery_cnt_reg; 2966 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL 2967 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0 2968 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2969 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL 2970 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL 2971 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL 2972 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 2973 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL 2974 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2 2975 u8 unused_1[3]; 2976 u8 valid; 2977 }; 2978 2979 /* hwrm_func_echo_response_input (size:192b/24B) */ 2980 struct hwrm_func_echo_response_input { 2981 __le16 req_type; 2982 __le16 cmpl_ring; 2983 __le16 seq_id; 2984 __le16 target_id; 2985 __le64 resp_addr; 2986 __le32 event_data1; 2987 __le32 event_data2; 2988 }; 2989 2990 /* hwrm_func_echo_response_output (size:128b/16B) */ 2991 struct hwrm_func_echo_response_output { 2992 __le16 error_code; 2993 __le16 req_type; 2994 __le16 seq_id; 2995 __le16 resp_len; 2996 u8 unused_0[7]; 2997 u8 valid; 2998 }; 2999 3000 /* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */ 3001 struct hwrm_func_ptp_pin_qcfg_input { 3002 __le16 req_type; 3003 __le16 cmpl_ring; 3004 __le16 seq_id; 3005 __le16 target_id; 3006 __le64 resp_addr; 3007 u8 unused_0[8]; 3008 }; 3009 3010 /* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */ 3011 struct hwrm_func_ptp_pin_qcfg_output { 3012 __le16 error_code; 3013 __le16 req_type; 3014 __le16 seq_id; 3015 __le16 resp_len; 3016 u8 num_pins; 3017 u8 state; 3018 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN0_ENABLED 0x1UL 3019 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN1_ENABLED 0x2UL 3020 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN2_ENABLED 0x4UL 3021 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN3_ENABLED 0x8UL 3022 u8 pin0_usage; 3023 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_NONE 0x0UL 3024 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_IN 0x1UL 3025 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_OUT 0x2UL 3026 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_IN 0x3UL 3027 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 0x4UL 3028 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 3029 u8 pin1_usage; 3030 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_NONE 0x0UL 3031 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_IN 0x1UL 3032 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_OUT 0x2UL 3033 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_IN 0x3UL 3034 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 0x4UL 3035 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 3036 u8 pin2_usage; 3037 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_NONE 0x0UL 3038 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_IN 0x1UL 3039 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_OUT 0x2UL 3040 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_IN 0x3UL 3041 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 0x4UL 3042 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 3043 u8 pin3_usage; 3044 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_NONE 0x0UL 3045 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_IN 0x1UL 3046 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_OUT 0x2UL 3047 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_IN 0x3UL 3048 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 0x4UL 3049 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 3050 u8 unused_0; 3051 u8 valid; 3052 }; 3053 3054 /* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */ 3055 struct hwrm_func_ptp_pin_cfg_input { 3056 __le16 req_type; 3057 __le16 cmpl_ring; 3058 __le16 seq_id; 3059 __le16 target_id; 3060 __le64 resp_addr; 3061 __le32 enables; 3062 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE 0x1UL 3063 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE 0x2UL 3064 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_STATE 0x4UL 3065 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_USAGE 0x8UL 3066 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_STATE 0x10UL 3067 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_USAGE 0x20UL 3068 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_STATE 0x40UL 3069 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_USAGE 0x80UL 3070 u8 pin0_state; 3071 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_DISABLED 0x0UL 3072 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 0x1UL 3073 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 3074 u8 pin0_usage; 3075 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_NONE 0x0UL 3076 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_IN 0x1UL 3077 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_OUT 0x2UL 3078 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_IN 0x3UL 3079 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 0x4UL 3080 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 3081 u8 pin1_state; 3082 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_DISABLED 0x0UL 3083 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 0x1UL 3084 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 3085 u8 pin1_usage; 3086 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_NONE 0x0UL 3087 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_IN 0x1UL 3088 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_OUT 0x2UL 3089 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_IN 0x3UL 3090 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 0x4UL 3091 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 3092 u8 pin2_state; 3093 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_DISABLED 0x0UL 3094 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 0x1UL 3095 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 3096 u8 pin2_usage; 3097 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_NONE 0x0UL 3098 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_IN 0x1UL 3099 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_OUT 0x2UL 3100 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_IN 0x3UL 3101 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 0x4UL 3102 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 3103 u8 pin3_state; 3104 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_DISABLED 0x0UL 3105 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 0x1UL 3106 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 3107 u8 pin3_usage; 3108 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_NONE 0x0UL 3109 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_IN 0x1UL 3110 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_OUT 0x2UL 3111 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_IN 0x3UL 3112 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 0x4UL 3113 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 3114 u8 unused_0[4]; 3115 }; 3116 3117 /* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */ 3118 struct hwrm_func_ptp_pin_cfg_output { 3119 __le16 error_code; 3120 __le16 req_type; 3121 __le16 seq_id; 3122 __le16 resp_len; 3123 u8 unused_0[7]; 3124 u8 valid; 3125 }; 3126 3127 /* hwrm_func_ptp_cfg_input (size:320b/40B) */ 3128 struct hwrm_func_ptp_cfg_input { 3129 __le16 req_type; 3130 __le16 cmpl_ring; 3131 __le16 seq_id; 3132 __le16 target_id; 3133 __le64 resp_addr; 3134 __le16 enables; 3135 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT 0x1UL 3136 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE 0x2UL 3137 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_PHASE 0x4UL 3138 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD 0x8UL 3139 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP 0x10UL 3140 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE 0x20UL 3141 u8 ptp_pps_event; 3142 #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_INTERNAL 0x1UL 3143 #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_EXTERNAL 0x2UL 3144 u8 ptp_freq_adj_dll_source; 3145 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_NONE 0x0UL 3146 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 0x1UL 3147 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 0x2UL 3148 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 0x3UL 3149 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 0x4UL 3150 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 0x5UL 3151 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 0x6UL 3152 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 0x7UL 3153 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 0x8UL 3154 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 0xffUL 3155 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 3156 u8 ptp_freq_adj_dll_phase; 3157 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_NONE 0x0UL 3158 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_4K 0x1UL 3159 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_8K 0x2UL 3160 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M 0x3UL 3161 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M 3162 u8 unused_0[3]; 3163 __le32 ptp_freq_adj_ext_period; 3164 __le32 ptp_freq_adj_ext_up; 3165 __le32 ptp_freq_adj_ext_phase_lower; 3166 __le32 ptp_freq_adj_ext_phase_upper; 3167 }; 3168 3169 /* hwrm_func_ptp_cfg_output (size:128b/16B) */ 3170 struct hwrm_func_ptp_cfg_output { 3171 __le16 error_code; 3172 __le16 req_type; 3173 __le16 seq_id; 3174 __le16 resp_len; 3175 u8 unused_0[7]; 3176 u8 valid; 3177 }; 3178 3179 /* hwrm_func_ptp_ts_query_input (size:192b/24B) */ 3180 struct hwrm_func_ptp_ts_query_input { 3181 __le16 req_type; 3182 __le16 cmpl_ring; 3183 __le16 seq_id; 3184 __le16 target_id; 3185 __le64 resp_addr; 3186 __le32 flags; 3187 #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PPS_TIME 0x1UL 3188 #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PTM_TIME 0x2UL 3189 u8 unused_0[4]; 3190 }; 3191 3192 /* hwrm_func_ptp_ts_query_output (size:320b/40B) */ 3193 struct hwrm_func_ptp_ts_query_output { 3194 __le16 error_code; 3195 __le16 req_type; 3196 __le16 seq_id; 3197 __le16 resp_len; 3198 __le64 pps_event_ts; 3199 __le64 ptm_res_local_ts; 3200 __le64 ptm_pmstr_ts; 3201 __le32 ptm_mstr_prop_dly; 3202 u8 unused_0[3]; 3203 u8 valid; 3204 }; 3205 3206 /* hwrm_func_drv_if_change_input (size:192b/24B) */ 3207 struct hwrm_func_drv_if_change_input { 3208 __le16 req_type; 3209 __le16 cmpl_ring; 3210 __le16 seq_id; 3211 __le16 target_id; 3212 __le64 resp_addr; 3213 __le32 flags; 3214 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 3215 __le32 unused; 3216 }; 3217 3218 /* hwrm_func_drv_if_change_output (size:128b/16B) */ 3219 struct hwrm_func_drv_if_change_output { 3220 __le16 error_code; 3221 __le16 req_type; 3222 __le16 seq_id; 3223 __le16 resp_len; 3224 __le32 flags; 3225 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 3226 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 3227 u8 unused_0[3]; 3228 u8 valid; 3229 }; 3230 3231 /* hwrm_port_phy_cfg_input (size:448b/56B) */ 3232 struct hwrm_port_phy_cfg_input { 3233 __le16 req_type; 3234 __le16 cmpl_ring; 3235 __le16 seq_id; 3236 __le16 target_id; 3237 __le64 resp_addr; 3238 __le32 flags; 3239 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 3240 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 3241 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 3242 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 3243 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 3244 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 3245 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 3246 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 3247 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 3248 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 3249 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 3250 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 3251 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 3252 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 3253 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 3254 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL 3255 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL 3256 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL 3257 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL 3258 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL 3259 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL 3260 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL 3261 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL 3262 __le32 enables; 3263 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 3264 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 3265 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 3266 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 3267 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 3268 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 3269 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 3270 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 3271 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 3272 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 3273 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 3274 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL 3275 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL 3276 __le16 port_id; 3277 __le16 force_link_speed; 3278 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 3279 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 3280 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 3281 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 3282 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 3283 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 3284 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 3285 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 3286 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 3287 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 3288 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 3289 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 3290 u8 auto_mode; 3291 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 3292 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 3293 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 3294 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 3295 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 3296 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 3297 u8 auto_duplex; 3298 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 3299 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 3300 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 3301 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 3302 u8 auto_pause; 3303 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 3304 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 3305 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 3306 u8 unused_0; 3307 __le16 auto_link_speed; 3308 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 3309 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 3310 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 3311 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 3312 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 3313 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 3314 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 3315 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 3316 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 3317 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 3318 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 3319 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 3320 __le16 auto_link_speed_mask; 3321 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 3322 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 3323 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 3324 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 3325 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 3326 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 3327 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 3328 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 3329 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 3330 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 3331 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 3332 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 3333 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 3334 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 3335 u8 wirespeed; 3336 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 3337 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 3338 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 3339 u8 lpbk; 3340 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 3341 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 3342 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 3343 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 3344 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 3345 u8 force_pause; 3346 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 3347 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 3348 u8 unused_1; 3349 __le32 preemphasis; 3350 __le16 eee_link_speed_mask; 3351 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 3352 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 3353 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 3354 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 3355 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 3356 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 3357 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 3358 __le16 force_pam4_link_speed; 3359 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 3360 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 3361 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 3362 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 3363 __le32 tx_lpi_timer; 3364 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 3365 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 3366 __le16 auto_link_pam4_speed_mask; 3367 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL 3368 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL 3369 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL 3370 u8 unused_2[2]; 3371 }; 3372 3373 /* hwrm_port_phy_cfg_output (size:128b/16B) */ 3374 struct hwrm_port_phy_cfg_output { 3375 __le16 error_code; 3376 __le16 req_type; 3377 __le16 seq_id; 3378 __le16 resp_len; 3379 u8 unused_0[7]; 3380 u8 valid; 3381 }; 3382 3383 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 3384 struct hwrm_port_phy_cfg_cmd_err { 3385 u8 code; 3386 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 3387 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 3388 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 3389 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 3390 u8 unused_0[7]; 3391 }; 3392 3393 /* hwrm_port_phy_qcfg_input (size:192b/24B) */ 3394 struct hwrm_port_phy_qcfg_input { 3395 __le16 req_type; 3396 __le16 cmpl_ring; 3397 __le16 seq_id; 3398 __le16 target_id; 3399 __le64 resp_addr; 3400 __le16 port_id; 3401 u8 unused_0[6]; 3402 }; 3403 3404 /* hwrm_port_phy_qcfg_output (size:768b/96B) */ 3405 struct hwrm_port_phy_qcfg_output { 3406 __le16 error_code; 3407 __le16 req_type; 3408 __le16 seq_id; 3409 __le16 resp_len; 3410 u8 link; 3411 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 3412 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 3413 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 3414 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 3415 u8 active_fec_signal_mode; 3416 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL 3417 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0 3418 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL 3419 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL 3420 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 3421 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL 3422 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4 3423 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4) 3424 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4) 3425 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4) 3426 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4) 3427 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4) 3428 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4) 3429 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4) 3430 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE 3431 __le16 link_speed; 3432 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 3433 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 3434 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 3435 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 3436 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 3437 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 3438 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 3439 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 3440 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 3441 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 3442 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 3443 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 3444 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 3445 u8 duplex_cfg; 3446 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 3447 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 3448 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 3449 u8 pause; 3450 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 3451 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 3452 __le16 support_speeds; 3453 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 3454 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 3455 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 3456 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 3457 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 3458 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 3459 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 3460 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 3461 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 3462 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 3463 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 3464 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 3465 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 3466 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 3467 __le16 force_link_speed; 3468 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 3469 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 3470 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 3471 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 3472 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 3473 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 3474 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 3475 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 3476 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 3477 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 3478 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 3479 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 3480 u8 auto_mode; 3481 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 3482 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 3483 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 3484 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 3485 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 3486 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 3487 u8 auto_pause; 3488 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 3489 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 3490 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 3491 __le16 auto_link_speed; 3492 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 3493 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 3494 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 3495 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 3496 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 3497 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 3498 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 3499 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 3500 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 3501 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 3502 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 3503 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 3504 __le16 auto_link_speed_mask; 3505 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 3506 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 3507 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 3508 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 3509 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 3510 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 3511 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 3512 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 3513 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 3514 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 3515 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 3516 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 3517 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 3518 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 3519 u8 wirespeed; 3520 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 3521 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 3522 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 3523 u8 lpbk; 3524 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 3525 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 3526 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 3527 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 3528 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 3529 u8 force_pause; 3530 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 3531 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 3532 u8 module_status; 3533 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 3534 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 3535 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 3536 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 3537 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 3538 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL 3539 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 3540 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 3541 __le32 preemphasis; 3542 u8 phy_maj; 3543 u8 phy_min; 3544 u8 phy_bld; 3545 u8 phy_type; 3546 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 3547 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 3548 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 3549 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 3550 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 3551 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 3552 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 3553 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 3554 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 3555 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 3556 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 3557 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 3558 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 3559 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 3560 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 3561 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 3562 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 3563 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 3564 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 3565 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 3566 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 3567 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 3568 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 3569 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 3570 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 3571 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 3572 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 3573 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 3574 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 3575 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 3576 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 3577 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 3578 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 3579 u8 media_type; 3580 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 3581 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 3582 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 3583 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 3584 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 3585 u8 xcvr_pkg_type; 3586 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 3587 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 3588 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 3589 u8 eee_config_phy_addr; 3590 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 3591 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 3592 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 3593 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 3594 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 3595 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 3596 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 3597 u8 parallel_detect; 3598 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 3599 __le16 link_partner_adv_speeds; 3600 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 3601 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 3602 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 3603 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 3604 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 3605 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 3606 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 3607 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 3608 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 3609 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 3610 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 3611 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 3612 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 3613 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 3614 u8 link_partner_adv_auto_mode; 3615 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 3616 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 3617 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 3618 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 3619 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 3620 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 3621 u8 link_partner_adv_pause; 3622 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 3623 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 3624 __le16 adv_eee_link_speed_mask; 3625 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 3626 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 3627 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 3628 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 3629 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 3630 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 3631 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 3632 __le16 link_partner_adv_eee_link_speed_mask; 3633 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 3634 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 3635 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 3636 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 3637 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 3638 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 3639 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 3640 __le32 xcvr_identifier_type_tx_lpi_timer; 3641 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 3642 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 3643 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 3644 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 3645 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 3646 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 3647 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 3648 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 3649 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 3650 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 3651 __le16 fec_cfg; 3652 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 3653 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 3654 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 3655 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 3656 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 3657 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 3658 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 3659 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL 3660 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL 3661 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL 3662 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL 3663 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL 3664 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL 3665 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL 3666 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL 3667 u8 duplex_state; 3668 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 3669 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 3670 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 3671 u8 option_flags; 3672 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 3673 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN 0x2UL 3674 char phy_vendor_name[16]; 3675 char phy_vendor_partnumber[16]; 3676 __le16 support_pam4_speeds; 3677 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL 3678 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL 3679 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL 3680 __le16 force_pam4_link_speed; 3681 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 3682 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 3683 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 3684 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 3685 __le16 auto_pam4_link_speed_mask; 3686 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL 3687 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL 3688 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL 3689 u8 link_partner_pam4_adv_speeds; 3690 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL 3691 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL 3692 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL 3693 u8 valid; 3694 }; 3695 3696 /* hwrm_port_mac_cfg_input (size:384b/48B) */ 3697 struct hwrm_port_mac_cfg_input { 3698 __le16 req_type; 3699 __le16 cmpl_ring; 3700 __le16 seq_id; 3701 __le16 target_id; 3702 __le64 resp_addr; 3703 __le32 flags; 3704 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 3705 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 3706 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 3707 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 3708 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 3709 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 3710 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 3711 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 3712 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 3713 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 3714 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 3715 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 3716 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 3717 #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL 3718 __le32 enables; 3719 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 3720 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 3721 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 3722 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 3723 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 3724 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 3725 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 3726 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 3727 #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL 3728 #define PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE 0x400UL 3729 __le16 port_id; 3730 u8 ipg; 3731 u8 lpbk; 3732 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 3733 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 3734 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 3735 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 3736 u8 vlan_pri2cos_map_pri; 3737 u8 reserved1; 3738 u8 tunnel_pri2cos_map_pri; 3739 u8 dscp2pri_map_pri; 3740 __le16 rx_ts_capture_ptp_msg_type; 3741 __le16 tx_ts_capture_ptp_msg_type; 3742 u8 cos_field_cfg; 3743 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 3744 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 3745 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 3746 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 3747 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 3748 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 3749 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 3750 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 3751 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 3752 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 3753 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 3754 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 3755 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 3756 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 3757 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 3758 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 3759 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 3760 u8 unused_0[3]; 3761 __le32 ptp_freq_adj_ppb; 3762 __le32 ptp_adj_phase; 3763 }; 3764 3765 /* hwrm_port_mac_cfg_output (size:128b/16B) */ 3766 struct hwrm_port_mac_cfg_output { 3767 __le16 error_code; 3768 __le16 req_type; 3769 __le16 seq_id; 3770 __le16 resp_len; 3771 __le16 mru; 3772 __le16 mtu; 3773 u8 ipg; 3774 u8 lpbk; 3775 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 3776 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 3777 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 3778 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 3779 u8 unused_0; 3780 u8 valid; 3781 }; 3782 3783 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 3784 struct hwrm_port_mac_ptp_qcfg_input { 3785 __le16 req_type; 3786 __le16 cmpl_ring; 3787 __le16 seq_id; 3788 __le16 target_id; 3789 __le64 resp_addr; 3790 __le16 port_id; 3791 u8 unused_0[6]; 3792 }; 3793 3794 /* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */ 3795 struct hwrm_port_mac_ptp_qcfg_output { 3796 __le16 error_code; 3797 __le16 req_type; 3798 __le16 seq_id; 3799 __le16 resp_len; 3800 u8 flags; 3801 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 3802 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL 3803 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL 3804 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK 0x10UL 3805 u8 unused_0[3]; 3806 __le32 rx_ts_reg_off_lower; 3807 __le32 rx_ts_reg_off_upper; 3808 __le32 rx_ts_reg_off_seq_id; 3809 __le32 rx_ts_reg_off_src_id_0; 3810 __le32 rx_ts_reg_off_src_id_1; 3811 __le32 rx_ts_reg_off_src_id_2; 3812 __le32 rx_ts_reg_off_domain_id; 3813 __le32 rx_ts_reg_off_fifo; 3814 __le32 rx_ts_reg_off_fifo_adv; 3815 __le32 rx_ts_reg_off_granularity; 3816 __le32 tx_ts_reg_off_lower; 3817 __le32 tx_ts_reg_off_upper; 3818 __le32 tx_ts_reg_off_seq_id; 3819 __le32 tx_ts_reg_off_fifo; 3820 __le32 tx_ts_reg_off_granularity; 3821 __le32 ts_ref_clock_reg_lower; 3822 __le32 ts_ref_clock_reg_upper; 3823 u8 unused_1[7]; 3824 u8 valid; 3825 }; 3826 3827 /* tx_port_stats (size:3264b/408B) */ 3828 struct tx_port_stats { 3829 __le64 tx_64b_frames; 3830 __le64 tx_65b_127b_frames; 3831 __le64 tx_128b_255b_frames; 3832 __le64 tx_256b_511b_frames; 3833 __le64 tx_512b_1023b_frames; 3834 __le64 tx_1024b_1518b_frames; 3835 __le64 tx_good_vlan_frames; 3836 __le64 tx_1519b_2047b_frames; 3837 __le64 tx_2048b_4095b_frames; 3838 __le64 tx_4096b_9216b_frames; 3839 __le64 tx_9217b_16383b_frames; 3840 __le64 tx_good_frames; 3841 __le64 tx_total_frames; 3842 __le64 tx_ucast_frames; 3843 __le64 tx_mcast_frames; 3844 __le64 tx_bcast_frames; 3845 __le64 tx_pause_frames; 3846 __le64 tx_pfc_frames; 3847 __le64 tx_jabber_frames; 3848 __le64 tx_fcs_err_frames; 3849 __le64 tx_control_frames; 3850 __le64 tx_oversz_frames; 3851 __le64 tx_single_dfrl_frames; 3852 __le64 tx_multi_dfrl_frames; 3853 __le64 tx_single_coll_frames; 3854 __le64 tx_multi_coll_frames; 3855 __le64 tx_late_coll_frames; 3856 __le64 tx_excessive_coll_frames; 3857 __le64 tx_frag_frames; 3858 __le64 tx_err; 3859 __le64 tx_tagged_frames; 3860 __le64 tx_dbl_tagged_frames; 3861 __le64 tx_runt_frames; 3862 __le64 tx_fifo_underruns; 3863 __le64 tx_pfc_ena_frames_pri0; 3864 __le64 tx_pfc_ena_frames_pri1; 3865 __le64 tx_pfc_ena_frames_pri2; 3866 __le64 tx_pfc_ena_frames_pri3; 3867 __le64 tx_pfc_ena_frames_pri4; 3868 __le64 tx_pfc_ena_frames_pri5; 3869 __le64 tx_pfc_ena_frames_pri6; 3870 __le64 tx_pfc_ena_frames_pri7; 3871 __le64 tx_eee_lpi_events; 3872 __le64 tx_eee_lpi_duration; 3873 __le64 tx_llfc_logical_msgs; 3874 __le64 tx_hcfc_msgs; 3875 __le64 tx_total_collisions; 3876 __le64 tx_bytes; 3877 __le64 tx_xthol_frames; 3878 __le64 tx_stat_discard; 3879 __le64 tx_stat_error; 3880 }; 3881 3882 /* rx_port_stats (size:4224b/528B) */ 3883 struct rx_port_stats { 3884 __le64 rx_64b_frames; 3885 __le64 rx_65b_127b_frames; 3886 __le64 rx_128b_255b_frames; 3887 __le64 rx_256b_511b_frames; 3888 __le64 rx_512b_1023b_frames; 3889 __le64 rx_1024b_1518b_frames; 3890 __le64 rx_good_vlan_frames; 3891 __le64 rx_1519b_2047b_frames; 3892 __le64 rx_2048b_4095b_frames; 3893 __le64 rx_4096b_9216b_frames; 3894 __le64 rx_9217b_16383b_frames; 3895 __le64 rx_total_frames; 3896 __le64 rx_ucast_frames; 3897 __le64 rx_mcast_frames; 3898 __le64 rx_bcast_frames; 3899 __le64 rx_fcs_err_frames; 3900 __le64 rx_ctrl_frames; 3901 __le64 rx_pause_frames; 3902 __le64 rx_pfc_frames; 3903 __le64 rx_unsupported_opcode_frames; 3904 __le64 rx_unsupported_da_pausepfc_frames; 3905 __le64 rx_wrong_sa_frames; 3906 __le64 rx_align_err_frames; 3907 __le64 rx_oor_len_frames; 3908 __le64 rx_code_err_frames; 3909 __le64 rx_false_carrier_frames; 3910 __le64 rx_ovrsz_frames; 3911 __le64 rx_jbr_frames; 3912 __le64 rx_mtu_err_frames; 3913 __le64 rx_match_crc_frames; 3914 __le64 rx_promiscuous_frames; 3915 __le64 rx_tagged_frames; 3916 __le64 rx_double_tagged_frames; 3917 __le64 rx_trunc_frames; 3918 __le64 rx_good_frames; 3919 __le64 rx_pfc_xon2xoff_frames_pri0; 3920 __le64 rx_pfc_xon2xoff_frames_pri1; 3921 __le64 rx_pfc_xon2xoff_frames_pri2; 3922 __le64 rx_pfc_xon2xoff_frames_pri3; 3923 __le64 rx_pfc_xon2xoff_frames_pri4; 3924 __le64 rx_pfc_xon2xoff_frames_pri5; 3925 __le64 rx_pfc_xon2xoff_frames_pri6; 3926 __le64 rx_pfc_xon2xoff_frames_pri7; 3927 __le64 rx_pfc_ena_frames_pri0; 3928 __le64 rx_pfc_ena_frames_pri1; 3929 __le64 rx_pfc_ena_frames_pri2; 3930 __le64 rx_pfc_ena_frames_pri3; 3931 __le64 rx_pfc_ena_frames_pri4; 3932 __le64 rx_pfc_ena_frames_pri5; 3933 __le64 rx_pfc_ena_frames_pri6; 3934 __le64 rx_pfc_ena_frames_pri7; 3935 __le64 rx_sch_crc_err_frames; 3936 __le64 rx_undrsz_frames; 3937 __le64 rx_frag_frames; 3938 __le64 rx_eee_lpi_events; 3939 __le64 rx_eee_lpi_duration; 3940 __le64 rx_llfc_physical_msgs; 3941 __le64 rx_llfc_logical_msgs; 3942 __le64 rx_llfc_msgs_with_crc_err; 3943 __le64 rx_hcfc_msgs; 3944 __le64 rx_hcfc_msgs_with_crc_err; 3945 __le64 rx_bytes; 3946 __le64 rx_runt_bytes; 3947 __le64 rx_runt_frames; 3948 __le64 rx_stat_discard; 3949 __le64 rx_stat_err; 3950 }; 3951 3952 /* hwrm_port_qstats_input (size:320b/40B) */ 3953 struct hwrm_port_qstats_input { 3954 __le16 req_type; 3955 __le16 cmpl_ring; 3956 __le16 seq_id; 3957 __le16 target_id; 3958 __le64 resp_addr; 3959 __le16 port_id; 3960 u8 flags; 3961 #define PORT_QSTATS_REQ_FLAGS_UNUSED 0x0UL 3962 #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 3963 #define PORT_QSTATS_REQ_FLAGS_LAST PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 3964 u8 unused_0[5]; 3965 __le64 tx_stat_host_addr; 3966 __le64 rx_stat_host_addr; 3967 }; 3968 3969 /* hwrm_port_qstats_output (size:128b/16B) */ 3970 struct hwrm_port_qstats_output { 3971 __le16 error_code; 3972 __le16 req_type; 3973 __le16 seq_id; 3974 __le16 resp_len; 3975 __le16 tx_stat_size; 3976 __le16 rx_stat_size; 3977 u8 unused_0[3]; 3978 u8 valid; 3979 }; 3980 3981 /* tx_port_stats_ext (size:2048b/256B) */ 3982 struct tx_port_stats_ext { 3983 __le64 tx_bytes_cos0; 3984 __le64 tx_bytes_cos1; 3985 __le64 tx_bytes_cos2; 3986 __le64 tx_bytes_cos3; 3987 __le64 tx_bytes_cos4; 3988 __le64 tx_bytes_cos5; 3989 __le64 tx_bytes_cos6; 3990 __le64 tx_bytes_cos7; 3991 __le64 tx_packets_cos0; 3992 __le64 tx_packets_cos1; 3993 __le64 tx_packets_cos2; 3994 __le64 tx_packets_cos3; 3995 __le64 tx_packets_cos4; 3996 __le64 tx_packets_cos5; 3997 __le64 tx_packets_cos6; 3998 __le64 tx_packets_cos7; 3999 __le64 pfc_pri0_tx_duration_us; 4000 __le64 pfc_pri0_tx_transitions; 4001 __le64 pfc_pri1_tx_duration_us; 4002 __le64 pfc_pri1_tx_transitions; 4003 __le64 pfc_pri2_tx_duration_us; 4004 __le64 pfc_pri2_tx_transitions; 4005 __le64 pfc_pri3_tx_duration_us; 4006 __le64 pfc_pri3_tx_transitions; 4007 __le64 pfc_pri4_tx_duration_us; 4008 __le64 pfc_pri4_tx_transitions; 4009 __le64 pfc_pri5_tx_duration_us; 4010 __le64 pfc_pri5_tx_transitions; 4011 __le64 pfc_pri6_tx_duration_us; 4012 __le64 pfc_pri6_tx_transitions; 4013 __le64 pfc_pri7_tx_duration_us; 4014 __le64 pfc_pri7_tx_transitions; 4015 }; 4016 4017 /* rx_port_stats_ext (size:3648b/456B) */ 4018 struct rx_port_stats_ext { 4019 __le64 link_down_events; 4020 __le64 continuous_pause_events; 4021 __le64 resume_pause_events; 4022 __le64 continuous_roce_pause_events; 4023 __le64 resume_roce_pause_events; 4024 __le64 rx_bytes_cos0; 4025 __le64 rx_bytes_cos1; 4026 __le64 rx_bytes_cos2; 4027 __le64 rx_bytes_cos3; 4028 __le64 rx_bytes_cos4; 4029 __le64 rx_bytes_cos5; 4030 __le64 rx_bytes_cos6; 4031 __le64 rx_bytes_cos7; 4032 __le64 rx_packets_cos0; 4033 __le64 rx_packets_cos1; 4034 __le64 rx_packets_cos2; 4035 __le64 rx_packets_cos3; 4036 __le64 rx_packets_cos4; 4037 __le64 rx_packets_cos5; 4038 __le64 rx_packets_cos6; 4039 __le64 rx_packets_cos7; 4040 __le64 pfc_pri0_rx_duration_us; 4041 __le64 pfc_pri0_rx_transitions; 4042 __le64 pfc_pri1_rx_duration_us; 4043 __le64 pfc_pri1_rx_transitions; 4044 __le64 pfc_pri2_rx_duration_us; 4045 __le64 pfc_pri2_rx_transitions; 4046 __le64 pfc_pri3_rx_duration_us; 4047 __le64 pfc_pri3_rx_transitions; 4048 __le64 pfc_pri4_rx_duration_us; 4049 __le64 pfc_pri4_rx_transitions; 4050 __le64 pfc_pri5_rx_duration_us; 4051 __le64 pfc_pri5_rx_transitions; 4052 __le64 pfc_pri6_rx_duration_us; 4053 __le64 pfc_pri6_rx_transitions; 4054 __le64 pfc_pri7_rx_duration_us; 4055 __le64 pfc_pri7_rx_transitions; 4056 __le64 rx_bits; 4057 __le64 rx_buffer_passed_threshold; 4058 __le64 rx_pcs_symbol_err; 4059 __le64 rx_corrected_bits; 4060 __le64 rx_discard_bytes_cos0; 4061 __le64 rx_discard_bytes_cos1; 4062 __le64 rx_discard_bytes_cos2; 4063 __le64 rx_discard_bytes_cos3; 4064 __le64 rx_discard_bytes_cos4; 4065 __le64 rx_discard_bytes_cos5; 4066 __le64 rx_discard_bytes_cos6; 4067 __le64 rx_discard_bytes_cos7; 4068 __le64 rx_discard_packets_cos0; 4069 __le64 rx_discard_packets_cos1; 4070 __le64 rx_discard_packets_cos2; 4071 __le64 rx_discard_packets_cos3; 4072 __le64 rx_discard_packets_cos4; 4073 __le64 rx_discard_packets_cos5; 4074 __le64 rx_discard_packets_cos6; 4075 __le64 rx_discard_packets_cos7; 4076 }; 4077 4078 /* hwrm_port_qstats_ext_input (size:320b/40B) */ 4079 struct hwrm_port_qstats_ext_input { 4080 __le16 req_type; 4081 __le16 cmpl_ring; 4082 __le16 seq_id; 4083 __le16 target_id; 4084 __le64 resp_addr; 4085 __le16 port_id; 4086 __le16 tx_stat_size; 4087 __le16 rx_stat_size; 4088 u8 flags; 4089 #define PORT_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 4090 #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL 4091 #define PORT_QSTATS_EXT_REQ_FLAGS_LAST PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 4092 u8 unused_0; 4093 __le64 tx_stat_host_addr; 4094 __le64 rx_stat_host_addr; 4095 }; 4096 4097 /* hwrm_port_qstats_ext_output (size:128b/16B) */ 4098 struct hwrm_port_qstats_ext_output { 4099 __le16 error_code; 4100 __le16 req_type; 4101 __le16 seq_id; 4102 __le16 resp_len; 4103 __le16 tx_stat_size; 4104 __le16 rx_stat_size; 4105 __le16 total_active_cos_queues; 4106 u8 flags; 4107 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 4108 u8 valid; 4109 }; 4110 4111 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */ 4112 struct hwrm_port_lpbk_qstats_input { 4113 __le16 req_type; 4114 __le16 cmpl_ring; 4115 __le16 seq_id; 4116 __le16 target_id; 4117 __le64 resp_addr; 4118 }; 4119 4120 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */ 4121 struct hwrm_port_lpbk_qstats_output { 4122 __le16 error_code; 4123 __le16 req_type; 4124 __le16 seq_id; 4125 __le16 resp_len; 4126 __le64 lpbk_ucast_frames; 4127 __le64 lpbk_mcast_frames; 4128 __le64 lpbk_bcast_frames; 4129 __le64 lpbk_ucast_bytes; 4130 __le64 lpbk_mcast_bytes; 4131 __le64 lpbk_bcast_bytes; 4132 __le64 tx_stat_discard; 4133 __le64 tx_stat_error; 4134 __le64 rx_stat_discard; 4135 __le64 rx_stat_error; 4136 u8 unused_0[7]; 4137 u8 valid; 4138 }; 4139 4140 /* hwrm_port_ecn_qstats_input (size:256b/32B) */ 4141 struct hwrm_port_ecn_qstats_input { 4142 __le16 req_type; 4143 __le16 cmpl_ring; 4144 __le16 seq_id; 4145 __le16 target_id; 4146 __le64 resp_addr; 4147 __le16 port_id; 4148 __le16 ecn_stat_buf_size; 4149 u8 flags; 4150 #define PORT_ECN_QSTATS_REQ_FLAGS_UNUSED 0x0UL 4151 #define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 4152 #define PORT_ECN_QSTATS_REQ_FLAGS_LAST PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 4153 u8 unused_0[3]; 4154 __le64 ecn_stat_host_addr; 4155 }; 4156 4157 /* hwrm_port_ecn_qstats_output (size:128b/16B) */ 4158 struct hwrm_port_ecn_qstats_output { 4159 __le16 error_code; 4160 __le16 req_type; 4161 __le16 seq_id; 4162 __le16 resp_len; 4163 __le16 ecn_stat_buf_size; 4164 u8 mark_en; 4165 u8 unused_0[4]; 4166 u8 valid; 4167 }; 4168 4169 /* port_stats_ecn (size:512b/64B) */ 4170 struct port_stats_ecn { 4171 __le64 mark_cnt_cos0; 4172 __le64 mark_cnt_cos1; 4173 __le64 mark_cnt_cos2; 4174 __le64 mark_cnt_cos3; 4175 __le64 mark_cnt_cos4; 4176 __le64 mark_cnt_cos5; 4177 __le64 mark_cnt_cos6; 4178 __le64 mark_cnt_cos7; 4179 }; 4180 4181 /* hwrm_port_clr_stats_input (size:192b/24B) */ 4182 struct hwrm_port_clr_stats_input { 4183 __le16 req_type; 4184 __le16 cmpl_ring; 4185 __le16 seq_id; 4186 __le16 target_id; 4187 __le64 resp_addr; 4188 __le16 port_id; 4189 u8 flags; 4190 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 4191 u8 unused_0[5]; 4192 }; 4193 4194 /* hwrm_port_clr_stats_output (size:128b/16B) */ 4195 struct hwrm_port_clr_stats_output { 4196 __le16 error_code; 4197 __le16 req_type; 4198 __le16 seq_id; 4199 __le16 resp_len; 4200 u8 unused_0[7]; 4201 u8 valid; 4202 }; 4203 4204 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ 4205 struct hwrm_port_lpbk_clr_stats_input { 4206 __le16 req_type; 4207 __le16 cmpl_ring; 4208 __le16 seq_id; 4209 __le16 target_id; 4210 __le64 resp_addr; 4211 }; 4212 4213 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 4214 struct hwrm_port_lpbk_clr_stats_output { 4215 __le16 error_code; 4216 __le16 req_type; 4217 __le16 seq_id; 4218 __le16 resp_len; 4219 u8 unused_0[7]; 4220 u8 valid; 4221 }; 4222 4223 /* hwrm_port_ts_query_input (size:256b/32B) */ 4224 struct hwrm_port_ts_query_input { 4225 __le16 req_type; 4226 __le16 cmpl_ring; 4227 __le16 seq_id; 4228 __le16 target_id; 4229 __le64 resp_addr; 4230 __le32 flags; 4231 #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL 4232 #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL 4233 #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL 4234 #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX 4235 #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL 4236 __le16 port_id; 4237 u8 unused_0[2]; 4238 __le16 enables; 4239 #define PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT 0x1UL 4240 #define PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID 0x2UL 4241 __le16 ts_req_timeout; 4242 __le32 ptp_seq_id; 4243 }; 4244 4245 /* hwrm_port_ts_query_output (size:192b/24B) */ 4246 struct hwrm_port_ts_query_output { 4247 __le16 error_code; 4248 __le16 req_type; 4249 __le16 seq_id; 4250 __le16 resp_len; 4251 __le64 ptp_msg_ts; 4252 __le16 ptp_msg_seqid; 4253 u8 unused_0[5]; 4254 u8 valid; 4255 }; 4256 4257 /* hwrm_port_phy_qcaps_input (size:192b/24B) */ 4258 struct hwrm_port_phy_qcaps_input { 4259 __le16 req_type; 4260 __le16 cmpl_ring; 4261 __le16 seq_id; 4262 __le16 target_id; 4263 __le64 resp_addr; 4264 __le16 port_id; 4265 u8 unused_0[6]; 4266 }; 4267 4268 /* hwrm_port_phy_qcaps_output (size:256b/32B) */ 4269 struct hwrm_port_phy_qcaps_output { 4270 __le16 error_code; 4271 __le16 req_type; 4272 __le16 seq_id; 4273 __le16 resp_len; 4274 u8 flags; 4275 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 4276 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 4277 #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL 4278 #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL 4279 #define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL 4280 #define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x20UL 4281 #define PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN 0x40UL 4282 #define PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS 0x80UL 4283 u8 port_cnt; 4284 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 4285 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 4286 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 4287 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 4288 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 4289 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4 4290 __le16 supported_speeds_force_mode; 4291 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 4292 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 4293 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 4294 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 4295 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 4296 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 4297 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 4298 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 4299 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 4300 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 4301 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 4302 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 4303 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 4304 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 4305 __le16 supported_speeds_auto_mode; 4306 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 4307 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 4308 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 4309 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 4310 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 4311 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 4312 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 4313 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 4314 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 4315 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 4316 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 4317 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 4318 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 4319 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 4320 __le16 supported_speeds_eee_mode; 4321 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 4322 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 4323 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 4324 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 4325 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 4326 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 4327 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 4328 __le32 tx_lpi_timer_low; 4329 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 4330 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 4331 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 4332 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 4333 __le32 valid_tx_lpi_timer_high; 4334 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 4335 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 4336 #define PORT_PHY_QCAPS_RESP_RSVD_MASK 0xff000000UL 4337 #define PORT_PHY_QCAPS_RESP_RSVD_SFT 24 4338 __le16 supported_pam4_speeds_auto_mode; 4339 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL 4340 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL 4341 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL 4342 __le16 supported_pam4_speeds_force_mode; 4343 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL 4344 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL 4345 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL 4346 u8 unused_0[3]; 4347 u8 valid; 4348 }; 4349 4350 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 4351 struct hwrm_port_phy_i2c_read_input { 4352 __le16 req_type; 4353 __le16 cmpl_ring; 4354 __le16 seq_id; 4355 __le16 target_id; 4356 __le64 resp_addr; 4357 __le32 flags; 4358 __le32 enables; 4359 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 4360 __le16 port_id; 4361 u8 i2c_slave_addr; 4362 u8 unused_0; 4363 __le16 page_number; 4364 __le16 page_offset; 4365 u8 data_length; 4366 u8 unused_1[7]; 4367 }; 4368 4369 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 4370 struct hwrm_port_phy_i2c_read_output { 4371 __le16 error_code; 4372 __le16 req_type; 4373 __le16 seq_id; 4374 __le16 resp_len; 4375 __le32 data[16]; 4376 u8 unused_0[7]; 4377 u8 valid; 4378 }; 4379 4380 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */ 4381 struct hwrm_port_phy_mdio_write_input { 4382 __le16 req_type; 4383 __le16 cmpl_ring; 4384 __le16 seq_id; 4385 __le16 target_id; 4386 __le64 resp_addr; 4387 __le32 unused_0[2]; 4388 __le16 port_id; 4389 u8 phy_addr; 4390 u8 dev_addr; 4391 __le16 reg_addr; 4392 __le16 reg_data; 4393 u8 cl45_mdio; 4394 u8 unused_1[7]; 4395 }; 4396 4397 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */ 4398 struct hwrm_port_phy_mdio_write_output { 4399 __le16 error_code; 4400 __le16 req_type; 4401 __le16 seq_id; 4402 __le16 resp_len; 4403 u8 unused_0[7]; 4404 u8 valid; 4405 }; 4406 4407 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */ 4408 struct hwrm_port_phy_mdio_read_input { 4409 __le16 req_type; 4410 __le16 cmpl_ring; 4411 __le16 seq_id; 4412 __le16 target_id; 4413 __le64 resp_addr; 4414 __le32 unused_0[2]; 4415 __le16 port_id; 4416 u8 phy_addr; 4417 u8 dev_addr; 4418 __le16 reg_addr; 4419 u8 cl45_mdio; 4420 u8 unused_1; 4421 }; 4422 4423 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */ 4424 struct hwrm_port_phy_mdio_read_output { 4425 __le16 error_code; 4426 __le16 req_type; 4427 __le16 seq_id; 4428 __le16 resp_len; 4429 __le16 reg_data; 4430 u8 unused_0[5]; 4431 u8 valid; 4432 }; 4433 4434 /* hwrm_port_led_cfg_input (size:512b/64B) */ 4435 struct hwrm_port_led_cfg_input { 4436 __le16 req_type; 4437 __le16 cmpl_ring; 4438 __le16 seq_id; 4439 __le16 target_id; 4440 __le64 resp_addr; 4441 __le32 enables; 4442 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 4443 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 4444 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 4445 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 4446 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 4447 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 4448 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 4449 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 4450 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 4451 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 4452 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 4453 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 4454 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 4455 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 4456 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 4457 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 4458 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 4459 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 4460 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 4461 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 4462 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 4463 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 4464 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 4465 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 4466 __le16 port_id; 4467 u8 num_leds; 4468 u8 rsvd; 4469 u8 led0_id; 4470 u8 led0_state; 4471 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 4472 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 4473 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 4474 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 4475 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 4476 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 4477 u8 led0_color; 4478 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 4479 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 4480 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 4481 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 4482 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 4483 u8 unused_0; 4484 __le16 led0_blink_on; 4485 __le16 led0_blink_off; 4486 u8 led0_group_id; 4487 u8 rsvd0; 4488 u8 led1_id; 4489 u8 led1_state; 4490 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 4491 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 4492 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 4493 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 4494 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 4495 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 4496 u8 led1_color; 4497 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 4498 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 4499 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 4500 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 4501 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 4502 u8 unused_1; 4503 __le16 led1_blink_on; 4504 __le16 led1_blink_off; 4505 u8 led1_group_id; 4506 u8 rsvd1; 4507 u8 led2_id; 4508 u8 led2_state; 4509 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 4510 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 4511 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 4512 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 4513 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 4514 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 4515 u8 led2_color; 4516 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 4517 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 4518 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 4519 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 4520 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 4521 u8 unused_2; 4522 __le16 led2_blink_on; 4523 __le16 led2_blink_off; 4524 u8 led2_group_id; 4525 u8 rsvd2; 4526 u8 led3_id; 4527 u8 led3_state; 4528 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 4529 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 4530 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 4531 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 4532 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 4533 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 4534 u8 led3_color; 4535 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 4536 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 4537 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 4538 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 4539 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 4540 u8 unused_3; 4541 __le16 led3_blink_on; 4542 __le16 led3_blink_off; 4543 u8 led3_group_id; 4544 u8 rsvd3; 4545 }; 4546 4547 /* hwrm_port_led_cfg_output (size:128b/16B) */ 4548 struct hwrm_port_led_cfg_output { 4549 __le16 error_code; 4550 __le16 req_type; 4551 __le16 seq_id; 4552 __le16 resp_len; 4553 u8 unused_0[7]; 4554 u8 valid; 4555 }; 4556 4557 /* hwrm_port_led_qcfg_input (size:192b/24B) */ 4558 struct hwrm_port_led_qcfg_input { 4559 __le16 req_type; 4560 __le16 cmpl_ring; 4561 __le16 seq_id; 4562 __le16 target_id; 4563 __le64 resp_addr; 4564 __le16 port_id; 4565 u8 unused_0[6]; 4566 }; 4567 4568 /* hwrm_port_led_qcfg_output (size:448b/56B) */ 4569 struct hwrm_port_led_qcfg_output { 4570 __le16 error_code; 4571 __le16 req_type; 4572 __le16 seq_id; 4573 __le16 resp_len; 4574 u8 num_leds; 4575 u8 led0_id; 4576 u8 led0_type; 4577 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 4578 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 4579 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 4580 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 4581 u8 led0_state; 4582 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 4583 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 4584 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 4585 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 4586 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 4587 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 4588 u8 led0_color; 4589 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 4590 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 4591 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 4592 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 4593 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 4594 u8 unused_0; 4595 __le16 led0_blink_on; 4596 __le16 led0_blink_off; 4597 u8 led0_group_id; 4598 u8 led1_id; 4599 u8 led1_type; 4600 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 4601 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 4602 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 4603 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 4604 u8 led1_state; 4605 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 4606 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 4607 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 4608 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 4609 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 4610 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 4611 u8 led1_color; 4612 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 4613 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 4614 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 4615 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 4616 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 4617 u8 unused_1; 4618 __le16 led1_blink_on; 4619 __le16 led1_blink_off; 4620 u8 led1_group_id; 4621 u8 led2_id; 4622 u8 led2_type; 4623 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 4624 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 4625 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 4626 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 4627 u8 led2_state; 4628 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 4629 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 4630 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 4631 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 4632 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 4633 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 4634 u8 led2_color; 4635 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 4636 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 4637 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 4638 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 4639 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 4640 u8 unused_2; 4641 __le16 led2_blink_on; 4642 __le16 led2_blink_off; 4643 u8 led2_group_id; 4644 u8 led3_id; 4645 u8 led3_type; 4646 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 4647 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 4648 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 4649 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 4650 u8 led3_state; 4651 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 4652 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 4653 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 4654 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 4655 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 4656 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 4657 u8 led3_color; 4658 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 4659 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 4660 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 4661 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 4662 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 4663 u8 unused_3; 4664 __le16 led3_blink_on; 4665 __le16 led3_blink_off; 4666 u8 led3_group_id; 4667 u8 unused_4[6]; 4668 u8 valid; 4669 }; 4670 4671 /* hwrm_port_led_qcaps_input (size:192b/24B) */ 4672 struct hwrm_port_led_qcaps_input { 4673 __le16 req_type; 4674 __le16 cmpl_ring; 4675 __le16 seq_id; 4676 __le16 target_id; 4677 __le64 resp_addr; 4678 __le16 port_id; 4679 u8 unused_0[6]; 4680 }; 4681 4682 /* hwrm_port_led_qcaps_output (size:384b/48B) */ 4683 struct hwrm_port_led_qcaps_output { 4684 __le16 error_code; 4685 __le16 req_type; 4686 __le16 seq_id; 4687 __le16 resp_len; 4688 u8 num_leds; 4689 u8 unused[3]; 4690 u8 led0_id; 4691 u8 led0_type; 4692 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 4693 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 4694 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 4695 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 4696 u8 led0_group_id; 4697 u8 unused_0; 4698 __le16 led0_state_caps; 4699 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 4700 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 4701 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 4702 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4703 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4704 __le16 led0_color_caps; 4705 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 4706 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4707 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4708 u8 led1_id; 4709 u8 led1_type; 4710 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 4711 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 4712 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 4713 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 4714 u8 led1_group_id; 4715 u8 unused_1; 4716 __le16 led1_state_caps; 4717 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 4718 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 4719 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 4720 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4721 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4722 __le16 led1_color_caps; 4723 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 4724 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4725 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4726 u8 led2_id; 4727 u8 led2_type; 4728 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 4729 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 4730 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 4731 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 4732 u8 led2_group_id; 4733 u8 unused_2; 4734 __le16 led2_state_caps; 4735 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 4736 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 4737 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 4738 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4739 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4740 __le16 led2_color_caps; 4741 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 4742 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4743 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4744 u8 led3_id; 4745 u8 led3_type; 4746 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 4747 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 4748 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 4749 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 4750 u8 led3_group_id; 4751 u8 unused_3; 4752 __le16 led3_state_caps; 4753 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 4754 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 4755 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 4756 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4757 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4758 __le16 led3_color_caps; 4759 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 4760 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4761 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4762 u8 unused_4[3]; 4763 u8 valid; 4764 }; 4765 4766 /* hwrm_queue_qportcfg_input (size:192b/24B) */ 4767 struct hwrm_queue_qportcfg_input { 4768 __le16 req_type; 4769 __le16 cmpl_ring; 4770 __le16 seq_id; 4771 __le16 target_id; 4772 __le64 resp_addr; 4773 __le32 flags; 4774 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 4775 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 4776 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 4777 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 4778 __le16 port_id; 4779 u8 drv_qmap_cap; 4780 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 4781 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 4782 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 4783 u8 unused_0; 4784 }; 4785 4786 /* hwrm_queue_qportcfg_output (size:1344b/168B) */ 4787 struct hwrm_queue_qportcfg_output { 4788 __le16 error_code; 4789 __le16 req_type; 4790 __le16 seq_id; 4791 __le16 resp_len; 4792 u8 max_configurable_queues; 4793 u8 max_configurable_lossless_queues; 4794 u8 queue_cfg_allowed; 4795 u8 queue_cfg_info; 4796 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 4797 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_USE_PROFILE_TYPE 0x2UL 4798 u8 queue_pfcenable_cfg_allowed; 4799 u8 queue_pri2cos_cfg_allowed; 4800 u8 queue_cos2bw_cfg_allowed; 4801 u8 queue_id0; 4802 u8 queue_id0_service_profile; 4803 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 4804 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 4805 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4806 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4807 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4808 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 4809 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 4810 u8 queue_id1; 4811 u8 queue_id1_service_profile; 4812 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 4813 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 4814 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4815 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4816 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4817 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 4818 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 4819 u8 queue_id2; 4820 u8 queue_id2_service_profile; 4821 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 4822 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 4823 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4824 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4825 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4826 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 4827 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 4828 u8 queue_id3; 4829 u8 queue_id3_service_profile; 4830 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 4831 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 4832 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4833 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4834 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4835 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 4836 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 4837 u8 queue_id4; 4838 u8 queue_id4_service_profile; 4839 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 4840 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 4841 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4842 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4843 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4844 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 4845 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 4846 u8 queue_id5; 4847 u8 queue_id5_service_profile; 4848 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 4849 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 4850 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4851 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4852 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4853 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 4854 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 4855 u8 queue_id6; 4856 u8 queue_id6_service_profile; 4857 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 4858 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 4859 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4860 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4861 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4862 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 4863 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 4864 u8 queue_id7; 4865 u8 queue_id7_service_profile; 4866 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 4867 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 4868 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4869 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4870 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4871 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 4872 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 4873 u8 queue_id0_service_profile_type; 4874 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4875 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC 0x2UL 4876 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP 0x4UL 4877 char qid0_name[16]; 4878 char qid1_name[16]; 4879 char qid2_name[16]; 4880 char qid3_name[16]; 4881 char qid4_name[16]; 4882 char qid5_name[16]; 4883 char qid6_name[16]; 4884 char qid7_name[16]; 4885 u8 queue_id1_service_profile_type; 4886 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4887 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC 0x2UL 4888 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP 0x4UL 4889 u8 queue_id2_service_profile_type; 4890 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4891 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC 0x2UL 4892 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP 0x4UL 4893 u8 queue_id3_service_profile_type; 4894 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4895 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC 0x2UL 4896 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP 0x4UL 4897 u8 queue_id4_service_profile_type; 4898 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4899 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC 0x2UL 4900 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP 0x4UL 4901 u8 queue_id5_service_profile_type; 4902 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4903 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC 0x2UL 4904 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP 0x4UL 4905 u8 queue_id6_service_profile_type; 4906 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4907 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC 0x2UL 4908 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP 0x4UL 4909 u8 queue_id7_service_profile_type; 4910 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4911 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC 0x2UL 4912 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP 0x4UL 4913 u8 valid; 4914 }; 4915 4916 /* hwrm_queue_qcfg_input (size:192b/24B) */ 4917 struct hwrm_queue_qcfg_input { 4918 __le16 req_type; 4919 __le16 cmpl_ring; 4920 __le16 seq_id; 4921 __le16 target_id; 4922 __le64 resp_addr; 4923 __le32 flags; 4924 #define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL 4925 #define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL 4926 #define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL 4927 #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX 4928 __le32 queue_id; 4929 }; 4930 4931 /* hwrm_queue_qcfg_output (size:128b/16B) */ 4932 struct hwrm_queue_qcfg_output { 4933 __le16 error_code; 4934 __le16 req_type; 4935 __le16 seq_id; 4936 __le16 resp_len; 4937 __le32 queue_len; 4938 u8 service_profile; 4939 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL 4940 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL 4941 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL 4942 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 4943 u8 queue_cfg_info; 4944 #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 4945 u8 unused_0; 4946 u8 valid; 4947 }; 4948 4949 /* hwrm_queue_cfg_input (size:320b/40B) */ 4950 struct hwrm_queue_cfg_input { 4951 __le16 req_type; 4952 __le16 cmpl_ring; 4953 __le16 seq_id; 4954 __le16 target_id; 4955 __le64 resp_addr; 4956 __le32 flags; 4957 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 4958 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 4959 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 4960 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 4961 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 4962 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 4963 __le32 enables; 4964 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 4965 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 4966 __le32 queue_id; 4967 __le32 dflt_len; 4968 u8 service_profile; 4969 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 4970 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 4971 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 4972 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 4973 u8 unused_0[7]; 4974 }; 4975 4976 /* hwrm_queue_cfg_output (size:128b/16B) */ 4977 struct hwrm_queue_cfg_output { 4978 __le16 error_code; 4979 __le16 req_type; 4980 __le16 seq_id; 4981 __le16 resp_len; 4982 u8 unused_0[7]; 4983 u8 valid; 4984 }; 4985 4986 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 4987 struct hwrm_queue_pfcenable_qcfg_input { 4988 __le16 req_type; 4989 __le16 cmpl_ring; 4990 __le16 seq_id; 4991 __le16 target_id; 4992 __le64 resp_addr; 4993 __le16 port_id; 4994 u8 unused_0[6]; 4995 }; 4996 4997 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 4998 struct hwrm_queue_pfcenable_qcfg_output { 4999 __le16 error_code; 5000 __le16 req_type; 5001 __le16 seq_id; 5002 __le16 resp_len; 5003 __le32 flags; 5004 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 5005 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 5006 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 5007 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 5008 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 5009 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 5010 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 5011 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 5012 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 5013 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 5014 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 5015 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 5016 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 5017 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 5018 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 5019 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 5020 u8 unused_0[3]; 5021 u8 valid; 5022 }; 5023 5024 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 5025 struct hwrm_queue_pfcenable_cfg_input { 5026 __le16 req_type; 5027 __le16 cmpl_ring; 5028 __le16 seq_id; 5029 __le16 target_id; 5030 __le64 resp_addr; 5031 __le32 flags; 5032 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 5033 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 5034 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 5035 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 5036 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 5037 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 5038 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 5039 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 5040 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 5041 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 5042 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 5043 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 5044 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 5045 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 5046 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 5047 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 5048 __le16 port_id; 5049 u8 unused_0[2]; 5050 }; 5051 5052 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 5053 struct hwrm_queue_pfcenable_cfg_output { 5054 __le16 error_code; 5055 __le16 req_type; 5056 __le16 seq_id; 5057 __le16 resp_len; 5058 u8 unused_0[7]; 5059 u8 valid; 5060 }; 5061 5062 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 5063 struct hwrm_queue_pri2cos_qcfg_input { 5064 __le16 req_type; 5065 __le16 cmpl_ring; 5066 __le16 seq_id; 5067 __le16 target_id; 5068 __le64 resp_addr; 5069 __le32 flags; 5070 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 5071 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 5072 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 5073 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 5074 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 5075 u8 port_id; 5076 u8 unused_0[3]; 5077 }; 5078 5079 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 5080 struct hwrm_queue_pri2cos_qcfg_output { 5081 __le16 error_code; 5082 __le16 req_type; 5083 __le16 seq_id; 5084 __le16 resp_len; 5085 u8 pri0_cos_queue_id; 5086 u8 pri1_cos_queue_id; 5087 u8 pri2_cos_queue_id; 5088 u8 pri3_cos_queue_id; 5089 u8 pri4_cos_queue_id; 5090 u8 pri5_cos_queue_id; 5091 u8 pri6_cos_queue_id; 5092 u8 pri7_cos_queue_id; 5093 u8 queue_cfg_info; 5094 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 5095 u8 unused_0[6]; 5096 u8 valid; 5097 }; 5098 5099 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 5100 struct hwrm_queue_pri2cos_cfg_input { 5101 __le16 req_type; 5102 __le16 cmpl_ring; 5103 __le16 seq_id; 5104 __le16 target_id; 5105 __le64 resp_addr; 5106 __le32 flags; 5107 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 5108 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 5109 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 5110 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 5111 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 5112 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 5113 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 5114 __le32 enables; 5115 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 5116 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 5117 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 5118 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 5119 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 5120 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 5121 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 5122 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 5123 u8 port_id; 5124 u8 pri0_cos_queue_id; 5125 u8 pri1_cos_queue_id; 5126 u8 pri2_cos_queue_id; 5127 u8 pri3_cos_queue_id; 5128 u8 pri4_cos_queue_id; 5129 u8 pri5_cos_queue_id; 5130 u8 pri6_cos_queue_id; 5131 u8 pri7_cos_queue_id; 5132 u8 unused_0[7]; 5133 }; 5134 5135 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 5136 struct hwrm_queue_pri2cos_cfg_output { 5137 __le16 error_code; 5138 __le16 req_type; 5139 __le16 seq_id; 5140 __le16 resp_len; 5141 u8 unused_0[7]; 5142 u8 valid; 5143 }; 5144 5145 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 5146 struct hwrm_queue_cos2bw_qcfg_input { 5147 __le16 req_type; 5148 __le16 cmpl_ring; 5149 __le16 seq_id; 5150 __le16 target_id; 5151 __le64 resp_addr; 5152 __le16 port_id; 5153 u8 unused_0[6]; 5154 }; 5155 5156 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 5157 struct hwrm_queue_cos2bw_qcfg_output { 5158 __le16 error_code; 5159 __le16 req_type; 5160 __le16 seq_id; 5161 __le16 resp_len; 5162 u8 queue_id0; 5163 u8 unused_0; 5164 __le16 unused_1; 5165 __le32 queue_id0_min_bw; 5166 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5167 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 5168 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 5169 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 5170 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 5171 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 5172 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5173 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 5174 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5175 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5176 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5177 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5178 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5179 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5180 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 5181 __le32 queue_id0_max_bw; 5182 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5183 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 5184 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 5185 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 5186 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 5187 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 5188 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5189 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 5190 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5191 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5192 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5193 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5194 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5195 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5196 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 5197 u8 queue_id0_tsa_assign; 5198 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 5199 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 5200 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5201 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 5202 u8 queue_id0_pri_lvl; 5203 u8 queue_id0_bw_weight; 5204 u8 queue_id1; 5205 __le32 queue_id1_min_bw; 5206 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5207 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 5208 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 5209 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 5210 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 5211 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 5212 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5213 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 5214 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5215 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5216 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5217 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5218 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5219 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5220 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 5221 __le32 queue_id1_max_bw; 5222 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5223 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 5224 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 5225 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 5226 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 5227 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 5228 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5229 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 5230 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5231 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5232 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5233 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5234 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5235 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5236 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 5237 u8 queue_id1_tsa_assign; 5238 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 5239 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 5240 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5241 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 5242 u8 queue_id1_pri_lvl; 5243 u8 queue_id1_bw_weight; 5244 u8 queue_id2; 5245 __le32 queue_id2_min_bw; 5246 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5247 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 5248 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 5249 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 5250 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 5251 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 5252 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5253 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 5254 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5255 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5256 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5257 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5258 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5259 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5260 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 5261 __le32 queue_id2_max_bw; 5262 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5263 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 5264 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 5265 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 5266 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 5267 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 5268 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5269 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 5270 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5271 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5272 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5273 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5274 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5275 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5276 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 5277 u8 queue_id2_tsa_assign; 5278 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 5279 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 5280 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5281 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 5282 u8 queue_id2_pri_lvl; 5283 u8 queue_id2_bw_weight; 5284 u8 queue_id3; 5285 __le32 queue_id3_min_bw; 5286 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5287 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 5288 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 5289 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 5290 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 5291 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 5292 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5293 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 5294 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5295 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5296 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5297 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5298 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5299 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5300 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 5301 __le32 queue_id3_max_bw; 5302 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5303 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 5304 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 5305 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 5306 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 5307 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 5308 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5309 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 5310 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5311 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5312 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5313 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5314 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5315 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5316 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 5317 u8 queue_id3_tsa_assign; 5318 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 5319 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 5320 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5321 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 5322 u8 queue_id3_pri_lvl; 5323 u8 queue_id3_bw_weight; 5324 u8 queue_id4; 5325 __le32 queue_id4_min_bw; 5326 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5327 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 5328 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 5329 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 5330 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 5331 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 5332 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5333 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 5334 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5335 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5336 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5337 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5338 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5339 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5340 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 5341 __le32 queue_id4_max_bw; 5342 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5343 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 5344 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 5345 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 5346 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 5347 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 5348 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5349 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 5350 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5351 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5352 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5353 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5354 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5355 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5356 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 5357 u8 queue_id4_tsa_assign; 5358 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 5359 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 5360 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5361 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 5362 u8 queue_id4_pri_lvl; 5363 u8 queue_id4_bw_weight; 5364 u8 queue_id5; 5365 __le32 queue_id5_min_bw; 5366 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5367 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 5368 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 5369 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 5370 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 5371 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 5372 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5373 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 5374 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5375 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5376 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5377 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5378 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5379 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5380 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 5381 __le32 queue_id5_max_bw; 5382 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5383 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 5384 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 5385 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 5386 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 5387 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 5388 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5389 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 5390 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5391 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5392 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5393 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5394 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5395 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5396 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 5397 u8 queue_id5_tsa_assign; 5398 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 5399 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 5400 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5401 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 5402 u8 queue_id5_pri_lvl; 5403 u8 queue_id5_bw_weight; 5404 u8 queue_id6; 5405 __le32 queue_id6_min_bw; 5406 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5407 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 5408 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 5409 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 5410 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 5411 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 5412 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5413 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 5414 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5415 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5416 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5417 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5418 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5419 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5420 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 5421 __le32 queue_id6_max_bw; 5422 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5423 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 5424 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 5425 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 5426 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 5427 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 5428 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5429 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 5430 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5431 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5432 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5433 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5434 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5435 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5436 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 5437 u8 queue_id6_tsa_assign; 5438 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 5439 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 5440 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5441 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 5442 u8 queue_id6_pri_lvl; 5443 u8 queue_id6_bw_weight; 5444 u8 queue_id7; 5445 __le32 queue_id7_min_bw; 5446 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5447 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 5448 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 5449 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 5450 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 5451 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 5452 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5453 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 5454 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5455 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5456 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5457 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5458 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5459 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5460 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 5461 __le32 queue_id7_max_bw; 5462 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5463 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 5464 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 5465 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 5466 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 5467 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 5468 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5469 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 5470 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5471 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5472 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5473 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5474 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5475 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5476 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 5477 u8 queue_id7_tsa_assign; 5478 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 5479 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 5480 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5481 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 5482 u8 queue_id7_pri_lvl; 5483 u8 queue_id7_bw_weight; 5484 u8 unused_2[4]; 5485 u8 valid; 5486 }; 5487 5488 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 5489 struct hwrm_queue_cos2bw_cfg_input { 5490 __le16 req_type; 5491 __le16 cmpl_ring; 5492 __le16 seq_id; 5493 __le16 target_id; 5494 __le64 resp_addr; 5495 __le32 flags; 5496 __le32 enables; 5497 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 5498 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 5499 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 5500 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 5501 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 5502 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 5503 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 5504 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 5505 __le16 port_id; 5506 u8 queue_id0; 5507 u8 unused_0; 5508 __le32 queue_id0_min_bw; 5509 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5510 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 5511 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 5512 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 5513 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 5514 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 5515 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5516 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 5517 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5518 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5519 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5520 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5521 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5522 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5523 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 5524 __le32 queue_id0_max_bw; 5525 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5526 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 5527 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 5528 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 5529 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 5530 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 5531 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5532 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 5533 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5534 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5535 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5536 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5537 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5538 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5539 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 5540 u8 queue_id0_tsa_assign; 5541 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 5542 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 5543 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5544 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 5545 u8 queue_id0_pri_lvl; 5546 u8 queue_id0_bw_weight; 5547 u8 queue_id1; 5548 __le32 queue_id1_min_bw; 5549 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5550 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 5551 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 5552 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 5553 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 5554 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 5555 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5556 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 5557 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5558 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5559 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5560 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5561 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5562 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5563 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 5564 __le32 queue_id1_max_bw; 5565 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5566 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 5567 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 5568 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 5569 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 5570 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 5571 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5572 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 5573 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5574 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5575 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5576 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5577 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5578 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5579 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 5580 u8 queue_id1_tsa_assign; 5581 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 5582 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 5583 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5584 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 5585 u8 queue_id1_pri_lvl; 5586 u8 queue_id1_bw_weight; 5587 u8 queue_id2; 5588 __le32 queue_id2_min_bw; 5589 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5590 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 5591 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 5592 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 5593 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 5594 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 5595 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5596 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 5597 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5598 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5599 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5600 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5601 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5602 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5603 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 5604 __le32 queue_id2_max_bw; 5605 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5606 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 5607 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 5608 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 5609 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 5610 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 5611 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5612 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 5613 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5614 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5615 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5616 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5617 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5618 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5619 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 5620 u8 queue_id2_tsa_assign; 5621 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 5622 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 5623 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5624 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 5625 u8 queue_id2_pri_lvl; 5626 u8 queue_id2_bw_weight; 5627 u8 queue_id3; 5628 __le32 queue_id3_min_bw; 5629 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5630 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 5631 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 5632 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 5633 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 5634 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 5635 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5636 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 5637 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5638 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5639 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5640 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5641 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5642 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5643 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 5644 __le32 queue_id3_max_bw; 5645 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5646 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 5647 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 5648 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 5649 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 5650 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 5651 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5652 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 5653 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5654 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5655 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5656 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5657 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5658 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5659 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 5660 u8 queue_id3_tsa_assign; 5661 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 5662 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 5663 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5664 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 5665 u8 queue_id3_pri_lvl; 5666 u8 queue_id3_bw_weight; 5667 u8 queue_id4; 5668 __le32 queue_id4_min_bw; 5669 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5670 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 5671 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 5672 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 5673 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 5674 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 5675 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5676 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 5677 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5678 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5679 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5680 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5681 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5682 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5683 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 5684 __le32 queue_id4_max_bw; 5685 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5686 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 5687 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 5688 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 5689 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 5690 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 5691 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5692 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 5693 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5694 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5695 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5696 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5697 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5698 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5699 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 5700 u8 queue_id4_tsa_assign; 5701 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 5702 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 5703 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5704 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 5705 u8 queue_id4_pri_lvl; 5706 u8 queue_id4_bw_weight; 5707 u8 queue_id5; 5708 __le32 queue_id5_min_bw; 5709 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5710 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 5711 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 5712 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 5713 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 5714 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 5715 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5716 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 5717 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5718 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5719 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5720 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5721 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5722 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5723 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 5724 __le32 queue_id5_max_bw; 5725 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5726 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 5727 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 5728 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 5729 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 5730 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 5731 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5732 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 5733 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5734 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5735 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5736 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5737 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5738 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5739 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 5740 u8 queue_id5_tsa_assign; 5741 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 5742 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 5743 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5744 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 5745 u8 queue_id5_pri_lvl; 5746 u8 queue_id5_bw_weight; 5747 u8 queue_id6; 5748 __le32 queue_id6_min_bw; 5749 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5750 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 5751 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 5752 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 5753 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 5754 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 5755 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5756 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 5757 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5758 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5759 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5760 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5761 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5762 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5763 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 5764 __le32 queue_id6_max_bw; 5765 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5766 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 5767 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 5768 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 5769 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 5770 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 5771 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5772 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 5773 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5774 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5775 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5776 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5777 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5778 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5779 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 5780 u8 queue_id6_tsa_assign; 5781 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 5782 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 5783 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5784 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 5785 u8 queue_id6_pri_lvl; 5786 u8 queue_id6_bw_weight; 5787 u8 queue_id7; 5788 __le32 queue_id7_min_bw; 5789 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5790 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 5791 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 5792 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 5793 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 5794 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 5795 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5796 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 5797 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5798 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5799 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5800 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5801 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5802 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5803 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 5804 __le32 queue_id7_max_bw; 5805 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5806 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 5807 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 5808 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 5809 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 5810 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 5811 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5812 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 5813 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5814 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5815 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5816 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5817 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5818 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5819 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 5820 u8 queue_id7_tsa_assign; 5821 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 5822 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 5823 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5824 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 5825 u8 queue_id7_pri_lvl; 5826 u8 queue_id7_bw_weight; 5827 u8 unused_1[5]; 5828 }; 5829 5830 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 5831 struct hwrm_queue_cos2bw_cfg_output { 5832 __le16 error_code; 5833 __le16 req_type; 5834 __le16 seq_id; 5835 __le16 resp_len; 5836 u8 unused_0[7]; 5837 u8 valid; 5838 }; 5839 5840 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 5841 struct hwrm_queue_dscp_qcaps_input { 5842 __le16 req_type; 5843 __le16 cmpl_ring; 5844 __le16 seq_id; 5845 __le16 target_id; 5846 __le64 resp_addr; 5847 u8 port_id; 5848 u8 unused_0[7]; 5849 }; 5850 5851 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 5852 struct hwrm_queue_dscp_qcaps_output { 5853 __le16 error_code; 5854 __le16 req_type; 5855 __le16 seq_id; 5856 __le16 resp_len; 5857 u8 num_dscp_bits; 5858 u8 unused_0; 5859 __le16 max_entries; 5860 u8 unused_1[3]; 5861 u8 valid; 5862 }; 5863 5864 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 5865 struct hwrm_queue_dscp2pri_qcfg_input { 5866 __le16 req_type; 5867 __le16 cmpl_ring; 5868 __le16 seq_id; 5869 __le16 target_id; 5870 __le64 resp_addr; 5871 __le64 dest_data_addr; 5872 u8 port_id; 5873 u8 unused_0; 5874 __le16 dest_data_buffer_size; 5875 u8 unused_1[4]; 5876 }; 5877 5878 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 5879 struct hwrm_queue_dscp2pri_qcfg_output { 5880 __le16 error_code; 5881 __le16 req_type; 5882 __le16 seq_id; 5883 __le16 resp_len; 5884 __le16 entry_cnt; 5885 u8 default_pri; 5886 u8 unused_0[4]; 5887 u8 valid; 5888 }; 5889 5890 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 5891 struct hwrm_queue_dscp2pri_cfg_input { 5892 __le16 req_type; 5893 __le16 cmpl_ring; 5894 __le16 seq_id; 5895 __le16 target_id; 5896 __le64 resp_addr; 5897 __le64 src_data_addr; 5898 __le32 flags; 5899 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 5900 __le32 enables; 5901 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 5902 u8 port_id; 5903 u8 default_pri; 5904 __le16 entry_cnt; 5905 u8 unused_0[4]; 5906 }; 5907 5908 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 5909 struct hwrm_queue_dscp2pri_cfg_output { 5910 __le16 error_code; 5911 __le16 req_type; 5912 __le16 seq_id; 5913 __le16 resp_len; 5914 u8 unused_0[7]; 5915 u8 valid; 5916 }; 5917 5918 /* hwrm_vnic_alloc_input (size:192b/24B) */ 5919 struct hwrm_vnic_alloc_input { 5920 __le16 req_type; 5921 __le16 cmpl_ring; 5922 __le16 seq_id; 5923 __le16 target_id; 5924 __le64 resp_addr; 5925 __le32 flags; 5926 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 5927 #define VNIC_ALLOC_REQ_FLAGS_VIRTIO_NET_FID_VALID 0x2UL 5928 __le16 virtio_net_fid; 5929 u8 unused_0[2]; 5930 }; 5931 5932 /* hwrm_vnic_alloc_output (size:128b/16B) */ 5933 struct hwrm_vnic_alloc_output { 5934 __le16 error_code; 5935 __le16 req_type; 5936 __le16 seq_id; 5937 __le16 resp_len; 5938 __le32 vnic_id; 5939 u8 unused_0[3]; 5940 u8 valid; 5941 }; 5942 5943 /* hwrm_vnic_free_input (size:192b/24B) */ 5944 struct hwrm_vnic_free_input { 5945 __le16 req_type; 5946 __le16 cmpl_ring; 5947 __le16 seq_id; 5948 __le16 target_id; 5949 __le64 resp_addr; 5950 __le32 vnic_id; 5951 u8 unused_0[4]; 5952 }; 5953 5954 /* hwrm_vnic_free_output (size:128b/16B) */ 5955 struct hwrm_vnic_free_output { 5956 __le16 error_code; 5957 __le16 req_type; 5958 __le16 seq_id; 5959 __le16 resp_len; 5960 u8 unused_0[7]; 5961 u8 valid; 5962 }; 5963 5964 /* hwrm_vnic_cfg_input (size:384b/48B) */ 5965 struct hwrm_vnic_cfg_input { 5966 __le16 req_type; 5967 __le16 cmpl_ring; 5968 __le16 seq_id; 5969 __le16 target_id; 5970 __le64 resp_addr; 5971 __le32 flags; 5972 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 5973 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 5974 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 5975 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 5976 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 5977 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 5978 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 5979 __le32 enables; 5980 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 5981 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 5982 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 5983 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 5984 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 5985 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 5986 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 5987 #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL 5988 #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL 5989 __le16 vnic_id; 5990 __le16 dflt_ring_grp; 5991 __le16 rss_rule; 5992 __le16 cos_rule; 5993 __le16 lb_rule; 5994 __le16 mru; 5995 __le16 default_rx_ring_id; 5996 __le16 default_cmpl_ring_id; 5997 __le16 queue_id; 5998 u8 rx_csum_v2_mode; 5999 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL 6000 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK 0x1UL 6001 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 0x2UL 6002 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 6003 u8 unused0[5]; 6004 }; 6005 6006 /* hwrm_vnic_cfg_output (size:128b/16B) */ 6007 struct hwrm_vnic_cfg_output { 6008 __le16 error_code; 6009 __le16 req_type; 6010 __le16 seq_id; 6011 __le16 resp_len; 6012 u8 unused_0[7]; 6013 u8 valid; 6014 }; 6015 6016 /* hwrm_vnic_qcaps_input (size:192b/24B) */ 6017 struct hwrm_vnic_qcaps_input { 6018 __le16 req_type; 6019 __le16 cmpl_ring; 6020 __le16 seq_id; 6021 __le16 target_id; 6022 __le64 resp_addr; 6023 __le32 enables; 6024 u8 unused_0[4]; 6025 }; 6026 6027 /* hwrm_vnic_qcaps_output (size:192b/24B) */ 6028 struct hwrm_vnic_qcaps_output { 6029 __le16 error_code; 6030 __le16 req_type; 6031 __le16 seq_id; 6032 __le16 resp_len; 6033 __le16 mru; 6034 u8 unused_0[2]; 6035 __le32 flags; 6036 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 6037 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 6038 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 6039 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 6040 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 6041 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 6042 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 6043 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 6044 #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL 6045 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL 6046 #define VNIC_QCAPS_RESP_FLAGS_VNIC_STATE_CAP 0x400UL 6047 #define VNIC_QCAPS_RESP_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP 0x800UL 6048 #define VNIC_QCAPS_RESP_FLAGS_METADATA_FORMAT_CAP 0x1000UL 6049 #define VNIC_QCAPS_RESP_FLAGS_RSS_STRICT_HASH_TYPE_CAP 0x2000UL 6050 __le16 max_aggs_supported; 6051 u8 unused_1[5]; 6052 u8 valid; 6053 }; 6054 6055 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ 6056 struct hwrm_vnic_tpa_cfg_input { 6057 __le16 req_type; 6058 __le16 cmpl_ring; 6059 __le16 seq_id; 6060 __le16 target_id; 6061 __le64 resp_addr; 6062 __le32 flags; 6063 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 6064 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 6065 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 6066 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 6067 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 6068 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 6069 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 6070 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 6071 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL 6072 __le32 enables; 6073 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 6074 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 6075 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 6076 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 6077 __le16 vnic_id; 6078 __le16 max_agg_segs; 6079 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 6080 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 6081 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 6082 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 6083 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 6084 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 6085 __le16 max_aggs; 6086 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 6087 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 6088 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 6089 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 6090 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 6091 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 6092 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 6093 u8 unused_0[2]; 6094 __le32 max_agg_timer; 6095 __le32 min_agg_len; 6096 }; 6097 6098 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 6099 struct hwrm_vnic_tpa_cfg_output { 6100 __le16 error_code; 6101 __le16 req_type; 6102 __le16 seq_id; 6103 __le16 resp_len; 6104 u8 unused_0[7]; 6105 u8 valid; 6106 }; 6107 6108 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 6109 struct hwrm_vnic_tpa_qcfg_input { 6110 __le16 req_type; 6111 __le16 cmpl_ring; 6112 __le16 seq_id; 6113 __le16 target_id; 6114 __le64 resp_addr; 6115 __le16 vnic_id; 6116 u8 unused_0[6]; 6117 }; 6118 6119 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 6120 struct hwrm_vnic_tpa_qcfg_output { 6121 __le16 error_code; 6122 __le16 req_type; 6123 __le16 seq_id; 6124 __le16 resp_len; 6125 __le32 flags; 6126 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 6127 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 6128 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 6129 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 6130 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 6131 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 6132 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 6133 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 6134 __le16 max_agg_segs; 6135 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 6136 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 6137 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 6138 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 6139 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 6140 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 6141 __le16 max_aggs; 6142 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 6143 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 6144 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 6145 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 6146 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 6147 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 6148 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 6149 __le32 max_agg_timer; 6150 __le32 min_agg_len; 6151 u8 unused_0[7]; 6152 u8 valid; 6153 }; 6154 6155 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 6156 struct hwrm_vnic_rss_cfg_input { 6157 __le16 req_type; 6158 __le16 cmpl_ring; 6159 __le16 seq_id; 6160 __le16 target_id; 6161 __le64 resp_addr; 6162 __le32 hash_type; 6163 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 6164 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 6165 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 6166 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 6167 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 6168 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 6169 __le16 vnic_id; 6170 u8 ring_table_pair_index; 6171 u8 hash_mode_flags; 6172 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 6173 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 6174 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 6175 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 6176 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 6177 __le64 ring_grp_tbl_addr; 6178 __le64 hash_key_tbl_addr; 6179 __le16 rss_ctx_idx; 6180 u8 unused_1[6]; 6181 }; 6182 6183 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 6184 struct hwrm_vnic_rss_cfg_output { 6185 __le16 error_code; 6186 __le16 req_type; 6187 __le16 seq_id; 6188 __le16 resp_len; 6189 u8 unused_0[7]; 6190 u8 valid; 6191 }; 6192 6193 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ 6194 struct hwrm_vnic_rss_cfg_cmd_err { 6195 u8 code; 6196 #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 6197 #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL 6198 #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 6199 u8 unused_0[7]; 6200 }; 6201 6202 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 6203 struct hwrm_vnic_plcmodes_cfg_input { 6204 __le16 req_type; 6205 __le16 cmpl_ring; 6206 __le16 seq_id; 6207 __le16 target_id; 6208 __le64 resp_addr; 6209 __le32 flags; 6210 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 6211 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 6212 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 6213 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 6214 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 6215 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 6216 #define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT 0x40UL 6217 __le32 enables; 6218 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 6219 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 6220 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 6221 #define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID 0x8UL 6222 __le32 vnic_id; 6223 __le16 jumbo_thresh; 6224 __le16 hds_offset; 6225 __le16 hds_threshold; 6226 __le16 max_bds; 6227 u8 unused_0[4]; 6228 }; 6229 6230 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 6231 struct hwrm_vnic_plcmodes_cfg_output { 6232 __le16 error_code; 6233 __le16 req_type; 6234 __le16 seq_id; 6235 __le16 resp_len; 6236 u8 unused_0[7]; 6237 u8 valid; 6238 }; 6239 6240 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 6241 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 6242 __le16 req_type; 6243 __le16 cmpl_ring; 6244 __le16 seq_id; 6245 __le16 target_id; 6246 __le64 resp_addr; 6247 }; 6248 6249 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 6250 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 6251 __le16 error_code; 6252 __le16 req_type; 6253 __le16 seq_id; 6254 __le16 resp_len; 6255 __le16 rss_cos_lb_ctx_id; 6256 u8 unused_0[5]; 6257 u8 valid; 6258 }; 6259 6260 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 6261 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 6262 __le16 req_type; 6263 __le16 cmpl_ring; 6264 __le16 seq_id; 6265 __le16 target_id; 6266 __le64 resp_addr; 6267 __le16 rss_cos_lb_ctx_id; 6268 u8 unused_0[6]; 6269 }; 6270 6271 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 6272 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 6273 __le16 error_code; 6274 __le16 req_type; 6275 __le16 seq_id; 6276 __le16 resp_len; 6277 u8 unused_0[7]; 6278 u8 valid; 6279 }; 6280 6281 /* hwrm_ring_alloc_input (size:704b/88B) */ 6282 struct hwrm_ring_alloc_input { 6283 __le16 req_type; 6284 __le16 cmpl_ring; 6285 __le16 seq_id; 6286 __le16 target_id; 6287 __le64 resp_addr; 6288 __le32 enables; 6289 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 6290 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 6291 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 6292 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 6293 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 6294 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 6295 #define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL 6296 #define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL 6297 u8 ring_type; 6298 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 6299 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 6300 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 6301 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 6302 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 6303 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 6304 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 6305 u8 unused_0; 6306 __le16 flags; 6307 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 6308 __le64 page_tbl_addr; 6309 __le32 fbo; 6310 u8 page_size; 6311 u8 page_tbl_depth; 6312 __le16 schq_id; 6313 __le32 length; 6314 __le16 logical_id; 6315 __le16 cmpl_ring_id; 6316 __le16 queue_id; 6317 __le16 rx_buf_size; 6318 __le16 rx_ring_id; 6319 __le16 nq_ring_id; 6320 __le16 ring_arb_cfg; 6321 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 6322 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 6323 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 6324 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 6325 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 6326 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 6327 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 6328 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 6329 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 6330 __le16 unused_3; 6331 __le32 reserved3; 6332 __le32 stat_ctx_id; 6333 __le32 reserved4; 6334 __le32 max_bw; 6335 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6336 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 6337 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 6338 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 6339 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 6340 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 6341 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6342 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 6343 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6344 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6345 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6346 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6347 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6348 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6349 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 6350 u8 int_mode; 6351 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 6352 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 6353 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 6354 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 6355 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 6356 u8 mpc_chnls_type; 6357 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE 0x0UL 6358 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE 0x1UL 6359 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA 0x2UL 6360 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL 6361 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL 6362 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 6363 u8 unused_4[2]; 6364 __le64 cq_handle; 6365 }; 6366 6367 /* hwrm_ring_alloc_output (size:128b/16B) */ 6368 struct hwrm_ring_alloc_output { 6369 __le16 error_code; 6370 __le16 req_type; 6371 __le16 seq_id; 6372 __le16 resp_len; 6373 __le16 ring_id; 6374 __le16 logical_ring_id; 6375 u8 push_buffer_index; 6376 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 6377 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 6378 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_LAST RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 6379 u8 unused_0[2]; 6380 u8 valid; 6381 }; 6382 6383 /* hwrm_ring_free_input (size:256b/32B) */ 6384 struct hwrm_ring_free_input { 6385 __le16 req_type; 6386 __le16 cmpl_ring; 6387 __le16 seq_id; 6388 __le16 target_id; 6389 __le64 resp_addr; 6390 u8 ring_type; 6391 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 6392 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 6393 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 6394 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 6395 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 6396 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 6397 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 6398 u8 flags; 6399 #define RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 0x1UL 6400 #define RING_FREE_REQ_FLAGS_LAST RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 6401 __le16 ring_id; 6402 __le32 prod_idx; 6403 __le32 opaque; 6404 __le32 unused_1; 6405 }; 6406 6407 /* hwrm_ring_free_output (size:128b/16B) */ 6408 struct hwrm_ring_free_output { 6409 __le16 error_code; 6410 __le16 req_type; 6411 __le16 seq_id; 6412 __le16 resp_len; 6413 u8 unused_0[7]; 6414 u8 valid; 6415 }; 6416 6417 /* hwrm_ring_reset_input (size:192b/24B) */ 6418 struct hwrm_ring_reset_input { 6419 __le16 req_type; 6420 __le16 cmpl_ring; 6421 __le16 seq_id; 6422 __le16 target_id; 6423 __le64 resp_addr; 6424 u8 ring_type; 6425 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 6426 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 6427 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 6428 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 6429 #define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL 6430 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_RX_RING_GRP 6431 u8 unused_0; 6432 __le16 ring_id; 6433 u8 unused_1[4]; 6434 }; 6435 6436 /* hwrm_ring_reset_output (size:128b/16B) */ 6437 struct hwrm_ring_reset_output { 6438 __le16 error_code; 6439 __le16 req_type; 6440 __le16 seq_id; 6441 __le16 resp_len; 6442 u8 push_buffer_index; 6443 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 6444 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 6445 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_LAST RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 6446 u8 unused_0[3]; 6447 u8 consumer_idx[3]; 6448 u8 valid; 6449 }; 6450 6451 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 6452 struct hwrm_ring_aggint_qcaps_input { 6453 __le16 req_type; 6454 __le16 cmpl_ring; 6455 __le16 seq_id; 6456 __le16 target_id; 6457 __le64 resp_addr; 6458 }; 6459 6460 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 6461 struct hwrm_ring_aggint_qcaps_output { 6462 __le16 error_code; 6463 __le16 req_type; 6464 __le16 seq_id; 6465 __le16 resp_len; 6466 __le32 cmpl_params; 6467 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 6468 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 6469 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 6470 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 6471 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 6472 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 6473 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 6474 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 6475 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 6476 __le32 nq_params; 6477 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 6478 __le16 num_cmpl_dma_aggr_min; 6479 __le16 num_cmpl_dma_aggr_max; 6480 __le16 num_cmpl_dma_aggr_during_int_min; 6481 __le16 num_cmpl_dma_aggr_during_int_max; 6482 __le16 cmpl_aggr_dma_tmr_min; 6483 __le16 cmpl_aggr_dma_tmr_max; 6484 __le16 cmpl_aggr_dma_tmr_during_int_min; 6485 __le16 cmpl_aggr_dma_tmr_during_int_max; 6486 __le16 int_lat_tmr_min_min; 6487 __le16 int_lat_tmr_min_max; 6488 __le16 int_lat_tmr_max_min; 6489 __le16 int_lat_tmr_max_max; 6490 __le16 num_cmpl_aggr_int_min; 6491 __le16 num_cmpl_aggr_int_max; 6492 __le16 timer_units; 6493 u8 unused_0[1]; 6494 u8 valid; 6495 }; 6496 6497 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 6498 struct hwrm_ring_cmpl_ring_qaggint_params_input { 6499 __le16 req_type; 6500 __le16 cmpl_ring; 6501 __le16 seq_id; 6502 __le16 target_id; 6503 __le64 resp_addr; 6504 __le16 ring_id; 6505 __le16 flags; 6506 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL 6507 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0 6508 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 6509 u8 unused_0[4]; 6510 }; 6511 6512 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 6513 struct hwrm_ring_cmpl_ring_qaggint_params_output { 6514 __le16 error_code; 6515 __le16 req_type; 6516 __le16 seq_id; 6517 __le16 resp_len; 6518 __le16 flags; 6519 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 6520 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 6521 __le16 num_cmpl_dma_aggr; 6522 __le16 num_cmpl_dma_aggr_during_int; 6523 __le16 cmpl_aggr_dma_tmr; 6524 __le16 cmpl_aggr_dma_tmr_during_int; 6525 __le16 int_lat_tmr_min; 6526 __le16 int_lat_tmr_max; 6527 __le16 num_cmpl_aggr_int; 6528 u8 unused_0[7]; 6529 u8 valid; 6530 }; 6531 6532 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 6533 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 6534 __le16 req_type; 6535 __le16 cmpl_ring; 6536 __le16 seq_id; 6537 __le16 target_id; 6538 __le64 resp_addr; 6539 __le16 ring_id; 6540 __le16 flags; 6541 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 6542 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 6543 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 6544 __le16 num_cmpl_dma_aggr; 6545 __le16 num_cmpl_dma_aggr_during_int; 6546 __le16 cmpl_aggr_dma_tmr; 6547 __le16 cmpl_aggr_dma_tmr_during_int; 6548 __le16 int_lat_tmr_min; 6549 __le16 int_lat_tmr_max; 6550 __le16 num_cmpl_aggr_int; 6551 __le16 enables; 6552 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 6553 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 6554 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 6555 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 6556 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 6557 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 6558 u8 unused_0[4]; 6559 }; 6560 6561 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 6562 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 6563 __le16 error_code; 6564 __le16 req_type; 6565 __le16 seq_id; 6566 __le16 resp_len; 6567 u8 unused_0[7]; 6568 u8 valid; 6569 }; 6570 6571 /* hwrm_ring_grp_alloc_input (size:192b/24B) */ 6572 struct hwrm_ring_grp_alloc_input { 6573 __le16 req_type; 6574 __le16 cmpl_ring; 6575 __le16 seq_id; 6576 __le16 target_id; 6577 __le64 resp_addr; 6578 __le16 cr; 6579 __le16 rr; 6580 __le16 ar; 6581 __le16 sc; 6582 }; 6583 6584 /* hwrm_ring_grp_alloc_output (size:128b/16B) */ 6585 struct hwrm_ring_grp_alloc_output { 6586 __le16 error_code; 6587 __le16 req_type; 6588 __le16 seq_id; 6589 __le16 resp_len; 6590 __le32 ring_group_id; 6591 u8 unused_0[3]; 6592 u8 valid; 6593 }; 6594 6595 /* hwrm_ring_grp_free_input (size:192b/24B) */ 6596 struct hwrm_ring_grp_free_input { 6597 __le16 req_type; 6598 __le16 cmpl_ring; 6599 __le16 seq_id; 6600 __le16 target_id; 6601 __le64 resp_addr; 6602 __le32 ring_group_id; 6603 u8 unused_0[4]; 6604 }; 6605 6606 /* hwrm_ring_grp_free_output (size:128b/16B) */ 6607 struct hwrm_ring_grp_free_output { 6608 __le16 error_code; 6609 __le16 req_type; 6610 __le16 seq_id; 6611 __le16 resp_len; 6612 u8 unused_0[7]; 6613 u8 valid; 6614 }; 6615 6616 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL 6617 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL 6618 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL 6619 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL 6620 6621 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 6622 struct hwrm_cfa_l2_filter_alloc_input { 6623 __le16 req_type; 6624 __le16 cmpl_ring; 6625 __le16 seq_id; 6626 __le16 target_id; 6627 __le64 resp_addr; 6628 __le32 flags; 6629 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 6630 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 6631 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 6632 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 6633 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 6634 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 6635 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 6636 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 6637 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 6638 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 6639 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 6640 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 6641 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 6642 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL 6643 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL 6644 __le32 enables; 6645 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 6646 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 6647 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 6648 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 6649 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 6650 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 6651 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 6652 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 6653 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 6654 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 6655 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 6656 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 6657 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 6658 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 6659 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 6660 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 6661 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 6662 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL 6663 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL 6664 u8 l2_addr[6]; 6665 u8 num_vlans; 6666 u8 t_num_vlans; 6667 u8 l2_addr_mask[6]; 6668 __le16 l2_ovlan; 6669 __le16 l2_ovlan_mask; 6670 __le16 l2_ivlan; 6671 __le16 l2_ivlan_mask; 6672 u8 unused_1[2]; 6673 u8 t_l2_addr[6]; 6674 u8 unused_2[2]; 6675 u8 t_l2_addr_mask[6]; 6676 __le16 t_l2_ovlan; 6677 __le16 t_l2_ovlan_mask; 6678 __le16 t_l2_ivlan; 6679 __le16 t_l2_ivlan_mask; 6680 u8 src_type; 6681 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 6682 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 6683 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 6684 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 6685 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 6686 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 6687 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 6688 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 6689 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 6690 u8 unused_3; 6691 __le32 src_id; 6692 u8 tunnel_type; 6693 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6694 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6695 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6696 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6697 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6698 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6699 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6700 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6701 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6702 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6703 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6704 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6705 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6706 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6707 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6708 u8 unused_4; 6709 __le16 dst_id; 6710 __le16 mirror_vnic_id; 6711 u8 pri_hint; 6712 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 6713 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 6714 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 6715 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 6716 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 6717 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 6718 u8 unused_5; 6719 __le32 unused_6; 6720 __le64 l2_filter_id_hint; 6721 }; 6722 6723 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 6724 struct hwrm_cfa_l2_filter_alloc_output { 6725 __le16 error_code; 6726 __le16 req_type; 6727 __le16 seq_id; 6728 __le16 resp_len; 6729 __le64 l2_filter_id; 6730 __le32 flow_id; 6731 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6732 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6733 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6734 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6735 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6736 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 6737 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6738 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6739 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6740 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 6741 u8 unused_0[3]; 6742 u8 valid; 6743 }; 6744 6745 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 6746 struct hwrm_cfa_l2_filter_free_input { 6747 __le16 req_type; 6748 __le16 cmpl_ring; 6749 __le16 seq_id; 6750 __le16 target_id; 6751 __le64 resp_addr; 6752 __le64 l2_filter_id; 6753 }; 6754 6755 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 6756 struct hwrm_cfa_l2_filter_free_output { 6757 __le16 error_code; 6758 __le16 req_type; 6759 __le16 seq_id; 6760 __le16 resp_len; 6761 u8 unused_0[7]; 6762 u8 valid; 6763 }; 6764 6765 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ 6766 struct hwrm_cfa_l2_filter_cfg_input { 6767 __le16 req_type; 6768 __le16 cmpl_ring; 6769 __le16 seq_id; 6770 __le16 target_id; 6771 __le64 resp_addr; 6772 __le32 flags; 6773 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 6774 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 6775 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 6776 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 6777 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 6778 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 6779 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 6780 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 6781 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 6782 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 6783 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 6784 __le32 enables; 6785 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 6786 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 6787 __le64 l2_filter_id; 6788 __le32 dst_id; 6789 __le32 new_mirror_vnic_id; 6790 }; 6791 6792 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 6793 struct hwrm_cfa_l2_filter_cfg_output { 6794 __le16 error_code; 6795 __le16 req_type; 6796 __le16 seq_id; 6797 __le16 resp_len; 6798 u8 unused_0[7]; 6799 u8 valid; 6800 }; 6801 6802 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 6803 struct hwrm_cfa_l2_set_rx_mask_input { 6804 __le16 req_type; 6805 __le16 cmpl_ring; 6806 __le16 seq_id; 6807 __le16 target_id; 6808 __le64 resp_addr; 6809 __le32 vnic_id; 6810 __le32 mask; 6811 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 6812 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 6813 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 6814 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 6815 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 6816 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 6817 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 6818 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 6819 __le64 mc_tbl_addr; 6820 __le32 num_mc_entries; 6821 u8 unused_0[4]; 6822 __le64 vlan_tag_tbl_addr; 6823 __le32 num_vlan_tags; 6824 u8 unused_1[4]; 6825 }; 6826 6827 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 6828 struct hwrm_cfa_l2_set_rx_mask_output { 6829 __le16 error_code; 6830 __le16 req_type; 6831 __le16 seq_id; 6832 __le16 resp_len; 6833 u8 unused_0[7]; 6834 u8 valid; 6835 }; 6836 6837 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 6838 struct hwrm_cfa_l2_set_rx_mask_cmd_err { 6839 u8 code; 6840 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 6841 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 6842 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 6843 u8 unused_0[7]; 6844 }; 6845 6846 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 6847 struct hwrm_cfa_tunnel_filter_alloc_input { 6848 __le16 req_type; 6849 __le16 cmpl_ring; 6850 __le16 seq_id; 6851 __le16 target_id; 6852 __le64 resp_addr; 6853 __le32 flags; 6854 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 6855 __le32 enables; 6856 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 6857 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 6858 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 6859 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 6860 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 6861 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 6862 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 6863 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 6864 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 6865 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 6866 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 6867 __le64 l2_filter_id; 6868 u8 l2_addr[6]; 6869 __le16 l2_ivlan; 6870 __le32 l3_addr[4]; 6871 __le32 t_l3_addr[4]; 6872 u8 l3_addr_type; 6873 u8 t_l3_addr_type; 6874 u8 tunnel_type; 6875 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6876 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6877 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6878 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6879 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6880 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6881 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6882 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6883 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6884 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6885 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6886 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6887 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6888 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6889 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6890 u8 tunnel_flags; 6891 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 6892 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 6893 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 6894 __le32 vni; 6895 __le32 dst_vnic_id; 6896 __le32 mirror_vnic_id; 6897 }; 6898 6899 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 6900 struct hwrm_cfa_tunnel_filter_alloc_output { 6901 __le16 error_code; 6902 __le16 req_type; 6903 __le16 seq_id; 6904 __le16 resp_len; 6905 __le64 tunnel_filter_id; 6906 __le32 flow_id; 6907 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6908 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6909 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6910 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6911 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6912 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 6913 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6914 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6915 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6916 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 6917 u8 unused_0[3]; 6918 u8 valid; 6919 }; 6920 6921 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 6922 struct hwrm_cfa_tunnel_filter_free_input { 6923 __le16 req_type; 6924 __le16 cmpl_ring; 6925 __le16 seq_id; 6926 __le16 target_id; 6927 __le64 resp_addr; 6928 __le64 tunnel_filter_id; 6929 }; 6930 6931 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 6932 struct hwrm_cfa_tunnel_filter_free_output { 6933 __le16 error_code; 6934 __le16 req_type; 6935 __le16 seq_id; 6936 __le16 resp_len; 6937 u8 unused_0[7]; 6938 u8 valid; 6939 }; 6940 6941 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 6942 struct hwrm_vxlan_ipv4_hdr { 6943 u8 ver_hlen; 6944 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 6945 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 6946 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 6947 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 6948 u8 tos; 6949 __be16 ip_id; 6950 __be16 flags_frag_offset; 6951 u8 ttl; 6952 u8 protocol; 6953 __be32 src_ip_addr; 6954 __be32 dest_ip_addr; 6955 }; 6956 6957 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 6958 struct hwrm_vxlan_ipv6_hdr { 6959 __be32 ver_tc_flow_label; 6960 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 6961 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 6962 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 6963 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 6964 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 6965 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 6966 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 6967 __be16 payload_len; 6968 u8 next_hdr; 6969 u8 ttl; 6970 __be32 src_ip_addr[4]; 6971 __be32 dest_ip_addr[4]; 6972 }; 6973 6974 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 6975 struct hwrm_cfa_encap_data_vxlan { 6976 u8 src_mac_addr[6]; 6977 __le16 unused_0; 6978 u8 dst_mac_addr[6]; 6979 u8 num_vlan_tags; 6980 u8 unused_1; 6981 __be16 ovlan_tpid; 6982 __be16 ovlan_tci; 6983 __be16 ivlan_tpid; 6984 __be16 ivlan_tci; 6985 __le32 l3[10]; 6986 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 6987 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 6988 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 6989 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 6990 __be16 src_port; 6991 __be16 dst_port; 6992 __be32 vni; 6993 u8 hdr_rsvd0[3]; 6994 u8 hdr_rsvd1; 6995 u8 hdr_flags; 6996 u8 unused[3]; 6997 }; 6998 6999 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 7000 struct hwrm_cfa_encap_record_alloc_input { 7001 __le16 req_type; 7002 __le16 cmpl_ring; 7003 __le16 seq_id; 7004 __le16 target_id; 7005 __le64 resp_addr; 7006 __le32 flags; 7007 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7008 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL 7009 u8 encap_type; 7010 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 7011 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 7012 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 7013 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 7014 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 7015 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 7016 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 7017 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 7018 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 7019 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 7020 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 7021 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL 7022 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 7023 u8 unused_0[3]; 7024 __le32 encap_data[20]; 7025 }; 7026 7027 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 7028 struct hwrm_cfa_encap_record_alloc_output { 7029 __le16 error_code; 7030 __le16 req_type; 7031 __le16 seq_id; 7032 __le16 resp_len; 7033 __le32 encap_record_id; 7034 u8 unused_0[3]; 7035 u8 valid; 7036 }; 7037 7038 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 7039 struct hwrm_cfa_encap_record_free_input { 7040 __le16 req_type; 7041 __le16 cmpl_ring; 7042 __le16 seq_id; 7043 __le16 target_id; 7044 __le64 resp_addr; 7045 __le32 encap_record_id; 7046 u8 unused_0[4]; 7047 }; 7048 7049 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 7050 struct hwrm_cfa_encap_record_free_output { 7051 __le16 error_code; 7052 __le16 req_type; 7053 __le16 seq_id; 7054 __le16 resp_len; 7055 u8 unused_0[7]; 7056 u8 valid; 7057 }; 7058 7059 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 7060 struct hwrm_cfa_ntuple_filter_alloc_input { 7061 __le16 req_type; 7062 __le16 cmpl_ring; 7063 __le16 seq_id; 7064 __le16 target_id; 7065 __le64 resp_addr; 7066 __le32 flags; 7067 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7068 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 7069 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 7070 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL 7071 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL 7072 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL 7073 __le32 enables; 7074 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 7075 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 7076 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 7077 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 7078 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 7079 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 7080 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 7081 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 7082 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 7083 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 7084 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 7085 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 7086 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 7087 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 7088 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 7089 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 7090 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 7091 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 7092 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 7093 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL 7094 __le64 l2_filter_id; 7095 u8 src_macaddr[6]; 7096 __be16 ethertype; 7097 u8 ip_addr_type; 7098 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 7099 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 7100 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 7101 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 7102 u8 ip_protocol; 7103 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 7104 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 7105 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 7106 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 7107 __le16 dst_id; 7108 __le16 mirror_vnic_id; 7109 u8 tunnel_type; 7110 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7111 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7112 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7113 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7114 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7115 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7116 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7117 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7118 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7119 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7120 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7121 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7122 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7123 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7124 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7125 u8 pri_hint; 7126 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 7127 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 7128 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 7129 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 7130 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 7131 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 7132 __be32 src_ipaddr[4]; 7133 __be32 src_ipaddr_mask[4]; 7134 __be32 dst_ipaddr[4]; 7135 __be32 dst_ipaddr_mask[4]; 7136 __be16 src_port; 7137 __be16 src_port_mask; 7138 __be16 dst_port; 7139 __be16 dst_port_mask; 7140 __le64 ntuple_filter_id_hint; 7141 }; 7142 7143 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 7144 struct hwrm_cfa_ntuple_filter_alloc_output { 7145 __le16 error_code; 7146 __le16 req_type; 7147 __le16 seq_id; 7148 __le16 resp_len; 7149 __le64 ntuple_filter_id; 7150 __le32 flow_id; 7151 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7152 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7153 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7154 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7155 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7156 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 7157 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7158 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7159 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7160 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7161 u8 unused_0[3]; 7162 u8 valid; 7163 }; 7164 7165 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 7166 struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 7167 u8 code; 7168 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 7169 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 7170 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 7171 u8 unused_0[7]; 7172 }; 7173 7174 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 7175 struct hwrm_cfa_ntuple_filter_free_input { 7176 __le16 req_type; 7177 __le16 cmpl_ring; 7178 __le16 seq_id; 7179 __le16 target_id; 7180 __le64 resp_addr; 7181 __le64 ntuple_filter_id; 7182 }; 7183 7184 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 7185 struct hwrm_cfa_ntuple_filter_free_output { 7186 __le16 error_code; 7187 __le16 req_type; 7188 __le16 seq_id; 7189 __le16 resp_len; 7190 u8 unused_0[7]; 7191 u8 valid; 7192 }; 7193 7194 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 7195 struct hwrm_cfa_ntuple_filter_cfg_input { 7196 __le16 req_type; 7197 __le16 cmpl_ring; 7198 __le16 seq_id; 7199 __le16 target_id; 7200 __le64 resp_addr; 7201 __le32 enables; 7202 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 7203 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 7204 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 7205 __le32 flags; 7206 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL 7207 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL 7208 __le64 ntuple_filter_id; 7209 __le32 new_dst_id; 7210 __le32 new_mirror_vnic_id; 7211 __le16 new_meter_instance_id; 7212 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 7213 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 7214 u8 unused_1[6]; 7215 }; 7216 7217 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 7218 struct hwrm_cfa_ntuple_filter_cfg_output { 7219 __le16 error_code; 7220 __le16 req_type; 7221 __le16 seq_id; 7222 __le16 resp_len; 7223 u8 unused_0[7]; 7224 u8 valid; 7225 }; 7226 7227 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 7228 struct hwrm_cfa_decap_filter_alloc_input { 7229 __le16 req_type; 7230 __le16 cmpl_ring; 7231 __le16 seq_id; 7232 __le16 target_id; 7233 __le64 resp_addr; 7234 __le32 flags; 7235 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 7236 __le32 enables; 7237 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 7238 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 7239 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 7240 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 7241 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 7242 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 7243 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 7244 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 7245 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 7246 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 7247 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 7248 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 7249 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 7250 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 7251 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 7252 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 7253 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 7254 __be32 tunnel_id; 7255 u8 tunnel_type; 7256 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7257 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7258 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7259 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7260 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7261 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7262 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7263 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7264 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7265 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7266 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7267 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7268 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7269 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7270 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7271 u8 unused_0; 7272 __le16 unused_1; 7273 u8 src_macaddr[6]; 7274 u8 unused_2[2]; 7275 u8 dst_macaddr[6]; 7276 __be16 ovlan_vid; 7277 __be16 ivlan_vid; 7278 __be16 t_ovlan_vid; 7279 __be16 t_ivlan_vid; 7280 __be16 ethertype; 7281 u8 ip_addr_type; 7282 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 7283 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 7284 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 7285 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 7286 u8 ip_protocol; 7287 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 7288 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 7289 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 7290 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 7291 __le16 unused_3; 7292 __le32 unused_4; 7293 __be32 src_ipaddr[4]; 7294 __be32 dst_ipaddr[4]; 7295 __be16 src_port; 7296 __be16 dst_port; 7297 __le16 dst_id; 7298 __le16 l2_ctxt_ref_id; 7299 }; 7300 7301 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 7302 struct hwrm_cfa_decap_filter_alloc_output { 7303 __le16 error_code; 7304 __le16 req_type; 7305 __le16 seq_id; 7306 __le16 resp_len; 7307 __le32 decap_filter_id; 7308 u8 unused_0[3]; 7309 u8 valid; 7310 }; 7311 7312 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 7313 struct hwrm_cfa_decap_filter_free_input { 7314 __le16 req_type; 7315 __le16 cmpl_ring; 7316 __le16 seq_id; 7317 __le16 target_id; 7318 __le64 resp_addr; 7319 __le32 decap_filter_id; 7320 u8 unused_0[4]; 7321 }; 7322 7323 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 7324 struct hwrm_cfa_decap_filter_free_output { 7325 __le16 error_code; 7326 __le16 req_type; 7327 __le16 seq_id; 7328 __le16 resp_len; 7329 u8 unused_0[7]; 7330 u8 valid; 7331 }; 7332 7333 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 7334 struct hwrm_cfa_flow_alloc_input { 7335 __le16 req_type; 7336 __le16 cmpl_ring; 7337 __le16 seq_id; 7338 __le16 target_id; 7339 __le64 resp_addr; 7340 __le16 flags; 7341 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 7342 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 7343 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 7344 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 7345 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 7346 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 7347 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 7348 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 7349 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 7350 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 7351 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 7352 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 7353 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 7354 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 7355 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 7356 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 7357 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL 7358 __le16 src_fid; 7359 __le32 tunnel_handle; 7360 __le16 action_flags; 7361 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 7362 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 7363 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 7364 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 7365 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 7366 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 7367 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 7368 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 7369 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 7370 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 7371 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 7372 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL 7373 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL 7374 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL 7375 __le16 dst_fid; 7376 __be16 l2_rewrite_vlan_tpid; 7377 __be16 l2_rewrite_vlan_tci; 7378 __le16 act_meter_id; 7379 __le16 ref_flow_handle; 7380 __be16 ethertype; 7381 __be16 outer_vlan_tci; 7382 __be16 dmac[3]; 7383 __be16 inner_vlan_tci; 7384 __be16 smac[3]; 7385 u8 ip_dst_mask_len; 7386 u8 ip_src_mask_len; 7387 __be32 ip_dst[4]; 7388 __be32 ip_src[4]; 7389 __be16 l4_src_port; 7390 __be16 l4_src_port_mask; 7391 __be16 l4_dst_port; 7392 __be16 l4_dst_port_mask; 7393 __be32 nat_ip_address[4]; 7394 __be16 l2_rewrite_dmac[3]; 7395 __be16 nat_port; 7396 __be16 l2_rewrite_smac[3]; 7397 u8 ip_proto; 7398 u8 tunnel_type; 7399 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7400 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7401 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7402 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7403 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7404 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7405 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7406 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7407 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7408 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7409 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7410 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7411 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7412 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7413 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7414 }; 7415 7416 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 7417 struct hwrm_cfa_flow_alloc_output { 7418 __le16 error_code; 7419 __le16 req_type; 7420 __le16 seq_id; 7421 __le16 resp_len; 7422 __le16 flow_handle; 7423 u8 unused_0[2]; 7424 __le32 flow_id; 7425 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7426 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7427 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7428 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7429 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7430 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT 7431 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7432 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7433 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7434 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX 7435 __le64 ext_flow_handle; 7436 __le32 flow_counter_id; 7437 u8 unused_1[3]; 7438 u8 valid; 7439 }; 7440 7441 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ 7442 struct hwrm_cfa_flow_alloc_cmd_err { 7443 u8 code; 7444 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 7445 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL 7446 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL 7447 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL 7448 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL 7449 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL 7450 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL 7451 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL 7452 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 7453 u8 unused_0[7]; 7454 }; 7455 7456 /* hwrm_cfa_flow_free_input (size:256b/32B) */ 7457 struct hwrm_cfa_flow_free_input { 7458 __le16 req_type; 7459 __le16 cmpl_ring; 7460 __le16 seq_id; 7461 __le16 target_id; 7462 __le64 resp_addr; 7463 __le16 flow_handle; 7464 __le16 unused_0; 7465 __le32 flow_counter_id; 7466 __le64 ext_flow_handle; 7467 }; 7468 7469 /* hwrm_cfa_flow_free_output (size:256b/32B) */ 7470 struct hwrm_cfa_flow_free_output { 7471 __le16 error_code; 7472 __le16 req_type; 7473 __le16 seq_id; 7474 __le16 resp_len; 7475 __le64 packet; 7476 __le64 byte; 7477 u8 unused_0[7]; 7478 u8 valid; 7479 }; 7480 7481 /* hwrm_cfa_flow_info_input (size:256b/32B) */ 7482 struct hwrm_cfa_flow_info_input { 7483 __le16 req_type; 7484 __le16 cmpl_ring; 7485 __le16 seq_id; 7486 __le16 target_id; 7487 __le64 resp_addr; 7488 __le16 flow_handle; 7489 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL 7490 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT 0 7491 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL 7492 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL 7493 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL 7494 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL 7495 u8 unused_0[6]; 7496 __le64 ext_flow_handle; 7497 }; 7498 7499 /* hwrm_cfa_flow_info_output (size:5632b/704B) */ 7500 struct hwrm_cfa_flow_info_output { 7501 __le16 error_code; 7502 __le16 req_type; 7503 __le16 seq_id; 7504 __le16 resp_len; 7505 u8 flags; 7506 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL 7507 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL 7508 u8 profile; 7509 __le16 src_fid; 7510 __le16 dst_fid; 7511 __le16 l2_ctxt_id; 7512 __le64 em_info; 7513 __le64 tcam_info; 7514 __le64 vfp_tcam_info; 7515 __le16 ar_id; 7516 __le16 flow_handle; 7517 __le32 tunnel_handle; 7518 __le16 flow_timer; 7519 u8 unused_0[6]; 7520 __le32 flow_key_data[130]; 7521 __le32 flow_action_info[30]; 7522 u8 unused_1[7]; 7523 u8 valid; 7524 }; 7525 7526 /* hwrm_cfa_flow_stats_input (size:640b/80B) */ 7527 struct hwrm_cfa_flow_stats_input { 7528 __le16 req_type; 7529 __le16 cmpl_ring; 7530 __le16 seq_id; 7531 __le16 target_id; 7532 __le64 resp_addr; 7533 __le16 num_flows; 7534 __le16 flow_handle_0; 7535 __le16 flow_handle_1; 7536 __le16 flow_handle_2; 7537 __le16 flow_handle_3; 7538 __le16 flow_handle_4; 7539 __le16 flow_handle_5; 7540 __le16 flow_handle_6; 7541 __le16 flow_handle_7; 7542 __le16 flow_handle_8; 7543 __le16 flow_handle_9; 7544 u8 unused_0[2]; 7545 __le32 flow_id_0; 7546 __le32 flow_id_1; 7547 __le32 flow_id_2; 7548 __le32 flow_id_3; 7549 __le32 flow_id_4; 7550 __le32 flow_id_5; 7551 __le32 flow_id_6; 7552 __le32 flow_id_7; 7553 __le32 flow_id_8; 7554 __le32 flow_id_9; 7555 }; 7556 7557 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 7558 struct hwrm_cfa_flow_stats_output { 7559 __le16 error_code; 7560 __le16 req_type; 7561 __le16 seq_id; 7562 __le16 resp_len; 7563 __le64 packet_0; 7564 __le64 packet_1; 7565 __le64 packet_2; 7566 __le64 packet_3; 7567 __le64 packet_4; 7568 __le64 packet_5; 7569 __le64 packet_6; 7570 __le64 packet_7; 7571 __le64 packet_8; 7572 __le64 packet_9; 7573 __le64 byte_0; 7574 __le64 byte_1; 7575 __le64 byte_2; 7576 __le64 byte_3; 7577 __le64 byte_4; 7578 __le64 byte_5; 7579 __le64 byte_6; 7580 __le64 byte_7; 7581 __le64 byte_8; 7582 __le64 byte_9; 7583 u8 unused_0[7]; 7584 u8 valid; 7585 }; 7586 7587 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 7588 struct hwrm_cfa_vfr_alloc_input { 7589 __le16 req_type; 7590 __le16 cmpl_ring; 7591 __le16 seq_id; 7592 __le16 target_id; 7593 __le64 resp_addr; 7594 __le16 vf_id; 7595 __le16 reserved; 7596 u8 unused_0[4]; 7597 char vfr_name[32]; 7598 }; 7599 7600 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 7601 struct hwrm_cfa_vfr_alloc_output { 7602 __le16 error_code; 7603 __le16 req_type; 7604 __le16 seq_id; 7605 __le16 resp_len; 7606 __le16 rx_cfa_code; 7607 __le16 tx_cfa_action; 7608 u8 unused_0[3]; 7609 u8 valid; 7610 }; 7611 7612 /* hwrm_cfa_vfr_free_input (size:448b/56B) */ 7613 struct hwrm_cfa_vfr_free_input { 7614 __le16 req_type; 7615 __le16 cmpl_ring; 7616 __le16 seq_id; 7617 __le16 target_id; 7618 __le64 resp_addr; 7619 char vfr_name[32]; 7620 __le16 vf_id; 7621 __le16 reserved; 7622 u8 unused_0[4]; 7623 }; 7624 7625 /* hwrm_cfa_vfr_free_output (size:128b/16B) */ 7626 struct hwrm_cfa_vfr_free_output { 7627 __le16 error_code; 7628 __le16 req_type; 7629 __le16 seq_id; 7630 __le16 resp_len; 7631 u8 unused_0[7]; 7632 u8 valid; 7633 }; 7634 7635 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ 7636 struct hwrm_cfa_eem_qcaps_input { 7637 __le16 req_type; 7638 __le16 cmpl_ring; 7639 __le16 seq_id; 7640 __le16 target_id; 7641 __le64 resp_addr; 7642 __le32 flags; 7643 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL 7644 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL 7645 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 7646 __le32 unused_0; 7647 }; 7648 7649 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ 7650 struct hwrm_cfa_eem_qcaps_output { 7651 __le16 error_code; 7652 __le16 req_type; 7653 __le16 seq_id; 7654 __le16 resp_len; 7655 __le32 flags; 7656 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL 7657 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL 7658 #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL 7659 #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL 7660 __le32 unused_0; 7661 __le32 supported; 7662 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL 7663 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL 7664 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL 7665 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL 7666 #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL 7667 __le32 max_entries_supported; 7668 __le16 key_entry_size; 7669 __le16 record_entry_size; 7670 __le16 efc_entry_size; 7671 __le16 fid_entry_size; 7672 u8 unused_1[7]; 7673 u8 valid; 7674 }; 7675 7676 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */ 7677 struct hwrm_cfa_eem_cfg_input { 7678 __le16 req_type; 7679 __le16 cmpl_ring; 7680 __le16 seq_id; 7681 __le16 target_id; 7682 __le64 resp_addr; 7683 __le32 flags; 7684 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL 7685 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL 7686 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 7687 #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL 7688 __le16 group_id; 7689 __le16 unused_0; 7690 __le32 num_entries; 7691 __le32 unused_1; 7692 __le16 key0_ctx_id; 7693 __le16 key1_ctx_id; 7694 __le16 record_ctx_id; 7695 __le16 efc_ctx_id; 7696 __le16 fid_ctx_id; 7697 __le16 unused_2; 7698 __le32 unused_3; 7699 }; 7700 7701 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */ 7702 struct hwrm_cfa_eem_cfg_output { 7703 __le16 error_code; 7704 __le16 req_type; 7705 __le16 seq_id; 7706 __le16 resp_len; 7707 u8 unused_0[7]; 7708 u8 valid; 7709 }; 7710 7711 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ 7712 struct hwrm_cfa_eem_qcfg_input { 7713 __le16 req_type; 7714 __le16 cmpl_ring; 7715 __le16 seq_id; 7716 __le16 target_id; 7717 __le64 resp_addr; 7718 __le32 flags; 7719 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL 7720 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL 7721 __le32 unused_0; 7722 }; 7723 7724 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ 7725 struct hwrm_cfa_eem_qcfg_output { 7726 __le16 error_code; 7727 __le16 req_type; 7728 __le16 seq_id; 7729 __le16 resp_len; 7730 __le32 flags; 7731 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL 7732 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL 7733 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL 7734 __le32 num_entries; 7735 __le16 key0_ctx_id; 7736 __le16 key1_ctx_id; 7737 __le16 record_ctx_id; 7738 __le16 efc_ctx_id; 7739 __le16 fid_ctx_id; 7740 u8 unused_2[5]; 7741 u8 valid; 7742 }; 7743 7744 /* hwrm_cfa_eem_op_input (size:192b/24B) */ 7745 struct hwrm_cfa_eem_op_input { 7746 __le16 req_type; 7747 __le16 cmpl_ring; 7748 __le16 seq_id; 7749 __le16 target_id; 7750 __le64 resp_addr; 7751 __le32 flags; 7752 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL 7753 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL 7754 __le16 unused_0; 7755 __le16 op; 7756 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL 7757 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL 7758 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL 7759 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL 7760 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP 7761 }; 7762 7763 /* hwrm_cfa_eem_op_output (size:128b/16B) */ 7764 struct hwrm_cfa_eem_op_output { 7765 __le16 error_code; 7766 __le16 req_type; 7767 __le16 seq_id; 7768 __le16 resp_len; 7769 u8 unused_0[7]; 7770 u8 valid; 7771 }; 7772 7773 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ 7774 struct hwrm_cfa_adv_flow_mgnt_qcaps_input { 7775 __le16 req_type; 7776 __le16 cmpl_ring; 7777 __le16 seq_id; 7778 __le16 target_id; 7779 __le64 resp_addr; 7780 __le32 unused_0[4]; 7781 }; 7782 7783 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ 7784 struct hwrm_cfa_adv_flow_mgnt_qcaps_output { 7785 __le16 error_code; 7786 __le16 req_type; 7787 __le16 seq_id; 7788 __le16 resp_len; 7789 __le32 flags; 7790 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL 7791 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL 7792 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL 7793 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL 7794 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL 7795 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL 7796 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL 7797 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL 7798 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL 7799 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL 7800 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL 7801 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL 7802 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL 7803 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL 7804 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL 7805 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TRUFLOW_CAPABLE 0x8000UL 7806 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED 0x10000UL 7807 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_LAG_SUPPORTED 0x20000UL 7808 u8 unused_0[3]; 7809 u8 valid; 7810 }; 7811 7812 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 7813 struct hwrm_tunnel_dst_port_query_input { 7814 __le16 req_type; 7815 __le16 cmpl_ring; 7816 __le16 seq_id; 7817 __le16 target_id; 7818 __le64 resp_addr; 7819 u8 tunnel_type; 7820 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7821 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7822 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7823 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7824 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7825 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7826 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7827 u8 unused_0[7]; 7828 }; 7829 7830 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 7831 struct hwrm_tunnel_dst_port_query_output { 7832 __le16 error_code; 7833 __le16 req_type; 7834 __le16 seq_id; 7835 __le16 resp_len; 7836 __le16 tunnel_dst_port_id; 7837 __be16 tunnel_dst_port_val; 7838 u8 unused_0[3]; 7839 u8 valid; 7840 }; 7841 7842 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 7843 struct hwrm_tunnel_dst_port_alloc_input { 7844 __le16 req_type; 7845 __le16 cmpl_ring; 7846 __le16 seq_id; 7847 __le16 target_id; 7848 __le64 resp_addr; 7849 u8 tunnel_type; 7850 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7851 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7852 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7853 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7854 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7855 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7856 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7857 u8 unused_0; 7858 __be16 tunnel_dst_port_val; 7859 u8 unused_1[4]; 7860 }; 7861 7862 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 7863 struct hwrm_tunnel_dst_port_alloc_output { 7864 __le16 error_code; 7865 __le16 req_type; 7866 __le16 seq_id; 7867 __le16 resp_len; 7868 __le16 tunnel_dst_port_id; 7869 u8 unused_0[5]; 7870 u8 valid; 7871 }; 7872 7873 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 7874 struct hwrm_tunnel_dst_port_free_input { 7875 __le16 req_type; 7876 __le16 cmpl_ring; 7877 __le16 seq_id; 7878 __le16 target_id; 7879 __le64 resp_addr; 7880 u8 tunnel_type; 7881 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7882 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7883 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7884 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7885 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7886 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7887 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7888 u8 unused_0; 7889 __le16 tunnel_dst_port_id; 7890 u8 unused_1[4]; 7891 }; 7892 7893 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 7894 struct hwrm_tunnel_dst_port_free_output { 7895 __le16 error_code; 7896 __le16 req_type; 7897 __le16 seq_id; 7898 __le16 resp_len; 7899 u8 unused_1[7]; 7900 u8 valid; 7901 }; 7902 7903 /* ctx_hw_stats (size:1280b/160B) */ 7904 struct ctx_hw_stats { 7905 __le64 rx_ucast_pkts; 7906 __le64 rx_mcast_pkts; 7907 __le64 rx_bcast_pkts; 7908 __le64 rx_discard_pkts; 7909 __le64 rx_error_pkts; 7910 __le64 rx_ucast_bytes; 7911 __le64 rx_mcast_bytes; 7912 __le64 rx_bcast_bytes; 7913 __le64 tx_ucast_pkts; 7914 __le64 tx_mcast_pkts; 7915 __le64 tx_bcast_pkts; 7916 __le64 tx_error_pkts; 7917 __le64 tx_discard_pkts; 7918 __le64 tx_ucast_bytes; 7919 __le64 tx_mcast_bytes; 7920 __le64 tx_bcast_bytes; 7921 __le64 tpa_pkts; 7922 __le64 tpa_bytes; 7923 __le64 tpa_events; 7924 __le64 tpa_aborts; 7925 }; 7926 7927 /* ctx_hw_stats_ext (size:1408b/176B) */ 7928 struct ctx_hw_stats_ext { 7929 __le64 rx_ucast_pkts; 7930 __le64 rx_mcast_pkts; 7931 __le64 rx_bcast_pkts; 7932 __le64 rx_discard_pkts; 7933 __le64 rx_error_pkts; 7934 __le64 rx_ucast_bytes; 7935 __le64 rx_mcast_bytes; 7936 __le64 rx_bcast_bytes; 7937 __le64 tx_ucast_pkts; 7938 __le64 tx_mcast_pkts; 7939 __le64 tx_bcast_pkts; 7940 __le64 tx_error_pkts; 7941 __le64 tx_discard_pkts; 7942 __le64 tx_ucast_bytes; 7943 __le64 tx_mcast_bytes; 7944 __le64 tx_bcast_bytes; 7945 __le64 rx_tpa_eligible_pkt; 7946 __le64 rx_tpa_eligible_bytes; 7947 __le64 rx_tpa_pkt; 7948 __le64 rx_tpa_bytes; 7949 __le64 rx_tpa_errors; 7950 __le64 rx_tpa_events; 7951 }; 7952 7953 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */ 7954 struct hwrm_stat_ctx_alloc_input { 7955 __le16 req_type; 7956 __le16 cmpl_ring; 7957 __le16 seq_id; 7958 __le16 target_id; 7959 __le64 resp_addr; 7960 __le64 stats_dma_addr; 7961 __le32 update_period_ms; 7962 u8 stat_ctx_flags; 7963 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 7964 u8 unused_0; 7965 __le16 stats_dma_length; 7966 }; 7967 7968 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 7969 struct hwrm_stat_ctx_alloc_output { 7970 __le16 error_code; 7971 __le16 req_type; 7972 __le16 seq_id; 7973 __le16 resp_len; 7974 __le32 stat_ctx_id; 7975 u8 unused_0[3]; 7976 u8 valid; 7977 }; 7978 7979 /* hwrm_stat_ctx_free_input (size:192b/24B) */ 7980 struct hwrm_stat_ctx_free_input { 7981 __le16 req_type; 7982 __le16 cmpl_ring; 7983 __le16 seq_id; 7984 __le16 target_id; 7985 __le64 resp_addr; 7986 __le32 stat_ctx_id; 7987 u8 unused_0[4]; 7988 }; 7989 7990 /* hwrm_stat_ctx_free_output (size:128b/16B) */ 7991 struct hwrm_stat_ctx_free_output { 7992 __le16 error_code; 7993 __le16 req_type; 7994 __le16 seq_id; 7995 __le16 resp_len; 7996 __le32 stat_ctx_id; 7997 u8 unused_0[3]; 7998 u8 valid; 7999 }; 8000 8001 /* hwrm_stat_ctx_query_input (size:192b/24B) */ 8002 struct hwrm_stat_ctx_query_input { 8003 __le16 req_type; 8004 __le16 cmpl_ring; 8005 __le16 seq_id; 8006 __le16 target_id; 8007 __le64 resp_addr; 8008 __le32 stat_ctx_id; 8009 u8 flags; 8010 #define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 8011 u8 unused_0[3]; 8012 }; 8013 8014 /* hwrm_stat_ctx_query_output (size:1408b/176B) */ 8015 struct hwrm_stat_ctx_query_output { 8016 __le16 error_code; 8017 __le16 req_type; 8018 __le16 seq_id; 8019 __le16 resp_len; 8020 __le64 tx_ucast_pkts; 8021 __le64 tx_mcast_pkts; 8022 __le64 tx_bcast_pkts; 8023 __le64 tx_discard_pkts; 8024 __le64 tx_error_pkts; 8025 __le64 tx_ucast_bytes; 8026 __le64 tx_mcast_bytes; 8027 __le64 tx_bcast_bytes; 8028 __le64 rx_ucast_pkts; 8029 __le64 rx_mcast_pkts; 8030 __le64 rx_bcast_pkts; 8031 __le64 rx_discard_pkts; 8032 __le64 rx_error_pkts; 8033 __le64 rx_ucast_bytes; 8034 __le64 rx_mcast_bytes; 8035 __le64 rx_bcast_bytes; 8036 __le64 rx_agg_pkts; 8037 __le64 rx_agg_bytes; 8038 __le64 rx_agg_events; 8039 __le64 rx_agg_aborts; 8040 u8 unused_0[7]; 8041 u8 valid; 8042 }; 8043 8044 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ 8045 struct hwrm_stat_ext_ctx_query_input { 8046 __le16 req_type; 8047 __le16 cmpl_ring; 8048 __le16 seq_id; 8049 __le16 target_id; 8050 __le64 resp_addr; 8051 __le32 stat_ctx_id; 8052 u8 flags; 8053 #define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 8054 u8 unused_0[3]; 8055 }; 8056 8057 /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */ 8058 struct hwrm_stat_ext_ctx_query_output { 8059 __le16 error_code; 8060 __le16 req_type; 8061 __le16 seq_id; 8062 __le16 resp_len; 8063 __le64 rx_ucast_pkts; 8064 __le64 rx_mcast_pkts; 8065 __le64 rx_bcast_pkts; 8066 __le64 rx_discard_pkts; 8067 __le64 rx_error_pkts; 8068 __le64 rx_ucast_bytes; 8069 __le64 rx_mcast_bytes; 8070 __le64 rx_bcast_bytes; 8071 __le64 tx_ucast_pkts; 8072 __le64 tx_mcast_pkts; 8073 __le64 tx_bcast_pkts; 8074 __le64 tx_error_pkts; 8075 __le64 tx_discard_pkts; 8076 __le64 tx_ucast_bytes; 8077 __le64 tx_mcast_bytes; 8078 __le64 tx_bcast_bytes; 8079 __le64 rx_tpa_eligible_pkt; 8080 __le64 rx_tpa_eligible_bytes; 8081 __le64 rx_tpa_pkt; 8082 __le64 rx_tpa_bytes; 8083 __le64 rx_tpa_errors; 8084 __le64 rx_tpa_events; 8085 u8 unused_0[7]; 8086 u8 valid; 8087 }; 8088 8089 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 8090 struct hwrm_stat_ctx_clr_stats_input { 8091 __le16 req_type; 8092 __le16 cmpl_ring; 8093 __le16 seq_id; 8094 __le16 target_id; 8095 __le64 resp_addr; 8096 __le32 stat_ctx_id; 8097 u8 unused_0[4]; 8098 }; 8099 8100 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 8101 struct hwrm_stat_ctx_clr_stats_output { 8102 __le16 error_code; 8103 __le16 req_type; 8104 __le16 seq_id; 8105 __le16 resp_len; 8106 u8 unused_0[7]; 8107 u8 valid; 8108 }; 8109 8110 /* hwrm_pcie_qstats_input (size:256b/32B) */ 8111 struct hwrm_pcie_qstats_input { 8112 __le16 req_type; 8113 __le16 cmpl_ring; 8114 __le16 seq_id; 8115 __le16 target_id; 8116 __le64 resp_addr; 8117 __le16 pcie_stat_size; 8118 u8 unused_0[6]; 8119 __le64 pcie_stat_host_addr; 8120 }; 8121 8122 /* hwrm_pcie_qstats_output (size:128b/16B) */ 8123 struct hwrm_pcie_qstats_output { 8124 __le16 error_code; 8125 __le16 req_type; 8126 __le16 seq_id; 8127 __le16 resp_len; 8128 __le16 pcie_stat_size; 8129 u8 unused_0[5]; 8130 u8 valid; 8131 }; 8132 8133 /* pcie_ctx_hw_stats (size:768b/96B) */ 8134 struct pcie_ctx_hw_stats { 8135 __le64 pcie_pl_signal_integrity; 8136 __le64 pcie_dl_signal_integrity; 8137 __le64 pcie_tl_signal_integrity; 8138 __le64 pcie_link_integrity; 8139 __le64 pcie_tx_traffic_rate; 8140 __le64 pcie_rx_traffic_rate; 8141 __le64 pcie_tx_dllp_statistics; 8142 __le64 pcie_rx_dllp_statistics; 8143 __le64 pcie_equalization_time; 8144 __le32 pcie_ltssm_histogram[4]; 8145 __le64 pcie_recovery_histogram; 8146 }; 8147 8148 /* hwrm_fw_reset_input (size:192b/24B) */ 8149 struct hwrm_fw_reset_input { 8150 __le16 req_type; 8151 __le16 cmpl_ring; 8152 __le16 seq_id; 8153 __le16 target_id; 8154 __le64 resp_addr; 8155 u8 embedded_proc_type; 8156 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 8157 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 8158 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 8159 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 8160 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 8161 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 8162 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 8163 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 8164 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL 8165 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 8166 u8 selfrst_status; 8167 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 8168 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 8169 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 8170 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 8171 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 8172 u8 host_idx; 8173 u8 flags; 8174 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL 8175 u8 unused_0[4]; 8176 }; 8177 8178 /* hwrm_fw_reset_output (size:128b/16B) */ 8179 struct hwrm_fw_reset_output { 8180 __le16 error_code; 8181 __le16 req_type; 8182 __le16 seq_id; 8183 __le16 resp_len; 8184 u8 selfrst_status; 8185 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 8186 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 8187 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 8188 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 8189 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 8190 u8 unused_0[6]; 8191 u8 valid; 8192 }; 8193 8194 /* hwrm_fw_qstatus_input (size:192b/24B) */ 8195 struct hwrm_fw_qstatus_input { 8196 __le16 req_type; 8197 __le16 cmpl_ring; 8198 __le16 seq_id; 8199 __le16 target_id; 8200 __le64 resp_addr; 8201 u8 embedded_proc_type; 8202 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 8203 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 8204 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 8205 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 8206 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 8207 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 8208 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 8209 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 8210 u8 unused_0[7]; 8211 }; 8212 8213 /* hwrm_fw_qstatus_output (size:128b/16B) */ 8214 struct hwrm_fw_qstatus_output { 8215 __le16 error_code; 8216 __le16 req_type; 8217 __le16 seq_id; 8218 __le16 resp_len; 8219 u8 selfrst_status; 8220 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 8221 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 8222 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 8223 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL 8224 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 8225 u8 nvm_option_action_status; 8226 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_NONE 0x0UL 8227 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_HOTRESET 0x1UL 8228 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_WARMBOOT 0x2UL 8229 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 0x3UL 8230 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_LAST FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 8231 u8 unused_0[5]; 8232 u8 valid; 8233 }; 8234 8235 /* hwrm_fw_set_time_input (size:256b/32B) */ 8236 struct hwrm_fw_set_time_input { 8237 __le16 req_type; 8238 __le16 cmpl_ring; 8239 __le16 seq_id; 8240 __le16 target_id; 8241 __le64 resp_addr; 8242 __le16 year; 8243 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 8244 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 8245 u8 month; 8246 u8 day; 8247 u8 hour; 8248 u8 minute; 8249 u8 second; 8250 u8 unused_0; 8251 __le16 millisecond; 8252 __le16 zone; 8253 #define FW_SET_TIME_REQ_ZONE_UTC 0 8254 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535 8255 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 8256 u8 unused_1[4]; 8257 }; 8258 8259 /* hwrm_fw_set_time_output (size:128b/16B) */ 8260 struct hwrm_fw_set_time_output { 8261 __le16 error_code; 8262 __le16 req_type; 8263 __le16 seq_id; 8264 __le16 resp_len; 8265 u8 unused_0[7]; 8266 u8 valid; 8267 }; 8268 8269 /* hwrm_struct_hdr (size:128b/16B) */ 8270 struct hwrm_struct_hdr { 8271 __le16 struct_id; 8272 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 8273 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 8274 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 8275 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 8276 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 8277 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 8278 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 8279 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL 8280 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 8281 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 8282 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 8283 #define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL 8284 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 8285 __le16 len; 8286 u8 version; 8287 u8 count; 8288 __le16 subtype; 8289 __le16 next_offset; 8290 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 8291 u8 unused_0[6]; 8292 }; 8293 8294 /* hwrm_struct_data_dcbx_app (size:64b/8B) */ 8295 struct hwrm_struct_data_dcbx_app { 8296 __be16 protocol_id; 8297 u8 protocol_selector; 8298 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 8299 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 8300 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 8301 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 8302 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 8303 u8 priority; 8304 u8 valid; 8305 u8 unused_0[3]; 8306 }; 8307 8308 /* hwrm_fw_set_structured_data_input (size:256b/32B) */ 8309 struct hwrm_fw_set_structured_data_input { 8310 __le16 req_type; 8311 __le16 cmpl_ring; 8312 __le16 seq_id; 8313 __le16 target_id; 8314 __le64 resp_addr; 8315 __le64 src_data_addr; 8316 __le16 data_len; 8317 u8 hdr_cnt; 8318 u8 unused_0[5]; 8319 }; 8320 8321 /* hwrm_fw_set_structured_data_output (size:128b/16B) */ 8322 struct hwrm_fw_set_structured_data_output { 8323 __le16 error_code; 8324 __le16 req_type; 8325 __le16 seq_id; 8326 __le16 resp_len; 8327 u8 unused_0[7]; 8328 u8 valid; 8329 }; 8330 8331 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 8332 struct hwrm_fw_set_structured_data_cmd_err { 8333 u8 code; 8334 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 8335 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 8336 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 8337 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 8338 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 8339 u8 unused_0[7]; 8340 }; 8341 8342 /* hwrm_fw_get_structured_data_input (size:256b/32B) */ 8343 struct hwrm_fw_get_structured_data_input { 8344 __le16 req_type; 8345 __le16 cmpl_ring; 8346 __le16 seq_id; 8347 __le16 target_id; 8348 __le64 resp_addr; 8349 __le64 dest_data_addr; 8350 __le16 data_len; 8351 __le16 structure_id; 8352 __le16 subtype; 8353 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 8354 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 8355 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 8356 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 8357 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 8358 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 8359 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 8360 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 8361 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 8362 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 8363 u8 count; 8364 u8 unused_0; 8365 }; 8366 8367 /* hwrm_fw_get_structured_data_output (size:128b/16B) */ 8368 struct hwrm_fw_get_structured_data_output { 8369 __le16 error_code; 8370 __le16 req_type; 8371 __le16 seq_id; 8372 __le16 resp_len; 8373 u8 hdr_cnt; 8374 u8 unused_0[6]; 8375 u8 valid; 8376 }; 8377 8378 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 8379 struct hwrm_fw_get_structured_data_cmd_err { 8380 u8 code; 8381 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 8382 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 8383 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 8384 u8 unused_0[7]; 8385 }; 8386 8387 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 8388 struct hwrm_exec_fwd_resp_input { 8389 __le16 req_type; 8390 __le16 cmpl_ring; 8391 __le16 seq_id; 8392 __le16 target_id; 8393 __le64 resp_addr; 8394 __le32 encap_request[26]; 8395 __le16 encap_resp_target_id; 8396 u8 unused_0[6]; 8397 }; 8398 8399 /* hwrm_exec_fwd_resp_output (size:128b/16B) */ 8400 struct hwrm_exec_fwd_resp_output { 8401 __le16 error_code; 8402 __le16 req_type; 8403 __le16 seq_id; 8404 __le16 resp_len; 8405 u8 unused_0[7]; 8406 u8 valid; 8407 }; 8408 8409 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 8410 struct hwrm_reject_fwd_resp_input { 8411 __le16 req_type; 8412 __le16 cmpl_ring; 8413 __le16 seq_id; 8414 __le16 target_id; 8415 __le64 resp_addr; 8416 __le32 encap_request[26]; 8417 __le16 encap_resp_target_id; 8418 u8 unused_0[6]; 8419 }; 8420 8421 /* hwrm_reject_fwd_resp_output (size:128b/16B) */ 8422 struct hwrm_reject_fwd_resp_output { 8423 __le16 error_code; 8424 __le16 req_type; 8425 __le16 seq_id; 8426 __le16 resp_len; 8427 u8 unused_0[7]; 8428 u8 valid; 8429 }; 8430 8431 /* hwrm_fwd_resp_input (size:1024b/128B) */ 8432 struct hwrm_fwd_resp_input { 8433 __le16 req_type; 8434 __le16 cmpl_ring; 8435 __le16 seq_id; 8436 __le16 target_id; 8437 __le64 resp_addr; 8438 __le16 encap_resp_target_id; 8439 __le16 encap_resp_cmpl_ring; 8440 __le16 encap_resp_len; 8441 u8 unused_0; 8442 u8 unused_1; 8443 __le64 encap_resp_addr; 8444 __le32 encap_resp[24]; 8445 }; 8446 8447 /* hwrm_fwd_resp_output (size:128b/16B) */ 8448 struct hwrm_fwd_resp_output { 8449 __le16 error_code; 8450 __le16 req_type; 8451 __le16 seq_id; 8452 __le16 resp_len; 8453 u8 unused_0[7]; 8454 u8 valid; 8455 }; 8456 8457 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 8458 struct hwrm_fwd_async_event_cmpl_input { 8459 __le16 req_type; 8460 __le16 cmpl_ring; 8461 __le16 seq_id; 8462 __le16 target_id; 8463 __le64 resp_addr; 8464 __le16 encap_async_event_target_id; 8465 u8 unused_0[6]; 8466 __le32 encap_async_event_cmpl[4]; 8467 }; 8468 8469 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 8470 struct hwrm_fwd_async_event_cmpl_output { 8471 __le16 error_code; 8472 __le16 req_type; 8473 __le16 seq_id; 8474 __le16 resp_len; 8475 u8 unused_0[7]; 8476 u8 valid; 8477 }; 8478 8479 /* hwrm_temp_monitor_query_input (size:128b/16B) */ 8480 struct hwrm_temp_monitor_query_input { 8481 __le16 req_type; 8482 __le16 cmpl_ring; 8483 __le16 seq_id; 8484 __le16 target_id; 8485 __le64 resp_addr; 8486 }; 8487 8488 /* hwrm_temp_monitor_query_output (size:128b/16B) */ 8489 struct hwrm_temp_monitor_query_output { 8490 __le16 error_code; 8491 __le16 req_type; 8492 __le16 seq_id; 8493 __le16 resp_len; 8494 u8 temp; 8495 u8 phy_temp; 8496 u8 om_temp; 8497 u8 flags; 8498 #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL 8499 #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL 8500 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL 8501 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL 8502 #define TEMP_MONITOR_QUERY_RESP_FLAGS_EXT_TEMP_FIELDS_AVAILABLE 0x10UL 8503 u8 temp2; 8504 u8 phy_temp2; 8505 u8 om_temp2; 8506 u8 valid; 8507 }; 8508 8509 /* hwrm_wol_filter_alloc_input (size:512b/64B) */ 8510 struct hwrm_wol_filter_alloc_input { 8511 __le16 req_type; 8512 __le16 cmpl_ring; 8513 __le16 seq_id; 8514 __le16 target_id; 8515 __le64 resp_addr; 8516 __le32 flags; 8517 __le32 enables; 8518 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 8519 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 8520 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 8521 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 8522 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 8523 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 8524 __le16 port_id; 8525 u8 wol_type; 8526 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 8527 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 8528 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 8529 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 8530 u8 unused_0[5]; 8531 u8 mac_address[6]; 8532 __le16 pattern_offset; 8533 __le16 pattern_buf_size; 8534 __le16 pattern_mask_size; 8535 u8 unused_1[4]; 8536 __le64 pattern_buf_addr; 8537 __le64 pattern_mask_addr; 8538 }; 8539 8540 /* hwrm_wol_filter_alloc_output (size:128b/16B) */ 8541 struct hwrm_wol_filter_alloc_output { 8542 __le16 error_code; 8543 __le16 req_type; 8544 __le16 seq_id; 8545 __le16 resp_len; 8546 u8 wol_filter_id; 8547 u8 unused_0[6]; 8548 u8 valid; 8549 }; 8550 8551 /* hwrm_wol_filter_free_input (size:256b/32B) */ 8552 struct hwrm_wol_filter_free_input { 8553 __le16 req_type; 8554 __le16 cmpl_ring; 8555 __le16 seq_id; 8556 __le16 target_id; 8557 __le64 resp_addr; 8558 __le32 flags; 8559 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 8560 __le32 enables; 8561 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 8562 __le16 port_id; 8563 u8 wol_filter_id; 8564 u8 unused_0[5]; 8565 }; 8566 8567 /* hwrm_wol_filter_free_output (size:128b/16B) */ 8568 struct hwrm_wol_filter_free_output { 8569 __le16 error_code; 8570 __le16 req_type; 8571 __le16 seq_id; 8572 __le16 resp_len; 8573 u8 unused_0[7]; 8574 u8 valid; 8575 }; 8576 8577 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 8578 struct hwrm_wol_filter_qcfg_input { 8579 __le16 req_type; 8580 __le16 cmpl_ring; 8581 __le16 seq_id; 8582 __le16 target_id; 8583 __le64 resp_addr; 8584 __le16 port_id; 8585 __le16 handle; 8586 u8 unused_0[4]; 8587 __le64 pattern_buf_addr; 8588 __le16 pattern_buf_size; 8589 u8 unused_1[6]; 8590 __le64 pattern_mask_addr; 8591 __le16 pattern_mask_size; 8592 u8 unused_2[6]; 8593 }; 8594 8595 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 8596 struct hwrm_wol_filter_qcfg_output { 8597 __le16 error_code; 8598 __le16 req_type; 8599 __le16 seq_id; 8600 __le16 resp_len; 8601 __le16 next_handle; 8602 u8 wol_filter_id; 8603 u8 wol_type; 8604 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 8605 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 8606 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 8607 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 8608 __le32 unused_0; 8609 u8 mac_address[6]; 8610 __le16 pattern_offset; 8611 __le16 pattern_size; 8612 __le16 pattern_mask_size; 8613 u8 unused_1[3]; 8614 u8 valid; 8615 }; 8616 8617 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 8618 struct hwrm_wol_reason_qcfg_input { 8619 __le16 req_type; 8620 __le16 cmpl_ring; 8621 __le16 seq_id; 8622 __le16 target_id; 8623 __le64 resp_addr; 8624 __le16 port_id; 8625 u8 unused_0[6]; 8626 __le64 wol_pkt_buf_addr; 8627 __le16 wol_pkt_buf_size; 8628 u8 unused_1[6]; 8629 }; 8630 8631 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 8632 struct hwrm_wol_reason_qcfg_output { 8633 __le16 error_code; 8634 __le16 req_type; 8635 __le16 seq_id; 8636 __le16 resp_len; 8637 u8 wol_filter_id; 8638 u8 wol_reason; 8639 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 8640 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 8641 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 8642 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 8643 u8 wol_pkt_len; 8644 u8 unused_0[4]; 8645 u8 valid; 8646 }; 8647 8648 /* hwrm_dbg_read_direct_input (size:256b/32B) */ 8649 struct hwrm_dbg_read_direct_input { 8650 __le16 req_type; 8651 __le16 cmpl_ring; 8652 __le16 seq_id; 8653 __le16 target_id; 8654 __le64 resp_addr; 8655 __le64 host_dest_addr; 8656 __le32 read_addr; 8657 __le32 read_len32; 8658 }; 8659 8660 /* hwrm_dbg_read_direct_output (size:128b/16B) */ 8661 struct hwrm_dbg_read_direct_output { 8662 __le16 error_code; 8663 __le16 req_type; 8664 __le16 seq_id; 8665 __le16 resp_len; 8666 __le32 crc32; 8667 u8 unused_0[3]; 8668 u8 valid; 8669 }; 8670 8671 /* hwrm_dbg_qcaps_input (size:192b/24B) */ 8672 struct hwrm_dbg_qcaps_input { 8673 __le16 req_type; 8674 __le16 cmpl_ring; 8675 __le16 seq_id; 8676 __le16 target_id; 8677 __le64 resp_addr; 8678 __le16 fid; 8679 u8 unused_0[6]; 8680 }; 8681 8682 /* hwrm_dbg_qcaps_output (size:192b/24B) */ 8683 struct hwrm_dbg_qcaps_output { 8684 __le16 error_code; 8685 __le16 req_type; 8686 __le16 seq_id; 8687 __le16 resp_len; 8688 __le16 fid; 8689 u8 unused_0[2]; 8690 __le32 coredump_component_disable_caps; 8691 #define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM 0x1UL 8692 __le32 flags; 8693 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL 8694 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL 8695 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL 8696 #define DBG_QCAPS_RESP_FLAGS_USEQ 0x8UL 8697 u8 unused_1[3]; 8698 u8 valid; 8699 }; 8700 8701 /* hwrm_dbg_qcfg_input (size:192b/24B) */ 8702 struct hwrm_dbg_qcfg_input { 8703 __le16 req_type; 8704 __le16 cmpl_ring; 8705 __le16 seq_id; 8706 __le16 target_id; 8707 __le64 resp_addr; 8708 __le16 fid; 8709 __le16 flags; 8710 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK 0x3UL 8711 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0 8712 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM 0x0UL 8713 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR 0x1UL 8714 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 0x2UL 8715 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 8716 __le32 coredump_component_disable_flags; 8717 #define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM 0x1UL 8718 }; 8719 8720 /* hwrm_dbg_qcfg_output (size:256b/32B) */ 8721 struct hwrm_dbg_qcfg_output { 8722 __le16 error_code; 8723 __le16 req_type; 8724 __le16 seq_id; 8725 __le16 resp_len; 8726 __le16 fid; 8727 u8 unused_0[2]; 8728 __le32 coredump_size; 8729 __le32 flags; 8730 #define DBG_QCFG_RESP_FLAGS_UART_LOG 0x1UL 8731 #define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY 0x2UL 8732 #define DBG_QCFG_RESP_FLAGS_FW_TRACE 0x4UL 8733 #define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY 0x8UL 8734 #define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY 0x10UL 8735 #define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG 0x20UL 8736 __le16 async_cmpl_ring; 8737 u8 unused_2[2]; 8738 __le32 crashdump_size; 8739 u8 unused_3[3]; 8740 u8 valid; 8741 }; 8742 8743 /* coredump_segment_record (size:128b/16B) */ 8744 struct coredump_segment_record { 8745 __le16 component_id; 8746 __le16 segment_id; 8747 __le16 max_instances; 8748 u8 version_hi; 8749 u8 version_low; 8750 u8 seg_flags; 8751 u8 compress_flags; 8752 #define SFLAG_COMPRESSED_ZLIB 0x1UL 8753 u8 unused_0[2]; 8754 __le32 segment_len; 8755 }; 8756 8757 /* hwrm_dbg_coredump_list_input (size:256b/32B) */ 8758 struct hwrm_dbg_coredump_list_input { 8759 __le16 req_type; 8760 __le16 cmpl_ring; 8761 __le16 seq_id; 8762 __le16 target_id; 8763 __le64 resp_addr; 8764 __le64 host_dest_addr; 8765 __le32 host_buf_len; 8766 __le16 seq_no; 8767 u8 flags; 8768 #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL 8769 u8 unused_0[1]; 8770 }; 8771 8772 /* hwrm_dbg_coredump_list_output (size:128b/16B) */ 8773 struct hwrm_dbg_coredump_list_output { 8774 __le16 error_code; 8775 __le16 req_type; 8776 __le16 seq_id; 8777 __le16 resp_len; 8778 u8 flags; 8779 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 8780 u8 unused_0; 8781 __le16 total_segments; 8782 __le16 data_len; 8783 u8 unused_1; 8784 u8 valid; 8785 }; 8786 8787 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 8788 struct hwrm_dbg_coredump_initiate_input { 8789 __le16 req_type; 8790 __le16 cmpl_ring; 8791 __le16 seq_id; 8792 __le16 target_id; 8793 __le64 resp_addr; 8794 __le16 component_id; 8795 __le16 segment_id; 8796 __le16 instance; 8797 __le16 unused_0; 8798 u8 seg_flags; 8799 u8 unused_1[7]; 8800 }; 8801 8802 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 8803 struct hwrm_dbg_coredump_initiate_output { 8804 __le16 error_code; 8805 __le16 req_type; 8806 __le16 seq_id; 8807 __le16 resp_len; 8808 u8 unused_0[7]; 8809 u8 valid; 8810 }; 8811 8812 /* coredump_data_hdr (size:128b/16B) */ 8813 struct coredump_data_hdr { 8814 __le32 address; 8815 __le32 flags_length; 8816 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK 0xffffffUL 8817 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT 0 8818 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS 0x1000000UL 8819 __le32 instance; 8820 __le32 next_offset; 8821 }; 8822 8823 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 8824 struct hwrm_dbg_coredump_retrieve_input { 8825 __le16 req_type; 8826 __le16 cmpl_ring; 8827 __le16 seq_id; 8828 __le16 target_id; 8829 __le64 resp_addr; 8830 __le64 host_dest_addr; 8831 __le32 host_buf_len; 8832 __le32 unused_0; 8833 __le16 component_id; 8834 __le16 segment_id; 8835 __le16 instance; 8836 __le16 unused_1; 8837 u8 seg_flags; 8838 u8 unused_2; 8839 __le16 unused_3; 8840 __le32 unused_4; 8841 __le32 seq_no; 8842 __le32 unused_5; 8843 }; 8844 8845 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 8846 struct hwrm_dbg_coredump_retrieve_output { 8847 __le16 error_code; 8848 __le16 req_type; 8849 __le16 seq_id; 8850 __le16 resp_len; 8851 u8 flags; 8852 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 8853 u8 unused_0; 8854 __le16 data_len; 8855 u8 unused_1[3]; 8856 u8 valid; 8857 }; 8858 8859 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 8860 struct hwrm_dbg_ring_info_get_input { 8861 __le16 req_type; 8862 __le16 cmpl_ring; 8863 __le16 seq_id; 8864 __le16 target_id; 8865 __le64 resp_addr; 8866 u8 ring_type; 8867 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 8868 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 8869 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 8870 #define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 0x3UL 8871 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 8872 u8 unused_0[3]; 8873 __le32 fw_ring_id; 8874 }; 8875 8876 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 8877 struct hwrm_dbg_ring_info_get_output { 8878 __le16 error_code; 8879 __le16 req_type; 8880 __le16 seq_id; 8881 __le16 resp_len; 8882 __le32 producer_index; 8883 __le32 consumer_index; 8884 __le32 cag_vector_ctrl; 8885 u8 unused_0[3]; 8886 u8 valid; 8887 }; 8888 8889 /* hwrm_nvm_read_input (size:320b/40B) */ 8890 struct hwrm_nvm_read_input { 8891 __le16 req_type; 8892 __le16 cmpl_ring; 8893 __le16 seq_id; 8894 __le16 target_id; 8895 __le64 resp_addr; 8896 __le64 host_dest_addr; 8897 __le16 dir_idx; 8898 u8 unused_0[2]; 8899 __le32 offset; 8900 __le32 len; 8901 u8 unused_1[4]; 8902 }; 8903 8904 /* hwrm_nvm_read_output (size:128b/16B) */ 8905 struct hwrm_nvm_read_output { 8906 __le16 error_code; 8907 __le16 req_type; 8908 __le16 seq_id; 8909 __le16 resp_len; 8910 u8 unused_0[7]; 8911 u8 valid; 8912 }; 8913 8914 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 8915 struct hwrm_nvm_get_dir_entries_input { 8916 __le16 req_type; 8917 __le16 cmpl_ring; 8918 __le16 seq_id; 8919 __le16 target_id; 8920 __le64 resp_addr; 8921 __le64 host_dest_addr; 8922 }; 8923 8924 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 8925 struct hwrm_nvm_get_dir_entries_output { 8926 __le16 error_code; 8927 __le16 req_type; 8928 __le16 seq_id; 8929 __le16 resp_len; 8930 u8 unused_0[7]; 8931 u8 valid; 8932 }; 8933 8934 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 8935 struct hwrm_nvm_get_dir_info_input { 8936 __le16 req_type; 8937 __le16 cmpl_ring; 8938 __le16 seq_id; 8939 __le16 target_id; 8940 __le64 resp_addr; 8941 }; 8942 8943 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 8944 struct hwrm_nvm_get_dir_info_output { 8945 __le16 error_code; 8946 __le16 req_type; 8947 __le16 seq_id; 8948 __le16 resp_len; 8949 __le32 entries; 8950 __le32 entry_length; 8951 u8 unused_0[7]; 8952 u8 valid; 8953 }; 8954 8955 /* hwrm_nvm_write_input (size:384b/48B) */ 8956 struct hwrm_nvm_write_input { 8957 __le16 req_type; 8958 __le16 cmpl_ring; 8959 __le16 seq_id; 8960 __le16 target_id; 8961 __le64 resp_addr; 8962 __le64 host_src_addr; 8963 __le16 dir_type; 8964 __le16 dir_ordinal; 8965 __le16 dir_ext; 8966 __le16 dir_attr; 8967 __le32 dir_data_length; 8968 __le16 option; 8969 __le16 flags; 8970 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 8971 __le32 dir_item_length; 8972 __le32 unused_0; 8973 }; 8974 8975 /* hwrm_nvm_write_output (size:128b/16B) */ 8976 struct hwrm_nvm_write_output { 8977 __le16 error_code; 8978 __le16 req_type; 8979 __le16 seq_id; 8980 __le16 resp_len; 8981 __le32 dir_item_length; 8982 __le16 dir_idx; 8983 u8 unused_0; 8984 u8 valid; 8985 }; 8986 8987 /* hwrm_nvm_write_cmd_err (size:64b/8B) */ 8988 struct hwrm_nvm_write_cmd_err { 8989 u8 code; 8990 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 8991 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 8992 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 8993 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 8994 u8 unused_0[7]; 8995 }; 8996 8997 /* hwrm_nvm_modify_input (size:320b/40B) */ 8998 struct hwrm_nvm_modify_input { 8999 __le16 req_type; 9000 __le16 cmpl_ring; 9001 __le16 seq_id; 9002 __le16 target_id; 9003 __le64 resp_addr; 9004 __le64 host_src_addr; 9005 __le16 dir_idx; 9006 __le16 flags; 9007 #define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL 9008 #define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL 9009 __le32 offset; 9010 __le32 len; 9011 u8 unused_1[4]; 9012 }; 9013 9014 /* hwrm_nvm_modify_output (size:128b/16B) */ 9015 struct hwrm_nvm_modify_output { 9016 __le16 error_code; 9017 __le16 req_type; 9018 __le16 seq_id; 9019 __le16 resp_len; 9020 u8 unused_0[7]; 9021 u8 valid; 9022 }; 9023 9024 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 9025 struct hwrm_nvm_find_dir_entry_input { 9026 __le16 req_type; 9027 __le16 cmpl_ring; 9028 __le16 seq_id; 9029 __le16 target_id; 9030 __le64 resp_addr; 9031 __le32 enables; 9032 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 9033 __le16 dir_idx; 9034 __le16 dir_type; 9035 __le16 dir_ordinal; 9036 __le16 dir_ext; 9037 u8 opt_ordinal; 9038 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 9039 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 9040 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 9041 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 9042 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 9043 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 9044 u8 unused_0[3]; 9045 }; 9046 9047 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 9048 struct hwrm_nvm_find_dir_entry_output { 9049 __le16 error_code; 9050 __le16 req_type; 9051 __le16 seq_id; 9052 __le16 resp_len; 9053 __le32 dir_item_length; 9054 __le32 dir_data_length; 9055 __le32 fw_ver; 9056 __le16 dir_ordinal; 9057 __le16 dir_idx; 9058 u8 unused_0[7]; 9059 u8 valid; 9060 }; 9061 9062 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 9063 struct hwrm_nvm_erase_dir_entry_input { 9064 __le16 req_type; 9065 __le16 cmpl_ring; 9066 __le16 seq_id; 9067 __le16 target_id; 9068 __le64 resp_addr; 9069 __le16 dir_idx; 9070 u8 unused_0[6]; 9071 }; 9072 9073 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 9074 struct hwrm_nvm_erase_dir_entry_output { 9075 __le16 error_code; 9076 __le16 req_type; 9077 __le16 seq_id; 9078 __le16 resp_len; 9079 u8 unused_0[7]; 9080 u8 valid; 9081 }; 9082 9083 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 9084 struct hwrm_nvm_get_dev_info_input { 9085 __le16 req_type; 9086 __le16 cmpl_ring; 9087 __le16 seq_id; 9088 __le16 target_id; 9089 __le64 resp_addr; 9090 }; 9091 9092 /* hwrm_nvm_get_dev_info_output (size:640b/80B) */ 9093 struct hwrm_nvm_get_dev_info_output { 9094 __le16 error_code; 9095 __le16 req_type; 9096 __le16 seq_id; 9097 __le16 resp_len; 9098 __le16 manufacturer_id; 9099 __le16 device_id; 9100 __le32 sector_size; 9101 __le32 nvram_size; 9102 __le32 reserved_size; 9103 __le32 available_size; 9104 u8 nvm_cfg_ver_maj; 9105 u8 nvm_cfg_ver_min; 9106 u8 nvm_cfg_ver_upd; 9107 u8 flags; 9108 #define NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID 0x1UL 9109 char pkg_name[16]; 9110 __le16 hwrm_fw_major; 9111 __le16 hwrm_fw_minor; 9112 __le16 hwrm_fw_build; 9113 __le16 hwrm_fw_patch; 9114 __le16 mgmt_fw_major; 9115 __le16 mgmt_fw_minor; 9116 __le16 mgmt_fw_build; 9117 __le16 mgmt_fw_patch; 9118 __le16 roce_fw_major; 9119 __le16 roce_fw_minor; 9120 __le16 roce_fw_build; 9121 __le16 roce_fw_patch; 9122 u8 unused_0[7]; 9123 u8 valid; 9124 }; 9125 9126 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 9127 struct hwrm_nvm_mod_dir_entry_input { 9128 __le16 req_type; 9129 __le16 cmpl_ring; 9130 __le16 seq_id; 9131 __le16 target_id; 9132 __le64 resp_addr; 9133 __le32 enables; 9134 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 9135 __le16 dir_idx; 9136 __le16 dir_ordinal; 9137 __le16 dir_ext; 9138 __le16 dir_attr; 9139 __le32 checksum; 9140 }; 9141 9142 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 9143 struct hwrm_nvm_mod_dir_entry_output { 9144 __le16 error_code; 9145 __le16 req_type; 9146 __le16 seq_id; 9147 __le16 resp_len; 9148 u8 unused_0[7]; 9149 u8 valid; 9150 }; 9151 9152 /* hwrm_nvm_verify_update_input (size:192b/24B) */ 9153 struct hwrm_nvm_verify_update_input { 9154 __le16 req_type; 9155 __le16 cmpl_ring; 9156 __le16 seq_id; 9157 __le16 target_id; 9158 __le64 resp_addr; 9159 __le16 dir_type; 9160 __le16 dir_ordinal; 9161 __le16 dir_ext; 9162 u8 unused_0[2]; 9163 }; 9164 9165 /* hwrm_nvm_verify_update_output (size:128b/16B) */ 9166 struct hwrm_nvm_verify_update_output { 9167 __le16 error_code; 9168 __le16 req_type; 9169 __le16 seq_id; 9170 __le16 resp_len; 9171 u8 unused_0[7]; 9172 u8 valid; 9173 }; 9174 9175 /* hwrm_nvm_install_update_input (size:192b/24B) */ 9176 struct hwrm_nvm_install_update_input { 9177 __le16 req_type; 9178 __le16 cmpl_ring; 9179 __le16 seq_id; 9180 __le16 target_id; 9181 __le64 resp_addr; 9182 __le32 install_type; 9183 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 9184 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 9185 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 9186 __le16 flags; 9187 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 9188 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 9189 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 9190 #define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY 0x8UL 9191 u8 unused_0[2]; 9192 }; 9193 9194 /* hwrm_nvm_install_update_output (size:192b/24B) */ 9195 struct hwrm_nvm_install_update_output { 9196 __le16 error_code; 9197 __le16 req_type; 9198 __le16 seq_id; 9199 __le16 resp_len; 9200 __le64 installed_items; 9201 u8 result; 9202 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 9203 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 9204 u8 problem_item; 9205 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 9206 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 9207 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 9208 u8 reset_required; 9209 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 9210 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 9211 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 9212 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 9213 u8 unused_0[4]; 9214 u8 valid; 9215 }; 9216 9217 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 9218 struct hwrm_nvm_install_update_cmd_err { 9219 u8 code; 9220 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 9221 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 9222 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 9223 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK 0x3UL 9224 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK 9225 u8 unused_0[7]; 9226 }; 9227 9228 /* hwrm_nvm_get_variable_input (size:320b/40B) */ 9229 struct hwrm_nvm_get_variable_input { 9230 __le16 req_type; 9231 __le16 cmpl_ring; 9232 __le16 seq_id; 9233 __le16 target_id; 9234 __le64 resp_addr; 9235 __le64 dest_data_addr; 9236 __le16 data_len; 9237 __le16 option_num; 9238 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 9239 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 9240 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 9241 __le16 dimensions; 9242 __le16 index_0; 9243 __le16 index_1; 9244 __le16 index_2; 9245 __le16 index_3; 9246 u8 flags; 9247 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 9248 u8 unused_0; 9249 }; 9250 9251 /* hwrm_nvm_get_variable_output (size:128b/16B) */ 9252 struct hwrm_nvm_get_variable_output { 9253 __le16 error_code; 9254 __le16 req_type; 9255 __le16 seq_id; 9256 __le16 resp_len; 9257 __le16 data_len; 9258 __le16 option_num; 9259 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 9260 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 9261 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 9262 u8 unused_0[3]; 9263 u8 valid; 9264 }; 9265 9266 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 9267 struct hwrm_nvm_get_variable_cmd_err { 9268 u8 code; 9269 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 9270 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 9271 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 9272 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 9273 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 9274 u8 unused_0[7]; 9275 }; 9276 9277 /* hwrm_nvm_set_variable_input (size:320b/40B) */ 9278 struct hwrm_nvm_set_variable_input { 9279 __le16 req_type; 9280 __le16 cmpl_ring; 9281 __le16 seq_id; 9282 __le16 target_id; 9283 __le64 resp_addr; 9284 __le64 src_data_addr; 9285 __le16 data_len; 9286 __le16 option_num; 9287 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 9288 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 9289 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 9290 __le16 dimensions; 9291 __le16 index_0; 9292 __le16 index_1; 9293 __le16 index_2; 9294 __le16 index_3; 9295 u8 flags; 9296 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 9297 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 9298 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 9299 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 9300 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 9301 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 9302 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 9303 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 9304 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL 9305 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4 9306 #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL 9307 u8 unused_0; 9308 }; 9309 9310 /* hwrm_nvm_set_variable_output (size:128b/16B) */ 9311 struct hwrm_nvm_set_variable_output { 9312 __le16 error_code; 9313 __le16 req_type; 9314 __le16 seq_id; 9315 __le16 resp_len; 9316 u8 unused_0[7]; 9317 u8 valid; 9318 }; 9319 9320 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 9321 struct hwrm_nvm_set_variable_cmd_err { 9322 u8 code; 9323 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 9324 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 9325 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 9326 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 9327 u8 unused_0[7]; 9328 }; 9329 9330 /* hwrm_selftest_qlist_input (size:128b/16B) */ 9331 struct hwrm_selftest_qlist_input { 9332 __le16 req_type; 9333 __le16 cmpl_ring; 9334 __le16 seq_id; 9335 __le16 target_id; 9336 __le64 resp_addr; 9337 }; 9338 9339 /* hwrm_selftest_qlist_output (size:2240b/280B) */ 9340 struct hwrm_selftest_qlist_output { 9341 __le16 error_code; 9342 __le16 req_type; 9343 __le16 seq_id; 9344 __le16 resp_len; 9345 u8 num_tests; 9346 u8 available_tests; 9347 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 9348 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 9349 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 9350 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 9351 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 9352 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 9353 u8 offline_tests; 9354 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 9355 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 9356 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 9357 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 9358 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 9359 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 9360 u8 unused_0; 9361 __le16 test_timeout; 9362 u8 unused_1[2]; 9363 char test0_name[32]; 9364 char test1_name[32]; 9365 char test2_name[32]; 9366 char test3_name[32]; 9367 char test4_name[32]; 9368 char test5_name[32]; 9369 char test6_name[32]; 9370 char test7_name[32]; 9371 u8 eyescope_target_BER_support; 9372 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED 0x0UL 9373 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED 0x1UL 9374 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL 9375 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL 9376 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL 9377 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 9378 u8 unused_2[6]; 9379 u8 valid; 9380 }; 9381 9382 /* hwrm_selftest_exec_input (size:192b/24B) */ 9383 struct hwrm_selftest_exec_input { 9384 __le16 req_type; 9385 __le16 cmpl_ring; 9386 __le16 seq_id; 9387 __le16 target_id; 9388 __le64 resp_addr; 9389 u8 flags; 9390 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 9391 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 9392 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 9393 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 9394 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 9395 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 9396 u8 unused_0[7]; 9397 }; 9398 9399 /* hwrm_selftest_exec_output (size:128b/16B) */ 9400 struct hwrm_selftest_exec_output { 9401 __le16 error_code; 9402 __le16 req_type; 9403 __le16 seq_id; 9404 __le16 resp_len; 9405 u8 requested_tests; 9406 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 9407 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 9408 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 9409 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 9410 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 9411 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 9412 u8 test_success; 9413 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 9414 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 9415 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 9416 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 9417 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 9418 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 9419 u8 unused_0[5]; 9420 u8 valid; 9421 }; 9422 9423 /* hwrm_selftest_irq_input (size:128b/16B) */ 9424 struct hwrm_selftest_irq_input { 9425 __le16 req_type; 9426 __le16 cmpl_ring; 9427 __le16 seq_id; 9428 __le16 target_id; 9429 __le64 resp_addr; 9430 }; 9431 9432 /* hwrm_selftest_irq_output (size:128b/16B) */ 9433 struct hwrm_selftest_irq_output { 9434 __le16 error_code; 9435 __le16 req_type; 9436 __le16 seq_id; 9437 __le16 resp_len; 9438 u8 unused_0[7]; 9439 u8 valid; 9440 }; 9441 9442 /* db_push_info (size:64b/8B) */ 9443 struct db_push_info { 9444 u32 push_size_push_index; 9445 #define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL 9446 #define DB_PUSH_INFO_PUSH_INDEX_SFT 0 9447 #define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL 9448 #define DB_PUSH_INFO_PUSH_SIZE_SFT 24 9449 u32 reserved32; 9450 }; 9451 9452 /* fw_status_reg (size:32b/4B) */ 9453 struct fw_status_reg { 9454 u32 fw_status; 9455 #define FW_STATUS_REG_CODE_MASK 0xffffUL 9456 #define FW_STATUS_REG_CODE_SFT 0 9457 #define FW_STATUS_REG_CODE_READY 0x8000UL 9458 #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY 9459 #define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL 9460 #define FW_STATUS_REG_RECOVERABLE 0x20000UL 9461 #define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL 9462 #define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL 9463 #define FW_STATUS_REG_SHUTDOWN 0x100000UL 9464 #define FW_STATUS_REG_CRASHED_NO_MASTER 0x200000UL 9465 #define FW_STATUS_REG_RECOVERING 0x400000UL 9466 }; 9467 9468 /* hcomm_status (size:64b/8B) */ 9469 struct hcomm_status { 9470 u32 sig_ver; 9471 #define HCOMM_STATUS_VER_MASK 0xffUL 9472 #define HCOMM_STATUS_VER_SFT 0 9473 #define HCOMM_STATUS_VER_LATEST 0x1UL 9474 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST 9475 #define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL 9476 #define HCOMM_STATUS_SIGNATURE_SFT 8 9477 #define HCOMM_STATUS_SIGNATURE_VAL (0x484353UL << 8) 9478 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL 9479 u32 fw_status_loc; 9480 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK 0x3UL 9481 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 9482 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG 0x0UL 9483 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC 0x1UL 9484 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 0x2UL 9485 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 0x3UL 9486 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 9487 #define HCOMM_STATUS_TRUE_OFFSET_MASK 0xfffffffcUL 9488 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 9489 }; 9490 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL 9491 9492 #endif /* _BNXT_HSI_H_ */ 9493