1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2014-2018 Broadcom Limited 5 * Copyright (c) 2018-2024 Broadcom Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * DO NOT MODIFY!!! This file is automatically generated. 12 */ 13 14 #ifndef _BNXT_HSI_H_ 15 #define _BNXT_HSI_H_ 16 17 /* hwrm_cmd_hdr (size:128b/16B) */ 18 struct hwrm_cmd_hdr { 19 __le16 req_type; 20 __le16 cmpl_ring; 21 __le16 seq_id; 22 __le16 target_id; 23 __le64 resp_addr; 24 }; 25 26 /* hwrm_resp_hdr (size:64b/8B) */ 27 struct hwrm_resp_hdr { 28 __le16 error_code; 29 __le16 req_type; 30 __le16 seq_id; 31 __le16 resp_len; 32 }; 33 34 #define CMD_DISCR_TLV_ENCAP 0x8000UL 35 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 36 37 38 #define TLV_TYPE_HWRM_REQUEST 0x1UL 39 #define TLV_TYPE_HWRM_RESPONSE 0x2UL 40 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 41 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 42 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 43 #define TLV_TYPE_QUERY_ROCE_CC_GEN2 0x6UL 44 #define TLV_TYPE_MODIFY_ROCE_CC_GEN2 0x7UL 45 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL 46 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 47 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 48 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 49 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL 50 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL 51 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 52 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL 53 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL 54 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 55 56 57 /* tlv (size:64b/8B) */ 58 struct tlv { 59 __le16 cmd_discr; 60 u8 reserved_8b; 61 u8 flags; 62 #define TLV_FLAGS_MORE 0x1UL 63 #define TLV_FLAGS_MORE_LAST 0x0UL 64 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 65 #define TLV_FLAGS_REQUIRED 0x2UL 66 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 67 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 68 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 69 __le16 tlv_type; 70 __le16 length; 71 }; 72 73 /* input (size:128b/16B) */ 74 struct input { 75 __le16 req_type; 76 __le16 cmpl_ring; 77 __le16 seq_id; 78 __le16 target_id; 79 __le64 resp_addr; 80 }; 81 82 /* output (size:64b/8B) */ 83 struct output { 84 __le16 error_code; 85 __le16 req_type; 86 __le16 seq_id; 87 __le16 resp_len; 88 }; 89 90 /* hwrm_short_input (size:128b/16B) */ 91 struct hwrm_short_input { 92 __le16 req_type; 93 __le16 signature; 94 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 95 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 96 __le16 target_id; 97 #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL 98 #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL 99 #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS 100 __le16 size; 101 __le64 req_addr; 102 }; 103 104 /* cmd_nums (size:64b/8B) */ 105 struct cmd_nums { 106 __le16 req_type; 107 #define HWRM_VER_GET 0x0UL 108 #define HWRM_FUNC_ECHO_RESPONSE 0xbUL 109 #define HWRM_ERROR_RECOVERY_QCFG 0xcUL 110 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 111 #define HWRM_FUNC_BUF_UNRGTR 0xeUL 112 #define HWRM_FUNC_VF_CFG 0xfUL 113 #define HWRM_RESERVED1 0x10UL 114 #define HWRM_FUNC_RESET 0x11UL 115 #define HWRM_FUNC_GETFID 0x12UL 116 #define HWRM_FUNC_VF_ALLOC 0x13UL 117 #define HWRM_FUNC_VF_FREE 0x14UL 118 #define HWRM_FUNC_QCAPS 0x15UL 119 #define HWRM_FUNC_QCFG 0x16UL 120 #define HWRM_FUNC_CFG 0x17UL 121 #define HWRM_FUNC_QSTATS 0x18UL 122 #define HWRM_FUNC_CLR_STATS 0x19UL 123 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 124 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 125 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 126 #define HWRM_FUNC_DRV_RGTR 0x1dUL 127 #define HWRM_FUNC_DRV_QVER 0x1eUL 128 #define HWRM_FUNC_BUF_RGTR 0x1fUL 129 #define HWRM_PORT_PHY_CFG 0x20UL 130 #define HWRM_PORT_MAC_CFG 0x21UL 131 #define HWRM_PORT_TS_QUERY 0x22UL 132 #define HWRM_PORT_QSTATS 0x23UL 133 #define HWRM_PORT_LPBK_QSTATS 0x24UL 134 #define HWRM_PORT_CLR_STATS 0x25UL 135 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 136 #define HWRM_PORT_PHY_QCFG 0x27UL 137 #define HWRM_PORT_MAC_QCFG 0x28UL 138 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 139 #define HWRM_PORT_PHY_QCAPS 0x2aUL 140 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 141 #define HWRM_PORT_PHY_I2C_READ 0x2cUL 142 #define HWRM_PORT_LED_CFG 0x2dUL 143 #define HWRM_PORT_LED_QCFG 0x2eUL 144 #define HWRM_PORT_LED_QCAPS 0x2fUL 145 #define HWRM_QUEUE_QPORTCFG 0x30UL 146 #define HWRM_QUEUE_QCFG 0x31UL 147 #define HWRM_QUEUE_CFG 0x32UL 148 #define HWRM_FUNC_VLAN_CFG 0x33UL 149 #define HWRM_FUNC_VLAN_QCFG 0x34UL 150 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 151 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 152 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 153 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 154 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 155 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 156 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 157 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 158 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 159 #define HWRM_VNIC_ALLOC 0x40UL 160 #define HWRM_VNIC_FREE 0x41UL 161 #define HWRM_VNIC_CFG 0x42UL 162 #define HWRM_VNIC_QCFG 0x43UL 163 #define HWRM_VNIC_TPA_CFG 0x44UL 164 #define HWRM_VNIC_TPA_QCFG 0x45UL 165 #define HWRM_VNIC_RSS_CFG 0x46UL 166 #define HWRM_VNIC_RSS_QCFG 0x47UL 167 #define HWRM_VNIC_PLCMODES_CFG 0x48UL 168 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 169 #define HWRM_VNIC_QCAPS 0x4aUL 170 #define HWRM_VNIC_UPDATE 0x4bUL 171 #define HWRM_RING_ALLOC 0x50UL 172 #define HWRM_RING_FREE 0x51UL 173 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 174 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 175 #define HWRM_RING_AGGINT_QCAPS 0x54UL 176 #define HWRM_RING_SCHQ_ALLOC 0x55UL 177 #define HWRM_RING_SCHQ_CFG 0x56UL 178 #define HWRM_RING_SCHQ_FREE 0x57UL 179 #define HWRM_RING_RESET 0x5eUL 180 #define HWRM_RING_GRP_ALLOC 0x60UL 181 #define HWRM_RING_GRP_FREE 0x61UL 182 #define HWRM_RING_CFG 0x62UL 183 #define HWRM_RING_QCFG 0x63UL 184 #define HWRM_RESERVED5 0x64UL 185 #define HWRM_RESERVED6 0x65UL 186 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 187 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 188 #define HWRM_QUEUE_MPLS_QCAPS 0x80UL 189 #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL 190 #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL 191 #define HWRM_QUEUE_VLANPRI_QCAPS 0x83UL 192 #define HWRM_QUEUE_VLANPRI2PRI_QCFG 0x84UL 193 #define HWRM_QUEUE_VLANPRI2PRI_CFG 0x85UL 194 #define HWRM_QUEUE_GLOBAL_CFG 0x86UL 195 #define HWRM_QUEUE_GLOBAL_QCFG 0x87UL 196 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG 0x88UL 197 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG 0x89UL 198 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG 0x8aUL 199 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG 0x8bUL 200 #define HWRM_QUEUE_QCAPS 0x8cUL 201 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_QCFG 0x8dUL 202 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG 0x8eUL 203 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_QCFG 0x8fUL 204 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 205 #define HWRM_CFA_L2_FILTER_FREE 0x91UL 206 #define HWRM_CFA_L2_FILTER_CFG 0x92UL 207 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 208 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 209 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 210 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 211 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 212 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 213 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 214 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 215 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 216 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 217 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 218 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 219 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 220 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 221 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 222 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG 0xa3UL 223 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 224 #define HWRM_STAT_CTX_ALLOC 0xb0UL 225 #define HWRM_STAT_CTX_FREE 0xb1UL 226 #define HWRM_STAT_CTX_QUERY 0xb2UL 227 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 228 #define HWRM_PORT_QSTATS_EXT 0xb4UL 229 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL 230 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL 231 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL 232 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL 233 #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL 234 #define HWRM_RESERVED7 0xbaUL 235 #define HWRM_PORT_TX_FIR_CFG 0xbbUL 236 #define HWRM_PORT_TX_FIR_QCFG 0xbcUL 237 #define HWRM_PORT_ECN_QSTATS 0xbdUL 238 #define HWRM_FW_LIVEPATCH_QUERY 0xbeUL 239 #define HWRM_FW_LIVEPATCH 0xbfUL 240 #define HWRM_FW_RESET 0xc0UL 241 #define HWRM_FW_QSTATUS 0xc1UL 242 #define HWRM_FW_HEALTH_CHECK 0xc2UL 243 #define HWRM_FW_SYNC 0xc3UL 244 #define HWRM_FW_STATE_QCAPS 0xc4UL 245 #define HWRM_FW_STATE_QUIESCE 0xc5UL 246 #define HWRM_FW_STATE_BACKUP 0xc6UL 247 #define HWRM_FW_STATE_RESTORE 0xc7UL 248 #define HWRM_FW_SET_TIME 0xc8UL 249 #define HWRM_FW_GET_TIME 0xc9UL 250 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 251 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 252 #define HWRM_FW_IPC_MAILBOX 0xccUL 253 #define HWRM_FW_ECN_CFG 0xcdUL 254 #define HWRM_FW_ECN_QCFG 0xceUL 255 #define HWRM_FW_SECURE_CFG 0xcfUL 256 #define HWRM_EXEC_FWD_RESP 0xd0UL 257 #define HWRM_REJECT_FWD_RESP 0xd1UL 258 #define HWRM_FWD_RESP 0xd2UL 259 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 260 #define HWRM_OEM_CMD 0xd4UL 261 #define HWRM_PORT_PRBS_TEST 0xd5UL 262 #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL 263 #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL 264 #define HWRM_FW_STATE_UNQUIESCE 0xd8UL 265 #define HWRM_PORT_DSC_DUMP 0xd9UL 266 #define HWRM_PORT_EP_TX_QCFG 0xdaUL 267 #define HWRM_PORT_EP_TX_CFG 0xdbUL 268 #define HWRM_PORT_CFG 0xdcUL 269 #define HWRM_PORT_QCFG 0xddUL 270 #define HWRM_PORT_MAC_QCAPS 0xdfUL 271 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 272 #define HWRM_REG_POWER_QUERY 0xe1UL 273 #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL 274 #define HWRM_REG_POWER_HISTOGRAM 0xe3UL 275 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 276 #define HWRM_WOL_FILTER_FREE 0xf1UL 277 #define HWRM_WOL_FILTER_QCFG 0xf2UL 278 #define HWRM_WOL_REASON_QCFG 0xf3UL 279 #define HWRM_CFA_METER_QCAPS 0xf4UL 280 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 281 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 282 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 283 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 284 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 285 #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL 286 #define HWRM_CFA_VFR_ALLOC 0xfdUL 287 #define HWRM_CFA_VFR_FREE 0xfeUL 288 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 289 #define HWRM_CFA_VF_PAIR_FREE 0x101UL 290 #define HWRM_CFA_VF_PAIR_INFO 0x102UL 291 #define HWRM_CFA_FLOW_ALLOC 0x103UL 292 #define HWRM_CFA_FLOW_FREE 0x104UL 293 #define HWRM_CFA_FLOW_FLUSH 0x105UL 294 #define HWRM_CFA_FLOW_STATS 0x106UL 295 #define HWRM_CFA_FLOW_INFO 0x107UL 296 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 297 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 298 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 299 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 300 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 301 #define HWRM_CFA_PAIR_ALLOC 0x10dUL 302 #define HWRM_CFA_PAIR_FREE 0x10eUL 303 #define HWRM_CFA_PAIR_INFO 0x10fUL 304 #define HWRM_FW_IPC_MSG 0x110UL 305 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 306 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 307 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL 308 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL 309 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL 310 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL 311 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL 312 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL 313 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL 314 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL 315 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL 316 #define HWRM_CFA_COUNTER_CFG 0x11cUL 317 #define HWRM_CFA_COUNTER_QCFG 0x11dUL 318 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL 319 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL 320 #define HWRM_CFA_EEM_QCAPS 0x120UL 321 #define HWRM_CFA_EEM_CFG 0x121UL 322 #define HWRM_CFA_EEM_QCFG 0x122UL 323 #define HWRM_CFA_EEM_OP 0x123UL 324 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL 325 #define HWRM_CFA_TFLIB 0x125UL 326 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR 0x126UL 327 #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR 0x127UL 328 #define HWRM_CFA_TLS_FILTER_ALLOC 0x128UL 329 #define HWRM_CFA_TLS_FILTER_FREE 0x129UL 330 #define HWRM_CFA_RELEASE_AFM_FUNC 0x12aUL 331 #define HWRM_ENGINE_CKV_STATUS 0x12eUL 332 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 333 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 334 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 335 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 336 #define HWRM_ENGINE_CKV_FLUSH 0x133UL 337 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 338 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 339 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL 340 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL 341 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 342 #define HWRM_ENGINE_QG_QUERY 0x13dUL 343 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 344 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 345 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 346 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 347 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 348 #define HWRM_ENGINE_QG_METER_BIND 0x143UL 349 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 350 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 351 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 352 #define HWRM_ENGINE_SG_QUERY 0x147UL 353 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 354 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 355 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 356 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 357 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 358 #define HWRM_ENGINE_STATS_CONFIG 0x155UL 359 #define HWRM_ENGINE_STATS_CLEAR 0x156UL 360 #define HWRM_ENGINE_STATS_QUERY 0x157UL 361 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL 362 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 363 #define HWRM_ENGINE_RQ_FREE 0x15fUL 364 #define HWRM_ENGINE_CQ_ALLOC 0x160UL 365 #define HWRM_ENGINE_CQ_FREE 0x161UL 366 #define HWRM_ENGINE_NQ_ALLOC 0x162UL 367 #define HWRM_ENGINE_NQ_FREE 0x163UL 368 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 369 #define HWRM_ENGINE_FUNC_QCFG 0x165UL 370 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 371 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 372 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 373 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 374 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 375 #define HWRM_FUNC_VF_BW_CFG 0x195UL 376 #define HWRM_FUNC_VF_BW_QCFG 0x196UL 377 #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL 378 #define HWRM_FUNC_QSTATS_EXT 0x198UL 379 #define HWRM_STAT_EXT_CTX_QUERY 0x199UL 380 #define HWRM_FUNC_SPD_CFG 0x19aUL 381 #define HWRM_FUNC_SPD_QCFG 0x19bUL 382 #define HWRM_FUNC_PTP_PIN_QCFG 0x19cUL 383 #define HWRM_FUNC_PTP_PIN_CFG 0x19dUL 384 #define HWRM_FUNC_PTP_CFG 0x19eUL 385 #define HWRM_FUNC_PTP_TS_QUERY 0x19fUL 386 #define HWRM_FUNC_PTP_EXT_CFG 0x1a0UL 387 #define HWRM_FUNC_PTP_EXT_QCFG 0x1a1UL 388 #define HWRM_FUNC_KEY_CTX_ALLOC 0x1a2UL 389 #define HWRM_FUNC_BACKING_STORE_CFG_V2 0x1a3UL 390 #define HWRM_FUNC_BACKING_STORE_QCFG_V2 0x1a4UL 391 #define HWRM_FUNC_DBR_PACING_CFG 0x1a5UL 392 #define HWRM_FUNC_DBR_PACING_QCFG 0x1a6UL 393 #define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT 0x1a7UL 394 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2 0x1a8UL 395 #define HWRM_FUNC_DBR_PACING_NQLIST_QUERY 0x1a9UL 396 #define HWRM_FUNC_DBR_RECOVERY_COMPLETED 0x1aaUL 397 #define HWRM_FUNC_SYNCE_CFG 0x1abUL 398 #define HWRM_FUNC_SYNCE_QCFG 0x1acUL 399 #define HWRM_FUNC_KEY_CTX_FREE 0x1adUL 400 #define HWRM_FUNC_LAG_MODE_CFG 0x1aeUL 401 #define HWRM_FUNC_LAG_MODE_QCFG 0x1afUL 402 #define HWRM_FUNC_LAG_CREATE 0x1b0UL 403 #define HWRM_FUNC_LAG_UPDATE 0x1b1UL 404 #define HWRM_FUNC_LAG_FREE 0x1b2UL 405 #define HWRM_FUNC_LAG_QCFG 0x1b3UL 406 #define HWRM_SELFTEST_QLIST 0x200UL 407 #define HWRM_SELFTEST_EXEC 0x201UL 408 #define HWRM_SELFTEST_IRQ 0x202UL 409 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 410 #define HWRM_PCIE_QSTATS 0x204UL 411 #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL 412 #define HWRM_MFG_TIMERS_QUERY 0x206UL 413 #define HWRM_MFG_OTP_CFG 0x207UL 414 #define HWRM_MFG_OTP_QCFG 0x208UL 415 #define HWRM_MFG_HDMA_TEST 0x209UL 416 #define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL 417 #define HWRM_MFG_FRU_EEPROM_READ 0x20bUL 418 #define HWRM_MFG_SOC_IMAGE 0x20cUL 419 #define HWRM_MFG_SOC_QSTATUS 0x20dUL 420 #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE 0x20eUL 421 #define HWRM_MFG_PARAM_CRITICAL_DATA_READ 0x20fUL 422 #define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH 0x210UL 423 #define HWRM_MFG_PRVSN_EXPORT_CSR 0x211UL 424 #define HWRM_MFG_PRVSN_IMPORT_CERT 0x212UL 425 #define HWRM_MFG_PRVSN_GET_STATE 0x213UL 426 #define HWRM_MFG_GET_NVM_MEASUREMENT 0x214UL 427 #define HWRM_MFG_PSOC_QSTATUS 0x215UL 428 #define HWRM_MFG_SELFTEST_QLIST 0x216UL 429 #define HWRM_MFG_SELFTEST_EXEC 0x217UL 430 #define HWRM_STAT_GENERIC_QSTATS 0x218UL 431 #define HWRM_MFG_PRVSN_EXPORT_CERT 0x219UL 432 #define HWRM_STAT_DB_ERROR_QSTATS 0x21aUL 433 #define HWRM_UDCC_QCAPS 0x258UL 434 #define HWRM_UDCC_CFG 0x259UL 435 #define HWRM_UDCC_QCFG 0x25aUL 436 #define HWRM_UDCC_SESSION_CFG 0x25bUL 437 #define HWRM_UDCC_SESSION_QCFG 0x25cUL 438 #define HWRM_UDCC_SESSION_QUERY 0x25dUL 439 #define HWRM_UDCC_COMP_CFG 0x25eUL 440 #define HWRM_UDCC_COMP_QCFG 0x25fUL 441 #define HWRM_UDCC_COMP_QUERY 0x260UL 442 #define HWRM_TF 0x2bcUL 443 #define HWRM_TF_VERSION_GET 0x2bdUL 444 #define HWRM_TF_SESSION_OPEN 0x2c6UL 445 #define HWRM_TF_SESSION_REGISTER 0x2c8UL 446 #define HWRM_TF_SESSION_UNREGISTER 0x2c9UL 447 #define HWRM_TF_SESSION_CLOSE 0x2caUL 448 #define HWRM_TF_SESSION_QCFG 0x2cbUL 449 #define HWRM_TF_SESSION_RESC_QCAPS 0x2ccUL 450 #define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL 451 #define HWRM_TF_SESSION_RESC_FREE 0x2ceUL 452 #define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL 453 #define HWRM_TF_SESSION_RESC_INFO 0x2d0UL 454 #define HWRM_TF_SESSION_HOTUP_STATE_SET 0x2d1UL 455 #define HWRM_TF_SESSION_HOTUP_STATE_GET 0x2d2UL 456 #define HWRM_TF_TBL_TYPE_GET 0x2daUL 457 #define HWRM_TF_TBL_TYPE_SET 0x2dbUL 458 #define HWRM_TF_TBL_TYPE_BULK_GET 0x2dcUL 459 #define HWRM_TF_EM_INSERT 0x2eaUL 460 #define HWRM_TF_EM_DELETE 0x2ebUL 461 #define HWRM_TF_EM_HASH_INSERT 0x2ecUL 462 #define HWRM_TF_EM_MOVE 0x2edUL 463 #define HWRM_TF_TCAM_SET 0x2f8UL 464 #define HWRM_TF_TCAM_GET 0x2f9UL 465 #define HWRM_TF_TCAM_MOVE 0x2faUL 466 #define HWRM_TF_TCAM_FREE 0x2fbUL 467 #define HWRM_TF_GLOBAL_CFG_SET 0x2fcUL 468 #define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL 469 #define HWRM_TF_IF_TBL_SET 0x2feUL 470 #define HWRM_TF_IF_TBL_GET 0x2ffUL 471 #define HWRM_TF_RESC_USAGE_SET 0x300UL 472 #define HWRM_TF_RESC_USAGE_QUERY 0x301UL 473 #define HWRM_TF_TBL_TYPE_ALLOC 0x302UL 474 #define HWRM_TF_TBL_TYPE_FREE 0x303UL 475 #define HWRM_TFC_TBL_SCOPE_QCAPS 0x380UL 476 #define HWRM_TFC_TBL_SCOPE_ID_ALLOC 0x381UL 477 #define HWRM_TFC_TBL_SCOPE_CONFIG 0x382UL 478 #define HWRM_TFC_TBL_SCOPE_DECONFIG 0x383UL 479 #define HWRM_TFC_TBL_SCOPE_FID_ADD 0x384UL 480 #define HWRM_TFC_TBL_SCOPE_FID_REM 0x385UL 481 #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC 0x386UL 482 #define HWRM_TFC_TBL_SCOPE_POOL_FREE 0x387UL 483 #define HWRM_TFC_SESSION_ID_ALLOC 0x388UL 484 #define HWRM_TFC_SESSION_FID_ADD 0x389UL 485 #define HWRM_TFC_SESSION_FID_REM 0x38aUL 486 #define HWRM_TFC_IDENT_ALLOC 0x38bUL 487 #define HWRM_TFC_IDENT_FREE 0x38cUL 488 #define HWRM_TFC_IDX_TBL_ALLOC 0x38dUL 489 #define HWRM_TFC_IDX_TBL_ALLOC_SET 0x38eUL 490 #define HWRM_TFC_IDX_TBL_SET 0x38fUL 491 #define HWRM_TFC_IDX_TBL_GET 0x390UL 492 #define HWRM_TFC_IDX_TBL_FREE 0x391UL 493 #define HWRM_TFC_GLOBAL_ID_ALLOC 0x392UL 494 #define HWRM_TFC_TCAM_SET 0x393UL 495 #define HWRM_TFC_TCAM_GET 0x394UL 496 #define HWRM_TFC_TCAM_ALLOC 0x395UL 497 #define HWRM_TFC_TCAM_ALLOC_SET 0x396UL 498 #define HWRM_TFC_TCAM_FREE 0x397UL 499 #define HWRM_TFC_IF_TBL_SET 0x398UL 500 #define HWRM_TFC_IF_TBL_GET 0x399UL 501 #define HWRM_TFC_TBL_SCOPE_CONFIG_GET 0x39aUL 502 #define HWRM_TFC_RESC_USAGE_QUERY 0x39bUL 503 #define HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS 0x39cUL 504 #define HWRM_QUEUE_PFCWD_TIMEOUT_CFG 0x39dUL 505 #define HWRM_QUEUE_PFCWD_TIMEOUT_QCFG 0x39eUL 506 #define HWRM_SV 0x400UL 507 #define HWRM_DBG_LOG_BUFFER_FLUSH 0xff0fUL 508 #define HWRM_DBG_READ_DIRECT 0xff10UL 509 #define HWRM_DBG_READ_INDIRECT 0xff11UL 510 #define HWRM_DBG_WRITE_DIRECT 0xff12UL 511 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 512 #define HWRM_DBG_DUMP 0xff14UL 513 #define HWRM_DBG_ERASE_NVM 0xff15UL 514 #define HWRM_DBG_CFG 0xff16UL 515 #define HWRM_DBG_COREDUMP_LIST 0xff17UL 516 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 517 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 518 #define HWRM_DBG_FW_CLI 0xff1aUL 519 #define HWRM_DBG_I2C_CMD 0xff1bUL 520 #define HWRM_DBG_RING_INFO_GET 0xff1cUL 521 #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL 522 #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL 523 #define HWRM_DBG_DRV_TRACE 0xff1fUL 524 #define HWRM_DBG_QCAPS 0xff20UL 525 #define HWRM_DBG_QCFG 0xff21UL 526 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL 527 #define HWRM_DBG_USEQ_ALLOC 0xff23UL 528 #define HWRM_DBG_USEQ_FREE 0xff24UL 529 #define HWRM_DBG_USEQ_FLUSH 0xff25UL 530 #define HWRM_DBG_USEQ_QCAPS 0xff26UL 531 #define HWRM_DBG_USEQ_CW_CFG 0xff27UL 532 #define HWRM_DBG_USEQ_SCHED_CFG 0xff28UL 533 #define HWRM_DBG_USEQ_RUN 0xff29UL 534 #define HWRM_DBG_USEQ_DELIVERY_REQ 0xff2aUL 535 #define HWRM_DBG_USEQ_RESP_HDR 0xff2bUL 536 #define HWRM_NVM_GET_VPD_FIELD_INFO 0xffeaUL 537 #define HWRM_NVM_SET_VPD_FIELD_INFO 0xffebUL 538 #define HWRM_NVM_DEFRAG 0xffecUL 539 #define HWRM_NVM_REQ_ARBITRATION 0xffedUL 540 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 541 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 542 #define HWRM_NVM_FLUSH 0xfff0UL 543 #define HWRM_NVM_GET_VARIABLE 0xfff1UL 544 #define HWRM_NVM_SET_VARIABLE 0xfff2UL 545 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 546 #define HWRM_NVM_MODIFY 0xfff4UL 547 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 548 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 549 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 550 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 551 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 552 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 553 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 554 #define HWRM_NVM_RAW_DUMP 0xfffcUL 555 #define HWRM_NVM_READ 0xfffdUL 556 #define HWRM_NVM_WRITE 0xfffeUL 557 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 558 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 559 __le16 unused_0[3]; 560 }; 561 562 /* ret_codes (size:64b/8B) */ 563 struct ret_codes { 564 __le16 error_code; 565 #define HWRM_ERR_CODE_SUCCESS 0x0UL 566 #define HWRM_ERR_CODE_FAIL 0x1UL 567 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 568 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 569 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 570 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 571 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 572 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 573 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 574 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 575 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL 576 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL 577 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL 578 #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL 579 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL 580 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 581 #define HWRM_ERR_CODE_BUSY 0x10UL 582 #define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL 583 #define HWRM_ERR_CODE_PF_UNAVAILABLE 0x12UL 584 #define HWRM_ERR_CODE_ENTITY_NOT_PRESENT 0x13UL 585 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 586 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 587 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 588 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 589 __le16 unused_0[3]; 590 }; 591 592 /* hwrm_err_output (size:128b/16B) */ 593 struct hwrm_err_output { 594 __le16 error_code; 595 __le16 req_type; 596 __le16 seq_id; 597 __le16 resp_len; 598 __le32 opaque_0; 599 __le16 opaque_1; 600 u8 cmd_err; 601 u8 valid; 602 }; 603 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 604 #define HWRM_MAX_REQ_LEN 128 605 #define HWRM_MAX_RESP_LEN 704 606 #define HW_HASH_INDEX_SIZE 0x80 607 #define HW_HASH_KEY_SIZE 40 608 #define HWRM_RESP_VALID_KEY 1 609 #define HWRM_TARGET_ID_BONO 0xFFF8 610 #define HWRM_TARGET_ID_KONG 0xFFF9 611 #define HWRM_TARGET_ID_APE 0xFFFA 612 #define HWRM_TARGET_ID_TOOLS 0xFFFD 613 #define HWRM_VERSION_MAJOR 1 614 #define HWRM_VERSION_MINOR 10 615 #define HWRM_VERSION_UPDATE 3 616 #define HWRM_VERSION_RSVD 44 617 #define HWRM_VERSION_STR "1.10.3.44" 618 619 /* hwrm_ver_get_input (size:192b/24B) */ 620 struct hwrm_ver_get_input { 621 __le16 req_type; 622 __le16 cmpl_ring; 623 __le16 seq_id; 624 __le16 target_id; 625 __le64 resp_addr; 626 u8 hwrm_intf_maj; 627 u8 hwrm_intf_min; 628 u8 hwrm_intf_upd; 629 u8 unused_0[5]; 630 }; 631 632 /* hwrm_ver_get_output (size:1408b/176B) */ 633 struct hwrm_ver_get_output { 634 __le16 error_code; 635 __le16 req_type; 636 __le16 seq_id; 637 __le16 resp_len; 638 u8 hwrm_intf_maj_8b; 639 u8 hwrm_intf_min_8b; 640 u8 hwrm_intf_upd_8b; 641 u8 hwrm_intf_rsvd_8b; 642 u8 hwrm_fw_maj_8b; 643 u8 hwrm_fw_min_8b; 644 u8 hwrm_fw_bld_8b; 645 u8 hwrm_fw_rsvd_8b; 646 u8 mgmt_fw_maj_8b; 647 u8 mgmt_fw_min_8b; 648 u8 mgmt_fw_bld_8b; 649 u8 mgmt_fw_rsvd_8b; 650 u8 netctrl_fw_maj_8b; 651 u8 netctrl_fw_min_8b; 652 u8 netctrl_fw_bld_8b; 653 u8 netctrl_fw_rsvd_8b; 654 __le32 dev_caps_cfg; 655 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 656 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 657 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 658 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 659 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 660 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 661 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 662 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 663 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 664 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL 665 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL 666 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL 667 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL 668 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL 669 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL 670 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE 0x8000UL 671 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_SOC_CAPABLE 0x10000UL 672 u8 roce_fw_maj_8b; 673 u8 roce_fw_min_8b; 674 u8 roce_fw_bld_8b; 675 u8 roce_fw_rsvd_8b; 676 char hwrm_fw_name[16]; 677 char mgmt_fw_name[16]; 678 char netctrl_fw_name[16]; 679 char active_pkg_name[16]; 680 char roce_fw_name[16]; 681 __le16 chip_num; 682 u8 chip_rev; 683 u8 chip_metal; 684 u8 chip_bond_id; 685 u8 chip_platform_type; 686 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 687 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 688 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 689 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 690 __le16 max_req_win_len; 691 __le16 max_resp_len; 692 __le16 def_req_timeout; 693 u8 flags; 694 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 695 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 696 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY_BACKING_STORE 0x4UL 697 u8 unused_0[2]; 698 u8 always_1; 699 __le16 hwrm_intf_major; 700 __le16 hwrm_intf_minor; 701 __le16 hwrm_intf_build; 702 __le16 hwrm_intf_patch; 703 __le16 hwrm_fw_major; 704 __le16 hwrm_fw_minor; 705 __le16 hwrm_fw_build; 706 __le16 hwrm_fw_patch; 707 __le16 mgmt_fw_major; 708 __le16 mgmt_fw_minor; 709 __le16 mgmt_fw_build; 710 __le16 mgmt_fw_patch; 711 __le16 netctrl_fw_major; 712 __le16 netctrl_fw_minor; 713 __le16 netctrl_fw_build; 714 __le16 netctrl_fw_patch; 715 __le16 roce_fw_major; 716 __le16 roce_fw_minor; 717 __le16 roce_fw_build; 718 __le16 roce_fw_patch; 719 __le16 max_ext_req_len; 720 __le16 max_req_timeout; 721 u8 unused_1[3]; 722 u8 valid; 723 }; 724 725 /* eject_cmpl (size:128b/16B) */ 726 struct eject_cmpl { 727 __le16 type; 728 #define EJECT_CMPL_TYPE_MASK 0x3fUL 729 #define EJECT_CMPL_TYPE_SFT 0 730 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 731 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 732 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL 733 #define EJECT_CMPL_FLAGS_SFT 6 734 #define EJECT_CMPL_FLAGS_ERROR 0x40UL 735 __le16 len; 736 __le32 opaque; 737 __le16 v; 738 #define EJECT_CMPL_V 0x1UL 739 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL 740 #define EJECT_CMPL_ERRORS_SFT 1 741 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL 742 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 743 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1) 744 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1) 745 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1) 746 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1) 747 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH 748 __le16 reserved16; 749 __le32 unused_2; 750 }; 751 752 /* hwrm_cmpl (size:128b/16B) */ 753 struct hwrm_cmpl { 754 __le16 type; 755 #define CMPL_TYPE_MASK 0x3fUL 756 #define CMPL_TYPE_SFT 0 757 #define CMPL_TYPE_HWRM_DONE 0x20UL 758 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 759 __le16 sequence_id; 760 __le32 unused_1; 761 __le32 v; 762 #define CMPL_V 0x1UL 763 __le32 unused_3; 764 }; 765 766 /* hwrm_fwd_req_cmpl (size:128b/16B) */ 767 struct hwrm_fwd_req_cmpl { 768 __le16 req_len_type; 769 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 770 #define FWD_REQ_CMPL_TYPE_SFT 0 771 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 772 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 773 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 774 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 775 __le16 source_id; 776 __le32 unused0; 777 __le32 req_buf_addr_v[2]; 778 #define FWD_REQ_CMPL_V 0x1UL 779 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 780 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 781 }; 782 783 /* hwrm_fwd_resp_cmpl (size:128b/16B) */ 784 struct hwrm_fwd_resp_cmpl { 785 __le16 type; 786 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 787 #define FWD_RESP_CMPL_TYPE_SFT 0 788 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 789 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 790 __le16 source_id; 791 __le16 resp_len; 792 __le16 unused_1; 793 __le32 resp_buf_addr_v[2]; 794 #define FWD_RESP_CMPL_V 0x1UL 795 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 796 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 797 }; 798 799 /* hwrm_async_event_cmpl (size:128b/16B) */ 800 struct hwrm_async_event_cmpl { 801 __le16 type; 802 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 803 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 804 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 805 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 806 __le16 event_id; 807 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 808 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 809 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 810 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 811 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 812 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 813 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 814 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 815 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 816 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL 817 #define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG 0xaUL 818 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 819 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 820 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 821 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 822 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 823 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 824 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 825 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 826 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 827 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 828 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 829 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 830 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL 831 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 832 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 833 #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL 834 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL 835 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL 836 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL 837 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL 838 #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL 839 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL 840 #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL 841 #define ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST 0x42UL 842 #define ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE 0x43UL 843 #define ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP 0x44UL 844 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT 0x45UL 845 #define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD 0x46UL 846 #define ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE 0x47UL 847 #define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE 0x48UL 848 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR 0x49UL 849 #define ASYNC_EVENT_CMPL_EVENT_ID_CTX_ERROR 0x4aUL 850 #define ASYNC_EVENT_CMPL_EVENT_ID_UDCC_SESSION_CHANGE 0x4bUL 851 #define ASYNC_EVENT_CMPL_EVENT_ID_DBG_BUF_PRODUCER 0x4cUL 852 #define ASYNC_EVENT_CMPL_EVENT_ID_PEER_MMAP_CHANGE 0x4dUL 853 #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x4eUL 854 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 855 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 856 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 857 __le32 event_data2; 858 u8 opaque_v; 859 #define ASYNC_EVENT_CMPL_V 0x1UL 860 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 861 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 862 u8 timestamp_lo; 863 __le16 timestamp_hi; 864 __le32 event_data1; 865 }; 866 867 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 868 struct hwrm_async_event_cmpl_link_status_change { 869 __le16 type; 870 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 871 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 872 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 873 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 874 __le16 event_id; 875 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 876 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 877 __le32 event_data2; 878 u8 opaque_v; 879 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 880 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 881 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 882 u8 timestamp_lo; 883 __le16 timestamp_hi; 884 __le32 event_data1; 885 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 886 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 887 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 888 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 889 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 890 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 891 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 892 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 893 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 894 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 895 }; 896 897 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 898 struct hwrm_async_event_cmpl_port_conn_not_allowed { 899 __le16 type; 900 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 901 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 902 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 903 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 904 __le16 event_id; 905 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 906 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 907 __le32 event_data2; 908 u8 opaque_v; 909 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 910 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 911 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 912 u8 timestamp_lo; 913 __le16 timestamp_hi; 914 __le32 event_data1; 915 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 916 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 917 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 918 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 919 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 920 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 921 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 922 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 923 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 924 }; 925 926 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 927 struct hwrm_async_event_cmpl_link_speed_cfg_change { 928 __le16 type; 929 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 930 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 931 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 932 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 933 __le16 event_id; 934 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 935 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 936 __le32 event_data2; 937 u8 opaque_v; 938 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 939 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 940 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 941 u8 timestamp_lo; 942 __le16 timestamp_hi; 943 __le32 event_data1; 944 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 945 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 946 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 947 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 948 }; 949 950 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ 951 struct hwrm_async_event_cmpl_reset_notify { 952 __le16 type; 953 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL 954 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 955 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 956 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 957 __le16 event_id; 958 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 959 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 960 __le32 event_data2; 961 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK 0xffffUL 962 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0 963 u8 opaque_v; 964 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 965 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL 966 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 967 u8 timestamp_lo; 968 __le16 timestamp_hi; 969 __le32 event_data1; 970 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL 971 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0 972 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL 973 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL 974 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 975 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL 976 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8 977 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 978 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 979 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 980 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET (0x4UL << 8) 981 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION (0x5UL << 8) 982 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION 983 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 984 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 985 }; 986 987 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ 988 struct hwrm_async_event_cmpl_error_recovery { 989 __le16 type; 990 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL 991 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 992 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 993 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 994 __le16 event_id; 995 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL 996 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 997 __le32 event_data2; 998 u8 opaque_v; 999 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL 1000 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL 1001 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 1002 u8 timestamp_lo; 1003 __le16 timestamp_hi; 1004 __le32 event_data1; 1005 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL 1006 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0 1007 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL 1008 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL 1009 }; 1010 1011 /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */ 1012 struct hwrm_async_event_cmpl_ring_monitor_msg { 1013 __le16 type; 1014 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK 0x3fUL 1015 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0 1016 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1017 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 1018 __le16 event_id; 1019 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL 1020 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 1021 __le32 event_data2; 1022 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL 1023 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0 1024 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX 0x0UL 1025 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX 0x1UL 1026 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 0x2UL 1027 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 1028 u8 opaque_v; 1029 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V 0x1UL 1030 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL 1031 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1 1032 u8 timestamp_lo; 1033 __le16 timestamp_hi; 1034 __le32 event_data1; 1035 }; 1036 1037 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 1038 struct hwrm_async_event_cmpl_vf_cfg_change { 1039 __le16 type; 1040 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 1041 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 1042 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1043 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 1044 __le16 event_id; 1045 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 1046 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 1047 __le32 event_data2; 1048 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK 0xffffUL 1049 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0 1050 u8 opaque_v; 1051 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 1052 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 1053 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 1054 u8 timestamp_lo; 1055 __le16 timestamp_hi; 1056 __le32 event_data1; 1057 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 1058 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 1059 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 1060 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 1061 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 1062 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TF_OWNERSHIP_RELEASE 0x20UL 1063 }; 1064 1065 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ 1066 struct hwrm_async_event_cmpl_default_vnic_change { 1067 __le16 type; 1068 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL 1069 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0 1070 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1071 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 1072 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL 1073 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6 1074 __le16 event_id; 1075 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL 1076 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 1077 __le32 event_data2; 1078 u8 opaque_v; 1079 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL 1080 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL 1081 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1 1082 u8 timestamp_lo; 1083 __le16 timestamp_hi; 1084 __le32 event_data1; 1085 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL 1086 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0 1087 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL 1088 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL 1089 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 1090 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL 1091 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2 1092 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL 1093 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10 1094 }; 1095 1096 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ 1097 struct hwrm_async_event_cmpl_hw_flow_aged { 1098 __le16 type; 1099 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL 1100 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 1101 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1102 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 1103 __le16 event_id; 1104 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL 1105 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 1106 __le32 event_data2; 1107 u8 opaque_v; 1108 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL 1109 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL 1110 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 1111 u8 timestamp_lo; 1112 __le16 timestamp_hi; 1113 __le32 event_data1; 1114 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL 1115 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0 1116 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL 1117 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31) 1118 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31) 1119 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX 1120 }; 1121 1122 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ 1123 struct hwrm_async_event_cmpl_eem_cache_flush_req { 1124 __le16 type; 1125 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL 1126 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0 1127 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1128 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 1129 __le16 event_id; 1130 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 1131 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 1132 __le32 event_data2; 1133 u8 opaque_v; 1134 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL 1135 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL 1136 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 1137 u8 timestamp_lo; 1138 __le16 timestamp_hi; 1139 __le32 event_data1; 1140 }; 1141 1142 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ 1143 struct hwrm_async_event_cmpl_eem_cache_flush_done { 1144 __le16 type; 1145 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL 1146 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0 1147 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1148 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 1149 __le16 event_id; 1150 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 1151 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 1152 __le32 event_data2; 1153 u8 opaque_v; 1154 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL 1155 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL 1156 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 1157 u8 timestamp_lo; 1158 __le16 timestamp_hi; 1159 __le32 event_data1; 1160 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL 1161 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0 1162 }; 1163 1164 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ 1165 struct hwrm_async_event_cmpl_deferred_response { 1166 __le16 type; 1167 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK 0x3fUL 1168 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0 1169 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1170 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 1171 __le16 event_id; 1172 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL 1173 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 1174 __le32 event_data2; 1175 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL 1176 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0 1177 u8 opaque_v; 1178 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V 0x1UL 1179 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL 1180 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1 1181 u8 timestamp_lo; 1182 __le16 timestamp_hi; 1183 __le32 event_data1; 1184 }; 1185 1186 /* hwrm_async_event_cmpl_echo_request (size:128b/16B) */ 1187 struct hwrm_async_event_cmpl_echo_request { 1188 __le16 type; 1189 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK 0x3fUL 1190 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0 1191 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1192 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 1193 __le16 event_id; 1194 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 0x42UL 1195 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 1196 __le32 event_data2; 1197 u8 opaque_v; 1198 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_V 0x1UL 1199 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK 0xfeUL 1200 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1 1201 u8 timestamp_lo; 1202 __le16 timestamp_hi; 1203 __le32 event_data1; 1204 }; 1205 1206 /* hwrm_async_event_cmpl_phc_update (size:128b/16B) */ 1207 struct hwrm_async_event_cmpl_phc_update { 1208 __le16 type; 1209 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_MASK 0x3fUL 1210 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_SFT 0 1211 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1212 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT 1213 __le16 event_id; 1214 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 0x43UL 1215 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 1216 __le32 event_data2; 1217 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_MASK 0xffffUL 1218 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_SFT 0 1219 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_MASK 0xffff0000UL 1220 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_SFT 16 1221 u8 opaque_v; 1222 #define ASYNC_EVENT_CMPL_PHC_UPDATE_V 0x1UL 1223 #define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_MASK 0xfeUL 1224 #define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_SFT 1 1225 u8 timestamp_lo; 1226 __le16 timestamp_hi; 1227 __le32 event_data1; 1228 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK 0xfUL 1229 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT 0 1230 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_MASTER 0x1UL 1231 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_SECONDARY 0x2UL 1232 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_FAILOVER 0x3UL 1233 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE 0x4UL 1234 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE 1235 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK 0xffff0UL 1236 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT 4 1237 }; 1238 1239 /* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */ 1240 struct hwrm_async_event_cmpl_pps_timestamp { 1241 __le16 type; 1242 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK 0x3fUL 1243 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0 1244 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1245 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 1246 __le16 event_id; 1247 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 0x44UL 1248 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 1249 __le32 event_data2; 1250 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE 0x1UL 1251 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL 0x0UL 1252 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 0x1UL 1253 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 1254 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK 0xeUL 1255 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT 1 1256 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK 0xffff0UL 1257 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT 4 1258 u8 opaque_v; 1259 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V 0x1UL 1260 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK 0xfeUL 1261 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1 1262 u8 timestamp_lo; 1263 __le16 timestamp_hi; 1264 __le32 event_data1; 1265 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK 0xffffffffUL 1266 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT 0 1267 }; 1268 1269 /* hwrm_async_event_cmpl_error_report (size:128b/16B) */ 1270 struct hwrm_async_event_cmpl_error_report { 1271 __le16 type; 1272 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK 0x3fUL 1273 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0 1274 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1275 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 1276 __le16 event_id; 1277 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 0x45UL 1278 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 1279 __le32 event_data2; 1280 u8 opaque_v; 1281 #define ASYNC_EVENT_CMPL_ERROR_REPORT_V 0x1UL 1282 #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK 0xfeUL 1283 #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1 1284 u8 timestamp_lo; 1285 __le16 timestamp_hi; 1286 __le32 event_data1; 1287 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1288 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0 1289 }; 1290 1291 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */ 1292 struct hwrm_async_event_cmpl_hwrm_error { 1293 __le16 type; 1294 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL 1295 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 1296 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1297 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 1298 __le16 event_id; 1299 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL 1300 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 1301 __le32 event_data2; 1302 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL 1303 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 1304 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL 1305 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL 1306 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL 1307 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 1308 u8 opaque_v; 1309 #define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL 1310 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL 1311 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 1312 u8 timestamp_lo; 1313 __le16 timestamp_hi; 1314 __le32 event_data1; 1315 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL 1316 }; 1317 1318 /* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */ 1319 struct hwrm_async_event_cmpl_error_report_base { 1320 __le16 type; 1321 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK 0x3fUL 1322 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0 1323 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1324 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 1325 __le16 event_id; 1326 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 0x45UL 1327 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 1328 __le32 event_data2; 1329 u8 opaque_v; 1330 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V 0x1UL 1331 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK 0xfeUL 1332 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1 1333 u8 timestamp_lo; 1334 __le16 timestamp_hi; 1335 __le32 event_data1; 1336 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1337 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT 0 1338 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED 0x0UL 1339 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 1340 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 1341 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM 0x3UL 1342 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL 1343 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD 0x5UL 1344 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 0x6UL 1345 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 1346 }; 1347 1348 /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ 1349 struct hwrm_async_event_cmpl_error_report_pause_storm { 1350 __le16 type; 1351 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK 0x3fUL 1352 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT 0 1353 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1354 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 1355 __le16 event_id; 1356 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 0x45UL 1357 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 1358 __le32 event_data2; 1359 u8 opaque_v; 1360 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V 0x1UL 1361 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK 0xfeUL 1362 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1 1363 u8 timestamp_lo; 1364 __le16 timestamp_hi; 1365 __le32 event_data1; 1366 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1367 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT 0 1368 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 1369 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 1370 }; 1371 1372 /* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */ 1373 struct hwrm_async_event_cmpl_error_report_invalid_signal { 1374 __le16 type; 1375 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK 0x3fUL 1376 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT 0 1377 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1378 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 1379 __le16 event_id; 1380 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 0x45UL 1381 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 1382 __le32 event_data2; 1383 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK 0xffUL 1384 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT 0 1385 u8 opaque_v; 1386 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V 0x1UL 1387 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK 0xfeUL 1388 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1 1389 u8 timestamp_lo; 1390 __le16 timestamp_hi; 1391 __le32 event_data1; 1392 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1393 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT 0 1394 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 1395 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 1396 }; 1397 1398 /* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */ 1399 struct hwrm_async_event_cmpl_error_report_nvm { 1400 __le16 type; 1401 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK 0x3fUL 1402 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0 1403 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1404 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 1405 __le16 event_id; 1406 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 0x45UL 1407 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 1408 __le32 event_data2; 1409 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK 0xffffffffUL 1410 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT 0 1411 u8 opaque_v; 1412 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V 0x1UL 1413 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK 0xfeUL 1414 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1 1415 u8 timestamp_lo; 1416 __le16 timestamp_hi; 1417 __le32 event_data1; 1418 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1419 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT 0 1420 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 0x3UL 1421 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 1422 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK 0xff00UL 1423 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT 8 1424 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE (0x1UL << 8) 1425 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE (0x2UL << 8) 1426 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE 1427 }; 1428 1429 /* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */ 1430 struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold { 1431 __le16 type; 1432 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK 0x3fUL 1433 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT 0 1434 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1435 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT 1436 __le16 event_id; 1437 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT 0x45UL 1438 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT 1439 __le32 event_data2; 1440 u8 opaque_v; 1441 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V 0x1UL 1442 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK 0xfeUL 1443 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT 1 1444 u8 timestamp_lo; 1445 __le16 timestamp_hi; 1446 __le32 event_data1; 1447 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1448 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT 0 1449 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL 1450 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 1451 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK 0xffffff00UL 1452 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT 8 1453 }; 1454 1455 /* hwrm_async_event_cmpl_error_report_thermal (size:128b/16B) */ 1456 struct hwrm_async_event_cmpl_error_report_thermal { 1457 __le16 type; 1458 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_MASK 0x3fUL 1459 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_SFT 0 1460 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1461 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT 1462 __le16 event_id; 1463 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT 0x45UL 1464 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT 1465 __le32 event_data2; 1466 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK 0xffUL 1467 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_SFT 0 1468 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_MASK 0xff00UL 1469 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_SFT 8 1470 u8 opaque_v; 1471 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_V 0x1UL 1472 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_MASK 0xfeUL 1473 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_SFT 1 1474 u8 timestamp_lo; 1475 __le16 timestamp_hi; 1476 __le32 event_data1; 1477 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1478 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_SFT 0 1479 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT 0x5UL 1480 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT 1481 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_MASK 0x700UL 1482 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SFT 8 1483 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_WARN (0x0UL << 8) 1484 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_CRITICAL (0x1UL << 8) 1485 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_FATAL (0x2UL << 8) 1486 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN (0x3UL << 8) 1487 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN 1488 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR 0x800UL 1489 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_DECREASING (0x0UL << 11) 1490 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING (0x1UL << 11) 1491 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING 1492 }; 1493 1494 /* hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported (size:128b/16B) */ 1495 struct hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported { 1496 __le16 type; 1497 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_MASK 0x3fUL 1498 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_SFT 0 1499 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1500 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT 1501 __le16 event_id; 1502 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT 0x45UL 1503 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT 1504 __le32 event_data2; 1505 u8 opaque_v; 1506 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_V 0x1UL 1507 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_MASK 0xfeUL 1508 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_SFT 1 1509 u8 timestamp_lo; 1510 __le16 timestamp_hi; 1511 __le32 event_data1; 1512 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1513 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_SFT 0 1514 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 0x6UL 1515 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 1516 }; 1517 1518 /* hwrm_func_reset_input (size:192b/24B) */ 1519 struct hwrm_func_reset_input { 1520 __le16 req_type; 1521 __le16 cmpl_ring; 1522 __le16 seq_id; 1523 __le16 target_id; 1524 __le64 resp_addr; 1525 __le32 enables; 1526 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 1527 __le16 vf_id; 1528 u8 func_reset_level; 1529 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 1530 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 1531 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 1532 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 1533 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 1534 u8 unused_0; 1535 }; 1536 1537 /* hwrm_func_reset_output (size:128b/16B) */ 1538 struct hwrm_func_reset_output { 1539 __le16 error_code; 1540 __le16 req_type; 1541 __le16 seq_id; 1542 __le16 resp_len; 1543 u8 unused_0[7]; 1544 u8 valid; 1545 }; 1546 1547 /* hwrm_func_getfid_input (size:192b/24B) */ 1548 struct hwrm_func_getfid_input { 1549 __le16 req_type; 1550 __le16 cmpl_ring; 1551 __le16 seq_id; 1552 __le16 target_id; 1553 __le64 resp_addr; 1554 __le32 enables; 1555 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 1556 __le16 pci_id; 1557 u8 unused_0[2]; 1558 }; 1559 1560 /* hwrm_func_getfid_output (size:128b/16B) */ 1561 struct hwrm_func_getfid_output { 1562 __le16 error_code; 1563 __le16 req_type; 1564 __le16 seq_id; 1565 __le16 resp_len; 1566 __le16 fid; 1567 u8 unused_0[5]; 1568 u8 valid; 1569 }; 1570 1571 /* hwrm_func_vf_alloc_input (size:192b/24B) */ 1572 struct hwrm_func_vf_alloc_input { 1573 __le16 req_type; 1574 __le16 cmpl_ring; 1575 __le16 seq_id; 1576 __le16 target_id; 1577 __le64 resp_addr; 1578 __le32 enables; 1579 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 1580 __le16 first_vf_id; 1581 __le16 num_vfs; 1582 }; 1583 1584 /* hwrm_func_vf_alloc_output (size:128b/16B) */ 1585 struct hwrm_func_vf_alloc_output { 1586 __le16 error_code; 1587 __le16 req_type; 1588 __le16 seq_id; 1589 __le16 resp_len; 1590 __le16 first_vf_id; 1591 u8 unused_0[5]; 1592 u8 valid; 1593 }; 1594 1595 /* hwrm_func_vf_free_input (size:192b/24B) */ 1596 struct hwrm_func_vf_free_input { 1597 __le16 req_type; 1598 __le16 cmpl_ring; 1599 __le16 seq_id; 1600 __le16 target_id; 1601 __le64 resp_addr; 1602 __le32 enables; 1603 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 1604 __le16 first_vf_id; 1605 __le16 num_vfs; 1606 }; 1607 1608 /* hwrm_func_vf_free_output (size:128b/16B) */ 1609 struct hwrm_func_vf_free_output { 1610 __le16 error_code; 1611 __le16 req_type; 1612 __le16 seq_id; 1613 __le16 resp_len; 1614 u8 unused_0[7]; 1615 u8 valid; 1616 }; 1617 1618 /* hwrm_func_vf_cfg_input (size:576b/72B) */ 1619 struct hwrm_func_vf_cfg_input { 1620 __le16 req_type; 1621 __le16 cmpl_ring; 1622 __le16 seq_id; 1623 __le16 target_id; 1624 __le64 resp_addr; 1625 __le32 enables; 1626 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 1627 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 1628 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 1629 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 1630 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 1631 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 1632 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 1633 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 1634 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 1635 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 1636 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 1637 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 1638 #define FUNC_VF_CFG_REQ_ENABLES_NUM_KTLS_TX_KEY_CTXS 0x1000UL 1639 #define FUNC_VF_CFG_REQ_ENABLES_NUM_KTLS_RX_KEY_CTXS 0x2000UL 1640 #define FUNC_VF_CFG_REQ_ENABLES_NUM_QUIC_TX_KEY_CTXS 0x4000UL 1641 #define FUNC_VF_CFG_REQ_ENABLES_NUM_QUIC_RX_KEY_CTXS 0x8000UL 1642 __le16 mtu; 1643 __le16 guest_vlan; 1644 __le16 async_event_cr; 1645 u8 dflt_mac_addr[6]; 1646 __le32 flags; 1647 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 1648 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 1649 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 1650 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 1651 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 1652 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 1653 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 1654 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 1655 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x100UL 1656 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x200UL 1657 __le16 num_rsscos_ctxs; 1658 __le16 num_cmpl_rings; 1659 __le16 num_tx_rings; 1660 __le16 num_rx_rings; 1661 __le16 num_l2_ctxs; 1662 __le16 num_vnics; 1663 __le16 num_stat_ctxs; 1664 __le16 num_hw_ring_grps; 1665 __le32 num_ktls_tx_key_ctxs; 1666 __le32 num_ktls_rx_key_ctxs; 1667 __le16 num_msix; 1668 u8 unused[2]; 1669 __le32 num_quic_tx_key_ctxs; 1670 __le32 num_quic_rx_key_ctxs; 1671 }; 1672 1673 /* hwrm_func_vf_cfg_output (size:128b/16B) */ 1674 struct hwrm_func_vf_cfg_output { 1675 __le16 error_code; 1676 __le16 req_type; 1677 __le16 seq_id; 1678 __le16 resp_len; 1679 u8 unused_0[7]; 1680 u8 valid; 1681 }; 1682 1683 /* hwrm_func_qcaps_input (size:192b/24B) */ 1684 struct hwrm_func_qcaps_input { 1685 __le16 req_type; 1686 __le16 cmpl_ring; 1687 __le16 seq_id; 1688 __le16 target_id; 1689 __le64 resp_addr; 1690 __le16 fid; 1691 u8 unused_0[6]; 1692 }; 1693 1694 /* hwrm_func_qcaps_output (size:1088b/136B) */ 1695 struct hwrm_func_qcaps_output { 1696 __le16 error_code; 1697 __le16 req_type; 1698 __le16 seq_id; 1699 __le16 resp_len; 1700 __le16 fid; 1701 __le16 port_id; 1702 __le32 flags; 1703 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1704 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 1705 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1706 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1707 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1708 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1709 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1710 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1711 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1712 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1713 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 1714 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 1715 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 1716 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 1717 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 1718 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 1719 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 1720 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 1721 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 1722 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 1723 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 1724 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL 1725 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL 1726 #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL 1727 #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL 1728 #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL 1729 #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL 1730 #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL 1731 #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL 1732 #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL 1733 #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL 1734 #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL 1735 u8 mac_address[6]; 1736 __le16 max_rsscos_ctx; 1737 __le16 max_cmpl_rings; 1738 __le16 max_tx_rings; 1739 __le16 max_rx_rings; 1740 __le16 max_l2_ctxs; 1741 __le16 max_vnics; 1742 __le16 first_vf_id; 1743 __le16 max_vfs; 1744 __le16 max_stat_ctx; 1745 __le32 max_encap_records; 1746 __le32 max_decap_records; 1747 __le32 max_tx_em_flows; 1748 __le32 max_tx_wm_flows; 1749 __le32 max_rx_em_flows; 1750 __le32 max_rx_wm_flows; 1751 __le32 max_mcast_filters; 1752 __le32 max_flow_id; 1753 __le32 max_hw_ring_grps; 1754 __le16 max_sp_tx_rings; 1755 __le16 max_msix_vfs; 1756 __le32 flags_ext; 1757 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL 1758 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL 1759 #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL 1760 #define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT 0x8UL 1761 #define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT 0x10UL 1762 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL 1763 #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL 1764 #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL 1765 #define FUNC_QCAPS_RESP_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED 0x100UL 1766 #define FUNC_QCAPS_RESP_FLAGS_EXT_SOC_SPD_SUPPORTED 0x200UL 1767 #define FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED 0x400UL 1768 #define FUNC_QCAPS_RESP_FLAGS_EXT_FAST_RESET_CAPABLE 0x800UL 1769 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_METADATA_CFG_CAPABLE 0x1000UL 1770 #define FUNC_QCAPS_RESP_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED 0x2000UL 1771 #define FUNC_QCAPS_RESP_FLAGS_EXT_BD_METADATA_SUPPORTED 0x4000UL 1772 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECHO_REQUEST_SUPPORTED 0x8000UL 1773 #define FUNC_QCAPS_RESP_FLAGS_EXT_NPAR_1_2_SUPPORTED 0x10000UL 1774 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PTM_SUPPORTED 0x20000UL 1775 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED 0x40000UL 1776 #define FUNC_QCAPS_RESP_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED 0x80000UL 1777 #define FUNC_QCAPS_RESP_FLAGS_EXT_PARTITION_BW_SUPPORTED 0x100000UL 1778 #define FUNC_QCAPS_RESP_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED 0x200000UL 1779 #define FUNC_QCAPS_RESP_FLAGS_EXT_KTLS_SUPPORTED 0x400000UL 1780 #define FUNC_QCAPS_RESP_FLAGS_EXT_EP_RATE_CONTROL 0x800000UL 1781 #define FUNC_QCAPS_RESP_FLAGS_EXT_MIN_BW_SUPPORTED 0x1000000UL 1782 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_COAL_CMPL_CAP 0x2000000UL 1783 #define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_SUPPORTED 0x4000000UL 1784 #define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_REQUIRED 0x8000000UL 1785 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED 0x10000000UL 1786 #define FUNC_QCAPS_RESP_FLAGS_EXT_DBR_PACING_SUPPORTED 0x20000000UL 1787 #define FUNC_QCAPS_RESP_FLAGS_EXT_HW_DBR_DROP_RECOV_SUPPORTED 0x40000000UL 1788 #define FUNC_QCAPS_RESP_FLAGS_EXT_DISABLE_CQ_OVERFLOW_DETECTION_SUPPORTED 0x80000000UL 1789 u8 max_schqs; 1790 u8 mpc_chnls_cap; 1791 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL 1792 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE 0x2UL 1793 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA 0x4UL 1794 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA 0x8UL 1795 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE 0x10UL 1796 __le16 max_key_ctxs_alloc; 1797 __le32 flags_ext2; 1798 #define FUNC_QCAPS_RESP_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED 0x1UL 1799 #define FUNC_QCAPS_RESP_FLAGS_EXT2_QUIC_SUPPORTED 0x2UL 1800 #define FUNC_QCAPS_RESP_FLAGS_EXT2_KDNET_SUPPORTED 0x4UL 1801 #define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED 0x8UL 1802 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED 0x10UL 1803 #define FUNC_QCAPS_RESP_FLAGS_EXT2_GENERIC_STATS_SUPPORTED 0x20UL 1804 #define FUNC_QCAPS_RESP_FLAGS_EXT2_UDP_GSO_SUPPORTED 0x40UL 1805 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SYNCE_SUPPORTED 0x80UL 1806 #define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED 0x100UL 1807 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TX_PKT_TS_CMPL_SUPPORTED 0x200UL 1808 #define FUNC_QCAPS_RESP_FLAGS_EXT2_HW_LAG_SUPPORTED 0x400UL 1809 #define FUNC_QCAPS_RESP_FLAGS_EXT2_ON_CHIP_CTX_SUPPORTED 0x800UL 1810 #define FUNC_QCAPS_RESP_FLAGS_EXT2_STEERING_TAG_SUPPORTED 0x1000UL 1811 #define FUNC_QCAPS_RESP_FLAGS_EXT2_ENHANCED_VF_SCALE_SUPPORTED 0x2000UL 1812 #define FUNC_QCAPS_RESP_FLAGS_EXT2_KEY_XID_PARTITION_SUPPORTED 0x4000UL 1813 #define FUNC_QCAPS_RESP_FLAGS_EXT2_CONCURRENT_KTLS_QUIC_SUPPORTED 0x8000UL 1814 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_CROSS_TC_CAP_SUPPORTED 0x10000UL 1815 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_PER_TC_CAP_SUPPORTED 0x20000UL 1816 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_PER_TC_RESERVATION_SUPPORTED 0x40000UL 1817 #define FUNC_QCAPS_RESP_FLAGS_EXT2_DB_ERROR_STATS_SUPPORTED 0x80000UL 1818 #define FUNC_QCAPS_RESP_FLAGS_EXT2_ROCE_VF_RESOURCE_MGMT_SUPPORTED 0x100000UL 1819 #define FUNC_QCAPS_RESP_FLAGS_EXT2_UDCC_SUPPORTED 0x200000UL 1820 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TIMED_TX_SO_TXTIME_SUPPORTED 0x400000UL 1821 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_MAX_RESOURCE_LIMITS_SUPPORTED 0x800000UL 1822 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TF_INGRESS_NIC_FLOW_SUPPORTED 0x1000000UL 1823 #define FUNC_QCAPS_RESP_FLAGS_EXT2_LPBK_STATS_SUPPORTED 0x2000000UL 1824 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TF_EGRESS_NIC_FLOW_SUPPORTED 0x4000000UL 1825 #define FUNC_QCAPS_RESP_FLAGS_EXT2_MULTI_LOSSLESS_QUEUES_SUPPORTED 0x8000000UL 1826 #define FUNC_QCAPS_RESP_FLAGS_EXT2_PEER_MMAP_SUPPORTED 0x10000000UL 1827 __le16 tunnel_disable_flag; 1828 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN 0x1UL 1829 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NGE 0x2UL 1830 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NVGRE 0x4UL 1831 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_L2GRE 0x8UL 1832 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_GRE 0x10UL 1833 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP 0x20UL 1834 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_MPLS 0x40UL 1835 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE 0x80UL 1836 __le16 xid_partition_cap; 1837 #define FUNC_QCAPS_RESP_XID_PARTITION_CAP_TX_CK 0x1UL 1838 #define FUNC_QCAPS_RESP_XID_PARTITION_CAP_RX_CK 0x2UL 1839 u8 device_serial_number[8]; 1840 __le16 ctxs_per_partition; 1841 __le16 max_tso_segs; 1842 __le32 roce_vf_max_av; 1843 __le32 roce_vf_max_cq; 1844 __le32 roce_vf_max_mrw; 1845 __le32 roce_vf_max_qp; 1846 __le32 roce_vf_max_srq; 1847 __le32 roce_vf_max_gid; 1848 u8 unused_3[3]; 1849 u8 valid; 1850 }; 1851 1852 /* hwrm_func_qcfg_input (size:192b/24B) */ 1853 struct hwrm_func_qcfg_input { 1854 __le16 req_type; 1855 __le16 cmpl_ring; 1856 __le16 seq_id; 1857 __le16 target_id; 1858 __le64 resp_addr; 1859 __le16 fid; 1860 u8 unused_0[6]; 1861 }; 1862 1863 /* hwrm_func_qcfg_output (size:1280b/160B) */ 1864 struct hwrm_func_qcfg_output { 1865 __le16 error_code; 1866 __le16 req_type; 1867 __le16 seq_id; 1868 __le16 resp_len; 1869 __le16 fid; 1870 __le16 port_id; 1871 __le16 vlan; 1872 __le16 flags; 1873 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1874 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1875 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 1876 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 1877 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 1878 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 1879 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 1880 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL 1881 #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL 1882 #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL 1883 #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL 1884 #define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL 1885 #define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED 0x1000UL 1886 #define FUNC_QCFG_RESP_FLAGS_MULTI_ROOT 0x2000UL 1887 #define FUNC_QCFG_RESP_FLAGS_ENABLE_RDMA_SRIOV 0x4000UL 1888 #define FUNC_QCFG_RESP_FLAGS_ROCE_VNIC_ID_VALID 0x8000UL 1889 u8 mac_address[6]; 1890 __le16 pci_id; 1891 __le16 alloc_rsscos_ctx; 1892 __le16 alloc_cmpl_rings; 1893 __le16 alloc_tx_rings; 1894 __le16 alloc_rx_rings; 1895 __le16 alloc_l2_ctx; 1896 __le16 alloc_vnics; 1897 __le16 admin_mtu; 1898 __le16 mru; 1899 __le16 stat_ctx_id; 1900 u8 port_partition_type; 1901 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1902 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1903 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1904 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1905 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 1906 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_2 0x5UL 1907 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 1908 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 1909 u8 port_pf_cnt; 1910 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 1911 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 1912 __le16 dflt_vnic_id; 1913 __le16 max_mtu_configured; 1914 __le32 min_bw; 1915 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1916 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 1917 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 1918 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 1919 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 1920 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 1921 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1922 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 1923 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1924 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1925 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1926 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1927 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1928 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1929 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 1930 __le32 max_bw; 1931 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1932 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 1933 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 1934 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 1935 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 1936 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 1937 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1938 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 1939 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1940 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1941 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1942 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1943 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1944 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1945 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 1946 u8 evb_mode; 1947 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 1948 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 1949 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 1950 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 1951 u8 options; 1952 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1953 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 1954 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1955 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1956 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 1957 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1958 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 1959 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1960 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1961 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1962 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 1963 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 1964 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 1965 __le16 alloc_vfs; 1966 __le32 alloc_mcast_filters; 1967 __le32 alloc_hw_ring_grps; 1968 __le16 alloc_sp_tx_rings; 1969 __le16 alloc_stat_ctx; 1970 __le16 alloc_msix; 1971 __le16 registered_vfs; 1972 __le16 l2_doorbell_bar_size_kb; 1973 u8 active_endpoints; 1974 u8 always_1; 1975 __le32 reset_addr_poll; 1976 __le16 legacy_l2_db_size_kb; 1977 __le16 svif_info; 1978 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL 1979 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0 1980 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL 1981 u8 mpc_chnls; 1982 #define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED 0x1UL 1983 #define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED 0x2UL 1984 #define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL 1985 #define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL 1986 #define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL 1987 u8 db_page_size; 1988 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_4KB 0x0UL 1989 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_8KB 0x1UL 1990 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_16KB 0x2UL 1991 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_32KB 0x3UL 1992 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_64KB 0x4UL 1993 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_128KB 0x5UL 1994 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_256KB 0x6UL 1995 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_512KB 0x7UL 1996 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_1MB 0x8UL 1997 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_2MB 0x9UL 1998 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB 0xaUL 1999 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_LAST FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB 2000 __le16 roce_vnic_id; 2001 __le32 partition_min_bw; 2002 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2003 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_SFT 0 2004 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE 0x10000000UL 2005 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 2006 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 2007 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES 2008 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2009 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 2010 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2011 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 2012 __le32 partition_max_bw; 2013 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2014 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_SFT 0 2015 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE 0x10000000UL 2016 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 2017 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 2018 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES 2019 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2020 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 2021 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2022 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 2023 __le16 host_mtu; 2024 u8 unused_3[2]; 2025 u8 unused_4[2]; 2026 u8 port_kdnet_mode; 2027 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_DISABLED 0x0UL 2028 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED 0x1UL 2029 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_LAST FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED 2030 u8 kdnet_pcie_function; 2031 __le16 port_kdnet_fid; 2032 u8 unused_5[2]; 2033 __le32 num_ktls_tx_key_ctxs; 2034 __le32 num_ktls_rx_key_ctxs; 2035 u8 lag_id; 2036 u8 parif; 2037 u8 fw_lag_id; 2038 u8 unused_6; 2039 __le32 num_quic_tx_key_ctxs; 2040 __le32 num_quic_rx_key_ctxs; 2041 __le32 roce_max_av_per_vf; 2042 __le32 roce_max_cq_per_vf; 2043 __le32 roce_max_mrw_per_vf; 2044 __le32 roce_max_qp_per_vf; 2045 __le32 roce_max_srq_per_vf; 2046 __le32 roce_max_gid_per_vf; 2047 __le16 xid_partition_cfg; 2048 #define FUNC_QCFG_RESP_XID_PARTITION_CFG_TX_CK 0x1UL 2049 #define FUNC_QCFG_RESP_XID_PARTITION_CFG_RX_CK 0x2UL 2050 u8 unused_7; 2051 u8 valid; 2052 }; 2053 2054 /* hwrm_func_cfg_input (size:1280b/160B) */ 2055 struct hwrm_func_cfg_input { 2056 __le16 req_type; 2057 __le16 cmpl_ring; 2058 __le16 seq_id; 2059 __le16 target_id; 2060 __le64 resp_addr; 2061 __le16 fid; 2062 __le16 num_msix; 2063 __le32 flags; 2064 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 2065 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 2066 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 2067 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 2068 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 2069 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 2070 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 2071 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 2072 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 2073 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 2074 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 2075 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 2076 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 2077 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 2078 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 2079 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 2080 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 2081 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL 2082 #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL 2083 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL 2084 #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL 2085 #define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS 0x4000000UL 2086 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x8000000UL 2087 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL 2088 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_ENABLE 0x20000000UL 2089 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_DISABLE 0x40000000UL 2090 __le32 enables; 2091 #define FUNC_CFG_REQ_ENABLES_ADMIN_MTU 0x1UL 2092 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 2093 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 2094 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 2095 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 2096 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 2097 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 2098 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 2099 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 2100 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 2101 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 2102 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 2103 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 2104 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 2105 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 2106 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 2107 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 2108 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 2109 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 2110 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 2111 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 2112 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 2113 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 2114 #define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL 2115 #define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL 2116 #define FUNC_CFG_REQ_ENABLES_MPC_CHNLS 0x2000000UL 2117 #define FUNC_CFG_REQ_ENABLES_PARTITION_MIN_BW 0x4000000UL 2118 #define FUNC_CFG_REQ_ENABLES_PARTITION_MAX_BW 0x8000000UL 2119 #define FUNC_CFG_REQ_ENABLES_TPID 0x10000000UL 2120 #define FUNC_CFG_REQ_ENABLES_HOST_MTU 0x20000000UL 2121 #define FUNC_CFG_REQ_ENABLES_KTLS_TX_KEY_CTXS 0x40000000UL 2122 #define FUNC_CFG_REQ_ENABLES_KTLS_RX_KEY_CTXS 0x80000000UL 2123 __le16 admin_mtu; 2124 __le16 mru; 2125 __le16 num_rsscos_ctxs; 2126 __le16 num_cmpl_rings; 2127 __le16 num_tx_rings; 2128 __le16 num_rx_rings; 2129 __le16 num_l2_ctxs; 2130 __le16 num_vnics; 2131 __le16 num_stat_ctxs; 2132 __le16 num_hw_ring_grps; 2133 u8 dflt_mac_addr[6]; 2134 __le16 dflt_vlan; 2135 __be32 dflt_ip_addr[4]; 2136 __le32 min_bw; 2137 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2138 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 2139 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 2140 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 2141 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 2142 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 2143 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2144 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 2145 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2146 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2147 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2148 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2149 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2150 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2151 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 2152 __le32 max_bw; 2153 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2154 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 2155 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 2156 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 2157 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 2158 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 2159 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2160 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 2161 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2162 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2163 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2164 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2165 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2166 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2167 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 2168 __le16 async_event_cr; 2169 u8 vlan_antispoof_mode; 2170 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 2171 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 2172 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 2173 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 2174 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 2175 u8 allowed_vlan_pris; 2176 u8 evb_mode; 2177 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 2178 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 2179 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 2180 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 2181 u8 options; 2182 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 2183 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 2184 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 2185 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 2186 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 2187 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 2188 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 2189 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 2190 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 2191 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 2192 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 2193 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 2194 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 2195 __le16 num_mcast_filters; 2196 __le16 schq_id; 2197 __le16 mpc_chnls; 2198 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE 0x1UL 2199 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE 0x2UL 2200 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE 0x4UL 2201 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE 0x8UL 2202 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE 0x10UL 2203 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE 0x20UL 2204 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE 0x40UL 2205 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE 0x80UL 2206 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE 0x100UL 2207 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE 0x200UL 2208 __le32 partition_min_bw; 2209 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2210 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_SFT 0 2211 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE 0x10000000UL 2212 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 2213 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 2214 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES 2215 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2216 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 2217 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2218 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 2219 __le32 partition_max_bw; 2220 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2221 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_SFT 0 2222 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE 0x10000000UL 2223 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 2224 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 2225 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES 2226 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2227 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 2228 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2229 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 2230 __be16 tpid; 2231 __le16 host_mtu; 2232 __le32 flags2; 2233 #define FUNC_CFG_REQ_FLAGS2_KTLS_KEY_CTX_ASSETS_TEST 0x1UL 2234 #define FUNC_CFG_REQ_FLAGS2_QUIC_KEY_CTX_ASSETS_TEST 0x2UL 2235 __le32 enables2; 2236 #define FUNC_CFG_REQ_ENABLES2_KDNET 0x1UL 2237 #define FUNC_CFG_REQ_ENABLES2_DB_PAGE_SIZE 0x2UL 2238 #define FUNC_CFG_REQ_ENABLES2_QUIC_TX_KEY_CTXS 0x4UL 2239 #define FUNC_CFG_REQ_ENABLES2_QUIC_RX_KEY_CTXS 0x8UL 2240 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_AV_PER_VF 0x10UL 2241 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_CQ_PER_VF 0x20UL 2242 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_MRW_PER_VF 0x40UL 2243 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_QP_PER_VF 0x80UL 2244 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_SRQ_PER_VF 0x100UL 2245 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_GID_PER_VF 0x200UL 2246 #define FUNC_CFG_REQ_ENABLES2_XID_PARTITION_CFG 0x400UL 2247 u8 port_kdnet_mode; 2248 #define FUNC_CFG_REQ_PORT_KDNET_MODE_DISABLED 0x0UL 2249 #define FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED 0x1UL 2250 #define FUNC_CFG_REQ_PORT_KDNET_MODE_LAST FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED 2251 u8 db_page_size; 2252 #define FUNC_CFG_REQ_DB_PAGE_SIZE_4KB 0x0UL 2253 #define FUNC_CFG_REQ_DB_PAGE_SIZE_8KB 0x1UL 2254 #define FUNC_CFG_REQ_DB_PAGE_SIZE_16KB 0x2UL 2255 #define FUNC_CFG_REQ_DB_PAGE_SIZE_32KB 0x3UL 2256 #define FUNC_CFG_REQ_DB_PAGE_SIZE_64KB 0x4UL 2257 #define FUNC_CFG_REQ_DB_PAGE_SIZE_128KB 0x5UL 2258 #define FUNC_CFG_REQ_DB_PAGE_SIZE_256KB 0x6UL 2259 #define FUNC_CFG_REQ_DB_PAGE_SIZE_512KB 0x7UL 2260 #define FUNC_CFG_REQ_DB_PAGE_SIZE_1MB 0x8UL 2261 #define FUNC_CFG_REQ_DB_PAGE_SIZE_2MB 0x9UL 2262 #define FUNC_CFG_REQ_DB_PAGE_SIZE_4MB 0xaUL 2263 #define FUNC_CFG_REQ_DB_PAGE_SIZE_LAST FUNC_CFG_REQ_DB_PAGE_SIZE_4MB 2264 u8 unused_1[2]; 2265 __le32 num_ktls_tx_key_ctxs; 2266 __le32 num_ktls_rx_key_ctxs; 2267 __le32 num_quic_tx_key_ctxs; 2268 __le32 num_quic_rx_key_ctxs; 2269 __le32 roce_max_av_per_vf; 2270 __le32 roce_max_cq_per_vf; 2271 __le32 roce_max_mrw_per_vf; 2272 __le32 roce_max_qp_per_vf; 2273 __le32 roce_max_srq_per_vf; 2274 __le32 roce_max_gid_per_vf; 2275 __le16 xid_partition_cfg; 2276 #define FUNC_CFG_REQ_XID_PARTITION_CFG_TX_CK 0x1UL 2277 #define FUNC_CFG_REQ_XID_PARTITION_CFG_RX_CK 0x2UL 2278 __le16 unused_2; 2279 }; 2280 2281 /* hwrm_func_cfg_output (size:128b/16B) */ 2282 struct hwrm_func_cfg_output { 2283 __le16 error_code; 2284 __le16 req_type; 2285 __le16 seq_id; 2286 __le16 resp_len; 2287 u8 unused_0[7]; 2288 u8 valid; 2289 }; 2290 2291 /* hwrm_func_cfg_cmd_err (size:64b/8B) */ 2292 struct hwrm_func_cfg_cmd_err { 2293 u8 code; 2294 #define FUNC_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 2295 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_RANGE 0x1UL 2296 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_MORE_THAN_MAX 0x2UL 2297 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_UNSUPPORTED 0x3UL 2298 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT 0x4UL 2299 #define FUNC_CFG_CMD_ERR_CODE_LAST FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT 2300 u8 unused_0[7]; 2301 }; 2302 2303 /* hwrm_func_qstats_input (size:192b/24B) */ 2304 struct hwrm_func_qstats_input { 2305 __le16 req_type; 2306 __le16 cmpl_ring; 2307 __le16 seq_id; 2308 __le16 target_id; 2309 __le64 resp_addr; 2310 __le16 fid; 2311 u8 flags; 2312 #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL 2313 #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL 2314 #define FUNC_QSTATS_REQ_FLAGS_L2_ONLY 0x4UL 2315 u8 unused_0[5]; 2316 }; 2317 2318 /* hwrm_func_qstats_output (size:1408b/176B) */ 2319 struct hwrm_func_qstats_output { 2320 __le16 error_code; 2321 __le16 req_type; 2322 __le16 seq_id; 2323 __le16 resp_len; 2324 __le64 tx_ucast_pkts; 2325 __le64 tx_mcast_pkts; 2326 __le64 tx_bcast_pkts; 2327 __le64 tx_discard_pkts; 2328 __le64 tx_drop_pkts; 2329 __le64 tx_ucast_bytes; 2330 __le64 tx_mcast_bytes; 2331 __le64 tx_bcast_bytes; 2332 __le64 rx_ucast_pkts; 2333 __le64 rx_mcast_pkts; 2334 __le64 rx_bcast_pkts; 2335 __le64 rx_discard_pkts; 2336 __le64 rx_drop_pkts; 2337 __le64 rx_ucast_bytes; 2338 __le64 rx_mcast_bytes; 2339 __le64 rx_bcast_bytes; 2340 __le64 rx_agg_pkts; 2341 __le64 rx_agg_bytes; 2342 __le64 rx_agg_events; 2343 __le64 rx_agg_aborts; 2344 u8 clear_seq; 2345 u8 unused_0[6]; 2346 u8 valid; 2347 }; 2348 2349 /* hwrm_func_qstats_ext_input (size:256b/32B) */ 2350 struct hwrm_func_qstats_ext_input { 2351 __le16 req_type; 2352 __le16 cmpl_ring; 2353 __le16 seq_id; 2354 __le16 target_id; 2355 __le64 resp_addr; 2356 __le16 fid; 2357 u8 flags; 2358 #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL 2359 #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL 2360 u8 unused_0[1]; 2361 __le32 enables; 2362 #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL 2363 __le16 schq_id; 2364 __le16 traffic_class; 2365 u8 unused_1[4]; 2366 }; 2367 2368 /* hwrm_func_qstats_ext_output (size:1536b/192B) */ 2369 struct hwrm_func_qstats_ext_output { 2370 __le16 error_code; 2371 __le16 req_type; 2372 __le16 seq_id; 2373 __le16 resp_len; 2374 __le64 rx_ucast_pkts; 2375 __le64 rx_mcast_pkts; 2376 __le64 rx_bcast_pkts; 2377 __le64 rx_discard_pkts; 2378 __le64 rx_error_pkts; 2379 __le64 rx_ucast_bytes; 2380 __le64 rx_mcast_bytes; 2381 __le64 rx_bcast_bytes; 2382 __le64 tx_ucast_pkts; 2383 __le64 tx_mcast_pkts; 2384 __le64 tx_bcast_pkts; 2385 __le64 tx_error_pkts; 2386 __le64 tx_discard_pkts; 2387 __le64 tx_ucast_bytes; 2388 __le64 tx_mcast_bytes; 2389 __le64 tx_bcast_bytes; 2390 __le64 rx_tpa_eligible_pkt; 2391 __le64 rx_tpa_eligible_bytes; 2392 __le64 rx_tpa_pkt; 2393 __le64 rx_tpa_bytes; 2394 __le64 rx_tpa_errors; 2395 __le64 rx_tpa_events; 2396 u8 unused_0[7]; 2397 u8 valid; 2398 }; 2399 2400 /* hwrm_func_clr_stats_input (size:192b/24B) */ 2401 struct hwrm_func_clr_stats_input { 2402 __le16 req_type; 2403 __le16 cmpl_ring; 2404 __le16 seq_id; 2405 __le16 target_id; 2406 __le64 resp_addr; 2407 __le16 fid; 2408 u8 unused_0[6]; 2409 }; 2410 2411 /* hwrm_func_clr_stats_output (size:128b/16B) */ 2412 struct hwrm_func_clr_stats_output { 2413 __le16 error_code; 2414 __le16 req_type; 2415 __le16 seq_id; 2416 __le16 resp_len; 2417 u8 unused_0[7]; 2418 u8 valid; 2419 }; 2420 2421 /* hwrm_func_vf_resc_free_input (size:192b/24B) */ 2422 struct hwrm_func_vf_resc_free_input { 2423 __le16 req_type; 2424 __le16 cmpl_ring; 2425 __le16 seq_id; 2426 __le16 target_id; 2427 __le64 resp_addr; 2428 __le16 vf_id; 2429 u8 unused_0[6]; 2430 }; 2431 2432 /* hwrm_func_vf_resc_free_output (size:128b/16B) */ 2433 struct hwrm_func_vf_resc_free_output { 2434 __le16 error_code; 2435 __le16 req_type; 2436 __le16 seq_id; 2437 __le16 resp_len; 2438 u8 unused_0[7]; 2439 u8 valid; 2440 }; 2441 2442 /* hwrm_func_drv_rgtr_input (size:896b/112B) */ 2443 struct hwrm_func_drv_rgtr_input { 2444 __le16 req_type; 2445 __le16 cmpl_ring; 2446 __le16 seq_id; 2447 __le16 target_id; 2448 __le64 resp_addr; 2449 __le32 flags; 2450 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 2451 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 2452 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 2453 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 2454 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 2455 #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL 2456 #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL 2457 #define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT 0x80UL 2458 #define FUNC_DRV_RGTR_REQ_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT 0x100UL 2459 #define FUNC_DRV_RGTR_REQ_FLAGS_NPAR_1_2_SUPPORT 0x200UL 2460 #define FUNC_DRV_RGTR_REQ_FLAGS_ASYM_QUEUE_CFG_SUPPORT 0x400UL 2461 #define FUNC_DRV_RGTR_REQ_FLAGS_TF_INGRESS_NIC_FLOW_MODE 0x800UL 2462 #define FUNC_DRV_RGTR_REQ_FLAGS_TF_EGRESS_NIC_FLOW_MODE 0x1000UL 2463 __le32 enables; 2464 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 2465 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 2466 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 2467 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 2468 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 2469 __le16 os_type; 2470 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 2471 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 2472 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 2473 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 2474 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 2475 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 2476 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 2477 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 2478 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 2479 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 2480 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 2481 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 2482 u8 ver_maj_8b; 2483 u8 ver_min_8b; 2484 u8 ver_upd_8b; 2485 u8 unused_0[3]; 2486 __le32 timestamp; 2487 u8 unused_1[4]; 2488 __le32 vf_req_fwd[8]; 2489 __le32 async_event_fwd[8]; 2490 __le16 ver_maj; 2491 __le16 ver_min; 2492 __le16 ver_upd; 2493 __le16 ver_patch; 2494 }; 2495 2496 /* hwrm_func_drv_rgtr_output (size:128b/16B) */ 2497 struct hwrm_func_drv_rgtr_output { 2498 __le16 error_code; 2499 __le16 req_type; 2500 __le16 seq_id; 2501 __le16 resp_len; 2502 __le32 flags; 2503 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 2504 u8 unused_0[3]; 2505 u8 valid; 2506 }; 2507 2508 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 2509 struct hwrm_func_drv_unrgtr_input { 2510 __le16 req_type; 2511 __le16 cmpl_ring; 2512 __le16 seq_id; 2513 __le16 target_id; 2514 __le64 resp_addr; 2515 __le32 flags; 2516 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 2517 u8 unused_0[4]; 2518 }; 2519 2520 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 2521 struct hwrm_func_drv_unrgtr_output { 2522 __le16 error_code; 2523 __le16 req_type; 2524 __le16 seq_id; 2525 __le16 resp_len; 2526 u8 unused_0[7]; 2527 u8 valid; 2528 }; 2529 2530 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 2531 struct hwrm_func_buf_rgtr_input { 2532 __le16 req_type; 2533 __le16 cmpl_ring; 2534 __le16 seq_id; 2535 __le16 target_id; 2536 __le64 resp_addr; 2537 __le32 enables; 2538 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 2539 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 2540 __le16 vf_id; 2541 __le16 req_buf_num_pages; 2542 __le16 req_buf_page_size; 2543 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 2544 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 2545 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 2546 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 2547 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 2548 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 2549 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 2550 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 2551 __le16 req_buf_len; 2552 __le16 resp_buf_len; 2553 u8 unused_0[2]; 2554 __le64 req_buf_page_addr0; 2555 __le64 req_buf_page_addr1; 2556 __le64 req_buf_page_addr2; 2557 __le64 req_buf_page_addr3; 2558 __le64 req_buf_page_addr4; 2559 __le64 req_buf_page_addr5; 2560 __le64 req_buf_page_addr6; 2561 __le64 req_buf_page_addr7; 2562 __le64 req_buf_page_addr8; 2563 __le64 req_buf_page_addr9; 2564 __le64 error_buf_addr; 2565 __le64 resp_buf_addr; 2566 }; 2567 2568 /* hwrm_func_buf_rgtr_output (size:128b/16B) */ 2569 struct hwrm_func_buf_rgtr_output { 2570 __le16 error_code; 2571 __le16 req_type; 2572 __le16 seq_id; 2573 __le16 resp_len; 2574 u8 unused_0[7]; 2575 u8 valid; 2576 }; 2577 2578 /* hwrm_func_drv_qver_input (size:192b/24B) */ 2579 struct hwrm_func_drv_qver_input { 2580 __le16 req_type; 2581 __le16 cmpl_ring; 2582 __le16 seq_id; 2583 __le16 target_id; 2584 __le64 resp_addr; 2585 __le32 reserved; 2586 __le16 fid; 2587 u8 driver_type; 2588 #define FUNC_DRV_QVER_REQ_DRIVER_TYPE_L2 0x0UL 2589 #define FUNC_DRV_QVER_REQ_DRIVER_TYPE_ROCE 0x1UL 2590 #define FUNC_DRV_QVER_REQ_DRIVER_TYPE_LAST FUNC_DRV_QVER_REQ_DRIVER_TYPE_ROCE 2591 u8 unused_0; 2592 }; 2593 2594 /* hwrm_func_drv_qver_output (size:256b/32B) */ 2595 struct hwrm_func_drv_qver_output { 2596 __le16 error_code; 2597 __le16 req_type; 2598 __le16 seq_id; 2599 __le16 resp_len; 2600 __le16 os_type; 2601 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 2602 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 2603 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 2604 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 2605 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 2606 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 2607 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 2608 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 2609 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 2610 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 2611 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 2612 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 2613 u8 ver_maj_8b; 2614 u8 ver_min_8b; 2615 u8 ver_upd_8b; 2616 u8 unused_0[3]; 2617 __le16 ver_maj; 2618 __le16 ver_min; 2619 __le16 ver_upd; 2620 __le16 ver_patch; 2621 u8 unused_1[7]; 2622 u8 valid; 2623 }; 2624 2625 /* hwrm_func_resource_qcaps_input (size:192b/24B) */ 2626 struct hwrm_func_resource_qcaps_input { 2627 __le16 req_type; 2628 __le16 cmpl_ring; 2629 __le16 seq_id; 2630 __le16 target_id; 2631 __le64 resp_addr; 2632 __le16 fid; 2633 u8 unused_0[6]; 2634 }; 2635 2636 /* hwrm_func_resource_qcaps_output (size:704b/88B) */ 2637 struct hwrm_func_resource_qcaps_output { 2638 __le16 error_code; 2639 __le16 req_type; 2640 __le16 seq_id; 2641 __le16 resp_len; 2642 __le16 max_vfs; 2643 __le16 max_msix; 2644 __le16 vf_reservation_strategy; 2645 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 2646 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 2647 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 2648 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 2649 __le16 min_rsscos_ctx; 2650 __le16 max_rsscos_ctx; 2651 __le16 min_cmpl_rings; 2652 __le16 max_cmpl_rings; 2653 __le16 min_tx_rings; 2654 __le16 max_tx_rings; 2655 __le16 min_rx_rings; 2656 __le16 max_rx_rings; 2657 __le16 min_l2_ctxs; 2658 __le16 max_l2_ctxs; 2659 __le16 min_vnics; 2660 __le16 max_vnics; 2661 __le16 min_stat_ctx; 2662 __le16 max_stat_ctx; 2663 __le16 min_hw_ring_grps; 2664 __le16 max_hw_ring_grps; 2665 __le16 max_tx_scheduler_inputs; 2666 __le16 flags; 2667 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 2668 __le16 min_msix; 2669 __le32 min_ktls_tx_key_ctxs; 2670 __le32 max_ktls_tx_key_ctxs; 2671 __le32 min_ktls_rx_key_ctxs; 2672 __le32 max_ktls_rx_key_ctxs; 2673 __le32 min_quic_tx_key_ctxs; 2674 __le32 max_quic_tx_key_ctxs; 2675 __le32 min_quic_rx_key_ctxs; 2676 __le32 max_quic_rx_key_ctxs; 2677 u8 unused_0[3]; 2678 u8 valid; 2679 }; 2680 2681 /* hwrm_func_vf_resource_cfg_input (size:704b/88B) */ 2682 struct hwrm_func_vf_resource_cfg_input { 2683 __le16 req_type; 2684 __le16 cmpl_ring; 2685 __le16 seq_id; 2686 __le16 target_id; 2687 __le64 resp_addr; 2688 __le16 vf_id; 2689 __le16 max_msix; 2690 __le16 min_rsscos_ctx; 2691 __le16 max_rsscos_ctx; 2692 __le16 min_cmpl_rings; 2693 __le16 max_cmpl_rings; 2694 __le16 min_tx_rings; 2695 __le16 max_tx_rings; 2696 __le16 min_rx_rings; 2697 __le16 max_rx_rings; 2698 __le16 min_l2_ctxs; 2699 __le16 max_l2_ctxs; 2700 __le16 min_vnics; 2701 __le16 max_vnics; 2702 __le16 min_stat_ctx; 2703 __le16 max_stat_ctx; 2704 __le16 min_hw_ring_grps; 2705 __le16 max_hw_ring_grps; 2706 __le16 flags; 2707 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 2708 __le16 min_msix; 2709 __le32 min_ktls_tx_key_ctxs; 2710 __le32 max_ktls_tx_key_ctxs; 2711 __le32 min_ktls_rx_key_ctxs; 2712 __le32 max_ktls_rx_key_ctxs; 2713 __le32 min_quic_tx_key_ctxs; 2714 __le32 max_quic_tx_key_ctxs; 2715 __le32 min_quic_rx_key_ctxs; 2716 __le32 max_quic_rx_key_ctxs; 2717 }; 2718 2719 /* hwrm_func_vf_resource_cfg_output (size:384b/48B) */ 2720 struct hwrm_func_vf_resource_cfg_output { 2721 __le16 error_code; 2722 __le16 req_type; 2723 __le16 seq_id; 2724 __le16 resp_len; 2725 __le16 reserved_rsscos_ctx; 2726 __le16 reserved_cmpl_rings; 2727 __le16 reserved_tx_rings; 2728 __le16 reserved_rx_rings; 2729 __le16 reserved_l2_ctxs; 2730 __le16 reserved_vnics; 2731 __le16 reserved_stat_ctx; 2732 __le16 reserved_hw_ring_grps; 2733 __le32 reserved_ktls_tx_key_ctxs; 2734 __le32 reserved_ktls_rx_key_ctxs; 2735 __le32 reserved_quic_tx_key_ctxs; 2736 __le32 reserved_quic_rx_key_ctxs; 2737 u8 unused_0[7]; 2738 u8 valid; 2739 }; 2740 2741 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 2742 struct hwrm_func_backing_store_qcaps_input { 2743 __le16 req_type; 2744 __le16 cmpl_ring; 2745 __le16 seq_id; 2746 __le16 target_id; 2747 __le64 resp_addr; 2748 }; 2749 2750 /* hwrm_func_backing_store_qcaps_output (size:832b/104B) */ 2751 struct hwrm_func_backing_store_qcaps_output { 2752 __le16 error_code; 2753 __le16 req_type; 2754 __le16 seq_id; 2755 __le16 resp_len; 2756 __le32 qp_max_entries; 2757 __le16 qp_min_qp1_entries; 2758 __le16 qp_max_l2_entries; 2759 __le16 qp_entry_size; 2760 __le16 srq_max_l2_entries; 2761 __le32 srq_max_entries; 2762 __le16 srq_entry_size; 2763 __le16 cq_max_l2_entries; 2764 __le32 cq_max_entries; 2765 __le16 cq_entry_size; 2766 __le16 vnic_max_vnic_entries; 2767 __le16 vnic_max_ring_table_entries; 2768 __le16 vnic_entry_size; 2769 __le32 stat_max_entries; 2770 __le16 stat_entry_size; 2771 __le16 tqm_entry_size; 2772 __le32 tqm_min_entries_per_ring; 2773 __le32 tqm_max_entries_per_ring; 2774 __le32 mrav_max_entries; 2775 __le16 mrav_entry_size; 2776 __le16 tim_entry_size; 2777 __le32 tim_max_entries; 2778 __le16 mrav_num_entries_units; 2779 u8 tqm_entries_multiple; 2780 u8 ctx_kind_initializer; 2781 __le16 ctx_init_mask; 2782 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_QP 0x1UL 2783 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_SRQ 0x2UL 2784 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_CQ 0x4UL 2785 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_VNIC 0x8UL 2786 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_STAT 0x10UL 2787 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_MRAV 0x20UL 2788 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_TKC 0x40UL 2789 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_RKC 0x80UL 2790 u8 qp_init_offset; 2791 u8 srq_init_offset; 2792 u8 cq_init_offset; 2793 u8 vnic_init_offset; 2794 u8 tqm_fp_rings_count; 2795 u8 stat_init_offset; 2796 u8 mrav_init_offset; 2797 u8 tqm_fp_rings_count_ext; 2798 u8 tkc_init_offset; 2799 u8 rkc_init_offset; 2800 __le16 tkc_entry_size; 2801 __le16 rkc_entry_size; 2802 __le32 tkc_max_entries; 2803 __le32 rkc_max_entries; 2804 __le16 fast_qpmd_qp_num_entries; 2805 u8 rsvd1[5]; 2806 u8 valid; 2807 }; 2808 2809 /* tqm_fp_ring_cfg (size:128b/16B) */ 2810 struct tqm_fp_ring_cfg { 2811 u8 tqm_ring_pg_size_tqm_ring_lvl; 2812 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK 0xfUL 2813 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0 2814 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 0x0UL 2815 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 0x1UL 2816 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 0x2UL 2817 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 2818 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK 0xf0UL 2819 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4 2820 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2821 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2822 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2823 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2824 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2825 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2826 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G 2827 u8 unused[3]; 2828 __le32 tqm_ring_num_entries; 2829 __le64 tqm_ring_page_dir; 2830 }; 2831 2832 /* hwrm_func_backing_store_cfg_input (size:2688b/336B) */ 2833 struct hwrm_func_backing_store_cfg_input { 2834 __le16 req_type; 2835 __le16 cmpl_ring; 2836 __le16 seq_id; 2837 __le16 target_id; 2838 __le64 resp_addr; 2839 __le32 flags; 2840 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 2841 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL 2842 __le32 enables; 2843 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 2844 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 2845 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 2846 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 2847 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 2848 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 2849 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 2850 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 2851 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 2852 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 2853 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 2854 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 2855 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 2856 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 2857 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 2858 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 2859 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING8 0x10000UL 2860 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING9 0x20000UL 2861 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING10 0x40000UL 2862 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TKC 0x80000UL 2863 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_RKC 0x100000UL 2864 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP_FAST_QPMD 0x200000UL 2865 u8 qpc_pg_size_qpc_lvl; 2866 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 2867 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 2868 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 2869 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 2870 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 2871 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 2872 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 2873 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 2874 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 2875 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 2876 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 2877 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 2878 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 2879 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 2880 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 2881 u8 srq_pg_size_srq_lvl; 2882 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 2883 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 2884 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 2885 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 2886 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 2887 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 2888 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 2889 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 2890 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 2891 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 2892 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 2893 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 2894 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 2895 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 2896 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 2897 u8 cq_pg_size_cq_lvl; 2898 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 2899 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 2900 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 2901 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 2902 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 2903 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 2904 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 2905 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 2906 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 2907 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 2908 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 2909 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 2910 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 2911 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 2912 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 2913 u8 vnic_pg_size_vnic_lvl; 2914 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 2915 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 2916 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 2917 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 2918 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 2919 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 2920 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 2921 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 2922 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 2923 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 2924 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 2925 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 2926 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 2927 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 2928 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 2929 u8 stat_pg_size_stat_lvl; 2930 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 2931 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 2932 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 2933 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 2934 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 2935 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 2936 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 2937 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 2938 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 2939 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 2940 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 2941 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 2942 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 2943 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 2944 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 2945 u8 tqm_sp_pg_size_tqm_sp_lvl; 2946 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 2947 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 2948 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 2949 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 2950 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 2951 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 2952 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 2953 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 2954 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 2955 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 2956 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 2957 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 2958 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 2959 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 2960 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 2961 u8 tqm_ring0_pg_size_tqm_ring0_lvl; 2962 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 2963 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 2964 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 2965 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 2966 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 2967 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 2968 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 2969 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 2970 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 2971 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 2972 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 2973 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 2974 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 2975 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 2976 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 2977 u8 tqm_ring1_pg_size_tqm_ring1_lvl; 2978 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 2979 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 2980 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 2981 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 2982 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 2983 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 2984 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 2985 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 2986 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 2987 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 2988 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 2989 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 2990 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 2991 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 2992 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 2993 u8 tqm_ring2_pg_size_tqm_ring2_lvl; 2994 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 2995 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 2996 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 2997 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 2998 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 2999 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 3000 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 3001 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 3002 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 3003 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 3004 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 3005 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 3006 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 3007 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 3008 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 3009 u8 tqm_ring3_pg_size_tqm_ring3_lvl; 3010 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 3011 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 3012 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 3013 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 3014 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 3015 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 3016 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 3017 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 3018 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 3019 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 3020 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 3021 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 3022 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 3023 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 3024 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 3025 u8 tqm_ring4_pg_size_tqm_ring4_lvl; 3026 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 3027 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 3028 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 3029 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 3030 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 3031 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 3032 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 3033 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 3034 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 3035 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 3036 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 3037 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 3038 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 3039 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 3040 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 3041 u8 tqm_ring5_pg_size_tqm_ring5_lvl; 3042 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 3043 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 3044 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 3045 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 3046 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 3047 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 3048 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 3049 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 3050 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 3051 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 3052 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 3053 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 3054 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 3055 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 3056 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 3057 u8 tqm_ring6_pg_size_tqm_ring6_lvl; 3058 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 3059 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 3060 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 3061 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 3062 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 3063 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 3064 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 3065 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 3066 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 3067 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 3068 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 3069 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 3070 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 3071 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 3072 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 3073 u8 tqm_ring7_pg_size_tqm_ring7_lvl; 3074 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 3075 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 3076 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 3077 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 3078 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 3079 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 3080 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 3081 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 3082 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 3083 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 3084 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 3085 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 3086 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 3087 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 3088 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 3089 u8 mrav_pg_size_mrav_lvl; 3090 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 3091 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 3092 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 3093 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL 3094 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 3095 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 3096 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 3097 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 3098 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 3099 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 3100 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 3101 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 3102 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 3103 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 3104 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 3105 u8 tim_pg_size_tim_lvl; 3106 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 3107 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 3108 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 3109 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 3110 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 3111 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 3112 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 3113 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 3114 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 3115 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 3116 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 3117 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 3118 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 3119 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 3120 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 3121 __le64 qpc_page_dir; 3122 __le64 srq_page_dir; 3123 __le64 cq_page_dir; 3124 __le64 vnic_page_dir; 3125 __le64 stat_page_dir; 3126 __le64 tqm_sp_page_dir; 3127 __le64 tqm_ring0_page_dir; 3128 __le64 tqm_ring1_page_dir; 3129 __le64 tqm_ring2_page_dir; 3130 __le64 tqm_ring3_page_dir; 3131 __le64 tqm_ring4_page_dir; 3132 __le64 tqm_ring5_page_dir; 3133 __le64 tqm_ring6_page_dir; 3134 __le64 tqm_ring7_page_dir; 3135 __le64 mrav_page_dir; 3136 __le64 tim_page_dir; 3137 __le32 qp_num_entries; 3138 __le32 srq_num_entries; 3139 __le32 cq_num_entries; 3140 __le32 stat_num_entries; 3141 __le32 tqm_sp_num_entries; 3142 __le32 tqm_ring0_num_entries; 3143 __le32 tqm_ring1_num_entries; 3144 __le32 tqm_ring2_num_entries; 3145 __le32 tqm_ring3_num_entries; 3146 __le32 tqm_ring4_num_entries; 3147 __le32 tqm_ring5_num_entries; 3148 __le32 tqm_ring6_num_entries; 3149 __le32 tqm_ring7_num_entries; 3150 __le32 mrav_num_entries; 3151 __le32 tim_num_entries; 3152 __le16 qp_num_qp1_entries; 3153 __le16 qp_num_l2_entries; 3154 __le16 qp_entry_size; 3155 __le16 srq_num_l2_entries; 3156 __le16 srq_entry_size; 3157 __le16 cq_num_l2_entries; 3158 __le16 cq_entry_size; 3159 __le16 vnic_num_vnic_entries; 3160 __le16 vnic_num_ring_table_entries; 3161 __le16 vnic_entry_size; 3162 __le16 stat_entry_size; 3163 __le16 tqm_entry_size; 3164 __le16 mrav_entry_size; 3165 __le16 tim_entry_size; 3166 u8 tqm_ring8_pg_size_tqm_ring_lvl; 3167 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_MASK 0xfUL 3168 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_SFT 0 3169 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_0 0x0UL 3170 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_1 0x1UL 3171 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 0x2UL 3172 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 3173 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_MASK 0xf0UL 3174 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_SFT 4 3175 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 3176 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 3177 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 3178 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 3179 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 3180 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 3181 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G 3182 u8 ring8_unused[3]; 3183 __le32 tqm_ring8_num_entries; 3184 __le64 tqm_ring8_page_dir; 3185 u8 tqm_ring9_pg_size_tqm_ring_lvl; 3186 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_MASK 0xfUL 3187 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_SFT 0 3188 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_0 0x0UL 3189 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_1 0x1UL 3190 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 0x2UL 3191 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 3192 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_MASK 0xf0UL 3193 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_SFT 4 3194 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 3195 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 3196 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 3197 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 3198 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 3199 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 3200 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G 3201 u8 ring9_unused[3]; 3202 __le32 tqm_ring9_num_entries; 3203 __le64 tqm_ring9_page_dir; 3204 u8 tqm_ring10_pg_size_tqm_ring_lvl; 3205 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_MASK 0xfUL 3206 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_SFT 0 3207 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_0 0x0UL 3208 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_1 0x1UL 3209 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 0x2UL 3210 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 3211 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_MASK 0xf0UL 3212 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_SFT 4 3213 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 3214 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 3215 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 3216 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 3217 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 3218 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 3219 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G 3220 u8 ring10_unused[3]; 3221 __le32 tqm_ring10_num_entries; 3222 __le64 tqm_ring10_page_dir; 3223 __le32 tkc_num_entries; 3224 __le32 rkc_num_entries; 3225 __le64 tkc_page_dir; 3226 __le64 rkc_page_dir; 3227 __le16 tkc_entry_size; 3228 __le16 rkc_entry_size; 3229 u8 tkc_pg_size_tkc_lvl; 3230 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_MASK 0xfUL 3231 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_SFT 0 3232 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_0 0x0UL 3233 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_1 0x1UL 3234 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 0x2UL 3235 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 3236 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_MASK 0xf0UL 3237 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_SFT 4 3238 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_4K (0x0UL << 4) 3239 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8K (0x1UL << 4) 3240 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_64K (0x2UL << 4) 3241 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_2M (0x3UL << 4) 3242 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8M (0x4UL << 4) 3243 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G (0x5UL << 4) 3244 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G 3245 u8 rkc_pg_size_rkc_lvl; 3246 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_MASK 0xfUL 3247 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_SFT 0 3248 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_0 0x0UL 3249 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_1 0x1UL 3250 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 0x2UL 3251 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 3252 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_MASK 0xf0UL 3253 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_SFT 4 3254 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_4K (0x0UL << 4) 3255 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8K (0x1UL << 4) 3256 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_64K (0x2UL << 4) 3257 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_2M (0x3UL << 4) 3258 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8M (0x4UL << 4) 3259 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G (0x5UL << 4) 3260 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G 3261 __le16 qp_num_fast_qpmd_entries; 3262 }; 3263 3264 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 3265 struct hwrm_func_backing_store_cfg_output { 3266 __le16 error_code; 3267 __le16 req_type; 3268 __le16 seq_id; 3269 __le16 resp_len; 3270 u8 unused_0[7]; 3271 u8 valid; 3272 }; 3273 3274 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */ 3275 struct hwrm_error_recovery_qcfg_input { 3276 __le16 req_type; 3277 __le16 cmpl_ring; 3278 __le16 seq_id; 3279 __le16 target_id; 3280 __le64 resp_addr; 3281 u8 unused_0[8]; 3282 }; 3283 3284 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ 3285 struct hwrm_error_recovery_qcfg_output { 3286 __le16 error_code; 3287 __le16 req_type; 3288 __le16 seq_id; 3289 __le16 resp_len; 3290 __le32 flags; 3291 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL 3292 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL 3293 __le32 driver_polling_freq; 3294 __le32 master_func_wait_period; 3295 __le32 normal_func_wait_period; 3296 __le32 master_func_wait_period_after_reset; 3297 __le32 max_bailout_time_after_reset; 3298 __le32 fw_health_status_reg; 3299 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL 3300 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0 3301 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3302 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL 3303 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL 3304 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL 3305 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 3306 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL 3307 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2 3308 __le32 fw_heartbeat_reg; 3309 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL 3310 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0 3311 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3312 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL 3313 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL 3314 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL 3315 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 3316 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL 3317 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2 3318 __le32 fw_reset_cnt_reg; 3319 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL 3320 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0 3321 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3322 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL 3323 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL 3324 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL 3325 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 3326 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL 3327 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2 3328 __le32 reset_inprogress_reg; 3329 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL 3330 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0 3331 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3332 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL 3333 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL 3334 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL 3335 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 3336 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL 3337 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2 3338 __le32 reset_inprogress_reg_mask; 3339 u8 unused_0[3]; 3340 u8 reg_array_cnt; 3341 __le32 reset_reg[16]; 3342 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL 3343 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0 3344 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3345 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL 3346 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL 3347 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL 3348 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 3349 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL 3350 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2 3351 __le32 reset_reg_val[16]; 3352 u8 delay_after_reset[16]; 3353 __le32 err_recovery_cnt_reg; 3354 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL 3355 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0 3356 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3357 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL 3358 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL 3359 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL 3360 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 3361 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL 3362 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2 3363 u8 unused_1[3]; 3364 u8 valid; 3365 }; 3366 3367 /* hwrm_func_echo_response_input (size:192b/24B) */ 3368 struct hwrm_func_echo_response_input { 3369 __le16 req_type; 3370 __le16 cmpl_ring; 3371 __le16 seq_id; 3372 __le16 target_id; 3373 __le64 resp_addr; 3374 __le32 event_data1; 3375 __le32 event_data2; 3376 }; 3377 3378 /* hwrm_func_echo_response_output (size:128b/16B) */ 3379 struct hwrm_func_echo_response_output { 3380 __le16 error_code; 3381 __le16 req_type; 3382 __le16 seq_id; 3383 __le16 resp_len; 3384 u8 unused_0[7]; 3385 u8 valid; 3386 }; 3387 3388 /* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */ 3389 struct hwrm_func_ptp_pin_qcfg_input { 3390 __le16 req_type; 3391 __le16 cmpl_ring; 3392 __le16 seq_id; 3393 __le16 target_id; 3394 __le64 resp_addr; 3395 u8 unused_0[8]; 3396 }; 3397 3398 /* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */ 3399 struct hwrm_func_ptp_pin_qcfg_output { 3400 __le16 error_code; 3401 __le16 req_type; 3402 __le16 seq_id; 3403 __le16 resp_len; 3404 u8 num_pins; 3405 u8 state; 3406 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN0_ENABLED 0x1UL 3407 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN1_ENABLED 0x2UL 3408 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN2_ENABLED 0x4UL 3409 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN3_ENABLED 0x8UL 3410 u8 pin0_usage; 3411 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_NONE 0x0UL 3412 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_IN 0x1UL 3413 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_OUT 0x2UL 3414 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_IN 0x3UL 3415 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 0x4UL 3416 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 3417 u8 pin1_usage; 3418 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_NONE 0x0UL 3419 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_IN 0x1UL 3420 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_OUT 0x2UL 3421 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_IN 0x3UL 3422 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 0x4UL 3423 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 3424 u8 pin2_usage; 3425 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_NONE 0x0UL 3426 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_IN 0x1UL 3427 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_OUT 0x2UL 3428 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_IN 0x3UL 3429 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 0x4UL 3430 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3431 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3432 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3433 u8 pin3_usage; 3434 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_NONE 0x0UL 3435 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_IN 0x1UL 3436 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_OUT 0x2UL 3437 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_IN 0x3UL 3438 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 0x4UL 3439 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3440 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3441 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3442 u8 unused_0; 3443 u8 valid; 3444 }; 3445 3446 /* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */ 3447 struct hwrm_func_ptp_pin_cfg_input { 3448 __le16 req_type; 3449 __le16 cmpl_ring; 3450 __le16 seq_id; 3451 __le16 target_id; 3452 __le64 resp_addr; 3453 __le32 enables; 3454 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE 0x1UL 3455 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE 0x2UL 3456 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_STATE 0x4UL 3457 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_USAGE 0x8UL 3458 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_STATE 0x10UL 3459 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_USAGE 0x20UL 3460 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_STATE 0x40UL 3461 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_USAGE 0x80UL 3462 u8 pin0_state; 3463 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_DISABLED 0x0UL 3464 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 0x1UL 3465 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 3466 u8 pin0_usage; 3467 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_NONE 0x0UL 3468 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_IN 0x1UL 3469 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_OUT 0x2UL 3470 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_IN 0x3UL 3471 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 0x4UL 3472 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 3473 u8 pin1_state; 3474 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_DISABLED 0x0UL 3475 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 0x1UL 3476 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 3477 u8 pin1_usage; 3478 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_NONE 0x0UL 3479 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_IN 0x1UL 3480 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_OUT 0x2UL 3481 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_IN 0x3UL 3482 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 0x4UL 3483 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 3484 u8 pin2_state; 3485 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_DISABLED 0x0UL 3486 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 0x1UL 3487 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 3488 u8 pin2_usage; 3489 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_NONE 0x0UL 3490 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_IN 0x1UL 3491 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_OUT 0x2UL 3492 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_IN 0x3UL 3493 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 0x4UL 3494 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3495 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3496 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3497 u8 pin3_state; 3498 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_DISABLED 0x0UL 3499 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 0x1UL 3500 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 3501 u8 pin3_usage; 3502 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_NONE 0x0UL 3503 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_IN 0x1UL 3504 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_OUT 0x2UL 3505 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_IN 0x3UL 3506 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 0x4UL 3507 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3508 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3509 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3510 u8 unused_0[4]; 3511 }; 3512 3513 /* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */ 3514 struct hwrm_func_ptp_pin_cfg_output { 3515 __le16 error_code; 3516 __le16 req_type; 3517 __le16 seq_id; 3518 __le16 resp_len; 3519 u8 unused_0[7]; 3520 u8 valid; 3521 }; 3522 3523 /* hwrm_func_ptp_cfg_input (size:384b/48B) */ 3524 struct hwrm_func_ptp_cfg_input { 3525 __le16 req_type; 3526 __le16 cmpl_ring; 3527 __le16 seq_id; 3528 __le16 target_id; 3529 __le64 resp_addr; 3530 __le16 enables; 3531 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT 0x1UL 3532 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE 0x2UL 3533 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_PHASE 0x4UL 3534 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD 0x8UL 3535 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP 0x10UL 3536 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE 0x20UL 3537 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME 0x40UL 3538 u8 ptp_pps_event; 3539 #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_INTERNAL 0x1UL 3540 #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_EXTERNAL 0x2UL 3541 u8 ptp_freq_adj_dll_source; 3542 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_NONE 0x0UL 3543 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 0x1UL 3544 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 0x2UL 3545 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 0x3UL 3546 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 0x4UL 3547 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 0x5UL 3548 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 0x6UL 3549 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 0x7UL 3550 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 0x8UL 3551 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 0xffUL 3552 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 3553 u8 ptp_freq_adj_dll_phase; 3554 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_NONE 0x0UL 3555 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_4K 0x1UL 3556 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_8K 0x2UL 3557 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M 0x3UL 3558 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_25M 0x4UL 3559 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_25M 3560 u8 unused_0[3]; 3561 __le32 ptp_freq_adj_ext_period; 3562 __le32 ptp_freq_adj_ext_up; 3563 __le32 ptp_freq_adj_ext_phase_lower; 3564 __le32 ptp_freq_adj_ext_phase_upper; 3565 __le64 ptp_set_time; 3566 }; 3567 3568 /* hwrm_func_ptp_cfg_output (size:128b/16B) */ 3569 struct hwrm_func_ptp_cfg_output { 3570 __le16 error_code; 3571 __le16 req_type; 3572 __le16 seq_id; 3573 __le16 resp_len; 3574 u8 unused_0[7]; 3575 u8 valid; 3576 }; 3577 3578 /* hwrm_func_ptp_ts_query_input (size:192b/24B) */ 3579 struct hwrm_func_ptp_ts_query_input { 3580 __le16 req_type; 3581 __le16 cmpl_ring; 3582 __le16 seq_id; 3583 __le16 target_id; 3584 __le64 resp_addr; 3585 __le32 flags; 3586 #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PPS_TIME 0x1UL 3587 #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PTM_TIME 0x2UL 3588 u8 unused_0[4]; 3589 }; 3590 3591 /* hwrm_func_ptp_ts_query_output (size:320b/40B) */ 3592 struct hwrm_func_ptp_ts_query_output { 3593 __le16 error_code; 3594 __le16 req_type; 3595 __le16 seq_id; 3596 __le16 resp_len; 3597 __le64 pps_event_ts; 3598 __le64 ptm_local_ts; 3599 __le64 ptm_system_ts; 3600 __le32 ptm_link_delay; 3601 u8 unused_0[3]; 3602 u8 valid; 3603 }; 3604 3605 /* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */ 3606 struct hwrm_func_ptp_ext_cfg_input { 3607 __le16 req_type; 3608 __le16 cmpl_ring; 3609 __le16 seq_id; 3610 __le16 target_id; 3611 __le64 resp_addr; 3612 __le16 enables; 3613 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_MASTER_FID 0x1UL 3614 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_FID 0x2UL 3615 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_MODE 0x4UL 3616 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_FAILOVER_TIMER 0x8UL 3617 __le16 phc_master_fid; 3618 __le16 phc_sec_fid; 3619 u8 phc_sec_mode; 3620 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_SWITCH 0x0UL 3621 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_ALL 0x1UL 3622 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY 0x2UL 3623 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_LAST FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY 3624 u8 unused_0; 3625 __le32 failover_timer; 3626 u8 unused_1[4]; 3627 }; 3628 3629 /* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */ 3630 struct hwrm_func_ptp_ext_cfg_output { 3631 __le16 error_code; 3632 __le16 req_type; 3633 __le16 seq_id; 3634 __le16 resp_len; 3635 u8 unused_0[7]; 3636 u8 valid; 3637 }; 3638 3639 /* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */ 3640 struct hwrm_func_ptp_ext_qcfg_input { 3641 __le16 req_type; 3642 __le16 cmpl_ring; 3643 __le16 seq_id; 3644 __le16 target_id; 3645 __le64 resp_addr; 3646 u8 unused_0[8]; 3647 }; 3648 3649 /* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */ 3650 struct hwrm_func_ptp_ext_qcfg_output { 3651 __le16 error_code; 3652 __le16 req_type; 3653 __le16 seq_id; 3654 __le16 resp_len; 3655 __le16 phc_master_fid; 3656 __le16 phc_sec_fid; 3657 __le16 phc_active_fid0; 3658 __le16 phc_active_fid1; 3659 __le32 last_failover_event; 3660 __le16 from_fid; 3661 __le16 to_fid; 3662 u8 unused_0[7]; 3663 u8 valid; 3664 }; 3665 3666 /* hwrm_func_backing_store_cfg_v2_input (size:448b/56B) */ 3667 struct hwrm_func_backing_store_cfg_v2_input { 3668 __le16 req_type; 3669 __le16 cmpl_ring; 3670 __le16 seq_id; 3671 __le16 target_id; 3672 __le64 resp_addr; 3673 __le16 type; 3674 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QP 0x0UL 3675 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ 0x1UL 3676 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ 0x2UL 3677 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_VNIC 0x3UL 3678 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_STAT 0x4UL 3679 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3680 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3681 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MRAV 0xeUL 3682 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TIM 0xfUL 3683 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TX_CK 0x13UL 3684 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RX_CK 0x14UL 3685 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3686 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3687 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3688 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3689 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3690 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 3691 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_XID_PARTITION 0x1dUL 3692 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRT_TRACE 0x1eUL 3693 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRT2_TRACE 0x1fUL 3694 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CRT_TRACE 0x20UL 3695 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CRT2_TRACE 0x21UL 3696 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RIGP0_TRACE 0x22UL 3697 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL 3698 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL 3699 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 0xffffUL 3700 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 3701 __le16 instance; 3702 __le32 flags; 3703 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_PREBOOT_MODE 0x1UL 3704 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_CFG_ALL_DONE 0x2UL 3705 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_EXTEND 0x4UL 3706 __le64 page_dir; 3707 __le32 num_entries; 3708 __le16 entry_size; 3709 u8 page_size_pbl_level; 3710 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_MASK 0xfUL 3711 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_SFT 0 3712 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_0 0x0UL 3713 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_1 0x1UL 3714 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2 0x2UL 3715 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2 3716 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_MASK 0xf0UL 3717 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_SFT 4 3718 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_4K (0x0UL << 4) 3719 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8K (0x1UL << 4) 3720 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_64K (0x2UL << 4) 3721 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_2M (0x3UL << 4) 3722 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8M (0x4UL << 4) 3723 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G (0x5UL << 4) 3724 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G 3725 u8 subtype_valid_cnt; 3726 __le32 split_entry_0; 3727 __le32 split_entry_1; 3728 __le32 split_entry_2; 3729 __le32 split_entry_3; 3730 }; 3731 3732 /* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */ 3733 struct hwrm_func_backing_store_cfg_v2_output { 3734 __le16 error_code; 3735 __le16 req_type; 3736 __le16 seq_id; 3737 __le16 resp_len; 3738 u8 rsvd0[7]; 3739 u8 valid; 3740 }; 3741 3742 /* hwrm_func_backing_store_qcfg_v2_input (size:192b/24B) */ 3743 struct hwrm_func_backing_store_qcfg_v2_input { 3744 __le16 req_type; 3745 __le16 cmpl_ring; 3746 __le16 seq_id; 3747 __le16 target_id; 3748 __le64 resp_addr; 3749 __le16 type; 3750 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QP 0x0UL 3751 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ 0x1UL 3752 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ 0x2UL 3753 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_VNIC 0x3UL 3754 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_STAT 0x4UL 3755 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3756 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3757 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MRAV 0xeUL 3758 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TIM 0xfUL 3759 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TX_CK 0x13UL 3760 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RX_CK 0x14UL 3761 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3762 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3763 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3764 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3765 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3766 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 3767 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_XID_PARTITION_TABLE 0x1dUL 3768 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRT_TRACE 0x1eUL 3769 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRT2_TRACE 0x1fUL 3770 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CRT_TRACE 0x20UL 3771 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CRT2_TRACE 0x21UL 3772 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RIGP0_TRACE 0x22UL 3773 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL 3774 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL 3775 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 0xffffUL 3776 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 3777 __le16 instance; 3778 u8 rsvd[4]; 3779 }; 3780 3781 /* hwrm_func_backing_store_qcfg_v2_output (size:448b/56B) */ 3782 struct hwrm_func_backing_store_qcfg_v2_output { 3783 __le16 error_code; 3784 __le16 req_type; 3785 __le16 seq_id; 3786 __le16 resp_len; 3787 __le16 type; 3788 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QP 0x0UL 3789 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRQ 0x1UL 3790 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CQ 0x2UL 3791 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_VNIC 0x3UL 3792 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_STAT 0x4UL 3793 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SP_TQM_RING 0x5UL 3794 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_FP_TQM_RING 0x6UL 3795 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MRAV 0xeUL 3796 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TIM 0xfUL 3797 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TX_CK 0x13UL 3798 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RX_CK 0x14UL 3799 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MP_TQM_RING 0x15UL 3800 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TBL_SCOPE 0x1cUL 3801 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_XID_PARTITION 0x1dUL 3802 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRT_TRACE 0x1eUL 3803 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRT2_TRACE 0x1fUL 3804 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CRT_TRACE 0x20UL 3805 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CRT2_TRACE 0x21UL 3806 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RIGP0_TRACE 0x22UL 3807 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_L2_HWRM_TRACE 0x23UL 3808 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_ROCE_HWRM_TRACE 0x24UL 3809 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 0xffffUL 3810 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 3811 __le16 instance; 3812 __le32 flags; 3813 __le64 page_dir; 3814 __le32 num_entries; 3815 u8 page_size_pbl_level; 3816 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_MASK 0xfUL 3817 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_SFT 0 3818 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_0 0x0UL 3819 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_1 0x1UL 3820 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2 0x2UL 3821 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2 3822 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_MASK 0xf0UL 3823 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_SFT 4 3824 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_4K (0x0UL << 4) 3825 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8K (0x1UL << 4) 3826 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_64K (0x2UL << 4) 3827 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_2M (0x3UL << 4) 3828 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8M (0x4UL << 4) 3829 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G (0x5UL << 4) 3830 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G 3831 u8 subtype_valid_cnt; 3832 u8 rsvd[2]; 3833 __le32 split_entry_0; 3834 __le32 split_entry_1; 3835 __le32 split_entry_2; 3836 __le32 split_entry_3; 3837 u8 rsvd2[7]; 3838 u8 valid; 3839 }; 3840 3841 /* qpc_split_entries (size:128b/16B) */ 3842 struct qpc_split_entries { 3843 __le32 qp_num_l2_entries; 3844 __le32 qp_num_qp1_entries; 3845 __le32 qp_num_fast_qpmd_entries; 3846 __le32 rsvd; 3847 }; 3848 3849 /* srq_split_entries (size:128b/16B) */ 3850 struct srq_split_entries { 3851 __le32 srq_num_l2_entries; 3852 __le32 rsvd; 3853 __le32 rsvd2[2]; 3854 }; 3855 3856 /* cq_split_entries (size:128b/16B) */ 3857 struct cq_split_entries { 3858 __le32 cq_num_l2_entries; 3859 __le32 rsvd; 3860 __le32 rsvd2[2]; 3861 }; 3862 3863 /* vnic_split_entries (size:128b/16B) */ 3864 struct vnic_split_entries { 3865 __le32 vnic_num_vnic_entries; 3866 __le32 rsvd; 3867 __le32 rsvd2[2]; 3868 }; 3869 3870 /* mrav_split_entries (size:128b/16B) */ 3871 struct mrav_split_entries { 3872 __le32 mrav_num_av_entries; 3873 __le32 rsvd; 3874 __le32 rsvd2[2]; 3875 }; 3876 3877 /* ts_split_entries (size:128b/16B) */ 3878 struct ts_split_entries { 3879 __le32 region_num_entries; 3880 u8 tsid; 3881 u8 lkup_static_bkt_cnt_exp[2]; 3882 u8 rsvd; 3883 __le32 rsvd2[2]; 3884 }; 3885 3886 /* hwrm_func_backing_store_qcaps_v2_input (size:192b/24B) */ 3887 struct hwrm_func_backing_store_qcaps_v2_input { 3888 __le16 req_type; 3889 __le16 cmpl_ring; 3890 __le16 seq_id; 3891 __le16 target_id; 3892 __le64 resp_addr; 3893 __le16 type; 3894 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP 0x0UL 3895 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ 0x1UL 3896 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ 0x2UL 3897 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC 0x3UL 3898 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT 0x4UL 3899 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3900 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3901 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV 0xeUL 3902 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM 0xfUL 3903 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TX_CK 0x13UL 3904 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RX_CK 0x14UL 3905 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3906 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3907 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3908 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3909 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3910 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 3911 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_XID_PARTITION 0x1dUL 3912 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT_TRACE 0x1eUL 3913 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT2_TRACE 0x1fUL 3914 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT_TRACE 0x20UL 3915 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT2_TRACE 0x21UL 3916 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP0_TRACE 0x22UL 3917 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL 3918 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL 3919 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 0xffffUL 3920 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 3921 u8 rsvd[6]; 3922 }; 3923 3924 /* hwrm_func_backing_store_qcaps_v2_output (size:448b/56B) */ 3925 struct hwrm_func_backing_store_qcaps_v2_output { 3926 __le16 error_code; 3927 __le16 req_type; 3928 __le16 seq_id; 3929 __le16 resp_len; 3930 __le16 type; 3931 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QP 0x0UL 3932 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ 0x1UL 3933 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ 0x2UL 3934 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_VNIC 0x3UL 3935 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_STAT 0x4UL 3936 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SP_TQM_RING 0x5UL 3937 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_FP_TQM_RING 0x6UL 3938 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MRAV 0xeUL 3939 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TIM 0xfUL 3940 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TX_CK 0x13UL 3941 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RX_CK 0x14UL 3942 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MP_TQM_RING 0x15UL 3943 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SQ_DB_SHADOW 0x16UL 3944 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RQ_DB_SHADOW 0x17UL 3945 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ_DB_SHADOW 0x18UL 3946 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ_DB_SHADOW 0x19UL 3947 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TBL_SCOPE 0x1cUL 3948 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_XID_PARTITION 0x1dUL 3949 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRT_TRACE 0x1eUL 3950 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRT2_TRACE 0x1fUL 3951 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CRT_TRACE 0x20UL 3952 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CRT2_TRACE 0x21UL 3953 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RIGP0_TRACE 0x22UL 3954 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_L2_HWRM_TRACE 0x23UL 3955 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_ROCE_HWRM_TRACE 0x24UL 3956 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 0xffffUL 3957 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 3958 __le16 entry_size; 3959 __le32 flags; 3960 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ENABLE_CTX_KIND_INIT 0x1UL 3961 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID 0x2UL 3962 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_DRIVER_MANAGED_MEMORY 0x4UL 3963 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ROCE_QP_PSEUDO_STATIC_ALLOC 0x8UL 3964 __le32 instance_bit_map; 3965 u8 ctx_init_value; 3966 u8 ctx_init_offset; 3967 u8 entry_multiple; 3968 u8 rsvd; 3969 __le32 max_num_entries; 3970 __le32 min_num_entries; 3971 __le16 next_valid_type; 3972 u8 subtype_valid_cnt; 3973 u8 exact_cnt_bit_map; 3974 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_0_EXACT 0x1UL 3975 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_1_EXACT 0x2UL 3976 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_2_EXACT 0x4UL 3977 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_3_EXACT 0x8UL 3978 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_UNUSED_MASK 0xf0UL 3979 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_UNUSED_SFT 4 3980 __le32 split_entry_0; 3981 __le32 split_entry_1; 3982 __le32 split_entry_2; 3983 __le32 split_entry_3; 3984 u8 rsvd3[3]; 3985 u8 valid; 3986 }; 3987 3988 /* hwrm_func_dbr_pacing_qcfg_input (size:128b/16B) */ 3989 struct hwrm_func_dbr_pacing_qcfg_input { 3990 __le16 req_type; 3991 __le16 cmpl_ring; 3992 __le16 seq_id; 3993 __le16 target_id; 3994 __le64 resp_addr; 3995 }; 3996 3997 /* hwrm_func_dbr_pacing_qcfg_output (size:512b/64B) */ 3998 struct hwrm_func_dbr_pacing_qcfg_output { 3999 __le16 error_code; 4000 __le16 req_type; 4001 __le16 seq_id; 4002 __le16 resp_len; 4003 u8 flags; 4004 #define FUNC_DBR_PACING_QCFG_RESP_FLAGS_DBR_NQ_EVENT_ENABLED 0x1UL 4005 u8 unused_0[7]; 4006 __le32 dbr_stat_db_fifo_reg; 4007 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK 0x3UL 4008 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_SFT 0 4009 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_PCIE_CFG 0x0UL 4010 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC 0x1UL 4011 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR0 0x2UL 4012 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1 0x3UL 4013 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_LAST FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1 4014 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_MASK 0xfffffffcUL 4015 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SFT 2 4016 __le32 dbr_stat_db_fifo_reg_watermark_mask; 4017 u8 dbr_stat_db_fifo_reg_watermark_shift; 4018 u8 unused_1[3]; 4019 __le32 dbr_stat_db_fifo_reg_fifo_room_mask; 4020 u8 dbr_stat_db_fifo_reg_fifo_room_shift; 4021 u8 unused_2[3]; 4022 __le32 dbr_throttling_aeq_arm_reg; 4023 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_MASK 0x3UL 4024 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_SFT 0 4025 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_PCIE_CFG 0x0UL 4026 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_GRC 0x1UL 4027 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR0 0x2UL 4028 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1 0x3UL 4029 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_LAST FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1 4030 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_MASK 0xfffffffcUL 4031 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SFT 2 4032 u8 dbr_throttling_aeq_arm_reg_val; 4033 u8 unused_3[3]; 4034 __le32 dbr_stat_db_max_fifo_depth; 4035 __le32 primary_nq_id; 4036 __le32 pacing_threshold; 4037 u8 unused_4[7]; 4038 u8 valid; 4039 }; 4040 4041 /* hwrm_func_drv_if_change_input (size:192b/24B) */ 4042 struct hwrm_func_drv_if_change_input { 4043 __le16 req_type; 4044 __le16 cmpl_ring; 4045 __le16 seq_id; 4046 __le16 target_id; 4047 __le64 resp_addr; 4048 __le32 flags; 4049 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 4050 __le32 unused; 4051 }; 4052 4053 /* hwrm_func_drv_if_change_output (size:128b/16B) */ 4054 struct hwrm_func_drv_if_change_output { 4055 __le16 error_code; 4056 __le16 req_type; 4057 __le16 seq_id; 4058 __le16 resp_len; 4059 __le32 flags; 4060 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 4061 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 4062 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_CAPS_CHANGE 0x4UL 4063 u8 unused_0[3]; 4064 u8 valid; 4065 }; 4066 4067 /* hwrm_port_phy_cfg_input (size:512b/64B) */ 4068 struct hwrm_port_phy_cfg_input { 4069 __le16 req_type; 4070 __le16 cmpl_ring; 4071 __le16 seq_id; 4072 __le16 target_id; 4073 __le64 resp_addr; 4074 __le32 flags; 4075 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 4076 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 4077 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 4078 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 4079 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 4080 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 4081 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 4082 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 4083 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 4084 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 4085 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 4086 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 4087 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 4088 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 4089 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 4090 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL 4091 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL 4092 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL 4093 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL 4094 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL 4095 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL 4096 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL 4097 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL 4098 __le32 enables; 4099 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 4100 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 4101 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 4102 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 4103 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 4104 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 4105 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 4106 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 4107 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 4108 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 4109 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 4110 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL 4111 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL 4112 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2 0x2000UL 4113 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEEDS2_MASK 0x4000UL 4114 __le16 port_id; 4115 __le16 force_link_speed; 4116 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 4117 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 4118 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 4119 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 4120 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 4121 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 4122 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 4123 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 4124 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 4125 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 4126 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 4127 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 4128 u8 auto_mode; 4129 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 4130 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 4131 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 4132 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 4133 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 4134 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 4135 u8 auto_duplex; 4136 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 4137 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 4138 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 4139 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 4140 u8 auto_pause; 4141 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 4142 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 4143 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 4144 u8 mgmt_flag; 4145 #define PORT_PHY_CFG_REQ_MGMT_FLAG_LINK_RELEASE 0x1UL 4146 #define PORT_PHY_CFG_REQ_MGMT_FLAG_MGMT_VALID 0x80UL 4147 __le16 auto_link_speed; 4148 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 4149 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 4150 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 4151 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 4152 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 4153 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 4154 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 4155 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 4156 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 4157 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 4158 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 4159 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 4160 __le16 auto_link_speed_mask; 4161 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 4162 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 4163 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 4164 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 4165 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 4166 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 4167 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 4168 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 4169 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 4170 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 4171 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 4172 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 4173 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 4174 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 4175 u8 wirespeed; 4176 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 4177 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 4178 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 4179 u8 lpbk; 4180 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 4181 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 4182 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 4183 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 4184 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 4185 u8 force_pause; 4186 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 4187 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 4188 u8 unused_1; 4189 __le32 preemphasis; 4190 __le16 eee_link_speed_mask; 4191 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 4192 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 4193 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 4194 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 4195 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 4196 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 4197 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 4198 __le16 force_pam4_link_speed; 4199 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 4200 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 4201 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 4202 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 4203 __le32 tx_lpi_timer; 4204 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 4205 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 4206 __le16 auto_link_pam4_speed_mask; 4207 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL 4208 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL 4209 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL 4210 __le16 force_link_speeds2; 4211 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_1GB 0xaUL 4212 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_10GB 0x64UL 4213 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_25GB 0xfaUL 4214 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_40GB 0x190UL 4215 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB 0x1f4UL 4216 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB 0x3e8UL 4217 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56 0x1f5UL 4218 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56 0x3e9UL 4219 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56 0x7d1UL 4220 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56 0xfa1UL 4221 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL 4222 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL 4223 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL 4224 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_800GB_PAM4_112 0x1f42UL 4225 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_800GB_PAM4_112 4226 __le16 auto_link_speeds2_mask; 4227 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_1GB 0x1UL 4228 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_10GB 0x2UL 4229 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_25GB 0x4UL 4230 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_40GB 0x8UL 4231 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB 0x10UL 4232 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB 0x20UL 4233 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB_PAM4_56 0x40UL 4234 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_56 0x80UL 4235 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_56 0x100UL 4236 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_56 0x200UL 4237 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_112 0x400UL 4238 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_112 0x800UL 4239 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_112 0x1000UL 4240 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_800GB_PAM4_112 0x2000UL 4241 u8 unused_2[6]; 4242 }; 4243 4244 /* hwrm_port_phy_cfg_output (size:128b/16B) */ 4245 struct hwrm_port_phy_cfg_output { 4246 __le16 error_code; 4247 __le16 req_type; 4248 __le16 seq_id; 4249 __le16 resp_len; 4250 u8 unused_0[7]; 4251 u8 valid; 4252 }; 4253 4254 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 4255 struct hwrm_port_phy_cfg_cmd_err { 4256 u8 code; 4257 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 4258 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 4259 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 4260 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 4261 u8 unused_0[7]; 4262 }; 4263 4264 /* hwrm_port_phy_qcfg_input (size:192b/24B) */ 4265 struct hwrm_port_phy_qcfg_input { 4266 __le16 req_type; 4267 __le16 cmpl_ring; 4268 __le16 seq_id; 4269 __le16 target_id; 4270 __le64 resp_addr; 4271 __le16 port_id; 4272 u8 unused_0[6]; 4273 }; 4274 4275 /* hwrm_port_phy_qcfg_output (size:832b/104B) */ 4276 struct hwrm_port_phy_qcfg_output { 4277 __le16 error_code; 4278 __le16 req_type; 4279 __le16 seq_id; 4280 __le16 resp_len; 4281 u8 link; 4282 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 4283 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 4284 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 4285 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 4286 u8 active_fec_signal_mode; 4287 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL 4288 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0 4289 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL 4290 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL 4291 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112 0x2UL 4292 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112 4293 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL 4294 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4 4295 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4) 4296 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4) 4297 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4) 4298 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4) 4299 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4) 4300 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4) 4301 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4) 4302 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE 4303 __le16 link_speed; 4304 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 4305 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 4306 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 4307 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 4308 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 4309 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 4310 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 4311 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 4312 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 4313 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 4314 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 4315 #define PORT_PHY_QCFG_RESP_LINK_SPEED_400GB 0xfa0UL 4316 #define PORT_PHY_QCFG_RESP_LINK_SPEED_800GB 0x1f40UL 4317 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 4318 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 4319 u8 duplex_cfg; 4320 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 4321 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 4322 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 4323 u8 pause; 4324 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 4325 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 4326 __le16 support_speeds; 4327 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 4328 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 4329 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 4330 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 4331 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 4332 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 4333 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 4334 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 4335 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 4336 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 4337 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 4338 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 4339 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 4340 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 4341 __le16 force_link_speed; 4342 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 4343 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 4344 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 4345 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 4346 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 4347 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 4348 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 4349 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 4350 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 4351 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 4352 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 4353 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 4354 u8 auto_mode; 4355 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 4356 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 4357 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 4358 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 4359 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 4360 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 4361 u8 auto_pause; 4362 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 4363 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 4364 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 4365 __le16 auto_link_speed; 4366 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 4367 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 4368 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 4369 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 4370 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 4371 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 4372 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 4373 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 4374 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 4375 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 4376 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 4377 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 4378 __le16 auto_link_speed_mask; 4379 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 4380 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 4381 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 4382 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 4383 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 4384 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 4385 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 4386 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 4387 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 4388 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 4389 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 4390 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 4391 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 4392 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 4393 u8 wirespeed; 4394 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 4395 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 4396 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 4397 u8 lpbk; 4398 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 4399 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 4400 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 4401 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 4402 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 4403 u8 force_pause; 4404 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 4405 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 4406 u8 module_status; 4407 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 4408 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 4409 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 4410 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 4411 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 4412 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL 4413 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 4414 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 4415 __le32 preemphasis; 4416 u8 phy_maj; 4417 u8 phy_min; 4418 u8 phy_bld; 4419 u8 phy_type; 4420 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 4421 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 4422 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 4423 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 4424 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 4425 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 4426 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 4427 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 4428 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 4429 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 4430 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 4431 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 4432 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 4433 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 4434 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 4435 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 4436 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 4437 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 4438 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 4439 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 4440 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 4441 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 4442 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 4443 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 4444 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 4445 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 4446 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 4447 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 4448 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 4449 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 4450 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 4451 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 4452 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR 0x20UL 4453 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR 0x21UL 4454 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR 0x22UL 4455 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER 0x23UL 4456 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2 0x24UL 4457 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2 0x25UL 4458 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2 0x26UL 4459 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2 0x27UL 4460 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR 0x28UL 4461 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR 0x29UL 4462 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR 0x2aUL 4463 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER 0x2bUL 4464 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2 0x2cUL 4465 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2 0x2dUL 4466 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2 0x2eUL 4467 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2 0x2fUL 4468 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8 0x30UL 4469 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8 0x31UL 4470 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8 0x32UL 4471 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8 0x33UL 4472 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4 0x34UL 4473 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4 0x35UL 4474 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4 0x36UL 4475 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4 0x37UL 4476 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASECR8 0x38UL 4477 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASESR8 0x39UL 4478 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASELR8 0x3aUL 4479 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEER8 0x3bUL 4480 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEFR8 0x3cUL 4481 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEDR8 0x3dUL 4482 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEDR8 4483 u8 media_type; 4484 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 4485 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 4486 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 4487 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 4488 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 4489 u8 xcvr_pkg_type; 4490 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 4491 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 4492 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 4493 u8 eee_config_phy_addr; 4494 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 4495 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 4496 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 4497 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 4498 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 4499 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 4500 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 4501 u8 parallel_detect; 4502 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 4503 __le16 link_partner_adv_speeds; 4504 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 4505 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 4506 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 4507 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 4508 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 4509 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 4510 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 4511 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 4512 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 4513 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 4514 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 4515 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 4516 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 4517 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 4518 u8 link_partner_adv_auto_mode; 4519 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 4520 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 4521 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 4522 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 4523 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 4524 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 4525 u8 link_partner_adv_pause; 4526 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 4527 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 4528 __le16 adv_eee_link_speed_mask; 4529 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 4530 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 4531 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 4532 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 4533 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 4534 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 4535 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 4536 __le16 link_partner_adv_eee_link_speed_mask; 4537 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 4538 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 4539 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 4540 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 4541 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 4542 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 4543 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 4544 __le32 xcvr_identifier_type_tx_lpi_timer; 4545 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 4546 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 4547 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 4548 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 4549 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 4550 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 4551 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 4552 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 4553 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 4554 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPDD (0x18UL << 24) 4555 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP112 (0x1eUL << 24) 4556 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFPDD (0x1fUL << 24) 4557 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_CSFP (0x20UL << 24) 4558 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_CSFP 4559 __le16 fec_cfg; 4560 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 4561 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 4562 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 4563 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 4564 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 4565 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 4566 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 4567 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL 4568 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL 4569 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL 4570 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL 4571 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL 4572 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL 4573 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL 4574 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL 4575 u8 duplex_state; 4576 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 4577 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 4578 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 4579 u8 option_flags; 4580 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 4581 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN 0x2UL 4582 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SPEEDS2_SUPPORTED 0x4UL 4583 char phy_vendor_name[16]; 4584 char phy_vendor_partnumber[16]; 4585 __le16 support_pam4_speeds; 4586 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL 4587 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL 4588 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL 4589 __le16 force_pam4_link_speed; 4590 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 4591 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 4592 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 4593 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 4594 __le16 auto_pam4_link_speed_mask; 4595 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL 4596 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL 4597 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL 4598 u8 link_partner_pam4_adv_speeds; 4599 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL 4600 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL 4601 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL 4602 u8 link_down_reason; 4603 #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF 0x1UL 4604 __le16 support_speeds2; 4605 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB 0x1UL 4606 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB 0x2UL 4607 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_25GB 0x4UL 4608 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_40GB 0x8UL 4609 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB 0x10UL 4610 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB 0x20UL 4611 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB_PAM4_56 0x40UL 4612 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_56 0x80UL 4613 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_56 0x100UL 4614 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_56 0x200UL 4615 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_112 0x400UL 4616 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_112 0x800UL 4617 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_112 0x1000UL 4618 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_800GB_PAM4_112 0x2000UL 4619 __le16 force_link_speeds2; 4620 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_1GB 0xaUL 4621 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_10GB 0x64UL 4622 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_25GB 0xfaUL 4623 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_40GB 0x190UL 4624 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB 0x1f4UL 4625 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB 0x3e8UL 4626 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB_PAM4_56 0x1f5UL 4627 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_56 0x3e9UL 4628 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_56 0x7d1UL 4629 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_56 0xfa1UL 4630 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL 4631 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL 4632 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL 4633 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112 0x1f42UL 4634 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112 4635 __le16 auto_link_speeds2; 4636 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_1GB 0x1UL 4637 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_10GB 0x2UL 4638 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_25GB 0x4UL 4639 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_40GB 0x8UL 4640 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB 0x10UL 4641 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB 0x20UL 4642 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB_PAM4_56 0x40UL 4643 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_56 0x80UL 4644 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_56 0x100UL 4645 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_56 0x200UL 4646 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_112 0x400UL 4647 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_112 0x800UL 4648 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_112 0x1000UL 4649 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_800GB_PAM4_112 0x2000UL 4650 u8 active_lanes; 4651 u8 valid; 4652 }; 4653 4654 /* hwrm_port_mac_cfg_input (size:448b/56B) */ 4655 struct hwrm_port_mac_cfg_input { 4656 __le16 req_type; 4657 __le16 cmpl_ring; 4658 __le16 seq_id; 4659 __le16 target_id; 4660 __le64 resp_addr; 4661 __le32 flags; 4662 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 4663 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 4664 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 4665 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 4666 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 4667 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 4668 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 4669 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 4670 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 4671 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 4672 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 4673 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 4674 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 4675 #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL 4676 #define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE 0x4000UL 4677 #define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE 0x8000UL 4678 __le32 enables; 4679 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 4680 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 4681 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 4682 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 4683 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 4684 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 4685 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 4686 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 4687 #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL 4688 #define PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE 0x400UL 4689 #define PORT_MAC_CFG_REQ_ENABLES_PTP_LOAD_CONTROL 0x800UL 4690 __le16 port_id; 4691 u8 ipg; 4692 u8 lpbk; 4693 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 4694 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 4695 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 4696 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 4697 u8 vlan_pri2cos_map_pri; 4698 u8 reserved1; 4699 u8 tunnel_pri2cos_map_pri; 4700 u8 dscp2pri_map_pri; 4701 __le16 rx_ts_capture_ptp_msg_type; 4702 __le16 tx_ts_capture_ptp_msg_type; 4703 u8 cos_field_cfg; 4704 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 4705 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 4706 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 4707 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 4708 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 4709 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 4710 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 4711 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 4712 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 4713 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 4714 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 4715 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 4716 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 4717 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 4718 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 4719 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 4720 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 4721 u8 unused_0[3]; 4722 __le32 ptp_freq_adj_ppb; 4723 u8 unused_1[3]; 4724 u8 ptp_load_control; 4725 #define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_NONE 0x0UL 4726 #define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_IMMEDIATE 0x1UL 4727 #define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_PPS_EVENT 0x2UL 4728 #define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_LAST PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_PPS_EVENT 4729 __le64 ptp_adj_phase; 4730 }; 4731 4732 /* hwrm_port_mac_cfg_output (size:128b/16B) */ 4733 struct hwrm_port_mac_cfg_output { 4734 __le16 error_code; 4735 __le16 req_type; 4736 __le16 seq_id; 4737 __le16 resp_len; 4738 __le16 mru; 4739 __le16 mtu; 4740 u8 ipg; 4741 u8 lpbk; 4742 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 4743 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 4744 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 4745 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 4746 u8 unused_0; 4747 u8 valid; 4748 }; 4749 4750 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 4751 struct hwrm_port_mac_ptp_qcfg_input { 4752 __le16 req_type; 4753 __le16 cmpl_ring; 4754 __le16 seq_id; 4755 __le16 target_id; 4756 __le64 resp_addr; 4757 __le16 port_id; 4758 u8 unused_0[6]; 4759 }; 4760 4761 /* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */ 4762 struct hwrm_port_mac_ptp_qcfg_output { 4763 __le16 error_code; 4764 __le16 req_type; 4765 __le16 seq_id; 4766 __le16 resp_len; 4767 u8 flags; 4768 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 4769 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL 4770 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL 4771 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK 0x10UL 4772 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_RTC_CONFIGURED 0x20UL 4773 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_64B_PHC_TIME 0x40UL 4774 u8 unused_0[3]; 4775 __le32 rx_ts_reg_off_lower; 4776 __le32 rx_ts_reg_off_upper; 4777 __le32 rx_ts_reg_off_seq_id; 4778 __le32 rx_ts_reg_off_src_id_0; 4779 __le32 rx_ts_reg_off_src_id_1; 4780 __le32 rx_ts_reg_off_src_id_2; 4781 __le32 rx_ts_reg_off_domain_id; 4782 __le32 rx_ts_reg_off_fifo; 4783 __le32 rx_ts_reg_off_fifo_adv; 4784 __le32 rx_ts_reg_off_granularity; 4785 __le32 tx_ts_reg_off_lower; 4786 __le32 tx_ts_reg_off_upper; 4787 __le32 tx_ts_reg_off_seq_id; 4788 __le32 tx_ts_reg_off_fifo; 4789 __le32 tx_ts_reg_off_granularity; 4790 __le32 ts_ref_clock_reg_lower; 4791 __le32 ts_ref_clock_reg_upper; 4792 u8 unused_1[7]; 4793 u8 valid; 4794 }; 4795 4796 /* tx_port_stats (size:3264b/408B) */ 4797 struct tx_port_stats { 4798 __le64 tx_64b_frames; 4799 __le64 tx_65b_127b_frames; 4800 __le64 tx_128b_255b_frames; 4801 __le64 tx_256b_511b_frames; 4802 __le64 tx_512b_1023b_frames; 4803 __le64 tx_1024b_1518b_frames; 4804 __le64 tx_good_vlan_frames; 4805 __le64 tx_1519b_2047b_frames; 4806 __le64 tx_2048b_4095b_frames; 4807 __le64 tx_4096b_9216b_frames; 4808 __le64 tx_9217b_16383b_frames; 4809 __le64 tx_good_frames; 4810 __le64 tx_total_frames; 4811 __le64 tx_ucast_frames; 4812 __le64 tx_mcast_frames; 4813 __le64 tx_bcast_frames; 4814 __le64 tx_pause_frames; 4815 __le64 tx_pfc_frames; 4816 __le64 tx_jabber_frames; 4817 __le64 tx_fcs_err_frames; 4818 __le64 tx_control_frames; 4819 __le64 tx_oversz_frames; 4820 __le64 tx_single_dfrl_frames; 4821 __le64 tx_multi_dfrl_frames; 4822 __le64 tx_single_coll_frames; 4823 __le64 tx_multi_coll_frames; 4824 __le64 tx_late_coll_frames; 4825 __le64 tx_excessive_coll_frames; 4826 __le64 tx_frag_frames; 4827 __le64 tx_err; 4828 __le64 tx_tagged_frames; 4829 __le64 tx_dbl_tagged_frames; 4830 __le64 tx_runt_frames; 4831 __le64 tx_fifo_underruns; 4832 __le64 tx_pfc_ena_frames_pri0; 4833 __le64 tx_pfc_ena_frames_pri1; 4834 __le64 tx_pfc_ena_frames_pri2; 4835 __le64 tx_pfc_ena_frames_pri3; 4836 __le64 tx_pfc_ena_frames_pri4; 4837 __le64 tx_pfc_ena_frames_pri5; 4838 __le64 tx_pfc_ena_frames_pri6; 4839 __le64 tx_pfc_ena_frames_pri7; 4840 __le64 tx_eee_lpi_events; 4841 __le64 tx_eee_lpi_duration; 4842 __le64 tx_llfc_logical_msgs; 4843 __le64 tx_hcfc_msgs; 4844 __le64 tx_total_collisions; 4845 __le64 tx_bytes; 4846 __le64 tx_xthol_frames; 4847 __le64 tx_stat_discard; 4848 __le64 tx_stat_error; 4849 }; 4850 4851 /* rx_port_stats (size:4224b/528B) */ 4852 struct rx_port_stats { 4853 __le64 rx_64b_frames; 4854 __le64 rx_65b_127b_frames; 4855 __le64 rx_128b_255b_frames; 4856 __le64 rx_256b_511b_frames; 4857 __le64 rx_512b_1023b_frames; 4858 __le64 rx_1024b_1518b_frames; 4859 __le64 rx_good_vlan_frames; 4860 __le64 rx_1519b_2047b_frames; 4861 __le64 rx_2048b_4095b_frames; 4862 __le64 rx_4096b_9216b_frames; 4863 __le64 rx_9217b_16383b_frames; 4864 __le64 rx_total_frames; 4865 __le64 rx_ucast_frames; 4866 __le64 rx_mcast_frames; 4867 __le64 rx_bcast_frames; 4868 __le64 rx_fcs_err_frames; 4869 __le64 rx_ctrl_frames; 4870 __le64 rx_pause_frames; 4871 __le64 rx_pfc_frames; 4872 __le64 rx_unsupported_opcode_frames; 4873 __le64 rx_unsupported_da_pausepfc_frames; 4874 __le64 rx_wrong_sa_frames; 4875 __le64 rx_align_err_frames; 4876 __le64 rx_oor_len_frames; 4877 __le64 rx_code_err_frames; 4878 __le64 rx_false_carrier_frames; 4879 __le64 rx_ovrsz_frames; 4880 __le64 rx_jbr_frames; 4881 __le64 rx_mtu_err_frames; 4882 __le64 rx_match_crc_frames; 4883 __le64 rx_promiscuous_frames; 4884 __le64 rx_tagged_frames; 4885 __le64 rx_double_tagged_frames; 4886 __le64 rx_trunc_frames; 4887 __le64 rx_good_frames; 4888 __le64 rx_pfc_xon2xoff_frames_pri0; 4889 __le64 rx_pfc_xon2xoff_frames_pri1; 4890 __le64 rx_pfc_xon2xoff_frames_pri2; 4891 __le64 rx_pfc_xon2xoff_frames_pri3; 4892 __le64 rx_pfc_xon2xoff_frames_pri4; 4893 __le64 rx_pfc_xon2xoff_frames_pri5; 4894 __le64 rx_pfc_xon2xoff_frames_pri6; 4895 __le64 rx_pfc_xon2xoff_frames_pri7; 4896 __le64 rx_pfc_ena_frames_pri0; 4897 __le64 rx_pfc_ena_frames_pri1; 4898 __le64 rx_pfc_ena_frames_pri2; 4899 __le64 rx_pfc_ena_frames_pri3; 4900 __le64 rx_pfc_ena_frames_pri4; 4901 __le64 rx_pfc_ena_frames_pri5; 4902 __le64 rx_pfc_ena_frames_pri6; 4903 __le64 rx_pfc_ena_frames_pri7; 4904 __le64 rx_sch_crc_err_frames; 4905 __le64 rx_undrsz_frames; 4906 __le64 rx_frag_frames; 4907 __le64 rx_eee_lpi_events; 4908 __le64 rx_eee_lpi_duration; 4909 __le64 rx_llfc_physical_msgs; 4910 __le64 rx_llfc_logical_msgs; 4911 __le64 rx_llfc_msgs_with_crc_err; 4912 __le64 rx_hcfc_msgs; 4913 __le64 rx_hcfc_msgs_with_crc_err; 4914 __le64 rx_bytes; 4915 __le64 rx_runt_bytes; 4916 __le64 rx_runt_frames; 4917 __le64 rx_stat_discard; 4918 __le64 rx_stat_err; 4919 }; 4920 4921 /* hwrm_port_qstats_input (size:320b/40B) */ 4922 struct hwrm_port_qstats_input { 4923 __le16 req_type; 4924 __le16 cmpl_ring; 4925 __le16 seq_id; 4926 __le16 target_id; 4927 __le64 resp_addr; 4928 __le16 port_id; 4929 u8 flags; 4930 #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 4931 u8 unused_0[5]; 4932 __le64 tx_stat_host_addr; 4933 __le64 rx_stat_host_addr; 4934 }; 4935 4936 /* hwrm_port_qstats_output (size:128b/16B) */ 4937 struct hwrm_port_qstats_output { 4938 __le16 error_code; 4939 __le16 req_type; 4940 __le16 seq_id; 4941 __le16 resp_len; 4942 __le16 tx_stat_size; 4943 __le16 rx_stat_size; 4944 u8 unused_0[3]; 4945 u8 valid; 4946 }; 4947 4948 /* tx_port_stats_ext (size:2048b/256B) */ 4949 struct tx_port_stats_ext { 4950 __le64 tx_bytes_cos0; 4951 __le64 tx_bytes_cos1; 4952 __le64 tx_bytes_cos2; 4953 __le64 tx_bytes_cos3; 4954 __le64 tx_bytes_cos4; 4955 __le64 tx_bytes_cos5; 4956 __le64 tx_bytes_cos6; 4957 __le64 tx_bytes_cos7; 4958 __le64 tx_packets_cos0; 4959 __le64 tx_packets_cos1; 4960 __le64 tx_packets_cos2; 4961 __le64 tx_packets_cos3; 4962 __le64 tx_packets_cos4; 4963 __le64 tx_packets_cos5; 4964 __le64 tx_packets_cos6; 4965 __le64 tx_packets_cos7; 4966 __le64 pfc_pri0_tx_duration_us; 4967 __le64 pfc_pri0_tx_transitions; 4968 __le64 pfc_pri1_tx_duration_us; 4969 __le64 pfc_pri1_tx_transitions; 4970 __le64 pfc_pri2_tx_duration_us; 4971 __le64 pfc_pri2_tx_transitions; 4972 __le64 pfc_pri3_tx_duration_us; 4973 __le64 pfc_pri3_tx_transitions; 4974 __le64 pfc_pri4_tx_duration_us; 4975 __le64 pfc_pri4_tx_transitions; 4976 __le64 pfc_pri5_tx_duration_us; 4977 __le64 pfc_pri5_tx_transitions; 4978 __le64 pfc_pri6_tx_duration_us; 4979 __le64 pfc_pri6_tx_transitions; 4980 __le64 pfc_pri7_tx_duration_us; 4981 __le64 pfc_pri7_tx_transitions; 4982 }; 4983 4984 /* rx_port_stats_ext (size:3904b/488B) */ 4985 struct rx_port_stats_ext { 4986 __le64 link_down_events; 4987 __le64 continuous_pause_events; 4988 __le64 resume_pause_events; 4989 __le64 continuous_roce_pause_events; 4990 __le64 resume_roce_pause_events; 4991 __le64 rx_bytes_cos0; 4992 __le64 rx_bytes_cos1; 4993 __le64 rx_bytes_cos2; 4994 __le64 rx_bytes_cos3; 4995 __le64 rx_bytes_cos4; 4996 __le64 rx_bytes_cos5; 4997 __le64 rx_bytes_cos6; 4998 __le64 rx_bytes_cos7; 4999 __le64 rx_packets_cos0; 5000 __le64 rx_packets_cos1; 5001 __le64 rx_packets_cos2; 5002 __le64 rx_packets_cos3; 5003 __le64 rx_packets_cos4; 5004 __le64 rx_packets_cos5; 5005 __le64 rx_packets_cos6; 5006 __le64 rx_packets_cos7; 5007 __le64 pfc_pri0_rx_duration_us; 5008 __le64 pfc_pri0_rx_transitions; 5009 __le64 pfc_pri1_rx_duration_us; 5010 __le64 pfc_pri1_rx_transitions; 5011 __le64 pfc_pri2_rx_duration_us; 5012 __le64 pfc_pri2_rx_transitions; 5013 __le64 pfc_pri3_rx_duration_us; 5014 __le64 pfc_pri3_rx_transitions; 5015 __le64 pfc_pri4_rx_duration_us; 5016 __le64 pfc_pri4_rx_transitions; 5017 __le64 pfc_pri5_rx_duration_us; 5018 __le64 pfc_pri5_rx_transitions; 5019 __le64 pfc_pri6_rx_duration_us; 5020 __le64 pfc_pri6_rx_transitions; 5021 __le64 pfc_pri7_rx_duration_us; 5022 __le64 pfc_pri7_rx_transitions; 5023 __le64 rx_bits; 5024 __le64 rx_buffer_passed_threshold; 5025 __le64 rx_pcs_symbol_err; 5026 __le64 rx_corrected_bits; 5027 __le64 rx_discard_bytes_cos0; 5028 __le64 rx_discard_bytes_cos1; 5029 __le64 rx_discard_bytes_cos2; 5030 __le64 rx_discard_bytes_cos3; 5031 __le64 rx_discard_bytes_cos4; 5032 __le64 rx_discard_bytes_cos5; 5033 __le64 rx_discard_bytes_cos6; 5034 __le64 rx_discard_bytes_cos7; 5035 __le64 rx_discard_packets_cos0; 5036 __le64 rx_discard_packets_cos1; 5037 __le64 rx_discard_packets_cos2; 5038 __le64 rx_discard_packets_cos3; 5039 __le64 rx_discard_packets_cos4; 5040 __le64 rx_discard_packets_cos5; 5041 __le64 rx_discard_packets_cos6; 5042 __le64 rx_discard_packets_cos7; 5043 __le64 rx_fec_corrected_blocks; 5044 __le64 rx_fec_uncorrectable_blocks; 5045 __le64 rx_filter_miss; 5046 __le64 rx_fec_symbol_err; 5047 }; 5048 5049 /* hwrm_port_qstats_ext_input (size:320b/40B) */ 5050 struct hwrm_port_qstats_ext_input { 5051 __le16 req_type; 5052 __le16 cmpl_ring; 5053 __le16 seq_id; 5054 __le16 target_id; 5055 __le64 resp_addr; 5056 __le16 port_id; 5057 __le16 tx_stat_size; 5058 __le16 rx_stat_size; 5059 u8 flags; 5060 #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL 5061 u8 unused_0; 5062 __le64 tx_stat_host_addr; 5063 __le64 rx_stat_host_addr; 5064 }; 5065 5066 /* hwrm_port_qstats_ext_output (size:128b/16B) */ 5067 struct hwrm_port_qstats_ext_output { 5068 __le16 error_code; 5069 __le16 req_type; 5070 __le16 seq_id; 5071 __le16 resp_len; 5072 __le16 tx_stat_size; 5073 __le16 rx_stat_size; 5074 __le16 total_active_cos_queues; 5075 u8 flags; 5076 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 5077 u8 valid; 5078 }; 5079 5080 /* hwrm_port_lpbk_qstats_input (size:256b/32B) */ 5081 struct hwrm_port_lpbk_qstats_input { 5082 __le16 req_type; 5083 __le16 cmpl_ring; 5084 __le16 seq_id; 5085 __le16 target_id; 5086 __le64 resp_addr; 5087 __le16 lpbk_stat_size; 5088 u8 flags; 5089 #define PORT_LPBK_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 5090 u8 unused_0[5]; 5091 __le64 lpbk_stat_host_addr; 5092 }; 5093 5094 /* hwrm_port_lpbk_qstats_output (size:128b/16B) */ 5095 struct hwrm_port_lpbk_qstats_output { 5096 __le16 error_code; 5097 __le16 req_type; 5098 __le16 seq_id; 5099 __le16 resp_len; 5100 __le16 lpbk_stat_size; 5101 u8 unused_0[5]; 5102 u8 valid; 5103 }; 5104 5105 /* port_lpbk_stats (size:640b/80B) */ 5106 struct port_lpbk_stats { 5107 __le64 lpbk_ucast_frames; 5108 __le64 lpbk_mcast_frames; 5109 __le64 lpbk_bcast_frames; 5110 __le64 lpbk_ucast_bytes; 5111 __le64 lpbk_mcast_bytes; 5112 __le64 lpbk_bcast_bytes; 5113 __le64 lpbk_tx_discards; 5114 __le64 lpbk_tx_errors; 5115 __le64 lpbk_rx_discards; 5116 __le64 lpbk_rx_errors; 5117 }; 5118 5119 /* hwrm_port_ecn_qstats_input (size:256b/32B) */ 5120 struct hwrm_port_ecn_qstats_input { 5121 __le16 req_type; 5122 __le16 cmpl_ring; 5123 __le16 seq_id; 5124 __le16 target_id; 5125 __le64 resp_addr; 5126 __le16 port_id; 5127 __le16 ecn_stat_buf_size; 5128 u8 flags; 5129 #define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 5130 u8 unused_0[3]; 5131 __le64 ecn_stat_host_addr; 5132 }; 5133 5134 /* hwrm_port_ecn_qstats_output (size:128b/16B) */ 5135 struct hwrm_port_ecn_qstats_output { 5136 __le16 error_code; 5137 __le16 req_type; 5138 __le16 seq_id; 5139 __le16 resp_len; 5140 __le16 ecn_stat_buf_size; 5141 u8 mark_en; 5142 u8 unused_0[4]; 5143 u8 valid; 5144 }; 5145 5146 /* port_stats_ecn (size:512b/64B) */ 5147 struct port_stats_ecn { 5148 __le64 mark_cnt_cos0; 5149 __le64 mark_cnt_cos1; 5150 __le64 mark_cnt_cos2; 5151 __le64 mark_cnt_cos3; 5152 __le64 mark_cnt_cos4; 5153 __le64 mark_cnt_cos5; 5154 __le64 mark_cnt_cos6; 5155 __le64 mark_cnt_cos7; 5156 }; 5157 5158 /* hwrm_port_clr_stats_input (size:192b/24B) */ 5159 struct hwrm_port_clr_stats_input { 5160 __le16 req_type; 5161 __le16 cmpl_ring; 5162 __le16 seq_id; 5163 __le16 target_id; 5164 __le64 resp_addr; 5165 __le16 port_id; 5166 u8 flags; 5167 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 5168 u8 unused_0[5]; 5169 }; 5170 5171 /* hwrm_port_clr_stats_output (size:128b/16B) */ 5172 struct hwrm_port_clr_stats_output { 5173 __le16 error_code; 5174 __le16 req_type; 5175 __le16 seq_id; 5176 __le16 resp_len; 5177 u8 unused_0[7]; 5178 u8 valid; 5179 }; 5180 5181 /* hwrm_port_lpbk_clr_stats_input (size:192b/24B) */ 5182 struct hwrm_port_lpbk_clr_stats_input { 5183 __le16 req_type; 5184 __le16 cmpl_ring; 5185 __le16 seq_id; 5186 __le16 target_id; 5187 __le64 resp_addr; 5188 __le16 port_id; 5189 u8 unused_0[6]; 5190 }; 5191 5192 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 5193 struct hwrm_port_lpbk_clr_stats_output { 5194 __le16 error_code; 5195 __le16 req_type; 5196 __le16 seq_id; 5197 __le16 resp_len; 5198 u8 unused_0[7]; 5199 u8 valid; 5200 }; 5201 5202 /* hwrm_port_ts_query_input (size:320b/40B) */ 5203 struct hwrm_port_ts_query_input { 5204 __le16 req_type; 5205 __le16 cmpl_ring; 5206 __le16 seq_id; 5207 __le16 target_id; 5208 __le64 resp_addr; 5209 __le32 flags; 5210 #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL 5211 #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL 5212 #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL 5213 #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX 5214 #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL 5215 __le16 port_id; 5216 u8 unused_0[2]; 5217 __le16 enables; 5218 #define PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT 0x1UL 5219 #define PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID 0x2UL 5220 #define PORT_TS_QUERY_REQ_ENABLES_PTP_HDR_OFFSET 0x4UL 5221 __le16 ts_req_timeout; 5222 __le32 ptp_seq_id; 5223 __le16 ptp_hdr_offset; 5224 u8 unused_1[6]; 5225 }; 5226 5227 /* hwrm_port_ts_query_output (size:192b/24B) */ 5228 struct hwrm_port_ts_query_output { 5229 __le16 error_code; 5230 __le16 req_type; 5231 __le16 seq_id; 5232 __le16 resp_len; 5233 __le64 ptp_msg_ts; 5234 __le16 ptp_msg_seqid; 5235 u8 unused_0[5]; 5236 u8 valid; 5237 }; 5238 5239 /* hwrm_port_phy_qcaps_input (size:192b/24B) */ 5240 struct hwrm_port_phy_qcaps_input { 5241 __le16 req_type; 5242 __le16 cmpl_ring; 5243 __le16 seq_id; 5244 __le16 target_id; 5245 __le64 resp_addr; 5246 __le16 port_id; 5247 u8 unused_0[6]; 5248 }; 5249 5250 /* hwrm_port_phy_qcaps_output (size:320b/40B) */ 5251 struct hwrm_port_phy_qcaps_output { 5252 __le16 error_code; 5253 __le16 req_type; 5254 __le16 seq_id; 5255 __le16 resp_len; 5256 u8 flags; 5257 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 5258 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 5259 #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL 5260 #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL 5261 #define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL 5262 #define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x20UL 5263 #define PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN 0x40UL 5264 #define PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS 0x80UL 5265 u8 port_cnt; 5266 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 5267 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 5268 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 5269 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 5270 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 5271 #define PORT_PHY_QCAPS_RESP_PORT_CNT_12 0xcUL 5272 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_12 5273 __le16 supported_speeds_force_mode; 5274 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 5275 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 5276 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 5277 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 5278 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 5279 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 5280 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 5281 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 5282 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 5283 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 5284 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 5285 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 5286 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 5287 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 5288 __le16 supported_speeds_auto_mode; 5289 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 5290 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 5291 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 5292 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 5293 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 5294 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 5295 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 5296 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 5297 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 5298 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 5299 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 5300 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 5301 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 5302 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 5303 __le16 supported_speeds_eee_mode; 5304 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 5305 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 5306 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 5307 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 5308 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 5309 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 5310 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 5311 __le32 tx_lpi_timer_low; 5312 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 5313 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 5314 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 5315 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 5316 __le32 valid_tx_lpi_timer_high; 5317 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 5318 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 5319 #define PORT_PHY_QCAPS_RESP_RSVD_MASK 0xff000000UL 5320 #define PORT_PHY_QCAPS_RESP_RSVD_SFT 24 5321 __le16 supported_pam4_speeds_auto_mode; 5322 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL 5323 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL 5324 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL 5325 __le16 supported_pam4_speeds_force_mode; 5326 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL 5327 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL 5328 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL 5329 __le16 flags2; 5330 #define PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED 0x1UL 5331 #define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED 0x2UL 5332 #define PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED 0x4UL 5333 #define PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED 0x8UL 5334 #define PORT_PHY_QCAPS_RESP_FLAGS2_REMOTE_LPBK_UNSUPPORTED 0x10UL 5335 u8 internal_port_cnt; 5336 u8 unused_0; 5337 __le16 supported_speeds2_force_mode; 5338 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_1GB 0x1UL 5339 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_10GB 0x2UL 5340 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_25GB 0x4UL 5341 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_40GB 0x8UL 5342 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB 0x10UL 5343 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB 0x20UL 5344 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB_PAM4_56 0x40UL 5345 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_56 0x80UL 5346 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_56 0x100UL 5347 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_56 0x200UL 5348 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_112 0x400UL 5349 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_112 0x800UL 5350 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_112 0x1000UL 5351 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_800GB_PAM4_112 0x2000UL 5352 __le16 supported_speeds2_auto_mode; 5353 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_1GB 0x1UL 5354 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_10GB 0x2UL 5355 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_25GB 0x4UL 5356 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_40GB 0x8UL 5357 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB 0x10UL 5358 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB 0x20UL 5359 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB_PAM4_56 0x40UL 5360 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_56 0x80UL 5361 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_56 0x100UL 5362 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_56 0x200UL 5363 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_112 0x400UL 5364 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_112 0x800UL 5365 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_112 0x1000UL 5366 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_800GB_PAM4_112 0x2000UL 5367 u8 unused_1[3]; 5368 u8 valid; 5369 }; 5370 5371 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 5372 struct hwrm_port_phy_i2c_read_input { 5373 __le16 req_type; 5374 __le16 cmpl_ring; 5375 __le16 seq_id; 5376 __le16 target_id; 5377 __le64 resp_addr; 5378 __le32 flags; 5379 __le32 enables; 5380 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 5381 #define PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER 0x2UL 5382 __le16 port_id; 5383 u8 i2c_slave_addr; 5384 u8 bank_number; 5385 __le16 page_number; 5386 __le16 page_offset; 5387 u8 data_length; 5388 u8 unused_1[7]; 5389 }; 5390 5391 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 5392 struct hwrm_port_phy_i2c_read_output { 5393 __le16 error_code; 5394 __le16 req_type; 5395 __le16 seq_id; 5396 __le16 resp_len; 5397 __le32 data[16]; 5398 u8 unused_0[7]; 5399 u8 valid; 5400 }; 5401 5402 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */ 5403 struct hwrm_port_phy_mdio_write_input { 5404 __le16 req_type; 5405 __le16 cmpl_ring; 5406 __le16 seq_id; 5407 __le16 target_id; 5408 __le64 resp_addr; 5409 __le32 unused_0[2]; 5410 __le16 port_id; 5411 u8 phy_addr; 5412 u8 dev_addr; 5413 __le16 reg_addr; 5414 __le16 reg_data; 5415 u8 cl45_mdio; 5416 u8 unused_1[7]; 5417 }; 5418 5419 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */ 5420 struct hwrm_port_phy_mdio_write_output { 5421 __le16 error_code; 5422 __le16 req_type; 5423 __le16 seq_id; 5424 __le16 resp_len; 5425 u8 unused_0[7]; 5426 u8 valid; 5427 }; 5428 5429 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */ 5430 struct hwrm_port_phy_mdio_read_input { 5431 __le16 req_type; 5432 __le16 cmpl_ring; 5433 __le16 seq_id; 5434 __le16 target_id; 5435 __le64 resp_addr; 5436 __le32 unused_0[2]; 5437 __le16 port_id; 5438 u8 phy_addr; 5439 u8 dev_addr; 5440 __le16 reg_addr; 5441 u8 cl45_mdio; 5442 u8 unused_1; 5443 }; 5444 5445 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */ 5446 struct hwrm_port_phy_mdio_read_output { 5447 __le16 error_code; 5448 __le16 req_type; 5449 __le16 seq_id; 5450 __le16 resp_len; 5451 __le16 reg_data; 5452 u8 unused_0[5]; 5453 u8 valid; 5454 }; 5455 5456 /* hwrm_port_led_cfg_input (size:512b/64B) */ 5457 struct hwrm_port_led_cfg_input { 5458 __le16 req_type; 5459 __le16 cmpl_ring; 5460 __le16 seq_id; 5461 __le16 target_id; 5462 __le64 resp_addr; 5463 __le32 enables; 5464 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 5465 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 5466 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 5467 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 5468 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 5469 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 5470 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 5471 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 5472 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 5473 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 5474 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 5475 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 5476 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 5477 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 5478 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 5479 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 5480 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 5481 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 5482 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 5483 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 5484 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 5485 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 5486 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 5487 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 5488 __le16 port_id; 5489 u8 num_leds; 5490 u8 rsvd; 5491 u8 led0_id; 5492 u8 led0_state; 5493 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 5494 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 5495 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 5496 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 5497 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 5498 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 5499 u8 led0_color; 5500 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 5501 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 5502 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 5503 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 5504 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 5505 u8 unused_0; 5506 __le16 led0_blink_on; 5507 __le16 led0_blink_off; 5508 u8 led0_group_id; 5509 u8 rsvd0; 5510 u8 led1_id; 5511 u8 led1_state; 5512 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 5513 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 5514 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 5515 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 5516 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 5517 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 5518 u8 led1_color; 5519 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 5520 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 5521 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 5522 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 5523 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 5524 u8 unused_1; 5525 __le16 led1_blink_on; 5526 __le16 led1_blink_off; 5527 u8 led1_group_id; 5528 u8 rsvd1; 5529 u8 led2_id; 5530 u8 led2_state; 5531 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 5532 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 5533 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 5534 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 5535 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 5536 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 5537 u8 led2_color; 5538 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 5539 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 5540 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 5541 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 5542 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 5543 u8 unused_2; 5544 __le16 led2_blink_on; 5545 __le16 led2_blink_off; 5546 u8 led2_group_id; 5547 u8 rsvd2; 5548 u8 led3_id; 5549 u8 led3_state; 5550 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 5551 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 5552 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 5553 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 5554 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 5555 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 5556 u8 led3_color; 5557 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 5558 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 5559 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 5560 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 5561 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 5562 u8 unused_3; 5563 __le16 led3_blink_on; 5564 __le16 led3_blink_off; 5565 u8 led3_group_id; 5566 u8 rsvd3; 5567 }; 5568 5569 /* hwrm_port_led_cfg_output (size:128b/16B) */ 5570 struct hwrm_port_led_cfg_output { 5571 __le16 error_code; 5572 __le16 req_type; 5573 __le16 seq_id; 5574 __le16 resp_len; 5575 u8 unused_0[7]; 5576 u8 valid; 5577 }; 5578 5579 /* hwrm_port_led_qcfg_input (size:192b/24B) */ 5580 struct hwrm_port_led_qcfg_input { 5581 __le16 req_type; 5582 __le16 cmpl_ring; 5583 __le16 seq_id; 5584 __le16 target_id; 5585 __le64 resp_addr; 5586 __le16 port_id; 5587 u8 unused_0[6]; 5588 }; 5589 5590 /* hwrm_port_led_qcfg_output (size:448b/56B) */ 5591 struct hwrm_port_led_qcfg_output { 5592 __le16 error_code; 5593 __le16 req_type; 5594 __le16 seq_id; 5595 __le16 resp_len; 5596 u8 num_leds; 5597 u8 led0_id; 5598 u8 led0_type; 5599 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 5600 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 5601 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 5602 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 5603 u8 led0_state; 5604 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 5605 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 5606 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 5607 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 5608 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 5609 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 5610 u8 led0_color; 5611 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 5612 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 5613 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 5614 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 5615 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 5616 u8 unused_0; 5617 __le16 led0_blink_on; 5618 __le16 led0_blink_off; 5619 u8 led0_group_id; 5620 u8 led1_id; 5621 u8 led1_type; 5622 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 5623 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 5624 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 5625 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 5626 u8 led1_state; 5627 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 5628 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 5629 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 5630 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 5631 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 5632 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 5633 u8 led1_color; 5634 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 5635 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 5636 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 5637 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 5638 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 5639 u8 unused_1; 5640 __le16 led1_blink_on; 5641 __le16 led1_blink_off; 5642 u8 led1_group_id; 5643 u8 led2_id; 5644 u8 led2_type; 5645 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 5646 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 5647 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 5648 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 5649 u8 led2_state; 5650 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 5651 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 5652 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 5653 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 5654 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 5655 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 5656 u8 led2_color; 5657 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 5658 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 5659 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 5660 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 5661 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 5662 u8 unused_2; 5663 __le16 led2_blink_on; 5664 __le16 led2_blink_off; 5665 u8 led2_group_id; 5666 u8 led3_id; 5667 u8 led3_type; 5668 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 5669 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 5670 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 5671 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 5672 u8 led3_state; 5673 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 5674 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 5675 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 5676 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 5677 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 5678 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 5679 u8 led3_color; 5680 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 5681 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 5682 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 5683 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 5684 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 5685 u8 unused_3; 5686 __le16 led3_blink_on; 5687 __le16 led3_blink_off; 5688 u8 led3_group_id; 5689 u8 unused_4[6]; 5690 u8 valid; 5691 }; 5692 5693 /* hwrm_port_led_qcaps_input (size:192b/24B) */ 5694 struct hwrm_port_led_qcaps_input { 5695 __le16 req_type; 5696 __le16 cmpl_ring; 5697 __le16 seq_id; 5698 __le16 target_id; 5699 __le64 resp_addr; 5700 __le16 port_id; 5701 u8 unused_0[6]; 5702 }; 5703 5704 /* hwrm_port_led_qcaps_output (size:384b/48B) */ 5705 struct hwrm_port_led_qcaps_output { 5706 __le16 error_code; 5707 __le16 req_type; 5708 __le16 seq_id; 5709 __le16 resp_len; 5710 u8 num_leds; 5711 u8 unused[3]; 5712 u8 led0_id; 5713 u8 led0_type; 5714 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 5715 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 5716 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 5717 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 5718 u8 led0_group_id; 5719 u8 unused_0; 5720 __le16 led0_state_caps; 5721 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 5722 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 5723 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 5724 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5725 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5726 __le16 led0_color_caps; 5727 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 5728 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5729 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5730 u8 led1_id; 5731 u8 led1_type; 5732 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 5733 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 5734 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 5735 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 5736 u8 led1_group_id; 5737 u8 unused_1; 5738 __le16 led1_state_caps; 5739 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 5740 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 5741 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 5742 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5743 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5744 __le16 led1_color_caps; 5745 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 5746 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5747 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5748 u8 led2_id; 5749 u8 led2_type; 5750 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 5751 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 5752 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 5753 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 5754 u8 led2_group_id; 5755 u8 unused_2; 5756 __le16 led2_state_caps; 5757 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 5758 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 5759 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 5760 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5761 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5762 __le16 led2_color_caps; 5763 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 5764 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5765 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5766 u8 led3_id; 5767 u8 led3_type; 5768 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 5769 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 5770 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 5771 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 5772 u8 led3_group_id; 5773 u8 unused_3; 5774 __le16 led3_state_caps; 5775 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 5776 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 5777 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 5778 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5779 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5780 __le16 led3_color_caps; 5781 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 5782 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5783 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5784 u8 unused_4[3]; 5785 u8 valid; 5786 }; 5787 5788 /* hwrm_port_mac_qcaps_input (size:192b/24B) */ 5789 struct hwrm_port_mac_qcaps_input { 5790 __le16 req_type; 5791 __le16 cmpl_ring; 5792 __le16 seq_id; 5793 __le16 target_id; 5794 __le64 resp_addr; 5795 __le16 port_id; 5796 u8 unused_0[6]; 5797 }; 5798 5799 /* hwrm_port_mac_qcaps_output (size:128b/16B) */ 5800 struct hwrm_port_mac_qcaps_output { 5801 __le16 error_code; 5802 __le16 req_type; 5803 __le16 seq_id; 5804 __le16 resp_len; 5805 u8 flags; 5806 #define PORT_MAC_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x1UL 5807 #define PORT_MAC_QCAPS_RESP_FLAGS_REMOTE_LPBK_SUPPORTED 0x2UL 5808 u8 unused_0[6]; 5809 u8 valid; 5810 }; 5811 5812 /* hwrm_queue_qportcfg_input (size:192b/24B) */ 5813 struct hwrm_queue_qportcfg_input { 5814 __le16 req_type; 5815 __le16 cmpl_ring; 5816 __le16 seq_id; 5817 __le16 target_id; 5818 __le64 resp_addr; 5819 __le32 flags; 5820 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 5821 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 5822 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 5823 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 5824 __le16 port_id; 5825 u8 drv_qmap_cap; 5826 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 5827 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 5828 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 5829 u8 unused_0; 5830 }; 5831 5832 /* hwrm_queue_qportcfg_output (size:1344b/168B) */ 5833 struct hwrm_queue_qportcfg_output { 5834 __le16 error_code; 5835 __le16 req_type; 5836 __le16 seq_id; 5837 __le16 resp_len; 5838 u8 max_configurable_queues; 5839 u8 max_configurable_lossless_queues; 5840 u8 queue_cfg_allowed; 5841 u8 queue_cfg_info; 5842 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 5843 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_USE_PROFILE_TYPE 0x2UL 5844 u8 queue_pfcenable_cfg_allowed; 5845 u8 queue_pri2cos_cfg_allowed; 5846 u8 queue_cos2bw_cfg_allowed; 5847 u8 queue_id0; 5848 u8 queue_id0_service_profile; 5849 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 5850 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 5851 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5852 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5853 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5854 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 5855 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 5856 u8 queue_id1; 5857 u8 queue_id1_service_profile; 5858 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 5859 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 5860 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5861 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5862 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5863 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 5864 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 5865 u8 queue_id2; 5866 u8 queue_id2_service_profile; 5867 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 5868 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 5869 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5870 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5871 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5872 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 5873 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 5874 u8 queue_id3; 5875 u8 queue_id3_service_profile; 5876 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 5877 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 5878 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5879 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5880 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5881 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 5882 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 5883 u8 queue_id4; 5884 u8 queue_id4_service_profile; 5885 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 5886 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 5887 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5888 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5889 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5890 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 5891 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 5892 u8 queue_id5; 5893 u8 queue_id5_service_profile; 5894 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 5895 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 5896 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5897 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5898 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5899 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 5900 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 5901 u8 queue_id6; 5902 u8 queue_id6_service_profile; 5903 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 5904 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 5905 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5906 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5907 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5908 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 5909 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 5910 u8 queue_id7; 5911 u8 queue_id7_service_profile; 5912 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 5913 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 5914 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5915 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5916 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5917 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 5918 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 5919 u8 queue_id0_service_profile_type; 5920 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5921 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC 0x2UL 5922 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP 0x4UL 5923 char qid0_name[16]; 5924 char qid1_name[16]; 5925 char qid2_name[16]; 5926 char qid3_name[16]; 5927 char qid4_name[16]; 5928 char qid5_name[16]; 5929 char qid6_name[16]; 5930 char qid7_name[16]; 5931 u8 queue_id1_service_profile_type; 5932 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5933 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC 0x2UL 5934 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP 0x4UL 5935 u8 queue_id2_service_profile_type; 5936 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5937 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC 0x2UL 5938 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP 0x4UL 5939 u8 queue_id3_service_profile_type; 5940 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5941 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC 0x2UL 5942 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP 0x4UL 5943 u8 queue_id4_service_profile_type; 5944 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5945 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC 0x2UL 5946 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP 0x4UL 5947 u8 queue_id5_service_profile_type; 5948 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5949 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC 0x2UL 5950 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP 0x4UL 5951 u8 queue_id6_service_profile_type; 5952 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5953 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC 0x2UL 5954 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP 0x4UL 5955 u8 queue_id7_service_profile_type; 5956 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5957 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC 0x2UL 5958 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP 0x4UL 5959 u8 valid; 5960 }; 5961 5962 /* hwrm_queue_qcfg_input (size:192b/24B) */ 5963 struct hwrm_queue_qcfg_input { 5964 __le16 req_type; 5965 __le16 cmpl_ring; 5966 __le16 seq_id; 5967 __le16 target_id; 5968 __le64 resp_addr; 5969 __le32 flags; 5970 #define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL 5971 #define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL 5972 #define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL 5973 #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX 5974 __le32 queue_id; 5975 }; 5976 5977 /* hwrm_queue_qcfg_output (size:128b/16B) */ 5978 struct hwrm_queue_qcfg_output { 5979 __le16 error_code; 5980 __le16 req_type; 5981 __le16 seq_id; 5982 __le16 resp_len; 5983 __le32 queue_len; 5984 u8 service_profile; 5985 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL 5986 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL 5987 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL 5988 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 5989 u8 queue_cfg_info; 5990 #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 5991 u8 unused_0; 5992 u8 valid; 5993 }; 5994 5995 /* hwrm_queue_cfg_input (size:320b/40B) */ 5996 struct hwrm_queue_cfg_input { 5997 __le16 req_type; 5998 __le16 cmpl_ring; 5999 __le16 seq_id; 6000 __le16 target_id; 6001 __le64 resp_addr; 6002 __le32 flags; 6003 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 6004 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 6005 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 6006 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 6007 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 6008 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 6009 __le32 enables; 6010 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 6011 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 6012 __le32 queue_id; 6013 __le32 dflt_len; 6014 u8 service_profile; 6015 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 6016 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 6017 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 6018 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 6019 u8 unused_0[7]; 6020 }; 6021 6022 /* hwrm_queue_cfg_output (size:128b/16B) */ 6023 struct hwrm_queue_cfg_output { 6024 __le16 error_code; 6025 __le16 req_type; 6026 __le16 seq_id; 6027 __le16 resp_len; 6028 u8 unused_0[7]; 6029 u8 valid; 6030 }; 6031 6032 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 6033 struct hwrm_queue_pfcenable_qcfg_input { 6034 __le16 req_type; 6035 __le16 cmpl_ring; 6036 __le16 seq_id; 6037 __le16 target_id; 6038 __le64 resp_addr; 6039 __le16 port_id; 6040 u8 unused_0[6]; 6041 }; 6042 6043 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 6044 struct hwrm_queue_pfcenable_qcfg_output { 6045 __le16 error_code; 6046 __le16 req_type; 6047 __le16 seq_id; 6048 __le16 resp_len; 6049 __le32 flags; 6050 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 6051 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 6052 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 6053 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 6054 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 6055 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 6056 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 6057 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 6058 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 6059 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 6060 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 6061 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 6062 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 6063 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 6064 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 6065 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 6066 u8 unused_0[3]; 6067 u8 valid; 6068 }; 6069 6070 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 6071 struct hwrm_queue_pfcenable_cfg_input { 6072 __le16 req_type; 6073 __le16 cmpl_ring; 6074 __le16 seq_id; 6075 __le16 target_id; 6076 __le64 resp_addr; 6077 __le32 flags; 6078 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 6079 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 6080 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 6081 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 6082 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 6083 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 6084 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 6085 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 6086 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 6087 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 6088 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 6089 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 6090 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 6091 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 6092 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 6093 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 6094 __le16 port_id; 6095 u8 unused_0[2]; 6096 }; 6097 6098 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 6099 struct hwrm_queue_pfcenable_cfg_output { 6100 __le16 error_code; 6101 __le16 req_type; 6102 __le16 seq_id; 6103 __le16 resp_len; 6104 u8 unused_0[7]; 6105 u8 valid; 6106 }; 6107 6108 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 6109 struct hwrm_queue_pri2cos_qcfg_input { 6110 __le16 req_type; 6111 __le16 cmpl_ring; 6112 __le16 seq_id; 6113 __le16 target_id; 6114 __le64 resp_addr; 6115 __le32 flags; 6116 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 6117 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 6118 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 6119 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 6120 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 6121 u8 port_id; 6122 u8 unused_0[3]; 6123 }; 6124 6125 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 6126 struct hwrm_queue_pri2cos_qcfg_output { 6127 __le16 error_code; 6128 __le16 req_type; 6129 __le16 seq_id; 6130 __le16 resp_len; 6131 u8 pri0_cos_queue_id; 6132 u8 pri1_cos_queue_id; 6133 u8 pri2_cos_queue_id; 6134 u8 pri3_cos_queue_id; 6135 u8 pri4_cos_queue_id; 6136 u8 pri5_cos_queue_id; 6137 u8 pri6_cos_queue_id; 6138 u8 pri7_cos_queue_id; 6139 u8 queue_cfg_info; 6140 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 6141 u8 unused_0[6]; 6142 u8 valid; 6143 }; 6144 6145 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 6146 struct hwrm_queue_pri2cos_cfg_input { 6147 __le16 req_type; 6148 __le16 cmpl_ring; 6149 __le16 seq_id; 6150 __le16 target_id; 6151 __le64 resp_addr; 6152 __le32 flags; 6153 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 6154 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 6155 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 6156 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 6157 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 6158 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 6159 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 6160 __le32 enables; 6161 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 6162 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 6163 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 6164 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 6165 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 6166 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 6167 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 6168 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 6169 u8 port_id; 6170 u8 pri0_cos_queue_id; 6171 u8 pri1_cos_queue_id; 6172 u8 pri2_cos_queue_id; 6173 u8 pri3_cos_queue_id; 6174 u8 pri4_cos_queue_id; 6175 u8 pri5_cos_queue_id; 6176 u8 pri6_cos_queue_id; 6177 u8 pri7_cos_queue_id; 6178 u8 unused_0[7]; 6179 }; 6180 6181 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 6182 struct hwrm_queue_pri2cos_cfg_output { 6183 __le16 error_code; 6184 __le16 req_type; 6185 __le16 seq_id; 6186 __le16 resp_len; 6187 u8 unused_0[7]; 6188 u8 valid; 6189 }; 6190 6191 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 6192 struct hwrm_queue_cos2bw_qcfg_input { 6193 __le16 req_type; 6194 __le16 cmpl_ring; 6195 __le16 seq_id; 6196 __le16 target_id; 6197 __le64 resp_addr; 6198 __le16 port_id; 6199 u8 unused_0[6]; 6200 }; 6201 6202 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 6203 struct hwrm_queue_cos2bw_qcfg_output { 6204 __le16 error_code; 6205 __le16 req_type; 6206 __le16 seq_id; 6207 __le16 resp_len; 6208 u8 queue_id0; 6209 u8 unused_0; 6210 __le16 unused_1; 6211 __le32 queue_id0_min_bw; 6212 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6213 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 6214 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 6215 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 6216 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 6217 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 6218 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6219 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 6220 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6221 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6222 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6223 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6224 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6225 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6226 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 6227 __le32 queue_id0_max_bw; 6228 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6229 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 6230 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 6231 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 6232 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 6233 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 6234 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6235 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 6236 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6237 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6238 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6239 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6240 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6241 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6242 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 6243 u8 queue_id0_tsa_assign; 6244 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 6245 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 6246 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6247 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 6248 u8 queue_id0_pri_lvl; 6249 u8 queue_id0_bw_weight; 6250 struct { 6251 u8 queue_id; 6252 __le32 queue_id_min_bw; 6253 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6254 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_SFT 0 6255 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE 0x10000000UL 6256 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BITS (0x0UL << 28) 6257 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BYTES (0x1UL << 28) 6258 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BYTES 6259 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6260 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_SFT 29 6261 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6262 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6263 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6264 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6265 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6266 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6267 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID 6268 __le32 queue_id_max_bw; 6269 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6270 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_SFT 0 6271 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE 0x10000000UL 6272 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BITS (0x0UL << 28) 6273 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BYTES (0x1UL << 28) 6274 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BYTES 6275 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6276 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_SFT 29 6277 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6278 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6279 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6280 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6281 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6282 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6283 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID 6284 u8 queue_id_tsa_assign; 6285 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_SP 0x0UL 6286 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_ETS 0x1UL 6287 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6288 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_RESERVED_LAST 0xffUL 6289 u8 queue_id_pri_lvl; 6290 u8 queue_id_bw_weight; 6291 } __packed cfg[7]; 6292 u8 unused_2[4]; 6293 u8 valid; 6294 }; 6295 6296 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 6297 struct hwrm_queue_cos2bw_cfg_input { 6298 __le16 req_type; 6299 __le16 cmpl_ring; 6300 __le16 seq_id; 6301 __le16 target_id; 6302 __le64 resp_addr; 6303 __le32 flags; 6304 __le32 enables; 6305 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 6306 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 6307 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 6308 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 6309 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 6310 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 6311 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 6312 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 6313 __le16 port_id; 6314 u8 queue_id0; 6315 u8 unused_0; 6316 __le32 queue_id0_min_bw; 6317 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6318 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 6319 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 6320 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 6321 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 6322 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 6323 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6324 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 6325 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6326 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6327 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6328 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6329 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6330 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6331 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 6332 __le32 queue_id0_max_bw; 6333 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6334 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 6335 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 6336 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 6337 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 6338 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 6339 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6340 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 6341 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6342 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6343 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6344 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6345 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6346 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6347 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 6348 u8 queue_id0_tsa_assign; 6349 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 6350 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 6351 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6352 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 6353 u8 queue_id0_pri_lvl; 6354 u8 queue_id0_bw_weight; 6355 struct { 6356 u8 queue_id; 6357 __le32 queue_id_min_bw; 6358 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6359 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_SFT 0 6360 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE 0x10000000UL 6361 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BITS (0x0UL << 28) 6362 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BYTES (0x1UL << 28) 6363 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BYTES 6364 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6365 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_SFT 29 6366 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6367 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6368 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6369 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6370 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6371 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6372 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID 6373 __le32 queue_id_max_bw; 6374 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6375 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_SFT 0 6376 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE 0x10000000UL 6377 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BITS (0x0UL << 28) 6378 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BYTES (0x1UL << 28) 6379 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BYTES 6380 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6381 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_SFT 29 6382 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6383 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6384 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6385 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6386 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6387 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6388 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID 6389 u8 queue_id_tsa_assign; 6390 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_SP 0x0UL 6391 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_ETS 0x1UL 6392 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6393 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_RESERVED_LAST 0xffUL 6394 u8 queue_id_pri_lvl; 6395 u8 queue_id_bw_weight; 6396 } __packed cfg[7]; 6397 u8 unused_1[5]; 6398 }; 6399 6400 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 6401 struct hwrm_queue_cos2bw_cfg_output { 6402 __le16 error_code; 6403 __le16 req_type; 6404 __le16 seq_id; 6405 __le16 resp_len; 6406 u8 unused_0[7]; 6407 u8 valid; 6408 }; 6409 6410 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 6411 struct hwrm_queue_dscp_qcaps_input { 6412 __le16 req_type; 6413 __le16 cmpl_ring; 6414 __le16 seq_id; 6415 __le16 target_id; 6416 __le64 resp_addr; 6417 u8 port_id; 6418 u8 unused_0[7]; 6419 }; 6420 6421 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 6422 struct hwrm_queue_dscp_qcaps_output { 6423 __le16 error_code; 6424 __le16 req_type; 6425 __le16 seq_id; 6426 __le16 resp_len; 6427 u8 num_dscp_bits; 6428 u8 unused_0; 6429 __le16 max_entries; 6430 u8 unused_1[3]; 6431 u8 valid; 6432 }; 6433 6434 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 6435 struct hwrm_queue_dscp2pri_qcfg_input { 6436 __le16 req_type; 6437 __le16 cmpl_ring; 6438 __le16 seq_id; 6439 __le16 target_id; 6440 __le64 resp_addr; 6441 __le64 dest_data_addr; 6442 u8 port_id; 6443 u8 unused_0; 6444 __le16 dest_data_buffer_size; 6445 u8 unused_1[4]; 6446 }; 6447 6448 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 6449 struct hwrm_queue_dscp2pri_qcfg_output { 6450 __le16 error_code; 6451 __le16 req_type; 6452 __le16 seq_id; 6453 __le16 resp_len; 6454 __le16 entry_cnt; 6455 u8 default_pri; 6456 u8 unused_0[4]; 6457 u8 valid; 6458 }; 6459 6460 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 6461 struct hwrm_queue_dscp2pri_cfg_input { 6462 __le16 req_type; 6463 __le16 cmpl_ring; 6464 __le16 seq_id; 6465 __le16 target_id; 6466 __le64 resp_addr; 6467 __le64 src_data_addr; 6468 __le32 flags; 6469 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 6470 __le32 enables; 6471 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 6472 u8 port_id; 6473 u8 default_pri; 6474 __le16 entry_cnt; 6475 u8 unused_0[4]; 6476 }; 6477 6478 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 6479 struct hwrm_queue_dscp2pri_cfg_output { 6480 __le16 error_code; 6481 __le16 req_type; 6482 __le16 seq_id; 6483 __le16 resp_len; 6484 u8 unused_0[7]; 6485 u8 valid; 6486 }; 6487 6488 /* hwrm_vnic_alloc_input (size:192b/24B) */ 6489 struct hwrm_vnic_alloc_input { 6490 __le16 req_type; 6491 __le16 cmpl_ring; 6492 __le16 seq_id; 6493 __le16 target_id; 6494 __le64 resp_addr; 6495 __le32 flags; 6496 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 6497 #define VNIC_ALLOC_REQ_FLAGS_VIRTIO_NET_FID_VALID 0x2UL 6498 __le16 virtio_net_fid; 6499 u8 unused_0[2]; 6500 }; 6501 6502 /* hwrm_vnic_alloc_output (size:128b/16B) */ 6503 struct hwrm_vnic_alloc_output { 6504 __le16 error_code; 6505 __le16 req_type; 6506 __le16 seq_id; 6507 __le16 resp_len; 6508 __le32 vnic_id; 6509 u8 unused_0[3]; 6510 u8 valid; 6511 }; 6512 6513 /* hwrm_vnic_free_input (size:192b/24B) */ 6514 struct hwrm_vnic_free_input { 6515 __le16 req_type; 6516 __le16 cmpl_ring; 6517 __le16 seq_id; 6518 __le16 target_id; 6519 __le64 resp_addr; 6520 __le32 vnic_id; 6521 u8 unused_0[4]; 6522 }; 6523 6524 /* hwrm_vnic_free_output (size:128b/16B) */ 6525 struct hwrm_vnic_free_output { 6526 __le16 error_code; 6527 __le16 req_type; 6528 __le16 seq_id; 6529 __le16 resp_len; 6530 u8 unused_0[7]; 6531 u8 valid; 6532 }; 6533 6534 /* hwrm_vnic_cfg_input (size:384b/48B) */ 6535 struct hwrm_vnic_cfg_input { 6536 __le16 req_type; 6537 __le16 cmpl_ring; 6538 __le16 seq_id; 6539 __le16 target_id; 6540 __le64 resp_addr; 6541 __le32 flags; 6542 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 6543 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 6544 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 6545 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 6546 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 6547 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 6548 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 6549 #define VNIC_CFG_REQ_FLAGS_PORTCOS_MAPPING_MODE 0x80UL 6550 __le32 enables; 6551 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 6552 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 6553 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 6554 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 6555 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 6556 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 6557 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 6558 #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL 6559 #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL 6560 #define VNIC_CFG_REQ_ENABLES_L2_CQE_MODE 0x200UL 6561 __le16 vnic_id; 6562 __le16 dflt_ring_grp; 6563 __le16 rss_rule; 6564 __le16 cos_rule; 6565 __le16 lb_rule; 6566 __le16 mru; 6567 __le16 default_rx_ring_id; 6568 __le16 default_cmpl_ring_id; 6569 __le16 queue_id; 6570 u8 rx_csum_v2_mode; 6571 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL 6572 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK 0x1UL 6573 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 0x2UL 6574 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 6575 u8 l2_cqe_mode; 6576 #define VNIC_CFG_REQ_L2_CQE_MODE_DEFAULT 0x0UL 6577 #define VNIC_CFG_REQ_L2_CQE_MODE_COMPRESSED 0x1UL 6578 #define VNIC_CFG_REQ_L2_CQE_MODE_MIXED 0x2UL 6579 #define VNIC_CFG_REQ_L2_CQE_MODE_LAST VNIC_CFG_REQ_L2_CQE_MODE_MIXED 6580 u8 unused0[4]; 6581 }; 6582 6583 /* hwrm_vnic_cfg_output (size:128b/16B) */ 6584 struct hwrm_vnic_cfg_output { 6585 __le16 error_code; 6586 __le16 req_type; 6587 __le16 seq_id; 6588 __le16 resp_len; 6589 u8 unused_0[7]; 6590 u8 valid; 6591 }; 6592 6593 /* hwrm_vnic_qcaps_input (size:192b/24B) */ 6594 struct hwrm_vnic_qcaps_input { 6595 __le16 req_type; 6596 __le16 cmpl_ring; 6597 __le16 seq_id; 6598 __le16 target_id; 6599 __le64 resp_addr; 6600 __le32 enables; 6601 u8 unused_0[4]; 6602 }; 6603 6604 /* hwrm_vnic_qcaps_output (size:192b/24B) */ 6605 struct hwrm_vnic_qcaps_output { 6606 __le16 error_code; 6607 __le16 req_type; 6608 __le16 seq_id; 6609 __le16 resp_len; 6610 __le16 mru; 6611 u8 unused_0[2]; 6612 __le32 flags; 6613 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 6614 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 6615 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 6616 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 6617 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 6618 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 6619 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 6620 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 6621 #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL 6622 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL 6623 #define VNIC_QCAPS_RESP_FLAGS_VNIC_STATE_CAP 0x400UL 6624 #define VNIC_QCAPS_RESP_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP 0x800UL 6625 #define VNIC_QCAPS_RESP_FLAGS_METADATA_FORMAT_CAP 0x1000UL 6626 #define VNIC_QCAPS_RESP_FLAGS_RSS_STRICT_HASH_TYPE_CAP 0x2000UL 6627 #define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP 0x4000UL 6628 #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CAP 0x8000UL 6629 #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_XOR_CAP 0x10000UL 6630 #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CHKSM_CAP 0x20000UL 6631 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPV6_FLOW_LABEL_CAP 0x40000UL 6632 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V3_CAP 0x80000UL 6633 #define VNIC_QCAPS_RESP_FLAGS_L2_CQE_MODE_CAP 0x100000UL 6634 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP 0x200000UL 6635 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP 0x400000UL 6636 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP 0x800000UL 6637 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP 0x1000000UL 6638 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP 0x2000000UL 6639 #define VNIC_QCAPS_RESP_FLAGS_PORTCOS_MAPPING_MODE 0x4000000UL 6640 #define VNIC_QCAPS_RESP_FLAGS_RSS_PROF_TCAM_MODE_ENABLED 0x8000000UL 6641 #define VNIC_QCAPS_RESP_FLAGS_VNIC_RSS_HASH_MODE_CAP 0x10000000UL 6642 #define VNIC_QCAPS_RESP_FLAGS_HW_TUNNEL_TPA_CAP 0x20000000UL 6643 __le16 max_aggs_supported; 6644 u8 unused_1[5]; 6645 u8 valid; 6646 }; 6647 6648 /* hwrm_vnic_tpa_cfg_input (size:384b/48B) */ 6649 struct hwrm_vnic_tpa_cfg_input { 6650 __le16 req_type; 6651 __le16 cmpl_ring; 6652 __le16 seq_id; 6653 __le16 target_id; 6654 __le64 resp_addr; 6655 __le32 flags; 6656 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 6657 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 6658 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 6659 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 6660 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 6661 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 6662 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 6663 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 6664 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL 6665 __le32 enables; 6666 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 6667 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 6668 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 6669 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 6670 #define VNIC_TPA_CFG_REQ_ENABLES_TNL_TPA_EN 0x10UL 6671 __le16 vnic_id; 6672 __le16 max_agg_segs; 6673 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 6674 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 6675 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 6676 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 6677 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 6678 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 6679 __le16 max_aggs; 6680 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 6681 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 6682 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 6683 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 6684 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 6685 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 6686 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 6687 u8 unused_0[2]; 6688 __le32 max_agg_timer; 6689 __le32 min_agg_len; 6690 __le32 tnl_tpa_en_bitmap; 6691 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN 0x1UL 6692 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GENEVE 0x2UL 6693 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_NVGRE 0x4UL 6694 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GRE 0x8UL 6695 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_IPV4 0x10UL 6696 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_IPV6 0x20UL 6697 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN_GPE 0x40UL 6698 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN_CUST1 0x80UL 6699 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GRE_CUST1 0x100UL 6700 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR1 0x200UL 6701 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR2 0x400UL 6702 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR3 0x800UL 6703 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR4 0x1000UL 6704 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR5 0x2000UL 6705 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR6 0x4000UL 6706 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR7 0x8000UL 6707 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR8 0x10000UL 6708 u8 unused_1[4]; 6709 }; 6710 6711 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 6712 struct hwrm_vnic_tpa_cfg_output { 6713 __le16 error_code; 6714 __le16 req_type; 6715 __le16 seq_id; 6716 __le16 resp_len; 6717 u8 unused_0[7]; 6718 u8 valid; 6719 }; 6720 6721 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 6722 struct hwrm_vnic_tpa_qcfg_input { 6723 __le16 req_type; 6724 __le16 cmpl_ring; 6725 __le16 seq_id; 6726 __le16 target_id; 6727 __le64 resp_addr; 6728 __le16 vnic_id; 6729 u8 unused_0[6]; 6730 }; 6731 6732 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 6733 struct hwrm_vnic_tpa_qcfg_output { 6734 __le16 error_code; 6735 __le16 req_type; 6736 __le16 seq_id; 6737 __le16 resp_len; 6738 __le32 flags; 6739 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 6740 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 6741 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 6742 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 6743 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 6744 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 6745 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 6746 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 6747 __le16 max_agg_segs; 6748 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 6749 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 6750 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 6751 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 6752 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 6753 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 6754 __le16 max_aggs; 6755 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 6756 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 6757 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 6758 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 6759 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 6760 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 6761 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 6762 __le32 max_agg_timer; 6763 __le32 min_agg_len; 6764 __le32 tnl_tpa_en_bitmap; 6765 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN 0x1UL 6766 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GENEVE 0x2UL 6767 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_NVGRE 0x4UL 6768 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GRE 0x8UL 6769 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_IPV4 0x10UL 6770 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_IPV6 0x20UL 6771 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN_GPE 0x40UL 6772 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN_CUST1 0x80UL 6773 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GRE_CUST1 0x100UL 6774 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR1 0x200UL 6775 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR2 0x400UL 6776 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR3 0x800UL 6777 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR4 0x1000UL 6778 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR5 0x2000UL 6779 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR6 0x4000UL 6780 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR7 0x8000UL 6781 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR8 0x10000UL 6782 u8 unused_0[3]; 6783 u8 valid; 6784 }; 6785 6786 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 6787 struct hwrm_vnic_rss_cfg_input { 6788 __le16 req_type; 6789 __le16 cmpl_ring; 6790 __le16 seq_id; 6791 __le16 target_id; 6792 __le64 resp_addr; 6793 __le32 hash_type; 6794 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 6795 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 6796 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 6797 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 6798 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 6799 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 6800 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL 0x40UL 6801 #define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 0x80UL 6802 #define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4 0x100UL 6803 #define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 0x200UL 6804 #define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6 0x400UL 6805 __le16 vnic_id; 6806 u8 ring_table_pair_index; 6807 u8 hash_mode_flags; 6808 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 6809 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 6810 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 6811 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 6812 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 6813 __le64 ring_grp_tbl_addr; 6814 __le64 hash_key_tbl_addr; 6815 __le16 rss_ctx_idx; 6816 u8 flags; 6817 #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_INCLUDE 0x1UL 6818 #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_EXCLUDE 0x2UL 6819 #define VNIC_RSS_CFG_REQ_FLAGS_IPSEC_HASH_TYPE_CFG_SUPPORT 0x4UL 6820 u8 ring_select_mode; 6821 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ 0x0UL 6822 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_XOR 0x1UL 6823 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL 6824 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_LAST VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 6825 u8 unused_1[4]; 6826 }; 6827 6828 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 6829 struct hwrm_vnic_rss_cfg_output { 6830 __le16 error_code; 6831 __le16 req_type; 6832 __le16 seq_id; 6833 __le16 resp_len; 6834 u8 unused_0[7]; 6835 u8 valid; 6836 }; 6837 6838 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ 6839 struct hwrm_vnic_rss_cfg_cmd_err { 6840 u8 code; 6841 #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 6842 #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL 6843 #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 6844 u8 unused_0[7]; 6845 }; 6846 6847 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */ 6848 struct hwrm_vnic_rss_qcfg_input { 6849 __le16 req_type; 6850 __le16 cmpl_ring; 6851 __le16 seq_id; 6852 __le16 target_id; 6853 __le64 resp_addr; 6854 __le16 rss_ctx_idx; 6855 __le16 vnic_id; 6856 u8 unused_0[4]; 6857 }; 6858 6859 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */ 6860 struct hwrm_vnic_rss_qcfg_output { 6861 __le16 error_code; 6862 __le16 req_type; 6863 __le16 seq_id; 6864 __le16 resp_len; 6865 __le32 hash_type; 6866 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV4 0x1UL 6867 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV4 0x2UL 6868 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV4 0x4UL 6869 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6 0x8UL 6870 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV6 0x10UL 6871 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV6 0x20UL 6872 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6_FLOW_LABEL 0x40UL 6873 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV4 0x80UL 6874 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV4 0x100UL 6875 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV6 0x200UL 6876 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV6 0x400UL 6877 u8 unused_0[4]; 6878 __le32 hash_key[10]; 6879 u8 hash_mode_flags; 6880 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_DEFAULT 0x1UL 6881 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 6882 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 6883 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 6884 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 6885 u8 ring_select_mode; 6886 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ 0x0UL 6887 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_XOR 0x1UL 6888 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL 6889 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_LAST VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 6890 u8 unused_1[5]; 6891 u8 valid; 6892 }; 6893 6894 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 6895 struct hwrm_vnic_plcmodes_cfg_input { 6896 __le16 req_type; 6897 __le16 cmpl_ring; 6898 __le16 seq_id; 6899 __le16 target_id; 6900 __le64 resp_addr; 6901 __le32 flags; 6902 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 6903 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 6904 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 6905 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 6906 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 6907 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 6908 #define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT 0x40UL 6909 __le32 enables; 6910 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 6911 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 6912 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 6913 #define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID 0x8UL 6914 __le32 vnic_id; 6915 __le16 jumbo_thresh; 6916 __le16 hds_offset; 6917 __le16 hds_threshold; 6918 __le16 max_bds; 6919 u8 unused_0[4]; 6920 }; 6921 6922 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 6923 struct hwrm_vnic_plcmodes_cfg_output { 6924 __le16 error_code; 6925 __le16 req_type; 6926 __le16 seq_id; 6927 __le16 resp_len; 6928 u8 unused_0[7]; 6929 u8 valid; 6930 }; 6931 6932 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 6933 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 6934 __le16 req_type; 6935 __le16 cmpl_ring; 6936 __le16 seq_id; 6937 __le16 target_id; 6938 __le64 resp_addr; 6939 }; 6940 6941 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 6942 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 6943 __le16 error_code; 6944 __le16 req_type; 6945 __le16 seq_id; 6946 __le16 resp_len; 6947 __le16 rss_cos_lb_ctx_id; 6948 u8 unused_0[5]; 6949 u8 valid; 6950 }; 6951 6952 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 6953 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 6954 __le16 req_type; 6955 __le16 cmpl_ring; 6956 __le16 seq_id; 6957 __le16 target_id; 6958 __le64 resp_addr; 6959 __le16 rss_cos_lb_ctx_id; 6960 u8 unused_0[6]; 6961 }; 6962 6963 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 6964 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 6965 __le16 error_code; 6966 __le16 req_type; 6967 __le16 seq_id; 6968 __le16 resp_len; 6969 u8 unused_0[7]; 6970 u8 valid; 6971 }; 6972 6973 /* hwrm_ring_alloc_input (size:704b/88B) */ 6974 struct hwrm_ring_alloc_input { 6975 __le16 req_type; 6976 __le16 cmpl_ring; 6977 __le16 seq_id; 6978 __le16 target_id; 6979 __le64 resp_addr; 6980 __le32 enables; 6981 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 6982 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 6983 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 6984 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 6985 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 6986 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 6987 #define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL 6988 #define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL 6989 #define RING_ALLOC_REQ_ENABLES_STEERING_TAG_VALID 0x800UL 6990 u8 ring_type; 6991 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 6992 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 6993 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 6994 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 6995 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 6996 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 6997 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 6998 u8 cmpl_coal_cnt; 6999 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_OFF 0x0UL 7000 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_4 0x1UL 7001 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_8 0x2UL 7002 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_12 0x3UL 7003 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_16 0x4UL 7004 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_24 0x5UL 7005 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_32 0x6UL 7006 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_48 0x7UL 7007 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_64 0x8UL 7008 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_96 0x9UL 7009 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_128 0xaUL 7010 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_192 0xbUL 7011 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_256 0xcUL 7012 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_320 0xdUL 7013 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_384 0xeUL 7014 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 0xfUL 7015 #define RING_ALLOC_REQ_CMPL_COAL_CNT_LAST RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 7016 __le16 flags; 7017 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 7018 #define RING_ALLOC_REQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION 0x2UL 7019 #define RING_ALLOC_REQ_FLAGS_NQ_DBR_PACING 0x4UL 7020 #define RING_ALLOC_REQ_FLAGS_TX_PKT_TS_CMPL_ENABLE 0x8UL 7021 __le64 page_tbl_addr; 7022 __le32 fbo; 7023 u8 page_size; 7024 u8 page_tbl_depth; 7025 __le16 schq_id; 7026 __le32 length; 7027 __le16 logical_id; 7028 __le16 cmpl_ring_id; 7029 __le16 queue_id; 7030 __le16 rx_buf_size; 7031 __le16 rx_ring_id; 7032 __le16 nq_ring_id; 7033 __le16 ring_arb_cfg; 7034 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 7035 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 7036 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 7037 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 7038 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 7039 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 7040 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 7041 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 7042 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 7043 __le16 steering_tag; 7044 __le32 reserved3; 7045 __le32 stat_ctx_id; 7046 __le32 reserved4; 7047 __le32 max_bw; 7048 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 7049 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 7050 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 7051 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 7052 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 7053 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 7054 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 7055 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 7056 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 7057 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 7058 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 7059 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 7060 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 7061 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 7062 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 7063 u8 int_mode; 7064 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 7065 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 7066 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 7067 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 7068 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 7069 u8 mpc_chnls_type; 7070 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE 0x0UL 7071 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE 0x1UL 7072 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA 0x2UL 7073 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL 7074 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL 7075 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 7076 u8 unused_4[2]; 7077 __le64 cq_handle; 7078 }; 7079 7080 /* hwrm_ring_alloc_output (size:128b/16B) */ 7081 struct hwrm_ring_alloc_output { 7082 __le16 error_code; 7083 __le16 req_type; 7084 __le16 seq_id; 7085 __le16 resp_len; 7086 __le16 ring_id; 7087 __le16 logical_ring_id; 7088 u8 push_buffer_index; 7089 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 7090 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 7091 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_LAST RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 7092 u8 unused_0[2]; 7093 u8 valid; 7094 }; 7095 7096 /* hwrm_ring_free_input (size:256b/32B) */ 7097 struct hwrm_ring_free_input { 7098 __le16 req_type; 7099 __le16 cmpl_ring; 7100 __le16 seq_id; 7101 __le16 target_id; 7102 __le64 resp_addr; 7103 u8 ring_type; 7104 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 7105 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 7106 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 7107 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 7108 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 7109 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 7110 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 7111 u8 flags; 7112 #define RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 0x1UL 7113 #define RING_FREE_REQ_FLAGS_LAST RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 7114 __le16 ring_id; 7115 __le32 prod_idx; 7116 __le32 opaque; 7117 __le32 unused_1; 7118 }; 7119 7120 /* hwrm_ring_free_output (size:128b/16B) */ 7121 struct hwrm_ring_free_output { 7122 __le16 error_code; 7123 __le16 req_type; 7124 __le16 seq_id; 7125 __le16 resp_len; 7126 u8 unused_0[7]; 7127 u8 valid; 7128 }; 7129 7130 /* hwrm_ring_reset_input (size:192b/24B) */ 7131 struct hwrm_ring_reset_input { 7132 __le16 req_type; 7133 __le16 cmpl_ring; 7134 __le16 seq_id; 7135 __le16 target_id; 7136 __le64 resp_addr; 7137 u8 ring_type; 7138 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 7139 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 7140 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 7141 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 7142 #define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL 7143 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_RX_RING_GRP 7144 u8 unused_0; 7145 __le16 ring_id; 7146 u8 unused_1[4]; 7147 }; 7148 7149 /* hwrm_ring_reset_output (size:128b/16B) */ 7150 struct hwrm_ring_reset_output { 7151 __le16 error_code; 7152 __le16 req_type; 7153 __le16 seq_id; 7154 __le16 resp_len; 7155 u8 push_buffer_index; 7156 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 7157 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 7158 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_LAST RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 7159 u8 unused_0[3]; 7160 u8 consumer_idx[3]; 7161 u8 valid; 7162 }; 7163 7164 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 7165 struct hwrm_ring_aggint_qcaps_input { 7166 __le16 req_type; 7167 __le16 cmpl_ring; 7168 __le16 seq_id; 7169 __le16 target_id; 7170 __le64 resp_addr; 7171 }; 7172 7173 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 7174 struct hwrm_ring_aggint_qcaps_output { 7175 __le16 error_code; 7176 __le16 req_type; 7177 __le16 seq_id; 7178 __le16 resp_len; 7179 __le32 cmpl_params; 7180 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 7181 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 7182 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 7183 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 7184 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 7185 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 7186 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 7187 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 7188 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 7189 __le32 nq_params; 7190 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 7191 __le16 num_cmpl_dma_aggr_min; 7192 __le16 num_cmpl_dma_aggr_max; 7193 __le16 num_cmpl_dma_aggr_during_int_min; 7194 __le16 num_cmpl_dma_aggr_during_int_max; 7195 __le16 cmpl_aggr_dma_tmr_min; 7196 __le16 cmpl_aggr_dma_tmr_max; 7197 __le16 cmpl_aggr_dma_tmr_during_int_min; 7198 __le16 cmpl_aggr_dma_tmr_during_int_max; 7199 __le16 int_lat_tmr_min_min; 7200 __le16 int_lat_tmr_min_max; 7201 __le16 int_lat_tmr_max_min; 7202 __le16 int_lat_tmr_max_max; 7203 __le16 num_cmpl_aggr_int_min; 7204 __le16 num_cmpl_aggr_int_max; 7205 __le16 timer_units; 7206 u8 unused_0[1]; 7207 u8 valid; 7208 }; 7209 7210 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 7211 struct hwrm_ring_cmpl_ring_qaggint_params_input { 7212 __le16 req_type; 7213 __le16 cmpl_ring; 7214 __le16 seq_id; 7215 __le16 target_id; 7216 __le64 resp_addr; 7217 __le16 ring_id; 7218 __le16 flags; 7219 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL 7220 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0 7221 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 7222 u8 unused_0[4]; 7223 }; 7224 7225 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 7226 struct hwrm_ring_cmpl_ring_qaggint_params_output { 7227 __le16 error_code; 7228 __le16 req_type; 7229 __le16 seq_id; 7230 __le16 resp_len; 7231 __le16 flags; 7232 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 7233 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 7234 __le16 num_cmpl_dma_aggr; 7235 __le16 num_cmpl_dma_aggr_during_int; 7236 __le16 cmpl_aggr_dma_tmr; 7237 __le16 cmpl_aggr_dma_tmr_during_int; 7238 __le16 int_lat_tmr_min; 7239 __le16 int_lat_tmr_max; 7240 __le16 num_cmpl_aggr_int; 7241 u8 unused_0[7]; 7242 u8 valid; 7243 }; 7244 7245 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 7246 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 7247 __le16 req_type; 7248 __le16 cmpl_ring; 7249 __le16 seq_id; 7250 __le16 target_id; 7251 __le64 resp_addr; 7252 __le16 ring_id; 7253 __le16 flags; 7254 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 7255 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 7256 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 7257 __le16 num_cmpl_dma_aggr; 7258 __le16 num_cmpl_dma_aggr_during_int; 7259 __le16 cmpl_aggr_dma_tmr; 7260 __le16 cmpl_aggr_dma_tmr_during_int; 7261 __le16 int_lat_tmr_min; 7262 __le16 int_lat_tmr_max; 7263 __le16 num_cmpl_aggr_int; 7264 __le16 enables; 7265 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 7266 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 7267 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 7268 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 7269 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 7270 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 7271 u8 unused_0[4]; 7272 }; 7273 7274 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 7275 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 7276 __le16 error_code; 7277 __le16 req_type; 7278 __le16 seq_id; 7279 __le16 resp_len; 7280 u8 unused_0[7]; 7281 u8 valid; 7282 }; 7283 7284 /* hwrm_ring_grp_alloc_input (size:192b/24B) */ 7285 struct hwrm_ring_grp_alloc_input { 7286 __le16 req_type; 7287 __le16 cmpl_ring; 7288 __le16 seq_id; 7289 __le16 target_id; 7290 __le64 resp_addr; 7291 __le16 cr; 7292 __le16 rr; 7293 __le16 ar; 7294 __le16 sc; 7295 }; 7296 7297 /* hwrm_ring_grp_alloc_output (size:128b/16B) */ 7298 struct hwrm_ring_grp_alloc_output { 7299 __le16 error_code; 7300 __le16 req_type; 7301 __le16 seq_id; 7302 __le16 resp_len; 7303 __le32 ring_group_id; 7304 u8 unused_0[3]; 7305 u8 valid; 7306 }; 7307 7308 /* hwrm_ring_grp_free_input (size:192b/24B) */ 7309 struct hwrm_ring_grp_free_input { 7310 __le16 req_type; 7311 __le16 cmpl_ring; 7312 __le16 seq_id; 7313 __le16 target_id; 7314 __le64 resp_addr; 7315 __le32 ring_group_id; 7316 u8 unused_0[4]; 7317 }; 7318 7319 /* hwrm_ring_grp_free_output (size:128b/16B) */ 7320 struct hwrm_ring_grp_free_output { 7321 __le16 error_code; 7322 __le16 req_type; 7323 __le16 seq_id; 7324 __le16 resp_len; 7325 u8 unused_0[7]; 7326 u8 valid; 7327 }; 7328 7329 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL 7330 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL 7331 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL 7332 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL 7333 7334 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 7335 struct hwrm_cfa_l2_filter_alloc_input { 7336 __le16 req_type; 7337 __le16 cmpl_ring; 7338 __le16 seq_id; 7339 __le16 target_id; 7340 __le64 resp_addr; 7341 __le32 flags; 7342 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 7343 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 7344 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 7345 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 7346 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 7347 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 7348 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 7349 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 7350 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 7351 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 7352 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 7353 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 7354 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 7355 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL 7356 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL 7357 __le32 enables; 7358 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 7359 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 7360 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 7361 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 7362 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 7363 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 7364 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 7365 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 7366 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 7367 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 7368 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 7369 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 7370 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 7371 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 7372 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 7373 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 7374 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 7375 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL 7376 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL 7377 u8 l2_addr[6]; 7378 u8 num_vlans; 7379 u8 t_num_vlans; 7380 u8 l2_addr_mask[6]; 7381 __le16 l2_ovlan; 7382 __le16 l2_ovlan_mask; 7383 __le16 l2_ivlan; 7384 __le16 l2_ivlan_mask; 7385 u8 unused_1[2]; 7386 u8 t_l2_addr[6]; 7387 u8 unused_2[2]; 7388 u8 t_l2_addr_mask[6]; 7389 __le16 t_l2_ovlan; 7390 __le16 t_l2_ovlan_mask; 7391 __le16 t_l2_ivlan; 7392 __le16 t_l2_ivlan_mask; 7393 u8 src_type; 7394 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 7395 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 7396 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 7397 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 7398 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 7399 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 7400 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 7401 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 7402 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 7403 u8 unused_3; 7404 __le32 src_id; 7405 u8 tunnel_type; 7406 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7407 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7408 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7409 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7410 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7411 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7412 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7413 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7414 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7415 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7416 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7417 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7418 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7419 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 7420 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7421 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7422 u8 unused_4; 7423 __le16 dst_id; 7424 __le16 mirror_vnic_id; 7425 u8 pri_hint; 7426 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 7427 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 7428 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 7429 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 7430 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 7431 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 7432 u8 unused_5; 7433 __le32 unused_6; 7434 __le64 l2_filter_id_hint; 7435 }; 7436 7437 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 7438 struct hwrm_cfa_l2_filter_alloc_output { 7439 __le16 error_code; 7440 __le16 req_type; 7441 __le16 seq_id; 7442 __le16 resp_len; 7443 __le64 l2_filter_id; 7444 __le32 flow_id; 7445 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7446 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7447 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7448 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7449 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7450 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 7451 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7452 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7453 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7454 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7455 u8 unused_0[3]; 7456 u8 valid; 7457 }; 7458 7459 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 7460 struct hwrm_cfa_l2_filter_free_input { 7461 __le16 req_type; 7462 __le16 cmpl_ring; 7463 __le16 seq_id; 7464 __le16 target_id; 7465 __le64 resp_addr; 7466 __le64 l2_filter_id; 7467 }; 7468 7469 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 7470 struct hwrm_cfa_l2_filter_free_output { 7471 __le16 error_code; 7472 __le16 req_type; 7473 __le16 seq_id; 7474 __le16 resp_len; 7475 u8 unused_0[7]; 7476 u8 valid; 7477 }; 7478 7479 /* hwrm_cfa_l2_filter_cfg_input (size:384b/48B) */ 7480 struct hwrm_cfa_l2_filter_cfg_input { 7481 __le16 req_type; 7482 __le16 cmpl_ring; 7483 __le16 seq_id; 7484 __le16 target_id; 7485 __le64 resp_addr; 7486 __le32 flags; 7487 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 7488 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 7489 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 7490 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 7491 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 7492 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 7493 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 7494 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 7495 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 7496 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 7497 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 7498 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_MASK 0x30UL 7499 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_SFT 4 7500 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_NO_UPDATE (0x0UL << 4) 7501 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_BYPASS_LKUP (0x1UL << 4) 7502 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_ENABLE_LKUP (0x2UL << 4) 7503 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_ENABLE_LKUP 7504 __le32 enables; 7505 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 7506 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 7507 #define CFA_L2_FILTER_CFG_REQ_ENABLES_PROF_FUNC 0x4UL 7508 #define CFA_L2_FILTER_CFG_REQ_ENABLES_L2_CONTEXT_ID 0x8UL 7509 __le64 l2_filter_id; 7510 __le32 dst_id; 7511 __le32 new_mirror_vnic_id; 7512 __le32 prof_func; 7513 __le32 l2_context_id; 7514 }; 7515 7516 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 7517 struct hwrm_cfa_l2_filter_cfg_output { 7518 __le16 error_code; 7519 __le16 req_type; 7520 __le16 seq_id; 7521 __le16 resp_len; 7522 u8 unused_0[7]; 7523 u8 valid; 7524 }; 7525 7526 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 7527 struct hwrm_cfa_l2_set_rx_mask_input { 7528 __le16 req_type; 7529 __le16 cmpl_ring; 7530 __le16 seq_id; 7531 __le16 target_id; 7532 __le64 resp_addr; 7533 __le32 vnic_id; 7534 __le32 mask; 7535 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 7536 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 7537 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 7538 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 7539 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 7540 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 7541 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 7542 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 7543 __le64 mc_tbl_addr; 7544 __le32 num_mc_entries; 7545 u8 unused_0[4]; 7546 __le64 vlan_tag_tbl_addr; 7547 __le32 num_vlan_tags; 7548 u8 unused_1[4]; 7549 }; 7550 7551 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 7552 struct hwrm_cfa_l2_set_rx_mask_output { 7553 __le16 error_code; 7554 __le16 req_type; 7555 __le16 seq_id; 7556 __le16 resp_len; 7557 u8 unused_0[7]; 7558 u8 valid; 7559 }; 7560 7561 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 7562 struct hwrm_cfa_l2_set_rx_mask_cmd_err { 7563 u8 code; 7564 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 7565 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 7566 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 7567 u8 unused_0[7]; 7568 }; 7569 7570 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 7571 struct hwrm_cfa_tunnel_filter_alloc_input { 7572 __le16 req_type; 7573 __le16 cmpl_ring; 7574 __le16 seq_id; 7575 __le16 target_id; 7576 __le64 resp_addr; 7577 __le32 flags; 7578 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7579 __le32 enables; 7580 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 7581 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 7582 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 7583 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 7584 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 7585 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 7586 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 7587 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 7588 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 7589 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 7590 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 7591 __le64 l2_filter_id; 7592 u8 l2_addr[6]; 7593 __le16 l2_ivlan; 7594 __le32 l3_addr[4]; 7595 __le32 t_l3_addr[4]; 7596 u8 l3_addr_type; 7597 u8 t_l3_addr_type; 7598 u8 tunnel_type; 7599 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7600 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7601 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7602 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7603 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7604 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7605 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7606 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7607 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7608 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7609 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7610 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7611 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7612 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 7613 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7614 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7615 u8 tunnel_flags; 7616 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 7617 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 7618 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 7619 __le32 vni; 7620 __le32 dst_vnic_id; 7621 __le32 mirror_vnic_id; 7622 }; 7623 7624 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 7625 struct hwrm_cfa_tunnel_filter_alloc_output { 7626 __le16 error_code; 7627 __le16 req_type; 7628 __le16 seq_id; 7629 __le16 resp_len; 7630 __le64 tunnel_filter_id; 7631 __le32 flow_id; 7632 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7633 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7634 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7635 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7636 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7637 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 7638 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7639 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7640 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7641 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7642 u8 unused_0[3]; 7643 u8 valid; 7644 }; 7645 7646 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 7647 struct hwrm_cfa_tunnel_filter_free_input { 7648 __le16 req_type; 7649 __le16 cmpl_ring; 7650 __le16 seq_id; 7651 __le16 target_id; 7652 __le64 resp_addr; 7653 __le64 tunnel_filter_id; 7654 }; 7655 7656 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 7657 struct hwrm_cfa_tunnel_filter_free_output { 7658 __le16 error_code; 7659 __le16 req_type; 7660 __le16 seq_id; 7661 __le16 resp_len; 7662 u8 unused_0[7]; 7663 u8 valid; 7664 }; 7665 7666 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 7667 struct hwrm_vxlan_ipv4_hdr { 7668 u8 ver_hlen; 7669 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 7670 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 7671 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 7672 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 7673 u8 tos; 7674 __be16 ip_id; 7675 __be16 flags_frag_offset; 7676 u8 ttl; 7677 u8 protocol; 7678 __be32 src_ip_addr; 7679 __be32 dest_ip_addr; 7680 }; 7681 7682 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 7683 struct hwrm_vxlan_ipv6_hdr { 7684 __be32 ver_tc_flow_label; 7685 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 7686 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 7687 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 7688 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 7689 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 7690 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 7691 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 7692 __be16 payload_len; 7693 u8 next_hdr; 7694 u8 ttl; 7695 __be32 src_ip_addr[4]; 7696 __be32 dest_ip_addr[4]; 7697 }; 7698 7699 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 7700 struct hwrm_cfa_encap_data_vxlan { 7701 u8 src_mac_addr[6]; 7702 __le16 unused_0; 7703 u8 dst_mac_addr[6]; 7704 u8 num_vlan_tags; 7705 u8 unused_1; 7706 __be16 ovlan_tpid; 7707 __be16 ovlan_tci; 7708 __be16 ivlan_tpid; 7709 __be16 ivlan_tci; 7710 __le32 l3[10]; 7711 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 7712 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 7713 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 7714 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 7715 __be16 src_port; 7716 __be16 dst_port; 7717 __be32 vni; 7718 u8 hdr_rsvd0[3]; 7719 u8 hdr_rsvd1; 7720 u8 hdr_flags; 7721 u8 unused[3]; 7722 }; 7723 7724 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 7725 struct hwrm_cfa_encap_record_alloc_input { 7726 __le16 req_type; 7727 __le16 cmpl_ring; 7728 __le16 seq_id; 7729 __le16 target_id; 7730 __le64 resp_addr; 7731 __le32 flags; 7732 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7733 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL 7734 u8 encap_type; 7735 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 7736 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 7737 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 7738 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 7739 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 7740 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 7741 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 7742 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 7743 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 7744 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 7745 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 7746 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL 7747 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE 0x10UL 7748 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE 7749 u8 unused_0[3]; 7750 __le32 encap_data[20]; 7751 }; 7752 7753 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 7754 struct hwrm_cfa_encap_record_alloc_output { 7755 __le16 error_code; 7756 __le16 req_type; 7757 __le16 seq_id; 7758 __le16 resp_len; 7759 __le32 encap_record_id; 7760 u8 unused_0[3]; 7761 u8 valid; 7762 }; 7763 7764 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 7765 struct hwrm_cfa_encap_record_free_input { 7766 __le16 req_type; 7767 __le16 cmpl_ring; 7768 __le16 seq_id; 7769 __le16 target_id; 7770 __le64 resp_addr; 7771 __le32 encap_record_id; 7772 u8 unused_0[4]; 7773 }; 7774 7775 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 7776 struct hwrm_cfa_encap_record_free_output { 7777 __le16 error_code; 7778 __le16 req_type; 7779 __le16 seq_id; 7780 __le16 resp_len; 7781 u8 unused_0[7]; 7782 u8 valid; 7783 }; 7784 7785 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 7786 struct hwrm_cfa_ntuple_filter_alloc_input { 7787 __le16 req_type; 7788 __le16 cmpl_ring; 7789 __le16 seq_id; 7790 __le16 target_id; 7791 __le64 resp_addr; 7792 __le32 flags; 7793 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7794 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 7795 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 7796 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL 7797 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL 7798 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL 7799 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_NO_L2_CONTEXT 0x40UL 7800 __le32 enables; 7801 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 7802 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 7803 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 7804 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 7805 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 7806 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 7807 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 7808 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 7809 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 7810 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 7811 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 7812 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 7813 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 7814 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 7815 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 7816 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 7817 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 7818 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 7819 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 7820 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL 7821 __le64 l2_filter_id; 7822 u8 src_macaddr[6]; 7823 __be16 ethertype; 7824 u8 ip_addr_type; 7825 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 7826 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 7827 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 7828 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 7829 u8 ip_protocol; 7830 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 7831 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 7832 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 7833 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_ICMP 0x1UL 7834 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_ICMPV6 0x3aUL 7835 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD 0xffUL 7836 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD 7837 __le16 dst_id; 7838 __le16 rfs_ring_tbl_idx; 7839 u8 tunnel_type; 7840 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7841 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7842 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7843 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7844 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7845 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7846 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7847 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7848 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7849 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7850 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7851 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7852 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7853 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 7854 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7855 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7856 u8 pri_hint; 7857 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 7858 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 7859 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 7860 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 7861 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 7862 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 7863 __be32 src_ipaddr[4]; 7864 __be32 src_ipaddr_mask[4]; 7865 __be32 dst_ipaddr[4]; 7866 __be32 dst_ipaddr_mask[4]; 7867 __be16 src_port; 7868 __be16 src_port_mask; 7869 __be16 dst_port; 7870 __be16 dst_port_mask; 7871 __le64 ntuple_filter_id_hint; 7872 }; 7873 7874 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 7875 struct hwrm_cfa_ntuple_filter_alloc_output { 7876 __le16 error_code; 7877 __le16 req_type; 7878 __le16 seq_id; 7879 __le16 resp_len; 7880 __le64 ntuple_filter_id; 7881 __le32 flow_id; 7882 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7883 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7884 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7885 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7886 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7887 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 7888 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7889 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7890 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7891 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7892 u8 unused_0[3]; 7893 u8 valid; 7894 }; 7895 7896 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 7897 struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 7898 u8 code; 7899 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 7900 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 7901 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 7902 u8 unused_0[7]; 7903 }; 7904 7905 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 7906 struct hwrm_cfa_ntuple_filter_free_input { 7907 __le16 req_type; 7908 __le16 cmpl_ring; 7909 __le16 seq_id; 7910 __le16 target_id; 7911 __le64 resp_addr; 7912 __le64 ntuple_filter_id; 7913 }; 7914 7915 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 7916 struct hwrm_cfa_ntuple_filter_free_output { 7917 __le16 error_code; 7918 __le16 req_type; 7919 __le16 seq_id; 7920 __le16 resp_len; 7921 u8 unused_0[7]; 7922 u8 valid; 7923 }; 7924 7925 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 7926 struct hwrm_cfa_ntuple_filter_cfg_input { 7927 __le16 req_type; 7928 __le16 cmpl_ring; 7929 __le16 seq_id; 7930 __le16 target_id; 7931 __le64 resp_addr; 7932 __le32 enables; 7933 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 7934 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 7935 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 7936 __le32 flags; 7937 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL 7938 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL 7939 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_NO_L2_CONTEXT 0x4UL 7940 __le64 ntuple_filter_id; 7941 __le32 new_dst_id; 7942 __le32 new_mirror_vnic_id; 7943 __le16 new_meter_instance_id; 7944 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 7945 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 7946 u8 unused_1[6]; 7947 }; 7948 7949 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 7950 struct hwrm_cfa_ntuple_filter_cfg_output { 7951 __le16 error_code; 7952 __le16 req_type; 7953 __le16 seq_id; 7954 __le16 resp_len; 7955 u8 unused_0[7]; 7956 u8 valid; 7957 }; 7958 7959 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 7960 struct hwrm_cfa_decap_filter_alloc_input { 7961 __le16 req_type; 7962 __le16 cmpl_ring; 7963 __le16 seq_id; 7964 __le16 target_id; 7965 __le64 resp_addr; 7966 __le32 flags; 7967 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 7968 __le32 enables; 7969 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 7970 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 7971 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 7972 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 7973 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 7974 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 7975 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 7976 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 7977 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 7978 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 7979 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 7980 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 7981 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 7982 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 7983 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 7984 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 7985 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 7986 __be32 tunnel_id; 7987 u8 tunnel_type; 7988 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7989 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7990 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7991 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7992 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7993 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7994 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7995 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7996 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7997 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7998 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7999 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8000 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8001 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8002 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 8003 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 8004 u8 unused_0; 8005 __le16 unused_1; 8006 u8 src_macaddr[6]; 8007 u8 unused_2[2]; 8008 u8 dst_macaddr[6]; 8009 __be16 ovlan_vid; 8010 __be16 ivlan_vid; 8011 __be16 t_ovlan_vid; 8012 __be16 t_ivlan_vid; 8013 __be16 ethertype; 8014 u8 ip_addr_type; 8015 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 8016 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 8017 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 8018 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 8019 u8 ip_protocol; 8020 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 8021 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 8022 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 8023 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 8024 __le16 unused_3; 8025 __le32 unused_4; 8026 __be32 src_ipaddr[4]; 8027 __be32 dst_ipaddr[4]; 8028 __be16 src_port; 8029 __be16 dst_port; 8030 __le16 dst_id; 8031 __le16 l2_ctxt_ref_id; 8032 }; 8033 8034 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 8035 struct hwrm_cfa_decap_filter_alloc_output { 8036 __le16 error_code; 8037 __le16 req_type; 8038 __le16 seq_id; 8039 __le16 resp_len; 8040 __le32 decap_filter_id; 8041 u8 unused_0[3]; 8042 u8 valid; 8043 }; 8044 8045 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 8046 struct hwrm_cfa_decap_filter_free_input { 8047 __le16 req_type; 8048 __le16 cmpl_ring; 8049 __le16 seq_id; 8050 __le16 target_id; 8051 __le64 resp_addr; 8052 __le32 decap_filter_id; 8053 u8 unused_0[4]; 8054 }; 8055 8056 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 8057 struct hwrm_cfa_decap_filter_free_output { 8058 __le16 error_code; 8059 __le16 req_type; 8060 __le16 seq_id; 8061 __le16 resp_len; 8062 u8 unused_0[7]; 8063 u8 valid; 8064 }; 8065 8066 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 8067 struct hwrm_cfa_flow_alloc_input { 8068 __le16 req_type; 8069 __le16 cmpl_ring; 8070 __le16 seq_id; 8071 __le16 target_id; 8072 __le64 resp_addr; 8073 __le16 flags; 8074 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 8075 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 8076 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 8077 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 8078 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 8079 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 8080 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 8081 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 8082 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 8083 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 8084 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 8085 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 8086 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 8087 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 8088 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 8089 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 8090 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL 8091 __le16 src_fid; 8092 __le32 tunnel_handle; 8093 __le16 action_flags; 8094 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 8095 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 8096 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 8097 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 8098 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 8099 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 8100 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 8101 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 8102 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 8103 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 8104 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 8105 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL 8106 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL 8107 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL 8108 __le16 dst_fid; 8109 __be16 l2_rewrite_vlan_tpid; 8110 __be16 l2_rewrite_vlan_tci; 8111 __le16 act_meter_id; 8112 __le16 ref_flow_handle; 8113 __be16 ethertype; 8114 __be16 outer_vlan_tci; 8115 __be16 dmac[3]; 8116 __be16 inner_vlan_tci; 8117 __be16 smac[3]; 8118 u8 ip_dst_mask_len; 8119 u8 ip_src_mask_len; 8120 __be32 ip_dst[4]; 8121 __be32 ip_src[4]; 8122 __be16 l4_src_port; 8123 __be16 l4_src_port_mask; 8124 __be16 l4_dst_port; 8125 __be16 l4_dst_port_mask; 8126 __be32 nat_ip_address[4]; 8127 __be16 l2_rewrite_dmac[3]; 8128 __be16 nat_port; 8129 __be16 l2_rewrite_smac[3]; 8130 u8 ip_proto; 8131 u8 tunnel_type; 8132 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 8133 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8134 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 8135 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 8136 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 8137 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8138 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 8139 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 8140 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 8141 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8142 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8143 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8144 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8145 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8146 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 8147 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 8148 }; 8149 8150 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 8151 struct hwrm_cfa_flow_alloc_output { 8152 __le16 error_code; 8153 __le16 req_type; 8154 __le16 seq_id; 8155 __le16 resp_len; 8156 __le16 flow_handle; 8157 u8 unused_0[2]; 8158 __le32 flow_id; 8159 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 8160 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 8161 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 8162 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 8163 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 8164 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT 8165 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 8166 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 8167 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 8168 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX 8169 __le64 ext_flow_handle; 8170 __le32 flow_counter_id; 8171 u8 unused_1[3]; 8172 u8 valid; 8173 }; 8174 8175 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ 8176 struct hwrm_cfa_flow_alloc_cmd_err { 8177 u8 code; 8178 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 8179 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL 8180 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL 8181 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL 8182 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL 8183 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL 8184 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL 8185 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL 8186 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 8187 u8 unused_0[7]; 8188 }; 8189 8190 /* hwrm_cfa_flow_free_input (size:256b/32B) */ 8191 struct hwrm_cfa_flow_free_input { 8192 __le16 req_type; 8193 __le16 cmpl_ring; 8194 __le16 seq_id; 8195 __le16 target_id; 8196 __le64 resp_addr; 8197 __le16 flow_handle; 8198 __le16 unused_0; 8199 __le32 flow_counter_id; 8200 __le64 ext_flow_handle; 8201 }; 8202 8203 /* hwrm_cfa_flow_free_output (size:256b/32B) */ 8204 struct hwrm_cfa_flow_free_output { 8205 __le16 error_code; 8206 __le16 req_type; 8207 __le16 seq_id; 8208 __le16 resp_len; 8209 __le64 packet; 8210 __le64 byte; 8211 u8 unused_0[7]; 8212 u8 valid; 8213 }; 8214 8215 /* hwrm_cfa_flow_info_input (size:256b/32B) */ 8216 struct hwrm_cfa_flow_info_input { 8217 __le16 req_type; 8218 __le16 cmpl_ring; 8219 __le16 seq_id; 8220 __le16 target_id; 8221 __le64 resp_addr; 8222 __le16 flow_handle; 8223 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL 8224 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL 8225 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL 8226 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_TX 0x3000UL 8227 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL 8228 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL 8229 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT_RX 0x9000UL 8230 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT_RX 0xa000UL 8231 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_RX 0xb000UL 8232 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX 0xc000UL 8233 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_LAST CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX 8234 u8 unused_0[6]; 8235 __le64 ext_flow_handle; 8236 }; 8237 8238 /* hwrm_cfa_flow_info_output (size:5632b/704B) */ 8239 struct hwrm_cfa_flow_info_output { 8240 __le16 error_code; 8241 __le16 req_type; 8242 __le16 seq_id; 8243 __le16 resp_len; 8244 u8 flags; 8245 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL 8246 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL 8247 u8 profile; 8248 __le16 src_fid; 8249 __le16 dst_fid; 8250 __le16 l2_ctxt_id; 8251 __le64 em_info; 8252 __le64 tcam_info; 8253 __le64 vfp_tcam_info; 8254 __le16 ar_id; 8255 __le16 flow_handle; 8256 __le32 tunnel_handle; 8257 __le16 flow_timer; 8258 u8 unused_0[6]; 8259 __le32 flow_key_data[130]; 8260 __le32 flow_action_info[30]; 8261 u8 unused_1[7]; 8262 u8 valid; 8263 }; 8264 8265 /* hwrm_cfa_flow_stats_input (size:640b/80B) */ 8266 struct hwrm_cfa_flow_stats_input { 8267 __le16 req_type; 8268 __le16 cmpl_ring; 8269 __le16 seq_id; 8270 __le16 target_id; 8271 __le64 resp_addr; 8272 __le16 num_flows; 8273 __le16 flow_handle_0; 8274 __le16 flow_handle_1; 8275 __le16 flow_handle_2; 8276 __le16 flow_handle_3; 8277 __le16 flow_handle_4; 8278 __le16 flow_handle_5; 8279 __le16 flow_handle_6; 8280 __le16 flow_handle_7; 8281 __le16 flow_handle_8; 8282 __le16 flow_handle_9; 8283 u8 unused_0[2]; 8284 __le32 flow_id_0; 8285 __le32 flow_id_1; 8286 __le32 flow_id_2; 8287 __le32 flow_id_3; 8288 __le32 flow_id_4; 8289 __le32 flow_id_5; 8290 __le32 flow_id_6; 8291 __le32 flow_id_7; 8292 __le32 flow_id_8; 8293 __le32 flow_id_9; 8294 }; 8295 8296 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 8297 struct hwrm_cfa_flow_stats_output { 8298 __le16 error_code; 8299 __le16 req_type; 8300 __le16 seq_id; 8301 __le16 resp_len; 8302 __le64 packet_0; 8303 __le64 packet_1; 8304 __le64 packet_2; 8305 __le64 packet_3; 8306 __le64 packet_4; 8307 __le64 packet_5; 8308 __le64 packet_6; 8309 __le64 packet_7; 8310 __le64 packet_8; 8311 __le64 packet_9; 8312 __le64 byte_0; 8313 __le64 byte_1; 8314 __le64 byte_2; 8315 __le64 byte_3; 8316 __le64 byte_4; 8317 __le64 byte_5; 8318 __le64 byte_6; 8319 __le64 byte_7; 8320 __le64 byte_8; 8321 __le64 byte_9; 8322 __le16 flow_hits; 8323 u8 unused_0[5]; 8324 u8 valid; 8325 }; 8326 8327 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 8328 struct hwrm_cfa_vfr_alloc_input { 8329 __le16 req_type; 8330 __le16 cmpl_ring; 8331 __le16 seq_id; 8332 __le16 target_id; 8333 __le64 resp_addr; 8334 __le16 vf_id; 8335 __le16 reserved; 8336 u8 unused_0[4]; 8337 char vfr_name[32]; 8338 }; 8339 8340 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 8341 struct hwrm_cfa_vfr_alloc_output { 8342 __le16 error_code; 8343 __le16 req_type; 8344 __le16 seq_id; 8345 __le16 resp_len; 8346 __le16 rx_cfa_code; 8347 __le16 tx_cfa_action; 8348 u8 unused_0[3]; 8349 u8 valid; 8350 }; 8351 8352 /* hwrm_cfa_vfr_free_input (size:448b/56B) */ 8353 struct hwrm_cfa_vfr_free_input { 8354 __le16 req_type; 8355 __le16 cmpl_ring; 8356 __le16 seq_id; 8357 __le16 target_id; 8358 __le64 resp_addr; 8359 char vfr_name[32]; 8360 __le16 vf_id; 8361 __le16 reserved; 8362 u8 unused_0[4]; 8363 }; 8364 8365 /* hwrm_cfa_vfr_free_output (size:128b/16B) */ 8366 struct hwrm_cfa_vfr_free_output { 8367 __le16 error_code; 8368 __le16 req_type; 8369 __le16 seq_id; 8370 __le16 resp_len; 8371 u8 unused_0[7]; 8372 u8 valid; 8373 }; 8374 8375 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ 8376 struct hwrm_cfa_eem_qcaps_input { 8377 __le16 req_type; 8378 __le16 cmpl_ring; 8379 __le16 seq_id; 8380 __le16 target_id; 8381 __le64 resp_addr; 8382 __le32 flags; 8383 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL 8384 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL 8385 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 8386 __le32 unused_0; 8387 }; 8388 8389 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ 8390 struct hwrm_cfa_eem_qcaps_output { 8391 __le16 error_code; 8392 __le16 req_type; 8393 __le16 seq_id; 8394 __le16 resp_len; 8395 __le32 flags; 8396 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL 8397 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL 8398 #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL 8399 #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL 8400 __le32 unused_0; 8401 __le32 supported; 8402 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL 8403 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL 8404 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL 8405 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL 8406 #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL 8407 __le32 max_entries_supported; 8408 __le16 key_entry_size; 8409 __le16 record_entry_size; 8410 __le16 efc_entry_size; 8411 __le16 fid_entry_size; 8412 u8 unused_1[7]; 8413 u8 valid; 8414 }; 8415 8416 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */ 8417 struct hwrm_cfa_eem_cfg_input { 8418 __le16 req_type; 8419 __le16 cmpl_ring; 8420 __le16 seq_id; 8421 __le16 target_id; 8422 __le64 resp_addr; 8423 __le32 flags; 8424 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL 8425 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL 8426 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 8427 #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL 8428 __le16 group_id; 8429 __le16 unused_0; 8430 __le32 num_entries; 8431 __le32 unused_1; 8432 __le16 key0_ctx_id; 8433 __le16 key1_ctx_id; 8434 __le16 record_ctx_id; 8435 __le16 efc_ctx_id; 8436 __le16 fid_ctx_id; 8437 __le16 unused_2; 8438 __le32 unused_3; 8439 }; 8440 8441 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */ 8442 struct hwrm_cfa_eem_cfg_output { 8443 __le16 error_code; 8444 __le16 req_type; 8445 __le16 seq_id; 8446 __le16 resp_len; 8447 u8 unused_0[7]; 8448 u8 valid; 8449 }; 8450 8451 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ 8452 struct hwrm_cfa_eem_qcfg_input { 8453 __le16 req_type; 8454 __le16 cmpl_ring; 8455 __le16 seq_id; 8456 __le16 target_id; 8457 __le64 resp_addr; 8458 __le32 flags; 8459 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL 8460 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL 8461 __le32 unused_0; 8462 }; 8463 8464 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ 8465 struct hwrm_cfa_eem_qcfg_output { 8466 __le16 error_code; 8467 __le16 req_type; 8468 __le16 seq_id; 8469 __le16 resp_len; 8470 __le32 flags; 8471 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL 8472 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL 8473 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL 8474 __le32 num_entries; 8475 __le16 key0_ctx_id; 8476 __le16 key1_ctx_id; 8477 __le16 record_ctx_id; 8478 __le16 efc_ctx_id; 8479 __le16 fid_ctx_id; 8480 u8 unused_2[5]; 8481 u8 valid; 8482 }; 8483 8484 /* hwrm_cfa_eem_op_input (size:192b/24B) */ 8485 struct hwrm_cfa_eem_op_input { 8486 __le16 req_type; 8487 __le16 cmpl_ring; 8488 __le16 seq_id; 8489 __le16 target_id; 8490 __le64 resp_addr; 8491 __le32 flags; 8492 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL 8493 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL 8494 __le16 unused_0; 8495 __le16 op; 8496 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL 8497 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL 8498 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL 8499 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL 8500 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP 8501 }; 8502 8503 /* hwrm_cfa_eem_op_output (size:128b/16B) */ 8504 struct hwrm_cfa_eem_op_output { 8505 __le16 error_code; 8506 __le16 req_type; 8507 __le16 seq_id; 8508 __le16 resp_len; 8509 u8 unused_0[7]; 8510 u8 valid; 8511 }; 8512 8513 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ 8514 struct hwrm_cfa_adv_flow_mgnt_qcaps_input { 8515 __le16 req_type; 8516 __le16 cmpl_ring; 8517 __le16 seq_id; 8518 __le16 target_id; 8519 __le64 resp_addr; 8520 __le32 unused_0[4]; 8521 }; 8522 8523 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ 8524 struct hwrm_cfa_adv_flow_mgnt_qcaps_output { 8525 __le16 error_code; 8526 __le16 req_type; 8527 __le16 seq_id; 8528 __le16 resp_len; 8529 __le32 flags; 8530 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL 8531 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL 8532 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL 8533 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL 8534 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL 8535 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL 8536 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL 8537 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL 8538 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL 8539 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL 8540 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL 8541 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL 8542 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL 8543 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL 8544 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL 8545 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TRUFLOW_CAPABLE 0x8000UL 8546 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED 0x10000UL 8547 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_LAG_SUPPORTED 0x20000UL 8548 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED 0x40000UL 8549 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NIC_FLOW_STATS_SUPPORTED 0x80000UL 8550 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED 0x100000UL 8551 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V3_SUPPORTED 0x200000UL 8552 u8 unused_0[3]; 8553 u8 valid; 8554 }; 8555 8556 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 8557 struct hwrm_tunnel_dst_port_query_input { 8558 __le16 req_type; 8559 __le16 cmpl_ring; 8560 __le16 seq_id; 8561 __le16 target_id; 8562 __le64 resp_addr; 8563 u8 tunnel_type; 8564 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8565 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8566 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8567 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8568 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8569 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8570 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL 8571 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ECPRI 0xeUL 8572 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_SRV6 0xfUL 8573 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8574 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GRE 0x11UL 8575 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR 0x12UL 8576 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 0x13UL 8577 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 0x14UL 8578 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 0x15UL 8579 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 0x16UL 8580 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 0x17UL 8581 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 0x18UL 8582 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 0x19UL 8583 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 8584 u8 tunnel_next_proto; 8585 u8 unused_0[6]; 8586 }; 8587 8588 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 8589 struct hwrm_tunnel_dst_port_query_output { 8590 __le16 error_code; 8591 __le16 req_type; 8592 __le16 seq_id; 8593 __le16 resp_len; 8594 __le16 tunnel_dst_port_id; 8595 __be16 tunnel_dst_port_val; 8596 u8 upar_in_use; 8597 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR0 0x1UL 8598 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR1 0x2UL 8599 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR2 0x4UL 8600 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR3 0x8UL 8601 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR4 0x10UL 8602 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR5 0x20UL 8603 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR6 0x40UL 8604 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR7 0x80UL 8605 u8 status; 8606 #define TUNNEL_DST_PORT_QUERY_RESP_STATUS_CHIP_LEVEL 0x1UL 8607 #define TUNNEL_DST_PORT_QUERY_RESP_STATUS_FUNC_LEVEL 0x2UL 8608 u8 unused_0; 8609 u8 valid; 8610 }; 8611 8612 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 8613 struct hwrm_tunnel_dst_port_alloc_input { 8614 __le16 req_type; 8615 __le16 cmpl_ring; 8616 __le16 seq_id; 8617 __le16 target_id; 8618 __le64 resp_addr; 8619 u8 tunnel_type; 8620 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8621 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8622 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8623 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8624 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8625 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8626 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL 8627 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ECPRI 0xeUL 8628 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_SRV6 0xfUL 8629 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8630 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GRE 0x11UL 8631 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR 0x12UL 8632 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 0x13UL 8633 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 0x14UL 8634 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 0x15UL 8635 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 0x16UL 8636 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 0x17UL 8637 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 0x18UL 8638 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 0x19UL 8639 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 8640 u8 tunnel_next_proto; 8641 __be16 tunnel_dst_port_val; 8642 u8 unused_0[4]; 8643 }; 8644 8645 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 8646 struct hwrm_tunnel_dst_port_alloc_output { 8647 __le16 error_code; 8648 __le16 req_type; 8649 __le16 seq_id; 8650 __le16 resp_len; 8651 __le16 tunnel_dst_port_id; 8652 u8 error_info; 8653 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_SUCCESS 0x0UL 8654 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ALLOCATED 0x1UL 8655 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_NO_RESOURCE 0x2UL 8656 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ENABLED 0x3UL 8657 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_LAST TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ENABLED 8658 u8 upar_in_use; 8659 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR0 0x1UL 8660 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR1 0x2UL 8661 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR2 0x4UL 8662 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR3 0x8UL 8663 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR4 0x10UL 8664 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR5 0x20UL 8665 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR6 0x40UL 8666 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR7 0x80UL 8667 u8 unused_0[3]; 8668 u8 valid; 8669 }; 8670 8671 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 8672 struct hwrm_tunnel_dst_port_free_input { 8673 __le16 req_type; 8674 __le16 cmpl_ring; 8675 __le16 seq_id; 8676 __le16 target_id; 8677 __le64 resp_addr; 8678 u8 tunnel_type; 8679 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8680 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8681 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8682 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8683 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8684 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8685 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL 8686 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ECPRI 0xeUL 8687 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_SRV6 0xfUL 8688 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8689 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GRE 0x11UL 8690 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR 0x12UL 8691 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 0x13UL 8692 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 0x14UL 8693 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 0x15UL 8694 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 0x16UL 8695 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 0x17UL 8696 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 0x18UL 8697 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 0x19UL 8698 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 8699 u8 tunnel_next_proto; 8700 __le16 tunnel_dst_port_id; 8701 u8 unused_0[4]; 8702 }; 8703 8704 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 8705 struct hwrm_tunnel_dst_port_free_output { 8706 __le16 error_code; 8707 __le16 req_type; 8708 __le16 seq_id; 8709 __le16 resp_len; 8710 u8 error_info; 8711 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_SUCCESS 0x0UL 8712 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_OWNER 0x1UL 8713 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED 0x2UL 8714 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_LAST TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED 8715 u8 unused_1[6]; 8716 u8 valid; 8717 }; 8718 8719 /* ctx_hw_stats (size:1280b/160B) */ 8720 struct ctx_hw_stats { 8721 __le64 rx_ucast_pkts; 8722 __le64 rx_mcast_pkts; 8723 __le64 rx_bcast_pkts; 8724 __le64 rx_discard_pkts; 8725 __le64 rx_error_pkts; 8726 __le64 rx_ucast_bytes; 8727 __le64 rx_mcast_bytes; 8728 __le64 rx_bcast_bytes; 8729 __le64 tx_ucast_pkts; 8730 __le64 tx_mcast_pkts; 8731 __le64 tx_bcast_pkts; 8732 __le64 tx_error_pkts; 8733 __le64 tx_discard_pkts; 8734 __le64 tx_ucast_bytes; 8735 __le64 tx_mcast_bytes; 8736 __le64 tx_bcast_bytes; 8737 __le64 tpa_pkts; 8738 __le64 tpa_bytes; 8739 __le64 tpa_events; 8740 __le64 tpa_aborts; 8741 }; 8742 8743 /* ctx_hw_stats_ext (size:1408b/176B) */ 8744 struct ctx_hw_stats_ext { 8745 __le64 rx_ucast_pkts; 8746 __le64 rx_mcast_pkts; 8747 __le64 rx_bcast_pkts; 8748 __le64 rx_discard_pkts; 8749 __le64 rx_error_pkts; 8750 __le64 rx_ucast_bytes; 8751 __le64 rx_mcast_bytes; 8752 __le64 rx_bcast_bytes; 8753 __le64 tx_ucast_pkts; 8754 __le64 tx_mcast_pkts; 8755 __le64 tx_bcast_pkts; 8756 __le64 tx_error_pkts; 8757 __le64 tx_discard_pkts; 8758 __le64 tx_ucast_bytes; 8759 __le64 tx_mcast_bytes; 8760 __le64 tx_bcast_bytes; 8761 __le64 rx_tpa_eligible_pkt; 8762 __le64 rx_tpa_eligible_bytes; 8763 __le64 rx_tpa_pkt; 8764 __le64 rx_tpa_bytes; 8765 __le64 rx_tpa_errors; 8766 __le64 rx_tpa_events; 8767 }; 8768 8769 /* hwrm_stat_ctx_alloc_input (size:320b/40B) */ 8770 struct hwrm_stat_ctx_alloc_input { 8771 __le16 req_type; 8772 __le16 cmpl_ring; 8773 __le16 seq_id; 8774 __le16 target_id; 8775 __le64 resp_addr; 8776 __le64 stats_dma_addr; 8777 __le32 update_period_ms; 8778 u8 stat_ctx_flags; 8779 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 8780 u8 unused_0; 8781 __le16 stats_dma_length; 8782 __le16 flags; 8783 #define STAT_CTX_ALLOC_REQ_FLAGS_STEERING_TAG_VALID 0x1UL 8784 __le16 steering_tag; 8785 __le32 unused_1; 8786 }; 8787 8788 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 8789 struct hwrm_stat_ctx_alloc_output { 8790 __le16 error_code; 8791 __le16 req_type; 8792 __le16 seq_id; 8793 __le16 resp_len; 8794 __le32 stat_ctx_id; 8795 u8 unused_0[3]; 8796 u8 valid; 8797 }; 8798 8799 /* hwrm_stat_ctx_free_input (size:192b/24B) */ 8800 struct hwrm_stat_ctx_free_input { 8801 __le16 req_type; 8802 __le16 cmpl_ring; 8803 __le16 seq_id; 8804 __le16 target_id; 8805 __le64 resp_addr; 8806 __le32 stat_ctx_id; 8807 u8 unused_0[4]; 8808 }; 8809 8810 /* hwrm_stat_ctx_free_output (size:128b/16B) */ 8811 struct hwrm_stat_ctx_free_output { 8812 __le16 error_code; 8813 __le16 req_type; 8814 __le16 seq_id; 8815 __le16 resp_len; 8816 __le32 stat_ctx_id; 8817 u8 unused_0[3]; 8818 u8 valid; 8819 }; 8820 8821 /* hwrm_stat_ctx_query_input (size:192b/24B) */ 8822 struct hwrm_stat_ctx_query_input { 8823 __le16 req_type; 8824 __le16 cmpl_ring; 8825 __le16 seq_id; 8826 __le16 target_id; 8827 __le64 resp_addr; 8828 __le32 stat_ctx_id; 8829 u8 flags; 8830 #define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 8831 u8 unused_0[3]; 8832 }; 8833 8834 /* hwrm_stat_ctx_query_output (size:1408b/176B) */ 8835 struct hwrm_stat_ctx_query_output { 8836 __le16 error_code; 8837 __le16 req_type; 8838 __le16 seq_id; 8839 __le16 resp_len; 8840 __le64 tx_ucast_pkts; 8841 __le64 tx_mcast_pkts; 8842 __le64 tx_bcast_pkts; 8843 __le64 tx_discard_pkts; 8844 __le64 tx_error_pkts; 8845 __le64 tx_ucast_bytes; 8846 __le64 tx_mcast_bytes; 8847 __le64 tx_bcast_bytes; 8848 __le64 rx_ucast_pkts; 8849 __le64 rx_mcast_pkts; 8850 __le64 rx_bcast_pkts; 8851 __le64 rx_discard_pkts; 8852 __le64 rx_error_pkts; 8853 __le64 rx_ucast_bytes; 8854 __le64 rx_mcast_bytes; 8855 __le64 rx_bcast_bytes; 8856 __le64 rx_agg_pkts; 8857 __le64 rx_agg_bytes; 8858 __le64 rx_agg_events; 8859 __le64 rx_agg_aborts; 8860 u8 unused_0[7]; 8861 u8 valid; 8862 }; 8863 8864 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ 8865 struct hwrm_stat_ext_ctx_query_input { 8866 __le16 req_type; 8867 __le16 cmpl_ring; 8868 __le16 seq_id; 8869 __le16 target_id; 8870 __le64 resp_addr; 8871 __le32 stat_ctx_id; 8872 u8 flags; 8873 #define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 8874 u8 unused_0[3]; 8875 }; 8876 8877 /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */ 8878 struct hwrm_stat_ext_ctx_query_output { 8879 __le16 error_code; 8880 __le16 req_type; 8881 __le16 seq_id; 8882 __le16 resp_len; 8883 __le64 rx_ucast_pkts; 8884 __le64 rx_mcast_pkts; 8885 __le64 rx_bcast_pkts; 8886 __le64 rx_discard_pkts; 8887 __le64 rx_error_pkts; 8888 __le64 rx_ucast_bytes; 8889 __le64 rx_mcast_bytes; 8890 __le64 rx_bcast_bytes; 8891 __le64 tx_ucast_pkts; 8892 __le64 tx_mcast_pkts; 8893 __le64 tx_bcast_pkts; 8894 __le64 tx_error_pkts; 8895 __le64 tx_discard_pkts; 8896 __le64 tx_ucast_bytes; 8897 __le64 tx_mcast_bytes; 8898 __le64 tx_bcast_bytes; 8899 __le64 rx_tpa_eligible_pkt; 8900 __le64 rx_tpa_eligible_bytes; 8901 __le64 rx_tpa_pkt; 8902 __le64 rx_tpa_bytes; 8903 __le64 rx_tpa_errors; 8904 __le64 rx_tpa_events; 8905 u8 unused_0[7]; 8906 u8 valid; 8907 }; 8908 8909 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 8910 struct hwrm_stat_ctx_clr_stats_input { 8911 __le16 req_type; 8912 __le16 cmpl_ring; 8913 __le16 seq_id; 8914 __le16 target_id; 8915 __le64 resp_addr; 8916 __le32 stat_ctx_id; 8917 u8 unused_0[4]; 8918 }; 8919 8920 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 8921 struct hwrm_stat_ctx_clr_stats_output { 8922 __le16 error_code; 8923 __le16 req_type; 8924 __le16 seq_id; 8925 __le16 resp_len; 8926 u8 unused_0[7]; 8927 u8 valid; 8928 }; 8929 8930 /* hwrm_pcie_qstats_input (size:256b/32B) */ 8931 struct hwrm_pcie_qstats_input { 8932 __le16 req_type; 8933 __le16 cmpl_ring; 8934 __le16 seq_id; 8935 __le16 target_id; 8936 __le64 resp_addr; 8937 __le16 pcie_stat_size; 8938 u8 unused_0[6]; 8939 __le64 pcie_stat_host_addr; 8940 }; 8941 8942 /* hwrm_pcie_qstats_output (size:128b/16B) */ 8943 struct hwrm_pcie_qstats_output { 8944 __le16 error_code; 8945 __le16 req_type; 8946 __le16 seq_id; 8947 __le16 resp_len; 8948 __le16 pcie_stat_size; 8949 u8 unused_0[5]; 8950 u8 valid; 8951 }; 8952 8953 /* pcie_ctx_hw_stats (size:768b/96B) */ 8954 struct pcie_ctx_hw_stats { 8955 __le64 pcie_pl_signal_integrity; 8956 __le64 pcie_dl_signal_integrity; 8957 __le64 pcie_tl_signal_integrity; 8958 __le64 pcie_link_integrity; 8959 __le64 pcie_tx_traffic_rate; 8960 __le64 pcie_rx_traffic_rate; 8961 __le64 pcie_tx_dllp_statistics; 8962 __le64 pcie_rx_dllp_statistics; 8963 __le64 pcie_equalization_time; 8964 __le32 pcie_ltssm_histogram[4]; 8965 __le64 pcie_recovery_histogram; 8966 }; 8967 8968 /* hwrm_stat_generic_qstats_input (size:256b/32B) */ 8969 struct hwrm_stat_generic_qstats_input { 8970 __le16 req_type; 8971 __le16 cmpl_ring; 8972 __le16 seq_id; 8973 __le16 target_id; 8974 __le64 resp_addr; 8975 __le16 generic_stat_size; 8976 u8 flags; 8977 #define STAT_GENERIC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 8978 u8 unused_0[5]; 8979 __le64 generic_stat_host_addr; 8980 }; 8981 8982 /* hwrm_stat_generic_qstats_output (size:128b/16B) */ 8983 struct hwrm_stat_generic_qstats_output { 8984 __le16 error_code; 8985 __le16 req_type; 8986 __le16 seq_id; 8987 __le16 resp_len; 8988 __le16 generic_stat_size; 8989 u8 unused_0[5]; 8990 u8 valid; 8991 }; 8992 8993 /* generic_sw_hw_stats (size:1472b/184B) */ 8994 struct generic_sw_hw_stats { 8995 __le64 pcie_statistics_tx_tlp; 8996 __le64 pcie_statistics_rx_tlp; 8997 __le64 pcie_credit_fc_hdr_posted; 8998 __le64 pcie_credit_fc_hdr_nonposted; 8999 __le64 pcie_credit_fc_hdr_cmpl; 9000 __le64 pcie_credit_fc_data_posted; 9001 __le64 pcie_credit_fc_data_nonposted; 9002 __le64 pcie_credit_fc_data_cmpl; 9003 __le64 pcie_credit_fc_tgt_nonposted; 9004 __le64 pcie_credit_fc_tgt_data_posted; 9005 __le64 pcie_credit_fc_tgt_hdr_posted; 9006 __le64 pcie_credit_fc_cmpl_hdr_posted; 9007 __le64 pcie_credit_fc_cmpl_data_posted; 9008 __le64 pcie_cmpl_longest; 9009 __le64 pcie_cmpl_shortest; 9010 __le64 cache_miss_count_cfcq; 9011 __le64 cache_miss_count_cfcs; 9012 __le64 cache_miss_count_cfcc; 9013 __le64 cache_miss_count_cfcm; 9014 __le64 hw_db_recov_dbs_dropped; 9015 __le64 hw_db_recov_drops_serviced; 9016 __le64 hw_db_recov_dbs_recovered; 9017 __le64 hw_db_recov_oo_drop_count; 9018 }; 9019 9020 /* hwrm_fw_reset_input (size:192b/24B) */ 9021 struct hwrm_fw_reset_input { 9022 __le16 req_type; 9023 __le16 cmpl_ring; 9024 __le16 seq_id; 9025 __le16 target_id; 9026 __le64 resp_addr; 9027 u8 embedded_proc_type; 9028 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 9029 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 9030 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 9031 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 9032 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 9033 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 9034 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 9035 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 9036 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL 9037 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 9038 u8 selfrst_status; 9039 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 9040 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 9041 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 9042 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 9043 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 9044 u8 host_idx; 9045 u8 flags; 9046 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL 9047 #define FW_RESET_REQ_FLAGS_FW_ACTIVATION 0x2UL 9048 u8 unused_0[4]; 9049 }; 9050 9051 /* hwrm_fw_reset_output (size:128b/16B) */ 9052 struct hwrm_fw_reset_output { 9053 __le16 error_code; 9054 __le16 req_type; 9055 __le16 seq_id; 9056 __le16 resp_len; 9057 u8 selfrst_status; 9058 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 9059 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 9060 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 9061 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 9062 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 9063 u8 unused_0[6]; 9064 u8 valid; 9065 }; 9066 9067 /* hwrm_fw_qstatus_input (size:192b/24B) */ 9068 struct hwrm_fw_qstatus_input { 9069 __le16 req_type; 9070 __le16 cmpl_ring; 9071 __le16 seq_id; 9072 __le16 target_id; 9073 __le64 resp_addr; 9074 u8 embedded_proc_type; 9075 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 9076 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 9077 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 9078 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 9079 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 9080 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 9081 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 9082 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 9083 u8 unused_0[7]; 9084 }; 9085 9086 /* hwrm_fw_qstatus_output (size:128b/16B) */ 9087 struct hwrm_fw_qstatus_output { 9088 __le16 error_code; 9089 __le16 req_type; 9090 __le16 seq_id; 9091 __le16 resp_len; 9092 u8 selfrst_status; 9093 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 9094 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 9095 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 9096 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL 9097 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 9098 u8 nvm_option_action_status; 9099 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_NONE 0x0UL 9100 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_HOTRESET 0x1UL 9101 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_WARMBOOT 0x2UL 9102 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 0x3UL 9103 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_LAST FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 9104 u8 unused_0[5]; 9105 u8 valid; 9106 }; 9107 9108 /* hwrm_fw_set_time_input (size:256b/32B) */ 9109 struct hwrm_fw_set_time_input { 9110 __le16 req_type; 9111 __le16 cmpl_ring; 9112 __le16 seq_id; 9113 __le16 target_id; 9114 __le64 resp_addr; 9115 __le16 year; 9116 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 9117 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 9118 u8 month; 9119 u8 day; 9120 u8 hour; 9121 u8 minute; 9122 u8 second; 9123 u8 unused_0; 9124 __le16 millisecond; 9125 __le16 zone; 9126 #define FW_SET_TIME_REQ_ZONE_UTC 0 9127 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535 9128 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 9129 u8 unused_1[4]; 9130 }; 9131 9132 /* hwrm_fw_set_time_output (size:128b/16B) */ 9133 struct hwrm_fw_set_time_output { 9134 __le16 error_code; 9135 __le16 req_type; 9136 __le16 seq_id; 9137 __le16 resp_len; 9138 u8 unused_0[7]; 9139 u8 valid; 9140 }; 9141 9142 /* hwrm_struct_hdr (size:128b/16B) */ 9143 struct hwrm_struct_hdr { 9144 __le16 struct_id; 9145 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 9146 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 9147 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 9148 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 9149 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 9150 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 9151 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 9152 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL 9153 #define STRUCT_HDR_STRUCT_ID_PEER_MMAP 0x429UL 9154 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 9155 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 9156 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 9157 #define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL 9158 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 9159 __le16 len; 9160 u8 version; 9161 u8 count; 9162 __le16 subtype; 9163 __le16 next_offset; 9164 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 9165 u8 unused_0[6]; 9166 }; 9167 9168 /* hwrm_struct_data_dcbx_app (size:64b/8B) */ 9169 struct hwrm_struct_data_dcbx_app { 9170 __be16 protocol_id; 9171 u8 protocol_selector; 9172 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 9173 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 9174 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 9175 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 9176 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 9177 u8 priority; 9178 u8 valid; 9179 u8 unused_0[3]; 9180 }; 9181 9182 /* hwrm_fw_set_structured_data_input (size:256b/32B) */ 9183 struct hwrm_fw_set_structured_data_input { 9184 __le16 req_type; 9185 __le16 cmpl_ring; 9186 __le16 seq_id; 9187 __le16 target_id; 9188 __le64 resp_addr; 9189 __le64 src_data_addr; 9190 __le16 data_len; 9191 u8 hdr_cnt; 9192 u8 unused_0[5]; 9193 }; 9194 9195 /* hwrm_fw_set_structured_data_output (size:128b/16B) */ 9196 struct hwrm_fw_set_structured_data_output { 9197 __le16 error_code; 9198 __le16 req_type; 9199 __le16 seq_id; 9200 __le16 resp_len; 9201 u8 unused_0[7]; 9202 u8 valid; 9203 }; 9204 9205 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 9206 struct hwrm_fw_set_structured_data_cmd_err { 9207 u8 code; 9208 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 9209 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 9210 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 9211 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 9212 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 9213 u8 unused_0[7]; 9214 }; 9215 9216 /* hwrm_fw_get_structured_data_input (size:256b/32B) */ 9217 struct hwrm_fw_get_structured_data_input { 9218 __le16 req_type; 9219 __le16 cmpl_ring; 9220 __le16 seq_id; 9221 __le16 target_id; 9222 __le64 resp_addr; 9223 __le64 dest_data_addr; 9224 __le16 data_len; 9225 __le16 structure_id; 9226 __le16 subtype; 9227 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 9228 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 9229 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 9230 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 9231 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 9232 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 9233 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 9234 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 9235 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 9236 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 9237 u8 count; 9238 u8 unused_0; 9239 }; 9240 9241 /* hwrm_fw_get_structured_data_output (size:128b/16B) */ 9242 struct hwrm_fw_get_structured_data_output { 9243 __le16 error_code; 9244 __le16 req_type; 9245 __le16 seq_id; 9246 __le16 resp_len; 9247 u8 hdr_cnt; 9248 u8 unused_0[6]; 9249 u8 valid; 9250 }; 9251 9252 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 9253 struct hwrm_fw_get_structured_data_cmd_err { 9254 u8 code; 9255 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 9256 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 9257 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 9258 u8 unused_0[7]; 9259 }; 9260 9261 /* hwrm_fw_livepatch_query_input (size:192b/24B) */ 9262 struct hwrm_fw_livepatch_query_input { 9263 __le16 req_type; 9264 __le16 cmpl_ring; 9265 __le16 seq_id; 9266 __le16 target_id; 9267 __le64 resp_addr; 9268 u8 fw_target; 9269 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_COMMON_FW 0x1UL 9270 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 0x2UL 9271 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_LAST FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 9272 u8 unused_0[7]; 9273 }; 9274 9275 /* hwrm_fw_livepatch_query_output (size:640b/80B) */ 9276 struct hwrm_fw_livepatch_query_output { 9277 __le16 error_code; 9278 __le16 req_type; 9279 __le16 seq_id; 9280 __le16 resp_len; 9281 char install_ver[32]; 9282 char active_ver[32]; 9283 __le16 status_flags; 9284 #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_INSTALL 0x1UL 9285 #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_ACTIVE 0x2UL 9286 u8 unused_0[5]; 9287 u8 valid; 9288 }; 9289 9290 /* hwrm_fw_livepatch_input (size:256b/32B) */ 9291 struct hwrm_fw_livepatch_input { 9292 __le16 req_type; 9293 __le16 cmpl_ring; 9294 __le16 seq_id; 9295 __le16 target_id; 9296 __le64 resp_addr; 9297 u8 opcode; 9298 #define FW_LIVEPATCH_REQ_OPCODE_ACTIVATE 0x1UL 9299 #define FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 0x2UL 9300 #define FW_LIVEPATCH_REQ_OPCODE_LAST FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 9301 u8 fw_target; 9302 #define FW_LIVEPATCH_REQ_FW_TARGET_COMMON_FW 0x1UL 9303 #define FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 0x2UL 9304 #define FW_LIVEPATCH_REQ_FW_TARGET_LAST FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 9305 u8 loadtype; 9306 #define FW_LIVEPATCH_REQ_LOADTYPE_NVM_INSTALL 0x1UL 9307 #define FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 0x2UL 9308 #define FW_LIVEPATCH_REQ_LOADTYPE_LAST FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 9309 u8 flags; 9310 __le32 patch_len; 9311 __le64 host_addr; 9312 }; 9313 9314 /* hwrm_fw_livepatch_output (size:128b/16B) */ 9315 struct hwrm_fw_livepatch_output { 9316 __le16 error_code; 9317 __le16 req_type; 9318 __le16 seq_id; 9319 __le16 resp_len; 9320 u8 unused_0[7]; 9321 u8 valid; 9322 }; 9323 9324 /* hwrm_fw_livepatch_cmd_err (size:64b/8B) */ 9325 struct hwrm_fw_livepatch_cmd_err { 9326 u8 code; 9327 #define FW_LIVEPATCH_CMD_ERR_CODE_UNKNOWN 0x0UL 9328 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_OPCODE 0x1UL 9329 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_TARGET 0x2UL 9330 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_SUPPORTED 0x3UL 9331 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_INSTALLED 0x4UL 9332 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_PATCHED 0x5UL 9333 #define FW_LIVEPATCH_CMD_ERR_CODE_AUTH_FAIL 0x6UL 9334 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_HEADER 0x7UL 9335 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_SIZE 0x8UL 9336 #define FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 0x9UL 9337 #define FW_LIVEPATCH_CMD_ERR_CODE_LAST FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 9338 u8 unused_0[7]; 9339 }; 9340 9341 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 9342 struct hwrm_exec_fwd_resp_input { 9343 __le16 req_type; 9344 __le16 cmpl_ring; 9345 __le16 seq_id; 9346 __le16 target_id; 9347 __le64 resp_addr; 9348 __le32 encap_request[26]; 9349 __le16 encap_resp_target_id; 9350 u8 unused_0[6]; 9351 }; 9352 9353 /* hwrm_exec_fwd_resp_output (size:128b/16B) */ 9354 struct hwrm_exec_fwd_resp_output { 9355 __le16 error_code; 9356 __le16 req_type; 9357 __le16 seq_id; 9358 __le16 resp_len; 9359 u8 unused_0[7]; 9360 u8 valid; 9361 }; 9362 9363 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 9364 struct hwrm_reject_fwd_resp_input { 9365 __le16 req_type; 9366 __le16 cmpl_ring; 9367 __le16 seq_id; 9368 __le16 target_id; 9369 __le64 resp_addr; 9370 __le32 encap_request[26]; 9371 __le16 encap_resp_target_id; 9372 u8 unused_0[6]; 9373 }; 9374 9375 /* hwrm_reject_fwd_resp_output (size:128b/16B) */ 9376 struct hwrm_reject_fwd_resp_output { 9377 __le16 error_code; 9378 __le16 req_type; 9379 __le16 seq_id; 9380 __le16 resp_len; 9381 u8 unused_0[7]; 9382 u8 valid; 9383 }; 9384 9385 /* hwrm_fwd_resp_input (size:1024b/128B) */ 9386 struct hwrm_fwd_resp_input { 9387 __le16 req_type; 9388 __le16 cmpl_ring; 9389 __le16 seq_id; 9390 __le16 target_id; 9391 __le64 resp_addr; 9392 __le16 encap_resp_target_id; 9393 __le16 encap_resp_cmpl_ring; 9394 __le16 encap_resp_len; 9395 u8 unused_0; 9396 u8 unused_1; 9397 __le64 encap_resp_addr; 9398 __le32 encap_resp[24]; 9399 }; 9400 9401 /* hwrm_fwd_resp_output (size:128b/16B) */ 9402 struct hwrm_fwd_resp_output { 9403 __le16 error_code; 9404 __le16 req_type; 9405 __le16 seq_id; 9406 __le16 resp_len; 9407 u8 unused_0[7]; 9408 u8 valid; 9409 }; 9410 9411 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 9412 struct hwrm_fwd_async_event_cmpl_input { 9413 __le16 req_type; 9414 __le16 cmpl_ring; 9415 __le16 seq_id; 9416 __le16 target_id; 9417 __le64 resp_addr; 9418 __le16 encap_async_event_target_id; 9419 u8 unused_0[6]; 9420 __le32 encap_async_event_cmpl[4]; 9421 }; 9422 9423 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 9424 struct hwrm_fwd_async_event_cmpl_output { 9425 __le16 error_code; 9426 __le16 req_type; 9427 __le16 seq_id; 9428 __le16 resp_len; 9429 u8 unused_0[7]; 9430 u8 valid; 9431 }; 9432 9433 /* hwrm_temp_monitor_query_input (size:128b/16B) */ 9434 struct hwrm_temp_monitor_query_input { 9435 __le16 req_type; 9436 __le16 cmpl_ring; 9437 __le16 seq_id; 9438 __le16 target_id; 9439 __le64 resp_addr; 9440 }; 9441 9442 /* hwrm_temp_monitor_query_output (size:192b/24B) */ 9443 struct hwrm_temp_monitor_query_output { 9444 __le16 error_code; 9445 __le16 req_type; 9446 __le16 seq_id; 9447 __le16 resp_len; 9448 u8 temp; 9449 u8 phy_temp; 9450 u8 om_temp; 9451 u8 flags; 9452 #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL 9453 #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL 9454 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL 9455 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL 9456 #define TEMP_MONITOR_QUERY_RESP_FLAGS_EXT_TEMP_FIELDS_AVAILABLE 0x10UL 9457 #define TEMP_MONITOR_QUERY_RESP_FLAGS_THRESHOLD_VALUES_AVAILABLE 0x20UL 9458 u8 temp2; 9459 u8 phy_temp2; 9460 u8 om_temp2; 9461 u8 warn_threshold; 9462 u8 critical_threshold; 9463 u8 fatal_threshold; 9464 u8 shutdown_threshold; 9465 u8 unused_0[4]; 9466 u8 valid; 9467 }; 9468 9469 /* hwrm_wol_filter_alloc_input (size:512b/64B) */ 9470 struct hwrm_wol_filter_alloc_input { 9471 __le16 req_type; 9472 __le16 cmpl_ring; 9473 __le16 seq_id; 9474 __le16 target_id; 9475 __le64 resp_addr; 9476 __le32 flags; 9477 __le32 enables; 9478 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 9479 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 9480 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 9481 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 9482 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 9483 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 9484 __le16 port_id; 9485 u8 wol_type; 9486 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 9487 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 9488 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 9489 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 9490 u8 unused_0[5]; 9491 u8 mac_address[6]; 9492 __le16 pattern_offset; 9493 __le16 pattern_buf_size; 9494 __le16 pattern_mask_size; 9495 u8 unused_1[4]; 9496 __le64 pattern_buf_addr; 9497 __le64 pattern_mask_addr; 9498 }; 9499 9500 /* hwrm_wol_filter_alloc_output (size:128b/16B) */ 9501 struct hwrm_wol_filter_alloc_output { 9502 __le16 error_code; 9503 __le16 req_type; 9504 __le16 seq_id; 9505 __le16 resp_len; 9506 u8 wol_filter_id; 9507 u8 unused_0[6]; 9508 u8 valid; 9509 }; 9510 9511 /* hwrm_wol_filter_free_input (size:256b/32B) */ 9512 struct hwrm_wol_filter_free_input { 9513 __le16 req_type; 9514 __le16 cmpl_ring; 9515 __le16 seq_id; 9516 __le16 target_id; 9517 __le64 resp_addr; 9518 __le32 flags; 9519 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 9520 __le32 enables; 9521 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 9522 __le16 port_id; 9523 u8 wol_filter_id; 9524 u8 unused_0[5]; 9525 }; 9526 9527 /* hwrm_wol_filter_free_output (size:128b/16B) */ 9528 struct hwrm_wol_filter_free_output { 9529 __le16 error_code; 9530 __le16 req_type; 9531 __le16 seq_id; 9532 __le16 resp_len; 9533 u8 unused_0[7]; 9534 u8 valid; 9535 }; 9536 9537 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 9538 struct hwrm_wol_filter_qcfg_input { 9539 __le16 req_type; 9540 __le16 cmpl_ring; 9541 __le16 seq_id; 9542 __le16 target_id; 9543 __le64 resp_addr; 9544 __le16 port_id; 9545 __le16 handle; 9546 u8 unused_0[4]; 9547 __le64 pattern_buf_addr; 9548 __le16 pattern_buf_size; 9549 u8 unused_1[6]; 9550 __le64 pattern_mask_addr; 9551 __le16 pattern_mask_size; 9552 u8 unused_2[6]; 9553 }; 9554 9555 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 9556 struct hwrm_wol_filter_qcfg_output { 9557 __le16 error_code; 9558 __le16 req_type; 9559 __le16 seq_id; 9560 __le16 resp_len; 9561 __le16 next_handle; 9562 u8 wol_filter_id; 9563 u8 wol_type; 9564 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 9565 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 9566 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 9567 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 9568 __le32 unused_0; 9569 u8 mac_address[6]; 9570 __le16 pattern_offset; 9571 __le16 pattern_size; 9572 __le16 pattern_mask_size; 9573 u8 unused_1[3]; 9574 u8 valid; 9575 }; 9576 9577 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 9578 struct hwrm_wol_reason_qcfg_input { 9579 __le16 req_type; 9580 __le16 cmpl_ring; 9581 __le16 seq_id; 9582 __le16 target_id; 9583 __le64 resp_addr; 9584 __le16 port_id; 9585 u8 unused_0[6]; 9586 __le64 wol_pkt_buf_addr; 9587 __le16 wol_pkt_buf_size; 9588 u8 unused_1[6]; 9589 }; 9590 9591 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 9592 struct hwrm_wol_reason_qcfg_output { 9593 __le16 error_code; 9594 __le16 req_type; 9595 __le16 seq_id; 9596 __le16 resp_len; 9597 u8 wol_filter_id; 9598 u8 wol_reason; 9599 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 9600 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 9601 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 9602 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 9603 u8 wol_pkt_len; 9604 u8 unused_0[4]; 9605 u8 valid; 9606 }; 9607 9608 /* hwrm_dbg_read_direct_input (size:256b/32B) */ 9609 struct hwrm_dbg_read_direct_input { 9610 __le16 req_type; 9611 __le16 cmpl_ring; 9612 __le16 seq_id; 9613 __le16 target_id; 9614 __le64 resp_addr; 9615 __le64 host_dest_addr; 9616 __le32 read_addr; 9617 __le32 read_len32; 9618 }; 9619 9620 /* hwrm_dbg_read_direct_output (size:128b/16B) */ 9621 struct hwrm_dbg_read_direct_output { 9622 __le16 error_code; 9623 __le16 req_type; 9624 __le16 seq_id; 9625 __le16 resp_len; 9626 __le32 crc32; 9627 u8 unused_0[3]; 9628 u8 valid; 9629 }; 9630 9631 /* hwrm_dbg_qcaps_input (size:192b/24B) */ 9632 struct hwrm_dbg_qcaps_input { 9633 __le16 req_type; 9634 __le16 cmpl_ring; 9635 __le16 seq_id; 9636 __le16 target_id; 9637 __le64 resp_addr; 9638 __le16 fid; 9639 u8 unused_0[6]; 9640 }; 9641 9642 /* hwrm_dbg_qcaps_output (size:192b/24B) */ 9643 struct hwrm_dbg_qcaps_output { 9644 __le16 error_code; 9645 __le16 req_type; 9646 __le16 seq_id; 9647 __le16 resp_len; 9648 __le16 fid; 9649 u8 unused_0[2]; 9650 __le32 coredump_component_disable_caps; 9651 #define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM 0x1UL 9652 __le32 flags; 9653 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL 9654 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL 9655 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL 9656 #define DBG_QCAPS_RESP_FLAGS_USEQ 0x8UL 9657 u8 unused_1[3]; 9658 u8 valid; 9659 }; 9660 9661 /* hwrm_dbg_qcfg_input (size:192b/24B) */ 9662 struct hwrm_dbg_qcfg_input { 9663 __le16 req_type; 9664 __le16 cmpl_ring; 9665 __le16 seq_id; 9666 __le16 target_id; 9667 __le64 resp_addr; 9668 __le16 fid; 9669 __le16 flags; 9670 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK 0x3UL 9671 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0 9672 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM 0x0UL 9673 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR 0x1UL 9674 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 0x2UL 9675 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 9676 __le32 coredump_component_disable_flags; 9677 #define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM 0x1UL 9678 }; 9679 9680 /* hwrm_dbg_qcfg_output (size:256b/32B) */ 9681 struct hwrm_dbg_qcfg_output { 9682 __le16 error_code; 9683 __le16 req_type; 9684 __le16 seq_id; 9685 __le16 resp_len; 9686 __le16 fid; 9687 u8 unused_0[2]; 9688 __le32 coredump_size; 9689 __le32 flags; 9690 #define DBG_QCFG_RESP_FLAGS_UART_LOG 0x1UL 9691 #define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY 0x2UL 9692 #define DBG_QCFG_RESP_FLAGS_FW_TRACE 0x4UL 9693 #define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY 0x8UL 9694 #define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY 0x10UL 9695 #define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG 0x20UL 9696 __le16 async_cmpl_ring; 9697 u8 unused_2[2]; 9698 __le32 crashdump_size; 9699 u8 unused_3[3]; 9700 u8 valid; 9701 }; 9702 9703 /* hwrm_dbg_crashdump_medium_cfg_input (size:320b/40B) */ 9704 struct hwrm_dbg_crashdump_medium_cfg_input { 9705 __le16 req_type; 9706 __le16 cmpl_ring; 9707 __le16 seq_id; 9708 __le16 target_id; 9709 __le64 resp_addr; 9710 __le16 output_dest_flags; 9711 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_TYPE_DDR 0x1UL 9712 __le16 pg_size_lvl; 9713 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_MASK 0x3UL 9714 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_SFT 0 9715 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_0 0x0UL 9716 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_1 0x1UL 9717 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2 0x2UL 9718 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2 9719 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_MASK 0x1cUL 9720 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_SFT 2 9721 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_4K (0x0UL << 2) 9722 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8K (0x1UL << 2) 9723 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_64K (0x2UL << 2) 9724 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_2M (0x3UL << 2) 9725 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8M (0x4UL << 2) 9726 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G (0x5UL << 2) 9727 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G 9728 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_MASK 0xffe0UL 9729 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_SFT 5 9730 __le32 size; 9731 __le32 coredump_component_disable_flags; 9732 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_NVRAM 0x1UL 9733 __le32 unused_0; 9734 __le64 pbl; 9735 }; 9736 9737 /* hwrm_dbg_crashdump_medium_cfg_output (size:128b/16B) */ 9738 struct hwrm_dbg_crashdump_medium_cfg_output { 9739 __le16 error_code; 9740 __le16 req_type; 9741 __le16 seq_id; 9742 __le16 resp_len; 9743 u8 unused_1[7]; 9744 u8 valid; 9745 }; 9746 9747 /* coredump_segment_record (size:128b/16B) */ 9748 struct coredump_segment_record { 9749 __le16 component_id; 9750 __le16 segment_id; 9751 __le16 max_instances; 9752 u8 version_hi; 9753 u8 version_low; 9754 u8 seg_flags; 9755 u8 compress_flags; 9756 #define SFLAG_COMPRESSED_ZLIB 0x1UL 9757 u8 unused_0[2]; 9758 __le32 segment_len; 9759 }; 9760 9761 /* hwrm_dbg_coredump_list_input (size:256b/32B) */ 9762 struct hwrm_dbg_coredump_list_input { 9763 __le16 req_type; 9764 __le16 cmpl_ring; 9765 __le16 seq_id; 9766 __le16 target_id; 9767 __le64 resp_addr; 9768 __le64 host_dest_addr; 9769 __le32 host_buf_len; 9770 __le16 seq_no; 9771 u8 flags; 9772 #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL 9773 u8 unused_0[1]; 9774 }; 9775 9776 /* hwrm_dbg_coredump_list_output (size:128b/16B) */ 9777 struct hwrm_dbg_coredump_list_output { 9778 __le16 error_code; 9779 __le16 req_type; 9780 __le16 seq_id; 9781 __le16 resp_len; 9782 u8 flags; 9783 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 9784 u8 unused_0; 9785 __le16 total_segments; 9786 __le16 data_len; 9787 u8 unused_1; 9788 u8 valid; 9789 }; 9790 9791 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 9792 struct hwrm_dbg_coredump_initiate_input { 9793 __le16 req_type; 9794 __le16 cmpl_ring; 9795 __le16 seq_id; 9796 __le16 target_id; 9797 __le64 resp_addr; 9798 __le16 component_id; 9799 __le16 segment_id; 9800 __le16 instance; 9801 __le16 unused_0; 9802 u8 seg_flags; 9803 #define DBG_COREDUMP_INITIATE_REQ_SEG_FLAGS_LIVE_DATA 0x1UL 9804 #define DBG_COREDUMP_INITIATE_REQ_SEG_FLAGS_CRASH_DATA 0x2UL 9805 #define DBG_COREDUMP_INITIATE_REQ_SEG_FLAGS_COLLECT_CTX_L1_CACHE 0x4UL 9806 u8 unused_1[7]; 9807 }; 9808 9809 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 9810 struct hwrm_dbg_coredump_initiate_output { 9811 __le16 error_code; 9812 __le16 req_type; 9813 __le16 seq_id; 9814 __le16 resp_len; 9815 u8 unused_0[7]; 9816 u8 valid; 9817 }; 9818 9819 /* coredump_data_hdr (size:128b/16B) */ 9820 struct coredump_data_hdr { 9821 __le32 address; 9822 __le32 flags_length; 9823 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK 0xffffffUL 9824 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT 0 9825 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS 0x1000000UL 9826 __le32 instance; 9827 __le32 next_offset; 9828 }; 9829 9830 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 9831 struct hwrm_dbg_coredump_retrieve_input { 9832 __le16 req_type; 9833 __le16 cmpl_ring; 9834 __le16 seq_id; 9835 __le16 target_id; 9836 __le64 resp_addr; 9837 __le64 host_dest_addr; 9838 __le32 host_buf_len; 9839 __le32 unused_0; 9840 __le16 component_id; 9841 __le16 segment_id; 9842 __le16 instance; 9843 __le16 unused_1; 9844 u8 seg_flags; 9845 u8 unused_2; 9846 __le16 unused_3; 9847 __le32 unused_4; 9848 __le32 seq_no; 9849 __le32 unused_5; 9850 }; 9851 9852 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 9853 struct hwrm_dbg_coredump_retrieve_output { 9854 __le16 error_code; 9855 __le16 req_type; 9856 __le16 seq_id; 9857 __le16 resp_len; 9858 u8 flags; 9859 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 9860 u8 unused_0; 9861 __le16 data_len; 9862 u8 unused_1[3]; 9863 u8 valid; 9864 }; 9865 9866 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 9867 struct hwrm_dbg_ring_info_get_input { 9868 __le16 req_type; 9869 __le16 cmpl_ring; 9870 __le16 seq_id; 9871 __le16 target_id; 9872 __le64 resp_addr; 9873 u8 ring_type; 9874 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 9875 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 9876 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 9877 #define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 0x3UL 9878 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 9879 u8 unused_0[3]; 9880 __le32 fw_ring_id; 9881 }; 9882 9883 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 9884 struct hwrm_dbg_ring_info_get_output { 9885 __le16 error_code; 9886 __le16 req_type; 9887 __le16 seq_id; 9888 __le16 resp_len; 9889 __le32 producer_index; 9890 __le32 consumer_index; 9891 __le32 cag_vector_ctrl; 9892 __le16 st_tag; 9893 u8 unused_0; 9894 u8 valid; 9895 }; 9896 9897 /* hwrm_nvm_read_input (size:320b/40B) */ 9898 struct hwrm_nvm_read_input { 9899 __le16 req_type; 9900 __le16 cmpl_ring; 9901 __le16 seq_id; 9902 __le16 target_id; 9903 __le64 resp_addr; 9904 __le64 host_dest_addr; 9905 __le16 dir_idx; 9906 u8 unused_0[2]; 9907 __le32 offset; 9908 __le32 len; 9909 u8 unused_1[4]; 9910 }; 9911 9912 /* hwrm_nvm_read_output (size:128b/16B) */ 9913 struct hwrm_nvm_read_output { 9914 __le16 error_code; 9915 __le16 req_type; 9916 __le16 seq_id; 9917 __le16 resp_len; 9918 u8 unused_0[7]; 9919 u8 valid; 9920 }; 9921 9922 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 9923 struct hwrm_nvm_get_dir_entries_input { 9924 __le16 req_type; 9925 __le16 cmpl_ring; 9926 __le16 seq_id; 9927 __le16 target_id; 9928 __le64 resp_addr; 9929 __le64 host_dest_addr; 9930 }; 9931 9932 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 9933 struct hwrm_nvm_get_dir_entries_output { 9934 __le16 error_code; 9935 __le16 req_type; 9936 __le16 seq_id; 9937 __le16 resp_len; 9938 u8 unused_0[7]; 9939 u8 valid; 9940 }; 9941 9942 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 9943 struct hwrm_nvm_get_dir_info_input { 9944 __le16 req_type; 9945 __le16 cmpl_ring; 9946 __le16 seq_id; 9947 __le16 target_id; 9948 __le64 resp_addr; 9949 }; 9950 9951 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 9952 struct hwrm_nvm_get_dir_info_output { 9953 __le16 error_code; 9954 __le16 req_type; 9955 __le16 seq_id; 9956 __le16 resp_len; 9957 __le32 entries; 9958 __le32 entry_length; 9959 u8 unused_0[7]; 9960 u8 valid; 9961 }; 9962 9963 /* hwrm_nvm_write_input (size:448b/56B) */ 9964 struct hwrm_nvm_write_input { 9965 __le16 req_type; 9966 __le16 cmpl_ring; 9967 __le16 seq_id; 9968 __le16 target_id; 9969 __le64 resp_addr; 9970 __le64 host_src_addr; 9971 __le16 dir_type; 9972 __le16 dir_ordinal; 9973 __le16 dir_ext; 9974 __le16 dir_attr; 9975 __le32 dir_data_length; 9976 __le16 option; 9977 __le16 flags; 9978 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 9979 #define NVM_WRITE_REQ_FLAGS_BATCH_MODE 0x2UL 9980 #define NVM_WRITE_REQ_FLAGS_BATCH_LAST 0x4UL 9981 __le32 dir_item_length; 9982 __le32 offset; 9983 __le32 len; 9984 __le32 unused_0; 9985 }; 9986 9987 /* hwrm_nvm_write_output (size:128b/16B) */ 9988 struct hwrm_nvm_write_output { 9989 __le16 error_code; 9990 __le16 req_type; 9991 __le16 seq_id; 9992 __le16 resp_len; 9993 __le32 dir_item_length; 9994 __le16 dir_idx; 9995 u8 unused_0; 9996 u8 valid; 9997 }; 9998 9999 /* hwrm_nvm_write_cmd_err (size:64b/8B) */ 10000 struct hwrm_nvm_write_cmd_err { 10001 u8 code; 10002 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 10003 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 10004 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 10005 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 10006 u8 unused_0[7]; 10007 }; 10008 10009 /* hwrm_nvm_modify_input (size:320b/40B) */ 10010 struct hwrm_nvm_modify_input { 10011 __le16 req_type; 10012 __le16 cmpl_ring; 10013 __le16 seq_id; 10014 __le16 target_id; 10015 __le64 resp_addr; 10016 __le64 host_src_addr; 10017 __le16 dir_idx; 10018 __le16 flags; 10019 #define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL 10020 #define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL 10021 __le32 offset; 10022 __le32 len; 10023 u8 unused_1[4]; 10024 }; 10025 10026 /* hwrm_nvm_modify_output (size:128b/16B) */ 10027 struct hwrm_nvm_modify_output { 10028 __le16 error_code; 10029 __le16 req_type; 10030 __le16 seq_id; 10031 __le16 resp_len; 10032 u8 unused_0[7]; 10033 u8 valid; 10034 }; 10035 10036 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 10037 struct hwrm_nvm_find_dir_entry_input { 10038 __le16 req_type; 10039 __le16 cmpl_ring; 10040 __le16 seq_id; 10041 __le16 target_id; 10042 __le64 resp_addr; 10043 __le32 enables; 10044 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 10045 __le16 dir_idx; 10046 __le16 dir_type; 10047 __le16 dir_ordinal; 10048 __le16 dir_ext; 10049 u8 opt_ordinal; 10050 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 10051 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 10052 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 10053 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 10054 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 10055 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 10056 u8 unused_0[3]; 10057 }; 10058 10059 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 10060 struct hwrm_nvm_find_dir_entry_output { 10061 __le16 error_code; 10062 __le16 req_type; 10063 __le16 seq_id; 10064 __le16 resp_len; 10065 __le32 dir_item_length; 10066 __le32 dir_data_length; 10067 __le32 fw_ver; 10068 __le16 dir_ordinal; 10069 __le16 dir_idx; 10070 u8 unused_0[7]; 10071 u8 valid; 10072 }; 10073 10074 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 10075 struct hwrm_nvm_erase_dir_entry_input { 10076 __le16 req_type; 10077 __le16 cmpl_ring; 10078 __le16 seq_id; 10079 __le16 target_id; 10080 __le64 resp_addr; 10081 __le16 dir_idx; 10082 u8 unused_0[6]; 10083 }; 10084 10085 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 10086 struct hwrm_nvm_erase_dir_entry_output { 10087 __le16 error_code; 10088 __le16 req_type; 10089 __le16 seq_id; 10090 __le16 resp_len; 10091 u8 unused_0[7]; 10092 u8 valid; 10093 }; 10094 10095 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 10096 struct hwrm_nvm_get_dev_info_input { 10097 __le16 req_type; 10098 __le16 cmpl_ring; 10099 __le16 seq_id; 10100 __le16 target_id; 10101 __le64 resp_addr; 10102 }; 10103 10104 /* hwrm_nvm_get_dev_info_output (size:704b/88B) */ 10105 struct hwrm_nvm_get_dev_info_output { 10106 __le16 error_code; 10107 __le16 req_type; 10108 __le16 seq_id; 10109 __le16 resp_len; 10110 __le16 manufacturer_id; 10111 __le16 device_id; 10112 __le32 sector_size; 10113 __le32 nvram_size; 10114 __le32 reserved_size; 10115 __le32 available_size; 10116 u8 nvm_cfg_ver_maj; 10117 u8 nvm_cfg_ver_min; 10118 u8 nvm_cfg_ver_upd; 10119 u8 flags; 10120 #define NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID 0x1UL 10121 char pkg_name[16]; 10122 __le16 hwrm_fw_major; 10123 __le16 hwrm_fw_minor; 10124 __le16 hwrm_fw_build; 10125 __le16 hwrm_fw_patch; 10126 __le16 mgmt_fw_major; 10127 __le16 mgmt_fw_minor; 10128 __le16 mgmt_fw_build; 10129 __le16 mgmt_fw_patch; 10130 __le16 roce_fw_major; 10131 __le16 roce_fw_minor; 10132 __le16 roce_fw_build; 10133 __le16 roce_fw_patch; 10134 __le16 netctrl_fw_major; 10135 __le16 netctrl_fw_minor; 10136 __le16 netctrl_fw_build; 10137 __le16 netctrl_fw_patch; 10138 u8 unused_0[7]; 10139 u8 valid; 10140 }; 10141 10142 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 10143 struct hwrm_nvm_mod_dir_entry_input { 10144 __le16 req_type; 10145 __le16 cmpl_ring; 10146 __le16 seq_id; 10147 __le16 target_id; 10148 __le64 resp_addr; 10149 __le32 enables; 10150 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 10151 __le16 dir_idx; 10152 __le16 dir_ordinal; 10153 __le16 dir_ext; 10154 __le16 dir_attr; 10155 __le32 checksum; 10156 }; 10157 10158 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 10159 struct hwrm_nvm_mod_dir_entry_output { 10160 __le16 error_code; 10161 __le16 req_type; 10162 __le16 seq_id; 10163 __le16 resp_len; 10164 u8 unused_0[7]; 10165 u8 valid; 10166 }; 10167 10168 /* hwrm_nvm_verify_update_input (size:192b/24B) */ 10169 struct hwrm_nvm_verify_update_input { 10170 __le16 req_type; 10171 __le16 cmpl_ring; 10172 __le16 seq_id; 10173 __le16 target_id; 10174 __le64 resp_addr; 10175 __le16 dir_type; 10176 __le16 dir_ordinal; 10177 __le16 dir_ext; 10178 u8 unused_0[2]; 10179 }; 10180 10181 /* hwrm_nvm_verify_update_output (size:128b/16B) */ 10182 struct hwrm_nvm_verify_update_output { 10183 __le16 error_code; 10184 __le16 req_type; 10185 __le16 seq_id; 10186 __le16 resp_len; 10187 u8 unused_0[7]; 10188 u8 valid; 10189 }; 10190 10191 /* hwrm_nvm_install_update_input (size:192b/24B) */ 10192 struct hwrm_nvm_install_update_input { 10193 __le16 req_type; 10194 __le16 cmpl_ring; 10195 __le16 seq_id; 10196 __le16 target_id; 10197 __le64 resp_addr; 10198 __le32 install_type; 10199 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 10200 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 10201 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 10202 __le16 flags; 10203 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 10204 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 10205 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 10206 #define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY 0x8UL 10207 u8 unused_0[2]; 10208 }; 10209 10210 /* hwrm_nvm_install_update_output (size:192b/24B) */ 10211 struct hwrm_nvm_install_update_output { 10212 __le16 error_code; 10213 __le16 req_type; 10214 __le16 seq_id; 10215 __le16 resp_len; 10216 __le64 installed_items; 10217 u8 result; 10218 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 10219 #define NVM_INSTALL_UPDATE_RESP_RESULT_FAILURE 0xffUL 10220 #define NVM_INSTALL_UPDATE_RESP_RESULT_MALLOC_FAILURE 0xfdUL 10221 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER 0xfbUL 10222 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER 0xf3UL 10223 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE 0xf2UL 10224 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER 0xecUL 10225 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE 0xebUL 10226 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM 0xeaUL 10227 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH 0xe9UL 10228 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST 0xe8UL 10229 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER 0xe7UL 10230 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM 0xe6UL 10231 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM 0xe5UL 10232 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH 0xe4UL 10233 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE 0xe1UL 10234 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV 0xceUL 10235 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID 0xcdUL 10236 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR 0xccUL 10237 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID 0xcbUL 10238 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM 0xc5UL 10239 #define NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM 0xc4UL 10240 #define NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM 0xc3UL 10241 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR 0xb9UL 10242 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR 0xb8UL 10243 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR 0xb7UL 10244 #define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND 0xb0UL 10245 #define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED 0xa7UL 10246 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED 10247 u8 problem_item; 10248 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 10249 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 10250 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 10251 u8 reset_required; 10252 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 10253 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 10254 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 10255 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 10256 u8 unused_0[4]; 10257 u8 valid; 10258 }; 10259 10260 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 10261 struct hwrm_nvm_install_update_cmd_err { 10262 u8 code; 10263 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 10264 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 10265 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 10266 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK 0x3UL 10267 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT 0x4UL 10268 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT 10269 u8 unused_0[7]; 10270 }; 10271 10272 /* hwrm_nvm_get_variable_input (size:320b/40B) */ 10273 struct hwrm_nvm_get_variable_input { 10274 __le16 req_type; 10275 __le16 cmpl_ring; 10276 __le16 seq_id; 10277 __le16 target_id; 10278 __le64 resp_addr; 10279 __le64 dest_data_addr; 10280 __le16 data_len; 10281 __le16 option_num; 10282 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 10283 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 10284 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 10285 __le16 dimensions; 10286 __le16 index_0; 10287 __le16 index_1; 10288 __le16 index_2; 10289 __le16 index_3; 10290 u8 flags; 10291 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 10292 u8 unused_0; 10293 }; 10294 10295 /* hwrm_nvm_get_variable_output (size:128b/16B) */ 10296 struct hwrm_nvm_get_variable_output { 10297 __le16 error_code; 10298 __le16 req_type; 10299 __le16 seq_id; 10300 __le16 resp_len; 10301 __le16 data_len; 10302 __le16 option_num; 10303 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 10304 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 10305 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 10306 u8 unused_0[3]; 10307 u8 valid; 10308 }; 10309 10310 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 10311 struct hwrm_nvm_get_variable_cmd_err { 10312 u8 code; 10313 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 10314 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 10315 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 10316 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 10317 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 10318 u8 unused_0[7]; 10319 }; 10320 10321 /* hwrm_nvm_set_variable_input (size:320b/40B) */ 10322 struct hwrm_nvm_set_variable_input { 10323 __le16 req_type; 10324 __le16 cmpl_ring; 10325 __le16 seq_id; 10326 __le16 target_id; 10327 __le64 resp_addr; 10328 __le64 src_data_addr; 10329 __le16 data_len; 10330 __le16 option_num; 10331 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 10332 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 10333 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 10334 __le16 dimensions; 10335 __le16 index_0; 10336 __le16 index_1; 10337 __le16 index_2; 10338 __le16 index_3; 10339 u8 flags; 10340 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 10341 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 10342 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 10343 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 10344 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 10345 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 10346 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 10347 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 10348 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL 10349 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4 10350 #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL 10351 u8 unused_0; 10352 }; 10353 10354 /* hwrm_nvm_set_variable_output (size:128b/16B) */ 10355 struct hwrm_nvm_set_variable_output { 10356 __le16 error_code; 10357 __le16 req_type; 10358 __le16 seq_id; 10359 __le16 resp_len; 10360 u8 unused_0[7]; 10361 u8 valid; 10362 }; 10363 10364 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 10365 struct hwrm_nvm_set_variable_cmd_err { 10366 u8 code; 10367 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 10368 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 10369 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 10370 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 10371 u8 unused_0[7]; 10372 }; 10373 10374 /* hwrm_selftest_qlist_input (size:128b/16B) */ 10375 struct hwrm_selftest_qlist_input { 10376 __le16 req_type; 10377 __le16 cmpl_ring; 10378 __le16 seq_id; 10379 __le16 target_id; 10380 __le64 resp_addr; 10381 }; 10382 10383 /* hwrm_selftest_qlist_output (size:2240b/280B) */ 10384 struct hwrm_selftest_qlist_output { 10385 __le16 error_code; 10386 __le16 req_type; 10387 __le16 seq_id; 10388 __le16 resp_len; 10389 u8 num_tests; 10390 u8 available_tests; 10391 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 10392 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 10393 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 10394 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 10395 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 10396 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 10397 u8 offline_tests; 10398 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 10399 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 10400 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 10401 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 10402 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 10403 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 10404 u8 unused_0; 10405 __le16 test_timeout; 10406 u8 unused_1[2]; 10407 char test_name[8][32]; 10408 u8 eyescope_target_BER_support; 10409 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED 0x0UL 10410 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED 0x1UL 10411 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL 10412 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL 10413 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL 10414 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 10415 u8 unused_2[6]; 10416 u8 valid; 10417 }; 10418 10419 /* hwrm_selftest_exec_input (size:192b/24B) */ 10420 struct hwrm_selftest_exec_input { 10421 __le16 req_type; 10422 __le16 cmpl_ring; 10423 __le16 seq_id; 10424 __le16 target_id; 10425 __le64 resp_addr; 10426 u8 flags; 10427 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 10428 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 10429 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 10430 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 10431 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 10432 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 10433 u8 unused_0[7]; 10434 }; 10435 10436 /* hwrm_selftest_exec_output (size:128b/16B) */ 10437 struct hwrm_selftest_exec_output { 10438 __le16 error_code; 10439 __le16 req_type; 10440 __le16 seq_id; 10441 __le16 resp_len; 10442 u8 requested_tests; 10443 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 10444 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 10445 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 10446 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 10447 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 10448 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 10449 u8 test_success; 10450 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 10451 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 10452 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 10453 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 10454 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 10455 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 10456 u8 unused_0[5]; 10457 u8 valid; 10458 }; 10459 10460 /* hwrm_selftest_irq_input (size:128b/16B) */ 10461 struct hwrm_selftest_irq_input { 10462 __le16 req_type; 10463 __le16 cmpl_ring; 10464 __le16 seq_id; 10465 __le16 target_id; 10466 __le64 resp_addr; 10467 }; 10468 10469 /* hwrm_selftest_irq_output (size:128b/16B) */ 10470 struct hwrm_selftest_irq_output { 10471 __le16 error_code; 10472 __le16 req_type; 10473 __le16 seq_id; 10474 __le16 resp_len; 10475 u8 unused_0[7]; 10476 u8 valid; 10477 }; 10478 10479 /* dbc_dbc (size:64b/8B) */ 10480 struct dbc_dbc { 10481 __le32 index; 10482 #define DBC_DBC_INDEX_MASK 0xffffffUL 10483 #define DBC_DBC_INDEX_SFT 0 10484 #define DBC_DBC_EPOCH 0x1000000UL 10485 #define DBC_DBC_TOGGLE_MASK 0x6000000UL 10486 #define DBC_DBC_TOGGLE_SFT 25 10487 __le32 type_path_xid; 10488 #define DBC_DBC_XID_MASK 0xfffffUL 10489 #define DBC_DBC_XID_SFT 0 10490 #define DBC_DBC_PATH_MASK 0x3000000UL 10491 #define DBC_DBC_PATH_SFT 24 10492 #define DBC_DBC_PATH_ROCE (0x0UL << 24) 10493 #define DBC_DBC_PATH_L2 (0x1UL << 24) 10494 #define DBC_DBC_PATH_ENGINE (0x2UL << 24) 10495 #define DBC_DBC_PATH_LAST DBC_DBC_PATH_ENGINE 10496 #define DBC_DBC_VALID 0x4000000UL 10497 #define DBC_DBC_DEBUG_TRACE 0x8000000UL 10498 #define DBC_DBC_TYPE_MASK 0xf0000000UL 10499 #define DBC_DBC_TYPE_SFT 28 10500 #define DBC_DBC_TYPE_SQ (0x0UL << 28) 10501 #define DBC_DBC_TYPE_RQ (0x1UL << 28) 10502 #define DBC_DBC_TYPE_SRQ (0x2UL << 28) 10503 #define DBC_DBC_TYPE_SRQ_ARM (0x3UL << 28) 10504 #define DBC_DBC_TYPE_CQ (0x4UL << 28) 10505 #define DBC_DBC_TYPE_CQ_ARMSE (0x5UL << 28) 10506 #define DBC_DBC_TYPE_CQ_ARMALL (0x6UL << 28) 10507 #define DBC_DBC_TYPE_CQ_ARMENA (0x7UL << 28) 10508 #define DBC_DBC_TYPE_SRQ_ARMENA (0x8UL << 28) 10509 #define DBC_DBC_TYPE_CQ_CUTOFF_ACK (0x9UL << 28) 10510 #define DBC_DBC_TYPE_NQ (0xaUL << 28) 10511 #define DBC_DBC_TYPE_NQ_ARM (0xbUL << 28) 10512 #define DBC_DBC_TYPE_NQ_MASK (0xeUL << 28) 10513 #define DBC_DBC_TYPE_NULL (0xfUL << 28) 10514 #define DBC_DBC_TYPE_LAST DBC_DBC_TYPE_NULL 10515 }; 10516 10517 /* db_push_start (size:64b/8B) */ 10518 struct db_push_start { 10519 u64 db; 10520 #define DB_PUSH_START_DB_INDEX_MASK 0xffffffUL 10521 #define DB_PUSH_START_DB_INDEX_SFT 0 10522 #define DB_PUSH_START_DB_PI_LO_MASK 0xff000000UL 10523 #define DB_PUSH_START_DB_PI_LO_SFT 24 10524 #define DB_PUSH_START_DB_XID_MASK 0xfffff00000000ULL 10525 #define DB_PUSH_START_DB_XID_SFT 32 10526 #define DB_PUSH_START_DB_PI_HI_MASK 0xf0000000000000ULL 10527 #define DB_PUSH_START_DB_PI_HI_SFT 52 10528 #define DB_PUSH_START_DB_TYPE_MASK 0xf000000000000000ULL 10529 #define DB_PUSH_START_DB_TYPE_SFT 60 10530 #define DB_PUSH_START_DB_TYPE_PUSH_START (0xcULL << 60) 10531 #define DB_PUSH_START_DB_TYPE_PUSH_END (0xdULL << 60) 10532 #define DB_PUSH_START_DB_TYPE_LAST DB_PUSH_START_DB_TYPE_PUSH_END 10533 }; 10534 10535 /* db_push_end (size:64b/8B) */ 10536 struct db_push_end { 10537 u64 db; 10538 #define DB_PUSH_END_DB_INDEX_MASK 0xffffffUL 10539 #define DB_PUSH_END_DB_INDEX_SFT 0 10540 #define DB_PUSH_END_DB_PI_LO_MASK 0xff000000UL 10541 #define DB_PUSH_END_DB_PI_LO_SFT 24 10542 #define DB_PUSH_END_DB_XID_MASK 0xfffff00000000ULL 10543 #define DB_PUSH_END_DB_XID_SFT 32 10544 #define DB_PUSH_END_DB_PI_HI_MASK 0xf0000000000000ULL 10545 #define DB_PUSH_END_DB_PI_HI_SFT 52 10546 #define DB_PUSH_END_DB_PATH_MASK 0x300000000000000ULL 10547 #define DB_PUSH_END_DB_PATH_SFT 56 10548 #define DB_PUSH_END_DB_PATH_ROCE (0x0ULL << 56) 10549 #define DB_PUSH_END_DB_PATH_L2 (0x1ULL << 56) 10550 #define DB_PUSH_END_DB_PATH_ENGINE (0x2ULL << 56) 10551 #define DB_PUSH_END_DB_PATH_LAST DB_PUSH_END_DB_PATH_ENGINE 10552 #define DB_PUSH_END_DB_DEBUG_TRACE 0x800000000000000ULL 10553 #define DB_PUSH_END_DB_TYPE_MASK 0xf000000000000000ULL 10554 #define DB_PUSH_END_DB_TYPE_SFT 60 10555 #define DB_PUSH_END_DB_TYPE_PUSH_START (0xcULL << 60) 10556 #define DB_PUSH_END_DB_TYPE_PUSH_END (0xdULL << 60) 10557 #define DB_PUSH_END_DB_TYPE_LAST DB_PUSH_END_DB_TYPE_PUSH_END 10558 }; 10559 10560 /* db_push_info (size:64b/8B) */ 10561 struct db_push_info { 10562 u32 push_size_push_index; 10563 #define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL 10564 #define DB_PUSH_INFO_PUSH_INDEX_SFT 0 10565 #define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL 10566 #define DB_PUSH_INFO_PUSH_SIZE_SFT 24 10567 u32 reserved32; 10568 }; 10569 10570 /* fw_status_reg (size:32b/4B) */ 10571 struct fw_status_reg { 10572 u32 fw_status; 10573 #define FW_STATUS_REG_CODE_MASK 0xffffUL 10574 #define FW_STATUS_REG_CODE_SFT 0 10575 #define FW_STATUS_REG_CODE_READY 0x8000UL 10576 #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY 10577 #define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL 10578 #define FW_STATUS_REG_RECOVERABLE 0x20000UL 10579 #define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL 10580 #define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL 10581 #define FW_STATUS_REG_SHUTDOWN 0x100000UL 10582 #define FW_STATUS_REG_CRASHED_NO_MASTER 0x200000UL 10583 #define FW_STATUS_REG_RECOVERING 0x400000UL 10584 #define FW_STATUS_REG_MANU_DEBUG_STATUS 0x800000UL 10585 }; 10586 10587 /* hcomm_status (size:64b/8B) */ 10588 struct hcomm_status { 10589 u32 sig_ver; 10590 #define HCOMM_STATUS_VER_MASK 0xffUL 10591 #define HCOMM_STATUS_VER_SFT 0 10592 #define HCOMM_STATUS_VER_LATEST 0x1UL 10593 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST 10594 #define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL 10595 #define HCOMM_STATUS_SIGNATURE_SFT 8 10596 #define HCOMM_STATUS_SIGNATURE_VAL (0x484353UL << 8) 10597 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL 10598 u32 fw_status_loc; 10599 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK 0x3UL 10600 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 10601 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG 0x0UL 10602 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC 0x1UL 10603 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 0x2UL 10604 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 0x3UL 10605 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 10606 #define HCOMM_STATUS_TRUE_OFFSET_MASK 0xfffffffcUL 10607 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 10608 }; 10609 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL 10610 10611 #endif /* _BNXT_HSI_H_ */ 10612