1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2014-2018 Broadcom Limited 5 * Copyright (c) 2018-2021 Broadcom Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * DO NOT MODIFY!!! This file is automatically generated. 12 */ 13 14 #ifndef _BNXT_HSI_H_ 15 #define _BNXT_HSI_H_ 16 17 /* hwrm_cmd_hdr (size:128b/16B) */ 18 struct hwrm_cmd_hdr { 19 __le16 req_type; 20 __le16 cmpl_ring; 21 __le16 seq_id; 22 __le16 target_id; 23 __le64 resp_addr; 24 }; 25 26 /* hwrm_resp_hdr (size:64b/8B) */ 27 struct hwrm_resp_hdr { 28 __le16 error_code; 29 __le16 req_type; 30 __le16 seq_id; 31 __le16 resp_len; 32 }; 33 34 #define CMD_DISCR_TLV_ENCAP 0x8000UL 35 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 36 37 38 #define TLV_TYPE_HWRM_REQUEST 0x1UL 39 #define TLV_TYPE_HWRM_RESPONSE 0x2UL 40 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 41 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 42 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 43 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL 44 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 45 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 46 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 47 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL 48 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL 49 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 50 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL 51 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL 52 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 53 54 55 /* tlv (size:64b/8B) */ 56 struct tlv { 57 __le16 cmd_discr; 58 u8 reserved_8b; 59 u8 flags; 60 #define TLV_FLAGS_MORE 0x1UL 61 #define TLV_FLAGS_MORE_LAST 0x0UL 62 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 63 #define TLV_FLAGS_REQUIRED 0x2UL 64 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 65 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 66 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 67 __le16 tlv_type; 68 __le16 length; 69 }; 70 71 /* input (size:128b/16B) */ 72 struct input { 73 __le16 req_type; 74 __le16 cmpl_ring; 75 __le16 seq_id; 76 __le16 target_id; 77 __le64 resp_addr; 78 }; 79 80 /* output (size:64b/8B) */ 81 struct output { 82 __le16 error_code; 83 __le16 req_type; 84 __le16 seq_id; 85 __le16 resp_len; 86 }; 87 88 /* hwrm_short_input (size:128b/16B) */ 89 struct hwrm_short_input { 90 __le16 req_type; 91 __le16 signature; 92 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 93 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 94 __le16 target_id; 95 #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL 96 #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL 97 #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS 98 __le16 size; 99 __le64 req_addr; 100 }; 101 102 /* cmd_nums (size:64b/8B) */ 103 struct cmd_nums { 104 __le16 req_type; 105 #define HWRM_VER_GET 0x0UL 106 #define HWRM_FUNC_ECHO_RESPONSE 0xbUL 107 #define HWRM_ERROR_RECOVERY_QCFG 0xcUL 108 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 109 #define HWRM_FUNC_BUF_UNRGTR 0xeUL 110 #define HWRM_FUNC_VF_CFG 0xfUL 111 #define HWRM_RESERVED1 0x10UL 112 #define HWRM_FUNC_RESET 0x11UL 113 #define HWRM_FUNC_GETFID 0x12UL 114 #define HWRM_FUNC_VF_ALLOC 0x13UL 115 #define HWRM_FUNC_VF_FREE 0x14UL 116 #define HWRM_FUNC_QCAPS 0x15UL 117 #define HWRM_FUNC_QCFG 0x16UL 118 #define HWRM_FUNC_CFG 0x17UL 119 #define HWRM_FUNC_QSTATS 0x18UL 120 #define HWRM_FUNC_CLR_STATS 0x19UL 121 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 122 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 123 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 124 #define HWRM_FUNC_DRV_RGTR 0x1dUL 125 #define HWRM_FUNC_DRV_QVER 0x1eUL 126 #define HWRM_FUNC_BUF_RGTR 0x1fUL 127 #define HWRM_PORT_PHY_CFG 0x20UL 128 #define HWRM_PORT_MAC_CFG 0x21UL 129 #define HWRM_PORT_TS_QUERY 0x22UL 130 #define HWRM_PORT_QSTATS 0x23UL 131 #define HWRM_PORT_LPBK_QSTATS 0x24UL 132 #define HWRM_PORT_CLR_STATS 0x25UL 133 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 134 #define HWRM_PORT_PHY_QCFG 0x27UL 135 #define HWRM_PORT_MAC_QCFG 0x28UL 136 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 137 #define HWRM_PORT_PHY_QCAPS 0x2aUL 138 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 139 #define HWRM_PORT_PHY_I2C_READ 0x2cUL 140 #define HWRM_PORT_LED_CFG 0x2dUL 141 #define HWRM_PORT_LED_QCFG 0x2eUL 142 #define HWRM_PORT_LED_QCAPS 0x2fUL 143 #define HWRM_QUEUE_QPORTCFG 0x30UL 144 #define HWRM_QUEUE_QCFG 0x31UL 145 #define HWRM_QUEUE_CFG 0x32UL 146 #define HWRM_FUNC_VLAN_CFG 0x33UL 147 #define HWRM_FUNC_VLAN_QCFG 0x34UL 148 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 149 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 150 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 151 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 152 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 153 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 154 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 155 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 156 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 157 #define HWRM_VNIC_ALLOC 0x40UL 158 #define HWRM_VNIC_FREE 0x41UL 159 #define HWRM_VNIC_CFG 0x42UL 160 #define HWRM_VNIC_QCFG 0x43UL 161 #define HWRM_VNIC_TPA_CFG 0x44UL 162 #define HWRM_VNIC_TPA_QCFG 0x45UL 163 #define HWRM_VNIC_RSS_CFG 0x46UL 164 #define HWRM_VNIC_RSS_QCFG 0x47UL 165 #define HWRM_VNIC_PLCMODES_CFG 0x48UL 166 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 167 #define HWRM_VNIC_QCAPS 0x4aUL 168 #define HWRM_VNIC_UPDATE 0x4bUL 169 #define HWRM_RING_ALLOC 0x50UL 170 #define HWRM_RING_FREE 0x51UL 171 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 172 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 173 #define HWRM_RING_AGGINT_QCAPS 0x54UL 174 #define HWRM_RING_SCHQ_ALLOC 0x55UL 175 #define HWRM_RING_SCHQ_CFG 0x56UL 176 #define HWRM_RING_SCHQ_FREE 0x57UL 177 #define HWRM_RING_RESET 0x5eUL 178 #define HWRM_RING_GRP_ALLOC 0x60UL 179 #define HWRM_RING_GRP_FREE 0x61UL 180 #define HWRM_RING_CFG 0x62UL 181 #define HWRM_RING_QCFG 0x63UL 182 #define HWRM_RESERVED5 0x64UL 183 #define HWRM_RESERVED6 0x65UL 184 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 185 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 186 #define HWRM_QUEUE_MPLS_QCAPS 0x80UL 187 #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL 188 #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL 189 #define HWRM_QUEUE_VLANPRI_QCAPS 0x83UL 190 #define HWRM_QUEUE_VLANPRI2PRI_QCFG 0x84UL 191 #define HWRM_QUEUE_VLANPRI2PRI_CFG 0x85UL 192 #define HWRM_QUEUE_GLOBAL_CFG 0x86UL 193 #define HWRM_QUEUE_GLOBAL_QCFG 0x87UL 194 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 195 #define HWRM_CFA_L2_FILTER_FREE 0x91UL 196 #define HWRM_CFA_L2_FILTER_CFG 0x92UL 197 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 198 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 199 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 200 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 201 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 202 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 203 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 204 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 205 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 206 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 207 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 208 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 209 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 210 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 211 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 212 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 213 #define HWRM_STAT_CTX_ALLOC 0xb0UL 214 #define HWRM_STAT_CTX_FREE 0xb1UL 215 #define HWRM_STAT_CTX_QUERY 0xb2UL 216 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 217 #define HWRM_PORT_QSTATS_EXT 0xb4UL 218 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL 219 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL 220 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL 221 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL 222 #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL 223 #define HWRM_RESERVED7 0xbaUL 224 #define HWRM_PORT_TX_FIR_CFG 0xbbUL 225 #define HWRM_PORT_TX_FIR_QCFG 0xbcUL 226 #define HWRM_PORT_ECN_QSTATS 0xbdUL 227 #define HWRM_FW_LIVEPATCH_QUERY 0xbeUL 228 #define HWRM_FW_LIVEPATCH 0xbfUL 229 #define HWRM_FW_RESET 0xc0UL 230 #define HWRM_FW_QSTATUS 0xc1UL 231 #define HWRM_FW_HEALTH_CHECK 0xc2UL 232 #define HWRM_FW_SYNC 0xc3UL 233 #define HWRM_FW_STATE_QCAPS 0xc4UL 234 #define HWRM_FW_STATE_QUIESCE 0xc5UL 235 #define HWRM_FW_STATE_BACKUP 0xc6UL 236 #define HWRM_FW_STATE_RESTORE 0xc7UL 237 #define HWRM_FW_SET_TIME 0xc8UL 238 #define HWRM_FW_GET_TIME 0xc9UL 239 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 240 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 241 #define HWRM_FW_IPC_MAILBOX 0xccUL 242 #define HWRM_FW_ECN_CFG 0xcdUL 243 #define HWRM_FW_ECN_QCFG 0xceUL 244 #define HWRM_FW_SECURE_CFG 0xcfUL 245 #define HWRM_EXEC_FWD_RESP 0xd0UL 246 #define HWRM_REJECT_FWD_RESP 0xd1UL 247 #define HWRM_FWD_RESP 0xd2UL 248 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 249 #define HWRM_OEM_CMD 0xd4UL 250 #define HWRM_PORT_PRBS_TEST 0xd5UL 251 #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL 252 #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL 253 #define HWRM_FW_STATE_UNQUIESCE 0xd8UL 254 #define HWRM_PORT_DSC_DUMP 0xd9UL 255 #define HWRM_PORT_EP_TX_QCFG 0xdaUL 256 #define HWRM_PORT_EP_TX_CFG 0xdbUL 257 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 258 #define HWRM_REG_POWER_QUERY 0xe1UL 259 #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL 260 #define HWRM_REG_POWER_HISTOGRAM 0xe3UL 261 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 262 #define HWRM_WOL_FILTER_FREE 0xf1UL 263 #define HWRM_WOL_FILTER_QCFG 0xf2UL 264 #define HWRM_WOL_REASON_QCFG 0xf3UL 265 #define HWRM_CFA_METER_QCAPS 0xf4UL 266 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 267 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 268 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 269 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 270 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 271 #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL 272 #define HWRM_CFA_VFR_ALLOC 0xfdUL 273 #define HWRM_CFA_VFR_FREE 0xfeUL 274 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 275 #define HWRM_CFA_VF_PAIR_FREE 0x101UL 276 #define HWRM_CFA_VF_PAIR_INFO 0x102UL 277 #define HWRM_CFA_FLOW_ALLOC 0x103UL 278 #define HWRM_CFA_FLOW_FREE 0x104UL 279 #define HWRM_CFA_FLOW_FLUSH 0x105UL 280 #define HWRM_CFA_FLOW_STATS 0x106UL 281 #define HWRM_CFA_FLOW_INFO 0x107UL 282 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 283 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 284 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 285 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 286 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 287 #define HWRM_CFA_PAIR_ALLOC 0x10dUL 288 #define HWRM_CFA_PAIR_FREE 0x10eUL 289 #define HWRM_CFA_PAIR_INFO 0x10fUL 290 #define HWRM_FW_IPC_MSG 0x110UL 291 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 292 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 293 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL 294 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL 295 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL 296 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL 297 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL 298 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL 299 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL 300 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL 301 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL 302 #define HWRM_CFA_COUNTER_CFG 0x11cUL 303 #define HWRM_CFA_COUNTER_QCFG 0x11dUL 304 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL 305 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL 306 #define HWRM_CFA_EEM_QCAPS 0x120UL 307 #define HWRM_CFA_EEM_CFG 0x121UL 308 #define HWRM_CFA_EEM_QCFG 0x122UL 309 #define HWRM_CFA_EEM_OP 0x123UL 310 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL 311 #define HWRM_CFA_TFLIB 0x125UL 312 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR 0x126UL 313 #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR 0x127UL 314 #define HWRM_ENGINE_CKV_STATUS 0x12eUL 315 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 316 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 317 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 318 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 319 #define HWRM_ENGINE_CKV_FLUSH 0x133UL 320 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 321 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 322 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL 323 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL 324 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 325 #define HWRM_ENGINE_QG_QUERY 0x13dUL 326 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 327 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 328 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 329 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 330 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 331 #define HWRM_ENGINE_QG_METER_BIND 0x143UL 332 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 333 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 334 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 335 #define HWRM_ENGINE_SG_QUERY 0x147UL 336 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 337 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 338 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 339 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 340 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 341 #define HWRM_ENGINE_STATS_CONFIG 0x155UL 342 #define HWRM_ENGINE_STATS_CLEAR 0x156UL 343 #define HWRM_ENGINE_STATS_QUERY 0x157UL 344 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL 345 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 346 #define HWRM_ENGINE_RQ_FREE 0x15fUL 347 #define HWRM_ENGINE_CQ_ALLOC 0x160UL 348 #define HWRM_ENGINE_CQ_FREE 0x161UL 349 #define HWRM_ENGINE_NQ_ALLOC 0x162UL 350 #define HWRM_ENGINE_NQ_FREE 0x163UL 351 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 352 #define HWRM_ENGINE_FUNC_QCFG 0x165UL 353 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 354 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 355 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 356 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 357 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 358 #define HWRM_FUNC_VF_BW_CFG 0x195UL 359 #define HWRM_FUNC_VF_BW_QCFG 0x196UL 360 #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL 361 #define HWRM_FUNC_QSTATS_EXT 0x198UL 362 #define HWRM_STAT_EXT_CTX_QUERY 0x199UL 363 #define HWRM_FUNC_SPD_CFG 0x19aUL 364 #define HWRM_FUNC_SPD_QCFG 0x19bUL 365 #define HWRM_FUNC_PTP_PIN_QCFG 0x19cUL 366 #define HWRM_FUNC_PTP_PIN_CFG 0x19dUL 367 #define HWRM_FUNC_PTP_CFG 0x19eUL 368 #define HWRM_FUNC_PTP_TS_QUERY 0x19fUL 369 #define HWRM_FUNC_PTP_EXT_CFG 0x1a0UL 370 #define HWRM_FUNC_PTP_EXT_QCFG 0x1a1UL 371 #define HWRM_FUNC_KEY_CTX_ALLOC 0x1a2UL 372 #define HWRM_FUNC_BACKING_STORE_CFG_V2 0x1a3UL 373 #define HWRM_FUNC_BACKING_STORE_QCFG_V2 0x1a4UL 374 #define HWRM_FUNC_DBR_PACING_CFG 0x1a5UL 375 #define HWRM_FUNC_DBR_PACING_QCFG 0x1a6UL 376 #define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT 0x1a7UL 377 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2 0x1a8UL 378 #define HWRM_SELFTEST_QLIST 0x200UL 379 #define HWRM_SELFTEST_EXEC 0x201UL 380 #define HWRM_SELFTEST_IRQ 0x202UL 381 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 382 #define HWRM_PCIE_QSTATS 0x204UL 383 #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL 384 #define HWRM_MFG_TIMERS_QUERY 0x206UL 385 #define HWRM_MFG_OTP_CFG 0x207UL 386 #define HWRM_MFG_OTP_QCFG 0x208UL 387 #define HWRM_MFG_HDMA_TEST 0x209UL 388 #define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL 389 #define HWRM_MFG_FRU_EEPROM_READ 0x20bUL 390 #define HWRM_MFG_SOC_IMAGE 0x20cUL 391 #define HWRM_MFG_SOC_QSTATUS 0x20dUL 392 #define HWRM_MFG_PARAM_SEEPROM_SYNC 0x20eUL 393 #define HWRM_MFG_PARAM_SEEPROM_READ 0x20fUL 394 #define HWRM_MFG_PARAM_SEEPROM_HEALTH 0x210UL 395 #define HWRM_MFG_PRVSN_EXPORT_CSR 0x211UL 396 #define HWRM_MFG_PRVSN_IMPORT_CERT 0x212UL 397 #define HWRM_MFG_PRVSN_GET_STATE 0x213UL 398 #define HWRM_MFG_GET_NVM_MEASUREMENT 0x214UL 399 #define HWRM_MFG_PSOC_QSTATUS 0x215UL 400 #define HWRM_MFG_SELFTEST_QLIST 0x216UL 401 #define HWRM_MFG_SELFTEST_EXEC 0x217UL 402 #define HWRM_TF 0x2bcUL 403 #define HWRM_TF_VERSION_GET 0x2bdUL 404 #define HWRM_TF_SESSION_OPEN 0x2c6UL 405 #define HWRM_TF_SESSION_ATTACH 0x2c7UL 406 #define HWRM_TF_SESSION_REGISTER 0x2c8UL 407 #define HWRM_TF_SESSION_UNREGISTER 0x2c9UL 408 #define HWRM_TF_SESSION_CLOSE 0x2caUL 409 #define HWRM_TF_SESSION_QCFG 0x2cbUL 410 #define HWRM_TF_SESSION_RESC_QCAPS 0x2ccUL 411 #define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL 412 #define HWRM_TF_SESSION_RESC_FREE 0x2ceUL 413 #define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL 414 #define HWRM_TF_SESSION_RESC_INFO 0x2d0UL 415 #define HWRM_TF_TBL_TYPE_GET 0x2daUL 416 #define HWRM_TF_TBL_TYPE_SET 0x2dbUL 417 #define HWRM_TF_TBL_TYPE_BULK_GET 0x2dcUL 418 #define HWRM_TF_CTXT_MEM_ALLOC 0x2e2UL 419 #define HWRM_TF_CTXT_MEM_FREE 0x2e3UL 420 #define HWRM_TF_CTXT_MEM_RGTR 0x2e4UL 421 #define HWRM_TF_CTXT_MEM_UNRGTR 0x2e5UL 422 #define HWRM_TF_EXT_EM_QCAPS 0x2e6UL 423 #define HWRM_TF_EXT_EM_OP 0x2e7UL 424 #define HWRM_TF_EXT_EM_CFG 0x2e8UL 425 #define HWRM_TF_EXT_EM_QCFG 0x2e9UL 426 #define HWRM_TF_EM_INSERT 0x2eaUL 427 #define HWRM_TF_EM_DELETE 0x2ebUL 428 #define HWRM_TF_EM_HASH_INSERT 0x2ecUL 429 #define HWRM_TF_EM_MOVE 0x2edUL 430 #define HWRM_TF_TCAM_SET 0x2f8UL 431 #define HWRM_TF_TCAM_GET 0x2f9UL 432 #define HWRM_TF_TCAM_MOVE 0x2faUL 433 #define HWRM_TF_TCAM_FREE 0x2fbUL 434 #define HWRM_TF_GLOBAL_CFG_SET 0x2fcUL 435 #define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL 436 #define HWRM_TF_IF_TBL_SET 0x2feUL 437 #define HWRM_TF_IF_TBL_GET 0x2ffUL 438 #define HWRM_SV 0x400UL 439 #define HWRM_DBG_READ_DIRECT 0xff10UL 440 #define HWRM_DBG_READ_INDIRECT 0xff11UL 441 #define HWRM_DBG_WRITE_DIRECT 0xff12UL 442 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 443 #define HWRM_DBG_DUMP 0xff14UL 444 #define HWRM_DBG_ERASE_NVM 0xff15UL 445 #define HWRM_DBG_CFG 0xff16UL 446 #define HWRM_DBG_COREDUMP_LIST 0xff17UL 447 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 448 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 449 #define HWRM_DBG_FW_CLI 0xff1aUL 450 #define HWRM_DBG_I2C_CMD 0xff1bUL 451 #define HWRM_DBG_RING_INFO_GET 0xff1cUL 452 #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL 453 #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL 454 #define HWRM_DBG_DRV_TRACE 0xff1fUL 455 #define HWRM_DBG_QCAPS 0xff20UL 456 #define HWRM_DBG_QCFG 0xff21UL 457 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL 458 #define HWRM_DBG_USEQ_ALLOC 0xff23UL 459 #define HWRM_DBG_USEQ_FREE 0xff24UL 460 #define HWRM_DBG_USEQ_FLUSH 0xff25UL 461 #define HWRM_DBG_USEQ_QCAPS 0xff26UL 462 #define HWRM_DBG_USEQ_CW_CFG 0xff27UL 463 #define HWRM_DBG_USEQ_SCHED_CFG 0xff28UL 464 #define HWRM_DBG_USEQ_RUN 0xff29UL 465 #define HWRM_DBG_USEQ_DELIVERY_REQ 0xff2aUL 466 #define HWRM_DBG_USEQ_RESP_HDR 0xff2bUL 467 #define HWRM_NVM_DEFRAG 0xffecUL 468 #define HWRM_NVM_REQ_ARBITRATION 0xffedUL 469 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 470 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 471 #define HWRM_NVM_FLUSH 0xfff0UL 472 #define HWRM_NVM_GET_VARIABLE 0xfff1UL 473 #define HWRM_NVM_SET_VARIABLE 0xfff2UL 474 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 475 #define HWRM_NVM_MODIFY 0xfff4UL 476 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 477 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 478 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 479 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 480 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 481 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 482 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 483 #define HWRM_NVM_RAW_DUMP 0xfffcUL 484 #define HWRM_NVM_READ 0xfffdUL 485 #define HWRM_NVM_WRITE 0xfffeUL 486 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 487 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 488 __le16 unused_0[3]; 489 }; 490 491 /* ret_codes (size:64b/8B) */ 492 struct ret_codes { 493 __le16 error_code; 494 #define HWRM_ERR_CODE_SUCCESS 0x0UL 495 #define HWRM_ERR_CODE_FAIL 0x1UL 496 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 497 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 498 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 499 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 500 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 501 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 502 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 503 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 504 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL 505 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL 506 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL 507 #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL 508 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL 509 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 510 #define HWRM_ERR_CODE_BUSY 0x10UL 511 #define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL 512 #define HWRM_ERR_CODE_PF_UNAVAILABLE 0x12UL 513 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 514 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 515 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 516 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 517 __le16 unused_0[3]; 518 }; 519 520 /* hwrm_err_output (size:128b/16B) */ 521 struct hwrm_err_output { 522 __le16 error_code; 523 __le16 req_type; 524 __le16 seq_id; 525 __le16 resp_len; 526 __le32 opaque_0; 527 __le16 opaque_1; 528 u8 cmd_err; 529 u8 valid; 530 }; 531 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 532 #define HWRM_MAX_REQ_LEN 128 533 #define HWRM_MAX_RESP_LEN 704 534 #define HW_HASH_INDEX_SIZE 0x80 535 #define HW_HASH_KEY_SIZE 40 536 #define HWRM_RESP_VALID_KEY 1 537 #define HWRM_TARGET_ID_BONO 0xFFF8 538 #define HWRM_TARGET_ID_KONG 0xFFF9 539 #define HWRM_TARGET_ID_APE 0xFFFA 540 #define HWRM_TARGET_ID_TOOLS 0xFFFD 541 #define HWRM_VERSION_MAJOR 1 542 #define HWRM_VERSION_MINOR 10 543 #define HWRM_VERSION_UPDATE 2 544 #define HWRM_VERSION_RSVD 73 545 #define HWRM_VERSION_STR "1.10.2.73" 546 547 /* hwrm_ver_get_input (size:192b/24B) */ 548 struct hwrm_ver_get_input { 549 __le16 req_type; 550 __le16 cmpl_ring; 551 __le16 seq_id; 552 __le16 target_id; 553 __le64 resp_addr; 554 u8 hwrm_intf_maj; 555 u8 hwrm_intf_min; 556 u8 hwrm_intf_upd; 557 u8 unused_0[5]; 558 }; 559 560 /* hwrm_ver_get_output (size:1408b/176B) */ 561 struct hwrm_ver_get_output { 562 __le16 error_code; 563 __le16 req_type; 564 __le16 seq_id; 565 __le16 resp_len; 566 u8 hwrm_intf_maj_8b; 567 u8 hwrm_intf_min_8b; 568 u8 hwrm_intf_upd_8b; 569 u8 hwrm_intf_rsvd_8b; 570 u8 hwrm_fw_maj_8b; 571 u8 hwrm_fw_min_8b; 572 u8 hwrm_fw_bld_8b; 573 u8 hwrm_fw_rsvd_8b; 574 u8 mgmt_fw_maj_8b; 575 u8 mgmt_fw_min_8b; 576 u8 mgmt_fw_bld_8b; 577 u8 mgmt_fw_rsvd_8b; 578 u8 netctrl_fw_maj_8b; 579 u8 netctrl_fw_min_8b; 580 u8 netctrl_fw_bld_8b; 581 u8 netctrl_fw_rsvd_8b; 582 __le32 dev_caps_cfg; 583 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 584 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 585 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 586 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 587 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 588 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 589 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 590 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 591 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 592 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL 593 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL 594 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL 595 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL 596 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL 597 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL 598 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE 0x8000UL 599 u8 roce_fw_maj_8b; 600 u8 roce_fw_min_8b; 601 u8 roce_fw_bld_8b; 602 u8 roce_fw_rsvd_8b; 603 char hwrm_fw_name[16]; 604 char mgmt_fw_name[16]; 605 char netctrl_fw_name[16]; 606 char active_pkg_name[16]; 607 char roce_fw_name[16]; 608 __le16 chip_num; 609 u8 chip_rev; 610 u8 chip_metal; 611 u8 chip_bond_id; 612 u8 chip_platform_type; 613 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 614 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 615 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 616 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 617 __le16 max_req_win_len; 618 __le16 max_resp_len; 619 __le16 def_req_timeout; 620 u8 flags; 621 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 622 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 623 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY_BACKING_STORE 0x4UL 624 u8 unused_0[2]; 625 u8 always_1; 626 __le16 hwrm_intf_major; 627 __le16 hwrm_intf_minor; 628 __le16 hwrm_intf_build; 629 __le16 hwrm_intf_patch; 630 __le16 hwrm_fw_major; 631 __le16 hwrm_fw_minor; 632 __le16 hwrm_fw_build; 633 __le16 hwrm_fw_patch; 634 __le16 mgmt_fw_major; 635 __le16 mgmt_fw_minor; 636 __le16 mgmt_fw_build; 637 __le16 mgmt_fw_patch; 638 __le16 netctrl_fw_major; 639 __le16 netctrl_fw_minor; 640 __le16 netctrl_fw_build; 641 __le16 netctrl_fw_patch; 642 __le16 roce_fw_major; 643 __le16 roce_fw_minor; 644 __le16 roce_fw_build; 645 __le16 roce_fw_patch; 646 __le16 max_ext_req_len; 647 __le16 max_req_timeout; 648 u8 unused_1[3]; 649 u8 valid; 650 }; 651 652 /* eject_cmpl (size:128b/16B) */ 653 struct eject_cmpl { 654 __le16 type; 655 #define EJECT_CMPL_TYPE_MASK 0x3fUL 656 #define EJECT_CMPL_TYPE_SFT 0 657 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 658 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 659 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL 660 #define EJECT_CMPL_FLAGS_SFT 6 661 #define EJECT_CMPL_FLAGS_ERROR 0x40UL 662 __le16 len; 663 __le32 opaque; 664 __le16 v; 665 #define EJECT_CMPL_V 0x1UL 666 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL 667 #define EJECT_CMPL_ERRORS_SFT 1 668 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL 669 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 670 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1) 671 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1) 672 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1) 673 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1) 674 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH 675 __le16 reserved16; 676 __le32 unused_2; 677 }; 678 679 /* hwrm_cmpl (size:128b/16B) */ 680 struct hwrm_cmpl { 681 __le16 type; 682 #define CMPL_TYPE_MASK 0x3fUL 683 #define CMPL_TYPE_SFT 0 684 #define CMPL_TYPE_HWRM_DONE 0x20UL 685 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 686 __le16 sequence_id; 687 __le32 unused_1; 688 __le32 v; 689 #define CMPL_V 0x1UL 690 __le32 unused_3; 691 }; 692 693 /* hwrm_fwd_req_cmpl (size:128b/16B) */ 694 struct hwrm_fwd_req_cmpl { 695 __le16 req_len_type; 696 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 697 #define FWD_REQ_CMPL_TYPE_SFT 0 698 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 699 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 700 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 701 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 702 __le16 source_id; 703 __le32 unused0; 704 __le32 req_buf_addr_v[2]; 705 #define FWD_REQ_CMPL_V 0x1UL 706 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 707 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 708 }; 709 710 /* hwrm_fwd_resp_cmpl (size:128b/16B) */ 711 struct hwrm_fwd_resp_cmpl { 712 __le16 type; 713 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 714 #define FWD_RESP_CMPL_TYPE_SFT 0 715 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 716 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 717 __le16 source_id; 718 __le16 resp_len; 719 __le16 unused_1; 720 __le32 resp_buf_addr_v[2]; 721 #define FWD_RESP_CMPL_V 0x1UL 722 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 723 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 724 }; 725 726 /* hwrm_async_event_cmpl (size:128b/16B) */ 727 struct hwrm_async_event_cmpl { 728 __le16 type; 729 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 730 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 731 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 732 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 733 __le16 event_id; 734 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 735 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 736 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 737 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 738 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 739 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 740 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 741 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 742 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 743 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL 744 #define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG 0xaUL 745 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 746 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 747 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 748 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 749 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 750 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 751 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 752 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 753 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 754 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 755 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 756 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 757 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL 758 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 759 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 760 #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL 761 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL 762 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL 763 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL 764 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL 765 #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL 766 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL 767 #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL 768 #define ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST 0x42UL 769 #define ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE 0x43UL 770 #define ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP 0x44UL 771 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT 0x45UL 772 #define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD 0x46UL 773 #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x47UL 774 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 775 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 776 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 777 __le32 event_data2; 778 u8 opaque_v; 779 #define ASYNC_EVENT_CMPL_V 0x1UL 780 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 781 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 782 u8 timestamp_lo; 783 __le16 timestamp_hi; 784 __le32 event_data1; 785 }; 786 787 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 788 struct hwrm_async_event_cmpl_link_status_change { 789 __le16 type; 790 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 791 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 792 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 793 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 794 __le16 event_id; 795 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 796 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 797 __le32 event_data2; 798 u8 opaque_v; 799 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 800 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 801 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 802 u8 timestamp_lo; 803 __le16 timestamp_hi; 804 __le32 event_data1; 805 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 806 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 807 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 808 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 809 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 810 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 811 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 812 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 813 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 814 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 815 }; 816 817 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 818 struct hwrm_async_event_cmpl_port_conn_not_allowed { 819 __le16 type; 820 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 821 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 822 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 823 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 824 __le16 event_id; 825 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 826 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 827 __le32 event_data2; 828 u8 opaque_v; 829 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 830 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 831 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 832 u8 timestamp_lo; 833 __le16 timestamp_hi; 834 __le32 event_data1; 835 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 836 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 837 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 838 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 839 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 840 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 841 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 842 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 843 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 844 }; 845 846 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 847 struct hwrm_async_event_cmpl_link_speed_cfg_change { 848 __le16 type; 849 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 850 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 851 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 852 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 853 __le16 event_id; 854 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 855 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 856 __le32 event_data2; 857 u8 opaque_v; 858 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 859 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 860 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 861 u8 timestamp_lo; 862 __le16 timestamp_hi; 863 __le32 event_data1; 864 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 865 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 866 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 867 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 868 }; 869 870 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ 871 struct hwrm_async_event_cmpl_reset_notify { 872 __le16 type; 873 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL 874 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 875 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 876 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 877 __le16 event_id; 878 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 879 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 880 __le32 event_data2; 881 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK 0xffffUL 882 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0 883 u8 opaque_v; 884 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 885 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL 886 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 887 u8 timestamp_lo; 888 __le16 timestamp_hi; 889 __le32 event_data1; 890 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL 891 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0 892 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL 893 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL 894 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 895 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL 896 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8 897 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 898 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 899 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 900 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET (0x4UL << 8) 901 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION (0x5UL << 8) 902 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION 903 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 904 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 905 }; 906 907 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ 908 struct hwrm_async_event_cmpl_error_recovery { 909 __le16 type; 910 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL 911 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 912 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 913 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 914 __le16 event_id; 915 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL 916 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 917 __le32 event_data2; 918 u8 opaque_v; 919 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL 920 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL 921 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 922 u8 timestamp_lo; 923 __le16 timestamp_hi; 924 __le32 event_data1; 925 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL 926 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0 927 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL 928 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL 929 }; 930 931 /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */ 932 struct hwrm_async_event_cmpl_ring_monitor_msg { 933 __le16 type; 934 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK 0x3fUL 935 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0 936 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 0x2eUL 937 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 938 __le16 event_id; 939 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL 940 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 941 __le32 event_data2; 942 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL 943 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0 944 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX 0x0UL 945 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX 0x1UL 946 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 0x2UL 947 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 948 u8 opaque_v; 949 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V 0x1UL 950 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL 951 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1 952 u8 timestamp_lo; 953 __le16 timestamp_hi; 954 __le32 event_data1; 955 }; 956 957 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 958 struct hwrm_async_event_cmpl_vf_cfg_change { 959 __le16 type; 960 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 961 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 962 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 963 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 964 __le16 event_id; 965 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 966 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 967 __le32 event_data2; 968 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK 0xffffUL 969 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0 970 u8 opaque_v; 971 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 972 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 973 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 974 u8 timestamp_lo; 975 __le16 timestamp_hi; 976 __le32 event_data1; 977 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 978 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 979 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 980 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 981 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 982 }; 983 984 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ 985 struct hwrm_async_event_cmpl_default_vnic_change { 986 __le16 type; 987 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL 988 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0 989 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 990 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 991 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL 992 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6 993 __le16 event_id; 994 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL 995 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 996 __le32 event_data2; 997 u8 opaque_v; 998 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL 999 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL 1000 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1 1001 u8 timestamp_lo; 1002 __le16 timestamp_hi; 1003 __le32 event_data1; 1004 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL 1005 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0 1006 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL 1007 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL 1008 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 1009 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL 1010 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2 1011 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL 1012 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10 1013 }; 1014 1015 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ 1016 struct hwrm_async_event_cmpl_hw_flow_aged { 1017 __le16 type; 1018 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL 1019 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 1020 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1021 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 1022 __le16 event_id; 1023 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL 1024 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 1025 __le32 event_data2; 1026 u8 opaque_v; 1027 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL 1028 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL 1029 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 1030 u8 timestamp_lo; 1031 __le16 timestamp_hi; 1032 __le32 event_data1; 1033 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL 1034 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0 1035 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL 1036 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31) 1037 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31) 1038 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX 1039 }; 1040 1041 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ 1042 struct hwrm_async_event_cmpl_eem_cache_flush_req { 1043 __le16 type; 1044 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL 1045 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0 1046 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1047 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 1048 __le16 event_id; 1049 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 1050 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 1051 __le32 event_data2; 1052 u8 opaque_v; 1053 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL 1054 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL 1055 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 1056 u8 timestamp_lo; 1057 __le16 timestamp_hi; 1058 __le32 event_data1; 1059 }; 1060 1061 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ 1062 struct hwrm_async_event_cmpl_eem_cache_flush_done { 1063 __le16 type; 1064 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL 1065 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0 1066 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1067 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 1068 __le16 event_id; 1069 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 1070 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 1071 __le32 event_data2; 1072 u8 opaque_v; 1073 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL 1074 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL 1075 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 1076 u8 timestamp_lo; 1077 __le16 timestamp_hi; 1078 __le32 event_data1; 1079 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL 1080 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0 1081 }; 1082 1083 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ 1084 struct hwrm_async_event_cmpl_deferred_response { 1085 __le16 type; 1086 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK 0x3fUL 1087 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0 1088 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1089 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 1090 __le16 event_id; 1091 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL 1092 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 1093 __le32 event_data2; 1094 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL 1095 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0 1096 u8 opaque_v; 1097 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V 0x1UL 1098 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL 1099 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1 1100 u8 timestamp_lo; 1101 __le16 timestamp_hi; 1102 __le32 event_data1; 1103 }; 1104 1105 /* hwrm_async_event_cmpl_echo_request (size:128b/16B) */ 1106 struct hwrm_async_event_cmpl_echo_request { 1107 __le16 type; 1108 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK 0x3fUL 1109 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0 1110 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1111 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 1112 __le16 event_id; 1113 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 0x42UL 1114 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 1115 __le32 event_data2; 1116 u8 opaque_v; 1117 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_V 0x1UL 1118 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK 0xfeUL 1119 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1 1120 u8 timestamp_lo; 1121 __le16 timestamp_hi; 1122 __le32 event_data1; 1123 }; 1124 1125 /* hwrm_async_event_cmpl_phc_update (size:128b/16B) */ 1126 struct hwrm_async_event_cmpl_phc_update { 1127 __le16 type; 1128 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_MASK 0x3fUL 1129 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_SFT 0 1130 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1131 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT 1132 __le16 event_id; 1133 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 0x43UL 1134 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 1135 __le32 event_data2; 1136 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_MASK 0xffffUL 1137 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_SFT 0 1138 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_MASK 0xffff0000UL 1139 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_SFT 16 1140 u8 opaque_v; 1141 #define ASYNC_EVENT_CMPL_PHC_UPDATE_V 0x1UL 1142 #define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_MASK 0xfeUL 1143 #define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_SFT 1 1144 u8 timestamp_lo; 1145 __le16 timestamp_hi; 1146 __le32 event_data1; 1147 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK 0xfUL 1148 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT 0 1149 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_MASTER 0x1UL 1150 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_SECONDARY 0x2UL 1151 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_FAILOVER 0x3UL 1152 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE 0x4UL 1153 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE 1154 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK 0xffff0UL 1155 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT 4 1156 }; 1157 1158 /* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */ 1159 struct hwrm_async_event_cmpl_pps_timestamp { 1160 __le16 type; 1161 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK 0x3fUL 1162 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0 1163 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1164 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 1165 __le16 event_id; 1166 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 0x44UL 1167 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 1168 __le32 event_data2; 1169 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE 0x1UL 1170 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL 0x0UL 1171 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 0x1UL 1172 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 1173 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK 0xeUL 1174 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT 1 1175 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK 0xffff0UL 1176 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT 4 1177 u8 opaque_v; 1178 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V 0x1UL 1179 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK 0xfeUL 1180 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1 1181 u8 timestamp_lo; 1182 __le16 timestamp_hi; 1183 __le32 event_data1; 1184 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK 0xffffffffUL 1185 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT 0 1186 }; 1187 1188 /* hwrm_async_event_cmpl_error_report (size:128b/16B) */ 1189 struct hwrm_async_event_cmpl_error_report { 1190 __le16 type; 1191 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK 0x3fUL 1192 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0 1193 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1194 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 1195 __le16 event_id; 1196 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 0x45UL 1197 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 1198 __le32 event_data2; 1199 u8 opaque_v; 1200 #define ASYNC_EVENT_CMPL_ERROR_REPORT_V 0x1UL 1201 #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK 0xfeUL 1202 #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1 1203 u8 timestamp_lo; 1204 __le16 timestamp_hi; 1205 __le32 event_data1; 1206 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1207 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0 1208 }; 1209 1210 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */ 1211 struct hwrm_async_event_cmpl_hwrm_error { 1212 __le16 type; 1213 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL 1214 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 1215 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1216 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 1217 __le16 event_id; 1218 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL 1219 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 1220 __le32 event_data2; 1221 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL 1222 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 1223 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL 1224 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL 1225 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL 1226 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 1227 u8 opaque_v; 1228 #define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL 1229 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL 1230 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 1231 u8 timestamp_lo; 1232 __le16 timestamp_hi; 1233 __le32 event_data1; 1234 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL 1235 }; 1236 1237 /* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */ 1238 struct hwrm_async_event_cmpl_error_report_base { 1239 __le16 type; 1240 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK 0x3fUL 1241 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0 1242 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1243 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 1244 __le16 event_id; 1245 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 0x45UL 1246 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 1247 __le32 event_data2; 1248 u8 opaque_v; 1249 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V 0x1UL 1250 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK 0xfeUL 1251 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1 1252 u8 timestamp_lo; 1253 __le16 timestamp_hi; 1254 __le32 event_data1; 1255 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1256 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT 0 1257 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED 0x0UL 1258 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 1259 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 1260 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM 0x3UL 1261 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL 1262 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 1263 }; 1264 1265 /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ 1266 struct hwrm_async_event_cmpl_error_report_pause_storm { 1267 __le16 type; 1268 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK 0x3fUL 1269 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT 0 1270 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1271 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 1272 __le16 event_id; 1273 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 0x45UL 1274 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 1275 __le32 event_data2; 1276 u8 opaque_v; 1277 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V 0x1UL 1278 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK 0xfeUL 1279 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1 1280 u8 timestamp_lo; 1281 __le16 timestamp_hi; 1282 __le32 event_data1; 1283 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1284 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT 0 1285 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 1286 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 1287 }; 1288 1289 /* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */ 1290 struct hwrm_async_event_cmpl_error_report_invalid_signal { 1291 __le16 type; 1292 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK 0x3fUL 1293 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT 0 1294 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1295 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 1296 __le16 event_id; 1297 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 0x45UL 1298 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 1299 __le32 event_data2; 1300 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK 0xffUL 1301 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT 0 1302 u8 opaque_v; 1303 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V 0x1UL 1304 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK 0xfeUL 1305 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1 1306 u8 timestamp_lo; 1307 __le16 timestamp_hi; 1308 __le32 event_data1; 1309 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1310 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT 0 1311 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 1312 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 1313 }; 1314 1315 /* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */ 1316 struct hwrm_async_event_cmpl_error_report_nvm { 1317 __le16 type; 1318 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK 0x3fUL 1319 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0 1320 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1321 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 1322 __le16 event_id; 1323 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 0x45UL 1324 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 1325 __le32 event_data2; 1326 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK 0xffffffffUL 1327 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT 0 1328 u8 opaque_v; 1329 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V 0x1UL 1330 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK 0xfeUL 1331 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1 1332 u8 timestamp_lo; 1333 __le16 timestamp_hi; 1334 __le32 event_data1; 1335 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1336 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT 0 1337 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 0x3UL 1338 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 1339 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK 0xff00UL 1340 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT 8 1341 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE (0x1UL << 8) 1342 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE (0x2UL << 8) 1343 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE 1344 }; 1345 1346 /* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */ 1347 struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold { 1348 __le16 type; 1349 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK 0x3fUL 1350 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT 0 1351 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1352 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT 1353 __le16 event_id; 1354 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT 0x45UL 1355 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT 1356 __le32 event_data2; 1357 u8 opaque_v; 1358 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V 0x1UL 1359 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK 0xfeUL 1360 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT 1 1361 u8 timestamp_lo; 1362 __le16 timestamp_hi; 1363 __le32 event_data1; 1364 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1365 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT 0 1366 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL 1367 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 1368 }; 1369 1370 /* hwrm_func_reset_input (size:192b/24B) */ 1371 struct hwrm_func_reset_input { 1372 __le16 req_type; 1373 __le16 cmpl_ring; 1374 __le16 seq_id; 1375 __le16 target_id; 1376 __le64 resp_addr; 1377 __le32 enables; 1378 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 1379 __le16 vf_id; 1380 u8 func_reset_level; 1381 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 1382 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 1383 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 1384 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 1385 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 1386 u8 unused_0; 1387 }; 1388 1389 /* hwrm_func_reset_output (size:128b/16B) */ 1390 struct hwrm_func_reset_output { 1391 __le16 error_code; 1392 __le16 req_type; 1393 __le16 seq_id; 1394 __le16 resp_len; 1395 u8 unused_0[7]; 1396 u8 valid; 1397 }; 1398 1399 /* hwrm_func_getfid_input (size:192b/24B) */ 1400 struct hwrm_func_getfid_input { 1401 __le16 req_type; 1402 __le16 cmpl_ring; 1403 __le16 seq_id; 1404 __le16 target_id; 1405 __le64 resp_addr; 1406 __le32 enables; 1407 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 1408 __le16 pci_id; 1409 u8 unused_0[2]; 1410 }; 1411 1412 /* hwrm_func_getfid_output (size:128b/16B) */ 1413 struct hwrm_func_getfid_output { 1414 __le16 error_code; 1415 __le16 req_type; 1416 __le16 seq_id; 1417 __le16 resp_len; 1418 __le16 fid; 1419 u8 unused_0[5]; 1420 u8 valid; 1421 }; 1422 1423 /* hwrm_func_vf_alloc_input (size:192b/24B) */ 1424 struct hwrm_func_vf_alloc_input { 1425 __le16 req_type; 1426 __le16 cmpl_ring; 1427 __le16 seq_id; 1428 __le16 target_id; 1429 __le64 resp_addr; 1430 __le32 enables; 1431 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 1432 __le16 first_vf_id; 1433 __le16 num_vfs; 1434 }; 1435 1436 /* hwrm_func_vf_alloc_output (size:128b/16B) */ 1437 struct hwrm_func_vf_alloc_output { 1438 __le16 error_code; 1439 __le16 req_type; 1440 __le16 seq_id; 1441 __le16 resp_len; 1442 __le16 first_vf_id; 1443 u8 unused_0[5]; 1444 u8 valid; 1445 }; 1446 1447 /* hwrm_func_vf_free_input (size:192b/24B) */ 1448 struct hwrm_func_vf_free_input { 1449 __le16 req_type; 1450 __le16 cmpl_ring; 1451 __le16 seq_id; 1452 __le16 target_id; 1453 __le64 resp_addr; 1454 __le32 enables; 1455 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 1456 __le16 first_vf_id; 1457 __le16 num_vfs; 1458 }; 1459 1460 /* hwrm_func_vf_free_output (size:128b/16B) */ 1461 struct hwrm_func_vf_free_output { 1462 __le16 error_code; 1463 __le16 req_type; 1464 __le16 seq_id; 1465 __le16 resp_len; 1466 u8 unused_0[7]; 1467 u8 valid; 1468 }; 1469 1470 /* hwrm_func_vf_cfg_input (size:448b/56B) */ 1471 struct hwrm_func_vf_cfg_input { 1472 __le16 req_type; 1473 __le16 cmpl_ring; 1474 __le16 seq_id; 1475 __le16 target_id; 1476 __le64 resp_addr; 1477 __le32 enables; 1478 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 1479 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 1480 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 1481 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 1482 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 1483 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 1484 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 1485 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 1486 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 1487 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 1488 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 1489 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 1490 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_KEY_CTXS 0x1000UL 1491 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_KEY_CTXS 0x2000UL 1492 __le16 mtu; 1493 __le16 guest_vlan; 1494 __le16 async_event_cr; 1495 u8 dflt_mac_addr[6]; 1496 __le32 flags; 1497 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 1498 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 1499 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 1500 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 1501 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 1502 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 1503 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 1504 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 1505 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x100UL 1506 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x200UL 1507 __le16 num_rsscos_ctxs; 1508 __le16 num_cmpl_rings; 1509 __le16 num_tx_rings; 1510 __le16 num_rx_rings; 1511 __le16 num_l2_ctxs; 1512 __le16 num_vnics; 1513 __le16 num_stat_ctxs; 1514 __le16 num_hw_ring_grps; 1515 __le16 num_tx_key_ctxs; 1516 __le16 num_rx_key_ctxs; 1517 }; 1518 1519 /* hwrm_func_vf_cfg_output (size:128b/16B) */ 1520 struct hwrm_func_vf_cfg_output { 1521 __le16 error_code; 1522 __le16 req_type; 1523 __le16 seq_id; 1524 __le16 resp_len; 1525 u8 unused_0[7]; 1526 u8 valid; 1527 }; 1528 1529 /* hwrm_func_qcaps_input (size:192b/24B) */ 1530 struct hwrm_func_qcaps_input { 1531 __le16 req_type; 1532 __le16 cmpl_ring; 1533 __le16 seq_id; 1534 __le16 target_id; 1535 __le64 resp_addr; 1536 __le16 fid; 1537 u8 unused_0[6]; 1538 }; 1539 1540 /* hwrm_func_qcaps_output (size:768b/96B) */ 1541 struct hwrm_func_qcaps_output { 1542 __le16 error_code; 1543 __le16 req_type; 1544 __le16 seq_id; 1545 __le16 resp_len; 1546 __le16 fid; 1547 __le16 port_id; 1548 __le32 flags; 1549 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1550 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 1551 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1552 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1553 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1554 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1555 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1556 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1557 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1558 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1559 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 1560 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 1561 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 1562 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 1563 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 1564 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 1565 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 1566 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 1567 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 1568 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 1569 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 1570 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL 1571 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL 1572 #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL 1573 #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL 1574 #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL 1575 #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL 1576 #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL 1577 #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL 1578 #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL 1579 #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL 1580 #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL 1581 u8 mac_address[6]; 1582 __le16 max_rsscos_ctx; 1583 __le16 max_cmpl_rings; 1584 __le16 max_tx_rings; 1585 __le16 max_rx_rings; 1586 __le16 max_l2_ctxs; 1587 __le16 max_vnics; 1588 __le16 first_vf_id; 1589 __le16 max_vfs; 1590 __le16 max_stat_ctx; 1591 __le32 max_encap_records; 1592 __le32 max_decap_records; 1593 __le32 max_tx_em_flows; 1594 __le32 max_tx_wm_flows; 1595 __le32 max_rx_em_flows; 1596 __le32 max_rx_wm_flows; 1597 __le32 max_mcast_filters; 1598 __le32 max_flow_id; 1599 __le32 max_hw_ring_grps; 1600 __le16 max_sp_tx_rings; 1601 __le16 max_msix_vfs; 1602 __le32 flags_ext; 1603 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL 1604 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL 1605 #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL 1606 #define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT 0x8UL 1607 #define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT 0x10UL 1608 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL 1609 #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL 1610 #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL 1611 #define FUNC_QCAPS_RESP_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED 0x100UL 1612 #define FUNC_QCAPS_RESP_FLAGS_EXT_SOC_SPD_SUPPORTED 0x200UL 1613 #define FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED 0x400UL 1614 #define FUNC_QCAPS_RESP_FLAGS_EXT_FAST_RESET_CAPABLE 0x800UL 1615 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_METADATA_CFG_CAPABLE 0x1000UL 1616 #define FUNC_QCAPS_RESP_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED 0x2000UL 1617 #define FUNC_QCAPS_RESP_FLAGS_EXT_BD_METADATA_SUPPORTED 0x4000UL 1618 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECHO_REQUEST_SUPPORTED 0x8000UL 1619 #define FUNC_QCAPS_RESP_FLAGS_EXT_NPAR_1_2_SUPPORTED 0x10000UL 1620 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PTM_SUPPORTED 0x20000UL 1621 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED 0x40000UL 1622 #define FUNC_QCAPS_RESP_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED 0x80000UL 1623 #define FUNC_QCAPS_RESP_FLAGS_EXT_PARTITION_BW_SUPPORTED 0x100000UL 1624 #define FUNC_QCAPS_RESP_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED 0x200000UL 1625 #define FUNC_QCAPS_RESP_FLAGS_EXT_KTLS_SUPPORTED 0x400000UL 1626 #define FUNC_QCAPS_RESP_FLAGS_EXT_EP_RATE_CONTROL 0x800000UL 1627 #define FUNC_QCAPS_RESP_FLAGS_EXT_MIN_BW_SUPPORTED 0x1000000UL 1628 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_COAL_CMPL_CAP 0x2000000UL 1629 #define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_SUPPORTED 0x4000000UL 1630 #define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_REQUIRED 0x8000000UL 1631 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED 0x10000000UL 1632 #define FUNC_QCAPS_RESP_FLAGS_EXT_DBR_PACING_SUPPORTED 0x20000000UL 1633 u8 max_schqs; 1634 u8 mpc_chnls_cap; 1635 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL 1636 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE 0x2UL 1637 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA 0x4UL 1638 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA 0x8UL 1639 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE 0x10UL 1640 __le16 max_key_ctxs_alloc; 1641 u8 unused_1[7]; 1642 u8 valid; 1643 }; 1644 1645 /* hwrm_func_qcfg_input (size:192b/24B) */ 1646 struct hwrm_func_qcfg_input { 1647 __le16 req_type; 1648 __le16 cmpl_ring; 1649 __le16 seq_id; 1650 __le16 target_id; 1651 __le64 resp_addr; 1652 __le16 fid; 1653 u8 unused_0[6]; 1654 }; 1655 1656 /* hwrm_func_qcfg_output (size:896b/112B) */ 1657 struct hwrm_func_qcfg_output { 1658 __le16 error_code; 1659 __le16 req_type; 1660 __le16 seq_id; 1661 __le16 resp_len; 1662 __le16 fid; 1663 __le16 port_id; 1664 __le16 vlan; 1665 __le16 flags; 1666 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1667 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1668 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 1669 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 1670 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 1671 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 1672 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 1673 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL 1674 #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL 1675 #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL 1676 #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL 1677 #define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL 1678 #define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED 0x1000UL 1679 #define FUNC_QCFG_RESP_FLAGS_MULTI_ROOT 0x2000UL 1680 #define FUNC_QCFG_RESP_FLAGS_ENABLE_RDMA_SRIOV 0x4000UL 1681 u8 mac_address[6]; 1682 __le16 pci_id; 1683 __le16 alloc_rsscos_ctx; 1684 __le16 alloc_cmpl_rings; 1685 __le16 alloc_tx_rings; 1686 __le16 alloc_rx_rings; 1687 __le16 alloc_l2_ctx; 1688 __le16 alloc_vnics; 1689 __le16 admin_mtu; 1690 __le16 mru; 1691 __le16 stat_ctx_id; 1692 u8 port_partition_type; 1693 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1694 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1695 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1696 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1697 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 1698 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_2 0x5UL 1699 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 1700 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 1701 u8 port_pf_cnt; 1702 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 1703 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 1704 __le16 dflt_vnic_id; 1705 __le16 max_mtu_configured; 1706 __le32 min_bw; 1707 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1708 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 1709 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 1710 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 1711 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 1712 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 1713 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1714 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 1715 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1716 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1717 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1718 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1719 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1720 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1721 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 1722 __le32 max_bw; 1723 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1724 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 1725 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 1726 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 1727 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 1728 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 1729 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1730 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 1731 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1732 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1733 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1734 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1735 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1736 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1737 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 1738 u8 evb_mode; 1739 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 1740 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 1741 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 1742 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 1743 u8 options; 1744 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1745 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 1746 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1747 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1748 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 1749 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1750 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 1751 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1752 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1753 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1754 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 1755 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 1756 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 1757 __le16 alloc_vfs; 1758 __le32 alloc_mcast_filters; 1759 __le32 alloc_hw_ring_grps; 1760 __le16 alloc_sp_tx_rings; 1761 __le16 alloc_stat_ctx; 1762 __le16 alloc_msix; 1763 __le16 registered_vfs; 1764 __le16 l2_doorbell_bar_size_kb; 1765 u8 unused_1; 1766 u8 always_1; 1767 __le32 reset_addr_poll; 1768 __le16 legacy_l2_db_size_kb; 1769 __le16 svif_info; 1770 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL 1771 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0 1772 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL 1773 u8 mpc_chnls; 1774 #define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED 0x1UL 1775 #define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED 0x2UL 1776 #define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL 1777 #define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL 1778 #define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL 1779 u8 unused_2[3]; 1780 __le32 partition_min_bw; 1781 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1782 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_SFT 0 1783 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE 0x10000000UL 1784 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 1785 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 1786 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES 1787 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1788 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 1789 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1790 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 1791 __le32 partition_max_bw; 1792 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1793 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_SFT 0 1794 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE 0x10000000UL 1795 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 1796 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 1797 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES 1798 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1799 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 1800 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1801 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 1802 __le16 host_mtu; 1803 __le16 alloc_tx_key_ctxs; 1804 __le16 alloc_rx_key_ctxs; 1805 u8 unused_3[5]; 1806 u8 valid; 1807 }; 1808 1809 /* hwrm_func_cfg_input (size:896b/112B) */ 1810 struct hwrm_func_cfg_input { 1811 __le16 req_type; 1812 __le16 cmpl_ring; 1813 __le16 seq_id; 1814 __le16 target_id; 1815 __le64 resp_addr; 1816 __le16 fid; 1817 __le16 num_msix; 1818 __le32 flags; 1819 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 1820 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 1821 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 1822 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 1823 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 1824 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 1825 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 1826 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 1827 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 1828 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 1829 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 1830 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 1831 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 1832 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 1833 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 1834 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 1835 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 1836 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL 1837 #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL 1838 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL 1839 #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL 1840 #define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS 0x4000000UL 1841 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x8000000UL 1842 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL 1843 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_ENABLE 0x20000000UL 1844 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_DISABLE 0x40000000UL 1845 __le32 enables; 1846 #define FUNC_CFG_REQ_ENABLES_ADMIN_MTU 0x1UL 1847 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1848 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1849 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1850 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1851 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1852 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1853 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1854 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1855 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1856 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1857 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1858 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1859 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1860 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1861 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1862 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1863 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1864 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1865 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1866 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 1867 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 1868 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 1869 #define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL 1870 #define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL 1871 #define FUNC_CFG_REQ_ENABLES_MPC_CHNLS 0x2000000UL 1872 #define FUNC_CFG_REQ_ENABLES_PARTITION_MIN_BW 0x4000000UL 1873 #define FUNC_CFG_REQ_ENABLES_PARTITION_MAX_BW 0x8000000UL 1874 #define FUNC_CFG_REQ_ENABLES_TPID 0x10000000UL 1875 #define FUNC_CFG_REQ_ENABLES_HOST_MTU 0x20000000UL 1876 #define FUNC_CFG_REQ_ENABLES_TX_KEY_CTXS 0x40000000UL 1877 #define FUNC_CFG_REQ_ENABLES_RX_KEY_CTXS 0x80000000UL 1878 __le16 admin_mtu; 1879 __le16 mru; 1880 __le16 num_rsscos_ctxs; 1881 __le16 num_cmpl_rings; 1882 __le16 num_tx_rings; 1883 __le16 num_rx_rings; 1884 __le16 num_l2_ctxs; 1885 __le16 num_vnics; 1886 __le16 num_stat_ctxs; 1887 __le16 num_hw_ring_grps; 1888 u8 dflt_mac_addr[6]; 1889 __le16 dflt_vlan; 1890 __be32 dflt_ip_addr[4]; 1891 __le32 min_bw; 1892 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1893 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 1894 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 1895 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 1896 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 1897 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 1898 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1899 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 1900 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1901 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1902 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1903 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1904 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1905 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1906 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1907 __le32 max_bw; 1908 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1909 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1910 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1911 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1912 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1913 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1914 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1915 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1916 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1917 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1918 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1919 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1920 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1921 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1922 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1923 __le16 async_event_cr; 1924 u8 vlan_antispoof_mode; 1925 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1926 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1927 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1928 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1929 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 1930 u8 allowed_vlan_pris; 1931 u8 evb_mode; 1932 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1933 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1934 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1935 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 1936 u8 options; 1937 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1938 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 1939 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1940 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1941 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 1942 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1943 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 1944 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1945 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1946 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1947 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 1948 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 1949 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 1950 __le16 num_mcast_filters; 1951 __le16 schq_id; 1952 __le16 mpc_chnls; 1953 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE 0x1UL 1954 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE 0x2UL 1955 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE 0x4UL 1956 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE 0x8UL 1957 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE 0x10UL 1958 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE 0x20UL 1959 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE 0x40UL 1960 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE 0x80UL 1961 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE 0x100UL 1962 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE 0x200UL 1963 __le32 partition_min_bw; 1964 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1965 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_SFT 0 1966 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE 0x10000000UL 1967 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 1968 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 1969 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES 1970 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1971 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 1972 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1973 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 1974 __le32 partition_max_bw; 1975 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1976 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_SFT 0 1977 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE 0x10000000UL 1978 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 1979 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 1980 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES 1981 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1982 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 1983 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1984 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 1985 __be16 tpid; 1986 __le16 host_mtu; 1987 __le16 num_tx_key_ctxs; 1988 __le16 num_rx_key_ctxs; 1989 u8 unused_0[4]; 1990 }; 1991 1992 /* hwrm_func_cfg_output (size:128b/16B) */ 1993 struct hwrm_func_cfg_output { 1994 __le16 error_code; 1995 __le16 req_type; 1996 __le16 seq_id; 1997 __le16 resp_len; 1998 u8 unused_0[7]; 1999 u8 valid; 2000 }; 2001 2002 /* hwrm_func_cfg_cmd_err (size:64b/8B) */ 2003 struct hwrm_func_cfg_cmd_err { 2004 u8 code; 2005 #define FUNC_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 2006 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_RANGE 0x1UL 2007 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_MORE_THAN_MAX 0x2UL 2008 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_UNSUPPORTED 0x3UL 2009 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT 0x4UL 2010 #define FUNC_CFG_CMD_ERR_CODE_LAST FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT 2011 u8 unused_0[7]; 2012 }; 2013 2014 /* hwrm_func_qstats_input (size:192b/24B) */ 2015 struct hwrm_func_qstats_input { 2016 __le16 req_type; 2017 __le16 cmpl_ring; 2018 __le16 seq_id; 2019 __le16 target_id; 2020 __le64 resp_addr; 2021 __le16 fid; 2022 u8 flags; 2023 #define FUNC_QSTATS_REQ_FLAGS_UNUSED 0x0UL 2024 #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL 2025 #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL 2026 #define FUNC_QSTATS_REQ_FLAGS_LAST FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 2027 u8 unused_0[5]; 2028 }; 2029 2030 /* hwrm_func_qstats_output (size:1408b/176B) */ 2031 struct hwrm_func_qstats_output { 2032 __le16 error_code; 2033 __le16 req_type; 2034 __le16 seq_id; 2035 __le16 resp_len; 2036 __le64 tx_ucast_pkts; 2037 __le64 tx_mcast_pkts; 2038 __le64 tx_bcast_pkts; 2039 __le64 tx_discard_pkts; 2040 __le64 tx_drop_pkts; 2041 __le64 tx_ucast_bytes; 2042 __le64 tx_mcast_bytes; 2043 __le64 tx_bcast_bytes; 2044 __le64 rx_ucast_pkts; 2045 __le64 rx_mcast_pkts; 2046 __le64 rx_bcast_pkts; 2047 __le64 rx_discard_pkts; 2048 __le64 rx_drop_pkts; 2049 __le64 rx_ucast_bytes; 2050 __le64 rx_mcast_bytes; 2051 __le64 rx_bcast_bytes; 2052 __le64 rx_agg_pkts; 2053 __le64 rx_agg_bytes; 2054 __le64 rx_agg_events; 2055 __le64 rx_agg_aborts; 2056 u8 unused_0[7]; 2057 u8 valid; 2058 }; 2059 2060 /* hwrm_func_qstats_ext_input (size:256b/32B) */ 2061 struct hwrm_func_qstats_ext_input { 2062 __le16 req_type; 2063 __le16 cmpl_ring; 2064 __le16 seq_id; 2065 __le16 target_id; 2066 __le64 resp_addr; 2067 __le16 fid; 2068 u8 flags; 2069 #define FUNC_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 2070 #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL 2071 #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL 2072 #define FUNC_QSTATS_EXT_REQ_FLAGS_LAST FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 2073 u8 unused_0[1]; 2074 __le32 enables; 2075 #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL 2076 __le16 schq_id; 2077 __le16 traffic_class; 2078 u8 unused_1[4]; 2079 }; 2080 2081 /* hwrm_func_qstats_ext_output (size:1536b/192B) */ 2082 struct hwrm_func_qstats_ext_output { 2083 __le16 error_code; 2084 __le16 req_type; 2085 __le16 seq_id; 2086 __le16 resp_len; 2087 __le64 rx_ucast_pkts; 2088 __le64 rx_mcast_pkts; 2089 __le64 rx_bcast_pkts; 2090 __le64 rx_discard_pkts; 2091 __le64 rx_error_pkts; 2092 __le64 rx_ucast_bytes; 2093 __le64 rx_mcast_bytes; 2094 __le64 rx_bcast_bytes; 2095 __le64 tx_ucast_pkts; 2096 __le64 tx_mcast_pkts; 2097 __le64 tx_bcast_pkts; 2098 __le64 tx_error_pkts; 2099 __le64 tx_discard_pkts; 2100 __le64 tx_ucast_bytes; 2101 __le64 tx_mcast_bytes; 2102 __le64 tx_bcast_bytes; 2103 __le64 rx_tpa_eligible_pkt; 2104 __le64 rx_tpa_eligible_bytes; 2105 __le64 rx_tpa_pkt; 2106 __le64 rx_tpa_bytes; 2107 __le64 rx_tpa_errors; 2108 __le64 rx_tpa_events; 2109 u8 unused_0[7]; 2110 u8 valid; 2111 }; 2112 2113 /* hwrm_func_clr_stats_input (size:192b/24B) */ 2114 struct hwrm_func_clr_stats_input { 2115 __le16 req_type; 2116 __le16 cmpl_ring; 2117 __le16 seq_id; 2118 __le16 target_id; 2119 __le64 resp_addr; 2120 __le16 fid; 2121 u8 unused_0[6]; 2122 }; 2123 2124 /* hwrm_func_clr_stats_output (size:128b/16B) */ 2125 struct hwrm_func_clr_stats_output { 2126 __le16 error_code; 2127 __le16 req_type; 2128 __le16 seq_id; 2129 __le16 resp_len; 2130 u8 unused_0[7]; 2131 u8 valid; 2132 }; 2133 2134 /* hwrm_func_vf_resc_free_input (size:192b/24B) */ 2135 struct hwrm_func_vf_resc_free_input { 2136 __le16 req_type; 2137 __le16 cmpl_ring; 2138 __le16 seq_id; 2139 __le16 target_id; 2140 __le64 resp_addr; 2141 __le16 vf_id; 2142 u8 unused_0[6]; 2143 }; 2144 2145 /* hwrm_func_vf_resc_free_output (size:128b/16B) */ 2146 struct hwrm_func_vf_resc_free_output { 2147 __le16 error_code; 2148 __le16 req_type; 2149 __le16 seq_id; 2150 __le16 resp_len; 2151 u8 unused_0[7]; 2152 u8 valid; 2153 }; 2154 2155 /* hwrm_func_drv_rgtr_input (size:896b/112B) */ 2156 struct hwrm_func_drv_rgtr_input { 2157 __le16 req_type; 2158 __le16 cmpl_ring; 2159 __le16 seq_id; 2160 __le16 target_id; 2161 __le64 resp_addr; 2162 __le32 flags; 2163 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 2164 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 2165 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 2166 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 2167 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 2168 #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL 2169 #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL 2170 #define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT 0x80UL 2171 #define FUNC_DRV_RGTR_REQ_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT 0x100UL 2172 #define FUNC_DRV_RGTR_REQ_FLAGS_NPAR_1_2_SUPPORT 0x200UL 2173 __le32 enables; 2174 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 2175 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 2176 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 2177 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 2178 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 2179 __le16 os_type; 2180 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 2181 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 2182 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 2183 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 2184 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 2185 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 2186 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 2187 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 2188 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 2189 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 2190 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 2191 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 2192 u8 ver_maj_8b; 2193 u8 ver_min_8b; 2194 u8 ver_upd_8b; 2195 u8 unused_0[3]; 2196 __le32 timestamp; 2197 u8 unused_1[4]; 2198 __le32 vf_req_fwd[8]; 2199 __le32 async_event_fwd[8]; 2200 __le16 ver_maj; 2201 __le16 ver_min; 2202 __le16 ver_upd; 2203 __le16 ver_patch; 2204 }; 2205 2206 /* hwrm_func_drv_rgtr_output (size:128b/16B) */ 2207 struct hwrm_func_drv_rgtr_output { 2208 __le16 error_code; 2209 __le16 req_type; 2210 __le16 seq_id; 2211 __le16 resp_len; 2212 __le32 flags; 2213 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 2214 u8 unused_0[3]; 2215 u8 valid; 2216 }; 2217 2218 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 2219 struct hwrm_func_drv_unrgtr_input { 2220 __le16 req_type; 2221 __le16 cmpl_ring; 2222 __le16 seq_id; 2223 __le16 target_id; 2224 __le64 resp_addr; 2225 __le32 flags; 2226 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 2227 u8 unused_0[4]; 2228 }; 2229 2230 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 2231 struct hwrm_func_drv_unrgtr_output { 2232 __le16 error_code; 2233 __le16 req_type; 2234 __le16 seq_id; 2235 __le16 resp_len; 2236 u8 unused_0[7]; 2237 u8 valid; 2238 }; 2239 2240 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 2241 struct hwrm_func_buf_rgtr_input { 2242 __le16 req_type; 2243 __le16 cmpl_ring; 2244 __le16 seq_id; 2245 __le16 target_id; 2246 __le64 resp_addr; 2247 __le32 enables; 2248 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 2249 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 2250 __le16 vf_id; 2251 __le16 req_buf_num_pages; 2252 __le16 req_buf_page_size; 2253 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 2254 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 2255 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 2256 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 2257 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 2258 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 2259 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 2260 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 2261 __le16 req_buf_len; 2262 __le16 resp_buf_len; 2263 u8 unused_0[2]; 2264 __le64 req_buf_page_addr0; 2265 __le64 req_buf_page_addr1; 2266 __le64 req_buf_page_addr2; 2267 __le64 req_buf_page_addr3; 2268 __le64 req_buf_page_addr4; 2269 __le64 req_buf_page_addr5; 2270 __le64 req_buf_page_addr6; 2271 __le64 req_buf_page_addr7; 2272 __le64 req_buf_page_addr8; 2273 __le64 req_buf_page_addr9; 2274 __le64 error_buf_addr; 2275 __le64 resp_buf_addr; 2276 }; 2277 2278 /* hwrm_func_buf_rgtr_output (size:128b/16B) */ 2279 struct hwrm_func_buf_rgtr_output { 2280 __le16 error_code; 2281 __le16 req_type; 2282 __le16 seq_id; 2283 __le16 resp_len; 2284 u8 unused_0[7]; 2285 u8 valid; 2286 }; 2287 2288 /* hwrm_func_drv_qver_input (size:192b/24B) */ 2289 struct hwrm_func_drv_qver_input { 2290 __le16 req_type; 2291 __le16 cmpl_ring; 2292 __le16 seq_id; 2293 __le16 target_id; 2294 __le64 resp_addr; 2295 __le32 reserved; 2296 __le16 fid; 2297 u8 unused_0[2]; 2298 }; 2299 2300 /* hwrm_func_drv_qver_output (size:256b/32B) */ 2301 struct hwrm_func_drv_qver_output { 2302 __le16 error_code; 2303 __le16 req_type; 2304 __le16 seq_id; 2305 __le16 resp_len; 2306 __le16 os_type; 2307 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 2308 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 2309 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 2310 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 2311 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 2312 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 2313 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 2314 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 2315 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 2316 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 2317 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 2318 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 2319 u8 ver_maj_8b; 2320 u8 ver_min_8b; 2321 u8 ver_upd_8b; 2322 u8 unused_0[3]; 2323 __le16 ver_maj; 2324 __le16 ver_min; 2325 __le16 ver_upd; 2326 __le16 ver_patch; 2327 u8 unused_1[7]; 2328 u8 valid; 2329 }; 2330 2331 /* hwrm_func_resource_qcaps_input (size:192b/24B) */ 2332 struct hwrm_func_resource_qcaps_input { 2333 __le16 req_type; 2334 __le16 cmpl_ring; 2335 __le16 seq_id; 2336 __le16 target_id; 2337 __le64 resp_addr; 2338 __le16 fid; 2339 u8 unused_0[6]; 2340 }; 2341 2342 /* hwrm_func_resource_qcaps_output (size:512b/64B) */ 2343 struct hwrm_func_resource_qcaps_output { 2344 __le16 error_code; 2345 __le16 req_type; 2346 __le16 seq_id; 2347 __le16 resp_len; 2348 __le16 max_vfs; 2349 __le16 max_msix; 2350 __le16 vf_reservation_strategy; 2351 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 2352 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 2353 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 2354 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 2355 __le16 min_rsscos_ctx; 2356 __le16 max_rsscos_ctx; 2357 __le16 min_cmpl_rings; 2358 __le16 max_cmpl_rings; 2359 __le16 min_tx_rings; 2360 __le16 max_tx_rings; 2361 __le16 min_rx_rings; 2362 __le16 max_rx_rings; 2363 __le16 min_l2_ctxs; 2364 __le16 max_l2_ctxs; 2365 __le16 min_vnics; 2366 __le16 max_vnics; 2367 __le16 min_stat_ctx; 2368 __le16 max_stat_ctx; 2369 __le16 min_hw_ring_grps; 2370 __le16 max_hw_ring_grps; 2371 __le16 max_tx_scheduler_inputs; 2372 __le16 flags; 2373 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 2374 __le16 min_tx_key_ctxs; 2375 __le16 max_tx_key_ctxs; 2376 __le16 min_rx_key_ctxs; 2377 __le16 max_rx_key_ctxs; 2378 u8 unused_0[5]; 2379 u8 valid; 2380 }; 2381 2382 /* hwrm_func_vf_resource_cfg_input (size:512b/64B) */ 2383 struct hwrm_func_vf_resource_cfg_input { 2384 __le16 req_type; 2385 __le16 cmpl_ring; 2386 __le16 seq_id; 2387 __le16 target_id; 2388 __le64 resp_addr; 2389 __le16 vf_id; 2390 __le16 max_msix; 2391 __le16 min_rsscos_ctx; 2392 __le16 max_rsscos_ctx; 2393 __le16 min_cmpl_rings; 2394 __le16 max_cmpl_rings; 2395 __le16 min_tx_rings; 2396 __le16 max_tx_rings; 2397 __le16 min_rx_rings; 2398 __le16 max_rx_rings; 2399 __le16 min_l2_ctxs; 2400 __le16 max_l2_ctxs; 2401 __le16 min_vnics; 2402 __le16 max_vnics; 2403 __le16 min_stat_ctx; 2404 __le16 max_stat_ctx; 2405 __le16 min_hw_ring_grps; 2406 __le16 max_hw_ring_grps; 2407 __le16 flags; 2408 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 2409 __le16 min_tx_key_ctxs; 2410 __le16 max_tx_key_ctxs; 2411 __le16 min_rx_key_ctxs; 2412 __le16 max_rx_key_ctxs; 2413 u8 unused_0[2]; 2414 }; 2415 2416 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ 2417 struct hwrm_func_vf_resource_cfg_output { 2418 __le16 error_code; 2419 __le16 req_type; 2420 __le16 seq_id; 2421 __le16 resp_len; 2422 __le16 reserved_rsscos_ctx; 2423 __le16 reserved_cmpl_rings; 2424 __le16 reserved_tx_rings; 2425 __le16 reserved_rx_rings; 2426 __le16 reserved_l2_ctxs; 2427 __le16 reserved_vnics; 2428 __le16 reserved_stat_ctx; 2429 __le16 reserved_hw_ring_grps; 2430 __le16 reserved_tx_key_ctxs; 2431 __le16 reserved_rx_key_ctxs; 2432 u8 unused_0[3]; 2433 u8 valid; 2434 }; 2435 2436 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 2437 struct hwrm_func_backing_store_qcaps_input { 2438 __le16 req_type; 2439 __le16 cmpl_ring; 2440 __le16 seq_id; 2441 __le16 target_id; 2442 __le64 resp_addr; 2443 }; 2444 2445 /* hwrm_func_backing_store_qcaps_output (size:832b/104B) */ 2446 struct hwrm_func_backing_store_qcaps_output { 2447 __le16 error_code; 2448 __le16 req_type; 2449 __le16 seq_id; 2450 __le16 resp_len; 2451 __le32 qp_max_entries; 2452 __le16 qp_min_qp1_entries; 2453 __le16 qp_max_l2_entries; 2454 __le16 qp_entry_size; 2455 __le16 srq_max_l2_entries; 2456 __le32 srq_max_entries; 2457 __le16 srq_entry_size; 2458 __le16 cq_max_l2_entries; 2459 __le32 cq_max_entries; 2460 __le16 cq_entry_size; 2461 __le16 vnic_max_vnic_entries; 2462 __le16 vnic_max_ring_table_entries; 2463 __le16 vnic_entry_size; 2464 __le32 stat_max_entries; 2465 __le16 stat_entry_size; 2466 __le16 tqm_entry_size; 2467 __le32 tqm_min_entries_per_ring; 2468 __le32 tqm_max_entries_per_ring; 2469 __le32 mrav_max_entries; 2470 __le16 mrav_entry_size; 2471 __le16 tim_entry_size; 2472 __le32 tim_max_entries; 2473 __le16 mrav_num_entries_units; 2474 u8 tqm_entries_multiple; 2475 u8 ctx_kind_initializer; 2476 __le16 ctx_init_mask; 2477 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_QP 0x1UL 2478 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_SRQ 0x2UL 2479 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_CQ 0x4UL 2480 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_VNIC 0x8UL 2481 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_STAT 0x10UL 2482 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_MRAV 0x20UL 2483 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_TKC 0x40UL 2484 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_RKC 0x80UL 2485 u8 qp_init_offset; 2486 u8 srq_init_offset; 2487 u8 cq_init_offset; 2488 u8 vnic_init_offset; 2489 u8 tqm_fp_rings_count; 2490 u8 stat_init_offset; 2491 u8 mrav_init_offset; 2492 u8 tqm_fp_rings_count_ext; 2493 u8 tkc_init_offset; 2494 u8 rkc_init_offset; 2495 __le16 tkc_entry_size; 2496 __le16 rkc_entry_size; 2497 __le32 tkc_max_entries; 2498 __le32 rkc_max_entries; 2499 u8 rsvd1[7]; 2500 u8 valid; 2501 }; 2502 2503 /* tqm_fp_ring_cfg (size:128b/16B) */ 2504 struct tqm_fp_ring_cfg { 2505 u8 tqm_ring_pg_size_tqm_ring_lvl; 2506 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK 0xfUL 2507 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0 2508 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 0x0UL 2509 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 0x1UL 2510 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 0x2UL 2511 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 2512 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK 0xf0UL 2513 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4 2514 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2515 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2516 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2517 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2518 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2519 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2520 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G 2521 u8 unused[3]; 2522 __le32 tqm_ring_num_entries; 2523 __le64 tqm_ring_page_dir; 2524 }; 2525 2526 /* hwrm_func_backing_store_cfg_input (size:2688b/336B) */ 2527 struct hwrm_func_backing_store_cfg_input { 2528 __le16 req_type; 2529 __le16 cmpl_ring; 2530 __le16 seq_id; 2531 __le16 target_id; 2532 __le64 resp_addr; 2533 __le32 flags; 2534 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 2535 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL 2536 __le32 enables; 2537 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 2538 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 2539 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 2540 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 2541 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 2542 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 2543 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 2544 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 2545 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 2546 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 2547 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 2548 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 2549 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 2550 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 2551 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 2552 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 2553 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING8 0x10000UL 2554 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING9 0x20000UL 2555 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING10 0x40000UL 2556 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TKC 0x80000UL 2557 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_RKC 0x100000UL 2558 u8 qpc_pg_size_qpc_lvl; 2559 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 2560 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 2561 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 2562 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 2563 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 2564 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 2565 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 2566 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 2567 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 2568 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 2569 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 2570 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 2571 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 2572 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 2573 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 2574 u8 srq_pg_size_srq_lvl; 2575 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 2576 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 2577 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 2578 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 2579 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 2580 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 2581 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 2582 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 2583 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 2584 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 2585 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 2586 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 2587 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 2588 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 2589 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 2590 u8 cq_pg_size_cq_lvl; 2591 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 2592 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 2593 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 2594 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 2595 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 2596 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 2597 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 2598 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 2599 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 2600 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 2601 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 2602 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 2603 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 2604 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 2605 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 2606 u8 vnic_pg_size_vnic_lvl; 2607 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 2608 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 2609 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 2610 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 2611 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 2612 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 2613 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 2614 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 2615 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 2616 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 2617 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 2618 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 2619 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 2620 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 2621 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 2622 u8 stat_pg_size_stat_lvl; 2623 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 2624 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 2625 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 2626 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 2627 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 2628 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 2629 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 2630 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 2631 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 2632 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 2633 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 2634 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 2635 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 2636 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 2637 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 2638 u8 tqm_sp_pg_size_tqm_sp_lvl; 2639 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 2640 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 2641 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 2642 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 2643 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 2644 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 2645 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 2646 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 2647 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 2648 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 2649 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 2650 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 2651 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 2652 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 2653 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 2654 u8 tqm_ring0_pg_size_tqm_ring0_lvl; 2655 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 2656 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 2657 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 2658 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 2659 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 2660 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 2661 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 2662 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 2663 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 2664 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 2665 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 2666 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 2667 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 2668 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 2669 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 2670 u8 tqm_ring1_pg_size_tqm_ring1_lvl; 2671 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 2672 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 2673 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 2674 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 2675 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 2676 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 2677 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 2678 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 2679 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 2680 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 2681 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 2682 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 2683 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 2684 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 2685 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 2686 u8 tqm_ring2_pg_size_tqm_ring2_lvl; 2687 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 2688 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 2689 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 2690 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 2691 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 2692 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 2693 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 2694 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 2695 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 2696 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 2697 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 2698 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 2699 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 2700 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 2701 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 2702 u8 tqm_ring3_pg_size_tqm_ring3_lvl; 2703 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 2704 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 2705 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 2706 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 2707 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 2708 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 2709 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 2710 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 2711 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 2712 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 2713 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 2714 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 2715 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 2716 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 2717 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 2718 u8 tqm_ring4_pg_size_tqm_ring4_lvl; 2719 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 2720 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 2721 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 2722 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 2723 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 2724 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 2725 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 2726 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 2727 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 2728 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 2729 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 2730 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 2731 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 2732 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 2733 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 2734 u8 tqm_ring5_pg_size_tqm_ring5_lvl; 2735 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 2736 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 2737 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 2738 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 2739 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 2740 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 2741 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 2742 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 2743 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 2744 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 2745 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 2746 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 2747 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 2748 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 2749 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 2750 u8 tqm_ring6_pg_size_tqm_ring6_lvl; 2751 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 2752 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 2753 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 2754 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 2755 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 2756 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 2757 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 2758 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 2759 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 2760 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 2761 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 2762 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 2763 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 2764 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 2765 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 2766 u8 tqm_ring7_pg_size_tqm_ring7_lvl; 2767 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 2768 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 2769 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 2770 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 2771 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 2772 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 2773 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 2774 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 2775 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 2776 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 2777 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 2778 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 2779 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 2780 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 2781 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 2782 u8 mrav_pg_size_mrav_lvl; 2783 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 2784 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 2785 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 2786 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL 2787 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 2788 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 2789 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 2790 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 2791 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 2792 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 2793 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 2794 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 2795 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 2796 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 2797 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 2798 u8 tim_pg_size_tim_lvl; 2799 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 2800 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 2801 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 2802 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 2803 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 2804 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 2805 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 2806 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 2807 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 2808 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 2809 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 2810 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 2811 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 2812 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 2813 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 2814 __le64 qpc_page_dir; 2815 __le64 srq_page_dir; 2816 __le64 cq_page_dir; 2817 __le64 vnic_page_dir; 2818 __le64 stat_page_dir; 2819 __le64 tqm_sp_page_dir; 2820 __le64 tqm_ring0_page_dir; 2821 __le64 tqm_ring1_page_dir; 2822 __le64 tqm_ring2_page_dir; 2823 __le64 tqm_ring3_page_dir; 2824 __le64 tqm_ring4_page_dir; 2825 __le64 tqm_ring5_page_dir; 2826 __le64 tqm_ring6_page_dir; 2827 __le64 tqm_ring7_page_dir; 2828 __le64 mrav_page_dir; 2829 __le64 tim_page_dir; 2830 __le32 qp_num_entries; 2831 __le32 srq_num_entries; 2832 __le32 cq_num_entries; 2833 __le32 stat_num_entries; 2834 __le32 tqm_sp_num_entries; 2835 __le32 tqm_ring0_num_entries; 2836 __le32 tqm_ring1_num_entries; 2837 __le32 tqm_ring2_num_entries; 2838 __le32 tqm_ring3_num_entries; 2839 __le32 tqm_ring4_num_entries; 2840 __le32 tqm_ring5_num_entries; 2841 __le32 tqm_ring6_num_entries; 2842 __le32 tqm_ring7_num_entries; 2843 __le32 mrav_num_entries; 2844 __le32 tim_num_entries; 2845 __le16 qp_num_qp1_entries; 2846 __le16 qp_num_l2_entries; 2847 __le16 qp_entry_size; 2848 __le16 srq_num_l2_entries; 2849 __le16 srq_entry_size; 2850 __le16 cq_num_l2_entries; 2851 __le16 cq_entry_size; 2852 __le16 vnic_num_vnic_entries; 2853 __le16 vnic_num_ring_table_entries; 2854 __le16 vnic_entry_size; 2855 __le16 stat_entry_size; 2856 __le16 tqm_entry_size; 2857 __le16 mrav_entry_size; 2858 __le16 tim_entry_size; 2859 u8 tqm_ring8_pg_size_tqm_ring_lvl; 2860 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_MASK 0xfUL 2861 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_SFT 0 2862 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_0 0x0UL 2863 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_1 0x1UL 2864 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 0x2UL 2865 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 2866 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_MASK 0xf0UL 2867 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_SFT 4 2868 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2869 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2870 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2871 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2872 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2873 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2874 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G 2875 u8 ring8_unused[3]; 2876 __le32 tqm_ring8_num_entries; 2877 __le64 tqm_ring8_page_dir; 2878 u8 tqm_ring9_pg_size_tqm_ring_lvl; 2879 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_MASK 0xfUL 2880 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_SFT 0 2881 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_0 0x0UL 2882 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_1 0x1UL 2883 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 0x2UL 2884 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 2885 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_MASK 0xf0UL 2886 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_SFT 4 2887 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2888 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2889 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2890 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2891 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2892 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2893 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G 2894 u8 ring9_unused[3]; 2895 __le32 tqm_ring9_num_entries; 2896 __le64 tqm_ring9_page_dir; 2897 u8 tqm_ring10_pg_size_tqm_ring_lvl; 2898 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_MASK 0xfUL 2899 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_SFT 0 2900 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_0 0x0UL 2901 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_1 0x1UL 2902 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 0x2UL 2903 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 2904 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_MASK 0xf0UL 2905 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_SFT 4 2906 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2907 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2908 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2909 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2910 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2911 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2912 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G 2913 u8 ring10_unused[3]; 2914 __le32 tqm_ring10_num_entries; 2915 __le64 tqm_ring10_page_dir; 2916 __le32 tkc_num_entries; 2917 __le32 rkc_num_entries; 2918 __le64 tkc_page_dir; 2919 __le64 rkc_page_dir; 2920 __le16 tkc_entry_size; 2921 __le16 rkc_entry_size; 2922 u8 tkc_pg_size_tkc_lvl; 2923 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_MASK 0xfUL 2924 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_SFT 0 2925 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_0 0x0UL 2926 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_1 0x1UL 2927 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 0x2UL 2928 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 2929 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_MASK 0xf0UL 2930 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_SFT 4 2931 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_4K (0x0UL << 4) 2932 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8K (0x1UL << 4) 2933 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_64K (0x2UL << 4) 2934 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_2M (0x3UL << 4) 2935 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8M (0x4UL << 4) 2936 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G (0x5UL << 4) 2937 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G 2938 u8 rkc_pg_size_rkc_lvl; 2939 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_MASK 0xfUL 2940 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_SFT 0 2941 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_0 0x0UL 2942 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_1 0x1UL 2943 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 0x2UL 2944 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 2945 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_MASK 0xf0UL 2946 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_SFT 4 2947 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_4K (0x0UL << 4) 2948 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8K (0x1UL << 4) 2949 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_64K (0x2UL << 4) 2950 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_2M (0x3UL << 4) 2951 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8M (0x4UL << 4) 2952 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G (0x5UL << 4) 2953 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G 2954 u8 rsvd[2]; 2955 }; 2956 2957 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 2958 struct hwrm_func_backing_store_cfg_output { 2959 __le16 error_code; 2960 __le16 req_type; 2961 __le16 seq_id; 2962 __le16 resp_len; 2963 u8 unused_0[7]; 2964 u8 valid; 2965 }; 2966 2967 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */ 2968 struct hwrm_error_recovery_qcfg_input { 2969 __le16 req_type; 2970 __le16 cmpl_ring; 2971 __le16 seq_id; 2972 __le16 target_id; 2973 __le64 resp_addr; 2974 u8 unused_0[8]; 2975 }; 2976 2977 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ 2978 struct hwrm_error_recovery_qcfg_output { 2979 __le16 error_code; 2980 __le16 req_type; 2981 __le16 seq_id; 2982 __le16 resp_len; 2983 __le32 flags; 2984 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL 2985 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL 2986 __le32 driver_polling_freq; 2987 __le32 master_func_wait_period; 2988 __le32 normal_func_wait_period; 2989 __le32 master_func_wait_period_after_reset; 2990 __le32 max_bailout_time_after_reset; 2991 __le32 fw_health_status_reg; 2992 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL 2993 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0 2994 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2995 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL 2996 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL 2997 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL 2998 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 2999 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL 3000 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2 3001 __le32 fw_heartbeat_reg; 3002 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL 3003 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0 3004 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3005 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL 3006 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL 3007 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL 3008 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 3009 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL 3010 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2 3011 __le32 fw_reset_cnt_reg; 3012 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL 3013 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0 3014 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3015 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL 3016 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL 3017 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL 3018 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 3019 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL 3020 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2 3021 __le32 reset_inprogress_reg; 3022 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL 3023 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0 3024 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3025 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL 3026 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL 3027 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL 3028 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 3029 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL 3030 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2 3031 __le32 reset_inprogress_reg_mask; 3032 u8 unused_0[3]; 3033 u8 reg_array_cnt; 3034 __le32 reset_reg[16]; 3035 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL 3036 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0 3037 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3038 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL 3039 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL 3040 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL 3041 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 3042 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL 3043 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2 3044 __le32 reset_reg_val[16]; 3045 u8 delay_after_reset[16]; 3046 __le32 err_recovery_cnt_reg; 3047 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL 3048 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0 3049 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3050 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL 3051 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL 3052 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL 3053 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 3054 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL 3055 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2 3056 u8 unused_1[3]; 3057 u8 valid; 3058 }; 3059 3060 /* hwrm_func_echo_response_input (size:192b/24B) */ 3061 struct hwrm_func_echo_response_input { 3062 __le16 req_type; 3063 __le16 cmpl_ring; 3064 __le16 seq_id; 3065 __le16 target_id; 3066 __le64 resp_addr; 3067 __le32 event_data1; 3068 __le32 event_data2; 3069 }; 3070 3071 /* hwrm_func_echo_response_output (size:128b/16B) */ 3072 struct hwrm_func_echo_response_output { 3073 __le16 error_code; 3074 __le16 req_type; 3075 __le16 seq_id; 3076 __le16 resp_len; 3077 u8 unused_0[7]; 3078 u8 valid; 3079 }; 3080 3081 /* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */ 3082 struct hwrm_func_ptp_pin_qcfg_input { 3083 __le16 req_type; 3084 __le16 cmpl_ring; 3085 __le16 seq_id; 3086 __le16 target_id; 3087 __le64 resp_addr; 3088 u8 unused_0[8]; 3089 }; 3090 3091 /* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */ 3092 struct hwrm_func_ptp_pin_qcfg_output { 3093 __le16 error_code; 3094 __le16 req_type; 3095 __le16 seq_id; 3096 __le16 resp_len; 3097 u8 num_pins; 3098 u8 state; 3099 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN0_ENABLED 0x1UL 3100 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN1_ENABLED 0x2UL 3101 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN2_ENABLED 0x4UL 3102 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN3_ENABLED 0x8UL 3103 u8 pin0_usage; 3104 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_NONE 0x0UL 3105 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_IN 0x1UL 3106 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_OUT 0x2UL 3107 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_IN 0x3UL 3108 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 0x4UL 3109 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 3110 u8 pin1_usage; 3111 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_NONE 0x0UL 3112 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_IN 0x1UL 3113 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_OUT 0x2UL 3114 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_IN 0x3UL 3115 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 0x4UL 3116 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 3117 u8 pin2_usage; 3118 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_NONE 0x0UL 3119 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_IN 0x1UL 3120 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_OUT 0x2UL 3121 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_IN 0x3UL 3122 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 0x4UL 3123 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 3124 u8 pin3_usage; 3125 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_NONE 0x0UL 3126 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_IN 0x1UL 3127 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_OUT 0x2UL 3128 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_IN 0x3UL 3129 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 0x4UL 3130 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 3131 u8 unused_0; 3132 u8 valid; 3133 }; 3134 3135 /* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */ 3136 struct hwrm_func_ptp_pin_cfg_input { 3137 __le16 req_type; 3138 __le16 cmpl_ring; 3139 __le16 seq_id; 3140 __le16 target_id; 3141 __le64 resp_addr; 3142 __le32 enables; 3143 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE 0x1UL 3144 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE 0x2UL 3145 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_STATE 0x4UL 3146 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_USAGE 0x8UL 3147 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_STATE 0x10UL 3148 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_USAGE 0x20UL 3149 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_STATE 0x40UL 3150 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_USAGE 0x80UL 3151 u8 pin0_state; 3152 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_DISABLED 0x0UL 3153 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 0x1UL 3154 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 3155 u8 pin0_usage; 3156 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_NONE 0x0UL 3157 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_IN 0x1UL 3158 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_OUT 0x2UL 3159 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_IN 0x3UL 3160 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 0x4UL 3161 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 3162 u8 pin1_state; 3163 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_DISABLED 0x0UL 3164 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 0x1UL 3165 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 3166 u8 pin1_usage; 3167 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_NONE 0x0UL 3168 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_IN 0x1UL 3169 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_OUT 0x2UL 3170 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_IN 0x3UL 3171 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 0x4UL 3172 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 3173 u8 pin2_state; 3174 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_DISABLED 0x0UL 3175 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 0x1UL 3176 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 3177 u8 pin2_usage; 3178 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_NONE 0x0UL 3179 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_IN 0x1UL 3180 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_OUT 0x2UL 3181 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_IN 0x3UL 3182 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 0x4UL 3183 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 3184 u8 pin3_state; 3185 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_DISABLED 0x0UL 3186 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 0x1UL 3187 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 3188 u8 pin3_usage; 3189 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_NONE 0x0UL 3190 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_IN 0x1UL 3191 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_OUT 0x2UL 3192 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_IN 0x3UL 3193 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 0x4UL 3194 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 3195 u8 unused_0[4]; 3196 }; 3197 3198 /* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */ 3199 struct hwrm_func_ptp_pin_cfg_output { 3200 __le16 error_code; 3201 __le16 req_type; 3202 __le16 seq_id; 3203 __le16 resp_len; 3204 u8 unused_0[7]; 3205 u8 valid; 3206 }; 3207 3208 /* hwrm_func_ptp_cfg_input (size:384b/48B) */ 3209 struct hwrm_func_ptp_cfg_input { 3210 __le16 req_type; 3211 __le16 cmpl_ring; 3212 __le16 seq_id; 3213 __le16 target_id; 3214 __le64 resp_addr; 3215 __le16 enables; 3216 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT 0x1UL 3217 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE 0x2UL 3218 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_PHASE 0x4UL 3219 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD 0x8UL 3220 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP 0x10UL 3221 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE 0x20UL 3222 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME 0x40UL 3223 u8 ptp_pps_event; 3224 #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_INTERNAL 0x1UL 3225 #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_EXTERNAL 0x2UL 3226 u8 ptp_freq_adj_dll_source; 3227 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_NONE 0x0UL 3228 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 0x1UL 3229 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 0x2UL 3230 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 0x3UL 3231 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 0x4UL 3232 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 0x5UL 3233 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 0x6UL 3234 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 0x7UL 3235 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 0x8UL 3236 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 0xffUL 3237 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 3238 u8 ptp_freq_adj_dll_phase; 3239 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_NONE 0x0UL 3240 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_4K 0x1UL 3241 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_8K 0x2UL 3242 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M 0x3UL 3243 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M 3244 u8 unused_0[3]; 3245 __le32 ptp_freq_adj_ext_period; 3246 __le32 ptp_freq_adj_ext_up; 3247 __le32 ptp_freq_adj_ext_phase_lower; 3248 __le32 ptp_freq_adj_ext_phase_upper; 3249 __le64 ptp_set_time; 3250 }; 3251 3252 /* hwrm_func_ptp_cfg_output (size:128b/16B) */ 3253 struct hwrm_func_ptp_cfg_output { 3254 __le16 error_code; 3255 __le16 req_type; 3256 __le16 seq_id; 3257 __le16 resp_len; 3258 u8 unused_0[7]; 3259 u8 valid; 3260 }; 3261 3262 /* hwrm_func_ptp_ts_query_input (size:192b/24B) */ 3263 struct hwrm_func_ptp_ts_query_input { 3264 __le16 req_type; 3265 __le16 cmpl_ring; 3266 __le16 seq_id; 3267 __le16 target_id; 3268 __le64 resp_addr; 3269 __le32 flags; 3270 #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PPS_TIME 0x1UL 3271 #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PTM_TIME 0x2UL 3272 u8 unused_0[4]; 3273 }; 3274 3275 /* hwrm_func_ptp_ts_query_output (size:320b/40B) */ 3276 struct hwrm_func_ptp_ts_query_output { 3277 __le16 error_code; 3278 __le16 req_type; 3279 __le16 seq_id; 3280 __le16 resp_len; 3281 __le64 pps_event_ts; 3282 __le64 ptm_res_local_ts; 3283 __le64 ptm_pmstr_ts; 3284 __le32 ptm_mstr_prop_dly; 3285 u8 unused_0[3]; 3286 u8 valid; 3287 }; 3288 3289 /* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */ 3290 struct hwrm_func_ptp_ext_cfg_input { 3291 __le16 req_type; 3292 __le16 cmpl_ring; 3293 __le16 seq_id; 3294 __le16 target_id; 3295 __le64 resp_addr; 3296 __le16 enables; 3297 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_MASTER_FID 0x1UL 3298 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_FID 0x2UL 3299 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_MODE 0x4UL 3300 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_FAILOVER_TIMER 0x8UL 3301 __le16 phc_master_fid; 3302 __le16 phc_sec_fid; 3303 u8 phc_sec_mode; 3304 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_SWITCH 0x0UL 3305 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_ALL 0x1UL 3306 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY 0x2UL 3307 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_LAST FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY 3308 u8 unused_0; 3309 __le32 failover_timer; 3310 u8 unused_1[4]; 3311 }; 3312 3313 /* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */ 3314 struct hwrm_func_ptp_ext_cfg_output { 3315 __le16 error_code; 3316 __le16 req_type; 3317 __le16 seq_id; 3318 __le16 resp_len; 3319 u8 unused_0[7]; 3320 u8 valid; 3321 }; 3322 3323 /* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */ 3324 struct hwrm_func_ptp_ext_qcfg_input { 3325 __le16 req_type; 3326 __le16 cmpl_ring; 3327 __le16 seq_id; 3328 __le16 target_id; 3329 __le64 resp_addr; 3330 u8 unused_0[8]; 3331 }; 3332 3333 /* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */ 3334 struct hwrm_func_ptp_ext_qcfg_output { 3335 __le16 error_code; 3336 __le16 req_type; 3337 __le16 seq_id; 3338 __le16 resp_len; 3339 __le16 phc_master_fid; 3340 __le16 phc_sec_fid; 3341 __le16 phc_active_fid0; 3342 __le16 phc_active_fid1; 3343 __le32 last_failover_event; 3344 __le16 from_fid; 3345 __le16 to_fid; 3346 u8 unused_0[7]; 3347 u8 valid; 3348 }; 3349 3350 /* hwrm_func_backing_store_cfg_v2_input (size:448b/56B) */ 3351 struct hwrm_func_backing_store_cfg_v2_input { 3352 __le16 req_type; 3353 __le16 cmpl_ring; 3354 __le16 seq_id; 3355 __le16 target_id; 3356 __le64 resp_addr; 3357 __le16 type; 3358 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QP 0x0UL 3359 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ 0x1UL 3360 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ 0x2UL 3361 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_VNIC 0x3UL 3362 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_STAT 0x4UL 3363 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3364 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3365 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MRAV 0xeUL 3366 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TIM 0xfUL 3367 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TKC 0x13UL 3368 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RKC 0x14UL 3369 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3370 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 0xffffUL 3371 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 3372 __le16 instance; 3373 __le32 flags; 3374 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_PREBOOT_MODE 0x1UL 3375 __le64 page_dir; 3376 __le32 num_entries; 3377 __le16 entry_size; 3378 u8 page_size_pbl_level; 3379 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_MASK 0xfUL 3380 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_SFT 0 3381 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_0 0x0UL 3382 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_1 0x1UL 3383 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2 0x2UL 3384 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2 3385 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_MASK 0xf0UL 3386 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_SFT 4 3387 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_4K (0x0UL << 4) 3388 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8K (0x1UL << 4) 3389 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_64K (0x2UL << 4) 3390 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_2M (0x3UL << 4) 3391 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8M (0x4UL << 4) 3392 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G (0x5UL << 4) 3393 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G 3394 u8 subtype_valid_cnt; 3395 __le32 split_entry_0; 3396 __le32 split_entry_1; 3397 __le32 split_entry_2; 3398 __le32 split_entry_3; 3399 }; 3400 3401 /* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */ 3402 struct hwrm_func_backing_store_cfg_v2_output { 3403 __le16 error_code; 3404 __le16 req_type; 3405 __le16 seq_id; 3406 __le16 resp_len; 3407 u8 rsvd0[7]; 3408 u8 valid; 3409 }; 3410 3411 /* hwrm_func_backing_store_qcfg_v2_input (size:192b/24B) */ 3412 struct hwrm_func_backing_store_qcfg_v2_input { 3413 __le16 req_type; 3414 __le16 cmpl_ring; 3415 __le16 seq_id; 3416 __le16 target_id; 3417 __le64 resp_addr; 3418 __le16 type; 3419 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QP 0x0UL 3420 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ 0x1UL 3421 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ 0x2UL 3422 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_VNIC 0x3UL 3423 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_STAT 0x4UL 3424 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3425 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3426 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MRAV 0xeUL 3427 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TIM 0xfUL 3428 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TKC 0x13UL 3429 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RKC 0x14UL 3430 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3431 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 0xffffUL 3432 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 3433 __le16 instance; 3434 u8 rsvd[4]; 3435 }; 3436 3437 /* hwrm_func_backing_store_qcfg_v2_output (size:448b/56B) */ 3438 struct hwrm_func_backing_store_qcfg_v2_output { 3439 __le16 error_code; 3440 __le16 req_type; 3441 __le16 seq_id; 3442 __le16 resp_len; 3443 __le16 type; 3444 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QP 0x0UL 3445 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRQ 0x1UL 3446 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CQ 0x2UL 3447 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_VNIC 0x3UL 3448 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_STAT 0x4UL 3449 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SP_TQM_RING 0x5UL 3450 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_FP_TQM_RING 0x6UL 3451 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MRAV 0xeUL 3452 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TIM 0xfUL 3453 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TKC 0x13UL 3454 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RKC 0x14UL 3455 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MP_TQM_RING 0x15UL 3456 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 0xffffUL 3457 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 3458 __le16 instance; 3459 __le32 flags; 3460 __le64 page_dir; 3461 __le32 num_entries; 3462 u8 page_size_pbl_level; 3463 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_MASK 0xfUL 3464 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_SFT 0 3465 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_0 0x0UL 3466 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_1 0x1UL 3467 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2 0x2UL 3468 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2 3469 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_MASK 0xf0UL 3470 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_SFT 4 3471 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_4K (0x0UL << 4) 3472 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8K (0x1UL << 4) 3473 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_64K (0x2UL << 4) 3474 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_2M (0x3UL << 4) 3475 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8M (0x4UL << 4) 3476 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G (0x5UL << 4) 3477 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G 3478 u8 subtype_valid_cnt; 3479 u8 rsvd[2]; 3480 __le32 split_entry_0; 3481 __le32 split_entry_1; 3482 __le32 split_entry_2; 3483 __le32 split_entry_3; 3484 u8 rsvd2[7]; 3485 u8 valid; 3486 }; 3487 3488 /* qpc_split_entries (size:128b/16B) */ 3489 struct qpc_split_entries { 3490 __le32 qp_num_l2_entries; 3491 __le32 qp_num_qp1_entries; 3492 __le32 rsvd[2]; 3493 }; 3494 3495 /* srq_split_entries (size:128b/16B) */ 3496 struct srq_split_entries { 3497 __le32 srq_num_l2_entries; 3498 __le32 rsvd; 3499 __le32 rsvd2[2]; 3500 }; 3501 3502 /* cq_split_entries (size:128b/16B) */ 3503 struct cq_split_entries { 3504 __le32 cq_num_l2_entries; 3505 __le32 rsvd; 3506 __le32 rsvd2[2]; 3507 }; 3508 3509 /* vnic_split_entries (size:128b/16B) */ 3510 struct vnic_split_entries { 3511 __le32 vnic_num_vnic_entries; 3512 __le32 rsvd; 3513 __le32 rsvd2[2]; 3514 }; 3515 3516 /* mrav_split_entries (size:128b/16B) */ 3517 struct mrav_split_entries { 3518 __le32 mrav_num_av_entries; 3519 __le32 rsvd; 3520 __le32 rsvd2[2]; 3521 }; 3522 3523 /* hwrm_func_backing_store_qcaps_v2_input (size:192b/24B) */ 3524 struct hwrm_func_backing_store_qcaps_v2_input { 3525 __le16 req_type; 3526 __le16 cmpl_ring; 3527 __le16 seq_id; 3528 __le16 target_id; 3529 __le64 resp_addr; 3530 __le16 type; 3531 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP 0x0UL 3532 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ 0x1UL 3533 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ 0x2UL 3534 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC 0x3UL 3535 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT 0x4UL 3536 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3537 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3538 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV 0xeUL 3539 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM 0xfUL 3540 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TKC 0x13UL 3541 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RKC 0x14UL 3542 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3543 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 0xffffUL 3544 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 3545 u8 rsvd[6]; 3546 }; 3547 3548 /* hwrm_func_backing_store_qcaps_v2_output (size:448b/56B) */ 3549 struct hwrm_func_backing_store_qcaps_v2_output { 3550 __le16 error_code; 3551 __le16 req_type; 3552 __le16 seq_id; 3553 __le16 resp_len; 3554 __le16 type; 3555 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QP 0x0UL 3556 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ 0x1UL 3557 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ 0x2UL 3558 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_VNIC 0x3UL 3559 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_STAT 0x4UL 3560 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SP_TQM_RING 0x5UL 3561 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_FP_TQM_RING 0x6UL 3562 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MRAV 0xeUL 3563 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TIM 0xfUL 3564 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TKC 0x13UL 3565 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RKC 0x14UL 3566 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MP_TQM_RING 0x15UL 3567 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 0xffffUL 3568 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 3569 __le16 entry_size; 3570 __le32 flags; 3571 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ENABLE_CTX_KIND_INIT 0x1UL 3572 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID 0x2UL 3573 __le32 instance_bit_map; 3574 u8 ctx_init_value; 3575 u8 ctx_init_offset; 3576 u8 entry_multiple; 3577 u8 rsvd; 3578 __le32 max_num_entries; 3579 __le32 min_num_entries; 3580 __le16 next_valid_type; 3581 u8 subtype_valid_cnt; 3582 u8 rsvd2; 3583 __le32 split_entry_0; 3584 __le32 split_entry_1; 3585 __le32 split_entry_2; 3586 __le32 split_entry_3; 3587 u8 rsvd3[3]; 3588 u8 valid; 3589 }; 3590 3591 /* hwrm_func_drv_if_change_input (size:192b/24B) */ 3592 struct hwrm_func_drv_if_change_input { 3593 __le16 req_type; 3594 __le16 cmpl_ring; 3595 __le16 seq_id; 3596 __le16 target_id; 3597 __le64 resp_addr; 3598 __le32 flags; 3599 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 3600 __le32 unused; 3601 }; 3602 3603 /* hwrm_func_drv_if_change_output (size:128b/16B) */ 3604 struct hwrm_func_drv_if_change_output { 3605 __le16 error_code; 3606 __le16 req_type; 3607 __le16 seq_id; 3608 __le16 resp_len; 3609 __le32 flags; 3610 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 3611 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 3612 u8 unused_0[3]; 3613 u8 valid; 3614 }; 3615 3616 /* hwrm_port_phy_cfg_input (size:448b/56B) */ 3617 struct hwrm_port_phy_cfg_input { 3618 __le16 req_type; 3619 __le16 cmpl_ring; 3620 __le16 seq_id; 3621 __le16 target_id; 3622 __le64 resp_addr; 3623 __le32 flags; 3624 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 3625 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 3626 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 3627 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 3628 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 3629 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 3630 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 3631 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 3632 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 3633 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 3634 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 3635 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 3636 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 3637 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 3638 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 3639 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL 3640 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL 3641 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL 3642 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL 3643 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL 3644 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL 3645 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL 3646 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL 3647 __le32 enables; 3648 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 3649 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 3650 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 3651 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 3652 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 3653 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 3654 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 3655 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 3656 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 3657 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 3658 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 3659 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL 3660 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL 3661 __le16 port_id; 3662 __le16 force_link_speed; 3663 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 3664 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 3665 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 3666 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 3667 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 3668 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 3669 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 3670 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 3671 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 3672 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 3673 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 3674 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 3675 u8 auto_mode; 3676 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 3677 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 3678 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 3679 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 3680 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 3681 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 3682 u8 auto_duplex; 3683 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 3684 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 3685 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 3686 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 3687 u8 auto_pause; 3688 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 3689 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 3690 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 3691 u8 unused_0; 3692 __le16 auto_link_speed; 3693 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 3694 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 3695 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 3696 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 3697 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 3698 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 3699 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 3700 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 3701 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 3702 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 3703 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 3704 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 3705 __le16 auto_link_speed_mask; 3706 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 3707 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 3708 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 3709 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 3710 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 3711 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 3712 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 3713 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 3714 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 3715 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 3716 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 3717 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 3718 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 3719 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 3720 u8 wirespeed; 3721 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 3722 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 3723 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 3724 u8 lpbk; 3725 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 3726 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 3727 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 3728 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 3729 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 3730 u8 force_pause; 3731 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 3732 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 3733 u8 unused_1; 3734 __le32 preemphasis; 3735 __le16 eee_link_speed_mask; 3736 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 3737 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 3738 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 3739 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 3740 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 3741 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 3742 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 3743 __le16 force_pam4_link_speed; 3744 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 3745 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 3746 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 3747 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 3748 __le32 tx_lpi_timer; 3749 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 3750 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 3751 __le16 auto_link_pam4_speed_mask; 3752 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL 3753 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL 3754 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL 3755 u8 unused_2[2]; 3756 }; 3757 3758 /* hwrm_port_phy_cfg_output (size:128b/16B) */ 3759 struct hwrm_port_phy_cfg_output { 3760 __le16 error_code; 3761 __le16 req_type; 3762 __le16 seq_id; 3763 __le16 resp_len; 3764 u8 unused_0[7]; 3765 u8 valid; 3766 }; 3767 3768 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 3769 struct hwrm_port_phy_cfg_cmd_err { 3770 u8 code; 3771 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 3772 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 3773 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 3774 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 3775 u8 unused_0[7]; 3776 }; 3777 3778 /* hwrm_port_phy_qcfg_input (size:192b/24B) */ 3779 struct hwrm_port_phy_qcfg_input { 3780 __le16 req_type; 3781 __le16 cmpl_ring; 3782 __le16 seq_id; 3783 __le16 target_id; 3784 __le64 resp_addr; 3785 __le16 port_id; 3786 u8 unused_0[6]; 3787 }; 3788 3789 /* hwrm_port_phy_qcfg_output (size:768b/96B) */ 3790 struct hwrm_port_phy_qcfg_output { 3791 __le16 error_code; 3792 __le16 req_type; 3793 __le16 seq_id; 3794 __le16 resp_len; 3795 u8 link; 3796 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 3797 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 3798 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 3799 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 3800 u8 active_fec_signal_mode; 3801 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL 3802 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0 3803 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL 3804 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL 3805 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 3806 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL 3807 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4 3808 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4) 3809 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4) 3810 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4) 3811 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4) 3812 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4) 3813 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4) 3814 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4) 3815 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE 3816 __le16 link_speed; 3817 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 3818 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 3819 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 3820 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 3821 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 3822 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 3823 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 3824 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 3825 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 3826 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 3827 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 3828 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 3829 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 3830 u8 duplex_cfg; 3831 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 3832 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 3833 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 3834 u8 pause; 3835 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 3836 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 3837 __le16 support_speeds; 3838 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 3839 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 3840 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 3841 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 3842 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 3843 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 3844 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 3845 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 3846 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 3847 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 3848 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 3849 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 3850 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 3851 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 3852 __le16 force_link_speed; 3853 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 3854 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 3855 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 3856 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 3857 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 3858 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 3859 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 3860 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 3861 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 3862 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 3863 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 3864 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 3865 u8 auto_mode; 3866 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 3867 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 3868 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 3869 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 3870 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 3871 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 3872 u8 auto_pause; 3873 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 3874 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 3875 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 3876 __le16 auto_link_speed; 3877 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 3878 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 3879 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 3880 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 3881 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 3882 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 3883 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 3884 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 3885 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 3886 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 3887 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 3888 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 3889 __le16 auto_link_speed_mask; 3890 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 3891 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 3892 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 3893 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 3894 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 3895 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 3896 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 3897 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 3898 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 3899 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 3900 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 3901 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 3902 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 3903 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 3904 u8 wirespeed; 3905 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 3906 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 3907 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 3908 u8 lpbk; 3909 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 3910 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 3911 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 3912 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 3913 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 3914 u8 force_pause; 3915 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 3916 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 3917 u8 module_status; 3918 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 3919 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 3920 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 3921 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 3922 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 3923 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL 3924 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 3925 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 3926 __le32 preemphasis; 3927 u8 phy_maj; 3928 u8 phy_min; 3929 u8 phy_bld; 3930 u8 phy_type; 3931 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 3932 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 3933 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 3934 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 3935 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 3936 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 3937 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 3938 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 3939 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 3940 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 3941 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 3942 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 3943 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 3944 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 3945 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 3946 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 3947 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 3948 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 3949 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 3950 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 3951 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 3952 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 3953 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 3954 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 3955 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 3956 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 3957 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 3958 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 3959 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 3960 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 3961 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 3962 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 3963 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR 0x20UL 3964 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR 0x21UL 3965 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR 0x22UL 3966 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER 0x23UL 3967 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2 0x24UL 3968 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2 0x25UL 3969 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2 0x26UL 3970 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2 0x27UL 3971 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2 3972 u8 media_type; 3973 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 3974 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 3975 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 3976 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 3977 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 3978 u8 xcvr_pkg_type; 3979 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 3980 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 3981 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 3982 u8 eee_config_phy_addr; 3983 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 3984 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 3985 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 3986 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 3987 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 3988 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 3989 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 3990 u8 parallel_detect; 3991 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 3992 __le16 link_partner_adv_speeds; 3993 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 3994 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 3995 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 3996 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 3997 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 3998 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 3999 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 4000 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 4001 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 4002 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 4003 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 4004 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 4005 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 4006 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 4007 u8 link_partner_adv_auto_mode; 4008 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 4009 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 4010 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 4011 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 4012 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 4013 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 4014 u8 link_partner_adv_pause; 4015 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 4016 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 4017 __le16 adv_eee_link_speed_mask; 4018 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 4019 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 4020 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 4021 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 4022 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 4023 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 4024 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 4025 __le16 link_partner_adv_eee_link_speed_mask; 4026 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 4027 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 4028 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 4029 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 4030 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 4031 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 4032 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 4033 __le32 xcvr_identifier_type_tx_lpi_timer; 4034 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 4035 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 4036 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 4037 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 4038 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 4039 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 4040 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 4041 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 4042 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 4043 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 4044 __le16 fec_cfg; 4045 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 4046 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 4047 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 4048 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 4049 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 4050 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 4051 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 4052 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL 4053 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL 4054 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL 4055 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL 4056 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL 4057 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL 4058 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL 4059 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL 4060 u8 duplex_state; 4061 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 4062 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 4063 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 4064 u8 option_flags; 4065 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 4066 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN 0x2UL 4067 char phy_vendor_name[16]; 4068 char phy_vendor_partnumber[16]; 4069 __le16 support_pam4_speeds; 4070 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL 4071 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL 4072 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL 4073 __le16 force_pam4_link_speed; 4074 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 4075 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 4076 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 4077 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 4078 __le16 auto_pam4_link_speed_mask; 4079 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL 4080 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL 4081 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL 4082 u8 link_partner_pam4_adv_speeds; 4083 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL 4084 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL 4085 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL 4086 u8 valid; 4087 }; 4088 4089 /* hwrm_port_mac_cfg_input (size:448b/56B) */ 4090 struct hwrm_port_mac_cfg_input { 4091 __le16 req_type; 4092 __le16 cmpl_ring; 4093 __le16 seq_id; 4094 __le16 target_id; 4095 __le64 resp_addr; 4096 __le32 flags; 4097 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 4098 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 4099 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 4100 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 4101 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 4102 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 4103 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 4104 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 4105 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 4106 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 4107 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 4108 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 4109 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 4110 #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL 4111 __le32 enables; 4112 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 4113 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 4114 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 4115 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 4116 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 4117 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 4118 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 4119 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 4120 #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL 4121 #define PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE 0x400UL 4122 __le16 port_id; 4123 u8 ipg; 4124 u8 lpbk; 4125 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 4126 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 4127 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 4128 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 4129 u8 vlan_pri2cos_map_pri; 4130 u8 reserved1; 4131 u8 tunnel_pri2cos_map_pri; 4132 u8 dscp2pri_map_pri; 4133 __le16 rx_ts_capture_ptp_msg_type; 4134 __le16 tx_ts_capture_ptp_msg_type; 4135 u8 cos_field_cfg; 4136 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 4137 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 4138 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 4139 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 4140 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 4141 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 4142 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 4143 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 4144 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 4145 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 4146 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 4147 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 4148 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 4149 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 4150 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 4151 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 4152 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 4153 u8 unused_0[3]; 4154 __le32 ptp_freq_adj_ppb; 4155 u8 unused_1[4]; 4156 __le64 ptp_adj_phase; 4157 }; 4158 4159 /* hwrm_port_mac_cfg_output (size:128b/16B) */ 4160 struct hwrm_port_mac_cfg_output { 4161 __le16 error_code; 4162 __le16 req_type; 4163 __le16 seq_id; 4164 __le16 resp_len; 4165 __le16 mru; 4166 __le16 mtu; 4167 u8 ipg; 4168 u8 lpbk; 4169 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 4170 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 4171 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 4172 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 4173 u8 unused_0; 4174 u8 valid; 4175 }; 4176 4177 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 4178 struct hwrm_port_mac_ptp_qcfg_input { 4179 __le16 req_type; 4180 __le16 cmpl_ring; 4181 __le16 seq_id; 4182 __le16 target_id; 4183 __le64 resp_addr; 4184 __le16 port_id; 4185 u8 unused_0[6]; 4186 }; 4187 4188 /* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */ 4189 struct hwrm_port_mac_ptp_qcfg_output { 4190 __le16 error_code; 4191 __le16 req_type; 4192 __le16 seq_id; 4193 __le16 resp_len; 4194 u8 flags; 4195 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 4196 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL 4197 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL 4198 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK 0x10UL 4199 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_RTC_CONFIGURED 0x20UL 4200 u8 unused_0[3]; 4201 __le32 rx_ts_reg_off_lower; 4202 __le32 rx_ts_reg_off_upper; 4203 __le32 rx_ts_reg_off_seq_id; 4204 __le32 rx_ts_reg_off_src_id_0; 4205 __le32 rx_ts_reg_off_src_id_1; 4206 __le32 rx_ts_reg_off_src_id_2; 4207 __le32 rx_ts_reg_off_domain_id; 4208 __le32 rx_ts_reg_off_fifo; 4209 __le32 rx_ts_reg_off_fifo_adv; 4210 __le32 rx_ts_reg_off_granularity; 4211 __le32 tx_ts_reg_off_lower; 4212 __le32 tx_ts_reg_off_upper; 4213 __le32 tx_ts_reg_off_seq_id; 4214 __le32 tx_ts_reg_off_fifo; 4215 __le32 tx_ts_reg_off_granularity; 4216 __le32 ts_ref_clock_reg_lower; 4217 __le32 ts_ref_clock_reg_upper; 4218 u8 unused_1[7]; 4219 u8 valid; 4220 }; 4221 4222 /* tx_port_stats (size:3264b/408B) */ 4223 struct tx_port_stats { 4224 __le64 tx_64b_frames; 4225 __le64 tx_65b_127b_frames; 4226 __le64 tx_128b_255b_frames; 4227 __le64 tx_256b_511b_frames; 4228 __le64 tx_512b_1023b_frames; 4229 __le64 tx_1024b_1518b_frames; 4230 __le64 tx_good_vlan_frames; 4231 __le64 tx_1519b_2047b_frames; 4232 __le64 tx_2048b_4095b_frames; 4233 __le64 tx_4096b_9216b_frames; 4234 __le64 tx_9217b_16383b_frames; 4235 __le64 tx_good_frames; 4236 __le64 tx_total_frames; 4237 __le64 tx_ucast_frames; 4238 __le64 tx_mcast_frames; 4239 __le64 tx_bcast_frames; 4240 __le64 tx_pause_frames; 4241 __le64 tx_pfc_frames; 4242 __le64 tx_jabber_frames; 4243 __le64 tx_fcs_err_frames; 4244 __le64 tx_control_frames; 4245 __le64 tx_oversz_frames; 4246 __le64 tx_single_dfrl_frames; 4247 __le64 tx_multi_dfrl_frames; 4248 __le64 tx_single_coll_frames; 4249 __le64 tx_multi_coll_frames; 4250 __le64 tx_late_coll_frames; 4251 __le64 tx_excessive_coll_frames; 4252 __le64 tx_frag_frames; 4253 __le64 tx_err; 4254 __le64 tx_tagged_frames; 4255 __le64 tx_dbl_tagged_frames; 4256 __le64 tx_runt_frames; 4257 __le64 tx_fifo_underruns; 4258 __le64 tx_pfc_ena_frames_pri0; 4259 __le64 tx_pfc_ena_frames_pri1; 4260 __le64 tx_pfc_ena_frames_pri2; 4261 __le64 tx_pfc_ena_frames_pri3; 4262 __le64 tx_pfc_ena_frames_pri4; 4263 __le64 tx_pfc_ena_frames_pri5; 4264 __le64 tx_pfc_ena_frames_pri6; 4265 __le64 tx_pfc_ena_frames_pri7; 4266 __le64 tx_eee_lpi_events; 4267 __le64 tx_eee_lpi_duration; 4268 __le64 tx_llfc_logical_msgs; 4269 __le64 tx_hcfc_msgs; 4270 __le64 tx_total_collisions; 4271 __le64 tx_bytes; 4272 __le64 tx_xthol_frames; 4273 __le64 tx_stat_discard; 4274 __le64 tx_stat_error; 4275 }; 4276 4277 /* rx_port_stats (size:4224b/528B) */ 4278 struct rx_port_stats { 4279 __le64 rx_64b_frames; 4280 __le64 rx_65b_127b_frames; 4281 __le64 rx_128b_255b_frames; 4282 __le64 rx_256b_511b_frames; 4283 __le64 rx_512b_1023b_frames; 4284 __le64 rx_1024b_1518b_frames; 4285 __le64 rx_good_vlan_frames; 4286 __le64 rx_1519b_2047b_frames; 4287 __le64 rx_2048b_4095b_frames; 4288 __le64 rx_4096b_9216b_frames; 4289 __le64 rx_9217b_16383b_frames; 4290 __le64 rx_total_frames; 4291 __le64 rx_ucast_frames; 4292 __le64 rx_mcast_frames; 4293 __le64 rx_bcast_frames; 4294 __le64 rx_fcs_err_frames; 4295 __le64 rx_ctrl_frames; 4296 __le64 rx_pause_frames; 4297 __le64 rx_pfc_frames; 4298 __le64 rx_unsupported_opcode_frames; 4299 __le64 rx_unsupported_da_pausepfc_frames; 4300 __le64 rx_wrong_sa_frames; 4301 __le64 rx_align_err_frames; 4302 __le64 rx_oor_len_frames; 4303 __le64 rx_code_err_frames; 4304 __le64 rx_false_carrier_frames; 4305 __le64 rx_ovrsz_frames; 4306 __le64 rx_jbr_frames; 4307 __le64 rx_mtu_err_frames; 4308 __le64 rx_match_crc_frames; 4309 __le64 rx_promiscuous_frames; 4310 __le64 rx_tagged_frames; 4311 __le64 rx_double_tagged_frames; 4312 __le64 rx_trunc_frames; 4313 __le64 rx_good_frames; 4314 __le64 rx_pfc_xon2xoff_frames_pri0; 4315 __le64 rx_pfc_xon2xoff_frames_pri1; 4316 __le64 rx_pfc_xon2xoff_frames_pri2; 4317 __le64 rx_pfc_xon2xoff_frames_pri3; 4318 __le64 rx_pfc_xon2xoff_frames_pri4; 4319 __le64 rx_pfc_xon2xoff_frames_pri5; 4320 __le64 rx_pfc_xon2xoff_frames_pri6; 4321 __le64 rx_pfc_xon2xoff_frames_pri7; 4322 __le64 rx_pfc_ena_frames_pri0; 4323 __le64 rx_pfc_ena_frames_pri1; 4324 __le64 rx_pfc_ena_frames_pri2; 4325 __le64 rx_pfc_ena_frames_pri3; 4326 __le64 rx_pfc_ena_frames_pri4; 4327 __le64 rx_pfc_ena_frames_pri5; 4328 __le64 rx_pfc_ena_frames_pri6; 4329 __le64 rx_pfc_ena_frames_pri7; 4330 __le64 rx_sch_crc_err_frames; 4331 __le64 rx_undrsz_frames; 4332 __le64 rx_frag_frames; 4333 __le64 rx_eee_lpi_events; 4334 __le64 rx_eee_lpi_duration; 4335 __le64 rx_llfc_physical_msgs; 4336 __le64 rx_llfc_logical_msgs; 4337 __le64 rx_llfc_msgs_with_crc_err; 4338 __le64 rx_hcfc_msgs; 4339 __le64 rx_hcfc_msgs_with_crc_err; 4340 __le64 rx_bytes; 4341 __le64 rx_runt_bytes; 4342 __le64 rx_runt_frames; 4343 __le64 rx_stat_discard; 4344 __le64 rx_stat_err; 4345 }; 4346 4347 /* hwrm_port_qstats_input (size:320b/40B) */ 4348 struct hwrm_port_qstats_input { 4349 __le16 req_type; 4350 __le16 cmpl_ring; 4351 __le16 seq_id; 4352 __le16 target_id; 4353 __le64 resp_addr; 4354 __le16 port_id; 4355 u8 flags; 4356 #define PORT_QSTATS_REQ_FLAGS_UNUSED 0x0UL 4357 #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 4358 #define PORT_QSTATS_REQ_FLAGS_LAST PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 4359 u8 unused_0[5]; 4360 __le64 tx_stat_host_addr; 4361 __le64 rx_stat_host_addr; 4362 }; 4363 4364 /* hwrm_port_qstats_output (size:128b/16B) */ 4365 struct hwrm_port_qstats_output { 4366 __le16 error_code; 4367 __le16 req_type; 4368 __le16 seq_id; 4369 __le16 resp_len; 4370 __le16 tx_stat_size; 4371 __le16 rx_stat_size; 4372 u8 unused_0[3]; 4373 u8 valid; 4374 }; 4375 4376 /* tx_port_stats_ext (size:2048b/256B) */ 4377 struct tx_port_stats_ext { 4378 __le64 tx_bytes_cos0; 4379 __le64 tx_bytes_cos1; 4380 __le64 tx_bytes_cos2; 4381 __le64 tx_bytes_cos3; 4382 __le64 tx_bytes_cos4; 4383 __le64 tx_bytes_cos5; 4384 __le64 tx_bytes_cos6; 4385 __le64 tx_bytes_cos7; 4386 __le64 tx_packets_cos0; 4387 __le64 tx_packets_cos1; 4388 __le64 tx_packets_cos2; 4389 __le64 tx_packets_cos3; 4390 __le64 tx_packets_cos4; 4391 __le64 tx_packets_cos5; 4392 __le64 tx_packets_cos6; 4393 __le64 tx_packets_cos7; 4394 __le64 pfc_pri0_tx_duration_us; 4395 __le64 pfc_pri0_tx_transitions; 4396 __le64 pfc_pri1_tx_duration_us; 4397 __le64 pfc_pri1_tx_transitions; 4398 __le64 pfc_pri2_tx_duration_us; 4399 __le64 pfc_pri2_tx_transitions; 4400 __le64 pfc_pri3_tx_duration_us; 4401 __le64 pfc_pri3_tx_transitions; 4402 __le64 pfc_pri4_tx_duration_us; 4403 __le64 pfc_pri4_tx_transitions; 4404 __le64 pfc_pri5_tx_duration_us; 4405 __le64 pfc_pri5_tx_transitions; 4406 __le64 pfc_pri6_tx_duration_us; 4407 __le64 pfc_pri6_tx_transitions; 4408 __le64 pfc_pri7_tx_duration_us; 4409 __le64 pfc_pri7_tx_transitions; 4410 }; 4411 4412 /* rx_port_stats_ext (size:3776b/472B) */ 4413 struct rx_port_stats_ext { 4414 __le64 link_down_events; 4415 __le64 continuous_pause_events; 4416 __le64 resume_pause_events; 4417 __le64 continuous_roce_pause_events; 4418 __le64 resume_roce_pause_events; 4419 __le64 rx_bytes_cos0; 4420 __le64 rx_bytes_cos1; 4421 __le64 rx_bytes_cos2; 4422 __le64 rx_bytes_cos3; 4423 __le64 rx_bytes_cos4; 4424 __le64 rx_bytes_cos5; 4425 __le64 rx_bytes_cos6; 4426 __le64 rx_bytes_cos7; 4427 __le64 rx_packets_cos0; 4428 __le64 rx_packets_cos1; 4429 __le64 rx_packets_cos2; 4430 __le64 rx_packets_cos3; 4431 __le64 rx_packets_cos4; 4432 __le64 rx_packets_cos5; 4433 __le64 rx_packets_cos6; 4434 __le64 rx_packets_cos7; 4435 __le64 pfc_pri0_rx_duration_us; 4436 __le64 pfc_pri0_rx_transitions; 4437 __le64 pfc_pri1_rx_duration_us; 4438 __le64 pfc_pri1_rx_transitions; 4439 __le64 pfc_pri2_rx_duration_us; 4440 __le64 pfc_pri2_rx_transitions; 4441 __le64 pfc_pri3_rx_duration_us; 4442 __le64 pfc_pri3_rx_transitions; 4443 __le64 pfc_pri4_rx_duration_us; 4444 __le64 pfc_pri4_rx_transitions; 4445 __le64 pfc_pri5_rx_duration_us; 4446 __le64 pfc_pri5_rx_transitions; 4447 __le64 pfc_pri6_rx_duration_us; 4448 __le64 pfc_pri6_rx_transitions; 4449 __le64 pfc_pri7_rx_duration_us; 4450 __le64 pfc_pri7_rx_transitions; 4451 __le64 rx_bits; 4452 __le64 rx_buffer_passed_threshold; 4453 __le64 rx_pcs_symbol_err; 4454 __le64 rx_corrected_bits; 4455 __le64 rx_discard_bytes_cos0; 4456 __le64 rx_discard_bytes_cos1; 4457 __le64 rx_discard_bytes_cos2; 4458 __le64 rx_discard_bytes_cos3; 4459 __le64 rx_discard_bytes_cos4; 4460 __le64 rx_discard_bytes_cos5; 4461 __le64 rx_discard_bytes_cos6; 4462 __le64 rx_discard_bytes_cos7; 4463 __le64 rx_discard_packets_cos0; 4464 __le64 rx_discard_packets_cos1; 4465 __le64 rx_discard_packets_cos2; 4466 __le64 rx_discard_packets_cos3; 4467 __le64 rx_discard_packets_cos4; 4468 __le64 rx_discard_packets_cos5; 4469 __le64 rx_discard_packets_cos6; 4470 __le64 rx_discard_packets_cos7; 4471 __le64 rx_fec_corrected_blocks; 4472 __le64 rx_fec_uncorrectable_blocks; 4473 }; 4474 4475 /* hwrm_port_qstats_ext_input (size:320b/40B) */ 4476 struct hwrm_port_qstats_ext_input { 4477 __le16 req_type; 4478 __le16 cmpl_ring; 4479 __le16 seq_id; 4480 __le16 target_id; 4481 __le64 resp_addr; 4482 __le16 port_id; 4483 __le16 tx_stat_size; 4484 __le16 rx_stat_size; 4485 u8 flags; 4486 #define PORT_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 4487 #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL 4488 #define PORT_QSTATS_EXT_REQ_FLAGS_LAST PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 4489 u8 unused_0; 4490 __le64 tx_stat_host_addr; 4491 __le64 rx_stat_host_addr; 4492 }; 4493 4494 /* hwrm_port_qstats_ext_output (size:128b/16B) */ 4495 struct hwrm_port_qstats_ext_output { 4496 __le16 error_code; 4497 __le16 req_type; 4498 __le16 seq_id; 4499 __le16 resp_len; 4500 __le16 tx_stat_size; 4501 __le16 rx_stat_size; 4502 __le16 total_active_cos_queues; 4503 u8 flags; 4504 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 4505 u8 valid; 4506 }; 4507 4508 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */ 4509 struct hwrm_port_lpbk_qstats_input { 4510 __le16 req_type; 4511 __le16 cmpl_ring; 4512 __le16 seq_id; 4513 __le16 target_id; 4514 __le64 resp_addr; 4515 }; 4516 4517 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */ 4518 struct hwrm_port_lpbk_qstats_output { 4519 __le16 error_code; 4520 __le16 req_type; 4521 __le16 seq_id; 4522 __le16 resp_len; 4523 __le64 lpbk_ucast_frames; 4524 __le64 lpbk_mcast_frames; 4525 __le64 lpbk_bcast_frames; 4526 __le64 lpbk_ucast_bytes; 4527 __le64 lpbk_mcast_bytes; 4528 __le64 lpbk_bcast_bytes; 4529 __le64 tx_stat_discard; 4530 __le64 tx_stat_error; 4531 __le64 rx_stat_discard; 4532 __le64 rx_stat_error; 4533 u8 unused_0[7]; 4534 u8 valid; 4535 }; 4536 4537 /* hwrm_port_ecn_qstats_input (size:256b/32B) */ 4538 struct hwrm_port_ecn_qstats_input { 4539 __le16 req_type; 4540 __le16 cmpl_ring; 4541 __le16 seq_id; 4542 __le16 target_id; 4543 __le64 resp_addr; 4544 __le16 port_id; 4545 __le16 ecn_stat_buf_size; 4546 u8 flags; 4547 #define PORT_ECN_QSTATS_REQ_FLAGS_UNUSED 0x0UL 4548 #define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 4549 #define PORT_ECN_QSTATS_REQ_FLAGS_LAST PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 4550 u8 unused_0[3]; 4551 __le64 ecn_stat_host_addr; 4552 }; 4553 4554 /* hwrm_port_ecn_qstats_output (size:128b/16B) */ 4555 struct hwrm_port_ecn_qstats_output { 4556 __le16 error_code; 4557 __le16 req_type; 4558 __le16 seq_id; 4559 __le16 resp_len; 4560 __le16 ecn_stat_buf_size; 4561 u8 mark_en; 4562 u8 unused_0[4]; 4563 u8 valid; 4564 }; 4565 4566 /* port_stats_ecn (size:512b/64B) */ 4567 struct port_stats_ecn { 4568 __le64 mark_cnt_cos0; 4569 __le64 mark_cnt_cos1; 4570 __le64 mark_cnt_cos2; 4571 __le64 mark_cnt_cos3; 4572 __le64 mark_cnt_cos4; 4573 __le64 mark_cnt_cos5; 4574 __le64 mark_cnt_cos6; 4575 __le64 mark_cnt_cos7; 4576 }; 4577 4578 /* hwrm_port_clr_stats_input (size:192b/24B) */ 4579 struct hwrm_port_clr_stats_input { 4580 __le16 req_type; 4581 __le16 cmpl_ring; 4582 __le16 seq_id; 4583 __le16 target_id; 4584 __le64 resp_addr; 4585 __le16 port_id; 4586 u8 flags; 4587 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 4588 u8 unused_0[5]; 4589 }; 4590 4591 /* hwrm_port_clr_stats_output (size:128b/16B) */ 4592 struct hwrm_port_clr_stats_output { 4593 __le16 error_code; 4594 __le16 req_type; 4595 __le16 seq_id; 4596 __le16 resp_len; 4597 u8 unused_0[7]; 4598 u8 valid; 4599 }; 4600 4601 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ 4602 struct hwrm_port_lpbk_clr_stats_input { 4603 __le16 req_type; 4604 __le16 cmpl_ring; 4605 __le16 seq_id; 4606 __le16 target_id; 4607 __le64 resp_addr; 4608 }; 4609 4610 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 4611 struct hwrm_port_lpbk_clr_stats_output { 4612 __le16 error_code; 4613 __le16 req_type; 4614 __le16 seq_id; 4615 __le16 resp_len; 4616 u8 unused_0[7]; 4617 u8 valid; 4618 }; 4619 4620 /* hwrm_port_ts_query_input (size:320b/40B) */ 4621 struct hwrm_port_ts_query_input { 4622 __le16 req_type; 4623 __le16 cmpl_ring; 4624 __le16 seq_id; 4625 __le16 target_id; 4626 __le64 resp_addr; 4627 __le32 flags; 4628 #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL 4629 #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL 4630 #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL 4631 #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX 4632 #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL 4633 __le16 port_id; 4634 u8 unused_0[2]; 4635 __le16 enables; 4636 #define PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT 0x1UL 4637 #define PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID 0x2UL 4638 #define PORT_TS_QUERY_REQ_ENABLES_PTP_HDR_OFFSET 0x4UL 4639 __le16 ts_req_timeout; 4640 __le32 ptp_seq_id; 4641 __le16 ptp_hdr_offset; 4642 u8 unused_1[6]; 4643 }; 4644 4645 /* hwrm_port_ts_query_output (size:192b/24B) */ 4646 struct hwrm_port_ts_query_output { 4647 __le16 error_code; 4648 __le16 req_type; 4649 __le16 seq_id; 4650 __le16 resp_len; 4651 __le64 ptp_msg_ts; 4652 __le16 ptp_msg_seqid; 4653 u8 unused_0[5]; 4654 u8 valid; 4655 }; 4656 4657 /* hwrm_port_phy_qcaps_input (size:192b/24B) */ 4658 struct hwrm_port_phy_qcaps_input { 4659 __le16 req_type; 4660 __le16 cmpl_ring; 4661 __le16 seq_id; 4662 __le16 target_id; 4663 __le64 resp_addr; 4664 __le16 port_id; 4665 u8 unused_0[6]; 4666 }; 4667 4668 /* hwrm_port_phy_qcaps_output (size:256b/32B) */ 4669 struct hwrm_port_phy_qcaps_output { 4670 __le16 error_code; 4671 __le16 req_type; 4672 __le16 seq_id; 4673 __le16 resp_len; 4674 u8 flags; 4675 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 4676 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 4677 #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL 4678 #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL 4679 #define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL 4680 #define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x20UL 4681 #define PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN 0x40UL 4682 #define PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS 0x80UL 4683 u8 port_cnt; 4684 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 4685 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 4686 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 4687 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 4688 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 4689 #define PORT_PHY_QCAPS_RESP_PORT_CNT_12 0xcUL 4690 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_12 4691 __le16 supported_speeds_force_mode; 4692 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 4693 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 4694 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 4695 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 4696 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 4697 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 4698 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 4699 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 4700 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 4701 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 4702 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 4703 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 4704 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 4705 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 4706 __le16 supported_speeds_auto_mode; 4707 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 4708 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 4709 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 4710 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 4711 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 4712 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 4713 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 4714 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 4715 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 4716 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 4717 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 4718 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 4719 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 4720 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 4721 __le16 supported_speeds_eee_mode; 4722 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 4723 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 4724 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 4725 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 4726 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 4727 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 4728 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 4729 __le32 tx_lpi_timer_low; 4730 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 4731 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 4732 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 4733 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 4734 __le32 valid_tx_lpi_timer_high; 4735 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 4736 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 4737 #define PORT_PHY_QCAPS_RESP_RSVD_MASK 0xff000000UL 4738 #define PORT_PHY_QCAPS_RESP_RSVD_SFT 24 4739 __le16 supported_pam4_speeds_auto_mode; 4740 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL 4741 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL 4742 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL 4743 __le16 supported_pam4_speeds_force_mode; 4744 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL 4745 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL 4746 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL 4747 __le16 flags2; 4748 #define PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED 0x1UL 4749 #define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED 0x2UL 4750 u8 internal_port_cnt; 4751 u8 valid; 4752 }; 4753 4754 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 4755 struct hwrm_port_phy_i2c_read_input { 4756 __le16 req_type; 4757 __le16 cmpl_ring; 4758 __le16 seq_id; 4759 __le16 target_id; 4760 __le64 resp_addr; 4761 __le32 flags; 4762 __le32 enables; 4763 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 4764 __le16 port_id; 4765 u8 i2c_slave_addr; 4766 u8 unused_0; 4767 __le16 page_number; 4768 __le16 page_offset; 4769 u8 data_length; 4770 u8 unused_1[7]; 4771 }; 4772 4773 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 4774 struct hwrm_port_phy_i2c_read_output { 4775 __le16 error_code; 4776 __le16 req_type; 4777 __le16 seq_id; 4778 __le16 resp_len; 4779 __le32 data[16]; 4780 u8 unused_0[7]; 4781 u8 valid; 4782 }; 4783 4784 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */ 4785 struct hwrm_port_phy_mdio_write_input { 4786 __le16 req_type; 4787 __le16 cmpl_ring; 4788 __le16 seq_id; 4789 __le16 target_id; 4790 __le64 resp_addr; 4791 __le32 unused_0[2]; 4792 __le16 port_id; 4793 u8 phy_addr; 4794 u8 dev_addr; 4795 __le16 reg_addr; 4796 __le16 reg_data; 4797 u8 cl45_mdio; 4798 u8 unused_1[7]; 4799 }; 4800 4801 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */ 4802 struct hwrm_port_phy_mdio_write_output { 4803 __le16 error_code; 4804 __le16 req_type; 4805 __le16 seq_id; 4806 __le16 resp_len; 4807 u8 unused_0[7]; 4808 u8 valid; 4809 }; 4810 4811 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */ 4812 struct hwrm_port_phy_mdio_read_input { 4813 __le16 req_type; 4814 __le16 cmpl_ring; 4815 __le16 seq_id; 4816 __le16 target_id; 4817 __le64 resp_addr; 4818 __le32 unused_0[2]; 4819 __le16 port_id; 4820 u8 phy_addr; 4821 u8 dev_addr; 4822 __le16 reg_addr; 4823 u8 cl45_mdio; 4824 u8 unused_1; 4825 }; 4826 4827 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */ 4828 struct hwrm_port_phy_mdio_read_output { 4829 __le16 error_code; 4830 __le16 req_type; 4831 __le16 seq_id; 4832 __le16 resp_len; 4833 __le16 reg_data; 4834 u8 unused_0[5]; 4835 u8 valid; 4836 }; 4837 4838 /* hwrm_port_led_cfg_input (size:512b/64B) */ 4839 struct hwrm_port_led_cfg_input { 4840 __le16 req_type; 4841 __le16 cmpl_ring; 4842 __le16 seq_id; 4843 __le16 target_id; 4844 __le64 resp_addr; 4845 __le32 enables; 4846 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 4847 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 4848 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 4849 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 4850 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 4851 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 4852 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 4853 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 4854 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 4855 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 4856 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 4857 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 4858 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 4859 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 4860 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 4861 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 4862 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 4863 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 4864 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 4865 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 4866 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 4867 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 4868 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 4869 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 4870 __le16 port_id; 4871 u8 num_leds; 4872 u8 rsvd; 4873 u8 led0_id; 4874 u8 led0_state; 4875 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 4876 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 4877 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 4878 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 4879 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 4880 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 4881 u8 led0_color; 4882 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 4883 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 4884 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 4885 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 4886 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 4887 u8 unused_0; 4888 __le16 led0_blink_on; 4889 __le16 led0_blink_off; 4890 u8 led0_group_id; 4891 u8 rsvd0; 4892 u8 led1_id; 4893 u8 led1_state; 4894 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 4895 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 4896 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 4897 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 4898 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 4899 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 4900 u8 led1_color; 4901 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 4902 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 4903 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 4904 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 4905 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 4906 u8 unused_1; 4907 __le16 led1_blink_on; 4908 __le16 led1_blink_off; 4909 u8 led1_group_id; 4910 u8 rsvd1; 4911 u8 led2_id; 4912 u8 led2_state; 4913 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 4914 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 4915 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 4916 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 4917 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 4918 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 4919 u8 led2_color; 4920 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 4921 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 4922 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 4923 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 4924 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 4925 u8 unused_2; 4926 __le16 led2_blink_on; 4927 __le16 led2_blink_off; 4928 u8 led2_group_id; 4929 u8 rsvd2; 4930 u8 led3_id; 4931 u8 led3_state; 4932 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 4933 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 4934 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 4935 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 4936 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 4937 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 4938 u8 led3_color; 4939 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 4940 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 4941 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 4942 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 4943 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 4944 u8 unused_3; 4945 __le16 led3_blink_on; 4946 __le16 led3_blink_off; 4947 u8 led3_group_id; 4948 u8 rsvd3; 4949 }; 4950 4951 /* hwrm_port_led_cfg_output (size:128b/16B) */ 4952 struct hwrm_port_led_cfg_output { 4953 __le16 error_code; 4954 __le16 req_type; 4955 __le16 seq_id; 4956 __le16 resp_len; 4957 u8 unused_0[7]; 4958 u8 valid; 4959 }; 4960 4961 /* hwrm_port_led_qcfg_input (size:192b/24B) */ 4962 struct hwrm_port_led_qcfg_input { 4963 __le16 req_type; 4964 __le16 cmpl_ring; 4965 __le16 seq_id; 4966 __le16 target_id; 4967 __le64 resp_addr; 4968 __le16 port_id; 4969 u8 unused_0[6]; 4970 }; 4971 4972 /* hwrm_port_led_qcfg_output (size:448b/56B) */ 4973 struct hwrm_port_led_qcfg_output { 4974 __le16 error_code; 4975 __le16 req_type; 4976 __le16 seq_id; 4977 __le16 resp_len; 4978 u8 num_leds; 4979 u8 led0_id; 4980 u8 led0_type; 4981 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 4982 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 4983 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 4984 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 4985 u8 led0_state; 4986 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 4987 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 4988 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 4989 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 4990 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 4991 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 4992 u8 led0_color; 4993 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 4994 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 4995 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 4996 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 4997 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 4998 u8 unused_0; 4999 __le16 led0_blink_on; 5000 __le16 led0_blink_off; 5001 u8 led0_group_id; 5002 u8 led1_id; 5003 u8 led1_type; 5004 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 5005 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 5006 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 5007 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 5008 u8 led1_state; 5009 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 5010 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 5011 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 5012 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 5013 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 5014 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 5015 u8 led1_color; 5016 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 5017 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 5018 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 5019 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 5020 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 5021 u8 unused_1; 5022 __le16 led1_blink_on; 5023 __le16 led1_blink_off; 5024 u8 led1_group_id; 5025 u8 led2_id; 5026 u8 led2_type; 5027 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 5028 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 5029 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 5030 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 5031 u8 led2_state; 5032 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 5033 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 5034 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 5035 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 5036 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 5037 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 5038 u8 led2_color; 5039 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 5040 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 5041 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 5042 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 5043 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 5044 u8 unused_2; 5045 __le16 led2_blink_on; 5046 __le16 led2_blink_off; 5047 u8 led2_group_id; 5048 u8 led3_id; 5049 u8 led3_type; 5050 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 5051 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 5052 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 5053 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 5054 u8 led3_state; 5055 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 5056 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 5057 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 5058 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 5059 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 5060 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 5061 u8 led3_color; 5062 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 5063 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 5064 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 5065 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 5066 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 5067 u8 unused_3; 5068 __le16 led3_blink_on; 5069 __le16 led3_blink_off; 5070 u8 led3_group_id; 5071 u8 unused_4[6]; 5072 u8 valid; 5073 }; 5074 5075 /* hwrm_port_led_qcaps_input (size:192b/24B) */ 5076 struct hwrm_port_led_qcaps_input { 5077 __le16 req_type; 5078 __le16 cmpl_ring; 5079 __le16 seq_id; 5080 __le16 target_id; 5081 __le64 resp_addr; 5082 __le16 port_id; 5083 u8 unused_0[6]; 5084 }; 5085 5086 /* hwrm_port_led_qcaps_output (size:384b/48B) */ 5087 struct hwrm_port_led_qcaps_output { 5088 __le16 error_code; 5089 __le16 req_type; 5090 __le16 seq_id; 5091 __le16 resp_len; 5092 u8 num_leds; 5093 u8 unused[3]; 5094 u8 led0_id; 5095 u8 led0_type; 5096 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 5097 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 5098 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 5099 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 5100 u8 led0_group_id; 5101 u8 unused_0; 5102 __le16 led0_state_caps; 5103 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 5104 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 5105 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 5106 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5107 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5108 __le16 led0_color_caps; 5109 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 5110 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5111 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5112 u8 led1_id; 5113 u8 led1_type; 5114 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 5115 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 5116 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 5117 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 5118 u8 led1_group_id; 5119 u8 unused_1; 5120 __le16 led1_state_caps; 5121 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 5122 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 5123 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 5124 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5125 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5126 __le16 led1_color_caps; 5127 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 5128 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5129 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5130 u8 led2_id; 5131 u8 led2_type; 5132 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 5133 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 5134 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 5135 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 5136 u8 led2_group_id; 5137 u8 unused_2; 5138 __le16 led2_state_caps; 5139 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 5140 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 5141 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 5142 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5143 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5144 __le16 led2_color_caps; 5145 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 5146 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5147 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5148 u8 led3_id; 5149 u8 led3_type; 5150 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 5151 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 5152 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 5153 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 5154 u8 led3_group_id; 5155 u8 unused_3; 5156 __le16 led3_state_caps; 5157 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 5158 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 5159 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 5160 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5161 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5162 __le16 led3_color_caps; 5163 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 5164 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5165 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5166 u8 unused_4[3]; 5167 u8 valid; 5168 }; 5169 5170 /* hwrm_queue_qportcfg_input (size:192b/24B) */ 5171 struct hwrm_queue_qportcfg_input { 5172 __le16 req_type; 5173 __le16 cmpl_ring; 5174 __le16 seq_id; 5175 __le16 target_id; 5176 __le64 resp_addr; 5177 __le32 flags; 5178 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 5179 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 5180 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 5181 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 5182 __le16 port_id; 5183 u8 drv_qmap_cap; 5184 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 5185 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 5186 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 5187 u8 unused_0; 5188 }; 5189 5190 /* hwrm_queue_qportcfg_output (size:1344b/168B) */ 5191 struct hwrm_queue_qportcfg_output { 5192 __le16 error_code; 5193 __le16 req_type; 5194 __le16 seq_id; 5195 __le16 resp_len; 5196 u8 max_configurable_queues; 5197 u8 max_configurable_lossless_queues; 5198 u8 queue_cfg_allowed; 5199 u8 queue_cfg_info; 5200 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 5201 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_USE_PROFILE_TYPE 0x2UL 5202 u8 queue_pfcenable_cfg_allowed; 5203 u8 queue_pri2cos_cfg_allowed; 5204 u8 queue_cos2bw_cfg_allowed; 5205 u8 queue_id0; 5206 u8 queue_id0_service_profile; 5207 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 5208 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 5209 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5210 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5211 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5212 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 5213 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 5214 u8 queue_id1; 5215 u8 queue_id1_service_profile; 5216 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 5217 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 5218 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5219 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5220 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5221 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 5222 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 5223 u8 queue_id2; 5224 u8 queue_id2_service_profile; 5225 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 5226 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 5227 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5228 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5229 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5230 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 5231 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 5232 u8 queue_id3; 5233 u8 queue_id3_service_profile; 5234 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 5235 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 5236 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5237 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5238 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5239 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 5240 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 5241 u8 queue_id4; 5242 u8 queue_id4_service_profile; 5243 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 5244 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 5245 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5246 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5247 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5248 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 5249 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 5250 u8 queue_id5; 5251 u8 queue_id5_service_profile; 5252 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 5253 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 5254 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5255 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5256 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5257 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 5258 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 5259 u8 queue_id6; 5260 u8 queue_id6_service_profile; 5261 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 5262 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 5263 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5264 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5265 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5266 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 5267 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 5268 u8 queue_id7; 5269 u8 queue_id7_service_profile; 5270 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 5271 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 5272 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5273 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5274 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5275 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 5276 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 5277 u8 queue_id0_service_profile_type; 5278 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5279 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC 0x2UL 5280 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP 0x4UL 5281 char qid0_name[16]; 5282 char qid1_name[16]; 5283 char qid2_name[16]; 5284 char qid3_name[16]; 5285 char qid4_name[16]; 5286 char qid5_name[16]; 5287 char qid6_name[16]; 5288 char qid7_name[16]; 5289 u8 queue_id1_service_profile_type; 5290 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5291 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC 0x2UL 5292 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP 0x4UL 5293 u8 queue_id2_service_profile_type; 5294 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5295 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC 0x2UL 5296 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP 0x4UL 5297 u8 queue_id3_service_profile_type; 5298 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5299 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC 0x2UL 5300 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP 0x4UL 5301 u8 queue_id4_service_profile_type; 5302 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5303 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC 0x2UL 5304 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP 0x4UL 5305 u8 queue_id5_service_profile_type; 5306 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5307 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC 0x2UL 5308 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP 0x4UL 5309 u8 queue_id6_service_profile_type; 5310 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5311 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC 0x2UL 5312 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP 0x4UL 5313 u8 queue_id7_service_profile_type; 5314 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE 0x1UL 5315 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC 0x2UL 5316 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP 0x4UL 5317 u8 valid; 5318 }; 5319 5320 /* hwrm_queue_qcfg_input (size:192b/24B) */ 5321 struct hwrm_queue_qcfg_input { 5322 __le16 req_type; 5323 __le16 cmpl_ring; 5324 __le16 seq_id; 5325 __le16 target_id; 5326 __le64 resp_addr; 5327 __le32 flags; 5328 #define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL 5329 #define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL 5330 #define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL 5331 #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX 5332 __le32 queue_id; 5333 }; 5334 5335 /* hwrm_queue_qcfg_output (size:128b/16B) */ 5336 struct hwrm_queue_qcfg_output { 5337 __le16 error_code; 5338 __le16 req_type; 5339 __le16 seq_id; 5340 __le16 resp_len; 5341 __le32 queue_len; 5342 u8 service_profile; 5343 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL 5344 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL 5345 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL 5346 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 5347 u8 queue_cfg_info; 5348 #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 5349 u8 unused_0; 5350 u8 valid; 5351 }; 5352 5353 /* hwrm_queue_cfg_input (size:320b/40B) */ 5354 struct hwrm_queue_cfg_input { 5355 __le16 req_type; 5356 __le16 cmpl_ring; 5357 __le16 seq_id; 5358 __le16 target_id; 5359 __le64 resp_addr; 5360 __le32 flags; 5361 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 5362 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 5363 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 5364 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 5365 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 5366 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 5367 __le32 enables; 5368 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 5369 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 5370 __le32 queue_id; 5371 __le32 dflt_len; 5372 u8 service_profile; 5373 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 5374 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 5375 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 5376 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 5377 u8 unused_0[7]; 5378 }; 5379 5380 /* hwrm_queue_cfg_output (size:128b/16B) */ 5381 struct hwrm_queue_cfg_output { 5382 __le16 error_code; 5383 __le16 req_type; 5384 __le16 seq_id; 5385 __le16 resp_len; 5386 u8 unused_0[7]; 5387 u8 valid; 5388 }; 5389 5390 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 5391 struct hwrm_queue_pfcenable_qcfg_input { 5392 __le16 req_type; 5393 __le16 cmpl_ring; 5394 __le16 seq_id; 5395 __le16 target_id; 5396 __le64 resp_addr; 5397 __le16 port_id; 5398 u8 unused_0[6]; 5399 }; 5400 5401 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 5402 struct hwrm_queue_pfcenable_qcfg_output { 5403 __le16 error_code; 5404 __le16 req_type; 5405 __le16 seq_id; 5406 __le16 resp_len; 5407 __le32 flags; 5408 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 5409 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 5410 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 5411 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 5412 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 5413 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 5414 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 5415 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 5416 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 5417 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 5418 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 5419 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 5420 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 5421 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 5422 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 5423 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 5424 u8 unused_0[3]; 5425 u8 valid; 5426 }; 5427 5428 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 5429 struct hwrm_queue_pfcenable_cfg_input { 5430 __le16 req_type; 5431 __le16 cmpl_ring; 5432 __le16 seq_id; 5433 __le16 target_id; 5434 __le64 resp_addr; 5435 __le32 flags; 5436 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 5437 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 5438 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 5439 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 5440 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 5441 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 5442 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 5443 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 5444 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 5445 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 5446 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 5447 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 5448 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 5449 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 5450 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 5451 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 5452 __le16 port_id; 5453 u8 unused_0[2]; 5454 }; 5455 5456 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 5457 struct hwrm_queue_pfcenable_cfg_output { 5458 __le16 error_code; 5459 __le16 req_type; 5460 __le16 seq_id; 5461 __le16 resp_len; 5462 u8 unused_0[7]; 5463 u8 valid; 5464 }; 5465 5466 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 5467 struct hwrm_queue_pri2cos_qcfg_input { 5468 __le16 req_type; 5469 __le16 cmpl_ring; 5470 __le16 seq_id; 5471 __le16 target_id; 5472 __le64 resp_addr; 5473 __le32 flags; 5474 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 5475 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 5476 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 5477 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 5478 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 5479 u8 port_id; 5480 u8 unused_0[3]; 5481 }; 5482 5483 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 5484 struct hwrm_queue_pri2cos_qcfg_output { 5485 __le16 error_code; 5486 __le16 req_type; 5487 __le16 seq_id; 5488 __le16 resp_len; 5489 u8 pri0_cos_queue_id; 5490 u8 pri1_cos_queue_id; 5491 u8 pri2_cos_queue_id; 5492 u8 pri3_cos_queue_id; 5493 u8 pri4_cos_queue_id; 5494 u8 pri5_cos_queue_id; 5495 u8 pri6_cos_queue_id; 5496 u8 pri7_cos_queue_id; 5497 u8 queue_cfg_info; 5498 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 5499 u8 unused_0[6]; 5500 u8 valid; 5501 }; 5502 5503 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 5504 struct hwrm_queue_pri2cos_cfg_input { 5505 __le16 req_type; 5506 __le16 cmpl_ring; 5507 __le16 seq_id; 5508 __le16 target_id; 5509 __le64 resp_addr; 5510 __le32 flags; 5511 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 5512 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 5513 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 5514 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 5515 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 5516 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 5517 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 5518 __le32 enables; 5519 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 5520 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 5521 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 5522 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 5523 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 5524 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 5525 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 5526 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 5527 u8 port_id; 5528 u8 pri0_cos_queue_id; 5529 u8 pri1_cos_queue_id; 5530 u8 pri2_cos_queue_id; 5531 u8 pri3_cos_queue_id; 5532 u8 pri4_cos_queue_id; 5533 u8 pri5_cos_queue_id; 5534 u8 pri6_cos_queue_id; 5535 u8 pri7_cos_queue_id; 5536 u8 unused_0[7]; 5537 }; 5538 5539 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 5540 struct hwrm_queue_pri2cos_cfg_output { 5541 __le16 error_code; 5542 __le16 req_type; 5543 __le16 seq_id; 5544 __le16 resp_len; 5545 u8 unused_0[7]; 5546 u8 valid; 5547 }; 5548 5549 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 5550 struct hwrm_queue_cos2bw_qcfg_input { 5551 __le16 req_type; 5552 __le16 cmpl_ring; 5553 __le16 seq_id; 5554 __le16 target_id; 5555 __le64 resp_addr; 5556 __le16 port_id; 5557 u8 unused_0[6]; 5558 }; 5559 5560 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 5561 struct hwrm_queue_cos2bw_qcfg_output { 5562 __le16 error_code; 5563 __le16 req_type; 5564 __le16 seq_id; 5565 __le16 resp_len; 5566 u8 queue_id0; 5567 u8 unused_0; 5568 __le16 unused_1; 5569 __le32 queue_id0_min_bw; 5570 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5571 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 5572 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 5573 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 5574 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 5575 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 5576 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5577 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 5578 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5579 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5580 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5581 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5582 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5583 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5584 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 5585 __le32 queue_id0_max_bw; 5586 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5587 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 5588 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 5589 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 5590 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 5591 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 5592 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5593 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 5594 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5595 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5596 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5597 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5598 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5599 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5600 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 5601 u8 queue_id0_tsa_assign; 5602 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 5603 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 5604 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5605 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 5606 u8 queue_id0_pri_lvl; 5607 u8 queue_id0_bw_weight; 5608 u8 queue_id1; 5609 __le32 queue_id1_min_bw; 5610 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5611 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 5612 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 5613 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 5614 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 5615 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 5616 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5617 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 5618 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5619 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5620 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5621 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5622 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5623 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5624 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 5625 __le32 queue_id1_max_bw; 5626 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5627 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 5628 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 5629 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 5630 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 5631 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 5632 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5633 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 5634 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5635 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5636 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5637 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5638 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5639 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5640 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 5641 u8 queue_id1_tsa_assign; 5642 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 5643 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 5644 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5645 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 5646 u8 queue_id1_pri_lvl; 5647 u8 queue_id1_bw_weight; 5648 u8 queue_id2; 5649 __le32 queue_id2_min_bw; 5650 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5651 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 5652 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 5653 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 5654 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 5655 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 5656 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5657 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 5658 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5659 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5660 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5661 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5662 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5663 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5664 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 5665 __le32 queue_id2_max_bw; 5666 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5667 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 5668 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 5669 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 5670 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 5671 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 5672 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5673 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 5674 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5675 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5676 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5677 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5678 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5679 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5680 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 5681 u8 queue_id2_tsa_assign; 5682 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 5683 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 5684 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5685 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 5686 u8 queue_id2_pri_lvl; 5687 u8 queue_id2_bw_weight; 5688 u8 queue_id3; 5689 __le32 queue_id3_min_bw; 5690 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5691 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 5692 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 5693 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 5694 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 5695 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 5696 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5697 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 5698 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5699 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5700 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5701 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5702 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5703 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5704 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 5705 __le32 queue_id3_max_bw; 5706 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5707 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 5708 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 5709 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 5710 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 5711 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 5712 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5713 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 5714 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5715 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5716 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5717 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5718 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5719 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5720 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 5721 u8 queue_id3_tsa_assign; 5722 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 5723 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 5724 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5725 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 5726 u8 queue_id3_pri_lvl; 5727 u8 queue_id3_bw_weight; 5728 u8 queue_id4; 5729 __le32 queue_id4_min_bw; 5730 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5731 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 5732 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 5733 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 5734 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 5735 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 5736 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5737 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 5738 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5739 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5740 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5741 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5742 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5743 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5744 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 5745 __le32 queue_id4_max_bw; 5746 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5747 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 5748 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 5749 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 5750 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 5751 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 5752 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5753 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 5754 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5755 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5756 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5757 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5758 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5759 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5760 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 5761 u8 queue_id4_tsa_assign; 5762 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 5763 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 5764 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5765 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 5766 u8 queue_id4_pri_lvl; 5767 u8 queue_id4_bw_weight; 5768 u8 queue_id5; 5769 __le32 queue_id5_min_bw; 5770 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5771 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 5772 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 5773 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 5774 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 5775 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 5776 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5777 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 5778 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5779 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5780 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5781 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5782 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5783 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5784 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 5785 __le32 queue_id5_max_bw; 5786 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5787 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 5788 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 5789 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 5790 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 5791 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 5792 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5793 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 5794 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5795 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5796 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5797 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5798 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5799 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5800 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 5801 u8 queue_id5_tsa_assign; 5802 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 5803 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 5804 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5805 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 5806 u8 queue_id5_pri_lvl; 5807 u8 queue_id5_bw_weight; 5808 u8 queue_id6; 5809 __le32 queue_id6_min_bw; 5810 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5811 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 5812 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 5813 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 5814 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 5815 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 5816 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5817 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 5818 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5819 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5820 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5821 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5822 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5823 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5824 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 5825 __le32 queue_id6_max_bw; 5826 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5827 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 5828 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 5829 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 5830 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 5831 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 5832 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5833 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 5834 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5835 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5836 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5837 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5838 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5839 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5840 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 5841 u8 queue_id6_tsa_assign; 5842 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 5843 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 5844 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5845 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 5846 u8 queue_id6_pri_lvl; 5847 u8 queue_id6_bw_weight; 5848 u8 queue_id7; 5849 __le32 queue_id7_min_bw; 5850 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5851 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 5852 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 5853 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 5854 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 5855 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 5856 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5857 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 5858 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5859 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5860 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5861 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5862 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5863 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5864 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 5865 __le32 queue_id7_max_bw; 5866 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5867 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 5868 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 5869 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 5870 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 5871 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 5872 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5873 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 5874 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5875 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5876 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5877 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5878 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5879 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5880 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 5881 u8 queue_id7_tsa_assign; 5882 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 5883 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 5884 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5885 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 5886 u8 queue_id7_pri_lvl; 5887 u8 queue_id7_bw_weight; 5888 u8 unused_2[4]; 5889 u8 valid; 5890 }; 5891 5892 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 5893 struct hwrm_queue_cos2bw_cfg_input { 5894 __le16 req_type; 5895 __le16 cmpl_ring; 5896 __le16 seq_id; 5897 __le16 target_id; 5898 __le64 resp_addr; 5899 __le32 flags; 5900 __le32 enables; 5901 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 5902 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 5903 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 5904 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 5905 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 5906 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 5907 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 5908 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 5909 __le16 port_id; 5910 u8 queue_id0; 5911 u8 unused_0; 5912 __le32 queue_id0_min_bw; 5913 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5914 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 5915 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 5916 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 5917 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 5918 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 5919 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5920 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 5921 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5922 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5923 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5924 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5925 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5926 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5927 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 5928 __le32 queue_id0_max_bw; 5929 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5930 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 5931 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 5932 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 5933 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 5934 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 5935 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5936 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 5937 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5938 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5939 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5940 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5941 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5942 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5943 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 5944 u8 queue_id0_tsa_assign; 5945 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 5946 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 5947 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5948 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 5949 u8 queue_id0_pri_lvl; 5950 u8 queue_id0_bw_weight; 5951 u8 queue_id1; 5952 __le32 queue_id1_min_bw; 5953 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5954 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 5955 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 5956 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 5957 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 5958 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 5959 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5960 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 5961 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5962 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5963 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5964 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5965 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5966 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5967 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 5968 __le32 queue_id1_max_bw; 5969 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5970 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 5971 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 5972 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 5973 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 5974 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 5975 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5976 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 5977 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5978 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5979 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5980 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5981 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5982 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5983 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 5984 u8 queue_id1_tsa_assign; 5985 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 5986 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 5987 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5988 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 5989 u8 queue_id1_pri_lvl; 5990 u8 queue_id1_bw_weight; 5991 u8 queue_id2; 5992 __le32 queue_id2_min_bw; 5993 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5994 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 5995 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 5996 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 5997 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 5998 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 5999 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6000 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 6001 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6002 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6003 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6004 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6005 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6006 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6007 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 6008 __le32 queue_id2_max_bw; 6009 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6010 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 6011 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 6012 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 6013 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 6014 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 6015 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6016 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 6017 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6018 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6019 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6020 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6021 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6022 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6023 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 6024 u8 queue_id2_tsa_assign; 6025 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 6026 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 6027 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6028 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 6029 u8 queue_id2_pri_lvl; 6030 u8 queue_id2_bw_weight; 6031 u8 queue_id3; 6032 __le32 queue_id3_min_bw; 6033 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6034 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 6035 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 6036 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 6037 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 6038 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 6039 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6040 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 6041 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6042 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6043 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6044 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6045 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6046 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6047 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 6048 __le32 queue_id3_max_bw; 6049 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6050 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 6051 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 6052 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 6053 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 6054 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 6055 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6056 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 6057 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6058 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6059 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6060 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6061 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6062 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6063 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 6064 u8 queue_id3_tsa_assign; 6065 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 6066 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 6067 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6068 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 6069 u8 queue_id3_pri_lvl; 6070 u8 queue_id3_bw_weight; 6071 u8 queue_id4; 6072 __le32 queue_id4_min_bw; 6073 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6074 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 6075 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 6076 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 6077 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 6078 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 6079 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6080 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 6081 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6082 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6083 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6084 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6085 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6086 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6087 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 6088 __le32 queue_id4_max_bw; 6089 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6090 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 6091 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 6092 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 6093 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 6094 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 6095 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6096 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 6097 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6098 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6099 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6100 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6101 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6102 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6103 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 6104 u8 queue_id4_tsa_assign; 6105 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 6106 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 6107 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6108 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 6109 u8 queue_id4_pri_lvl; 6110 u8 queue_id4_bw_weight; 6111 u8 queue_id5; 6112 __le32 queue_id5_min_bw; 6113 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6114 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 6115 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 6116 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 6117 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 6118 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 6119 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6120 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 6121 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6122 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6123 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6124 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6125 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6126 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6127 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 6128 __le32 queue_id5_max_bw; 6129 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6130 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 6131 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 6132 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 6133 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 6134 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 6135 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6136 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 6137 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6138 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6139 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6140 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6141 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6142 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6143 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 6144 u8 queue_id5_tsa_assign; 6145 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 6146 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 6147 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6148 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 6149 u8 queue_id5_pri_lvl; 6150 u8 queue_id5_bw_weight; 6151 u8 queue_id6; 6152 __le32 queue_id6_min_bw; 6153 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6154 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 6155 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 6156 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 6157 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 6158 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 6159 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6160 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 6161 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6162 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6163 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6164 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6165 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6166 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6167 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 6168 __le32 queue_id6_max_bw; 6169 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6170 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 6171 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 6172 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 6173 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 6174 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 6175 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6176 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 6177 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6178 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6179 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6180 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6181 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6182 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6183 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 6184 u8 queue_id6_tsa_assign; 6185 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 6186 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 6187 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6188 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 6189 u8 queue_id6_pri_lvl; 6190 u8 queue_id6_bw_weight; 6191 u8 queue_id7; 6192 __le32 queue_id7_min_bw; 6193 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6194 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 6195 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 6196 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 6197 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 6198 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 6199 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6200 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 6201 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6202 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6203 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6204 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6205 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6206 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6207 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 6208 __le32 queue_id7_max_bw; 6209 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6210 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 6211 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 6212 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 6213 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 6214 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 6215 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6216 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 6217 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6218 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6219 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6220 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6221 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6222 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6223 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 6224 u8 queue_id7_tsa_assign; 6225 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 6226 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 6227 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6228 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 6229 u8 queue_id7_pri_lvl; 6230 u8 queue_id7_bw_weight; 6231 u8 unused_1[5]; 6232 }; 6233 6234 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 6235 struct hwrm_queue_cos2bw_cfg_output { 6236 __le16 error_code; 6237 __le16 req_type; 6238 __le16 seq_id; 6239 __le16 resp_len; 6240 u8 unused_0[7]; 6241 u8 valid; 6242 }; 6243 6244 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 6245 struct hwrm_queue_dscp_qcaps_input { 6246 __le16 req_type; 6247 __le16 cmpl_ring; 6248 __le16 seq_id; 6249 __le16 target_id; 6250 __le64 resp_addr; 6251 u8 port_id; 6252 u8 unused_0[7]; 6253 }; 6254 6255 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 6256 struct hwrm_queue_dscp_qcaps_output { 6257 __le16 error_code; 6258 __le16 req_type; 6259 __le16 seq_id; 6260 __le16 resp_len; 6261 u8 num_dscp_bits; 6262 u8 unused_0; 6263 __le16 max_entries; 6264 u8 unused_1[3]; 6265 u8 valid; 6266 }; 6267 6268 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 6269 struct hwrm_queue_dscp2pri_qcfg_input { 6270 __le16 req_type; 6271 __le16 cmpl_ring; 6272 __le16 seq_id; 6273 __le16 target_id; 6274 __le64 resp_addr; 6275 __le64 dest_data_addr; 6276 u8 port_id; 6277 u8 unused_0; 6278 __le16 dest_data_buffer_size; 6279 u8 unused_1[4]; 6280 }; 6281 6282 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 6283 struct hwrm_queue_dscp2pri_qcfg_output { 6284 __le16 error_code; 6285 __le16 req_type; 6286 __le16 seq_id; 6287 __le16 resp_len; 6288 __le16 entry_cnt; 6289 u8 default_pri; 6290 u8 unused_0[4]; 6291 u8 valid; 6292 }; 6293 6294 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 6295 struct hwrm_queue_dscp2pri_cfg_input { 6296 __le16 req_type; 6297 __le16 cmpl_ring; 6298 __le16 seq_id; 6299 __le16 target_id; 6300 __le64 resp_addr; 6301 __le64 src_data_addr; 6302 __le32 flags; 6303 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 6304 __le32 enables; 6305 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 6306 u8 port_id; 6307 u8 default_pri; 6308 __le16 entry_cnt; 6309 u8 unused_0[4]; 6310 }; 6311 6312 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 6313 struct hwrm_queue_dscp2pri_cfg_output { 6314 __le16 error_code; 6315 __le16 req_type; 6316 __le16 seq_id; 6317 __le16 resp_len; 6318 u8 unused_0[7]; 6319 u8 valid; 6320 }; 6321 6322 /* hwrm_vnic_alloc_input (size:192b/24B) */ 6323 struct hwrm_vnic_alloc_input { 6324 __le16 req_type; 6325 __le16 cmpl_ring; 6326 __le16 seq_id; 6327 __le16 target_id; 6328 __le64 resp_addr; 6329 __le32 flags; 6330 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 6331 #define VNIC_ALLOC_REQ_FLAGS_VIRTIO_NET_FID_VALID 0x2UL 6332 __le16 virtio_net_fid; 6333 u8 unused_0[2]; 6334 }; 6335 6336 /* hwrm_vnic_alloc_output (size:128b/16B) */ 6337 struct hwrm_vnic_alloc_output { 6338 __le16 error_code; 6339 __le16 req_type; 6340 __le16 seq_id; 6341 __le16 resp_len; 6342 __le32 vnic_id; 6343 u8 unused_0[3]; 6344 u8 valid; 6345 }; 6346 6347 /* hwrm_vnic_free_input (size:192b/24B) */ 6348 struct hwrm_vnic_free_input { 6349 __le16 req_type; 6350 __le16 cmpl_ring; 6351 __le16 seq_id; 6352 __le16 target_id; 6353 __le64 resp_addr; 6354 __le32 vnic_id; 6355 u8 unused_0[4]; 6356 }; 6357 6358 /* hwrm_vnic_free_output (size:128b/16B) */ 6359 struct hwrm_vnic_free_output { 6360 __le16 error_code; 6361 __le16 req_type; 6362 __le16 seq_id; 6363 __le16 resp_len; 6364 u8 unused_0[7]; 6365 u8 valid; 6366 }; 6367 6368 /* hwrm_vnic_cfg_input (size:384b/48B) */ 6369 struct hwrm_vnic_cfg_input { 6370 __le16 req_type; 6371 __le16 cmpl_ring; 6372 __le16 seq_id; 6373 __le16 target_id; 6374 __le64 resp_addr; 6375 __le32 flags; 6376 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 6377 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 6378 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 6379 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 6380 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 6381 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 6382 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 6383 __le32 enables; 6384 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 6385 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 6386 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 6387 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 6388 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 6389 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 6390 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 6391 #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL 6392 #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL 6393 __le16 vnic_id; 6394 __le16 dflt_ring_grp; 6395 __le16 rss_rule; 6396 __le16 cos_rule; 6397 __le16 lb_rule; 6398 __le16 mru; 6399 __le16 default_rx_ring_id; 6400 __le16 default_cmpl_ring_id; 6401 __le16 queue_id; 6402 u8 rx_csum_v2_mode; 6403 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL 6404 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK 0x1UL 6405 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 0x2UL 6406 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 6407 u8 unused0[5]; 6408 }; 6409 6410 /* hwrm_vnic_cfg_output (size:128b/16B) */ 6411 struct hwrm_vnic_cfg_output { 6412 __le16 error_code; 6413 __le16 req_type; 6414 __le16 seq_id; 6415 __le16 resp_len; 6416 u8 unused_0[7]; 6417 u8 valid; 6418 }; 6419 6420 /* hwrm_vnic_qcaps_input (size:192b/24B) */ 6421 struct hwrm_vnic_qcaps_input { 6422 __le16 req_type; 6423 __le16 cmpl_ring; 6424 __le16 seq_id; 6425 __le16 target_id; 6426 __le64 resp_addr; 6427 __le32 enables; 6428 u8 unused_0[4]; 6429 }; 6430 6431 /* hwrm_vnic_qcaps_output (size:192b/24B) */ 6432 struct hwrm_vnic_qcaps_output { 6433 __le16 error_code; 6434 __le16 req_type; 6435 __le16 seq_id; 6436 __le16 resp_len; 6437 __le16 mru; 6438 u8 unused_0[2]; 6439 __le32 flags; 6440 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 6441 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 6442 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 6443 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 6444 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 6445 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 6446 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 6447 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 6448 #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL 6449 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL 6450 #define VNIC_QCAPS_RESP_FLAGS_VNIC_STATE_CAP 0x400UL 6451 #define VNIC_QCAPS_RESP_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP 0x800UL 6452 #define VNIC_QCAPS_RESP_FLAGS_METADATA_FORMAT_CAP 0x1000UL 6453 #define VNIC_QCAPS_RESP_FLAGS_RSS_STRICT_HASH_TYPE_CAP 0x2000UL 6454 #define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP 0x4000UL 6455 #define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_FUNCTION_TOEPLITZ_CAP 0x8000UL 6456 #define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_FUNCTION_XOR_CAP 0x10000UL 6457 #define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_FUNCTION_CHKSM_CAP 0x20000UL 6458 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPV6_FLOW_LABEL_CAP 0x40000UL 6459 __le16 max_aggs_supported; 6460 u8 unused_1[5]; 6461 u8 valid; 6462 }; 6463 6464 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ 6465 struct hwrm_vnic_tpa_cfg_input { 6466 __le16 req_type; 6467 __le16 cmpl_ring; 6468 __le16 seq_id; 6469 __le16 target_id; 6470 __le64 resp_addr; 6471 __le32 flags; 6472 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 6473 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 6474 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 6475 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 6476 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 6477 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 6478 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 6479 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 6480 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL 6481 __le32 enables; 6482 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 6483 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 6484 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 6485 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 6486 __le16 vnic_id; 6487 __le16 max_agg_segs; 6488 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 6489 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 6490 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 6491 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 6492 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 6493 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 6494 __le16 max_aggs; 6495 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 6496 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 6497 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 6498 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 6499 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 6500 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 6501 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 6502 u8 unused_0[2]; 6503 __le32 max_agg_timer; 6504 __le32 min_agg_len; 6505 }; 6506 6507 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 6508 struct hwrm_vnic_tpa_cfg_output { 6509 __le16 error_code; 6510 __le16 req_type; 6511 __le16 seq_id; 6512 __le16 resp_len; 6513 u8 unused_0[7]; 6514 u8 valid; 6515 }; 6516 6517 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 6518 struct hwrm_vnic_tpa_qcfg_input { 6519 __le16 req_type; 6520 __le16 cmpl_ring; 6521 __le16 seq_id; 6522 __le16 target_id; 6523 __le64 resp_addr; 6524 __le16 vnic_id; 6525 u8 unused_0[6]; 6526 }; 6527 6528 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 6529 struct hwrm_vnic_tpa_qcfg_output { 6530 __le16 error_code; 6531 __le16 req_type; 6532 __le16 seq_id; 6533 __le16 resp_len; 6534 __le32 flags; 6535 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 6536 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 6537 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 6538 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 6539 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 6540 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 6541 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 6542 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 6543 __le16 max_agg_segs; 6544 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 6545 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 6546 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 6547 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 6548 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 6549 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 6550 __le16 max_aggs; 6551 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 6552 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 6553 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 6554 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 6555 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 6556 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 6557 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 6558 __le32 max_agg_timer; 6559 __le32 min_agg_len; 6560 u8 unused_0[7]; 6561 u8 valid; 6562 }; 6563 6564 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 6565 struct hwrm_vnic_rss_cfg_input { 6566 __le16 req_type; 6567 __le16 cmpl_ring; 6568 __le16 seq_id; 6569 __le16 target_id; 6570 __le64 resp_addr; 6571 __le32 hash_type; 6572 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 6573 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 6574 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 6575 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 6576 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 6577 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 6578 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL 0x40UL 6579 __le16 vnic_id; 6580 u8 ring_table_pair_index; 6581 u8 hash_mode_flags; 6582 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 6583 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 6584 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 6585 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 6586 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 6587 __le64 ring_grp_tbl_addr; 6588 __le64 hash_key_tbl_addr; 6589 __le16 rss_ctx_idx; 6590 u8 flags; 6591 #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_INCLUDE 0x1UL 6592 #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_EXCLUDE 0x2UL 6593 u8 rss_hash_function; 6594 #define VNIC_RSS_CFG_REQ_RSS_HASH_FUNCTION_TOEPLITZ 0x0UL 6595 #define VNIC_RSS_CFG_REQ_RSS_HASH_FUNCTION_XOR 0x1UL 6596 #define VNIC_RSS_CFG_REQ_RSS_HASH_FUNCTION_CHECKSUM 0x2UL 6597 #define VNIC_RSS_CFG_REQ_RSS_HASH_FUNCTION_LAST VNIC_RSS_CFG_REQ_RSS_HASH_FUNCTION_CHECKSUM 6598 u8 unused_1[4]; 6599 }; 6600 6601 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 6602 struct hwrm_vnic_rss_cfg_output { 6603 __le16 error_code; 6604 __le16 req_type; 6605 __le16 seq_id; 6606 __le16 resp_len; 6607 u8 unused_0[7]; 6608 u8 valid; 6609 }; 6610 6611 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ 6612 struct hwrm_vnic_rss_cfg_cmd_err { 6613 u8 code; 6614 #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 6615 #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL 6616 #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 6617 u8 unused_0[7]; 6618 }; 6619 6620 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 6621 struct hwrm_vnic_plcmodes_cfg_input { 6622 __le16 req_type; 6623 __le16 cmpl_ring; 6624 __le16 seq_id; 6625 __le16 target_id; 6626 __le64 resp_addr; 6627 __le32 flags; 6628 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 6629 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 6630 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 6631 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 6632 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 6633 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 6634 #define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT 0x40UL 6635 __le32 enables; 6636 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 6637 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 6638 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 6639 #define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID 0x8UL 6640 __le32 vnic_id; 6641 __le16 jumbo_thresh; 6642 __le16 hds_offset; 6643 __le16 hds_threshold; 6644 __le16 max_bds; 6645 u8 unused_0[4]; 6646 }; 6647 6648 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 6649 struct hwrm_vnic_plcmodes_cfg_output { 6650 __le16 error_code; 6651 __le16 req_type; 6652 __le16 seq_id; 6653 __le16 resp_len; 6654 u8 unused_0[7]; 6655 u8 valid; 6656 }; 6657 6658 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 6659 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 6660 __le16 req_type; 6661 __le16 cmpl_ring; 6662 __le16 seq_id; 6663 __le16 target_id; 6664 __le64 resp_addr; 6665 }; 6666 6667 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 6668 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 6669 __le16 error_code; 6670 __le16 req_type; 6671 __le16 seq_id; 6672 __le16 resp_len; 6673 __le16 rss_cos_lb_ctx_id; 6674 u8 unused_0[5]; 6675 u8 valid; 6676 }; 6677 6678 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 6679 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 6680 __le16 req_type; 6681 __le16 cmpl_ring; 6682 __le16 seq_id; 6683 __le16 target_id; 6684 __le64 resp_addr; 6685 __le16 rss_cos_lb_ctx_id; 6686 u8 unused_0[6]; 6687 }; 6688 6689 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 6690 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 6691 __le16 error_code; 6692 __le16 req_type; 6693 __le16 seq_id; 6694 __le16 resp_len; 6695 u8 unused_0[7]; 6696 u8 valid; 6697 }; 6698 6699 /* hwrm_ring_alloc_input (size:704b/88B) */ 6700 struct hwrm_ring_alloc_input { 6701 __le16 req_type; 6702 __le16 cmpl_ring; 6703 __le16 seq_id; 6704 __le16 target_id; 6705 __le64 resp_addr; 6706 __le32 enables; 6707 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 6708 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 6709 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 6710 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 6711 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 6712 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 6713 #define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL 6714 #define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL 6715 u8 ring_type; 6716 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 6717 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 6718 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 6719 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 6720 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 6721 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 6722 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 6723 u8 cmpl_coal_cnt; 6724 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_OFF 0x0UL 6725 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_4 0x1UL 6726 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_8 0x2UL 6727 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_12 0x3UL 6728 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_16 0x4UL 6729 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_24 0x5UL 6730 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_32 0x6UL 6731 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_48 0x7UL 6732 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_64 0x8UL 6733 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_96 0x9UL 6734 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_128 0xaUL 6735 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_192 0xbUL 6736 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_256 0xcUL 6737 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_320 0xdUL 6738 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_384 0xeUL 6739 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 0xfUL 6740 #define RING_ALLOC_REQ_CMPL_COAL_CNT_LAST RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 6741 __le16 flags; 6742 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 6743 __le64 page_tbl_addr; 6744 __le32 fbo; 6745 u8 page_size; 6746 u8 page_tbl_depth; 6747 __le16 schq_id; 6748 __le32 length; 6749 __le16 logical_id; 6750 __le16 cmpl_ring_id; 6751 __le16 queue_id; 6752 __le16 rx_buf_size; 6753 __le16 rx_ring_id; 6754 __le16 nq_ring_id; 6755 __le16 ring_arb_cfg; 6756 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 6757 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 6758 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 6759 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 6760 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 6761 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 6762 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 6763 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 6764 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 6765 __le16 unused_3; 6766 __le32 reserved3; 6767 __le32 stat_ctx_id; 6768 __le32 reserved4; 6769 __le32 max_bw; 6770 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6771 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 6772 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 6773 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 6774 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 6775 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 6776 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6777 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 6778 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6779 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6780 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6781 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6782 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6783 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6784 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 6785 u8 int_mode; 6786 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 6787 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 6788 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 6789 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 6790 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 6791 u8 mpc_chnls_type; 6792 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE 0x0UL 6793 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE 0x1UL 6794 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA 0x2UL 6795 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL 6796 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL 6797 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 6798 u8 unused_4[2]; 6799 __le64 cq_handle; 6800 }; 6801 6802 /* hwrm_ring_alloc_output (size:128b/16B) */ 6803 struct hwrm_ring_alloc_output { 6804 __le16 error_code; 6805 __le16 req_type; 6806 __le16 seq_id; 6807 __le16 resp_len; 6808 __le16 ring_id; 6809 __le16 logical_ring_id; 6810 u8 push_buffer_index; 6811 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 6812 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 6813 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_LAST RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 6814 u8 unused_0[2]; 6815 u8 valid; 6816 }; 6817 6818 /* hwrm_ring_free_input (size:256b/32B) */ 6819 struct hwrm_ring_free_input { 6820 __le16 req_type; 6821 __le16 cmpl_ring; 6822 __le16 seq_id; 6823 __le16 target_id; 6824 __le64 resp_addr; 6825 u8 ring_type; 6826 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 6827 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 6828 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 6829 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 6830 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 6831 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 6832 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 6833 u8 flags; 6834 #define RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 0x1UL 6835 #define RING_FREE_REQ_FLAGS_LAST RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 6836 __le16 ring_id; 6837 __le32 prod_idx; 6838 __le32 opaque; 6839 __le32 unused_1; 6840 }; 6841 6842 /* hwrm_ring_free_output (size:128b/16B) */ 6843 struct hwrm_ring_free_output { 6844 __le16 error_code; 6845 __le16 req_type; 6846 __le16 seq_id; 6847 __le16 resp_len; 6848 u8 unused_0[7]; 6849 u8 valid; 6850 }; 6851 6852 /* hwrm_ring_reset_input (size:192b/24B) */ 6853 struct hwrm_ring_reset_input { 6854 __le16 req_type; 6855 __le16 cmpl_ring; 6856 __le16 seq_id; 6857 __le16 target_id; 6858 __le64 resp_addr; 6859 u8 ring_type; 6860 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 6861 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 6862 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 6863 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 6864 #define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL 6865 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_RX_RING_GRP 6866 u8 unused_0; 6867 __le16 ring_id; 6868 u8 unused_1[4]; 6869 }; 6870 6871 /* hwrm_ring_reset_output (size:128b/16B) */ 6872 struct hwrm_ring_reset_output { 6873 __le16 error_code; 6874 __le16 req_type; 6875 __le16 seq_id; 6876 __le16 resp_len; 6877 u8 push_buffer_index; 6878 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 6879 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 6880 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_LAST RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 6881 u8 unused_0[3]; 6882 u8 consumer_idx[3]; 6883 u8 valid; 6884 }; 6885 6886 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 6887 struct hwrm_ring_aggint_qcaps_input { 6888 __le16 req_type; 6889 __le16 cmpl_ring; 6890 __le16 seq_id; 6891 __le16 target_id; 6892 __le64 resp_addr; 6893 }; 6894 6895 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 6896 struct hwrm_ring_aggint_qcaps_output { 6897 __le16 error_code; 6898 __le16 req_type; 6899 __le16 seq_id; 6900 __le16 resp_len; 6901 __le32 cmpl_params; 6902 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 6903 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 6904 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 6905 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 6906 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 6907 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 6908 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 6909 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 6910 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 6911 __le32 nq_params; 6912 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 6913 __le16 num_cmpl_dma_aggr_min; 6914 __le16 num_cmpl_dma_aggr_max; 6915 __le16 num_cmpl_dma_aggr_during_int_min; 6916 __le16 num_cmpl_dma_aggr_during_int_max; 6917 __le16 cmpl_aggr_dma_tmr_min; 6918 __le16 cmpl_aggr_dma_tmr_max; 6919 __le16 cmpl_aggr_dma_tmr_during_int_min; 6920 __le16 cmpl_aggr_dma_tmr_during_int_max; 6921 __le16 int_lat_tmr_min_min; 6922 __le16 int_lat_tmr_min_max; 6923 __le16 int_lat_tmr_max_min; 6924 __le16 int_lat_tmr_max_max; 6925 __le16 num_cmpl_aggr_int_min; 6926 __le16 num_cmpl_aggr_int_max; 6927 __le16 timer_units; 6928 u8 unused_0[1]; 6929 u8 valid; 6930 }; 6931 6932 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 6933 struct hwrm_ring_cmpl_ring_qaggint_params_input { 6934 __le16 req_type; 6935 __le16 cmpl_ring; 6936 __le16 seq_id; 6937 __le16 target_id; 6938 __le64 resp_addr; 6939 __le16 ring_id; 6940 __le16 flags; 6941 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL 6942 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0 6943 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 6944 u8 unused_0[4]; 6945 }; 6946 6947 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 6948 struct hwrm_ring_cmpl_ring_qaggint_params_output { 6949 __le16 error_code; 6950 __le16 req_type; 6951 __le16 seq_id; 6952 __le16 resp_len; 6953 __le16 flags; 6954 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 6955 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 6956 __le16 num_cmpl_dma_aggr; 6957 __le16 num_cmpl_dma_aggr_during_int; 6958 __le16 cmpl_aggr_dma_tmr; 6959 __le16 cmpl_aggr_dma_tmr_during_int; 6960 __le16 int_lat_tmr_min; 6961 __le16 int_lat_tmr_max; 6962 __le16 num_cmpl_aggr_int; 6963 u8 unused_0[7]; 6964 u8 valid; 6965 }; 6966 6967 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 6968 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 6969 __le16 req_type; 6970 __le16 cmpl_ring; 6971 __le16 seq_id; 6972 __le16 target_id; 6973 __le64 resp_addr; 6974 __le16 ring_id; 6975 __le16 flags; 6976 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 6977 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 6978 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 6979 __le16 num_cmpl_dma_aggr; 6980 __le16 num_cmpl_dma_aggr_during_int; 6981 __le16 cmpl_aggr_dma_tmr; 6982 __le16 cmpl_aggr_dma_tmr_during_int; 6983 __le16 int_lat_tmr_min; 6984 __le16 int_lat_tmr_max; 6985 __le16 num_cmpl_aggr_int; 6986 __le16 enables; 6987 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 6988 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 6989 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 6990 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 6991 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 6992 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 6993 u8 unused_0[4]; 6994 }; 6995 6996 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 6997 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 6998 __le16 error_code; 6999 __le16 req_type; 7000 __le16 seq_id; 7001 __le16 resp_len; 7002 u8 unused_0[7]; 7003 u8 valid; 7004 }; 7005 7006 /* hwrm_ring_grp_alloc_input (size:192b/24B) */ 7007 struct hwrm_ring_grp_alloc_input { 7008 __le16 req_type; 7009 __le16 cmpl_ring; 7010 __le16 seq_id; 7011 __le16 target_id; 7012 __le64 resp_addr; 7013 __le16 cr; 7014 __le16 rr; 7015 __le16 ar; 7016 __le16 sc; 7017 }; 7018 7019 /* hwrm_ring_grp_alloc_output (size:128b/16B) */ 7020 struct hwrm_ring_grp_alloc_output { 7021 __le16 error_code; 7022 __le16 req_type; 7023 __le16 seq_id; 7024 __le16 resp_len; 7025 __le32 ring_group_id; 7026 u8 unused_0[3]; 7027 u8 valid; 7028 }; 7029 7030 /* hwrm_ring_grp_free_input (size:192b/24B) */ 7031 struct hwrm_ring_grp_free_input { 7032 __le16 req_type; 7033 __le16 cmpl_ring; 7034 __le16 seq_id; 7035 __le16 target_id; 7036 __le64 resp_addr; 7037 __le32 ring_group_id; 7038 u8 unused_0[4]; 7039 }; 7040 7041 /* hwrm_ring_grp_free_output (size:128b/16B) */ 7042 struct hwrm_ring_grp_free_output { 7043 __le16 error_code; 7044 __le16 req_type; 7045 __le16 seq_id; 7046 __le16 resp_len; 7047 u8 unused_0[7]; 7048 u8 valid; 7049 }; 7050 7051 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL 7052 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL 7053 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL 7054 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL 7055 7056 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 7057 struct hwrm_cfa_l2_filter_alloc_input { 7058 __le16 req_type; 7059 __le16 cmpl_ring; 7060 __le16 seq_id; 7061 __le16 target_id; 7062 __le64 resp_addr; 7063 __le32 flags; 7064 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 7065 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 7066 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 7067 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 7068 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 7069 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 7070 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 7071 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 7072 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 7073 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 7074 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 7075 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 7076 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 7077 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL 7078 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL 7079 __le32 enables; 7080 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 7081 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 7082 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 7083 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 7084 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 7085 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 7086 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 7087 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 7088 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 7089 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 7090 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 7091 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 7092 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 7093 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 7094 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 7095 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 7096 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 7097 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL 7098 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL 7099 u8 l2_addr[6]; 7100 u8 num_vlans; 7101 u8 t_num_vlans; 7102 u8 l2_addr_mask[6]; 7103 __le16 l2_ovlan; 7104 __le16 l2_ovlan_mask; 7105 __le16 l2_ivlan; 7106 __le16 l2_ivlan_mask; 7107 u8 unused_1[2]; 7108 u8 t_l2_addr[6]; 7109 u8 unused_2[2]; 7110 u8 t_l2_addr_mask[6]; 7111 __le16 t_l2_ovlan; 7112 __le16 t_l2_ovlan_mask; 7113 __le16 t_l2_ivlan; 7114 __le16 t_l2_ivlan_mask; 7115 u8 src_type; 7116 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 7117 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 7118 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 7119 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 7120 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 7121 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 7122 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 7123 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 7124 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 7125 u8 unused_3; 7126 __le32 src_id; 7127 u8 tunnel_type; 7128 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7129 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7130 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7131 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7132 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7133 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7134 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7135 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7136 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7137 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7138 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7139 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7140 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7141 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7142 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7143 u8 unused_4; 7144 __le16 dst_id; 7145 __le16 mirror_vnic_id; 7146 u8 pri_hint; 7147 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 7148 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 7149 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 7150 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 7151 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 7152 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 7153 u8 unused_5; 7154 __le32 unused_6; 7155 __le64 l2_filter_id_hint; 7156 }; 7157 7158 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 7159 struct hwrm_cfa_l2_filter_alloc_output { 7160 __le16 error_code; 7161 __le16 req_type; 7162 __le16 seq_id; 7163 __le16 resp_len; 7164 __le64 l2_filter_id; 7165 __le32 flow_id; 7166 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7167 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7168 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7169 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7170 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7171 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 7172 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7173 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7174 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7175 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7176 u8 unused_0[3]; 7177 u8 valid; 7178 }; 7179 7180 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 7181 struct hwrm_cfa_l2_filter_free_input { 7182 __le16 req_type; 7183 __le16 cmpl_ring; 7184 __le16 seq_id; 7185 __le16 target_id; 7186 __le64 resp_addr; 7187 __le64 l2_filter_id; 7188 }; 7189 7190 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 7191 struct hwrm_cfa_l2_filter_free_output { 7192 __le16 error_code; 7193 __le16 req_type; 7194 __le16 seq_id; 7195 __le16 resp_len; 7196 u8 unused_0[7]; 7197 u8 valid; 7198 }; 7199 7200 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ 7201 struct hwrm_cfa_l2_filter_cfg_input { 7202 __le16 req_type; 7203 __le16 cmpl_ring; 7204 __le16 seq_id; 7205 __le16 target_id; 7206 __le64 resp_addr; 7207 __le32 flags; 7208 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 7209 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 7210 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 7211 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 7212 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 7213 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 7214 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 7215 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 7216 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 7217 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 7218 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 7219 __le32 enables; 7220 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 7221 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 7222 __le64 l2_filter_id; 7223 __le32 dst_id; 7224 __le32 new_mirror_vnic_id; 7225 }; 7226 7227 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 7228 struct hwrm_cfa_l2_filter_cfg_output { 7229 __le16 error_code; 7230 __le16 req_type; 7231 __le16 seq_id; 7232 __le16 resp_len; 7233 u8 unused_0[7]; 7234 u8 valid; 7235 }; 7236 7237 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 7238 struct hwrm_cfa_l2_set_rx_mask_input { 7239 __le16 req_type; 7240 __le16 cmpl_ring; 7241 __le16 seq_id; 7242 __le16 target_id; 7243 __le64 resp_addr; 7244 __le32 vnic_id; 7245 __le32 mask; 7246 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 7247 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 7248 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 7249 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 7250 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 7251 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 7252 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 7253 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 7254 __le64 mc_tbl_addr; 7255 __le32 num_mc_entries; 7256 u8 unused_0[4]; 7257 __le64 vlan_tag_tbl_addr; 7258 __le32 num_vlan_tags; 7259 u8 unused_1[4]; 7260 }; 7261 7262 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 7263 struct hwrm_cfa_l2_set_rx_mask_output { 7264 __le16 error_code; 7265 __le16 req_type; 7266 __le16 seq_id; 7267 __le16 resp_len; 7268 u8 unused_0[7]; 7269 u8 valid; 7270 }; 7271 7272 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 7273 struct hwrm_cfa_l2_set_rx_mask_cmd_err { 7274 u8 code; 7275 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 7276 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 7277 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 7278 u8 unused_0[7]; 7279 }; 7280 7281 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 7282 struct hwrm_cfa_tunnel_filter_alloc_input { 7283 __le16 req_type; 7284 __le16 cmpl_ring; 7285 __le16 seq_id; 7286 __le16 target_id; 7287 __le64 resp_addr; 7288 __le32 flags; 7289 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7290 __le32 enables; 7291 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 7292 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 7293 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 7294 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 7295 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 7296 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 7297 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 7298 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 7299 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 7300 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 7301 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 7302 __le64 l2_filter_id; 7303 u8 l2_addr[6]; 7304 __le16 l2_ivlan; 7305 __le32 l3_addr[4]; 7306 __le32 t_l3_addr[4]; 7307 u8 l3_addr_type; 7308 u8 t_l3_addr_type; 7309 u8 tunnel_type; 7310 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7311 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7312 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7313 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7314 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7315 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7316 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7317 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7318 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7319 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7320 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7321 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7322 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7323 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7324 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7325 u8 tunnel_flags; 7326 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 7327 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 7328 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 7329 __le32 vni; 7330 __le32 dst_vnic_id; 7331 __le32 mirror_vnic_id; 7332 }; 7333 7334 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 7335 struct hwrm_cfa_tunnel_filter_alloc_output { 7336 __le16 error_code; 7337 __le16 req_type; 7338 __le16 seq_id; 7339 __le16 resp_len; 7340 __le64 tunnel_filter_id; 7341 __le32 flow_id; 7342 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7343 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7344 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7345 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7346 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7347 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 7348 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7349 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7350 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7351 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7352 u8 unused_0[3]; 7353 u8 valid; 7354 }; 7355 7356 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 7357 struct hwrm_cfa_tunnel_filter_free_input { 7358 __le16 req_type; 7359 __le16 cmpl_ring; 7360 __le16 seq_id; 7361 __le16 target_id; 7362 __le64 resp_addr; 7363 __le64 tunnel_filter_id; 7364 }; 7365 7366 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 7367 struct hwrm_cfa_tunnel_filter_free_output { 7368 __le16 error_code; 7369 __le16 req_type; 7370 __le16 seq_id; 7371 __le16 resp_len; 7372 u8 unused_0[7]; 7373 u8 valid; 7374 }; 7375 7376 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 7377 struct hwrm_vxlan_ipv4_hdr { 7378 u8 ver_hlen; 7379 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 7380 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 7381 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 7382 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 7383 u8 tos; 7384 __be16 ip_id; 7385 __be16 flags_frag_offset; 7386 u8 ttl; 7387 u8 protocol; 7388 __be32 src_ip_addr; 7389 __be32 dest_ip_addr; 7390 }; 7391 7392 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 7393 struct hwrm_vxlan_ipv6_hdr { 7394 __be32 ver_tc_flow_label; 7395 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 7396 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 7397 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 7398 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 7399 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 7400 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 7401 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 7402 __be16 payload_len; 7403 u8 next_hdr; 7404 u8 ttl; 7405 __be32 src_ip_addr[4]; 7406 __be32 dest_ip_addr[4]; 7407 }; 7408 7409 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 7410 struct hwrm_cfa_encap_data_vxlan { 7411 u8 src_mac_addr[6]; 7412 __le16 unused_0; 7413 u8 dst_mac_addr[6]; 7414 u8 num_vlan_tags; 7415 u8 unused_1; 7416 __be16 ovlan_tpid; 7417 __be16 ovlan_tci; 7418 __be16 ivlan_tpid; 7419 __be16 ivlan_tci; 7420 __le32 l3[10]; 7421 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 7422 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 7423 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 7424 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 7425 __be16 src_port; 7426 __be16 dst_port; 7427 __be32 vni; 7428 u8 hdr_rsvd0[3]; 7429 u8 hdr_rsvd1; 7430 u8 hdr_flags; 7431 u8 unused[3]; 7432 }; 7433 7434 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 7435 struct hwrm_cfa_encap_record_alloc_input { 7436 __le16 req_type; 7437 __le16 cmpl_ring; 7438 __le16 seq_id; 7439 __le16 target_id; 7440 __le64 resp_addr; 7441 __le32 flags; 7442 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7443 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL 7444 u8 encap_type; 7445 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 7446 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 7447 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 7448 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 7449 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 7450 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 7451 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 7452 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 7453 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 7454 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 7455 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 7456 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL 7457 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 7458 u8 unused_0[3]; 7459 __le32 encap_data[20]; 7460 }; 7461 7462 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 7463 struct hwrm_cfa_encap_record_alloc_output { 7464 __le16 error_code; 7465 __le16 req_type; 7466 __le16 seq_id; 7467 __le16 resp_len; 7468 __le32 encap_record_id; 7469 u8 unused_0[3]; 7470 u8 valid; 7471 }; 7472 7473 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 7474 struct hwrm_cfa_encap_record_free_input { 7475 __le16 req_type; 7476 __le16 cmpl_ring; 7477 __le16 seq_id; 7478 __le16 target_id; 7479 __le64 resp_addr; 7480 __le32 encap_record_id; 7481 u8 unused_0[4]; 7482 }; 7483 7484 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 7485 struct hwrm_cfa_encap_record_free_output { 7486 __le16 error_code; 7487 __le16 req_type; 7488 __le16 seq_id; 7489 __le16 resp_len; 7490 u8 unused_0[7]; 7491 u8 valid; 7492 }; 7493 7494 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 7495 struct hwrm_cfa_ntuple_filter_alloc_input { 7496 __le16 req_type; 7497 __le16 cmpl_ring; 7498 __le16 seq_id; 7499 __le16 target_id; 7500 __le64 resp_addr; 7501 __le32 flags; 7502 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7503 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 7504 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 7505 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL 7506 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL 7507 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL 7508 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_NO_L2_CONTEXT 0x40UL 7509 __le32 enables; 7510 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 7511 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 7512 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 7513 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 7514 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 7515 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 7516 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 7517 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 7518 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 7519 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 7520 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 7521 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 7522 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 7523 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 7524 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 7525 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 7526 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 7527 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 7528 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 7529 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL 7530 __le64 l2_filter_id; 7531 u8 src_macaddr[6]; 7532 __be16 ethertype; 7533 u8 ip_addr_type; 7534 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 7535 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 7536 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 7537 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 7538 u8 ip_protocol; 7539 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 7540 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 7541 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 7542 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 7543 __le16 dst_id; 7544 __le16 mirror_vnic_id; 7545 u8 tunnel_type; 7546 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7547 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7548 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7549 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7550 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7551 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7552 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7553 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7554 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7555 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7556 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7557 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7558 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7559 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7560 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7561 u8 pri_hint; 7562 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 7563 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 7564 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 7565 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 7566 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 7567 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 7568 __be32 src_ipaddr[4]; 7569 __be32 src_ipaddr_mask[4]; 7570 __be32 dst_ipaddr[4]; 7571 __be32 dst_ipaddr_mask[4]; 7572 __be16 src_port; 7573 __be16 src_port_mask; 7574 __be16 dst_port; 7575 __be16 dst_port_mask; 7576 __le64 ntuple_filter_id_hint; 7577 }; 7578 7579 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 7580 struct hwrm_cfa_ntuple_filter_alloc_output { 7581 __le16 error_code; 7582 __le16 req_type; 7583 __le16 seq_id; 7584 __le16 resp_len; 7585 __le64 ntuple_filter_id; 7586 __le32 flow_id; 7587 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7588 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7589 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7590 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7591 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7592 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 7593 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7594 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7595 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7596 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7597 u8 unused_0[3]; 7598 u8 valid; 7599 }; 7600 7601 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 7602 struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 7603 u8 code; 7604 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 7605 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 7606 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 7607 u8 unused_0[7]; 7608 }; 7609 7610 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 7611 struct hwrm_cfa_ntuple_filter_free_input { 7612 __le16 req_type; 7613 __le16 cmpl_ring; 7614 __le16 seq_id; 7615 __le16 target_id; 7616 __le64 resp_addr; 7617 __le64 ntuple_filter_id; 7618 }; 7619 7620 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 7621 struct hwrm_cfa_ntuple_filter_free_output { 7622 __le16 error_code; 7623 __le16 req_type; 7624 __le16 seq_id; 7625 __le16 resp_len; 7626 u8 unused_0[7]; 7627 u8 valid; 7628 }; 7629 7630 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 7631 struct hwrm_cfa_ntuple_filter_cfg_input { 7632 __le16 req_type; 7633 __le16 cmpl_ring; 7634 __le16 seq_id; 7635 __le16 target_id; 7636 __le64 resp_addr; 7637 __le32 enables; 7638 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 7639 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 7640 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 7641 __le32 flags; 7642 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL 7643 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL 7644 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_NO_L2_CONTEXT 0x4UL 7645 __le64 ntuple_filter_id; 7646 __le32 new_dst_id; 7647 __le32 new_mirror_vnic_id; 7648 __le16 new_meter_instance_id; 7649 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 7650 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 7651 u8 unused_1[6]; 7652 }; 7653 7654 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 7655 struct hwrm_cfa_ntuple_filter_cfg_output { 7656 __le16 error_code; 7657 __le16 req_type; 7658 __le16 seq_id; 7659 __le16 resp_len; 7660 u8 unused_0[7]; 7661 u8 valid; 7662 }; 7663 7664 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 7665 struct hwrm_cfa_decap_filter_alloc_input { 7666 __le16 req_type; 7667 __le16 cmpl_ring; 7668 __le16 seq_id; 7669 __le16 target_id; 7670 __le64 resp_addr; 7671 __le32 flags; 7672 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 7673 __le32 enables; 7674 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 7675 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 7676 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 7677 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 7678 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 7679 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 7680 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 7681 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 7682 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 7683 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 7684 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 7685 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 7686 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 7687 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 7688 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 7689 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 7690 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 7691 __be32 tunnel_id; 7692 u8 tunnel_type; 7693 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7694 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7695 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7696 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7697 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7698 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7699 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7700 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7701 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7702 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7703 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7704 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7705 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7706 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7707 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7708 u8 unused_0; 7709 __le16 unused_1; 7710 u8 src_macaddr[6]; 7711 u8 unused_2[2]; 7712 u8 dst_macaddr[6]; 7713 __be16 ovlan_vid; 7714 __be16 ivlan_vid; 7715 __be16 t_ovlan_vid; 7716 __be16 t_ivlan_vid; 7717 __be16 ethertype; 7718 u8 ip_addr_type; 7719 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 7720 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 7721 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 7722 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 7723 u8 ip_protocol; 7724 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 7725 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 7726 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 7727 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 7728 __le16 unused_3; 7729 __le32 unused_4; 7730 __be32 src_ipaddr[4]; 7731 __be32 dst_ipaddr[4]; 7732 __be16 src_port; 7733 __be16 dst_port; 7734 __le16 dst_id; 7735 __le16 l2_ctxt_ref_id; 7736 }; 7737 7738 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 7739 struct hwrm_cfa_decap_filter_alloc_output { 7740 __le16 error_code; 7741 __le16 req_type; 7742 __le16 seq_id; 7743 __le16 resp_len; 7744 __le32 decap_filter_id; 7745 u8 unused_0[3]; 7746 u8 valid; 7747 }; 7748 7749 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 7750 struct hwrm_cfa_decap_filter_free_input { 7751 __le16 req_type; 7752 __le16 cmpl_ring; 7753 __le16 seq_id; 7754 __le16 target_id; 7755 __le64 resp_addr; 7756 __le32 decap_filter_id; 7757 u8 unused_0[4]; 7758 }; 7759 7760 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 7761 struct hwrm_cfa_decap_filter_free_output { 7762 __le16 error_code; 7763 __le16 req_type; 7764 __le16 seq_id; 7765 __le16 resp_len; 7766 u8 unused_0[7]; 7767 u8 valid; 7768 }; 7769 7770 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 7771 struct hwrm_cfa_flow_alloc_input { 7772 __le16 req_type; 7773 __le16 cmpl_ring; 7774 __le16 seq_id; 7775 __le16 target_id; 7776 __le64 resp_addr; 7777 __le16 flags; 7778 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 7779 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 7780 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 7781 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 7782 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 7783 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 7784 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 7785 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 7786 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 7787 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 7788 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 7789 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 7790 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 7791 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 7792 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 7793 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 7794 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL 7795 __le16 src_fid; 7796 __le32 tunnel_handle; 7797 __le16 action_flags; 7798 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 7799 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 7800 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 7801 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 7802 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 7803 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 7804 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 7805 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 7806 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 7807 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 7808 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 7809 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL 7810 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL 7811 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL 7812 __le16 dst_fid; 7813 __be16 l2_rewrite_vlan_tpid; 7814 __be16 l2_rewrite_vlan_tci; 7815 __le16 act_meter_id; 7816 __le16 ref_flow_handle; 7817 __be16 ethertype; 7818 __be16 outer_vlan_tci; 7819 __be16 dmac[3]; 7820 __be16 inner_vlan_tci; 7821 __be16 smac[3]; 7822 u8 ip_dst_mask_len; 7823 u8 ip_src_mask_len; 7824 __be32 ip_dst[4]; 7825 __be32 ip_src[4]; 7826 __be16 l4_src_port; 7827 __be16 l4_src_port_mask; 7828 __be16 l4_dst_port; 7829 __be16 l4_dst_port_mask; 7830 __be32 nat_ip_address[4]; 7831 __be16 l2_rewrite_dmac[3]; 7832 __be16 nat_port; 7833 __be16 l2_rewrite_smac[3]; 7834 u8 ip_proto; 7835 u8 tunnel_type; 7836 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7837 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7838 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7839 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7840 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7841 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7842 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7843 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7844 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7845 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7846 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7847 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7848 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7849 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7850 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7851 }; 7852 7853 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 7854 struct hwrm_cfa_flow_alloc_output { 7855 __le16 error_code; 7856 __le16 req_type; 7857 __le16 seq_id; 7858 __le16 resp_len; 7859 __le16 flow_handle; 7860 u8 unused_0[2]; 7861 __le32 flow_id; 7862 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7863 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7864 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7865 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7866 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7867 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT 7868 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7869 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7870 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7871 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX 7872 __le64 ext_flow_handle; 7873 __le32 flow_counter_id; 7874 u8 unused_1[3]; 7875 u8 valid; 7876 }; 7877 7878 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ 7879 struct hwrm_cfa_flow_alloc_cmd_err { 7880 u8 code; 7881 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 7882 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL 7883 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL 7884 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL 7885 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL 7886 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL 7887 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL 7888 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL 7889 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 7890 u8 unused_0[7]; 7891 }; 7892 7893 /* hwrm_cfa_flow_free_input (size:256b/32B) */ 7894 struct hwrm_cfa_flow_free_input { 7895 __le16 req_type; 7896 __le16 cmpl_ring; 7897 __le16 seq_id; 7898 __le16 target_id; 7899 __le64 resp_addr; 7900 __le16 flow_handle; 7901 __le16 unused_0; 7902 __le32 flow_counter_id; 7903 __le64 ext_flow_handle; 7904 }; 7905 7906 /* hwrm_cfa_flow_free_output (size:256b/32B) */ 7907 struct hwrm_cfa_flow_free_output { 7908 __le16 error_code; 7909 __le16 req_type; 7910 __le16 seq_id; 7911 __le16 resp_len; 7912 __le64 packet; 7913 __le64 byte; 7914 u8 unused_0[7]; 7915 u8 valid; 7916 }; 7917 7918 /* hwrm_cfa_flow_info_input (size:256b/32B) */ 7919 struct hwrm_cfa_flow_info_input { 7920 __le16 req_type; 7921 __le16 cmpl_ring; 7922 __le16 seq_id; 7923 __le16 target_id; 7924 __le64 resp_addr; 7925 __le16 flow_handle; 7926 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL 7927 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT 0 7928 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL 7929 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL 7930 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL 7931 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL 7932 u8 unused_0[6]; 7933 __le64 ext_flow_handle; 7934 }; 7935 7936 /* hwrm_cfa_flow_info_output (size:5632b/704B) */ 7937 struct hwrm_cfa_flow_info_output { 7938 __le16 error_code; 7939 __le16 req_type; 7940 __le16 seq_id; 7941 __le16 resp_len; 7942 u8 flags; 7943 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL 7944 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL 7945 u8 profile; 7946 __le16 src_fid; 7947 __le16 dst_fid; 7948 __le16 l2_ctxt_id; 7949 __le64 em_info; 7950 __le64 tcam_info; 7951 __le64 vfp_tcam_info; 7952 __le16 ar_id; 7953 __le16 flow_handle; 7954 __le32 tunnel_handle; 7955 __le16 flow_timer; 7956 u8 unused_0[6]; 7957 __le32 flow_key_data[130]; 7958 __le32 flow_action_info[30]; 7959 u8 unused_1[7]; 7960 u8 valid; 7961 }; 7962 7963 /* hwrm_cfa_flow_stats_input (size:640b/80B) */ 7964 struct hwrm_cfa_flow_stats_input { 7965 __le16 req_type; 7966 __le16 cmpl_ring; 7967 __le16 seq_id; 7968 __le16 target_id; 7969 __le64 resp_addr; 7970 __le16 num_flows; 7971 __le16 flow_handle_0; 7972 __le16 flow_handle_1; 7973 __le16 flow_handle_2; 7974 __le16 flow_handle_3; 7975 __le16 flow_handle_4; 7976 __le16 flow_handle_5; 7977 __le16 flow_handle_6; 7978 __le16 flow_handle_7; 7979 __le16 flow_handle_8; 7980 __le16 flow_handle_9; 7981 u8 unused_0[2]; 7982 __le32 flow_id_0; 7983 __le32 flow_id_1; 7984 __le32 flow_id_2; 7985 __le32 flow_id_3; 7986 __le32 flow_id_4; 7987 __le32 flow_id_5; 7988 __le32 flow_id_6; 7989 __le32 flow_id_7; 7990 __le32 flow_id_8; 7991 __le32 flow_id_9; 7992 }; 7993 7994 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 7995 struct hwrm_cfa_flow_stats_output { 7996 __le16 error_code; 7997 __le16 req_type; 7998 __le16 seq_id; 7999 __le16 resp_len; 8000 __le64 packet_0; 8001 __le64 packet_1; 8002 __le64 packet_2; 8003 __le64 packet_3; 8004 __le64 packet_4; 8005 __le64 packet_5; 8006 __le64 packet_6; 8007 __le64 packet_7; 8008 __le64 packet_8; 8009 __le64 packet_9; 8010 __le64 byte_0; 8011 __le64 byte_1; 8012 __le64 byte_2; 8013 __le64 byte_3; 8014 __le64 byte_4; 8015 __le64 byte_5; 8016 __le64 byte_6; 8017 __le64 byte_7; 8018 __le64 byte_8; 8019 __le64 byte_9; 8020 u8 unused_0[7]; 8021 u8 valid; 8022 }; 8023 8024 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 8025 struct hwrm_cfa_vfr_alloc_input { 8026 __le16 req_type; 8027 __le16 cmpl_ring; 8028 __le16 seq_id; 8029 __le16 target_id; 8030 __le64 resp_addr; 8031 __le16 vf_id; 8032 __le16 reserved; 8033 u8 unused_0[4]; 8034 char vfr_name[32]; 8035 }; 8036 8037 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 8038 struct hwrm_cfa_vfr_alloc_output { 8039 __le16 error_code; 8040 __le16 req_type; 8041 __le16 seq_id; 8042 __le16 resp_len; 8043 __le16 rx_cfa_code; 8044 __le16 tx_cfa_action; 8045 u8 unused_0[3]; 8046 u8 valid; 8047 }; 8048 8049 /* hwrm_cfa_vfr_free_input (size:448b/56B) */ 8050 struct hwrm_cfa_vfr_free_input { 8051 __le16 req_type; 8052 __le16 cmpl_ring; 8053 __le16 seq_id; 8054 __le16 target_id; 8055 __le64 resp_addr; 8056 char vfr_name[32]; 8057 __le16 vf_id; 8058 __le16 reserved; 8059 u8 unused_0[4]; 8060 }; 8061 8062 /* hwrm_cfa_vfr_free_output (size:128b/16B) */ 8063 struct hwrm_cfa_vfr_free_output { 8064 __le16 error_code; 8065 __le16 req_type; 8066 __le16 seq_id; 8067 __le16 resp_len; 8068 u8 unused_0[7]; 8069 u8 valid; 8070 }; 8071 8072 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ 8073 struct hwrm_cfa_eem_qcaps_input { 8074 __le16 req_type; 8075 __le16 cmpl_ring; 8076 __le16 seq_id; 8077 __le16 target_id; 8078 __le64 resp_addr; 8079 __le32 flags; 8080 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL 8081 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL 8082 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 8083 __le32 unused_0; 8084 }; 8085 8086 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ 8087 struct hwrm_cfa_eem_qcaps_output { 8088 __le16 error_code; 8089 __le16 req_type; 8090 __le16 seq_id; 8091 __le16 resp_len; 8092 __le32 flags; 8093 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL 8094 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL 8095 #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL 8096 #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL 8097 __le32 unused_0; 8098 __le32 supported; 8099 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL 8100 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL 8101 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL 8102 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL 8103 #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL 8104 __le32 max_entries_supported; 8105 __le16 key_entry_size; 8106 __le16 record_entry_size; 8107 __le16 efc_entry_size; 8108 __le16 fid_entry_size; 8109 u8 unused_1[7]; 8110 u8 valid; 8111 }; 8112 8113 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */ 8114 struct hwrm_cfa_eem_cfg_input { 8115 __le16 req_type; 8116 __le16 cmpl_ring; 8117 __le16 seq_id; 8118 __le16 target_id; 8119 __le64 resp_addr; 8120 __le32 flags; 8121 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL 8122 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL 8123 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 8124 #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL 8125 __le16 group_id; 8126 __le16 unused_0; 8127 __le32 num_entries; 8128 __le32 unused_1; 8129 __le16 key0_ctx_id; 8130 __le16 key1_ctx_id; 8131 __le16 record_ctx_id; 8132 __le16 efc_ctx_id; 8133 __le16 fid_ctx_id; 8134 __le16 unused_2; 8135 __le32 unused_3; 8136 }; 8137 8138 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */ 8139 struct hwrm_cfa_eem_cfg_output { 8140 __le16 error_code; 8141 __le16 req_type; 8142 __le16 seq_id; 8143 __le16 resp_len; 8144 u8 unused_0[7]; 8145 u8 valid; 8146 }; 8147 8148 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ 8149 struct hwrm_cfa_eem_qcfg_input { 8150 __le16 req_type; 8151 __le16 cmpl_ring; 8152 __le16 seq_id; 8153 __le16 target_id; 8154 __le64 resp_addr; 8155 __le32 flags; 8156 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL 8157 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL 8158 __le32 unused_0; 8159 }; 8160 8161 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ 8162 struct hwrm_cfa_eem_qcfg_output { 8163 __le16 error_code; 8164 __le16 req_type; 8165 __le16 seq_id; 8166 __le16 resp_len; 8167 __le32 flags; 8168 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL 8169 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL 8170 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL 8171 __le32 num_entries; 8172 __le16 key0_ctx_id; 8173 __le16 key1_ctx_id; 8174 __le16 record_ctx_id; 8175 __le16 efc_ctx_id; 8176 __le16 fid_ctx_id; 8177 u8 unused_2[5]; 8178 u8 valid; 8179 }; 8180 8181 /* hwrm_cfa_eem_op_input (size:192b/24B) */ 8182 struct hwrm_cfa_eem_op_input { 8183 __le16 req_type; 8184 __le16 cmpl_ring; 8185 __le16 seq_id; 8186 __le16 target_id; 8187 __le64 resp_addr; 8188 __le32 flags; 8189 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL 8190 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL 8191 __le16 unused_0; 8192 __le16 op; 8193 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL 8194 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL 8195 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL 8196 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL 8197 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP 8198 }; 8199 8200 /* hwrm_cfa_eem_op_output (size:128b/16B) */ 8201 struct hwrm_cfa_eem_op_output { 8202 __le16 error_code; 8203 __le16 req_type; 8204 __le16 seq_id; 8205 __le16 resp_len; 8206 u8 unused_0[7]; 8207 u8 valid; 8208 }; 8209 8210 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ 8211 struct hwrm_cfa_adv_flow_mgnt_qcaps_input { 8212 __le16 req_type; 8213 __le16 cmpl_ring; 8214 __le16 seq_id; 8215 __le16 target_id; 8216 __le64 resp_addr; 8217 __le32 unused_0[4]; 8218 }; 8219 8220 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ 8221 struct hwrm_cfa_adv_flow_mgnt_qcaps_output { 8222 __le16 error_code; 8223 __le16 req_type; 8224 __le16 seq_id; 8225 __le16 resp_len; 8226 __le32 flags; 8227 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL 8228 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL 8229 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL 8230 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL 8231 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL 8232 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL 8233 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL 8234 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL 8235 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL 8236 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL 8237 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL 8238 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL 8239 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL 8240 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL 8241 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL 8242 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TRUFLOW_CAPABLE 0x8000UL 8243 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED 0x10000UL 8244 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_LAG_SUPPORTED 0x20000UL 8245 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED 0x40000UL 8246 u8 unused_0[3]; 8247 u8 valid; 8248 }; 8249 8250 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 8251 struct hwrm_tunnel_dst_port_query_input { 8252 __le16 req_type; 8253 __le16 cmpl_ring; 8254 __le16 seq_id; 8255 __le16 target_id; 8256 __le64 resp_addr; 8257 u8 tunnel_type; 8258 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8259 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8260 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8261 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8262 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8263 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8264 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 8265 u8 unused_0[7]; 8266 }; 8267 8268 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 8269 struct hwrm_tunnel_dst_port_query_output { 8270 __le16 error_code; 8271 __le16 req_type; 8272 __le16 seq_id; 8273 __le16 resp_len; 8274 __le16 tunnel_dst_port_id; 8275 __be16 tunnel_dst_port_val; 8276 u8 unused_0[3]; 8277 u8 valid; 8278 }; 8279 8280 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 8281 struct hwrm_tunnel_dst_port_alloc_input { 8282 __le16 req_type; 8283 __le16 cmpl_ring; 8284 __le16 seq_id; 8285 __le16 target_id; 8286 __le64 resp_addr; 8287 u8 tunnel_type; 8288 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8289 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8290 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8291 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8292 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8293 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8294 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 8295 u8 unused_0; 8296 __be16 tunnel_dst_port_val; 8297 u8 unused_1[4]; 8298 }; 8299 8300 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 8301 struct hwrm_tunnel_dst_port_alloc_output { 8302 __le16 error_code; 8303 __le16 req_type; 8304 __le16 seq_id; 8305 __le16 resp_len; 8306 __le16 tunnel_dst_port_id; 8307 u8 unused_0[5]; 8308 u8 valid; 8309 }; 8310 8311 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 8312 struct hwrm_tunnel_dst_port_free_input { 8313 __le16 req_type; 8314 __le16 cmpl_ring; 8315 __le16 seq_id; 8316 __le16 target_id; 8317 __le64 resp_addr; 8318 u8 tunnel_type; 8319 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8320 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8321 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8322 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8323 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8324 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8325 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 8326 u8 unused_0; 8327 __le16 tunnel_dst_port_id; 8328 u8 unused_1[4]; 8329 }; 8330 8331 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 8332 struct hwrm_tunnel_dst_port_free_output { 8333 __le16 error_code; 8334 __le16 req_type; 8335 __le16 seq_id; 8336 __le16 resp_len; 8337 u8 unused_1[7]; 8338 u8 valid; 8339 }; 8340 8341 /* ctx_hw_stats (size:1280b/160B) */ 8342 struct ctx_hw_stats { 8343 __le64 rx_ucast_pkts; 8344 __le64 rx_mcast_pkts; 8345 __le64 rx_bcast_pkts; 8346 __le64 rx_discard_pkts; 8347 __le64 rx_error_pkts; 8348 __le64 rx_ucast_bytes; 8349 __le64 rx_mcast_bytes; 8350 __le64 rx_bcast_bytes; 8351 __le64 tx_ucast_pkts; 8352 __le64 tx_mcast_pkts; 8353 __le64 tx_bcast_pkts; 8354 __le64 tx_error_pkts; 8355 __le64 tx_discard_pkts; 8356 __le64 tx_ucast_bytes; 8357 __le64 tx_mcast_bytes; 8358 __le64 tx_bcast_bytes; 8359 __le64 tpa_pkts; 8360 __le64 tpa_bytes; 8361 __le64 tpa_events; 8362 __le64 tpa_aborts; 8363 }; 8364 8365 /* ctx_hw_stats_ext (size:1408b/176B) */ 8366 struct ctx_hw_stats_ext { 8367 __le64 rx_ucast_pkts; 8368 __le64 rx_mcast_pkts; 8369 __le64 rx_bcast_pkts; 8370 __le64 rx_discard_pkts; 8371 __le64 rx_error_pkts; 8372 __le64 rx_ucast_bytes; 8373 __le64 rx_mcast_bytes; 8374 __le64 rx_bcast_bytes; 8375 __le64 tx_ucast_pkts; 8376 __le64 tx_mcast_pkts; 8377 __le64 tx_bcast_pkts; 8378 __le64 tx_error_pkts; 8379 __le64 tx_discard_pkts; 8380 __le64 tx_ucast_bytes; 8381 __le64 tx_mcast_bytes; 8382 __le64 tx_bcast_bytes; 8383 __le64 rx_tpa_eligible_pkt; 8384 __le64 rx_tpa_eligible_bytes; 8385 __le64 rx_tpa_pkt; 8386 __le64 rx_tpa_bytes; 8387 __le64 rx_tpa_errors; 8388 __le64 rx_tpa_events; 8389 }; 8390 8391 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */ 8392 struct hwrm_stat_ctx_alloc_input { 8393 __le16 req_type; 8394 __le16 cmpl_ring; 8395 __le16 seq_id; 8396 __le16 target_id; 8397 __le64 resp_addr; 8398 __le64 stats_dma_addr; 8399 __le32 update_period_ms; 8400 u8 stat_ctx_flags; 8401 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 8402 u8 unused_0; 8403 __le16 stats_dma_length; 8404 }; 8405 8406 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 8407 struct hwrm_stat_ctx_alloc_output { 8408 __le16 error_code; 8409 __le16 req_type; 8410 __le16 seq_id; 8411 __le16 resp_len; 8412 __le32 stat_ctx_id; 8413 u8 unused_0[3]; 8414 u8 valid; 8415 }; 8416 8417 /* hwrm_stat_ctx_free_input (size:192b/24B) */ 8418 struct hwrm_stat_ctx_free_input { 8419 __le16 req_type; 8420 __le16 cmpl_ring; 8421 __le16 seq_id; 8422 __le16 target_id; 8423 __le64 resp_addr; 8424 __le32 stat_ctx_id; 8425 u8 unused_0[4]; 8426 }; 8427 8428 /* hwrm_stat_ctx_free_output (size:128b/16B) */ 8429 struct hwrm_stat_ctx_free_output { 8430 __le16 error_code; 8431 __le16 req_type; 8432 __le16 seq_id; 8433 __le16 resp_len; 8434 __le32 stat_ctx_id; 8435 u8 unused_0[3]; 8436 u8 valid; 8437 }; 8438 8439 /* hwrm_stat_ctx_query_input (size:192b/24B) */ 8440 struct hwrm_stat_ctx_query_input { 8441 __le16 req_type; 8442 __le16 cmpl_ring; 8443 __le16 seq_id; 8444 __le16 target_id; 8445 __le64 resp_addr; 8446 __le32 stat_ctx_id; 8447 u8 flags; 8448 #define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 8449 u8 unused_0[3]; 8450 }; 8451 8452 /* hwrm_stat_ctx_query_output (size:1408b/176B) */ 8453 struct hwrm_stat_ctx_query_output { 8454 __le16 error_code; 8455 __le16 req_type; 8456 __le16 seq_id; 8457 __le16 resp_len; 8458 __le64 tx_ucast_pkts; 8459 __le64 tx_mcast_pkts; 8460 __le64 tx_bcast_pkts; 8461 __le64 tx_discard_pkts; 8462 __le64 tx_error_pkts; 8463 __le64 tx_ucast_bytes; 8464 __le64 tx_mcast_bytes; 8465 __le64 tx_bcast_bytes; 8466 __le64 rx_ucast_pkts; 8467 __le64 rx_mcast_pkts; 8468 __le64 rx_bcast_pkts; 8469 __le64 rx_discard_pkts; 8470 __le64 rx_error_pkts; 8471 __le64 rx_ucast_bytes; 8472 __le64 rx_mcast_bytes; 8473 __le64 rx_bcast_bytes; 8474 __le64 rx_agg_pkts; 8475 __le64 rx_agg_bytes; 8476 __le64 rx_agg_events; 8477 __le64 rx_agg_aborts; 8478 u8 unused_0[7]; 8479 u8 valid; 8480 }; 8481 8482 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ 8483 struct hwrm_stat_ext_ctx_query_input { 8484 __le16 req_type; 8485 __le16 cmpl_ring; 8486 __le16 seq_id; 8487 __le16 target_id; 8488 __le64 resp_addr; 8489 __le32 stat_ctx_id; 8490 u8 flags; 8491 #define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 8492 u8 unused_0[3]; 8493 }; 8494 8495 /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */ 8496 struct hwrm_stat_ext_ctx_query_output { 8497 __le16 error_code; 8498 __le16 req_type; 8499 __le16 seq_id; 8500 __le16 resp_len; 8501 __le64 rx_ucast_pkts; 8502 __le64 rx_mcast_pkts; 8503 __le64 rx_bcast_pkts; 8504 __le64 rx_discard_pkts; 8505 __le64 rx_error_pkts; 8506 __le64 rx_ucast_bytes; 8507 __le64 rx_mcast_bytes; 8508 __le64 rx_bcast_bytes; 8509 __le64 tx_ucast_pkts; 8510 __le64 tx_mcast_pkts; 8511 __le64 tx_bcast_pkts; 8512 __le64 tx_error_pkts; 8513 __le64 tx_discard_pkts; 8514 __le64 tx_ucast_bytes; 8515 __le64 tx_mcast_bytes; 8516 __le64 tx_bcast_bytes; 8517 __le64 rx_tpa_eligible_pkt; 8518 __le64 rx_tpa_eligible_bytes; 8519 __le64 rx_tpa_pkt; 8520 __le64 rx_tpa_bytes; 8521 __le64 rx_tpa_errors; 8522 __le64 rx_tpa_events; 8523 u8 unused_0[7]; 8524 u8 valid; 8525 }; 8526 8527 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 8528 struct hwrm_stat_ctx_clr_stats_input { 8529 __le16 req_type; 8530 __le16 cmpl_ring; 8531 __le16 seq_id; 8532 __le16 target_id; 8533 __le64 resp_addr; 8534 __le32 stat_ctx_id; 8535 u8 unused_0[4]; 8536 }; 8537 8538 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 8539 struct hwrm_stat_ctx_clr_stats_output { 8540 __le16 error_code; 8541 __le16 req_type; 8542 __le16 seq_id; 8543 __le16 resp_len; 8544 u8 unused_0[7]; 8545 u8 valid; 8546 }; 8547 8548 /* hwrm_pcie_qstats_input (size:256b/32B) */ 8549 struct hwrm_pcie_qstats_input { 8550 __le16 req_type; 8551 __le16 cmpl_ring; 8552 __le16 seq_id; 8553 __le16 target_id; 8554 __le64 resp_addr; 8555 __le16 pcie_stat_size; 8556 u8 unused_0[6]; 8557 __le64 pcie_stat_host_addr; 8558 }; 8559 8560 /* hwrm_pcie_qstats_output (size:128b/16B) */ 8561 struct hwrm_pcie_qstats_output { 8562 __le16 error_code; 8563 __le16 req_type; 8564 __le16 seq_id; 8565 __le16 resp_len; 8566 __le16 pcie_stat_size; 8567 u8 unused_0[5]; 8568 u8 valid; 8569 }; 8570 8571 /* pcie_ctx_hw_stats (size:768b/96B) */ 8572 struct pcie_ctx_hw_stats { 8573 __le64 pcie_pl_signal_integrity; 8574 __le64 pcie_dl_signal_integrity; 8575 __le64 pcie_tl_signal_integrity; 8576 __le64 pcie_link_integrity; 8577 __le64 pcie_tx_traffic_rate; 8578 __le64 pcie_rx_traffic_rate; 8579 __le64 pcie_tx_dllp_statistics; 8580 __le64 pcie_rx_dllp_statistics; 8581 __le64 pcie_equalization_time; 8582 __le32 pcie_ltssm_histogram[4]; 8583 __le64 pcie_recovery_histogram; 8584 }; 8585 8586 /* hwrm_fw_reset_input (size:192b/24B) */ 8587 struct hwrm_fw_reset_input { 8588 __le16 req_type; 8589 __le16 cmpl_ring; 8590 __le16 seq_id; 8591 __le16 target_id; 8592 __le64 resp_addr; 8593 u8 embedded_proc_type; 8594 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 8595 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 8596 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 8597 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 8598 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 8599 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 8600 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 8601 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 8602 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL 8603 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 8604 u8 selfrst_status; 8605 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 8606 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 8607 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 8608 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 8609 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 8610 u8 host_idx; 8611 u8 flags; 8612 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL 8613 #define FW_RESET_REQ_FLAGS_FW_ACTIVATION 0x2UL 8614 u8 unused_0[4]; 8615 }; 8616 8617 /* hwrm_fw_reset_output (size:128b/16B) */ 8618 struct hwrm_fw_reset_output { 8619 __le16 error_code; 8620 __le16 req_type; 8621 __le16 seq_id; 8622 __le16 resp_len; 8623 u8 selfrst_status; 8624 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 8625 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 8626 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 8627 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 8628 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 8629 u8 unused_0[6]; 8630 u8 valid; 8631 }; 8632 8633 /* hwrm_fw_qstatus_input (size:192b/24B) */ 8634 struct hwrm_fw_qstatus_input { 8635 __le16 req_type; 8636 __le16 cmpl_ring; 8637 __le16 seq_id; 8638 __le16 target_id; 8639 __le64 resp_addr; 8640 u8 embedded_proc_type; 8641 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 8642 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 8643 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 8644 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 8645 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 8646 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 8647 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 8648 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 8649 u8 unused_0[7]; 8650 }; 8651 8652 /* hwrm_fw_qstatus_output (size:128b/16B) */ 8653 struct hwrm_fw_qstatus_output { 8654 __le16 error_code; 8655 __le16 req_type; 8656 __le16 seq_id; 8657 __le16 resp_len; 8658 u8 selfrst_status; 8659 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 8660 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 8661 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 8662 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL 8663 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 8664 u8 nvm_option_action_status; 8665 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_NONE 0x0UL 8666 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_HOTRESET 0x1UL 8667 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_WARMBOOT 0x2UL 8668 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 0x3UL 8669 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_LAST FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 8670 u8 unused_0[5]; 8671 u8 valid; 8672 }; 8673 8674 /* hwrm_fw_set_time_input (size:256b/32B) */ 8675 struct hwrm_fw_set_time_input { 8676 __le16 req_type; 8677 __le16 cmpl_ring; 8678 __le16 seq_id; 8679 __le16 target_id; 8680 __le64 resp_addr; 8681 __le16 year; 8682 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 8683 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 8684 u8 month; 8685 u8 day; 8686 u8 hour; 8687 u8 minute; 8688 u8 second; 8689 u8 unused_0; 8690 __le16 millisecond; 8691 __le16 zone; 8692 #define FW_SET_TIME_REQ_ZONE_UTC 0 8693 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535 8694 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 8695 u8 unused_1[4]; 8696 }; 8697 8698 /* hwrm_fw_set_time_output (size:128b/16B) */ 8699 struct hwrm_fw_set_time_output { 8700 __le16 error_code; 8701 __le16 req_type; 8702 __le16 seq_id; 8703 __le16 resp_len; 8704 u8 unused_0[7]; 8705 u8 valid; 8706 }; 8707 8708 /* hwrm_struct_hdr (size:128b/16B) */ 8709 struct hwrm_struct_hdr { 8710 __le16 struct_id; 8711 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 8712 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 8713 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 8714 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 8715 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 8716 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 8717 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 8718 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL 8719 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 8720 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 8721 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 8722 #define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL 8723 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 8724 __le16 len; 8725 u8 version; 8726 u8 count; 8727 __le16 subtype; 8728 __le16 next_offset; 8729 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 8730 u8 unused_0[6]; 8731 }; 8732 8733 /* hwrm_struct_data_dcbx_app (size:64b/8B) */ 8734 struct hwrm_struct_data_dcbx_app { 8735 __be16 protocol_id; 8736 u8 protocol_selector; 8737 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 8738 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 8739 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 8740 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 8741 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 8742 u8 priority; 8743 u8 valid; 8744 u8 unused_0[3]; 8745 }; 8746 8747 /* hwrm_fw_set_structured_data_input (size:256b/32B) */ 8748 struct hwrm_fw_set_structured_data_input { 8749 __le16 req_type; 8750 __le16 cmpl_ring; 8751 __le16 seq_id; 8752 __le16 target_id; 8753 __le64 resp_addr; 8754 __le64 src_data_addr; 8755 __le16 data_len; 8756 u8 hdr_cnt; 8757 u8 unused_0[5]; 8758 }; 8759 8760 /* hwrm_fw_set_structured_data_output (size:128b/16B) */ 8761 struct hwrm_fw_set_structured_data_output { 8762 __le16 error_code; 8763 __le16 req_type; 8764 __le16 seq_id; 8765 __le16 resp_len; 8766 u8 unused_0[7]; 8767 u8 valid; 8768 }; 8769 8770 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 8771 struct hwrm_fw_set_structured_data_cmd_err { 8772 u8 code; 8773 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 8774 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 8775 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 8776 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 8777 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 8778 u8 unused_0[7]; 8779 }; 8780 8781 /* hwrm_fw_get_structured_data_input (size:256b/32B) */ 8782 struct hwrm_fw_get_structured_data_input { 8783 __le16 req_type; 8784 __le16 cmpl_ring; 8785 __le16 seq_id; 8786 __le16 target_id; 8787 __le64 resp_addr; 8788 __le64 dest_data_addr; 8789 __le16 data_len; 8790 __le16 structure_id; 8791 __le16 subtype; 8792 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 8793 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 8794 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 8795 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 8796 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 8797 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 8798 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 8799 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 8800 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 8801 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 8802 u8 count; 8803 u8 unused_0; 8804 }; 8805 8806 /* hwrm_fw_get_structured_data_output (size:128b/16B) */ 8807 struct hwrm_fw_get_structured_data_output { 8808 __le16 error_code; 8809 __le16 req_type; 8810 __le16 seq_id; 8811 __le16 resp_len; 8812 u8 hdr_cnt; 8813 u8 unused_0[6]; 8814 u8 valid; 8815 }; 8816 8817 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 8818 struct hwrm_fw_get_structured_data_cmd_err { 8819 u8 code; 8820 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 8821 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 8822 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 8823 u8 unused_0[7]; 8824 }; 8825 8826 /* hwrm_fw_livepatch_query_input (size:192b/24B) */ 8827 struct hwrm_fw_livepatch_query_input { 8828 __le16 req_type; 8829 __le16 cmpl_ring; 8830 __le16 seq_id; 8831 __le16 target_id; 8832 __le64 resp_addr; 8833 u8 fw_target; 8834 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_COMMON_FW 0x1UL 8835 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 0x2UL 8836 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_LAST FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 8837 u8 unused_0[7]; 8838 }; 8839 8840 /* hwrm_fw_livepatch_query_output (size:640b/80B) */ 8841 struct hwrm_fw_livepatch_query_output { 8842 __le16 error_code; 8843 __le16 req_type; 8844 __le16 seq_id; 8845 __le16 resp_len; 8846 char install_ver[32]; 8847 char active_ver[32]; 8848 __le16 status_flags; 8849 #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_INSTALL 0x1UL 8850 #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_ACTIVE 0x2UL 8851 u8 unused_0[5]; 8852 u8 valid; 8853 }; 8854 8855 /* hwrm_fw_livepatch_input (size:256b/32B) */ 8856 struct hwrm_fw_livepatch_input { 8857 __le16 req_type; 8858 __le16 cmpl_ring; 8859 __le16 seq_id; 8860 __le16 target_id; 8861 __le64 resp_addr; 8862 u8 opcode; 8863 #define FW_LIVEPATCH_REQ_OPCODE_ACTIVATE 0x1UL 8864 #define FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 0x2UL 8865 #define FW_LIVEPATCH_REQ_OPCODE_LAST FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 8866 u8 fw_target; 8867 #define FW_LIVEPATCH_REQ_FW_TARGET_COMMON_FW 0x1UL 8868 #define FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 0x2UL 8869 #define FW_LIVEPATCH_REQ_FW_TARGET_LAST FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 8870 u8 loadtype; 8871 #define FW_LIVEPATCH_REQ_LOADTYPE_NVM_INSTALL 0x1UL 8872 #define FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 0x2UL 8873 #define FW_LIVEPATCH_REQ_LOADTYPE_LAST FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 8874 u8 flags; 8875 __le32 patch_len; 8876 __le64 host_addr; 8877 }; 8878 8879 /* hwrm_fw_livepatch_output (size:128b/16B) */ 8880 struct hwrm_fw_livepatch_output { 8881 __le16 error_code; 8882 __le16 req_type; 8883 __le16 seq_id; 8884 __le16 resp_len; 8885 u8 unused_0[7]; 8886 u8 valid; 8887 }; 8888 8889 /* hwrm_fw_livepatch_cmd_err (size:64b/8B) */ 8890 struct hwrm_fw_livepatch_cmd_err { 8891 u8 code; 8892 #define FW_LIVEPATCH_CMD_ERR_CODE_UNKNOWN 0x0UL 8893 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_OPCODE 0x1UL 8894 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_TARGET 0x2UL 8895 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_SUPPORTED 0x3UL 8896 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_INSTALLED 0x4UL 8897 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_PATCHED 0x5UL 8898 #define FW_LIVEPATCH_CMD_ERR_CODE_AUTH_FAIL 0x6UL 8899 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_HEADER 0x7UL 8900 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_SIZE 0x8UL 8901 #define FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 0x9UL 8902 #define FW_LIVEPATCH_CMD_ERR_CODE_LAST FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 8903 u8 unused_0[7]; 8904 }; 8905 8906 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 8907 struct hwrm_exec_fwd_resp_input { 8908 __le16 req_type; 8909 __le16 cmpl_ring; 8910 __le16 seq_id; 8911 __le16 target_id; 8912 __le64 resp_addr; 8913 __le32 encap_request[26]; 8914 __le16 encap_resp_target_id; 8915 u8 unused_0[6]; 8916 }; 8917 8918 /* hwrm_exec_fwd_resp_output (size:128b/16B) */ 8919 struct hwrm_exec_fwd_resp_output { 8920 __le16 error_code; 8921 __le16 req_type; 8922 __le16 seq_id; 8923 __le16 resp_len; 8924 u8 unused_0[7]; 8925 u8 valid; 8926 }; 8927 8928 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 8929 struct hwrm_reject_fwd_resp_input { 8930 __le16 req_type; 8931 __le16 cmpl_ring; 8932 __le16 seq_id; 8933 __le16 target_id; 8934 __le64 resp_addr; 8935 __le32 encap_request[26]; 8936 __le16 encap_resp_target_id; 8937 u8 unused_0[6]; 8938 }; 8939 8940 /* hwrm_reject_fwd_resp_output (size:128b/16B) */ 8941 struct hwrm_reject_fwd_resp_output { 8942 __le16 error_code; 8943 __le16 req_type; 8944 __le16 seq_id; 8945 __le16 resp_len; 8946 u8 unused_0[7]; 8947 u8 valid; 8948 }; 8949 8950 /* hwrm_fwd_resp_input (size:1024b/128B) */ 8951 struct hwrm_fwd_resp_input { 8952 __le16 req_type; 8953 __le16 cmpl_ring; 8954 __le16 seq_id; 8955 __le16 target_id; 8956 __le64 resp_addr; 8957 __le16 encap_resp_target_id; 8958 __le16 encap_resp_cmpl_ring; 8959 __le16 encap_resp_len; 8960 u8 unused_0; 8961 u8 unused_1; 8962 __le64 encap_resp_addr; 8963 __le32 encap_resp[24]; 8964 }; 8965 8966 /* hwrm_fwd_resp_output (size:128b/16B) */ 8967 struct hwrm_fwd_resp_output { 8968 __le16 error_code; 8969 __le16 req_type; 8970 __le16 seq_id; 8971 __le16 resp_len; 8972 u8 unused_0[7]; 8973 u8 valid; 8974 }; 8975 8976 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 8977 struct hwrm_fwd_async_event_cmpl_input { 8978 __le16 req_type; 8979 __le16 cmpl_ring; 8980 __le16 seq_id; 8981 __le16 target_id; 8982 __le64 resp_addr; 8983 __le16 encap_async_event_target_id; 8984 u8 unused_0[6]; 8985 __le32 encap_async_event_cmpl[4]; 8986 }; 8987 8988 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 8989 struct hwrm_fwd_async_event_cmpl_output { 8990 __le16 error_code; 8991 __le16 req_type; 8992 __le16 seq_id; 8993 __le16 resp_len; 8994 u8 unused_0[7]; 8995 u8 valid; 8996 }; 8997 8998 /* hwrm_temp_monitor_query_input (size:128b/16B) */ 8999 struct hwrm_temp_monitor_query_input { 9000 __le16 req_type; 9001 __le16 cmpl_ring; 9002 __le16 seq_id; 9003 __le16 target_id; 9004 __le64 resp_addr; 9005 }; 9006 9007 /* hwrm_temp_monitor_query_output (size:128b/16B) */ 9008 struct hwrm_temp_monitor_query_output { 9009 __le16 error_code; 9010 __le16 req_type; 9011 __le16 seq_id; 9012 __le16 resp_len; 9013 u8 temp; 9014 u8 phy_temp; 9015 u8 om_temp; 9016 u8 flags; 9017 #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL 9018 #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL 9019 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL 9020 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL 9021 #define TEMP_MONITOR_QUERY_RESP_FLAGS_EXT_TEMP_FIELDS_AVAILABLE 0x10UL 9022 u8 temp2; 9023 u8 phy_temp2; 9024 u8 om_temp2; 9025 u8 valid; 9026 }; 9027 9028 /* hwrm_wol_filter_alloc_input (size:512b/64B) */ 9029 struct hwrm_wol_filter_alloc_input { 9030 __le16 req_type; 9031 __le16 cmpl_ring; 9032 __le16 seq_id; 9033 __le16 target_id; 9034 __le64 resp_addr; 9035 __le32 flags; 9036 __le32 enables; 9037 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 9038 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 9039 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 9040 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 9041 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 9042 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 9043 __le16 port_id; 9044 u8 wol_type; 9045 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 9046 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 9047 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 9048 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 9049 u8 unused_0[5]; 9050 u8 mac_address[6]; 9051 __le16 pattern_offset; 9052 __le16 pattern_buf_size; 9053 __le16 pattern_mask_size; 9054 u8 unused_1[4]; 9055 __le64 pattern_buf_addr; 9056 __le64 pattern_mask_addr; 9057 }; 9058 9059 /* hwrm_wol_filter_alloc_output (size:128b/16B) */ 9060 struct hwrm_wol_filter_alloc_output { 9061 __le16 error_code; 9062 __le16 req_type; 9063 __le16 seq_id; 9064 __le16 resp_len; 9065 u8 wol_filter_id; 9066 u8 unused_0[6]; 9067 u8 valid; 9068 }; 9069 9070 /* hwrm_wol_filter_free_input (size:256b/32B) */ 9071 struct hwrm_wol_filter_free_input { 9072 __le16 req_type; 9073 __le16 cmpl_ring; 9074 __le16 seq_id; 9075 __le16 target_id; 9076 __le64 resp_addr; 9077 __le32 flags; 9078 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 9079 __le32 enables; 9080 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 9081 __le16 port_id; 9082 u8 wol_filter_id; 9083 u8 unused_0[5]; 9084 }; 9085 9086 /* hwrm_wol_filter_free_output (size:128b/16B) */ 9087 struct hwrm_wol_filter_free_output { 9088 __le16 error_code; 9089 __le16 req_type; 9090 __le16 seq_id; 9091 __le16 resp_len; 9092 u8 unused_0[7]; 9093 u8 valid; 9094 }; 9095 9096 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 9097 struct hwrm_wol_filter_qcfg_input { 9098 __le16 req_type; 9099 __le16 cmpl_ring; 9100 __le16 seq_id; 9101 __le16 target_id; 9102 __le64 resp_addr; 9103 __le16 port_id; 9104 __le16 handle; 9105 u8 unused_0[4]; 9106 __le64 pattern_buf_addr; 9107 __le16 pattern_buf_size; 9108 u8 unused_1[6]; 9109 __le64 pattern_mask_addr; 9110 __le16 pattern_mask_size; 9111 u8 unused_2[6]; 9112 }; 9113 9114 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 9115 struct hwrm_wol_filter_qcfg_output { 9116 __le16 error_code; 9117 __le16 req_type; 9118 __le16 seq_id; 9119 __le16 resp_len; 9120 __le16 next_handle; 9121 u8 wol_filter_id; 9122 u8 wol_type; 9123 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 9124 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 9125 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 9126 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 9127 __le32 unused_0; 9128 u8 mac_address[6]; 9129 __le16 pattern_offset; 9130 __le16 pattern_size; 9131 __le16 pattern_mask_size; 9132 u8 unused_1[3]; 9133 u8 valid; 9134 }; 9135 9136 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 9137 struct hwrm_wol_reason_qcfg_input { 9138 __le16 req_type; 9139 __le16 cmpl_ring; 9140 __le16 seq_id; 9141 __le16 target_id; 9142 __le64 resp_addr; 9143 __le16 port_id; 9144 u8 unused_0[6]; 9145 __le64 wol_pkt_buf_addr; 9146 __le16 wol_pkt_buf_size; 9147 u8 unused_1[6]; 9148 }; 9149 9150 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 9151 struct hwrm_wol_reason_qcfg_output { 9152 __le16 error_code; 9153 __le16 req_type; 9154 __le16 seq_id; 9155 __le16 resp_len; 9156 u8 wol_filter_id; 9157 u8 wol_reason; 9158 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 9159 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 9160 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 9161 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 9162 u8 wol_pkt_len; 9163 u8 unused_0[4]; 9164 u8 valid; 9165 }; 9166 9167 /* hwrm_dbg_read_direct_input (size:256b/32B) */ 9168 struct hwrm_dbg_read_direct_input { 9169 __le16 req_type; 9170 __le16 cmpl_ring; 9171 __le16 seq_id; 9172 __le16 target_id; 9173 __le64 resp_addr; 9174 __le64 host_dest_addr; 9175 __le32 read_addr; 9176 __le32 read_len32; 9177 }; 9178 9179 /* hwrm_dbg_read_direct_output (size:128b/16B) */ 9180 struct hwrm_dbg_read_direct_output { 9181 __le16 error_code; 9182 __le16 req_type; 9183 __le16 seq_id; 9184 __le16 resp_len; 9185 __le32 crc32; 9186 u8 unused_0[3]; 9187 u8 valid; 9188 }; 9189 9190 /* hwrm_dbg_qcaps_input (size:192b/24B) */ 9191 struct hwrm_dbg_qcaps_input { 9192 __le16 req_type; 9193 __le16 cmpl_ring; 9194 __le16 seq_id; 9195 __le16 target_id; 9196 __le64 resp_addr; 9197 __le16 fid; 9198 u8 unused_0[6]; 9199 }; 9200 9201 /* hwrm_dbg_qcaps_output (size:192b/24B) */ 9202 struct hwrm_dbg_qcaps_output { 9203 __le16 error_code; 9204 __le16 req_type; 9205 __le16 seq_id; 9206 __le16 resp_len; 9207 __le16 fid; 9208 u8 unused_0[2]; 9209 __le32 coredump_component_disable_caps; 9210 #define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM 0x1UL 9211 __le32 flags; 9212 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL 9213 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL 9214 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL 9215 #define DBG_QCAPS_RESP_FLAGS_USEQ 0x8UL 9216 u8 unused_1[3]; 9217 u8 valid; 9218 }; 9219 9220 /* hwrm_dbg_qcfg_input (size:192b/24B) */ 9221 struct hwrm_dbg_qcfg_input { 9222 __le16 req_type; 9223 __le16 cmpl_ring; 9224 __le16 seq_id; 9225 __le16 target_id; 9226 __le64 resp_addr; 9227 __le16 fid; 9228 __le16 flags; 9229 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK 0x3UL 9230 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0 9231 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM 0x0UL 9232 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR 0x1UL 9233 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 0x2UL 9234 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 9235 __le32 coredump_component_disable_flags; 9236 #define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM 0x1UL 9237 }; 9238 9239 /* hwrm_dbg_qcfg_output (size:256b/32B) */ 9240 struct hwrm_dbg_qcfg_output { 9241 __le16 error_code; 9242 __le16 req_type; 9243 __le16 seq_id; 9244 __le16 resp_len; 9245 __le16 fid; 9246 u8 unused_0[2]; 9247 __le32 coredump_size; 9248 __le32 flags; 9249 #define DBG_QCFG_RESP_FLAGS_UART_LOG 0x1UL 9250 #define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY 0x2UL 9251 #define DBG_QCFG_RESP_FLAGS_FW_TRACE 0x4UL 9252 #define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY 0x8UL 9253 #define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY 0x10UL 9254 #define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG 0x20UL 9255 __le16 async_cmpl_ring; 9256 u8 unused_2[2]; 9257 __le32 crashdump_size; 9258 u8 unused_3[3]; 9259 u8 valid; 9260 }; 9261 9262 /* hwrm_dbg_crashdump_medium_cfg_input (size:320b/40B) */ 9263 struct hwrm_dbg_crashdump_medium_cfg_input { 9264 __le16 req_type; 9265 __le16 cmpl_ring; 9266 __le16 seq_id; 9267 __le16 target_id; 9268 __le64 resp_addr; 9269 __le16 output_dest_flags; 9270 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_TYPE_DDR 0x1UL 9271 __le16 pg_size_lvl; 9272 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_MASK 0x3UL 9273 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_SFT 0 9274 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_0 0x0UL 9275 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_1 0x1UL 9276 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2 0x2UL 9277 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2 9278 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_MASK 0x1cUL 9279 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_SFT 2 9280 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_4K (0x0UL << 2) 9281 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8K (0x1UL << 2) 9282 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_64K (0x2UL << 2) 9283 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_2M (0x3UL << 2) 9284 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8M (0x4UL << 2) 9285 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G (0x5UL << 2) 9286 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G 9287 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_MASK 0xffe0UL 9288 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_SFT 5 9289 __le32 size; 9290 __le32 coredump_component_disable_flags; 9291 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_NVRAM 0x1UL 9292 __le32 unused_0; 9293 __le64 pbl; 9294 }; 9295 9296 /* hwrm_dbg_crashdump_medium_cfg_output (size:128b/16B) */ 9297 struct hwrm_dbg_crashdump_medium_cfg_output { 9298 __le16 error_code; 9299 __le16 req_type; 9300 __le16 seq_id; 9301 __le16 resp_len; 9302 u8 unused_1[7]; 9303 u8 valid; 9304 }; 9305 9306 /* coredump_segment_record (size:128b/16B) */ 9307 struct coredump_segment_record { 9308 __le16 component_id; 9309 __le16 segment_id; 9310 __le16 max_instances; 9311 u8 version_hi; 9312 u8 version_low; 9313 u8 seg_flags; 9314 u8 compress_flags; 9315 #define SFLAG_COMPRESSED_ZLIB 0x1UL 9316 u8 unused_0[2]; 9317 __le32 segment_len; 9318 }; 9319 9320 /* hwrm_dbg_coredump_list_input (size:256b/32B) */ 9321 struct hwrm_dbg_coredump_list_input { 9322 __le16 req_type; 9323 __le16 cmpl_ring; 9324 __le16 seq_id; 9325 __le16 target_id; 9326 __le64 resp_addr; 9327 __le64 host_dest_addr; 9328 __le32 host_buf_len; 9329 __le16 seq_no; 9330 u8 flags; 9331 #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL 9332 u8 unused_0[1]; 9333 }; 9334 9335 /* hwrm_dbg_coredump_list_output (size:128b/16B) */ 9336 struct hwrm_dbg_coredump_list_output { 9337 __le16 error_code; 9338 __le16 req_type; 9339 __le16 seq_id; 9340 __le16 resp_len; 9341 u8 flags; 9342 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 9343 u8 unused_0; 9344 __le16 total_segments; 9345 __le16 data_len; 9346 u8 unused_1; 9347 u8 valid; 9348 }; 9349 9350 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 9351 struct hwrm_dbg_coredump_initiate_input { 9352 __le16 req_type; 9353 __le16 cmpl_ring; 9354 __le16 seq_id; 9355 __le16 target_id; 9356 __le64 resp_addr; 9357 __le16 component_id; 9358 __le16 segment_id; 9359 __le16 instance; 9360 __le16 unused_0; 9361 u8 seg_flags; 9362 u8 unused_1[7]; 9363 }; 9364 9365 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 9366 struct hwrm_dbg_coredump_initiate_output { 9367 __le16 error_code; 9368 __le16 req_type; 9369 __le16 seq_id; 9370 __le16 resp_len; 9371 u8 unused_0[7]; 9372 u8 valid; 9373 }; 9374 9375 /* coredump_data_hdr (size:128b/16B) */ 9376 struct coredump_data_hdr { 9377 __le32 address; 9378 __le32 flags_length; 9379 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK 0xffffffUL 9380 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT 0 9381 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS 0x1000000UL 9382 __le32 instance; 9383 __le32 next_offset; 9384 }; 9385 9386 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 9387 struct hwrm_dbg_coredump_retrieve_input { 9388 __le16 req_type; 9389 __le16 cmpl_ring; 9390 __le16 seq_id; 9391 __le16 target_id; 9392 __le64 resp_addr; 9393 __le64 host_dest_addr; 9394 __le32 host_buf_len; 9395 __le32 unused_0; 9396 __le16 component_id; 9397 __le16 segment_id; 9398 __le16 instance; 9399 __le16 unused_1; 9400 u8 seg_flags; 9401 u8 unused_2; 9402 __le16 unused_3; 9403 __le32 unused_4; 9404 __le32 seq_no; 9405 __le32 unused_5; 9406 }; 9407 9408 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 9409 struct hwrm_dbg_coredump_retrieve_output { 9410 __le16 error_code; 9411 __le16 req_type; 9412 __le16 seq_id; 9413 __le16 resp_len; 9414 u8 flags; 9415 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 9416 u8 unused_0; 9417 __le16 data_len; 9418 u8 unused_1[3]; 9419 u8 valid; 9420 }; 9421 9422 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 9423 struct hwrm_dbg_ring_info_get_input { 9424 __le16 req_type; 9425 __le16 cmpl_ring; 9426 __le16 seq_id; 9427 __le16 target_id; 9428 __le64 resp_addr; 9429 u8 ring_type; 9430 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 9431 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 9432 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 9433 #define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 0x3UL 9434 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 9435 u8 unused_0[3]; 9436 __le32 fw_ring_id; 9437 }; 9438 9439 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 9440 struct hwrm_dbg_ring_info_get_output { 9441 __le16 error_code; 9442 __le16 req_type; 9443 __le16 seq_id; 9444 __le16 resp_len; 9445 __le32 producer_index; 9446 __le32 consumer_index; 9447 __le32 cag_vector_ctrl; 9448 u8 unused_0[3]; 9449 u8 valid; 9450 }; 9451 9452 /* hwrm_nvm_read_input (size:320b/40B) */ 9453 struct hwrm_nvm_read_input { 9454 __le16 req_type; 9455 __le16 cmpl_ring; 9456 __le16 seq_id; 9457 __le16 target_id; 9458 __le64 resp_addr; 9459 __le64 host_dest_addr; 9460 __le16 dir_idx; 9461 u8 unused_0[2]; 9462 __le32 offset; 9463 __le32 len; 9464 u8 unused_1[4]; 9465 }; 9466 9467 /* hwrm_nvm_read_output (size:128b/16B) */ 9468 struct hwrm_nvm_read_output { 9469 __le16 error_code; 9470 __le16 req_type; 9471 __le16 seq_id; 9472 __le16 resp_len; 9473 u8 unused_0[7]; 9474 u8 valid; 9475 }; 9476 9477 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 9478 struct hwrm_nvm_get_dir_entries_input { 9479 __le16 req_type; 9480 __le16 cmpl_ring; 9481 __le16 seq_id; 9482 __le16 target_id; 9483 __le64 resp_addr; 9484 __le64 host_dest_addr; 9485 }; 9486 9487 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 9488 struct hwrm_nvm_get_dir_entries_output { 9489 __le16 error_code; 9490 __le16 req_type; 9491 __le16 seq_id; 9492 __le16 resp_len; 9493 u8 unused_0[7]; 9494 u8 valid; 9495 }; 9496 9497 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 9498 struct hwrm_nvm_get_dir_info_input { 9499 __le16 req_type; 9500 __le16 cmpl_ring; 9501 __le16 seq_id; 9502 __le16 target_id; 9503 __le64 resp_addr; 9504 }; 9505 9506 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 9507 struct hwrm_nvm_get_dir_info_output { 9508 __le16 error_code; 9509 __le16 req_type; 9510 __le16 seq_id; 9511 __le16 resp_len; 9512 __le32 entries; 9513 __le32 entry_length; 9514 u8 unused_0[7]; 9515 u8 valid; 9516 }; 9517 9518 /* hwrm_nvm_write_input (size:448b/56B) */ 9519 struct hwrm_nvm_write_input { 9520 __le16 req_type; 9521 __le16 cmpl_ring; 9522 __le16 seq_id; 9523 __le16 target_id; 9524 __le64 resp_addr; 9525 __le64 host_src_addr; 9526 __le16 dir_type; 9527 __le16 dir_ordinal; 9528 __le16 dir_ext; 9529 __le16 dir_attr; 9530 __le32 dir_data_length; 9531 __le16 option; 9532 __le16 flags; 9533 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 9534 #define NVM_WRITE_REQ_FLAGS_BATCH_MODE 0x2UL 9535 #define NVM_WRITE_REQ_FLAGS_BATCH_LAST 0x4UL 9536 __le32 dir_item_length; 9537 __le32 offset; 9538 __le32 len; 9539 __le32 unused_0; 9540 }; 9541 9542 /* hwrm_nvm_write_output (size:128b/16B) */ 9543 struct hwrm_nvm_write_output { 9544 __le16 error_code; 9545 __le16 req_type; 9546 __le16 seq_id; 9547 __le16 resp_len; 9548 __le32 dir_item_length; 9549 __le16 dir_idx; 9550 u8 unused_0; 9551 u8 valid; 9552 }; 9553 9554 /* hwrm_nvm_write_cmd_err (size:64b/8B) */ 9555 struct hwrm_nvm_write_cmd_err { 9556 u8 code; 9557 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 9558 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 9559 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 9560 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 9561 u8 unused_0[7]; 9562 }; 9563 9564 /* hwrm_nvm_modify_input (size:320b/40B) */ 9565 struct hwrm_nvm_modify_input { 9566 __le16 req_type; 9567 __le16 cmpl_ring; 9568 __le16 seq_id; 9569 __le16 target_id; 9570 __le64 resp_addr; 9571 __le64 host_src_addr; 9572 __le16 dir_idx; 9573 __le16 flags; 9574 #define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL 9575 #define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL 9576 __le32 offset; 9577 __le32 len; 9578 u8 unused_1[4]; 9579 }; 9580 9581 /* hwrm_nvm_modify_output (size:128b/16B) */ 9582 struct hwrm_nvm_modify_output { 9583 __le16 error_code; 9584 __le16 req_type; 9585 __le16 seq_id; 9586 __le16 resp_len; 9587 u8 unused_0[7]; 9588 u8 valid; 9589 }; 9590 9591 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 9592 struct hwrm_nvm_find_dir_entry_input { 9593 __le16 req_type; 9594 __le16 cmpl_ring; 9595 __le16 seq_id; 9596 __le16 target_id; 9597 __le64 resp_addr; 9598 __le32 enables; 9599 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 9600 __le16 dir_idx; 9601 __le16 dir_type; 9602 __le16 dir_ordinal; 9603 __le16 dir_ext; 9604 u8 opt_ordinal; 9605 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 9606 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 9607 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 9608 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 9609 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 9610 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 9611 u8 unused_0[3]; 9612 }; 9613 9614 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 9615 struct hwrm_nvm_find_dir_entry_output { 9616 __le16 error_code; 9617 __le16 req_type; 9618 __le16 seq_id; 9619 __le16 resp_len; 9620 __le32 dir_item_length; 9621 __le32 dir_data_length; 9622 __le32 fw_ver; 9623 __le16 dir_ordinal; 9624 __le16 dir_idx; 9625 u8 unused_0[7]; 9626 u8 valid; 9627 }; 9628 9629 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 9630 struct hwrm_nvm_erase_dir_entry_input { 9631 __le16 req_type; 9632 __le16 cmpl_ring; 9633 __le16 seq_id; 9634 __le16 target_id; 9635 __le64 resp_addr; 9636 __le16 dir_idx; 9637 u8 unused_0[6]; 9638 }; 9639 9640 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 9641 struct hwrm_nvm_erase_dir_entry_output { 9642 __le16 error_code; 9643 __le16 req_type; 9644 __le16 seq_id; 9645 __le16 resp_len; 9646 u8 unused_0[7]; 9647 u8 valid; 9648 }; 9649 9650 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 9651 struct hwrm_nvm_get_dev_info_input { 9652 __le16 req_type; 9653 __le16 cmpl_ring; 9654 __le16 seq_id; 9655 __le16 target_id; 9656 __le64 resp_addr; 9657 }; 9658 9659 /* hwrm_nvm_get_dev_info_output (size:640b/80B) */ 9660 struct hwrm_nvm_get_dev_info_output { 9661 __le16 error_code; 9662 __le16 req_type; 9663 __le16 seq_id; 9664 __le16 resp_len; 9665 __le16 manufacturer_id; 9666 __le16 device_id; 9667 __le32 sector_size; 9668 __le32 nvram_size; 9669 __le32 reserved_size; 9670 __le32 available_size; 9671 u8 nvm_cfg_ver_maj; 9672 u8 nvm_cfg_ver_min; 9673 u8 nvm_cfg_ver_upd; 9674 u8 flags; 9675 #define NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID 0x1UL 9676 char pkg_name[16]; 9677 __le16 hwrm_fw_major; 9678 __le16 hwrm_fw_minor; 9679 __le16 hwrm_fw_build; 9680 __le16 hwrm_fw_patch; 9681 __le16 mgmt_fw_major; 9682 __le16 mgmt_fw_minor; 9683 __le16 mgmt_fw_build; 9684 __le16 mgmt_fw_patch; 9685 __le16 roce_fw_major; 9686 __le16 roce_fw_minor; 9687 __le16 roce_fw_build; 9688 __le16 roce_fw_patch; 9689 u8 unused_0[7]; 9690 u8 valid; 9691 }; 9692 9693 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 9694 struct hwrm_nvm_mod_dir_entry_input { 9695 __le16 req_type; 9696 __le16 cmpl_ring; 9697 __le16 seq_id; 9698 __le16 target_id; 9699 __le64 resp_addr; 9700 __le32 enables; 9701 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 9702 __le16 dir_idx; 9703 __le16 dir_ordinal; 9704 __le16 dir_ext; 9705 __le16 dir_attr; 9706 __le32 checksum; 9707 }; 9708 9709 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 9710 struct hwrm_nvm_mod_dir_entry_output { 9711 __le16 error_code; 9712 __le16 req_type; 9713 __le16 seq_id; 9714 __le16 resp_len; 9715 u8 unused_0[7]; 9716 u8 valid; 9717 }; 9718 9719 /* hwrm_nvm_verify_update_input (size:192b/24B) */ 9720 struct hwrm_nvm_verify_update_input { 9721 __le16 req_type; 9722 __le16 cmpl_ring; 9723 __le16 seq_id; 9724 __le16 target_id; 9725 __le64 resp_addr; 9726 __le16 dir_type; 9727 __le16 dir_ordinal; 9728 __le16 dir_ext; 9729 u8 unused_0[2]; 9730 }; 9731 9732 /* hwrm_nvm_verify_update_output (size:128b/16B) */ 9733 struct hwrm_nvm_verify_update_output { 9734 __le16 error_code; 9735 __le16 req_type; 9736 __le16 seq_id; 9737 __le16 resp_len; 9738 u8 unused_0[7]; 9739 u8 valid; 9740 }; 9741 9742 /* hwrm_nvm_install_update_input (size:192b/24B) */ 9743 struct hwrm_nvm_install_update_input { 9744 __le16 req_type; 9745 __le16 cmpl_ring; 9746 __le16 seq_id; 9747 __le16 target_id; 9748 __le64 resp_addr; 9749 __le32 install_type; 9750 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 9751 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 9752 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 9753 __le16 flags; 9754 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 9755 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 9756 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 9757 #define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY 0x8UL 9758 u8 unused_0[2]; 9759 }; 9760 9761 /* hwrm_nvm_install_update_output (size:192b/24B) */ 9762 struct hwrm_nvm_install_update_output { 9763 __le16 error_code; 9764 __le16 req_type; 9765 __le16 seq_id; 9766 __le16 resp_len; 9767 __le64 installed_items; 9768 u8 result; 9769 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 9770 #define NVM_INSTALL_UPDATE_RESP_RESULT_FAILURE 0xffUL 9771 #define NVM_INSTALL_UPDATE_RESP_RESULT_MALLOC_FAILURE 0xfdUL 9772 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER 0xfbUL 9773 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER 0xf3UL 9774 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE 0xf2UL 9775 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER 0xecUL 9776 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE 0xebUL 9777 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM 0xeaUL 9778 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH 0xe9UL 9779 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST 0xe8UL 9780 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER 0xe7UL 9781 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM 0xe6UL 9782 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM 0xe5UL 9783 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH 0xe4UL 9784 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE 0xe1UL 9785 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV 0xceUL 9786 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID 0xcdUL 9787 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR 0xccUL 9788 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID 0xcbUL 9789 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM 0xc5UL 9790 #define NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM 0xc4UL 9791 #define NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM 0xc3UL 9792 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR 0xb9UL 9793 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR 0xb8UL 9794 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR 0xb7UL 9795 #define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND 0xb0UL 9796 #define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED 0xa7UL 9797 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED 9798 u8 problem_item; 9799 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 9800 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 9801 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 9802 u8 reset_required; 9803 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 9804 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 9805 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 9806 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 9807 u8 unused_0[4]; 9808 u8 valid; 9809 }; 9810 9811 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 9812 struct hwrm_nvm_install_update_cmd_err { 9813 u8 code; 9814 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 9815 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 9816 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 9817 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK 0x3UL 9818 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK 9819 u8 unused_0[7]; 9820 }; 9821 9822 /* hwrm_nvm_get_variable_input (size:320b/40B) */ 9823 struct hwrm_nvm_get_variable_input { 9824 __le16 req_type; 9825 __le16 cmpl_ring; 9826 __le16 seq_id; 9827 __le16 target_id; 9828 __le64 resp_addr; 9829 __le64 dest_data_addr; 9830 __le16 data_len; 9831 __le16 option_num; 9832 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 9833 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 9834 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 9835 __le16 dimensions; 9836 __le16 index_0; 9837 __le16 index_1; 9838 __le16 index_2; 9839 __le16 index_3; 9840 u8 flags; 9841 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 9842 u8 unused_0; 9843 }; 9844 9845 /* hwrm_nvm_get_variable_output (size:128b/16B) */ 9846 struct hwrm_nvm_get_variable_output { 9847 __le16 error_code; 9848 __le16 req_type; 9849 __le16 seq_id; 9850 __le16 resp_len; 9851 __le16 data_len; 9852 __le16 option_num; 9853 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 9854 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 9855 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 9856 u8 unused_0[3]; 9857 u8 valid; 9858 }; 9859 9860 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 9861 struct hwrm_nvm_get_variable_cmd_err { 9862 u8 code; 9863 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 9864 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 9865 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 9866 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 9867 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 9868 u8 unused_0[7]; 9869 }; 9870 9871 /* hwrm_nvm_set_variable_input (size:320b/40B) */ 9872 struct hwrm_nvm_set_variable_input { 9873 __le16 req_type; 9874 __le16 cmpl_ring; 9875 __le16 seq_id; 9876 __le16 target_id; 9877 __le64 resp_addr; 9878 __le64 src_data_addr; 9879 __le16 data_len; 9880 __le16 option_num; 9881 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 9882 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 9883 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 9884 __le16 dimensions; 9885 __le16 index_0; 9886 __le16 index_1; 9887 __le16 index_2; 9888 __le16 index_3; 9889 u8 flags; 9890 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 9891 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 9892 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 9893 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 9894 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 9895 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 9896 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 9897 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 9898 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL 9899 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4 9900 #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL 9901 u8 unused_0; 9902 }; 9903 9904 /* hwrm_nvm_set_variable_output (size:128b/16B) */ 9905 struct hwrm_nvm_set_variable_output { 9906 __le16 error_code; 9907 __le16 req_type; 9908 __le16 seq_id; 9909 __le16 resp_len; 9910 u8 unused_0[7]; 9911 u8 valid; 9912 }; 9913 9914 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 9915 struct hwrm_nvm_set_variable_cmd_err { 9916 u8 code; 9917 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 9918 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 9919 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 9920 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 9921 u8 unused_0[7]; 9922 }; 9923 9924 /* hwrm_selftest_qlist_input (size:128b/16B) */ 9925 struct hwrm_selftest_qlist_input { 9926 __le16 req_type; 9927 __le16 cmpl_ring; 9928 __le16 seq_id; 9929 __le16 target_id; 9930 __le64 resp_addr; 9931 }; 9932 9933 /* hwrm_selftest_qlist_output (size:2240b/280B) */ 9934 struct hwrm_selftest_qlist_output { 9935 __le16 error_code; 9936 __le16 req_type; 9937 __le16 seq_id; 9938 __le16 resp_len; 9939 u8 num_tests; 9940 u8 available_tests; 9941 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 9942 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 9943 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 9944 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 9945 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 9946 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 9947 u8 offline_tests; 9948 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 9949 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 9950 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 9951 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 9952 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 9953 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 9954 u8 unused_0; 9955 __le16 test_timeout; 9956 u8 unused_1[2]; 9957 char test0_name[32]; 9958 char test1_name[32]; 9959 char test2_name[32]; 9960 char test3_name[32]; 9961 char test4_name[32]; 9962 char test5_name[32]; 9963 char test6_name[32]; 9964 char test7_name[32]; 9965 u8 eyescope_target_BER_support; 9966 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED 0x0UL 9967 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED 0x1UL 9968 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL 9969 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL 9970 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL 9971 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 9972 u8 unused_2[6]; 9973 u8 valid; 9974 }; 9975 9976 /* hwrm_selftest_exec_input (size:192b/24B) */ 9977 struct hwrm_selftest_exec_input { 9978 __le16 req_type; 9979 __le16 cmpl_ring; 9980 __le16 seq_id; 9981 __le16 target_id; 9982 __le64 resp_addr; 9983 u8 flags; 9984 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 9985 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 9986 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 9987 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 9988 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 9989 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 9990 u8 unused_0[7]; 9991 }; 9992 9993 /* hwrm_selftest_exec_output (size:128b/16B) */ 9994 struct hwrm_selftest_exec_output { 9995 __le16 error_code; 9996 __le16 req_type; 9997 __le16 seq_id; 9998 __le16 resp_len; 9999 u8 requested_tests; 10000 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 10001 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 10002 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 10003 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 10004 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 10005 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 10006 u8 test_success; 10007 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 10008 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 10009 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 10010 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 10011 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 10012 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 10013 u8 unused_0[5]; 10014 u8 valid; 10015 }; 10016 10017 /* hwrm_selftest_irq_input (size:128b/16B) */ 10018 struct hwrm_selftest_irq_input { 10019 __le16 req_type; 10020 __le16 cmpl_ring; 10021 __le16 seq_id; 10022 __le16 target_id; 10023 __le64 resp_addr; 10024 }; 10025 10026 /* hwrm_selftest_irq_output (size:128b/16B) */ 10027 struct hwrm_selftest_irq_output { 10028 __le16 error_code; 10029 __le16 req_type; 10030 __le16 seq_id; 10031 __le16 resp_len; 10032 u8 unused_0[7]; 10033 u8 valid; 10034 }; 10035 10036 /* db_push_info (size:64b/8B) */ 10037 struct db_push_info { 10038 u32 push_size_push_index; 10039 #define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL 10040 #define DB_PUSH_INFO_PUSH_INDEX_SFT 0 10041 #define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL 10042 #define DB_PUSH_INFO_PUSH_SIZE_SFT 24 10043 u32 reserved32; 10044 }; 10045 10046 /* fw_status_reg (size:32b/4B) */ 10047 struct fw_status_reg { 10048 u32 fw_status; 10049 #define FW_STATUS_REG_CODE_MASK 0xffffUL 10050 #define FW_STATUS_REG_CODE_SFT 0 10051 #define FW_STATUS_REG_CODE_READY 0x8000UL 10052 #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY 10053 #define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL 10054 #define FW_STATUS_REG_RECOVERABLE 0x20000UL 10055 #define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL 10056 #define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL 10057 #define FW_STATUS_REG_SHUTDOWN 0x100000UL 10058 #define FW_STATUS_REG_CRASHED_NO_MASTER 0x200000UL 10059 #define FW_STATUS_REG_RECOVERING 0x400000UL 10060 }; 10061 10062 /* hcomm_status (size:64b/8B) */ 10063 struct hcomm_status { 10064 u32 sig_ver; 10065 #define HCOMM_STATUS_VER_MASK 0xffUL 10066 #define HCOMM_STATUS_VER_SFT 0 10067 #define HCOMM_STATUS_VER_LATEST 0x1UL 10068 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST 10069 #define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL 10070 #define HCOMM_STATUS_SIGNATURE_SFT 8 10071 #define HCOMM_STATUS_SIGNATURE_VAL (0x484353UL << 8) 10072 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL 10073 u32 fw_status_loc; 10074 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK 0x3UL 10075 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 10076 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG 0x0UL 10077 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC 0x1UL 10078 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 0x2UL 10079 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 0x3UL 10080 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 10081 #define HCOMM_STATUS_TRUE_OFFSET_MASK 0xfffffffcUL 10082 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 10083 }; 10084 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL 10085 10086 #endif /* _BNXT_HSI_H_ */ 10087