1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 10 #ifndef BNXT_HSI_H 11 #define BNXT_HSI_H 12 13 /* per-context HW statistics -- chip view */ 14 struct ctx_hw_stats { 15 __le64 rx_ucast_pkts; 16 __le64 rx_mcast_pkts; 17 __le64 rx_bcast_pkts; 18 __le64 rx_discard_pkts; 19 __le64 rx_drop_pkts; 20 __le64 rx_ucast_bytes; 21 __le64 rx_mcast_bytes; 22 __le64 rx_bcast_bytes; 23 __le64 tx_ucast_pkts; 24 __le64 tx_mcast_pkts; 25 __le64 tx_bcast_pkts; 26 __le64 tx_discard_pkts; 27 __le64 tx_drop_pkts; 28 __le64 tx_ucast_bytes; 29 __le64 tx_mcast_bytes; 30 __le64 tx_bcast_bytes; 31 __le64 tpa_pkts; 32 __le64 tpa_bytes; 33 __le64 tpa_events; 34 __le64 tpa_aborts; 35 }; 36 37 /* Statistics Ejection Buffer Completion Record (16 bytes) */ 38 struct eject_cmpl { 39 __le16 type; 40 #define EJECT_CMPL_TYPE_MASK 0x3fUL 41 #define EJECT_CMPL_TYPE_SFT 0 42 #define EJECT_CMPL_TYPE_STAT_EJECT (0x1aUL << 0) 43 __le16 len; 44 __le32 opaque; 45 __le32 v; 46 #define EJECT_CMPL_V 0x1UL 47 __le32 unused_2; 48 }; 49 50 /* HWRM Completion Record (16 bytes) */ 51 struct hwrm_cmpl { 52 __le16 type; 53 #define HWRM_CMPL_TYPE_MASK 0x3fUL 54 #define HWRM_CMPL_TYPE_SFT 0 55 #define HWRM_CMPL_TYPE_HWRM_DONE (0x20UL << 0) 56 __le16 sequence_id; 57 __le32 unused_1; 58 __le32 v; 59 #define HWRM_CMPL_V 0x1UL 60 __le32 unused_3; 61 }; 62 63 /* HWRM Forwarded Request (16 bytes) */ 64 struct hwrm_fwd_req_cmpl { 65 __le16 req_len_type; 66 #define HWRM_FWD_REQ_CMPL_TYPE_MASK 0x3fUL 67 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0 68 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ (0x22UL << 0) 69 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 70 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6 71 __le16 source_id; 72 __le32 unused_0; 73 __le32 req_buf_addr_v[2]; 74 #define HWRM_FWD_REQ_CMPL_V 0x1UL 75 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 76 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 77 }; 78 79 /* HWRM Forwarded Response (16 bytes) */ 80 struct hwrm_fwd_resp_cmpl { 81 __le16 type; 82 #define HWRM_FWD_RESP_CMPL_TYPE_MASK 0x3fUL 83 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0 84 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP (0x24UL << 0) 85 __le16 source_id; 86 __le16 resp_len; 87 __le16 unused_1; 88 __le32 resp_buf_addr_v[2]; 89 #define HWRM_FWD_RESP_CMPL_V 0x1UL 90 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 91 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 92 }; 93 94 /* HWRM Asynchronous Event Completion Record (16 bytes) */ 95 struct hwrm_async_event_cmpl { 96 __le16 type; 97 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 98 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0 99 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 100 __le16 event_id; 101 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE (0x0UL << 0) 102 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE (0x1UL << 0) 103 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE (0x2UL << 0) 104 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE (0x3UL << 0) 105 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED (0x4UL << 0) 106 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED (0x5UL << 0) 107 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE (0x6UL << 0) 108 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD (0x10UL << 0) 109 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD (0x11UL << 0) 110 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD (0x20UL << 0) 111 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD (0x21UL << 0) 112 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR (0x30UL << 0) 113 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE (0x31UL << 0) 114 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE (0x32UL << 0) 115 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE (0x33UL << 0) 116 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR (0xffUL << 0) 117 __le32 event_data2; 118 u8 opaque_v; 119 #define HWRM_ASYNC_EVENT_CMPL_V 0x1UL 120 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 121 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1 122 u8 timestamp_lo; 123 __le16 timestamp_hi; 124 __le32 event_data1; 125 }; 126 127 /* HWRM Asynchronous Event Completion Record for link status change (16 bytes) */ 128 struct hwrm_async_event_cmpl_link_status_change { 129 __le16 type; 130 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 131 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 132 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 133 __le16 event_id; 134 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE (0x0UL << 0) 135 __le32 event_data2; 136 u8 opaque_v; 137 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 138 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 139 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 140 u8 timestamp_lo; 141 __le16 timestamp_hi; 142 __le32 event_data1; 143 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 144 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN (0x0UL << 0) 145 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP (0x1UL << 0) 146 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 147 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 148 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 149 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 150 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 151 }; 152 153 /* HWRM Asynchronous Event Completion Record for link MTU change (16 bytes) */ 154 struct hwrm_async_event_cmpl_link_mtu_change { 155 __le16 type; 156 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK 0x3fUL 157 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0 158 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 159 __le16 event_id; 160 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE (0x1UL << 0) 161 __le32 event_data2; 162 u8 opaque_v; 163 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V 0x1UL 164 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK 0xfeUL 165 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1 166 u8 timestamp_lo; 167 __le16 timestamp_hi; 168 __le32 event_data1; 169 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK 0xffffUL 170 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0 171 }; 172 173 /* HWRM Asynchronous Event Completion Record for link speed change (16 bytes) */ 174 struct hwrm_async_event_cmpl_link_speed_change { 175 __le16 type; 176 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK 0x3fUL 177 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0 178 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 179 __le16 event_id; 180 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE (0x2UL << 0) 181 __le32 event_data2; 182 u8 opaque_v; 183 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V 0x1UL 184 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK 0xfeUL 185 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1 186 u8 timestamp_lo; 187 __le16 timestamp_hi; 188 __le32 event_data1; 189 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE 0x1UL 190 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK 0xfffeUL 191 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT 1 192 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB (0x1UL << 1) 193 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB (0xaUL << 1) 194 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB (0x14UL << 1) 195 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB (0x19UL << 1) 196 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB (0x64UL << 1) 197 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB (0xc8UL << 1) 198 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB (0xfaUL << 1) 199 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB (0x190UL << 1) 200 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB (0x1f4UL << 1) 201 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB (0x3e8UL << 1) 202 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10MB (0xffffUL << 1) 203 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10MB 204 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0000UL 205 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT 16 206 }; 207 208 /* HWRM Asynchronous Event Completion Record for DCB Config change (16 bytes) */ 209 struct hwrm_async_event_cmpl_dcb_config_change { 210 __le16 type; 211 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK 0x3fUL 212 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0 213 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 214 __le16 event_id; 215 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE (0x3UL << 0) 216 __le32 event_data2; 217 u8 opaque_v; 218 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V 0x1UL 219 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK 0xfeUL 220 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1 221 u8 timestamp_lo; 222 __le16 timestamp_hi; 223 __le32 event_data1; 224 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 225 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 226 }; 227 228 /* HWRM Asynchronous Event Completion Record for port connection not allowed (16 bytes) */ 229 struct hwrm_async_event_cmpl_port_conn_not_allowed { 230 __le16 type; 231 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 232 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 233 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 234 __le16 event_id; 235 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED (0x4UL << 0) 236 __le32 event_data2; 237 u8 opaque_v; 238 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 239 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 240 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 241 u8 timestamp_lo; 242 __le16 timestamp_hi; 243 __le32 event_data1; 244 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 245 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 246 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 247 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 248 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 249 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 250 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 251 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 252 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 253 }; 254 255 /* HWRM Asynchronous Event Completion Record for link speed config not allowed (16 bytes) */ 256 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { 257 __le16 type; 258 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK 0x3fUL 259 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT 0 260 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 261 __le16 event_id; 262 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED (0x5UL << 0) 263 __le32 event_data2; 264 u8 opaque_v; 265 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V 0x1UL 266 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 267 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1 268 u8 timestamp_lo; 269 __le16 timestamp_hi; 270 __le32 event_data1; 271 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 272 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 273 }; 274 275 /* HWRM Asynchronous Event Completion Record for link speed configuration change (16 bytes) */ 276 struct hwrm_async_event_cmpl_link_speed_cfg_change { 277 __le16 type; 278 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 279 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 280 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 281 __le16 event_id; 282 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE (0x6UL << 0) 283 __le32 event_data2; 284 u8 opaque_v; 285 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 286 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 287 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 288 u8 timestamp_lo; 289 __le16 timestamp_hi; 290 __le32 event_data1; 291 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 292 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 293 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 294 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 295 }; 296 297 /* HWRM Asynchronous Event Completion Record for Function Driver Unload (16 bytes) */ 298 struct hwrm_async_event_cmpl_func_drvr_unload { 299 __le16 type; 300 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK 0x3fUL 301 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0 302 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 303 __le16 event_id; 304 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD (0x10UL << 0) 305 __le32 event_data2; 306 u8 opaque_v; 307 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V 0x1UL 308 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL 309 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1 310 u8 timestamp_lo; 311 __le16 timestamp_hi; 312 __le32 event_data1; 313 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 314 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 315 }; 316 317 /* HWRM Asynchronous Event Completion Record for Function Driver load (16 bytes) */ 318 struct hwrm_async_event_cmpl_func_drvr_load { 319 __le16 type; 320 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK 0x3fUL 321 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0 322 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 323 __le16 event_id; 324 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD (0x11UL << 0) 325 __le32 event_data2; 326 u8 opaque_v; 327 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V 0x1UL 328 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK 0xfeUL 329 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1 330 u8 timestamp_lo; 331 __le16 timestamp_hi; 332 __le32 event_data1; 333 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 334 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 335 }; 336 337 /* HWRM Asynchronous Event Completion Record for PF Driver Unload (16 bytes) */ 338 struct hwrm_async_event_cmpl_pf_drvr_unload { 339 __le16 type; 340 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK 0x3fUL 341 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0 342 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 343 __le16 event_id; 344 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD (0x20UL << 0) 345 __le32 event_data2; 346 u8 opaque_v; 347 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V 0x1UL 348 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL 349 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1 350 u8 timestamp_lo; 351 __le16 timestamp_hi; 352 __le32 event_data1; 353 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 354 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 355 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK 0x70000UL 356 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16 357 }; 358 359 /* HWRM Asynchronous Event Completion Record for PF Driver load (16 bytes) */ 360 struct hwrm_async_event_cmpl_pf_drvr_load { 361 __le16 type; 362 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK 0x3fUL 363 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0 364 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 365 __le16 event_id; 366 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD (0x21UL << 0) 367 __le32 event_data2; 368 u8 opaque_v; 369 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V 0x1UL 370 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK 0xfeUL 371 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1 372 u8 timestamp_lo; 373 __le16 timestamp_hi; 374 __le32 event_data1; 375 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 376 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 377 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK 0x70000UL 378 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16 379 }; 380 381 /* HWRM Asynchronous Event Completion Record for VF FLR (16 bytes) */ 382 struct hwrm_async_event_cmpl_vf_flr { 383 __le16 type; 384 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK 0x3fUL 385 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0 386 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 387 __le16 event_id; 388 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR (0x30UL << 0) 389 __le32 event_data2; 390 u8 opaque_v; 391 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V 0x1UL 392 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK 0xfeUL 393 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1 394 u8 timestamp_lo; 395 __le16 timestamp_hi; 396 __le32 event_data1; 397 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK 0xffffUL 398 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0 399 }; 400 401 /* HWRM Asynchronous Event Completion Record for VF MAC Addr change (16 bytes) */ 402 struct hwrm_async_event_cmpl_vf_mac_addr_change { 403 __le16 type; 404 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK 0x3fUL 405 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0 406 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 407 __le16 event_id; 408 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE (0x31UL << 0) 409 __le32 event_data2; 410 u8 opaque_v; 411 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V 0x1UL 412 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK 0xfeUL 413 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1 414 u8 timestamp_lo; 415 __le16 timestamp_hi; 416 __le32 event_data1; 417 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK 0xffffUL 418 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0 419 }; 420 421 /* HWRM Asynchronous Event Completion Record for PF-VF communication status change (16 bytes) */ 422 struct hwrm_async_event_cmpl_pf_vf_comm_status_change { 423 __le16 type; 424 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK 0x3fUL 425 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT 0 426 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 427 __le16 event_id; 428 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE (0x32UL << 0) 429 __le32 event_data2; 430 u8 opaque_v; 431 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V 0x1UL 432 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 433 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1 434 u8 timestamp_lo; 435 __le16 timestamp_hi; 436 __le32 event_data1; 437 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED 0x1UL 438 }; 439 440 /* HWRM Asynchronous Event Completion Record for VF configuration change (16 bytes) */ 441 struct hwrm_async_event_cmpl_vf_cfg_change { 442 __le16 type; 443 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 444 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 445 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 446 __le16 event_id; 447 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE (0x33UL << 0) 448 __le32 event_data2; 449 u8 opaque_v; 450 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 451 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 452 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 453 u8 timestamp_lo; 454 __le16 timestamp_hi; 455 __le32 event_data1; 456 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 457 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 458 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 459 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 460 }; 461 462 /* HWRM Asynchronous Event Completion Record for HWRM Error (16 bytes) */ 463 struct hwrm_async_event_cmpl_hwrm_error { 464 __le16 type; 465 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL 466 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 467 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 468 __le16 event_id; 469 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR (0xffUL << 0) 470 __le32 event_data2; 471 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL 472 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 473 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING (0x0UL << 0) 474 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL (0x1UL << 0) 475 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL (0x2UL << 0) 476 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 477 u8 opaque_v; 478 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL 479 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL 480 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 481 u8 timestamp_lo; 482 __le16 timestamp_hi; 483 __le32 event_data1; 484 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL 485 }; 486 487 /* HW Resource Manager Specification 1.2.2 */ 488 #define HWRM_VERSION_MAJOR 1 489 #define HWRM_VERSION_MINOR 2 490 #define HWRM_VERSION_UPDATE 2 491 492 #define HWRM_VERSION_STR "1.2.2" 493 /* 494 * Following is the signature for HWRM message field that indicates not 495 * applicable (All F's). Need to cast it the size of the field if needed. 496 */ 497 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 498 #define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */ 499 #define HWRM_MAX_RESP_LEN (176) /* hwrm_func_qstats */ 500 #define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */ 501 #define HW_HASH_KEY_SIZE 40 502 #define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */ 503 /* Input (16 bytes) */ 504 struct input { 505 __le16 req_type; 506 __le16 cmpl_ring; 507 __le16 seq_id; 508 __le16 target_id; 509 __le64 resp_addr; 510 }; 511 512 /* Output (8 bytes) */ 513 struct output { 514 __le16 error_code; 515 __le16 req_type; 516 __le16 seq_id; 517 __le16 resp_len; 518 }; 519 520 /* Command numbering (8 bytes) */ 521 struct cmd_nums { 522 __le16 req_type; 523 #define HWRM_VER_GET (0x0UL) 524 #define HWRM_FUNC_BUF_UNRGTR (0xeUL) 525 #define HWRM_FUNC_VF_CFG (0xfUL) 526 #define RESERVED1 (0x10UL) 527 #define HWRM_FUNC_RESET (0x11UL) 528 #define HWRM_FUNC_GETFID (0x12UL) 529 #define HWRM_FUNC_VF_ALLOC (0x13UL) 530 #define HWRM_FUNC_VF_FREE (0x14UL) 531 #define HWRM_FUNC_QCAPS (0x15UL) 532 #define HWRM_FUNC_QCFG (0x16UL) 533 #define HWRM_FUNC_CFG (0x17UL) 534 #define HWRM_FUNC_QSTATS (0x18UL) 535 #define HWRM_FUNC_CLR_STATS (0x19UL) 536 #define HWRM_FUNC_DRV_UNRGTR (0x1aUL) 537 #define HWRM_FUNC_VF_RESC_FREE (0x1bUL) 538 #define HWRM_FUNC_VF_VNIC_IDS_QUERY (0x1cUL) 539 #define HWRM_FUNC_DRV_RGTR (0x1dUL) 540 #define HWRM_FUNC_DRV_QVER (0x1eUL) 541 #define HWRM_FUNC_BUF_RGTR (0x1fUL) 542 #define HWRM_PORT_PHY_CFG (0x20UL) 543 #define HWRM_PORT_MAC_CFG (0x21UL) 544 #define HWRM_PORT_TS_QUERY (0x22UL) 545 #define HWRM_PORT_QSTATS (0x23UL) 546 #define HWRM_PORT_LPBK_QSTATS (0x24UL) 547 #define HWRM_PORT_CLR_STATS (0x25UL) 548 #define HWRM_PORT_LPBK_CLR_STATS (0x26UL) 549 #define HWRM_PORT_PHY_QCFG (0x27UL) 550 #define HWRM_PORT_MAC_QCFG (0x28UL) 551 #define HWRM_PORT_BLINK_LED (0x29UL) 552 #define HWRM_PORT_PHY_QCAPS (0x2aUL) 553 #define HWRM_PORT_PHY_I2C_WRITE (0x2bUL) 554 #define HWRM_PORT_PHY_I2C_READ (0x2cUL) 555 #define HWRM_QUEUE_QPORTCFG (0x30UL) 556 #define HWRM_QUEUE_QCFG (0x31UL) 557 #define HWRM_QUEUE_CFG (0x32UL) 558 #define HWRM_QUEUE_BUFFERS_QCFG (0x33UL) 559 #define HWRM_QUEUE_BUFFERS_CFG (0x34UL) 560 #define HWRM_QUEUE_PFCENABLE_QCFG (0x35UL) 561 #define HWRM_QUEUE_PFCENABLE_CFG (0x36UL) 562 #define HWRM_QUEUE_PRI2COS_QCFG (0x37UL) 563 #define HWRM_QUEUE_PRI2COS_CFG (0x38UL) 564 #define HWRM_QUEUE_COS2BW_QCFG (0x39UL) 565 #define HWRM_QUEUE_COS2BW_CFG (0x3aUL) 566 #define HWRM_VNIC_ALLOC (0x40UL) 567 #define HWRM_VNIC_FREE (0x41UL) 568 #define HWRM_VNIC_CFG (0x42UL) 569 #define HWRM_VNIC_QCFG (0x43UL) 570 #define HWRM_VNIC_TPA_CFG (0x44UL) 571 #define HWRM_VNIC_TPA_QCFG (0x45UL) 572 #define HWRM_VNIC_RSS_CFG (0x46UL) 573 #define HWRM_VNIC_RSS_QCFG (0x47UL) 574 #define HWRM_VNIC_PLCMODES_CFG (0x48UL) 575 #define HWRM_VNIC_PLCMODES_QCFG (0x49UL) 576 #define HWRM_RING_ALLOC (0x50UL) 577 #define HWRM_RING_FREE (0x51UL) 578 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS (0x52UL) 579 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS (0x53UL) 580 #define HWRM_RING_RESET (0x5eUL) 581 #define HWRM_RING_GRP_ALLOC (0x60UL) 582 #define HWRM_RING_GRP_FREE (0x61UL) 583 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (0x70UL) 584 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE (0x71UL) 585 #define HWRM_CFA_L2_FILTER_ALLOC (0x90UL) 586 #define HWRM_CFA_L2_FILTER_FREE (0x91UL) 587 #define HWRM_CFA_L2_FILTER_CFG (0x92UL) 588 #define HWRM_CFA_L2_SET_RX_MASK (0x93UL) 589 #define RESERVED3 (0x94UL) 590 #define HWRM_CFA_TUNNEL_FILTER_ALLOC (0x95UL) 591 #define HWRM_CFA_TUNNEL_FILTER_FREE (0x96UL) 592 #define HWRM_CFA_ENCAP_RECORD_ALLOC (0x97UL) 593 #define HWRM_CFA_ENCAP_RECORD_FREE (0x98UL) 594 #define HWRM_CFA_NTUPLE_FILTER_ALLOC (0x99UL) 595 #define HWRM_CFA_NTUPLE_FILTER_FREE (0x9aUL) 596 #define HWRM_CFA_NTUPLE_FILTER_CFG (0x9bUL) 597 #define HWRM_CFA_EM_FLOW_ALLOC (0x9cUL) 598 #define HWRM_CFA_EM_FLOW_FREE (0x9dUL) 599 #define HWRM_CFA_EM_FLOW_CFG (0x9eUL) 600 #define HWRM_TUNNEL_DST_PORT_QUERY (0xa0UL) 601 #define HWRM_TUNNEL_DST_PORT_ALLOC (0xa1UL) 602 #define HWRM_TUNNEL_DST_PORT_FREE (0xa2UL) 603 #define HWRM_STAT_CTX_ALLOC (0xb0UL) 604 #define HWRM_STAT_CTX_FREE (0xb1UL) 605 #define HWRM_STAT_CTX_QUERY (0xb2UL) 606 #define HWRM_STAT_CTX_CLR_STATS (0xb3UL) 607 #define HWRM_FW_RESET (0xc0UL) 608 #define HWRM_FW_QSTATUS (0xc1UL) 609 #define HWRM_EXEC_FWD_RESP (0xd0UL) 610 #define HWRM_REJECT_FWD_RESP (0xd1UL) 611 #define HWRM_FWD_RESP (0xd2UL) 612 #define HWRM_FWD_ASYNC_EVENT_CMPL (0xd3UL) 613 #define HWRM_TEMP_MONITOR_QUERY (0xe0UL) 614 #define HWRM_DBG_READ_DIRECT (0xff10UL) 615 #define HWRM_DBG_READ_INDIRECT (0xff11UL) 616 #define HWRM_DBG_WRITE_DIRECT (0xff12UL) 617 #define HWRM_DBG_WRITE_INDIRECT (0xff13UL) 618 #define HWRM_DBG_DUMP (0xff14UL) 619 #define HWRM_NVM_MODIFY (0xfff4UL) 620 #define HWRM_NVM_VERIFY_UPDATE (0xfff5UL) 621 #define HWRM_NVM_GET_DEV_INFO (0xfff6UL) 622 #define HWRM_NVM_ERASE_DIR_ENTRY (0xfff7UL) 623 #define HWRM_NVM_MOD_DIR_ENTRY (0xfff8UL) 624 #define HWRM_NVM_FIND_DIR_ENTRY (0xfff9UL) 625 #define HWRM_NVM_GET_DIR_ENTRIES (0xfffaUL) 626 #define HWRM_NVM_GET_DIR_INFO (0xfffbUL) 627 #define HWRM_NVM_RAW_DUMP (0xfffcUL) 628 #define HWRM_NVM_READ (0xfffdUL) 629 #define HWRM_NVM_WRITE (0xfffeUL) 630 #define HWRM_NVM_RAW_WRITE_BLK (0xffffUL) 631 __le16 unused_0[3]; 632 }; 633 634 /* Return Codes (8 bytes) */ 635 struct ret_codes { 636 __le16 error_code; 637 #define HWRM_ERR_CODE_SUCCESS (0x0UL) 638 #define HWRM_ERR_CODE_FAIL (0x1UL) 639 #define HWRM_ERR_CODE_INVALID_PARAMS (0x2UL) 640 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (0x3UL) 641 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR (0x4UL) 642 #define HWRM_ERR_CODE_INVALID_FLAGS (0x5UL) 643 #define HWRM_ERR_CODE_INVALID_ENABLES (0x6UL) 644 #define HWRM_ERR_CODE_HWRM_ERROR (0xfUL) 645 #define HWRM_ERR_CODE_UNKNOWN_ERR (0xfffeUL) 646 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED (0xffffUL) 647 __le16 unused_0[3]; 648 }; 649 650 /* Output (16 bytes) */ 651 struct hwrm_err_output { 652 __le16 error_code; 653 __le16 req_type; 654 __le16 seq_id; 655 __le16 resp_len; 656 __le32 opaque_0; 657 __le16 opaque_1; 658 u8 cmd_err; 659 u8 valid; 660 }; 661 662 /* Port Tx Statistics Formats (408 bytes) */ 663 struct tx_port_stats { 664 __le64 tx_64b_frames; 665 __le64 tx_65b_127b_frames; 666 __le64 tx_128b_255b_frames; 667 __le64 tx_256b_511b_frames; 668 __le64 tx_512b_1023b_frames; 669 __le64 tx_1024b_1518_frames; 670 __le64 tx_good_vlan_frames; 671 __le64 tx_1519b_2047_frames; 672 __le64 tx_2048b_4095b_frames; 673 __le64 tx_4096b_9216b_frames; 674 __le64 tx_9217b_16383b_frames; 675 __le64 tx_good_frames; 676 __le64 tx_total_frames; 677 __le64 tx_ucast_frames; 678 __le64 tx_mcast_frames; 679 __le64 tx_bcast_frames; 680 __le64 tx_pause_frames; 681 __le64 tx_pfc_frames; 682 __le64 tx_jabber_frames; 683 __le64 tx_fcs_err_frames; 684 __le64 tx_control_frames; 685 __le64 tx_oversz_frames; 686 __le64 tx_single_dfrl_frames; 687 __le64 tx_multi_dfrl_frames; 688 __le64 tx_single_coll_frames; 689 __le64 tx_multi_coll_frames; 690 __le64 tx_late_coll_frames; 691 __le64 tx_excessive_coll_frames; 692 __le64 tx_frag_frames; 693 __le64 tx_err; 694 __le64 tx_tagged_frames; 695 __le64 tx_dbl_tagged_frames; 696 __le64 tx_runt_frames; 697 __le64 tx_fifo_underruns; 698 __le64 tx_pfc_ena_frames_pri0; 699 __le64 tx_pfc_ena_frames_pri1; 700 __le64 tx_pfc_ena_frames_pri2; 701 __le64 tx_pfc_ena_frames_pri3; 702 __le64 tx_pfc_ena_frames_pri4; 703 __le64 tx_pfc_ena_frames_pri5; 704 __le64 tx_pfc_ena_frames_pri6; 705 __le64 tx_pfc_ena_frames_pri7; 706 __le64 tx_eee_lpi_events; 707 __le64 tx_eee_lpi_duration; 708 __le64 tx_llfc_logical_msgs; 709 __le64 tx_hcfc_msgs; 710 __le64 tx_total_collisions; 711 __le64 tx_bytes; 712 __le64 tx_xthol_frames; 713 __le64 tx_stat_discard; 714 __le64 tx_stat_error; 715 }; 716 717 /* Port Rx Statistics Formats (528 bytes) */ 718 struct rx_port_stats { 719 __le64 rx_64b_frames; 720 __le64 rx_65b_127b_frames; 721 __le64 rx_128b_255b_frames; 722 __le64 rx_256b_511b_frames; 723 __le64 rx_512b_1023b_frames; 724 __le64 rx_1024b_1518_frames; 725 __le64 rx_good_vlan_frames; 726 __le64 rx_1519b_2047b_frames; 727 __le64 rx_2048b_4095b_frames; 728 __le64 rx_4096b_9216b_frames; 729 __le64 rx_9217b_16383b_frames; 730 __le64 rx_total_frames; 731 __le64 rx_ucast_frames; 732 __le64 rx_mcast_frames; 733 __le64 rx_bcast_frames; 734 __le64 rx_fcs_err_frames; 735 __le64 rx_ctrl_frames; 736 __le64 rx_pause_frames; 737 __le64 rx_pfc_frames; 738 __le64 rx_unsupported_opcode_frames; 739 __le64 rx_unsupported_da_pausepfc_frames; 740 __le64 rx_wrong_sa_frames; 741 __le64 rx_align_err_frames; 742 __le64 rx_oor_len_frames; 743 __le64 rx_code_err_frames; 744 __le64 rx_false_carrier_frames; 745 __le64 rx_ovrsz_frames; 746 __le64 rx_jbr_frames; 747 __le64 rx_mtu_err_frames; 748 __le64 rx_match_crc_frames; 749 __le64 rx_promiscuous_frames; 750 __le64 rx_tagged_frames; 751 __le64 rx_double_tagged_frames; 752 __le64 rx_trunc_frames; 753 __le64 rx_good_frames; 754 __le64 rx_pfc_xon2xoff_frames_pri0; 755 __le64 rx_pfc_xon2xoff_frames_pri1; 756 __le64 rx_pfc_xon2xoff_frames_pri2; 757 __le64 rx_pfc_xon2xoff_frames_pri3; 758 __le64 rx_pfc_xon2xoff_frames_pri4; 759 __le64 rx_pfc_xon2xoff_frames_pri5; 760 __le64 rx_pfc_xon2xoff_frames_pri6; 761 __le64 rx_pfc_xon2xoff_frames_pri7; 762 __le64 rx_pfc_ena_frames_pri0; 763 __le64 rx_pfc_ena_frames_pri1; 764 __le64 rx_pfc_ena_frames_pri2; 765 __le64 rx_pfc_ena_frames_pri3; 766 __le64 rx_pfc_ena_frames_pri4; 767 __le64 rx_pfc_ena_frames_pri5; 768 __le64 rx_pfc_ena_frames_pri6; 769 __le64 rx_pfc_ena_frames_pri7; 770 __le64 rx_sch_crc_err_frames; 771 __le64 rx_undrsz_frames; 772 __le64 rx_frag_frames; 773 __le64 rx_eee_lpi_events; 774 __le64 rx_eee_lpi_duration; 775 __le64 rx_llfc_physical_msgs; 776 __le64 rx_llfc_logical_msgs; 777 __le64 rx_llfc_msgs_with_crc_err; 778 __le64 rx_hcfc_msgs; 779 __le64 rx_hcfc_msgs_with_crc_err; 780 __le64 rx_bytes; 781 __le64 rx_runt_bytes; 782 __le64 rx_runt_frames; 783 __le64 rx_stat_discard; 784 __le64 rx_stat_err; 785 }; 786 787 /* hwrm_ver_get */ 788 /* Input (24 bytes) */ 789 struct hwrm_ver_get_input { 790 __le16 req_type; 791 __le16 cmpl_ring; 792 __le16 seq_id; 793 __le16 target_id; 794 __le64 resp_addr; 795 u8 hwrm_intf_maj; 796 u8 hwrm_intf_min; 797 u8 hwrm_intf_upd; 798 u8 unused_0[5]; 799 }; 800 801 /* Output (128 bytes) */ 802 struct hwrm_ver_get_output { 803 __le16 error_code; 804 __le16 req_type; 805 __le16 seq_id; 806 __le16 resp_len; 807 u8 hwrm_intf_maj; 808 u8 hwrm_intf_min; 809 u8 hwrm_intf_upd; 810 u8 hwrm_intf_rsvd; 811 u8 hwrm_fw_maj; 812 u8 hwrm_fw_min; 813 u8 hwrm_fw_bld; 814 u8 hwrm_fw_rsvd; 815 u8 mgmt_fw_maj; 816 u8 mgmt_fw_min; 817 u8 mgmt_fw_bld; 818 u8 mgmt_fw_rsvd; 819 u8 netctrl_fw_maj; 820 u8 netctrl_fw_min; 821 u8 netctrl_fw_bld; 822 u8 netctrl_fw_rsvd; 823 __le32 reserved1; 824 u8 roce_fw_maj; 825 u8 roce_fw_min; 826 u8 roce_fw_bld; 827 u8 roce_fw_rsvd; 828 char hwrm_fw_name[16]; 829 char mgmt_fw_name[16]; 830 char netctrl_fw_name[16]; 831 __le32 reserved2[4]; 832 char roce_fw_name[16]; 833 __le16 chip_num; 834 u8 chip_rev; 835 u8 chip_metal; 836 u8 chip_bond_id; 837 u8 chip_platform_type; 838 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC (0x0UL << 0) 839 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA (0x1UL << 0) 840 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM (0x2UL << 0) 841 __le16 max_req_win_len; 842 __le16 max_resp_len; 843 __le16 def_req_timeout; 844 u8 unused_0; 845 u8 unused_1; 846 u8 unused_2; 847 u8 valid; 848 }; 849 850 /* hwrm_func_reset */ 851 /* Input (24 bytes) */ 852 struct hwrm_func_reset_input { 853 __le16 req_type; 854 __le16 cmpl_ring; 855 __le16 seq_id; 856 __le16 target_id; 857 __le64 resp_addr; 858 __le32 enables; 859 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 860 __le16 vf_id; 861 u8 func_reset_level; 862 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL (0x0UL << 0) 863 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME (0x1UL << 0) 864 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN (0x2UL << 0) 865 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF (0x3UL << 0) 866 u8 unused_0; 867 }; 868 869 /* Output (16 bytes) */ 870 struct hwrm_func_reset_output { 871 __le16 error_code; 872 __le16 req_type; 873 __le16 seq_id; 874 __le16 resp_len; 875 __le32 unused_0; 876 u8 unused_1; 877 u8 unused_2; 878 u8 unused_3; 879 u8 valid; 880 }; 881 882 /* hwrm_func_getfid */ 883 /* Input (24 bytes) */ 884 struct hwrm_func_getfid_input { 885 __le16 req_type; 886 __le16 cmpl_ring; 887 __le16 seq_id; 888 __le16 target_id; 889 __le64 resp_addr; 890 __le32 enables; 891 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 892 __le16 pci_id; 893 __le16 unused_0; 894 }; 895 896 /* Output (16 bytes) */ 897 struct hwrm_func_getfid_output { 898 __le16 error_code; 899 __le16 req_type; 900 __le16 seq_id; 901 __le16 resp_len; 902 __le16 fid; 903 u8 unused_0; 904 u8 unused_1; 905 u8 unused_2; 906 u8 unused_3; 907 u8 unused_4; 908 u8 valid; 909 }; 910 911 /* hwrm_func_vf_alloc */ 912 /* Input (24 bytes) */ 913 struct hwrm_func_vf_alloc_input { 914 __le16 req_type; 915 __le16 cmpl_ring; 916 __le16 seq_id; 917 __le16 target_id; 918 __le64 resp_addr; 919 __le32 enables; 920 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 921 __le16 first_vf_id; 922 __le16 num_vfs; 923 }; 924 925 /* Output (16 bytes) */ 926 struct hwrm_func_vf_alloc_output { 927 __le16 error_code; 928 __le16 req_type; 929 __le16 seq_id; 930 __le16 resp_len; 931 __le16 first_vf_id; 932 u8 unused_0; 933 u8 unused_1; 934 u8 unused_2; 935 u8 unused_3; 936 u8 unused_4; 937 u8 valid; 938 }; 939 940 /* hwrm_func_vf_free */ 941 /* Input (24 bytes) */ 942 struct hwrm_func_vf_free_input { 943 __le16 req_type; 944 __le16 cmpl_ring; 945 __le16 seq_id; 946 __le16 target_id; 947 __le64 resp_addr; 948 __le32 enables; 949 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 950 __le16 first_vf_id; 951 __le16 num_vfs; 952 }; 953 954 /* Output (16 bytes) */ 955 struct hwrm_func_vf_free_output { 956 __le16 error_code; 957 __le16 req_type; 958 __le16 seq_id; 959 __le16 resp_len; 960 __le32 unused_0; 961 u8 unused_1; 962 u8 unused_2; 963 u8 unused_3; 964 u8 valid; 965 }; 966 967 /* hwrm_func_vf_cfg */ 968 /* Input (32 bytes) */ 969 struct hwrm_func_vf_cfg_input { 970 __le16 req_type; 971 __le16 cmpl_ring; 972 __le16 seq_id; 973 __le16 target_id; 974 __le64 resp_addr; 975 __le32 enables; 976 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 977 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 978 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 979 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 980 __le16 mtu; 981 __le16 guest_vlan; 982 __le16 async_event_cr; 983 u8 dflt_mac_addr[6]; 984 }; 985 986 /* Output (16 bytes) */ 987 struct hwrm_func_vf_cfg_output { 988 __le16 error_code; 989 __le16 req_type; 990 __le16 seq_id; 991 __le16 resp_len; 992 __le32 unused_0; 993 u8 unused_1; 994 u8 unused_2; 995 u8 unused_3; 996 u8 valid; 997 }; 998 999 /* hwrm_func_qcaps */ 1000 /* Input (24 bytes) */ 1001 struct hwrm_func_qcaps_input { 1002 __le16 req_type; 1003 __le16 cmpl_ring; 1004 __le16 seq_id; 1005 __le16 target_id; 1006 __le64 resp_addr; 1007 __le16 fid; 1008 __le16 unused_0[3]; 1009 }; 1010 1011 /* Output (80 bytes) */ 1012 struct hwrm_func_qcaps_output { 1013 __le16 error_code; 1014 __le16 req_type; 1015 __le16 seq_id; 1016 __le16 resp_len; 1017 __le16 fid; 1018 __le16 port_id; 1019 __le32 flags; 1020 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1021 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 1022 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1023 u8 mac_address[6]; 1024 __le16 max_rsscos_ctx; 1025 __le16 max_cmpl_rings; 1026 __le16 max_tx_rings; 1027 __le16 max_rx_rings; 1028 __le16 max_l2_ctxs; 1029 __le16 max_vnics; 1030 __le16 first_vf_id; 1031 __le16 max_vfs; 1032 __le16 max_stat_ctx; 1033 __le32 max_encap_records; 1034 __le32 max_decap_records; 1035 __le32 max_tx_em_flows; 1036 __le32 max_tx_wm_flows; 1037 __le32 max_rx_em_flows; 1038 __le32 max_rx_wm_flows; 1039 __le32 max_mcast_filters; 1040 __le32 max_flow_id; 1041 __le32 max_hw_ring_grps; 1042 u8 unused_0; 1043 u8 unused_1; 1044 u8 unused_2; 1045 u8 valid; 1046 }; 1047 1048 /* hwrm_func_qcfg */ 1049 /* Input (24 bytes) */ 1050 struct hwrm_func_qcfg_input { 1051 __le16 req_type; 1052 __le16 cmpl_ring; 1053 __le16 seq_id; 1054 __le16 target_id; 1055 __le64 resp_addr; 1056 __le16 fid; 1057 __le16 unused_0[3]; 1058 }; 1059 1060 /* Output (72 bytes) */ 1061 struct hwrm_func_qcfg_output { 1062 __le16 error_code; 1063 __le16 req_type; 1064 __le16 seq_id; 1065 __le16 resp_len; 1066 __le16 fid; 1067 __le16 port_id; 1068 __le16 vlan; 1069 u8 unused_0; 1070 u8 unused_1; 1071 u8 mac_address[6]; 1072 __le16 pci_id; 1073 __le16 alloc_rsscos_ctx; 1074 __le16 alloc_cmpl_rings; 1075 __le16 alloc_tx_rings; 1076 __le16 alloc_rx_rings; 1077 __le16 alloc_l2_ctx; 1078 __le16 alloc_vnics; 1079 __le16 mtu; 1080 __le16 mru; 1081 __le16 stat_ctx_id; 1082 u8 port_partition_type; 1083 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF (0x0UL << 0) 1084 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS (0x1UL << 0) 1085 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 (0x2UL << 0) 1086 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 (0x3UL << 0) 1087 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 (0x4UL << 0) 1088 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN (0xffUL << 0) 1089 u8 unused_2; 1090 __le16 dflt_vnic_id; 1091 u8 unused_3; 1092 u8 unused_4; 1093 __le32 min_bw; 1094 __le32 max_bw; 1095 u8 evb_mode; 1096 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB (0x0UL << 0) 1097 #define FUNC_QCFG_RESP_EVB_MODE_VEB (0x1UL << 0) 1098 #define FUNC_QCFG_RESP_EVB_MODE_VEPA (0x2UL << 0) 1099 u8 unused_5; 1100 __le16 unused_6; 1101 __le32 alloc_mcast_filters; 1102 __le32 alloc_hw_ring_grps; 1103 u8 unused_7; 1104 u8 unused_8; 1105 u8 unused_9; 1106 u8 valid; 1107 }; 1108 1109 /* hwrm_func_cfg */ 1110 /* Input (88 bytes) */ 1111 struct hwrm_func_cfg_input { 1112 __le16 req_type; 1113 __le16 cmpl_ring; 1114 __le16 seq_id; 1115 __le16 target_id; 1116 __le64 resp_addr; 1117 __le16 fid; 1118 u8 unused_0; 1119 u8 unused_1; 1120 __le32 flags; 1121 #define FUNC_CFG_REQ_FLAGS_PROM_MODE 0x1UL 1122 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK 0x2UL 1123 #define FUNC_CFG_REQ_FLAGS_SRC_IP_ADDR_CHECK 0x4UL 1124 #define FUNC_CFG_REQ_FLAGS_VLAN_PRI_MATCH 0x8UL 1125 #define FUNC_CFG_REQ_FLAGS_DFLT_PRI_NOMATCH 0x10UL 1126 #define FUNC_CFG_REQ_FLAGS_DISABLE_PAUSE 0x20UL 1127 #define FUNC_CFG_REQ_FLAGS_DISABLE_STP 0x40UL 1128 #define FUNC_CFG_REQ_FLAGS_DISABLE_LLDP 0x80UL 1129 #define FUNC_CFG_REQ_FLAGS_DISABLE_PTPV2 0x100UL 1130 __le32 enables; 1131 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 1132 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1133 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1134 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1135 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1136 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1137 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1138 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1139 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1140 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1141 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1142 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1143 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1144 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1145 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1146 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1147 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1148 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1149 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1150 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1151 __le16 mtu; 1152 __le16 mru; 1153 __le16 num_rsscos_ctxs; 1154 __le16 num_cmpl_rings; 1155 __le16 num_tx_rings; 1156 __le16 num_rx_rings; 1157 __le16 num_l2_ctxs; 1158 __le16 num_vnics; 1159 __le16 num_stat_ctxs; 1160 __le16 num_hw_ring_grps; 1161 u8 dflt_mac_addr[6]; 1162 __le16 dflt_vlan; 1163 __be32 dflt_ip_addr[4]; 1164 __le32 min_bw; 1165 __le32 max_bw; 1166 __le16 async_event_cr; 1167 u8 vlan_antispoof_mode; 1168 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK (0x0UL << 0) 1169 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN (0x1UL << 0) 1170 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE (0x2UL << 0) 1171 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN (0x3UL << 0) 1172 u8 allowed_vlan_pris; 1173 u8 evb_mode; 1174 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB (0x0UL << 0) 1175 #define FUNC_CFG_REQ_EVB_MODE_VEB (0x1UL << 0) 1176 #define FUNC_CFG_REQ_EVB_MODE_VEPA (0x2UL << 0) 1177 u8 unused_2; 1178 __le16 num_mcast_filters; 1179 }; 1180 1181 /* Output (16 bytes) */ 1182 struct hwrm_func_cfg_output { 1183 __le16 error_code; 1184 __le16 req_type; 1185 __le16 seq_id; 1186 __le16 resp_len; 1187 __le32 unused_0; 1188 u8 unused_1; 1189 u8 unused_2; 1190 u8 unused_3; 1191 u8 valid; 1192 }; 1193 1194 /* hwrm_func_qstats */ 1195 /* Input (24 bytes) */ 1196 struct hwrm_func_qstats_input { 1197 __le16 req_type; 1198 __le16 cmpl_ring; 1199 __le16 seq_id; 1200 __le16 target_id; 1201 __le64 resp_addr; 1202 __le16 fid; 1203 __le16 unused_0[3]; 1204 }; 1205 1206 /* Output (176 bytes) */ 1207 struct hwrm_func_qstats_output { 1208 __le16 error_code; 1209 __le16 req_type; 1210 __le16 seq_id; 1211 __le16 resp_len; 1212 __le64 tx_ucast_pkts; 1213 __le64 tx_mcast_pkts; 1214 __le64 tx_bcast_pkts; 1215 __le64 tx_err_pkts; 1216 __le64 tx_drop_pkts; 1217 __le64 tx_ucast_bytes; 1218 __le64 tx_mcast_bytes; 1219 __le64 tx_bcast_bytes; 1220 __le64 rx_ucast_pkts; 1221 __le64 rx_mcast_pkts; 1222 __le64 rx_bcast_pkts; 1223 __le64 rx_err_pkts; 1224 __le64 rx_drop_pkts; 1225 __le64 rx_ucast_bytes; 1226 __le64 rx_mcast_bytes; 1227 __le64 rx_bcast_bytes; 1228 __le64 rx_agg_pkts; 1229 __le64 rx_agg_bytes; 1230 __le64 rx_agg_events; 1231 __le64 rx_agg_aborts; 1232 __le32 unused_0; 1233 u8 unused_1; 1234 u8 unused_2; 1235 u8 unused_3; 1236 u8 valid; 1237 }; 1238 1239 /* hwrm_func_clr_stats */ 1240 /* Input (24 bytes) */ 1241 struct hwrm_func_clr_stats_input { 1242 __le16 req_type; 1243 __le16 cmpl_ring; 1244 __le16 seq_id; 1245 __le16 target_id; 1246 __le64 resp_addr; 1247 __le16 fid; 1248 __le16 unused_0[3]; 1249 }; 1250 1251 /* Output (16 bytes) */ 1252 struct hwrm_func_clr_stats_output { 1253 __le16 error_code; 1254 __le16 req_type; 1255 __le16 seq_id; 1256 __le16 resp_len; 1257 __le32 unused_0; 1258 u8 unused_1; 1259 u8 unused_2; 1260 u8 unused_3; 1261 u8 valid; 1262 }; 1263 1264 /* hwrm_func_vf_resc_free */ 1265 /* Input (24 bytes) */ 1266 struct hwrm_func_vf_resc_free_input { 1267 __le16 req_type; 1268 __le16 cmpl_ring; 1269 __le16 seq_id; 1270 __le16 target_id; 1271 __le64 resp_addr; 1272 __le16 vf_id; 1273 __le16 unused_0[3]; 1274 }; 1275 1276 /* Output (16 bytes) */ 1277 struct hwrm_func_vf_resc_free_output { 1278 __le16 error_code; 1279 __le16 req_type; 1280 __le16 seq_id; 1281 __le16 resp_len; 1282 __le32 unused_0; 1283 u8 unused_1; 1284 u8 unused_2; 1285 u8 unused_3; 1286 u8 valid; 1287 }; 1288 1289 /* hwrm_func_vf_vnic_ids_query */ 1290 /* Input (32 bytes) */ 1291 struct hwrm_func_vf_vnic_ids_query_input { 1292 __le16 req_type; 1293 __le16 cmpl_ring; 1294 __le16 seq_id; 1295 __le16 target_id; 1296 __le64 resp_addr; 1297 __le16 vf_id; 1298 u8 unused_0; 1299 u8 unused_1; 1300 __le32 max_vnic_id_cnt; 1301 __le64 vnic_id_tbl_addr; 1302 }; 1303 1304 /* Output (16 bytes) */ 1305 struct hwrm_func_vf_vnic_ids_query_output { 1306 __le16 error_code; 1307 __le16 req_type; 1308 __le16 seq_id; 1309 __le16 resp_len; 1310 __le32 vnic_id_cnt; 1311 u8 unused_0; 1312 u8 unused_1; 1313 u8 unused_2; 1314 u8 valid; 1315 }; 1316 1317 /* hwrm_func_drv_rgtr */ 1318 /* Input (80 bytes) */ 1319 struct hwrm_func_drv_rgtr_input { 1320 __le16 req_type; 1321 __le16 cmpl_ring; 1322 __le16 seq_id; 1323 __le16 target_id; 1324 __le64 resp_addr; 1325 __le32 flags; 1326 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1327 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1328 __le32 enables; 1329 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1330 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1331 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1332 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1333 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1334 __le16 os_type; 1335 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN (0x0UL << 0) 1336 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER (0x1UL << 0) 1337 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS (0xeUL << 0) 1338 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS (0x12UL << 0) 1339 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS (0x1dUL << 0) 1340 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX (0x24UL << 0) 1341 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD (0x2aUL << 0) 1342 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI (0x68UL << 0) 1343 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 (0x73UL << 0) 1344 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 (0x74UL << 0) 1345 u8 ver_maj; 1346 u8 ver_min; 1347 u8 ver_upd; 1348 u8 unused_0; 1349 __le16 unused_1; 1350 __le32 timestamp; 1351 __le32 unused_2; 1352 __le32 vf_req_fwd[8]; 1353 __le32 async_event_fwd[8]; 1354 }; 1355 1356 /* Output (16 bytes) */ 1357 struct hwrm_func_drv_rgtr_output { 1358 __le16 error_code; 1359 __le16 req_type; 1360 __le16 seq_id; 1361 __le16 resp_len; 1362 __le32 unused_0; 1363 u8 unused_1; 1364 u8 unused_2; 1365 u8 unused_3; 1366 u8 valid; 1367 }; 1368 1369 /* hwrm_func_drv_unrgtr */ 1370 /* Input (24 bytes) */ 1371 struct hwrm_func_drv_unrgtr_input { 1372 __le16 req_type; 1373 __le16 cmpl_ring; 1374 __le16 seq_id; 1375 __le16 target_id; 1376 __le64 resp_addr; 1377 __le32 flags; 1378 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1379 __le32 unused_0; 1380 }; 1381 1382 /* Output (16 bytes) */ 1383 struct hwrm_func_drv_unrgtr_output { 1384 __le16 error_code; 1385 __le16 req_type; 1386 __le16 seq_id; 1387 __le16 resp_len; 1388 __le32 unused_0; 1389 u8 unused_1; 1390 u8 unused_2; 1391 u8 unused_3; 1392 u8 valid; 1393 }; 1394 1395 /* hwrm_func_buf_rgtr */ 1396 /* Input (128 bytes) */ 1397 struct hwrm_func_buf_rgtr_input { 1398 __le16 req_type; 1399 __le16 cmpl_ring; 1400 __le16 seq_id; 1401 __le16 target_id; 1402 __le64 resp_addr; 1403 __le32 enables; 1404 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1405 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1406 __le16 vf_id; 1407 __le16 req_buf_num_pages; 1408 __le16 req_buf_page_size; 1409 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B (0x4UL << 0) 1410 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K (0xcUL << 0) 1411 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K (0xdUL << 0) 1412 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K (0x10UL << 0) 1413 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M (0x16UL << 0) 1414 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M (0x17UL << 0) 1415 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G (0x1eUL << 0) 1416 __le16 req_buf_len; 1417 __le16 resp_buf_len; 1418 u8 unused_0; 1419 u8 unused_1; 1420 __le64 req_buf_page_addr0; 1421 __le64 req_buf_page_addr1; 1422 __le64 req_buf_page_addr2; 1423 __le64 req_buf_page_addr3; 1424 __le64 req_buf_page_addr4; 1425 __le64 req_buf_page_addr5; 1426 __le64 req_buf_page_addr6; 1427 __le64 req_buf_page_addr7; 1428 __le64 req_buf_page_addr8; 1429 __le64 req_buf_page_addr9; 1430 __le64 error_buf_addr; 1431 __le64 resp_buf_addr; 1432 }; 1433 1434 /* Output (16 bytes) */ 1435 struct hwrm_func_buf_rgtr_output { 1436 __le16 error_code; 1437 __le16 req_type; 1438 __le16 seq_id; 1439 __le16 resp_len; 1440 __le32 unused_0; 1441 u8 unused_1; 1442 u8 unused_2; 1443 u8 unused_3; 1444 u8 valid; 1445 }; 1446 1447 /* hwrm_func_drv_qver */ 1448 /* Input (24 bytes) */ 1449 struct hwrm_func_drv_qver_input { 1450 __le16 req_type; 1451 __le16 cmpl_ring; 1452 __le16 seq_id; 1453 __le16 target_id; 1454 __le64 resp_addr; 1455 __le32 reserved; 1456 __le16 fid; 1457 __le16 unused_0; 1458 }; 1459 1460 /* Output (16 bytes) */ 1461 struct hwrm_func_drv_qver_output { 1462 __le16 error_code; 1463 __le16 req_type; 1464 __le16 seq_id; 1465 __le16 resp_len; 1466 __le16 os_type; 1467 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN (0x0UL << 0) 1468 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER (0x1UL << 0) 1469 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS (0xeUL << 0) 1470 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS (0x12UL << 0) 1471 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS (0x1dUL << 0) 1472 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX (0x24UL << 0) 1473 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD (0x2aUL << 0) 1474 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI (0x68UL << 0) 1475 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 (0x73UL << 0) 1476 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 (0x74UL << 0) 1477 u8 ver_maj; 1478 u8 ver_min; 1479 u8 ver_upd; 1480 u8 unused_0; 1481 u8 unused_1; 1482 u8 valid; 1483 }; 1484 1485 /* hwrm_port_phy_cfg */ 1486 /* Input (56 bytes) */ 1487 struct hwrm_port_phy_cfg_input { 1488 __le16 req_type; 1489 __le16 cmpl_ring; 1490 __le16 seq_id; 1491 __le16 target_id; 1492 __le64 resp_addr; 1493 __le32 flags; 1494 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 1495 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DOWN 0x2UL 1496 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 1497 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 1498 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 1499 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 1500 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 1501 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 1502 __le32 enables; 1503 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 1504 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 1505 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 1506 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 1507 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 1508 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 1509 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 1510 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 1511 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 1512 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 1513 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 1514 __le16 port_id; 1515 __le16 force_link_speed; 1516 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB (0x1UL << 0) 1517 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB (0xaUL << 0) 1518 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB (0x14UL << 0) 1519 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB (0x19UL << 0) 1520 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB (0x64UL << 0) 1521 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB (0xc8UL << 0) 1522 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB (0xfaUL << 0) 1523 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB (0x190UL << 0) 1524 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB (0x1f4UL << 0) 1525 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB (0x3e8UL << 0) 1526 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB (0xffffUL << 0) 1527 u8 auto_mode; 1528 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE (0x0UL << 0) 1529 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS (0x1UL << 0) 1530 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED (0x2UL << 0) 1531 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW (0x3UL << 0) 1532 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK (0x4UL << 0) 1533 u8 auto_duplex; 1534 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF (0x0UL << 0) 1535 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL (0x1UL << 0) 1536 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH (0x2UL << 0) 1537 u8 auto_pause; 1538 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 1539 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 1540 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1541 u8 unused_0; 1542 __le16 auto_link_speed; 1543 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB (0x1UL << 0) 1544 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB (0xaUL << 0) 1545 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB (0x14UL << 0) 1546 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB (0x19UL << 0) 1547 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB (0x64UL << 0) 1548 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB (0xc8UL << 0) 1549 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB (0xfaUL << 0) 1550 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB (0x190UL << 0) 1551 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB (0x1f4UL << 0) 1552 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB (0x3e8UL << 0) 1553 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB (0xffffUL << 0) 1554 __le16 auto_link_speed_mask; 1555 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1556 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1557 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1558 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1559 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1560 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1561 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1562 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1563 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1564 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1565 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1566 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 1567 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 1568 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1569 u8 wirespeed; 1570 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF (0x0UL << 0) 1571 #define PORT_PHY_CFG_REQ_WIRESPEED_ON (0x1UL << 0) 1572 u8 lpbk; 1573 #define PORT_PHY_CFG_REQ_LPBK_NONE (0x0UL << 0) 1574 #define PORT_PHY_CFG_REQ_LPBK_LOCAL (0x1UL << 0) 1575 #define PORT_PHY_CFG_REQ_LPBK_REMOTE (0x2UL << 0) 1576 u8 force_pause; 1577 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 1578 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 1579 u8 unused_1; 1580 __le32 preemphasis; 1581 __le16 eee_link_speed_mask; 1582 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1583 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 1584 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1585 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 1586 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1587 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1588 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 1589 u8 unused_2; 1590 u8 unused_3; 1591 __le32 tx_lpi_timer; 1592 __le32 unused_4; 1593 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 1594 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 1595 }; 1596 1597 /* Output (16 bytes) */ 1598 struct hwrm_port_phy_cfg_output { 1599 __le16 error_code; 1600 __le16 req_type; 1601 __le16 seq_id; 1602 __le16 resp_len; 1603 __le32 unused_0; 1604 u8 unused_1; 1605 u8 unused_2; 1606 u8 unused_3; 1607 u8 valid; 1608 }; 1609 1610 /* hwrm_port_phy_qcfg */ 1611 /* Input (24 bytes) */ 1612 struct hwrm_port_phy_qcfg_input { 1613 __le16 req_type; 1614 __le16 cmpl_ring; 1615 __le16 seq_id; 1616 __le16 target_id; 1617 __le64 resp_addr; 1618 __le16 port_id; 1619 __le16 unused_0[3]; 1620 }; 1621 1622 /* Output (96 bytes) */ 1623 struct hwrm_port_phy_qcfg_output { 1624 __le16 error_code; 1625 __le16 req_type; 1626 __le16 seq_id; 1627 __le16 resp_len; 1628 u8 link; 1629 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK (0x0UL << 0) 1630 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL (0x1UL << 0) 1631 #define PORT_PHY_QCFG_RESP_LINK_LINK (0x2UL << 0) 1632 u8 unused_0; 1633 __le16 link_speed; 1634 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB (0x1UL << 0) 1635 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB (0xaUL << 0) 1636 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB (0x14UL << 0) 1637 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB (0x19UL << 0) 1638 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB (0x64UL << 0) 1639 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB (0xc8UL << 0) 1640 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB (0xfaUL << 0) 1641 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB (0x190UL << 0) 1642 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB (0x1f4UL << 0) 1643 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB (0x3e8UL << 0) 1644 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB (0xffffUL << 0) 1645 u8 duplex; 1646 #define PORT_PHY_QCFG_RESP_DUPLEX_HALF (0x0UL << 0) 1647 #define PORT_PHY_QCFG_RESP_DUPLEX_FULL (0x1UL << 0) 1648 u8 pause; 1649 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 1650 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 1651 __le16 support_speeds; 1652 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 1653 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 1654 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 1655 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 1656 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 1657 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 1658 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 1659 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 1660 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 1661 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 1662 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 1663 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 1664 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 1665 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 1666 __le16 force_link_speed; 1667 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB (0x1UL << 0) 1668 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB (0xaUL << 0) 1669 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB (0x14UL << 0) 1670 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB (0x19UL << 0) 1671 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB (0x64UL << 0) 1672 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB (0xc8UL << 0) 1673 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB (0xfaUL << 0) 1674 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB (0x190UL << 0) 1675 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB (0x1f4UL << 0) 1676 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB (0x3e8UL << 0) 1677 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB (0xffffUL << 0) 1678 u8 auto_mode; 1679 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE (0x0UL << 0) 1680 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS (0x1UL << 0) 1681 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED (0x2UL << 0) 1682 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW (0x3UL << 0) 1683 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK (0x4UL << 0) 1684 u8 auto_pause; 1685 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 1686 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 1687 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1688 __le16 auto_link_speed; 1689 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB (0x1UL << 0) 1690 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB (0xaUL << 0) 1691 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB (0x14UL << 0) 1692 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB (0x19UL << 0) 1693 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB (0x64UL << 0) 1694 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB (0xc8UL << 0) 1695 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB (0xfaUL << 0) 1696 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB (0x190UL << 0) 1697 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB (0x1f4UL << 0) 1698 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB (0x3e8UL << 0) 1699 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB (0xffffUL << 0) 1700 __le16 auto_link_speed_mask; 1701 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1702 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1703 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1704 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1705 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1706 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1707 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1708 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1709 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1710 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1711 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1712 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 1713 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 1714 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1715 u8 wirespeed; 1716 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF (0x0UL << 0) 1717 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON (0x1UL << 0) 1718 u8 lpbk; 1719 #define PORT_PHY_QCFG_RESP_LPBK_NONE (0x0UL << 0) 1720 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL (0x1UL << 0) 1721 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE (0x2UL << 0) 1722 u8 force_pause; 1723 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 1724 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 1725 u8 module_status; 1726 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE (0x0UL << 0) 1727 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX (0x1UL << 0) 1728 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG (0x2UL << 0) 1729 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN (0x3UL << 0) 1730 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED (0x4UL << 0) 1731 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE (0xffUL << 0) 1732 __le32 preemphasis; 1733 u8 phy_maj; 1734 u8 phy_min; 1735 u8 phy_bld; 1736 u8 phy_type; 1737 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN (0x0UL << 0) 1738 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR (0x1UL << 0) 1739 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 (0x2UL << 0) 1740 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR (0x3UL << 0) 1741 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR (0x4UL << 0) 1742 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 (0x5UL << 0) 1743 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX (0x6UL << 0) 1744 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR (0x7UL << 0) 1745 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET (0x8UL << 0) 1746 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE (0x9UL << 0) 1747 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY (0xaUL << 0) 1748 u8 media_type; 1749 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN (0x0UL << 0) 1750 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP (0x1UL << 0) 1751 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC (0x2UL << 0) 1752 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE (0x3UL << 0) 1753 u8 xcvr_pkg_type; 1754 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL (0x1UL << 0) 1755 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL (0x2UL << 0) 1756 u8 eee_config_phy_addr; 1757 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 1758 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 1759 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 1760 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 1761 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 1762 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 1763 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 1764 u8 parallel_detect; 1765 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 1766 #define PORT_PHY_QCFG_RESP_RESERVED_MASK 0xfeUL 1767 #define PORT_PHY_QCFG_RESP_RESERVED_SFT 1 1768 __le16 link_partner_adv_speeds; 1769 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 1770 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 1771 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 1772 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 1773 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 1774 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 1775 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 1776 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 1777 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 1778 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 1779 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 1780 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 1781 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 1782 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 1783 u8 link_partner_adv_auto_mode; 1784 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE (0x0UL << 0) 1785 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS (0x1UL << 0) 1786 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED (0x2UL << 0) 1787 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW (0x3UL << 0) 1788 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK (0x4UL << 0) 1789 u8 link_partner_adv_pause; 1790 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 1791 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 1792 __le16 adv_eee_link_speed_mask; 1793 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1794 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 1795 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1796 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 1797 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1798 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1799 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 1800 __le16 link_partner_adv_eee_link_speed_mask; 1801 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1802 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 1803 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1804 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 1805 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1806 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1807 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 1808 __le32 xcvr_identifier_type_tx_lpi_timer; 1809 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 1810 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 1811 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 1812 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 1813 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 1814 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 1815 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 1816 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 1817 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 1818 __le32 unused_1; 1819 char phy_vendor_name[16]; 1820 char phy_vendor_partnumber[16]; 1821 __le32 unused_2; 1822 u8 unused_3; 1823 u8 unused_4; 1824 u8 unused_5; 1825 u8 valid; 1826 }; 1827 1828 /* hwrm_port_mac_cfg */ 1829 /* Input (40 bytes) */ 1830 struct hwrm_port_mac_cfg_input { 1831 __le16 req_type; 1832 __le16 cmpl_ring; 1833 __le16 seq_id; 1834 __le16 target_id; 1835 __le64 resp_addr; 1836 __le32 flags; 1837 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 1838 #define PORT_MAC_CFG_REQ_FLAGS_COS_ASSIGNMENT_ENABLE 0x2UL 1839 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 1840 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 1841 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 1842 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 1843 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 1844 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 1845 __le32 enables; 1846 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 1847 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 1848 #define PORT_MAC_CFG_REQ_ENABLES_IVLAN_PRI2COS_MAP_PRI 0x4UL 1849 #define PORT_MAC_CFG_REQ_ENABLES_LCOS_MAP_PRI 0x8UL 1850 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 1851 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 1852 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 1853 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 1854 __le16 port_id; 1855 u8 ipg; 1856 u8 lpbk; 1857 #define PORT_MAC_CFG_REQ_LPBK_NONE (0x0UL << 0) 1858 #define PORT_MAC_CFG_REQ_LPBK_LOCAL (0x1UL << 0) 1859 #define PORT_MAC_CFG_REQ_LPBK_REMOTE (0x2UL << 0) 1860 u8 ivlan_pri2cos_map_pri; 1861 u8 lcos_map_pri; 1862 u8 tunnel_pri2cos_map_pri; 1863 u8 dscp2pri_map_pri; 1864 __le16 rx_ts_capture_ptp_msg_type; 1865 __le16 tx_ts_capture_ptp_msg_type; 1866 __le32 unused_0; 1867 }; 1868 1869 /* Output (16 bytes) */ 1870 struct hwrm_port_mac_cfg_output { 1871 __le16 error_code; 1872 __le16 req_type; 1873 __le16 seq_id; 1874 __le16 resp_len; 1875 __le16 mru; 1876 __le16 mtu; 1877 u8 ipg; 1878 u8 lpbk; 1879 #define PORT_MAC_CFG_RESP_LPBK_NONE (0x0UL << 0) 1880 #define PORT_MAC_CFG_RESP_LPBK_LOCAL (0x1UL << 0) 1881 #define PORT_MAC_CFG_RESP_LPBK_REMOTE (0x2UL << 0) 1882 u8 unused_0; 1883 u8 valid; 1884 }; 1885 1886 /* hwrm_port_qstats */ 1887 /* Input (40 bytes) */ 1888 struct hwrm_port_qstats_input { 1889 __le16 req_type; 1890 __le16 cmpl_ring; 1891 __le16 seq_id; 1892 __le16 target_id; 1893 __le64 resp_addr; 1894 __le16 port_id; 1895 u8 unused_0; 1896 u8 unused_1; 1897 u8 unused_2[3]; 1898 u8 unused_3; 1899 __le64 tx_stat_host_addr; 1900 __le64 rx_stat_host_addr; 1901 }; 1902 1903 /* Output (16 bytes) */ 1904 struct hwrm_port_qstats_output { 1905 __le16 error_code; 1906 __le16 req_type; 1907 __le16 seq_id; 1908 __le16 resp_len; 1909 __le16 tx_stat_size; 1910 __le16 rx_stat_size; 1911 u8 unused_0; 1912 u8 unused_1; 1913 u8 unused_2; 1914 u8 valid; 1915 }; 1916 1917 /* hwrm_port_lpbk_qstats */ 1918 /* Input (16 bytes) */ 1919 struct hwrm_port_lpbk_qstats_input { 1920 __le16 req_type; 1921 __le16 cmpl_ring; 1922 __le16 seq_id; 1923 __le16 target_id; 1924 __le64 resp_addr; 1925 }; 1926 1927 /* Output (96 bytes) */ 1928 struct hwrm_port_lpbk_qstats_output { 1929 __le16 error_code; 1930 __le16 req_type; 1931 __le16 seq_id; 1932 __le16 resp_len; 1933 __le64 lpbk_ucast_frames; 1934 __le64 lpbk_mcast_frames; 1935 __le64 lpbk_bcast_frames; 1936 __le64 lpbk_ucast_bytes; 1937 __le64 lpbk_mcast_bytes; 1938 __le64 lpbk_bcast_bytes; 1939 __le64 tx_stat_discard; 1940 __le64 tx_stat_error; 1941 __le64 rx_stat_discard; 1942 __le64 rx_stat_error; 1943 __le32 unused_0; 1944 u8 unused_1; 1945 u8 unused_2; 1946 u8 unused_3; 1947 u8 valid; 1948 }; 1949 1950 /* hwrm_port_clr_stats */ 1951 /* Input (24 bytes) */ 1952 struct hwrm_port_clr_stats_input { 1953 __le16 req_type; 1954 __le16 cmpl_ring; 1955 __le16 seq_id; 1956 __le16 target_id; 1957 __le64 resp_addr; 1958 __le16 port_id; 1959 __le16 unused_0[3]; 1960 }; 1961 1962 /* Output (16 bytes) */ 1963 struct hwrm_port_clr_stats_output { 1964 __le16 error_code; 1965 __le16 req_type; 1966 __le16 seq_id; 1967 __le16 resp_len; 1968 __le32 unused_0; 1969 u8 unused_1; 1970 u8 unused_2; 1971 u8 unused_3; 1972 u8 valid; 1973 }; 1974 1975 /* hwrm_port_lpbk_clr_stats */ 1976 /* Input (16 bytes) */ 1977 struct hwrm_port_lpbk_clr_stats_input { 1978 __le16 req_type; 1979 __le16 cmpl_ring; 1980 __le16 seq_id; 1981 __le16 target_id; 1982 __le64 resp_addr; 1983 }; 1984 1985 /* Output (16 bytes) */ 1986 struct hwrm_port_lpbk_clr_stats_output { 1987 __le16 error_code; 1988 __le16 req_type; 1989 __le16 seq_id; 1990 __le16 resp_len; 1991 __le32 unused_0; 1992 u8 unused_1; 1993 u8 unused_2; 1994 u8 unused_3; 1995 u8 valid; 1996 }; 1997 1998 /* hwrm_port_blink_led */ 1999 /* Input (24 bytes) */ 2000 struct hwrm_port_blink_led_input { 2001 __le16 req_type; 2002 __le16 cmpl_ring; 2003 __le16 seq_id; 2004 __le16 target_id; 2005 __le64 resp_addr; 2006 __le32 num_blinks; 2007 __le32 unused_0; 2008 }; 2009 2010 /* Output (16 bytes) */ 2011 struct hwrm_port_blink_led_output { 2012 __le16 error_code; 2013 __le16 req_type; 2014 __le16 seq_id; 2015 __le16 resp_len; 2016 __le32 unused_0; 2017 u8 unused_1; 2018 u8 unused_2; 2019 u8 unused_3; 2020 u8 valid; 2021 }; 2022 2023 /* hwrm_port_phy_qcaps */ 2024 /* Input (24 bytes) */ 2025 struct hwrm_port_phy_qcaps_input { 2026 __le16 req_type; 2027 __le16 cmpl_ring; 2028 __le16 seq_id; 2029 __le16 target_id; 2030 __le64 resp_addr; 2031 __le16 port_id; 2032 __le16 unused_0[3]; 2033 }; 2034 2035 /* Output (24 bytes) */ 2036 struct hwrm_port_phy_qcaps_output { 2037 __le16 error_code; 2038 __le16 req_type; 2039 __le16 seq_id; 2040 __le16 resp_len; 2041 u8 eee_supported; 2042 #define PORT_PHY_QCAPS_RESP_EEE_SUPPORTED 0x1UL 2043 #define PORT_PHY_QCAPS_RESP_RSVD1_MASK 0xfeUL 2044 #define PORT_PHY_QCAPS_RESP_RSVD1_SFT 1 2045 u8 unused_0; 2046 __le16 supported_speeds_force_mode; 2047 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 2048 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 2049 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 2050 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 2051 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 2052 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 2053 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 2054 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 2055 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 2056 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 2057 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 2058 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 2059 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 2060 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 2061 __le16 supported_speeds_auto_mode; 2062 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 2063 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 2064 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 2065 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 2066 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 2067 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 2068 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 2069 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 2070 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 2071 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 2072 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 2073 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 2074 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 2075 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 2076 __le16 supported_speeds_eee_mode; 2077 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 2078 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 2079 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 2080 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 2081 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 2082 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 2083 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 2084 __le32 tx_lpi_timer_low; 2085 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 2086 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 2087 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 2088 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 2089 __le32 valid_tx_lpi_timer_high; 2090 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 2091 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 2092 #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL 2093 #define PORT_PHY_QCAPS_RESP_VALID_SFT 24 2094 }; 2095 2096 /* hwrm_port_phy_i2c_read */ 2097 /* Input (40 bytes) */ 2098 struct hwrm_port_phy_i2c_read_input { 2099 __le16 req_type; 2100 __le16 cmpl_ring; 2101 __le16 seq_id; 2102 __le16 target_id; 2103 __le64 resp_addr; 2104 __le32 flags; 2105 __le32 enables; 2106 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 2107 __le16 port_id; 2108 u8 i2c_slave_addr; 2109 u8 unused_0; 2110 __le16 page_number; 2111 __le16 page_offset; 2112 u8 data_length; 2113 u8 unused_1[7]; 2114 }; 2115 2116 /* Output (80 bytes) */ 2117 struct hwrm_port_phy_i2c_read_output { 2118 __le16 error_code; 2119 __le16 req_type; 2120 __le16 seq_id; 2121 __le16 resp_len; 2122 __le32 data[16]; 2123 __le32 unused_0; 2124 u8 unused_1; 2125 u8 unused_2; 2126 u8 unused_3; 2127 u8 valid; 2128 }; 2129 2130 /* Input (24 bytes) */ 2131 struct hwrm_queue_qportcfg_input { 2132 __le16 req_type; 2133 __le16 cmpl_ring; 2134 __le16 seq_id; 2135 __le16 target_id; 2136 __le64 resp_addr; 2137 __le32 flags; 2138 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 2139 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 2140 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 2141 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 2142 __le16 port_id; 2143 __le16 unused_0; 2144 }; 2145 2146 /* Output (32 bytes) */ 2147 struct hwrm_queue_qportcfg_output { 2148 __le16 error_code; 2149 __le16 req_type; 2150 __le16 seq_id; 2151 __le16 resp_len; 2152 u8 max_configurable_queues; 2153 u8 max_configurable_lossless_queues; 2154 u8 queue_cfg_allowed; 2155 u8 queue_buffers_cfg_allowed; 2156 u8 queue_pfcenable_cfg_allowed; 2157 u8 queue_pri2cos_cfg_allowed; 2158 u8 queue_cos2bw_cfg_allowed; 2159 u8 queue_id0; 2160 u8 queue_id0_service_profile; 2161 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY (0x0UL << 0) 2162 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 2163 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 2164 u8 queue_id1; 2165 u8 queue_id1_service_profile; 2166 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY (0x0UL << 0) 2167 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 2168 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 2169 u8 queue_id2; 2170 u8 queue_id2_service_profile; 2171 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY (0x0UL << 0) 2172 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 2173 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 2174 u8 queue_id3; 2175 u8 queue_id3_service_profile; 2176 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY (0x0UL << 0) 2177 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 2178 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 2179 u8 queue_id4; 2180 u8 queue_id4_service_profile; 2181 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY (0x0UL << 0) 2182 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 2183 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 2184 u8 queue_id5; 2185 u8 queue_id5_service_profile; 2186 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY (0x0UL << 0) 2187 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 2188 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 2189 u8 queue_id6; 2190 u8 queue_id6_service_profile; 2191 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY (0x0UL << 0) 2192 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 2193 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 2194 u8 queue_id7; 2195 u8 queue_id7_service_profile; 2196 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY (0x0UL << 0) 2197 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 2198 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 2199 u8 valid; 2200 }; 2201 2202 /* hwrm_queue_cfg */ 2203 /* Input (40 bytes) */ 2204 struct hwrm_queue_cfg_input { 2205 __le16 req_type; 2206 __le16 cmpl_ring; 2207 __le16 seq_id; 2208 __le16 target_id; 2209 __le64 resp_addr; 2210 __le32 flags; 2211 #define QUEUE_CFG_REQ_FLAGS_PATH 0x1UL 2212 #define QUEUE_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 2213 #define QUEUE_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 2214 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_RX 2215 __le32 enables; 2216 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 2217 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 2218 __le32 queue_id; 2219 __le32 dflt_len; 2220 u8 service_profile; 2221 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY (0x0UL << 0) 2222 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 2223 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 2224 u8 unused_0[7]; 2225 }; 2226 2227 /* Output (16 bytes) */ 2228 struct hwrm_queue_cfg_output { 2229 __le16 error_code; 2230 __le16 req_type; 2231 __le16 seq_id; 2232 __le16 resp_len; 2233 __le32 unused_0; 2234 u8 unused_1; 2235 u8 unused_2; 2236 u8 unused_3; 2237 u8 valid; 2238 }; 2239 2240 /* hwrm_queue_buffers_cfg */ 2241 /* Input (56 bytes) */ 2242 struct hwrm_queue_buffers_cfg_input { 2243 __le16 req_type; 2244 __le16 cmpl_ring; 2245 __le16 seq_id; 2246 __le16 target_id; 2247 __le64 resp_addr; 2248 __le32 flags; 2249 #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH 0x1UL 2250 #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 2251 #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 2252 #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_LAST QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_RX 2253 __le32 enables; 2254 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_RESERVED 0x1UL 2255 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_SHARED 0x2UL 2256 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_XOFF 0x4UL 2257 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_XON 0x8UL 2258 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_FULL 0x10UL 2259 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_NOTFULL 0x20UL 2260 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_MAX 0x40UL 2261 __le32 queue_id; 2262 __le32 reserved; 2263 __le32 shared; 2264 __le32 xoff; 2265 __le32 xon; 2266 __le32 full; 2267 __le32 notfull; 2268 __le32 max; 2269 }; 2270 2271 /* Output (16 bytes) */ 2272 struct hwrm_queue_buffers_cfg_output { 2273 __le16 error_code; 2274 __le16 req_type; 2275 __le16 seq_id; 2276 __le16 resp_len; 2277 __le32 unused_0; 2278 u8 unused_1; 2279 u8 unused_2; 2280 u8 unused_3; 2281 u8 valid; 2282 }; 2283 2284 /* hwrm_queue_pfcenable_cfg */ 2285 /* Input (24 bytes) */ 2286 struct hwrm_queue_pfcenable_cfg_input { 2287 __le16 req_type; 2288 __le16 cmpl_ring; 2289 __le16 seq_id; 2290 __le16 target_id; 2291 __le64 resp_addr; 2292 __le32 flags; 2293 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 2294 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 2295 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 2296 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 2297 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 2298 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 2299 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 2300 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 2301 __le16 port_id; 2302 __le16 unused_0; 2303 }; 2304 2305 /* Output (16 bytes) */ 2306 struct hwrm_queue_pfcenable_cfg_output { 2307 __le16 error_code; 2308 __le16 req_type; 2309 __le16 seq_id; 2310 __le16 resp_len; 2311 __le32 unused_0; 2312 u8 unused_1; 2313 u8 unused_2; 2314 u8 unused_3; 2315 u8 valid; 2316 }; 2317 2318 /* hwrm_queue_pri2cos_cfg */ 2319 /* Input (40 bytes) */ 2320 struct hwrm_queue_pri2cos_cfg_input { 2321 __le16 req_type; 2322 __le16 cmpl_ring; 2323 __le16 seq_id; 2324 __le16 target_id; 2325 __le64 resp_addr; 2326 __le32 flags; 2327 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH 0x1UL 2328 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 2329 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 2330 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 2331 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x2UL 2332 __le32 enables; 2333 u8 port_id; 2334 u8 pri0_cos_queue_id; 2335 u8 pri1_cos_queue_id; 2336 u8 pri2_cos_queue_id; 2337 u8 pri3_cos_queue_id; 2338 u8 pri4_cos_queue_id; 2339 u8 pri5_cos_queue_id; 2340 u8 pri6_cos_queue_id; 2341 u8 pri7_cos_queue_id; 2342 u8 unused_0[7]; 2343 }; 2344 2345 /* Output (16 bytes) */ 2346 struct hwrm_queue_pri2cos_cfg_output { 2347 __le16 error_code; 2348 __le16 req_type; 2349 __le16 seq_id; 2350 __le16 resp_len; 2351 __le32 unused_0; 2352 u8 unused_1; 2353 u8 unused_2; 2354 u8 unused_3; 2355 u8 valid; 2356 }; 2357 2358 /* hwrm_queue_cos2bw_cfg */ 2359 /* Input (128 bytes) */ 2360 struct hwrm_queue_cos2bw_cfg_input { 2361 __le16 req_type; 2362 __le16 cmpl_ring; 2363 __le16 seq_id; 2364 __le16 target_id; 2365 __le64 resp_addr; 2366 __le32 flags; 2367 __le32 enables; 2368 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 2369 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 2370 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 2371 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 2372 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 2373 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 2374 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 2375 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 2376 __le16 port_id; 2377 u8 queue_id0; 2378 u8 unused_0; 2379 __le32 queue_id0_min_bw; 2380 __le32 queue_id0_max_bw; 2381 u8 queue_id0_tsa_assign; 2382 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP (0x0UL << 0) 2383 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS (0x1UL << 0) 2384 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0) 2385 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0) 2386 u8 queue_id0_pri_lvl; 2387 u8 queue_id0_bw_weight; 2388 u8 queue_id1; 2389 __le32 queue_id1_min_bw; 2390 __le32 queue_id1_max_bw; 2391 u8 queue_id1_tsa_assign; 2392 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP (0x0UL << 0) 2393 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS (0x1UL << 0) 2394 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0) 2395 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0) 2396 u8 queue_id1_pri_lvl; 2397 u8 queue_id1_bw_weight; 2398 u8 queue_id2; 2399 __le32 queue_id2_min_bw; 2400 __le32 queue_id2_max_bw; 2401 u8 queue_id2_tsa_assign; 2402 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP (0x0UL << 0) 2403 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS (0x1UL << 0) 2404 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0) 2405 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0) 2406 u8 queue_id2_pri_lvl; 2407 u8 queue_id2_bw_weight; 2408 u8 queue_id3; 2409 __le32 queue_id3_min_bw; 2410 __le32 queue_id3_max_bw; 2411 u8 queue_id3_tsa_assign; 2412 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP (0x0UL << 0) 2413 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS (0x1UL << 0) 2414 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0) 2415 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0) 2416 u8 queue_id3_pri_lvl; 2417 u8 queue_id3_bw_weight; 2418 u8 queue_id4; 2419 __le32 queue_id4_min_bw; 2420 __le32 queue_id4_max_bw; 2421 u8 queue_id4_tsa_assign; 2422 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP (0x0UL << 0) 2423 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS (0x1UL << 0) 2424 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0) 2425 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0) 2426 u8 queue_id4_pri_lvl; 2427 u8 queue_id4_bw_weight; 2428 u8 queue_id5; 2429 __le32 queue_id5_min_bw; 2430 __le32 queue_id5_max_bw; 2431 u8 queue_id5_tsa_assign; 2432 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP (0x0UL << 0) 2433 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS (0x1UL << 0) 2434 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0) 2435 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0) 2436 u8 queue_id5_pri_lvl; 2437 u8 queue_id5_bw_weight; 2438 u8 queue_id6; 2439 __le32 queue_id6_min_bw; 2440 __le32 queue_id6_max_bw; 2441 u8 queue_id6_tsa_assign; 2442 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP (0x0UL << 0) 2443 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS (0x1UL << 0) 2444 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0) 2445 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0) 2446 u8 queue_id6_pri_lvl; 2447 u8 queue_id6_bw_weight; 2448 u8 queue_id7; 2449 __le32 queue_id7_min_bw; 2450 __le32 queue_id7_max_bw; 2451 u8 queue_id7_tsa_assign; 2452 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP (0x0UL << 0) 2453 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS (0x1UL << 0) 2454 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0) 2455 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0) 2456 u8 queue_id7_pri_lvl; 2457 u8 queue_id7_bw_weight; 2458 u8 unused_1[5]; 2459 }; 2460 2461 /* Output (16 bytes) */ 2462 struct hwrm_queue_cos2bw_cfg_output { 2463 __le16 error_code; 2464 __le16 req_type; 2465 __le16 seq_id; 2466 __le16 resp_len; 2467 __le32 unused_0; 2468 u8 unused_1; 2469 u8 unused_2; 2470 u8 unused_3; 2471 u8 valid; 2472 }; 2473 2474 /* hwrm_vnic_alloc */ 2475 /* Input (24 bytes) */ 2476 struct hwrm_vnic_alloc_input { 2477 __le16 req_type; 2478 __le16 cmpl_ring; 2479 __le16 seq_id; 2480 __le16 target_id; 2481 __le64 resp_addr; 2482 __le32 flags; 2483 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 2484 __le32 unused_0; 2485 }; 2486 2487 /* Output (16 bytes) */ 2488 struct hwrm_vnic_alloc_output { 2489 __le16 error_code; 2490 __le16 req_type; 2491 __le16 seq_id; 2492 __le16 resp_len; 2493 __le32 vnic_id; 2494 u8 unused_0; 2495 u8 unused_1; 2496 u8 unused_2; 2497 u8 valid; 2498 }; 2499 2500 /* hwrm_vnic_free */ 2501 /* Input (24 bytes) */ 2502 struct hwrm_vnic_free_input { 2503 __le16 req_type; 2504 __le16 cmpl_ring; 2505 __le16 seq_id; 2506 __le16 target_id; 2507 __le64 resp_addr; 2508 __le32 vnic_id; 2509 __le32 unused_0; 2510 }; 2511 2512 /* Output (16 bytes) */ 2513 struct hwrm_vnic_free_output { 2514 __le16 error_code; 2515 __le16 req_type; 2516 __le16 seq_id; 2517 __le16 resp_len; 2518 __le32 unused_0; 2519 u8 unused_1; 2520 u8 unused_2; 2521 u8 unused_3; 2522 u8 valid; 2523 }; 2524 2525 /* hwrm_vnic_cfg */ 2526 /* Input (40 bytes) */ 2527 struct hwrm_vnic_cfg_input { 2528 __le16 req_type; 2529 __le16 cmpl_ring; 2530 __le16 seq_id; 2531 __le16 target_id; 2532 __le64 resp_addr; 2533 __le32 flags; 2534 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 2535 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 2536 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 2537 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 2538 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 2539 __le32 enables; 2540 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 2541 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 2542 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 2543 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 2544 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 2545 __le16 vnic_id; 2546 __le16 dflt_ring_grp; 2547 __le16 rss_rule; 2548 __le16 cos_rule; 2549 __le16 lb_rule; 2550 __le16 mru; 2551 __le32 unused_0; 2552 }; 2553 2554 /* Output (16 bytes) */ 2555 struct hwrm_vnic_cfg_output { 2556 __le16 error_code; 2557 __le16 req_type; 2558 __le16 seq_id; 2559 __le16 resp_len; 2560 __le32 unused_0; 2561 u8 unused_1; 2562 u8 unused_2; 2563 u8 unused_3; 2564 u8 valid; 2565 }; 2566 2567 /* hwrm_vnic_tpa_cfg */ 2568 /* Input (40 bytes) */ 2569 struct hwrm_vnic_tpa_cfg_input { 2570 __le16 req_type; 2571 __le16 cmpl_ring; 2572 __le16 seq_id; 2573 __le16 target_id; 2574 __le64 resp_addr; 2575 __le32 flags; 2576 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 2577 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 2578 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 2579 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 2580 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 2581 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 2582 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 2583 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 2584 __le32 enables; 2585 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 2586 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 2587 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 2588 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 2589 __le16 vnic_id; 2590 __le16 max_agg_segs; 2591 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 (0x0UL << 0) 2592 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 (0x1UL << 0) 2593 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 (0x2UL << 0) 2594 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 (0x3UL << 0) 2595 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX (0x1fUL << 0) 2596 __le16 max_aggs; 2597 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 (0x0UL << 0) 2598 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 (0x1UL << 0) 2599 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 (0x2UL << 0) 2600 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 (0x3UL << 0) 2601 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 (0x4UL << 0) 2602 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX (0x7UL << 0) 2603 u8 unused_0; 2604 u8 unused_1; 2605 __le32 max_agg_timer; 2606 __le32 min_agg_len; 2607 }; 2608 2609 /* Output (16 bytes) */ 2610 struct hwrm_vnic_tpa_cfg_output { 2611 __le16 error_code; 2612 __le16 req_type; 2613 __le16 seq_id; 2614 __le16 resp_len; 2615 __le32 unused_0; 2616 u8 unused_1; 2617 u8 unused_2; 2618 u8 unused_3; 2619 u8 valid; 2620 }; 2621 2622 /* hwrm_vnic_rss_cfg */ 2623 /* Input (48 bytes) */ 2624 struct hwrm_vnic_rss_cfg_input { 2625 __le16 req_type; 2626 __le16 cmpl_ring; 2627 __le16 seq_id; 2628 __le16 target_id; 2629 __le64 resp_addr; 2630 __le32 hash_type; 2631 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 2632 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 2633 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 2634 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 2635 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 2636 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 2637 __le32 unused_0; 2638 __le64 ring_grp_tbl_addr; 2639 __le64 hash_key_tbl_addr; 2640 __le16 rss_ctx_idx; 2641 __le16 unused_1[3]; 2642 }; 2643 2644 /* Output (16 bytes) */ 2645 struct hwrm_vnic_rss_cfg_output { 2646 __le16 error_code; 2647 __le16 req_type; 2648 __le16 seq_id; 2649 __le16 resp_len; 2650 __le32 unused_0; 2651 u8 unused_1; 2652 u8 unused_2; 2653 u8 unused_3; 2654 u8 valid; 2655 }; 2656 2657 /* hwrm_vnic_plcmodes_cfg */ 2658 /* Input (40 bytes) */ 2659 struct hwrm_vnic_plcmodes_cfg_input { 2660 __le16 req_type; 2661 __le16 cmpl_ring; 2662 __le16 seq_id; 2663 __le16 target_id; 2664 __le64 resp_addr; 2665 __le32 flags; 2666 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 2667 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 2668 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 2669 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 2670 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 2671 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 2672 __le32 enables; 2673 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 2674 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 2675 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 2676 __le32 vnic_id; 2677 __le16 jumbo_thresh; 2678 __le16 hds_offset; 2679 __le16 hds_threshold; 2680 __le16 unused_0[3]; 2681 }; 2682 2683 /* Output (16 bytes) */ 2684 struct hwrm_vnic_plcmodes_cfg_output { 2685 __le16 error_code; 2686 __le16 req_type; 2687 __le16 seq_id; 2688 __le16 resp_len; 2689 __le32 unused_0; 2690 u8 unused_1; 2691 u8 unused_2; 2692 u8 unused_3; 2693 u8 valid; 2694 }; 2695 2696 /* hwrm_vnic_rss_cos_lb_ctx_alloc */ 2697 /* Input (16 bytes) */ 2698 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 2699 __le16 req_type; 2700 __le16 cmpl_ring; 2701 __le16 seq_id; 2702 __le16 target_id; 2703 __le64 resp_addr; 2704 }; 2705 2706 /* Output (16 bytes) */ 2707 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 2708 __le16 error_code; 2709 __le16 req_type; 2710 __le16 seq_id; 2711 __le16 resp_len; 2712 __le16 rss_cos_lb_ctx_id; 2713 u8 unused_0; 2714 u8 unused_1; 2715 u8 unused_2; 2716 u8 unused_3; 2717 u8 unused_4; 2718 u8 valid; 2719 }; 2720 2721 /* hwrm_vnic_rss_cos_lb_ctx_free */ 2722 /* Input (24 bytes) */ 2723 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 2724 __le16 req_type; 2725 __le16 cmpl_ring; 2726 __le16 seq_id; 2727 __le16 target_id; 2728 __le64 resp_addr; 2729 __le16 rss_cos_lb_ctx_id; 2730 __le16 unused_0[3]; 2731 }; 2732 2733 /* Output (16 bytes) */ 2734 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 2735 __le16 error_code; 2736 __le16 req_type; 2737 __le16 seq_id; 2738 __le16 resp_len; 2739 __le32 unused_0; 2740 u8 unused_1; 2741 u8 unused_2; 2742 u8 unused_3; 2743 u8 valid; 2744 }; 2745 2746 /* hwrm_ring_alloc */ 2747 /* Input (80 bytes) */ 2748 struct hwrm_ring_alloc_input { 2749 __le16 req_type; 2750 __le16 cmpl_ring; 2751 __le16 seq_id; 2752 __le16 target_id; 2753 __le64 resp_addr; 2754 __le32 enables; 2755 #define RING_ALLOC_REQ_ENABLES_RESERVED1 0x1UL 2756 #define RING_ALLOC_REQ_ENABLES_RESERVED2 0x2UL 2757 #define RING_ALLOC_REQ_ENABLES_RESERVED3 0x4UL 2758 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 2759 #define RING_ALLOC_REQ_ENABLES_RESERVED4 0x10UL 2760 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 2761 u8 ring_type; 2762 #define RING_ALLOC_REQ_RING_TYPE_CMPL (0x0UL << 0) 2763 #define RING_ALLOC_REQ_RING_TYPE_TX (0x1UL << 0) 2764 #define RING_ALLOC_REQ_RING_TYPE_RX (0x2UL << 0) 2765 u8 unused_0; 2766 __le16 unused_1; 2767 __le64 page_tbl_addr; 2768 __le32 fbo; 2769 u8 page_size; 2770 u8 page_tbl_depth; 2771 u8 unused_2; 2772 u8 unused_3; 2773 __le32 length; 2774 __le16 logical_id; 2775 __le16 cmpl_ring_id; 2776 __le16 queue_id; 2777 u8 unused_4; 2778 u8 unused_5; 2779 __le32 reserved1; 2780 __le16 reserved2; 2781 u8 unused_6; 2782 u8 unused_7; 2783 __le32 reserved3; 2784 __le32 stat_ctx_id; 2785 __le32 reserved4; 2786 __le32 max_bw; 2787 u8 int_mode; 2788 #define RING_ALLOC_REQ_INT_MODE_LEGACY (0x0UL << 0) 2789 #define RING_ALLOC_REQ_INT_MODE_RSVD (0x1UL << 0) 2790 #define RING_ALLOC_REQ_INT_MODE_MSIX (0x2UL << 0) 2791 #define RING_ALLOC_REQ_INT_MODE_POLL (0x3UL << 0) 2792 u8 unused_8[3]; 2793 }; 2794 2795 /* Output (16 bytes) */ 2796 struct hwrm_ring_alloc_output { 2797 __le16 error_code; 2798 __le16 req_type; 2799 __le16 seq_id; 2800 __le16 resp_len; 2801 __le16 ring_id; 2802 __le16 logical_ring_id; 2803 u8 unused_0; 2804 u8 unused_1; 2805 u8 unused_2; 2806 u8 valid; 2807 }; 2808 2809 /* hwrm_ring_free */ 2810 /* Input (24 bytes) */ 2811 struct hwrm_ring_free_input { 2812 __le16 req_type; 2813 __le16 cmpl_ring; 2814 __le16 seq_id; 2815 __le16 target_id; 2816 __le64 resp_addr; 2817 u8 ring_type; 2818 #define RING_FREE_REQ_RING_TYPE_CMPL (0x0UL << 0) 2819 #define RING_FREE_REQ_RING_TYPE_TX (0x1UL << 0) 2820 #define RING_FREE_REQ_RING_TYPE_RX (0x2UL << 0) 2821 u8 unused_0; 2822 __le16 ring_id; 2823 __le32 unused_1; 2824 }; 2825 2826 /* Output (16 bytes) */ 2827 struct hwrm_ring_free_output { 2828 __le16 error_code; 2829 __le16 req_type; 2830 __le16 seq_id; 2831 __le16 resp_len; 2832 __le32 unused_0; 2833 u8 unused_1; 2834 u8 unused_2; 2835 u8 unused_3; 2836 u8 valid; 2837 }; 2838 2839 /* hwrm_ring_cmpl_ring_qaggint_params */ 2840 /* Input (24 bytes) */ 2841 struct hwrm_ring_cmpl_ring_qaggint_params_input { 2842 __le16 req_type; 2843 __le16 cmpl_ring; 2844 __le16 seq_id; 2845 __le16 target_id; 2846 __le64 resp_addr; 2847 __le16 ring_id; 2848 __le16 unused_0[3]; 2849 }; 2850 2851 /* Output (32 bytes) */ 2852 struct hwrm_ring_cmpl_ring_qaggint_params_output { 2853 __le16 error_code; 2854 __le16 req_type; 2855 __le16 seq_id; 2856 __le16 resp_len; 2857 __le16 flags; 2858 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 2859 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 2860 __le16 num_cmpl_dma_aggr; 2861 __le16 num_cmpl_dma_aggr_during_int; 2862 __le16 cmpl_aggr_dma_tmr; 2863 __le16 cmpl_aggr_dma_tmr_during_int; 2864 __le16 int_lat_tmr_min; 2865 __le16 int_lat_tmr_max; 2866 __le16 num_cmpl_aggr_int; 2867 __le32 unused_0; 2868 u8 unused_1; 2869 u8 unused_2; 2870 u8 unused_3; 2871 u8 valid; 2872 }; 2873 2874 /* hwrm_ring_cmpl_ring_cfg_aggint_params */ 2875 /* Input (40 bytes) */ 2876 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 2877 __le16 req_type; 2878 __le16 cmpl_ring; 2879 __le16 seq_id; 2880 __le16 target_id; 2881 __le64 resp_addr; 2882 __le16 ring_id; 2883 __le16 flags; 2884 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 2885 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 2886 __le16 num_cmpl_dma_aggr; 2887 __le16 num_cmpl_dma_aggr_during_int; 2888 __le16 cmpl_aggr_dma_tmr; 2889 __le16 cmpl_aggr_dma_tmr_during_int; 2890 __le16 int_lat_tmr_min; 2891 __le16 int_lat_tmr_max; 2892 __le16 num_cmpl_aggr_int; 2893 __le16 unused_0[3]; 2894 }; 2895 2896 /* Output (16 bytes) */ 2897 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 2898 __le16 error_code; 2899 __le16 req_type; 2900 __le16 seq_id; 2901 __le16 resp_len; 2902 __le32 unused_0; 2903 u8 unused_1; 2904 u8 unused_2; 2905 u8 unused_3; 2906 u8 valid; 2907 }; 2908 2909 /* hwrm_ring_reset */ 2910 /* Input (24 bytes) */ 2911 struct hwrm_ring_reset_input { 2912 __le16 req_type; 2913 __le16 cmpl_ring; 2914 __le16 seq_id; 2915 __le16 target_id; 2916 __le64 resp_addr; 2917 u8 ring_type; 2918 #define RING_RESET_REQ_RING_TYPE_CMPL (0x0UL << 0) 2919 #define RING_RESET_REQ_RING_TYPE_TX (0x1UL << 0) 2920 #define RING_RESET_REQ_RING_TYPE_RX (0x2UL << 0) 2921 u8 unused_0; 2922 __le16 ring_id; 2923 __le32 unused_1; 2924 }; 2925 2926 /* Output (16 bytes) */ 2927 struct hwrm_ring_reset_output { 2928 __le16 error_code; 2929 __le16 req_type; 2930 __le16 seq_id; 2931 __le16 resp_len; 2932 __le32 unused_0; 2933 u8 unused_1; 2934 u8 unused_2; 2935 u8 unused_3; 2936 u8 valid; 2937 }; 2938 2939 /* hwrm_ring_grp_alloc */ 2940 /* Input (24 bytes) */ 2941 struct hwrm_ring_grp_alloc_input { 2942 __le16 req_type; 2943 __le16 cmpl_ring; 2944 __le16 seq_id; 2945 __le16 target_id; 2946 __le64 resp_addr; 2947 __le16 cr; 2948 __le16 rr; 2949 __le16 ar; 2950 __le16 sc; 2951 }; 2952 2953 /* Output (16 bytes) */ 2954 struct hwrm_ring_grp_alloc_output { 2955 __le16 error_code; 2956 __le16 req_type; 2957 __le16 seq_id; 2958 __le16 resp_len; 2959 __le32 ring_group_id; 2960 u8 unused_0; 2961 u8 unused_1; 2962 u8 unused_2; 2963 u8 valid; 2964 }; 2965 2966 /* hwrm_ring_grp_free */ 2967 /* Input (24 bytes) */ 2968 struct hwrm_ring_grp_free_input { 2969 __le16 req_type; 2970 __le16 cmpl_ring; 2971 __le16 seq_id; 2972 __le16 target_id; 2973 __le64 resp_addr; 2974 __le32 ring_group_id; 2975 __le32 unused_0; 2976 }; 2977 2978 /* Output (16 bytes) */ 2979 struct hwrm_ring_grp_free_output { 2980 __le16 error_code; 2981 __le16 req_type; 2982 __le16 seq_id; 2983 __le16 resp_len; 2984 __le32 unused_0; 2985 u8 unused_1; 2986 u8 unused_2; 2987 u8 unused_3; 2988 u8 valid; 2989 }; 2990 2991 /* hwrm_cfa_l2_filter_alloc */ 2992 /* Input (96 bytes) */ 2993 struct hwrm_cfa_l2_filter_alloc_input { 2994 __le16 req_type; 2995 __le16 cmpl_ring; 2996 __le16 seq_id; 2997 __le16 target_id; 2998 __le64 resp_addr; 2999 __le32 flags; 3000 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 3001 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX (0x0UL << 0) 3002 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX (0x1UL << 0) 3003 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 3004 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 3005 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 3006 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 3007 __le32 enables; 3008 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 3009 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 3010 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 3011 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 3012 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 3013 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 3014 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 3015 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 3016 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 3017 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 3018 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 3019 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 3020 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 3021 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 3022 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 3023 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 3024 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 3025 u8 l2_addr[6]; 3026 u8 unused_0; 3027 u8 unused_1; 3028 u8 l2_addr_mask[6]; 3029 __le16 l2_ovlan; 3030 __le16 l2_ovlan_mask; 3031 __le16 l2_ivlan; 3032 __le16 l2_ivlan_mask; 3033 u8 unused_2; 3034 u8 unused_3; 3035 u8 t_l2_addr[6]; 3036 u8 unused_4; 3037 u8 unused_5; 3038 u8 t_l2_addr_mask[6]; 3039 __le16 t_l2_ovlan; 3040 __le16 t_l2_ovlan_mask; 3041 __le16 t_l2_ivlan; 3042 __le16 t_l2_ivlan_mask; 3043 u8 src_type; 3044 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT (0x0UL << 0) 3045 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF (0x1UL << 0) 3046 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF (0x2UL << 0) 3047 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC (0x3UL << 0) 3048 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG (0x4UL << 0) 3049 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE (0x5UL << 0) 3050 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO (0x6UL << 0) 3051 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG (0x7UL << 0) 3052 u8 unused_6; 3053 __le32 src_id; 3054 u8 tunnel_type; 3055 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0) 3056 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0) 3057 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0) 3058 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0) 3059 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0) 3060 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0) 3061 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0) 3062 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT (0x7UL << 0) 3063 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0) 3064 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0) 3065 u8 unused_7; 3066 __le16 dst_id; 3067 __le16 mirror_vnic_id; 3068 u8 pri_hint; 3069 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER (0x0UL << 0) 3070 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER (0x1UL << 0) 3071 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER (0x2UL << 0) 3072 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX (0x3UL << 0) 3073 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN (0x4UL << 0) 3074 u8 unused_8; 3075 __le32 unused_9; 3076 __le64 l2_filter_id_hint; 3077 }; 3078 3079 /* Output (24 bytes) */ 3080 struct hwrm_cfa_l2_filter_alloc_output { 3081 __le16 error_code; 3082 __le16 req_type; 3083 __le16 seq_id; 3084 __le16 resp_len; 3085 __le64 l2_filter_id; 3086 __le32 flow_id; 3087 u8 unused_0; 3088 u8 unused_1; 3089 u8 unused_2; 3090 u8 valid; 3091 }; 3092 3093 /* hwrm_cfa_l2_filter_free */ 3094 /* Input (24 bytes) */ 3095 struct hwrm_cfa_l2_filter_free_input { 3096 __le16 req_type; 3097 __le16 cmpl_ring; 3098 __le16 seq_id; 3099 __le16 target_id; 3100 __le64 resp_addr; 3101 __le64 l2_filter_id; 3102 }; 3103 3104 /* Output (16 bytes) */ 3105 struct hwrm_cfa_l2_filter_free_output { 3106 __le16 error_code; 3107 __le16 req_type; 3108 __le16 seq_id; 3109 __le16 resp_len; 3110 __le32 unused_0; 3111 u8 unused_1; 3112 u8 unused_2; 3113 u8 unused_3; 3114 u8 valid; 3115 }; 3116 3117 /* hwrm_cfa_l2_filter_cfg */ 3118 /* Input (40 bytes) */ 3119 struct hwrm_cfa_l2_filter_cfg_input { 3120 __le16 req_type; 3121 __le16 cmpl_ring; 3122 __le16 seq_id; 3123 __le16 target_id; 3124 __le64 resp_addr; 3125 __le32 flags; 3126 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 3127 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 3128 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 3129 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 3130 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 3131 __le32 enables; 3132 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 3133 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 3134 __le64 l2_filter_id; 3135 __le32 dst_id; 3136 __le32 new_mirror_vnic_id; 3137 }; 3138 3139 /* Output (16 bytes) */ 3140 struct hwrm_cfa_l2_filter_cfg_output { 3141 __le16 error_code; 3142 __le16 req_type; 3143 __le16 seq_id; 3144 __le16 resp_len; 3145 __le32 unused_0; 3146 u8 unused_1; 3147 u8 unused_2; 3148 u8 unused_3; 3149 u8 valid; 3150 }; 3151 3152 /* hwrm_cfa_l2_set_rx_mask */ 3153 /* Input (40 bytes) */ 3154 struct hwrm_cfa_l2_set_rx_mask_input { 3155 __le16 req_type; 3156 __le16 cmpl_ring; 3157 __le16 seq_id; 3158 __le16 target_id; 3159 __le64 resp_addr; 3160 __le32 vnic_id; 3161 __le32 mask; 3162 #define CFA_L2_SET_RX_MASK_REQ_MASK_RESERVED 0x1UL 3163 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 3164 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 3165 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 3166 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 3167 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 3168 __le64 mc_tbl_addr; 3169 __le32 num_mc_entries; 3170 __le32 unused_0; 3171 }; 3172 3173 /* Output (16 bytes) */ 3174 struct hwrm_cfa_l2_set_rx_mask_output { 3175 __le16 error_code; 3176 __le16 req_type; 3177 __le16 seq_id; 3178 __le16 resp_len; 3179 __le32 unused_0; 3180 u8 unused_1; 3181 u8 unused_2; 3182 u8 unused_3; 3183 u8 valid; 3184 }; 3185 3186 /* hwrm_cfa_tunnel_filter_alloc */ 3187 /* Input (88 bytes) */ 3188 struct hwrm_cfa_tunnel_filter_alloc_input { 3189 __le16 req_type; 3190 __le16 cmpl_ring; 3191 __le16 seq_id; 3192 __le16 target_id; 3193 __le64 resp_addr; 3194 __le32 flags; 3195 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 3196 __le32 enables; 3197 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 3198 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 3199 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 3200 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 3201 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 3202 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 3203 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 3204 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 3205 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 3206 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 3207 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 3208 __le64 l2_filter_id; 3209 u8 l2_addr[6]; 3210 __le16 l2_ivlan; 3211 __le32 l3_addr[4]; 3212 __le32 t_l3_addr[4]; 3213 u8 l3_addr_type; 3214 u8 t_l3_addr_type; 3215 u8 tunnel_type; 3216 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0) 3217 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0) 3218 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0) 3219 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0) 3220 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0) 3221 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0) 3222 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0) 3223 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT (0x7UL << 0) 3224 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0) 3225 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0) 3226 u8 unused_0; 3227 __le32 vni; 3228 __le32 dst_vnic_id; 3229 __le32 mirror_vnic_id; 3230 }; 3231 3232 /* Output (24 bytes) */ 3233 struct hwrm_cfa_tunnel_filter_alloc_output { 3234 __le16 error_code; 3235 __le16 req_type; 3236 __le16 seq_id; 3237 __le16 resp_len; 3238 __le64 tunnel_filter_id; 3239 __le32 flow_id; 3240 u8 unused_0; 3241 u8 unused_1; 3242 u8 unused_2; 3243 u8 valid; 3244 }; 3245 3246 /* hwrm_cfa_tunnel_filter_free */ 3247 /* Input (24 bytes) */ 3248 struct hwrm_cfa_tunnel_filter_free_input { 3249 __le16 req_type; 3250 __le16 cmpl_ring; 3251 __le16 seq_id; 3252 __le16 target_id; 3253 __le64 resp_addr; 3254 __le64 tunnel_filter_id; 3255 }; 3256 3257 /* Output (16 bytes) */ 3258 struct hwrm_cfa_tunnel_filter_free_output { 3259 __le16 error_code; 3260 __le16 req_type; 3261 __le16 seq_id; 3262 __le16 resp_len; 3263 __le32 unused_0; 3264 u8 unused_1; 3265 u8 unused_2; 3266 u8 unused_3; 3267 u8 valid; 3268 }; 3269 3270 /* hwrm_cfa_encap_record_alloc */ 3271 /* Input (32 bytes) */ 3272 struct hwrm_cfa_encap_record_alloc_input { 3273 __le16 req_type; 3274 __le16 cmpl_ring; 3275 __le16 seq_id; 3276 __le16 target_id; 3277 __le64 resp_addr; 3278 __le32 flags; 3279 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 3280 u8 encap_type; 3281 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN (0x1UL << 0) 3282 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE (0x2UL << 0) 3283 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE (0x3UL << 0) 3284 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP (0x4UL << 0) 3285 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE (0x5UL << 0) 3286 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS (0x6UL << 0) 3287 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN (0x7UL << 0) 3288 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE (0x8UL << 0) 3289 u8 unused_0; 3290 __le16 unused_1; 3291 __le32 encap_data[16]; 3292 }; 3293 3294 /* Output (16 bytes) */ 3295 struct hwrm_cfa_encap_record_alloc_output { 3296 __le16 error_code; 3297 __le16 req_type; 3298 __le16 seq_id; 3299 __le16 resp_len; 3300 __le32 encap_record_id; 3301 u8 unused_0; 3302 u8 unused_1; 3303 u8 unused_2; 3304 u8 valid; 3305 }; 3306 3307 /* hwrm_cfa_encap_record_free */ 3308 /* Input (24 bytes) */ 3309 struct hwrm_cfa_encap_record_free_input { 3310 __le16 req_type; 3311 __le16 cmpl_ring; 3312 __le16 seq_id; 3313 __le16 target_id; 3314 __le64 resp_addr; 3315 __le32 encap_record_id; 3316 __le32 unused_0; 3317 }; 3318 3319 /* Output (16 bytes) */ 3320 struct hwrm_cfa_encap_record_free_output { 3321 __le16 error_code; 3322 __le16 req_type; 3323 __le16 seq_id; 3324 __le16 resp_len; 3325 __le32 unused_0; 3326 u8 unused_1; 3327 u8 unused_2; 3328 u8 unused_3; 3329 u8 valid; 3330 }; 3331 3332 /* hwrm_cfa_ntuple_filter_alloc */ 3333 /* Input (128 bytes) */ 3334 struct hwrm_cfa_ntuple_filter_alloc_input { 3335 __le16 req_type; 3336 __le16 cmpl_ring; 3337 __le16 seq_id; 3338 __le16 target_id; 3339 __le64 resp_addr; 3340 __le32 flags; 3341 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 3342 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 3343 __le32 enables; 3344 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 3345 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 3346 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 3347 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 3348 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 3349 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 3350 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 3351 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 3352 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 3353 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 3354 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 3355 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 3356 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 3357 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 3358 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 3359 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 3360 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 3361 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 3362 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 3363 __le64 l2_filter_id; 3364 u8 src_macaddr[6]; 3365 __be16 ethertype; 3366 u8 ip_addr_type; 3367 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN (0x0UL << 0) 3368 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 (0x4UL << 0) 3369 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 (0x6UL << 0) 3370 u8 ip_protocol; 3371 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN (0x0UL << 0) 3372 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP (0x6UL << 0) 3373 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP (0x11UL << 0) 3374 __le16 dst_id; 3375 __le16 mirror_vnic_id; 3376 u8 tunnel_type; 3377 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0) 3378 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0) 3379 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0) 3380 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0) 3381 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0) 3382 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0) 3383 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0) 3384 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT (0x7UL << 0) 3385 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0) 3386 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0) 3387 u8 pri_hint; 3388 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER (0x0UL << 0) 3389 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE (0x1UL << 0) 3390 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW (0x2UL << 0) 3391 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST (0x3UL << 0) 3392 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST (0x4UL << 0) 3393 __be32 src_ipaddr[4]; 3394 __be32 src_ipaddr_mask[4]; 3395 __be32 dst_ipaddr[4]; 3396 __be32 dst_ipaddr_mask[4]; 3397 __be16 src_port; 3398 __be16 src_port_mask; 3399 __be16 dst_port; 3400 __be16 dst_port_mask; 3401 __le64 ntuple_filter_id_hint; 3402 }; 3403 3404 /* Output (24 bytes) */ 3405 struct hwrm_cfa_ntuple_filter_alloc_output { 3406 __le16 error_code; 3407 __le16 req_type; 3408 __le16 seq_id; 3409 __le16 resp_len; 3410 __le64 ntuple_filter_id; 3411 __le32 flow_id; 3412 u8 unused_0; 3413 u8 unused_1; 3414 u8 unused_2; 3415 u8 valid; 3416 }; 3417 3418 /* hwrm_cfa_ntuple_filter_free */ 3419 /* Input (24 bytes) */ 3420 struct hwrm_cfa_ntuple_filter_free_input { 3421 __le16 req_type; 3422 __le16 cmpl_ring; 3423 __le16 seq_id; 3424 __le16 target_id; 3425 __le64 resp_addr; 3426 __le64 ntuple_filter_id; 3427 }; 3428 3429 /* Output (16 bytes) */ 3430 struct hwrm_cfa_ntuple_filter_free_output { 3431 __le16 error_code; 3432 __le16 req_type; 3433 __le16 seq_id; 3434 __le16 resp_len; 3435 __le32 unused_0; 3436 u8 unused_1; 3437 u8 unused_2; 3438 u8 unused_3; 3439 u8 valid; 3440 }; 3441 3442 /* hwrm_cfa_ntuple_filter_cfg */ 3443 /* Input (40 bytes) */ 3444 struct hwrm_cfa_ntuple_filter_cfg_input { 3445 __le16 req_type; 3446 __le16 cmpl_ring; 3447 __le16 seq_id; 3448 __le16 target_id; 3449 __le64 resp_addr; 3450 __le32 enables; 3451 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 3452 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 3453 __le32 unused_0; 3454 __le64 ntuple_filter_id; 3455 __le32 new_dst_id; 3456 __le32 new_mirror_vnic_id; 3457 }; 3458 3459 /* Output (16 bytes) */ 3460 struct hwrm_cfa_ntuple_filter_cfg_output { 3461 __le16 error_code; 3462 __le16 req_type; 3463 __le16 seq_id; 3464 __le16 resp_len; 3465 __le32 unused_0; 3466 u8 unused_1; 3467 u8 unused_2; 3468 u8 unused_3; 3469 u8 valid; 3470 }; 3471 3472 /* hwrm_tunnel_dst_port_query */ 3473 /* Input (24 bytes) */ 3474 struct hwrm_tunnel_dst_port_query_input { 3475 __le16 req_type; 3476 __le16 cmpl_ring; 3477 __le16 seq_id; 3478 __le16 target_id; 3479 __le64 resp_addr; 3480 u8 tunnel_type; 3481 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0) 3482 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0) 3483 u8 unused_0[7]; 3484 }; 3485 3486 /* Output (16 bytes) */ 3487 struct hwrm_tunnel_dst_port_query_output { 3488 __le16 error_code; 3489 __le16 req_type; 3490 __le16 seq_id; 3491 __le16 resp_len; 3492 __le16 tunnel_dst_port_id; 3493 __be16 tunnel_dst_port_val; 3494 u8 unused_0; 3495 u8 unused_1; 3496 u8 unused_2; 3497 u8 valid; 3498 }; 3499 3500 /* hwrm_tunnel_dst_port_alloc */ 3501 /* Input (24 bytes) */ 3502 struct hwrm_tunnel_dst_port_alloc_input { 3503 __le16 req_type; 3504 __le16 cmpl_ring; 3505 __le16 seq_id; 3506 __le16 target_id; 3507 __le64 resp_addr; 3508 u8 tunnel_type; 3509 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0) 3510 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0) 3511 u8 unused_0; 3512 __be16 tunnel_dst_port_val; 3513 __le32 unused_1; 3514 }; 3515 3516 /* Output (16 bytes) */ 3517 struct hwrm_tunnel_dst_port_alloc_output { 3518 __le16 error_code; 3519 __le16 req_type; 3520 __le16 seq_id; 3521 __le16 resp_len; 3522 __le16 tunnel_dst_port_id; 3523 u8 unused_0; 3524 u8 unused_1; 3525 u8 unused_2; 3526 u8 unused_3; 3527 u8 unused_4; 3528 u8 valid; 3529 }; 3530 3531 /* hwrm_tunnel_dst_port_free */ 3532 /* Input (24 bytes) */ 3533 struct hwrm_tunnel_dst_port_free_input { 3534 __le16 req_type; 3535 __le16 cmpl_ring; 3536 __le16 seq_id; 3537 __le16 target_id; 3538 __le64 resp_addr; 3539 u8 tunnel_type; 3540 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0) 3541 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0) 3542 u8 unused_0; 3543 __le16 tunnel_dst_port_id; 3544 __le32 unused_1; 3545 }; 3546 3547 /* Output (16 bytes) */ 3548 struct hwrm_tunnel_dst_port_free_output { 3549 __le16 error_code; 3550 __le16 req_type; 3551 __le16 seq_id; 3552 __le16 resp_len; 3553 __le32 unused_0; 3554 u8 unused_1; 3555 u8 unused_2; 3556 u8 unused_3; 3557 u8 valid; 3558 }; 3559 3560 /* hwrm_stat_ctx_alloc */ 3561 /* Input (32 bytes) */ 3562 struct hwrm_stat_ctx_alloc_input { 3563 __le16 req_type; 3564 __le16 cmpl_ring; 3565 __le16 seq_id; 3566 __le16 target_id; 3567 __le64 resp_addr; 3568 __le64 stats_dma_addr; 3569 __le32 update_period_ms; 3570 __le32 unused_0; 3571 }; 3572 3573 /* Output (16 bytes) */ 3574 struct hwrm_stat_ctx_alloc_output { 3575 __le16 error_code; 3576 __le16 req_type; 3577 __le16 seq_id; 3578 __le16 resp_len; 3579 __le32 stat_ctx_id; 3580 u8 unused_0; 3581 u8 unused_1; 3582 u8 unused_2; 3583 u8 valid; 3584 }; 3585 3586 /* hwrm_stat_ctx_free */ 3587 /* Input (24 bytes) */ 3588 struct hwrm_stat_ctx_free_input { 3589 __le16 req_type; 3590 __le16 cmpl_ring; 3591 __le16 seq_id; 3592 __le16 target_id; 3593 __le64 resp_addr; 3594 __le32 stat_ctx_id; 3595 __le32 unused_0; 3596 }; 3597 3598 /* Output (16 bytes) */ 3599 struct hwrm_stat_ctx_free_output { 3600 __le16 error_code; 3601 __le16 req_type; 3602 __le16 seq_id; 3603 __le16 resp_len; 3604 __le32 stat_ctx_id; 3605 u8 unused_0; 3606 u8 unused_1; 3607 u8 unused_2; 3608 u8 valid; 3609 }; 3610 3611 /* hwrm_stat_ctx_query */ 3612 /* Input (24 bytes) */ 3613 struct hwrm_stat_ctx_query_input { 3614 __le16 req_type; 3615 __le16 cmpl_ring; 3616 __le16 seq_id; 3617 __le16 target_id; 3618 __le64 resp_addr; 3619 __le32 stat_ctx_id; 3620 __le32 unused_0; 3621 }; 3622 3623 /* Output (176 bytes) */ 3624 struct hwrm_stat_ctx_query_output { 3625 __le16 error_code; 3626 __le16 req_type; 3627 __le16 seq_id; 3628 __le16 resp_len; 3629 __le64 tx_ucast_pkts; 3630 __le64 tx_mcast_pkts; 3631 __le64 tx_bcast_pkts; 3632 __le64 tx_err_pkts; 3633 __le64 tx_drop_pkts; 3634 __le64 tx_ucast_bytes; 3635 __le64 tx_mcast_bytes; 3636 __le64 tx_bcast_bytes; 3637 __le64 rx_ucast_pkts; 3638 __le64 rx_mcast_pkts; 3639 __le64 rx_bcast_pkts; 3640 __le64 rx_err_pkts; 3641 __le64 rx_drop_pkts; 3642 __le64 rx_ucast_bytes; 3643 __le64 rx_mcast_bytes; 3644 __le64 rx_bcast_bytes; 3645 __le64 rx_agg_pkts; 3646 __le64 rx_agg_bytes; 3647 __le64 rx_agg_events; 3648 __le64 rx_agg_aborts; 3649 __le32 unused_0; 3650 u8 unused_1; 3651 u8 unused_2; 3652 u8 unused_3; 3653 u8 valid; 3654 }; 3655 3656 /* hwrm_stat_ctx_clr_stats */ 3657 /* Input (24 bytes) */ 3658 struct hwrm_stat_ctx_clr_stats_input { 3659 __le16 req_type; 3660 __le16 cmpl_ring; 3661 __le16 seq_id; 3662 __le16 target_id; 3663 __le64 resp_addr; 3664 __le32 stat_ctx_id; 3665 __le32 unused_0; 3666 }; 3667 3668 /* Output (16 bytes) */ 3669 struct hwrm_stat_ctx_clr_stats_output { 3670 __le16 error_code; 3671 __le16 req_type; 3672 __le16 seq_id; 3673 __le16 resp_len; 3674 __le32 unused_0; 3675 u8 unused_1; 3676 u8 unused_2; 3677 u8 unused_3; 3678 u8 valid; 3679 }; 3680 3681 /* hwrm_fw_reset */ 3682 /* Input (24 bytes) */ 3683 struct hwrm_fw_reset_input { 3684 __le16 req_type; 3685 __le16 cmpl_ring; 3686 __le16 seq_id; 3687 __le16 target_id; 3688 __le64 resp_addr; 3689 u8 embedded_proc_type; 3690 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT (0x0UL << 0) 3691 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT (0x1UL << 0) 3692 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL (0x2UL << 0) 3693 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE (0x3UL << 0) 3694 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_RSVD (0x4UL << 0) 3695 u8 selfrst_status; 3696 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0) 3697 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0) 3698 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0) 3699 __le16 unused_0[3]; 3700 }; 3701 3702 /* Output (16 bytes) */ 3703 struct hwrm_fw_reset_output { 3704 __le16 error_code; 3705 __le16 req_type; 3706 __le16 seq_id; 3707 __le16 resp_len; 3708 u8 selfrst_status; 3709 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0) 3710 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0) 3711 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0) 3712 u8 unused_0; 3713 __le16 unused_1; 3714 u8 unused_2; 3715 u8 unused_3; 3716 u8 unused_4; 3717 u8 valid; 3718 }; 3719 3720 /* hwrm_fw_qstatus */ 3721 /* Input (24 bytes) */ 3722 struct hwrm_fw_qstatus_input { 3723 __le16 req_type; 3724 __le16 cmpl_ring; 3725 __le16 seq_id; 3726 __le16 target_id; 3727 __le64 resp_addr; 3728 u8 embedded_proc_type; 3729 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT (0x0UL << 0) 3730 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT (0x1UL << 0) 3731 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL (0x2UL << 0) 3732 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE (0x3UL << 0) 3733 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_RSVD (0x4UL << 0) 3734 u8 unused_0[7]; 3735 }; 3736 3737 /* Output (16 bytes) */ 3738 struct hwrm_fw_qstatus_output { 3739 __le16 error_code; 3740 __le16 req_type; 3741 __le16 seq_id; 3742 __le16 resp_len; 3743 u8 selfrst_status; 3744 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0) 3745 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0) 3746 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0) 3747 u8 unused_0; 3748 __le16 unused_1; 3749 u8 unused_2; 3750 u8 unused_3; 3751 u8 unused_4; 3752 u8 valid; 3753 }; 3754 3755 /* hwrm_exec_fwd_resp */ 3756 /* Input (128 bytes) */ 3757 struct hwrm_exec_fwd_resp_input { 3758 __le16 req_type; 3759 __le16 cmpl_ring; 3760 __le16 seq_id; 3761 __le16 target_id; 3762 __le64 resp_addr; 3763 __le32 encap_request[26]; 3764 __le16 encap_resp_target_id; 3765 __le16 unused_0[3]; 3766 }; 3767 3768 /* Output (16 bytes) */ 3769 struct hwrm_exec_fwd_resp_output { 3770 __le16 error_code; 3771 __le16 req_type; 3772 __le16 seq_id; 3773 __le16 resp_len; 3774 __le32 unused_0; 3775 u8 unused_1; 3776 u8 unused_2; 3777 u8 unused_3; 3778 u8 valid; 3779 }; 3780 3781 /* hwrm_reject_fwd_resp */ 3782 /* Input (128 bytes) */ 3783 struct hwrm_reject_fwd_resp_input { 3784 __le16 req_type; 3785 __le16 cmpl_ring; 3786 __le16 seq_id; 3787 __le16 target_id; 3788 __le64 resp_addr; 3789 __le32 encap_request[26]; 3790 __le16 encap_resp_target_id; 3791 __le16 unused_0[3]; 3792 }; 3793 3794 /* Output (16 bytes) */ 3795 struct hwrm_reject_fwd_resp_output { 3796 __le16 error_code; 3797 __le16 req_type; 3798 __le16 seq_id; 3799 __le16 resp_len; 3800 __le32 unused_0; 3801 u8 unused_1; 3802 u8 unused_2; 3803 u8 unused_3; 3804 u8 valid; 3805 }; 3806 3807 /* hwrm_fwd_resp */ 3808 /* Input (40 bytes) */ 3809 struct hwrm_fwd_resp_input { 3810 __le16 req_type; 3811 __le16 cmpl_ring; 3812 __le16 seq_id; 3813 __le16 target_id; 3814 __le64 resp_addr; 3815 __le16 encap_resp_target_id; 3816 __le16 encap_resp_cmpl_ring; 3817 __le16 encap_resp_len; 3818 u8 unused_0; 3819 u8 unused_1; 3820 __le64 encap_resp_addr; 3821 __le32 encap_resp[24]; 3822 }; 3823 3824 /* Output (16 bytes) */ 3825 struct hwrm_fwd_resp_output { 3826 __le16 error_code; 3827 __le16 req_type; 3828 __le16 seq_id; 3829 __le16 resp_len; 3830 __le32 unused_0; 3831 u8 unused_1; 3832 u8 unused_2; 3833 u8 unused_3; 3834 u8 valid; 3835 }; 3836 3837 /* hwrm_fwd_async_event_cmpl */ 3838 /* Input (32 bytes) */ 3839 struct hwrm_fwd_async_event_cmpl_input { 3840 __le16 req_type; 3841 __le16 cmpl_ring; 3842 __le16 seq_id; 3843 __le16 target_id; 3844 __le64 resp_addr; 3845 __le16 encap_async_event_target_id; 3846 u8 unused_0; 3847 u8 unused_1; 3848 u8 unused_2[3]; 3849 u8 unused_3; 3850 __le32 encap_async_event_cmpl[4]; 3851 }; 3852 3853 /* Output (16 bytes) */ 3854 struct hwrm_fwd_async_event_cmpl_output { 3855 __le16 error_code; 3856 __le16 req_type; 3857 __le16 seq_id; 3858 __le16 resp_len; 3859 __le32 unused_0; 3860 u8 unused_1; 3861 u8 unused_2; 3862 u8 unused_3; 3863 u8 valid; 3864 }; 3865 3866 /* hwrm_temp_monitor_query */ 3867 /* Input (16 bytes) */ 3868 struct hwrm_temp_monitor_query_input { 3869 __le16 req_type; 3870 __le16 cmpl_ring; 3871 __le16 seq_id; 3872 __le16 target_id; 3873 __le64 resp_addr; 3874 }; 3875 3876 /* Output (16 bytes) */ 3877 struct hwrm_temp_monitor_query_output { 3878 __le16 error_code; 3879 __le16 req_type; 3880 __le16 seq_id; 3881 __le16 resp_len; 3882 u8 temp; 3883 u8 unused_0; 3884 __le16 unused_1; 3885 u8 unused_2; 3886 u8 unused_3; 3887 u8 unused_4; 3888 u8 valid; 3889 }; 3890 3891 /* hwrm_nvm_raw_write_blk */ 3892 /* Input (32 bytes) */ 3893 struct hwrm_nvm_raw_write_blk_input { 3894 __le16 req_type; 3895 __le16 cmpl_ring; 3896 __le16 seq_id; 3897 __le16 target_id; 3898 __le64 resp_addr; 3899 __le64 host_src_addr; 3900 __le32 dest_addr; 3901 __le32 len; 3902 }; 3903 3904 /* Output (16 bytes) */ 3905 struct hwrm_nvm_raw_write_blk_output { 3906 __le16 error_code; 3907 __le16 req_type; 3908 __le16 seq_id; 3909 __le16 resp_len; 3910 __le32 unused_0; 3911 u8 unused_1; 3912 u8 unused_2; 3913 u8 unused_3; 3914 u8 valid; 3915 }; 3916 3917 /* hwrm_nvm_read */ 3918 /* Input (40 bytes) */ 3919 struct hwrm_nvm_read_input { 3920 __le16 req_type; 3921 __le16 cmpl_ring; 3922 __le16 seq_id; 3923 __le16 target_id; 3924 __le64 resp_addr; 3925 __le64 host_dest_addr; 3926 __le16 dir_idx; 3927 u8 unused_0; 3928 u8 unused_1; 3929 __le32 offset; 3930 __le32 len; 3931 __le32 unused_2; 3932 }; 3933 3934 /* Output (16 bytes) */ 3935 struct hwrm_nvm_read_output { 3936 __le16 error_code; 3937 __le16 req_type; 3938 __le16 seq_id; 3939 __le16 resp_len; 3940 __le32 unused_0; 3941 u8 unused_1; 3942 u8 unused_2; 3943 u8 unused_3; 3944 u8 valid; 3945 }; 3946 3947 /* hwrm_nvm_raw_dump */ 3948 /* Input (32 bytes) */ 3949 struct hwrm_nvm_raw_dump_input { 3950 __le16 req_type; 3951 __le16 cmpl_ring; 3952 __le16 seq_id; 3953 __le16 target_id; 3954 __le64 resp_addr; 3955 __le64 host_dest_addr; 3956 __le32 offset; 3957 __le32 len; 3958 }; 3959 3960 /* Output (16 bytes) */ 3961 struct hwrm_nvm_raw_dump_output { 3962 __le16 error_code; 3963 __le16 req_type; 3964 __le16 seq_id; 3965 __le16 resp_len; 3966 __le32 unused_0; 3967 u8 unused_1; 3968 u8 unused_2; 3969 u8 unused_3; 3970 u8 valid; 3971 }; 3972 3973 /* hwrm_nvm_get_dir_entries */ 3974 /* Input (24 bytes) */ 3975 struct hwrm_nvm_get_dir_entries_input { 3976 __le16 req_type; 3977 __le16 cmpl_ring; 3978 __le16 seq_id; 3979 __le16 target_id; 3980 __le64 resp_addr; 3981 __le64 host_dest_addr; 3982 }; 3983 3984 /* Output (16 bytes) */ 3985 struct hwrm_nvm_get_dir_entries_output { 3986 __le16 error_code; 3987 __le16 req_type; 3988 __le16 seq_id; 3989 __le16 resp_len; 3990 __le32 unused_0; 3991 u8 unused_1; 3992 u8 unused_2; 3993 u8 unused_3; 3994 u8 valid; 3995 }; 3996 3997 /* hwrm_nvm_get_dir_info */ 3998 /* Input (16 bytes) */ 3999 struct hwrm_nvm_get_dir_info_input { 4000 __le16 req_type; 4001 __le16 cmpl_ring; 4002 __le16 seq_id; 4003 __le16 target_id; 4004 __le64 resp_addr; 4005 }; 4006 4007 /* Output (24 bytes) */ 4008 struct hwrm_nvm_get_dir_info_output { 4009 __le16 error_code; 4010 __le16 req_type; 4011 __le16 seq_id; 4012 __le16 resp_len; 4013 __le32 entries; 4014 __le32 entry_length; 4015 __le32 unused_0; 4016 u8 unused_1; 4017 u8 unused_2; 4018 u8 unused_3; 4019 u8 valid; 4020 }; 4021 4022 /* hwrm_nvm_write */ 4023 /* Input (48 bytes) */ 4024 struct hwrm_nvm_write_input { 4025 __le16 req_type; 4026 __le16 cmpl_ring; 4027 __le16 seq_id; 4028 __le16 target_id; 4029 __le64 resp_addr; 4030 __le64 host_src_addr; 4031 __le16 dir_type; 4032 __le16 dir_ordinal; 4033 __le16 dir_ext; 4034 __le16 dir_attr; 4035 __le32 dir_data_length; 4036 __le16 option; 4037 __le16 flags; 4038 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 4039 __le32 dir_item_length; 4040 __le32 unused_0; 4041 }; 4042 4043 /* Output (16 bytes) */ 4044 struct hwrm_nvm_write_output { 4045 __le16 error_code; 4046 __le16 req_type; 4047 __le16 seq_id; 4048 __le16 resp_len; 4049 __le32 dir_item_length; 4050 __le16 dir_idx; 4051 u8 unused_0; 4052 u8 valid; 4053 }; 4054 4055 /* hwrm_nvm_modify */ 4056 /* Input (40 bytes) */ 4057 struct hwrm_nvm_modify_input { 4058 __le16 req_type; 4059 __le16 cmpl_ring; 4060 __le16 seq_id; 4061 __le16 target_id; 4062 __le64 resp_addr; 4063 __le64 host_src_addr; 4064 __le16 dir_idx; 4065 u8 unused_0; 4066 u8 unused_1; 4067 __le32 offset; 4068 __le32 len; 4069 __le32 unused_2; 4070 }; 4071 4072 /* Output (16 bytes) */ 4073 struct hwrm_nvm_modify_output { 4074 __le16 error_code; 4075 __le16 req_type; 4076 __le16 seq_id; 4077 __le16 resp_len; 4078 __le32 unused_0; 4079 u8 unused_1; 4080 u8 unused_2; 4081 u8 unused_3; 4082 u8 valid; 4083 }; 4084 4085 /* hwrm_nvm_find_dir_entry */ 4086 /* Input (32 bytes) */ 4087 struct hwrm_nvm_find_dir_entry_input { 4088 __le16 req_type; 4089 __le16 cmpl_ring; 4090 __le16 seq_id; 4091 __le16 target_id; 4092 __le64 resp_addr; 4093 __le32 enables; 4094 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 4095 __le16 dir_idx; 4096 __le16 dir_type; 4097 __le16 dir_ordinal; 4098 __le16 dir_ext; 4099 u8 opt_ordinal; 4100 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 4101 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 4102 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ (0x0UL << 0) 4103 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE (0x1UL << 0) 4104 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT (0x2UL << 0) 4105 u8 unused_1[3]; 4106 }; 4107 4108 /* Output (32 bytes) */ 4109 struct hwrm_nvm_find_dir_entry_output { 4110 __le16 error_code; 4111 __le16 req_type; 4112 __le16 seq_id; 4113 __le16 resp_len; 4114 __le32 dir_item_length; 4115 __le32 dir_data_length; 4116 __le32 fw_ver; 4117 __le16 dir_ordinal; 4118 __le16 dir_idx; 4119 __le32 unused_0; 4120 u8 unused_1; 4121 u8 unused_2; 4122 u8 unused_3; 4123 u8 valid; 4124 }; 4125 4126 /* hwrm_nvm_erase_dir_entry */ 4127 /* Input (24 bytes) */ 4128 struct hwrm_nvm_erase_dir_entry_input { 4129 __le16 req_type; 4130 __le16 cmpl_ring; 4131 __le16 seq_id; 4132 __le16 target_id; 4133 __le64 resp_addr; 4134 __le16 dir_idx; 4135 __le16 unused_0[3]; 4136 }; 4137 4138 /* Output (16 bytes) */ 4139 struct hwrm_nvm_erase_dir_entry_output { 4140 __le16 error_code; 4141 __le16 req_type; 4142 __le16 seq_id; 4143 __le16 resp_len; 4144 __le32 unused_0; 4145 u8 unused_1; 4146 u8 unused_2; 4147 u8 unused_3; 4148 u8 valid; 4149 }; 4150 4151 /* hwrm_nvm_get_dev_info */ 4152 /* Input (16 bytes) */ 4153 struct hwrm_nvm_get_dev_info_input { 4154 __le16 req_type; 4155 __le16 cmpl_ring; 4156 __le16 seq_id; 4157 __le16 target_id; 4158 __le64 resp_addr; 4159 }; 4160 4161 /* Output (32 bytes) */ 4162 struct hwrm_nvm_get_dev_info_output { 4163 __le16 error_code; 4164 __le16 req_type; 4165 __le16 seq_id; 4166 __le16 resp_len; 4167 __le16 manufacturer_id; 4168 __le16 device_id; 4169 __le32 sector_size; 4170 __le32 nvram_size; 4171 __le32 reserved_size; 4172 __le32 available_size; 4173 u8 unused_0; 4174 u8 unused_1; 4175 u8 unused_2; 4176 u8 valid; 4177 }; 4178 4179 /* hwrm_nvm_mod_dir_entry */ 4180 /* Input (32 bytes) */ 4181 struct hwrm_nvm_mod_dir_entry_input { 4182 __le16 req_type; 4183 __le16 cmpl_ring; 4184 __le16 seq_id; 4185 __le16 target_id; 4186 __le64 resp_addr; 4187 __le32 enables; 4188 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 4189 __le16 dir_idx; 4190 __le16 dir_ordinal; 4191 __le16 dir_ext; 4192 __le16 dir_attr; 4193 __le32 checksum; 4194 }; 4195 4196 /* Output (16 bytes) */ 4197 struct hwrm_nvm_mod_dir_entry_output { 4198 __le16 error_code; 4199 __le16 req_type; 4200 __le16 seq_id; 4201 __le16 resp_len; 4202 __le32 unused_0; 4203 u8 unused_1; 4204 u8 unused_2; 4205 u8 unused_3; 4206 u8 valid; 4207 }; 4208 4209 /* hwrm_nvm_verify_update */ 4210 /* Input (24 bytes) */ 4211 struct hwrm_nvm_verify_update_input { 4212 __le16 req_type; 4213 __le16 cmpl_ring; 4214 __le16 seq_id; 4215 __le16 target_id; 4216 __le64 resp_addr; 4217 __le16 dir_type; 4218 __le16 dir_ordinal; 4219 __le16 dir_ext; 4220 __le16 unused_0; 4221 }; 4222 4223 /* Output (16 bytes) */ 4224 struct hwrm_nvm_verify_update_output { 4225 __le16 error_code; 4226 __le16 req_type; 4227 __le16 seq_id; 4228 __le16 resp_len; 4229 __le32 unused_0; 4230 u8 unused_1; 4231 u8 unused_2; 4232 u8 unused_3; 4233 u8 valid; 4234 }; 4235 4236 #endif 4237