1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/bitops.h> 12 #include <linux/ctype.h> 13 #include <linux/stringify.h> 14 #include <linux/ethtool.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/linkmode.h> 17 #include <linux/interrupt.h> 18 #include <linux/pci.h> 19 #include <linux/etherdevice.h> 20 #include <linux/crc32.h> 21 #include <linux/firmware.h> 22 #include <linux/utsname.h> 23 #include <linux/time.h> 24 #include <linux/ptp_clock_kernel.h> 25 #include <linux/net_tstamp.h> 26 #include <linux/timecounter.h> 27 #include <net/netdev_queues.h> 28 #include <net/netlink.h> 29 #include <linux/bnxt/hsi.h> 30 #include "bnxt.h" 31 #include "bnxt_hwrm.h" 32 #include "bnxt_ulp.h" 33 #include "bnxt_xdp.h" 34 #include "bnxt_ptp.h" 35 #include "bnxt_ethtool.h" 36 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 37 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 38 #include "bnxt_coredump.h" 39 40 #define BNXT_NVM_ERR_MSG(dev, extack, msg) \ 41 do { \ 42 if (extack) \ 43 NL_SET_ERR_MSG_MOD(extack, msg); \ 44 netdev_err(dev, "%s\n", msg); \ 45 } while (0) 46 47 static u32 bnxt_get_msglevel(struct net_device *dev) 48 { 49 struct bnxt *bp = netdev_priv(dev); 50 51 return bp->msg_enable; 52 } 53 54 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 55 { 56 struct bnxt *bp = netdev_priv(dev); 57 58 bp->msg_enable = value; 59 } 60 61 static int bnxt_get_coalesce(struct net_device *dev, 62 struct ethtool_coalesce *coal, 63 struct kernel_ethtool_coalesce *kernel_coal, 64 struct netlink_ext_ack *extack) 65 { 66 struct bnxt *bp = netdev_priv(dev); 67 struct bnxt_coal *hw_coal; 68 u16 mult; 69 70 memset(coal, 0, sizeof(*coal)); 71 72 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 73 74 hw_coal = &bp->rx_coal; 75 mult = hw_coal->bufs_per_record; 76 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 77 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 78 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 79 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 80 if (hw_coal->flags & 81 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 82 kernel_coal->use_cqe_mode_rx = true; 83 84 hw_coal = &bp->tx_coal; 85 mult = hw_coal->bufs_per_record; 86 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 87 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 88 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 89 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 90 if (hw_coal->flags & 91 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 92 kernel_coal->use_cqe_mode_tx = true; 93 94 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 95 96 return 0; 97 } 98 99 static int bnxt_set_coalesce(struct net_device *dev, 100 struct ethtool_coalesce *coal, 101 struct kernel_ethtool_coalesce *kernel_coal, 102 struct netlink_ext_ack *extack) 103 { 104 struct bnxt *bp = netdev_priv(dev); 105 bool update_stats = false; 106 struct bnxt_coal *hw_coal; 107 int rc = 0; 108 u16 mult; 109 110 if (coal->use_adaptive_rx_coalesce) { 111 bp->flags |= BNXT_FLAG_DIM; 112 } else { 113 if (bp->flags & BNXT_FLAG_DIM) { 114 bp->flags &= ~(BNXT_FLAG_DIM); 115 goto reset_coalesce; 116 } 117 } 118 119 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) && 120 !(bp->coal_cap.cmpl_params & 121 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)) 122 return -EOPNOTSUPP; 123 124 hw_coal = &bp->rx_coal; 125 mult = hw_coal->bufs_per_record; 126 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 127 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 128 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 129 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 130 hw_coal->flags &= 131 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 132 if (kernel_coal->use_cqe_mode_rx) 133 hw_coal->flags |= 134 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 135 136 hw_coal = &bp->tx_coal; 137 mult = hw_coal->bufs_per_record; 138 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 139 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 140 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 141 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 142 hw_coal->flags &= 143 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 144 if (kernel_coal->use_cqe_mode_tx) 145 hw_coal->flags |= 146 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 147 148 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 149 u32 stats_ticks = coal->stats_block_coalesce_usecs; 150 151 /* Allow 0, which means disable. */ 152 if (stats_ticks) 153 stats_ticks = clamp_t(u32, stats_ticks, 154 BNXT_MIN_STATS_COAL_TICKS, 155 BNXT_MAX_STATS_COAL_TICKS); 156 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 157 bp->stats_coal_ticks = stats_ticks; 158 if (bp->stats_coal_ticks) 159 bp->current_interval = 160 bp->stats_coal_ticks * HZ / 1000000; 161 else 162 bp->current_interval = BNXT_TIMER_INTERVAL; 163 update_stats = true; 164 } 165 166 reset_coalesce: 167 if (test_bit(BNXT_STATE_OPEN, &bp->state)) { 168 if (update_stats) { 169 bnxt_close_nic(bp, true, false); 170 rc = bnxt_open_nic(bp, true, false); 171 } else { 172 rc = bnxt_hwrm_set_coal(bp); 173 } 174 } 175 176 return rc; 177 } 178 179 static const char * const bnxt_ring_rx_stats_str[] = { 180 "rx_ucast_packets", 181 "rx_mcast_packets", 182 "rx_bcast_packets", 183 "rx_discards", 184 "rx_errors", 185 "rx_ucast_bytes", 186 "rx_mcast_bytes", 187 "rx_bcast_bytes", 188 }; 189 190 static const char * const bnxt_ring_tx_stats_str[] = { 191 "tx_ucast_packets", 192 "tx_mcast_packets", 193 "tx_bcast_packets", 194 "tx_errors", 195 "tx_discards", 196 "tx_ucast_bytes", 197 "tx_mcast_bytes", 198 "tx_bcast_bytes", 199 }; 200 201 static const char * const bnxt_ring_tpa_stats_str[] = { 202 "tpa_packets", 203 "tpa_bytes", 204 "tpa_events", 205 "tpa_aborts", 206 }; 207 208 static const char * const bnxt_ring_tpa2_stats_str[] = { 209 "rx_tpa_eligible_pkt", 210 "rx_tpa_eligible_bytes", 211 "rx_tpa_pkt", 212 "rx_tpa_bytes", 213 "rx_tpa_errors", 214 "rx_tpa_events", 215 }; 216 217 static const char * const bnxt_rx_sw_stats_str[] = { 218 "rx_l4_csum_errors", 219 "rx_resets", 220 "rx_buf_errors", 221 }; 222 223 static const char * const bnxt_cmn_sw_stats_str[] = { 224 "missed_irqs", 225 }; 226 227 #define BNXT_RX_STATS_ENTRY(counter) \ 228 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 229 230 #define BNXT_TX_STATS_ENTRY(counter) \ 231 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 232 233 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 234 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 235 236 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 237 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 238 239 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 240 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 241 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 242 243 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 244 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 245 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 246 247 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 248 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 249 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 250 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 251 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 252 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 253 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 254 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 255 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 256 257 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 258 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 259 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 260 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 261 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 262 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 263 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 264 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 265 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 266 267 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 268 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 269 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 270 271 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 272 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 273 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 274 275 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 276 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 277 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 278 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 279 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 280 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 281 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 282 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 283 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 284 285 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 286 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 287 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 288 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 289 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 290 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 291 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 292 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 293 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 294 295 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 296 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 297 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 298 299 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 300 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 301 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 302 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 303 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 304 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 305 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 306 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 307 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 308 309 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 310 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 311 __stringify(counter##_pri##n) } 312 313 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 314 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 315 __stringify(counter##_pri##n) } 316 317 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 318 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 319 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 320 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 321 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 322 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 323 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 324 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 325 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 326 327 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 328 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 329 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 330 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 331 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 332 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 333 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 334 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 335 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 336 337 enum { 338 RX_TOTAL_DISCARDS, 339 TX_TOTAL_DISCARDS, 340 RX_NETPOLL_DISCARDS, 341 }; 342 343 static const char *const bnxt_ring_drv_stats_arr[] = { 344 "rx_total_l4_csum_errors", 345 "rx_total_resets", 346 "rx_total_buf_errors", 347 "rx_total_oom_discards", 348 "rx_total_netpoll_discards", 349 "rx_total_ring_discards", 350 "tx_total_resets", 351 "tx_total_ring_discards", 352 "total_missed_irqs", 353 }; 354 355 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str) 356 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str) 357 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str) 358 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str) 359 360 static const struct { 361 long offset; 362 char string[ETH_GSTRING_LEN]; 363 } bnxt_port_stats_arr[] = { 364 BNXT_RX_STATS_ENTRY(rx_64b_frames), 365 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 366 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 367 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 368 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 369 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 370 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 371 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 372 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 373 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 374 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 375 BNXT_RX_STATS_ENTRY(rx_total_frames), 376 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 377 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 378 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 379 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 380 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 381 BNXT_RX_STATS_ENTRY(rx_pause_frames), 382 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 383 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 384 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 385 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 386 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 387 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 388 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 389 BNXT_RX_STATS_ENTRY(rx_good_frames), 390 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 391 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 392 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 393 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 394 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 395 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 396 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 397 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 398 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 399 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 400 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 401 BNXT_RX_STATS_ENTRY(rx_bytes), 402 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 403 BNXT_RX_STATS_ENTRY(rx_runt_frames), 404 BNXT_RX_STATS_ENTRY(rx_stat_discard), 405 BNXT_RX_STATS_ENTRY(rx_stat_err), 406 407 BNXT_TX_STATS_ENTRY(tx_64b_frames), 408 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 409 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 410 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 411 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 412 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 413 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 414 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 415 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 416 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 417 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 418 BNXT_TX_STATS_ENTRY(tx_good_frames), 419 BNXT_TX_STATS_ENTRY(tx_total_frames), 420 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 421 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 422 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 423 BNXT_TX_STATS_ENTRY(tx_pause_frames), 424 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 425 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 426 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 427 BNXT_TX_STATS_ENTRY(tx_err), 428 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 429 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 430 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 431 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 432 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 433 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 434 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 435 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 436 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 437 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 438 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 439 BNXT_TX_STATS_ENTRY(tx_total_collisions), 440 BNXT_TX_STATS_ENTRY(tx_bytes), 441 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 442 BNXT_TX_STATS_ENTRY(tx_stat_discard), 443 BNXT_TX_STATS_ENTRY(tx_stat_error), 444 }; 445 446 static const struct { 447 long offset; 448 char string[ETH_GSTRING_LEN]; 449 } bnxt_port_stats_ext_arr[] = { 450 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 451 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 452 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 453 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 454 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 455 BNXT_RX_STATS_EXT_COS_ENTRIES, 456 BNXT_RX_STATS_EXT_PFC_ENTRIES, 457 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 458 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 459 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 460 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 461 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 462 BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks), 463 BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks), 464 BNXT_RX_STATS_EXT_ENTRY(rx_filter_miss), 465 }; 466 467 static const struct { 468 long offset; 469 char string[ETH_GSTRING_LEN]; 470 } bnxt_tx_port_stats_ext_arr[] = { 471 BNXT_TX_STATS_EXT_COS_ENTRIES, 472 BNXT_TX_STATS_EXT_PFC_ENTRIES, 473 }; 474 475 static const struct { 476 long base_off; 477 char string[ETH_GSTRING_LEN]; 478 } bnxt_rx_bytes_pri_arr[] = { 479 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 480 }; 481 482 static const struct { 483 long base_off; 484 char string[ETH_GSTRING_LEN]; 485 } bnxt_rx_pkts_pri_arr[] = { 486 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 487 }; 488 489 static const struct { 490 long base_off; 491 char string[ETH_GSTRING_LEN]; 492 } bnxt_tx_bytes_pri_arr[] = { 493 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 494 }; 495 496 static const struct { 497 long base_off; 498 char string[ETH_GSTRING_LEN]; 499 } bnxt_tx_pkts_pri_arr[] = { 500 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 501 }; 502 503 #define BNXT_NUM_RING_DRV_STATS ARRAY_SIZE(bnxt_ring_drv_stats_arr) 504 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 505 #define BNXT_NUM_STATS_PRI \ 506 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 507 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 508 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 509 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 510 511 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 512 { 513 if (BNXT_SUPPORTS_TPA(bp)) { 514 if (bp->max_tpa_v2) { 515 if (BNXT_CHIP_P5(bp)) 516 return BNXT_NUM_TPA_RING_STATS_P5; 517 return BNXT_NUM_TPA_RING_STATS_P7; 518 } 519 return BNXT_NUM_TPA_RING_STATS; 520 } 521 return 0; 522 } 523 524 static int bnxt_get_num_ring_stats(struct bnxt *bp) 525 { 526 int rx, tx, cmn; 527 528 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS + 529 bnxt_get_num_tpa_ring_stats(bp); 530 tx = NUM_RING_TX_HW_STATS; 531 cmn = NUM_RING_CMN_SW_STATS; 532 return rx * bp->rx_nr_rings + 533 tx * (bp->tx_nr_rings_xdp + bp->tx_nr_rings_per_tc) + 534 cmn * bp->cp_nr_rings; 535 } 536 537 static int bnxt_get_num_stats(struct bnxt *bp) 538 { 539 int num_stats = bnxt_get_num_ring_stats(bp); 540 int len; 541 542 num_stats += BNXT_NUM_RING_DRV_STATS; 543 544 if (bp->flags & BNXT_FLAG_PORT_STATS) 545 num_stats += BNXT_NUM_PORT_STATS; 546 547 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 548 len = min_t(int, bp->fw_rx_stats_ext_size, 549 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 550 num_stats += len; 551 len = min_t(int, bp->fw_tx_stats_ext_size, 552 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 553 num_stats += len; 554 if (bp->pri2cos_valid) 555 num_stats += BNXT_NUM_STATS_PRI; 556 } 557 558 return num_stats; 559 } 560 561 static int bnxt_get_sset_count(struct net_device *dev, int sset) 562 { 563 struct bnxt *bp = netdev_priv(dev); 564 565 switch (sset) { 566 case ETH_SS_STATS: 567 return bnxt_get_num_stats(bp); 568 case ETH_SS_TEST: 569 if (!bp->num_tests) 570 return -EOPNOTSUPP; 571 return bp->num_tests; 572 default: 573 return -EOPNOTSUPP; 574 } 575 } 576 577 static bool is_rx_ring(struct bnxt *bp, int ring_num) 578 { 579 return ring_num < bp->rx_nr_rings; 580 } 581 582 static bool is_tx_ring(struct bnxt *bp, int ring_num) 583 { 584 int tx_base = 0; 585 586 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 587 tx_base = bp->rx_nr_rings; 588 589 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings)) 590 return true; 591 return false; 592 } 593 594 static void bnxt_get_ethtool_stats(struct net_device *dev, 595 struct ethtool_stats *stats, u64 *buf) 596 { 597 struct bnxt_total_ring_drv_stats ring_drv_stats = {0}; 598 struct bnxt *bp = netdev_priv(dev); 599 u64 *curr, *prev; 600 u32 tpa_stats; 601 u32 i, j = 0; 602 603 if (!bp->bnapi) { 604 j += bnxt_get_num_ring_stats(bp); 605 goto skip_ring_stats; 606 } 607 608 tpa_stats = bnxt_get_num_tpa_ring_stats(bp); 609 for (i = 0; i < bp->cp_nr_rings; i++) { 610 struct bnxt_napi *bnapi = bp->bnapi[i]; 611 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 612 u64 *sw_stats = cpr->stats.sw_stats; 613 u64 *sw; 614 int k; 615 616 if (is_rx_ring(bp, i)) { 617 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++) 618 buf[j] = sw_stats[k]; 619 } 620 if (is_tx_ring(bp, i)) { 621 k = NUM_RING_RX_HW_STATS; 622 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 623 j++, k++) 624 buf[j] = sw_stats[k]; 625 } 626 if (!tpa_stats || !is_rx_ring(bp, i)) 627 goto skip_tpa_ring_stats; 628 629 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 630 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS + 631 tpa_stats; j++, k++) 632 buf[j] = sw_stats[k]; 633 634 skip_tpa_ring_stats: 635 sw = (u64 *)&cpr->sw_stats->rx; 636 if (is_rx_ring(bp, i)) { 637 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++) 638 buf[j] = sw[k]; 639 } 640 641 sw = (u64 *)&cpr->sw_stats->cmn; 642 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++) 643 buf[j] = sw[k]; 644 } 645 646 bnxt_get_ring_drv_stats(bp, &ring_drv_stats); 647 648 skip_ring_stats: 649 curr = &ring_drv_stats.rx_total_l4_csum_errors; 650 prev = &bp->ring_drv_stats_prev.rx_total_l4_csum_errors; 651 for (i = 0; i < BNXT_NUM_RING_DRV_STATS; i++, j++, curr++, prev++) 652 buf[j] = *curr + *prev; 653 654 if (bp->flags & BNXT_FLAG_PORT_STATS) { 655 u64 *port_stats = bp->port_stats.sw_stats; 656 657 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) 658 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset); 659 } 660 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 661 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats; 662 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats; 663 u32 len; 664 665 len = min_t(u32, bp->fw_rx_stats_ext_size, 666 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 667 for (i = 0; i < len; i++, j++) { 668 buf[j] = *(rx_port_stats_ext + 669 bnxt_port_stats_ext_arr[i].offset); 670 } 671 len = min_t(u32, bp->fw_tx_stats_ext_size, 672 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 673 for (i = 0; i < len; i++, j++) { 674 buf[j] = *(tx_port_stats_ext + 675 bnxt_tx_port_stats_ext_arr[i].offset); 676 } 677 if (bp->pri2cos_valid) { 678 for (i = 0; i < 8; i++, j++) { 679 long n = bnxt_rx_bytes_pri_arr[i].base_off + 680 bp->pri2cos_idx[i]; 681 682 buf[j] = *(rx_port_stats_ext + n); 683 } 684 for (i = 0; i < 8; i++, j++) { 685 long n = bnxt_rx_pkts_pri_arr[i].base_off + 686 bp->pri2cos_idx[i]; 687 688 buf[j] = *(rx_port_stats_ext + n); 689 } 690 for (i = 0; i < 8; i++, j++) { 691 u8 cos_idx = bp->pri2cos_idx[i]; 692 long n; 693 694 n = bnxt_tx_bytes_pri_arr[i].base_off + cos_idx; 695 buf[j] = *(tx_port_stats_ext + n); 696 if (bp->cos0_cos1_shared && !cos_idx) 697 buf[j] += *(tx_port_stats_ext + n + 1); 698 } 699 for (i = 0; i < 8; i++, j++) { 700 u8 cos_idx = bp->pri2cos_idx[i]; 701 long n; 702 703 n = bnxt_tx_pkts_pri_arr[i].base_off + cos_idx; 704 buf[j] = *(tx_port_stats_ext + n); 705 if (bp->cos0_cos1_shared && !cos_idx) 706 buf[j] += *(tx_port_stats_ext + n + 1); 707 } 708 } 709 } 710 } 711 712 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 713 { 714 struct bnxt *bp = netdev_priv(dev); 715 u32 i, j, num_str; 716 const char *str; 717 718 switch (stringset) { 719 case ETH_SS_STATS: 720 for (i = 0; i < bp->cp_nr_rings; i++) { 721 if (is_rx_ring(bp, i)) 722 for (j = 0; j < NUM_RING_RX_HW_STATS; j++) { 723 str = bnxt_ring_rx_stats_str[j]; 724 ethtool_sprintf(&buf, "[%d]: %s", i, 725 str); 726 } 727 if (is_tx_ring(bp, i)) 728 for (j = 0; j < NUM_RING_TX_HW_STATS; j++) { 729 str = bnxt_ring_tx_stats_str[j]; 730 ethtool_sprintf(&buf, "[%d]: %s", i, 731 str); 732 } 733 num_str = bnxt_get_num_tpa_ring_stats(bp); 734 if (!num_str || !is_rx_ring(bp, i)) 735 goto skip_tpa_stats; 736 737 if (bp->max_tpa_v2) 738 for (j = 0; j < num_str; j++) { 739 str = bnxt_ring_tpa2_stats_str[j]; 740 ethtool_sprintf(&buf, "[%d]: %s", i, 741 str); 742 } 743 else 744 for (j = 0; j < num_str; j++) { 745 str = bnxt_ring_tpa_stats_str[j]; 746 ethtool_sprintf(&buf, "[%d]: %s", i, 747 str); 748 } 749 skip_tpa_stats: 750 if (is_rx_ring(bp, i)) 751 for (j = 0; j < NUM_RING_RX_SW_STATS; j++) { 752 str = bnxt_rx_sw_stats_str[j]; 753 ethtool_sprintf(&buf, "[%d]: %s", i, 754 str); 755 } 756 for (j = 0; j < NUM_RING_CMN_SW_STATS; j++) { 757 str = bnxt_cmn_sw_stats_str[j]; 758 ethtool_sprintf(&buf, "[%d]: %s", i, str); 759 } 760 } 761 for (i = 0; i < BNXT_NUM_RING_DRV_STATS; i++) 762 ethtool_puts(&buf, bnxt_ring_drv_stats_arr[i]); 763 764 if (bp->flags & BNXT_FLAG_PORT_STATS) 765 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 766 str = bnxt_port_stats_arr[i].string; 767 ethtool_puts(&buf, str); 768 } 769 770 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 771 u32 len; 772 773 len = min_t(u32, bp->fw_rx_stats_ext_size, 774 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 775 for (i = 0; i < len; i++) { 776 str = bnxt_port_stats_ext_arr[i].string; 777 ethtool_puts(&buf, str); 778 } 779 780 len = min_t(u32, bp->fw_tx_stats_ext_size, 781 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 782 for (i = 0; i < len; i++) { 783 str = bnxt_tx_port_stats_ext_arr[i].string; 784 ethtool_puts(&buf, str); 785 } 786 787 if (bp->pri2cos_valid) { 788 for (i = 0; i < 8; i++) { 789 str = bnxt_rx_bytes_pri_arr[i].string; 790 ethtool_puts(&buf, str); 791 } 792 793 for (i = 0; i < 8; i++) { 794 str = bnxt_rx_pkts_pri_arr[i].string; 795 ethtool_puts(&buf, str); 796 } 797 798 for (i = 0; i < 8; i++) { 799 str = bnxt_tx_bytes_pri_arr[i].string; 800 ethtool_puts(&buf, str); 801 } 802 803 for (i = 0; i < 8; i++) { 804 str = bnxt_tx_pkts_pri_arr[i].string; 805 ethtool_puts(&buf, str); 806 } 807 } 808 } 809 break; 810 case ETH_SS_TEST: 811 if (bp->num_tests) 812 for (i = 0; i < bp->num_tests; i++) 813 ethtool_puts(&buf, bp->test_info->string[i]); 814 break; 815 default: 816 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 817 stringset); 818 break; 819 } 820 } 821 822 static void bnxt_get_ringparam(struct net_device *dev, 823 struct ethtool_ringparam *ering, 824 struct kernel_ethtool_ringparam *kernel_ering, 825 struct netlink_ext_ack *extack) 826 { 827 struct bnxt *bp = netdev_priv(dev); 828 829 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 830 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA; 831 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 832 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_ENABLED; 833 } else { 834 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 835 ering->rx_jumbo_max_pending = 0; 836 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_DISABLED; 837 } 838 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 839 840 ering->rx_pending = bp->rx_ring_size; 841 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 842 ering->tx_pending = bp->tx_ring_size; 843 844 kernel_ering->hds_thresh_max = BNXT_HDS_THRESHOLD_MAX; 845 } 846 847 static int bnxt_set_ringparam(struct net_device *dev, 848 struct ethtool_ringparam *ering, 849 struct kernel_ethtool_ringparam *kernel_ering, 850 struct netlink_ext_ack *extack) 851 { 852 u8 tcp_data_split = kernel_ering->tcp_data_split; 853 struct bnxt *bp = netdev_priv(dev); 854 u8 hds_config_mod; 855 856 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 857 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 858 (ering->tx_pending < BNXT_MIN_TX_DESC_CNT)) 859 return -EINVAL; 860 861 hds_config_mod = tcp_data_split != dev->cfg->hds_config; 862 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_DISABLED && hds_config_mod) 863 return -EINVAL; 864 865 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_ENABLED && 866 hds_config_mod && BNXT_RX_PAGE_MODE(bp)) { 867 NL_SET_ERR_MSG_MOD(extack, "tcp-data-split is disallowed when XDP is attached"); 868 return -EINVAL; 869 } 870 871 if (netif_running(dev)) 872 bnxt_close_nic(bp, false, false); 873 874 if (hds_config_mod) { 875 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_ENABLED) 876 bp->flags |= BNXT_FLAG_HDS; 877 else if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_UNKNOWN) 878 bp->flags &= ~BNXT_FLAG_HDS; 879 } 880 881 bp->rx_ring_size = ering->rx_pending; 882 bp->tx_ring_size = ering->tx_pending; 883 bnxt_set_ring_params(bp); 884 885 if (netif_running(dev)) 886 return bnxt_open_nic(bp, false, false); 887 888 return 0; 889 } 890 891 static void bnxt_get_channels(struct net_device *dev, 892 struct ethtool_channels *channel) 893 { 894 struct bnxt *bp = netdev_priv(dev); 895 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 896 int max_rx_rings, max_tx_rings, tcs; 897 int max_tx_sch_inputs, tx_grps; 898 899 /* Get the most up-to-date max_tx_sch_inputs. */ 900 if (netif_running(dev) && BNXT_NEW_RM(bp)) 901 bnxt_hwrm_func_resc_qcaps(bp, false); 902 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 903 904 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 905 if (max_tx_sch_inputs) 906 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 907 908 tcs = bp->num_tc; 909 tx_grps = max(tcs, 1); 910 if (bp->tx_nr_rings_xdp) 911 tx_grps++; 912 max_tx_rings /= tx_grps; 913 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 914 915 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 916 max_rx_rings = 0; 917 max_tx_rings = 0; 918 } 919 if (max_tx_sch_inputs) 920 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 921 922 if (tcs > 1) 923 max_tx_rings /= tcs; 924 925 channel->max_rx = max_rx_rings; 926 channel->max_tx = max_tx_rings; 927 channel->max_other = 0; 928 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 929 channel->combined_count = bp->rx_nr_rings; 930 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 931 channel->combined_count--; 932 } else { 933 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 934 channel->rx_count = bp->rx_nr_rings; 935 channel->tx_count = bp->tx_nr_rings_per_tc; 936 } 937 } 938 } 939 940 static int bnxt_set_channels(struct net_device *dev, 941 struct ethtool_channels *channel) 942 { 943 struct bnxt *bp = netdev_priv(dev); 944 int req_tx_rings, req_rx_rings, tcs; 945 u32 new_tbl_size = 0, old_tbl_size; 946 bool sh = false; 947 int tx_xdp = 0; 948 int rc = 0; 949 int tx_cp; 950 951 if (channel->other_count) 952 return -EINVAL; 953 954 if (!channel->combined_count && 955 (!channel->rx_count || !channel->tx_count)) 956 return -EINVAL; 957 958 if (channel->combined_count && 959 (channel->rx_count || channel->tx_count)) 960 return -EINVAL; 961 962 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 963 channel->tx_count)) 964 return -EINVAL; 965 966 if (channel->combined_count) 967 sh = true; 968 969 tcs = bp->num_tc; 970 971 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 972 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 973 if (bp->tx_nr_rings_xdp) { 974 if (!sh) { 975 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 976 return -EINVAL; 977 } 978 tx_xdp = req_rx_rings; 979 } 980 981 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 982 if (rc) { 983 netdev_warn(dev, "Unable to allocate the requested rings\n"); 984 return rc; 985 } 986 987 /* RSS table size only changes on P5 chips with older firmware; 988 * newer firmware always uses the largest table size. 989 */ 990 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) != 991 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings)) { 992 new_tbl_size = bnxt_get_nr_rss_ctxs(bp, req_rx_rings) * 993 BNXT_RSS_TABLE_ENTRIES_P5; 994 old_tbl_size = bnxt_get_rxfh_indir_size(dev); 995 996 if (!ethtool_rxfh_indir_can_resize(dev, bp->rss_indir_tbl, 997 old_tbl_size, 998 new_tbl_size)) { 999 netdev_warn(dev, "RSS table resize not possible\n"); 1000 return -EINVAL; 1001 } 1002 1003 rc = ethtool_rxfh_ctxs_can_resize(dev, new_tbl_size); 1004 if (rc) 1005 return rc; 1006 } 1007 1008 if (netif_running(dev)) { 1009 if (BNXT_PF(bp)) { 1010 /* TODO CHIMP_FW: Send message to all VF's 1011 * before PF unload 1012 */ 1013 } 1014 bnxt_close_nic(bp, true, false); 1015 } 1016 1017 if (new_tbl_size) { 1018 ethtool_rxfh_indir_resize(dev, bp->rss_indir_tbl, 1019 old_tbl_size, new_tbl_size); 1020 ethtool_rxfh_ctxs_resize(dev, new_tbl_size); 1021 } 1022 1023 if (sh) { 1024 bp->flags |= BNXT_FLAG_SHARED_RINGS; 1025 bp->rx_nr_rings = channel->combined_count; 1026 bp->tx_nr_rings_per_tc = channel->combined_count; 1027 } else { 1028 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 1029 bp->rx_nr_rings = channel->rx_count; 1030 bp->tx_nr_rings_per_tc = channel->tx_count; 1031 } 1032 bp->tx_nr_rings_xdp = tx_xdp; 1033 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 1034 if (tcs > 1) 1035 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 1036 1037 tx_cp = bnxt_num_tx_to_cp(bp, bp->tx_nr_rings); 1038 bp->cp_nr_rings = sh ? max_t(int, tx_cp, bp->rx_nr_rings) : 1039 tx_cp + bp->rx_nr_rings; 1040 1041 /* After changing number of rx channels, update NTUPLE feature. */ 1042 netdev_update_features(dev); 1043 if (netif_running(dev)) { 1044 rc = bnxt_open_nic(bp, true, false); 1045 if ((!rc) && BNXT_PF(bp)) { 1046 /* TODO CHIMP_FW: Send message to all VF's 1047 * to renable 1048 */ 1049 } 1050 } else { 1051 rc = bnxt_reserve_rings(bp, true); 1052 } 1053 1054 return rc; 1055 } 1056 1057 static u32 bnxt_get_all_fltr_ids_rcu(struct bnxt *bp, struct hlist_head tbl[], 1058 int tbl_size, u32 *ids, u32 start, 1059 u32 id_cnt) 1060 { 1061 int i, j = start; 1062 1063 if (j >= id_cnt) 1064 return j; 1065 for (i = 0; i < tbl_size; i++) { 1066 struct hlist_head *head; 1067 struct bnxt_filter_base *fltr; 1068 1069 head = &tbl[i]; 1070 hlist_for_each_entry_rcu(fltr, head, hash) { 1071 if (!fltr->flags || 1072 test_bit(BNXT_FLTR_FW_DELETED, &fltr->state)) 1073 continue; 1074 ids[j++] = fltr->sw_id; 1075 if (j == id_cnt) 1076 return j; 1077 } 1078 } 1079 return j; 1080 } 1081 1082 static struct bnxt_filter_base *bnxt_get_one_fltr_rcu(struct bnxt *bp, 1083 struct hlist_head tbl[], 1084 int tbl_size, u32 id) 1085 { 1086 int i; 1087 1088 for (i = 0; i < tbl_size; i++) { 1089 struct hlist_head *head; 1090 struct bnxt_filter_base *fltr; 1091 1092 head = &tbl[i]; 1093 hlist_for_each_entry_rcu(fltr, head, hash) { 1094 if (fltr->flags && fltr->sw_id == id) 1095 return fltr; 1096 } 1097 } 1098 return NULL; 1099 } 1100 1101 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 1102 u32 *rule_locs) 1103 { 1104 u32 count; 1105 1106 cmd->data = bp->ntp_fltr_count; 1107 rcu_read_lock(); 1108 count = bnxt_get_all_fltr_ids_rcu(bp, bp->l2_fltr_hash_tbl, 1109 BNXT_L2_FLTR_HASH_SIZE, rule_locs, 0, 1110 cmd->rule_cnt); 1111 cmd->rule_cnt = bnxt_get_all_fltr_ids_rcu(bp, bp->ntp_fltr_hash_tbl, 1112 BNXT_NTP_FLTR_HASH_SIZE, 1113 rule_locs, count, 1114 cmd->rule_cnt); 1115 rcu_read_unlock(); 1116 1117 return 0; 1118 } 1119 1120 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1121 { 1122 struct ethtool_rx_flow_spec *fs = 1123 (struct ethtool_rx_flow_spec *)&cmd->fs; 1124 struct bnxt_filter_base *fltr_base; 1125 struct bnxt_ntuple_filter *fltr; 1126 struct bnxt_flow_masks *fmasks; 1127 struct flow_keys *fkeys; 1128 int rc = -EINVAL; 1129 1130 if (fs->location >= bp->max_fltr) 1131 return rc; 1132 1133 rcu_read_lock(); 1134 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl, 1135 BNXT_L2_FLTR_HASH_SIZE, 1136 fs->location); 1137 if (fltr_base) { 1138 struct ethhdr *h_ether = &fs->h_u.ether_spec; 1139 struct ethhdr *m_ether = &fs->m_u.ether_spec; 1140 struct bnxt_l2_filter *l2_fltr; 1141 struct bnxt_l2_key *l2_key; 1142 1143 l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base); 1144 l2_key = &l2_fltr->l2_key; 1145 fs->flow_type = ETHER_FLOW; 1146 ether_addr_copy(h_ether->h_dest, l2_key->dst_mac_addr); 1147 eth_broadcast_addr(m_ether->h_dest); 1148 if (l2_key->vlan) { 1149 struct ethtool_flow_ext *m_ext = &fs->m_ext; 1150 struct ethtool_flow_ext *h_ext = &fs->h_ext; 1151 1152 fs->flow_type |= FLOW_EXT; 1153 m_ext->vlan_tci = htons(0xfff); 1154 h_ext->vlan_tci = htons(l2_key->vlan); 1155 } 1156 if (fltr_base->flags & BNXT_ACT_RING_DST) 1157 fs->ring_cookie = fltr_base->rxq; 1158 if (fltr_base->flags & BNXT_ACT_FUNC_DST) 1159 fs->ring_cookie = (u64)(fltr_base->vf_idx + 1) << 1160 ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 1161 rcu_read_unlock(); 1162 return 0; 1163 } 1164 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl, 1165 BNXT_NTP_FLTR_HASH_SIZE, 1166 fs->location); 1167 if (!fltr_base) { 1168 rcu_read_unlock(); 1169 return rc; 1170 } 1171 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base); 1172 1173 fkeys = &fltr->fkeys; 1174 fmasks = &fltr->fmasks; 1175 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 1176 if (fkeys->basic.ip_proto == BNXT_IP_PROTO_WILDCARD) { 1177 fs->flow_type = IP_USER_FLOW; 1178 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 1179 fs->h_u.usr_ip4_spec.proto = BNXT_IP_PROTO_WILDCARD; 1180 fs->m_u.usr_ip4_spec.proto = 0; 1181 } else if (fkeys->basic.ip_proto == IPPROTO_ICMP) { 1182 fs->flow_type = IP_USER_FLOW; 1183 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 1184 fs->h_u.usr_ip4_spec.proto = IPPROTO_ICMP; 1185 fs->m_u.usr_ip4_spec.proto = BNXT_IP_PROTO_FULL_MASK; 1186 } else if (fkeys->basic.ip_proto == IPPROTO_TCP) { 1187 fs->flow_type = TCP_V4_FLOW; 1188 } else if (fkeys->basic.ip_proto == IPPROTO_UDP) { 1189 fs->flow_type = UDP_V4_FLOW; 1190 } else { 1191 goto fltr_err; 1192 } 1193 1194 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 1195 fs->m_u.tcp_ip4_spec.ip4src = fmasks->addrs.v4addrs.src; 1196 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 1197 fs->m_u.tcp_ip4_spec.ip4dst = fmasks->addrs.v4addrs.dst; 1198 if (fs->flow_type == TCP_V4_FLOW || 1199 fs->flow_type == UDP_V4_FLOW) { 1200 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 1201 fs->m_u.tcp_ip4_spec.psrc = fmasks->ports.src; 1202 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 1203 fs->m_u.tcp_ip4_spec.pdst = fmasks->ports.dst; 1204 } 1205 } else { 1206 if (fkeys->basic.ip_proto == BNXT_IP_PROTO_WILDCARD) { 1207 fs->flow_type = IPV6_USER_FLOW; 1208 fs->h_u.usr_ip6_spec.l4_proto = BNXT_IP_PROTO_WILDCARD; 1209 fs->m_u.usr_ip6_spec.l4_proto = 0; 1210 } else if (fkeys->basic.ip_proto == IPPROTO_ICMPV6) { 1211 fs->flow_type = IPV6_USER_FLOW; 1212 fs->h_u.usr_ip6_spec.l4_proto = IPPROTO_ICMPV6; 1213 fs->m_u.usr_ip6_spec.l4_proto = BNXT_IP_PROTO_FULL_MASK; 1214 } else if (fkeys->basic.ip_proto == IPPROTO_TCP) { 1215 fs->flow_type = TCP_V6_FLOW; 1216 } else if (fkeys->basic.ip_proto == IPPROTO_UDP) { 1217 fs->flow_type = UDP_V6_FLOW; 1218 } else { 1219 goto fltr_err; 1220 } 1221 1222 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 1223 fkeys->addrs.v6addrs.src; 1224 *(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6src[0] = 1225 fmasks->addrs.v6addrs.src; 1226 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 1227 fkeys->addrs.v6addrs.dst; 1228 *(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6dst[0] = 1229 fmasks->addrs.v6addrs.dst; 1230 if (fs->flow_type == TCP_V6_FLOW || 1231 fs->flow_type == UDP_V6_FLOW) { 1232 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 1233 fs->m_u.tcp_ip6_spec.psrc = fmasks->ports.src; 1234 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 1235 fs->m_u.tcp_ip6_spec.pdst = fmasks->ports.dst; 1236 } 1237 } 1238 1239 if (fltr->base.flags & BNXT_ACT_DROP) { 1240 fs->ring_cookie = RX_CLS_FLOW_DISC; 1241 } else if (fltr->base.flags & BNXT_ACT_RSS_CTX) { 1242 fs->flow_type |= FLOW_RSS; 1243 cmd->rss_context = fltr->base.fw_vnic_id; 1244 } else { 1245 fs->ring_cookie = fltr->base.rxq; 1246 } 1247 rc = 0; 1248 1249 fltr_err: 1250 rcu_read_unlock(); 1251 1252 return rc; 1253 } 1254 1255 static struct bnxt_rss_ctx *bnxt_get_rss_ctx_from_index(struct bnxt *bp, 1256 u32 index) 1257 { 1258 struct ethtool_rxfh_context *ctx; 1259 1260 ctx = xa_load(&bp->dev->ethtool->rss_ctx, index); 1261 if (!ctx) 1262 return NULL; 1263 return ethtool_rxfh_context_priv(ctx); 1264 } 1265 1266 static int bnxt_alloc_vnic_rss_table(struct bnxt *bp, 1267 struct bnxt_vnic_info *vnic) 1268 { 1269 int size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5); 1270 1271 vnic->rss_table_size = size + HW_HASH_KEY_SIZE; 1272 vnic->rss_table = dma_alloc_coherent(&bp->pdev->dev, 1273 vnic->rss_table_size, 1274 &vnic->rss_table_dma_addr, 1275 GFP_KERNEL); 1276 if (!vnic->rss_table) 1277 return -ENOMEM; 1278 1279 vnic->rss_hash_key = ((void *)vnic->rss_table) + size; 1280 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; 1281 return 0; 1282 } 1283 1284 static int bnxt_add_l2_cls_rule(struct bnxt *bp, 1285 struct ethtool_rx_flow_spec *fs) 1286 { 1287 u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1288 u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1289 struct ethhdr *h_ether = &fs->h_u.ether_spec; 1290 struct ethhdr *m_ether = &fs->m_u.ether_spec; 1291 struct bnxt_l2_filter *fltr; 1292 struct bnxt_l2_key key; 1293 u16 vnic_id; 1294 u8 flags; 1295 int rc; 1296 1297 if (BNXT_CHIP_P5_PLUS(bp)) 1298 return -EOPNOTSUPP; 1299 1300 if (!is_broadcast_ether_addr(m_ether->h_dest)) 1301 return -EINVAL; 1302 ether_addr_copy(key.dst_mac_addr, h_ether->h_dest); 1303 key.vlan = 0; 1304 if (fs->flow_type & FLOW_EXT) { 1305 struct ethtool_flow_ext *m_ext = &fs->m_ext; 1306 struct ethtool_flow_ext *h_ext = &fs->h_ext; 1307 1308 if (m_ext->vlan_tci != htons(0xfff) || !h_ext->vlan_tci) 1309 return -EINVAL; 1310 key.vlan = ntohs(h_ext->vlan_tci); 1311 } 1312 1313 if (vf) { 1314 flags = BNXT_ACT_FUNC_DST; 1315 vnic_id = 0xffff; 1316 vf--; 1317 } else { 1318 flags = BNXT_ACT_RING_DST; 1319 vnic_id = bp->vnic_info[ring + 1].fw_vnic_id; 1320 } 1321 fltr = bnxt_alloc_new_l2_filter(bp, &key, flags); 1322 if (IS_ERR(fltr)) 1323 return PTR_ERR(fltr); 1324 1325 fltr->base.fw_vnic_id = vnic_id; 1326 fltr->base.rxq = ring; 1327 fltr->base.vf_idx = vf; 1328 rc = bnxt_hwrm_l2_filter_alloc(bp, fltr); 1329 if (rc) 1330 bnxt_del_l2_filter(bp, fltr); 1331 else 1332 fs->location = fltr->base.sw_id; 1333 return rc; 1334 } 1335 1336 static bool bnxt_verify_ntuple_ip4_flow(struct ethtool_usrip4_spec *ip_spec, 1337 struct ethtool_usrip4_spec *ip_mask) 1338 { 1339 u8 mproto = ip_mask->proto; 1340 u8 sproto = ip_spec->proto; 1341 1342 if (ip_mask->l4_4_bytes || ip_mask->tos || 1343 ip_spec->ip_ver != ETH_RX_NFC_IP4 || 1344 (mproto && (mproto != BNXT_IP_PROTO_FULL_MASK || sproto != IPPROTO_ICMP))) 1345 return false; 1346 return true; 1347 } 1348 1349 static bool bnxt_verify_ntuple_ip6_flow(struct ethtool_usrip6_spec *ip_spec, 1350 struct ethtool_usrip6_spec *ip_mask) 1351 { 1352 u8 mproto = ip_mask->l4_proto; 1353 u8 sproto = ip_spec->l4_proto; 1354 1355 if (ip_mask->l4_4_bytes || ip_mask->tclass || 1356 (mproto && (mproto != BNXT_IP_PROTO_FULL_MASK || sproto != IPPROTO_ICMPV6))) 1357 return false; 1358 return true; 1359 } 1360 1361 static int bnxt_add_ntuple_cls_rule(struct bnxt *bp, 1362 struct ethtool_rxnfc *cmd) 1363 { 1364 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1365 struct bnxt_ntuple_filter *new_fltr, *fltr; 1366 u32 flow_type = fs->flow_type & 0xff; 1367 struct bnxt_l2_filter *l2_fltr; 1368 struct bnxt_flow_masks *fmasks; 1369 struct flow_keys *fkeys; 1370 u32 idx; 1371 int rc; 1372 1373 if (!bp->vnic_info) 1374 return -EAGAIN; 1375 1376 if (fs->flow_type & (FLOW_MAC_EXT | FLOW_EXT)) 1377 return -EOPNOTSUPP; 1378 1379 if (fs->ring_cookie != RX_CLS_FLOW_DISC && 1380 ethtool_get_flow_spec_ring_vf(fs->ring_cookie)) 1381 return -EOPNOTSUPP; 1382 1383 if (flow_type == IP_USER_FLOW) { 1384 if (!bnxt_verify_ntuple_ip4_flow(&fs->h_u.usr_ip4_spec, 1385 &fs->m_u.usr_ip4_spec)) 1386 return -EOPNOTSUPP; 1387 } 1388 1389 if (flow_type == IPV6_USER_FLOW) { 1390 if (!bnxt_verify_ntuple_ip6_flow(&fs->h_u.usr_ip6_spec, 1391 &fs->m_u.usr_ip6_spec)) 1392 return -EOPNOTSUPP; 1393 } 1394 1395 new_fltr = kzalloc_obj(*new_fltr); 1396 if (!new_fltr) 1397 return -ENOMEM; 1398 1399 l2_fltr = bp->vnic_info[BNXT_VNIC_DEFAULT].l2_filters[0]; 1400 atomic_inc(&l2_fltr->refcnt); 1401 new_fltr->l2_fltr = l2_fltr; 1402 fmasks = &new_fltr->fmasks; 1403 fkeys = &new_fltr->fkeys; 1404 1405 rc = -EOPNOTSUPP; 1406 switch (flow_type) { 1407 case IP_USER_FLOW: { 1408 struct ethtool_usrip4_spec *ip_spec = &fs->h_u.usr_ip4_spec; 1409 struct ethtool_usrip4_spec *ip_mask = &fs->m_u.usr_ip4_spec; 1410 1411 fkeys->basic.ip_proto = ip_mask->proto ? ip_spec->proto 1412 : BNXT_IP_PROTO_WILDCARD; 1413 fkeys->basic.n_proto = htons(ETH_P_IP); 1414 fkeys->addrs.v4addrs.src = ip_spec->ip4src; 1415 fmasks->addrs.v4addrs.src = ip_mask->ip4src; 1416 fkeys->addrs.v4addrs.dst = ip_spec->ip4dst; 1417 fmasks->addrs.v4addrs.dst = ip_mask->ip4dst; 1418 break; 1419 } 1420 case TCP_V4_FLOW: 1421 case UDP_V4_FLOW: { 1422 struct ethtool_tcpip4_spec *ip_spec = &fs->h_u.tcp_ip4_spec; 1423 struct ethtool_tcpip4_spec *ip_mask = &fs->m_u.tcp_ip4_spec; 1424 1425 fkeys->basic.ip_proto = IPPROTO_TCP; 1426 if (flow_type == UDP_V4_FLOW) 1427 fkeys->basic.ip_proto = IPPROTO_UDP; 1428 fkeys->basic.n_proto = htons(ETH_P_IP); 1429 fkeys->addrs.v4addrs.src = ip_spec->ip4src; 1430 fmasks->addrs.v4addrs.src = ip_mask->ip4src; 1431 fkeys->addrs.v4addrs.dst = ip_spec->ip4dst; 1432 fmasks->addrs.v4addrs.dst = ip_mask->ip4dst; 1433 fkeys->ports.src = ip_spec->psrc; 1434 fmasks->ports.src = ip_mask->psrc; 1435 fkeys->ports.dst = ip_spec->pdst; 1436 fmasks->ports.dst = ip_mask->pdst; 1437 break; 1438 } 1439 case IPV6_USER_FLOW: { 1440 struct ethtool_usrip6_spec *ip_spec = &fs->h_u.usr_ip6_spec; 1441 struct ethtool_usrip6_spec *ip_mask = &fs->m_u.usr_ip6_spec; 1442 1443 fkeys->basic.ip_proto = ip_mask->l4_proto ? ip_spec->l4_proto 1444 : BNXT_IP_PROTO_WILDCARD; 1445 fkeys->basic.n_proto = htons(ETH_P_IPV6); 1446 fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src; 1447 fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src; 1448 fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst; 1449 fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst; 1450 break; 1451 } 1452 case TCP_V6_FLOW: 1453 case UDP_V6_FLOW: { 1454 struct ethtool_tcpip6_spec *ip_spec = &fs->h_u.tcp_ip6_spec; 1455 struct ethtool_tcpip6_spec *ip_mask = &fs->m_u.tcp_ip6_spec; 1456 1457 fkeys->basic.ip_proto = IPPROTO_TCP; 1458 if (flow_type == UDP_V6_FLOW) 1459 fkeys->basic.ip_proto = IPPROTO_UDP; 1460 fkeys->basic.n_proto = htons(ETH_P_IPV6); 1461 1462 fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src; 1463 fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src; 1464 fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst; 1465 fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst; 1466 fkeys->ports.src = ip_spec->psrc; 1467 fmasks->ports.src = ip_mask->psrc; 1468 fkeys->ports.dst = ip_spec->pdst; 1469 fmasks->ports.dst = ip_mask->pdst; 1470 break; 1471 } 1472 default: 1473 rc = -EOPNOTSUPP; 1474 goto ntuple_err; 1475 } 1476 if (!memcmp(&BNXT_FLOW_MASK_NONE, fmasks, sizeof(*fmasks))) 1477 goto ntuple_err; 1478 1479 idx = bnxt_get_ntp_filter_idx(bp, fkeys, NULL); 1480 rcu_read_lock(); 1481 fltr = bnxt_lookup_ntp_filter_from_idx(bp, new_fltr, idx); 1482 if (fltr) { 1483 rcu_read_unlock(); 1484 rc = -EEXIST; 1485 goto ntuple_err; 1486 } 1487 rcu_read_unlock(); 1488 1489 new_fltr->base.flags = BNXT_ACT_NO_AGING; 1490 if (fs->flow_type & FLOW_RSS) { 1491 struct bnxt_rss_ctx *rss_ctx; 1492 1493 new_fltr->base.fw_vnic_id = 0; 1494 new_fltr->base.flags |= BNXT_ACT_RSS_CTX; 1495 rss_ctx = bnxt_get_rss_ctx_from_index(bp, cmd->rss_context); 1496 if (rss_ctx) { 1497 new_fltr->base.fw_vnic_id = rss_ctx->index; 1498 } else { 1499 rc = -EINVAL; 1500 goto ntuple_err; 1501 } 1502 } 1503 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1504 new_fltr->base.flags |= BNXT_ACT_DROP; 1505 else 1506 new_fltr->base.rxq = ethtool_get_flow_spec_ring(fs->ring_cookie); 1507 __set_bit(BNXT_FLTR_VALID, &new_fltr->base.state); 1508 rc = bnxt_insert_ntp_filter(bp, new_fltr, idx); 1509 if (!rc) { 1510 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, new_fltr); 1511 if (rc) { 1512 bnxt_del_ntp_filter(bp, new_fltr); 1513 return rc; 1514 } 1515 fs->location = new_fltr->base.sw_id; 1516 return 0; 1517 } 1518 1519 ntuple_err: 1520 atomic_dec(&l2_fltr->refcnt); 1521 kfree(new_fltr); 1522 return rc; 1523 } 1524 1525 static int bnxt_srxclsrlins(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1526 { 1527 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1528 u32 ring, flow_type; 1529 int rc; 1530 u8 vf; 1531 1532 if (!netif_running(bp->dev)) 1533 return -EAGAIN; 1534 if (!(bp->flags & BNXT_FLAG_RFS)) 1535 return -EPERM; 1536 if (fs->location != RX_CLS_LOC_ANY) 1537 return -EINVAL; 1538 1539 flow_type = fs->flow_type; 1540 if ((flow_type == IP_USER_FLOW || 1541 flow_type == IPV6_USER_FLOW) && 1542 !(bp->fw_cap & BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO)) 1543 return -EOPNOTSUPP; 1544 if (flow_type & FLOW_MAC_EXT) 1545 return -EINVAL; 1546 flow_type &= ~FLOW_EXT; 1547 1548 if (fs->ring_cookie == RX_CLS_FLOW_DISC && flow_type != ETHER_FLOW) 1549 return bnxt_add_ntuple_cls_rule(bp, cmd); 1550 1551 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1552 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1553 if (BNXT_VF(bp) && vf) 1554 return -EINVAL; 1555 if (BNXT_PF(bp) && vf > bp->pf.active_vfs) 1556 return -EINVAL; 1557 if (!vf && ring >= bp->rx_nr_rings) 1558 return -EINVAL; 1559 1560 if (flow_type == ETHER_FLOW) 1561 rc = bnxt_add_l2_cls_rule(bp, fs); 1562 else 1563 rc = bnxt_add_ntuple_cls_rule(bp, cmd); 1564 return rc; 1565 } 1566 1567 static int bnxt_srxclsrldel(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1568 { 1569 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1570 struct bnxt_filter_base *fltr_base; 1571 struct bnxt_ntuple_filter *fltr; 1572 u32 id = fs->location; 1573 1574 rcu_read_lock(); 1575 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl, 1576 BNXT_L2_FLTR_HASH_SIZE, id); 1577 if (fltr_base) { 1578 struct bnxt_l2_filter *l2_fltr; 1579 1580 l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base); 1581 rcu_read_unlock(); 1582 bnxt_hwrm_l2_filter_free(bp, l2_fltr); 1583 bnxt_del_l2_filter(bp, l2_fltr); 1584 return 0; 1585 } 1586 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl, 1587 BNXT_NTP_FLTR_HASH_SIZE, id); 1588 if (!fltr_base) { 1589 rcu_read_unlock(); 1590 return -ENOENT; 1591 } 1592 1593 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base); 1594 if (!(fltr->base.flags & BNXT_ACT_NO_AGING)) { 1595 rcu_read_unlock(); 1596 return -EINVAL; 1597 } 1598 rcu_read_unlock(); 1599 bnxt_hwrm_cfa_ntuple_filter_free(bp, fltr); 1600 bnxt_del_ntp_filter(bp, fltr); 1601 return 0; 1602 } 1603 1604 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1605 { 1606 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1607 return RXH_IP_SRC | RXH_IP_DST; 1608 return 0; 1609 } 1610 1611 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1612 { 1613 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1614 return RXH_IP_SRC | RXH_IP_DST; 1615 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL) 1616 return RXH_IP_SRC | RXH_IP_DST | RXH_IP6_FL; 1617 return 0; 1618 } 1619 1620 static int bnxt_get_rxfh_fields(struct net_device *dev, 1621 struct ethtool_rxfh_fields *cmd) 1622 { 1623 struct bnxt *bp = netdev_priv(dev); 1624 1625 cmd->data = 0; 1626 switch (cmd->flow_type) { 1627 case TCP_V4_FLOW: 1628 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1629 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1630 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1631 cmd->data |= get_ethtool_ipv4_rss(bp); 1632 break; 1633 case UDP_V4_FLOW: 1634 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1635 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1636 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1637 fallthrough; 1638 case AH_ESP_V4_FLOW: 1639 if (bp->rss_hash_cfg & 1640 (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1641 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4)) 1642 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1643 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1644 fallthrough; 1645 case SCTP_V4_FLOW: 1646 case AH_V4_FLOW: 1647 case ESP_V4_FLOW: 1648 case IPV4_FLOW: 1649 cmd->data |= get_ethtool_ipv4_rss(bp); 1650 break; 1651 1652 case TCP_V6_FLOW: 1653 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1654 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1655 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1656 cmd->data |= get_ethtool_ipv6_rss(bp); 1657 break; 1658 case UDP_V6_FLOW: 1659 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1660 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1661 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1662 fallthrough; 1663 case AH_ESP_V6_FLOW: 1664 if (bp->rss_hash_cfg & 1665 (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1666 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6)) 1667 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1668 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1669 fallthrough; 1670 case SCTP_V6_FLOW: 1671 case AH_V6_FLOW: 1672 case ESP_V6_FLOW: 1673 case IPV6_FLOW: 1674 cmd->data |= get_ethtool_ipv6_rss(bp); 1675 break; 1676 } 1677 return 0; 1678 } 1679 1680 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1681 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1682 1683 static int bnxt_set_rxfh_fields(struct net_device *dev, 1684 const struct ethtool_rxfh_fields *cmd, 1685 struct netlink_ext_ack *extack) 1686 { 1687 struct bnxt *bp = netdev_priv(dev); 1688 int tuple, rc = 0; 1689 u32 rss_hash_cfg; 1690 1691 rss_hash_cfg = bp->rss_hash_cfg; 1692 1693 if (cmd->data == RXH_4TUPLE) 1694 tuple = 4; 1695 else if (cmd->data == RXH_2TUPLE || 1696 cmd->data == (RXH_2TUPLE | RXH_IP6_FL)) 1697 tuple = 2; 1698 else if (!cmd->data) 1699 tuple = 0; 1700 else 1701 return -EINVAL; 1702 1703 if (cmd->data & RXH_IP6_FL && 1704 !(bp->rss_cap & BNXT_RSS_CAP_IPV6_FLOW_LABEL_RSS_CAP)) 1705 return -EINVAL; 1706 1707 if (cmd->flow_type == TCP_V4_FLOW) { 1708 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1709 if (tuple == 4) 1710 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1711 } else if (cmd->flow_type == UDP_V4_FLOW) { 1712 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP)) 1713 return -EINVAL; 1714 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1715 if (tuple == 4) 1716 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1717 } else if (cmd->flow_type == TCP_V6_FLOW) { 1718 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1719 if (tuple == 4) 1720 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1721 } else if (cmd->flow_type == UDP_V6_FLOW) { 1722 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP)) 1723 return -EINVAL; 1724 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1725 if (tuple == 4) 1726 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1727 } else if (cmd->flow_type == AH_ESP_V4_FLOW) { 1728 if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V4_RSS_CAP) || 1729 !(bp->rss_cap & BNXT_RSS_CAP_ESP_V4_RSS_CAP))) 1730 return -EINVAL; 1731 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1732 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4); 1733 if (tuple == 4) 1734 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1735 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4; 1736 } else if (cmd->flow_type == AH_ESP_V6_FLOW) { 1737 if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V6_RSS_CAP) || 1738 !(bp->rss_cap & BNXT_RSS_CAP_ESP_V6_RSS_CAP))) 1739 return -EINVAL; 1740 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1741 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6); 1742 if (tuple == 4) 1743 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1744 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6; 1745 } else if (tuple == 4) { 1746 return -EINVAL; 1747 } 1748 1749 switch (cmd->flow_type) { 1750 case TCP_V4_FLOW: 1751 case UDP_V4_FLOW: 1752 case SCTP_V4_FLOW: 1753 case AH_ESP_V4_FLOW: 1754 case AH_V4_FLOW: 1755 case ESP_V4_FLOW: 1756 case IPV4_FLOW: 1757 if (tuple == 2) 1758 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1759 else if (!tuple) 1760 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1761 break; 1762 1763 case TCP_V6_FLOW: 1764 case UDP_V6_FLOW: 1765 case SCTP_V6_FLOW: 1766 case AH_ESP_V6_FLOW: 1767 case AH_V6_FLOW: 1768 case ESP_V6_FLOW: 1769 case IPV6_FLOW: 1770 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 | 1771 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL); 1772 if (!tuple) 1773 break; 1774 if (cmd->data & RXH_IP6_FL) 1775 rss_hash_cfg |= 1776 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL; 1777 else if (tuple == 2) 1778 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1779 break; 1780 } 1781 1782 if (bp->rss_hash_cfg == rss_hash_cfg) 1783 return 0; 1784 1785 if (bp->rss_cap & BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA) 1786 bp->rss_hash_delta = bp->rss_hash_cfg ^ rss_hash_cfg; 1787 bp->rss_hash_cfg = rss_hash_cfg; 1788 if (netif_running(bp->dev)) { 1789 bnxt_close_nic(bp, false, false); 1790 rc = bnxt_open_nic(bp, false, false); 1791 } 1792 return rc; 1793 } 1794 1795 static u32 bnxt_get_rx_ring_count(struct net_device *dev) 1796 { 1797 struct bnxt *bp = netdev_priv(dev); 1798 1799 return bp->rx_nr_rings; 1800 } 1801 1802 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1803 u32 *rule_locs) 1804 { 1805 struct bnxt *bp = netdev_priv(dev); 1806 int rc = 0; 1807 1808 switch (cmd->cmd) { 1809 case ETHTOOL_GRXCLSRLCNT: 1810 cmd->rule_cnt = bp->ntp_fltr_count; 1811 cmd->data = bp->max_fltr | RX_CLS_LOC_SPECIAL; 1812 break; 1813 1814 case ETHTOOL_GRXCLSRLALL: 1815 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1816 break; 1817 1818 case ETHTOOL_GRXCLSRULE: 1819 rc = bnxt_grxclsrule(bp, cmd); 1820 break; 1821 1822 default: 1823 rc = -EOPNOTSUPP; 1824 break; 1825 } 1826 1827 return rc; 1828 } 1829 1830 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1831 { 1832 struct bnxt *bp = netdev_priv(dev); 1833 int rc; 1834 1835 switch (cmd->cmd) { 1836 case ETHTOOL_SRXCLSRLINS: 1837 rc = bnxt_srxclsrlins(bp, cmd); 1838 break; 1839 1840 case ETHTOOL_SRXCLSRLDEL: 1841 rc = bnxt_srxclsrldel(bp, cmd); 1842 break; 1843 1844 default: 1845 rc = -EOPNOTSUPP; 1846 break; 1847 } 1848 return rc; 1849 } 1850 1851 u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1852 { 1853 struct bnxt *bp = netdev_priv(dev); 1854 1855 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) 1856 return bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) * 1857 BNXT_RSS_TABLE_ENTRIES_P5; 1858 return HW_HASH_INDEX_SIZE; 1859 } 1860 1861 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1862 { 1863 return HW_HASH_KEY_SIZE; 1864 } 1865 1866 static int bnxt_get_rxfh(struct net_device *dev, 1867 struct ethtool_rxfh_param *rxfh) 1868 { 1869 struct bnxt_rss_ctx *rss_ctx = NULL; 1870 struct bnxt *bp = netdev_priv(dev); 1871 u32 *indir_tbl = bp->rss_indir_tbl; 1872 struct bnxt_vnic_info *vnic; 1873 u32 i, tbl_size; 1874 1875 rxfh->hfunc = ETH_RSS_HASH_TOP; 1876 1877 if (!bp->vnic_info) 1878 return 0; 1879 1880 vnic = &bp->vnic_info[BNXT_VNIC_DEFAULT]; 1881 if (rxfh->rss_context) { 1882 struct ethtool_rxfh_context *ctx; 1883 1884 ctx = xa_load(&bp->dev->ethtool->rss_ctx, rxfh->rss_context); 1885 if (!ctx) 1886 return -EINVAL; 1887 indir_tbl = ethtool_rxfh_context_indir(ctx); 1888 rss_ctx = ethtool_rxfh_context_priv(ctx); 1889 vnic = &rss_ctx->vnic; 1890 } 1891 1892 if (rxfh->indir && indir_tbl) { 1893 tbl_size = bnxt_get_rxfh_indir_size(dev); 1894 for (i = 0; i < tbl_size; i++) 1895 rxfh->indir[i] = indir_tbl[i]; 1896 } 1897 1898 if (rxfh->key && vnic->rss_hash_key) 1899 memcpy(rxfh->key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1900 1901 return 0; 1902 } 1903 1904 static void bnxt_modify_rss(struct bnxt *bp, struct ethtool_rxfh_context *ctx, 1905 struct bnxt_rss_ctx *rss_ctx, 1906 const struct ethtool_rxfh_param *rxfh) 1907 { 1908 if (rxfh->key) { 1909 if (rss_ctx) { 1910 memcpy(rss_ctx->vnic.rss_hash_key, rxfh->key, 1911 HW_HASH_KEY_SIZE); 1912 } else { 1913 memcpy(bp->rss_hash_key, rxfh->key, HW_HASH_KEY_SIZE); 1914 bp->rss_hash_key_updated = true; 1915 } 1916 } 1917 if (rxfh->indir) { 1918 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(bp->dev); 1919 u32 *indir_tbl = bp->rss_indir_tbl; 1920 1921 if (rss_ctx) 1922 indir_tbl = ethtool_rxfh_context_indir(ctx); 1923 for (i = 0; i < tbl_size; i++) 1924 indir_tbl[i] = rxfh->indir[i]; 1925 pad = bp->rss_indir_tbl_entries - tbl_size; 1926 if (pad) 1927 memset(&indir_tbl[i], 0, pad * sizeof(*indir_tbl)); 1928 } 1929 } 1930 1931 static int bnxt_rxfh_context_check(struct bnxt *bp, 1932 const struct ethtool_rxfh_param *rxfh, 1933 struct netlink_ext_ack *extack) 1934 { 1935 if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP) { 1936 NL_SET_ERR_MSG_MOD(extack, "RSS hash function not supported"); 1937 return -EOPNOTSUPP; 1938 } 1939 1940 if (!BNXT_SUPPORTS_MULTI_RSS_CTX(bp)) { 1941 NL_SET_ERR_MSG_MOD(extack, "RSS contexts not supported"); 1942 return -EOPNOTSUPP; 1943 } 1944 1945 if (!netif_running(bp->dev)) { 1946 NL_SET_ERR_MSG_MOD(extack, "Unable to set RSS contexts when interface is down"); 1947 return -EAGAIN; 1948 } 1949 1950 return 0; 1951 } 1952 1953 static int bnxt_create_rxfh_context(struct net_device *dev, 1954 struct ethtool_rxfh_context *ctx, 1955 const struct ethtool_rxfh_param *rxfh, 1956 struct netlink_ext_ack *extack) 1957 { 1958 struct bnxt *bp = netdev_priv(dev); 1959 struct bnxt_rss_ctx *rss_ctx; 1960 struct bnxt_vnic_info *vnic; 1961 int rc; 1962 1963 rc = bnxt_rxfh_context_check(bp, rxfh, extack); 1964 if (rc) 1965 return rc; 1966 1967 if (bp->num_rss_ctx >= BNXT_MAX_ETH_RSS_CTX) { 1968 NL_SET_ERR_MSG_FMT_MOD(extack, "Out of RSS contexts, maximum %u", 1969 BNXT_MAX_ETH_RSS_CTX); 1970 return -EINVAL; 1971 } 1972 1973 if (!bnxt_rfs_capable(bp, true)) { 1974 NL_SET_ERR_MSG_MOD(extack, "Out hardware resources"); 1975 return -ENOMEM; 1976 } 1977 1978 rss_ctx = ethtool_rxfh_context_priv(ctx); 1979 1980 bp->num_rss_ctx++; 1981 1982 vnic = &rss_ctx->vnic; 1983 vnic->rss_ctx = ctx; 1984 vnic->flags |= BNXT_VNIC_RSSCTX_FLAG; 1985 vnic->vnic_id = BNXT_VNIC_ID_INVALID; 1986 rc = bnxt_alloc_vnic_rss_table(bp, vnic); 1987 if (rc) 1988 goto out; 1989 1990 /* Populate defaults in the context */ 1991 bnxt_set_dflt_rss_indir_tbl(bp, ctx); 1992 ctx->hfunc = ETH_RSS_HASH_TOP; 1993 memcpy(vnic->rss_hash_key, bp->rss_hash_key, HW_HASH_KEY_SIZE); 1994 memcpy(ethtool_rxfh_context_key(ctx), 1995 bp->rss_hash_key, HW_HASH_KEY_SIZE); 1996 1997 rc = bnxt_hwrm_vnic_alloc(bp, vnic, 0, bp->rx_nr_rings); 1998 if (rc) { 1999 NL_SET_ERR_MSG_MOD(extack, "Unable to allocate VNIC"); 2000 goto out; 2001 } 2002 2003 rc = bnxt_hwrm_vnic_set_tpa(bp, vnic, bp->flags & BNXT_FLAG_TPA); 2004 if (rc) { 2005 NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA"); 2006 goto out; 2007 } 2008 bnxt_modify_rss(bp, ctx, rss_ctx, rxfh); 2009 2010 rc = __bnxt_setup_vnic_p5(bp, vnic); 2011 if (rc) { 2012 NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA"); 2013 goto out; 2014 } 2015 2016 rss_ctx->index = rxfh->rss_context; 2017 return 0; 2018 out: 2019 bnxt_del_one_rss_ctx(bp, rss_ctx, true); 2020 return rc; 2021 } 2022 2023 static int bnxt_modify_rxfh_context(struct net_device *dev, 2024 struct ethtool_rxfh_context *ctx, 2025 const struct ethtool_rxfh_param *rxfh, 2026 struct netlink_ext_ack *extack) 2027 { 2028 struct bnxt *bp = netdev_priv(dev); 2029 struct bnxt_rss_ctx *rss_ctx; 2030 int rc; 2031 2032 rc = bnxt_rxfh_context_check(bp, rxfh, extack); 2033 if (rc) 2034 return rc; 2035 2036 rss_ctx = ethtool_rxfh_context_priv(ctx); 2037 2038 bnxt_modify_rss(bp, ctx, rss_ctx, rxfh); 2039 2040 return bnxt_hwrm_vnic_rss_cfg_p5(bp, &rss_ctx->vnic); 2041 } 2042 2043 static int bnxt_remove_rxfh_context(struct net_device *dev, 2044 struct ethtool_rxfh_context *ctx, 2045 u32 rss_context, 2046 struct netlink_ext_ack *extack) 2047 { 2048 struct bnxt *bp = netdev_priv(dev); 2049 struct bnxt_rss_ctx *rss_ctx; 2050 2051 rss_ctx = ethtool_rxfh_context_priv(ctx); 2052 2053 bnxt_del_one_rss_ctx(bp, rss_ctx, true); 2054 return 0; 2055 } 2056 2057 static int bnxt_set_rxfh(struct net_device *dev, 2058 struct ethtool_rxfh_param *rxfh, 2059 struct netlink_ext_ack *extack) 2060 { 2061 struct bnxt *bp = netdev_priv(dev); 2062 int rc = 0; 2063 2064 if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP) 2065 return -EOPNOTSUPP; 2066 2067 bnxt_modify_rss(bp, NULL, NULL, rxfh); 2068 2069 if (netif_running(bp->dev)) { 2070 bnxt_close_nic(bp, false, false); 2071 rc = bnxt_open_nic(bp, false, false); 2072 } 2073 return rc; 2074 } 2075 2076 static void bnxt_get_drvinfo(struct net_device *dev, 2077 struct ethtool_drvinfo *info) 2078 { 2079 struct bnxt *bp = netdev_priv(dev); 2080 2081 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 2082 strscpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 2083 strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 2084 info->n_stats = bnxt_get_num_stats(bp); 2085 info->testinfo_len = bp->num_tests; 2086 /* TODO CHIMP_FW: eeprom dump details */ 2087 info->eedump_len = 0; 2088 /* TODO CHIMP FW: reg dump details */ 2089 info->regdump_len = 0; 2090 } 2091 2092 static int bnxt_get_regs_len(struct net_device *dev) 2093 { 2094 struct bnxt *bp = netdev_priv(dev); 2095 2096 if (!BNXT_PF(bp)) 2097 return -EOPNOTSUPP; 2098 2099 return BNXT_PXP_REG_LEN + bp->pcie_stat_len; 2100 } 2101 2102 static void * 2103 __bnxt_hwrm_pcie_qstats(struct bnxt *bp, struct hwrm_pcie_qstats_input *req) 2104 { 2105 struct pcie_ctx_hw_stats_v2 *hw_pcie_stats; 2106 dma_addr_t hw_pcie_stats_addr; 2107 int rc; 2108 2109 hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats), 2110 &hw_pcie_stats_addr); 2111 if (!hw_pcie_stats) 2112 return NULL; 2113 2114 req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats)); 2115 req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr); 2116 rc = hwrm_req_send(bp, req); 2117 2118 return rc ? NULL : hw_pcie_stats; 2119 } 2120 2121 #define BNXT_PCIE_32B_ENTRY(start, end) \ 2122 { offsetof(struct pcie_ctx_hw_stats_v2, start),\ 2123 offsetof(struct pcie_ctx_hw_stats_v2, end) } 2124 2125 static const struct { 2126 u16 start; 2127 u16 end; 2128 } bnxt_pcie_32b_entries[] = { 2129 BNXT_PCIE_32B_ENTRY(pcie_ltssm_histogram[0], pcie_ltssm_histogram[3]), 2130 BNXT_PCIE_32B_ENTRY(pcie_tl_credit_nph_histogram[0], unused_1), 2131 BNXT_PCIE_32B_ENTRY(pcie_rd_latency_histogram[0], unused_2), 2132 }; 2133 2134 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs, 2135 void *_p) 2136 { 2137 struct hwrm_pcie_qstats_output *resp; 2138 struct hwrm_pcie_qstats_input *req; 2139 struct bnxt *bp = netdev_priv(dev); 2140 u8 *src; 2141 2142 regs->version = 0; 2143 if (!(bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_REG_ACCESS_RESTRICTED)) 2144 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p); 2145 2146 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 2147 return; 2148 2149 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS)) 2150 return; 2151 2152 resp = hwrm_req_hold(bp, req); 2153 src = __bnxt_hwrm_pcie_qstats(bp, req); 2154 if (src) { 2155 u8 *dst = (u8 *)(_p + BNXT_PXP_REG_LEN); 2156 int i, j, len; 2157 2158 len = min(bp->pcie_stat_len, le16_to_cpu(resp->pcie_stat_size)); 2159 if (len <= sizeof(struct pcie_ctx_hw_stats)) 2160 regs->version = 1; 2161 else if (len < sizeof(struct pcie_ctx_hw_stats_v2)) 2162 regs->version = 2; 2163 else 2164 regs->version = 3; 2165 2166 for (i = 0, j = 0; i < len; ) { 2167 if (i >= bnxt_pcie_32b_entries[j].start && 2168 i <= bnxt_pcie_32b_entries[j].end) { 2169 u32 *dst32 = (u32 *)(dst + i); 2170 2171 *dst32 = le32_to_cpu(*(__le32 *)(src + i)); 2172 i += 4; 2173 if (i > bnxt_pcie_32b_entries[j].end && 2174 j < ARRAY_SIZE(bnxt_pcie_32b_entries) - 1) 2175 j++; 2176 } else { 2177 u64 *dst64 = (u64 *)(dst + i); 2178 2179 *dst64 = le64_to_cpu(*(__le64 *)(src + i)); 2180 i += 8; 2181 } 2182 } 2183 } 2184 hwrm_req_drop(bp, req); 2185 } 2186 2187 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2188 { 2189 struct bnxt *bp = netdev_priv(dev); 2190 2191 wol->supported = 0; 2192 wol->wolopts = 0; 2193 memset(&wol->sopass, 0, sizeof(wol->sopass)); 2194 if (bp->flags & BNXT_FLAG_WOL_CAP) { 2195 wol->supported = WAKE_MAGIC; 2196 if (bp->wol) 2197 wol->wolopts = WAKE_MAGIC; 2198 } 2199 } 2200 2201 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2202 { 2203 struct bnxt *bp = netdev_priv(dev); 2204 2205 if (wol->wolopts & ~WAKE_MAGIC) 2206 return -EINVAL; 2207 2208 if (wol->wolopts & WAKE_MAGIC) { 2209 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 2210 return -EINVAL; 2211 if (!bp->wol) { 2212 if (bnxt_hwrm_alloc_wol_fltr(bp)) 2213 return -EBUSY; 2214 bp->wol = 1; 2215 } 2216 } else { 2217 if (bp->wol) { 2218 if (bnxt_hwrm_free_wol_fltr(bp)) 2219 return -EBUSY; 2220 bp->wol = 0; 2221 } 2222 } 2223 return 0; 2224 } 2225 2226 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 2227 void _bnxt_fw_to_linkmode(unsigned long *mode, u16 fw_speeds) 2228 { 2229 linkmode_zero(mode); 2230 2231 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 2232 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode); 2233 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 2234 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode); 2235 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 2236 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT, mode); 2237 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 2238 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode); 2239 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 2240 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode); 2241 } 2242 2243 enum bnxt_media_type { 2244 BNXT_MEDIA_UNKNOWN = 0, 2245 BNXT_MEDIA_TP, 2246 BNXT_MEDIA_CR, 2247 BNXT_MEDIA_SR, 2248 BNXT_MEDIA_LR_ER_FR, 2249 BNXT_MEDIA_KR, 2250 BNXT_MEDIA_KX, 2251 BNXT_MEDIA_X, 2252 __BNXT_MEDIA_END, 2253 }; 2254 2255 static const enum bnxt_media_type bnxt_phy_types[] = { 2256 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR] = BNXT_MEDIA_CR, 2257 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4] = BNXT_MEDIA_KR, 2258 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR] = BNXT_MEDIA_LR_ER_FR, 2259 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR] = BNXT_MEDIA_SR, 2260 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2] = BNXT_MEDIA_KR, 2261 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX] = BNXT_MEDIA_KX, 2262 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR] = BNXT_MEDIA_KR, 2263 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASET] = BNXT_MEDIA_TP, 2264 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE] = BNXT_MEDIA_TP, 2265 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L] = BNXT_MEDIA_CR, 2266 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S] = BNXT_MEDIA_CR, 2267 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N] = BNXT_MEDIA_CR, 2268 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR] = BNXT_MEDIA_SR, 2269 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4] = BNXT_MEDIA_CR, 2270 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4] = BNXT_MEDIA_SR, 2271 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2272 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2273 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10] = BNXT_MEDIA_SR, 2274 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4] = BNXT_MEDIA_CR, 2275 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4] = BNXT_MEDIA_SR, 2276 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2277 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2278 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE] = BNXT_MEDIA_SR, 2279 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET] = BNXT_MEDIA_TP, 2280 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX] = BNXT_MEDIA_X, 2281 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX] = BNXT_MEDIA_X, 2282 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4] = BNXT_MEDIA_CR, 2283 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4] = BNXT_MEDIA_SR, 2284 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2285 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2286 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR] = BNXT_MEDIA_CR, 2287 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR] = BNXT_MEDIA_SR, 2288 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR] = BNXT_MEDIA_LR_ER_FR, 2289 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER] = BNXT_MEDIA_LR_ER_FR, 2290 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2] = BNXT_MEDIA_CR, 2291 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2] = BNXT_MEDIA_SR, 2292 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2] = BNXT_MEDIA_LR_ER_FR, 2293 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2] = BNXT_MEDIA_LR_ER_FR, 2294 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR] = BNXT_MEDIA_CR, 2295 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR] = BNXT_MEDIA_SR, 2296 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR] = BNXT_MEDIA_LR_ER_FR, 2297 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER] = BNXT_MEDIA_LR_ER_FR, 2298 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2] = BNXT_MEDIA_CR, 2299 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2] = BNXT_MEDIA_SR, 2300 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2] = BNXT_MEDIA_LR_ER_FR, 2301 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2] = BNXT_MEDIA_LR_ER_FR, 2302 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8] = BNXT_MEDIA_CR, 2303 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8] = BNXT_MEDIA_SR, 2304 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8] = BNXT_MEDIA_LR_ER_FR, 2305 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8] = BNXT_MEDIA_LR_ER_FR, 2306 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4] = BNXT_MEDIA_CR, 2307 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4] = BNXT_MEDIA_SR, 2308 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2309 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2310 }; 2311 2312 static enum bnxt_media_type 2313 bnxt_get_media(struct bnxt_link_info *link_info) 2314 { 2315 switch (link_info->media_type) { 2316 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP: 2317 return BNXT_MEDIA_TP; 2318 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC: 2319 return BNXT_MEDIA_CR; 2320 default: 2321 if (link_info->phy_type < ARRAY_SIZE(bnxt_phy_types)) 2322 return bnxt_phy_types[link_info->phy_type]; 2323 return BNXT_MEDIA_UNKNOWN; 2324 } 2325 } 2326 2327 enum bnxt_link_speed_indices { 2328 BNXT_LINK_SPEED_UNKNOWN = 0, 2329 BNXT_LINK_SPEED_100MB_IDX, 2330 BNXT_LINK_SPEED_1GB_IDX, 2331 BNXT_LINK_SPEED_10GB_IDX, 2332 BNXT_LINK_SPEED_25GB_IDX, 2333 BNXT_LINK_SPEED_40GB_IDX, 2334 BNXT_LINK_SPEED_50GB_IDX, 2335 BNXT_LINK_SPEED_100GB_IDX, 2336 BNXT_LINK_SPEED_200GB_IDX, 2337 BNXT_LINK_SPEED_400GB_IDX, 2338 __BNXT_LINK_SPEED_END 2339 }; 2340 2341 static enum bnxt_link_speed_indices bnxt_fw_speed_idx(u16 speed) 2342 { 2343 switch (speed) { 2344 case BNXT_LINK_SPEED_100MB: return BNXT_LINK_SPEED_100MB_IDX; 2345 case BNXT_LINK_SPEED_1GB: return BNXT_LINK_SPEED_1GB_IDX; 2346 case BNXT_LINK_SPEED_10GB: return BNXT_LINK_SPEED_10GB_IDX; 2347 case BNXT_LINK_SPEED_25GB: return BNXT_LINK_SPEED_25GB_IDX; 2348 case BNXT_LINK_SPEED_40GB: return BNXT_LINK_SPEED_40GB_IDX; 2349 case BNXT_LINK_SPEED_50GB: 2350 case BNXT_LINK_SPEED_50GB_PAM4: 2351 return BNXT_LINK_SPEED_50GB_IDX; 2352 case BNXT_LINK_SPEED_100GB: 2353 case BNXT_LINK_SPEED_100GB_PAM4: 2354 case BNXT_LINK_SPEED_100GB_PAM4_112: 2355 return BNXT_LINK_SPEED_100GB_IDX; 2356 case BNXT_LINK_SPEED_200GB: 2357 case BNXT_LINK_SPEED_200GB_PAM4: 2358 case BNXT_LINK_SPEED_200GB_PAM4_112: 2359 return BNXT_LINK_SPEED_200GB_IDX; 2360 case BNXT_LINK_SPEED_400GB: 2361 case BNXT_LINK_SPEED_400GB_PAM4: 2362 case BNXT_LINK_SPEED_400GB_PAM4_112: 2363 return BNXT_LINK_SPEED_400GB_IDX; 2364 default: return BNXT_LINK_SPEED_UNKNOWN; 2365 } 2366 } 2367 2368 static const enum ethtool_link_mode_bit_indices 2369 bnxt_link_modes[__BNXT_LINK_SPEED_END][BNXT_SIG_MODE_MAX][__BNXT_MEDIA_END] = { 2370 [BNXT_LINK_SPEED_100MB_IDX] = { 2371 { 2372 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_100baseT_Full_BIT, 2373 }, 2374 }, 2375 [BNXT_LINK_SPEED_1GB_IDX] = { 2376 { 2377 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 2378 /* historically baseT, but DAC is more correctly baseX */ 2379 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 2380 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2381 [BNXT_MEDIA_X] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 2382 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2383 }, 2384 }, 2385 [BNXT_LINK_SPEED_10GB_IDX] = { 2386 { 2387 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 2388 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 2389 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 2390 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 2391 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 2392 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 2393 }, 2394 }, 2395 [BNXT_LINK_SPEED_25GB_IDX] = { 2396 { 2397 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 2398 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 2399 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 2400 }, 2401 }, 2402 [BNXT_LINK_SPEED_40GB_IDX] = { 2403 { 2404 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 2405 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 2406 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 2407 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 2408 }, 2409 }, 2410 [BNXT_LINK_SPEED_50GB_IDX] = { 2411 [BNXT_SIG_MODE_NRZ] = { 2412 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 2413 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 2414 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 2415 }, 2416 [BNXT_SIG_MODE_PAM4] = { 2417 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 2418 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 2419 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 2420 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 2421 }, 2422 }, 2423 [BNXT_LINK_SPEED_100GB_IDX] = { 2424 [BNXT_SIG_MODE_NRZ] = { 2425 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 2426 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 2427 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 2428 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 2429 }, 2430 [BNXT_SIG_MODE_PAM4] = { 2431 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 2432 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 2433 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 2434 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 2435 }, 2436 [BNXT_SIG_MODE_PAM4_112] = { 2437 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR_Full_BIT, 2438 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR_Full_BIT, 2439 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR_Full_BIT, 2440 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT, 2441 }, 2442 }, 2443 [BNXT_LINK_SPEED_200GB_IDX] = { 2444 [BNXT_SIG_MODE_PAM4] = { 2445 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT, 2446 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 2447 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 2448 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 2449 }, 2450 [BNXT_SIG_MODE_PAM4_112] = { 2451 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT, 2452 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT, 2453 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT, 2454 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT, 2455 }, 2456 }, 2457 [BNXT_LINK_SPEED_400GB_IDX] = { 2458 [BNXT_SIG_MODE_PAM4] = { 2459 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT, 2460 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT, 2461 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT, 2462 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT, 2463 }, 2464 [BNXT_SIG_MODE_PAM4_112] = { 2465 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT, 2466 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT, 2467 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT, 2468 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT, 2469 }, 2470 }, 2471 }; 2472 2473 #define BNXT_LINK_MODE_UNKNOWN -1 2474 2475 static enum ethtool_link_mode_bit_indices 2476 bnxt_get_link_mode(struct bnxt_link_info *link_info) 2477 { 2478 enum ethtool_link_mode_bit_indices link_mode; 2479 enum bnxt_link_speed_indices speed; 2480 enum bnxt_media_type media; 2481 u8 sig_mode; 2482 2483 if (link_info->phy_link_status != BNXT_LINK_LINK) 2484 return BNXT_LINK_MODE_UNKNOWN; 2485 2486 media = bnxt_get_media(link_info); 2487 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 2488 speed = bnxt_fw_speed_idx(link_info->link_speed); 2489 sig_mode = link_info->active_fec_sig_mode & 2490 PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK; 2491 } else { 2492 speed = bnxt_fw_speed_idx(link_info->req_link_speed); 2493 sig_mode = link_info->req_signal_mode; 2494 } 2495 if (sig_mode >= BNXT_SIG_MODE_MAX) 2496 return BNXT_LINK_MODE_UNKNOWN; 2497 2498 /* Note ETHTOOL_LINK_MODE_10baseT_Half_BIT == 0 is a legal Linux 2499 * link mode, but since no such devices exist, the zeroes in the 2500 * map can be conveniently used to represent unknown link modes. 2501 */ 2502 link_mode = bnxt_link_modes[speed][sig_mode][media]; 2503 if (!link_mode) 2504 return BNXT_LINK_MODE_UNKNOWN; 2505 2506 switch (link_mode) { 2507 case ETHTOOL_LINK_MODE_100baseT_Full_BIT: 2508 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2509 link_mode = ETHTOOL_LINK_MODE_100baseT_Half_BIT; 2510 break; 2511 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT: 2512 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2513 link_mode = ETHTOOL_LINK_MODE_1000baseT_Half_BIT; 2514 break; 2515 default: 2516 break; 2517 } 2518 2519 return link_mode; 2520 } 2521 2522 static void bnxt_get_ethtool_modes(struct bnxt_link_info *link_info, 2523 struct ethtool_link_ksettings *lk_ksettings) 2524 { 2525 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2526 2527 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) { 2528 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2529 lk_ksettings->link_modes.supported); 2530 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2531 lk_ksettings->link_modes.supported); 2532 } 2533 2534 if (link_info->support_auto_speeds || link_info->support_auto_speeds2 || 2535 link_info->support_pam4_auto_speeds) 2536 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2537 lk_ksettings->link_modes.supported); 2538 2539 if (~link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 2540 return; 2541 2542 if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_RX) 2543 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2544 lk_ksettings->link_modes.advertising); 2545 if (hweight8(link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) == 1) 2546 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2547 lk_ksettings->link_modes.advertising); 2548 if (link_info->lp_pause & BNXT_LINK_PAUSE_RX) 2549 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2550 lk_ksettings->link_modes.lp_advertising); 2551 if (hweight8(link_info->lp_pause & BNXT_LINK_PAUSE_BOTH) == 1) 2552 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2553 lk_ksettings->link_modes.lp_advertising); 2554 } 2555 2556 static const u16 bnxt_nrz_speed_masks[] = { 2557 [BNXT_LINK_SPEED_100MB_IDX] = BNXT_LINK_SPEED_MSK_100MB, 2558 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEED_MSK_1GB, 2559 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEED_MSK_10GB, 2560 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEED_MSK_25GB, 2561 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEED_MSK_40GB, 2562 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEED_MSK_50GB, 2563 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEED_MSK_100GB, 2564 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2565 }; 2566 2567 static const u16 bnxt_pam4_speed_masks[] = { 2568 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_50GB, 2569 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_100GB, 2570 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_200GB, 2571 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2572 }; 2573 2574 static const u16 bnxt_nrz_speeds2_masks[] = { 2575 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEEDS2_MSK_1GB, 2576 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEEDS2_MSK_10GB, 2577 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEEDS2_MSK_25GB, 2578 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEEDS2_MSK_40GB, 2579 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB, 2580 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB, 2581 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2582 }; 2583 2584 static const u16 bnxt_pam4_speeds2_masks[] = { 2585 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB_PAM4, 2586 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4, 2587 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4, 2588 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4, 2589 }; 2590 2591 static const u16 bnxt_pam4_112_speeds2_masks[] = { 2592 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112, 2593 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112, 2594 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112, 2595 }; 2596 2597 static enum bnxt_link_speed_indices 2598 bnxt_encoding_speed_idx(u8 sig_mode, u16 phy_flags, u16 speed_msk) 2599 { 2600 const u16 *speeds; 2601 int idx, len; 2602 2603 switch (sig_mode) { 2604 case BNXT_SIG_MODE_NRZ: 2605 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2606 speeds = bnxt_nrz_speeds2_masks; 2607 len = ARRAY_SIZE(bnxt_nrz_speeds2_masks); 2608 } else { 2609 speeds = bnxt_nrz_speed_masks; 2610 len = ARRAY_SIZE(bnxt_nrz_speed_masks); 2611 } 2612 break; 2613 case BNXT_SIG_MODE_PAM4: 2614 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2615 speeds = bnxt_pam4_speeds2_masks; 2616 len = ARRAY_SIZE(bnxt_pam4_speeds2_masks); 2617 } else { 2618 speeds = bnxt_pam4_speed_masks; 2619 len = ARRAY_SIZE(bnxt_pam4_speed_masks); 2620 } 2621 break; 2622 case BNXT_SIG_MODE_PAM4_112: 2623 speeds = bnxt_pam4_112_speeds2_masks; 2624 len = ARRAY_SIZE(bnxt_pam4_112_speeds2_masks); 2625 break; 2626 default: 2627 return BNXT_LINK_SPEED_UNKNOWN; 2628 } 2629 2630 for (idx = 0; idx < len; idx++) { 2631 if (speeds[idx] == speed_msk) 2632 return idx; 2633 } 2634 2635 return BNXT_LINK_SPEED_UNKNOWN; 2636 } 2637 2638 #define BNXT_FW_SPEED_MSK_BITS 16 2639 2640 static void 2641 __bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media, 2642 u8 sig_mode, u16 phy_flags, unsigned long *et_mask) 2643 { 2644 enum ethtool_link_mode_bit_indices link_mode; 2645 enum bnxt_link_speed_indices speed; 2646 u8 bit; 2647 2648 for_each_set_bit(bit, &fw_mask, BNXT_FW_SPEED_MSK_BITS) { 2649 speed = bnxt_encoding_speed_idx(sig_mode, phy_flags, 1 << bit); 2650 if (!speed) 2651 continue; 2652 2653 link_mode = bnxt_link_modes[speed][sig_mode][media]; 2654 if (!link_mode) 2655 continue; 2656 2657 linkmode_set_bit(link_mode, et_mask); 2658 } 2659 } 2660 2661 static void 2662 bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media, 2663 u8 sig_mode, u16 phy_flags, unsigned long *et_mask) 2664 { 2665 if (media) { 2666 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags, 2667 et_mask); 2668 return; 2669 } 2670 2671 /* list speeds for all media if unknown */ 2672 for (media = 1; media < __BNXT_MEDIA_END; media++) 2673 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags, 2674 et_mask); 2675 } 2676 2677 static void 2678 bnxt_get_all_ethtool_support_speeds(struct bnxt_link_info *link_info, 2679 enum bnxt_media_type media, 2680 struct ethtool_link_ksettings *lk_ksettings) 2681 { 2682 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2683 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0; 2684 u16 phy_flags = bp->phy_flags; 2685 2686 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2687 sp_nrz = link_info->support_speeds2; 2688 sp_pam4 = link_info->support_speeds2; 2689 sp_pam4_112 = link_info->support_speeds2; 2690 } else { 2691 sp_nrz = link_info->support_speeds; 2692 sp_pam4 = link_info->support_pam4_speeds; 2693 } 2694 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags, 2695 lk_ksettings->link_modes.supported); 2696 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags, 2697 lk_ksettings->link_modes.supported); 2698 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112, 2699 phy_flags, lk_ksettings->link_modes.supported); 2700 } 2701 2702 static void 2703 bnxt_get_all_ethtool_adv_speeds(struct bnxt_link_info *link_info, 2704 enum bnxt_media_type media, 2705 struct ethtool_link_ksettings *lk_ksettings) 2706 { 2707 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2708 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0; 2709 u16 phy_flags = bp->phy_flags; 2710 2711 sp_nrz = link_info->advertising; 2712 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2713 sp_pam4 = link_info->advertising; 2714 sp_pam4_112 = link_info->advertising; 2715 } else { 2716 sp_pam4 = link_info->advertising_pam4; 2717 } 2718 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags, 2719 lk_ksettings->link_modes.advertising); 2720 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags, 2721 lk_ksettings->link_modes.advertising); 2722 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112, 2723 phy_flags, lk_ksettings->link_modes.advertising); 2724 } 2725 2726 static void 2727 bnxt_get_all_ethtool_lp_speeds(struct bnxt_link_info *link_info, 2728 enum bnxt_media_type media, 2729 struct ethtool_link_ksettings *lk_ksettings) 2730 { 2731 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2732 u16 phy_flags = bp->phy_flags; 2733 2734 bnxt_get_ethtool_speeds(link_info->lp_auto_link_speeds, media, 2735 BNXT_SIG_MODE_NRZ, phy_flags, 2736 lk_ksettings->link_modes.lp_advertising); 2737 bnxt_get_ethtool_speeds(link_info->lp_auto_pam4_link_speeds, media, 2738 BNXT_SIG_MODE_PAM4, phy_flags, 2739 lk_ksettings->link_modes.lp_advertising); 2740 } 2741 2742 static void bnxt_update_speed(u32 *delta, bool installed_media, u16 *speeds, 2743 u16 speed_msk, const unsigned long *et_mask, 2744 enum ethtool_link_mode_bit_indices mode) 2745 { 2746 bool mode_desired = linkmode_test_bit(mode, et_mask); 2747 2748 if (!mode) 2749 return; 2750 2751 /* enabled speeds for installed media should override */ 2752 if (installed_media && mode_desired) { 2753 *speeds |= speed_msk; 2754 *delta |= speed_msk; 2755 return; 2756 } 2757 2758 /* many to one mapping, only allow one change per fw_speed bit */ 2759 if (!(*delta & speed_msk) && (mode_desired == !(*speeds & speed_msk))) { 2760 *speeds ^= speed_msk; 2761 *delta |= speed_msk; 2762 } 2763 } 2764 2765 static void bnxt_set_ethtool_speeds(struct bnxt_link_info *link_info, 2766 const unsigned long *et_mask) 2767 { 2768 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2769 u16 const *sp_msks, *sp_pam4_msks, *sp_pam4_112_msks; 2770 enum bnxt_media_type media = bnxt_get_media(link_info); 2771 u16 *adv, *adv_pam4, *adv_pam4_112 = NULL; 2772 u32 delta_pam4_112 = 0; 2773 u32 delta_pam4 = 0; 2774 u32 delta_nrz = 0; 2775 int i, m; 2776 2777 adv = &link_info->advertising; 2778 if (bp->phy_flags & BNXT_PHY_FL_SPEEDS2) { 2779 adv_pam4 = &link_info->advertising; 2780 adv_pam4_112 = &link_info->advertising; 2781 sp_msks = bnxt_nrz_speeds2_masks; 2782 sp_pam4_msks = bnxt_pam4_speeds2_masks; 2783 sp_pam4_112_msks = bnxt_pam4_112_speeds2_masks; 2784 } else { 2785 adv_pam4 = &link_info->advertising_pam4; 2786 sp_msks = bnxt_nrz_speed_masks; 2787 sp_pam4_msks = bnxt_pam4_speed_masks; 2788 } 2789 for (i = 1; i < __BNXT_LINK_SPEED_END; i++) { 2790 /* accept any legal media from user */ 2791 for (m = 1; m < __BNXT_MEDIA_END; m++) { 2792 bnxt_update_speed(&delta_nrz, m == media, 2793 adv, sp_msks[i], et_mask, 2794 bnxt_link_modes[i][BNXT_SIG_MODE_NRZ][m]); 2795 bnxt_update_speed(&delta_pam4, m == media, 2796 adv_pam4, sp_pam4_msks[i], et_mask, 2797 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4][m]); 2798 if (!adv_pam4_112) 2799 continue; 2800 2801 bnxt_update_speed(&delta_pam4_112, m == media, 2802 adv_pam4_112, sp_pam4_112_msks[i], et_mask, 2803 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4_112][m]); 2804 } 2805 } 2806 } 2807 2808 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info, 2809 struct ethtool_link_ksettings *lk_ksettings) 2810 { 2811 u16 fec_cfg = link_info->fec_cfg; 2812 2813 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) { 2814 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 2815 lk_ksettings->link_modes.advertising); 2816 return; 2817 } 2818 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 2819 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 2820 lk_ksettings->link_modes.advertising); 2821 if (fec_cfg & BNXT_FEC_ENC_RS) 2822 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 2823 lk_ksettings->link_modes.advertising); 2824 if (fec_cfg & BNXT_FEC_ENC_LLRS) 2825 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 2826 lk_ksettings->link_modes.advertising); 2827 } 2828 2829 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info, 2830 struct ethtool_link_ksettings *lk_ksettings) 2831 { 2832 u16 fec_cfg = link_info->fec_cfg; 2833 2834 if (fec_cfg & BNXT_FEC_NONE) { 2835 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 2836 lk_ksettings->link_modes.supported); 2837 return; 2838 } 2839 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP) 2840 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 2841 lk_ksettings->link_modes.supported); 2842 if (fec_cfg & BNXT_FEC_ENC_RS_CAP) 2843 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 2844 lk_ksettings->link_modes.supported); 2845 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP) 2846 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 2847 lk_ksettings->link_modes.supported); 2848 } 2849 2850 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 2851 { 2852 switch (fw_link_speed) { 2853 case BNXT_LINK_SPEED_100MB: 2854 return SPEED_100; 2855 case BNXT_LINK_SPEED_1GB: 2856 return SPEED_1000; 2857 case BNXT_LINK_SPEED_2_5GB: 2858 return SPEED_2500; 2859 case BNXT_LINK_SPEED_10GB: 2860 return SPEED_10000; 2861 case BNXT_LINK_SPEED_20GB: 2862 return SPEED_20000; 2863 case BNXT_LINK_SPEED_25GB: 2864 return SPEED_25000; 2865 case BNXT_LINK_SPEED_40GB: 2866 return SPEED_40000; 2867 case BNXT_LINK_SPEED_50GB: 2868 case BNXT_LINK_SPEED_50GB_PAM4: 2869 return SPEED_50000; 2870 case BNXT_LINK_SPEED_100GB: 2871 case BNXT_LINK_SPEED_100GB_PAM4: 2872 case BNXT_LINK_SPEED_100GB_PAM4_112: 2873 return SPEED_100000; 2874 case BNXT_LINK_SPEED_200GB: 2875 case BNXT_LINK_SPEED_200GB_PAM4: 2876 case BNXT_LINK_SPEED_200GB_PAM4_112: 2877 return SPEED_200000; 2878 case BNXT_LINK_SPEED_400GB: 2879 case BNXT_LINK_SPEED_400GB_PAM4: 2880 case BNXT_LINK_SPEED_400GB_PAM4_112: 2881 return SPEED_400000; 2882 default: 2883 return SPEED_UNKNOWN; 2884 } 2885 } 2886 2887 static void bnxt_get_default_speeds(struct ethtool_link_ksettings *lk_ksettings, 2888 struct bnxt_link_info *link_info) 2889 { 2890 struct ethtool_link_settings *base = &lk_ksettings->base; 2891 2892 if (link_info->link_state == BNXT_LINK_STATE_UP) { 2893 base->speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 2894 base->duplex = DUPLEX_HALF; 2895 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2896 base->duplex = DUPLEX_FULL; 2897 lk_ksettings->lanes = link_info->active_lanes; 2898 } else if (!link_info->autoneg) { 2899 base->speed = bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 2900 base->duplex = DUPLEX_HALF; 2901 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 2902 base->duplex = DUPLEX_FULL; 2903 } 2904 } 2905 2906 static int bnxt_get_link_ksettings(struct net_device *dev, 2907 struct ethtool_link_ksettings *lk_ksettings) 2908 { 2909 struct ethtool_link_settings *base = &lk_ksettings->base; 2910 enum ethtool_link_mode_bit_indices link_mode; 2911 struct bnxt *bp = netdev_priv(dev); 2912 struct bnxt_link_info *link_info; 2913 enum bnxt_media_type media; 2914 2915 ethtool_link_ksettings_zero_link_mode(lk_ksettings, lp_advertising); 2916 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 2917 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 2918 base->duplex = DUPLEX_UNKNOWN; 2919 base->speed = SPEED_UNKNOWN; 2920 link_info = &bp->link_info; 2921 2922 mutex_lock(&bp->link_lock); 2923 bnxt_get_ethtool_modes(link_info, lk_ksettings); 2924 media = bnxt_get_media(link_info); 2925 bnxt_get_all_ethtool_support_speeds(link_info, media, lk_ksettings); 2926 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings); 2927 link_mode = bnxt_get_link_mode(link_info); 2928 if (link_mode != BNXT_LINK_MODE_UNKNOWN) 2929 ethtool_params_from_link_mode(lk_ksettings, link_mode); 2930 else 2931 bnxt_get_default_speeds(lk_ksettings, link_info); 2932 2933 if (link_info->autoneg) { 2934 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings); 2935 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2936 lk_ksettings->link_modes.advertising); 2937 base->autoneg = AUTONEG_ENABLE; 2938 bnxt_get_all_ethtool_adv_speeds(link_info, media, lk_ksettings); 2939 if (link_info->phy_link_status == BNXT_LINK_LINK) 2940 bnxt_get_all_ethtool_lp_speeds(link_info, media, 2941 lk_ksettings); 2942 } else { 2943 base->autoneg = AUTONEG_DISABLE; 2944 } 2945 2946 base->port = PORT_NONE; 2947 if (media == BNXT_MEDIA_TP) { 2948 base->port = PORT_TP; 2949 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2950 lk_ksettings->link_modes.supported); 2951 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2952 lk_ksettings->link_modes.advertising); 2953 } else if (media == BNXT_MEDIA_KR) { 2954 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, 2955 lk_ksettings->link_modes.supported); 2956 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, 2957 lk_ksettings->link_modes.advertising); 2958 } else { 2959 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 2960 lk_ksettings->link_modes.supported); 2961 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 2962 lk_ksettings->link_modes.advertising); 2963 2964 if (media == BNXT_MEDIA_CR) 2965 base->port = PORT_DA; 2966 else 2967 base->port = PORT_FIBRE; 2968 } 2969 base->phy_address = link_info->phy_addr; 2970 mutex_unlock(&bp->link_lock); 2971 2972 return 0; 2973 } 2974 2975 static int 2976 bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed, u32 lanes) 2977 { 2978 struct bnxt *bp = netdev_priv(dev); 2979 struct bnxt_link_info *link_info = &bp->link_info; 2980 u16 support_pam4_spds = link_info->support_pam4_speeds; 2981 u16 support_spds2 = link_info->support_speeds2; 2982 u16 support_spds = link_info->support_speeds; 2983 u8 sig_mode = BNXT_SIG_MODE_NRZ; 2984 u32 lanes_needed = 1; 2985 u16 fw_speed = 0; 2986 2987 switch (ethtool_speed) { 2988 case SPEED_100: 2989 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 2990 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB; 2991 break; 2992 case SPEED_1000: 2993 if ((support_spds & BNXT_LINK_SPEED_MSK_1GB) || 2994 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_1GB)) 2995 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 2996 break; 2997 case SPEED_2500: 2998 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 2999 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB; 3000 break; 3001 case SPEED_10000: 3002 if ((support_spds & BNXT_LINK_SPEED_MSK_10GB) || 3003 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_10GB)) 3004 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 3005 break; 3006 case SPEED_20000: 3007 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) { 3008 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB; 3009 lanes_needed = 2; 3010 } 3011 break; 3012 case SPEED_25000: 3013 if ((support_spds & BNXT_LINK_SPEED_MSK_25GB) || 3014 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_25GB)) 3015 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 3016 break; 3017 case SPEED_40000: 3018 if ((support_spds & BNXT_LINK_SPEED_MSK_40GB) || 3019 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_40GB)) { 3020 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 3021 lanes_needed = 4; 3022 } 3023 break; 3024 case SPEED_50000: 3025 if (((support_spds & BNXT_LINK_SPEED_MSK_50GB) || 3026 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB)) && 3027 lanes != 1) { 3028 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 3029 lanes_needed = 2; 3030 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) { 3031 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB; 3032 sig_mode = BNXT_SIG_MODE_PAM4; 3033 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB_PAM4) { 3034 fw_speed = BNXT_LINK_SPEED_50GB_PAM4; 3035 sig_mode = BNXT_SIG_MODE_PAM4; 3036 } 3037 break; 3038 case SPEED_100000: 3039 if (((support_spds & BNXT_LINK_SPEED_MSK_100GB) || 3040 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB)) && 3041 lanes != 2 && lanes != 1) { 3042 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB; 3043 lanes_needed = 4; 3044 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) { 3045 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB; 3046 sig_mode = BNXT_SIG_MODE_PAM4; 3047 lanes_needed = 2; 3048 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4) && 3049 lanes != 1) { 3050 fw_speed = BNXT_LINK_SPEED_100GB_PAM4; 3051 sig_mode = BNXT_SIG_MODE_PAM4; 3052 lanes_needed = 2; 3053 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112) { 3054 fw_speed = BNXT_LINK_SPEED_100GB_PAM4_112; 3055 sig_mode = BNXT_SIG_MODE_PAM4_112; 3056 } 3057 break; 3058 case SPEED_200000: 3059 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) { 3060 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB; 3061 sig_mode = BNXT_SIG_MODE_PAM4; 3062 lanes_needed = 4; 3063 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4) && 3064 lanes != 2) { 3065 fw_speed = BNXT_LINK_SPEED_200GB_PAM4; 3066 sig_mode = BNXT_SIG_MODE_PAM4; 3067 lanes_needed = 4; 3068 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112) { 3069 fw_speed = BNXT_LINK_SPEED_200GB_PAM4_112; 3070 sig_mode = BNXT_SIG_MODE_PAM4_112; 3071 lanes_needed = 2; 3072 } 3073 break; 3074 case SPEED_400000: 3075 if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4) && 3076 lanes != 4) { 3077 fw_speed = BNXT_LINK_SPEED_400GB_PAM4; 3078 sig_mode = BNXT_SIG_MODE_PAM4; 3079 lanes_needed = 8; 3080 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112) { 3081 fw_speed = BNXT_LINK_SPEED_400GB_PAM4_112; 3082 sig_mode = BNXT_SIG_MODE_PAM4_112; 3083 lanes_needed = 4; 3084 } 3085 break; 3086 } 3087 3088 if (!fw_speed) { 3089 netdev_err(dev, "unsupported speed!\n"); 3090 return -EINVAL; 3091 } 3092 3093 if (lanes && lanes != lanes_needed) { 3094 netdev_err(dev, "unsupported number of lanes for speed\n"); 3095 return -EINVAL; 3096 } 3097 3098 if (link_info->req_link_speed == fw_speed && 3099 link_info->req_signal_mode == sig_mode && 3100 link_info->autoneg == 0) 3101 return -EALREADY; 3102 3103 link_info->req_link_speed = fw_speed; 3104 link_info->req_signal_mode = sig_mode; 3105 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 3106 link_info->autoneg = 0; 3107 link_info->advertising = 0; 3108 link_info->advertising_pam4 = 0; 3109 3110 return 0; 3111 } 3112 3113 u16 bnxt_get_fw_auto_link_speeds(const unsigned long *mode) 3114 { 3115 u16 fw_speed_mask = 0; 3116 3117 if (linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode) || 3118 linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mode)) 3119 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 3120 3121 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode) || 3122 linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, mode)) 3123 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 3124 3125 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode)) 3126 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 3127 3128 if (linkmode_test_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode)) 3129 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 3130 3131 return fw_speed_mask; 3132 } 3133 3134 static int bnxt_set_link_ksettings(struct net_device *dev, 3135 const struct ethtool_link_ksettings *lk_ksettings) 3136 { 3137 struct bnxt *bp = netdev_priv(dev); 3138 struct bnxt_link_info *link_info = &bp->link_info; 3139 const struct ethtool_link_settings *base = &lk_ksettings->base; 3140 bool set_pause = false; 3141 u32 speed, lanes = 0; 3142 int rc = 0; 3143 3144 if (!BNXT_PHY_CFG_ABLE(bp)) 3145 return -EOPNOTSUPP; 3146 3147 mutex_lock(&bp->link_lock); 3148 if (base->autoneg == AUTONEG_ENABLE) { 3149 bnxt_set_ethtool_speeds(link_info, 3150 lk_ksettings->link_modes.advertising); 3151 link_info->autoneg |= BNXT_AUTONEG_SPEED; 3152 if (!link_info->advertising && !link_info->advertising_pam4) { 3153 link_info->advertising = link_info->support_auto_speeds; 3154 link_info->advertising_pam4 = 3155 link_info->support_pam4_auto_speeds; 3156 } 3157 /* any change to autoneg will cause link change, therefore the 3158 * driver should put back the original pause setting in autoneg 3159 */ 3160 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 3161 set_pause = true; 3162 } else { 3163 u8 phy_type = link_info->phy_type; 3164 3165 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 3166 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 3167 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 3168 netdev_err(dev, "10GBase-T devices must autoneg\n"); 3169 rc = -EINVAL; 3170 goto set_setting_exit; 3171 } 3172 if (base->duplex == DUPLEX_HALF) { 3173 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 3174 rc = -EINVAL; 3175 goto set_setting_exit; 3176 } 3177 speed = base->speed; 3178 lanes = lk_ksettings->lanes; 3179 rc = bnxt_force_link_speed(dev, speed, lanes); 3180 if (rc) { 3181 if (rc == -EALREADY) 3182 rc = 0; 3183 goto set_setting_exit; 3184 } 3185 } 3186 3187 if (netif_running(dev)) 3188 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 3189 3190 set_setting_exit: 3191 mutex_unlock(&bp->link_lock); 3192 return rc; 3193 } 3194 3195 static int bnxt_get_fecparam(struct net_device *dev, 3196 struct ethtool_fecparam *fec) 3197 { 3198 struct bnxt *bp = netdev_priv(dev); 3199 struct bnxt_link_info *link_info; 3200 u8 active_fec; 3201 u16 fec_cfg; 3202 3203 link_info = &bp->link_info; 3204 fec_cfg = link_info->fec_cfg; 3205 active_fec = link_info->active_fec_sig_mode & 3206 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK; 3207 if (fec_cfg & BNXT_FEC_NONE) { 3208 fec->fec = ETHTOOL_FEC_NONE; 3209 fec->active_fec = ETHTOOL_FEC_NONE; 3210 return 0; 3211 } 3212 if (fec_cfg & BNXT_FEC_AUTONEG) 3213 fec->fec |= ETHTOOL_FEC_AUTO; 3214 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 3215 fec->fec |= ETHTOOL_FEC_BASER; 3216 if (fec_cfg & BNXT_FEC_ENC_RS) 3217 fec->fec |= ETHTOOL_FEC_RS; 3218 if (fec_cfg & BNXT_FEC_ENC_LLRS) 3219 fec->fec |= ETHTOOL_FEC_LLRS; 3220 3221 switch (active_fec) { 3222 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE: 3223 fec->active_fec |= ETHTOOL_FEC_BASER; 3224 break; 3225 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE: 3226 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE: 3227 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE: 3228 fec->active_fec |= ETHTOOL_FEC_RS; 3229 break; 3230 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE: 3231 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE: 3232 fec->active_fec |= ETHTOOL_FEC_LLRS; 3233 break; 3234 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE: 3235 fec->active_fec |= ETHTOOL_FEC_OFF; 3236 break; 3237 } 3238 return 0; 3239 } 3240 3241 static const struct ethtool_fec_hist_range bnxt_fec_ranges[] = { 3242 { 0, 0}, 3243 { 1, 1}, 3244 { 2, 2}, 3245 { 3, 3}, 3246 { 4, 4}, 3247 { 5, 5}, 3248 { 6, 6}, 3249 { 7, 7}, 3250 { 8, 8}, 3251 { 9, 9}, 3252 { 10, 10}, 3253 { 11, 11}, 3254 { 12, 12}, 3255 { 13, 13}, 3256 { 14, 14}, 3257 { 15, 15}, 3258 { 0, 0}, 3259 }; 3260 3261 static void bnxt_hwrm_port_phy_fdrstat(struct bnxt *bp, 3262 struct ethtool_fec_hist *hist) 3263 { 3264 struct ethtool_fec_hist_value *values = hist->values; 3265 struct hwrm_port_phy_fdrstat_output *resp; 3266 struct hwrm_port_phy_fdrstat_input *req; 3267 int rc, i; 3268 3269 if (!(bp->phy_flags & BNXT_PHY_FL_FDRSTATS)) 3270 return; 3271 3272 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_FDRSTAT); 3273 if (rc) 3274 return; 3275 3276 req->port_id = cpu_to_le16(bp->pf.port_id); 3277 req->ops = cpu_to_le16(PORT_PHY_FDRSTAT_REQ_OPS_COUNTER); 3278 resp = hwrm_req_hold(bp, req); 3279 rc = hwrm_req_send(bp, req); 3280 if (!rc) { 3281 hist->ranges = bnxt_fec_ranges; 3282 for (i = 0; i <= 15; i++) { 3283 __le64 sum = resp->accumulated_codewords_err_s[i]; 3284 3285 values[i].sum = le64_to_cpu(sum); 3286 } 3287 } 3288 hwrm_req_drop(bp, req); 3289 } 3290 3291 static void bnxt_get_fec_stats(struct net_device *dev, 3292 struct ethtool_fec_stats *fec_stats, 3293 struct ethtool_fec_hist *hist) 3294 { 3295 struct bnxt *bp = netdev_priv(dev); 3296 u64 *rx; 3297 3298 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 3299 return; 3300 3301 rx = bp->rx_port_stats_ext.sw_stats; 3302 fec_stats->corrected_bits.total = 3303 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits)); 3304 3305 if (bp->fw_rx_stats_ext_size <= BNXT_RX_STATS_EXT_NUM_LEGACY) 3306 return; 3307 3308 fec_stats->corrected_blocks.total = 3309 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)); 3310 fec_stats->uncorrectable_blocks.total = 3311 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_uncorrectable_blocks)); 3312 bnxt_hwrm_port_phy_fdrstat(bp, hist); 3313 } 3314 3315 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info, 3316 u32 fec) 3317 { 3318 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE; 3319 3320 if (fec & ETHTOOL_FEC_BASER) 3321 fw_fec |= BNXT_FEC_BASE_R_ON(link_info); 3322 else if (fec & ETHTOOL_FEC_RS) 3323 fw_fec |= BNXT_FEC_RS_ON(link_info); 3324 else if (fec & ETHTOOL_FEC_LLRS) 3325 fw_fec |= BNXT_FEC_LLRS_ON; 3326 return fw_fec; 3327 } 3328 3329 static int bnxt_set_fecparam(struct net_device *dev, 3330 struct ethtool_fecparam *fecparam) 3331 { 3332 struct hwrm_port_phy_cfg_input *req; 3333 struct bnxt *bp = netdev_priv(dev); 3334 struct bnxt_link_info *link_info; 3335 u32 new_cfg, fec = fecparam->fec; 3336 u16 fec_cfg; 3337 int rc; 3338 3339 link_info = &bp->link_info; 3340 fec_cfg = link_info->fec_cfg; 3341 if (fec_cfg & BNXT_FEC_NONE) 3342 return -EOPNOTSUPP; 3343 3344 if (fec & ETHTOOL_FEC_OFF) { 3345 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE | 3346 BNXT_FEC_ALL_OFF(link_info); 3347 goto apply_fec; 3348 } 3349 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) || 3350 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) || 3351 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) || 3352 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP))) 3353 return -EINVAL; 3354 3355 if (fec & ETHTOOL_FEC_AUTO) { 3356 if (!link_info->autoneg) 3357 return -EINVAL; 3358 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE; 3359 } else { 3360 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec); 3361 } 3362 3363 apply_fec: 3364 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 3365 if (rc) 3366 return rc; 3367 req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 3368 rc = hwrm_req_send(bp, req); 3369 /* update current settings */ 3370 if (!rc) { 3371 mutex_lock(&bp->link_lock); 3372 bnxt_update_link(bp, false); 3373 mutex_unlock(&bp->link_lock); 3374 } 3375 return rc; 3376 } 3377 3378 static void bnxt_get_pauseparam(struct net_device *dev, 3379 struct ethtool_pauseparam *epause) 3380 { 3381 struct bnxt *bp = netdev_priv(dev); 3382 struct bnxt_link_info *link_info = &bp->link_info; 3383 3384 if (BNXT_VF(bp)) 3385 return; 3386 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 3387 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 3388 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 3389 } 3390 3391 static void bnxt_get_pause_stats(struct net_device *dev, 3392 struct ethtool_pause_stats *epstat) 3393 { 3394 struct bnxt *bp = netdev_priv(dev); 3395 u64 *rx, *tx; 3396 3397 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 3398 return; 3399 3400 rx = bp->port_stats.sw_stats; 3401 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 3402 3403 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames); 3404 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames); 3405 } 3406 3407 static int bnxt_set_pauseparam(struct net_device *dev, 3408 struct ethtool_pauseparam *epause) 3409 { 3410 int rc = 0; 3411 struct bnxt *bp = netdev_priv(dev); 3412 struct bnxt_link_info *link_info = &bp->link_info; 3413 3414 if (!BNXT_PHY_CFG_ABLE(bp) || (bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 3415 return -EOPNOTSUPP; 3416 3417 mutex_lock(&bp->link_lock); 3418 if (epause->autoneg) { 3419 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 3420 rc = -EINVAL; 3421 goto pause_exit; 3422 } 3423 3424 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 3425 link_info->req_flow_ctrl = 0; 3426 } else { 3427 /* when transition from auto pause to force pause, 3428 * force a link change 3429 */ 3430 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 3431 link_info->force_link_chng = true; 3432 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 3433 link_info->req_flow_ctrl = 0; 3434 } 3435 if (epause->rx_pause) 3436 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 3437 3438 if (epause->tx_pause) 3439 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 3440 3441 if (netif_running(dev)) 3442 rc = bnxt_hwrm_set_pause(bp); 3443 3444 pause_exit: 3445 mutex_unlock(&bp->link_lock); 3446 return rc; 3447 } 3448 3449 static u32 bnxt_get_link(struct net_device *dev) 3450 { 3451 struct bnxt *bp = netdev_priv(dev); 3452 3453 /* TODO: handle MF, VF, driver close case */ 3454 return BNXT_LINK_IS_UP(bp); 3455 } 3456 3457 static int bnxt_get_link_ext_state(struct net_device *dev, 3458 struct ethtool_link_ext_state_info *info) 3459 { 3460 struct bnxt *bp = netdev_priv(dev); 3461 u8 reason; 3462 3463 if (BNXT_LINK_IS_UP(bp)) 3464 return -ENODATA; 3465 3466 reason = bp->link_info.link_down_reason; 3467 if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF) { 3468 info->link_ext_state = ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE; 3469 info->link_training = ETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT; 3470 return 0; 3471 } 3472 if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_CABLE_REMOVED) { 3473 info->link_ext_state = ETHTOOL_LINK_EXT_STATE_NO_CABLE; 3474 return 0; 3475 } 3476 if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_OTP_SPEED_VIOLATION) { 3477 info->link_ext_state = ETHTOOL_LINK_EXT_STATE_OTP_SPEED_VIOLATION; 3478 return 0; 3479 } 3480 if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_MODULE_FAULT) { 3481 info->link_ext_state = ETHTOOL_LINK_EXT_STATE_MODULE; 3482 return 0; 3483 } 3484 if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_BMC_REQUEST) { 3485 info->link_ext_state = ETHTOOL_LINK_EXT_STATE_BMC_REQUEST_DOWN; 3486 return 0; 3487 } 3488 return -ENODATA; 3489 } 3490 3491 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp, 3492 struct hwrm_nvm_get_dev_info_output *nvm_dev_info) 3493 { 3494 struct hwrm_nvm_get_dev_info_output *resp; 3495 struct hwrm_nvm_get_dev_info_input *req; 3496 int rc; 3497 3498 if (BNXT_VF(bp)) 3499 return -EOPNOTSUPP; 3500 3501 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO); 3502 if (rc) 3503 return rc; 3504 3505 resp = hwrm_req_hold(bp, req); 3506 rc = hwrm_req_send(bp, req); 3507 if (!rc) 3508 memcpy(nvm_dev_info, resp, sizeof(*resp)); 3509 hwrm_req_drop(bp, req); 3510 return rc; 3511 } 3512 3513 static void bnxt_print_admin_err(struct bnxt *bp) 3514 { 3515 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 3516 } 3517 3518 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 3519 u16 ext, u16 *index, u32 *item_length, 3520 u32 *data_length); 3521 3522 int bnxt_flash_nvram(struct net_device *dev, u16 dir_type, 3523 u16 dir_ordinal, u16 dir_ext, u16 dir_attr, 3524 u32 dir_item_len, const u8 *data, 3525 size_t data_len) 3526 { 3527 struct bnxt *bp = netdev_priv(dev); 3528 struct hwrm_nvm_write_input *req; 3529 int rc; 3530 3531 rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE); 3532 if (rc) 3533 return rc; 3534 3535 if (data_len && data) { 3536 dma_addr_t dma_handle; 3537 u8 *kmem; 3538 3539 kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle); 3540 if (!kmem) { 3541 hwrm_req_drop(bp, req); 3542 return -ENOMEM; 3543 } 3544 3545 req->dir_data_length = cpu_to_le32(data_len); 3546 3547 memcpy(kmem, data, data_len); 3548 req->host_src_addr = cpu_to_le64(dma_handle); 3549 } 3550 3551 hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout); 3552 req->dir_type = cpu_to_le16(dir_type); 3553 req->dir_ordinal = cpu_to_le16(dir_ordinal); 3554 req->dir_ext = cpu_to_le16(dir_ext); 3555 req->dir_attr = cpu_to_le16(dir_attr); 3556 req->dir_item_length = cpu_to_le32(dir_item_len); 3557 rc = hwrm_req_send(bp, req); 3558 3559 if (rc == -EACCES) 3560 bnxt_print_admin_err(bp); 3561 return rc; 3562 } 3563 3564 int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type, 3565 u8 self_reset, u8 flags) 3566 { 3567 struct bnxt *bp = netdev_priv(dev); 3568 struct hwrm_fw_reset_input *req; 3569 int rc; 3570 3571 if (!bnxt_hwrm_reset_permitted(bp)) { 3572 netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver"); 3573 return -EPERM; 3574 } 3575 3576 rc = hwrm_req_init(bp, req, HWRM_FW_RESET); 3577 if (rc) 3578 return rc; 3579 3580 req->embedded_proc_type = proc_type; 3581 req->selfrst_status = self_reset; 3582 req->flags = flags; 3583 3584 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) { 3585 rc = hwrm_req_send_silent(bp, req); 3586 } else { 3587 rc = hwrm_req_send(bp, req); 3588 if (rc == -EACCES) 3589 bnxt_print_admin_err(bp); 3590 } 3591 return rc; 3592 } 3593 3594 static int bnxt_firmware_reset(struct net_device *dev, 3595 enum bnxt_nvm_directory_type dir_type) 3596 { 3597 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE; 3598 u8 proc_type, flags = 0; 3599 3600 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 3601 /* (e.g. when firmware isn't already running) */ 3602 switch (dir_type) { 3603 case BNX_DIR_TYPE_CHIMP_PATCH: 3604 case BNX_DIR_TYPE_BOOTCODE: 3605 case BNX_DIR_TYPE_BOOTCODE_2: 3606 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 3607 /* Self-reset ChiMP upon next PCIe reset: */ 3608 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 3609 break; 3610 case BNX_DIR_TYPE_APE_FW: 3611 case BNX_DIR_TYPE_APE_PATCH: 3612 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 3613 /* Self-reset APE upon next PCIe reset: */ 3614 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 3615 break; 3616 case BNX_DIR_TYPE_KONG_FW: 3617 case BNX_DIR_TYPE_KONG_PATCH: 3618 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 3619 break; 3620 case BNX_DIR_TYPE_BONO_FW: 3621 case BNX_DIR_TYPE_BONO_PATCH: 3622 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 3623 break; 3624 default: 3625 return -EINVAL; 3626 } 3627 3628 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags); 3629 } 3630 3631 static int bnxt_firmware_reset_chip(struct net_device *dev) 3632 { 3633 struct bnxt *bp = netdev_priv(dev); 3634 u8 flags = 0; 3635 3636 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 3637 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 3638 3639 return bnxt_hwrm_firmware_reset(dev, 3640 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP, 3641 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP, 3642 flags); 3643 } 3644 3645 static int bnxt_firmware_reset_ap(struct net_device *dev) 3646 { 3647 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP, 3648 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE, 3649 0); 3650 } 3651 3652 static int bnxt_flash_firmware(struct net_device *dev, 3653 u16 dir_type, 3654 const u8 *fw_data, 3655 size_t fw_size) 3656 { 3657 int rc = 0; 3658 u16 code_type; 3659 u32 stored_crc; 3660 u32 calculated_crc; 3661 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 3662 3663 switch (dir_type) { 3664 case BNX_DIR_TYPE_BOOTCODE: 3665 case BNX_DIR_TYPE_BOOTCODE_2: 3666 code_type = CODE_BOOT; 3667 break; 3668 case BNX_DIR_TYPE_CHIMP_PATCH: 3669 code_type = CODE_CHIMP_PATCH; 3670 break; 3671 case BNX_DIR_TYPE_APE_FW: 3672 code_type = CODE_MCTP_PASSTHRU; 3673 break; 3674 case BNX_DIR_TYPE_APE_PATCH: 3675 code_type = CODE_APE_PATCH; 3676 break; 3677 case BNX_DIR_TYPE_KONG_FW: 3678 code_type = CODE_KONG_FW; 3679 break; 3680 case BNX_DIR_TYPE_KONG_PATCH: 3681 code_type = CODE_KONG_PATCH; 3682 break; 3683 case BNX_DIR_TYPE_BONO_FW: 3684 code_type = CODE_BONO_FW; 3685 break; 3686 case BNX_DIR_TYPE_BONO_PATCH: 3687 code_type = CODE_BONO_PATCH; 3688 break; 3689 default: 3690 netdev_err(dev, "Unsupported directory entry type: %u\n", 3691 dir_type); 3692 return -EINVAL; 3693 } 3694 if (fw_size < sizeof(struct bnxt_fw_header)) { 3695 netdev_err(dev, "Invalid firmware file size: %u\n", 3696 (unsigned int)fw_size); 3697 return -EINVAL; 3698 } 3699 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 3700 netdev_err(dev, "Invalid firmware signature: %08X\n", 3701 le32_to_cpu(header->signature)); 3702 return -EINVAL; 3703 } 3704 if (header->code_type != code_type) { 3705 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 3706 code_type, header->code_type); 3707 return -EINVAL; 3708 } 3709 if (header->device != DEVICE_CUMULUS_FAMILY) { 3710 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 3711 DEVICE_CUMULUS_FAMILY, header->device); 3712 return -EINVAL; 3713 } 3714 /* Confirm the CRC32 checksum of the file: */ 3715 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 3716 sizeof(stored_crc))); 3717 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 3718 if (calculated_crc != stored_crc) { 3719 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 3720 (unsigned long)stored_crc, 3721 (unsigned long)calculated_crc); 3722 return -EINVAL; 3723 } 3724 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3725 0, 0, 0, fw_data, fw_size); 3726 if (rc == 0) /* Firmware update successful */ 3727 rc = bnxt_firmware_reset(dev, dir_type); 3728 3729 return rc; 3730 } 3731 3732 static int bnxt_flash_microcode(struct net_device *dev, 3733 u16 dir_type, 3734 const u8 *fw_data, 3735 size_t fw_size) 3736 { 3737 struct bnxt_ucode_trailer *trailer; 3738 u32 calculated_crc; 3739 u32 stored_crc; 3740 int rc = 0; 3741 3742 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 3743 netdev_err(dev, "Invalid microcode file size: %u\n", 3744 (unsigned int)fw_size); 3745 return -EINVAL; 3746 } 3747 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 3748 sizeof(*trailer))); 3749 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 3750 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 3751 le32_to_cpu(trailer->sig)); 3752 return -EINVAL; 3753 } 3754 if (le16_to_cpu(trailer->dir_type) != dir_type) { 3755 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 3756 dir_type, le16_to_cpu(trailer->dir_type)); 3757 return -EINVAL; 3758 } 3759 if (le16_to_cpu(trailer->trailer_length) < 3760 sizeof(struct bnxt_ucode_trailer)) { 3761 netdev_err(dev, "Invalid microcode trailer length: %d\n", 3762 le16_to_cpu(trailer->trailer_length)); 3763 return -EINVAL; 3764 } 3765 3766 /* Confirm the CRC32 checksum of the file: */ 3767 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 3768 sizeof(stored_crc))); 3769 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 3770 if (calculated_crc != stored_crc) { 3771 netdev_err(dev, 3772 "CRC32 (%08lX) does not match calculated: %08lX\n", 3773 (unsigned long)stored_crc, 3774 (unsigned long)calculated_crc); 3775 return -EINVAL; 3776 } 3777 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3778 0, 0, 0, fw_data, fw_size); 3779 3780 return rc; 3781 } 3782 3783 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 3784 { 3785 switch (dir_type) { 3786 case BNX_DIR_TYPE_CHIMP_PATCH: 3787 case BNX_DIR_TYPE_BOOTCODE: 3788 case BNX_DIR_TYPE_BOOTCODE_2: 3789 case BNX_DIR_TYPE_APE_FW: 3790 case BNX_DIR_TYPE_APE_PATCH: 3791 case BNX_DIR_TYPE_KONG_FW: 3792 case BNX_DIR_TYPE_KONG_PATCH: 3793 case BNX_DIR_TYPE_BONO_FW: 3794 case BNX_DIR_TYPE_BONO_PATCH: 3795 return true; 3796 } 3797 3798 return false; 3799 } 3800 3801 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 3802 { 3803 switch (dir_type) { 3804 case BNX_DIR_TYPE_AVS: 3805 case BNX_DIR_TYPE_EXP_ROM_MBA: 3806 case BNX_DIR_TYPE_PCIE: 3807 case BNX_DIR_TYPE_TSCF_UCODE: 3808 case BNX_DIR_TYPE_EXT_PHY: 3809 case BNX_DIR_TYPE_CCM: 3810 case BNX_DIR_TYPE_ISCSI_BOOT: 3811 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 3812 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 3813 return true; 3814 } 3815 3816 return false; 3817 } 3818 3819 static bool bnxt_dir_type_is_executable(u16 dir_type) 3820 { 3821 return bnxt_dir_type_is_ape_bin_format(dir_type) || 3822 bnxt_dir_type_is_other_exec_format(dir_type); 3823 } 3824 3825 static int bnxt_flash_firmware_from_file(struct net_device *dev, 3826 u16 dir_type, 3827 const char *filename) 3828 { 3829 const struct firmware *fw; 3830 int rc; 3831 3832 rc = request_firmware(&fw, filename, &dev->dev); 3833 if (rc != 0) { 3834 netdev_err(dev, "Error %d requesting firmware file: %s\n", 3835 rc, filename); 3836 return rc; 3837 } 3838 if (bnxt_dir_type_is_ape_bin_format(dir_type)) 3839 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 3840 else if (bnxt_dir_type_is_other_exec_format(dir_type)) 3841 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 3842 else 3843 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3844 0, 0, 0, fw->data, fw->size); 3845 release_firmware(fw); 3846 return rc; 3847 } 3848 3849 #define MSG_INTEGRITY_ERR "PKG install error : Data integrity on NVM" 3850 #define MSG_INVALID_PKG "PKG install error : Invalid package" 3851 #define MSG_AUTHENTICATION_ERR "PKG install error : Authentication error" 3852 #define MSG_INVALID_DEV "PKG install error : Invalid device" 3853 #define MSG_INTERNAL_ERR "PKG install error : Internal error" 3854 #define MSG_NO_PKG_UPDATE_AREA_ERR "PKG update area not created in nvram" 3855 #define MSG_NO_SPACE_ERR "PKG insufficient update area in nvram" 3856 #define MSG_RESIZE_UPDATE_ERR "Resize UPDATE entry error" 3857 #define MSG_ANTI_ROLLBACK_ERR "HWRM_NVM_INSTALL_UPDATE failure due to Anti-rollback detected" 3858 #define MSG_GENERIC_FAILURE_ERR "HWRM_NVM_INSTALL_UPDATE failure" 3859 3860 static int nvm_update_err_to_stderr(struct net_device *dev, u8 result, 3861 struct netlink_ext_ack *extack) 3862 { 3863 switch (result) { 3864 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER: 3865 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER: 3866 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR: 3867 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR: 3868 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND: 3869 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED: 3870 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTEGRITY_ERR); 3871 return -EINVAL; 3872 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE: 3873 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER: 3874 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE: 3875 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM: 3876 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH: 3877 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST: 3878 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER: 3879 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM: 3880 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM: 3881 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH: 3882 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE: 3883 case NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM: 3884 case NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM: 3885 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_PKG); 3886 return -ENOPKG; 3887 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR: 3888 BNXT_NVM_ERR_MSG(dev, extack, MSG_AUTHENTICATION_ERR); 3889 return -EPERM; 3890 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV: 3891 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID: 3892 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR: 3893 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID: 3894 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM: 3895 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_DEV); 3896 return -EOPNOTSUPP; 3897 default: 3898 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTERNAL_ERR); 3899 return -EIO; 3900 } 3901 } 3902 3903 #define BNXT_PKG_DMA_SIZE 0x40000 3904 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE)) 3905 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST)) 3906 3907 static int bnxt_hwrm_nvm_defrag(struct bnxt *bp) 3908 { 3909 struct hwrm_nvm_defrag_input *req; 3910 int rc; 3911 3912 rc = hwrm_req_init(bp, req, HWRM_NVM_DEFRAG); 3913 if (rc) 3914 return rc; 3915 req->flags = cpu_to_le32(NVM_DEFRAG_REQ_FLAGS_DEFRAG); 3916 hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout); 3917 3918 return hwrm_req_send(bp, req); 3919 } 3920 3921 static int bnxt_resize_update_entry(struct net_device *dev, size_t fw_size, 3922 struct netlink_ext_ack *extack) 3923 { 3924 struct bnxt *bp = netdev_priv(dev); 3925 bool retry = false; 3926 u32 item_len; 3927 int rc; 3928 3929 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 3930 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, NULL, 3931 &item_len, NULL); 3932 if (rc) { 3933 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 3934 return rc; 3935 } 3936 3937 if (fw_size > item_len) { 3938 do { 3939 rc = bnxt_flash_nvram(dev, BNX_DIR_TYPE_UPDATE, 3940 BNX_DIR_ORDINAL_FIRST, 0, 1, 3941 round_up(fw_size, 4096), NULL, 3942 0); 3943 3944 if (rc == -ENOSPC) { 3945 if (retry || bnxt_hwrm_nvm_defrag(bp)) 3946 break; 3947 retry = true; 3948 } 3949 } while (rc == -ENOSPC); 3950 3951 if (rc) { 3952 BNXT_NVM_ERR_MSG(dev, extack, MSG_RESIZE_UPDATE_ERR); 3953 return rc; 3954 } 3955 } 3956 return 0; 3957 } 3958 3959 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw, 3960 u32 install_type, struct netlink_ext_ack *extack) 3961 { 3962 struct hwrm_nvm_install_update_input *install; 3963 struct hwrm_nvm_install_update_output *resp; 3964 struct hwrm_nvm_modify_input *modify; 3965 struct bnxt *bp = netdev_priv(dev); 3966 bool defrag_attempted = false; 3967 dma_addr_t dma_handle; 3968 u8 *kmem = NULL; 3969 u32 modify_len; 3970 u32 item_len; 3971 u8 cmd_err; 3972 u16 index; 3973 int rc; 3974 3975 /* resize before flashing larger image than available space */ 3976 rc = bnxt_resize_update_entry(dev, fw->size, extack); 3977 if (rc) 3978 return rc; 3979 3980 bnxt_hwrm_fw_set_time(bp); 3981 3982 rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY); 3983 if (rc) 3984 return rc; 3985 3986 /* Try allocating a large DMA buffer first. Older fw will 3987 * cause excessive NVRAM erases when using small blocks. 3988 */ 3989 modify_len = roundup_pow_of_two(fw->size); 3990 modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE); 3991 while (1) { 3992 kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle); 3993 if (!kmem && modify_len > PAGE_SIZE) 3994 modify_len /= 2; 3995 else 3996 break; 3997 } 3998 if (!kmem) { 3999 hwrm_req_drop(bp, modify); 4000 return -ENOMEM; 4001 } 4002 4003 rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE); 4004 if (rc) { 4005 hwrm_req_drop(bp, modify); 4006 return rc; 4007 } 4008 4009 hwrm_req_timeout(bp, modify, bp->hwrm_cmd_max_timeout); 4010 hwrm_req_timeout(bp, install, bp->hwrm_cmd_max_timeout); 4011 4012 hwrm_req_hold(bp, modify); 4013 modify->host_src_addr = cpu_to_le64(dma_handle); 4014 4015 resp = hwrm_req_hold(bp, install); 4016 if ((install_type & 0xffff) == 0) 4017 install_type >>= 16; 4018 install->install_type = cpu_to_le32(install_type); 4019 4020 do { 4021 u32 copied = 0, len = modify_len; 4022 4023 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 4024 BNX_DIR_ORDINAL_FIRST, 4025 BNX_DIR_EXT_NONE, 4026 &index, &item_len, NULL); 4027 if (rc) { 4028 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 4029 break; 4030 } 4031 if (fw->size > item_len) { 4032 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_SPACE_ERR); 4033 rc = -EFBIG; 4034 break; 4035 } 4036 4037 modify->dir_idx = cpu_to_le16(index); 4038 4039 if (fw->size > modify_len) 4040 modify->flags = BNXT_NVM_MORE_FLAG; 4041 while (copied < fw->size) { 4042 u32 balance = fw->size - copied; 4043 4044 if (balance <= modify_len) { 4045 len = balance; 4046 if (copied) 4047 modify->flags |= BNXT_NVM_LAST_FLAG; 4048 } 4049 memcpy(kmem, fw->data + copied, len); 4050 modify->len = cpu_to_le32(len); 4051 modify->offset = cpu_to_le32(copied); 4052 rc = hwrm_req_send(bp, modify); 4053 if (rc) 4054 goto pkg_abort; 4055 copied += len; 4056 } 4057 4058 rc = hwrm_req_send_silent(bp, install); 4059 if (!rc) 4060 break; 4061 4062 if (defrag_attempted) { 4063 /* We have tried to defragment already in the previous 4064 * iteration. Return with the result for INSTALL_UPDATE 4065 */ 4066 break; 4067 } 4068 4069 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 4070 4071 switch (cmd_err) { 4072 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK: 4073 BNXT_NVM_ERR_MSG(dev, extack, MSG_ANTI_ROLLBACK_ERR); 4074 rc = -EALREADY; 4075 break; 4076 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR: 4077 install->flags = 4078 cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 4079 4080 rc = hwrm_req_send_silent(bp, install); 4081 if (!rc) 4082 break; 4083 4084 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 4085 4086 if (cmd_err == NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) { 4087 /* FW has cleared NVM area, driver will create 4088 * UPDATE directory and try the flash again 4089 */ 4090 defrag_attempted = true; 4091 install->flags = 0; 4092 rc = bnxt_flash_nvram(bp->dev, 4093 BNX_DIR_TYPE_UPDATE, 4094 BNX_DIR_ORDINAL_FIRST, 4095 0, 0, item_len, NULL, 0); 4096 if (!rc) 4097 break; 4098 } 4099 fallthrough; 4100 default: 4101 BNXT_NVM_ERR_MSG(dev, extack, MSG_GENERIC_FAILURE_ERR); 4102 } 4103 } while (defrag_attempted && !rc); 4104 4105 pkg_abort: 4106 hwrm_req_drop(bp, modify); 4107 hwrm_req_drop(bp, install); 4108 4109 if (resp->result) { 4110 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 4111 (s8)resp->result, (int)resp->problem_item); 4112 rc = nvm_update_err_to_stderr(dev, resp->result, extack); 4113 } 4114 if (rc == -EACCES) 4115 bnxt_print_admin_err(bp); 4116 return rc; 4117 } 4118 4119 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename, 4120 u32 install_type, struct netlink_ext_ack *extack) 4121 { 4122 const struct firmware *fw; 4123 int rc; 4124 4125 rc = request_firmware(&fw, filename, &dev->dev); 4126 if (rc != 0) { 4127 netdev_err(dev, "PKG error %d requesting file: %s\n", 4128 rc, filename); 4129 return rc; 4130 } 4131 4132 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type, extack); 4133 4134 release_firmware(fw); 4135 4136 return rc; 4137 } 4138 4139 static int bnxt_flash_device(struct net_device *dev, 4140 struct ethtool_flash *flash) 4141 { 4142 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 4143 netdev_err(dev, "flashdev not supported from a virtual function\n"); 4144 return -EINVAL; 4145 } 4146 4147 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 4148 flash->region > 0xffff) 4149 return bnxt_flash_package_from_file(dev, flash->data, 4150 flash->region, NULL); 4151 4152 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 4153 } 4154 4155 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 4156 { 4157 struct hwrm_nvm_get_dir_info_output *output; 4158 struct hwrm_nvm_get_dir_info_input *req; 4159 struct bnxt *bp = netdev_priv(dev); 4160 int rc; 4161 4162 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO); 4163 if (rc) 4164 return rc; 4165 4166 output = hwrm_req_hold(bp, req); 4167 rc = hwrm_req_send(bp, req); 4168 if (!rc) { 4169 *entries = le32_to_cpu(output->entries); 4170 *length = le32_to_cpu(output->entry_length); 4171 } 4172 hwrm_req_drop(bp, req); 4173 return rc; 4174 } 4175 4176 static int bnxt_get_eeprom_len(struct net_device *dev) 4177 { 4178 struct bnxt *bp = netdev_priv(dev); 4179 4180 if (BNXT_VF(bp)) 4181 return 0; 4182 4183 /* The -1 return value allows the entire 32-bit range of offsets to be 4184 * passed via the ethtool command-line utility. 4185 */ 4186 return -1; 4187 } 4188 4189 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 4190 { 4191 struct bnxt *bp = netdev_priv(dev); 4192 int rc; 4193 u32 dir_entries; 4194 u32 entry_length; 4195 u8 *buf; 4196 size_t buflen; 4197 dma_addr_t dma_handle; 4198 struct hwrm_nvm_get_dir_entries_input *req; 4199 4200 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 4201 if (rc != 0) 4202 return rc; 4203 4204 if (!dir_entries || !entry_length) 4205 return -EIO; 4206 4207 /* Insert 2 bytes of directory info (count and size of entries) */ 4208 if (len < 2) 4209 return -EINVAL; 4210 4211 *data++ = dir_entries; 4212 *data++ = entry_length; 4213 len -= 2; 4214 memset(data, 0xff, len); 4215 4216 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES); 4217 if (rc) 4218 return rc; 4219 4220 buflen = mul_u32_u32(dir_entries, entry_length); 4221 buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle); 4222 if (!buf) { 4223 hwrm_req_drop(bp, req); 4224 return -ENOMEM; 4225 } 4226 req->host_dest_addr = cpu_to_le64(dma_handle); 4227 4228 hwrm_req_hold(bp, req); /* hold the slice */ 4229 rc = hwrm_req_send(bp, req); 4230 if (rc == 0) 4231 memcpy(data, buf, len > buflen ? buflen : len); 4232 hwrm_req_drop(bp, req); 4233 return rc; 4234 } 4235 4236 int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 4237 u32 length, u8 *data) 4238 { 4239 struct bnxt *bp = netdev_priv(dev); 4240 int rc; 4241 u8 *buf; 4242 dma_addr_t dma_handle; 4243 struct hwrm_nvm_read_input *req; 4244 4245 if (!length) 4246 return -EINVAL; 4247 4248 rc = hwrm_req_init(bp, req, HWRM_NVM_READ); 4249 if (rc) 4250 return rc; 4251 4252 buf = hwrm_req_dma_slice(bp, req, length, &dma_handle); 4253 if (!buf) { 4254 hwrm_req_drop(bp, req); 4255 return -ENOMEM; 4256 } 4257 4258 req->host_dest_addr = cpu_to_le64(dma_handle); 4259 req->dir_idx = cpu_to_le16(index); 4260 req->offset = cpu_to_le32(offset); 4261 req->len = cpu_to_le32(length); 4262 4263 hwrm_req_hold(bp, req); /* hold the slice */ 4264 rc = hwrm_req_send(bp, req); 4265 if (rc == 0) 4266 memcpy(data, buf, length); 4267 hwrm_req_drop(bp, req); 4268 return rc; 4269 } 4270 4271 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 4272 u16 ext, u16 *index, u32 *item_length, 4273 u32 *data_length) 4274 { 4275 struct hwrm_nvm_find_dir_entry_output *output; 4276 struct hwrm_nvm_find_dir_entry_input *req; 4277 struct bnxt *bp = netdev_priv(dev); 4278 int rc; 4279 4280 rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY); 4281 if (rc) 4282 return rc; 4283 4284 req->enables = 0; 4285 req->dir_idx = 0; 4286 req->dir_type = cpu_to_le16(type); 4287 req->dir_ordinal = cpu_to_le16(ordinal); 4288 req->dir_ext = cpu_to_le16(ext); 4289 req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 4290 output = hwrm_req_hold(bp, req); 4291 rc = hwrm_req_send_silent(bp, req); 4292 if (rc == 0) { 4293 if (index) 4294 *index = le16_to_cpu(output->dir_idx); 4295 if (item_length) 4296 *item_length = le32_to_cpu(output->dir_item_length); 4297 if (data_length) 4298 *data_length = le32_to_cpu(output->dir_data_length); 4299 } 4300 hwrm_req_drop(bp, req); 4301 return rc; 4302 } 4303 4304 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 4305 { 4306 char *retval = NULL; 4307 char *p; 4308 char *value; 4309 int field = 0; 4310 4311 if (datalen < 1) 4312 return NULL; 4313 /* null-terminate the log data (removing last '\n'): */ 4314 data[datalen - 1] = 0; 4315 for (p = data; *p != 0; p++) { 4316 field = 0; 4317 retval = NULL; 4318 while (*p != 0 && *p != '\n') { 4319 value = p; 4320 while (*p != 0 && *p != '\t' && *p != '\n') 4321 p++; 4322 if (field == desired_field) 4323 retval = value; 4324 if (*p != '\t') 4325 break; 4326 *p = 0; 4327 field++; 4328 p++; 4329 } 4330 if (*p == 0) 4331 break; 4332 *p = 0; 4333 } 4334 return retval; 4335 } 4336 4337 int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size) 4338 { 4339 struct bnxt *bp = netdev_priv(dev); 4340 u16 index = 0; 4341 char *pkgver; 4342 u32 pkglen; 4343 u8 *pkgbuf; 4344 int rc; 4345 4346 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 4347 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 4348 &index, NULL, &pkglen); 4349 if (rc) 4350 return rc; 4351 4352 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 4353 if (!pkgbuf) { 4354 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 4355 pkglen); 4356 return -ENOMEM; 4357 } 4358 4359 rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf); 4360 if (rc) 4361 goto err; 4362 4363 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 4364 pkglen); 4365 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) 4366 strscpy(ver, pkgver, size); 4367 else 4368 rc = -ENOENT; 4369 4370 err: 4371 kfree(pkgbuf); 4372 4373 return rc; 4374 } 4375 4376 static void bnxt_get_pkgver(struct net_device *dev) 4377 { 4378 struct bnxt *bp = netdev_priv(dev); 4379 char buf[FW_VER_STR_LEN - 5]; 4380 int len; 4381 4382 if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) { 4383 len = strlen(bp->fw_ver_str); 4384 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len, 4385 "/pkg %s", buf); 4386 } 4387 } 4388 4389 static int bnxt_get_eeprom(struct net_device *dev, 4390 struct ethtool_eeprom *eeprom, 4391 u8 *data) 4392 { 4393 u32 index; 4394 u32 offset; 4395 4396 if (eeprom->offset == 0) /* special offset value to get directory */ 4397 return bnxt_get_nvram_directory(dev, eeprom->len, data); 4398 4399 index = eeprom->offset >> 24; 4400 offset = eeprom->offset & 0xffffff; 4401 4402 if (index == 0) { 4403 netdev_err(dev, "unsupported index value: %d\n", index); 4404 return -EINVAL; 4405 } 4406 4407 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 4408 } 4409 4410 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 4411 { 4412 struct hwrm_nvm_erase_dir_entry_input *req; 4413 struct bnxt *bp = netdev_priv(dev); 4414 int rc; 4415 4416 rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY); 4417 if (rc) 4418 return rc; 4419 4420 req->dir_idx = cpu_to_le16(index); 4421 return hwrm_req_send(bp, req); 4422 } 4423 4424 static int bnxt_set_eeprom(struct net_device *dev, 4425 struct ethtool_eeprom *eeprom, 4426 u8 *data) 4427 { 4428 struct bnxt *bp = netdev_priv(dev); 4429 u8 index, dir_op; 4430 u16 type, ext, ordinal, attr; 4431 4432 if (!BNXT_PF(bp)) { 4433 netdev_err(dev, "NVM write not supported from a virtual function\n"); 4434 return -EINVAL; 4435 } 4436 4437 type = eeprom->magic >> 16; 4438 4439 if (type == 0xffff) { /* special value for directory operations */ 4440 index = eeprom->magic & 0xff; 4441 dir_op = eeprom->magic >> 8; 4442 if (index == 0) 4443 return -EINVAL; 4444 switch (dir_op) { 4445 case 0x0e: /* erase */ 4446 if (eeprom->offset != ~eeprom->magic) 4447 return -EINVAL; 4448 return bnxt_erase_nvram_directory(dev, index - 1); 4449 default: 4450 return -EINVAL; 4451 } 4452 } 4453 4454 /* Create or re-write an NVM item: */ 4455 if (bnxt_dir_type_is_executable(type)) 4456 return -EOPNOTSUPP; 4457 ext = eeprom->magic & 0xffff; 4458 ordinal = eeprom->offset >> 16; 4459 attr = eeprom->offset & 0xffff; 4460 4461 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data, 4462 eeprom->len); 4463 } 4464 4465 static int bnxt_set_eee(struct net_device *dev, struct ethtool_keee *edata) 4466 { 4467 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 4468 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp); 4469 struct bnxt *bp = netdev_priv(dev); 4470 struct ethtool_keee *eee = &bp->eee; 4471 struct bnxt_link_info *link_info = &bp->link_info; 4472 int rc = 0; 4473 4474 if (!BNXT_PHY_CFG_ABLE(bp)) 4475 return -EOPNOTSUPP; 4476 4477 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 4478 return -EOPNOTSUPP; 4479 4480 mutex_lock(&bp->link_lock); 4481 _bnxt_fw_to_linkmode(advertising, link_info->advertising); 4482 if (!edata->eee_enabled) 4483 goto eee_ok; 4484 4485 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 4486 netdev_warn(dev, "EEE requires autoneg\n"); 4487 rc = -EINVAL; 4488 goto eee_exit; 4489 } 4490 if (edata->tx_lpi_enabled) { 4491 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 4492 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 4493 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 4494 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 4495 rc = -EINVAL; 4496 goto eee_exit; 4497 } else if (!bp->lpi_tmr_hi) { 4498 edata->tx_lpi_timer = eee->tx_lpi_timer; 4499 } 4500 } 4501 if (linkmode_empty(edata->advertised)) { 4502 linkmode_and(edata->advertised, advertising, eee->supported); 4503 } else if (linkmode_andnot(tmp, edata->advertised, advertising)) { 4504 netdev_warn(dev, "EEE advertised must be a subset of autoneg advertised speeds\n"); 4505 rc = -EINVAL; 4506 goto eee_exit; 4507 } 4508 4509 linkmode_copy(eee->advertised, edata->advertised); 4510 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 4511 eee->tx_lpi_timer = edata->tx_lpi_timer; 4512 eee_ok: 4513 eee->eee_enabled = edata->eee_enabled; 4514 4515 if (netif_running(dev)) 4516 rc = bnxt_hwrm_set_link_setting(bp, false, true); 4517 4518 eee_exit: 4519 mutex_unlock(&bp->link_lock); 4520 return rc; 4521 } 4522 4523 static int bnxt_get_eee(struct net_device *dev, struct ethtool_keee *edata) 4524 { 4525 struct bnxt *bp = netdev_priv(dev); 4526 4527 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 4528 return -EOPNOTSUPP; 4529 4530 *edata = bp->eee; 4531 if (!bp->eee.eee_enabled) { 4532 /* Preserve tx_lpi_timer so that the last value will be used 4533 * by default when it is re-enabled. 4534 */ 4535 linkmode_zero(edata->advertised); 4536 edata->tx_lpi_enabled = 0; 4537 } 4538 4539 if (!bp->eee.eee_active) 4540 linkmode_zero(edata->lp_advertised); 4541 4542 return 0; 4543 } 4544 4545 static int bnxt_hwrm_pfcwd_qcfg(struct bnxt *bp, u16 *val) 4546 { 4547 struct hwrm_queue_pfcwd_timeout_qcfg_output *resp; 4548 struct hwrm_queue_pfcwd_timeout_qcfg_input *req; 4549 int rc; 4550 4551 rc = hwrm_req_init(bp, req, HWRM_QUEUE_PFCWD_TIMEOUT_QCFG); 4552 if (rc) 4553 return rc; 4554 resp = hwrm_req_hold(bp, req); 4555 rc = hwrm_req_send(bp, req); 4556 if (!rc) 4557 *val = le16_to_cpu(resp->pfcwd_timeout_value); 4558 hwrm_req_drop(bp, req); 4559 return rc; 4560 } 4561 4562 static int bnxt_hwrm_pfcwd_cfg(struct bnxt *bp, u16 val) 4563 { 4564 struct hwrm_queue_pfcwd_timeout_cfg_input *req; 4565 int rc; 4566 4567 rc = hwrm_req_init(bp, req, HWRM_QUEUE_PFCWD_TIMEOUT_CFG); 4568 if (rc) 4569 return rc; 4570 req->pfcwd_timeout_value = cpu_to_le16(val); 4571 rc = hwrm_req_send(bp, req); 4572 return rc; 4573 } 4574 4575 static int bnxt_set_tunable(struct net_device *dev, 4576 const struct ethtool_tunable *tuna, 4577 const void *data) 4578 { 4579 struct bnxt *bp = netdev_priv(dev); 4580 u32 rx_copybreak, val; 4581 4582 switch (tuna->id) { 4583 case ETHTOOL_RX_COPYBREAK: 4584 rx_copybreak = *(u32 *)data; 4585 if (rx_copybreak > BNXT_MAX_RX_COPYBREAK) 4586 return -ERANGE; 4587 if (rx_copybreak != bp->rx_copybreak) { 4588 if (netif_running(dev)) 4589 return -EBUSY; 4590 bp->rx_copybreak = rx_copybreak; 4591 } 4592 return 0; 4593 case ETHTOOL_PFC_PREVENTION_TOUT: 4594 if (BNXT_VF(bp) || !bp->max_pfcwd_tmo_ms) 4595 return -EOPNOTSUPP; 4596 4597 val = *(u16 *)data; 4598 if (val > bp->max_pfcwd_tmo_ms && 4599 val != PFC_STORM_PREVENTION_AUTO) 4600 return -EINVAL; 4601 return bnxt_hwrm_pfcwd_cfg(bp, val); 4602 default: 4603 return -EOPNOTSUPP; 4604 } 4605 } 4606 4607 static int bnxt_get_tunable(struct net_device *dev, 4608 const struct ethtool_tunable *tuna, void *data) 4609 { 4610 struct bnxt *bp = netdev_priv(dev); 4611 4612 switch (tuna->id) { 4613 case ETHTOOL_RX_COPYBREAK: 4614 *(u32 *)data = bp->rx_copybreak; 4615 break; 4616 case ETHTOOL_PFC_PREVENTION_TOUT: 4617 if (!bp->max_pfcwd_tmo_ms) 4618 return -EOPNOTSUPP; 4619 return bnxt_hwrm_pfcwd_qcfg(bp, data); 4620 default: 4621 return -EOPNOTSUPP; 4622 } 4623 4624 return 0; 4625 } 4626 4627 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 4628 u16 page_number, u8 bank, 4629 u16 start_addr, u16 data_length, 4630 u8 *buf) 4631 { 4632 struct hwrm_port_phy_i2c_read_output *output; 4633 struct hwrm_port_phy_i2c_read_input *req; 4634 int rc, byte_offset = 0; 4635 4636 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ); 4637 if (rc) 4638 return rc; 4639 4640 output = hwrm_req_hold(bp, req); 4641 req->i2c_slave_addr = i2c_addr; 4642 req->page_number = cpu_to_le16(page_number); 4643 req->port_id = cpu_to_le16(bp->pf.port_id); 4644 do { 4645 u16 xfer_size; 4646 4647 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 4648 data_length -= xfer_size; 4649 req->page_offset = cpu_to_le16(start_addr + byte_offset); 4650 req->data_length = xfer_size; 4651 req->enables = 4652 cpu_to_le32((start_addr + byte_offset ? 4653 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 4654 0) | 4655 (bank ? 4656 PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER : 4657 0)); 4658 rc = hwrm_req_send(bp, req); 4659 if (!rc) 4660 memcpy(buf + byte_offset, output->data, xfer_size); 4661 byte_offset += xfer_size; 4662 } while (!rc && data_length > 0); 4663 hwrm_req_drop(bp, req); 4664 4665 return rc; 4666 } 4667 4668 static int bnxt_get_module_info(struct net_device *dev, 4669 struct ethtool_modinfo *modinfo) 4670 { 4671 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 4672 struct bnxt *bp = netdev_priv(dev); 4673 int rc; 4674 4675 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 4676 return -EPERM; 4677 4678 /* No point in going further if phy status indicates 4679 * module is not inserted or if it is powered down or 4680 * if it is of type 10GBase-T 4681 */ 4682 if (bp->link_info.module_status > 4683 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 4684 return -EOPNOTSUPP; 4685 4686 /* This feature is not supported in older firmware versions */ 4687 if (bp->hwrm_spec_code < 0x10202) 4688 return -EOPNOTSUPP; 4689 4690 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 0, 4691 SFF_DIAG_SUPPORT_OFFSET + 1, 4692 data); 4693 if (!rc) { 4694 u8 module_id = data[0]; 4695 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 4696 4697 switch (module_id) { 4698 case SFF_MODULE_ID_SFP: 4699 modinfo->type = ETH_MODULE_SFF_8472; 4700 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 4701 if (!diag_supported) 4702 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 4703 break; 4704 case SFF_MODULE_ID_QSFP: 4705 case SFF_MODULE_ID_QSFP_PLUS: 4706 modinfo->type = ETH_MODULE_SFF_8436; 4707 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 4708 break; 4709 case SFF_MODULE_ID_QSFP28: 4710 modinfo->type = ETH_MODULE_SFF_8636; 4711 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 4712 break; 4713 default: 4714 rc = -EOPNOTSUPP; 4715 break; 4716 } 4717 } 4718 return rc; 4719 } 4720 4721 static int bnxt_get_module_eeprom(struct net_device *dev, 4722 struct ethtool_eeprom *eeprom, 4723 u8 *data) 4724 { 4725 struct bnxt *bp = netdev_priv(dev); 4726 u16 start = eeprom->offset, length = eeprom->len; 4727 int rc = 0; 4728 4729 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 4730 return -EPERM; 4731 4732 memset(data, 0, eeprom->len); 4733 4734 /* Read A0 portion of the EEPROM */ 4735 if (start < ETH_MODULE_SFF_8436_LEN) { 4736 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 4737 length = ETH_MODULE_SFF_8436_LEN - start; 4738 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 4739 start, length, data); 4740 if (rc) 4741 return rc; 4742 start += length; 4743 data += length; 4744 length = eeprom->len - length; 4745 } 4746 4747 /* Read A2 portion of the EEPROM */ 4748 if (length) { 4749 start -= ETH_MODULE_SFF_8436_LEN; 4750 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 0, 4751 start, length, data); 4752 } 4753 return rc; 4754 } 4755 4756 static int bnxt_get_module_status(struct bnxt *bp, struct netlink_ext_ack *extack) 4757 { 4758 if (bp->link_info.module_status <= 4759 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 4760 return 0; 4761 4762 if (bp->link_info.phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 4763 bp->link_info.phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE){ 4764 NL_SET_ERR_MSG_MOD(extack, "Operation not supported as PHY type is Base-T"); 4765 return -EOPNOTSUPP; 4766 } 4767 switch (bp->link_info.module_status) { 4768 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 4769 NL_SET_ERR_MSG_MOD(extack, "Transceiver module is powering down"); 4770 break; 4771 case PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED: 4772 NL_SET_ERR_MSG_MOD(extack, "Transceiver module not inserted"); 4773 break; 4774 case PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT: 4775 NL_SET_ERR_MSG_MOD(extack, "Transceiver module disabled due to current fault"); 4776 break; 4777 default: 4778 NL_SET_ERR_MSG_MOD(extack, "Unknown error"); 4779 break; 4780 } 4781 return -EINVAL; 4782 } 4783 4784 static int 4785 bnxt_mod_eeprom_by_page_precheck(struct bnxt *bp, 4786 const struct ethtool_module_eeprom *page_data, 4787 struct netlink_ext_ack *extack) 4788 { 4789 int rc; 4790 4791 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { 4792 NL_SET_ERR_MSG_MOD(extack, 4793 "Module read/write not permitted on untrusted VF"); 4794 return -EPERM; 4795 } 4796 4797 rc = bnxt_get_module_status(bp, extack); 4798 if (rc) 4799 return rc; 4800 4801 if (bp->hwrm_spec_code < 0x10202) { 4802 NL_SET_ERR_MSG_MOD(extack, "Firmware version too old"); 4803 return -EINVAL; 4804 } 4805 4806 if (page_data->bank && !(bp->phy_flags & BNXT_PHY_FL_BANK_SEL)) { 4807 NL_SET_ERR_MSG_MOD(extack, "Firmware not capable for bank selection"); 4808 return -EINVAL; 4809 } 4810 return 0; 4811 } 4812 4813 static int bnxt_get_module_eeprom_by_page(struct net_device *dev, 4814 const struct ethtool_module_eeprom *page_data, 4815 struct netlink_ext_ack *extack) 4816 { 4817 struct bnxt *bp = netdev_priv(dev); 4818 int rc; 4819 4820 rc = bnxt_mod_eeprom_by_page_precheck(bp, page_data, extack); 4821 if (rc) 4822 return rc; 4823 4824 rc = bnxt_read_sfp_module_eeprom_info(bp, page_data->i2c_address << 1, 4825 page_data->page, page_data->bank, 4826 page_data->offset, 4827 page_data->length, 4828 page_data->data); 4829 if (rc) { 4830 NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom read failed"); 4831 return rc; 4832 } 4833 return page_data->length; 4834 } 4835 4836 static int bnxt_write_sfp_module_eeprom_info(struct bnxt *bp, 4837 const struct ethtool_module_eeprom *page) 4838 { 4839 struct hwrm_port_phy_i2c_write_input *req; 4840 int bytes_written = 0; 4841 int rc; 4842 4843 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_WRITE); 4844 if (rc) 4845 return rc; 4846 4847 hwrm_req_hold(bp, req); 4848 req->i2c_slave_addr = page->i2c_address << 1; 4849 req->page_number = cpu_to_le16(page->page); 4850 req->bank_number = page->bank; 4851 req->port_id = cpu_to_le16(bp->pf.port_id); 4852 req->enables = cpu_to_le32(PORT_PHY_I2C_WRITE_REQ_ENABLES_PAGE_OFFSET | 4853 PORT_PHY_I2C_WRITE_REQ_ENABLES_BANK_NUMBER); 4854 4855 while (bytes_written < page->length) { 4856 u16 xfer_size; 4857 4858 xfer_size = min_t(u16, page->length - bytes_written, 4859 BNXT_MAX_PHY_I2C_RESP_SIZE); 4860 req->page_offset = cpu_to_le16(page->offset + bytes_written); 4861 req->data_length = xfer_size; 4862 memcpy(req->data, page->data + bytes_written, xfer_size); 4863 rc = hwrm_req_send(bp, req); 4864 if (rc) 4865 break; 4866 bytes_written += xfer_size; 4867 } 4868 4869 hwrm_req_drop(bp, req); 4870 return rc; 4871 } 4872 4873 static int bnxt_set_module_eeprom_by_page(struct net_device *dev, 4874 const struct ethtool_module_eeprom *page_data, 4875 struct netlink_ext_ack *extack) 4876 { 4877 struct bnxt *bp = netdev_priv(dev); 4878 int rc; 4879 4880 rc = bnxt_mod_eeprom_by_page_precheck(bp, page_data, extack); 4881 if (rc) 4882 return rc; 4883 4884 rc = bnxt_write_sfp_module_eeprom_info(bp, page_data); 4885 if (rc) { 4886 NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom write failed"); 4887 return rc; 4888 } 4889 return page_data->length; 4890 } 4891 4892 static int bnxt_nway_reset(struct net_device *dev) 4893 { 4894 int rc = 0; 4895 4896 struct bnxt *bp = netdev_priv(dev); 4897 struct bnxt_link_info *link_info = &bp->link_info; 4898 4899 if (!BNXT_PHY_CFG_ABLE(bp)) 4900 return -EOPNOTSUPP; 4901 4902 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 4903 return -EINVAL; 4904 4905 if (netif_running(dev)) 4906 rc = bnxt_hwrm_set_link_setting(bp, true, false); 4907 4908 return rc; 4909 } 4910 4911 static int bnxt_set_phys_id(struct net_device *dev, 4912 enum ethtool_phys_id_state state) 4913 { 4914 struct hwrm_port_led_cfg_input *req; 4915 struct bnxt *bp = netdev_priv(dev); 4916 struct bnxt_pf_info *pf = &bp->pf; 4917 struct bnxt_led_cfg *led_cfg; 4918 u8 led_state; 4919 __le16 duration; 4920 int rc, i; 4921 4922 if (!bp->num_leds || BNXT_VF(bp)) 4923 return -EOPNOTSUPP; 4924 4925 if (state == ETHTOOL_ID_ACTIVE) { 4926 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 4927 duration = cpu_to_le16(500); 4928 } else if (state == ETHTOOL_ID_INACTIVE) { 4929 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 4930 duration = cpu_to_le16(0); 4931 } else { 4932 return -EINVAL; 4933 } 4934 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG); 4935 if (rc) 4936 return rc; 4937 4938 req->port_id = cpu_to_le16(pf->port_id); 4939 req->num_leds = bp->num_leds; 4940 led_cfg = (struct bnxt_led_cfg *)&req->led0_id; 4941 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 4942 req->enables |= BNXT_LED_DFLT_ENABLES(i); 4943 led_cfg->led_id = bp->leds[i].led_id; 4944 led_cfg->led_state = led_state; 4945 led_cfg->led_blink_on = duration; 4946 led_cfg->led_blink_off = duration; 4947 led_cfg->led_group_id = bp->leds[i].led_group_id; 4948 } 4949 return hwrm_req_send(bp, req); 4950 } 4951 4952 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 4953 { 4954 struct hwrm_selftest_irq_input *req; 4955 int rc; 4956 4957 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ); 4958 if (rc) 4959 return rc; 4960 4961 req->cmpl_ring = cpu_to_le16(cmpl_ring); 4962 return hwrm_req_send(bp, req); 4963 } 4964 4965 static int bnxt_test_irq(struct bnxt *bp) 4966 { 4967 int i; 4968 4969 for (i = 0; i < bp->cp_nr_rings; i++) { 4970 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 4971 int rc; 4972 4973 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 4974 if (rc) 4975 return rc; 4976 } 4977 return 0; 4978 } 4979 4980 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 4981 { 4982 struct hwrm_port_mac_cfg_input *req; 4983 int rc; 4984 4985 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 4986 if (rc) 4987 return rc; 4988 4989 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 4990 if (enable) 4991 req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 4992 else 4993 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 4994 return hwrm_req_send(bp, req); 4995 } 4996 4997 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 4998 { 4999 struct hwrm_port_phy_qcaps_output *resp; 5000 struct hwrm_port_phy_qcaps_input *req; 5001 int rc; 5002 5003 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS); 5004 if (rc) 5005 return rc; 5006 5007 resp = hwrm_req_hold(bp, req); 5008 rc = hwrm_req_send(bp, req); 5009 if (!rc) 5010 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 5011 5012 hwrm_req_drop(bp, req); 5013 return rc; 5014 } 5015 5016 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 5017 struct hwrm_port_phy_cfg_input *req) 5018 { 5019 struct bnxt_link_info *link_info = &bp->link_info; 5020 u16 fw_advertising; 5021 u16 fw_speed; 5022 int rc; 5023 5024 if (!link_info->autoneg || 5025 (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK)) 5026 return 0; 5027 5028 rc = bnxt_query_force_speeds(bp, &fw_advertising); 5029 if (rc) 5030 return rc; 5031 5032 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 5033 if (BNXT_LINK_IS_UP(bp)) 5034 fw_speed = bp->link_info.link_speed; 5035 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 5036 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 5037 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 5038 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 5039 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 5040 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 5041 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 5042 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 5043 5044 req->force_link_speed = cpu_to_le16(fw_speed); 5045 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 5046 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 5047 rc = hwrm_req_send(bp, req); 5048 req->flags = 0; 5049 req->force_link_speed = cpu_to_le16(0); 5050 return rc; 5051 } 5052 5053 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 5054 { 5055 struct hwrm_port_phy_cfg_input *req; 5056 int rc; 5057 5058 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 5059 if (rc) 5060 return rc; 5061 5062 /* prevent bnxt_disable_an_for_lpbk() from consuming the request */ 5063 hwrm_req_hold(bp, req); 5064 5065 if (enable) { 5066 bnxt_disable_an_for_lpbk(bp, req); 5067 if (ext) 5068 req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 5069 else 5070 req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 5071 } else { 5072 req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 5073 } 5074 req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 5075 rc = hwrm_req_send(bp, req); 5076 hwrm_req_drop(bp, req); 5077 return rc; 5078 } 5079 5080 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 5081 u32 raw_cons, int pkt_size) 5082 { 5083 struct bnxt_napi *bnapi = cpr->bnapi; 5084 struct bnxt_rx_ring_info *rxr; 5085 struct bnxt_sw_rx_bd *rx_buf; 5086 struct rx_cmp *rxcmp; 5087 u16 cp_cons, cons; 5088 u8 *data; 5089 u32 len; 5090 int i; 5091 5092 rxr = bnapi->rx_ring; 5093 cp_cons = RING_CMP(raw_cons); 5094 rxcmp = (struct rx_cmp *) 5095 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 5096 cons = rxcmp->rx_cmp_opaque; 5097 rx_buf = &rxr->rx_buf_ring[cons]; 5098 data = rx_buf->data_ptr; 5099 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 5100 if (len != pkt_size) 5101 return -EIO; 5102 i = ETH_ALEN; 5103 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 5104 return -EIO; 5105 i += ETH_ALEN; 5106 for ( ; i < pkt_size; i++) { 5107 if (data[i] != (u8)(i & 0xff)) 5108 return -EIO; 5109 } 5110 return 0; 5111 } 5112 5113 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 5114 int pkt_size) 5115 { 5116 struct tx_cmp *txcmp; 5117 int rc = -EIO; 5118 u32 raw_cons; 5119 u32 cons; 5120 int i; 5121 5122 raw_cons = cpr->cp_raw_cons; 5123 for (i = 0; i < 200; i++) { 5124 cons = RING_CMP(raw_cons); 5125 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 5126 5127 if (!TX_CMP_VALID(txcmp, raw_cons)) { 5128 udelay(5); 5129 continue; 5130 } 5131 5132 /* The valid test of the entry must be done first before 5133 * reading any further. 5134 */ 5135 dma_rmb(); 5136 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP || 5137 TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_V3_CMP) { 5138 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 5139 raw_cons = NEXT_RAW_CMP(raw_cons); 5140 raw_cons = NEXT_RAW_CMP(raw_cons); 5141 break; 5142 } 5143 raw_cons = NEXT_RAW_CMP(raw_cons); 5144 } 5145 cpr->cp_raw_cons = raw_cons; 5146 return rc; 5147 } 5148 5149 static int bnxt_run_loopback(struct bnxt *bp) 5150 { 5151 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 5152 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 5153 struct bnxt_cp_ring_info *cpr; 5154 int pkt_size, i = 0; 5155 struct sk_buff *skb; 5156 dma_addr_t map; 5157 u8 *data; 5158 int rc; 5159 5160 cpr = &rxr->bnapi->cp_ring; 5161 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) 5162 cpr = rxr->rx_cpr; 5163 pkt_size = min(bp->dev->mtu + ETH_HLEN, max(BNXT_DEFAULT_RX_COPYBREAK, 5164 bp->rx_copybreak)); 5165 skb = netdev_alloc_skb(bp->dev, pkt_size); 5166 if (!skb) 5167 return -ENOMEM; 5168 data = skb_put(skb, pkt_size); 5169 ether_addr_copy(&data[i], bp->dev->dev_addr); 5170 i += ETH_ALEN; 5171 ether_addr_copy(&data[i], bp->dev->dev_addr); 5172 i += ETH_ALEN; 5173 for ( ; i < pkt_size; i++) 5174 data[i] = (u8)(i & 0xff); 5175 5176 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 5177 DMA_TO_DEVICE); 5178 if (dma_mapping_error(&bp->pdev->dev, map)) { 5179 dev_kfree_skb(skb); 5180 return -EIO; 5181 } 5182 bnxt_xmit_bd(bp, txr, map, pkt_size, NULL); 5183 5184 /* Sync BD data before updating doorbell */ 5185 wmb(); 5186 5187 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 5188 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 5189 5190 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE); 5191 dev_kfree_skb(skb); 5192 return rc; 5193 } 5194 5195 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 5196 { 5197 struct hwrm_selftest_exec_output *resp; 5198 struct hwrm_selftest_exec_input *req; 5199 int rc; 5200 5201 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC); 5202 if (rc) 5203 return rc; 5204 5205 hwrm_req_timeout(bp, req, bp->test_info->timeout); 5206 req->flags = test_mask; 5207 5208 resp = hwrm_req_hold(bp, req); 5209 rc = hwrm_req_send(bp, req); 5210 *test_results = resp->test_success; 5211 hwrm_req_drop(bp, req); 5212 return rc; 5213 } 5214 5215 #define BNXT_DRV_TESTS 4 5216 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 5217 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 5218 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 5219 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 5220 5221 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 5222 u64 *buf) 5223 { 5224 struct bnxt *bp = netdev_priv(dev); 5225 bool do_ext_lpbk = false; 5226 bool offline = false; 5227 u8 test_results = 0; 5228 u8 test_mask = 0; 5229 int rc = 0, i; 5230 5231 if (!bp->num_tests || !BNXT_PF(bp)) 5232 return; 5233 5234 memset(buf, 0, sizeof(u64) * bp->num_tests); 5235 if (etest->flags & ETH_TEST_FL_OFFLINE && 5236 bnxt_ulp_registered(bp->edev)) { 5237 etest->flags |= ETH_TEST_FL_FAILED; 5238 netdev_warn(dev, "Offline tests cannot be run with RoCE driver loaded\n"); 5239 return; 5240 } 5241 5242 if (!netif_running(dev)) { 5243 etest->flags |= ETH_TEST_FL_FAILED; 5244 return; 5245 } 5246 5247 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 5248 (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK)) 5249 do_ext_lpbk = true; 5250 5251 if (etest->flags & ETH_TEST_FL_OFFLINE) { 5252 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) { 5253 etest->flags |= ETH_TEST_FL_FAILED; 5254 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n"); 5255 return; 5256 } 5257 offline = true; 5258 } 5259 5260 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 5261 u8 bit_val = 1 << i; 5262 5263 if (!(bp->test_info->offline_mask & bit_val)) 5264 test_mask |= bit_val; 5265 else if (offline) 5266 test_mask |= bit_val; 5267 } 5268 if (!offline) { 5269 bnxt_run_fw_tests(bp, test_mask, &test_results); 5270 } else { 5271 bnxt_close_nic(bp, true, false); 5272 bnxt_run_fw_tests(bp, test_mask, &test_results); 5273 5274 rc = bnxt_half_open_nic(bp); 5275 if (rc) { 5276 etest->flags |= ETH_TEST_FL_FAILED; 5277 return; 5278 } 5279 buf[BNXT_MACLPBK_TEST_IDX] = 1; 5280 if (bp->mac_flags & BNXT_MAC_FL_NO_MAC_LPBK) 5281 goto skip_mac_loopback; 5282 5283 bnxt_hwrm_mac_loopback(bp, true); 5284 msleep(250); 5285 if (bnxt_run_loopback(bp)) 5286 etest->flags |= ETH_TEST_FL_FAILED; 5287 else 5288 buf[BNXT_MACLPBK_TEST_IDX] = 0; 5289 5290 bnxt_hwrm_mac_loopback(bp, false); 5291 skip_mac_loopback: 5292 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 5293 if (bp->phy_flags & BNXT_PHY_FL_NO_PHY_LPBK) 5294 goto skip_phy_loopback; 5295 5296 bnxt_hwrm_phy_loopback(bp, true, false); 5297 msleep(1000); 5298 if (bnxt_run_loopback(bp)) 5299 etest->flags |= ETH_TEST_FL_FAILED; 5300 else 5301 buf[BNXT_PHYLPBK_TEST_IDX] = 0; 5302 skip_phy_loopback: 5303 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 5304 if (do_ext_lpbk) { 5305 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 5306 bnxt_hwrm_phy_loopback(bp, true, true); 5307 msleep(1000); 5308 if (bnxt_run_loopback(bp)) 5309 etest->flags |= ETH_TEST_FL_FAILED; 5310 else 5311 buf[BNXT_EXTLPBK_TEST_IDX] = 0; 5312 } 5313 bnxt_hwrm_phy_loopback(bp, false, false); 5314 bnxt_half_close_nic(bp); 5315 rc = bnxt_open_nic(bp, true, true); 5316 } 5317 if (rc || bnxt_test_irq(bp)) { 5318 buf[BNXT_IRQ_TEST_IDX] = 1; 5319 etest->flags |= ETH_TEST_FL_FAILED; 5320 } 5321 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 5322 u8 bit_val = 1 << i; 5323 5324 if ((test_mask & bit_val) && !(test_results & bit_val)) { 5325 buf[i] = 1; 5326 etest->flags |= ETH_TEST_FL_FAILED; 5327 } 5328 } 5329 } 5330 5331 static int bnxt_reset(struct net_device *dev, u32 *flags) 5332 { 5333 struct bnxt *bp = netdev_priv(dev); 5334 bool reload = false; 5335 u32 req = *flags; 5336 5337 if (!req) 5338 return -EINVAL; 5339 5340 if (!BNXT_PF(bp)) { 5341 netdev_err(dev, "Reset is not supported from a VF\n"); 5342 return -EOPNOTSUPP; 5343 } 5344 5345 if (pci_vfs_assigned(bp->pdev) && 5346 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) { 5347 netdev_err(dev, 5348 "Reset not allowed when VFs are assigned to VMs\n"); 5349 return -EBUSY; 5350 } 5351 5352 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) { 5353 /* This feature is not supported in older firmware versions */ 5354 if (bp->hwrm_spec_code >= 0x10803) { 5355 if (!bnxt_firmware_reset_chip(dev)) { 5356 netdev_info(dev, "Firmware reset request successful.\n"); 5357 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) 5358 reload = true; 5359 *flags &= ~BNXT_FW_RESET_CHIP; 5360 } 5361 } else if (req == BNXT_FW_RESET_CHIP) { 5362 return -EOPNOTSUPP; /* only request, fail hard */ 5363 } 5364 } 5365 5366 if (!BNXT_CHIP_P4_PLUS(bp) && (req & BNXT_FW_RESET_AP)) { 5367 /* This feature is not supported in older firmware versions */ 5368 if (bp->hwrm_spec_code >= 0x10803) { 5369 if (!bnxt_firmware_reset_ap(dev)) { 5370 netdev_info(dev, "Reset application processor successful.\n"); 5371 reload = true; 5372 *flags &= ~BNXT_FW_RESET_AP; 5373 } 5374 } else if (req == BNXT_FW_RESET_AP) { 5375 return -EOPNOTSUPP; /* only request, fail hard */ 5376 } 5377 } 5378 5379 if (reload) 5380 netdev_info(dev, "Reload driver to complete reset\n"); 5381 5382 return 0; 5383 } 5384 5385 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump) 5386 { 5387 struct bnxt *bp = netdev_priv(dev); 5388 5389 if (dump->flag > BNXT_DUMP_LIVE_WITH_CTX_L1_CACHE) { 5390 netdev_info(dev, 5391 "Supports only Live(0), Crash(1), Driver(2), Live with cached context(3) dumps.\n"); 5392 return -EINVAL; 5393 } 5394 5395 if (dump->flag == BNXT_DUMP_CRASH) { 5396 if (bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR && 5397 (!IS_ENABLED(CONFIG_TEE_BNXT_FW))) { 5398 netdev_info(dev, 5399 "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n"); 5400 return -EOPNOTSUPP; 5401 } else if (!(bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR)) { 5402 netdev_info(dev, "Crash dump collection from host memory is not supported on this interface.\n"); 5403 return -EOPNOTSUPP; 5404 } 5405 } 5406 5407 bp->dump_flag = dump->flag; 5408 return 0; 5409 } 5410 5411 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 5412 { 5413 struct bnxt *bp = netdev_priv(dev); 5414 5415 if (bp->hwrm_spec_code < 0x10801) 5416 return -EOPNOTSUPP; 5417 5418 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 5419 bp->ver_resp.hwrm_fw_min_8b << 16 | 5420 bp->ver_resp.hwrm_fw_bld_8b << 8 | 5421 bp->ver_resp.hwrm_fw_rsvd_8b; 5422 5423 dump->flag = bp->dump_flag; 5424 dump->len = bnxt_get_coredump_length(bp, bp->dump_flag); 5425 return 0; 5426 } 5427 5428 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 5429 void *buf) 5430 { 5431 struct bnxt *bp = netdev_priv(dev); 5432 5433 if (bp->hwrm_spec_code < 0x10801) 5434 return -EOPNOTSUPP; 5435 5436 memset(buf, 0, dump->len); 5437 5438 dump->flag = bp->dump_flag; 5439 return bnxt_get_coredump(bp, dump->flag, buf, &dump->len); 5440 } 5441 5442 static int bnxt_get_ts_info(struct net_device *dev, 5443 struct kernel_ethtool_ts_info *info) 5444 { 5445 struct bnxt *bp = netdev_priv(dev); 5446 struct bnxt_ptp_cfg *ptp; 5447 5448 ptp = bp->ptp_cfg; 5449 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE; 5450 5451 if (!ptp) 5452 return 0; 5453 5454 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | 5455 SOF_TIMESTAMPING_RX_HARDWARE | 5456 SOF_TIMESTAMPING_RAW_HARDWARE; 5457 if (ptp->ptp_clock) 5458 info->phc_index = ptp_clock_index(ptp->ptp_clock); 5459 5460 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 5461 5462 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 5463 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 5464 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 5465 5466 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) 5467 info->rx_filters |= (1 << HWTSTAMP_FILTER_ALL); 5468 return 0; 5469 } 5470 5471 static void bnxt_hwrm_pcie_qstats(struct bnxt *bp) 5472 { 5473 struct hwrm_pcie_qstats_output *resp; 5474 struct hwrm_pcie_qstats_input *req; 5475 5476 bp->pcie_stat_len = 0; 5477 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 5478 return; 5479 5480 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS)) 5481 return; 5482 5483 resp = hwrm_req_hold(bp, req); 5484 if (__bnxt_hwrm_pcie_qstats(bp, req)) 5485 bp->pcie_stat_len = min_t(u16, 5486 le16_to_cpu(resp->pcie_stat_size), 5487 sizeof(struct pcie_ctx_hw_stats_v2)); 5488 hwrm_req_drop(bp, req); 5489 } 5490 5491 void bnxt_ethtool_init(struct bnxt *bp) 5492 { 5493 struct hwrm_selftest_qlist_output *resp; 5494 struct hwrm_selftest_qlist_input *req; 5495 struct bnxt_test_info *test_info; 5496 struct net_device *dev = bp->dev; 5497 int i, rc; 5498 5499 bnxt_hwrm_pcie_qstats(bp); 5500 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 5501 bnxt_get_pkgver(dev); 5502 5503 bp->num_tests = 0; 5504 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp)) 5505 return; 5506 5507 test_info = bp->test_info; 5508 if (!test_info) { 5509 test_info = kzalloc_obj(*bp->test_info); 5510 if (!test_info) 5511 return; 5512 bp->test_info = test_info; 5513 } 5514 5515 if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST)) 5516 return; 5517 5518 resp = hwrm_req_hold(bp, req); 5519 rc = hwrm_req_send_silent(bp, req); 5520 if (rc) 5521 goto ethtool_init_exit; 5522 5523 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 5524 if (bp->num_tests > BNXT_MAX_TEST) 5525 bp->num_tests = BNXT_MAX_TEST; 5526 5527 test_info->offline_mask = resp->offline_tests; 5528 test_info->timeout = le16_to_cpu(resp->test_timeout); 5529 if (!test_info->timeout) 5530 test_info->timeout = HWRM_CMD_TIMEOUT; 5531 for (i = 0; i < bp->num_tests; i++) { 5532 char *str = test_info->string[i]; 5533 char *fw_str = resp->test_name[i]; 5534 5535 if (i == BNXT_MACLPBK_TEST_IDX) { 5536 strcpy(str, "Mac loopback test (offline)"); 5537 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 5538 strcpy(str, "Phy loopback test (offline)"); 5539 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 5540 strcpy(str, "Ext loopback test (offline)"); 5541 } else if (i == BNXT_IRQ_TEST_IDX) { 5542 strcpy(str, "Interrupt_test (offline)"); 5543 } else { 5544 snprintf(str, ETH_GSTRING_LEN, "%s test (%s)", 5545 fw_str, test_info->offline_mask & (1 << i) ? 5546 "offline" : "online"); 5547 } 5548 } 5549 5550 ethtool_init_exit: 5551 hwrm_req_drop(bp, req); 5552 } 5553 5554 static void bnxt_get_eth_phy_stats(struct net_device *dev, 5555 struct ethtool_eth_phy_stats *phy_stats) 5556 { 5557 struct bnxt *bp = netdev_priv(dev); 5558 u64 *rx; 5559 5560 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 5561 return; 5562 5563 rx = bp->rx_port_stats_ext.sw_stats; 5564 phy_stats->SymbolErrorDuringCarrier = 5565 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err)); 5566 } 5567 5568 static void bnxt_get_eth_mac_stats(struct net_device *dev, 5569 struct ethtool_eth_mac_stats *mac_stats) 5570 { 5571 struct bnxt *bp = netdev_priv(dev); 5572 u64 *rx, *tx; 5573 5574 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5575 return; 5576 5577 rx = bp->port_stats.sw_stats; 5578 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 5579 5580 mac_stats->FramesReceivedOK = 5581 BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames); 5582 mac_stats->FramesTransmittedOK = 5583 BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames); 5584 mac_stats->FrameCheckSequenceErrors = 5585 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames); 5586 mac_stats->AlignmentErrors = 5587 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames); 5588 mac_stats->OutOfRangeLengthField = 5589 BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames); 5590 } 5591 5592 static void bnxt_get_eth_ctrl_stats(struct net_device *dev, 5593 struct ethtool_eth_ctrl_stats *ctrl_stats) 5594 { 5595 struct bnxt *bp = netdev_priv(dev); 5596 u64 *rx; 5597 5598 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5599 return; 5600 5601 rx = bp->port_stats.sw_stats; 5602 ctrl_stats->MACControlFramesReceived = 5603 BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames); 5604 } 5605 5606 static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = { 5607 { 0, 64 }, 5608 { 65, 127 }, 5609 { 128, 255 }, 5610 { 256, 511 }, 5611 { 512, 1023 }, 5612 { 1024, 1518 }, 5613 { 1519, 2047 }, 5614 { 2048, 4095 }, 5615 { 4096, 9216 }, 5616 { 9217, 16383 }, 5617 {} 5618 }; 5619 5620 static void bnxt_get_rmon_stats(struct net_device *dev, 5621 struct ethtool_rmon_stats *rmon_stats, 5622 const struct ethtool_rmon_hist_range **ranges) 5623 { 5624 struct bnxt *bp = netdev_priv(dev); 5625 u64 *rx, *tx; 5626 5627 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5628 return; 5629 5630 rx = bp->port_stats.sw_stats; 5631 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 5632 5633 rmon_stats->jabbers = 5634 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames); 5635 rmon_stats->oversize_pkts = 5636 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames); 5637 rmon_stats->undersize_pkts = 5638 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames); 5639 5640 rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames); 5641 rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames); 5642 rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames); 5643 rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames); 5644 rmon_stats->hist[4] = 5645 BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames); 5646 rmon_stats->hist[5] = 5647 BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames); 5648 rmon_stats->hist[6] = 5649 BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames); 5650 rmon_stats->hist[7] = 5651 BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames); 5652 rmon_stats->hist[8] = 5653 BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames); 5654 rmon_stats->hist[9] = 5655 BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames); 5656 5657 rmon_stats->hist_tx[0] = 5658 BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames); 5659 rmon_stats->hist_tx[1] = 5660 BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames); 5661 rmon_stats->hist_tx[2] = 5662 BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames); 5663 rmon_stats->hist_tx[3] = 5664 BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames); 5665 rmon_stats->hist_tx[4] = 5666 BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames); 5667 rmon_stats->hist_tx[5] = 5668 BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames); 5669 rmon_stats->hist_tx[6] = 5670 BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames); 5671 rmon_stats->hist_tx[7] = 5672 BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames); 5673 rmon_stats->hist_tx[8] = 5674 BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames); 5675 rmon_stats->hist_tx[9] = 5676 BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames); 5677 5678 *ranges = bnxt_rmon_ranges; 5679 } 5680 5681 static void bnxt_get_ptp_stats(struct net_device *dev, 5682 struct ethtool_ts_stats *ts_stats) 5683 { 5684 struct bnxt *bp = netdev_priv(dev); 5685 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 5686 5687 if (ptp) { 5688 ts_stats->pkts = ptp->stats.ts_pkts; 5689 ts_stats->lost = ptp->stats.ts_lost; 5690 ts_stats->err = atomic64_read(&ptp->stats.ts_err); 5691 } 5692 } 5693 5694 static void bnxt_get_link_ext_stats(struct net_device *dev, 5695 struct ethtool_link_ext_stats *stats) 5696 { 5697 struct bnxt *bp = netdev_priv(dev); 5698 u64 *rx; 5699 5700 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 5701 return; 5702 5703 rx = bp->rx_port_stats_ext.sw_stats; 5704 stats->link_down_events = 5705 *(rx + BNXT_RX_STATS_EXT_OFFSET(link_down_events)); 5706 } 5707 5708 void bnxt_ethtool_free(struct bnxt *bp) 5709 { 5710 kfree(bp->test_info); 5711 bp->test_info = NULL; 5712 } 5713 5714 const struct ethtool_ops bnxt_ethtool_ops = { 5715 .cap_link_lanes_supported = 1, 5716 .rxfh_per_ctx_key = 1, 5717 .rxfh_max_num_contexts = BNXT_MAX_ETH_RSS_CTX + 1, 5718 .rxfh_indir_space = BNXT_MAX_RSS_TABLE_ENTRIES_P5, 5719 .rxfh_priv_size = sizeof(struct bnxt_rss_ctx), 5720 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 5721 ETHTOOL_COALESCE_MAX_FRAMES | 5722 ETHTOOL_COALESCE_USECS_IRQ | 5723 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 5724 ETHTOOL_COALESCE_STATS_BLOCK_USECS | 5725 ETHTOOL_COALESCE_USE_ADAPTIVE_RX | 5726 ETHTOOL_COALESCE_USE_CQE, 5727 .supported_ring_params = ETHTOOL_RING_USE_TCP_DATA_SPLIT | 5728 ETHTOOL_RING_USE_HDS_THRS, 5729 .get_link_ksettings = bnxt_get_link_ksettings, 5730 .set_link_ksettings = bnxt_set_link_ksettings, 5731 .get_fec_stats = bnxt_get_fec_stats, 5732 .get_fecparam = bnxt_get_fecparam, 5733 .set_fecparam = bnxt_set_fecparam, 5734 .get_pause_stats = bnxt_get_pause_stats, 5735 .get_pauseparam = bnxt_get_pauseparam, 5736 .set_pauseparam = bnxt_set_pauseparam, 5737 .get_drvinfo = bnxt_get_drvinfo, 5738 .get_regs_len = bnxt_get_regs_len, 5739 .get_regs = bnxt_get_regs, 5740 .get_wol = bnxt_get_wol, 5741 .set_wol = bnxt_set_wol, 5742 .get_coalesce = bnxt_get_coalesce, 5743 .set_coalesce = bnxt_set_coalesce, 5744 .get_msglevel = bnxt_get_msglevel, 5745 .set_msglevel = bnxt_set_msglevel, 5746 .get_sset_count = bnxt_get_sset_count, 5747 .get_strings = bnxt_get_strings, 5748 .get_ethtool_stats = bnxt_get_ethtool_stats, 5749 .set_ringparam = bnxt_set_ringparam, 5750 .get_ringparam = bnxt_get_ringparam, 5751 .get_channels = bnxt_get_channels, 5752 .set_channels = bnxt_set_channels, 5753 .get_rxnfc = bnxt_get_rxnfc, 5754 .set_rxnfc = bnxt_set_rxnfc, 5755 .get_rx_ring_count = bnxt_get_rx_ring_count, 5756 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 5757 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 5758 .get_rxfh = bnxt_get_rxfh, 5759 .set_rxfh = bnxt_set_rxfh, 5760 .get_rxfh_fields = bnxt_get_rxfh_fields, 5761 .set_rxfh_fields = bnxt_set_rxfh_fields, 5762 .create_rxfh_context = bnxt_create_rxfh_context, 5763 .modify_rxfh_context = bnxt_modify_rxfh_context, 5764 .remove_rxfh_context = bnxt_remove_rxfh_context, 5765 .flash_device = bnxt_flash_device, 5766 .get_eeprom_len = bnxt_get_eeprom_len, 5767 .get_eeprom = bnxt_get_eeprom, 5768 .set_eeprom = bnxt_set_eeprom, 5769 .get_link = bnxt_get_link, 5770 .get_link_ext_state = bnxt_get_link_ext_state, 5771 .get_link_ext_stats = bnxt_get_link_ext_stats, 5772 .get_eee = bnxt_get_eee, 5773 .set_eee = bnxt_set_eee, 5774 .get_tunable = bnxt_get_tunable, 5775 .set_tunable = bnxt_set_tunable, 5776 .get_module_info = bnxt_get_module_info, 5777 .get_module_eeprom = bnxt_get_module_eeprom, 5778 .get_module_eeprom_by_page = bnxt_get_module_eeprom_by_page, 5779 .set_module_eeprom_by_page = bnxt_set_module_eeprom_by_page, 5780 .nway_reset = bnxt_nway_reset, 5781 .set_phys_id = bnxt_set_phys_id, 5782 .self_test = bnxt_self_test, 5783 .get_ts_info = bnxt_get_ts_info, 5784 .reset = bnxt_reset, 5785 .set_dump = bnxt_set_dump, 5786 .get_dump_flag = bnxt_get_dump_flag, 5787 .get_dump_data = bnxt_get_dump_data, 5788 .get_eth_phy_stats = bnxt_get_eth_phy_stats, 5789 .get_eth_mac_stats = bnxt_get_eth_mac_stats, 5790 .get_eth_ctrl_stats = bnxt_get_eth_ctrl_stats, 5791 .get_rmon_stats = bnxt_get_rmon_stats, 5792 .get_ts_stats = bnxt_get_ptp_stats, 5793 }; 5794