xref: /linux/drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c (revision d7f39aee79f04eeaa42085728423501b33ac5be5)
1 /* Broadcom NetXtreme-C/E network driver.
2  *
3  * Copyright (c) 2014-2016 Broadcom Corporation
4  * Copyright (c) 2016-2017 Broadcom Limited
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation.
9  */
10 
11 #include <linux/bitops.h>
12 #include <linux/ctype.h>
13 #include <linux/stringify.h>
14 #include <linux/ethtool.h>
15 #include <linux/ethtool_netlink.h>
16 #include <linux/linkmode.h>
17 #include <linux/interrupt.h>
18 #include <linux/pci.h>
19 #include <linux/etherdevice.h>
20 #include <linux/crc32.h>
21 #include <linux/firmware.h>
22 #include <linux/utsname.h>
23 #include <linux/time.h>
24 #include <linux/ptp_clock_kernel.h>
25 #include <linux/net_tstamp.h>
26 #include <linux/timecounter.h>
27 #include <net/netlink.h>
28 #include "bnxt_hsi.h"
29 #include "bnxt.h"
30 #include "bnxt_hwrm.h"
31 #include "bnxt_ulp.h"
32 #include "bnxt_xdp.h"
33 #include "bnxt_ptp.h"
34 #include "bnxt_ethtool.h"
35 #include "bnxt_nvm_defs.h"	/* NVRAM content constant and structure defs */
36 #include "bnxt_fw_hdr.h"	/* Firmware hdr constant and structure defs */
37 #include "bnxt_coredump.h"
38 
39 #define BNXT_NVM_ERR_MSG(dev, extack, msg)			\
40 	do {							\
41 		if (extack)					\
42 			NL_SET_ERR_MSG_MOD(extack, msg);	\
43 		netdev_err(dev, "%s\n", msg);			\
44 	} while (0)
45 
46 static u32 bnxt_get_msglevel(struct net_device *dev)
47 {
48 	struct bnxt *bp = netdev_priv(dev);
49 
50 	return bp->msg_enable;
51 }
52 
53 static void bnxt_set_msglevel(struct net_device *dev, u32 value)
54 {
55 	struct bnxt *bp = netdev_priv(dev);
56 
57 	bp->msg_enable = value;
58 }
59 
60 static int bnxt_get_coalesce(struct net_device *dev,
61 			     struct ethtool_coalesce *coal,
62 			     struct kernel_ethtool_coalesce *kernel_coal,
63 			     struct netlink_ext_ack *extack)
64 {
65 	struct bnxt *bp = netdev_priv(dev);
66 	struct bnxt_coal *hw_coal;
67 	u16 mult;
68 
69 	memset(coal, 0, sizeof(*coal));
70 
71 	coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM;
72 
73 	hw_coal = &bp->rx_coal;
74 	mult = hw_coal->bufs_per_record;
75 	coal->rx_coalesce_usecs = hw_coal->coal_ticks;
76 	coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult;
77 	coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
78 	coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
79 	if (hw_coal->flags &
80 	    RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET)
81 		kernel_coal->use_cqe_mode_rx = true;
82 
83 	hw_coal = &bp->tx_coal;
84 	mult = hw_coal->bufs_per_record;
85 	coal->tx_coalesce_usecs = hw_coal->coal_ticks;
86 	coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult;
87 	coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
88 	coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
89 	if (hw_coal->flags &
90 	    RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET)
91 		kernel_coal->use_cqe_mode_tx = true;
92 
93 	coal->stats_block_coalesce_usecs = bp->stats_coal_ticks;
94 
95 	return 0;
96 }
97 
98 static int bnxt_set_coalesce(struct net_device *dev,
99 			     struct ethtool_coalesce *coal,
100 			     struct kernel_ethtool_coalesce *kernel_coal,
101 			     struct netlink_ext_ack *extack)
102 {
103 	struct bnxt *bp = netdev_priv(dev);
104 	bool update_stats = false;
105 	struct bnxt_coal *hw_coal;
106 	int rc = 0;
107 	u16 mult;
108 
109 	if (coal->use_adaptive_rx_coalesce) {
110 		bp->flags |= BNXT_FLAG_DIM;
111 	} else {
112 		if (bp->flags & BNXT_FLAG_DIM) {
113 			bp->flags &= ~(BNXT_FLAG_DIM);
114 			goto reset_coalesce;
115 		}
116 	}
117 
118 	if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) &&
119 	    !(bp->coal_cap.cmpl_params &
120 	      RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET))
121 		return -EOPNOTSUPP;
122 
123 	hw_coal = &bp->rx_coal;
124 	mult = hw_coal->bufs_per_record;
125 	hw_coal->coal_ticks = coal->rx_coalesce_usecs;
126 	hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult;
127 	hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq;
128 	hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult;
129 	hw_coal->flags &=
130 		~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
131 	if (kernel_coal->use_cqe_mode_rx)
132 		hw_coal->flags |=
133 			RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
134 
135 	hw_coal = &bp->tx_coal;
136 	mult = hw_coal->bufs_per_record;
137 	hw_coal->coal_ticks = coal->tx_coalesce_usecs;
138 	hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult;
139 	hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq;
140 	hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult;
141 	hw_coal->flags &=
142 		~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
143 	if (kernel_coal->use_cqe_mode_tx)
144 		hw_coal->flags |=
145 			RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
146 
147 	if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) {
148 		u32 stats_ticks = coal->stats_block_coalesce_usecs;
149 
150 		/* Allow 0, which means disable. */
151 		if (stats_ticks)
152 			stats_ticks = clamp_t(u32, stats_ticks,
153 					      BNXT_MIN_STATS_COAL_TICKS,
154 					      BNXT_MAX_STATS_COAL_TICKS);
155 		stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS);
156 		bp->stats_coal_ticks = stats_ticks;
157 		if (bp->stats_coal_ticks)
158 			bp->current_interval =
159 				bp->stats_coal_ticks * HZ / 1000000;
160 		else
161 			bp->current_interval = BNXT_TIMER_INTERVAL;
162 		update_stats = true;
163 	}
164 
165 reset_coalesce:
166 	if (test_bit(BNXT_STATE_OPEN, &bp->state)) {
167 		if (update_stats) {
168 			bnxt_close_nic(bp, true, false);
169 			rc = bnxt_open_nic(bp, true, false);
170 		} else {
171 			rc = bnxt_hwrm_set_coal(bp);
172 		}
173 	}
174 
175 	return rc;
176 }
177 
178 static const char * const bnxt_ring_rx_stats_str[] = {
179 	"rx_ucast_packets",
180 	"rx_mcast_packets",
181 	"rx_bcast_packets",
182 	"rx_discards",
183 	"rx_errors",
184 	"rx_ucast_bytes",
185 	"rx_mcast_bytes",
186 	"rx_bcast_bytes",
187 };
188 
189 static const char * const bnxt_ring_tx_stats_str[] = {
190 	"tx_ucast_packets",
191 	"tx_mcast_packets",
192 	"tx_bcast_packets",
193 	"tx_errors",
194 	"tx_discards",
195 	"tx_ucast_bytes",
196 	"tx_mcast_bytes",
197 	"tx_bcast_bytes",
198 };
199 
200 static const char * const bnxt_ring_tpa_stats_str[] = {
201 	"tpa_packets",
202 	"tpa_bytes",
203 	"tpa_events",
204 	"tpa_aborts",
205 };
206 
207 static const char * const bnxt_ring_tpa2_stats_str[] = {
208 	"rx_tpa_eligible_pkt",
209 	"rx_tpa_eligible_bytes",
210 	"rx_tpa_pkt",
211 	"rx_tpa_bytes",
212 	"rx_tpa_errors",
213 	"rx_tpa_events",
214 };
215 
216 static const char * const bnxt_rx_sw_stats_str[] = {
217 	"rx_l4_csum_errors",
218 	"rx_resets",
219 	"rx_buf_errors",
220 };
221 
222 static const char * const bnxt_cmn_sw_stats_str[] = {
223 	"missed_irqs",
224 };
225 
226 #define BNXT_RX_STATS_ENTRY(counter)	\
227 	{ BNXT_RX_STATS_OFFSET(counter), __stringify(counter) }
228 
229 #define BNXT_TX_STATS_ENTRY(counter)	\
230 	{ BNXT_TX_STATS_OFFSET(counter), __stringify(counter) }
231 
232 #define BNXT_RX_STATS_EXT_ENTRY(counter)	\
233 	{ BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) }
234 
235 #define BNXT_TX_STATS_EXT_ENTRY(counter)	\
236 	{ BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) }
237 
238 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n)				\
239 	BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us),	\
240 	BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions)
241 
242 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n)				\
243 	BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us),	\
244 	BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions)
245 
246 #define BNXT_RX_STATS_EXT_PFC_ENTRIES				\
247 	BNXT_RX_STATS_EXT_PFC_ENTRY(0),				\
248 	BNXT_RX_STATS_EXT_PFC_ENTRY(1),				\
249 	BNXT_RX_STATS_EXT_PFC_ENTRY(2),				\
250 	BNXT_RX_STATS_EXT_PFC_ENTRY(3),				\
251 	BNXT_RX_STATS_EXT_PFC_ENTRY(4),				\
252 	BNXT_RX_STATS_EXT_PFC_ENTRY(5),				\
253 	BNXT_RX_STATS_EXT_PFC_ENTRY(6),				\
254 	BNXT_RX_STATS_EXT_PFC_ENTRY(7)
255 
256 #define BNXT_TX_STATS_EXT_PFC_ENTRIES				\
257 	BNXT_TX_STATS_EXT_PFC_ENTRY(0),				\
258 	BNXT_TX_STATS_EXT_PFC_ENTRY(1),				\
259 	BNXT_TX_STATS_EXT_PFC_ENTRY(2),				\
260 	BNXT_TX_STATS_EXT_PFC_ENTRY(3),				\
261 	BNXT_TX_STATS_EXT_PFC_ENTRY(4),				\
262 	BNXT_TX_STATS_EXT_PFC_ENTRY(5),				\
263 	BNXT_TX_STATS_EXT_PFC_ENTRY(6),				\
264 	BNXT_TX_STATS_EXT_PFC_ENTRY(7)
265 
266 #define BNXT_RX_STATS_EXT_COS_ENTRY(n)				\
267 	BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n),		\
268 	BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n)
269 
270 #define BNXT_TX_STATS_EXT_COS_ENTRY(n)				\
271 	BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n),		\
272 	BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n)
273 
274 #define BNXT_RX_STATS_EXT_COS_ENTRIES				\
275 	BNXT_RX_STATS_EXT_COS_ENTRY(0),				\
276 	BNXT_RX_STATS_EXT_COS_ENTRY(1),				\
277 	BNXT_RX_STATS_EXT_COS_ENTRY(2),				\
278 	BNXT_RX_STATS_EXT_COS_ENTRY(3),				\
279 	BNXT_RX_STATS_EXT_COS_ENTRY(4),				\
280 	BNXT_RX_STATS_EXT_COS_ENTRY(5),				\
281 	BNXT_RX_STATS_EXT_COS_ENTRY(6),				\
282 	BNXT_RX_STATS_EXT_COS_ENTRY(7)				\
283 
284 #define BNXT_TX_STATS_EXT_COS_ENTRIES				\
285 	BNXT_TX_STATS_EXT_COS_ENTRY(0),				\
286 	BNXT_TX_STATS_EXT_COS_ENTRY(1),				\
287 	BNXT_TX_STATS_EXT_COS_ENTRY(2),				\
288 	BNXT_TX_STATS_EXT_COS_ENTRY(3),				\
289 	BNXT_TX_STATS_EXT_COS_ENTRY(4),				\
290 	BNXT_TX_STATS_EXT_COS_ENTRY(5),				\
291 	BNXT_TX_STATS_EXT_COS_ENTRY(6),				\
292 	BNXT_TX_STATS_EXT_COS_ENTRY(7)				\
293 
294 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n)			\
295 	BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n),	\
296 	BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n)
297 
298 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES				\
299 	BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0),				\
300 	BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1),				\
301 	BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2),				\
302 	BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3),				\
303 	BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4),				\
304 	BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5),				\
305 	BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6),				\
306 	BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7)
307 
308 #define BNXT_RX_STATS_PRI_ENTRY(counter, n)		\
309 	{ BNXT_RX_STATS_EXT_OFFSET(counter##_cos0),	\
310 	  __stringify(counter##_pri##n) }
311 
312 #define BNXT_TX_STATS_PRI_ENTRY(counter, n)		\
313 	{ BNXT_TX_STATS_EXT_OFFSET(counter##_cos0),	\
314 	  __stringify(counter##_pri##n) }
315 
316 #define BNXT_RX_STATS_PRI_ENTRIES(counter)		\
317 	BNXT_RX_STATS_PRI_ENTRY(counter, 0),		\
318 	BNXT_RX_STATS_PRI_ENTRY(counter, 1),		\
319 	BNXT_RX_STATS_PRI_ENTRY(counter, 2),		\
320 	BNXT_RX_STATS_PRI_ENTRY(counter, 3),		\
321 	BNXT_RX_STATS_PRI_ENTRY(counter, 4),		\
322 	BNXT_RX_STATS_PRI_ENTRY(counter, 5),		\
323 	BNXT_RX_STATS_PRI_ENTRY(counter, 6),		\
324 	BNXT_RX_STATS_PRI_ENTRY(counter, 7)
325 
326 #define BNXT_TX_STATS_PRI_ENTRIES(counter)		\
327 	BNXT_TX_STATS_PRI_ENTRY(counter, 0),		\
328 	BNXT_TX_STATS_PRI_ENTRY(counter, 1),		\
329 	BNXT_TX_STATS_PRI_ENTRY(counter, 2),		\
330 	BNXT_TX_STATS_PRI_ENTRY(counter, 3),		\
331 	BNXT_TX_STATS_PRI_ENTRY(counter, 4),		\
332 	BNXT_TX_STATS_PRI_ENTRY(counter, 5),		\
333 	BNXT_TX_STATS_PRI_ENTRY(counter, 6),		\
334 	BNXT_TX_STATS_PRI_ENTRY(counter, 7)
335 
336 enum {
337 	RX_TOTAL_DISCARDS,
338 	TX_TOTAL_DISCARDS,
339 	RX_NETPOLL_DISCARDS,
340 };
341 
342 static const char *const bnxt_ring_err_stats_arr[] = {
343 	"rx_total_l4_csum_errors",
344 	"rx_total_resets",
345 	"rx_total_buf_errors",
346 	"rx_total_oom_discards",
347 	"rx_total_netpoll_discards",
348 	"rx_total_ring_discards",
349 	"tx_total_resets",
350 	"tx_total_ring_discards",
351 	"total_missed_irqs",
352 };
353 
354 #define NUM_RING_RX_SW_STATS		ARRAY_SIZE(bnxt_rx_sw_stats_str)
355 #define NUM_RING_CMN_SW_STATS		ARRAY_SIZE(bnxt_cmn_sw_stats_str)
356 #define NUM_RING_RX_HW_STATS		ARRAY_SIZE(bnxt_ring_rx_stats_str)
357 #define NUM_RING_TX_HW_STATS		ARRAY_SIZE(bnxt_ring_tx_stats_str)
358 
359 static const struct {
360 	long offset;
361 	char string[ETH_GSTRING_LEN];
362 } bnxt_port_stats_arr[] = {
363 	BNXT_RX_STATS_ENTRY(rx_64b_frames),
364 	BNXT_RX_STATS_ENTRY(rx_65b_127b_frames),
365 	BNXT_RX_STATS_ENTRY(rx_128b_255b_frames),
366 	BNXT_RX_STATS_ENTRY(rx_256b_511b_frames),
367 	BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames),
368 	BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames),
369 	BNXT_RX_STATS_ENTRY(rx_good_vlan_frames),
370 	BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames),
371 	BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames),
372 	BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames),
373 	BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames),
374 	BNXT_RX_STATS_ENTRY(rx_total_frames),
375 	BNXT_RX_STATS_ENTRY(rx_ucast_frames),
376 	BNXT_RX_STATS_ENTRY(rx_mcast_frames),
377 	BNXT_RX_STATS_ENTRY(rx_bcast_frames),
378 	BNXT_RX_STATS_ENTRY(rx_fcs_err_frames),
379 	BNXT_RX_STATS_ENTRY(rx_ctrl_frames),
380 	BNXT_RX_STATS_ENTRY(rx_pause_frames),
381 	BNXT_RX_STATS_ENTRY(rx_pfc_frames),
382 	BNXT_RX_STATS_ENTRY(rx_align_err_frames),
383 	BNXT_RX_STATS_ENTRY(rx_ovrsz_frames),
384 	BNXT_RX_STATS_ENTRY(rx_jbr_frames),
385 	BNXT_RX_STATS_ENTRY(rx_mtu_err_frames),
386 	BNXT_RX_STATS_ENTRY(rx_tagged_frames),
387 	BNXT_RX_STATS_ENTRY(rx_double_tagged_frames),
388 	BNXT_RX_STATS_ENTRY(rx_good_frames),
389 	BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0),
390 	BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1),
391 	BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2),
392 	BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3),
393 	BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4),
394 	BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5),
395 	BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6),
396 	BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7),
397 	BNXT_RX_STATS_ENTRY(rx_undrsz_frames),
398 	BNXT_RX_STATS_ENTRY(rx_eee_lpi_events),
399 	BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration),
400 	BNXT_RX_STATS_ENTRY(rx_bytes),
401 	BNXT_RX_STATS_ENTRY(rx_runt_bytes),
402 	BNXT_RX_STATS_ENTRY(rx_runt_frames),
403 	BNXT_RX_STATS_ENTRY(rx_stat_discard),
404 	BNXT_RX_STATS_ENTRY(rx_stat_err),
405 
406 	BNXT_TX_STATS_ENTRY(tx_64b_frames),
407 	BNXT_TX_STATS_ENTRY(tx_65b_127b_frames),
408 	BNXT_TX_STATS_ENTRY(tx_128b_255b_frames),
409 	BNXT_TX_STATS_ENTRY(tx_256b_511b_frames),
410 	BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames),
411 	BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames),
412 	BNXT_TX_STATS_ENTRY(tx_good_vlan_frames),
413 	BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames),
414 	BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames),
415 	BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames),
416 	BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames),
417 	BNXT_TX_STATS_ENTRY(tx_good_frames),
418 	BNXT_TX_STATS_ENTRY(tx_total_frames),
419 	BNXT_TX_STATS_ENTRY(tx_ucast_frames),
420 	BNXT_TX_STATS_ENTRY(tx_mcast_frames),
421 	BNXT_TX_STATS_ENTRY(tx_bcast_frames),
422 	BNXT_TX_STATS_ENTRY(tx_pause_frames),
423 	BNXT_TX_STATS_ENTRY(tx_pfc_frames),
424 	BNXT_TX_STATS_ENTRY(tx_jabber_frames),
425 	BNXT_TX_STATS_ENTRY(tx_fcs_err_frames),
426 	BNXT_TX_STATS_ENTRY(tx_err),
427 	BNXT_TX_STATS_ENTRY(tx_fifo_underruns),
428 	BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0),
429 	BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1),
430 	BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2),
431 	BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3),
432 	BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4),
433 	BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5),
434 	BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6),
435 	BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7),
436 	BNXT_TX_STATS_ENTRY(tx_eee_lpi_events),
437 	BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration),
438 	BNXT_TX_STATS_ENTRY(tx_total_collisions),
439 	BNXT_TX_STATS_ENTRY(tx_bytes),
440 	BNXT_TX_STATS_ENTRY(tx_xthol_frames),
441 	BNXT_TX_STATS_ENTRY(tx_stat_discard),
442 	BNXT_TX_STATS_ENTRY(tx_stat_error),
443 };
444 
445 static const struct {
446 	long offset;
447 	char string[ETH_GSTRING_LEN];
448 } bnxt_port_stats_ext_arr[] = {
449 	BNXT_RX_STATS_EXT_ENTRY(link_down_events),
450 	BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events),
451 	BNXT_RX_STATS_EXT_ENTRY(resume_pause_events),
452 	BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events),
453 	BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events),
454 	BNXT_RX_STATS_EXT_COS_ENTRIES,
455 	BNXT_RX_STATS_EXT_PFC_ENTRIES,
456 	BNXT_RX_STATS_EXT_ENTRY(rx_bits),
457 	BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold),
458 	BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err),
459 	BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits),
460 	BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES,
461 	BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks),
462 	BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks),
463 	BNXT_RX_STATS_EXT_ENTRY(rx_filter_miss),
464 };
465 
466 static const struct {
467 	long offset;
468 	char string[ETH_GSTRING_LEN];
469 } bnxt_tx_port_stats_ext_arr[] = {
470 	BNXT_TX_STATS_EXT_COS_ENTRIES,
471 	BNXT_TX_STATS_EXT_PFC_ENTRIES,
472 };
473 
474 static const struct {
475 	long base_off;
476 	char string[ETH_GSTRING_LEN];
477 } bnxt_rx_bytes_pri_arr[] = {
478 	BNXT_RX_STATS_PRI_ENTRIES(rx_bytes),
479 };
480 
481 static const struct {
482 	long base_off;
483 	char string[ETH_GSTRING_LEN];
484 } bnxt_rx_pkts_pri_arr[] = {
485 	BNXT_RX_STATS_PRI_ENTRIES(rx_packets),
486 };
487 
488 static const struct {
489 	long base_off;
490 	char string[ETH_GSTRING_LEN];
491 } bnxt_tx_bytes_pri_arr[] = {
492 	BNXT_TX_STATS_PRI_ENTRIES(tx_bytes),
493 };
494 
495 static const struct {
496 	long base_off;
497 	char string[ETH_GSTRING_LEN];
498 } bnxt_tx_pkts_pri_arr[] = {
499 	BNXT_TX_STATS_PRI_ENTRIES(tx_packets),
500 };
501 
502 #define BNXT_NUM_RING_ERR_STATS	ARRAY_SIZE(bnxt_ring_err_stats_arr)
503 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr)
504 #define BNXT_NUM_STATS_PRI			\
505 	(ARRAY_SIZE(bnxt_rx_bytes_pri_arr) +	\
506 	 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) +	\
507 	 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) +	\
508 	 ARRAY_SIZE(bnxt_tx_pkts_pri_arr))
509 
510 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp)
511 {
512 	if (BNXT_SUPPORTS_TPA(bp)) {
513 		if (bp->max_tpa_v2) {
514 			if (BNXT_CHIP_P5(bp))
515 				return BNXT_NUM_TPA_RING_STATS_P5;
516 			return BNXT_NUM_TPA_RING_STATS_P7;
517 		}
518 		return BNXT_NUM_TPA_RING_STATS;
519 	}
520 	return 0;
521 }
522 
523 static int bnxt_get_num_ring_stats(struct bnxt *bp)
524 {
525 	int rx, tx, cmn;
526 
527 	rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS +
528 	     bnxt_get_num_tpa_ring_stats(bp);
529 	tx = NUM_RING_TX_HW_STATS;
530 	cmn = NUM_RING_CMN_SW_STATS;
531 	return rx * bp->rx_nr_rings +
532 	       tx * (bp->tx_nr_rings_xdp + bp->tx_nr_rings_per_tc) +
533 	       cmn * bp->cp_nr_rings;
534 }
535 
536 static int bnxt_get_num_stats(struct bnxt *bp)
537 {
538 	int num_stats = bnxt_get_num_ring_stats(bp);
539 	int len;
540 
541 	num_stats += BNXT_NUM_RING_ERR_STATS;
542 
543 	if (bp->flags & BNXT_FLAG_PORT_STATS)
544 		num_stats += BNXT_NUM_PORT_STATS;
545 
546 	if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
547 		len = min_t(int, bp->fw_rx_stats_ext_size,
548 			    ARRAY_SIZE(bnxt_port_stats_ext_arr));
549 		num_stats += len;
550 		len = min_t(int, bp->fw_tx_stats_ext_size,
551 			    ARRAY_SIZE(bnxt_tx_port_stats_ext_arr));
552 		num_stats += len;
553 		if (bp->pri2cos_valid)
554 			num_stats += BNXT_NUM_STATS_PRI;
555 	}
556 
557 	return num_stats;
558 }
559 
560 static int bnxt_get_sset_count(struct net_device *dev, int sset)
561 {
562 	struct bnxt *bp = netdev_priv(dev);
563 
564 	switch (sset) {
565 	case ETH_SS_STATS:
566 		return bnxt_get_num_stats(bp);
567 	case ETH_SS_TEST:
568 		if (!bp->num_tests)
569 			return -EOPNOTSUPP;
570 		return bp->num_tests;
571 	default:
572 		return -EOPNOTSUPP;
573 	}
574 }
575 
576 static bool is_rx_ring(struct bnxt *bp, int ring_num)
577 {
578 	return ring_num < bp->rx_nr_rings;
579 }
580 
581 static bool is_tx_ring(struct bnxt *bp, int ring_num)
582 {
583 	int tx_base = 0;
584 
585 	if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
586 		tx_base = bp->rx_nr_rings;
587 
588 	if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings))
589 		return true;
590 	return false;
591 }
592 
593 static void bnxt_get_ethtool_stats(struct net_device *dev,
594 				   struct ethtool_stats *stats, u64 *buf)
595 {
596 	struct bnxt_total_ring_err_stats ring_err_stats = {0};
597 	struct bnxt *bp = netdev_priv(dev);
598 	u64 *curr, *prev;
599 	u32 tpa_stats;
600 	u32 i, j = 0;
601 
602 	if (!bp->bnapi) {
603 		j += bnxt_get_num_ring_stats(bp);
604 		goto skip_ring_stats;
605 	}
606 
607 	tpa_stats = bnxt_get_num_tpa_ring_stats(bp);
608 	for (i = 0; i < bp->cp_nr_rings; i++) {
609 		struct bnxt_napi *bnapi = bp->bnapi[i];
610 		struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
611 		u64 *sw_stats = cpr->stats.sw_stats;
612 		u64 *sw;
613 		int k;
614 
615 		if (is_rx_ring(bp, i)) {
616 			for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++)
617 				buf[j] = sw_stats[k];
618 		}
619 		if (is_tx_ring(bp, i)) {
620 			k = NUM_RING_RX_HW_STATS;
621 			for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS;
622 			       j++, k++)
623 				buf[j] = sw_stats[k];
624 		}
625 		if (!tpa_stats || !is_rx_ring(bp, i))
626 			goto skip_tpa_ring_stats;
627 
628 		k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS;
629 		for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS +
630 			   tpa_stats; j++, k++)
631 			buf[j] = sw_stats[k];
632 
633 skip_tpa_ring_stats:
634 		sw = (u64 *)&cpr->sw_stats->rx;
635 		if (is_rx_ring(bp, i)) {
636 			for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++)
637 				buf[j] = sw[k];
638 		}
639 
640 		sw = (u64 *)&cpr->sw_stats->cmn;
641 		for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++)
642 			buf[j] = sw[k];
643 	}
644 
645 	bnxt_get_ring_err_stats(bp, &ring_err_stats);
646 
647 skip_ring_stats:
648 	curr = &ring_err_stats.rx_total_l4_csum_errors;
649 	prev = &bp->ring_err_stats_prev.rx_total_l4_csum_errors;
650 	for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++, j++, curr++, prev++)
651 		buf[j] = *curr + *prev;
652 
653 	if (bp->flags & BNXT_FLAG_PORT_STATS) {
654 		u64 *port_stats = bp->port_stats.sw_stats;
655 
656 		for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++)
657 			buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset);
658 	}
659 	if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
660 		u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats;
661 		u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats;
662 		u32 len;
663 
664 		len = min_t(u32, bp->fw_rx_stats_ext_size,
665 			    ARRAY_SIZE(bnxt_port_stats_ext_arr));
666 		for (i = 0; i < len; i++, j++) {
667 			buf[j] = *(rx_port_stats_ext +
668 				   bnxt_port_stats_ext_arr[i].offset);
669 		}
670 		len = min_t(u32, bp->fw_tx_stats_ext_size,
671 			    ARRAY_SIZE(bnxt_tx_port_stats_ext_arr));
672 		for (i = 0; i < len; i++, j++) {
673 			buf[j] = *(tx_port_stats_ext +
674 				   bnxt_tx_port_stats_ext_arr[i].offset);
675 		}
676 		if (bp->pri2cos_valid) {
677 			for (i = 0; i < 8; i++, j++) {
678 				long n = bnxt_rx_bytes_pri_arr[i].base_off +
679 					 bp->pri2cos_idx[i];
680 
681 				buf[j] = *(rx_port_stats_ext + n);
682 			}
683 			for (i = 0; i < 8; i++, j++) {
684 				long n = bnxt_rx_pkts_pri_arr[i].base_off +
685 					 bp->pri2cos_idx[i];
686 
687 				buf[j] = *(rx_port_stats_ext + n);
688 			}
689 			for (i = 0; i < 8; i++, j++) {
690 				long n = bnxt_tx_bytes_pri_arr[i].base_off +
691 					 bp->pri2cos_idx[i];
692 
693 				buf[j] = *(tx_port_stats_ext + n);
694 			}
695 			for (i = 0; i < 8; i++, j++) {
696 				long n = bnxt_tx_pkts_pri_arr[i].base_off +
697 					 bp->pri2cos_idx[i];
698 
699 				buf[j] = *(tx_port_stats_ext + n);
700 			}
701 		}
702 	}
703 }
704 
705 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
706 {
707 	struct bnxt *bp = netdev_priv(dev);
708 	static const char * const *str;
709 	u32 i, j, num_str;
710 
711 	switch (stringset) {
712 	case ETH_SS_STATS:
713 		for (i = 0; i < bp->cp_nr_rings; i++) {
714 			if (is_rx_ring(bp, i)) {
715 				num_str = NUM_RING_RX_HW_STATS;
716 				for (j = 0; j < num_str; j++) {
717 					sprintf(buf, "[%d]: %s", i,
718 						bnxt_ring_rx_stats_str[j]);
719 					buf += ETH_GSTRING_LEN;
720 				}
721 			}
722 			if (is_tx_ring(bp, i)) {
723 				num_str = NUM_RING_TX_HW_STATS;
724 				for (j = 0; j < num_str; j++) {
725 					sprintf(buf, "[%d]: %s", i,
726 						bnxt_ring_tx_stats_str[j]);
727 					buf += ETH_GSTRING_LEN;
728 				}
729 			}
730 			num_str = bnxt_get_num_tpa_ring_stats(bp);
731 			if (!num_str || !is_rx_ring(bp, i))
732 				goto skip_tpa_stats;
733 
734 			if (bp->max_tpa_v2)
735 				str = bnxt_ring_tpa2_stats_str;
736 			else
737 				str = bnxt_ring_tpa_stats_str;
738 
739 			for (j = 0; j < num_str; j++) {
740 				sprintf(buf, "[%d]: %s", i, str[j]);
741 				buf += ETH_GSTRING_LEN;
742 			}
743 skip_tpa_stats:
744 			if (is_rx_ring(bp, i)) {
745 				num_str = NUM_RING_RX_SW_STATS;
746 				for (j = 0; j < num_str; j++) {
747 					sprintf(buf, "[%d]: %s", i,
748 						bnxt_rx_sw_stats_str[j]);
749 					buf += ETH_GSTRING_LEN;
750 				}
751 			}
752 			num_str = NUM_RING_CMN_SW_STATS;
753 			for (j = 0; j < num_str; j++) {
754 				sprintf(buf, "[%d]: %s", i,
755 					bnxt_cmn_sw_stats_str[j]);
756 				buf += ETH_GSTRING_LEN;
757 			}
758 		}
759 		for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++) {
760 			strscpy(buf, bnxt_ring_err_stats_arr[i], ETH_GSTRING_LEN);
761 			buf += ETH_GSTRING_LEN;
762 		}
763 
764 		if (bp->flags & BNXT_FLAG_PORT_STATS) {
765 			for (i = 0; i < BNXT_NUM_PORT_STATS; i++) {
766 				strcpy(buf, bnxt_port_stats_arr[i].string);
767 				buf += ETH_GSTRING_LEN;
768 			}
769 		}
770 		if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
771 			u32 len;
772 
773 			len = min_t(u32, bp->fw_rx_stats_ext_size,
774 				    ARRAY_SIZE(bnxt_port_stats_ext_arr));
775 			for (i = 0; i < len; i++) {
776 				strcpy(buf, bnxt_port_stats_ext_arr[i].string);
777 				buf += ETH_GSTRING_LEN;
778 			}
779 			len = min_t(u32, bp->fw_tx_stats_ext_size,
780 				    ARRAY_SIZE(bnxt_tx_port_stats_ext_arr));
781 			for (i = 0; i < len; i++) {
782 				strcpy(buf,
783 				       bnxt_tx_port_stats_ext_arr[i].string);
784 				buf += ETH_GSTRING_LEN;
785 			}
786 			if (bp->pri2cos_valid) {
787 				for (i = 0; i < 8; i++) {
788 					strcpy(buf,
789 					       bnxt_rx_bytes_pri_arr[i].string);
790 					buf += ETH_GSTRING_LEN;
791 				}
792 				for (i = 0; i < 8; i++) {
793 					strcpy(buf,
794 					       bnxt_rx_pkts_pri_arr[i].string);
795 					buf += ETH_GSTRING_LEN;
796 				}
797 				for (i = 0; i < 8; i++) {
798 					strcpy(buf,
799 					       bnxt_tx_bytes_pri_arr[i].string);
800 					buf += ETH_GSTRING_LEN;
801 				}
802 				for (i = 0; i < 8; i++) {
803 					strcpy(buf,
804 					       bnxt_tx_pkts_pri_arr[i].string);
805 					buf += ETH_GSTRING_LEN;
806 				}
807 			}
808 		}
809 		break;
810 	case ETH_SS_TEST:
811 		if (bp->num_tests)
812 			memcpy(buf, bp->test_info->string,
813 			       bp->num_tests * ETH_GSTRING_LEN);
814 		break;
815 	default:
816 		netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n",
817 			   stringset);
818 		break;
819 	}
820 }
821 
822 static void bnxt_get_ringparam(struct net_device *dev,
823 			       struct ethtool_ringparam *ering,
824 			       struct kernel_ethtool_ringparam *kernel_ering,
825 			       struct netlink_ext_ack *extack)
826 {
827 	struct bnxt *bp = netdev_priv(dev);
828 
829 	if (bp->flags & BNXT_FLAG_AGG_RINGS) {
830 		ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA;
831 		ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT;
832 		kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_ENABLED;
833 	} else {
834 		ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT;
835 		ering->rx_jumbo_max_pending = 0;
836 		kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_DISABLED;
837 	}
838 	ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT;
839 
840 	ering->rx_pending = bp->rx_ring_size;
841 	ering->rx_jumbo_pending = bp->rx_agg_ring_size;
842 	ering->tx_pending = bp->tx_ring_size;
843 }
844 
845 static int bnxt_set_ringparam(struct net_device *dev,
846 			      struct ethtool_ringparam *ering,
847 			      struct kernel_ethtool_ringparam *kernel_ering,
848 			      struct netlink_ext_ack *extack)
849 {
850 	struct bnxt *bp = netdev_priv(dev);
851 
852 	if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) ||
853 	    (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) ||
854 	    (ering->tx_pending < BNXT_MIN_TX_DESC_CNT))
855 		return -EINVAL;
856 
857 	if (netif_running(dev))
858 		bnxt_close_nic(bp, false, false);
859 
860 	bp->rx_ring_size = ering->rx_pending;
861 	bp->tx_ring_size = ering->tx_pending;
862 	bnxt_set_ring_params(bp);
863 
864 	if (netif_running(dev))
865 		return bnxt_open_nic(bp, false, false);
866 
867 	return 0;
868 }
869 
870 static void bnxt_get_channels(struct net_device *dev,
871 			      struct ethtool_channels *channel)
872 {
873 	struct bnxt *bp = netdev_priv(dev);
874 	struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
875 	int max_rx_rings, max_tx_rings, tcs;
876 	int max_tx_sch_inputs, tx_grps;
877 
878 	/* Get the most up-to-date max_tx_sch_inputs. */
879 	if (netif_running(dev) && BNXT_NEW_RM(bp))
880 		bnxt_hwrm_func_resc_qcaps(bp, false);
881 	max_tx_sch_inputs = hw_resc->max_tx_sch_inputs;
882 
883 	bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true);
884 	if (max_tx_sch_inputs)
885 		max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
886 
887 	tcs = bp->num_tc;
888 	tx_grps = max(tcs, 1);
889 	if (bp->tx_nr_rings_xdp)
890 		tx_grps++;
891 	max_tx_rings /= tx_grps;
892 	channel->max_combined = min_t(int, max_rx_rings, max_tx_rings);
893 
894 	if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) {
895 		max_rx_rings = 0;
896 		max_tx_rings = 0;
897 	}
898 	if (max_tx_sch_inputs)
899 		max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
900 
901 	if (tcs > 1)
902 		max_tx_rings /= tcs;
903 
904 	channel->max_rx = max_rx_rings;
905 	channel->max_tx = max_tx_rings;
906 	channel->max_other = 0;
907 	if (bp->flags & BNXT_FLAG_SHARED_RINGS) {
908 		channel->combined_count = bp->rx_nr_rings;
909 		if (BNXT_CHIP_TYPE_NITRO_A0(bp))
910 			channel->combined_count--;
911 	} else {
912 		if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) {
913 			channel->rx_count = bp->rx_nr_rings;
914 			channel->tx_count = bp->tx_nr_rings_per_tc;
915 		}
916 	}
917 }
918 
919 static int bnxt_set_channels(struct net_device *dev,
920 			     struct ethtool_channels *channel)
921 {
922 	struct bnxt *bp = netdev_priv(dev);
923 	int req_tx_rings, req_rx_rings, tcs;
924 	bool sh = false;
925 	int tx_xdp = 0;
926 	int rc = 0;
927 	int tx_cp;
928 
929 	if (channel->other_count)
930 		return -EINVAL;
931 
932 	if (!channel->combined_count &&
933 	    (!channel->rx_count || !channel->tx_count))
934 		return -EINVAL;
935 
936 	if (channel->combined_count &&
937 	    (channel->rx_count || channel->tx_count))
938 		return -EINVAL;
939 
940 	if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count ||
941 					    channel->tx_count))
942 		return -EINVAL;
943 
944 	if (channel->combined_count)
945 		sh = true;
946 
947 	tcs = bp->num_tc;
948 
949 	req_tx_rings = sh ? channel->combined_count : channel->tx_count;
950 	req_rx_rings = sh ? channel->combined_count : channel->rx_count;
951 	if (bp->tx_nr_rings_xdp) {
952 		if (!sh) {
953 			netdev_err(dev, "Only combined mode supported when XDP is enabled.\n");
954 			return -EINVAL;
955 		}
956 		tx_xdp = req_rx_rings;
957 	}
958 	rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp);
959 	if (rc) {
960 		netdev_warn(dev, "Unable to allocate the requested rings\n");
961 		return rc;
962 	}
963 
964 	if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) !=
965 	    bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) &&
966 	    netif_is_rxfh_configured(dev)) {
967 		netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n");
968 		return -EINVAL;
969 	}
970 
971 	bnxt_clear_usr_fltrs(bp, true);
972 	if (BNXT_SUPPORTS_MULTI_RSS_CTX(bp))
973 		bnxt_clear_rss_ctxs(bp, false);
974 	if (netif_running(dev)) {
975 		if (BNXT_PF(bp)) {
976 			/* TODO CHIMP_FW: Send message to all VF's
977 			 * before PF unload
978 			 */
979 		}
980 		bnxt_close_nic(bp, true, false);
981 	}
982 
983 	if (sh) {
984 		bp->flags |= BNXT_FLAG_SHARED_RINGS;
985 		bp->rx_nr_rings = channel->combined_count;
986 		bp->tx_nr_rings_per_tc = channel->combined_count;
987 	} else {
988 		bp->flags &= ~BNXT_FLAG_SHARED_RINGS;
989 		bp->rx_nr_rings = channel->rx_count;
990 		bp->tx_nr_rings_per_tc = channel->tx_count;
991 	}
992 	bp->tx_nr_rings_xdp = tx_xdp;
993 	bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp;
994 	if (tcs > 1)
995 		bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp;
996 
997 	tx_cp = bnxt_num_tx_to_cp(bp, bp->tx_nr_rings);
998 	bp->cp_nr_rings = sh ? max_t(int, tx_cp, bp->rx_nr_rings) :
999 			       tx_cp + bp->rx_nr_rings;
1000 
1001 	/* After changing number of rx channels, update NTUPLE feature. */
1002 	netdev_update_features(dev);
1003 	if (netif_running(dev)) {
1004 		rc = bnxt_open_nic(bp, true, false);
1005 		if ((!rc) && BNXT_PF(bp)) {
1006 			/* TODO CHIMP_FW: Send message to all VF's
1007 			 * to renable
1008 			 */
1009 		}
1010 	} else {
1011 		rc = bnxt_reserve_rings(bp, true);
1012 	}
1013 
1014 	return rc;
1015 }
1016 
1017 static u32 bnxt_get_all_fltr_ids_rcu(struct bnxt *bp, struct hlist_head tbl[],
1018 				     int tbl_size, u32 *ids, u32 start,
1019 				     u32 id_cnt)
1020 {
1021 	int i, j = start;
1022 
1023 	if (j >= id_cnt)
1024 		return j;
1025 	for (i = 0; i < tbl_size; i++) {
1026 		struct hlist_head *head;
1027 		struct bnxt_filter_base *fltr;
1028 
1029 		head = &tbl[i];
1030 		hlist_for_each_entry_rcu(fltr, head, hash) {
1031 			if (!fltr->flags ||
1032 			    test_bit(BNXT_FLTR_FW_DELETED, &fltr->state))
1033 				continue;
1034 			ids[j++] = fltr->sw_id;
1035 			if (j == id_cnt)
1036 				return j;
1037 		}
1038 	}
1039 	return j;
1040 }
1041 
1042 static struct bnxt_filter_base *bnxt_get_one_fltr_rcu(struct bnxt *bp,
1043 						      struct hlist_head tbl[],
1044 						      int tbl_size, u32 id)
1045 {
1046 	int i;
1047 
1048 	for (i = 0; i < tbl_size; i++) {
1049 		struct hlist_head *head;
1050 		struct bnxt_filter_base *fltr;
1051 
1052 		head = &tbl[i];
1053 		hlist_for_each_entry_rcu(fltr, head, hash) {
1054 			if (fltr->flags && fltr->sw_id == id)
1055 				return fltr;
1056 		}
1057 	}
1058 	return NULL;
1059 }
1060 
1061 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd,
1062 			    u32 *rule_locs)
1063 {
1064 	u32 count;
1065 
1066 	cmd->data = bp->ntp_fltr_count;
1067 	rcu_read_lock();
1068 	count = bnxt_get_all_fltr_ids_rcu(bp, bp->l2_fltr_hash_tbl,
1069 					  BNXT_L2_FLTR_HASH_SIZE, rule_locs, 0,
1070 					  cmd->rule_cnt);
1071 	cmd->rule_cnt = bnxt_get_all_fltr_ids_rcu(bp, bp->ntp_fltr_hash_tbl,
1072 						  BNXT_NTP_FLTR_HASH_SIZE,
1073 						  rule_locs, count,
1074 						  cmd->rule_cnt);
1075 	rcu_read_unlock();
1076 
1077 	return 0;
1078 }
1079 
1080 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1081 {
1082 	struct ethtool_rx_flow_spec *fs =
1083 		(struct ethtool_rx_flow_spec *)&cmd->fs;
1084 	struct bnxt_filter_base *fltr_base;
1085 	struct bnxt_ntuple_filter *fltr;
1086 	struct bnxt_flow_masks *fmasks;
1087 	struct flow_keys *fkeys;
1088 	int rc = -EINVAL;
1089 
1090 	if (fs->location >= bp->max_fltr)
1091 		return rc;
1092 
1093 	rcu_read_lock();
1094 	fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl,
1095 					  BNXT_L2_FLTR_HASH_SIZE,
1096 					  fs->location);
1097 	if (fltr_base) {
1098 		struct ethhdr *h_ether = &fs->h_u.ether_spec;
1099 		struct ethhdr *m_ether = &fs->m_u.ether_spec;
1100 		struct bnxt_l2_filter *l2_fltr;
1101 		struct bnxt_l2_key *l2_key;
1102 
1103 		l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base);
1104 		l2_key = &l2_fltr->l2_key;
1105 		fs->flow_type = ETHER_FLOW;
1106 		ether_addr_copy(h_ether->h_dest, l2_key->dst_mac_addr);
1107 		eth_broadcast_addr(m_ether->h_dest);
1108 		if (l2_key->vlan) {
1109 			struct ethtool_flow_ext *m_ext = &fs->m_ext;
1110 			struct ethtool_flow_ext *h_ext = &fs->h_ext;
1111 
1112 			fs->flow_type |= FLOW_EXT;
1113 			m_ext->vlan_tci = htons(0xfff);
1114 			h_ext->vlan_tci = htons(l2_key->vlan);
1115 		}
1116 		if (fltr_base->flags & BNXT_ACT_RING_DST)
1117 			fs->ring_cookie = fltr_base->rxq;
1118 		if (fltr_base->flags & BNXT_ACT_FUNC_DST)
1119 			fs->ring_cookie = (u64)(fltr_base->vf_idx + 1) <<
1120 					  ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
1121 		rcu_read_unlock();
1122 		return 0;
1123 	}
1124 	fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl,
1125 					  BNXT_NTP_FLTR_HASH_SIZE,
1126 					  fs->location);
1127 	if (!fltr_base) {
1128 		rcu_read_unlock();
1129 		return rc;
1130 	}
1131 	fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base);
1132 
1133 	fkeys = &fltr->fkeys;
1134 	fmasks = &fltr->fmasks;
1135 	if (fkeys->basic.n_proto == htons(ETH_P_IP)) {
1136 		if (fkeys->basic.ip_proto == IPPROTO_ICMP ||
1137 		    fkeys->basic.ip_proto == IPPROTO_RAW) {
1138 			fs->flow_type = IP_USER_FLOW;
1139 			fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
1140 			if (fkeys->basic.ip_proto == IPPROTO_ICMP)
1141 				fs->h_u.usr_ip4_spec.proto = IPPROTO_ICMP;
1142 			else
1143 				fs->h_u.usr_ip4_spec.proto = IPPROTO_RAW;
1144 			fs->m_u.usr_ip4_spec.proto = BNXT_IP_PROTO_FULL_MASK;
1145 		} else if (fkeys->basic.ip_proto == IPPROTO_TCP) {
1146 			fs->flow_type = TCP_V4_FLOW;
1147 		} else if (fkeys->basic.ip_proto == IPPROTO_UDP) {
1148 			fs->flow_type = UDP_V4_FLOW;
1149 		} else {
1150 			goto fltr_err;
1151 		}
1152 
1153 		fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src;
1154 		fs->m_u.tcp_ip4_spec.ip4src = fmasks->addrs.v4addrs.src;
1155 		fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst;
1156 		fs->m_u.tcp_ip4_spec.ip4dst = fmasks->addrs.v4addrs.dst;
1157 		if (fs->flow_type == TCP_V4_FLOW ||
1158 		    fs->flow_type == UDP_V4_FLOW) {
1159 			fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src;
1160 			fs->m_u.tcp_ip4_spec.psrc = fmasks->ports.src;
1161 			fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst;
1162 			fs->m_u.tcp_ip4_spec.pdst = fmasks->ports.dst;
1163 		}
1164 	} else {
1165 		if (fkeys->basic.ip_proto == IPPROTO_ICMPV6 ||
1166 		    fkeys->basic.ip_proto == IPPROTO_RAW) {
1167 			fs->flow_type = IPV6_USER_FLOW;
1168 			if (fkeys->basic.ip_proto == IPPROTO_ICMPV6)
1169 				fs->h_u.usr_ip6_spec.l4_proto = IPPROTO_ICMPV6;
1170 			else
1171 				fs->h_u.usr_ip6_spec.l4_proto = IPPROTO_RAW;
1172 			fs->m_u.usr_ip6_spec.l4_proto = BNXT_IP_PROTO_FULL_MASK;
1173 		} else if (fkeys->basic.ip_proto == IPPROTO_TCP) {
1174 			fs->flow_type = TCP_V6_FLOW;
1175 		} else if (fkeys->basic.ip_proto == IPPROTO_UDP) {
1176 			fs->flow_type = UDP_V6_FLOW;
1177 		} else {
1178 			goto fltr_err;
1179 		}
1180 
1181 		*(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] =
1182 			fkeys->addrs.v6addrs.src;
1183 		*(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6src[0] =
1184 			fmasks->addrs.v6addrs.src;
1185 		*(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] =
1186 			fkeys->addrs.v6addrs.dst;
1187 		*(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6dst[0] =
1188 			fmasks->addrs.v6addrs.dst;
1189 		if (fs->flow_type == TCP_V6_FLOW ||
1190 		    fs->flow_type == UDP_V6_FLOW) {
1191 			fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src;
1192 			fs->m_u.tcp_ip6_spec.psrc = fmasks->ports.src;
1193 			fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst;
1194 			fs->m_u.tcp_ip6_spec.pdst = fmasks->ports.dst;
1195 		}
1196 	}
1197 
1198 	if (fltr->base.flags & BNXT_ACT_DROP)
1199 		fs->ring_cookie = RX_CLS_FLOW_DISC;
1200 	else
1201 		fs->ring_cookie = fltr->base.rxq;
1202 	rc = 0;
1203 
1204 fltr_err:
1205 	rcu_read_unlock();
1206 
1207 	return rc;
1208 }
1209 
1210 static struct bnxt_rss_ctx *bnxt_get_rss_ctx_from_index(struct bnxt *bp,
1211 							u32 index)
1212 {
1213 	struct bnxt_rss_ctx *rss_ctx, *tmp;
1214 
1215 	list_for_each_entry_safe(rss_ctx, tmp, &bp->rss_ctx_list, list)
1216 		if (rss_ctx->index == index)
1217 			return rss_ctx;
1218 	return NULL;
1219 }
1220 
1221 static int bnxt_alloc_rss_ctx_rss_table(struct bnxt *bp,
1222 					struct bnxt_rss_ctx *rss_ctx)
1223 {
1224 	int size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5);
1225 	struct bnxt_vnic_info *vnic = &rss_ctx->vnic;
1226 
1227 	vnic->rss_table_size = size + HW_HASH_KEY_SIZE;
1228 	vnic->rss_table = dma_alloc_coherent(&bp->pdev->dev,
1229 					     vnic->rss_table_size,
1230 					     &vnic->rss_table_dma_addr,
1231 					     GFP_KERNEL);
1232 	if (!vnic->rss_table)
1233 		return -ENOMEM;
1234 
1235 	vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
1236 	vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
1237 	return 0;
1238 }
1239 
1240 static int bnxt_add_l2_cls_rule(struct bnxt *bp,
1241 				struct ethtool_rx_flow_spec *fs)
1242 {
1243 	u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie);
1244 	u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie);
1245 	struct ethhdr *h_ether = &fs->h_u.ether_spec;
1246 	struct ethhdr *m_ether = &fs->m_u.ether_spec;
1247 	struct bnxt_l2_filter *fltr;
1248 	struct bnxt_l2_key key;
1249 	u16 vnic_id;
1250 	u8 flags;
1251 	int rc;
1252 
1253 	if (BNXT_CHIP_P5_PLUS(bp))
1254 		return -EOPNOTSUPP;
1255 
1256 	if (!is_broadcast_ether_addr(m_ether->h_dest))
1257 		return -EINVAL;
1258 	ether_addr_copy(key.dst_mac_addr, h_ether->h_dest);
1259 	key.vlan = 0;
1260 	if (fs->flow_type & FLOW_EXT) {
1261 		struct ethtool_flow_ext *m_ext = &fs->m_ext;
1262 		struct ethtool_flow_ext *h_ext = &fs->h_ext;
1263 
1264 		if (m_ext->vlan_tci != htons(0xfff) || !h_ext->vlan_tci)
1265 			return -EINVAL;
1266 		key.vlan = ntohs(h_ext->vlan_tci);
1267 	}
1268 
1269 	if (vf) {
1270 		flags = BNXT_ACT_FUNC_DST;
1271 		vnic_id = 0xffff;
1272 		vf--;
1273 	} else {
1274 		flags = BNXT_ACT_RING_DST;
1275 		vnic_id = bp->vnic_info[ring + 1].fw_vnic_id;
1276 	}
1277 	fltr = bnxt_alloc_new_l2_filter(bp, &key, flags);
1278 	if (IS_ERR(fltr))
1279 		return PTR_ERR(fltr);
1280 
1281 	fltr->base.fw_vnic_id = vnic_id;
1282 	fltr->base.rxq = ring;
1283 	fltr->base.vf_idx = vf;
1284 	rc = bnxt_hwrm_l2_filter_alloc(bp, fltr);
1285 	if (rc)
1286 		bnxt_del_l2_filter(bp, fltr);
1287 	else
1288 		fs->location = fltr->base.sw_id;
1289 	return rc;
1290 }
1291 
1292 static bool bnxt_verify_ntuple_ip4_flow(struct ethtool_usrip4_spec *ip_spec,
1293 					struct ethtool_usrip4_spec *ip_mask)
1294 {
1295 	if (ip_mask->l4_4_bytes || ip_mask->tos ||
1296 	    ip_spec->ip_ver != ETH_RX_NFC_IP4 ||
1297 	    ip_mask->proto != BNXT_IP_PROTO_FULL_MASK ||
1298 	    (ip_spec->proto != IPPROTO_RAW && ip_spec->proto != IPPROTO_ICMP))
1299 		return false;
1300 	return true;
1301 }
1302 
1303 static bool bnxt_verify_ntuple_ip6_flow(struct ethtool_usrip6_spec *ip_spec,
1304 					struct ethtool_usrip6_spec *ip_mask)
1305 {
1306 	if (ip_mask->l4_4_bytes || ip_mask->tclass ||
1307 	    ip_mask->l4_proto != BNXT_IP_PROTO_FULL_MASK ||
1308 	    (ip_spec->l4_proto != IPPROTO_RAW &&
1309 	     ip_spec->l4_proto != IPPROTO_ICMPV6))
1310 		return false;
1311 	return true;
1312 }
1313 
1314 static int bnxt_add_ntuple_cls_rule(struct bnxt *bp,
1315 				    struct ethtool_rxnfc *cmd)
1316 {
1317 	struct ethtool_rx_flow_spec *fs = &cmd->fs;
1318 	struct bnxt_ntuple_filter *new_fltr, *fltr;
1319 	u32 flow_type = fs->flow_type & 0xff;
1320 	struct bnxt_l2_filter *l2_fltr;
1321 	struct bnxt_flow_masks *fmasks;
1322 	struct flow_keys *fkeys;
1323 	u32 idx, ring;
1324 	int rc;
1325 	u8 vf;
1326 
1327 	if (!bp->vnic_info)
1328 		return -EAGAIN;
1329 
1330 	vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie);
1331 	ring = ethtool_get_flow_spec_ring(fs->ring_cookie);
1332 	if ((fs->flow_type & (FLOW_MAC_EXT | FLOW_EXT)) || vf)
1333 		return -EOPNOTSUPP;
1334 
1335 	if (flow_type == IP_USER_FLOW) {
1336 		if (!bnxt_verify_ntuple_ip4_flow(&fs->h_u.usr_ip4_spec,
1337 						 &fs->m_u.usr_ip4_spec))
1338 			return -EOPNOTSUPP;
1339 	}
1340 
1341 	if (flow_type == IPV6_USER_FLOW) {
1342 		if (!bnxt_verify_ntuple_ip6_flow(&fs->h_u.usr_ip6_spec,
1343 						 &fs->m_u.usr_ip6_spec))
1344 			return -EOPNOTSUPP;
1345 	}
1346 
1347 	new_fltr = kzalloc(sizeof(*new_fltr), GFP_KERNEL);
1348 	if (!new_fltr)
1349 		return -ENOMEM;
1350 
1351 	l2_fltr = bp->vnic_info[BNXT_VNIC_DEFAULT].l2_filters[0];
1352 	atomic_inc(&l2_fltr->refcnt);
1353 	new_fltr->l2_fltr = l2_fltr;
1354 	fmasks = &new_fltr->fmasks;
1355 	fkeys = &new_fltr->fkeys;
1356 
1357 	rc = -EOPNOTSUPP;
1358 	switch (flow_type) {
1359 	case IP_USER_FLOW: {
1360 		struct ethtool_usrip4_spec *ip_spec = &fs->h_u.usr_ip4_spec;
1361 		struct ethtool_usrip4_spec *ip_mask = &fs->m_u.usr_ip4_spec;
1362 
1363 		fkeys->basic.ip_proto = ip_spec->proto;
1364 		fkeys->basic.n_proto = htons(ETH_P_IP);
1365 		fkeys->addrs.v4addrs.src = ip_spec->ip4src;
1366 		fmasks->addrs.v4addrs.src = ip_mask->ip4src;
1367 		fkeys->addrs.v4addrs.dst = ip_spec->ip4dst;
1368 		fmasks->addrs.v4addrs.dst = ip_mask->ip4dst;
1369 		break;
1370 	}
1371 	case TCP_V4_FLOW:
1372 	case UDP_V4_FLOW: {
1373 		struct ethtool_tcpip4_spec *ip_spec = &fs->h_u.tcp_ip4_spec;
1374 		struct ethtool_tcpip4_spec *ip_mask = &fs->m_u.tcp_ip4_spec;
1375 
1376 		fkeys->basic.ip_proto = IPPROTO_TCP;
1377 		if (flow_type == UDP_V4_FLOW)
1378 			fkeys->basic.ip_proto = IPPROTO_UDP;
1379 		fkeys->basic.n_proto = htons(ETH_P_IP);
1380 		fkeys->addrs.v4addrs.src = ip_spec->ip4src;
1381 		fmasks->addrs.v4addrs.src = ip_mask->ip4src;
1382 		fkeys->addrs.v4addrs.dst = ip_spec->ip4dst;
1383 		fmasks->addrs.v4addrs.dst = ip_mask->ip4dst;
1384 		fkeys->ports.src = ip_spec->psrc;
1385 		fmasks->ports.src = ip_mask->psrc;
1386 		fkeys->ports.dst = ip_spec->pdst;
1387 		fmasks->ports.dst = ip_mask->pdst;
1388 		break;
1389 	}
1390 	case IPV6_USER_FLOW: {
1391 		struct ethtool_usrip6_spec *ip_spec = &fs->h_u.usr_ip6_spec;
1392 		struct ethtool_usrip6_spec *ip_mask = &fs->m_u.usr_ip6_spec;
1393 
1394 		fkeys->basic.ip_proto = ip_spec->l4_proto;
1395 		fkeys->basic.n_proto = htons(ETH_P_IPV6);
1396 		fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src;
1397 		fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src;
1398 		fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst;
1399 		fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst;
1400 		break;
1401 	}
1402 	case TCP_V6_FLOW:
1403 	case UDP_V6_FLOW: {
1404 		struct ethtool_tcpip6_spec *ip_spec = &fs->h_u.tcp_ip6_spec;
1405 		struct ethtool_tcpip6_spec *ip_mask = &fs->m_u.tcp_ip6_spec;
1406 
1407 		fkeys->basic.ip_proto = IPPROTO_TCP;
1408 		if (flow_type == UDP_V6_FLOW)
1409 			fkeys->basic.ip_proto = IPPROTO_UDP;
1410 		fkeys->basic.n_proto = htons(ETH_P_IPV6);
1411 
1412 		fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src;
1413 		fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src;
1414 		fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst;
1415 		fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst;
1416 		fkeys->ports.src = ip_spec->psrc;
1417 		fmasks->ports.src = ip_mask->psrc;
1418 		fkeys->ports.dst = ip_spec->pdst;
1419 		fmasks->ports.dst = ip_mask->pdst;
1420 		break;
1421 	}
1422 	default:
1423 		rc = -EOPNOTSUPP;
1424 		goto ntuple_err;
1425 	}
1426 	if (!memcmp(&BNXT_FLOW_MASK_NONE, fmasks, sizeof(*fmasks)))
1427 		goto ntuple_err;
1428 
1429 	idx = bnxt_get_ntp_filter_idx(bp, fkeys, NULL);
1430 	rcu_read_lock();
1431 	fltr = bnxt_lookup_ntp_filter_from_idx(bp, new_fltr, idx);
1432 	if (fltr) {
1433 		rcu_read_unlock();
1434 		rc = -EEXIST;
1435 		goto ntuple_err;
1436 	}
1437 	rcu_read_unlock();
1438 
1439 	new_fltr->base.flags = BNXT_ACT_NO_AGING;
1440 	if (fs->flow_type & FLOW_RSS) {
1441 		struct bnxt_rss_ctx *rss_ctx;
1442 
1443 		new_fltr->base.fw_vnic_id = 0;
1444 		new_fltr->base.flags |= BNXT_ACT_RSS_CTX;
1445 		rss_ctx = bnxt_get_rss_ctx_from_index(bp, cmd->rss_context);
1446 		if (rss_ctx) {
1447 			new_fltr->base.fw_vnic_id = rss_ctx->index;
1448 		} else {
1449 			rc = -EINVAL;
1450 			goto ntuple_err;
1451 		}
1452 	}
1453 	if (fs->ring_cookie == RX_CLS_FLOW_DISC)
1454 		new_fltr->base.flags |= BNXT_ACT_DROP;
1455 	else
1456 		new_fltr->base.rxq = ring;
1457 	__set_bit(BNXT_FLTR_VALID, &new_fltr->base.state);
1458 	rc = bnxt_insert_ntp_filter(bp, new_fltr, idx);
1459 	if (!rc) {
1460 		rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, new_fltr);
1461 		if (rc) {
1462 			bnxt_del_ntp_filter(bp, new_fltr);
1463 			return rc;
1464 		}
1465 		fs->location = new_fltr->base.sw_id;
1466 		return 0;
1467 	}
1468 
1469 ntuple_err:
1470 	atomic_dec(&l2_fltr->refcnt);
1471 	kfree(new_fltr);
1472 	return rc;
1473 }
1474 
1475 static int bnxt_srxclsrlins(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1476 {
1477 	struct ethtool_rx_flow_spec *fs = &cmd->fs;
1478 	u32 ring, flow_type;
1479 	int rc;
1480 	u8 vf;
1481 
1482 	if (!netif_running(bp->dev))
1483 		return -EAGAIN;
1484 	if (!(bp->flags & BNXT_FLAG_RFS))
1485 		return -EPERM;
1486 	if (fs->location != RX_CLS_LOC_ANY)
1487 		return -EINVAL;
1488 
1489 	flow_type = fs->flow_type;
1490 	if ((flow_type == IP_USER_FLOW ||
1491 	     flow_type == IPV6_USER_FLOW) &&
1492 	    !(bp->fw_cap & BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO))
1493 		return -EOPNOTSUPP;
1494 	if (flow_type & FLOW_MAC_EXT)
1495 		return -EINVAL;
1496 	flow_type &= ~FLOW_EXT;
1497 
1498 	if (fs->ring_cookie == RX_CLS_FLOW_DISC && flow_type != ETHER_FLOW)
1499 		return bnxt_add_ntuple_cls_rule(bp, cmd);
1500 
1501 	ring = ethtool_get_flow_spec_ring(fs->ring_cookie);
1502 	vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie);
1503 	if (BNXT_VF(bp) && vf)
1504 		return -EINVAL;
1505 	if (BNXT_PF(bp) && vf > bp->pf.active_vfs)
1506 		return -EINVAL;
1507 	if (!vf && ring >= bp->rx_nr_rings)
1508 		return -EINVAL;
1509 
1510 	if (flow_type == ETHER_FLOW)
1511 		rc = bnxt_add_l2_cls_rule(bp, fs);
1512 	else
1513 		rc = bnxt_add_ntuple_cls_rule(bp, cmd);
1514 	return rc;
1515 }
1516 
1517 static int bnxt_srxclsrldel(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1518 {
1519 	struct ethtool_rx_flow_spec *fs = &cmd->fs;
1520 	struct bnxt_filter_base *fltr_base;
1521 	struct bnxt_ntuple_filter *fltr;
1522 	u32 id = fs->location;
1523 
1524 	rcu_read_lock();
1525 	fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl,
1526 					  BNXT_L2_FLTR_HASH_SIZE, id);
1527 	if (fltr_base) {
1528 		struct bnxt_l2_filter *l2_fltr;
1529 
1530 		l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base);
1531 		rcu_read_unlock();
1532 		bnxt_hwrm_l2_filter_free(bp, l2_fltr);
1533 		bnxt_del_l2_filter(bp, l2_fltr);
1534 		return 0;
1535 	}
1536 	fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl,
1537 					  BNXT_NTP_FLTR_HASH_SIZE, id);
1538 	if (!fltr_base) {
1539 		rcu_read_unlock();
1540 		return -ENOENT;
1541 	}
1542 
1543 	fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base);
1544 	if (!(fltr->base.flags & BNXT_ACT_NO_AGING)) {
1545 		rcu_read_unlock();
1546 		return -EINVAL;
1547 	}
1548 	rcu_read_unlock();
1549 	bnxt_hwrm_cfa_ntuple_filter_free(bp, fltr);
1550 	bnxt_del_ntp_filter(bp, fltr);
1551 	return 0;
1552 }
1553 
1554 static u64 get_ethtool_ipv4_rss(struct bnxt *bp)
1555 {
1556 	if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4)
1557 		return RXH_IP_SRC | RXH_IP_DST;
1558 	return 0;
1559 }
1560 
1561 static u64 get_ethtool_ipv6_rss(struct bnxt *bp)
1562 {
1563 	if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6)
1564 		return RXH_IP_SRC | RXH_IP_DST;
1565 	return 0;
1566 }
1567 
1568 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1569 {
1570 	cmd->data = 0;
1571 	switch (cmd->flow_type) {
1572 	case TCP_V4_FLOW:
1573 		if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4)
1574 			cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1575 				     RXH_L4_B_0_1 | RXH_L4_B_2_3;
1576 		cmd->data |= get_ethtool_ipv4_rss(bp);
1577 		break;
1578 	case UDP_V4_FLOW:
1579 		if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4)
1580 			cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1581 				     RXH_L4_B_0_1 | RXH_L4_B_2_3;
1582 		fallthrough;
1583 	case AH_ESP_V4_FLOW:
1584 		if (bp->rss_hash_cfg &
1585 		    (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 |
1586 		     VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4))
1587 			cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1588 				     RXH_L4_B_0_1 | RXH_L4_B_2_3;
1589 		fallthrough;
1590 	case SCTP_V4_FLOW:
1591 	case AH_V4_FLOW:
1592 	case ESP_V4_FLOW:
1593 	case IPV4_FLOW:
1594 		cmd->data |= get_ethtool_ipv4_rss(bp);
1595 		break;
1596 
1597 	case TCP_V6_FLOW:
1598 		if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6)
1599 			cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1600 				     RXH_L4_B_0_1 | RXH_L4_B_2_3;
1601 		cmd->data |= get_ethtool_ipv6_rss(bp);
1602 		break;
1603 	case UDP_V6_FLOW:
1604 		if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6)
1605 			cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1606 				     RXH_L4_B_0_1 | RXH_L4_B_2_3;
1607 		fallthrough;
1608 	case AH_ESP_V6_FLOW:
1609 		if (bp->rss_hash_cfg &
1610 		    (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 |
1611 		     VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6))
1612 			cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1613 				     RXH_L4_B_0_1 | RXH_L4_B_2_3;
1614 		fallthrough;
1615 	case SCTP_V6_FLOW:
1616 	case AH_V6_FLOW:
1617 	case ESP_V6_FLOW:
1618 	case IPV6_FLOW:
1619 		cmd->data |= get_ethtool_ipv6_rss(bp);
1620 		break;
1621 	}
1622 	return 0;
1623 }
1624 
1625 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)
1626 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST)
1627 
1628 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1629 {
1630 	u32 rss_hash_cfg = bp->rss_hash_cfg;
1631 	int tuple, rc = 0;
1632 
1633 	if (cmd->data == RXH_4TUPLE)
1634 		tuple = 4;
1635 	else if (cmd->data == RXH_2TUPLE)
1636 		tuple = 2;
1637 	else if (!cmd->data)
1638 		tuple = 0;
1639 	else
1640 		return -EINVAL;
1641 
1642 	if (cmd->flow_type == TCP_V4_FLOW) {
1643 		rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
1644 		if (tuple == 4)
1645 			rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
1646 	} else if (cmd->flow_type == UDP_V4_FLOW) {
1647 		if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP))
1648 			return -EINVAL;
1649 		rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
1650 		if (tuple == 4)
1651 			rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
1652 	} else if (cmd->flow_type == TCP_V6_FLOW) {
1653 		rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
1654 		if (tuple == 4)
1655 			rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
1656 	} else if (cmd->flow_type == UDP_V6_FLOW) {
1657 		if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP))
1658 			return -EINVAL;
1659 		rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
1660 		if (tuple == 4)
1661 			rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
1662 	} else if (cmd->flow_type == AH_ESP_V4_FLOW) {
1663 		if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V4_RSS_CAP) ||
1664 				   !(bp->rss_cap & BNXT_RSS_CAP_ESP_V4_RSS_CAP)))
1665 			return -EINVAL;
1666 		rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 |
1667 				  VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4);
1668 		if (tuple == 4)
1669 			rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 |
1670 					VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4;
1671 	} else if (cmd->flow_type == AH_ESP_V6_FLOW) {
1672 		if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V6_RSS_CAP) ||
1673 				   !(bp->rss_cap & BNXT_RSS_CAP_ESP_V6_RSS_CAP)))
1674 			return -EINVAL;
1675 		rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 |
1676 				  VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6);
1677 		if (tuple == 4)
1678 			rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 |
1679 					VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6;
1680 	} else if (tuple == 4) {
1681 		return -EINVAL;
1682 	}
1683 
1684 	switch (cmd->flow_type) {
1685 	case TCP_V4_FLOW:
1686 	case UDP_V4_FLOW:
1687 	case SCTP_V4_FLOW:
1688 	case AH_ESP_V4_FLOW:
1689 	case AH_V4_FLOW:
1690 	case ESP_V4_FLOW:
1691 	case IPV4_FLOW:
1692 		if (tuple == 2)
1693 			rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
1694 		else if (!tuple)
1695 			rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
1696 		break;
1697 
1698 	case TCP_V6_FLOW:
1699 	case UDP_V6_FLOW:
1700 	case SCTP_V6_FLOW:
1701 	case AH_ESP_V6_FLOW:
1702 	case AH_V6_FLOW:
1703 	case ESP_V6_FLOW:
1704 	case IPV6_FLOW:
1705 		if (tuple == 2)
1706 			rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6;
1707 		else if (!tuple)
1708 			rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6;
1709 		break;
1710 	}
1711 
1712 	if (bp->rss_hash_cfg == rss_hash_cfg)
1713 		return 0;
1714 
1715 	if (bp->rss_cap & BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA)
1716 		bp->rss_hash_delta = bp->rss_hash_cfg ^ rss_hash_cfg;
1717 	bp->rss_hash_cfg = rss_hash_cfg;
1718 	if (netif_running(bp->dev)) {
1719 		bnxt_close_nic(bp, false, false);
1720 		rc = bnxt_open_nic(bp, false, false);
1721 	}
1722 	return rc;
1723 }
1724 
1725 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1726 			  u32 *rule_locs)
1727 {
1728 	struct bnxt *bp = netdev_priv(dev);
1729 	int rc = 0;
1730 
1731 	switch (cmd->cmd) {
1732 	case ETHTOOL_GRXRINGS:
1733 		cmd->data = bp->rx_nr_rings;
1734 		break;
1735 
1736 	case ETHTOOL_GRXCLSRLCNT:
1737 		cmd->rule_cnt = bp->ntp_fltr_count;
1738 		cmd->data = bp->max_fltr | RX_CLS_LOC_SPECIAL;
1739 		break;
1740 
1741 	case ETHTOOL_GRXCLSRLALL:
1742 		rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs);
1743 		break;
1744 
1745 	case ETHTOOL_GRXCLSRULE:
1746 		rc = bnxt_grxclsrule(bp, cmd);
1747 		break;
1748 
1749 	case ETHTOOL_GRXFH:
1750 		rc = bnxt_grxfh(bp, cmd);
1751 		break;
1752 
1753 	default:
1754 		rc = -EOPNOTSUPP;
1755 		break;
1756 	}
1757 
1758 	return rc;
1759 }
1760 
1761 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1762 {
1763 	struct bnxt *bp = netdev_priv(dev);
1764 	int rc;
1765 
1766 	switch (cmd->cmd) {
1767 	case ETHTOOL_SRXFH:
1768 		rc = bnxt_srxfh(bp, cmd);
1769 		break;
1770 
1771 	case ETHTOOL_SRXCLSRLINS:
1772 		rc = bnxt_srxclsrlins(bp, cmd);
1773 		break;
1774 
1775 	case ETHTOOL_SRXCLSRLDEL:
1776 		rc = bnxt_srxclsrldel(bp, cmd);
1777 		break;
1778 
1779 	default:
1780 		rc = -EOPNOTSUPP;
1781 		break;
1782 	}
1783 	return rc;
1784 }
1785 
1786 u32 bnxt_get_rxfh_indir_size(struct net_device *dev)
1787 {
1788 	struct bnxt *bp = netdev_priv(dev);
1789 
1790 	if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
1791 		return bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) *
1792 		       BNXT_RSS_TABLE_ENTRIES_P5;
1793 	return HW_HASH_INDEX_SIZE;
1794 }
1795 
1796 static u32 bnxt_get_rxfh_key_size(struct net_device *dev)
1797 {
1798 	return HW_HASH_KEY_SIZE;
1799 }
1800 
1801 static int bnxt_get_rxfh(struct net_device *dev,
1802 			 struct ethtool_rxfh_param *rxfh)
1803 {
1804 	u32 rss_context = rxfh->rss_context;
1805 	struct bnxt_rss_ctx *rss_ctx = NULL;
1806 	struct bnxt *bp = netdev_priv(dev);
1807 	u16 *indir_tbl = bp->rss_indir_tbl;
1808 	struct bnxt_vnic_info *vnic;
1809 	u32 i, tbl_size;
1810 
1811 	rxfh->hfunc = ETH_RSS_HASH_TOP;
1812 
1813 	if (!bp->vnic_info)
1814 		return 0;
1815 
1816 	vnic = &bp->vnic_info[BNXT_VNIC_DEFAULT];
1817 	if (rxfh->rss_context) {
1818 		rss_ctx = bnxt_get_rss_ctx_from_index(bp, rss_context);
1819 		if (!rss_ctx)
1820 			return -EINVAL;
1821 		indir_tbl = rss_ctx->rss_indir_tbl;
1822 		vnic = &rss_ctx->vnic;
1823 	}
1824 
1825 	if (rxfh->indir && indir_tbl) {
1826 		tbl_size = bnxt_get_rxfh_indir_size(dev);
1827 		for (i = 0; i < tbl_size; i++)
1828 			rxfh->indir[i] = indir_tbl[i];
1829 	}
1830 
1831 	if (rxfh->key && vnic->rss_hash_key)
1832 		memcpy(rxfh->key, vnic->rss_hash_key, HW_HASH_KEY_SIZE);
1833 
1834 	return 0;
1835 }
1836 
1837 static void bnxt_modify_rss(struct bnxt *bp, struct bnxt_rss_ctx *rss_ctx,
1838 			    struct ethtool_rxfh_param *rxfh)
1839 {
1840 	if (rxfh->key) {
1841 		if (rss_ctx) {
1842 			memcpy(rss_ctx->vnic.rss_hash_key, rxfh->key,
1843 			       HW_HASH_KEY_SIZE);
1844 		} else {
1845 			memcpy(bp->rss_hash_key, rxfh->key, HW_HASH_KEY_SIZE);
1846 			bp->rss_hash_key_updated = true;
1847 		}
1848 	}
1849 	if (rxfh->indir) {
1850 		u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(bp->dev);
1851 		u16 *indir_tbl = bp->rss_indir_tbl;
1852 
1853 		if (rss_ctx)
1854 			indir_tbl = rss_ctx->rss_indir_tbl;
1855 		for (i = 0; i < tbl_size; i++)
1856 			indir_tbl[i] = rxfh->indir[i];
1857 		pad = bp->rss_indir_tbl_entries - tbl_size;
1858 		if (pad)
1859 			memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16));
1860 	}
1861 }
1862 
1863 static int bnxt_set_rxfh_context(struct bnxt *bp,
1864 				 struct ethtool_rxfh_param *rxfh,
1865 				 struct netlink_ext_ack *extack)
1866 {
1867 	u32 *rss_context = &rxfh->rss_context;
1868 	struct bnxt_rss_ctx *rss_ctx;
1869 	struct bnxt_vnic_info *vnic;
1870 	bool modify = false;
1871 	int bit_id;
1872 	int rc;
1873 
1874 	if (!BNXT_SUPPORTS_MULTI_RSS_CTX(bp)) {
1875 		NL_SET_ERR_MSG_MOD(extack, "RSS contexts not supported");
1876 		return -EOPNOTSUPP;
1877 	}
1878 
1879 	if (!netif_running(bp->dev)) {
1880 		NL_SET_ERR_MSG_MOD(extack, "Unable to set RSS contexts when interface is down");
1881 		return -EAGAIN;
1882 	}
1883 
1884 	if (*rss_context != ETH_RXFH_CONTEXT_ALLOC) {
1885 		rss_ctx = bnxt_get_rss_ctx_from_index(bp, *rss_context);
1886 		if (!rss_ctx) {
1887 			NL_SET_ERR_MSG_FMT_MOD(extack, "RSS context %u not found",
1888 					       *rss_context);
1889 			return -EINVAL;
1890 		}
1891 		if (*rss_context && rxfh->rss_delete) {
1892 			bnxt_del_one_rss_ctx(bp, rss_ctx, true);
1893 			return 0;
1894 		}
1895 		modify = true;
1896 		vnic = &rss_ctx->vnic;
1897 		goto modify_context;
1898 	}
1899 
1900 	if (bp->num_rss_ctx >= BNXT_MAX_ETH_RSS_CTX) {
1901 		NL_SET_ERR_MSG_FMT_MOD(extack, "Out of RSS contexts, maximum %u",
1902 				       BNXT_MAX_ETH_RSS_CTX);
1903 		return -EINVAL;
1904 	}
1905 
1906 	if (!bnxt_rfs_capable(bp, true)) {
1907 		NL_SET_ERR_MSG_MOD(extack, "Out hardware resources");
1908 		return -ENOMEM;
1909 	}
1910 
1911 	rss_ctx = bnxt_alloc_rss_ctx(bp);
1912 	if (!rss_ctx)
1913 		return -ENOMEM;
1914 
1915 	vnic = &rss_ctx->vnic;
1916 	vnic->flags |= BNXT_VNIC_RSSCTX_FLAG;
1917 	vnic->vnic_id = BNXT_VNIC_ID_INVALID;
1918 	rc = bnxt_alloc_rss_ctx_rss_table(bp, rss_ctx);
1919 	if (rc)
1920 		goto out;
1921 
1922 	rc = bnxt_alloc_rss_indir_tbl(bp, rss_ctx);
1923 	if (rc)
1924 		goto out;
1925 
1926 	bnxt_set_dflt_rss_indir_tbl(bp, rss_ctx);
1927 	memcpy(vnic->rss_hash_key, bp->rss_hash_key, HW_HASH_KEY_SIZE);
1928 
1929 	rc = bnxt_hwrm_vnic_alloc(bp, vnic, 0, bp->rx_nr_rings);
1930 	if (rc) {
1931 		NL_SET_ERR_MSG_MOD(extack, "Unable to allocate VNIC");
1932 		goto out;
1933 	}
1934 
1935 	rc = bnxt_hwrm_vnic_set_tpa(bp, vnic, bp->flags & BNXT_FLAG_TPA);
1936 	if (rc) {
1937 		NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA");
1938 		goto out;
1939 	}
1940 modify_context:
1941 	bnxt_modify_rss(bp, rss_ctx, rxfh);
1942 
1943 	if (modify)
1944 		return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
1945 
1946 	rc = __bnxt_setup_vnic_p5(bp, vnic);
1947 	if (rc) {
1948 		NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA");
1949 		goto out;
1950 	}
1951 
1952 	bit_id = bitmap_find_free_region(bp->rss_ctx_bmap,
1953 					 BNXT_RSS_CTX_BMAP_LEN, 0);
1954 	if (bit_id < 0) {
1955 		rc = -ENOMEM;
1956 		goto out;
1957 	}
1958 	rss_ctx->index = (u16)bit_id;
1959 	*rss_context = rss_ctx->index;
1960 
1961 	return 0;
1962 out:
1963 	bnxt_del_one_rss_ctx(bp, rss_ctx, true);
1964 	return rc;
1965 }
1966 
1967 static int bnxt_set_rxfh(struct net_device *dev,
1968 			 struct ethtool_rxfh_param *rxfh,
1969 			 struct netlink_ext_ack *extack)
1970 {
1971 	struct bnxt *bp = netdev_priv(dev);
1972 	int rc = 0;
1973 
1974 	if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP)
1975 		return -EOPNOTSUPP;
1976 
1977 	if (rxfh->rss_context)
1978 		return bnxt_set_rxfh_context(bp, rxfh, extack);
1979 
1980 	bnxt_modify_rss(bp, NULL, rxfh);
1981 
1982 	bnxt_clear_usr_fltrs(bp, false);
1983 	if (netif_running(bp->dev)) {
1984 		bnxt_close_nic(bp, false, false);
1985 		rc = bnxt_open_nic(bp, false, false);
1986 	}
1987 	return rc;
1988 }
1989 
1990 static void bnxt_get_drvinfo(struct net_device *dev,
1991 			     struct ethtool_drvinfo *info)
1992 {
1993 	struct bnxt *bp = netdev_priv(dev);
1994 
1995 	strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1996 	strscpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version));
1997 	strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1998 	info->n_stats = bnxt_get_num_stats(bp);
1999 	info->testinfo_len = bp->num_tests;
2000 	/* TODO CHIMP_FW: eeprom dump details */
2001 	info->eedump_len = 0;
2002 	/* TODO CHIMP FW: reg dump details */
2003 	info->regdump_len = 0;
2004 }
2005 
2006 static int bnxt_get_regs_len(struct net_device *dev)
2007 {
2008 	struct bnxt *bp = netdev_priv(dev);
2009 	int reg_len;
2010 
2011 	if (!BNXT_PF(bp))
2012 		return -EOPNOTSUPP;
2013 
2014 	reg_len = BNXT_PXP_REG_LEN;
2015 
2016 	if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)
2017 		reg_len += sizeof(struct pcie_ctx_hw_stats);
2018 
2019 	return reg_len;
2020 }
2021 
2022 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2023 			  void *_p)
2024 {
2025 	struct pcie_ctx_hw_stats *hw_pcie_stats;
2026 	struct hwrm_pcie_qstats_input *req;
2027 	struct bnxt *bp = netdev_priv(dev);
2028 	dma_addr_t hw_pcie_stats_addr;
2029 	int rc;
2030 
2031 	regs->version = 0;
2032 	bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p);
2033 
2034 	if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED))
2035 		return;
2036 
2037 	if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS))
2038 		return;
2039 
2040 	hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats),
2041 					   &hw_pcie_stats_addr);
2042 	if (!hw_pcie_stats) {
2043 		hwrm_req_drop(bp, req);
2044 		return;
2045 	}
2046 
2047 	regs->version = 1;
2048 	hwrm_req_hold(bp, req); /* hold on to slice */
2049 	req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats));
2050 	req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr);
2051 	rc = hwrm_req_send(bp, req);
2052 	if (!rc) {
2053 		__le64 *src = (__le64 *)hw_pcie_stats;
2054 		u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN);
2055 		int i;
2056 
2057 		for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++)
2058 			dst[i] = le64_to_cpu(src[i]);
2059 	}
2060 	hwrm_req_drop(bp, req);
2061 }
2062 
2063 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2064 {
2065 	struct bnxt *bp = netdev_priv(dev);
2066 
2067 	wol->supported = 0;
2068 	wol->wolopts = 0;
2069 	memset(&wol->sopass, 0, sizeof(wol->sopass));
2070 	if (bp->flags & BNXT_FLAG_WOL_CAP) {
2071 		wol->supported = WAKE_MAGIC;
2072 		if (bp->wol)
2073 			wol->wolopts = WAKE_MAGIC;
2074 	}
2075 }
2076 
2077 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2078 {
2079 	struct bnxt *bp = netdev_priv(dev);
2080 
2081 	if (wol->wolopts & ~WAKE_MAGIC)
2082 		return -EINVAL;
2083 
2084 	if (wol->wolopts & WAKE_MAGIC) {
2085 		if (!(bp->flags & BNXT_FLAG_WOL_CAP))
2086 			return -EINVAL;
2087 		if (!bp->wol) {
2088 			if (bnxt_hwrm_alloc_wol_fltr(bp))
2089 				return -EBUSY;
2090 			bp->wol = 1;
2091 		}
2092 	} else {
2093 		if (bp->wol) {
2094 			if (bnxt_hwrm_free_wol_fltr(bp))
2095 				return -EBUSY;
2096 			bp->wol = 0;
2097 		}
2098 	}
2099 	return 0;
2100 }
2101 
2102 /* TODO: support 25GB, 40GB, 50GB with different cable type */
2103 void _bnxt_fw_to_linkmode(unsigned long *mode, u16 fw_speeds)
2104 {
2105 	linkmode_zero(mode);
2106 
2107 	if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB)
2108 		linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode);
2109 	if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB)
2110 		linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode);
2111 	if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB)
2112 		linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT, mode);
2113 	if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB)
2114 		linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode);
2115 	if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB)
2116 		linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode);
2117 }
2118 
2119 enum bnxt_media_type {
2120 	BNXT_MEDIA_UNKNOWN = 0,
2121 	BNXT_MEDIA_TP,
2122 	BNXT_MEDIA_CR,
2123 	BNXT_MEDIA_SR,
2124 	BNXT_MEDIA_LR_ER_FR,
2125 	BNXT_MEDIA_KR,
2126 	BNXT_MEDIA_KX,
2127 	BNXT_MEDIA_X,
2128 	__BNXT_MEDIA_END,
2129 };
2130 
2131 static const enum bnxt_media_type bnxt_phy_types[] = {
2132 	[PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR] = BNXT_MEDIA_CR,
2133 	[PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4] =  BNXT_MEDIA_KR,
2134 	[PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR] = BNXT_MEDIA_LR_ER_FR,
2135 	[PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR] = BNXT_MEDIA_SR,
2136 	[PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2] = BNXT_MEDIA_KR,
2137 	[PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX] = BNXT_MEDIA_KX,
2138 	[PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR] = BNXT_MEDIA_KR,
2139 	[PORT_PHY_QCFG_RESP_PHY_TYPE_BASET] = BNXT_MEDIA_TP,
2140 	[PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE] = BNXT_MEDIA_TP,
2141 	[PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L] = BNXT_MEDIA_CR,
2142 	[PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S] = BNXT_MEDIA_CR,
2143 	[PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N] = BNXT_MEDIA_CR,
2144 	[PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR] = BNXT_MEDIA_SR,
2145 	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4] = BNXT_MEDIA_CR,
2146 	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4] = BNXT_MEDIA_SR,
2147 	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4] = BNXT_MEDIA_LR_ER_FR,
2148 	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4] = BNXT_MEDIA_LR_ER_FR,
2149 	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10] = BNXT_MEDIA_SR,
2150 	[PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4] = BNXT_MEDIA_CR,
2151 	[PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4] = BNXT_MEDIA_SR,
2152 	[PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4] = BNXT_MEDIA_LR_ER_FR,
2153 	[PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4] = BNXT_MEDIA_LR_ER_FR,
2154 	[PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE] = BNXT_MEDIA_SR,
2155 	[PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET] = BNXT_MEDIA_TP,
2156 	[PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX] = BNXT_MEDIA_X,
2157 	[PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX] = BNXT_MEDIA_X,
2158 	[PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4] = BNXT_MEDIA_CR,
2159 	[PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4] = BNXT_MEDIA_SR,
2160 	[PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4] = BNXT_MEDIA_LR_ER_FR,
2161 	[PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4] = BNXT_MEDIA_LR_ER_FR,
2162 	[PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR] = BNXT_MEDIA_CR,
2163 	[PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR] = BNXT_MEDIA_SR,
2164 	[PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR] = BNXT_MEDIA_LR_ER_FR,
2165 	[PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER] = BNXT_MEDIA_LR_ER_FR,
2166 	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2] = BNXT_MEDIA_CR,
2167 	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2] = BNXT_MEDIA_SR,
2168 	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2] = BNXT_MEDIA_LR_ER_FR,
2169 	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2] = BNXT_MEDIA_LR_ER_FR,
2170 	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR] = BNXT_MEDIA_CR,
2171 	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR] = BNXT_MEDIA_SR,
2172 	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR] = BNXT_MEDIA_LR_ER_FR,
2173 	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER] = BNXT_MEDIA_LR_ER_FR,
2174 	[PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2] = BNXT_MEDIA_CR,
2175 	[PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2] = BNXT_MEDIA_SR,
2176 	[PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2] = BNXT_MEDIA_LR_ER_FR,
2177 	[PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2] = BNXT_MEDIA_LR_ER_FR,
2178 	[PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8] = BNXT_MEDIA_CR,
2179 	[PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8] = BNXT_MEDIA_SR,
2180 	[PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8] = BNXT_MEDIA_LR_ER_FR,
2181 	[PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8] = BNXT_MEDIA_LR_ER_FR,
2182 	[PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4] = BNXT_MEDIA_CR,
2183 	[PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4] = BNXT_MEDIA_SR,
2184 	[PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4] = BNXT_MEDIA_LR_ER_FR,
2185 	[PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4] = BNXT_MEDIA_LR_ER_FR,
2186 };
2187 
2188 static enum bnxt_media_type
2189 bnxt_get_media(struct bnxt_link_info *link_info)
2190 {
2191 	switch (link_info->media_type) {
2192 	case PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP:
2193 		return BNXT_MEDIA_TP;
2194 	case PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC:
2195 		return BNXT_MEDIA_CR;
2196 	default:
2197 		if (link_info->phy_type < ARRAY_SIZE(bnxt_phy_types))
2198 			return bnxt_phy_types[link_info->phy_type];
2199 		return BNXT_MEDIA_UNKNOWN;
2200 	}
2201 }
2202 
2203 enum bnxt_link_speed_indices {
2204 	BNXT_LINK_SPEED_UNKNOWN = 0,
2205 	BNXT_LINK_SPEED_100MB_IDX,
2206 	BNXT_LINK_SPEED_1GB_IDX,
2207 	BNXT_LINK_SPEED_10GB_IDX,
2208 	BNXT_LINK_SPEED_25GB_IDX,
2209 	BNXT_LINK_SPEED_40GB_IDX,
2210 	BNXT_LINK_SPEED_50GB_IDX,
2211 	BNXT_LINK_SPEED_100GB_IDX,
2212 	BNXT_LINK_SPEED_200GB_IDX,
2213 	BNXT_LINK_SPEED_400GB_IDX,
2214 	__BNXT_LINK_SPEED_END
2215 };
2216 
2217 static enum bnxt_link_speed_indices bnxt_fw_speed_idx(u16 speed)
2218 {
2219 	switch (speed) {
2220 	case BNXT_LINK_SPEED_100MB: return BNXT_LINK_SPEED_100MB_IDX;
2221 	case BNXT_LINK_SPEED_1GB: return BNXT_LINK_SPEED_1GB_IDX;
2222 	case BNXT_LINK_SPEED_10GB: return BNXT_LINK_SPEED_10GB_IDX;
2223 	case BNXT_LINK_SPEED_25GB: return BNXT_LINK_SPEED_25GB_IDX;
2224 	case BNXT_LINK_SPEED_40GB: return BNXT_LINK_SPEED_40GB_IDX;
2225 	case BNXT_LINK_SPEED_50GB:
2226 	case BNXT_LINK_SPEED_50GB_PAM4:
2227 		return BNXT_LINK_SPEED_50GB_IDX;
2228 	case BNXT_LINK_SPEED_100GB:
2229 	case BNXT_LINK_SPEED_100GB_PAM4:
2230 	case BNXT_LINK_SPEED_100GB_PAM4_112:
2231 		return BNXT_LINK_SPEED_100GB_IDX;
2232 	case BNXT_LINK_SPEED_200GB:
2233 	case BNXT_LINK_SPEED_200GB_PAM4:
2234 	case BNXT_LINK_SPEED_200GB_PAM4_112:
2235 		return BNXT_LINK_SPEED_200GB_IDX;
2236 	case BNXT_LINK_SPEED_400GB:
2237 	case BNXT_LINK_SPEED_400GB_PAM4:
2238 	case BNXT_LINK_SPEED_400GB_PAM4_112:
2239 		return BNXT_LINK_SPEED_400GB_IDX;
2240 	default: return BNXT_LINK_SPEED_UNKNOWN;
2241 	}
2242 }
2243 
2244 static const enum ethtool_link_mode_bit_indices
2245 bnxt_link_modes[__BNXT_LINK_SPEED_END][BNXT_SIG_MODE_MAX][__BNXT_MEDIA_END] = {
2246 	[BNXT_LINK_SPEED_100MB_IDX] = {
2247 		{
2248 			[BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2249 		},
2250 	},
2251 	[BNXT_LINK_SPEED_1GB_IDX] = {
2252 		{
2253 			[BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
2254 			/* historically baseT, but DAC is more correctly baseX */
2255 			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
2256 			[BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2257 			[BNXT_MEDIA_X] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
2258 			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2259 		},
2260 	},
2261 	[BNXT_LINK_SPEED_10GB_IDX] = {
2262 		{
2263 			[BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2264 			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
2265 			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
2266 			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
2267 			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2268 			[BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2269 		},
2270 	},
2271 	[BNXT_LINK_SPEED_25GB_IDX] = {
2272 		{
2273 			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2274 			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2275 			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2276 		},
2277 	},
2278 	[BNXT_LINK_SPEED_40GB_IDX] = {
2279 		{
2280 			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2281 			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2282 			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2283 			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2284 		},
2285 	},
2286 	[BNXT_LINK_SPEED_50GB_IDX] = {
2287 		[BNXT_SIG_MODE_NRZ] = {
2288 			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2289 			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2290 			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2291 		},
2292 		[BNXT_SIG_MODE_PAM4] = {
2293 			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
2294 			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
2295 			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
2296 			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
2297 		},
2298 	},
2299 	[BNXT_LINK_SPEED_100GB_IDX] = {
2300 		[BNXT_SIG_MODE_NRZ] = {
2301 			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2302 			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2303 			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2304 			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2305 		},
2306 		[BNXT_SIG_MODE_PAM4] = {
2307 			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
2308 			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
2309 			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
2310 			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
2311 		},
2312 		[BNXT_SIG_MODE_PAM4_112] = {
2313 			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR_Full_BIT,
2314 			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR_Full_BIT,
2315 			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR_Full_BIT,
2316 			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT,
2317 		},
2318 	},
2319 	[BNXT_LINK_SPEED_200GB_IDX] = {
2320 		[BNXT_SIG_MODE_PAM4] = {
2321 			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT,
2322 			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
2323 			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
2324 			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
2325 		},
2326 		[BNXT_SIG_MODE_PAM4_112] = {
2327 			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT,
2328 			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT,
2329 			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT,
2330 			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT,
2331 		},
2332 	},
2333 	[BNXT_LINK_SPEED_400GB_IDX] = {
2334 		[BNXT_SIG_MODE_PAM4] = {
2335 			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT,
2336 			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT,
2337 			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT,
2338 			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT,
2339 		},
2340 		[BNXT_SIG_MODE_PAM4_112] = {
2341 			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT,
2342 			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT,
2343 			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT,
2344 			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT,
2345 		},
2346 	},
2347 };
2348 
2349 #define BNXT_LINK_MODE_UNKNOWN -1
2350 
2351 static enum ethtool_link_mode_bit_indices
2352 bnxt_get_link_mode(struct bnxt_link_info *link_info)
2353 {
2354 	enum ethtool_link_mode_bit_indices link_mode;
2355 	enum bnxt_link_speed_indices speed;
2356 	enum bnxt_media_type media;
2357 	u8 sig_mode;
2358 
2359 	if (link_info->phy_link_status != BNXT_LINK_LINK)
2360 		return BNXT_LINK_MODE_UNKNOWN;
2361 
2362 	media = bnxt_get_media(link_info);
2363 	if (BNXT_AUTO_MODE(link_info->auto_mode)) {
2364 		speed = bnxt_fw_speed_idx(link_info->link_speed);
2365 		sig_mode = link_info->active_fec_sig_mode &
2366 			PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK;
2367 	} else {
2368 		speed = bnxt_fw_speed_idx(link_info->req_link_speed);
2369 		sig_mode = link_info->req_signal_mode;
2370 	}
2371 	if (sig_mode >= BNXT_SIG_MODE_MAX)
2372 		return BNXT_LINK_MODE_UNKNOWN;
2373 
2374 	/* Note ETHTOOL_LINK_MODE_10baseT_Half_BIT == 0 is a legal Linux
2375 	 * link mode, but since no such devices exist, the zeroes in the
2376 	 * map can be conveniently used to represent unknown link modes.
2377 	 */
2378 	link_mode = bnxt_link_modes[speed][sig_mode][media];
2379 	if (!link_mode)
2380 		return BNXT_LINK_MODE_UNKNOWN;
2381 
2382 	switch (link_mode) {
2383 	case ETHTOOL_LINK_MODE_100baseT_Full_BIT:
2384 		if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL)
2385 			link_mode = ETHTOOL_LINK_MODE_100baseT_Half_BIT;
2386 		break;
2387 	case ETHTOOL_LINK_MODE_1000baseT_Full_BIT:
2388 		if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL)
2389 			link_mode = ETHTOOL_LINK_MODE_1000baseT_Half_BIT;
2390 		break;
2391 	default:
2392 		break;
2393 	}
2394 
2395 	return link_mode;
2396 }
2397 
2398 static void bnxt_get_ethtool_modes(struct bnxt_link_info *link_info,
2399 				   struct ethtool_link_ksettings *lk_ksettings)
2400 {
2401 	struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2402 
2403 	if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) {
2404 		linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2405 				 lk_ksettings->link_modes.supported);
2406 		linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2407 				 lk_ksettings->link_modes.supported);
2408 	}
2409 
2410 	if (link_info->support_auto_speeds || link_info->support_auto_speeds2 ||
2411 	    link_info->support_pam4_auto_speeds)
2412 		linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
2413 				 lk_ksettings->link_modes.supported);
2414 
2415 	if (~link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
2416 		return;
2417 
2418 	if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_RX)
2419 		linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2420 				 lk_ksettings->link_modes.advertising);
2421 	if (hweight8(link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) == 1)
2422 		linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2423 				 lk_ksettings->link_modes.advertising);
2424 	if (link_info->lp_pause & BNXT_LINK_PAUSE_RX)
2425 		linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2426 				 lk_ksettings->link_modes.lp_advertising);
2427 	if (hweight8(link_info->lp_pause & BNXT_LINK_PAUSE_BOTH) == 1)
2428 		linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2429 				 lk_ksettings->link_modes.lp_advertising);
2430 }
2431 
2432 static const u16 bnxt_nrz_speed_masks[] = {
2433 	[BNXT_LINK_SPEED_100MB_IDX] = BNXT_LINK_SPEED_MSK_100MB,
2434 	[BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEED_MSK_1GB,
2435 	[BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEED_MSK_10GB,
2436 	[BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEED_MSK_25GB,
2437 	[BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEED_MSK_40GB,
2438 	[BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEED_MSK_50GB,
2439 	[BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEED_MSK_100GB,
2440 	[__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */
2441 };
2442 
2443 static const u16 bnxt_pam4_speed_masks[] = {
2444 	[BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_50GB,
2445 	[BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_100GB,
2446 	[BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_200GB,
2447 	[__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */
2448 };
2449 
2450 static const u16 bnxt_nrz_speeds2_masks[] = {
2451 	[BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEEDS2_MSK_1GB,
2452 	[BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEEDS2_MSK_10GB,
2453 	[BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEEDS2_MSK_25GB,
2454 	[BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEEDS2_MSK_40GB,
2455 	[BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB,
2456 	[BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB,
2457 	[__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */
2458 };
2459 
2460 static const u16 bnxt_pam4_speeds2_masks[] = {
2461 	[BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB_PAM4,
2462 	[BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4,
2463 	[BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4,
2464 	[BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4,
2465 };
2466 
2467 static const u16 bnxt_pam4_112_speeds2_masks[] = {
2468 	[BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112,
2469 	[BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112,
2470 	[BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112,
2471 };
2472 
2473 static enum bnxt_link_speed_indices
2474 bnxt_encoding_speed_idx(u8 sig_mode, u16 phy_flags, u16 speed_msk)
2475 {
2476 	const u16 *speeds;
2477 	int idx, len;
2478 
2479 	switch (sig_mode) {
2480 	case BNXT_SIG_MODE_NRZ:
2481 		if (phy_flags & BNXT_PHY_FL_SPEEDS2) {
2482 			speeds = bnxt_nrz_speeds2_masks;
2483 			len = ARRAY_SIZE(bnxt_nrz_speeds2_masks);
2484 		} else {
2485 			speeds = bnxt_nrz_speed_masks;
2486 			len = ARRAY_SIZE(bnxt_nrz_speed_masks);
2487 		}
2488 		break;
2489 	case BNXT_SIG_MODE_PAM4:
2490 		if (phy_flags & BNXT_PHY_FL_SPEEDS2) {
2491 			speeds = bnxt_pam4_speeds2_masks;
2492 			len = ARRAY_SIZE(bnxt_pam4_speeds2_masks);
2493 		} else {
2494 			speeds = bnxt_pam4_speed_masks;
2495 			len = ARRAY_SIZE(bnxt_pam4_speed_masks);
2496 		}
2497 		break;
2498 	case BNXT_SIG_MODE_PAM4_112:
2499 		speeds = bnxt_pam4_112_speeds2_masks;
2500 		len = ARRAY_SIZE(bnxt_pam4_112_speeds2_masks);
2501 		break;
2502 	default:
2503 		return BNXT_LINK_SPEED_UNKNOWN;
2504 	}
2505 
2506 	for (idx = 0; idx < len; idx++) {
2507 		if (speeds[idx] == speed_msk)
2508 			return idx;
2509 	}
2510 
2511 	return BNXT_LINK_SPEED_UNKNOWN;
2512 }
2513 
2514 #define BNXT_FW_SPEED_MSK_BITS 16
2515 
2516 static void
2517 __bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media,
2518 			  u8 sig_mode, u16 phy_flags, unsigned long *et_mask)
2519 {
2520 	enum ethtool_link_mode_bit_indices link_mode;
2521 	enum bnxt_link_speed_indices speed;
2522 	u8 bit;
2523 
2524 	for_each_set_bit(bit, &fw_mask, BNXT_FW_SPEED_MSK_BITS) {
2525 		speed = bnxt_encoding_speed_idx(sig_mode, phy_flags, 1 << bit);
2526 		if (!speed)
2527 			continue;
2528 
2529 		link_mode = bnxt_link_modes[speed][sig_mode][media];
2530 		if (!link_mode)
2531 			continue;
2532 
2533 		linkmode_set_bit(link_mode, et_mask);
2534 	}
2535 }
2536 
2537 static void
2538 bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media,
2539 			u8 sig_mode, u16 phy_flags, unsigned long *et_mask)
2540 {
2541 	if (media) {
2542 		__bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags,
2543 					  et_mask);
2544 		return;
2545 	}
2546 
2547 	/* list speeds for all media if unknown */
2548 	for (media = 1; media < __BNXT_MEDIA_END; media++)
2549 		__bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags,
2550 					  et_mask);
2551 }
2552 
2553 static void
2554 bnxt_get_all_ethtool_support_speeds(struct bnxt_link_info *link_info,
2555 				    enum bnxt_media_type media,
2556 				    struct ethtool_link_ksettings *lk_ksettings)
2557 {
2558 	struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2559 	u16 sp_nrz, sp_pam4, sp_pam4_112 = 0;
2560 	u16 phy_flags = bp->phy_flags;
2561 
2562 	if (phy_flags & BNXT_PHY_FL_SPEEDS2) {
2563 		sp_nrz = link_info->support_speeds2;
2564 		sp_pam4 = link_info->support_speeds2;
2565 		sp_pam4_112 = link_info->support_speeds2;
2566 	} else {
2567 		sp_nrz = link_info->support_speeds;
2568 		sp_pam4 = link_info->support_pam4_speeds;
2569 	}
2570 	bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags,
2571 				lk_ksettings->link_modes.supported);
2572 	bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags,
2573 				lk_ksettings->link_modes.supported);
2574 	bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112,
2575 				phy_flags, lk_ksettings->link_modes.supported);
2576 }
2577 
2578 static void
2579 bnxt_get_all_ethtool_adv_speeds(struct bnxt_link_info *link_info,
2580 				enum bnxt_media_type media,
2581 				struct ethtool_link_ksettings *lk_ksettings)
2582 {
2583 	struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2584 	u16 sp_nrz, sp_pam4, sp_pam4_112 = 0;
2585 	u16 phy_flags = bp->phy_flags;
2586 
2587 	sp_nrz = link_info->advertising;
2588 	if (phy_flags & BNXT_PHY_FL_SPEEDS2) {
2589 		sp_pam4 = link_info->advertising;
2590 		sp_pam4_112 = link_info->advertising;
2591 	} else {
2592 		sp_pam4 = link_info->advertising_pam4;
2593 	}
2594 	bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags,
2595 				lk_ksettings->link_modes.advertising);
2596 	bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags,
2597 				lk_ksettings->link_modes.advertising);
2598 	bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112,
2599 				phy_flags, lk_ksettings->link_modes.advertising);
2600 }
2601 
2602 static void
2603 bnxt_get_all_ethtool_lp_speeds(struct bnxt_link_info *link_info,
2604 			       enum bnxt_media_type media,
2605 			       struct ethtool_link_ksettings *lk_ksettings)
2606 {
2607 	struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2608 	u16 phy_flags = bp->phy_flags;
2609 
2610 	bnxt_get_ethtool_speeds(link_info->lp_auto_link_speeds, media,
2611 				BNXT_SIG_MODE_NRZ, phy_flags,
2612 				lk_ksettings->link_modes.lp_advertising);
2613 	bnxt_get_ethtool_speeds(link_info->lp_auto_pam4_link_speeds, media,
2614 				BNXT_SIG_MODE_PAM4, phy_flags,
2615 				lk_ksettings->link_modes.lp_advertising);
2616 }
2617 
2618 static void bnxt_update_speed(u32 *delta, bool installed_media, u16 *speeds,
2619 			      u16 speed_msk, const unsigned long *et_mask,
2620 			      enum ethtool_link_mode_bit_indices mode)
2621 {
2622 	bool mode_desired = linkmode_test_bit(mode, et_mask);
2623 
2624 	if (!mode)
2625 		return;
2626 
2627 	/* enabled speeds for installed media should override */
2628 	if (installed_media && mode_desired) {
2629 		*speeds |= speed_msk;
2630 		*delta |= speed_msk;
2631 		return;
2632 	}
2633 
2634 	/* many to one mapping, only allow one change per fw_speed bit */
2635 	if (!(*delta & speed_msk) && (mode_desired == !(*speeds & speed_msk))) {
2636 		*speeds ^= speed_msk;
2637 		*delta |= speed_msk;
2638 	}
2639 }
2640 
2641 static void bnxt_set_ethtool_speeds(struct bnxt_link_info *link_info,
2642 				    const unsigned long *et_mask)
2643 {
2644 	struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2645 	u16 const *sp_msks, *sp_pam4_msks, *sp_pam4_112_msks;
2646 	enum bnxt_media_type media = bnxt_get_media(link_info);
2647 	u16 *adv, *adv_pam4, *adv_pam4_112 = NULL;
2648 	u32 delta_pam4_112 = 0;
2649 	u32 delta_pam4 = 0;
2650 	u32 delta_nrz = 0;
2651 	int i, m;
2652 
2653 	adv = &link_info->advertising;
2654 	if (bp->phy_flags & BNXT_PHY_FL_SPEEDS2) {
2655 		adv_pam4 = &link_info->advertising;
2656 		adv_pam4_112 = &link_info->advertising;
2657 		sp_msks = bnxt_nrz_speeds2_masks;
2658 		sp_pam4_msks = bnxt_pam4_speeds2_masks;
2659 		sp_pam4_112_msks = bnxt_pam4_112_speeds2_masks;
2660 	} else {
2661 		adv_pam4 = &link_info->advertising_pam4;
2662 		sp_msks = bnxt_nrz_speed_masks;
2663 		sp_pam4_msks = bnxt_pam4_speed_masks;
2664 	}
2665 	for (i = 1; i < __BNXT_LINK_SPEED_END; i++) {
2666 		/* accept any legal media from user */
2667 		for (m = 1; m < __BNXT_MEDIA_END; m++) {
2668 			bnxt_update_speed(&delta_nrz, m == media,
2669 					  adv, sp_msks[i], et_mask,
2670 					  bnxt_link_modes[i][BNXT_SIG_MODE_NRZ][m]);
2671 			bnxt_update_speed(&delta_pam4, m == media,
2672 					  adv_pam4, sp_pam4_msks[i], et_mask,
2673 					  bnxt_link_modes[i][BNXT_SIG_MODE_PAM4][m]);
2674 			if (!adv_pam4_112)
2675 				continue;
2676 
2677 			bnxt_update_speed(&delta_pam4_112, m == media,
2678 					  adv_pam4_112, sp_pam4_112_msks[i], et_mask,
2679 					  bnxt_link_modes[i][BNXT_SIG_MODE_PAM4_112][m]);
2680 		}
2681 	}
2682 }
2683 
2684 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info,
2685 				struct ethtool_link_ksettings *lk_ksettings)
2686 {
2687 	u16 fec_cfg = link_info->fec_cfg;
2688 
2689 	if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) {
2690 		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
2691 				 lk_ksettings->link_modes.advertising);
2692 		return;
2693 	}
2694 	if (fec_cfg & BNXT_FEC_ENC_BASE_R)
2695 		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
2696 				 lk_ksettings->link_modes.advertising);
2697 	if (fec_cfg & BNXT_FEC_ENC_RS)
2698 		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
2699 				 lk_ksettings->link_modes.advertising);
2700 	if (fec_cfg & BNXT_FEC_ENC_LLRS)
2701 		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
2702 				 lk_ksettings->link_modes.advertising);
2703 }
2704 
2705 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info,
2706 				struct ethtool_link_ksettings *lk_ksettings)
2707 {
2708 	u16 fec_cfg = link_info->fec_cfg;
2709 
2710 	if (fec_cfg & BNXT_FEC_NONE) {
2711 		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
2712 				 lk_ksettings->link_modes.supported);
2713 		return;
2714 	}
2715 	if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP)
2716 		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
2717 				 lk_ksettings->link_modes.supported);
2718 	if (fec_cfg & BNXT_FEC_ENC_RS_CAP)
2719 		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
2720 				 lk_ksettings->link_modes.supported);
2721 	if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP)
2722 		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
2723 				 lk_ksettings->link_modes.supported);
2724 }
2725 
2726 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed)
2727 {
2728 	switch (fw_link_speed) {
2729 	case BNXT_LINK_SPEED_100MB:
2730 		return SPEED_100;
2731 	case BNXT_LINK_SPEED_1GB:
2732 		return SPEED_1000;
2733 	case BNXT_LINK_SPEED_2_5GB:
2734 		return SPEED_2500;
2735 	case BNXT_LINK_SPEED_10GB:
2736 		return SPEED_10000;
2737 	case BNXT_LINK_SPEED_20GB:
2738 		return SPEED_20000;
2739 	case BNXT_LINK_SPEED_25GB:
2740 		return SPEED_25000;
2741 	case BNXT_LINK_SPEED_40GB:
2742 		return SPEED_40000;
2743 	case BNXT_LINK_SPEED_50GB:
2744 	case BNXT_LINK_SPEED_50GB_PAM4:
2745 		return SPEED_50000;
2746 	case BNXT_LINK_SPEED_100GB:
2747 	case BNXT_LINK_SPEED_100GB_PAM4:
2748 	case BNXT_LINK_SPEED_100GB_PAM4_112:
2749 		return SPEED_100000;
2750 	case BNXT_LINK_SPEED_200GB:
2751 	case BNXT_LINK_SPEED_200GB_PAM4:
2752 	case BNXT_LINK_SPEED_200GB_PAM4_112:
2753 		return SPEED_200000;
2754 	case BNXT_LINK_SPEED_400GB:
2755 	case BNXT_LINK_SPEED_400GB_PAM4:
2756 	case BNXT_LINK_SPEED_400GB_PAM4_112:
2757 		return SPEED_400000;
2758 	default:
2759 		return SPEED_UNKNOWN;
2760 	}
2761 }
2762 
2763 static void bnxt_get_default_speeds(struct ethtool_link_ksettings *lk_ksettings,
2764 				    struct bnxt_link_info *link_info)
2765 {
2766 	struct ethtool_link_settings *base = &lk_ksettings->base;
2767 
2768 	if (link_info->link_state == BNXT_LINK_STATE_UP) {
2769 		base->speed = bnxt_fw_to_ethtool_speed(link_info->link_speed);
2770 		base->duplex = DUPLEX_HALF;
2771 		if (link_info->duplex & BNXT_LINK_DUPLEX_FULL)
2772 			base->duplex = DUPLEX_FULL;
2773 		lk_ksettings->lanes = link_info->active_lanes;
2774 	} else if (!link_info->autoneg) {
2775 		base->speed = bnxt_fw_to_ethtool_speed(link_info->req_link_speed);
2776 		base->duplex = DUPLEX_HALF;
2777 		if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL)
2778 			base->duplex = DUPLEX_FULL;
2779 	}
2780 }
2781 
2782 static int bnxt_get_link_ksettings(struct net_device *dev,
2783 				   struct ethtool_link_ksettings *lk_ksettings)
2784 {
2785 	struct ethtool_link_settings *base = &lk_ksettings->base;
2786 	enum ethtool_link_mode_bit_indices link_mode;
2787 	struct bnxt *bp = netdev_priv(dev);
2788 	struct bnxt_link_info *link_info;
2789 	enum bnxt_media_type media;
2790 
2791 	ethtool_link_ksettings_zero_link_mode(lk_ksettings, lp_advertising);
2792 	ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising);
2793 	ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported);
2794 	base->duplex = DUPLEX_UNKNOWN;
2795 	base->speed = SPEED_UNKNOWN;
2796 	link_info = &bp->link_info;
2797 
2798 	mutex_lock(&bp->link_lock);
2799 	bnxt_get_ethtool_modes(link_info, lk_ksettings);
2800 	media = bnxt_get_media(link_info);
2801 	bnxt_get_all_ethtool_support_speeds(link_info, media, lk_ksettings);
2802 	bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings);
2803 	link_mode = bnxt_get_link_mode(link_info);
2804 	if (link_mode != BNXT_LINK_MODE_UNKNOWN)
2805 		ethtool_params_from_link_mode(lk_ksettings, link_mode);
2806 	else
2807 		bnxt_get_default_speeds(lk_ksettings, link_info);
2808 
2809 	if (link_info->autoneg) {
2810 		bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings);
2811 		linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
2812 				 lk_ksettings->link_modes.advertising);
2813 		base->autoneg = AUTONEG_ENABLE;
2814 		bnxt_get_all_ethtool_adv_speeds(link_info, media, lk_ksettings);
2815 		if (link_info->phy_link_status == BNXT_LINK_LINK)
2816 			bnxt_get_all_ethtool_lp_speeds(link_info, media,
2817 						       lk_ksettings);
2818 	} else {
2819 		base->autoneg = AUTONEG_DISABLE;
2820 	}
2821 
2822 	base->port = PORT_NONE;
2823 	if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
2824 		base->port = PORT_TP;
2825 		linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
2826 				 lk_ksettings->link_modes.supported);
2827 		linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
2828 				 lk_ksettings->link_modes.advertising);
2829 	} else {
2830 		linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
2831 				 lk_ksettings->link_modes.supported);
2832 		linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
2833 				 lk_ksettings->link_modes.advertising);
2834 
2835 		if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC)
2836 			base->port = PORT_DA;
2837 		else
2838 			base->port = PORT_FIBRE;
2839 	}
2840 	base->phy_address = link_info->phy_addr;
2841 	mutex_unlock(&bp->link_lock);
2842 
2843 	return 0;
2844 }
2845 
2846 static int
2847 bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed, u32 lanes)
2848 {
2849 	struct bnxt *bp = netdev_priv(dev);
2850 	struct bnxt_link_info *link_info = &bp->link_info;
2851 	u16 support_pam4_spds = link_info->support_pam4_speeds;
2852 	u16 support_spds2 = link_info->support_speeds2;
2853 	u16 support_spds = link_info->support_speeds;
2854 	u8 sig_mode = BNXT_SIG_MODE_NRZ;
2855 	u32 lanes_needed = 1;
2856 	u16 fw_speed = 0;
2857 
2858 	switch (ethtool_speed) {
2859 	case SPEED_100:
2860 		if (support_spds & BNXT_LINK_SPEED_MSK_100MB)
2861 			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB;
2862 		break;
2863 	case SPEED_1000:
2864 		if ((support_spds & BNXT_LINK_SPEED_MSK_1GB) ||
2865 		    (support_spds2 & BNXT_LINK_SPEEDS2_MSK_1GB))
2866 			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
2867 		break;
2868 	case SPEED_2500:
2869 		if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB)
2870 			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB;
2871 		break;
2872 	case SPEED_10000:
2873 		if ((support_spds & BNXT_LINK_SPEED_MSK_10GB) ||
2874 		    (support_spds2 & BNXT_LINK_SPEEDS2_MSK_10GB))
2875 			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
2876 		break;
2877 	case SPEED_20000:
2878 		if (support_spds & BNXT_LINK_SPEED_MSK_20GB) {
2879 			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB;
2880 			lanes_needed = 2;
2881 		}
2882 		break;
2883 	case SPEED_25000:
2884 		if ((support_spds & BNXT_LINK_SPEED_MSK_25GB) ||
2885 		    (support_spds2 & BNXT_LINK_SPEEDS2_MSK_25GB))
2886 			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
2887 		break;
2888 	case SPEED_40000:
2889 		if ((support_spds & BNXT_LINK_SPEED_MSK_40GB) ||
2890 		    (support_spds2 & BNXT_LINK_SPEEDS2_MSK_40GB)) {
2891 			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
2892 			lanes_needed = 4;
2893 		}
2894 		break;
2895 	case SPEED_50000:
2896 		if (((support_spds & BNXT_LINK_SPEED_MSK_50GB) ||
2897 		     (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB)) &&
2898 		    lanes != 1) {
2899 			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
2900 			lanes_needed = 2;
2901 		} else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) {
2902 			fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB;
2903 			sig_mode = BNXT_SIG_MODE_PAM4;
2904 		} else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB_PAM4) {
2905 			fw_speed = BNXT_LINK_SPEED_50GB_PAM4;
2906 			sig_mode = BNXT_SIG_MODE_PAM4;
2907 		}
2908 		break;
2909 	case SPEED_100000:
2910 		if (((support_spds & BNXT_LINK_SPEED_MSK_100GB) ||
2911 		     (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB)) &&
2912 		    lanes != 2 && lanes != 1) {
2913 			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB;
2914 			lanes_needed = 4;
2915 		} else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) {
2916 			fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB;
2917 			sig_mode = BNXT_SIG_MODE_PAM4;
2918 			lanes_needed = 2;
2919 		} else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4) &&
2920 			   lanes != 1) {
2921 			fw_speed = BNXT_LINK_SPEED_100GB_PAM4;
2922 			sig_mode = BNXT_SIG_MODE_PAM4;
2923 			lanes_needed = 2;
2924 		} else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112) {
2925 			fw_speed = BNXT_LINK_SPEED_100GB_PAM4_112;
2926 			sig_mode = BNXT_SIG_MODE_PAM4_112;
2927 		}
2928 		break;
2929 	case SPEED_200000:
2930 		if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) {
2931 			fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB;
2932 			sig_mode = BNXT_SIG_MODE_PAM4;
2933 			lanes_needed = 4;
2934 		} else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4) &&
2935 			   lanes != 2) {
2936 			fw_speed = BNXT_LINK_SPEED_200GB_PAM4;
2937 			sig_mode = BNXT_SIG_MODE_PAM4;
2938 			lanes_needed = 4;
2939 		} else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112) {
2940 			fw_speed = BNXT_LINK_SPEED_200GB_PAM4_112;
2941 			sig_mode = BNXT_SIG_MODE_PAM4_112;
2942 			lanes_needed = 2;
2943 		}
2944 		break;
2945 	case SPEED_400000:
2946 		if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4) &&
2947 		    lanes != 4) {
2948 			fw_speed = BNXT_LINK_SPEED_400GB_PAM4;
2949 			sig_mode = BNXT_SIG_MODE_PAM4;
2950 			lanes_needed = 8;
2951 		} else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112) {
2952 			fw_speed = BNXT_LINK_SPEED_400GB_PAM4_112;
2953 			sig_mode = BNXT_SIG_MODE_PAM4_112;
2954 			lanes_needed = 4;
2955 		}
2956 		break;
2957 	}
2958 
2959 	if (!fw_speed) {
2960 		netdev_err(dev, "unsupported speed!\n");
2961 		return -EINVAL;
2962 	}
2963 
2964 	if (lanes && lanes != lanes_needed) {
2965 		netdev_err(dev, "unsupported number of lanes for speed\n");
2966 		return -EINVAL;
2967 	}
2968 
2969 	if (link_info->req_link_speed == fw_speed &&
2970 	    link_info->req_signal_mode == sig_mode &&
2971 	    link_info->autoneg == 0)
2972 		return -EALREADY;
2973 
2974 	link_info->req_link_speed = fw_speed;
2975 	link_info->req_signal_mode = sig_mode;
2976 	link_info->req_duplex = BNXT_LINK_DUPLEX_FULL;
2977 	link_info->autoneg = 0;
2978 	link_info->advertising = 0;
2979 	link_info->advertising_pam4 = 0;
2980 
2981 	return 0;
2982 }
2983 
2984 u16 bnxt_get_fw_auto_link_speeds(const unsigned long *mode)
2985 {
2986 	u16 fw_speed_mask = 0;
2987 
2988 	if (linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode) ||
2989 	    linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mode))
2990 		fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB;
2991 
2992 	if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode) ||
2993 	    linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, mode))
2994 		fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB;
2995 
2996 	if (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode))
2997 		fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB;
2998 
2999 	if (linkmode_test_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode))
3000 		fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB;
3001 
3002 	return fw_speed_mask;
3003 }
3004 
3005 static int bnxt_set_link_ksettings(struct net_device *dev,
3006 			   const struct ethtool_link_ksettings *lk_ksettings)
3007 {
3008 	struct bnxt *bp = netdev_priv(dev);
3009 	struct bnxt_link_info *link_info = &bp->link_info;
3010 	const struct ethtool_link_settings *base = &lk_ksettings->base;
3011 	bool set_pause = false;
3012 	u32 speed, lanes = 0;
3013 	int rc = 0;
3014 
3015 	if (!BNXT_PHY_CFG_ABLE(bp))
3016 		return -EOPNOTSUPP;
3017 
3018 	mutex_lock(&bp->link_lock);
3019 	if (base->autoneg == AUTONEG_ENABLE) {
3020 		bnxt_set_ethtool_speeds(link_info,
3021 					lk_ksettings->link_modes.advertising);
3022 		link_info->autoneg |= BNXT_AUTONEG_SPEED;
3023 		if (!link_info->advertising && !link_info->advertising_pam4) {
3024 			link_info->advertising = link_info->support_auto_speeds;
3025 			link_info->advertising_pam4 =
3026 				link_info->support_pam4_auto_speeds;
3027 		}
3028 		/* any change to autoneg will cause link change, therefore the
3029 		 * driver should put back the original pause setting in autoneg
3030 		 */
3031 		if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE))
3032 			set_pause = true;
3033 	} else {
3034 		u8 phy_type = link_info->phy_type;
3035 
3036 		if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET  ||
3037 		    phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE ||
3038 		    link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
3039 			netdev_err(dev, "10GBase-T devices must autoneg\n");
3040 			rc = -EINVAL;
3041 			goto set_setting_exit;
3042 		}
3043 		if (base->duplex == DUPLEX_HALF) {
3044 			netdev_err(dev, "HALF DUPLEX is not supported!\n");
3045 			rc = -EINVAL;
3046 			goto set_setting_exit;
3047 		}
3048 		speed = base->speed;
3049 		lanes = lk_ksettings->lanes;
3050 		rc = bnxt_force_link_speed(dev, speed, lanes);
3051 		if (rc) {
3052 			if (rc == -EALREADY)
3053 				rc = 0;
3054 			goto set_setting_exit;
3055 		}
3056 	}
3057 
3058 	if (netif_running(dev))
3059 		rc = bnxt_hwrm_set_link_setting(bp, set_pause, false);
3060 
3061 set_setting_exit:
3062 	mutex_unlock(&bp->link_lock);
3063 	return rc;
3064 }
3065 
3066 static int bnxt_get_fecparam(struct net_device *dev,
3067 			     struct ethtool_fecparam *fec)
3068 {
3069 	struct bnxt *bp = netdev_priv(dev);
3070 	struct bnxt_link_info *link_info;
3071 	u8 active_fec;
3072 	u16 fec_cfg;
3073 
3074 	link_info = &bp->link_info;
3075 	fec_cfg = link_info->fec_cfg;
3076 	active_fec = link_info->active_fec_sig_mode &
3077 		     PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK;
3078 	if (fec_cfg & BNXT_FEC_NONE) {
3079 		fec->fec = ETHTOOL_FEC_NONE;
3080 		fec->active_fec = ETHTOOL_FEC_NONE;
3081 		return 0;
3082 	}
3083 	if (fec_cfg & BNXT_FEC_AUTONEG)
3084 		fec->fec |= ETHTOOL_FEC_AUTO;
3085 	if (fec_cfg & BNXT_FEC_ENC_BASE_R)
3086 		fec->fec |= ETHTOOL_FEC_BASER;
3087 	if (fec_cfg & BNXT_FEC_ENC_RS)
3088 		fec->fec |= ETHTOOL_FEC_RS;
3089 	if (fec_cfg & BNXT_FEC_ENC_LLRS)
3090 		fec->fec |= ETHTOOL_FEC_LLRS;
3091 
3092 	switch (active_fec) {
3093 	case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE:
3094 		fec->active_fec |= ETHTOOL_FEC_BASER;
3095 		break;
3096 	case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE:
3097 	case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE:
3098 	case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE:
3099 		fec->active_fec |= ETHTOOL_FEC_RS;
3100 		break;
3101 	case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE:
3102 	case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE:
3103 		fec->active_fec |= ETHTOOL_FEC_LLRS;
3104 		break;
3105 	case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE:
3106 		fec->active_fec |= ETHTOOL_FEC_OFF;
3107 		break;
3108 	}
3109 	return 0;
3110 }
3111 
3112 static void bnxt_get_fec_stats(struct net_device *dev,
3113 			       struct ethtool_fec_stats *fec_stats)
3114 {
3115 	struct bnxt *bp = netdev_priv(dev);
3116 	u64 *rx;
3117 
3118 	if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
3119 		return;
3120 
3121 	rx = bp->rx_port_stats_ext.sw_stats;
3122 	fec_stats->corrected_bits.total =
3123 		*(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits));
3124 
3125 	if (bp->fw_rx_stats_ext_size <= BNXT_RX_STATS_EXT_NUM_LEGACY)
3126 		return;
3127 
3128 	fec_stats->corrected_blocks.total =
3129 		*(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks));
3130 	fec_stats->uncorrectable_blocks.total =
3131 		*(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_uncorrectable_blocks));
3132 }
3133 
3134 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info,
3135 					 u32 fec)
3136 {
3137 	u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE;
3138 
3139 	if (fec & ETHTOOL_FEC_BASER)
3140 		fw_fec |= BNXT_FEC_BASE_R_ON(link_info);
3141 	else if (fec & ETHTOOL_FEC_RS)
3142 		fw_fec |= BNXT_FEC_RS_ON(link_info);
3143 	else if (fec & ETHTOOL_FEC_LLRS)
3144 		fw_fec |= BNXT_FEC_LLRS_ON;
3145 	return fw_fec;
3146 }
3147 
3148 static int bnxt_set_fecparam(struct net_device *dev,
3149 			     struct ethtool_fecparam *fecparam)
3150 {
3151 	struct hwrm_port_phy_cfg_input *req;
3152 	struct bnxt *bp = netdev_priv(dev);
3153 	struct bnxt_link_info *link_info;
3154 	u32 new_cfg, fec = fecparam->fec;
3155 	u16 fec_cfg;
3156 	int rc;
3157 
3158 	link_info = &bp->link_info;
3159 	fec_cfg = link_info->fec_cfg;
3160 	if (fec_cfg & BNXT_FEC_NONE)
3161 		return -EOPNOTSUPP;
3162 
3163 	if (fec & ETHTOOL_FEC_OFF) {
3164 		new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE |
3165 			  BNXT_FEC_ALL_OFF(link_info);
3166 		goto apply_fec;
3167 	}
3168 	if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) ||
3169 	    ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) ||
3170 	    ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) ||
3171 	    ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP)))
3172 		return -EINVAL;
3173 
3174 	if (fec & ETHTOOL_FEC_AUTO) {
3175 		if (!link_info->autoneg)
3176 			return -EINVAL;
3177 		new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE;
3178 	} else {
3179 		new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec);
3180 	}
3181 
3182 apply_fec:
3183 	rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
3184 	if (rc)
3185 		return rc;
3186 	req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
3187 	rc = hwrm_req_send(bp, req);
3188 	/* update current settings */
3189 	if (!rc) {
3190 		mutex_lock(&bp->link_lock);
3191 		bnxt_update_link(bp, false);
3192 		mutex_unlock(&bp->link_lock);
3193 	}
3194 	return rc;
3195 }
3196 
3197 static void bnxt_get_pauseparam(struct net_device *dev,
3198 				struct ethtool_pauseparam *epause)
3199 {
3200 	struct bnxt *bp = netdev_priv(dev);
3201 	struct bnxt_link_info *link_info = &bp->link_info;
3202 
3203 	if (BNXT_VF(bp))
3204 		return;
3205 	epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL);
3206 	epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX);
3207 	epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX);
3208 }
3209 
3210 static void bnxt_get_pause_stats(struct net_device *dev,
3211 				 struct ethtool_pause_stats *epstat)
3212 {
3213 	struct bnxt *bp = netdev_priv(dev);
3214 	u64 *rx, *tx;
3215 
3216 	if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
3217 		return;
3218 
3219 	rx = bp->port_stats.sw_stats;
3220 	tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
3221 
3222 	epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames);
3223 	epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames);
3224 }
3225 
3226 static int bnxt_set_pauseparam(struct net_device *dev,
3227 			       struct ethtool_pauseparam *epause)
3228 {
3229 	int rc = 0;
3230 	struct bnxt *bp = netdev_priv(dev);
3231 	struct bnxt_link_info *link_info = &bp->link_info;
3232 
3233 	if (!BNXT_PHY_CFG_ABLE(bp) || (bp->phy_flags & BNXT_PHY_FL_NO_PAUSE))
3234 		return -EOPNOTSUPP;
3235 
3236 	mutex_lock(&bp->link_lock);
3237 	if (epause->autoneg) {
3238 		if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
3239 			rc = -EINVAL;
3240 			goto pause_exit;
3241 		}
3242 
3243 		link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
3244 		link_info->req_flow_ctrl = 0;
3245 	} else {
3246 		/* when transition from auto pause to force pause,
3247 		 * force a link change
3248 		 */
3249 		if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
3250 			link_info->force_link_chng = true;
3251 		link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL;
3252 		link_info->req_flow_ctrl = 0;
3253 	}
3254 	if (epause->rx_pause)
3255 		link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX;
3256 
3257 	if (epause->tx_pause)
3258 		link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX;
3259 
3260 	if (netif_running(dev))
3261 		rc = bnxt_hwrm_set_pause(bp);
3262 
3263 pause_exit:
3264 	mutex_unlock(&bp->link_lock);
3265 	return rc;
3266 }
3267 
3268 static u32 bnxt_get_link(struct net_device *dev)
3269 {
3270 	struct bnxt *bp = netdev_priv(dev);
3271 
3272 	/* TODO: handle MF, VF, driver close case */
3273 	return BNXT_LINK_IS_UP(bp);
3274 }
3275 
3276 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp,
3277 			       struct hwrm_nvm_get_dev_info_output *nvm_dev_info)
3278 {
3279 	struct hwrm_nvm_get_dev_info_output *resp;
3280 	struct hwrm_nvm_get_dev_info_input *req;
3281 	int rc;
3282 
3283 	if (BNXT_VF(bp))
3284 		return -EOPNOTSUPP;
3285 
3286 	rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO);
3287 	if (rc)
3288 		return rc;
3289 
3290 	resp = hwrm_req_hold(bp, req);
3291 	rc = hwrm_req_send(bp, req);
3292 	if (!rc)
3293 		memcpy(nvm_dev_info, resp, sizeof(*resp));
3294 	hwrm_req_drop(bp, req);
3295 	return rc;
3296 }
3297 
3298 static void bnxt_print_admin_err(struct bnxt *bp)
3299 {
3300 	netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n");
3301 }
3302 
3303 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
3304 			 u16 ext, u16 *index, u32 *item_length,
3305 			 u32 *data_length);
3306 
3307 int bnxt_flash_nvram(struct net_device *dev, u16 dir_type,
3308 		     u16 dir_ordinal, u16 dir_ext, u16 dir_attr,
3309 		     u32 dir_item_len, const u8 *data,
3310 		     size_t data_len)
3311 {
3312 	struct bnxt *bp = netdev_priv(dev);
3313 	struct hwrm_nvm_write_input *req;
3314 	int rc;
3315 
3316 	rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE);
3317 	if (rc)
3318 		return rc;
3319 
3320 	if (data_len && data) {
3321 		dma_addr_t dma_handle;
3322 		u8 *kmem;
3323 
3324 		kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle);
3325 		if (!kmem) {
3326 			hwrm_req_drop(bp, req);
3327 			return -ENOMEM;
3328 		}
3329 
3330 		req->dir_data_length = cpu_to_le32(data_len);
3331 
3332 		memcpy(kmem, data, data_len);
3333 		req->host_src_addr = cpu_to_le64(dma_handle);
3334 	}
3335 
3336 	hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout);
3337 	req->dir_type = cpu_to_le16(dir_type);
3338 	req->dir_ordinal = cpu_to_le16(dir_ordinal);
3339 	req->dir_ext = cpu_to_le16(dir_ext);
3340 	req->dir_attr = cpu_to_le16(dir_attr);
3341 	req->dir_item_length = cpu_to_le32(dir_item_len);
3342 	rc = hwrm_req_send(bp, req);
3343 
3344 	if (rc == -EACCES)
3345 		bnxt_print_admin_err(bp);
3346 	return rc;
3347 }
3348 
3349 int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type,
3350 			     u8 self_reset, u8 flags)
3351 {
3352 	struct bnxt *bp = netdev_priv(dev);
3353 	struct hwrm_fw_reset_input *req;
3354 	int rc;
3355 
3356 	if (!bnxt_hwrm_reset_permitted(bp)) {
3357 		netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver");
3358 		return -EPERM;
3359 	}
3360 
3361 	rc = hwrm_req_init(bp, req, HWRM_FW_RESET);
3362 	if (rc)
3363 		return rc;
3364 
3365 	req->embedded_proc_type = proc_type;
3366 	req->selfrst_status = self_reset;
3367 	req->flags = flags;
3368 
3369 	if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) {
3370 		rc = hwrm_req_send_silent(bp, req);
3371 	} else {
3372 		rc = hwrm_req_send(bp, req);
3373 		if (rc == -EACCES)
3374 			bnxt_print_admin_err(bp);
3375 	}
3376 	return rc;
3377 }
3378 
3379 static int bnxt_firmware_reset(struct net_device *dev,
3380 			       enum bnxt_nvm_directory_type dir_type)
3381 {
3382 	u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE;
3383 	u8 proc_type, flags = 0;
3384 
3385 	/* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */
3386 	/*       (e.g. when firmware isn't already running) */
3387 	switch (dir_type) {
3388 	case BNX_DIR_TYPE_CHIMP_PATCH:
3389 	case BNX_DIR_TYPE_BOOTCODE:
3390 	case BNX_DIR_TYPE_BOOTCODE_2:
3391 		proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT;
3392 		/* Self-reset ChiMP upon next PCIe reset: */
3393 		self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
3394 		break;
3395 	case BNX_DIR_TYPE_APE_FW:
3396 	case BNX_DIR_TYPE_APE_PATCH:
3397 		proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT;
3398 		/* Self-reset APE upon next PCIe reset: */
3399 		self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
3400 		break;
3401 	case BNX_DIR_TYPE_KONG_FW:
3402 	case BNX_DIR_TYPE_KONG_PATCH:
3403 		proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL;
3404 		break;
3405 	case BNX_DIR_TYPE_BONO_FW:
3406 	case BNX_DIR_TYPE_BONO_PATCH:
3407 		proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE;
3408 		break;
3409 	default:
3410 		return -EINVAL;
3411 	}
3412 
3413 	return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags);
3414 }
3415 
3416 static int bnxt_firmware_reset_chip(struct net_device *dev)
3417 {
3418 	struct bnxt *bp = netdev_priv(dev);
3419 	u8 flags = 0;
3420 
3421 	if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
3422 		flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL;
3423 
3424 	return bnxt_hwrm_firmware_reset(dev,
3425 					FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP,
3426 					FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP,
3427 					flags);
3428 }
3429 
3430 static int bnxt_firmware_reset_ap(struct net_device *dev)
3431 {
3432 	return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP,
3433 					FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE,
3434 					0);
3435 }
3436 
3437 static int bnxt_flash_firmware(struct net_device *dev,
3438 			       u16 dir_type,
3439 			       const u8 *fw_data,
3440 			       size_t fw_size)
3441 {
3442 	int	rc = 0;
3443 	u16	code_type;
3444 	u32	stored_crc;
3445 	u32	calculated_crc;
3446 	struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data;
3447 
3448 	switch (dir_type) {
3449 	case BNX_DIR_TYPE_BOOTCODE:
3450 	case BNX_DIR_TYPE_BOOTCODE_2:
3451 		code_type = CODE_BOOT;
3452 		break;
3453 	case BNX_DIR_TYPE_CHIMP_PATCH:
3454 		code_type = CODE_CHIMP_PATCH;
3455 		break;
3456 	case BNX_DIR_TYPE_APE_FW:
3457 		code_type = CODE_MCTP_PASSTHRU;
3458 		break;
3459 	case BNX_DIR_TYPE_APE_PATCH:
3460 		code_type = CODE_APE_PATCH;
3461 		break;
3462 	case BNX_DIR_TYPE_KONG_FW:
3463 		code_type = CODE_KONG_FW;
3464 		break;
3465 	case BNX_DIR_TYPE_KONG_PATCH:
3466 		code_type = CODE_KONG_PATCH;
3467 		break;
3468 	case BNX_DIR_TYPE_BONO_FW:
3469 		code_type = CODE_BONO_FW;
3470 		break;
3471 	case BNX_DIR_TYPE_BONO_PATCH:
3472 		code_type = CODE_BONO_PATCH;
3473 		break;
3474 	default:
3475 		netdev_err(dev, "Unsupported directory entry type: %u\n",
3476 			   dir_type);
3477 		return -EINVAL;
3478 	}
3479 	if (fw_size < sizeof(struct bnxt_fw_header)) {
3480 		netdev_err(dev, "Invalid firmware file size: %u\n",
3481 			   (unsigned int)fw_size);
3482 		return -EINVAL;
3483 	}
3484 	if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) {
3485 		netdev_err(dev, "Invalid firmware signature: %08X\n",
3486 			   le32_to_cpu(header->signature));
3487 		return -EINVAL;
3488 	}
3489 	if (header->code_type != code_type) {
3490 		netdev_err(dev, "Expected firmware type: %d, read: %d\n",
3491 			   code_type, header->code_type);
3492 		return -EINVAL;
3493 	}
3494 	if (header->device != DEVICE_CUMULUS_FAMILY) {
3495 		netdev_err(dev, "Expected firmware device family %d, read: %d\n",
3496 			   DEVICE_CUMULUS_FAMILY, header->device);
3497 		return -EINVAL;
3498 	}
3499 	/* Confirm the CRC32 checksum of the file: */
3500 	stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
3501 					     sizeof(stored_crc)));
3502 	calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
3503 	if (calculated_crc != stored_crc) {
3504 		netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n",
3505 			   (unsigned long)stored_crc,
3506 			   (unsigned long)calculated_crc);
3507 		return -EINVAL;
3508 	}
3509 	rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
3510 			      0, 0, 0, fw_data, fw_size);
3511 	if (rc == 0)	/* Firmware update successful */
3512 		rc = bnxt_firmware_reset(dev, dir_type);
3513 
3514 	return rc;
3515 }
3516 
3517 static int bnxt_flash_microcode(struct net_device *dev,
3518 				u16 dir_type,
3519 				const u8 *fw_data,
3520 				size_t fw_size)
3521 {
3522 	struct bnxt_ucode_trailer *trailer;
3523 	u32 calculated_crc;
3524 	u32 stored_crc;
3525 	int rc = 0;
3526 
3527 	if (fw_size < sizeof(struct bnxt_ucode_trailer)) {
3528 		netdev_err(dev, "Invalid microcode file size: %u\n",
3529 			   (unsigned int)fw_size);
3530 		return -EINVAL;
3531 	}
3532 	trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size -
3533 						sizeof(*trailer)));
3534 	if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) {
3535 		netdev_err(dev, "Invalid microcode trailer signature: %08X\n",
3536 			   le32_to_cpu(trailer->sig));
3537 		return -EINVAL;
3538 	}
3539 	if (le16_to_cpu(trailer->dir_type) != dir_type) {
3540 		netdev_err(dev, "Expected microcode type: %d, read: %d\n",
3541 			   dir_type, le16_to_cpu(trailer->dir_type));
3542 		return -EINVAL;
3543 	}
3544 	if (le16_to_cpu(trailer->trailer_length) <
3545 		sizeof(struct bnxt_ucode_trailer)) {
3546 		netdev_err(dev, "Invalid microcode trailer length: %d\n",
3547 			   le16_to_cpu(trailer->trailer_length));
3548 		return -EINVAL;
3549 	}
3550 
3551 	/* Confirm the CRC32 checksum of the file: */
3552 	stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
3553 					     sizeof(stored_crc)));
3554 	calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
3555 	if (calculated_crc != stored_crc) {
3556 		netdev_err(dev,
3557 			   "CRC32 (%08lX) does not match calculated: %08lX\n",
3558 			   (unsigned long)stored_crc,
3559 			   (unsigned long)calculated_crc);
3560 		return -EINVAL;
3561 	}
3562 	rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
3563 			      0, 0, 0, fw_data, fw_size);
3564 
3565 	return rc;
3566 }
3567 
3568 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type)
3569 {
3570 	switch (dir_type) {
3571 	case BNX_DIR_TYPE_CHIMP_PATCH:
3572 	case BNX_DIR_TYPE_BOOTCODE:
3573 	case BNX_DIR_TYPE_BOOTCODE_2:
3574 	case BNX_DIR_TYPE_APE_FW:
3575 	case BNX_DIR_TYPE_APE_PATCH:
3576 	case BNX_DIR_TYPE_KONG_FW:
3577 	case BNX_DIR_TYPE_KONG_PATCH:
3578 	case BNX_DIR_TYPE_BONO_FW:
3579 	case BNX_DIR_TYPE_BONO_PATCH:
3580 		return true;
3581 	}
3582 
3583 	return false;
3584 }
3585 
3586 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type)
3587 {
3588 	switch (dir_type) {
3589 	case BNX_DIR_TYPE_AVS:
3590 	case BNX_DIR_TYPE_EXP_ROM_MBA:
3591 	case BNX_DIR_TYPE_PCIE:
3592 	case BNX_DIR_TYPE_TSCF_UCODE:
3593 	case BNX_DIR_TYPE_EXT_PHY:
3594 	case BNX_DIR_TYPE_CCM:
3595 	case BNX_DIR_TYPE_ISCSI_BOOT:
3596 	case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3597 	case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3598 		return true;
3599 	}
3600 
3601 	return false;
3602 }
3603 
3604 static bool bnxt_dir_type_is_executable(u16 dir_type)
3605 {
3606 	return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3607 		bnxt_dir_type_is_other_exec_format(dir_type);
3608 }
3609 
3610 static int bnxt_flash_firmware_from_file(struct net_device *dev,
3611 					 u16 dir_type,
3612 					 const char *filename)
3613 {
3614 	const struct firmware  *fw;
3615 	int			rc;
3616 
3617 	rc = request_firmware(&fw, filename, &dev->dev);
3618 	if (rc != 0) {
3619 		netdev_err(dev, "Error %d requesting firmware file: %s\n",
3620 			   rc, filename);
3621 		return rc;
3622 	}
3623 	if (bnxt_dir_type_is_ape_bin_format(dir_type))
3624 		rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size);
3625 	else if (bnxt_dir_type_is_other_exec_format(dir_type))
3626 		rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size);
3627 	else
3628 		rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
3629 				      0, 0, 0, fw->data, fw->size);
3630 	release_firmware(fw);
3631 	return rc;
3632 }
3633 
3634 #define MSG_INTEGRITY_ERR "PKG install error : Data integrity on NVM"
3635 #define MSG_INVALID_PKG "PKG install error : Invalid package"
3636 #define MSG_AUTHENTICATION_ERR "PKG install error : Authentication error"
3637 #define MSG_INVALID_DEV "PKG install error : Invalid device"
3638 #define MSG_INTERNAL_ERR "PKG install error : Internal error"
3639 #define MSG_NO_PKG_UPDATE_AREA_ERR "PKG update area not created in nvram"
3640 #define MSG_NO_SPACE_ERR "PKG insufficient update area in nvram"
3641 #define MSG_RESIZE_UPDATE_ERR "Resize UPDATE entry error"
3642 #define MSG_ANTI_ROLLBACK_ERR "HWRM_NVM_INSTALL_UPDATE failure due to Anti-rollback detected"
3643 #define MSG_GENERIC_FAILURE_ERR "HWRM_NVM_INSTALL_UPDATE failure"
3644 
3645 static int nvm_update_err_to_stderr(struct net_device *dev, u8 result,
3646 				    struct netlink_ext_ack *extack)
3647 {
3648 	switch (result) {
3649 	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER:
3650 	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER:
3651 	case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR:
3652 	case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR:
3653 	case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND:
3654 	case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED:
3655 		BNXT_NVM_ERR_MSG(dev, extack, MSG_INTEGRITY_ERR);
3656 		return -EINVAL;
3657 	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE:
3658 	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER:
3659 	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE:
3660 	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM:
3661 	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH:
3662 	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST:
3663 	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER:
3664 	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM:
3665 	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM:
3666 	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH:
3667 	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE:
3668 	case NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM:
3669 	case NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM:
3670 		BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_PKG);
3671 		return -ENOPKG;
3672 	case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR:
3673 		BNXT_NVM_ERR_MSG(dev, extack, MSG_AUTHENTICATION_ERR);
3674 		return -EPERM;
3675 	case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV:
3676 	case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID:
3677 	case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR:
3678 	case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID:
3679 	case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM:
3680 		BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_DEV);
3681 		return -EOPNOTSUPP;
3682 	default:
3683 		BNXT_NVM_ERR_MSG(dev, extack, MSG_INTERNAL_ERR);
3684 		return -EIO;
3685 	}
3686 }
3687 
3688 #define BNXT_PKG_DMA_SIZE	0x40000
3689 #define BNXT_NVM_MORE_FLAG	(cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE))
3690 #define BNXT_NVM_LAST_FLAG	(cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST))
3691 
3692 static int bnxt_resize_update_entry(struct net_device *dev, size_t fw_size,
3693 				    struct netlink_ext_ack *extack)
3694 {
3695 	u32 item_len;
3696 	int rc;
3697 
3698 	rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE,
3699 				  BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, NULL,
3700 				  &item_len, NULL);
3701 	if (rc) {
3702 		BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR);
3703 		return rc;
3704 	}
3705 
3706 	if (fw_size > item_len) {
3707 		rc = bnxt_flash_nvram(dev, BNX_DIR_TYPE_UPDATE,
3708 				      BNX_DIR_ORDINAL_FIRST, 0, 1,
3709 				      round_up(fw_size, 4096), NULL, 0);
3710 		if (rc) {
3711 			BNXT_NVM_ERR_MSG(dev, extack, MSG_RESIZE_UPDATE_ERR);
3712 			return rc;
3713 		}
3714 	}
3715 	return 0;
3716 }
3717 
3718 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw,
3719 				   u32 install_type, struct netlink_ext_ack *extack)
3720 {
3721 	struct hwrm_nvm_install_update_input *install;
3722 	struct hwrm_nvm_install_update_output *resp;
3723 	struct hwrm_nvm_modify_input *modify;
3724 	struct bnxt *bp = netdev_priv(dev);
3725 	bool defrag_attempted = false;
3726 	dma_addr_t dma_handle;
3727 	u8 *kmem = NULL;
3728 	u32 modify_len;
3729 	u32 item_len;
3730 	u8 cmd_err;
3731 	u16 index;
3732 	int rc;
3733 
3734 	/* resize before flashing larger image than available space */
3735 	rc = bnxt_resize_update_entry(dev, fw->size, extack);
3736 	if (rc)
3737 		return rc;
3738 
3739 	bnxt_hwrm_fw_set_time(bp);
3740 
3741 	rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY);
3742 	if (rc)
3743 		return rc;
3744 
3745 	/* Try allocating a large DMA buffer first.  Older fw will
3746 	 * cause excessive NVRAM erases when using small blocks.
3747 	 */
3748 	modify_len = roundup_pow_of_two(fw->size);
3749 	modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE);
3750 	while (1) {
3751 		kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle);
3752 		if (!kmem && modify_len > PAGE_SIZE)
3753 			modify_len /= 2;
3754 		else
3755 			break;
3756 	}
3757 	if (!kmem) {
3758 		hwrm_req_drop(bp, modify);
3759 		return -ENOMEM;
3760 	}
3761 
3762 	rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE);
3763 	if (rc) {
3764 		hwrm_req_drop(bp, modify);
3765 		return rc;
3766 	}
3767 
3768 	hwrm_req_timeout(bp, modify, bp->hwrm_cmd_max_timeout);
3769 	hwrm_req_timeout(bp, install, bp->hwrm_cmd_max_timeout);
3770 
3771 	hwrm_req_hold(bp, modify);
3772 	modify->host_src_addr = cpu_to_le64(dma_handle);
3773 
3774 	resp = hwrm_req_hold(bp, install);
3775 	if ((install_type & 0xffff) == 0)
3776 		install_type >>= 16;
3777 	install->install_type = cpu_to_le32(install_type);
3778 
3779 	do {
3780 		u32 copied = 0, len = modify_len;
3781 
3782 		rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE,
3783 					  BNX_DIR_ORDINAL_FIRST,
3784 					  BNX_DIR_EXT_NONE,
3785 					  &index, &item_len, NULL);
3786 		if (rc) {
3787 			BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR);
3788 			break;
3789 		}
3790 		if (fw->size > item_len) {
3791 			BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_SPACE_ERR);
3792 			rc = -EFBIG;
3793 			break;
3794 		}
3795 
3796 		modify->dir_idx = cpu_to_le16(index);
3797 
3798 		if (fw->size > modify_len)
3799 			modify->flags = BNXT_NVM_MORE_FLAG;
3800 		while (copied < fw->size) {
3801 			u32 balance = fw->size - copied;
3802 
3803 			if (balance <= modify_len) {
3804 				len = balance;
3805 				if (copied)
3806 					modify->flags |= BNXT_NVM_LAST_FLAG;
3807 			}
3808 			memcpy(kmem, fw->data + copied, len);
3809 			modify->len = cpu_to_le32(len);
3810 			modify->offset = cpu_to_le32(copied);
3811 			rc = hwrm_req_send(bp, modify);
3812 			if (rc)
3813 				goto pkg_abort;
3814 			copied += len;
3815 		}
3816 
3817 		rc = hwrm_req_send_silent(bp, install);
3818 		if (!rc)
3819 			break;
3820 
3821 		if (defrag_attempted) {
3822 			/* We have tried to defragment already in the previous
3823 			 * iteration. Return with the result for INSTALL_UPDATE
3824 			 */
3825 			break;
3826 		}
3827 
3828 		cmd_err = ((struct hwrm_err_output *)resp)->cmd_err;
3829 
3830 		switch (cmd_err) {
3831 		case NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK:
3832 			BNXT_NVM_ERR_MSG(dev, extack, MSG_ANTI_ROLLBACK_ERR);
3833 			rc = -EALREADY;
3834 			break;
3835 		case NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR:
3836 			install->flags =
3837 				cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG);
3838 
3839 			rc = hwrm_req_send_silent(bp, install);
3840 			if (!rc)
3841 				break;
3842 
3843 			cmd_err = ((struct hwrm_err_output *)resp)->cmd_err;
3844 
3845 			if (cmd_err == NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) {
3846 				/* FW has cleared NVM area, driver will create
3847 				 * UPDATE directory and try the flash again
3848 				 */
3849 				defrag_attempted = true;
3850 				install->flags = 0;
3851 				rc = bnxt_flash_nvram(bp->dev,
3852 						      BNX_DIR_TYPE_UPDATE,
3853 						      BNX_DIR_ORDINAL_FIRST,
3854 						      0, 0, item_len, NULL, 0);
3855 				if (!rc)
3856 					break;
3857 			}
3858 			fallthrough;
3859 		default:
3860 			BNXT_NVM_ERR_MSG(dev, extack, MSG_GENERIC_FAILURE_ERR);
3861 		}
3862 	} while (defrag_attempted && !rc);
3863 
3864 pkg_abort:
3865 	hwrm_req_drop(bp, modify);
3866 	hwrm_req_drop(bp, install);
3867 
3868 	if (resp->result) {
3869 		netdev_err(dev, "PKG install error = %d, problem_item = %d\n",
3870 			   (s8)resp->result, (int)resp->problem_item);
3871 		rc = nvm_update_err_to_stderr(dev, resp->result, extack);
3872 	}
3873 	if (rc == -EACCES)
3874 		bnxt_print_admin_err(bp);
3875 	return rc;
3876 }
3877 
3878 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename,
3879 					u32 install_type, struct netlink_ext_ack *extack)
3880 {
3881 	const struct firmware *fw;
3882 	int rc;
3883 
3884 	rc = request_firmware(&fw, filename, &dev->dev);
3885 	if (rc != 0) {
3886 		netdev_err(dev, "PKG error %d requesting file: %s\n",
3887 			   rc, filename);
3888 		return rc;
3889 	}
3890 
3891 	rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type, extack);
3892 
3893 	release_firmware(fw);
3894 
3895 	return rc;
3896 }
3897 
3898 static int bnxt_flash_device(struct net_device *dev,
3899 			     struct ethtool_flash *flash)
3900 {
3901 	if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) {
3902 		netdev_err(dev, "flashdev not supported from a virtual function\n");
3903 		return -EINVAL;
3904 	}
3905 
3906 	if (flash->region == ETHTOOL_FLASH_ALL_REGIONS ||
3907 	    flash->region > 0xffff)
3908 		return bnxt_flash_package_from_file(dev, flash->data,
3909 						    flash->region, NULL);
3910 
3911 	return bnxt_flash_firmware_from_file(dev, flash->region, flash->data);
3912 }
3913 
3914 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length)
3915 {
3916 	struct hwrm_nvm_get_dir_info_output *output;
3917 	struct hwrm_nvm_get_dir_info_input *req;
3918 	struct bnxt *bp = netdev_priv(dev);
3919 	int rc;
3920 
3921 	rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO);
3922 	if (rc)
3923 		return rc;
3924 
3925 	output = hwrm_req_hold(bp, req);
3926 	rc = hwrm_req_send(bp, req);
3927 	if (!rc) {
3928 		*entries = le32_to_cpu(output->entries);
3929 		*length = le32_to_cpu(output->entry_length);
3930 	}
3931 	hwrm_req_drop(bp, req);
3932 	return rc;
3933 }
3934 
3935 static int bnxt_get_eeprom_len(struct net_device *dev)
3936 {
3937 	struct bnxt *bp = netdev_priv(dev);
3938 
3939 	if (BNXT_VF(bp))
3940 		return 0;
3941 
3942 	/* The -1 return value allows the entire 32-bit range of offsets to be
3943 	 * passed via the ethtool command-line utility.
3944 	 */
3945 	return -1;
3946 }
3947 
3948 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data)
3949 {
3950 	struct bnxt *bp = netdev_priv(dev);
3951 	int rc;
3952 	u32 dir_entries;
3953 	u32 entry_length;
3954 	u8 *buf;
3955 	size_t buflen;
3956 	dma_addr_t dma_handle;
3957 	struct hwrm_nvm_get_dir_entries_input *req;
3958 
3959 	rc = nvm_get_dir_info(dev, &dir_entries, &entry_length);
3960 	if (rc != 0)
3961 		return rc;
3962 
3963 	if (!dir_entries || !entry_length)
3964 		return -EIO;
3965 
3966 	/* Insert 2 bytes of directory info (count and size of entries) */
3967 	if (len < 2)
3968 		return -EINVAL;
3969 
3970 	*data++ = dir_entries;
3971 	*data++ = entry_length;
3972 	len -= 2;
3973 	memset(data, 0xff, len);
3974 
3975 	rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES);
3976 	if (rc)
3977 		return rc;
3978 
3979 	buflen = mul_u32_u32(dir_entries, entry_length);
3980 	buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle);
3981 	if (!buf) {
3982 		hwrm_req_drop(bp, req);
3983 		return -ENOMEM;
3984 	}
3985 	req->host_dest_addr = cpu_to_le64(dma_handle);
3986 
3987 	hwrm_req_hold(bp, req); /* hold the slice */
3988 	rc = hwrm_req_send(bp, req);
3989 	if (rc == 0)
3990 		memcpy(data, buf, len > buflen ? buflen : len);
3991 	hwrm_req_drop(bp, req);
3992 	return rc;
3993 }
3994 
3995 int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset,
3996 			u32 length, u8 *data)
3997 {
3998 	struct bnxt *bp = netdev_priv(dev);
3999 	int rc;
4000 	u8 *buf;
4001 	dma_addr_t dma_handle;
4002 	struct hwrm_nvm_read_input *req;
4003 
4004 	if (!length)
4005 		return -EINVAL;
4006 
4007 	rc = hwrm_req_init(bp, req, HWRM_NVM_READ);
4008 	if (rc)
4009 		return rc;
4010 
4011 	buf = hwrm_req_dma_slice(bp, req, length, &dma_handle);
4012 	if (!buf) {
4013 		hwrm_req_drop(bp, req);
4014 		return -ENOMEM;
4015 	}
4016 
4017 	req->host_dest_addr = cpu_to_le64(dma_handle);
4018 	req->dir_idx = cpu_to_le16(index);
4019 	req->offset = cpu_to_le32(offset);
4020 	req->len = cpu_to_le32(length);
4021 
4022 	hwrm_req_hold(bp, req); /* hold the slice */
4023 	rc = hwrm_req_send(bp, req);
4024 	if (rc == 0)
4025 		memcpy(data, buf, length);
4026 	hwrm_req_drop(bp, req);
4027 	return rc;
4028 }
4029 
4030 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
4031 			 u16 ext, u16 *index, u32 *item_length,
4032 			 u32 *data_length)
4033 {
4034 	struct hwrm_nvm_find_dir_entry_output *output;
4035 	struct hwrm_nvm_find_dir_entry_input *req;
4036 	struct bnxt *bp = netdev_priv(dev);
4037 	int rc;
4038 
4039 	rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY);
4040 	if (rc)
4041 		return rc;
4042 
4043 	req->enables = 0;
4044 	req->dir_idx = 0;
4045 	req->dir_type = cpu_to_le16(type);
4046 	req->dir_ordinal = cpu_to_le16(ordinal);
4047 	req->dir_ext = cpu_to_le16(ext);
4048 	req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ;
4049 	output = hwrm_req_hold(bp, req);
4050 	rc = hwrm_req_send_silent(bp, req);
4051 	if (rc == 0) {
4052 		if (index)
4053 			*index = le16_to_cpu(output->dir_idx);
4054 		if (item_length)
4055 			*item_length = le32_to_cpu(output->dir_item_length);
4056 		if (data_length)
4057 			*data_length = le32_to_cpu(output->dir_data_length);
4058 	}
4059 	hwrm_req_drop(bp, req);
4060 	return rc;
4061 }
4062 
4063 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen)
4064 {
4065 	char	*retval = NULL;
4066 	char	*p;
4067 	char	*value;
4068 	int	field = 0;
4069 
4070 	if (datalen < 1)
4071 		return NULL;
4072 	/* null-terminate the log data (removing last '\n'): */
4073 	data[datalen - 1] = 0;
4074 	for (p = data; *p != 0; p++) {
4075 		field = 0;
4076 		retval = NULL;
4077 		while (*p != 0 && *p != '\n') {
4078 			value = p;
4079 			while (*p != 0 && *p != '\t' && *p != '\n')
4080 				p++;
4081 			if (field == desired_field)
4082 				retval = value;
4083 			if (*p != '\t')
4084 				break;
4085 			*p = 0;
4086 			field++;
4087 			p++;
4088 		}
4089 		if (*p == 0)
4090 			break;
4091 		*p = 0;
4092 	}
4093 	return retval;
4094 }
4095 
4096 int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size)
4097 {
4098 	struct bnxt *bp = netdev_priv(dev);
4099 	u16 index = 0;
4100 	char *pkgver;
4101 	u32 pkglen;
4102 	u8 *pkgbuf;
4103 	int rc;
4104 
4105 	rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG,
4106 				  BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE,
4107 				  &index, NULL, &pkglen);
4108 	if (rc)
4109 		return rc;
4110 
4111 	pkgbuf = kzalloc(pkglen, GFP_KERNEL);
4112 	if (!pkgbuf) {
4113 		dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n",
4114 			pkglen);
4115 		return -ENOMEM;
4116 	}
4117 
4118 	rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf);
4119 	if (rc)
4120 		goto err;
4121 
4122 	pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf,
4123 				   pkglen);
4124 	if (pkgver && *pkgver != 0 && isdigit(*pkgver))
4125 		strscpy(ver, pkgver, size);
4126 	else
4127 		rc = -ENOENT;
4128 
4129 err:
4130 	kfree(pkgbuf);
4131 
4132 	return rc;
4133 }
4134 
4135 static void bnxt_get_pkgver(struct net_device *dev)
4136 {
4137 	struct bnxt *bp = netdev_priv(dev);
4138 	char buf[FW_VER_STR_LEN];
4139 	int len;
4140 
4141 	if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) {
4142 		len = strlen(bp->fw_ver_str);
4143 		snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1,
4144 			 "/pkg %s", buf);
4145 	}
4146 }
4147 
4148 static int bnxt_get_eeprom(struct net_device *dev,
4149 			   struct ethtool_eeprom *eeprom,
4150 			   u8 *data)
4151 {
4152 	u32 index;
4153 	u32 offset;
4154 
4155 	if (eeprom->offset == 0) /* special offset value to get directory */
4156 		return bnxt_get_nvram_directory(dev, eeprom->len, data);
4157 
4158 	index = eeprom->offset >> 24;
4159 	offset = eeprom->offset & 0xffffff;
4160 
4161 	if (index == 0) {
4162 		netdev_err(dev, "unsupported index value: %d\n", index);
4163 		return -EINVAL;
4164 	}
4165 
4166 	return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data);
4167 }
4168 
4169 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index)
4170 {
4171 	struct hwrm_nvm_erase_dir_entry_input *req;
4172 	struct bnxt *bp = netdev_priv(dev);
4173 	int rc;
4174 
4175 	rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY);
4176 	if (rc)
4177 		return rc;
4178 
4179 	req->dir_idx = cpu_to_le16(index);
4180 	return hwrm_req_send(bp, req);
4181 }
4182 
4183 static int bnxt_set_eeprom(struct net_device *dev,
4184 			   struct ethtool_eeprom *eeprom,
4185 			   u8 *data)
4186 {
4187 	struct bnxt *bp = netdev_priv(dev);
4188 	u8 index, dir_op;
4189 	u16 type, ext, ordinal, attr;
4190 
4191 	if (!BNXT_PF(bp)) {
4192 		netdev_err(dev, "NVM write not supported from a virtual function\n");
4193 		return -EINVAL;
4194 	}
4195 
4196 	type = eeprom->magic >> 16;
4197 
4198 	if (type == 0xffff) { /* special value for directory operations */
4199 		index = eeprom->magic & 0xff;
4200 		dir_op = eeprom->magic >> 8;
4201 		if (index == 0)
4202 			return -EINVAL;
4203 		switch (dir_op) {
4204 		case 0x0e: /* erase */
4205 			if (eeprom->offset != ~eeprom->magic)
4206 				return -EINVAL;
4207 			return bnxt_erase_nvram_directory(dev, index - 1);
4208 		default:
4209 			return -EINVAL;
4210 		}
4211 	}
4212 
4213 	/* Create or re-write an NVM item: */
4214 	if (bnxt_dir_type_is_executable(type))
4215 		return -EOPNOTSUPP;
4216 	ext = eeprom->magic & 0xffff;
4217 	ordinal = eeprom->offset >> 16;
4218 	attr = eeprom->offset & 0xffff;
4219 
4220 	return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data,
4221 				eeprom->len);
4222 }
4223 
4224 static int bnxt_set_eee(struct net_device *dev, struct ethtool_keee *edata)
4225 {
4226 	__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
4227 	__ETHTOOL_DECLARE_LINK_MODE_MASK(tmp);
4228 	struct bnxt *bp = netdev_priv(dev);
4229 	struct ethtool_keee *eee = &bp->eee;
4230 	struct bnxt_link_info *link_info = &bp->link_info;
4231 	int rc = 0;
4232 
4233 	if (!BNXT_PHY_CFG_ABLE(bp))
4234 		return -EOPNOTSUPP;
4235 
4236 	if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP))
4237 		return -EOPNOTSUPP;
4238 
4239 	mutex_lock(&bp->link_lock);
4240 	_bnxt_fw_to_linkmode(advertising, link_info->advertising);
4241 	if (!edata->eee_enabled)
4242 		goto eee_ok;
4243 
4244 	if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
4245 		netdev_warn(dev, "EEE requires autoneg\n");
4246 		rc = -EINVAL;
4247 		goto eee_exit;
4248 	}
4249 	if (edata->tx_lpi_enabled) {
4250 		if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi ||
4251 				       edata->tx_lpi_timer < bp->lpi_tmr_lo)) {
4252 			netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n",
4253 				    bp->lpi_tmr_lo, bp->lpi_tmr_hi);
4254 			rc = -EINVAL;
4255 			goto eee_exit;
4256 		} else if (!bp->lpi_tmr_hi) {
4257 			edata->tx_lpi_timer = eee->tx_lpi_timer;
4258 		}
4259 	}
4260 	if (linkmode_empty(edata->advertised)) {
4261 		linkmode_and(edata->advertised, advertising, eee->supported);
4262 	} else if (linkmode_andnot(tmp, edata->advertised, advertising)) {
4263 		netdev_warn(dev, "EEE advertised must be a subset of autoneg advertised speeds\n");
4264 		rc = -EINVAL;
4265 		goto eee_exit;
4266 	}
4267 
4268 	linkmode_copy(eee->advertised, edata->advertised);
4269 	eee->tx_lpi_enabled = edata->tx_lpi_enabled;
4270 	eee->tx_lpi_timer = edata->tx_lpi_timer;
4271 eee_ok:
4272 	eee->eee_enabled = edata->eee_enabled;
4273 
4274 	if (netif_running(dev))
4275 		rc = bnxt_hwrm_set_link_setting(bp, false, true);
4276 
4277 eee_exit:
4278 	mutex_unlock(&bp->link_lock);
4279 	return rc;
4280 }
4281 
4282 static int bnxt_get_eee(struct net_device *dev, struct ethtool_keee *edata)
4283 {
4284 	struct bnxt *bp = netdev_priv(dev);
4285 
4286 	if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP))
4287 		return -EOPNOTSUPP;
4288 
4289 	*edata = bp->eee;
4290 	if (!bp->eee.eee_enabled) {
4291 		/* Preserve tx_lpi_timer so that the last value will be used
4292 		 * by default when it is re-enabled.
4293 		 */
4294 		linkmode_zero(edata->advertised);
4295 		edata->tx_lpi_enabled = 0;
4296 	}
4297 
4298 	if (!bp->eee.eee_active)
4299 		linkmode_zero(edata->lp_advertised);
4300 
4301 	return 0;
4302 }
4303 
4304 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr,
4305 					    u16 page_number, u8 bank,
4306 					    u16 start_addr, u16 data_length,
4307 					    u8 *buf)
4308 {
4309 	struct hwrm_port_phy_i2c_read_output *output;
4310 	struct hwrm_port_phy_i2c_read_input *req;
4311 	int rc, byte_offset = 0;
4312 
4313 	rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ);
4314 	if (rc)
4315 		return rc;
4316 
4317 	output = hwrm_req_hold(bp, req);
4318 	req->i2c_slave_addr = i2c_addr;
4319 	req->page_number = cpu_to_le16(page_number);
4320 	req->port_id = cpu_to_le16(bp->pf.port_id);
4321 	do {
4322 		u16 xfer_size;
4323 
4324 		xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
4325 		data_length -= xfer_size;
4326 		req->page_offset = cpu_to_le16(start_addr + byte_offset);
4327 		req->data_length = xfer_size;
4328 		req->enables =
4329 			cpu_to_le32((start_addr + byte_offset ?
4330 				     PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET :
4331 				     0) |
4332 				    (bank ?
4333 				     PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER :
4334 				     0));
4335 		rc = hwrm_req_send(bp, req);
4336 		if (!rc)
4337 			memcpy(buf + byte_offset, output->data, xfer_size);
4338 		byte_offset += xfer_size;
4339 	} while (!rc && data_length > 0);
4340 	hwrm_req_drop(bp, req);
4341 
4342 	return rc;
4343 }
4344 
4345 static int bnxt_get_module_info(struct net_device *dev,
4346 				struct ethtool_modinfo *modinfo)
4347 {
4348 	u8 data[SFF_DIAG_SUPPORT_OFFSET + 1];
4349 	struct bnxt *bp = netdev_priv(dev);
4350 	int rc;
4351 
4352 	/* No point in going further if phy status indicates
4353 	 * module is not inserted or if it is powered down or
4354 	 * if it is of type 10GBase-T
4355 	 */
4356 	if (bp->link_info.module_status >
4357 		PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG)
4358 		return -EOPNOTSUPP;
4359 
4360 	/* This feature is not supported in older firmware versions */
4361 	if (bp->hwrm_spec_code < 0x10202)
4362 		return -EOPNOTSUPP;
4363 
4364 	rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 0,
4365 					      SFF_DIAG_SUPPORT_OFFSET + 1,
4366 					      data);
4367 	if (!rc) {
4368 		u8 module_id = data[0];
4369 		u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET];
4370 
4371 		switch (module_id) {
4372 		case SFF_MODULE_ID_SFP:
4373 			modinfo->type = ETH_MODULE_SFF_8472;
4374 			modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
4375 			if (!diag_supported)
4376 				modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
4377 			break;
4378 		case SFF_MODULE_ID_QSFP:
4379 		case SFF_MODULE_ID_QSFP_PLUS:
4380 			modinfo->type = ETH_MODULE_SFF_8436;
4381 			modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
4382 			break;
4383 		case SFF_MODULE_ID_QSFP28:
4384 			modinfo->type = ETH_MODULE_SFF_8636;
4385 			modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
4386 			break;
4387 		default:
4388 			rc = -EOPNOTSUPP;
4389 			break;
4390 		}
4391 	}
4392 	return rc;
4393 }
4394 
4395 static int bnxt_get_module_eeprom(struct net_device *dev,
4396 				  struct ethtool_eeprom *eeprom,
4397 				  u8 *data)
4398 {
4399 	struct bnxt *bp = netdev_priv(dev);
4400 	u16  start = eeprom->offset, length = eeprom->len;
4401 	int rc = 0;
4402 
4403 	memset(data, 0, eeprom->len);
4404 
4405 	/* Read A0 portion of the EEPROM */
4406 	if (start < ETH_MODULE_SFF_8436_LEN) {
4407 		if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN)
4408 			length = ETH_MODULE_SFF_8436_LEN - start;
4409 		rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
4410 						      start, length, data);
4411 		if (rc)
4412 			return rc;
4413 		start += length;
4414 		data += length;
4415 		length = eeprom->len - length;
4416 	}
4417 
4418 	/* Read A2 portion of the EEPROM */
4419 	if (length) {
4420 		start -= ETH_MODULE_SFF_8436_LEN;
4421 		rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 0,
4422 						      start, length, data);
4423 	}
4424 	return rc;
4425 }
4426 
4427 static int bnxt_get_module_status(struct bnxt *bp, struct netlink_ext_ack *extack)
4428 {
4429 	if (bp->link_info.module_status <=
4430 	    PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG)
4431 		return 0;
4432 
4433 	switch (bp->link_info.module_status) {
4434 	case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
4435 		NL_SET_ERR_MSG_MOD(extack, "Transceiver module is powering down");
4436 		break;
4437 	case PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED:
4438 		NL_SET_ERR_MSG_MOD(extack, "Transceiver module not inserted");
4439 		break;
4440 	case PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT:
4441 		NL_SET_ERR_MSG_MOD(extack, "Transceiver module disabled due to current fault");
4442 		break;
4443 	default:
4444 		NL_SET_ERR_MSG_MOD(extack, "Unknown error");
4445 		break;
4446 	}
4447 	return -EINVAL;
4448 }
4449 
4450 static int bnxt_get_module_eeprom_by_page(struct net_device *dev,
4451 					  const struct ethtool_module_eeprom *page_data,
4452 					  struct netlink_ext_ack *extack)
4453 {
4454 	struct bnxt *bp = netdev_priv(dev);
4455 	int rc;
4456 
4457 	rc = bnxt_get_module_status(bp, extack);
4458 	if (rc)
4459 		return rc;
4460 
4461 	if (bp->hwrm_spec_code < 0x10202) {
4462 		NL_SET_ERR_MSG_MOD(extack, "Firmware version too old");
4463 		return -EINVAL;
4464 	}
4465 
4466 	if (page_data->bank && !(bp->phy_flags & BNXT_PHY_FL_BANK_SEL)) {
4467 		NL_SET_ERR_MSG_MOD(extack, "Firmware not capable for bank selection");
4468 		return -EINVAL;
4469 	}
4470 
4471 	rc = bnxt_read_sfp_module_eeprom_info(bp, page_data->i2c_address << 1,
4472 					      page_data->page, page_data->bank,
4473 					      page_data->offset,
4474 					      page_data->length,
4475 					      page_data->data);
4476 	if (rc) {
4477 		NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom read failed");
4478 		return rc;
4479 	}
4480 	return page_data->length;
4481 }
4482 
4483 static int bnxt_nway_reset(struct net_device *dev)
4484 {
4485 	int rc = 0;
4486 
4487 	struct bnxt *bp = netdev_priv(dev);
4488 	struct bnxt_link_info *link_info = &bp->link_info;
4489 
4490 	if (!BNXT_PHY_CFG_ABLE(bp))
4491 		return -EOPNOTSUPP;
4492 
4493 	if (!(link_info->autoneg & BNXT_AUTONEG_SPEED))
4494 		return -EINVAL;
4495 
4496 	if (netif_running(dev))
4497 		rc = bnxt_hwrm_set_link_setting(bp, true, false);
4498 
4499 	return rc;
4500 }
4501 
4502 static int bnxt_set_phys_id(struct net_device *dev,
4503 			    enum ethtool_phys_id_state state)
4504 {
4505 	struct hwrm_port_led_cfg_input *req;
4506 	struct bnxt *bp = netdev_priv(dev);
4507 	struct bnxt_pf_info *pf = &bp->pf;
4508 	struct bnxt_led_cfg *led_cfg;
4509 	u8 led_state;
4510 	__le16 duration;
4511 	int rc, i;
4512 
4513 	if (!bp->num_leds || BNXT_VF(bp))
4514 		return -EOPNOTSUPP;
4515 
4516 	if (state == ETHTOOL_ID_ACTIVE) {
4517 		led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT;
4518 		duration = cpu_to_le16(500);
4519 	} else if (state == ETHTOOL_ID_INACTIVE) {
4520 		led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT;
4521 		duration = cpu_to_le16(0);
4522 	} else {
4523 		return -EINVAL;
4524 	}
4525 	rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG);
4526 	if (rc)
4527 		return rc;
4528 
4529 	req->port_id = cpu_to_le16(pf->port_id);
4530 	req->num_leds = bp->num_leds;
4531 	led_cfg = (struct bnxt_led_cfg *)&req->led0_id;
4532 	for (i = 0; i < bp->num_leds; i++, led_cfg++) {
4533 		req->enables |= BNXT_LED_DFLT_ENABLES(i);
4534 		led_cfg->led_id = bp->leds[i].led_id;
4535 		led_cfg->led_state = led_state;
4536 		led_cfg->led_blink_on = duration;
4537 		led_cfg->led_blink_off = duration;
4538 		led_cfg->led_group_id = bp->leds[i].led_group_id;
4539 	}
4540 	return hwrm_req_send(bp, req);
4541 }
4542 
4543 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring)
4544 {
4545 	struct hwrm_selftest_irq_input *req;
4546 	int rc;
4547 
4548 	rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ);
4549 	if (rc)
4550 		return rc;
4551 
4552 	req->cmpl_ring = cpu_to_le16(cmpl_ring);
4553 	return hwrm_req_send(bp, req);
4554 }
4555 
4556 static int bnxt_test_irq(struct bnxt *bp)
4557 {
4558 	int i;
4559 
4560 	for (i = 0; i < bp->cp_nr_rings; i++) {
4561 		u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id;
4562 		int rc;
4563 
4564 		rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring);
4565 		if (rc)
4566 			return rc;
4567 	}
4568 	return 0;
4569 }
4570 
4571 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable)
4572 {
4573 	struct hwrm_port_mac_cfg_input *req;
4574 	int rc;
4575 
4576 	rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG);
4577 	if (rc)
4578 		return rc;
4579 
4580 	req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK);
4581 	if (enable)
4582 		req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL;
4583 	else
4584 		req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE;
4585 	return hwrm_req_send(bp, req);
4586 }
4587 
4588 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds)
4589 {
4590 	struct hwrm_port_phy_qcaps_output *resp;
4591 	struct hwrm_port_phy_qcaps_input *req;
4592 	int rc;
4593 
4594 	rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS);
4595 	if (rc)
4596 		return rc;
4597 
4598 	resp = hwrm_req_hold(bp, req);
4599 	rc = hwrm_req_send(bp, req);
4600 	if (!rc)
4601 		*force_speeds = le16_to_cpu(resp->supported_speeds_force_mode);
4602 
4603 	hwrm_req_drop(bp, req);
4604 	return rc;
4605 }
4606 
4607 static int bnxt_disable_an_for_lpbk(struct bnxt *bp,
4608 				    struct hwrm_port_phy_cfg_input *req)
4609 {
4610 	struct bnxt_link_info *link_info = &bp->link_info;
4611 	u16 fw_advertising;
4612 	u16 fw_speed;
4613 	int rc;
4614 
4615 	if (!link_info->autoneg ||
4616 	    (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK))
4617 		return 0;
4618 
4619 	rc = bnxt_query_force_speeds(bp, &fw_advertising);
4620 	if (rc)
4621 		return rc;
4622 
4623 	fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
4624 	if (BNXT_LINK_IS_UP(bp))
4625 		fw_speed = bp->link_info.link_speed;
4626 	else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB)
4627 		fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
4628 	else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB)
4629 		fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
4630 	else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB)
4631 		fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
4632 	else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB)
4633 		fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
4634 
4635 	req->force_link_speed = cpu_to_le16(fw_speed);
4636 	req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE |
4637 				  PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
4638 	rc = hwrm_req_send(bp, req);
4639 	req->flags = 0;
4640 	req->force_link_speed = cpu_to_le16(0);
4641 	return rc;
4642 }
4643 
4644 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext)
4645 {
4646 	struct hwrm_port_phy_cfg_input *req;
4647 	int rc;
4648 
4649 	rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
4650 	if (rc)
4651 		return rc;
4652 
4653 	/* prevent bnxt_disable_an_for_lpbk() from consuming the request */
4654 	hwrm_req_hold(bp, req);
4655 
4656 	if (enable) {
4657 		bnxt_disable_an_for_lpbk(bp, req);
4658 		if (ext)
4659 			req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL;
4660 		else
4661 			req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL;
4662 	} else {
4663 		req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE;
4664 	}
4665 	req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK);
4666 	rc = hwrm_req_send(bp, req);
4667 	hwrm_req_drop(bp, req);
4668 	return rc;
4669 }
4670 
4671 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
4672 			    u32 raw_cons, int pkt_size)
4673 {
4674 	struct bnxt_napi *bnapi = cpr->bnapi;
4675 	struct bnxt_rx_ring_info *rxr;
4676 	struct bnxt_sw_rx_bd *rx_buf;
4677 	struct rx_cmp *rxcmp;
4678 	u16 cp_cons, cons;
4679 	u8 *data;
4680 	u32 len;
4681 	int i;
4682 
4683 	rxr = bnapi->rx_ring;
4684 	cp_cons = RING_CMP(raw_cons);
4685 	rxcmp = (struct rx_cmp *)
4686 		&cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
4687 	cons = rxcmp->rx_cmp_opaque;
4688 	rx_buf = &rxr->rx_buf_ring[cons];
4689 	data = rx_buf->data_ptr;
4690 	len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
4691 	if (len != pkt_size)
4692 		return -EIO;
4693 	i = ETH_ALEN;
4694 	if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr))
4695 		return -EIO;
4696 	i += ETH_ALEN;
4697 	for (  ; i < pkt_size; i++) {
4698 		if (data[i] != (u8)(i & 0xff))
4699 			return -EIO;
4700 	}
4701 	return 0;
4702 }
4703 
4704 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
4705 			      int pkt_size)
4706 {
4707 	struct tx_cmp *txcmp;
4708 	int rc = -EIO;
4709 	u32 raw_cons;
4710 	u32 cons;
4711 	int i;
4712 
4713 	raw_cons = cpr->cp_raw_cons;
4714 	for (i = 0; i < 200; i++) {
4715 		cons = RING_CMP(raw_cons);
4716 		txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
4717 
4718 		if (!TX_CMP_VALID(txcmp, raw_cons)) {
4719 			udelay(5);
4720 			continue;
4721 		}
4722 
4723 		/* The valid test of the entry must be done first before
4724 		 * reading any further.
4725 		 */
4726 		dma_rmb();
4727 		if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP ||
4728 		    TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_V3_CMP) {
4729 			rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size);
4730 			raw_cons = NEXT_RAW_CMP(raw_cons);
4731 			raw_cons = NEXT_RAW_CMP(raw_cons);
4732 			break;
4733 		}
4734 		raw_cons = NEXT_RAW_CMP(raw_cons);
4735 	}
4736 	cpr->cp_raw_cons = raw_cons;
4737 	return rc;
4738 }
4739 
4740 static int bnxt_run_loopback(struct bnxt *bp)
4741 {
4742 	struct bnxt_tx_ring_info *txr = &bp->tx_ring[0];
4743 	struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4744 	struct bnxt_cp_ring_info *cpr;
4745 	int pkt_size, i = 0;
4746 	struct sk_buff *skb;
4747 	dma_addr_t map;
4748 	u8 *data;
4749 	int rc;
4750 
4751 	cpr = &rxr->bnapi->cp_ring;
4752 	if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
4753 		cpr = rxr->rx_cpr;
4754 	pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh);
4755 	skb = netdev_alloc_skb(bp->dev, pkt_size);
4756 	if (!skb)
4757 		return -ENOMEM;
4758 	data = skb_put(skb, pkt_size);
4759 	ether_addr_copy(&data[i], bp->dev->dev_addr);
4760 	i += ETH_ALEN;
4761 	ether_addr_copy(&data[i], bp->dev->dev_addr);
4762 	i += ETH_ALEN;
4763 	for ( ; i < pkt_size; i++)
4764 		data[i] = (u8)(i & 0xff);
4765 
4766 	map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
4767 			     DMA_TO_DEVICE);
4768 	if (dma_mapping_error(&bp->pdev->dev, map)) {
4769 		dev_kfree_skb(skb);
4770 		return -EIO;
4771 	}
4772 	bnxt_xmit_bd(bp, txr, map, pkt_size, NULL);
4773 
4774 	/* Sync BD data before updating doorbell */
4775 	wmb();
4776 
4777 	bnxt_db_write(bp, &txr->tx_db, txr->tx_prod);
4778 	rc = bnxt_poll_loopback(bp, cpr, pkt_size);
4779 
4780 	dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE);
4781 	dev_kfree_skb(skb);
4782 	return rc;
4783 }
4784 
4785 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results)
4786 {
4787 	struct hwrm_selftest_exec_output *resp;
4788 	struct hwrm_selftest_exec_input *req;
4789 	int rc;
4790 
4791 	rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC);
4792 	if (rc)
4793 		return rc;
4794 
4795 	hwrm_req_timeout(bp, req, bp->test_info->timeout);
4796 	req->flags = test_mask;
4797 
4798 	resp = hwrm_req_hold(bp, req);
4799 	rc = hwrm_req_send(bp, req);
4800 	*test_results = resp->test_success;
4801 	hwrm_req_drop(bp, req);
4802 	return rc;
4803 }
4804 
4805 #define BNXT_DRV_TESTS			4
4806 #define BNXT_MACLPBK_TEST_IDX		(bp->num_tests - BNXT_DRV_TESTS)
4807 #define BNXT_PHYLPBK_TEST_IDX		(BNXT_MACLPBK_TEST_IDX + 1)
4808 #define BNXT_EXTLPBK_TEST_IDX		(BNXT_MACLPBK_TEST_IDX + 2)
4809 #define BNXT_IRQ_TEST_IDX		(BNXT_MACLPBK_TEST_IDX + 3)
4810 
4811 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest,
4812 			   u64 *buf)
4813 {
4814 	struct bnxt *bp = netdev_priv(dev);
4815 	bool do_ext_lpbk = false;
4816 	bool offline = false;
4817 	u8 test_results = 0;
4818 	u8 test_mask = 0;
4819 	int rc = 0, i;
4820 
4821 	if (!bp->num_tests || !BNXT_PF(bp))
4822 		return;
4823 
4824 	if (etest->flags & ETH_TEST_FL_OFFLINE &&
4825 	    bnxt_ulp_registered(bp->edev)) {
4826 		etest->flags |= ETH_TEST_FL_FAILED;
4827 		netdev_warn(dev, "Offline tests cannot be run with RoCE driver loaded\n");
4828 		return;
4829 	}
4830 
4831 	memset(buf, 0, sizeof(u64) * bp->num_tests);
4832 	if (!netif_running(dev)) {
4833 		etest->flags |= ETH_TEST_FL_FAILED;
4834 		return;
4835 	}
4836 
4837 	if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) &&
4838 	    (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK))
4839 		do_ext_lpbk = true;
4840 
4841 	if (etest->flags & ETH_TEST_FL_OFFLINE) {
4842 		if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) {
4843 			etest->flags |= ETH_TEST_FL_FAILED;
4844 			netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n");
4845 			return;
4846 		}
4847 		offline = true;
4848 	}
4849 
4850 	for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
4851 		u8 bit_val = 1 << i;
4852 
4853 		if (!(bp->test_info->offline_mask & bit_val))
4854 			test_mask |= bit_val;
4855 		else if (offline)
4856 			test_mask |= bit_val;
4857 	}
4858 	if (!offline) {
4859 		bnxt_run_fw_tests(bp, test_mask, &test_results);
4860 	} else {
4861 		bnxt_close_nic(bp, true, false);
4862 		bnxt_run_fw_tests(bp, test_mask, &test_results);
4863 
4864 		buf[BNXT_MACLPBK_TEST_IDX] = 1;
4865 		bnxt_hwrm_mac_loopback(bp, true);
4866 		msleep(250);
4867 		rc = bnxt_half_open_nic(bp);
4868 		if (rc) {
4869 			bnxt_hwrm_mac_loopback(bp, false);
4870 			etest->flags |= ETH_TEST_FL_FAILED;
4871 			return;
4872 		}
4873 		if (bnxt_run_loopback(bp))
4874 			etest->flags |= ETH_TEST_FL_FAILED;
4875 		else
4876 			buf[BNXT_MACLPBK_TEST_IDX] = 0;
4877 
4878 		bnxt_hwrm_mac_loopback(bp, false);
4879 		bnxt_hwrm_phy_loopback(bp, true, false);
4880 		msleep(1000);
4881 		if (bnxt_run_loopback(bp)) {
4882 			buf[BNXT_PHYLPBK_TEST_IDX] = 1;
4883 			etest->flags |= ETH_TEST_FL_FAILED;
4884 		}
4885 		if (do_ext_lpbk) {
4886 			etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
4887 			bnxt_hwrm_phy_loopback(bp, true, true);
4888 			msleep(1000);
4889 			if (bnxt_run_loopback(bp)) {
4890 				buf[BNXT_EXTLPBK_TEST_IDX] = 1;
4891 				etest->flags |= ETH_TEST_FL_FAILED;
4892 			}
4893 		}
4894 		bnxt_hwrm_phy_loopback(bp, false, false);
4895 		bnxt_half_close_nic(bp);
4896 		rc = bnxt_open_nic(bp, true, true);
4897 	}
4898 	if (rc || bnxt_test_irq(bp)) {
4899 		buf[BNXT_IRQ_TEST_IDX] = 1;
4900 		etest->flags |= ETH_TEST_FL_FAILED;
4901 	}
4902 	for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
4903 		u8 bit_val = 1 << i;
4904 
4905 		if ((test_mask & bit_val) && !(test_results & bit_val)) {
4906 			buf[i] = 1;
4907 			etest->flags |= ETH_TEST_FL_FAILED;
4908 		}
4909 	}
4910 }
4911 
4912 static int bnxt_reset(struct net_device *dev, u32 *flags)
4913 {
4914 	struct bnxt *bp = netdev_priv(dev);
4915 	bool reload = false;
4916 	u32 req = *flags;
4917 
4918 	if (!req)
4919 		return -EINVAL;
4920 
4921 	if (!BNXT_PF(bp)) {
4922 		netdev_err(dev, "Reset is not supported from a VF\n");
4923 		return -EOPNOTSUPP;
4924 	}
4925 
4926 	if (pci_vfs_assigned(bp->pdev) &&
4927 	    !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) {
4928 		netdev_err(dev,
4929 			   "Reset not allowed when VFs are assigned to VMs\n");
4930 		return -EBUSY;
4931 	}
4932 
4933 	if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) {
4934 		/* This feature is not supported in older firmware versions */
4935 		if (bp->hwrm_spec_code >= 0x10803) {
4936 			if (!bnxt_firmware_reset_chip(dev)) {
4937 				netdev_info(dev, "Firmware reset request successful.\n");
4938 				if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET))
4939 					reload = true;
4940 				*flags &= ~BNXT_FW_RESET_CHIP;
4941 			}
4942 		} else if (req == BNXT_FW_RESET_CHIP) {
4943 			return -EOPNOTSUPP; /* only request, fail hard */
4944 		}
4945 	}
4946 
4947 	if (!BNXT_CHIP_P4_PLUS(bp) && (req & BNXT_FW_RESET_AP)) {
4948 		/* This feature is not supported in older firmware versions */
4949 		if (bp->hwrm_spec_code >= 0x10803) {
4950 			if (!bnxt_firmware_reset_ap(dev)) {
4951 				netdev_info(dev, "Reset application processor successful.\n");
4952 				reload = true;
4953 				*flags &= ~BNXT_FW_RESET_AP;
4954 			}
4955 		} else if (req == BNXT_FW_RESET_AP) {
4956 			return -EOPNOTSUPP; /* only request, fail hard */
4957 		}
4958 	}
4959 
4960 	if (reload)
4961 		netdev_info(dev, "Reload driver to complete reset\n");
4962 
4963 	return 0;
4964 }
4965 
4966 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump)
4967 {
4968 	struct bnxt *bp = netdev_priv(dev);
4969 
4970 	if (dump->flag > BNXT_DUMP_CRASH) {
4971 		netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n");
4972 		return -EINVAL;
4973 	}
4974 
4975 	if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) {
4976 		netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n");
4977 		return -EOPNOTSUPP;
4978 	}
4979 
4980 	bp->dump_flag = dump->flag;
4981 	return 0;
4982 }
4983 
4984 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump)
4985 {
4986 	struct bnxt *bp = netdev_priv(dev);
4987 
4988 	if (bp->hwrm_spec_code < 0x10801)
4989 		return -EOPNOTSUPP;
4990 
4991 	dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 |
4992 			bp->ver_resp.hwrm_fw_min_8b << 16 |
4993 			bp->ver_resp.hwrm_fw_bld_8b << 8 |
4994 			bp->ver_resp.hwrm_fw_rsvd_8b;
4995 
4996 	dump->flag = bp->dump_flag;
4997 	dump->len = bnxt_get_coredump_length(bp, bp->dump_flag);
4998 	return 0;
4999 }
5000 
5001 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump,
5002 			      void *buf)
5003 {
5004 	struct bnxt *bp = netdev_priv(dev);
5005 
5006 	if (bp->hwrm_spec_code < 0x10801)
5007 		return -EOPNOTSUPP;
5008 
5009 	memset(buf, 0, dump->len);
5010 
5011 	dump->flag = bp->dump_flag;
5012 	return bnxt_get_coredump(bp, dump->flag, buf, &dump->len);
5013 }
5014 
5015 static int bnxt_get_ts_info(struct net_device *dev,
5016 			    struct ethtool_ts_info *info)
5017 {
5018 	struct bnxt *bp = netdev_priv(dev);
5019 	struct bnxt_ptp_cfg *ptp;
5020 
5021 	ptp = bp->ptp_cfg;
5022 	info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
5023 				SOF_TIMESTAMPING_RX_SOFTWARE |
5024 				SOF_TIMESTAMPING_SOFTWARE;
5025 
5026 	info->phc_index = -1;
5027 	if (!ptp)
5028 		return 0;
5029 
5030 	info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
5031 				 SOF_TIMESTAMPING_RX_HARDWARE |
5032 				 SOF_TIMESTAMPING_RAW_HARDWARE;
5033 	if (ptp->ptp_clock)
5034 		info->phc_index = ptp_clock_index(ptp->ptp_clock);
5035 
5036 	info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
5037 
5038 	info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
5039 			   (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
5040 			   (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
5041 
5042 	if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS)
5043 		info->rx_filters |= (1 << HWTSTAMP_FILTER_ALL);
5044 	return 0;
5045 }
5046 
5047 void bnxt_ethtool_init(struct bnxt *bp)
5048 {
5049 	struct hwrm_selftest_qlist_output *resp;
5050 	struct hwrm_selftest_qlist_input *req;
5051 	struct bnxt_test_info *test_info;
5052 	struct net_device *dev = bp->dev;
5053 	int i, rc;
5054 
5055 	if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER))
5056 		bnxt_get_pkgver(dev);
5057 
5058 	bp->num_tests = 0;
5059 	if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp))
5060 		return;
5061 
5062 	test_info = bp->test_info;
5063 	if (!test_info) {
5064 		test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL);
5065 		if (!test_info)
5066 			return;
5067 		bp->test_info = test_info;
5068 	}
5069 
5070 	if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST))
5071 		return;
5072 
5073 	resp = hwrm_req_hold(bp, req);
5074 	rc = hwrm_req_send_silent(bp, req);
5075 	if (rc)
5076 		goto ethtool_init_exit;
5077 
5078 	bp->num_tests = resp->num_tests + BNXT_DRV_TESTS;
5079 	if (bp->num_tests > BNXT_MAX_TEST)
5080 		bp->num_tests = BNXT_MAX_TEST;
5081 
5082 	test_info->offline_mask = resp->offline_tests;
5083 	test_info->timeout = le16_to_cpu(resp->test_timeout);
5084 	if (!test_info->timeout)
5085 		test_info->timeout = HWRM_CMD_TIMEOUT;
5086 	for (i = 0; i < bp->num_tests; i++) {
5087 		char *str = test_info->string[i];
5088 		char *fw_str = resp->test_name[i];
5089 
5090 		if (i == BNXT_MACLPBK_TEST_IDX) {
5091 			strcpy(str, "Mac loopback test (offline)");
5092 		} else if (i == BNXT_PHYLPBK_TEST_IDX) {
5093 			strcpy(str, "Phy loopback test (offline)");
5094 		} else if (i == BNXT_EXTLPBK_TEST_IDX) {
5095 			strcpy(str, "Ext loopback test (offline)");
5096 		} else if (i == BNXT_IRQ_TEST_IDX) {
5097 			strcpy(str, "Interrupt_test (offline)");
5098 		} else {
5099 			snprintf(str, ETH_GSTRING_LEN, "%s test (%s)",
5100 				 fw_str, test_info->offline_mask & (1 << i) ?
5101 					"offline" : "online");
5102 		}
5103 	}
5104 
5105 ethtool_init_exit:
5106 	hwrm_req_drop(bp, req);
5107 }
5108 
5109 static void bnxt_get_eth_phy_stats(struct net_device *dev,
5110 				   struct ethtool_eth_phy_stats *phy_stats)
5111 {
5112 	struct bnxt *bp = netdev_priv(dev);
5113 	u64 *rx;
5114 
5115 	if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
5116 		return;
5117 
5118 	rx = bp->rx_port_stats_ext.sw_stats;
5119 	phy_stats->SymbolErrorDuringCarrier =
5120 		*(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err));
5121 }
5122 
5123 static void bnxt_get_eth_mac_stats(struct net_device *dev,
5124 				   struct ethtool_eth_mac_stats *mac_stats)
5125 {
5126 	struct bnxt *bp = netdev_priv(dev);
5127 	u64 *rx, *tx;
5128 
5129 	if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
5130 		return;
5131 
5132 	rx = bp->port_stats.sw_stats;
5133 	tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
5134 
5135 	mac_stats->FramesReceivedOK =
5136 		BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames);
5137 	mac_stats->FramesTransmittedOK =
5138 		BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames);
5139 	mac_stats->FrameCheckSequenceErrors =
5140 		BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames);
5141 	mac_stats->AlignmentErrors =
5142 		BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames);
5143 	mac_stats->OutOfRangeLengthField =
5144 		BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames);
5145 }
5146 
5147 static void bnxt_get_eth_ctrl_stats(struct net_device *dev,
5148 				    struct ethtool_eth_ctrl_stats *ctrl_stats)
5149 {
5150 	struct bnxt *bp = netdev_priv(dev);
5151 	u64 *rx;
5152 
5153 	if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
5154 		return;
5155 
5156 	rx = bp->port_stats.sw_stats;
5157 	ctrl_stats->MACControlFramesReceived =
5158 		BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames);
5159 }
5160 
5161 static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = {
5162 	{    0,    64 },
5163 	{   65,   127 },
5164 	{  128,   255 },
5165 	{  256,   511 },
5166 	{  512,  1023 },
5167 	{ 1024,  1518 },
5168 	{ 1519,  2047 },
5169 	{ 2048,  4095 },
5170 	{ 4096,  9216 },
5171 	{ 9217, 16383 },
5172 	{}
5173 };
5174 
5175 static void bnxt_get_rmon_stats(struct net_device *dev,
5176 				struct ethtool_rmon_stats *rmon_stats,
5177 				const struct ethtool_rmon_hist_range **ranges)
5178 {
5179 	struct bnxt *bp = netdev_priv(dev);
5180 	u64 *rx, *tx;
5181 
5182 	if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
5183 		return;
5184 
5185 	rx = bp->port_stats.sw_stats;
5186 	tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
5187 
5188 	rmon_stats->jabbers =
5189 		BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames);
5190 	rmon_stats->oversize_pkts =
5191 		BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames);
5192 	rmon_stats->undersize_pkts =
5193 		BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames);
5194 
5195 	rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames);
5196 	rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames);
5197 	rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames);
5198 	rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames);
5199 	rmon_stats->hist[4] =
5200 		BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames);
5201 	rmon_stats->hist[5] =
5202 		BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames);
5203 	rmon_stats->hist[6] =
5204 		BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames);
5205 	rmon_stats->hist[7] =
5206 		BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames);
5207 	rmon_stats->hist[8] =
5208 		BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames);
5209 	rmon_stats->hist[9] =
5210 		BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames);
5211 
5212 	rmon_stats->hist_tx[0] =
5213 		BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames);
5214 	rmon_stats->hist_tx[1] =
5215 		BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames);
5216 	rmon_stats->hist_tx[2] =
5217 		BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames);
5218 	rmon_stats->hist_tx[3] =
5219 		BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames);
5220 	rmon_stats->hist_tx[4] =
5221 		BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames);
5222 	rmon_stats->hist_tx[5] =
5223 		BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames);
5224 	rmon_stats->hist_tx[6] =
5225 		BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames);
5226 	rmon_stats->hist_tx[7] =
5227 		BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames);
5228 	rmon_stats->hist_tx[8] =
5229 		BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames);
5230 	rmon_stats->hist_tx[9] =
5231 		BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames);
5232 
5233 	*ranges = bnxt_rmon_ranges;
5234 }
5235 
5236 static void bnxt_get_ptp_stats(struct net_device *dev,
5237 			       struct ethtool_ts_stats *ts_stats)
5238 {
5239 	struct bnxt *bp = netdev_priv(dev);
5240 	struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5241 
5242 	if (ptp) {
5243 		ts_stats->pkts = ptp->stats.ts_pkts;
5244 		ts_stats->lost = ptp->stats.ts_lost;
5245 		ts_stats->err = atomic64_read(&ptp->stats.ts_err);
5246 	}
5247 }
5248 
5249 static void bnxt_get_link_ext_stats(struct net_device *dev,
5250 				    struct ethtool_link_ext_stats *stats)
5251 {
5252 	struct bnxt *bp = netdev_priv(dev);
5253 	u64 *rx;
5254 
5255 	if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
5256 		return;
5257 
5258 	rx = bp->rx_port_stats_ext.sw_stats;
5259 	stats->link_down_events =
5260 		*(rx + BNXT_RX_STATS_EXT_OFFSET(link_down_events));
5261 }
5262 
5263 void bnxt_ethtool_free(struct bnxt *bp)
5264 {
5265 	kfree(bp->test_info);
5266 	bp->test_info = NULL;
5267 }
5268 
5269 const struct ethtool_ops bnxt_ethtool_ops = {
5270 	.cap_link_lanes_supported	= 1,
5271 	.cap_rss_ctx_supported		= 1,
5272 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |
5273 				     ETHTOOL_COALESCE_MAX_FRAMES |
5274 				     ETHTOOL_COALESCE_USECS_IRQ |
5275 				     ETHTOOL_COALESCE_MAX_FRAMES_IRQ |
5276 				     ETHTOOL_COALESCE_STATS_BLOCK_USECS |
5277 				     ETHTOOL_COALESCE_USE_ADAPTIVE_RX |
5278 				     ETHTOOL_COALESCE_USE_CQE,
5279 	.get_link_ksettings	= bnxt_get_link_ksettings,
5280 	.set_link_ksettings	= bnxt_set_link_ksettings,
5281 	.get_fec_stats		= bnxt_get_fec_stats,
5282 	.get_fecparam		= bnxt_get_fecparam,
5283 	.set_fecparam		= bnxt_set_fecparam,
5284 	.get_pause_stats	= bnxt_get_pause_stats,
5285 	.get_pauseparam		= bnxt_get_pauseparam,
5286 	.set_pauseparam		= bnxt_set_pauseparam,
5287 	.get_drvinfo		= bnxt_get_drvinfo,
5288 	.get_regs_len		= bnxt_get_regs_len,
5289 	.get_regs		= bnxt_get_regs,
5290 	.get_wol		= bnxt_get_wol,
5291 	.set_wol		= bnxt_set_wol,
5292 	.get_coalesce		= bnxt_get_coalesce,
5293 	.set_coalesce		= bnxt_set_coalesce,
5294 	.get_msglevel		= bnxt_get_msglevel,
5295 	.set_msglevel		= bnxt_set_msglevel,
5296 	.get_sset_count		= bnxt_get_sset_count,
5297 	.get_strings		= bnxt_get_strings,
5298 	.get_ethtool_stats	= bnxt_get_ethtool_stats,
5299 	.set_ringparam		= bnxt_set_ringparam,
5300 	.get_ringparam		= bnxt_get_ringparam,
5301 	.get_channels		= bnxt_get_channels,
5302 	.set_channels		= bnxt_set_channels,
5303 	.get_rxnfc		= bnxt_get_rxnfc,
5304 	.set_rxnfc		= bnxt_set_rxnfc,
5305 	.get_rxfh_indir_size    = bnxt_get_rxfh_indir_size,
5306 	.get_rxfh_key_size      = bnxt_get_rxfh_key_size,
5307 	.get_rxfh               = bnxt_get_rxfh,
5308 	.set_rxfh		= bnxt_set_rxfh,
5309 	.flash_device		= bnxt_flash_device,
5310 	.get_eeprom_len         = bnxt_get_eeprom_len,
5311 	.get_eeprom             = bnxt_get_eeprom,
5312 	.set_eeprom		= bnxt_set_eeprom,
5313 	.get_link		= bnxt_get_link,
5314 	.get_link_ext_stats	= bnxt_get_link_ext_stats,
5315 	.get_eee		= bnxt_get_eee,
5316 	.set_eee		= bnxt_set_eee,
5317 	.get_module_info	= bnxt_get_module_info,
5318 	.get_module_eeprom	= bnxt_get_module_eeprom,
5319 	.get_module_eeprom_by_page = bnxt_get_module_eeprom_by_page,
5320 	.nway_reset		= bnxt_nway_reset,
5321 	.set_phys_id		= bnxt_set_phys_id,
5322 	.self_test		= bnxt_self_test,
5323 	.get_ts_info		= bnxt_get_ts_info,
5324 	.reset			= bnxt_reset,
5325 	.set_dump		= bnxt_set_dump,
5326 	.get_dump_flag		= bnxt_get_dump_flag,
5327 	.get_dump_data		= bnxt_get_dump_data,
5328 	.get_eth_phy_stats	= bnxt_get_eth_phy_stats,
5329 	.get_eth_mac_stats	= bnxt_get_eth_mac_stats,
5330 	.get_eth_ctrl_stats	= bnxt_get_eth_ctrl_stats,
5331 	.get_rmon_stats		= bnxt_get_rmon_stats,
5332 	.get_ts_stats		= bnxt_get_ptp_stats,
5333 };
5334