1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/bitops.h> 12 #include <linux/ctype.h> 13 #include <linux/stringify.h> 14 #include <linux/ethtool.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/linkmode.h> 17 #include <linux/interrupt.h> 18 #include <linux/pci.h> 19 #include <linux/etherdevice.h> 20 #include <linux/crc32.h> 21 #include <linux/firmware.h> 22 #include <linux/utsname.h> 23 #include <linux/time.h> 24 #include <linux/ptp_clock_kernel.h> 25 #include <linux/net_tstamp.h> 26 #include <linux/timecounter.h> 27 #include <net/netlink.h> 28 #include "bnxt_hsi.h" 29 #include "bnxt.h" 30 #include "bnxt_hwrm.h" 31 #include "bnxt_ulp.h" 32 #include "bnxt_xdp.h" 33 #include "bnxt_ptp.h" 34 #include "bnxt_ethtool.h" 35 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 36 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 37 #include "bnxt_coredump.h" 38 39 #define BNXT_NVM_ERR_MSG(dev, extack, msg) \ 40 do { \ 41 if (extack) \ 42 NL_SET_ERR_MSG_MOD(extack, msg); \ 43 netdev_err(dev, "%s\n", msg); \ 44 } while (0) 45 46 static u32 bnxt_get_msglevel(struct net_device *dev) 47 { 48 struct bnxt *bp = netdev_priv(dev); 49 50 return bp->msg_enable; 51 } 52 53 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 54 { 55 struct bnxt *bp = netdev_priv(dev); 56 57 bp->msg_enable = value; 58 } 59 60 static int bnxt_get_coalesce(struct net_device *dev, 61 struct ethtool_coalesce *coal, 62 struct kernel_ethtool_coalesce *kernel_coal, 63 struct netlink_ext_ack *extack) 64 { 65 struct bnxt *bp = netdev_priv(dev); 66 struct bnxt_coal *hw_coal; 67 u16 mult; 68 69 memset(coal, 0, sizeof(*coal)); 70 71 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 72 73 hw_coal = &bp->rx_coal; 74 mult = hw_coal->bufs_per_record; 75 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 76 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 77 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 78 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 79 if (hw_coal->flags & 80 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 81 kernel_coal->use_cqe_mode_rx = true; 82 83 hw_coal = &bp->tx_coal; 84 mult = hw_coal->bufs_per_record; 85 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 86 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 87 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 88 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 89 if (hw_coal->flags & 90 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 91 kernel_coal->use_cqe_mode_tx = true; 92 93 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 94 95 return 0; 96 } 97 98 static int bnxt_set_coalesce(struct net_device *dev, 99 struct ethtool_coalesce *coal, 100 struct kernel_ethtool_coalesce *kernel_coal, 101 struct netlink_ext_ack *extack) 102 { 103 struct bnxt *bp = netdev_priv(dev); 104 bool update_stats = false; 105 struct bnxt_coal *hw_coal; 106 int rc = 0; 107 u16 mult; 108 109 if (coal->use_adaptive_rx_coalesce) { 110 bp->flags |= BNXT_FLAG_DIM; 111 } else { 112 if (bp->flags & BNXT_FLAG_DIM) { 113 bp->flags &= ~(BNXT_FLAG_DIM); 114 goto reset_coalesce; 115 } 116 } 117 118 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) && 119 !(bp->coal_cap.cmpl_params & 120 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)) 121 return -EOPNOTSUPP; 122 123 hw_coal = &bp->rx_coal; 124 mult = hw_coal->bufs_per_record; 125 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 126 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 127 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 128 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 129 hw_coal->flags &= 130 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 131 if (kernel_coal->use_cqe_mode_rx) 132 hw_coal->flags |= 133 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 134 135 hw_coal = &bp->tx_coal; 136 mult = hw_coal->bufs_per_record; 137 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 138 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 139 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 140 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 141 hw_coal->flags &= 142 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 143 if (kernel_coal->use_cqe_mode_tx) 144 hw_coal->flags |= 145 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 146 147 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 148 u32 stats_ticks = coal->stats_block_coalesce_usecs; 149 150 /* Allow 0, which means disable. */ 151 if (stats_ticks) 152 stats_ticks = clamp_t(u32, stats_ticks, 153 BNXT_MIN_STATS_COAL_TICKS, 154 BNXT_MAX_STATS_COAL_TICKS); 155 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 156 bp->stats_coal_ticks = stats_ticks; 157 if (bp->stats_coal_ticks) 158 bp->current_interval = 159 bp->stats_coal_ticks * HZ / 1000000; 160 else 161 bp->current_interval = BNXT_TIMER_INTERVAL; 162 update_stats = true; 163 } 164 165 reset_coalesce: 166 if (test_bit(BNXT_STATE_OPEN, &bp->state)) { 167 if (update_stats) { 168 bnxt_close_nic(bp, true, false); 169 rc = bnxt_open_nic(bp, true, false); 170 } else { 171 rc = bnxt_hwrm_set_coal(bp); 172 } 173 } 174 175 return rc; 176 } 177 178 static const char * const bnxt_ring_rx_stats_str[] = { 179 "rx_ucast_packets", 180 "rx_mcast_packets", 181 "rx_bcast_packets", 182 "rx_discards", 183 "rx_errors", 184 "rx_ucast_bytes", 185 "rx_mcast_bytes", 186 "rx_bcast_bytes", 187 }; 188 189 static const char * const bnxt_ring_tx_stats_str[] = { 190 "tx_ucast_packets", 191 "tx_mcast_packets", 192 "tx_bcast_packets", 193 "tx_errors", 194 "tx_discards", 195 "tx_ucast_bytes", 196 "tx_mcast_bytes", 197 "tx_bcast_bytes", 198 }; 199 200 static const char * const bnxt_ring_tpa_stats_str[] = { 201 "tpa_packets", 202 "tpa_bytes", 203 "tpa_events", 204 "tpa_aborts", 205 }; 206 207 static const char * const bnxt_ring_tpa2_stats_str[] = { 208 "rx_tpa_eligible_pkt", 209 "rx_tpa_eligible_bytes", 210 "rx_tpa_pkt", 211 "rx_tpa_bytes", 212 "rx_tpa_errors", 213 "rx_tpa_events", 214 }; 215 216 static const char * const bnxt_rx_sw_stats_str[] = { 217 "rx_l4_csum_errors", 218 "rx_resets", 219 "rx_buf_errors", 220 }; 221 222 static const char * const bnxt_cmn_sw_stats_str[] = { 223 "missed_irqs", 224 }; 225 226 #define BNXT_RX_STATS_ENTRY(counter) \ 227 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 228 229 #define BNXT_TX_STATS_ENTRY(counter) \ 230 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 231 232 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 233 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 234 235 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 236 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 237 238 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 239 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 240 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 241 242 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 243 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 244 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 245 246 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 247 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 248 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 249 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 250 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 251 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 252 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 253 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 254 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 255 256 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 257 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 258 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 259 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 260 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 261 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 262 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 263 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 264 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 265 266 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 267 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 268 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 269 270 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 271 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 272 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 273 274 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 275 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 276 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 277 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 278 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 279 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 280 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 281 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 282 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 283 284 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 285 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 286 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 287 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 288 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 289 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 290 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 291 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 292 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 293 294 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 295 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 296 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 297 298 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 299 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 300 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 301 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 302 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 303 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 304 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 305 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 306 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 307 308 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 309 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 310 __stringify(counter##_pri##n) } 311 312 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 313 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 314 __stringify(counter##_pri##n) } 315 316 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 317 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 318 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 319 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 320 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 321 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 322 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 323 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 324 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 325 326 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 327 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 328 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 329 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 330 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 331 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 332 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 333 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 334 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 335 336 enum { 337 RX_TOTAL_DISCARDS, 338 TX_TOTAL_DISCARDS, 339 RX_NETPOLL_DISCARDS, 340 }; 341 342 static const char *const bnxt_ring_err_stats_arr[] = { 343 "rx_total_l4_csum_errors", 344 "rx_total_resets", 345 "rx_total_buf_errors", 346 "rx_total_oom_discards", 347 "rx_total_netpoll_discards", 348 "rx_total_ring_discards", 349 "tx_total_resets", 350 "tx_total_ring_discards", 351 "total_missed_irqs", 352 }; 353 354 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str) 355 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str) 356 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str) 357 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str) 358 359 static const struct { 360 long offset; 361 char string[ETH_GSTRING_LEN]; 362 } bnxt_port_stats_arr[] = { 363 BNXT_RX_STATS_ENTRY(rx_64b_frames), 364 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 365 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 366 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 367 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 368 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 369 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 370 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 371 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 372 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 373 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 374 BNXT_RX_STATS_ENTRY(rx_total_frames), 375 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 376 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 377 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 378 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 379 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 380 BNXT_RX_STATS_ENTRY(rx_pause_frames), 381 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 382 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 383 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 384 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 385 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 386 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 387 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 388 BNXT_RX_STATS_ENTRY(rx_good_frames), 389 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 390 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 391 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 392 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 393 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 394 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 395 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 396 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 397 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 398 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 399 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 400 BNXT_RX_STATS_ENTRY(rx_bytes), 401 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 402 BNXT_RX_STATS_ENTRY(rx_runt_frames), 403 BNXT_RX_STATS_ENTRY(rx_stat_discard), 404 BNXT_RX_STATS_ENTRY(rx_stat_err), 405 406 BNXT_TX_STATS_ENTRY(tx_64b_frames), 407 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 408 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 409 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 410 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 411 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 412 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 413 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 414 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 415 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 416 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 417 BNXT_TX_STATS_ENTRY(tx_good_frames), 418 BNXT_TX_STATS_ENTRY(tx_total_frames), 419 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 420 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 421 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 422 BNXT_TX_STATS_ENTRY(tx_pause_frames), 423 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 424 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 425 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 426 BNXT_TX_STATS_ENTRY(tx_err), 427 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 428 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 429 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 430 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 431 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 432 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 433 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 434 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 435 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 436 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 437 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 438 BNXT_TX_STATS_ENTRY(tx_total_collisions), 439 BNXT_TX_STATS_ENTRY(tx_bytes), 440 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 441 BNXT_TX_STATS_ENTRY(tx_stat_discard), 442 BNXT_TX_STATS_ENTRY(tx_stat_error), 443 }; 444 445 static const struct { 446 long offset; 447 char string[ETH_GSTRING_LEN]; 448 } bnxt_port_stats_ext_arr[] = { 449 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 450 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 451 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 452 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 453 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 454 BNXT_RX_STATS_EXT_COS_ENTRIES, 455 BNXT_RX_STATS_EXT_PFC_ENTRIES, 456 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 457 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 458 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 459 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 460 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 461 BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks), 462 BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks), 463 BNXT_RX_STATS_EXT_ENTRY(rx_filter_miss), 464 }; 465 466 static const struct { 467 long offset; 468 char string[ETH_GSTRING_LEN]; 469 } bnxt_tx_port_stats_ext_arr[] = { 470 BNXT_TX_STATS_EXT_COS_ENTRIES, 471 BNXT_TX_STATS_EXT_PFC_ENTRIES, 472 }; 473 474 static const struct { 475 long base_off; 476 char string[ETH_GSTRING_LEN]; 477 } bnxt_rx_bytes_pri_arr[] = { 478 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 479 }; 480 481 static const struct { 482 long base_off; 483 char string[ETH_GSTRING_LEN]; 484 } bnxt_rx_pkts_pri_arr[] = { 485 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 486 }; 487 488 static const struct { 489 long base_off; 490 char string[ETH_GSTRING_LEN]; 491 } bnxt_tx_bytes_pri_arr[] = { 492 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 493 }; 494 495 static const struct { 496 long base_off; 497 char string[ETH_GSTRING_LEN]; 498 } bnxt_tx_pkts_pri_arr[] = { 499 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 500 }; 501 502 #define BNXT_NUM_RING_ERR_STATS ARRAY_SIZE(bnxt_ring_err_stats_arr) 503 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 504 #define BNXT_NUM_STATS_PRI \ 505 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 506 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 507 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 508 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 509 510 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 511 { 512 if (BNXT_SUPPORTS_TPA(bp)) { 513 if (bp->max_tpa_v2) { 514 if (BNXT_CHIP_P5(bp)) 515 return BNXT_NUM_TPA_RING_STATS_P5; 516 return BNXT_NUM_TPA_RING_STATS_P7; 517 } 518 return BNXT_NUM_TPA_RING_STATS; 519 } 520 return 0; 521 } 522 523 static int bnxt_get_num_ring_stats(struct bnxt *bp) 524 { 525 int rx, tx, cmn; 526 527 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS + 528 bnxt_get_num_tpa_ring_stats(bp); 529 tx = NUM_RING_TX_HW_STATS; 530 cmn = NUM_RING_CMN_SW_STATS; 531 return rx * bp->rx_nr_rings + 532 tx * (bp->tx_nr_rings_xdp + bp->tx_nr_rings_per_tc) + 533 cmn * bp->cp_nr_rings; 534 } 535 536 static int bnxt_get_num_stats(struct bnxt *bp) 537 { 538 int num_stats = bnxt_get_num_ring_stats(bp); 539 int len; 540 541 num_stats += BNXT_NUM_RING_ERR_STATS; 542 543 if (bp->flags & BNXT_FLAG_PORT_STATS) 544 num_stats += BNXT_NUM_PORT_STATS; 545 546 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 547 len = min_t(int, bp->fw_rx_stats_ext_size, 548 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 549 num_stats += len; 550 len = min_t(int, bp->fw_tx_stats_ext_size, 551 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 552 num_stats += len; 553 if (bp->pri2cos_valid) 554 num_stats += BNXT_NUM_STATS_PRI; 555 } 556 557 return num_stats; 558 } 559 560 static int bnxt_get_sset_count(struct net_device *dev, int sset) 561 { 562 struct bnxt *bp = netdev_priv(dev); 563 564 switch (sset) { 565 case ETH_SS_STATS: 566 return bnxt_get_num_stats(bp); 567 case ETH_SS_TEST: 568 if (!bp->num_tests) 569 return -EOPNOTSUPP; 570 return bp->num_tests; 571 default: 572 return -EOPNOTSUPP; 573 } 574 } 575 576 static bool is_rx_ring(struct bnxt *bp, int ring_num) 577 { 578 return ring_num < bp->rx_nr_rings; 579 } 580 581 static bool is_tx_ring(struct bnxt *bp, int ring_num) 582 { 583 int tx_base = 0; 584 585 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 586 tx_base = bp->rx_nr_rings; 587 588 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings)) 589 return true; 590 return false; 591 } 592 593 static void bnxt_get_ethtool_stats(struct net_device *dev, 594 struct ethtool_stats *stats, u64 *buf) 595 { 596 struct bnxt_total_ring_err_stats ring_err_stats = {0}; 597 struct bnxt *bp = netdev_priv(dev); 598 u64 *curr, *prev; 599 u32 tpa_stats; 600 u32 i, j = 0; 601 602 if (!bp->bnapi) { 603 j += bnxt_get_num_ring_stats(bp); 604 goto skip_ring_stats; 605 } 606 607 tpa_stats = bnxt_get_num_tpa_ring_stats(bp); 608 for (i = 0; i < bp->cp_nr_rings; i++) { 609 struct bnxt_napi *bnapi = bp->bnapi[i]; 610 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 611 u64 *sw_stats = cpr->stats.sw_stats; 612 u64 *sw; 613 int k; 614 615 if (is_rx_ring(bp, i)) { 616 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++) 617 buf[j] = sw_stats[k]; 618 } 619 if (is_tx_ring(bp, i)) { 620 k = NUM_RING_RX_HW_STATS; 621 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 622 j++, k++) 623 buf[j] = sw_stats[k]; 624 } 625 if (!tpa_stats || !is_rx_ring(bp, i)) 626 goto skip_tpa_ring_stats; 627 628 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 629 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS + 630 tpa_stats; j++, k++) 631 buf[j] = sw_stats[k]; 632 633 skip_tpa_ring_stats: 634 sw = (u64 *)&cpr->sw_stats.rx; 635 if (is_rx_ring(bp, i)) { 636 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++) 637 buf[j] = sw[k]; 638 } 639 640 sw = (u64 *)&cpr->sw_stats.cmn; 641 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++) 642 buf[j] = sw[k]; 643 } 644 645 bnxt_get_ring_err_stats(bp, &ring_err_stats); 646 647 skip_ring_stats: 648 curr = &ring_err_stats.rx_total_l4_csum_errors; 649 prev = &bp->ring_err_stats_prev.rx_total_l4_csum_errors; 650 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++, j++, curr++, prev++) 651 buf[j] = *curr + *prev; 652 653 if (bp->flags & BNXT_FLAG_PORT_STATS) { 654 u64 *port_stats = bp->port_stats.sw_stats; 655 656 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) 657 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset); 658 } 659 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 660 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats; 661 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats; 662 u32 len; 663 664 len = min_t(u32, bp->fw_rx_stats_ext_size, 665 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 666 for (i = 0; i < len; i++, j++) { 667 buf[j] = *(rx_port_stats_ext + 668 bnxt_port_stats_ext_arr[i].offset); 669 } 670 len = min_t(u32, bp->fw_tx_stats_ext_size, 671 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 672 for (i = 0; i < len; i++, j++) { 673 buf[j] = *(tx_port_stats_ext + 674 bnxt_tx_port_stats_ext_arr[i].offset); 675 } 676 if (bp->pri2cos_valid) { 677 for (i = 0; i < 8; i++, j++) { 678 long n = bnxt_rx_bytes_pri_arr[i].base_off + 679 bp->pri2cos_idx[i]; 680 681 buf[j] = *(rx_port_stats_ext + n); 682 } 683 for (i = 0; i < 8; i++, j++) { 684 long n = bnxt_rx_pkts_pri_arr[i].base_off + 685 bp->pri2cos_idx[i]; 686 687 buf[j] = *(rx_port_stats_ext + n); 688 } 689 for (i = 0; i < 8; i++, j++) { 690 long n = bnxt_tx_bytes_pri_arr[i].base_off + 691 bp->pri2cos_idx[i]; 692 693 buf[j] = *(tx_port_stats_ext + n); 694 } 695 for (i = 0; i < 8; i++, j++) { 696 long n = bnxt_tx_pkts_pri_arr[i].base_off + 697 bp->pri2cos_idx[i]; 698 699 buf[j] = *(tx_port_stats_ext + n); 700 } 701 } 702 } 703 } 704 705 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 706 { 707 struct bnxt *bp = netdev_priv(dev); 708 static const char * const *str; 709 u32 i, j, num_str; 710 711 switch (stringset) { 712 case ETH_SS_STATS: 713 for (i = 0; i < bp->cp_nr_rings; i++) { 714 if (is_rx_ring(bp, i)) { 715 num_str = NUM_RING_RX_HW_STATS; 716 for (j = 0; j < num_str; j++) { 717 sprintf(buf, "[%d]: %s", i, 718 bnxt_ring_rx_stats_str[j]); 719 buf += ETH_GSTRING_LEN; 720 } 721 } 722 if (is_tx_ring(bp, i)) { 723 num_str = NUM_RING_TX_HW_STATS; 724 for (j = 0; j < num_str; j++) { 725 sprintf(buf, "[%d]: %s", i, 726 bnxt_ring_tx_stats_str[j]); 727 buf += ETH_GSTRING_LEN; 728 } 729 } 730 num_str = bnxt_get_num_tpa_ring_stats(bp); 731 if (!num_str || !is_rx_ring(bp, i)) 732 goto skip_tpa_stats; 733 734 if (bp->max_tpa_v2) 735 str = bnxt_ring_tpa2_stats_str; 736 else 737 str = bnxt_ring_tpa_stats_str; 738 739 for (j = 0; j < num_str; j++) { 740 sprintf(buf, "[%d]: %s", i, str[j]); 741 buf += ETH_GSTRING_LEN; 742 } 743 skip_tpa_stats: 744 if (is_rx_ring(bp, i)) { 745 num_str = NUM_RING_RX_SW_STATS; 746 for (j = 0; j < num_str; j++) { 747 sprintf(buf, "[%d]: %s", i, 748 bnxt_rx_sw_stats_str[j]); 749 buf += ETH_GSTRING_LEN; 750 } 751 } 752 num_str = NUM_RING_CMN_SW_STATS; 753 for (j = 0; j < num_str; j++) { 754 sprintf(buf, "[%d]: %s", i, 755 bnxt_cmn_sw_stats_str[j]); 756 buf += ETH_GSTRING_LEN; 757 } 758 } 759 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++) { 760 strscpy(buf, bnxt_ring_err_stats_arr[i], ETH_GSTRING_LEN); 761 buf += ETH_GSTRING_LEN; 762 } 763 764 if (bp->flags & BNXT_FLAG_PORT_STATS) { 765 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 766 strcpy(buf, bnxt_port_stats_arr[i].string); 767 buf += ETH_GSTRING_LEN; 768 } 769 } 770 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 771 u32 len; 772 773 len = min_t(u32, bp->fw_rx_stats_ext_size, 774 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 775 for (i = 0; i < len; i++) { 776 strcpy(buf, bnxt_port_stats_ext_arr[i].string); 777 buf += ETH_GSTRING_LEN; 778 } 779 len = min_t(u32, bp->fw_tx_stats_ext_size, 780 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 781 for (i = 0; i < len; i++) { 782 strcpy(buf, 783 bnxt_tx_port_stats_ext_arr[i].string); 784 buf += ETH_GSTRING_LEN; 785 } 786 if (bp->pri2cos_valid) { 787 for (i = 0; i < 8; i++) { 788 strcpy(buf, 789 bnxt_rx_bytes_pri_arr[i].string); 790 buf += ETH_GSTRING_LEN; 791 } 792 for (i = 0; i < 8; i++) { 793 strcpy(buf, 794 bnxt_rx_pkts_pri_arr[i].string); 795 buf += ETH_GSTRING_LEN; 796 } 797 for (i = 0; i < 8; i++) { 798 strcpy(buf, 799 bnxt_tx_bytes_pri_arr[i].string); 800 buf += ETH_GSTRING_LEN; 801 } 802 for (i = 0; i < 8; i++) { 803 strcpy(buf, 804 bnxt_tx_pkts_pri_arr[i].string); 805 buf += ETH_GSTRING_LEN; 806 } 807 } 808 } 809 break; 810 case ETH_SS_TEST: 811 if (bp->num_tests) 812 memcpy(buf, bp->test_info->string, 813 bp->num_tests * ETH_GSTRING_LEN); 814 break; 815 default: 816 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 817 stringset); 818 break; 819 } 820 } 821 822 static void bnxt_get_ringparam(struct net_device *dev, 823 struct ethtool_ringparam *ering, 824 struct kernel_ethtool_ringparam *kernel_ering, 825 struct netlink_ext_ack *extack) 826 { 827 struct bnxt *bp = netdev_priv(dev); 828 829 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 830 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA; 831 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 832 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_ENABLED; 833 } else { 834 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 835 ering->rx_jumbo_max_pending = 0; 836 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_DISABLED; 837 } 838 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 839 840 ering->rx_pending = bp->rx_ring_size; 841 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 842 ering->tx_pending = bp->tx_ring_size; 843 } 844 845 static int bnxt_set_ringparam(struct net_device *dev, 846 struct ethtool_ringparam *ering, 847 struct kernel_ethtool_ringparam *kernel_ering, 848 struct netlink_ext_ack *extack) 849 { 850 struct bnxt *bp = netdev_priv(dev); 851 852 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 853 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 854 (ering->tx_pending < BNXT_MIN_TX_DESC_CNT)) 855 return -EINVAL; 856 857 if (netif_running(dev)) 858 bnxt_close_nic(bp, false, false); 859 860 bp->rx_ring_size = ering->rx_pending; 861 bp->tx_ring_size = ering->tx_pending; 862 bnxt_set_ring_params(bp); 863 864 if (netif_running(dev)) 865 return bnxt_open_nic(bp, false, false); 866 867 return 0; 868 } 869 870 static void bnxt_get_channels(struct net_device *dev, 871 struct ethtool_channels *channel) 872 { 873 struct bnxt *bp = netdev_priv(dev); 874 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 875 int max_rx_rings, max_tx_rings, tcs; 876 int max_tx_sch_inputs, tx_grps; 877 878 /* Get the most up-to-date max_tx_sch_inputs. */ 879 if (netif_running(dev) && BNXT_NEW_RM(bp)) 880 bnxt_hwrm_func_resc_qcaps(bp, false); 881 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 882 883 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 884 if (max_tx_sch_inputs) 885 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 886 887 tcs = netdev_get_num_tc(dev); 888 tx_grps = max(tcs, 1); 889 if (bp->tx_nr_rings_xdp) 890 tx_grps++; 891 max_tx_rings /= tx_grps; 892 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 893 894 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 895 max_rx_rings = 0; 896 max_tx_rings = 0; 897 } 898 if (max_tx_sch_inputs) 899 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 900 901 if (tcs > 1) 902 max_tx_rings /= tcs; 903 904 channel->max_rx = max_rx_rings; 905 channel->max_tx = max_tx_rings; 906 channel->max_other = 0; 907 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 908 channel->combined_count = bp->rx_nr_rings; 909 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 910 channel->combined_count--; 911 } else { 912 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 913 channel->rx_count = bp->rx_nr_rings; 914 channel->tx_count = bp->tx_nr_rings_per_tc; 915 } 916 } 917 } 918 919 static int bnxt_set_channels(struct net_device *dev, 920 struct ethtool_channels *channel) 921 { 922 struct bnxt *bp = netdev_priv(dev); 923 int req_tx_rings, req_rx_rings, tcs; 924 bool sh = false; 925 int tx_xdp = 0; 926 int rc = 0; 927 int tx_cp; 928 929 if (channel->other_count) 930 return -EINVAL; 931 932 if (!channel->combined_count && 933 (!channel->rx_count || !channel->tx_count)) 934 return -EINVAL; 935 936 if (channel->combined_count && 937 (channel->rx_count || channel->tx_count)) 938 return -EINVAL; 939 940 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 941 channel->tx_count)) 942 return -EINVAL; 943 944 if (channel->combined_count) 945 sh = true; 946 947 tcs = netdev_get_num_tc(dev); 948 949 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 950 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 951 if (bp->tx_nr_rings_xdp) { 952 if (!sh) { 953 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 954 return -EINVAL; 955 } 956 tx_xdp = req_rx_rings; 957 } 958 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 959 if (rc) { 960 netdev_warn(dev, "Unable to allocate the requested rings\n"); 961 return rc; 962 } 963 964 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) != 965 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) && 966 netif_is_rxfh_configured(dev)) { 967 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n"); 968 return -EINVAL; 969 } 970 971 if (netif_running(dev)) { 972 if (BNXT_PF(bp)) { 973 /* TODO CHIMP_FW: Send message to all VF's 974 * before PF unload 975 */ 976 } 977 bnxt_close_nic(bp, true, false); 978 } 979 980 if (sh) { 981 bp->flags |= BNXT_FLAG_SHARED_RINGS; 982 bp->rx_nr_rings = channel->combined_count; 983 bp->tx_nr_rings_per_tc = channel->combined_count; 984 } else { 985 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 986 bp->rx_nr_rings = channel->rx_count; 987 bp->tx_nr_rings_per_tc = channel->tx_count; 988 } 989 bp->tx_nr_rings_xdp = tx_xdp; 990 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 991 if (tcs > 1) 992 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 993 994 tx_cp = bnxt_num_tx_to_cp(bp, bp->tx_nr_rings); 995 bp->cp_nr_rings = sh ? max_t(int, tx_cp, bp->rx_nr_rings) : 996 tx_cp + bp->rx_nr_rings; 997 998 /* After changing number of rx channels, update NTUPLE feature. */ 999 netdev_update_features(dev); 1000 if (netif_running(dev)) { 1001 rc = bnxt_open_nic(bp, true, false); 1002 if ((!rc) && BNXT_PF(bp)) { 1003 /* TODO CHIMP_FW: Send message to all VF's 1004 * to renable 1005 */ 1006 } 1007 } else { 1008 rc = bnxt_reserve_rings(bp, true); 1009 } 1010 1011 return rc; 1012 } 1013 1014 static u32 bnxt_get_all_fltr_ids_rcu(struct bnxt *bp, struct hlist_head tbl[], 1015 int tbl_size, u32 *ids, u32 start, 1016 u32 id_cnt) 1017 { 1018 int i, j = start; 1019 1020 if (j >= id_cnt) 1021 return j; 1022 for (i = 0; i < tbl_size; i++) { 1023 struct hlist_head *head; 1024 struct bnxt_filter_base *fltr; 1025 1026 head = &tbl[i]; 1027 hlist_for_each_entry_rcu(fltr, head, hash) { 1028 if (!fltr->flags || 1029 test_bit(BNXT_FLTR_FW_DELETED, &fltr->state)) 1030 continue; 1031 ids[j++] = fltr->sw_id; 1032 if (j == id_cnt) 1033 return j; 1034 } 1035 } 1036 return j; 1037 } 1038 1039 static struct bnxt_filter_base *bnxt_get_one_fltr_rcu(struct bnxt *bp, 1040 struct hlist_head tbl[], 1041 int tbl_size, u32 id) 1042 { 1043 int i; 1044 1045 for (i = 0; i < tbl_size; i++) { 1046 struct hlist_head *head; 1047 struct bnxt_filter_base *fltr; 1048 1049 head = &tbl[i]; 1050 hlist_for_each_entry_rcu(fltr, head, hash) { 1051 if (fltr->flags && fltr->sw_id == id) 1052 return fltr; 1053 } 1054 } 1055 return NULL; 1056 } 1057 1058 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 1059 u32 *rule_locs) 1060 { 1061 cmd->data = bp->ntp_fltr_count; 1062 rcu_read_lock(); 1063 cmd->rule_cnt = bnxt_get_all_fltr_ids_rcu(bp, bp->ntp_fltr_hash_tbl, 1064 BNXT_NTP_FLTR_HASH_SIZE, 1065 rule_locs, 0, cmd->rule_cnt); 1066 rcu_read_unlock(); 1067 1068 return 0; 1069 } 1070 1071 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1072 { 1073 struct ethtool_rx_flow_spec *fs = 1074 (struct ethtool_rx_flow_spec *)&cmd->fs; 1075 struct bnxt_filter_base *fltr_base; 1076 struct bnxt_ntuple_filter *fltr; 1077 struct flow_keys *fkeys; 1078 int rc = -EINVAL; 1079 1080 if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR) 1081 return rc; 1082 1083 rcu_read_lock(); 1084 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl, 1085 BNXT_NTP_FLTR_HASH_SIZE, 1086 fs->location); 1087 if (!fltr_base) { 1088 rcu_read_unlock(); 1089 return rc; 1090 } 1091 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base); 1092 1093 fkeys = &fltr->fkeys; 1094 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 1095 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1096 fs->flow_type = TCP_V4_FLOW; 1097 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1098 fs->flow_type = UDP_V4_FLOW; 1099 else 1100 goto fltr_err; 1101 1102 if (fltr->ntuple_flags & BNXT_NTUPLE_MATCH_SRC_IP) { 1103 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 1104 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0); 1105 } 1106 if (fltr->ntuple_flags & BNXT_NTUPLE_MATCH_DST_IP) { 1107 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 1108 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0); 1109 } 1110 if (fltr->ntuple_flags & BNXT_NTUPLE_MATCH_SRC_PORT) { 1111 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 1112 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0); 1113 } 1114 if (fltr->ntuple_flags & BNXT_NTUPLE_MATCH_DST_PORT) { 1115 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 1116 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0); 1117 } 1118 } else { 1119 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1120 fs->flow_type = TCP_V6_FLOW; 1121 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1122 fs->flow_type = UDP_V6_FLOW; 1123 else 1124 goto fltr_err; 1125 1126 if (fltr->ntuple_flags & BNXT_NTUPLE_MATCH_SRC_IP) { 1127 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 1128 fkeys->addrs.v6addrs.src; 1129 bnxt_fill_ipv6_mask(fs->m_u.tcp_ip6_spec.ip6src); 1130 } 1131 if (fltr->ntuple_flags & BNXT_NTUPLE_MATCH_DST_IP) { 1132 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 1133 fkeys->addrs.v6addrs.dst; 1134 bnxt_fill_ipv6_mask(fs->m_u.tcp_ip6_spec.ip6dst); 1135 } 1136 if (fltr->ntuple_flags & BNXT_NTUPLE_MATCH_SRC_PORT) { 1137 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 1138 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0); 1139 } 1140 if (fltr->ntuple_flags & BNXT_NTUPLE_MATCH_DST_PORT) { 1141 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 1142 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0); 1143 } 1144 } 1145 1146 fs->ring_cookie = fltr->base.rxq; 1147 rc = 0; 1148 1149 fltr_err: 1150 rcu_read_unlock(); 1151 1152 return rc; 1153 } 1154 1155 #define IPV4_ALL_MASK ((__force __be32)~0) 1156 #define L4_PORT_ALL_MASK ((__force __be16)~0) 1157 1158 static bool ipv6_mask_is_full(__be32 mask[4]) 1159 { 1160 return (mask[0] & mask[1] & mask[2] & mask[3]) == IPV4_ALL_MASK; 1161 } 1162 1163 static bool ipv6_mask_is_zero(__be32 mask[4]) 1164 { 1165 return !(mask[0] | mask[1] | mask[2] | mask[3]); 1166 } 1167 1168 static int bnxt_add_ntuple_cls_rule(struct bnxt *bp, 1169 struct ethtool_rx_flow_spec *fs) 1170 { 1171 u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1172 u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1173 struct bnxt_ntuple_filter *new_fltr, *fltr; 1174 struct bnxt_l2_filter *l2_fltr; 1175 u32 flow_type = fs->flow_type; 1176 struct flow_keys *fkeys; 1177 u32 idx; 1178 int rc; 1179 1180 if (!bp->vnic_info) 1181 return -EAGAIN; 1182 1183 if ((flow_type & (FLOW_MAC_EXT | FLOW_EXT)) || vf) 1184 return -EOPNOTSUPP; 1185 1186 new_fltr = kzalloc(sizeof(*new_fltr), GFP_KERNEL); 1187 if (!new_fltr) 1188 return -ENOMEM; 1189 1190 l2_fltr = bp->vnic_info[0].l2_filters[0]; 1191 atomic_inc(&l2_fltr->refcnt); 1192 new_fltr->l2_fltr = l2_fltr; 1193 fkeys = &new_fltr->fkeys; 1194 1195 rc = -EOPNOTSUPP; 1196 switch (flow_type) { 1197 case TCP_V4_FLOW: 1198 case UDP_V4_FLOW: { 1199 struct ethtool_tcpip4_spec *ip_spec = &fs->h_u.tcp_ip4_spec; 1200 struct ethtool_tcpip4_spec *ip_mask = &fs->m_u.tcp_ip4_spec; 1201 1202 fkeys->basic.ip_proto = IPPROTO_TCP; 1203 if (flow_type == UDP_V4_FLOW) 1204 fkeys->basic.ip_proto = IPPROTO_UDP; 1205 fkeys->basic.n_proto = htons(ETH_P_IP); 1206 1207 if (ip_mask->ip4src == IPV4_ALL_MASK) { 1208 fkeys->addrs.v4addrs.src = ip_spec->ip4src; 1209 new_fltr->ntuple_flags |= BNXT_NTUPLE_MATCH_SRC_IP; 1210 } else if (ip_mask->ip4src) { 1211 goto ntuple_err; 1212 } 1213 if (ip_mask->ip4dst == IPV4_ALL_MASK) { 1214 fkeys->addrs.v4addrs.dst = ip_spec->ip4dst; 1215 new_fltr->ntuple_flags |= BNXT_NTUPLE_MATCH_DST_IP; 1216 } else if (ip_mask->ip4dst) { 1217 goto ntuple_err; 1218 } 1219 1220 if (ip_mask->psrc == L4_PORT_ALL_MASK) { 1221 fkeys->ports.src = ip_spec->psrc; 1222 new_fltr->ntuple_flags |= BNXT_NTUPLE_MATCH_SRC_PORT; 1223 } else if (ip_mask->psrc) { 1224 goto ntuple_err; 1225 } 1226 if (ip_mask->pdst == L4_PORT_ALL_MASK) { 1227 fkeys->ports.dst = ip_spec->pdst; 1228 new_fltr->ntuple_flags |= BNXT_NTUPLE_MATCH_DST_PORT; 1229 } else if (ip_mask->pdst) { 1230 goto ntuple_err; 1231 } 1232 break; 1233 } 1234 case TCP_V6_FLOW: 1235 case UDP_V6_FLOW: { 1236 struct ethtool_tcpip6_spec *ip_spec = &fs->h_u.tcp_ip6_spec; 1237 struct ethtool_tcpip6_spec *ip_mask = &fs->m_u.tcp_ip6_spec; 1238 1239 fkeys->basic.ip_proto = IPPROTO_TCP; 1240 if (flow_type == UDP_V6_FLOW) 1241 fkeys->basic.ip_proto = IPPROTO_UDP; 1242 fkeys->basic.n_proto = htons(ETH_P_IPV6); 1243 1244 if (ipv6_mask_is_full(ip_mask->ip6src)) { 1245 fkeys->addrs.v6addrs.src = 1246 *(struct in6_addr *)&ip_spec->ip6src; 1247 new_fltr->ntuple_flags |= BNXT_NTUPLE_MATCH_SRC_IP; 1248 } else if (!ipv6_mask_is_zero(ip_mask->ip6src)) { 1249 goto ntuple_err; 1250 } 1251 if (ipv6_mask_is_full(ip_mask->ip6dst)) { 1252 fkeys->addrs.v6addrs.dst = 1253 *(struct in6_addr *)&ip_spec->ip6dst; 1254 new_fltr->ntuple_flags |= BNXT_NTUPLE_MATCH_DST_IP; 1255 } else if (!ipv6_mask_is_zero(ip_mask->ip6dst)) { 1256 goto ntuple_err; 1257 } 1258 1259 if (ip_mask->psrc == L4_PORT_ALL_MASK) { 1260 fkeys->ports.src = ip_spec->psrc; 1261 new_fltr->ntuple_flags |= BNXT_NTUPLE_MATCH_SRC_PORT; 1262 } else if (ip_mask->psrc) { 1263 goto ntuple_err; 1264 } 1265 if (ip_mask->pdst == L4_PORT_ALL_MASK) { 1266 fkeys->ports.dst = ip_spec->pdst; 1267 new_fltr->ntuple_flags |= BNXT_NTUPLE_MATCH_DST_PORT; 1268 } else if (ip_mask->pdst) { 1269 goto ntuple_err; 1270 } 1271 break; 1272 } 1273 default: 1274 rc = -EOPNOTSUPP; 1275 goto ntuple_err; 1276 } 1277 if (!new_fltr->ntuple_flags) 1278 goto ntuple_err; 1279 1280 idx = bnxt_get_ntp_filter_idx(bp, fkeys, NULL); 1281 rcu_read_lock(); 1282 fltr = bnxt_lookup_ntp_filter_from_idx(bp, new_fltr, idx); 1283 if (fltr) { 1284 rcu_read_unlock(); 1285 rc = -EEXIST; 1286 goto ntuple_err; 1287 } 1288 rcu_read_unlock(); 1289 1290 new_fltr->base.rxq = ring; 1291 new_fltr->base.flags = BNXT_ACT_NO_AGING; 1292 __set_bit(BNXT_FLTR_VALID, &new_fltr->base.state); 1293 rc = bnxt_insert_ntp_filter(bp, new_fltr, idx); 1294 if (!rc) { 1295 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, new_fltr); 1296 if (rc) { 1297 bnxt_del_ntp_filter(bp, new_fltr); 1298 return rc; 1299 } 1300 fs->location = new_fltr->base.sw_id; 1301 return 0; 1302 } 1303 1304 ntuple_err: 1305 atomic_dec(&l2_fltr->refcnt); 1306 kfree(new_fltr); 1307 return rc; 1308 } 1309 1310 static int bnxt_srxclsrlins(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1311 { 1312 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1313 u32 ring, flow_type; 1314 int rc; 1315 u8 vf; 1316 1317 if (!netif_running(bp->dev)) 1318 return -EAGAIN; 1319 if (!(bp->flags & BNXT_FLAG_RFS)) 1320 return -EPERM; 1321 if (fs->location != RX_CLS_LOC_ANY) 1322 return -EINVAL; 1323 1324 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1325 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1326 if (BNXT_VF(bp) && vf) 1327 return -EINVAL; 1328 if (BNXT_PF(bp) && vf > bp->pf.active_vfs) 1329 return -EINVAL; 1330 if (!vf && ring >= bp->rx_nr_rings) 1331 return -EINVAL; 1332 1333 flow_type = fs->flow_type; 1334 if (flow_type & (FLOW_MAC_EXT | FLOW_RSS)) 1335 return -EINVAL; 1336 flow_type &= ~FLOW_EXT; 1337 if (flow_type == ETHER_FLOW) 1338 rc = -EOPNOTSUPP; 1339 else 1340 rc = bnxt_add_ntuple_cls_rule(bp, fs); 1341 return rc; 1342 } 1343 1344 static int bnxt_srxclsrldel(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1345 { 1346 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1347 struct bnxt_filter_base *fltr_base; 1348 struct bnxt_ntuple_filter *fltr; 1349 1350 rcu_read_lock(); 1351 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl, 1352 BNXT_NTP_FLTR_HASH_SIZE, 1353 fs->location); 1354 if (!fltr_base) { 1355 rcu_read_unlock(); 1356 return -ENOENT; 1357 } 1358 1359 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base); 1360 if (!(fltr->base.flags & BNXT_ACT_NO_AGING)) { 1361 rcu_read_unlock(); 1362 return -EINVAL; 1363 } 1364 rcu_read_unlock(); 1365 bnxt_hwrm_cfa_ntuple_filter_free(bp, fltr); 1366 bnxt_del_ntp_filter(bp, fltr); 1367 return 0; 1368 } 1369 1370 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1371 { 1372 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1373 return RXH_IP_SRC | RXH_IP_DST; 1374 return 0; 1375 } 1376 1377 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1378 { 1379 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1380 return RXH_IP_SRC | RXH_IP_DST; 1381 return 0; 1382 } 1383 1384 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1385 { 1386 cmd->data = 0; 1387 switch (cmd->flow_type) { 1388 case TCP_V4_FLOW: 1389 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1390 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1391 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1392 cmd->data |= get_ethtool_ipv4_rss(bp); 1393 break; 1394 case UDP_V4_FLOW: 1395 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1396 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1397 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1398 fallthrough; 1399 case SCTP_V4_FLOW: 1400 case AH_ESP_V4_FLOW: 1401 case AH_V4_FLOW: 1402 case ESP_V4_FLOW: 1403 case IPV4_FLOW: 1404 cmd->data |= get_ethtool_ipv4_rss(bp); 1405 break; 1406 1407 case TCP_V6_FLOW: 1408 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1409 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1410 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1411 cmd->data |= get_ethtool_ipv6_rss(bp); 1412 break; 1413 case UDP_V6_FLOW: 1414 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1415 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1416 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1417 fallthrough; 1418 case SCTP_V6_FLOW: 1419 case AH_ESP_V6_FLOW: 1420 case AH_V6_FLOW: 1421 case ESP_V6_FLOW: 1422 case IPV6_FLOW: 1423 cmd->data |= get_ethtool_ipv6_rss(bp); 1424 break; 1425 } 1426 return 0; 1427 } 1428 1429 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1430 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1431 1432 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1433 { 1434 u32 rss_hash_cfg = bp->rss_hash_cfg; 1435 int tuple, rc = 0; 1436 1437 if (cmd->data == RXH_4TUPLE) 1438 tuple = 4; 1439 else if (cmd->data == RXH_2TUPLE) 1440 tuple = 2; 1441 else if (!cmd->data) 1442 tuple = 0; 1443 else 1444 return -EINVAL; 1445 1446 if (cmd->flow_type == TCP_V4_FLOW) { 1447 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1448 if (tuple == 4) 1449 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1450 } else if (cmd->flow_type == UDP_V4_FLOW) { 1451 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP)) 1452 return -EINVAL; 1453 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1454 if (tuple == 4) 1455 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1456 } else if (cmd->flow_type == TCP_V6_FLOW) { 1457 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1458 if (tuple == 4) 1459 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1460 } else if (cmd->flow_type == UDP_V6_FLOW) { 1461 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP)) 1462 return -EINVAL; 1463 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1464 if (tuple == 4) 1465 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1466 } else if (tuple == 4) { 1467 return -EINVAL; 1468 } 1469 1470 switch (cmd->flow_type) { 1471 case TCP_V4_FLOW: 1472 case UDP_V4_FLOW: 1473 case SCTP_V4_FLOW: 1474 case AH_ESP_V4_FLOW: 1475 case AH_V4_FLOW: 1476 case ESP_V4_FLOW: 1477 case IPV4_FLOW: 1478 if (tuple == 2) 1479 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1480 else if (!tuple) 1481 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1482 break; 1483 1484 case TCP_V6_FLOW: 1485 case UDP_V6_FLOW: 1486 case SCTP_V6_FLOW: 1487 case AH_ESP_V6_FLOW: 1488 case AH_V6_FLOW: 1489 case ESP_V6_FLOW: 1490 case IPV6_FLOW: 1491 if (tuple == 2) 1492 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1493 else if (!tuple) 1494 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1495 break; 1496 } 1497 1498 if (bp->rss_hash_cfg == rss_hash_cfg) 1499 return 0; 1500 1501 if (bp->rss_cap & BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA) 1502 bp->rss_hash_delta = bp->rss_hash_cfg ^ rss_hash_cfg; 1503 bp->rss_hash_cfg = rss_hash_cfg; 1504 if (netif_running(bp->dev)) { 1505 bnxt_close_nic(bp, false, false); 1506 rc = bnxt_open_nic(bp, false, false); 1507 } 1508 return rc; 1509 } 1510 1511 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1512 u32 *rule_locs) 1513 { 1514 struct bnxt *bp = netdev_priv(dev); 1515 int rc = 0; 1516 1517 switch (cmd->cmd) { 1518 case ETHTOOL_GRXRINGS: 1519 cmd->data = bp->rx_nr_rings; 1520 break; 1521 1522 case ETHTOOL_GRXCLSRLCNT: 1523 cmd->rule_cnt = bp->ntp_fltr_count; 1524 cmd->data = BNXT_NTP_FLTR_MAX_FLTR | RX_CLS_LOC_SPECIAL; 1525 break; 1526 1527 case ETHTOOL_GRXCLSRLALL: 1528 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1529 break; 1530 1531 case ETHTOOL_GRXCLSRULE: 1532 rc = bnxt_grxclsrule(bp, cmd); 1533 break; 1534 1535 case ETHTOOL_GRXFH: 1536 rc = bnxt_grxfh(bp, cmd); 1537 break; 1538 1539 default: 1540 rc = -EOPNOTSUPP; 1541 break; 1542 } 1543 1544 return rc; 1545 } 1546 1547 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1548 { 1549 struct bnxt *bp = netdev_priv(dev); 1550 int rc; 1551 1552 switch (cmd->cmd) { 1553 case ETHTOOL_SRXFH: 1554 rc = bnxt_srxfh(bp, cmd); 1555 break; 1556 1557 case ETHTOOL_SRXCLSRLINS: 1558 rc = bnxt_srxclsrlins(bp, cmd); 1559 break; 1560 1561 case ETHTOOL_SRXCLSRLDEL: 1562 rc = bnxt_srxclsrldel(bp, cmd); 1563 break; 1564 1565 default: 1566 rc = -EOPNOTSUPP; 1567 break; 1568 } 1569 return rc; 1570 } 1571 1572 u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1573 { 1574 struct bnxt *bp = netdev_priv(dev); 1575 1576 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) 1577 return ALIGN(bp->rx_nr_rings, BNXT_RSS_TABLE_ENTRIES_P5); 1578 return HW_HASH_INDEX_SIZE; 1579 } 1580 1581 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1582 { 1583 return HW_HASH_KEY_SIZE; 1584 } 1585 1586 static int bnxt_get_rxfh(struct net_device *dev, 1587 struct ethtool_rxfh_param *rxfh) 1588 { 1589 struct bnxt *bp = netdev_priv(dev); 1590 struct bnxt_vnic_info *vnic; 1591 u32 i, tbl_size; 1592 1593 rxfh->hfunc = ETH_RSS_HASH_TOP; 1594 1595 if (!bp->vnic_info) 1596 return 0; 1597 1598 vnic = &bp->vnic_info[0]; 1599 if (rxfh->indir && bp->rss_indir_tbl) { 1600 tbl_size = bnxt_get_rxfh_indir_size(dev); 1601 for (i = 0; i < tbl_size; i++) 1602 rxfh->indir[i] = bp->rss_indir_tbl[i]; 1603 } 1604 1605 if (rxfh->key && vnic->rss_hash_key) 1606 memcpy(rxfh->key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1607 1608 return 0; 1609 } 1610 1611 static int bnxt_set_rxfh(struct net_device *dev, 1612 struct ethtool_rxfh_param *rxfh, 1613 struct netlink_ext_ack *extack) 1614 { 1615 struct bnxt *bp = netdev_priv(dev); 1616 int rc = 0; 1617 1618 if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP) 1619 return -EOPNOTSUPP; 1620 1621 if (rxfh->key) 1622 return -EOPNOTSUPP; 1623 1624 if (rxfh->indir) { 1625 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(dev); 1626 1627 for (i = 0; i < tbl_size; i++) 1628 bp->rss_indir_tbl[i] = rxfh->indir[i]; 1629 pad = bp->rss_indir_tbl_entries - tbl_size; 1630 if (pad) 1631 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16)); 1632 } 1633 1634 if (netif_running(bp->dev)) { 1635 bnxt_close_nic(bp, false, false); 1636 rc = bnxt_open_nic(bp, false, false); 1637 } 1638 return rc; 1639 } 1640 1641 static void bnxt_get_drvinfo(struct net_device *dev, 1642 struct ethtool_drvinfo *info) 1643 { 1644 struct bnxt *bp = netdev_priv(dev); 1645 1646 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 1647 strscpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 1648 strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1649 info->n_stats = bnxt_get_num_stats(bp); 1650 info->testinfo_len = bp->num_tests; 1651 /* TODO CHIMP_FW: eeprom dump details */ 1652 info->eedump_len = 0; 1653 /* TODO CHIMP FW: reg dump details */ 1654 info->regdump_len = 0; 1655 } 1656 1657 static int bnxt_get_regs_len(struct net_device *dev) 1658 { 1659 struct bnxt *bp = netdev_priv(dev); 1660 int reg_len; 1661 1662 if (!BNXT_PF(bp)) 1663 return -EOPNOTSUPP; 1664 1665 reg_len = BNXT_PXP_REG_LEN; 1666 1667 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED) 1668 reg_len += sizeof(struct pcie_ctx_hw_stats); 1669 1670 return reg_len; 1671 } 1672 1673 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1674 void *_p) 1675 { 1676 struct pcie_ctx_hw_stats *hw_pcie_stats; 1677 struct hwrm_pcie_qstats_input *req; 1678 struct bnxt *bp = netdev_priv(dev); 1679 dma_addr_t hw_pcie_stats_addr; 1680 int rc; 1681 1682 regs->version = 0; 1683 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p); 1684 1685 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 1686 return; 1687 1688 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS)) 1689 return; 1690 1691 hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats), 1692 &hw_pcie_stats_addr); 1693 if (!hw_pcie_stats) { 1694 hwrm_req_drop(bp, req); 1695 return; 1696 } 1697 1698 regs->version = 1; 1699 hwrm_req_hold(bp, req); /* hold on to slice */ 1700 req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats)); 1701 req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr); 1702 rc = hwrm_req_send(bp, req); 1703 if (!rc) { 1704 __le64 *src = (__le64 *)hw_pcie_stats; 1705 u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN); 1706 int i; 1707 1708 for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++) 1709 dst[i] = le64_to_cpu(src[i]); 1710 } 1711 hwrm_req_drop(bp, req); 1712 } 1713 1714 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1715 { 1716 struct bnxt *bp = netdev_priv(dev); 1717 1718 wol->supported = 0; 1719 wol->wolopts = 0; 1720 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1721 if (bp->flags & BNXT_FLAG_WOL_CAP) { 1722 wol->supported = WAKE_MAGIC; 1723 if (bp->wol) 1724 wol->wolopts = WAKE_MAGIC; 1725 } 1726 } 1727 1728 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1729 { 1730 struct bnxt *bp = netdev_priv(dev); 1731 1732 if (wol->wolopts & ~WAKE_MAGIC) 1733 return -EINVAL; 1734 1735 if (wol->wolopts & WAKE_MAGIC) { 1736 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 1737 return -EINVAL; 1738 if (!bp->wol) { 1739 if (bnxt_hwrm_alloc_wol_fltr(bp)) 1740 return -EBUSY; 1741 bp->wol = 1; 1742 } 1743 } else { 1744 if (bp->wol) { 1745 if (bnxt_hwrm_free_wol_fltr(bp)) 1746 return -EBUSY; 1747 bp->wol = 0; 1748 } 1749 } 1750 return 0; 1751 } 1752 1753 u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause) 1754 { 1755 u32 speed_mask = 0; 1756 1757 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 1758 /* set the advertised speeds */ 1759 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 1760 speed_mask |= ADVERTISED_100baseT_Full; 1761 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 1762 speed_mask |= ADVERTISED_1000baseT_Full; 1763 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 1764 speed_mask |= ADVERTISED_2500baseX_Full; 1765 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 1766 speed_mask |= ADVERTISED_10000baseT_Full; 1767 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 1768 speed_mask |= ADVERTISED_40000baseCR4_Full; 1769 1770 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH) 1771 speed_mask |= ADVERTISED_Pause; 1772 else if (fw_pause & BNXT_LINK_PAUSE_TX) 1773 speed_mask |= ADVERTISED_Asym_Pause; 1774 else if (fw_pause & BNXT_LINK_PAUSE_RX) 1775 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; 1776 1777 return speed_mask; 1778 } 1779 1780 enum bnxt_media_type { 1781 BNXT_MEDIA_UNKNOWN = 0, 1782 BNXT_MEDIA_TP, 1783 BNXT_MEDIA_CR, 1784 BNXT_MEDIA_SR, 1785 BNXT_MEDIA_LR_ER_FR, 1786 BNXT_MEDIA_KR, 1787 BNXT_MEDIA_KX, 1788 BNXT_MEDIA_X, 1789 __BNXT_MEDIA_END, 1790 }; 1791 1792 static const enum bnxt_media_type bnxt_phy_types[] = { 1793 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR] = BNXT_MEDIA_CR, 1794 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4] = BNXT_MEDIA_KR, 1795 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR] = BNXT_MEDIA_LR_ER_FR, 1796 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR] = BNXT_MEDIA_SR, 1797 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2] = BNXT_MEDIA_KR, 1798 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX] = BNXT_MEDIA_KX, 1799 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR] = BNXT_MEDIA_KR, 1800 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASET] = BNXT_MEDIA_TP, 1801 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE] = BNXT_MEDIA_TP, 1802 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L] = BNXT_MEDIA_CR, 1803 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S] = BNXT_MEDIA_CR, 1804 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N] = BNXT_MEDIA_CR, 1805 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR] = BNXT_MEDIA_SR, 1806 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4] = BNXT_MEDIA_CR, 1807 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4] = BNXT_MEDIA_SR, 1808 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 1809 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 1810 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10] = BNXT_MEDIA_SR, 1811 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4] = BNXT_MEDIA_CR, 1812 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4] = BNXT_MEDIA_SR, 1813 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 1814 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 1815 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE] = BNXT_MEDIA_SR, 1816 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET] = BNXT_MEDIA_TP, 1817 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX] = BNXT_MEDIA_X, 1818 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX] = BNXT_MEDIA_X, 1819 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4] = BNXT_MEDIA_CR, 1820 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4] = BNXT_MEDIA_SR, 1821 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 1822 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 1823 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR] = BNXT_MEDIA_CR, 1824 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR] = BNXT_MEDIA_SR, 1825 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR] = BNXT_MEDIA_LR_ER_FR, 1826 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER] = BNXT_MEDIA_LR_ER_FR, 1827 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2] = BNXT_MEDIA_CR, 1828 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2] = BNXT_MEDIA_SR, 1829 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2] = BNXT_MEDIA_LR_ER_FR, 1830 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2] = BNXT_MEDIA_LR_ER_FR, 1831 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR] = BNXT_MEDIA_CR, 1832 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR] = BNXT_MEDIA_SR, 1833 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR] = BNXT_MEDIA_LR_ER_FR, 1834 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER] = BNXT_MEDIA_LR_ER_FR, 1835 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2] = BNXT_MEDIA_CR, 1836 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2] = BNXT_MEDIA_SR, 1837 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2] = BNXT_MEDIA_LR_ER_FR, 1838 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2] = BNXT_MEDIA_LR_ER_FR, 1839 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8] = BNXT_MEDIA_CR, 1840 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8] = BNXT_MEDIA_SR, 1841 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8] = BNXT_MEDIA_LR_ER_FR, 1842 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8] = BNXT_MEDIA_LR_ER_FR, 1843 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4] = BNXT_MEDIA_CR, 1844 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4] = BNXT_MEDIA_SR, 1845 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 1846 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 1847 }; 1848 1849 static enum bnxt_media_type 1850 bnxt_get_media(struct bnxt_link_info *link_info) 1851 { 1852 switch (link_info->media_type) { 1853 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP: 1854 return BNXT_MEDIA_TP; 1855 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC: 1856 return BNXT_MEDIA_CR; 1857 default: 1858 if (link_info->phy_type < ARRAY_SIZE(bnxt_phy_types)) 1859 return bnxt_phy_types[link_info->phy_type]; 1860 return BNXT_MEDIA_UNKNOWN; 1861 } 1862 } 1863 1864 enum bnxt_link_speed_indices { 1865 BNXT_LINK_SPEED_UNKNOWN = 0, 1866 BNXT_LINK_SPEED_100MB_IDX, 1867 BNXT_LINK_SPEED_1GB_IDX, 1868 BNXT_LINK_SPEED_10GB_IDX, 1869 BNXT_LINK_SPEED_25GB_IDX, 1870 BNXT_LINK_SPEED_40GB_IDX, 1871 BNXT_LINK_SPEED_50GB_IDX, 1872 BNXT_LINK_SPEED_100GB_IDX, 1873 BNXT_LINK_SPEED_200GB_IDX, 1874 BNXT_LINK_SPEED_400GB_IDX, 1875 __BNXT_LINK_SPEED_END 1876 }; 1877 1878 static enum bnxt_link_speed_indices bnxt_fw_speed_idx(u16 speed) 1879 { 1880 switch (speed) { 1881 case BNXT_LINK_SPEED_100MB: return BNXT_LINK_SPEED_100MB_IDX; 1882 case BNXT_LINK_SPEED_1GB: return BNXT_LINK_SPEED_1GB_IDX; 1883 case BNXT_LINK_SPEED_10GB: return BNXT_LINK_SPEED_10GB_IDX; 1884 case BNXT_LINK_SPEED_25GB: return BNXT_LINK_SPEED_25GB_IDX; 1885 case BNXT_LINK_SPEED_40GB: return BNXT_LINK_SPEED_40GB_IDX; 1886 case BNXT_LINK_SPEED_50GB: 1887 case BNXT_LINK_SPEED_50GB_PAM4: 1888 return BNXT_LINK_SPEED_50GB_IDX; 1889 case BNXT_LINK_SPEED_100GB: 1890 case BNXT_LINK_SPEED_100GB_PAM4: 1891 case BNXT_LINK_SPEED_100GB_PAM4_112: 1892 return BNXT_LINK_SPEED_100GB_IDX; 1893 case BNXT_LINK_SPEED_200GB: 1894 case BNXT_LINK_SPEED_200GB_PAM4: 1895 case BNXT_LINK_SPEED_200GB_PAM4_112: 1896 return BNXT_LINK_SPEED_200GB_IDX; 1897 case BNXT_LINK_SPEED_400GB: 1898 case BNXT_LINK_SPEED_400GB_PAM4: 1899 case BNXT_LINK_SPEED_400GB_PAM4_112: 1900 return BNXT_LINK_SPEED_400GB_IDX; 1901 default: return BNXT_LINK_SPEED_UNKNOWN; 1902 } 1903 } 1904 1905 static const enum ethtool_link_mode_bit_indices 1906 bnxt_link_modes[__BNXT_LINK_SPEED_END][BNXT_SIG_MODE_MAX][__BNXT_MEDIA_END] = { 1907 [BNXT_LINK_SPEED_100MB_IDX] = { 1908 { 1909 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1910 }, 1911 }, 1912 [BNXT_LINK_SPEED_1GB_IDX] = { 1913 { 1914 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1915 /* historically baseT, but DAC is more correctly baseX */ 1916 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1917 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 1918 [BNXT_MEDIA_X] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1919 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 1920 }, 1921 }, 1922 [BNXT_LINK_SPEED_10GB_IDX] = { 1923 { 1924 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1925 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 1926 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 1927 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 1928 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 1929 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 1930 }, 1931 }, 1932 [BNXT_LINK_SPEED_25GB_IDX] = { 1933 { 1934 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 1935 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 1936 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 1937 }, 1938 }, 1939 [BNXT_LINK_SPEED_40GB_IDX] = { 1940 { 1941 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 1942 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 1943 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 1944 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 1945 }, 1946 }, 1947 [BNXT_LINK_SPEED_50GB_IDX] = { 1948 [BNXT_SIG_MODE_NRZ] = { 1949 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 1950 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 1951 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 1952 }, 1953 [BNXT_SIG_MODE_PAM4] = { 1954 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 1955 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 1956 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 1957 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 1958 }, 1959 }, 1960 [BNXT_LINK_SPEED_100GB_IDX] = { 1961 [BNXT_SIG_MODE_NRZ] = { 1962 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 1963 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 1964 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 1965 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 1966 }, 1967 [BNXT_SIG_MODE_PAM4] = { 1968 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 1969 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 1970 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 1971 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 1972 }, 1973 [BNXT_SIG_MODE_PAM4_112] = { 1974 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR_Full_BIT, 1975 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR_Full_BIT, 1976 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR_Full_BIT, 1977 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT, 1978 }, 1979 }, 1980 [BNXT_LINK_SPEED_200GB_IDX] = { 1981 [BNXT_SIG_MODE_PAM4] = { 1982 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT, 1983 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 1984 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 1985 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 1986 }, 1987 [BNXT_SIG_MODE_PAM4_112] = { 1988 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT, 1989 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT, 1990 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT, 1991 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT, 1992 }, 1993 }, 1994 [BNXT_LINK_SPEED_400GB_IDX] = { 1995 [BNXT_SIG_MODE_PAM4] = { 1996 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT, 1997 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT, 1998 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT, 1999 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT, 2000 }, 2001 [BNXT_SIG_MODE_PAM4_112] = { 2002 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT, 2003 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT, 2004 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT, 2005 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT, 2006 }, 2007 }, 2008 }; 2009 2010 #define BNXT_LINK_MODE_UNKNOWN -1 2011 2012 static enum ethtool_link_mode_bit_indices 2013 bnxt_get_link_mode(struct bnxt_link_info *link_info) 2014 { 2015 enum ethtool_link_mode_bit_indices link_mode; 2016 enum bnxt_link_speed_indices speed; 2017 enum bnxt_media_type media; 2018 u8 sig_mode; 2019 2020 if (link_info->phy_link_status != BNXT_LINK_LINK) 2021 return BNXT_LINK_MODE_UNKNOWN; 2022 2023 media = bnxt_get_media(link_info); 2024 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 2025 speed = bnxt_fw_speed_idx(link_info->link_speed); 2026 sig_mode = link_info->active_fec_sig_mode & 2027 PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK; 2028 } else { 2029 speed = bnxt_fw_speed_idx(link_info->req_link_speed); 2030 sig_mode = link_info->req_signal_mode; 2031 } 2032 if (sig_mode >= BNXT_SIG_MODE_MAX) 2033 return BNXT_LINK_MODE_UNKNOWN; 2034 2035 /* Note ETHTOOL_LINK_MODE_10baseT_Half_BIT == 0 is a legal Linux 2036 * link mode, but since no such devices exist, the zeroes in the 2037 * map can be conveniently used to represent unknown link modes. 2038 */ 2039 link_mode = bnxt_link_modes[speed][sig_mode][media]; 2040 if (!link_mode) 2041 return BNXT_LINK_MODE_UNKNOWN; 2042 2043 switch (link_mode) { 2044 case ETHTOOL_LINK_MODE_100baseT_Full_BIT: 2045 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2046 link_mode = ETHTOOL_LINK_MODE_100baseT_Half_BIT; 2047 break; 2048 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT: 2049 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2050 link_mode = ETHTOOL_LINK_MODE_1000baseT_Half_BIT; 2051 break; 2052 default: 2053 break; 2054 } 2055 2056 return link_mode; 2057 } 2058 2059 static void bnxt_get_ethtool_modes(struct bnxt_link_info *link_info, 2060 struct ethtool_link_ksettings *lk_ksettings) 2061 { 2062 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2063 2064 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) { 2065 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2066 lk_ksettings->link_modes.supported); 2067 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2068 lk_ksettings->link_modes.supported); 2069 } 2070 2071 if (link_info->support_auto_speeds || link_info->support_auto_speeds2 || 2072 link_info->support_pam4_auto_speeds) 2073 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2074 lk_ksettings->link_modes.supported); 2075 2076 if (~link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 2077 return; 2078 2079 if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_RX) 2080 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2081 lk_ksettings->link_modes.advertising); 2082 if (hweight8(link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) == 1) 2083 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2084 lk_ksettings->link_modes.advertising); 2085 if (link_info->lp_pause & BNXT_LINK_PAUSE_RX) 2086 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2087 lk_ksettings->link_modes.lp_advertising); 2088 if (hweight8(link_info->lp_pause & BNXT_LINK_PAUSE_BOTH) == 1) 2089 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2090 lk_ksettings->link_modes.lp_advertising); 2091 } 2092 2093 static const u16 bnxt_nrz_speed_masks[] = { 2094 [BNXT_LINK_SPEED_100MB_IDX] = BNXT_LINK_SPEED_MSK_100MB, 2095 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEED_MSK_1GB, 2096 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEED_MSK_10GB, 2097 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEED_MSK_25GB, 2098 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEED_MSK_40GB, 2099 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEED_MSK_50GB, 2100 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEED_MSK_100GB, 2101 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2102 }; 2103 2104 static const u16 bnxt_pam4_speed_masks[] = { 2105 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_50GB, 2106 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_100GB, 2107 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_200GB, 2108 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2109 }; 2110 2111 static const u16 bnxt_nrz_speeds2_masks[] = { 2112 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEEDS2_MSK_1GB, 2113 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEEDS2_MSK_10GB, 2114 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEEDS2_MSK_25GB, 2115 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEEDS2_MSK_40GB, 2116 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB, 2117 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB, 2118 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2119 }; 2120 2121 static const u16 bnxt_pam4_speeds2_masks[] = { 2122 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB_PAM4, 2123 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4, 2124 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4, 2125 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4, 2126 }; 2127 2128 static const u16 bnxt_pam4_112_speeds2_masks[] = { 2129 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112, 2130 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112, 2131 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112, 2132 }; 2133 2134 static enum bnxt_link_speed_indices 2135 bnxt_encoding_speed_idx(u8 sig_mode, u16 phy_flags, u16 speed_msk) 2136 { 2137 const u16 *speeds; 2138 int idx, len; 2139 2140 switch (sig_mode) { 2141 case BNXT_SIG_MODE_NRZ: 2142 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2143 speeds = bnxt_nrz_speeds2_masks; 2144 len = ARRAY_SIZE(bnxt_nrz_speeds2_masks); 2145 } else { 2146 speeds = bnxt_nrz_speed_masks; 2147 len = ARRAY_SIZE(bnxt_nrz_speed_masks); 2148 } 2149 break; 2150 case BNXT_SIG_MODE_PAM4: 2151 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2152 speeds = bnxt_pam4_speeds2_masks; 2153 len = ARRAY_SIZE(bnxt_pam4_speeds2_masks); 2154 } else { 2155 speeds = bnxt_pam4_speed_masks; 2156 len = ARRAY_SIZE(bnxt_pam4_speed_masks); 2157 } 2158 break; 2159 case BNXT_SIG_MODE_PAM4_112: 2160 speeds = bnxt_pam4_112_speeds2_masks; 2161 len = ARRAY_SIZE(bnxt_pam4_112_speeds2_masks); 2162 break; 2163 default: 2164 return BNXT_LINK_SPEED_UNKNOWN; 2165 } 2166 2167 for (idx = 0; idx < len; idx++) { 2168 if (speeds[idx] == speed_msk) 2169 return idx; 2170 } 2171 2172 return BNXT_LINK_SPEED_UNKNOWN; 2173 } 2174 2175 #define BNXT_FW_SPEED_MSK_BITS 16 2176 2177 static void 2178 __bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media, 2179 u8 sig_mode, u16 phy_flags, unsigned long *et_mask) 2180 { 2181 enum ethtool_link_mode_bit_indices link_mode; 2182 enum bnxt_link_speed_indices speed; 2183 u8 bit; 2184 2185 for_each_set_bit(bit, &fw_mask, BNXT_FW_SPEED_MSK_BITS) { 2186 speed = bnxt_encoding_speed_idx(sig_mode, phy_flags, 1 << bit); 2187 if (!speed) 2188 continue; 2189 2190 link_mode = bnxt_link_modes[speed][sig_mode][media]; 2191 if (!link_mode) 2192 continue; 2193 2194 linkmode_set_bit(link_mode, et_mask); 2195 } 2196 } 2197 2198 static void 2199 bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media, 2200 u8 sig_mode, u16 phy_flags, unsigned long *et_mask) 2201 { 2202 if (media) { 2203 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags, 2204 et_mask); 2205 return; 2206 } 2207 2208 /* list speeds for all media if unknown */ 2209 for (media = 1; media < __BNXT_MEDIA_END; media++) 2210 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags, 2211 et_mask); 2212 } 2213 2214 static void 2215 bnxt_get_all_ethtool_support_speeds(struct bnxt_link_info *link_info, 2216 enum bnxt_media_type media, 2217 struct ethtool_link_ksettings *lk_ksettings) 2218 { 2219 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2220 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0; 2221 u16 phy_flags = bp->phy_flags; 2222 2223 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2224 sp_nrz = link_info->support_speeds2; 2225 sp_pam4 = link_info->support_speeds2; 2226 sp_pam4_112 = link_info->support_speeds2; 2227 } else { 2228 sp_nrz = link_info->support_speeds; 2229 sp_pam4 = link_info->support_pam4_speeds; 2230 } 2231 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags, 2232 lk_ksettings->link_modes.supported); 2233 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags, 2234 lk_ksettings->link_modes.supported); 2235 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112, 2236 phy_flags, lk_ksettings->link_modes.supported); 2237 } 2238 2239 static void 2240 bnxt_get_all_ethtool_adv_speeds(struct bnxt_link_info *link_info, 2241 enum bnxt_media_type media, 2242 struct ethtool_link_ksettings *lk_ksettings) 2243 { 2244 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2245 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0; 2246 u16 phy_flags = bp->phy_flags; 2247 2248 sp_nrz = link_info->advertising; 2249 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2250 sp_pam4 = link_info->advertising; 2251 sp_pam4_112 = link_info->advertising; 2252 } else { 2253 sp_pam4 = link_info->advertising_pam4; 2254 } 2255 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags, 2256 lk_ksettings->link_modes.advertising); 2257 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags, 2258 lk_ksettings->link_modes.advertising); 2259 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112, 2260 phy_flags, lk_ksettings->link_modes.advertising); 2261 } 2262 2263 static void 2264 bnxt_get_all_ethtool_lp_speeds(struct bnxt_link_info *link_info, 2265 enum bnxt_media_type media, 2266 struct ethtool_link_ksettings *lk_ksettings) 2267 { 2268 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2269 u16 phy_flags = bp->phy_flags; 2270 2271 bnxt_get_ethtool_speeds(link_info->lp_auto_link_speeds, media, 2272 BNXT_SIG_MODE_NRZ, phy_flags, 2273 lk_ksettings->link_modes.lp_advertising); 2274 bnxt_get_ethtool_speeds(link_info->lp_auto_pam4_link_speeds, media, 2275 BNXT_SIG_MODE_PAM4, phy_flags, 2276 lk_ksettings->link_modes.lp_advertising); 2277 } 2278 2279 static void bnxt_update_speed(u32 *delta, bool installed_media, u16 *speeds, 2280 u16 speed_msk, const unsigned long *et_mask, 2281 enum ethtool_link_mode_bit_indices mode) 2282 { 2283 bool mode_desired = linkmode_test_bit(mode, et_mask); 2284 2285 if (!mode) 2286 return; 2287 2288 /* enabled speeds for installed media should override */ 2289 if (installed_media && mode_desired) { 2290 *speeds |= speed_msk; 2291 *delta |= speed_msk; 2292 return; 2293 } 2294 2295 /* many to one mapping, only allow one change per fw_speed bit */ 2296 if (!(*delta & speed_msk) && (mode_desired == !(*speeds & speed_msk))) { 2297 *speeds ^= speed_msk; 2298 *delta |= speed_msk; 2299 } 2300 } 2301 2302 static void bnxt_set_ethtool_speeds(struct bnxt_link_info *link_info, 2303 const unsigned long *et_mask) 2304 { 2305 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2306 u16 const *sp_msks, *sp_pam4_msks, *sp_pam4_112_msks; 2307 enum bnxt_media_type media = bnxt_get_media(link_info); 2308 u16 *adv, *adv_pam4, *adv_pam4_112 = NULL; 2309 u32 delta_pam4_112 = 0; 2310 u32 delta_pam4 = 0; 2311 u32 delta_nrz = 0; 2312 int i, m; 2313 2314 adv = &link_info->advertising; 2315 if (bp->phy_flags & BNXT_PHY_FL_SPEEDS2) { 2316 adv_pam4 = &link_info->advertising; 2317 adv_pam4_112 = &link_info->advertising; 2318 sp_msks = bnxt_nrz_speeds2_masks; 2319 sp_pam4_msks = bnxt_pam4_speeds2_masks; 2320 sp_pam4_112_msks = bnxt_pam4_112_speeds2_masks; 2321 } else { 2322 adv_pam4 = &link_info->advertising_pam4; 2323 sp_msks = bnxt_nrz_speed_masks; 2324 sp_pam4_msks = bnxt_pam4_speed_masks; 2325 } 2326 for (i = 1; i < __BNXT_LINK_SPEED_END; i++) { 2327 /* accept any legal media from user */ 2328 for (m = 1; m < __BNXT_MEDIA_END; m++) { 2329 bnxt_update_speed(&delta_nrz, m == media, 2330 adv, sp_msks[i], et_mask, 2331 bnxt_link_modes[i][BNXT_SIG_MODE_NRZ][m]); 2332 bnxt_update_speed(&delta_pam4, m == media, 2333 adv_pam4, sp_pam4_msks[i], et_mask, 2334 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4][m]); 2335 if (!adv_pam4_112) 2336 continue; 2337 2338 bnxt_update_speed(&delta_pam4_112, m == media, 2339 adv_pam4_112, sp_pam4_112_msks[i], et_mask, 2340 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4_112][m]); 2341 } 2342 } 2343 } 2344 2345 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info, 2346 struct ethtool_link_ksettings *lk_ksettings) 2347 { 2348 u16 fec_cfg = link_info->fec_cfg; 2349 2350 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) { 2351 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 2352 lk_ksettings->link_modes.advertising); 2353 return; 2354 } 2355 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 2356 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 2357 lk_ksettings->link_modes.advertising); 2358 if (fec_cfg & BNXT_FEC_ENC_RS) 2359 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 2360 lk_ksettings->link_modes.advertising); 2361 if (fec_cfg & BNXT_FEC_ENC_LLRS) 2362 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 2363 lk_ksettings->link_modes.advertising); 2364 } 2365 2366 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info, 2367 struct ethtool_link_ksettings *lk_ksettings) 2368 { 2369 u16 fec_cfg = link_info->fec_cfg; 2370 2371 if (fec_cfg & BNXT_FEC_NONE) { 2372 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 2373 lk_ksettings->link_modes.supported); 2374 return; 2375 } 2376 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP) 2377 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 2378 lk_ksettings->link_modes.supported); 2379 if (fec_cfg & BNXT_FEC_ENC_RS_CAP) 2380 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 2381 lk_ksettings->link_modes.supported); 2382 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP) 2383 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 2384 lk_ksettings->link_modes.supported); 2385 } 2386 2387 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 2388 { 2389 switch (fw_link_speed) { 2390 case BNXT_LINK_SPEED_100MB: 2391 return SPEED_100; 2392 case BNXT_LINK_SPEED_1GB: 2393 return SPEED_1000; 2394 case BNXT_LINK_SPEED_2_5GB: 2395 return SPEED_2500; 2396 case BNXT_LINK_SPEED_10GB: 2397 return SPEED_10000; 2398 case BNXT_LINK_SPEED_20GB: 2399 return SPEED_20000; 2400 case BNXT_LINK_SPEED_25GB: 2401 return SPEED_25000; 2402 case BNXT_LINK_SPEED_40GB: 2403 return SPEED_40000; 2404 case BNXT_LINK_SPEED_50GB: 2405 case BNXT_LINK_SPEED_50GB_PAM4: 2406 return SPEED_50000; 2407 case BNXT_LINK_SPEED_100GB: 2408 case BNXT_LINK_SPEED_100GB_PAM4: 2409 case BNXT_LINK_SPEED_100GB_PAM4_112: 2410 return SPEED_100000; 2411 case BNXT_LINK_SPEED_200GB: 2412 case BNXT_LINK_SPEED_200GB_PAM4: 2413 case BNXT_LINK_SPEED_200GB_PAM4_112: 2414 return SPEED_200000; 2415 case BNXT_LINK_SPEED_400GB: 2416 case BNXT_LINK_SPEED_400GB_PAM4: 2417 case BNXT_LINK_SPEED_400GB_PAM4_112: 2418 return SPEED_400000; 2419 default: 2420 return SPEED_UNKNOWN; 2421 } 2422 } 2423 2424 static void bnxt_get_default_speeds(struct ethtool_link_ksettings *lk_ksettings, 2425 struct bnxt_link_info *link_info) 2426 { 2427 struct ethtool_link_settings *base = &lk_ksettings->base; 2428 2429 if (link_info->link_state == BNXT_LINK_STATE_UP) { 2430 base->speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 2431 base->duplex = DUPLEX_HALF; 2432 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2433 base->duplex = DUPLEX_FULL; 2434 lk_ksettings->lanes = link_info->active_lanes; 2435 } else if (!link_info->autoneg) { 2436 base->speed = bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 2437 base->duplex = DUPLEX_HALF; 2438 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 2439 base->duplex = DUPLEX_FULL; 2440 } 2441 } 2442 2443 static int bnxt_get_link_ksettings(struct net_device *dev, 2444 struct ethtool_link_ksettings *lk_ksettings) 2445 { 2446 struct ethtool_link_settings *base = &lk_ksettings->base; 2447 enum ethtool_link_mode_bit_indices link_mode; 2448 struct bnxt *bp = netdev_priv(dev); 2449 struct bnxt_link_info *link_info; 2450 enum bnxt_media_type media; 2451 2452 ethtool_link_ksettings_zero_link_mode(lk_ksettings, lp_advertising); 2453 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 2454 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 2455 base->duplex = DUPLEX_UNKNOWN; 2456 base->speed = SPEED_UNKNOWN; 2457 link_info = &bp->link_info; 2458 2459 mutex_lock(&bp->link_lock); 2460 bnxt_get_ethtool_modes(link_info, lk_ksettings); 2461 media = bnxt_get_media(link_info); 2462 bnxt_get_all_ethtool_support_speeds(link_info, media, lk_ksettings); 2463 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings); 2464 link_mode = bnxt_get_link_mode(link_info); 2465 if (link_mode != BNXT_LINK_MODE_UNKNOWN) 2466 ethtool_params_from_link_mode(lk_ksettings, link_mode); 2467 else 2468 bnxt_get_default_speeds(lk_ksettings, link_info); 2469 2470 if (link_info->autoneg) { 2471 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings); 2472 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2473 lk_ksettings->link_modes.advertising); 2474 base->autoneg = AUTONEG_ENABLE; 2475 bnxt_get_all_ethtool_adv_speeds(link_info, media, lk_ksettings); 2476 if (link_info->phy_link_status == BNXT_LINK_LINK) 2477 bnxt_get_all_ethtool_lp_speeds(link_info, media, 2478 lk_ksettings); 2479 } else { 2480 base->autoneg = AUTONEG_DISABLE; 2481 } 2482 2483 base->port = PORT_NONE; 2484 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 2485 base->port = PORT_TP; 2486 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2487 lk_ksettings->link_modes.supported); 2488 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2489 lk_ksettings->link_modes.advertising); 2490 } else { 2491 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 2492 lk_ksettings->link_modes.supported); 2493 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 2494 lk_ksettings->link_modes.advertising); 2495 2496 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC) 2497 base->port = PORT_DA; 2498 else 2499 base->port = PORT_FIBRE; 2500 } 2501 base->phy_address = link_info->phy_addr; 2502 mutex_unlock(&bp->link_lock); 2503 2504 return 0; 2505 } 2506 2507 static int 2508 bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed, u32 lanes) 2509 { 2510 struct bnxt *bp = netdev_priv(dev); 2511 struct bnxt_link_info *link_info = &bp->link_info; 2512 u16 support_pam4_spds = link_info->support_pam4_speeds; 2513 u16 support_spds2 = link_info->support_speeds2; 2514 u16 support_spds = link_info->support_speeds; 2515 u8 sig_mode = BNXT_SIG_MODE_NRZ; 2516 u32 lanes_needed = 1; 2517 u16 fw_speed = 0; 2518 2519 switch (ethtool_speed) { 2520 case SPEED_100: 2521 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 2522 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB; 2523 break; 2524 case SPEED_1000: 2525 if ((support_spds & BNXT_LINK_SPEED_MSK_1GB) || 2526 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_1GB)) 2527 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 2528 break; 2529 case SPEED_2500: 2530 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 2531 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB; 2532 break; 2533 case SPEED_10000: 2534 if ((support_spds & BNXT_LINK_SPEED_MSK_10GB) || 2535 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_10GB)) 2536 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 2537 break; 2538 case SPEED_20000: 2539 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) { 2540 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB; 2541 lanes_needed = 2; 2542 } 2543 break; 2544 case SPEED_25000: 2545 if ((support_spds & BNXT_LINK_SPEED_MSK_25GB) || 2546 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_25GB)) 2547 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 2548 break; 2549 case SPEED_40000: 2550 if ((support_spds & BNXT_LINK_SPEED_MSK_40GB) || 2551 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_40GB)) { 2552 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 2553 lanes_needed = 4; 2554 } 2555 break; 2556 case SPEED_50000: 2557 if (((support_spds & BNXT_LINK_SPEED_MSK_50GB) || 2558 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB)) && 2559 lanes != 1) { 2560 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 2561 lanes_needed = 2; 2562 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) { 2563 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB; 2564 sig_mode = BNXT_SIG_MODE_PAM4; 2565 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB_PAM4) { 2566 fw_speed = BNXT_LINK_SPEED_50GB_PAM4; 2567 sig_mode = BNXT_SIG_MODE_PAM4; 2568 } 2569 break; 2570 case SPEED_100000: 2571 if (((support_spds & BNXT_LINK_SPEED_MSK_100GB) || 2572 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB)) && 2573 lanes != 2 && lanes != 1) { 2574 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB; 2575 lanes_needed = 4; 2576 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) { 2577 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB; 2578 sig_mode = BNXT_SIG_MODE_PAM4; 2579 lanes_needed = 2; 2580 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4) && 2581 lanes != 1) { 2582 fw_speed = BNXT_LINK_SPEED_100GB_PAM4; 2583 sig_mode = BNXT_SIG_MODE_PAM4; 2584 lanes_needed = 2; 2585 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112) { 2586 fw_speed = BNXT_LINK_SPEED_100GB_PAM4_112; 2587 sig_mode = BNXT_SIG_MODE_PAM4_112; 2588 } 2589 break; 2590 case SPEED_200000: 2591 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) { 2592 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB; 2593 sig_mode = BNXT_SIG_MODE_PAM4; 2594 lanes_needed = 4; 2595 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4) && 2596 lanes != 2) { 2597 fw_speed = BNXT_LINK_SPEED_200GB_PAM4; 2598 sig_mode = BNXT_SIG_MODE_PAM4; 2599 lanes_needed = 4; 2600 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112) { 2601 fw_speed = BNXT_LINK_SPEED_200GB_PAM4_112; 2602 sig_mode = BNXT_SIG_MODE_PAM4_112; 2603 lanes_needed = 2; 2604 } 2605 break; 2606 case SPEED_400000: 2607 if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4) && 2608 lanes != 4) { 2609 fw_speed = BNXT_LINK_SPEED_400GB_PAM4; 2610 sig_mode = BNXT_SIG_MODE_PAM4; 2611 lanes_needed = 8; 2612 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112) { 2613 fw_speed = BNXT_LINK_SPEED_400GB_PAM4_112; 2614 sig_mode = BNXT_SIG_MODE_PAM4_112; 2615 lanes_needed = 4; 2616 } 2617 break; 2618 } 2619 2620 if (!fw_speed) { 2621 netdev_err(dev, "unsupported speed!\n"); 2622 return -EINVAL; 2623 } 2624 2625 if (lanes && lanes != lanes_needed) { 2626 netdev_err(dev, "unsupported number of lanes for speed\n"); 2627 return -EINVAL; 2628 } 2629 2630 if (link_info->req_link_speed == fw_speed && 2631 link_info->req_signal_mode == sig_mode && 2632 link_info->autoneg == 0) 2633 return -EALREADY; 2634 2635 link_info->req_link_speed = fw_speed; 2636 link_info->req_signal_mode = sig_mode; 2637 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 2638 link_info->autoneg = 0; 2639 link_info->advertising = 0; 2640 link_info->advertising_pam4 = 0; 2641 2642 return 0; 2643 } 2644 2645 u16 bnxt_get_fw_auto_link_speeds(u32 advertising) 2646 { 2647 u16 fw_speed_mask = 0; 2648 2649 /* only support autoneg at speed 100, 1000, and 10000 */ 2650 if (advertising & (ADVERTISED_100baseT_Full | 2651 ADVERTISED_100baseT_Half)) { 2652 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 2653 } 2654 if (advertising & (ADVERTISED_1000baseT_Full | 2655 ADVERTISED_1000baseT_Half)) { 2656 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 2657 } 2658 if (advertising & ADVERTISED_10000baseT_Full) 2659 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 2660 2661 if (advertising & ADVERTISED_40000baseCR4_Full) 2662 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 2663 2664 return fw_speed_mask; 2665 } 2666 2667 static int bnxt_set_link_ksettings(struct net_device *dev, 2668 const struct ethtool_link_ksettings *lk_ksettings) 2669 { 2670 struct bnxt *bp = netdev_priv(dev); 2671 struct bnxt_link_info *link_info = &bp->link_info; 2672 const struct ethtool_link_settings *base = &lk_ksettings->base; 2673 bool set_pause = false; 2674 u32 speed, lanes = 0; 2675 int rc = 0; 2676 2677 if (!BNXT_PHY_CFG_ABLE(bp)) 2678 return -EOPNOTSUPP; 2679 2680 mutex_lock(&bp->link_lock); 2681 if (base->autoneg == AUTONEG_ENABLE) { 2682 bnxt_set_ethtool_speeds(link_info, 2683 lk_ksettings->link_modes.advertising); 2684 link_info->autoneg |= BNXT_AUTONEG_SPEED; 2685 if (!link_info->advertising && !link_info->advertising_pam4) { 2686 link_info->advertising = link_info->support_auto_speeds; 2687 link_info->advertising_pam4 = 2688 link_info->support_pam4_auto_speeds; 2689 } 2690 /* any change to autoneg will cause link change, therefore the 2691 * driver should put back the original pause setting in autoneg 2692 */ 2693 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 2694 set_pause = true; 2695 } else { 2696 u8 phy_type = link_info->phy_type; 2697 2698 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 2699 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 2700 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 2701 netdev_err(dev, "10GBase-T devices must autoneg\n"); 2702 rc = -EINVAL; 2703 goto set_setting_exit; 2704 } 2705 if (base->duplex == DUPLEX_HALF) { 2706 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 2707 rc = -EINVAL; 2708 goto set_setting_exit; 2709 } 2710 speed = base->speed; 2711 lanes = lk_ksettings->lanes; 2712 rc = bnxt_force_link_speed(dev, speed, lanes); 2713 if (rc) { 2714 if (rc == -EALREADY) 2715 rc = 0; 2716 goto set_setting_exit; 2717 } 2718 } 2719 2720 if (netif_running(dev)) 2721 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 2722 2723 set_setting_exit: 2724 mutex_unlock(&bp->link_lock); 2725 return rc; 2726 } 2727 2728 static int bnxt_get_fecparam(struct net_device *dev, 2729 struct ethtool_fecparam *fec) 2730 { 2731 struct bnxt *bp = netdev_priv(dev); 2732 struct bnxt_link_info *link_info; 2733 u8 active_fec; 2734 u16 fec_cfg; 2735 2736 link_info = &bp->link_info; 2737 fec_cfg = link_info->fec_cfg; 2738 active_fec = link_info->active_fec_sig_mode & 2739 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK; 2740 if (fec_cfg & BNXT_FEC_NONE) { 2741 fec->fec = ETHTOOL_FEC_NONE; 2742 fec->active_fec = ETHTOOL_FEC_NONE; 2743 return 0; 2744 } 2745 if (fec_cfg & BNXT_FEC_AUTONEG) 2746 fec->fec |= ETHTOOL_FEC_AUTO; 2747 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 2748 fec->fec |= ETHTOOL_FEC_BASER; 2749 if (fec_cfg & BNXT_FEC_ENC_RS) 2750 fec->fec |= ETHTOOL_FEC_RS; 2751 if (fec_cfg & BNXT_FEC_ENC_LLRS) 2752 fec->fec |= ETHTOOL_FEC_LLRS; 2753 2754 switch (active_fec) { 2755 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE: 2756 fec->active_fec |= ETHTOOL_FEC_BASER; 2757 break; 2758 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE: 2759 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE: 2760 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE: 2761 fec->active_fec |= ETHTOOL_FEC_RS; 2762 break; 2763 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE: 2764 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE: 2765 fec->active_fec |= ETHTOOL_FEC_LLRS; 2766 break; 2767 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE: 2768 fec->active_fec |= ETHTOOL_FEC_OFF; 2769 break; 2770 } 2771 return 0; 2772 } 2773 2774 static void bnxt_get_fec_stats(struct net_device *dev, 2775 struct ethtool_fec_stats *fec_stats) 2776 { 2777 struct bnxt *bp = netdev_priv(dev); 2778 u64 *rx; 2779 2780 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 2781 return; 2782 2783 rx = bp->rx_port_stats_ext.sw_stats; 2784 fec_stats->corrected_bits.total = 2785 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits)); 2786 2787 if (bp->fw_rx_stats_ext_size <= BNXT_RX_STATS_EXT_NUM_LEGACY) 2788 return; 2789 2790 fec_stats->corrected_blocks.total = 2791 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)); 2792 fec_stats->uncorrectable_blocks.total = 2793 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_uncorrectable_blocks)); 2794 } 2795 2796 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info, 2797 u32 fec) 2798 { 2799 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE; 2800 2801 if (fec & ETHTOOL_FEC_BASER) 2802 fw_fec |= BNXT_FEC_BASE_R_ON(link_info); 2803 else if (fec & ETHTOOL_FEC_RS) 2804 fw_fec |= BNXT_FEC_RS_ON(link_info); 2805 else if (fec & ETHTOOL_FEC_LLRS) 2806 fw_fec |= BNXT_FEC_LLRS_ON; 2807 return fw_fec; 2808 } 2809 2810 static int bnxt_set_fecparam(struct net_device *dev, 2811 struct ethtool_fecparam *fecparam) 2812 { 2813 struct hwrm_port_phy_cfg_input *req; 2814 struct bnxt *bp = netdev_priv(dev); 2815 struct bnxt_link_info *link_info; 2816 u32 new_cfg, fec = fecparam->fec; 2817 u16 fec_cfg; 2818 int rc; 2819 2820 link_info = &bp->link_info; 2821 fec_cfg = link_info->fec_cfg; 2822 if (fec_cfg & BNXT_FEC_NONE) 2823 return -EOPNOTSUPP; 2824 2825 if (fec & ETHTOOL_FEC_OFF) { 2826 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE | 2827 BNXT_FEC_ALL_OFF(link_info); 2828 goto apply_fec; 2829 } 2830 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) || 2831 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) || 2832 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) || 2833 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP))) 2834 return -EINVAL; 2835 2836 if (fec & ETHTOOL_FEC_AUTO) { 2837 if (!link_info->autoneg) 2838 return -EINVAL; 2839 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE; 2840 } else { 2841 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec); 2842 } 2843 2844 apply_fec: 2845 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 2846 if (rc) 2847 return rc; 2848 req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 2849 rc = hwrm_req_send(bp, req); 2850 /* update current settings */ 2851 if (!rc) { 2852 mutex_lock(&bp->link_lock); 2853 bnxt_update_link(bp, false); 2854 mutex_unlock(&bp->link_lock); 2855 } 2856 return rc; 2857 } 2858 2859 static void bnxt_get_pauseparam(struct net_device *dev, 2860 struct ethtool_pauseparam *epause) 2861 { 2862 struct bnxt *bp = netdev_priv(dev); 2863 struct bnxt_link_info *link_info = &bp->link_info; 2864 2865 if (BNXT_VF(bp)) 2866 return; 2867 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 2868 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 2869 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 2870 } 2871 2872 static void bnxt_get_pause_stats(struct net_device *dev, 2873 struct ethtool_pause_stats *epstat) 2874 { 2875 struct bnxt *bp = netdev_priv(dev); 2876 u64 *rx, *tx; 2877 2878 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 2879 return; 2880 2881 rx = bp->port_stats.sw_stats; 2882 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 2883 2884 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames); 2885 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames); 2886 } 2887 2888 static int bnxt_set_pauseparam(struct net_device *dev, 2889 struct ethtool_pauseparam *epause) 2890 { 2891 int rc = 0; 2892 struct bnxt *bp = netdev_priv(dev); 2893 struct bnxt_link_info *link_info = &bp->link_info; 2894 2895 if (!BNXT_PHY_CFG_ABLE(bp) || (bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 2896 return -EOPNOTSUPP; 2897 2898 mutex_lock(&bp->link_lock); 2899 if (epause->autoneg) { 2900 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 2901 rc = -EINVAL; 2902 goto pause_exit; 2903 } 2904 2905 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 2906 link_info->req_flow_ctrl = 0; 2907 } else { 2908 /* when transition from auto pause to force pause, 2909 * force a link change 2910 */ 2911 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 2912 link_info->force_link_chng = true; 2913 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 2914 link_info->req_flow_ctrl = 0; 2915 } 2916 if (epause->rx_pause) 2917 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 2918 2919 if (epause->tx_pause) 2920 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 2921 2922 if (netif_running(dev)) 2923 rc = bnxt_hwrm_set_pause(bp); 2924 2925 pause_exit: 2926 mutex_unlock(&bp->link_lock); 2927 return rc; 2928 } 2929 2930 static u32 bnxt_get_link(struct net_device *dev) 2931 { 2932 struct bnxt *bp = netdev_priv(dev); 2933 2934 /* TODO: handle MF, VF, driver close case */ 2935 return BNXT_LINK_IS_UP(bp); 2936 } 2937 2938 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp, 2939 struct hwrm_nvm_get_dev_info_output *nvm_dev_info) 2940 { 2941 struct hwrm_nvm_get_dev_info_output *resp; 2942 struct hwrm_nvm_get_dev_info_input *req; 2943 int rc; 2944 2945 if (BNXT_VF(bp)) 2946 return -EOPNOTSUPP; 2947 2948 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO); 2949 if (rc) 2950 return rc; 2951 2952 resp = hwrm_req_hold(bp, req); 2953 rc = hwrm_req_send(bp, req); 2954 if (!rc) 2955 memcpy(nvm_dev_info, resp, sizeof(*resp)); 2956 hwrm_req_drop(bp, req); 2957 return rc; 2958 } 2959 2960 static void bnxt_print_admin_err(struct bnxt *bp) 2961 { 2962 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 2963 } 2964 2965 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 2966 u16 ext, u16 *index, u32 *item_length, 2967 u32 *data_length); 2968 2969 int bnxt_flash_nvram(struct net_device *dev, u16 dir_type, 2970 u16 dir_ordinal, u16 dir_ext, u16 dir_attr, 2971 u32 dir_item_len, const u8 *data, 2972 size_t data_len) 2973 { 2974 struct bnxt *bp = netdev_priv(dev); 2975 struct hwrm_nvm_write_input *req; 2976 int rc; 2977 2978 rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE); 2979 if (rc) 2980 return rc; 2981 2982 if (data_len && data) { 2983 dma_addr_t dma_handle; 2984 u8 *kmem; 2985 2986 kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle); 2987 if (!kmem) { 2988 hwrm_req_drop(bp, req); 2989 return -ENOMEM; 2990 } 2991 2992 req->dir_data_length = cpu_to_le32(data_len); 2993 2994 memcpy(kmem, data, data_len); 2995 req->host_src_addr = cpu_to_le64(dma_handle); 2996 } 2997 2998 hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout); 2999 req->dir_type = cpu_to_le16(dir_type); 3000 req->dir_ordinal = cpu_to_le16(dir_ordinal); 3001 req->dir_ext = cpu_to_le16(dir_ext); 3002 req->dir_attr = cpu_to_le16(dir_attr); 3003 req->dir_item_length = cpu_to_le32(dir_item_len); 3004 rc = hwrm_req_send(bp, req); 3005 3006 if (rc == -EACCES) 3007 bnxt_print_admin_err(bp); 3008 return rc; 3009 } 3010 3011 int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type, 3012 u8 self_reset, u8 flags) 3013 { 3014 struct bnxt *bp = netdev_priv(dev); 3015 struct hwrm_fw_reset_input *req; 3016 int rc; 3017 3018 if (!bnxt_hwrm_reset_permitted(bp)) { 3019 netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver"); 3020 return -EPERM; 3021 } 3022 3023 rc = hwrm_req_init(bp, req, HWRM_FW_RESET); 3024 if (rc) 3025 return rc; 3026 3027 req->embedded_proc_type = proc_type; 3028 req->selfrst_status = self_reset; 3029 req->flags = flags; 3030 3031 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) { 3032 rc = hwrm_req_send_silent(bp, req); 3033 } else { 3034 rc = hwrm_req_send(bp, req); 3035 if (rc == -EACCES) 3036 bnxt_print_admin_err(bp); 3037 } 3038 return rc; 3039 } 3040 3041 static int bnxt_firmware_reset(struct net_device *dev, 3042 enum bnxt_nvm_directory_type dir_type) 3043 { 3044 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE; 3045 u8 proc_type, flags = 0; 3046 3047 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 3048 /* (e.g. when firmware isn't already running) */ 3049 switch (dir_type) { 3050 case BNX_DIR_TYPE_CHIMP_PATCH: 3051 case BNX_DIR_TYPE_BOOTCODE: 3052 case BNX_DIR_TYPE_BOOTCODE_2: 3053 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 3054 /* Self-reset ChiMP upon next PCIe reset: */ 3055 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 3056 break; 3057 case BNX_DIR_TYPE_APE_FW: 3058 case BNX_DIR_TYPE_APE_PATCH: 3059 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 3060 /* Self-reset APE upon next PCIe reset: */ 3061 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 3062 break; 3063 case BNX_DIR_TYPE_KONG_FW: 3064 case BNX_DIR_TYPE_KONG_PATCH: 3065 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 3066 break; 3067 case BNX_DIR_TYPE_BONO_FW: 3068 case BNX_DIR_TYPE_BONO_PATCH: 3069 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 3070 break; 3071 default: 3072 return -EINVAL; 3073 } 3074 3075 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags); 3076 } 3077 3078 static int bnxt_firmware_reset_chip(struct net_device *dev) 3079 { 3080 struct bnxt *bp = netdev_priv(dev); 3081 u8 flags = 0; 3082 3083 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 3084 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 3085 3086 return bnxt_hwrm_firmware_reset(dev, 3087 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP, 3088 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP, 3089 flags); 3090 } 3091 3092 static int bnxt_firmware_reset_ap(struct net_device *dev) 3093 { 3094 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP, 3095 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE, 3096 0); 3097 } 3098 3099 static int bnxt_flash_firmware(struct net_device *dev, 3100 u16 dir_type, 3101 const u8 *fw_data, 3102 size_t fw_size) 3103 { 3104 int rc = 0; 3105 u16 code_type; 3106 u32 stored_crc; 3107 u32 calculated_crc; 3108 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 3109 3110 switch (dir_type) { 3111 case BNX_DIR_TYPE_BOOTCODE: 3112 case BNX_DIR_TYPE_BOOTCODE_2: 3113 code_type = CODE_BOOT; 3114 break; 3115 case BNX_DIR_TYPE_CHIMP_PATCH: 3116 code_type = CODE_CHIMP_PATCH; 3117 break; 3118 case BNX_DIR_TYPE_APE_FW: 3119 code_type = CODE_MCTP_PASSTHRU; 3120 break; 3121 case BNX_DIR_TYPE_APE_PATCH: 3122 code_type = CODE_APE_PATCH; 3123 break; 3124 case BNX_DIR_TYPE_KONG_FW: 3125 code_type = CODE_KONG_FW; 3126 break; 3127 case BNX_DIR_TYPE_KONG_PATCH: 3128 code_type = CODE_KONG_PATCH; 3129 break; 3130 case BNX_DIR_TYPE_BONO_FW: 3131 code_type = CODE_BONO_FW; 3132 break; 3133 case BNX_DIR_TYPE_BONO_PATCH: 3134 code_type = CODE_BONO_PATCH; 3135 break; 3136 default: 3137 netdev_err(dev, "Unsupported directory entry type: %u\n", 3138 dir_type); 3139 return -EINVAL; 3140 } 3141 if (fw_size < sizeof(struct bnxt_fw_header)) { 3142 netdev_err(dev, "Invalid firmware file size: %u\n", 3143 (unsigned int)fw_size); 3144 return -EINVAL; 3145 } 3146 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 3147 netdev_err(dev, "Invalid firmware signature: %08X\n", 3148 le32_to_cpu(header->signature)); 3149 return -EINVAL; 3150 } 3151 if (header->code_type != code_type) { 3152 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 3153 code_type, header->code_type); 3154 return -EINVAL; 3155 } 3156 if (header->device != DEVICE_CUMULUS_FAMILY) { 3157 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 3158 DEVICE_CUMULUS_FAMILY, header->device); 3159 return -EINVAL; 3160 } 3161 /* Confirm the CRC32 checksum of the file: */ 3162 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 3163 sizeof(stored_crc))); 3164 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 3165 if (calculated_crc != stored_crc) { 3166 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 3167 (unsigned long)stored_crc, 3168 (unsigned long)calculated_crc); 3169 return -EINVAL; 3170 } 3171 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3172 0, 0, 0, fw_data, fw_size); 3173 if (rc == 0) /* Firmware update successful */ 3174 rc = bnxt_firmware_reset(dev, dir_type); 3175 3176 return rc; 3177 } 3178 3179 static int bnxt_flash_microcode(struct net_device *dev, 3180 u16 dir_type, 3181 const u8 *fw_data, 3182 size_t fw_size) 3183 { 3184 struct bnxt_ucode_trailer *trailer; 3185 u32 calculated_crc; 3186 u32 stored_crc; 3187 int rc = 0; 3188 3189 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 3190 netdev_err(dev, "Invalid microcode file size: %u\n", 3191 (unsigned int)fw_size); 3192 return -EINVAL; 3193 } 3194 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 3195 sizeof(*trailer))); 3196 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 3197 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 3198 le32_to_cpu(trailer->sig)); 3199 return -EINVAL; 3200 } 3201 if (le16_to_cpu(trailer->dir_type) != dir_type) { 3202 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 3203 dir_type, le16_to_cpu(trailer->dir_type)); 3204 return -EINVAL; 3205 } 3206 if (le16_to_cpu(trailer->trailer_length) < 3207 sizeof(struct bnxt_ucode_trailer)) { 3208 netdev_err(dev, "Invalid microcode trailer length: %d\n", 3209 le16_to_cpu(trailer->trailer_length)); 3210 return -EINVAL; 3211 } 3212 3213 /* Confirm the CRC32 checksum of the file: */ 3214 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 3215 sizeof(stored_crc))); 3216 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 3217 if (calculated_crc != stored_crc) { 3218 netdev_err(dev, 3219 "CRC32 (%08lX) does not match calculated: %08lX\n", 3220 (unsigned long)stored_crc, 3221 (unsigned long)calculated_crc); 3222 return -EINVAL; 3223 } 3224 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3225 0, 0, 0, fw_data, fw_size); 3226 3227 return rc; 3228 } 3229 3230 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 3231 { 3232 switch (dir_type) { 3233 case BNX_DIR_TYPE_CHIMP_PATCH: 3234 case BNX_DIR_TYPE_BOOTCODE: 3235 case BNX_DIR_TYPE_BOOTCODE_2: 3236 case BNX_DIR_TYPE_APE_FW: 3237 case BNX_DIR_TYPE_APE_PATCH: 3238 case BNX_DIR_TYPE_KONG_FW: 3239 case BNX_DIR_TYPE_KONG_PATCH: 3240 case BNX_DIR_TYPE_BONO_FW: 3241 case BNX_DIR_TYPE_BONO_PATCH: 3242 return true; 3243 } 3244 3245 return false; 3246 } 3247 3248 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 3249 { 3250 switch (dir_type) { 3251 case BNX_DIR_TYPE_AVS: 3252 case BNX_DIR_TYPE_EXP_ROM_MBA: 3253 case BNX_DIR_TYPE_PCIE: 3254 case BNX_DIR_TYPE_TSCF_UCODE: 3255 case BNX_DIR_TYPE_EXT_PHY: 3256 case BNX_DIR_TYPE_CCM: 3257 case BNX_DIR_TYPE_ISCSI_BOOT: 3258 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 3259 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 3260 return true; 3261 } 3262 3263 return false; 3264 } 3265 3266 static bool bnxt_dir_type_is_executable(u16 dir_type) 3267 { 3268 return bnxt_dir_type_is_ape_bin_format(dir_type) || 3269 bnxt_dir_type_is_other_exec_format(dir_type); 3270 } 3271 3272 static int bnxt_flash_firmware_from_file(struct net_device *dev, 3273 u16 dir_type, 3274 const char *filename) 3275 { 3276 const struct firmware *fw; 3277 int rc; 3278 3279 rc = request_firmware(&fw, filename, &dev->dev); 3280 if (rc != 0) { 3281 netdev_err(dev, "Error %d requesting firmware file: %s\n", 3282 rc, filename); 3283 return rc; 3284 } 3285 if (bnxt_dir_type_is_ape_bin_format(dir_type)) 3286 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 3287 else if (bnxt_dir_type_is_other_exec_format(dir_type)) 3288 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 3289 else 3290 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3291 0, 0, 0, fw->data, fw->size); 3292 release_firmware(fw); 3293 return rc; 3294 } 3295 3296 #define MSG_INTEGRITY_ERR "PKG install error : Data integrity on NVM" 3297 #define MSG_INVALID_PKG "PKG install error : Invalid package" 3298 #define MSG_AUTHENTICATION_ERR "PKG install error : Authentication error" 3299 #define MSG_INVALID_DEV "PKG install error : Invalid device" 3300 #define MSG_INTERNAL_ERR "PKG install error : Internal error" 3301 #define MSG_NO_PKG_UPDATE_AREA_ERR "PKG update area not created in nvram" 3302 #define MSG_NO_SPACE_ERR "PKG insufficient update area in nvram" 3303 #define MSG_RESIZE_UPDATE_ERR "Resize UPDATE entry error" 3304 #define MSG_ANTI_ROLLBACK_ERR "HWRM_NVM_INSTALL_UPDATE failure due to Anti-rollback detected" 3305 #define MSG_GENERIC_FAILURE_ERR "HWRM_NVM_INSTALL_UPDATE failure" 3306 3307 static int nvm_update_err_to_stderr(struct net_device *dev, u8 result, 3308 struct netlink_ext_ack *extack) 3309 { 3310 switch (result) { 3311 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER: 3312 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER: 3313 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR: 3314 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR: 3315 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND: 3316 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED: 3317 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTEGRITY_ERR); 3318 return -EINVAL; 3319 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE: 3320 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER: 3321 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE: 3322 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM: 3323 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH: 3324 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST: 3325 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER: 3326 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM: 3327 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM: 3328 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH: 3329 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE: 3330 case NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM: 3331 case NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM: 3332 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_PKG); 3333 return -ENOPKG; 3334 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR: 3335 BNXT_NVM_ERR_MSG(dev, extack, MSG_AUTHENTICATION_ERR); 3336 return -EPERM; 3337 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV: 3338 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID: 3339 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR: 3340 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID: 3341 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM: 3342 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_DEV); 3343 return -EOPNOTSUPP; 3344 default: 3345 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTERNAL_ERR); 3346 return -EIO; 3347 } 3348 } 3349 3350 #define BNXT_PKG_DMA_SIZE 0x40000 3351 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE)) 3352 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST)) 3353 3354 static int bnxt_resize_update_entry(struct net_device *dev, size_t fw_size, 3355 struct netlink_ext_ack *extack) 3356 { 3357 u32 item_len; 3358 int rc; 3359 3360 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 3361 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, NULL, 3362 &item_len, NULL); 3363 if (rc) { 3364 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 3365 return rc; 3366 } 3367 3368 if (fw_size > item_len) { 3369 rc = bnxt_flash_nvram(dev, BNX_DIR_TYPE_UPDATE, 3370 BNX_DIR_ORDINAL_FIRST, 0, 1, 3371 round_up(fw_size, 4096), NULL, 0); 3372 if (rc) { 3373 BNXT_NVM_ERR_MSG(dev, extack, MSG_RESIZE_UPDATE_ERR); 3374 return rc; 3375 } 3376 } 3377 return 0; 3378 } 3379 3380 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw, 3381 u32 install_type, struct netlink_ext_ack *extack) 3382 { 3383 struct hwrm_nvm_install_update_input *install; 3384 struct hwrm_nvm_install_update_output *resp; 3385 struct hwrm_nvm_modify_input *modify; 3386 struct bnxt *bp = netdev_priv(dev); 3387 bool defrag_attempted = false; 3388 dma_addr_t dma_handle; 3389 u8 *kmem = NULL; 3390 u32 modify_len; 3391 u32 item_len; 3392 u8 cmd_err; 3393 u16 index; 3394 int rc; 3395 3396 /* resize before flashing larger image than available space */ 3397 rc = bnxt_resize_update_entry(dev, fw->size, extack); 3398 if (rc) 3399 return rc; 3400 3401 bnxt_hwrm_fw_set_time(bp); 3402 3403 rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY); 3404 if (rc) 3405 return rc; 3406 3407 /* Try allocating a large DMA buffer first. Older fw will 3408 * cause excessive NVRAM erases when using small blocks. 3409 */ 3410 modify_len = roundup_pow_of_two(fw->size); 3411 modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE); 3412 while (1) { 3413 kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle); 3414 if (!kmem && modify_len > PAGE_SIZE) 3415 modify_len /= 2; 3416 else 3417 break; 3418 } 3419 if (!kmem) { 3420 hwrm_req_drop(bp, modify); 3421 return -ENOMEM; 3422 } 3423 3424 rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE); 3425 if (rc) { 3426 hwrm_req_drop(bp, modify); 3427 return rc; 3428 } 3429 3430 hwrm_req_timeout(bp, modify, bp->hwrm_cmd_max_timeout); 3431 hwrm_req_timeout(bp, install, bp->hwrm_cmd_max_timeout); 3432 3433 hwrm_req_hold(bp, modify); 3434 modify->host_src_addr = cpu_to_le64(dma_handle); 3435 3436 resp = hwrm_req_hold(bp, install); 3437 if ((install_type & 0xffff) == 0) 3438 install_type >>= 16; 3439 install->install_type = cpu_to_le32(install_type); 3440 3441 do { 3442 u32 copied = 0, len = modify_len; 3443 3444 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 3445 BNX_DIR_ORDINAL_FIRST, 3446 BNX_DIR_EXT_NONE, 3447 &index, &item_len, NULL); 3448 if (rc) { 3449 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 3450 break; 3451 } 3452 if (fw->size > item_len) { 3453 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_SPACE_ERR); 3454 rc = -EFBIG; 3455 break; 3456 } 3457 3458 modify->dir_idx = cpu_to_le16(index); 3459 3460 if (fw->size > modify_len) 3461 modify->flags = BNXT_NVM_MORE_FLAG; 3462 while (copied < fw->size) { 3463 u32 balance = fw->size - copied; 3464 3465 if (balance <= modify_len) { 3466 len = balance; 3467 if (copied) 3468 modify->flags |= BNXT_NVM_LAST_FLAG; 3469 } 3470 memcpy(kmem, fw->data + copied, len); 3471 modify->len = cpu_to_le32(len); 3472 modify->offset = cpu_to_le32(copied); 3473 rc = hwrm_req_send(bp, modify); 3474 if (rc) 3475 goto pkg_abort; 3476 copied += len; 3477 } 3478 3479 rc = hwrm_req_send_silent(bp, install); 3480 if (!rc) 3481 break; 3482 3483 if (defrag_attempted) { 3484 /* We have tried to defragment already in the previous 3485 * iteration. Return with the result for INSTALL_UPDATE 3486 */ 3487 break; 3488 } 3489 3490 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 3491 3492 switch (cmd_err) { 3493 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK: 3494 BNXT_NVM_ERR_MSG(dev, extack, MSG_ANTI_ROLLBACK_ERR); 3495 rc = -EALREADY; 3496 break; 3497 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR: 3498 install->flags = 3499 cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 3500 3501 rc = hwrm_req_send_silent(bp, install); 3502 if (!rc) 3503 break; 3504 3505 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 3506 3507 if (cmd_err == NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) { 3508 /* FW has cleared NVM area, driver will create 3509 * UPDATE directory and try the flash again 3510 */ 3511 defrag_attempted = true; 3512 install->flags = 0; 3513 rc = bnxt_flash_nvram(bp->dev, 3514 BNX_DIR_TYPE_UPDATE, 3515 BNX_DIR_ORDINAL_FIRST, 3516 0, 0, item_len, NULL, 0); 3517 if (!rc) 3518 break; 3519 } 3520 fallthrough; 3521 default: 3522 BNXT_NVM_ERR_MSG(dev, extack, MSG_GENERIC_FAILURE_ERR); 3523 } 3524 } while (defrag_attempted && !rc); 3525 3526 pkg_abort: 3527 hwrm_req_drop(bp, modify); 3528 hwrm_req_drop(bp, install); 3529 3530 if (resp->result) { 3531 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 3532 (s8)resp->result, (int)resp->problem_item); 3533 rc = nvm_update_err_to_stderr(dev, resp->result, extack); 3534 } 3535 if (rc == -EACCES) 3536 bnxt_print_admin_err(bp); 3537 return rc; 3538 } 3539 3540 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename, 3541 u32 install_type, struct netlink_ext_ack *extack) 3542 { 3543 const struct firmware *fw; 3544 int rc; 3545 3546 rc = request_firmware(&fw, filename, &dev->dev); 3547 if (rc != 0) { 3548 netdev_err(dev, "PKG error %d requesting file: %s\n", 3549 rc, filename); 3550 return rc; 3551 } 3552 3553 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type, extack); 3554 3555 release_firmware(fw); 3556 3557 return rc; 3558 } 3559 3560 static int bnxt_flash_device(struct net_device *dev, 3561 struct ethtool_flash *flash) 3562 { 3563 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 3564 netdev_err(dev, "flashdev not supported from a virtual function\n"); 3565 return -EINVAL; 3566 } 3567 3568 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 3569 flash->region > 0xffff) 3570 return bnxt_flash_package_from_file(dev, flash->data, 3571 flash->region, NULL); 3572 3573 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 3574 } 3575 3576 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 3577 { 3578 struct hwrm_nvm_get_dir_info_output *output; 3579 struct hwrm_nvm_get_dir_info_input *req; 3580 struct bnxt *bp = netdev_priv(dev); 3581 int rc; 3582 3583 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO); 3584 if (rc) 3585 return rc; 3586 3587 output = hwrm_req_hold(bp, req); 3588 rc = hwrm_req_send(bp, req); 3589 if (!rc) { 3590 *entries = le32_to_cpu(output->entries); 3591 *length = le32_to_cpu(output->entry_length); 3592 } 3593 hwrm_req_drop(bp, req); 3594 return rc; 3595 } 3596 3597 static int bnxt_get_eeprom_len(struct net_device *dev) 3598 { 3599 struct bnxt *bp = netdev_priv(dev); 3600 3601 if (BNXT_VF(bp)) 3602 return 0; 3603 3604 /* The -1 return value allows the entire 32-bit range of offsets to be 3605 * passed via the ethtool command-line utility. 3606 */ 3607 return -1; 3608 } 3609 3610 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 3611 { 3612 struct bnxt *bp = netdev_priv(dev); 3613 int rc; 3614 u32 dir_entries; 3615 u32 entry_length; 3616 u8 *buf; 3617 size_t buflen; 3618 dma_addr_t dma_handle; 3619 struct hwrm_nvm_get_dir_entries_input *req; 3620 3621 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 3622 if (rc != 0) 3623 return rc; 3624 3625 if (!dir_entries || !entry_length) 3626 return -EIO; 3627 3628 /* Insert 2 bytes of directory info (count and size of entries) */ 3629 if (len < 2) 3630 return -EINVAL; 3631 3632 *data++ = dir_entries; 3633 *data++ = entry_length; 3634 len -= 2; 3635 memset(data, 0xff, len); 3636 3637 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES); 3638 if (rc) 3639 return rc; 3640 3641 buflen = mul_u32_u32(dir_entries, entry_length); 3642 buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle); 3643 if (!buf) { 3644 hwrm_req_drop(bp, req); 3645 return -ENOMEM; 3646 } 3647 req->host_dest_addr = cpu_to_le64(dma_handle); 3648 3649 hwrm_req_hold(bp, req); /* hold the slice */ 3650 rc = hwrm_req_send(bp, req); 3651 if (rc == 0) 3652 memcpy(data, buf, len > buflen ? buflen : len); 3653 hwrm_req_drop(bp, req); 3654 return rc; 3655 } 3656 3657 int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 3658 u32 length, u8 *data) 3659 { 3660 struct bnxt *bp = netdev_priv(dev); 3661 int rc; 3662 u8 *buf; 3663 dma_addr_t dma_handle; 3664 struct hwrm_nvm_read_input *req; 3665 3666 if (!length) 3667 return -EINVAL; 3668 3669 rc = hwrm_req_init(bp, req, HWRM_NVM_READ); 3670 if (rc) 3671 return rc; 3672 3673 buf = hwrm_req_dma_slice(bp, req, length, &dma_handle); 3674 if (!buf) { 3675 hwrm_req_drop(bp, req); 3676 return -ENOMEM; 3677 } 3678 3679 req->host_dest_addr = cpu_to_le64(dma_handle); 3680 req->dir_idx = cpu_to_le16(index); 3681 req->offset = cpu_to_le32(offset); 3682 req->len = cpu_to_le32(length); 3683 3684 hwrm_req_hold(bp, req); /* hold the slice */ 3685 rc = hwrm_req_send(bp, req); 3686 if (rc == 0) 3687 memcpy(data, buf, length); 3688 hwrm_req_drop(bp, req); 3689 return rc; 3690 } 3691 3692 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 3693 u16 ext, u16 *index, u32 *item_length, 3694 u32 *data_length) 3695 { 3696 struct hwrm_nvm_find_dir_entry_output *output; 3697 struct hwrm_nvm_find_dir_entry_input *req; 3698 struct bnxt *bp = netdev_priv(dev); 3699 int rc; 3700 3701 rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY); 3702 if (rc) 3703 return rc; 3704 3705 req->enables = 0; 3706 req->dir_idx = 0; 3707 req->dir_type = cpu_to_le16(type); 3708 req->dir_ordinal = cpu_to_le16(ordinal); 3709 req->dir_ext = cpu_to_le16(ext); 3710 req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 3711 output = hwrm_req_hold(bp, req); 3712 rc = hwrm_req_send_silent(bp, req); 3713 if (rc == 0) { 3714 if (index) 3715 *index = le16_to_cpu(output->dir_idx); 3716 if (item_length) 3717 *item_length = le32_to_cpu(output->dir_item_length); 3718 if (data_length) 3719 *data_length = le32_to_cpu(output->dir_data_length); 3720 } 3721 hwrm_req_drop(bp, req); 3722 return rc; 3723 } 3724 3725 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 3726 { 3727 char *retval = NULL; 3728 char *p; 3729 char *value; 3730 int field = 0; 3731 3732 if (datalen < 1) 3733 return NULL; 3734 /* null-terminate the log data (removing last '\n'): */ 3735 data[datalen - 1] = 0; 3736 for (p = data; *p != 0; p++) { 3737 field = 0; 3738 retval = NULL; 3739 while (*p != 0 && *p != '\n') { 3740 value = p; 3741 while (*p != 0 && *p != '\t' && *p != '\n') 3742 p++; 3743 if (field == desired_field) 3744 retval = value; 3745 if (*p != '\t') 3746 break; 3747 *p = 0; 3748 field++; 3749 p++; 3750 } 3751 if (*p == 0) 3752 break; 3753 *p = 0; 3754 } 3755 return retval; 3756 } 3757 3758 int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size) 3759 { 3760 struct bnxt *bp = netdev_priv(dev); 3761 u16 index = 0; 3762 char *pkgver; 3763 u32 pkglen; 3764 u8 *pkgbuf; 3765 int rc; 3766 3767 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 3768 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 3769 &index, NULL, &pkglen); 3770 if (rc) 3771 return rc; 3772 3773 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 3774 if (!pkgbuf) { 3775 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 3776 pkglen); 3777 return -ENOMEM; 3778 } 3779 3780 rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf); 3781 if (rc) 3782 goto err; 3783 3784 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 3785 pkglen); 3786 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) 3787 strscpy(ver, pkgver, size); 3788 else 3789 rc = -ENOENT; 3790 3791 err: 3792 kfree(pkgbuf); 3793 3794 return rc; 3795 } 3796 3797 static void bnxt_get_pkgver(struct net_device *dev) 3798 { 3799 struct bnxt *bp = netdev_priv(dev); 3800 char buf[FW_VER_STR_LEN]; 3801 int len; 3802 3803 if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) { 3804 len = strlen(bp->fw_ver_str); 3805 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1, 3806 "/pkg %s", buf); 3807 } 3808 } 3809 3810 static int bnxt_get_eeprom(struct net_device *dev, 3811 struct ethtool_eeprom *eeprom, 3812 u8 *data) 3813 { 3814 u32 index; 3815 u32 offset; 3816 3817 if (eeprom->offset == 0) /* special offset value to get directory */ 3818 return bnxt_get_nvram_directory(dev, eeprom->len, data); 3819 3820 index = eeprom->offset >> 24; 3821 offset = eeprom->offset & 0xffffff; 3822 3823 if (index == 0) { 3824 netdev_err(dev, "unsupported index value: %d\n", index); 3825 return -EINVAL; 3826 } 3827 3828 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 3829 } 3830 3831 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 3832 { 3833 struct hwrm_nvm_erase_dir_entry_input *req; 3834 struct bnxt *bp = netdev_priv(dev); 3835 int rc; 3836 3837 rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY); 3838 if (rc) 3839 return rc; 3840 3841 req->dir_idx = cpu_to_le16(index); 3842 return hwrm_req_send(bp, req); 3843 } 3844 3845 static int bnxt_set_eeprom(struct net_device *dev, 3846 struct ethtool_eeprom *eeprom, 3847 u8 *data) 3848 { 3849 struct bnxt *bp = netdev_priv(dev); 3850 u8 index, dir_op; 3851 u16 type, ext, ordinal, attr; 3852 3853 if (!BNXT_PF(bp)) { 3854 netdev_err(dev, "NVM write not supported from a virtual function\n"); 3855 return -EINVAL; 3856 } 3857 3858 type = eeprom->magic >> 16; 3859 3860 if (type == 0xffff) { /* special value for directory operations */ 3861 index = eeprom->magic & 0xff; 3862 dir_op = eeprom->magic >> 8; 3863 if (index == 0) 3864 return -EINVAL; 3865 switch (dir_op) { 3866 case 0x0e: /* erase */ 3867 if (eeprom->offset != ~eeprom->magic) 3868 return -EINVAL; 3869 return bnxt_erase_nvram_directory(dev, index - 1); 3870 default: 3871 return -EINVAL; 3872 } 3873 } 3874 3875 /* Create or re-write an NVM item: */ 3876 if (bnxt_dir_type_is_executable(type)) 3877 return -EOPNOTSUPP; 3878 ext = eeprom->magic & 0xffff; 3879 ordinal = eeprom->offset >> 16; 3880 attr = eeprom->offset & 0xffff; 3881 3882 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data, 3883 eeprom->len); 3884 } 3885 3886 static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata) 3887 { 3888 struct bnxt *bp = netdev_priv(dev); 3889 struct ethtool_eee *eee = &bp->eee; 3890 struct bnxt_link_info *link_info = &bp->link_info; 3891 u32 advertising; 3892 int rc = 0; 3893 3894 if (!BNXT_PHY_CFG_ABLE(bp)) 3895 return -EOPNOTSUPP; 3896 3897 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 3898 return -EOPNOTSUPP; 3899 3900 mutex_lock(&bp->link_lock); 3901 advertising = _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 3902 if (!edata->eee_enabled) 3903 goto eee_ok; 3904 3905 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 3906 netdev_warn(dev, "EEE requires autoneg\n"); 3907 rc = -EINVAL; 3908 goto eee_exit; 3909 } 3910 if (edata->tx_lpi_enabled) { 3911 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 3912 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 3913 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 3914 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 3915 rc = -EINVAL; 3916 goto eee_exit; 3917 } else if (!bp->lpi_tmr_hi) { 3918 edata->tx_lpi_timer = eee->tx_lpi_timer; 3919 } 3920 } 3921 if (!edata->advertised) { 3922 edata->advertised = advertising & eee->supported; 3923 } else if (edata->advertised & ~advertising) { 3924 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n", 3925 edata->advertised, advertising); 3926 rc = -EINVAL; 3927 goto eee_exit; 3928 } 3929 3930 eee->advertised = edata->advertised; 3931 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 3932 eee->tx_lpi_timer = edata->tx_lpi_timer; 3933 eee_ok: 3934 eee->eee_enabled = edata->eee_enabled; 3935 3936 if (netif_running(dev)) 3937 rc = bnxt_hwrm_set_link_setting(bp, false, true); 3938 3939 eee_exit: 3940 mutex_unlock(&bp->link_lock); 3941 return rc; 3942 } 3943 3944 static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata) 3945 { 3946 struct bnxt *bp = netdev_priv(dev); 3947 3948 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 3949 return -EOPNOTSUPP; 3950 3951 *edata = bp->eee; 3952 if (!bp->eee.eee_enabled) { 3953 /* Preserve tx_lpi_timer so that the last value will be used 3954 * by default when it is re-enabled. 3955 */ 3956 edata->advertised = 0; 3957 edata->tx_lpi_enabled = 0; 3958 } 3959 3960 if (!bp->eee.eee_active) 3961 edata->lp_advertised = 0; 3962 3963 return 0; 3964 } 3965 3966 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 3967 u16 page_number, u8 bank, 3968 u16 start_addr, u16 data_length, 3969 u8 *buf) 3970 { 3971 struct hwrm_port_phy_i2c_read_output *output; 3972 struct hwrm_port_phy_i2c_read_input *req; 3973 int rc, byte_offset = 0; 3974 3975 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ); 3976 if (rc) 3977 return rc; 3978 3979 output = hwrm_req_hold(bp, req); 3980 req->i2c_slave_addr = i2c_addr; 3981 req->page_number = cpu_to_le16(page_number); 3982 req->port_id = cpu_to_le16(bp->pf.port_id); 3983 do { 3984 u16 xfer_size; 3985 3986 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 3987 data_length -= xfer_size; 3988 req->page_offset = cpu_to_le16(start_addr + byte_offset); 3989 req->data_length = xfer_size; 3990 req->enables = 3991 cpu_to_le32((start_addr + byte_offset ? 3992 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 3993 0) | 3994 (bank ? 3995 PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER : 3996 0)); 3997 rc = hwrm_req_send(bp, req); 3998 if (!rc) 3999 memcpy(buf + byte_offset, output->data, xfer_size); 4000 byte_offset += xfer_size; 4001 } while (!rc && data_length > 0); 4002 hwrm_req_drop(bp, req); 4003 4004 return rc; 4005 } 4006 4007 static int bnxt_get_module_info(struct net_device *dev, 4008 struct ethtool_modinfo *modinfo) 4009 { 4010 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 4011 struct bnxt *bp = netdev_priv(dev); 4012 int rc; 4013 4014 /* No point in going further if phy status indicates 4015 * module is not inserted or if it is powered down or 4016 * if it is of type 10GBase-T 4017 */ 4018 if (bp->link_info.module_status > 4019 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 4020 return -EOPNOTSUPP; 4021 4022 /* This feature is not supported in older firmware versions */ 4023 if (bp->hwrm_spec_code < 0x10202) 4024 return -EOPNOTSUPP; 4025 4026 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 0, 4027 SFF_DIAG_SUPPORT_OFFSET + 1, 4028 data); 4029 if (!rc) { 4030 u8 module_id = data[0]; 4031 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 4032 4033 switch (module_id) { 4034 case SFF_MODULE_ID_SFP: 4035 modinfo->type = ETH_MODULE_SFF_8472; 4036 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 4037 if (!diag_supported) 4038 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 4039 break; 4040 case SFF_MODULE_ID_QSFP: 4041 case SFF_MODULE_ID_QSFP_PLUS: 4042 modinfo->type = ETH_MODULE_SFF_8436; 4043 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 4044 break; 4045 case SFF_MODULE_ID_QSFP28: 4046 modinfo->type = ETH_MODULE_SFF_8636; 4047 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 4048 break; 4049 default: 4050 rc = -EOPNOTSUPP; 4051 break; 4052 } 4053 } 4054 return rc; 4055 } 4056 4057 static int bnxt_get_module_eeprom(struct net_device *dev, 4058 struct ethtool_eeprom *eeprom, 4059 u8 *data) 4060 { 4061 struct bnxt *bp = netdev_priv(dev); 4062 u16 start = eeprom->offset, length = eeprom->len; 4063 int rc = 0; 4064 4065 memset(data, 0, eeprom->len); 4066 4067 /* Read A0 portion of the EEPROM */ 4068 if (start < ETH_MODULE_SFF_8436_LEN) { 4069 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 4070 length = ETH_MODULE_SFF_8436_LEN - start; 4071 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 4072 start, length, data); 4073 if (rc) 4074 return rc; 4075 start += length; 4076 data += length; 4077 length = eeprom->len - length; 4078 } 4079 4080 /* Read A2 portion of the EEPROM */ 4081 if (length) { 4082 start -= ETH_MODULE_SFF_8436_LEN; 4083 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 0, 4084 start, length, data); 4085 } 4086 return rc; 4087 } 4088 4089 static int bnxt_get_module_status(struct bnxt *bp, struct netlink_ext_ack *extack) 4090 { 4091 if (bp->link_info.module_status <= 4092 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 4093 return 0; 4094 4095 switch (bp->link_info.module_status) { 4096 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 4097 NL_SET_ERR_MSG_MOD(extack, "Transceiver module is powering down"); 4098 break; 4099 case PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED: 4100 NL_SET_ERR_MSG_MOD(extack, "Transceiver module not inserted"); 4101 break; 4102 case PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT: 4103 NL_SET_ERR_MSG_MOD(extack, "Transceiver module disabled due to current fault"); 4104 break; 4105 default: 4106 NL_SET_ERR_MSG_MOD(extack, "Unknown error"); 4107 break; 4108 } 4109 return -EINVAL; 4110 } 4111 4112 static int bnxt_get_module_eeprom_by_page(struct net_device *dev, 4113 const struct ethtool_module_eeprom *page_data, 4114 struct netlink_ext_ack *extack) 4115 { 4116 struct bnxt *bp = netdev_priv(dev); 4117 int rc; 4118 4119 rc = bnxt_get_module_status(bp, extack); 4120 if (rc) 4121 return rc; 4122 4123 if (bp->hwrm_spec_code < 0x10202) { 4124 NL_SET_ERR_MSG_MOD(extack, "Firmware version too old"); 4125 return -EINVAL; 4126 } 4127 4128 if (page_data->bank && !(bp->phy_flags & BNXT_PHY_FL_BANK_SEL)) { 4129 NL_SET_ERR_MSG_MOD(extack, "Firmware not capable for bank selection"); 4130 return -EINVAL; 4131 } 4132 4133 rc = bnxt_read_sfp_module_eeprom_info(bp, page_data->i2c_address << 1, 4134 page_data->page, page_data->bank, 4135 page_data->offset, 4136 page_data->length, 4137 page_data->data); 4138 if (rc) { 4139 NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom read failed"); 4140 return rc; 4141 } 4142 return page_data->length; 4143 } 4144 4145 static int bnxt_nway_reset(struct net_device *dev) 4146 { 4147 int rc = 0; 4148 4149 struct bnxt *bp = netdev_priv(dev); 4150 struct bnxt_link_info *link_info = &bp->link_info; 4151 4152 if (!BNXT_PHY_CFG_ABLE(bp)) 4153 return -EOPNOTSUPP; 4154 4155 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 4156 return -EINVAL; 4157 4158 if (netif_running(dev)) 4159 rc = bnxt_hwrm_set_link_setting(bp, true, false); 4160 4161 return rc; 4162 } 4163 4164 static int bnxt_set_phys_id(struct net_device *dev, 4165 enum ethtool_phys_id_state state) 4166 { 4167 struct hwrm_port_led_cfg_input *req; 4168 struct bnxt *bp = netdev_priv(dev); 4169 struct bnxt_pf_info *pf = &bp->pf; 4170 struct bnxt_led_cfg *led_cfg; 4171 u8 led_state; 4172 __le16 duration; 4173 int rc, i; 4174 4175 if (!bp->num_leds || BNXT_VF(bp)) 4176 return -EOPNOTSUPP; 4177 4178 if (state == ETHTOOL_ID_ACTIVE) { 4179 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 4180 duration = cpu_to_le16(500); 4181 } else if (state == ETHTOOL_ID_INACTIVE) { 4182 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 4183 duration = cpu_to_le16(0); 4184 } else { 4185 return -EINVAL; 4186 } 4187 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG); 4188 if (rc) 4189 return rc; 4190 4191 req->port_id = cpu_to_le16(pf->port_id); 4192 req->num_leds = bp->num_leds; 4193 led_cfg = (struct bnxt_led_cfg *)&req->led0_id; 4194 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 4195 req->enables |= BNXT_LED_DFLT_ENABLES(i); 4196 led_cfg->led_id = bp->leds[i].led_id; 4197 led_cfg->led_state = led_state; 4198 led_cfg->led_blink_on = duration; 4199 led_cfg->led_blink_off = duration; 4200 led_cfg->led_group_id = bp->leds[i].led_group_id; 4201 } 4202 return hwrm_req_send(bp, req); 4203 } 4204 4205 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 4206 { 4207 struct hwrm_selftest_irq_input *req; 4208 int rc; 4209 4210 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ); 4211 if (rc) 4212 return rc; 4213 4214 req->cmpl_ring = cpu_to_le16(cmpl_ring); 4215 return hwrm_req_send(bp, req); 4216 } 4217 4218 static int bnxt_test_irq(struct bnxt *bp) 4219 { 4220 int i; 4221 4222 for (i = 0; i < bp->cp_nr_rings; i++) { 4223 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 4224 int rc; 4225 4226 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 4227 if (rc) 4228 return rc; 4229 } 4230 return 0; 4231 } 4232 4233 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 4234 { 4235 struct hwrm_port_mac_cfg_input *req; 4236 int rc; 4237 4238 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 4239 if (rc) 4240 return rc; 4241 4242 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 4243 if (enable) 4244 req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 4245 else 4246 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 4247 return hwrm_req_send(bp, req); 4248 } 4249 4250 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 4251 { 4252 struct hwrm_port_phy_qcaps_output *resp; 4253 struct hwrm_port_phy_qcaps_input *req; 4254 int rc; 4255 4256 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS); 4257 if (rc) 4258 return rc; 4259 4260 resp = hwrm_req_hold(bp, req); 4261 rc = hwrm_req_send(bp, req); 4262 if (!rc) 4263 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 4264 4265 hwrm_req_drop(bp, req); 4266 return rc; 4267 } 4268 4269 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 4270 struct hwrm_port_phy_cfg_input *req) 4271 { 4272 struct bnxt_link_info *link_info = &bp->link_info; 4273 u16 fw_advertising; 4274 u16 fw_speed; 4275 int rc; 4276 4277 if (!link_info->autoneg || 4278 (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK)) 4279 return 0; 4280 4281 rc = bnxt_query_force_speeds(bp, &fw_advertising); 4282 if (rc) 4283 return rc; 4284 4285 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 4286 if (BNXT_LINK_IS_UP(bp)) 4287 fw_speed = bp->link_info.link_speed; 4288 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 4289 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 4290 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 4291 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 4292 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 4293 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 4294 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 4295 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 4296 4297 req->force_link_speed = cpu_to_le16(fw_speed); 4298 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 4299 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 4300 rc = hwrm_req_send(bp, req); 4301 req->flags = 0; 4302 req->force_link_speed = cpu_to_le16(0); 4303 return rc; 4304 } 4305 4306 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 4307 { 4308 struct hwrm_port_phy_cfg_input *req; 4309 int rc; 4310 4311 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 4312 if (rc) 4313 return rc; 4314 4315 /* prevent bnxt_disable_an_for_lpbk() from consuming the request */ 4316 hwrm_req_hold(bp, req); 4317 4318 if (enable) { 4319 bnxt_disable_an_for_lpbk(bp, req); 4320 if (ext) 4321 req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 4322 else 4323 req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 4324 } else { 4325 req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 4326 } 4327 req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 4328 rc = hwrm_req_send(bp, req); 4329 hwrm_req_drop(bp, req); 4330 return rc; 4331 } 4332 4333 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 4334 u32 raw_cons, int pkt_size) 4335 { 4336 struct bnxt_napi *bnapi = cpr->bnapi; 4337 struct bnxt_rx_ring_info *rxr; 4338 struct bnxt_sw_rx_bd *rx_buf; 4339 struct rx_cmp *rxcmp; 4340 u16 cp_cons, cons; 4341 u8 *data; 4342 u32 len; 4343 int i; 4344 4345 rxr = bnapi->rx_ring; 4346 cp_cons = RING_CMP(raw_cons); 4347 rxcmp = (struct rx_cmp *) 4348 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 4349 cons = rxcmp->rx_cmp_opaque; 4350 rx_buf = &rxr->rx_buf_ring[cons]; 4351 data = rx_buf->data_ptr; 4352 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 4353 if (len != pkt_size) 4354 return -EIO; 4355 i = ETH_ALEN; 4356 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 4357 return -EIO; 4358 i += ETH_ALEN; 4359 for ( ; i < pkt_size; i++) { 4360 if (data[i] != (u8)(i & 0xff)) 4361 return -EIO; 4362 } 4363 return 0; 4364 } 4365 4366 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 4367 int pkt_size) 4368 { 4369 struct tx_cmp *txcmp; 4370 int rc = -EIO; 4371 u32 raw_cons; 4372 u32 cons; 4373 int i; 4374 4375 raw_cons = cpr->cp_raw_cons; 4376 for (i = 0; i < 200; i++) { 4377 cons = RING_CMP(raw_cons); 4378 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 4379 4380 if (!TX_CMP_VALID(txcmp, raw_cons)) { 4381 udelay(5); 4382 continue; 4383 } 4384 4385 /* The valid test of the entry must be done first before 4386 * reading any further. 4387 */ 4388 dma_rmb(); 4389 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP || 4390 TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_V3_CMP) { 4391 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 4392 raw_cons = NEXT_RAW_CMP(raw_cons); 4393 raw_cons = NEXT_RAW_CMP(raw_cons); 4394 break; 4395 } 4396 raw_cons = NEXT_RAW_CMP(raw_cons); 4397 } 4398 cpr->cp_raw_cons = raw_cons; 4399 return rc; 4400 } 4401 4402 static int bnxt_run_loopback(struct bnxt *bp) 4403 { 4404 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 4405 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 4406 struct bnxt_cp_ring_info *cpr; 4407 int pkt_size, i = 0; 4408 struct sk_buff *skb; 4409 dma_addr_t map; 4410 u8 *data; 4411 int rc; 4412 4413 cpr = &rxr->bnapi->cp_ring; 4414 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) 4415 cpr = rxr->rx_cpr; 4416 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh); 4417 skb = netdev_alloc_skb(bp->dev, pkt_size); 4418 if (!skb) 4419 return -ENOMEM; 4420 data = skb_put(skb, pkt_size); 4421 ether_addr_copy(&data[i], bp->dev->dev_addr); 4422 i += ETH_ALEN; 4423 ether_addr_copy(&data[i], bp->dev->dev_addr); 4424 i += ETH_ALEN; 4425 for ( ; i < pkt_size; i++) 4426 data[i] = (u8)(i & 0xff); 4427 4428 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 4429 DMA_TO_DEVICE); 4430 if (dma_mapping_error(&bp->pdev->dev, map)) { 4431 dev_kfree_skb(skb); 4432 return -EIO; 4433 } 4434 bnxt_xmit_bd(bp, txr, map, pkt_size, NULL); 4435 4436 /* Sync BD data before updating doorbell */ 4437 wmb(); 4438 4439 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 4440 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 4441 4442 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE); 4443 dev_kfree_skb(skb); 4444 return rc; 4445 } 4446 4447 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 4448 { 4449 struct hwrm_selftest_exec_output *resp; 4450 struct hwrm_selftest_exec_input *req; 4451 int rc; 4452 4453 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC); 4454 if (rc) 4455 return rc; 4456 4457 hwrm_req_timeout(bp, req, bp->test_info->timeout); 4458 req->flags = test_mask; 4459 4460 resp = hwrm_req_hold(bp, req); 4461 rc = hwrm_req_send(bp, req); 4462 *test_results = resp->test_success; 4463 hwrm_req_drop(bp, req); 4464 return rc; 4465 } 4466 4467 #define BNXT_DRV_TESTS 4 4468 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 4469 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 4470 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 4471 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 4472 4473 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 4474 u64 *buf) 4475 { 4476 struct bnxt *bp = netdev_priv(dev); 4477 bool do_ext_lpbk = false; 4478 bool offline = false; 4479 u8 test_results = 0; 4480 u8 test_mask = 0; 4481 int rc = 0, i; 4482 4483 if (!bp->num_tests || !BNXT_PF(bp)) 4484 return; 4485 memset(buf, 0, sizeof(u64) * bp->num_tests); 4486 if (!netif_running(dev)) { 4487 etest->flags |= ETH_TEST_FL_FAILED; 4488 return; 4489 } 4490 4491 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 4492 (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK)) 4493 do_ext_lpbk = true; 4494 4495 if (etest->flags & ETH_TEST_FL_OFFLINE) { 4496 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) { 4497 etest->flags |= ETH_TEST_FL_FAILED; 4498 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n"); 4499 return; 4500 } 4501 offline = true; 4502 } 4503 4504 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 4505 u8 bit_val = 1 << i; 4506 4507 if (!(bp->test_info->offline_mask & bit_val)) 4508 test_mask |= bit_val; 4509 else if (offline) 4510 test_mask |= bit_val; 4511 } 4512 if (!offline) { 4513 bnxt_run_fw_tests(bp, test_mask, &test_results); 4514 } else { 4515 bnxt_ulp_stop(bp); 4516 bnxt_close_nic(bp, true, false); 4517 bnxt_run_fw_tests(bp, test_mask, &test_results); 4518 4519 buf[BNXT_MACLPBK_TEST_IDX] = 1; 4520 bnxt_hwrm_mac_loopback(bp, true); 4521 msleep(250); 4522 rc = bnxt_half_open_nic(bp); 4523 if (rc) { 4524 bnxt_hwrm_mac_loopback(bp, false); 4525 etest->flags |= ETH_TEST_FL_FAILED; 4526 bnxt_ulp_start(bp, rc); 4527 return; 4528 } 4529 if (bnxt_run_loopback(bp)) 4530 etest->flags |= ETH_TEST_FL_FAILED; 4531 else 4532 buf[BNXT_MACLPBK_TEST_IDX] = 0; 4533 4534 bnxt_hwrm_mac_loopback(bp, false); 4535 bnxt_hwrm_phy_loopback(bp, true, false); 4536 msleep(1000); 4537 if (bnxt_run_loopback(bp)) { 4538 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 4539 etest->flags |= ETH_TEST_FL_FAILED; 4540 } 4541 if (do_ext_lpbk) { 4542 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 4543 bnxt_hwrm_phy_loopback(bp, true, true); 4544 msleep(1000); 4545 if (bnxt_run_loopback(bp)) { 4546 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 4547 etest->flags |= ETH_TEST_FL_FAILED; 4548 } 4549 } 4550 bnxt_hwrm_phy_loopback(bp, false, false); 4551 bnxt_half_close_nic(bp); 4552 rc = bnxt_open_nic(bp, true, true); 4553 bnxt_ulp_start(bp, rc); 4554 } 4555 if (rc || bnxt_test_irq(bp)) { 4556 buf[BNXT_IRQ_TEST_IDX] = 1; 4557 etest->flags |= ETH_TEST_FL_FAILED; 4558 } 4559 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 4560 u8 bit_val = 1 << i; 4561 4562 if ((test_mask & bit_val) && !(test_results & bit_val)) { 4563 buf[i] = 1; 4564 etest->flags |= ETH_TEST_FL_FAILED; 4565 } 4566 } 4567 } 4568 4569 static int bnxt_reset(struct net_device *dev, u32 *flags) 4570 { 4571 struct bnxt *bp = netdev_priv(dev); 4572 bool reload = false; 4573 u32 req = *flags; 4574 4575 if (!req) 4576 return -EINVAL; 4577 4578 if (!BNXT_PF(bp)) { 4579 netdev_err(dev, "Reset is not supported from a VF\n"); 4580 return -EOPNOTSUPP; 4581 } 4582 4583 if (pci_vfs_assigned(bp->pdev) && 4584 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) { 4585 netdev_err(dev, 4586 "Reset not allowed when VFs are assigned to VMs\n"); 4587 return -EBUSY; 4588 } 4589 4590 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) { 4591 /* This feature is not supported in older firmware versions */ 4592 if (bp->hwrm_spec_code >= 0x10803) { 4593 if (!bnxt_firmware_reset_chip(dev)) { 4594 netdev_info(dev, "Firmware reset request successful.\n"); 4595 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) 4596 reload = true; 4597 *flags &= ~BNXT_FW_RESET_CHIP; 4598 } 4599 } else if (req == BNXT_FW_RESET_CHIP) { 4600 return -EOPNOTSUPP; /* only request, fail hard */ 4601 } 4602 } 4603 4604 if (!BNXT_CHIP_P4_PLUS(bp) && (req & BNXT_FW_RESET_AP)) { 4605 /* This feature is not supported in older firmware versions */ 4606 if (bp->hwrm_spec_code >= 0x10803) { 4607 if (!bnxt_firmware_reset_ap(dev)) { 4608 netdev_info(dev, "Reset application processor successful.\n"); 4609 reload = true; 4610 *flags &= ~BNXT_FW_RESET_AP; 4611 } 4612 } else if (req == BNXT_FW_RESET_AP) { 4613 return -EOPNOTSUPP; /* only request, fail hard */ 4614 } 4615 } 4616 4617 if (reload) 4618 netdev_info(dev, "Reload driver to complete reset\n"); 4619 4620 return 0; 4621 } 4622 4623 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump) 4624 { 4625 struct bnxt *bp = netdev_priv(dev); 4626 4627 if (dump->flag > BNXT_DUMP_CRASH) { 4628 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n"); 4629 return -EINVAL; 4630 } 4631 4632 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) { 4633 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n"); 4634 return -EOPNOTSUPP; 4635 } 4636 4637 bp->dump_flag = dump->flag; 4638 return 0; 4639 } 4640 4641 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 4642 { 4643 struct bnxt *bp = netdev_priv(dev); 4644 4645 if (bp->hwrm_spec_code < 0x10801) 4646 return -EOPNOTSUPP; 4647 4648 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 4649 bp->ver_resp.hwrm_fw_min_8b << 16 | 4650 bp->ver_resp.hwrm_fw_bld_8b << 8 | 4651 bp->ver_resp.hwrm_fw_rsvd_8b; 4652 4653 dump->flag = bp->dump_flag; 4654 dump->len = bnxt_get_coredump_length(bp, bp->dump_flag); 4655 return 0; 4656 } 4657 4658 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 4659 void *buf) 4660 { 4661 struct bnxt *bp = netdev_priv(dev); 4662 4663 if (bp->hwrm_spec_code < 0x10801) 4664 return -EOPNOTSUPP; 4665 4666 memset(buf, 0, dump->len); 4667 4668 dump->flag = bp->dump_flag; 4669 return bnxt_get_coredump(bp, dump->flag, buf, &dump->len); 4670 } 4671 4672 static int bnxt_get_ts_info(struct net_device *dev, 4673 struct ethtool_ts_info *info) 4674 { 4675 struct bnxt *bp = netdev_priv(dev); 4676 struct bnxt_ptp_cfg *ptp; 4677 4678 ptp = bp->ptp_cfg; 4679 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 4680 SOF_TIMESTAMPING_RX_SOFTWARE | 4681 SOF_TIMESTAMPING_SOFTWARE; 4682 4683 info->phc_index = -1; 4684 if (!ptp) 4685 return 0; 4686 4687 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | 4688 SOF_TIMESTAMPING_RX_HARDWARE | 4689 SOF_TIMESTAMPING_RAW_HARDWARE; 4690 if (ptp->ptp_clock) 4691 info->phc_index = ptp_clock_index(ptp->ptp_clock); 4692 4693 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 4694 4695 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 4696 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 4697 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 4698 4699 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) 4700 info->rx_filters |= (1 << HWTSTAMP_FILTER_ALL); 4701 return 0; 4702 } 4703 4704 void bnxt_ethtool_init(struct bnxt *bp) 4705 { 4706 struct hwrm_selftest_qlist_output *resp; 4707 struct hwrm_selftest_qlist_input *req; 4708 struct bnxt_test_info *test_info; 4709 struct net_device *dev = bp->dev; 4710 int i, rc; 4711 4712 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 4713 bnxt_get_pkgver(dev); 4714 4715 bp->num_tests = 0; 4716 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp)) 4717 return; 4718 4719 test_info = bp->test_info; 4720 if (!test_info) { 4721 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL); 4722 if (!test_info) 4723 return; 4724 bp->test_info = test_info; 4725 } 4726 4727 if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST)) 4728 return; 4729 4730 resp = hwrm_req_hold(bp, req); 4731 rc = hwrm_req_send_silent(bp, req); 4732 if (rc) 4733 goto ethtool_init_exit; 4734 4735 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 4736 if (bp->num_tests > BNXT_MAX_TEST) 4737 bp->num_tests = BNXT_MAX_TEST; 4738 4739 test_info->offline_mask = resp->offline_tests; 4740 test_info->timeout = le16_to_cpu(resp->test_timeout); 4741 if (!test_info->timeout) 4742 test_info->timeout = HWRM_CMD_TIMEOUT; 4743 for (i = 0; i < bp->num_tests; i++) { 4744 char *str = test_info->string[i]; 4745 char *fw_str = resp->test_name[i]; 4746 4747 if (i == BNXT_MACLPBK_TEST_IDX) { 4748 strcpy(str, "Mac loopback test (offline)"); 4749 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 4750 strcpy(str, "Phy loopback test (offline)"); 4751 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 4752 strcpy(str, "Ext loopback test (offline)"); 4753 } else if (i == BNXT_IRQ_TEST_IDX) { 4754 strcpy(str, "Interrupt_test (offline)"); 4755 } else { 4756 snprintf(str, ETH_GSTRING_LEN, "%s test (%s)", 4757 fw_str, test_info->offline_mask & (1 << i) ? 4758 "offline" : "online"); 4759 } 4760 } 4761 4762 ethtool_init_exit: 4763 hwrm_req_drop(bp, req); 4764 } 4765 4766 static void bnxt_get_eth_phy_stats(struct net_device *dev, 4767 struct ethtool_eth_phy_stats *phy_stats) 4768 { 4769 struct bnxt *bp = netdev_priv(dev); 4770 u64 *rx; 4771 4772 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 4773 return; 4774 4775 rx = bp->rx_port_stats_ext.sw_stats; 4776 phy_stats->SymbolErrorDuringCarrier = 4777 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err)); 4778 } 4779 4780 static void bnxt_get_eth_mac_stats(struct net_device *dev, 4781 struct ethtool_eth_mac_stats *mac_stats) 4782 { 4783 struct bnxt *bp = netdev_priv(dev); 4784 u64 *rx, *tx; 4785 4786 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 4787 return; 4788 4789 rx = bp->port_stats.sw_stats; 4790 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 4791 4792 mac_stats->FramesReceivedOK = 4793 BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames); 4794 mac_stats->FramesTransmittedOK = 4795 BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames); 4796 mac_stats->FrameCheckSequenceErrors = 4797 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames); 4798 mac_stats->AlignmentErrors = 4799 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames); 4800 mac_stats->OutOfRangeLengthField = 4801 BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames); 4802 } 4803 4804 static void bnxt_get_eth_ctrl_stats(struct net_device *dev, 4805 struct ethtool_eth_ctrl_stats *ctrl_stats) 4806 { 4807 struct bnxt *bp = netdev_priv(dev); 4808 u64 *rx; 4809 4810 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 4811 return; 4812 4813 rx = bp->port_stats.sw_stats; 4814 ctrl_stats->MACControlFramesReceived = 4815 BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames); 4816 } 4817 4818 static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = { 4819 { 0, 64 }, 4820 { 65, 127 }, 4821 { 128, 255 }, 4822 { 256, 511 }, 4823 { 512, 1023 }, 4824 { 1024, 1518 }, 4825 { 1519, 2047 }, 4826 { 2048, 4095 }, 4827 { 4096, 9216 }, 4828 { 9217, 16383 }, 4829 {} 4830 }; 4831 4832 static void bnxt_get_rmon_stats(struct net_device *dev, 4833 struct ethtool_rmon_stats *rmon_stats, 4834 const struct ethtool_rmon_hist_range **ranges) 4835 { 4836 struct bnxt *bp = netdev_priv(dev); 4837 u64 *rx, *tx; 4838 4839 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 4840 return; 4841 4842 rx = bp->port_stats.sw_stats; 4843 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 4844 4845 rmon_stats->jabbers = 4846 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames); 4847 rmon_stats->oversize_pkts = 4848 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames); 4849 rmon_stats->undersize_pkts = 4850 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames); 4851 4852 rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames); 4853 rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames); 4854 rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames); 4855 rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames); 4856 rmon_stats->hist[4] = 4857 BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames); 4858 rmon_stats->hist[5] = 4859 BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames); 4860 rmon_stats->hist[6] = 4861 BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames); 4862 rmon_stats->hist[7] = 4863 BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames); 4864 rmon_stats->hist[8] = 4865 BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames); 4866 rmon_stats->hist[9] = 4867 BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames); 4868 4869 rmon_stats->hist_tx[0] = 4870 BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames); 4871 rmon_stats->hist_tx[1] = 4872 BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames); 4873 rmon_stats->hist_tx[2] = 4874 BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames); 4875 rmon_stats->hist_tx[3] = 4876 BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames); 4877 rmon_stats->hist_tx[4] = 4878 BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames); 4879 rmon_stats->hist_tx[5] = 4880 BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames); 4881 rmon_stats->hist_tx[6] = 4882 BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames); 4883 rmon_stats->hist_tx[7] = 4884 BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames); 4885 rmon_stats->hist_tx[8] = 4886 BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames); 4887 rmon_stats->hist_tx[9] = 4888 BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames); 4889 4890 *ranges = bnxt_rmon_ranges; 4891 } 4892 4893 static void bnxt_get_link_ext_stats(struct net_device *dev, 4894 struct ethtool_link_ext_stats *stats) 4895 { 4896 struct bnxt *bp = netdev_priv(dev); 4897 u64 *rx; 4898 4899 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 4900 return; 4901 4902 rx = bp->rx_port_stats_ext.sw_stats; 4903 stats->link_down_events = 4904 *(rx + BNXT_RX_STATS_EXT_OFFSET(link_down_events)); 4905 } 4906 4907 void bnxt_ethtool_free(struct bnxt *bp) 4908 { 4909 kfree(bp->test_info); 4910 bp->test_info = NULL; 4911 } 4912 4913 const struct ethtool_ops bnxt_ethtool_ops = { 4914 .cap_link_lanes_supported = 1, 4915 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 4916 ETHTOOL_COALESCE_MAX_FRAMES | 4917 ETHTOOL_COALESCE_USECS_IRQ | 4918 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 4919 ETHTOOL_COALESCE_STATS_BLOCK_USECS | 4920 ETHTOOL_COALESCE_USE_ADAPTIVE_RX | 4921 ETHTOOL_COALESCE_USE_CQE, 4922 .get_link_ksettings = bnxt_get_link_ksettings, 4923 .set_link_ksettings = bnxt_set_link_ksettings, 4924 .get_fec_stats = bnxt_get_fec_stats, 4925 .get_fecparam = bnxt_get_fecparam, 4926 .set_fecparam = bnxt_set_fecparam, 4927 .get_pause_stats = bnxt_get_pause_stats, 4928 .get_pauseparam = bnxt_get_pauseparam, 4929 .set_pauseparam = bnxt_set_pauseparam, 4930 .get_drvinfo = bnxt_get_drvinfo, 4931 .get_regs_len = bnxt_get_regs_len, 4932 .get_regs = bnxt_get_regs, 4933 .get_wol = bnxt_get_wol, 4934 .set_wol = bnxt_set_wol, 4935 .get_coalesce = bnxt_get_coalesce, 4936 .set_coalesce = bnxt_set_coalesce, 4937 .get_msglevel = bnxt_get_msglevel, 4938 .set_msglevel = bnxt_set_msglevel, 4939 .get_sset_count = bnxt_get_sset_count, 4940 .get_strings = bnxt_get_strings, 4941 .get_ethtool_stats = bnxt_get_ethtool_stats, 4942 .set_ringparam = bnxt_set_ringparam, 4943 .get_ringparam = bnxt_get_ringparam, 4944 .get_channels = bnxt_get_channels, 4945 .set_channels = bnxt_set_channels, 4946 .get_rxnfc = bnxt_get_rxnfc, 4947 .set_rxnfc = bnxt_set_rxnfc, 4948 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 4949 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 4950 .get_rxfh = bnxt_get_rxfh, 4951 .set_rxfh = bnxt_set_rxfh, 4952 .flash_device = bnxt_flash_device, 4953 .get_eeprom_len = bnxt_get_eeprom_len, 4954 .get_eeprom = bnxt_get_eeprom, 4955 .set_eeprom = bnxt_set_eeprom, 4956 .get_link = bnxt_get_link, 4957 .get_link_ext_stats = bnxt_get_link_ext_stats, 4958 .get_eee = bnxt_get_eee, 4959 .set_eee = bnxt_set_eee, 4960 .get_module_info = bnxt_get_module_info, 4961 .get_module_eeprom = bnxt_get_module_eeprom, 4962 .get_module_eeprom_by_page = bnxt_get_module_eeprom_by_page, 4963 .nway_reset = bnxt_nway_reset, 4964 .set_phys_id = bnxt_set_phys_id, 4965 .self_test = bnxt_self_test, 4966 .get_ts_info = bnxt_get_ts_info, 4967 .reset = bnxt_reset, 4968 .set_dump = bnxt_set_dump, 4969 .get_dump_flag = bnxt_get_dump_flag, 4970 .get_dump_data = bnxt_get_dump_data, 4971 .get_eth_phy_stats = bnxt_get_eth_phy_stats, 4972 .get_eth_mac_stats = bnxt_get_eth_mac_stats, 4973 .get_eth_ctrl_stats = bnxt_get_eth_ctrl_stats, 4974 .get_rmon_stats = bnxt_get_rmon_stats, 4975 }; 4976