1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/bitops.h> 12 #include <linux/ctype.h> 13 #include <linux/stringify.h> 14 #include <linux/ethtool.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/linkmode.h> 17 #include <linux/interrupt.h> 18 #include <linux/pci.h> 19 #include <linux/etherdevice.h> 20 #include <linux/crc32.h> 21 #include <linux/firmware.h> 22 #include <linux/utsname.h> 23 #include <linux/time.h> 24 #include <linux/ptp_clock_kernel.h> 25 #include <linux/net_tstamp.h> 26 #include <linux/timecounter.h> 27 #include <net/netdev_queues.h> 28 #include <net/netlink.h> 29 #include <linux/bnxt/hsi.h> 30 #include "bnxt.h" 31 #include "bnxt_hwrm.h" 32 #include "bnxt_ulp.h" 33 #include "bnxt_xdp.h" 34 #include "bnxt_ptp.h" 35 #include "bnxt_ethtool.h" 36 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 37 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 38 #include "bnxt_coredump.h" 39 40 #define BNXT_NVM_ERR_MSG(dev, extack, msg) \ 41 do { \ 42 if (extack) \ 43 NL_SET_ERR_MSG_MOD(extack, msg); \ 44 netdev_err(dev, "%s\n", msg); \ 45 } while (0) 46 47 static u32 bnxt_get_msglevel(struct net_device *dev) 48 { 49 struct bnxt *bp = netdev_priv(dev); 50 51 return bp->msg_enable; 52 } 53 54 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 55 { 56 struct bnxt *bp = netdev_priv(dev); 57 58 bp->msg_enable = value; 59 } 60 61 static int bnxt_get_coalesce(struct net_device *dev, 62 struct ethtool_coalesce *coal, 63 struct kernel_ethtool_coalesce *kernel_coal, 64 struct netlink_ext_ack *extack) 65 { 66 struct bnxt *bp = netdev_priv(dev); 67 struct bnxt_coal *hw_coal; 68 u16 mult; 69 70 memset(coal, 0, sizeof(*coal)); 71 72 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 73 74 hw_coal = &bp->rx_coal; 75 mult = hw_coal->bufs_per_record; 76 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 77 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 78 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 79 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 80 if (hw_coal->flags & 81 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 82 kernel_coal->use_cqe_mode_rx = true; 83 84 hw_coal = &bp->tx_coal; 85 mult = hw_coal->bufs_per_record; 86 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 87 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 88 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 89 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 90 if (hw_coal->flags & 91 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 92 kernel_coal->use_cqe_mode_tx = true; 93 94 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 95 96 return 0; 97 } 98 99 static int bnxt_set_coalesce(struct net_device *dev, 100 struct ethtool_coalesce *coal, 101 struct kernel_ethtool_coalesce *kernel_coal, 102 struct netlink_ext_ack *extack) 103 { 104 struct bnxt *bp = netdev_priv(dev); 105 bool update_stats = false; 106 struct bnxt_coal *hw_coal; 107 int rc = 0; 108 u16 mult; 109 110 if (coal->use_adaptive_rx_coalesce) { 111 bp->flags |= BNXT_FLAG_DIM; 112 } else { 113 if (bp->flags & BNXT_FLAG_DIM) { 114 bp->flags &= ~(BNXT_FLAG_DIM); 115 goto reset_coalesce; 116 } 117 } 118 119 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) && 120 !(bp->coal_cap.cmpl_params & 121 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)) 122 return -EOPNOTSUPP; 123 124 hw_coal = &bp->rx_coal; 125 mult = hw_coal->bufs_per_record; 126 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 127 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 128 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 129 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 130 hw_coal->flags &= 131 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 132 if (kernel_coal->use_cqe_mode_rx) 133 hw_coal->flags |= 134 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 135 136 hw_coal = &bp->tx_coal; 137 mult = hw_coal->bufs_per_record; 138 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 139 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 140 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 141 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 142 hw_coal->flags &= 143 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 144 if (kernel_coal->use_cqe_mode_tx) 145 hw_coal->flags |= 146 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 147 148 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 149 u32 stats_ticks = coal->stats_block_coalesce_usecs; 150 151 /* Allow 0, which means disable. */ 152 if (stats_ticks) 153 stats_ticks = clamp_t(u32, stats_ticks, 154 BNXT_MIN_STATS_COAL_TICKS, 155 BNXT_MAX_STATS_COAL_TICKS); 156 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 157 bp->stats_coal_ticks = stats_ticks; 158 if (bp->stats_coal_ticks) 159 bp->current_interval = 160 bp->stats_coal_ticks * HZ / 1000000; 161 else 162 bp->current_interval = BNXT_TIMER_INTERVAL; 163 update_stats = true; 164 } 165 166 reset_coalesce: 167 if (test_bit(BNXT_STATE_OPEN, &bp->state)) { 168 if (update_stats) { 169 bnxt_close_nic(bp, true, false); 170 rc = bnxt_open_nic(bp, true, false); 171 } else { 172 rc = bnxt_hwrm_set_coal(bp); 173 } 174 } 175 176 return rc; 177 } 178 179 static const char * const bnxt_ring_rx_stats_str[] = { 180 "rx_ucast_packets", 181 "rx_mcast_packets", 182 "rx_bcast_packets", 183 "rx_discards", 184 "rx_errors", 185 "rx_ucast_bytes", 186 "rx_mcast_bytes", 187 "rx_bcast_bytes", 188 }; 189 190 static const char * const bnxt_ring_tx_stats_str[] = { 191 "tx_ucast_packets", 192 "tx_mcast_packets", 193 "tx_bcast_packets", 194 "tx_errors", 195 "tx_discards", 196 "tx_ucast_bytes", 197 "tx_mcast_bytes", 198 "tx_bcast_bytes", 199 }; 200 201 static const char * const bnxt_ring_tpa_stats_str[] = { 202 "tpa_packets", 203 "tpa_bytes", 204 "tpa_events", 205 "tpa_aborts", 206 }; 207 208 static const char * const bnxt_ring_tpa2_stats_str[] = { 209 "rx_tpa_eligible_pkt", 210 "rx_tpa_eligible_bytes", 211 "rx_tpa_pkt", 212 "rx_tpa_bytes", 213 "rx_tpa_errors", 214 "rx_tpa_events", 215 }; 216 217 static const char * const bnxt_rx_sw_stats_str[] = { 218 "rx_l4_csum_errors", 219 "rx_resets", 220 "rx_buf_errors", 221 }; 222 223 static const char * const bnxt_cmn_sw_stats_str[] = { 224 "missed_irqs", 225 }; 226 227 #define BNXT_RX_STATS_ENTRY(counter) \ 228 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 229 230 #define BNXT_TX_STATS_ENTRY(counter) \ 231 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 232 233 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 234 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 235 236 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 237 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 238 239 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 240 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 241 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 242 243 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 244 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 245 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 246 247 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 248 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 249 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 250 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 251 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 252 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 253 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 254 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 255 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 256 257 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 258 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 259 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 260 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 261 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 262 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 263 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 264 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 265 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 266 267 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 268 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 269 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 270 271 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 272 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 273 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 274 275 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 276 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 277 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 278 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 279 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 280 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 281 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 282 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 283 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 284 285 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 286 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 287 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 288 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 289 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 290 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 291 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 292 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 293 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 294 295 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 296 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 297 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 298 299 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 300 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 301 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 302 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 303 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 304 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 305 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 306 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 307 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 308 309 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 310 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 311 __stringify(counter##_pri##n) } 312 313 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 314 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 315 __stringify(counter##_pri##n) } 316 317 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 318 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 319 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 320 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 321 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 322 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 323 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 324 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 325 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 326 327 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 328 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 329 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 330 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 331 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 332 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 333 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 334 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 335 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 336 337 enum { 338 RX_TOTAL_DISCARDS, 339 TX_TOTAL_DISCARDS, 340 RX_NETPOLL_DISCARDS, 341 }; 342 343 static const char *const bnxt_ring_err_stats_arr[] = { 344 "rx_total_l4_csum_errors", 345 "rx_total_resets", 346 "rx_total_buf_errors", 347 "rx_total_oom_discards", 348 "rx_total_netpoll_discards", 349 "rx_total_ring_discards", 350 "tx_total_resets", 351 "tx_total_ring_discards", 352 "total_missed_irqs", 353 }; 354 355 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str) 356 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str) 357 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str) 358 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str) 359 360 static const struct { 361 long offset; 362 char string[ETH_GSTRING_LEN]; 363 } bnxt_port_stats_arr[] = { 364 BNXT_RX_STATS_ENTRY(rx_64b_frames), 365 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 366 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 367 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 368 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 369 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 370 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 371 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 372 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 373 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 374 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 375 BNXT_RX_STATS_ENTRY(rx_total_frames), 376 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 377 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 378 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 379 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 380 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 381 BNXT_RX_STATS_ENTRY(rx_pause_frames), 382 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 383 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 384 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 385 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 386 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 387 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 388 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 389 BNXT_RX_STATS_ENTRY(rx_good_frames), 390 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 391 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 392 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 393 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 394 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 395 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 396 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 397 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 398 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 399 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 400 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 401 BNXT_RX_STATS_ENTRY(rx_bytes), 402 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 403 BNXT_RX_STATS_ENTRY(rx_runt_frames), 404 BNXT_RX_STATS_ENTRY(rx_stat_discard), 405 BNXT_RX_STATS_ENTRY(rx_stat_err), 406 407 BNXT_TX_STATS_ENTRY(tx_64b_frames), 408 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 409 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 410 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 411 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 412 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 413 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 414 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 415 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 416 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 417 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 418 BNXT_TX_STATS_ENTRY(tx_good_frames), 419 BNXT_TX_STATS_ENTRY(tx_total_frames), 420 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 421 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 422 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 423 BNXT_TX_STATS_ENTRY(tx_pause_frames), 424 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 425 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 426 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 427 BNXT_TX_STATS_ENTRY(tx_err), 428 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 429 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 430 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 431 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 432 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 433 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 434 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 435 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 436 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 437 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 438 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 439 BNXT_TX_STATS_ENTRY(tx_total_collisions), 440 BNXT_TX_STATS_ENTRY(tx_bytes), 441 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 442 BNXT_TX_STATS_ENTRY(tx_stat_discard), 443 BNXT_TX_STATS_ENTRY(tx_stat_error), 444 }; 445 446 static const struct { 447 long offset; 448 char string[ETH_GSTRING_LEN]; 449 } bnxt_port_stats_ext_arr[] = { 450 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 451 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 452 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 453 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 454 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 455 BNXT_RX_STATS_EXT_COS_ENTRIES, 456 BNXT_RX_STATS_EXT_PFC_ENTRIES, 457 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 458 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 459 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 460 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 461 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 462 BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks), 463 BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks), 464 BNXT_RX_STATS_EXT_ENTRY(rx_filter_miss), 465 }; 466 467 static const struct { 468 long offset; 469 char string[ETH_GSTRING_LEN]; 470 } bnxt_tx_port_stats_ext_arr[] = { 471 BNXT_TX_STATS_EXT_COS_ENTRIES, 472 BNXT_TX_STATS_EXT_PFC_ENTRIES, 473 }; 474 475 static const struct { 476 long base_off; 477 char string[ETH_GSTRING_LEN]; 478 } bnxt_rx_bytes_pri_arr[] = { 479 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 480 }; 481 482 static const struct { 483 long base_off; 484 char string[ETH_GSTRING_LEN]; 485 } bnxt_rx_pkts_pri_arr[] = { 486 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 487 }; 488 489 static const struct { 490 long base_off; 491 char string[ETH_GSTRING_LEN]; 492 } bnxt_tx_bytes_pri_arr[] = { 493 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 494 }; 495 496 static const struct { 497 long base_off; 498 char string[ETH_GSTRING_LEN]; 499 } bnxt_tx_pkts_pri_arr[] = { 500 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 501 }; 502 503 #define BNXT_NUM_RING_ERR_STATS ARRAY_SIZE(bnxt_ring_err_stats_arr) 504 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 505 #define BNXT_NUM_STATS_PRI \ 506 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 507 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 508 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 509 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 510 511 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 512 { 513 if (BNXT_SUPPORTS_TPA(bp)) { 514 if (bp->max_tpa_v2) { 515 if (BNXT_CHIP_P5(bp)) 516 return BNXT_NUM_TPA_RING_STATS_P5; 517 return BNXT_NUM_TPA_RING_STATS_P7; 518 } 519 return BNXT_NUM_TPA_RING_STATS; 520 } 521 return 0; 522 } 523 524 static int bnxt_get_num_ring_stats(struct bnxt *bp) 525 { 526 int rx, tx, cmn; 527 528 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS + 529 bnxt_get_num_tpa_ring_stats(bp); 530 tx = NUM_RING_TX_HW_STATS; 531 cmn = NUM_RING_CMN_SW_STATS; 532 return rx * bp->rx_nr_rings + 533 tx * (bp->tx_nr_rings_xdp + bp->tx_nr_rings_per_tc) + 534 cmn * bp->cp_nr_rings; 535 } 536 537 static int bnxt_get_num_stats(struct bnxt *bp) 538 { 539 int num_stats = bnxt_get_num_ring_stats(bp); 540 int len; 541 542 num_stats += BNXT_NUM_RING_ERR_STATS; 543 544 if (bp->flags & BNXT_FLAG_PORT_STATS) 545 num_stats += BNXT_NUM_PORT_STATS; 546 547 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 548 len = min_t(int, bp->fw_rx_stats_ext_size, 549 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 550 num_stats += len; 551 len = min_t(int, bp->fw_tx_stats_ext_size, 552 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 553 num_stats += len; 554 if (bp->pri2cos_valid) 555 num_stats += BNXT_NUM_STATS_PRI; 556 } 557 558 return num_stats; 559 } 560 561 static int bnxt_get_sset_count(struct net_device *dev, int sset) 562 { 563 struct bnxt *bp = netdev_priv(dev); 564 565 switch (sset) { 566 case ETH_SS_STATS: 567 return bnxt_get_num_stats(bp); 568 case ETH_SS_TEST: 569 if (!bp->num_tests) 570 return -EOPNOTSUPP; 571 return bp->num_tests; 572 default: 573 return -EOPNOTSUPP; 574 } 575 } 576 577 static bool is_rx_ring(struct bnxt *bp, int ring_num) 578 { 579 return ring_num < bp->rx_nr_rings; 580 } 581 582 static bool is_tx_ring(struct bnxt *bp, int ring_num) 583 { 584 int tx_base = 0; 585 586 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 587 tx_base = bp->rx_nr_rings; 588 589 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings)) 590 return true; 591 return false; 592 } 593 594 static void bnxt_get_ethtool_stats(struct net_device *dev, 595 struct ethtool_stats *stats, u64 *buf) 596 { 597 struct bnxt_total_ring_err_stats ring_err_stats = {0}; 598 struct bnxt *bp = netdev_priv(dev); 599 u64 *curr, *prev; 600 u32 tpa_stats; 601 u32 i, j = 0; 602 603 if (!bp->bnapi) { 604 j += bnxt_get_num_ring_stats(bp); 605 goto skip_ring_stats; 606 } 607 608 tpa_stats = bnxt_get_num_tpa_ring_stats(bp); 609 for (i = 0; i < bp->cp_nr_rings; i++) { 610 struct bnxt_napi *bnapi = bp->bnapi[i]; 611 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 612 u64 *sw_stats = cpr->stats.sw_stats; 613 u64 *sw; 614 int k; 615 616 if (is_rx_ring(bp, i)) { 617 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++) 618 buf[j] = sw_stats[k]; 619 } 620 if (is_tx_ring(bp, i)) { 621 k = NUM_RING_RX_HW_STATS; 622 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 623 j++, k++) 624 buf[j] = sw_stats[k]; 625 } 626 if (!tpa_stats || !is_rx_ring(bp, i)) 627 goto skip_tpa_ring_stats; 628 629 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 630 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS + 631 tpa_stats; j++, k++) 632 buf[j] = sw_stats[k]; 633 634 skip_tpa_ring_stats: 635 sw = (u64 *)&cpr->sw_stats->rx; 636 if (is_rx_ring(bp, i)) { 637 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++) 638 buf[j] = sw[k]; 639 } 640 641 sw = (u64 *)&cpr->sw_stats->cmn; 642 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++) 643 buf[j] = sw[k]; 644 } 645 646 bnxt_get_ring_err_stats(bp, &ring_err_stats); 647 648 skip_ring_stats: 649 curr = &ring_err_stats.rx_total_l4_csum_errors; 650 prev = &bp->ring_err_stats_prev.rx_total_l4_csum_errors; 651 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++, j++, curr++, prev++) 652 buf[j] = *curr + *prev; 653 654 if (bp->flags & BNXT_FLAG_PORT_STATS) { 655 u64 *port_stats = bp->port_stats.sw_stats; 656 657 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) 658 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset); 659 } 660 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 661 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats; 662 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats; 663 u32 len; 664 665 len = min_t(u32, bp->fw_rx_stats_ext_size, 666 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 667 for (i = 0; i < len; i++, j++) { 668 buf[j] = *(rx_port_stats_ext + 669 bnxt_port_stats_ext_arr[i].offset); 670 } 671 len = min_t(u32, bp->fw_tx_stats_ext_size, 672 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 673 for (i = 0; i < len; i++, j++) { 674 buf[j] = *(tx_port_stats_ext + 675 bnxt_tx_port_stats_ext_arr[i].offset); 676 } 677 if (bp->pri2cos_valid) { 678 for (i = 0; i < 8; i++, j++) { 679 long n = bnxt_rx_bytes_pri_arr[i].base_off + 680 bp->pri2cos_idx[i]; 681 682 buf[j] = *(rx_port_stats_ext + n); 683 } 684 for (i = 0; i < 8; i++, j++) { 685 long n = bnxt_rx_pkts_pri_arr[i].base_off + 686 bp->pri2cos_idx[i]; 687 688 buf[j] = *(rx_port_stats_ext + n); 689 } 690 for (i = 0; i < 8; i++, j++) { 691 long n = bnxt_tx_bytes_pri_arr[i].base_off + 692 bp->pri2cos_idx[i]; 693 694 buf[j] = *(tx_port_stats_ext + n); 695 } 696 for (i = 0; i < 8; i++, j++) { 697 long n = bnxt_tx_pkts_pri_arr[i].base_off + 698 bp->pri2cos_idx[i]; 699 700 buf[j] = *(tx_port_stats_ext + n); 701 } 702 } 703 } 704 } 705 706 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 707 { 708 struct bnxt *bp = netdev_priv(dev); 709 u32 i, j, num_str; 710 const char *str; 711 712 switch (stringset) { 713 case ETH_SS_STATS: 714 for (i = 0; i < bp->cp_nr_rings; i++) { 715 if (is_rx_ring(bp, i)) 716 for (j = 0; j < NUM_RING_RX_HW_STATS; j++) { 717 str = bnxt_ring_rx_stats_str[j]; 718 ethtool_sprintf(&buf, "[%d]: %s", i, 719 str); 720 } 721 if (is_tx_ring(bp, i)) 722 for (j = 0; j < NUM_RING_TX_HW_STATS; j++) { 723 str = bnxt_ring_tx_stats_str[j]; 724 ethtool_sprintf(&buf, "[%d]: %s", i, 725 str); 726 } 727 num_str = bnxt_get_num_tpa_ring_stats(bp); 728 if (!num_str || !is_rx_ring(bp, i)) 729 goto skip_tpa_stats; 730 731 if (bp->max_tpa_v2) 732 for (j = 0; j < num_str; j++) { 733 str = bnxt_ring_tpa2_stats_str[j]; 734 ethtool_sprintf(&buf, "[%d]: %s", i, 735 str); 736 } 737 else 738 for (j = 0; j < num_str; j++) { 739 str = bnxt_ring_tpa_stats_str[j]; 740 ethtool_sprintf(&buf, "[%d]: %s", i, 741 str); 742 } 743 skip_tpa_stats: 744 if (is_rx_ring(bp, i)) 745 for (j = 0; j < NUM_RING_RX_SW_STATS; j++) { 746 str = bnxt_rx_sw_stats_str[j]; 747 ethtool_sprintf(&buf, "[%d]: %s", i, 748 str); 749 } 750 for (j = 0; j < NUM_RING_CMN_SW_STATS; j++) { 751 str = bnxt_cmn_sw_stats_str[j]; 752 ethtool_sprintf(&buf, "[%d]: %s", i, str); 753 } 754 } 755 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++) 756 ethtool_puts(&buf, bnxt_ring_err_stats_arr[i]); 757 758 if (bp->flags & BNXT_FLAG_PORT_STATS) 759 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 760 str = bnxt_port_stats_arr[i].string; 761 ethtool_puts(&buf, str); 762 } 763 764 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 765 u32 len; 766 767 len = min_t(u32, bp->fw_rx_stats_ext_size, 768 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 769 for (i = 0; i < len; i++) { 770 str = bnxt_port_stats_ext_arr[i].string; 771 ethtool_puts(&buf, str); 772 } 773 774 len = min_t(u32, bp->fw_tx_stats_ext_size, 775 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 776 for (i = 0; i < len; i++) { 777 str = bnxt_tx_port_stats_ext_arr[i].string; 778 ethtool_puts(&buf, str); 779 } 780 781 if (bp->pri2cos_valid) { 782 for (i = 0; i < 8; i++) { 783 str = bnxt_rx_bytes_pri_arr[i].string; 784 ethtool_puts(&buf, str); 785 } 786 787 for (i = 0; i < 8; i++) { 788 str = bnxt_rx_pkts_pri_arr[i].string; 789 ethtool_puts(&buf, str); 790 } 791 792 for (i = 0; i < 8; i++) { 793 str = bnxt_tx_bytes_pri_arr[i].string; 794 ethtool_puts(&buf, str); 795 } 796 797 for (i = 0; i < 8; i++) { 798 str = bnxt_tx_pkts_pri_arr[i].string; 799 ethtool_puts(&buf, str); 800 } 801 } 802 } 803 break; 804 case ETH_SS_TEST: 805 if (bp->num_tests) 806 for (i = 0; i < bp->num_tests; i++) 807 ethtool_puts(&buf, bp->test_info->string[i]); 808 break; 809 default: 810 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 811 stringset); 812 break; 813 } 814 } 815 816 static void bnxt_get_ringparam(struct net_device *dev, 817 struct ethtool_ringparam *ering, 818 struct kernel_ethtool_ringparam *kernel_ering, 819 struct netlink_ext_ack *extack) 820 { 821 struct bnxt *bp = netdev_priv(dev); 822 823 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 824 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA; 825 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 826 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_ENABLED; 827 } else { 828 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 829 ering->rx_jumbo_max_pending = 0; 830 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_DISABLED; 831 } 832 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 833 834 ering->rx_pending = bp->rx_ring_size; 835 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 836 ering->tx_pending = bp->tx_ring_size; 837 838 kernel_ering->hds_thresh_max = BNXT_HDS_THRESHOLD_MAX; 839 } 840 841 static int bnxt_set_ringparam(struct net_device *dev, 842 struct ethtool_ringparam *ering, 843 struct kernel_ethtool_ringparam *kernel_ering, 844 struct netlink_ext_ack *extack) 845 { 846 u8 tcp_data_split = kernel_ering->tcp_data_split; 847 struct bnxt *bp = netdev_priv(dev); 848 u8 hds_config_mod; 849 850 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 851 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 852 (ering->tx_pending < BNXT_MIN_TX_DESC_CNT)) 853 return -EINVAL; 854 855 hds_config_mod = tcp_data_split != dev->cfg->hds_config; 856 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_DISABLED && hds_config_mod) 857 return -EINVAL; 858 859 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_ENABLED && 860 hds_config_mod && BNXT_RX_PAGE_MODE(bp)) { 861 NL_SET_ERR_MSG_MOD(extack, "tcp-data-split is disallowed when XDP is attached"); 862 return -EINVAL; 863 } 864 865 if (netif_running(dev)) 866 bnxt_close_nic(bp, false, false); 867 868 if (hds_config_mod) { 869 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_ENABLED) 870 bp->flags |= BNXT_FLAG_HDS; 871 else if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_UNKNOWN) 872 bp->flags &= ~BNXT_FLAG_HDS; 873 } 874 875 bp->rx_ring_size = ering->rx_pending; 876 bp->tx_ring_size = ering->tx_pending; 877 bnxt_set_ring_params(bp); 878 879 if (netif_running(dev)) 880 return bnxt_open_nic(bp, false, false); 881 882 return 0; 883 } 884 885 static void bnxt_get_channels(struct net_device *dev, 886 struct ethtool_channels *channel) 887 { 888 struct bnxt *bp = netdev_priv(dev); 889 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 890 int max_rx_rings, max_tx_rings, tcs; 891 int max_tx_sch_inputs, tx_grps; 892 893 /* Get the most up-to-date max_tx_sch_inputs. */ 894 if (netif_running(dev) && BNXT_NEW_RM(bp)) 895 bnxt_hwrm_func_resc_qcaps(bp, false); 896 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 897 898 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 899 if (max_tx_sch_inputs) 900 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 901 902 tcs = bp->num_tc; 903 tx_grps = max(tcs, 1); 904 if (bp->tx_nr_rings_xdp) 905 tx_grps++; 906 max_tx_rings /= tx_grps; 907 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 908 909 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 910 max_rx_rings = 0; 911 max_tx_rings = 0; 912 } 913 if (max_tx_sch_inputs) 914 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 915 916 if (tcs > 1) 917 max_tx_rings /= tcs; 918 919 channel->max_rx = max_rx_rings; 920 channel->max_tx = max_tx_rings; 921 channel->max_other = 0; 922 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 923 channel->combined_count = bp->rx_nr_rings; 924 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 925 channel->combined_count--; 926 } else { 927 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 928 channel->rx_count = bp->rx_nr_rings; 929 channel->tx_count = bp->tx_nr_rings_per_tc; 930 } 931 } 932 } 933 934 static int bnxt_set_channels(struct net_device *dev, 935 struct ethtool_channels *channel) 936 { 937 struct bnxt *bp = netdev_priv(dev); 938 int req_tx_rings, req_rx_rings, tcs; 939 bool sh = false; 940 int tx_xdp = 0; 941 int rc = 0; 942 int tx_cp; 943 944 if (channel->other_count) 945 return -EINVAL; 946 947 if (!channel->combined_count && 948 (!channel->rx_count || !channel->tx_count)) 949 return -EINVAL; 950 951 if (channel->combined_count && 952 (channel->rx_count || channel->tx_count)) 953 return -EINVAL; 954 955 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 956 channel->tx_count)) 957 return -EINVAL; 958 959 if (channel->combined_count) 960 sh = true; 961 962 tcs = bp->num_tc; 963 964 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 965 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 966 if (bp->tx_nr_rings_xdp) { 967 if (!sh) { 968 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 969 return -EINVAL; 970 } 971 tx_xdp = req_rx_rings; 972 } 973 974 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) != 975 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) && 976 netif_is_rxfh_configured(dev)) { 977 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n"); 978 return -EINVAL; 979 } 980 981 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 982 if (rc) { 983 netdev_warn(dev, "Unable to allocate the requested rings\n"); 984 return rc; 985 } 986 987 if (netif_running(dev)) { 988 if (BNXT_PF(bp)) { 989 /* TODO CHIMP_FW: Send message to all VF's 990 * before PF unload 991 */ 992 } 993 bnxt_close_nic(bp, true, false); 994 } 995 996 if (sh) { 997 bp->flags |= BNXT_FLAG_SHARED_RINGS; 998 bp->rx_nr_rings = channel->combined_count; 999 bp->tx_nr_rings_per_tc = channel->combined_count; 1000 } else { 1001 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 1002 bp->rx_nr_rings = channel->rx_count; 1003 bp->tx_nr_rings_per_tc = channel->tx_count; 1004 } 1005 bp->tx_nr_rings_xdp = tx_xdp; 1006 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 1007 if (tcs > 1) 1008 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 1009 1010 tx_cp = bnxt_num_tx_to_cp(bp, bp->tx_nr_rings); 1011 bp->cp_nr_rings = sh ? max_t(int, tx_cp, bp->rx_nr_rings) : 1012 tx_cp + bp->rx_nr_rings; 1013 1014 /* After changing number of rx channels, update NTUPLE feature. */ 1015 netdev_update_features(dev); 1016 if (netif_running(dev)) { 1017 rc = bnxt_open_nic(bp, true, false); 1018 if ((!rc) && BNXT_PF(bp)) { 1019 /* TODO CHIMP_FW: Send message to all VF's 1020 * to renable 1021 */ 1022 } 1023 } else { 1024 rc = bnxt_reserve_rings(bp, true); 1025 } 1026 1027 return rc; 1028 } 1029 1030 static u32 bnxt_get_all_fltr_ids_rcu(struct bnxt *bp, struct hlist_head tbl[], 1031 int tbl_size, u32 *ids, u32 start, 1032 u32 id_cnt) 1033 { 1034 int i, j = start; 1035 1036 if (j >= id_cnt) 1037 return j; 1038 for (i = 0; i < tbl_size; i++) { 1039 struct hlist_head *head; 1040 struct bnxt_filter_base *fltr; 1041 1042 head = &tbl[i]; 1043 hlist_for_each_entry_rcu(fltr, head, hash) { 1044 if (!fltr->flags || 1045 test_bit(BNXT_FLTR_FW_DELETED, &fltr->state)) 1046 continue; 1047 ids[j++] = fltr->sw_id; 1048 if (j == id_cnt) 1049 return j; 1050 } 1051 } 1052 return j; 1053 } 1054 1055 static struct bnxt_filter_base *bnxt_get_one_fltr_rcu(struct bnxt *bp, 1056 struct hlist_head tbl[], 1057 int tbl_size, u32 id) 1058 { 1059 int i; 1060 1061 for (i = 0; i < tbl_size; i++) { 1062 struct hlist_head *head; 1063 struct bnxt_filter_base *fltr; 1064 1065 head = &tbl[i]; 1066 hlist_for_each_entry_rcu(fltr, head, hash) { 1067 if (fltr->flags && fltr->sw_id == id) 1068 return fltr; 1069 } 1070 } 1071 return NULL; 1072 } 1073 1074 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 1075 u32 *rule_locs) 1076 { 1077 u32 count; 1078 1079 cmd->data = bp->ntp_fltr_count; 1080 rcu_read_lock(); 1081 count = bnxt_get_all_fltr_ids_rcu(bp, bp->l2_fltr_hash_tbl, 1082 BNXT_L2_FLTR_HASH_SIZE, rule_locs, 0, 1083 cmd->rule_cnt); 1084 cmd->rule_cnt = bnxt_get_all_fltr_ids_rcu(bp, bp->ntp_fltr_hash_tbl, 1085 BNXT_NTP_FLTR_HASH_SIZE, 1086 rule_locs, count, 1087 cmd->rule_cnt); 1088 rcu_read_unlock(); 1089 1090 return 0; 1091 } 1092 1093 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1094 { 1095 struct ethtool_rx_flow_spec *fs = 1096 (struct ethtool_rx_flow_spec *)&cmd->fs; 1097 struct bnxt_filter_base *fltr_base; 1098 struct bnxt_ntuple_filter *fltr; 1099 struct bnxt_flow_masks *fmasks; 1100 struct flow_keys *fkeys; 1101 int rc = -EINVAL; 1102 1103 if (fs->location >= bp->max_fltr) 1104 return rc; 1105 1106 rcu_read_lock(); 1107 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl, 1108 BNXT_L2_FLTR_HASH_SIZE, 1109 fs->location); 1110 if (fltr_base) { 1111 struct ethhdr *h_ether = &fs->h_u.ether_spec; 1112 struct ethhdr *m_ether = &fs->m_u.ether_spec; 1113 struct bnxt_l2_filter *l2_fltr; 1114 struct bnxt_l2_key *l2_key; 1115 1116 l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base); 1117 l2_key = &l2_fltr->l2_key; 1118 fs->flow_type = ETHER_FLOW; 1119 ether_addr_copy(h_ether->h_dest, l2_key->dst_mac_addr); 1120 eth_broadcast_addr(m_ether->h_dest); 1121 if (l2_key->vlan) { 1122 struct ethtool_flow_ext *m_ext = &fs->m_ext; 1123 struct ethtool_flow_ext *h_ext = &fs->h_ext; 1124 1125 fs->flow_type |= FLOW_EXT; 1126 m_ext->vlan_tci = htons(0xfff); 1127 h_ext->vlan_tci = htons(l2_key->vlan); 1128 } 1129 if (fltr_base->flags & BNXT_ACT_RING_DST) 1130 fs->ring_cookie = fltr_base->rxq; 1131 if (fltr_base->flags & BNXT_ACT_FUNC_DST) 1132 fs->ring_cookie = (u64)(fltr_base->vf_idx + 1) << 1133 ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 1134 rcu_read_unlock(); 1135 return 0; 1136 } 1137 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl, 1138 BNXT_NTP_FLTR_HASH_SIZE, 1139 fs->location); 1140 if (!fltr_base) { 1141 rcu_read_unlock(); 1142 return rc; 1143 } 1144 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base); 1145 1146 fkeys = &fltr->fkeys; 1147 fmasks = &fltr->fmasks; 1148 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 1149 if (fkeys->basic.ip_proto == BNXT_IP_PROTO_WILDCARD) { 1150 fs->flow_type = IP_USER_FLOW; 1151 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 1152 fs->h_u.usr_ip4_spec.proto = BNXT_IP_PROTO_WILDCARD; 1153 fs->m_u.usr_ip4_spec.proto = 0; 1154 } else if (fkeys->basic.ip_proto == IPPROTO_ICMP) { 1155 fs->flow_type = IP_USER_FLOW; 1156 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 1157 fs->h_u.usr_ip4_spec.proto = IPPROTO_ICMP; 1158 fs->m_u.usr_ip4_spec.proto = BNXT_IP_PROTO_FULL_MASK; 1159 } else if (fkeys->basic.ip_proto == IPPROTO_TCP) { 1160 fs->flow_type = TCP_V4_FLOW; 1161 } else if (fkeys->basic.ip_proto == IPPROTO_UDP) { 1162 fs->flow_type = UDP_V4_FLOW; 1163 } else { 1164 goto fltr_err; 1165 } 1166 1167 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 1168 fs->m_u.tcp_ip4_spec.ip4src = fmasks->addrs.v4addrs.src; 1169 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 1170 fs->m_u.tcp_ip4_spec.ip4dst = fmasks->addrs.v4addrs.dst; 1171 if (fs->flow_type == TCP_V4_FLOW || 1172 fs->flow_type == UDP_V4_FLOW) { 1173 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 1174 fs->m_u.tcp_ip4_spec.psrc = fmasks->ports.src; 1175 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 1176 fs->m_u.tcp_ip4_spec.pdst = fmasks->ports.dst; 1177 } 1178 } else { 1179 if (fkeys->basic.ip_proto == BNXT_IP_PROTO_WILDCARD) { 1180 fs->flow_type = IPV6_USER_FLOW; 1181 fs->h_u.usr_ip6_spec.l4_proto = BNXT_IP_PROTO_WILDCARD; 1182 fs->m_u.usr_ip6_spec.l4_proto = 0; 1183 } else if (fkeys->basic.ip_proto == IPPROTO_ICMPV6) { 1184 fs->flow_type = IPV6_USER_FLOW; 1185 fs->h_u.usr_ip6_spec.l4_proto = IPPROTO_ICMPV6; 1186 fs->m_u.usr_ip6_spec.l4_proto = BNXT_IP_PROTO_FULL_MASK; 1187 } else if (fkeys->basic.ip_proto == IPPROTO_TCP) { 1188 fs->flow_type = TCP_V6_FLOW; 1189 } else if (fkeys->basic.ip_proto == IPPROTO_UDP) { 1190 fs->flow_type = UDP_V6_FLOW; 1191 } else { 1192 goto fltr_err; 1193 } 1194 1195 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 1196 fkeys->addrs.v6addrs.src; 1197 *(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6src[0] = 1198 fmasks->addrs.v6addrs.src; 1199 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 1200 fkeys->addrs.v6addrs.dst; 1201 *(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6dst[0] = 1202 fmasks->addrs.v6addrs.dst; 1203 if (fs->flow_type == TCP_V6_FLOW || 1204 fs->flow_type == UDP_V6_FLOW) { 1205 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 1206 fs->m_u.tcp_ip6_spec.psrc = fmasks->ports.src; 1207 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 1208 fs->m_u.tcp_ip6_spec.pdst = fmasks->ports.dst; 1209 } 1210 } 1211 1212 if (fltr->base.flags & BNXT_ACT_DROP) { 1213 fs->ring_cookie = RX_CLS_FLOW_DISC; 1214 } else if (fltr->base.flags & BNXT_ACT_RSS_CTX) { 1215 fs->flow_type |= FLOW_RSS; 1216 cmd->rss_context = fltr->base.fw_vnic_id; 1217 } else { 1218 fs->ring_cookie = fltr->base.rxq; 1219 } 1220 rc = 0; 1221 1222 fltr_err: 1223 rcu_read_unlock(); 1224 1225 return rc; 1226 } 1227 1228 static struct bnxt_rss_ctx *bnxt_get_rss_ctx_from_index(struct bnxt *bp, 1229 u32 index) 1230 { 1231 struct ethtool_rxfh_context *ctx; 1232 1233 ctx = xa_load(&bp->dev->ethtool->rss_ctx, index); 1234 if (!ctx) 1235 return NULL; 1236 return ethtool_rxfh_context_priv(ctx); 1237 } 1238 1239 static int bnxt_alloc_vnic_rss_table(struct bnxt *bp, 1240 struct bnxt_vnic_info *vnic) 1241 { 1242 int size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5); 1243 1244 vnic->rss_table_size = size + HW_HASH_KEY_SIZE; 1245 vnic->rss_table = dma_alloc_coherent(&bp->pdev->dev, 1246 vnic->rss_table_size, 1247 &vnic->rss_table_dma_addr, 1248 GFP_KERNEL); 1249 if (!vnic->rss_table) 1250 return -ENOMEM; 1251 1252 vnic->rss_hash_key = ((void *)vnic->rss_table) + size; 1253 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; 1254 return 0; 1255 } 1256 1257 static int bnxt_add_l2_cls_rule(struct bnxt *bp, 1258 struct ethtool_rx_flow_spec *fs) 1259 { 1260 u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1261 u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1262 struct ethhdr *h_ether = &fs->h_u.ether_spec; 1263 struct ethhdr *m_ether = &fs->m_u.ether_spec; 1264 struct bnxt_l2_filter *fltr; 1265 struct bnxt_l2_key key; 1266 u16 vnic_id; 1267 u8 flags; 1268 int rc; 1269 1270 if (BNXT_CHIP_P5_PLUS(bp)) 1271 return -EOPNOTSUPP; 1272 1273 if (!is_broadcast_ether_addr(m_ether->h_dest)) 1274 return -EINVAL; 1275 ether_addr_copy(key.dst_mac_addr, h_ether->h_dest); 1276 key.vlan = 0; 1277 if (fs->flow_type & FLOW_EXT) { 1278 struct ethtool_flow_ext *m_ext = &fs->m_ext; 1279 struct ethtool_flow_ext *h_ext = &fs->h_ext; 1280 1281 if (m_ext->vlan_tci != htons(0xfff) || !h_ext->vlan_tci) 1282 return -EINVAL; 1283 key.vlan = ntohs(h_ext->vlan_tci); 1284 } 1285 1286 if (vf) { 1287 flags = BNXT_ACT_FUNC_DST; 1288 vnic_id = 0xffff; 1289 vf--; 1290 } else { 1291 flags = BNXT_ACT_RING_DST; 1292 vnic_id = bp->vnic_info[ring + 1].fw_vnic_id; 1293 } 1294 fltr = bnxt_alloc_new_l2_filter(bp, &key, flags); 1295 if (IS_ERR(fltr)) 1296 return PTR_ERR(fltr); 1297 1298 fltr->base.fw_vnic_id = vnic_id; 1299 fltr->base.rxq = ring; 1300 fltr->base.vf_idx = vf; 1301 rc = bnxt_hwrm_l2_filter_alloc(bp, fltr); 1302 if (rc) 1303 bnxt_del_l2_filter(bp, fltr); 1304 else 1305 fs->location = fltr->base.sw_id; 1306 return rc; 1307 } 1308 1309 static bool bnxt_verify_ntuple_ip4_flow(struct ethtool_usrip4_spec *ip_spec, 1310 struct ethtool_usrip4_spec *ip_mask) 1311 { 1312 u8 mproto = ip_mask->proto; 1313 u8 sproto = ip_spec->proto; 1314 1315 if (ip_mask->l4_4_bytes || ip_mask->tos || 1316 ip_spec->ip_ver != ETH_RX_NFC_IP4 || 1317 (mproto && (mproto != BNXT_IP_PROTO_FULL_MASK || sproto != IPPROTO_ICMP))) 1318 return false; 1319 return true; 1320 } 1321 1322 static bool bnxt_verify_ntuple_ip6_flow(struct ethtool_usrip6_spec *ip_spec, 1323 struct ethtool_usrip6_spec *ip_mask) 1324 { 1325 u8 mproto = ip_mask->l4_proto; 1326 u8 sproto = ip_spec->l4_proto; 1327 1328 if (ip_mask->l4_4_bytes || ip_mask->tclass || 1329 (mproto && (mproto != BNXT_IP_PROTO_FULL_MASK || sproto != IPPROTO_ICMPV6))) 1330 return false; 1331 return true; 1332 } 1333 1334 static int bnxt_add_ntuple_cls_rule(struct bnxt *bp, 1335 struct ethtool_rxnfc *cmd) 1336 { 1337 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1338 struct bnxt_ntuple_filter *new_fltr, *fltr; 1339 u32 flow_type = fs->flow_type & 0xff; 1340 struct bnxt_l2_filter *l2_fltr; 1341 struct bnxt_flow_masks *fmasks; 1342 struct flow_keys *fkeys; 1343 u32 idx, ring; 1344 int rc; 1345 u8 vf; 1346 1347 if (!bp->vnic_info) 1348 return -EAGAIN; 1349 1350 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1351 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1352 if ((fs->flow_type & (FLOW_MAC_EXT | FLOW_EXT)) || vf) 1353 return -EOPNOTSUPP; 1354 1355 if (flow_type == IP_USER_FLOW) { 1356 if (!bnxt_verify_ntuple_ip4_flow(&fs->h_u.usr_ip4_spec, 1357 &fs->m_u.usr_ip4_spec)) 1358 return -EOPNOTSUPP; 1359 } 1360 1361 if (flow_type == IPV6_USER_FLOW) { 1362 if (!bnxt_verify_ntuple_ip6_flow(&fs->h_u.usr_ip6_spec, 1363 &fs->m_u.usr_ip6_spec)) 1364 return -EOPNOTSUPP; 1365 } 1366 1367 new_fltr = kzalloc(sizeof(*new_fltr), GFP_KERNEL); 1368 if (!new_fltr) 1369 return -ENOMEM; 1370 1371 l2_fltr = bp->vnic_info[BNXT_VNIC_DEFAULT].l2_filters[0]; 1372 atomic_inc(&l2_fltr->refcnt); 1373 new_fltr->l2_fltr = l2_fltr; 1374 fmasks = &new_fltr->fmasks; 1375 fkeys = &new_fltr->fkeys; 1376 1377 rc = -EOPNOTSUPP; 1378 switch (flow_type) { 1379 case IP_USER_FLOW: { 1380 struct ethtool_usrip4_spec *ip_spec = &fs->h_u.usr_ip4_spec; 1381 struct ethtool_usrip4_spec *ip_mask = &fs->m_u.usr_ip4_spec; 1382 1383 fkeys->basic.ip_proto = ip_mask->proto ? ip_spec->proto 1384 : BNXT_IP_PROTO_WILDCARD; 1385 fkeys->basic.n_proto = htons(ETH_P_IP); 1386 fkeys->addrs.v4addrs.src = ip_spec->ip4src; 1387 fmasks->addrs.v4addrs.src = ip_mask->ip4src; 1388 fkeys->addrs.v4addrs.dst = ip_spec->ip4dst; 1389 fmasks->addrs.v4addrs.dst = ip_mask->ip4dst; 1390 break; 1391 } 1392 case TCP_V4_FLOW: 1393 case UDP_V4_FLOW: { 1394 struct ethtool_tcpip4_spec *ip_spec = &fs->h_u.tcp_ip4_spec; 1395 struct ethtool_tcpip4_spec *ip_mask = &fs->m_u.tcp_ip4_spec; 1396 1397 fkeys->basic.ip_proto = IPPROTO_TCP; 1398 if (flow_type == UDP_V4_FLOW) 1399 fkeys->basic.ip_proto = IPPROTO_UDP; 1400 fkeys->basic.n_proto = htons(ETH_P_IP); 1401 fkeys->addrs.v4addrs.src = ip_spec->ip4src; 1402 fmasks->addrs.v4addrs.src = ip_mask->ip4src; 1403 fkeys->addrs.v4addrs.dst = ip_spec->ip4dst; 1404 fmasks->addrs.v4addrs.dst = ip_mask->ip4dst; 1405 fkeys->ports.src = ip_spec->psrc; 1406 fmasks->ports.src = ip_mask->psrc; 1407 fkeys->ports.dst = ip_spec->pdst; 1408 fmasks->ports.dst = ip_mask->pdst; 1409 break; 1410 } 1411 case IPV6_USER_FLOW: { 1412 struct ethtool_usrip6_spec *ip_spec = &fs->h_u.usr_ip6_spec; 1413 struct ethtool_usrip6_spec *ip_mask = &fs->m_u.usr_ip6_spec; 1414 1415 fkeys->basic.ip_proto = ip_mask->l4_proto ? ip_spec->l4_proto 1416 : BNXT_IP_PROTO_WILDCARD; 1417 fkeys->basic.n_proto = htons(ETH_P_IPV6); 1418 fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src; 1419 fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src; 1420 fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst; 1421 fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst; 1422 break; 1423 } 1424 case TCP_V6_FLOW: 1425 case UDP_V6_FLOW: { 1426 struct ethtool_tcpip6_spec *ip_spec = &fs->h_u.tcp_ip6_spec; 1427 struct ethtool_tcpip6_spec *ip_mask = &fs->m_u.tcp_ip6_spec; 1428 1429 fkeys->basic.ip_proto = IPPROTO_TCP; 1430 if (flow_type == UDP_V6_FLOW) 1431 fkeys->basic.ip_proto = IPPROTO_UDP; 1432 fkeys->basic.n_proto = htons(ETH_P_IPV6); 1433 1434 fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src; 1435 fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src; 1436 fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst; 1437 fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst; 1438 fkeys->ports.src = ip_spec->psrc; 1439 fmasks->ports.src = ip_mask->psrc; 1440 fkeys->ports.dst = ip_spec->pdst; 1441 fmasks->ports.dst = ip_mask->pdst; 1442 break; 1443 } 1444 default: 1445 rc = -EOPNOTSUPP; 1446 goto ntuple_err; 1447 } 1448 if (!memcmp(&BNXT_FLOW_MASK_NONE, fmasks, sizeof(*fmasks))) 1449 goto ntuple_err; 1450 1451 idx = bnxt_get_ntp_filter_idx(bp, fkeys, NULL); 1452 rcu_read_lock(); 1453 fltr = bnxt_lookup_ntp_filter_from_idx(bp, new_fltr, idx); 1454 if (fltr) { 1455 rcu_read_unlock(); 1456 rc = -EEXIST; 1457 goto ntuple_err; 1458 } 1459 rcu_read_unlock(); 1460 1461 new_fltr->base.flags = BNXT_ACT_NO_AGING; 1462 if (fs->flow_type & FLOW_RSS) { 1463 struct bnxt_rss_ctx *rss_ctx; 1464 1465 new_fltr->base.fw_vnic_id = 0; 1466 new_fltr->base.flags |= BNXT_ACT_RSS_CTX; 1467 rss_ctx = bnxt_get_rss_ctx_from_index(bp, cmd->rss_context); 1468 if (rss_ctx) { 1469 new_fltr->base.fw_vnic_id = rss_ctx->index; 1470 } else { 1471 rc = -EINVAL; 1472 goto ntuple_err; 1473 } 1474 } 1475 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1476 new_fltr->base.flags |= BNXT_ACT_DROP; 1477 else 1478 new_fltr->base.rxq = ring; 1479 __set_bit(BNXT_FLTR_VALID, &new_fltr->base.state); 1480 rc = bnxt_insert_ntp_filter(bp, new_fltr, idx); 1481 if (!rc) { 1482 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, new_fltr); 1483 if (rc) { 1484 bnxt_del_ntp_filter(bp, new_fltr); 1485 return rc; 1486 } 1487 fs->location = new_fltr->base.sw_id; 1488 return 0; 1489 } 1490 1491 ntuple_err: 1492 atomic_dec(&l2_fltr->refcnt); 1493 kfree(new_fltr); 1494 return rc; 1495 } 1496 1497 static int bnxt_srxclsrlins(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1498 { 1499 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1500 u32 ring, flow_type; 1501 int rc; 1502 u8 vf; 1503 1504 if (!netif_running(bp->dev)) 1505 return -EAGAIN; 1506 if (!(bp->flags & BNXT_FLAG_RFS)) 1507 return -EPERM; 1508 if (fs->location != RX_CLS_LOC_ANY) 1509 return -EINVAL; 1510 1511 flow_type = fs->flow_type; 1512 if ((flow_type == IP_USER_FLOW || 1513 flow_type == IPV6_USER_FLOW) && 1514 !(bp->fw_cap & BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO)) 1515 return -EOPNOTSUPP; 1516 if (flow_type & FLOW_MAC_EXT) 1517 return -EINVAL; 1518 flow_type &= ~FLOW_EXT; 1519 1520 if (fs->ring_cookie == RX_CLS_FLOW_DISC && flow_type != ETHER_FLOW) 1521 return bnxt_add_ntuple_cls_rule(bp, cmd); 1522 1523 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1524 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1525 if (BNXT_VF(bp) && vf) 1526 return -EINVAL; 1527 if (BNXT_PF(bp) && vf > bp->pf.active_vfs) 1528 return -EINVAL; 1529 if (!vf && ring >= bp->rx_nr_rings) 1530 return -EINVAL; 1531 1532 if (flow_type == ETHER_FLOW) 1533 rc = bnxt_add_l2_cls_rule(bp, fs); 1534 else 1535 rc = bnxt_add_ntuple_cls_rule(bp, cmd); 1536 return rc; 1537 } 1538 1539 static int bnxt_srxclsrldel(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1540 { 1541 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1542 struct bnxt_filter_base *fltr_base; 1543 struct bnxt_ntuple_filter *fltr; 1544 u32 id = fs->location; 1545 1546 rcu_read_lock(); 1547 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl, 1548 BNXT_L2_FLTR_HASH_SIZE, id); 1549 if (fltr_base) { 1550 struct bnxt_l2_filter *l2_fltr; 1551 1552 l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base); 1553 rcu_read_unlock(); 1554 bnxt_hwrm_l2_filter_free(bp, l2_fltr); 1555 bnxt_del_l2_filter(bp, l2_fltr); 1556 return 0; 1557 } 1558 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl, 1559 BNXT_NTP_FLTR_HASH_SIZE, id); 1560 if (!fltr_base) { 1561 rcu_read_unlock(); 1562 return -ENOENT; 1563 } 1564 1565 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base); 1566 if (!(fltr->base.flags & BNXT_ACT_NO_AGING)) { 1567 rcu_read_unlock(); 1568 return -EINVAL; 1569 } 1570 rcu_read_unlock(); 1571 bnxt_hwrm_cfa_ntuple_filter_free(bp, fltr); 1572 bnxt_del_ntp_filter(bp, fltr); 1573 return 0; 1574 } 1575 1576 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1577 { 1578 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1579 return RXH_IP_SRC | RXH_IP_DST; 1580 return 0; 1581 } 1582 1583 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1584 { 1585 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1586 return RXH_IP_SRC | RXH_IP_DST; 1587 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL) 1588 return RXH_IP_SRC | RXH_IP_DST | RXH_IP6_FL; 1589 return 0; 1590 } 1591 1592 static int bnxt_get_rxfh_fields(struct net_device *dev, 1593 struct ethtool_rxfh_fields *cmd) 1594 { 1595 struct bnxt *bp = netdev_priv(dev); 1596 1597 cmd->data = 0; 1598 switch (cmd->flow_type) { 1599 case TCP_V4_FLOW: 1600 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1601 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1602 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1603 cmd->data |= get_ethtool_ipv4_rss(bp); 1604 break; 1605 case UDP_V4_FLOW: 1606 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1607 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1608 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1609 fallthrough; 1610 case AH_ESP_V4_FLOW: 1611 if (bp->rss_hash_cfg & 1612 (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1613 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4)) 1614 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1615 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1616 fallthrough; 1617 case SCTP_V4_FLOW: 1618 case AH_V4_FLOW: 1619 case ESP_V4_FLOW: 1620 case IPV4_FLOW: 1621 cmd->data |= get_ethtool_ipv4_rss(bp); 1622 break; 1623 1624 case TCP_V6_FLOW: 1625 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1626 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1627 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1628 cmd->data |= get_ethtool_ipv6_rss(bp); 1629 break; 1630 case UDP_V6_FLOW: 1631 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1632 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1633 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1634 fallthrough; 1635 case AH_ESP_V6_FLOW: 1636 if (bp->rss_hash_cfg & 1637 (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1638 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6)) 1639 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1640 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1641 fallthrough; 1642 case SCTP_V6_FLOW: 1643 case AH_V6_FLOW: 1644 case ESP_V6_FLOW: 1645 case IPV6_FLOW: 1646 cmd->data |= get_ethtool_ipv6_rss(bp); 1647 break; 1648 } 1649 return 0; 1650 } 1651 1652 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1653 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1654 1655 static int bnxt_set_rxfh_fields(struct net_device *dev, 1656 const struct ethtool_rxfh_fields *cmd, 1657 struct netlink_ext_ack *extack) 1658 { 1659 struct bnxt *bp = netdev_priv(dev); 1660 int tuple, rc = 0; 1661 u32 rss_hash_cfg; 1662 1663 rss_hash_cfg = bp->rss_hash_cfg; 1664 1665 if (cmd->data == RXH_4TUPLE) 1666 tuple = 4; 1667 else if (cmd->data == RXH_2TUPLE || 1668 cmd->data == (RXH_2TUPLE | RXH_IP6_FL)) 1669 tuple = 2; 1670 else if (!cmd->data) 1671 tuple = 0; 1672 else 1673 return -EINVAL; 1674 1675 if (cmd->data & RXH_IP6_FL && 1676 !(bp->rss_cap & BNXT_RSS_CAP_IPV6_FLOW_LABEL_RSS_CAP)) 1677 return -EINVAL; 1678 1679 if (cmd->flow_type == TCP_V4_FLOW) { 1680 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1681 if (tuple == 4) 1682 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1683 } else if (cmd->flow_type == UDP_V4_FLOW) { 1684 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP)) 1685 return -EINVAL; 1686 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1687 if (tuple == 4) 1688 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1689 } else if (cmd->flow_type == TCP_V6_FLOW) { 1690 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1691 if (tuple == 4) 1692 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1693 } else if (cmd->flow_type == UDP_V6_FLOW) { 1694 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP)) 1695 return -EINVAL; 1696 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1697 if (tuple == 4) 1698 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1699 } else if (cmd->flow_type == AH_ESP_V4_FLOW) { 1700 if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V4_RSS_CAP) || 1701 !(bp->rss_cap & BNXT_RSS_CAP_ESP_V4_RSS_CAP))) 1702 return -EINVAL; 1703 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1704 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4); 1705 if (tuple == 4) 1706 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1707 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4; 1708 } else if (cmd->flow_type == AH_ESP_V6_FLOW) { 1709 if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V6_RSS_CAP) || 1710 !(bp->rss_cap & BNXT_RSS_CAP_ESP_V6_RSS_CAP))) 1711 return -EINVAL; 1712 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1713 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6); 1714 if (tuple == 4) 1715 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1716 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6; 1717 } else if (tuple == 4) { 1718 return -EINVAL; 1719 } 1720 1721 switch (cmd->flow_type) { 1722 case TCP_V4_FLOW: 1723 case UDP_V4_FLOW: 1724 case SCTP_V4_FLOW: 1725 case AH_ESP_V4_FLOW: 1726 case AH_V4_FLOW: 1727 case ESP_V4_FLOW: 1728 case IPV4_FLOW: 1729 if (tuple == 2) 1730 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1731 else if (!tuple) 1732 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1733 break; 1734 1735 case TCP_V6_FLOW: 1736 case UDP_V6_FLOW: 1737 case SCTP_V6_FLOW: 1738 case AH_ESP_V6_FLOW: 1739 case AH_V6_FLOW: 1740 case ESP_V6_FLOW: 1741 case IPV6_FLOW: 1742 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 | 1743 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL); 1744 if (!tuple) 1745 break; 1746 if (cmd->data & RXH_IP6_FL) 1747 rss_hash_cfg |= 1748 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL; 1749 else if (tuple == 2) 1750 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1751 break; 1752 } 1753 1754 if (bp->rss_hash_cfg == rss_hash_cfg) 1755 return 0; 1756 1757 if (bp->rss_cap & BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA) 1758 bp->rss_hash_delta = bp->rss_hash_cfg ^ rss_hash_cfg; 1759 bp->rss_hash_cfg = rss_hash_cfg; 1760 if (netif_running(bp->dev)) { 1761 bnxt_close_nic(bp, false, false); 1762 rc = bnxt_open_nic(bp, false, false); 1763 } 1764 return rc; 1765 } 1766 1767 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1768 u32 *rule_locs) 1769 { 1770 struct bnxt *bp = netdev_priv(dev); 1771 int rc = 0; 1772 1773 switch (cmd->cmd) { 1774 case ETHTOOL_GRXRINGS: 1775 cmd->data = bp->rx_nr_rings; 1776 break; 1777 1778 case ETHTOOL_GRXCLSRLCNT: 1779 cmd->rule_cnt = bp->ntp_fltr_count; 1780 cmd->data = bp->max_fltr | RX_CLS_LOC_SPECIAL; 1781 break; 1782 1783 case ETHTOOL_GRXCLSRLALL: 1784 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1785 break; 1786 1787 case ETHTOOL_GRXCLSRULE: 1788 rc = bnxt_grxclsrule(bp, cmd); 1789 break; 1790 1791 default: 1792 rc = -EOPNOTSUPP; 1793 break; 1794 } 1795 1796 return rc; 1797 } 1798 1799 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1800 { 1801 struct bnxt *bp = netdev_priv(dev); 1802 int rc; 1803 1804 switch (cmd->cmd) { 1805 case ETHTOOL_SRXCLSRLINS: 1806 rc = bnxt_srxclsrlins(bp, cmd); 1807 break; 1808 1809 case ETHTOOL_SRXCLSRLDEL: 1810 rc = bnxt_srxclsrldel(bp, cmd); 1811 break; 1812 1813 default: 1814 rc = -EOPNOTSUPP; 1815 break; 1816 } 1817 return rc; 1818 } 1819 1820 u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1821 { 1822 struct bnxt *bp = netdev_priv(dev); 1823 1824 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) 1825 return bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) * 1826 BNXT_RSS_TABLE_ENTRIES_P5; 1827 return HW_HASH_INDEX_SIZE; 1828 } 1829 1830 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1831 { 1832 return HW_HASH_KEY_SIZE; 1833 } 1834 1835 static int bnxt_get_rxfh(struct net_device *dev, 1836 struct ethtool_rxfh_param *rxfh) 1837 { 1838 struct bnxt_rss_ctx *rss_ctx = NULL; 1839 struct bnxt *bp = netdev_priv(dev); 1840 u32 *indir_tbl = bp->rss_indir_tbl; 1841 struct bnxt_vnic_info *vnic; 1842 u32 i, tbl_size; 1843 1844 rxfh->hfunc = ETH_RSS_HASH_TOP; 1845 1846 if (!bp->vnic_info) 1847 return 0; 1848 1849 vnic = &bp->vnic_info[BNXT_VNIC_DEFAULT]; 1850 if (rxfh->rss_context) { 1851 struct ethtool_rxfh_context *ctx; 1852 1853 ctx = xa_load(&bp->dev->ethtool->rss_ctx, rxfh->rss_context); 1854 if (!ctx) 1855 return -EINVAL; 1856 indir_tbl = ethtool_rxfh_context_indir(ctx); 1857 rss_ctx = ethtool_rxfh_context_priv(ctx); 1858 vnic = &rss_ctx->vnic; 1859 } 1860 1861 if (rxfh->indir && indir_tbl) { 1862 tbl_size = bnxt_get_rxfh_indir_size(dev); 1863 for (i = 0; i < tbl_size; i++) 1864 rxfh->indir[i] = indir_tbl[i]; 1865 } 1866 1867 if (rxfh->key && vnic->rss_hash_key) 1868 memcpy(rxfh->key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1869 1870 return 0; 1871 } 1872 1873 static void bnxt_modify_rss(struct bnxt *bp, struct ethtool_rxfh_context *ctx, 1874 struct bnxt_rss_ctx *rss_ctx, 1875 const struct ethtool_rxfh_param *rxfh) 1876 { 1877 if (rxfh->key) { 1878 if (rss_ctx) { 1879 memcpy(rss_ctx->vnic.rss_hash_key, rxfh->key, 1880 HW_HASH_KEY_SIZE); 1881 } else { 1882 memcpy(bp->rss_hash_key, rxfh->key, HW_HASH_KEY_SIZE); 1883 bp->rss_hash_key_updated = true; 1884 } 1885 } 1886 if (rxfh->indir) { 1887 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(bp->dev); 1888 u32 *indir_tbl = bp->rss_indir_tbl; 1889 1890 if (rss_ctx) 1891 indir_tbl = ethtool_rxfh_context_indir(ctx); 1892 for (i = 0; i < tbl_size; i++) 1893 indir_tbl[i] = rxfh->indir[i]; 1894 pad = bp->rss_indir_tbl_entries - tbl_size; 1895 if (pad) 1896 memset(&indir_tbl[i], 0, pad * sizeof(*indir_tbl)); 1897 } 1898 } 1899 1900 static int bnxt_rxfh_context_check(struct bnxt *bp, 1901 const struct ethtool_rxfh_param *rxfh, 1902 struct netlink_ext_ack *extack) 1903 { 1904 if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP) { 1905 NL_SET_ERR_MSG_MOD(extack, "RSS hash function not supported"); 1906 return -EOPNOTSUPP; 1907 } 1908 1909 if (!BNXT_SUPPORTS_MULTI_RSS_CTX(bp)) { 1910 NL_SET_ERR_MSG_MOD(extack, "RSS contexts not supported"); 1911 return -EOPNOTSUPP; 1912 } 1913 1914 if (!netif_running(bp->dev)) { 1915 NL_SET_ERR_MSG_MOD(extack, "Unable to set RSS contexts when interface is down"); 1916 return -EAGAIN; 1917 } 1918 1919 return 0; 1920 } 1921 1922 static int bnxt_create_rxfh_context(struct net_device *dev, 1923 struct ethtool_rxfh_context *ctx, 1924 const struct ethtool_rxfh_param *rxfh, 1925 struct netlink_ext_ack *extack) 1926 { 1927 struct bnxt *bp = netdev_priv(dev); 1928 struct bnxt_rss_ctx *rss_ctx; 1929 struct bnxt_vnic_info *vnic; 1930 int rc; 1931 1932 rc = bnxt_rxfh_context_check(bp, rxfh, extack); 1933 if (rc) 1934 return rc; 1935 1936 if (bp->num_rss_ctx >= BNXT_MAX_ETH_RSS_CTX) { 1937 NL_SET_ERR_MSG_FMT_MOD(extack, "Out of RSS contexts, maximum %u", 1938 BNXT_MAX_ETH_RSS_CTX); 1939 return -EINVAL; 1940 } 1941 1942 if (!bnxt_rfs_capable(bp, true)) { 1943 NL_SET_ERR_MSG_MOD(extack, "Out hardware resources"); 1944 return -ENOMEM; 1945 } 1946 1947 rss_ctx = ethtool_rxfh_context_priv(ctx); 1948 1949 bp->num_rss_ctx++; 1950 1951 vnic = &rss_ctx->vnic; 1952 vnic->rss_ctx = ctx; 1953 vnic->flags |= BNXT_VNIC_RSSCTX_FLAG; 1954 vnic->vnic_id = BNXT_VNIC_ID_INVALID; 1955 rc = bnxt_alloc_vnic_rss_table(bp, vnic); 1956 if (rc) 1957 goto out; 1958 1959 /* Populate defaults in the context */ 1960 bnxt_set_dflt_rss_indir_tbl(bp, ctx); 1961 ctx->hfunc = ETH_RSS_HASH_TOP; 1962 memcpy(vnic->rss_hash_key, bp->rss_hash_key, HW_HASH_KEY_SIZE); 1963 memcpy(ethtool_rxfh_context_key(ctx), 1964 bp->rss_hash_key, HW_HASH_KEY_SIZE); 1965 1966 rc = bnxt_hwrm_vnic_alloc(bp, vnic, 0, bp->rx_nr_rings); 1967 if (rc) { 1968 NL_SET_ERR_MSG_MOD(extack, "Unable to allocate VNIC"); 1969 goto out; 1970 } 1971 1972 rc = bnxt_hwrm_vnic_set_tpa(bp, vnic, bp->flags & BNXT_FLAG_TPA); 1973 if (rc) { 1974 NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA"); 1975 goto out; 1976 } 1977 bnxt_modify_rss(bp, ctx, rss_ctx, rxfh); 1978 1979 rc = __bnxt_setup_vnic_p5(bp, vnic); 1980 if (rc) { 1981 NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA"); 1982 goto out; 1983 } 1984 1985 rss_ctx->index = rxfh->rss_context; 1986 return 0; 1987 out: 1988 bnxt_del_one_rss_ctx(bp, rss_ctx, true); 1989 return rc; 1990 } 1991 1992 static int bnxt_modify_rxfh_context(struct net_device *dev, 1993 struct ethtool_rxfh_context *ctx, 1994 const struct ethtool_rxfh_param *rxfh, 1995 struct netlink_ext_ack *extack) 1996 { 1997 struct bnxt *bp = netdev_priv(dev); 1998 struct bnxt_rss_ctx *rss_ctx; 1999 int rc; 2000 2001 rc = bnxt_rxfh_context_check(bp, rxfh, extack); 2002 if (rc) 2003 return rc; 2004 2005 rss_ctx = ethtool_rxfh_context_priv(ctx); 2006 2007 bnxt_modify_rss(bp, ctx, rss_ctx, rxfh); 2008 2009 return bnxt_hwrm_vnic_rss_cfg_p5(bp, &rss_ctx->vnic); 2010 } 2011 2012 static int bnxt_remove_rxfh_context(struct net_device *dev, 2013 struct ethtool_rxfh_context *ctx, 2014 u32 rss_context, 2015 struct netlink_ext_ack *extack) 2016 { 2017 struct bnxt *bp = netdev_priv(dev); 2018 struct bnxt_rss_ctx *rss_ctx; 2019 2020 rss_ctx = ethtool_rxfh_context_priv(ctx); 2021 2022 bnxt_del_one_rss_ctx(bp, rss_ctx, true); 2023 return 0; 2024 } 2025 2026 static int bnxt_set_rxfh(struct net_device *dev, 2027 struct ethtool_rxfh_param *rxfh, 2028 struct netlink_ext_ack *extack) 2029 { 2030 struct bnxt *bp = netdev_priv(dev); 2031 int rc = 0; 2032 2033 if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP) 2034 return -EOPNOTSUPP; 2035 2036 bnxt_modify_rss(bp, NULL, NULL, rxfh); 2037 2038 if (netif_running(bp->dev)) { 2039 bnxt_close_nic(bp, false, false); 2040 rc = bnxt_open_nic(bp, false, false); 2041 } 2042 return rc; 2043 } 2044 2045 static void bnxt_get_drvinfo(struct net_device *dev, 2046 struct ethtool_drvinfo *info) 2047 { 2048 struct bnxt *bp = netdev_priv(dev); 2049 2050 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 2051 strscpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 2052 strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 2053 info->n_stats = bnxt_get_num_stats(bp); 2054 info->testinfo_len = bp->num_tests; 2055 /* TODO CHIMP_FW: eeprom dump details */ 2056 info->eedump_len = 0; 2057 /* TODO CHIMP FW: reg dump details */ 2058 info->regdump_len = 0; 2059 } 2060 2061 static int bnxt_get_regs_len(struct net_device *dev) 2062 { 2063 struct bnxt *bp = netdev_priv(dev); 2064 int reg_len; 2065 2066 if (!BNXT_PF(bp)) 2067 return -EOPNOTSUPP; 2068 2069 reg_len = BNXT_PXP_REG_LEN; 2070 2071 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED) 2072 reg_len += sizeof(struct pcie_ctx_hw_stats); 2073 2074 return reg_len; 2075 } 2076 2077 #define BNXT_PCIE_32B_ENTRY(start, end) \ 2078 { offsetof(struct pcie_ctx_hw_stats, start), \ 2079 offsetof(struct pcie_ctx_hw_stats, end) } 2080 2081 static const struct { 2082 u16 start; 2083 u16 end; 2084 } bnxt_pcie_32b_entries[] = { 2085 BNXT_PCIE_32B_ENTRY(pcie_ltssm_histogram[0], pcie_ltssm_histogram[3]), 2086 }; 2087 2088 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs, 2089 void *_p) 2090 { 2091 struct pcie_ctx_hw_stats *hw_pcie_stats; 2092 struct hwrm_pcie_qstats_input *req; 2093 struct bnxt *bp = netdev_priv(dev); 2094 dma_addr_t hw_pcie_stats_addr; 2095 int rc; 2096 2097 regs->version = 0; 2098 if (!(bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_REG_ACCESS_RESTRICTED)) 2099 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p); 2100 2101 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 2102 return; 2103 2104 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS)) 2105 return; 2106 2107 hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats), 2108 &hw_pcie_stats_addr); 2109 if (!hw_pcie_stats) { 2110 hwrm_req_drop(bp, req); 2111 return; 2112 } 2113 2114 regs->version = 1; 2115 hwrm_req_hold(bp, req); /* hold on to slice */ 2116 req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats)); 2117 req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr); 2118 rc = hwrm_req_send(bp, req); 2119 if (!rc) { 2120 u8 *dst = (u8 *)(_p + BNXT_PXP_REG_LEN); 2121 u8 *src = (u8 *)hw_pcie_stats; 2122 int i, j; 2123 2124 for (i = 0, j = 0; i < sizeof(*hw_pcie_stats); ) { 2125 if (i >= bnxt_pcie_32b_entries[j].start && 2126 i <= bnxt_pcie_32b_entries[j].end) { 2127 u32 *dst32 = (u32 *)(dst + i); 2128 2129 *dst32 = le32_to_cpu(*(__le32 *)(src + i)); 2130 i += 4; 2131 if (i > bnxt_pcie_32b_entries[j].end && 2132 j < ARRAY_SIZE(bnxt_pcie_32b_entries) - 1) 2133 j++; 2134 } else { 2135 u64 *dst64 = (u64 *)(dst + i); 2136 2137 *dst64 = le64_to_cpu(*(__le64 *)(src + i)); 2138 i += 8; 2139 } 2140 } 2141 } 2142 hwrm_req_drop(bp, req); 2143 } 2144 2145 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2146 { 2147 struct bnxt *bp = netdev_priv(dev); 2148 2149 wol->supported = 0; 2150 wol->wolopts = 0; 2151 memset(&wol->sopass, 0, sizeof(wol->sopass)); 2152 if (bp->flags & BNXT_FLAG_WOL_CAP) { 2153 wol->supported = WAKE_MAGIC; 2154 if (bp->wol) 2155 wol->wolopts = WAKE_MAGIC; 2156 } 2157 } 2158 2159 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2160 { 2161 struct bnxt *bp = netdev_priv(dev); 2162 2163 if (wol->wolopts & ~WAKE_MAGIC) 2164 return -EINVAL; 2165 2166 if (wol->wolopts & WAKE_MAGIC) { 2167 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 2168 return -EINVAL; 2169 if (!bp->wol) { 2170 if (bnxt_hwrm_alloc_wol_fltr(bp)) 2171 return -EBUSY; 2172 bp->wol = 1; 2173 } 2174 } else { 2175 if (bp->wol) { 2176 if (bnxt_hwrm_free_wol_fltr(bp)) 2177 return -EBUSY; 2178 bp->wol = 0; 2179 } 2180 } 2181 return 0; 2182 } 2183 2184 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 2185 void _bnxt_fw_to_linkmode(unsigned long *mode, u16 fw_speeds) 2186 { 2187 linkmode_zero(mode); 2188 2189 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 2190 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode); 2191 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 2192 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode); 2193 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 2194 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT, mode); 2195 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 2196 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode); 2197 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 2198 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode); 2199 } 2200 2201 enum bnxt_media_type { 2202 BNXT_MEDIA_UNKNOWN = 0, 2203 BNXT_MEDIA_TP, 2204 BNXT_MEDIA_CR, 2205 BNXT_MEDIA_SR, 2206 BNXT_MEDIA_LR_ER_FR, 2207 BNXT_MEDIA_KR, 2208 BNXT_MEDIA_KX, 2209 BNXT_MEDIA_X, 2210 __BNXT_MEDIA_END, 2211 }; 2212 2213 static const enum bnxt_media_type bnxt_phy_types[] = { 2214 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR] = BNXT_MEDIA_CR, 2215 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4] = BNXT_MEDIA_KR, 2216 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR] = BNXT_MEDIA_LR_ER_FR, 2217 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR] = BNXT_MEDIA_SR, 2218 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2] = BNXT_MEDIA_KR, 2219 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX] = BNXT_MEDIA_KX, 2220 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR] = BNXT_MEDIA_KR, 2221 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASET] = BNXT_MEDIA_TP, 2222 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE] = BNXT_MEDIA_TP, 2223 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L] = BNXT_MEDIA_CR, 2224 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S] = BNXT_MEDIA_CR, 2225 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N] = BNXT_MEDIA_CR, 2226 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR] = BNXT_MEDIA_SR, 2227 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4] = BNXT_MEDIA_CR, 2228 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4] = BNXT_MEDIA_SR, 2229 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2230 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2231 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10] = BNXT_MEDIA_SR, 2232 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4] = BNXT_MEDIA_CR, 2233 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4] = BNXT_MEDIA_SR, 2234 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2235 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2236 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE] = BNXT_MEDIA_SR, 2237 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET] = BNXT_MEDIA_TP, 2238 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX] = BNXT_MEDIA_X, 2239 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX] = BNXT_MEDIA_X, 2240 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4] = BNXT_MEDIA_CR, 2241 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4] = BNXT_MEDIA_SR, 2242 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2243 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2244 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR] = BNXT_MEDIA_CR, 2245 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR] = BNXT_MEDIA_SR, 2246 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR] = BNXT_MEDIA_LR_ER_FR, 2247 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER] = BNXT_MEDIA_LR_ER_FR, 2248 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2] = BNXT_MEDIA_CR, 2249 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2] = BNXT_MEDIA_SR, 2250 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2] = BNXT_MEDIA_LR_ER_FR, 2251 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2] = BNXT_MEDIA_LR_ER_FR, 2252 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR] = BNXT_MEDIA_CR, 2253 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR] = BNXT_MEDIA_SR, 2254 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR] = BNXT_MEDIA_LR_ER_FR, 2255 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER] = BNXT_MEDIA_LR_ER_FR, 2256 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2] = BNXT_MEDIA_CR, 2257 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2] = BNXT_MEDIA_SR, 2258 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2] = BNXT_MEDIA_LR_ER_FR, 2259 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2] = BNXT_MEDIA_LR_ER_FR, 2260 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8] = BNXT_MEDIA_CR, 2261 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8] = BNXT_MEDIA_SR, 2262 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8] = BNXT_MEDIA_LR_ER_FR, 2263 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8] = BNXT_MEDIA_LR_ER_FR, 2264 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4] = BNXT_MEDIA_CR, 2265 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4] = BNXT_MEDIA_SR, 2266 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2267 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2268 }; 2269 2270 static enum bnxt_media_type 2271 bnxt_get_media(struct bnxt_link_info *link_info) 2272 { 2273 switch (link_info->media_type) { 2274 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP: 2275 return BNXT_MEDIA_TP; 2276 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC: 2277 return BNXT_MEDIA_CR; 2278 default: 2279 if (link_info->phy_type < ARRAY_SIZE(bnxt_phy_types)) 2280 return bnxt_phy_types[link_info->phy_type]; 2281 return BNXT_MEDIA_UNKNOWN; 2282 } 2283 } 2284 2285 enum bnxt_link_speed_indices { 2286 BNXT_LINK_SPEED_UNKNOWN = 0, 2287 BNXT_LINK_SPEED_100MB_IDX, 2288 BNXT_LINK_SPEED_1GB_IDX, 2289 BNXT_LINK_SPEED_10GB_IDX, 2290 BNXT_LINK_SPEED_25GB_IDX, 2291 BNXT_LINK_SPEED_40GB_IDX, 2292 BNXT_LINK_SPEED_50GB_IDX, 2293 BNXT_LINK_SPEED_100GB_IDX, 2294 BNXT_LINK_SPEED_200GB_IDX, 2295 BNXT_LINK_SPEED_400GB_IDX, 2296 __BNXT_LINK_SPEED_END 2297 }; 2298 2299 static enum bnxt_link_speed_indices bnxt_fw_speed_idx(u16 speed) 2300 { 2301 switch (speed) { 2302 case BNXT_LINK_SPEED_100MB: return BNXT_LINK_SPEED_100MB_IDX; 2303 case BNXT_LINK_SPEED_1GB: return BNXT_LINK_SPEED_1GB_IDX; 2304 case BNXT_LINK_SPEED_10GB: return BNXT_LINK_SPEED_10GB_IDX; 2305 case BNXT_LINK_SPEED_25GB: return BNXT_LINK_SPEED_25GB_IDX; 2306 case BNXT_LINK_SPEED_40GB: return BNXT_LINK_SPEED_40GB_IDX; 2307 case BNXT_LINK_SPEED_50GB: 2308 case BNXT_LINK_SPEED_50GB_PAM4: 2309 return BNXT_LINK_SPEED_50GB_IDX; 2310 case BNXT_LINK_SPEED_100GB: 2311 case BNXT_LINK_SPEED_100GB_PAM4: 2312 case BNXT_LINK_SPEED_100GB_PAM4_112: 2313 return BNXT_LINK_SPEED_100GB_IDX; 2314 case BNXT_LINK_SPEED_200GB: 2315 case BNXT_LINK_SPEED_200GB_PAM4: 2316 case BNXT_LINK_SPEED_200GB_PAM4_112: 2317 return BNXT_LINK_SPEED_200GB_IDX; 2318 case BNXT_LINK_SPEED_400GB: 2319 case BNXT_LINK_SPEED_400GB_PAM4: 2320 case BNXT_LINK_SPEED_400GB_PAM4_112: 2321 return BNXT_LINK_SPEED_400GB_IDX; 2322 default: return BNXT_LINK_SPEED_UNKNOWN; 2323 } 2324 } 2325 2326 static const enum ethtool_link_mode_bit_indices 2327 bnxt_link_modes[__BNXT_LINK_SPEED_END][BNXT_SIG_MODE_MAX][__BNXT_MEDIA_END] = { 2328 [BNXT_LINK_SPEED_100MB_IDX] = { 2329 { 2330 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_100baseT_Full_BIT, 2331 }, 2332 }, 2333 [BNXT_LINK_SPEED_1GB_IDX] = { 2334 { 2335 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 2336 /* historically baseT, but DAC is more correctly baseX */ 2337 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 2338 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2339 [BNXT_MEDIA_X] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 2340 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2341 }, 2342 }, 2343 [BNXT_LINK_SPEED_10GB_IDX] = { 2344 { 2345 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 2346 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 2347 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 2348 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 2349 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 2350 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 2351 }, 2352 }, 2353 [BNXT_LINK_SPEED_25GB_IDX] = { 2354 { 2355 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 2356 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 2357 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 2358 }, 2359 }, 2360 [BNXT_LINK_SPEED_40GB_IDX] = { 2361 { 2362 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 2363 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 2364 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 2365 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 2366 }, 2367 }, 2368 [BNXT_LINK_SPEED_50GB_IDX] = { 2369 [BNXT_SIG_MODE_NRZ] = { 2370 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 2371 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 2372 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 2373 }, 2374 [BNXT_SIG_MODE_PAM4] = { 2375 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 2376 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 2377 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 2378 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 2379 }, 2380 }, 2381 [BNXT_LINK_SPEED_100GB_IDX] = { 2382 [BNXT_SIG_MODE_NRZ] = { 2383 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 2384 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 2385 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 2386 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 2387 }, 2388 [BNXT_SIG_MODE_PAM4] = { 2389 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 2390 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 2391 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 2392 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 2393 }, 2394 [BNXT_SIG_MODE_PAM4_112] = { 2395 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR_Full_BIT, 2396 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR_Full_BIT, 2397 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR_Full_BIT, 2398 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT, 2399 }, 2400 }, 2401 [BNXT_LINK_SPEED_200GB_IDX] = { 2402 [BNXT_SIG_MODE_PAM4] = { 2403 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT, 2404 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 2405 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 2406 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 2407 }, 2408 [BNXT_SIG_MODE_PAM4_112] = { 2409 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT, 2410 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT, 2411 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT, 2412 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT, 2413 }, 2414 }, 2415 [BNXT_LINK_SPEED_400GB_IDX] = { 2416 [BNXT_SIG_MODE_PAM4] = { 2417 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT, 2418 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT, 2419 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT, 2420 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT, 2421 }, 2422 [BNXT_SIG_MODE_PAM4_112] = { 2423 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT, 2424 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT, 2425 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT, 2426 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT, 2427 }, 2428 }, 2429 }; 2430 2431 #define BNXT_LINK_MODE_UNKNOWN -1 2432 2433 static enum ethtool_link_mode_bit_indices 2434 bnxt_get_link_mode(struct bnxt_link_info *link_info) 2435 { 2436 enum ethtool_link_mode_bit_indices link_mode; 2437 enum bnxt_link_speed_indices speed; 2438 enum bnxt_media_type media; 2439 u8 sig_mode; 2440 2441 if (link_info->phy_link_status != BNXT_LINK_LINK) 2442 return BNXT_LINK_MODE_UNKNOWN; 2443 2444 media = bnxt_get_media(link_info); 2445 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 2446 speed = bnxt_fw_speed_idx(link_info->link_speed); 2447 sig_mode = link_info->active_fec_sig_mode & 2448 PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK; 2449 } else { 2450 speed = bnxt_fw_speed_idx(link_info->req_link_speed); 2451 sig_mode = link_info->req_signal_mode; 2452 } 2453 if (sig_mode >= BNXT_SIG_MODE_MAX) 2454 return BNXT_LINK_MODE_UNKNOWN; 2455 2456 /* Note ETHTOOL_LINK_MODE_10baseT_Half_BIT == 0 is a legal Linux 2457 * link mode, but since no such devices exist, the zeroes in the 2458 * map can be conveniently used to represent unknown link modes. 2459 */ 2460 link_mode = bnxt_link_modes[speed][sig_mode][media]; 2461 if (!link_mode) 2462 return BNXT_LINK_MODE_UNKNOWN; 2463 2464 switch (link_mode) { 2465 case ETHTOOL_LINK_MODE_100baseT_Full_BIT: 2466 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2467 link_mode = ETHTOOL_LINK_MODE_100baseT_Half_BIT; 2468 break; 2469 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT: 2470 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2471 link_mode = ETHTOOL_LINK_MODE_1000baseT_Half_BIT; 2472 break; 2473 default: 2474 break; 2475 } 2476 2477 return link_mode; 2478 } 2479 2480 static void bnxt_get_ethtool_modes(struct bnxt_link_info *link_info, 2481 struct ethtool_link_ksettings *lk_ksettings) 2482 { 2483 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2484 2485 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) { 2486 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2487 lk_ksettings->link_modes.supported); 2488 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2489 lk_ksettings->link_modes.supported); 2490 } 2491 2492 if (link_info->support_auto_speeds || link_info->support_auto_speeds2 || 2493 link_info->support_pam4_auto_speeds) 2494 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2495 lk_ksettings->link_modes.supported); 2496 2497 if (~link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 2498 return; 2499 2500 if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_RX) 2501 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2502 lk_ksettings->link_modes.advertising); 2503 if (hweight8(link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) == 1) 2504 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2505 lk_ksettings->link_modes.advertising); 2506 if (link_info->lp_pause & BNXT_LINK_PAUSE_RX) 2507 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2508 lk_ksettings->link_modes.lp_advertising); 2509 if (hweight8(link_info->lp_pause & BNXT_LINK_PAUSE_BOTH) == 1) 2510 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2511 lk_ksettings->link_modes.lp_advertising); 2512 } 2513 2514 static const u16 bnxt_nrz_speed_masks[] = { 2515 [BNXT_LINK_SPEED_100MB_IDX] = BNXT_LINK_SPEED_MSK_100MB, 2516 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEED_MSK_1GB, 2517 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEED_MSK_10GB, 2518 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEED_MSK_25GB, 2519 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEED_MSK_40GB, 2520 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEED_MSK_50GB, 2521 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEED_MSK_100GB, 2522 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2523 }; 2524 2525 static const u16 bnxt_pam4_speed_masks[] = { 2526 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_50GB, 2527 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_100GB, 2528 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_200GB, 2529 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2530 }; 2531 2532 static const u16 bnxt_nrz_speeds2_masks[] = { 2533 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEEDS2_MSK_1GB, 2534 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEEDS2_MSK_10GB, 2535 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEEDS2_MSK_25GB, 2536 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEEDS2_MSK_40GB, 2537 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB, 2538 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB, 2539 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2540 }; 2541 2542 static const u16 bnxt_pam4_speeds2_masks[] = { 2543 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB_PAM4, 2544 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4, 2545 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4, 2546 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4, 2547 }; 2548 2549 static const u16 bnxt_pam4_112_speeds2_masks[] = { 2550 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112, 2551 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112, 2552 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112, 2553 }; 2554 2555 static enum bnxt_link_speed_indices 2556 bnxt_encoding_speed_idx(u8 sig_mode, u16 phy_flags, u16 speed_msk) 2557 { 2558 const u16 *speeds; 2559 int idx, len; 2560 2561 switch (sig_mode) { 2562 case BNXT_SIG_MODE_NRZ: 2563 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2564 speeds = bnxt_nrz_speeds2_masks; 2565 len = ARRAY_SIZE(bnxt_nrz_speeds2_masks); 2566 } else { 2567 speeds = bnxt_nrz_speed_masks; 2568 len = ARRAY_SIZE(bnxt_nrz_speed_masks); 2569 } 2570 break; 2571 case BNXT_SIG_MODE_PAM4: 2572 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2573 speeds = bnxt_pam4_speeds2_masks; 2574 len = ARRAY_SIZE(bnxt_pam4_speeds2_masks); 2575 } else { 2576 speeds = bnxt_pam4_speed_masks; 2577 len = ARRAY_SIZE(bnxt_pam4_speed_masks); 2578 } 2579 break; 2580 case BNXT_SIG_MODE_PAM4_112: 2581 speeds = bnxt_pam4_112_speeds2_masks; 2582 len = ARRAY_SIZE(bnxt_pam4_112_speeds2_masks); 2583 break; 2584 default: 2585 return BNXT_LINK_SPEED_UNKNOWN; 2586 } 2587 2588 for (idx = 0; idx < len; idx++) { 2589 if (speeds[idx] == speed_msk) 2590 return idx; 2591 } 2592 2593 return BNXT_LINK_SPEED_UNKNOWN; 2594 } 2595 2596 #define BNXT_FW_SPEED_MSK_BITS 16 2597 2598 static void 2599 __bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media, 2600 u8 sig_mode, u16 phy_flags, unsigned long *et_mask) 2601 { 2602 enum ethtool_link_mode_bit_indices link_mode; 2603 enum bnxt_link_speed_indices speed; 2604 u8 bit; 2605 2606 for_each_set_bit(bit, &fw_mask, BNXT_FW_SPEED_MSK_BITS) { 2607 speed = bnxt_encoding_speed_idx(sig_mode, phy_flags, 1 << bit); 2608 if (!speed) 2609 continue; 2610 2611 link_mode = bnxt_link_modes[speed][sig_mode][media]; 2612 if (!link_mode) 2613 continue; 2614 2615 linkmode_set_bit(link_mode, et_mask); 2616 } 2617 } 2618 2619 static void 2620 bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media, 2621 u8 sig_mode, u16 phy_flags, unsigned long *et_mask) 2622 { 2623 if (media) { 2624 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags, 2625 et_mask); 2626 return; 2627 } 2628 2629 /* list speeds for all media if unknown */ 2630 for (media = 1; media < __BNXT_MEDIA_END; media++) 2631 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags, 2632 et_mask); 2633 } 2634 2635 static void 2636 bnxt_get_all_ethtool_support_speeds(struct bnxt_link_info *link_info, 2637 enum bnxt_media_type media, 2638 struct ethtool_link_ksettings *lk_ksettings) 2639 { 2640 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2641 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0; 2642 u16 phy_flags = bp->phy_flags; 2643 2644 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2645 sp_nrz = link_info->support_speeds2; 2646 sp_pam4 = link_info->support_speeds2; 2647 sp_pam4_112 = link_info->support_speeds2; 2648 } else { 2649 sp_nrz = link_info->support_speeds; 2650 sp_pam4 = link_info->support_pam4_speeds; 2651 } 2652 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags, 2653 lk_ksettings->link_modes.supported); 2654 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags, 2655 lk_ksettings->link_modes.supported); 2656 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112, 2657 phy_flags, lk_ksettings->link_modes.supported); 2658 } 2659 2660 static void 2661 bnxt_get_all_ethtool_adv_speeds(struct bnxt_link_info *link_info, 2662 enum bnxt_media_type media, 2663 struct ethtool_link_ksettings *lk_ksettings) 2664 { 2665 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2666 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0; 2667 u16 phy_flags = bp->phy_flags; 2668 2669 sp_nrz = link_info->advertising; 2670 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2671 sp_pam4 = link_info->advertising; 2672 sp_pam4_112 = link_info->advertising; 2673 } else { 2674 sp_pam4 = link_info->advertising_pam4; 2675 } 2676 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags, 2677 lk_ksettings->link_modes.advertising); 2678 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags, 2679 lk_ksettings->link_modes.advertising); 2680 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112, 2681 phy_flags, lk_ksettings->link_modes.advertising); 2682 } 2683 2684 static void 2685 bnxt_get_all_ethtool_lp_speeds(struct bnxt_link_info *link_info, 2686 enum bnxt_media_type media, 2687 struct ethtool_link_ksettings *lk_ksettings) 2688 { 2689 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2690 u16 phy_flags = bp->phy_flags; 2691 2692 bnxt_get_ethtool_speeds(link_info->lp_auto_link_speeds, media, 2693 BNXT_SIG_MODE_NRZ, phy_flags, 2694 lk_ksettings->link_modes.lp_advertising); 2695 bnxt_get_ethtool_speeds(link_info->lp_auto_pam4_link_speeds, media, 2696 BNXT_SIG_MODE_PAM4, phy_flags, 2697 lk_ksettings->link_modes.lp_advertising); 2698 } 2699 2700 static void bnxt_update_speed(u32 *delta, bool installed_media, u16 *speeds, 2701 u16 speed_msk, const unsigned long *et_mask, 2702 enum ethtool_link_mode_bit_indices mode) 2703 { 2704 bool mode_desired = linkmode_test_bit(mode, et_mask); 2705 2706 if (!mode) 2707 return; 2708 2709 /* enabled speeds for installed media should override */ 2710 if (installed_media && mode_desired) { 2711 *speeds |= speed_msk; 2712 *delta |= speed_msk; 2713 return; 2714 } 2715 2716 /* many to one mapping, only allow one change per fw_speed bit */ 2717 if (!(*delta & speed_msk) && (mode_desired == !(*speeds & speed_msk))) { 2718 *speeds ^= speed_msk; 2719 *delta |= speed_msk; 2720 } 2721 } 2722 2723 static void bnxt_set_ethtool_speeds(struct bnxt_link_info *link_info, 2724 const unsigned long *et_mask) 2725 { 2726 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2727 u16 const *sp_msks, *sp_pam4_msks, *sp_pam4_112_msks; 2728 enum bnxt_media_type media = bnxt_get_media(link_info); 2729 u16 *adv, *adv_pam4, *adv_pam4_112 = NULL; 2730 u32 delta_pam4_112 = 0; 2731 u32 delta_pam4 = 0; 2732 u32 delta_nrz = 0; 2733 int i, m; 2734 2735 adv = &link_info->advertising; 2736 if (bp->phy_flags & BNXT_PHY_FL_SPEEDS2) { 2737 adv_pam4 = &link_info->advertising; 2738 adv_pam4_112 = &link_info->advertising; 2739 sp_msks = bnxt_nrz_speeds2_masks; 2740 sp_pam4_msks = bnxt_pam4_speeds2_masks; 2741 sp_pam4_112_msks = bnxt_pam4_112_speeds2_masks; 2742 } else { 2743 adv_pam4 = &link_info->advertising_pam4; 2744 sp_msks = bnxt_nrz_speed_masks; 2745 sp_pam4_msks = bnxt_pam4_speed_masks; 2746 } 2747 for (i = 1; i < __BNXT_LINK_SPEED_END; i++) { 2748 /* accept any legal media from user */ 2749 for (m = 1; m < __BNXT_MEDIA_END; m++) { 2750 bnxt_update_speed(&delta_nrz, m == media, 2751 adv, sp_msks[i], et_mask, 2752 bnxt_link_modes[i][BNXT_SIG_MODE_NRZ][m]); 2753 bnxt_update_speed(&delta_pam4, m == media, 2754 adv_pam4, sp_pam4_msks[i], et_mask, 2755 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4][m]); 2756 if (!adv_pam4_112) 2757 continue; 2758 2759 bnxt_update_speed(&delta_pam4_112, m == media, 2760 adv_pam4_112, sp_pam4_112_msks[i], et_mask, 2761 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4_112][m]); 2762 } 2763 } 2764 } 2765 2766 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info, 2767 struct ethtool_link_ksettings *lk_ksettings) 2768 { 2769 u16 fec_cfg = link_info->fec_cfg; 2770 2771 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) { 2772 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 2773 lk_ksettings->link_modes.advertising); 2774 return; 2775 } 2776 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 2777 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 2778 lk_ksettings->link_modes.advertising); 2779 if (fec_cfg & BNXT_FEC_ENC_RS) 2780 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 2781 lk_ksettings->link_modes.advertising); 2782 if (fec_cfg & BNXT_FEC_ENC_LLRS) 2783 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 2784 lk_ksettings->link_modes.advertising); 2785 } 2786 2787 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info, 2788 struct ethtool_link_ksettings *lk_ksettings) 2789 { 2790 u16 fec_cfg = link_info->fec_cfg; 2791 2792 if (fec_cfg & BNXT_FEC_NONE) { 2793 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 2794 lk_ksettings->link_modes.supported); 2795 return; 2796 } 2797 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP) 2798 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 2799 lk_ksettings->link_modes.supported); 2800 if (fec_cfg & BNXT_FEC_ENC_RS_CAP) 2801 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 2802 lk_ksettings->link_modes.supported); 2803 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP) 2804 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 2805 lk_ksettings->link_modes.supported); 2806 } 2807 2808 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 2809 { 2810 switch (fw_link_speed) { 2811 case BNXT_LINK_SPEED_100MB: 2812 return SPEED_100; 2813 case BNXT_LINK_SPEED_1GB: 2814 return SPEED_1000; 2815 case BNXT_LINK_SPEED_2_5GB: 2816 return SPEED_2500; 2817 case BNXT_LINK_SPEED_10GB: 2818 return SPEED_10000; 2819 case BNXT_LINK_SPEED_20GB: 2820 return SPEED_20000; 2821 case BNXT_LINK_SPEED_25GB: 2822 return SPEED_25000; 2823 case BNXT_LINK_SPEED_40GB: 2824 return SPEED_40000; 2825 case BNXT_LINK_SPEED_50GB: 2826 case BNXT_LINK_SPEED_50GB_PAM4: 2827 return SPEED_50000; 2828 case BNXT_LINK_SPEED_100GB: 2829 case BNXT_LINK_SPEED_100GB_PAM4: 2830 case BNXT_LINK_SPEED_100GB_PAM4_112: 2831 return SPEED_100000; 2832 case BNXT_LINK_SPEED_200GB: 2833 case BNXT_LINK_SPEED_200GB_PAM4: 2834 case BNXT_LINK_SPEED_200GB_PAM4_112: 2835 return SPEED_200000; 2836 case BNXT_LINK_SPEED_400GB: 2837 case BNXT_LINK_SPEED_400GB_PAM4: 2838 case BNXT_LINK_SPEED_400GB_PAM4_112: 2839 return SPEED_400000; 2840 default: 2841 return SPEED_UNKNOWN; 2842 } 2843 } 2844 2845 static void bnxt_get_default_speeds(struct ethtool_link_ksettings *lk_ksettings, 2846 struct bnxt_link_info *link_info) 2847 { 2848 struct ethtool_link_settings *base = &lk_ksettings->base; 2849 2850 if (link_info->link_state == BNXT_LINK_STATE_UP) { 2851 base->speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 2852 base->duplex = DUPLEX_HALF; 2853 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2854 base->duplex = DUPLEX_FULL; 2855 lk_ksettings->lanes = link_info->active_lanes; 2856 } else if (!link_info->autoneg) { 2857 base->speed = bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 2858 base->duplex = DUPLEX_HALF; 2859 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 2860 base->duplex = DUPLEX_FULL; 2861 } 2862 } 2863 2864 static int bnxt_get_link_ksettings(struct net_device *dev, 2865 struct ethtool_link_ksettings *lk_ksettings) 2866 { 2867 struct ethtool_link_settings *base = &lk_ksettings->base; 2868 enum ethtool_link_mode_bit_indices link_mode; 2869 struct bnxt *bp = netdev_priv(dev); 2870 struct bnxt_link_info *link_info; 2871 enum bnxt_media_type media; 2872 2873 ethtool_link_ksettings_zero_link_mode(lk_ksettings, lp_advertising); 2874 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 2875 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 2876 base->duplex = DUPLEX_UNKNOWN; 2877 base->speed = SPEED_UNKNOWN; 2878 link_info = &bp->link_info; 2879 2880 mutex_lock(&bp->link_lock); 2881 bnxt_get_ethtool_modes(link_info, lk_ksettings); 2882 media = bnxt_get_media(link_info); 2883 bnxt_get_all_ethtool_support_speeds(link_info, media, lk_ksettings); 2884 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings); 2885 link_mode = bnxt_get_link_mode(link_info); 2886 if (link_mode != BNXT_LINK_MODE_UNKNOWN) 2887 ethtool_params_from_link_mode(lk_ksettings, link_mode); 2888 else 2889 bnxt_get_default_speeds(lk_ksettings, link_info); 2890 2891 if (link_info->autoneg) { 2892 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings); 2893 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2894 lk_ksettings->link_modes.advertising); 2895 base->autoneg = AUTONEG_ENABLE; 2896 bnxt_get_all_ethtool_adv_speeds(link_info, media, lk_ksettings); 2897 if (link_info->phy_link_status == BNXT_LINK_LINK) 2898 bnxt_get_all_ethtool_lp_speeds(link_info, media, 2899 lk_ksettings); 2900 } else { 2901 base->autoneg = AUTONEG_DISABLE; 2902 } 2903 2904 base->port = PORT_NONE; 2905 if (media == BNXT_MEDIA_TP) { 2906 base->port = PORT_TP; 2907 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2908 lk_ksettings->link_modes.supported); 2909 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2910 lk_ksettings->link_modes.advertising); 2911 } else if (media == BNXT_MEDIA_KR) { 2912 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, 2913 lk_ksettings->link_modes.supported); 2914 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, 2915 lk_ksettings->link_modes.advertising); 2916 } else { 2917 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 2918 lk_ksettings->link_modes.supported); 2919 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 2920 lk_ksettings->link_modes.advertising); 2921 2922 if (media == BNXT_MEDIA_CR) 2923 base->port = PORT_DA; 2924 else 2925 base->port = PORT_FIBRE; 2926 } 2927 base->phy_address = link_info->phy_addr; 2928 mutex_unlock(&bp->link_lock); 2929 2930 return 0; 2931 } 2932 2933 static int 2934 bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed, u32 lanes) 2935 { 2936 struct bnxt *bp = netdev_priv(dev); 2937 struct bnxt_link_info *link_info = &bp->link_info; 2938 u16 support_pam4_spds = link_info->support_pam4_speeds; 2939 u16 support_spds2 = link_info->support_speeds2; 2940 u16 support_spds = link_info->support_speeds; 2941 u8 sig_mode = BNXT_SIG_MODE_NRZ; 2942 u32 lanes_needed = 1; 2943 u16 fw_speed = 0; 2944 2945 switch (ethtool_speed) { 2946 case SPEED_100: 2947 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 2948 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB; 2949 break; 2950 case SPEED_1000: 2951 if ((support_spds & BNXT_LINK_SPEED_MSK_1GB) || 2952 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_1GB)) 2953 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 2954 break; 2955 case SPEED_2500: 2956 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 2957 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB; 2958 break; 2959 case SPEED_10000: 2960 if ((support_spds & BNXT_LINK_SPEED_MSK_10GB) || 2961 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_10GB)) 2962 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 2963 break; 2964 case SPEED_20000: 2965 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) { 2966 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB; 2967 lanes_needed = 2; 2968 } 2969 break; 2970 case SPEED_25000: 2971 if ((support_spds & BNXT_LINK_SPEED_MSK_25GB) || 2972 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_25GB)) 2973 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 2974 break; 2975 case SPEED_40000: 2976 if ((support_spds & BNXT_LINK_SPEED_MSK_40GB) || 2977 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_40GB)) { 2978 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 2979 lanes_needed = 4; 2980 } 2981 break; 2982 case SPEED_50000: 2983 if (((support_spds & BNXT_LINK_SPEED_MSK_50GB) || 2984 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB)) && 2985 lanes != 1) { 2986 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 2987 lanes_needed = 2; 2988 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) { 2989 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB; 2990 sig_mode = BNXT_SIG_MODE_PAM4; 2991 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB_PAM4) { 2992 fw_speed = BNXT_LINK_SPEED_50GB_PAM4; 2993 sig_mode = BNXT_SIG_MODE_PAM4; 2994 } 2995 break; 2996 case SPEED_100000: 2997 if (((support_spds & BNXT_LINK_SPEED_MSK_100GB) || 2998 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB)) && 2999 lanes != 2 && lanes != 1) { 3000 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB; 3001 lanes_needed = 4; 3002 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) { 3003 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB; 3004 sig_mode = BNXT_SIG_MODE_PAM4; 3005 lanes_needed = 2; 3006 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4) && 3007 lanes != 1) { 3008 fw_speed = BNXT_LINK_SPEED_100GB_PAM4; 3009 sig_mode = BNXT_SIG_MODE_PAM4; 3010 lanes_needed = 2; 3011 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112) { 3012 fw_speed = BNXT_LINK_SPEED_100GB_PAM4_112; 3013 sig_mode = BNXT_SIG_MODE_PAM4_112; 3014 } 3015 break; 3016 case SPEED_200000: 3017 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) { 3018 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB; 3019 sig_mode = BNXT_SIG_MODE_PAM4; 3020 lanes_needed = 4; 3021 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4) && 3022 lanes != 2) { 3023 fw_speed = BNXT_LINK_SPEED_200GB_PAM4; 3024 sig_mode = BNXT_SIG_MODE_PAM4; 3025 lanes_needed = 4; 3026 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112) { 3027 fw_speed = BNXT_LINK_SPEED_200GB_PAM4_112; 3028 sig_mode = BNXT_SIG_MODE_PAM4_112; 3029 lanes_needed = 2; 3030 } 3031 break; 3032 case SPEED_400000: 3033 if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4) && 3034 lanes != 4) { 3035 fw_speed = BNXT_LINK_SPEED_400GB_PAM4; 3036 sig_mode = BNXT_SIG_MODE_PAM4; 3037 lanes_needed = 8; 3038 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112) { 3039 fw_speed = BNXT_LINK_SPEED_400GB_PAM4_112; 3040 sig_mode = BNXT_SIG_MODE_PAM4_112; 3041 lanes_needed = 4; 3042 } 3043 break; 3044 } 3045 3046 if (!fw_speed) { 3047 netdev_err(dev, "unsupported speed!\n"); 3048 return -EINVAL; 3049 } 3050 3051 if (lanes && lanes != lanes_needed) { 3052 netdev_err(dev, "unsupported number of lanes for speed\n"); 3053 return -EINVAL; 3054 } 3055 3056 if (link_info->req_link_speed == fw_speed && 3057 link_info->req_signal_mode == sig_mode && 3058 link_info->autoneg == 0) 3059 return -EALREADY; 3060 3061 link_info->req_link_speed = fw_speed; 3062 link_info->req_signal_mode = sig_mode; 3063 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 3064 link_info->autoneg = 0; 3065 link_info->advertising = 0; 3066 link_info->advertising_pam4 = 0; 3067 3068 return 0; 3069 } 3070 3071 u16 bnxt_get_fw_auto_link_speeds(const unsigned long *mode) 3072 { 3073 u16 fw_speed_mask = 0; 3074 3075 if (linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode) || 3076 linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mode)) 3077 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 3078 3079 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode) || 3080 linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, mode)) 3081 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 3082 3083 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode)) 3084 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 3085 3086 if (linkmode_test_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode)) 3087 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 3088 3089 return fw_speed_mask; 3090 } 3091 3092 static int bnxt_set_link_ksettings(struct net_device *dev, 3093 const struct ethtool_link_ksettings *lk_ksettings) 3094 { 3095 struct bnxt *bp = netdev_priv(dev); 3096 struct bnxt_link_info *link_info = &bp->link_info; 3097 const struct ethtool_link_settings *base = &lk_ksettings->base; 3098 bool set_pause = false; 3099 u32 speed, lanes = 0; 3100 int rc = 0; 3101 3102 if (!BNXT_PHY_CFG_ABLE(bp)) 3103 return -EOPNOTSUPP; 3104 3105 mutex_lock(&bp->link_lock); 3106 if (base->autoneg == AUTONEG_ENABLE) { 3107 bnxt_set_ethtool_speeds(link_info, 3108 lk_ksettings->link_modes.advertising); 3109 link_info->autoneg |= BNXT_AUTONEG_SPEED; 3110 if (!link_info->advertising && !link_info->advertising_pam4) { 3111 link_info->advertising = link_info->support_auto_speeds; 3112 link_info->advertising_pam4 = 3113 link_info->support_pam4_auto_speeds; 3114 } 3115 /* any change to autoneg will cause link change, therefore the 3116 * driver should put back the original pause setting in autoneg 3117 */ 3118 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 3119 set_pause = true; 3120 } else { 3121 u8 phy_type = link_info->phy_type; 3122 3123 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 3124 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 3125 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 3126 netdev_err(dev, "10GBase-T devices must autoneg\n"); 3127 rc = -EINVAL; 3128 goto set_setting_exit; 3129 } 3130 if (base->duplex == DUPLEX_HALF) { 3131 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 3132 rc = -EINVAL; 3133 goto set_setting_exit; 3134 } 3135 speed = base->speed; 3136 lanes = lk_ksettings->lanes; 3137 rc = bnxt_force_link_speed(dev, speed, lanes); 3138 if (rc) { 3139 if (rc == -EALREADY) 3140 rc = 0; 3141 goto set_setting_exit; 3142 } 3143 } 3144 3145 if (netif_running(dev)) 3146 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 3147 3148 set_setting_exit: 3149 mutex_unlock(&bp->link_lock); 3150 return rc; 3151 } 3152 3153 static int bnxt_get_fecparam(struct net_device *dev, 3154 struct ethtool_fecparam *fec) 3155 { 3156 struct bnxt *bp = netdev_priv(dev); 3157 struct bnxt_link_info *link_info; 3158 u8 active_fec; 3159 u16 fec_cfg; 3160 3161 link_info = &bp->link_info; 3162 fec_cfg = link_info->fec_cfg; 3163 active_fec = link_info->active_fec_sig_mode & 3164 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK; 3165 if (fec_cfg & BNXT_FEC_NONE) { 3166 fec->fec = ETHTOOL_FEC_NONE; 3167 fec->active_fec = ETHTOOL_FEC_NONE; 3168 return 0; 3169 } 3170 if (fec_cfg & BNXT_FEC_AUTONEG) 3171 fec->fec |= ETHTOOL_FEC_AUTO; 3172 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 3173 fec->fec |= ETHTOOL_FEC_BASER; 3174 if (fec_cfg & BNXT_FEC_ENC_RS) 3175 fec->fec |= ETHTOOL_FEC_RS; 3176 if (fec_cfg & BNXT_FEC_ENC_LLRS) 3177 fec->fec |= ETHTOOL_FEC_LLRS; 3178 3179 switch (active_fec) { 3180 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE: 3181 fec->active_fec |= ETHTOOL_FEC_BASER; 3182 break; 3183 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE: 3184 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE: 3185 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE: 3186 fec->active_fec |= ETHTOOL_FEC_RS; 3187 break; 3188 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE: 3189 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE: 3190 fec->active_fec |= ETHTOOL_FEC_LLRS; 3191 break; 3192 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE: 3193 fec->active_fec |= ETHTOOL_FEC_OFF; 3194 break; 3195 } 3196 return 0; 3197 } 3198 3199 static void bnxt_get_fec_stats(struct net_device *dev, 3200 struct ethtool_fec_stats *fec_stats) 3201 { 3202 struct bnxt *bp = netdev_priv(dev); 3203 u64 *rx; 3204 3205 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 3206 return; 3207 3208 rx = bp->rx_port_stats_ext.sw_stats; 3209 fec_stats->corrected_bits.total = 3210 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits)); 3211 3212 if (bp->fw_rx_stats_ext_size <= BNXT_RX_STATS_EXT_NUM_LEGACY) 3213 return; 3214 3215 fec_stats->corrected_blocks.total = 3216 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)); 3217 fec_stats->uncorrectable_blocks.total = 3218 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_uncorrectable_blocks)); 3219 } 3220 3221 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info, 3222 u32 fec) 3223 { 3224 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE; 3225 3226 if (fec & ETHTOOL_FEC_BASER) 3227 fw_fec |= BNXT_FEC_BASE_R_ON(link_info); 3228 else if (fec & ETHTOOL_FEC_RS) 3229 fw_fec |= BNXT_FEC_RS_ON(link_info); 3230 else if (fec & ETHTOOL_FEC_LLRS) 3231 fw_fec |= BNXT_FEC_LLRS_ON; 3232 return fw_fec; 3233 } 3234 3235 static int bnxt_set_fecparam(struct net_device *dev, 3236 struct ethtool_fecparam *fecparam) 3237 { 3238 struct hwrm_port_phy_cfg_input *req; 3239 struct bnxt *bp = netdev_priv(dev); 3240 struct bnxt_link_info *link_info; 3241 u32 new_cfg, fec = fecparam->fec; 3242 u16 fec_cfg; 3243 int rc; 3244 3245 link_info = &bp->link_info; 3246 fec_cfg = link_info->fec_cfg; 3247 if (fec_cfg & BNXT_FEC_NONE) 3248 return -EOPNOTSUPP; 3249 3250 if (fec & ETHTOOL_FEC_OFF) { 3251 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE | 3252 BNXT_FEC_ALL_OFF(link_info); 3253 goto apply_fec; 3254 } 3255 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) || 3256 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) || 3257 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) || 3258 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP))) 3259 return -EINVAL; 3260 3261 if (fec & ETHTOOL_FEC_AUTO) { 3262 if (!link_info->autoneg) 3263 return -EINVAL; 3264 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE; 3265 } else { 3266 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec); 3267 } 3268 3269 apply_fec: 3270 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 3271 if (rc) 3272 return rc; 3273 req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 3274 rc = hwrm_req_send(bp, req); 3275 /* update current settings */ 3276 if (!rc) { 3277 mutex_lock(&bp->link_lock); 3278 bnxt_update_link(bp, false); 3279 mutex_unlock(&bp->link_lock); 3280 } 3281 return rc; 3282 } 3283 3284 static void bnxt_get_pauseparam(struct net_device *dev, 3285 struct ethtool_pauseparam *epause) 3286 { 3287 struct bnxt *bp = netdev_priv(dev); 3288 struct bnxt_link_info *link_info = &bp->link_info; 3289 3290 if (BNXT_VF(bp)) 3291 return; 3292 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 3293 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 3294 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 3295 } 3296 3297 static void bnxt_get_pause_stats(struct net_device *dev, 3298 struct ethtool_pause_stats *epstat) 3299 { 3300 struct bnxt *bp = netdev_priv(dev); 3301 u64 *rx, *tx; 3302 3303 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 3304 return; 3305 3306 rx = bp->port_stats.sw_stats; 3307 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 3308 3309 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames); 3310 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames); 3311 } 3312 3313 static int bnxt_set_pauseparam(struct net_device *dev, 3314 struct ethtool_pauseparam *epause) 3315 { 3316 int rc = 0; 3317 struct bnxt *bp = netdev_priv(dev); 3318 struct bnxt_link_info *link_info = &bp->link_info; 3319 3320 if (!BNXT_PHY_CFG_ABLE(bp) || (bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 3321 return -EOPNOTSUPP; 3322 3323 mutex_lock(&bp->link_lock); 3324 if (epause->autoneg) { 3325 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 3326 rc = -EINVAL; 3327 goto pause_exit; 3328 } 3329 3330 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 3331 link_info->req_flow_ctrl = 0; 3332 } else { 3333 /* when transition from auto pause to force pause, 3334 * force a link change 3335 */ 3336 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 3337 link_info->force_link_chng = true; 3338 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 3339 link_info->req_flow_ctrl = 0; 3340 } 3341 if (epause->rx_pause) 3342 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 3343 3344 if (epause->tx_pause) 3345 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 3346 3347 if (netif_running(dev)) 3348 rc = bnxt_hwrm_set_pause(bp); 3349 3350 pause_exit: 3351 mutex_unlock(&bp->link_lock); 3352 return rc; 3353 } 3354 3355 static u32 bnxt_get_link(struct net_device *dev) 3356 { 3357 struct bnxt *bp = netdev_priv(dev); 3358 3359 /* TODO: handle MF, VF, driver close case */ 3360 return BNXT_LINK_IS_UP(bp); 3361 } 3362 3363 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp, 3364 struct hwrm_nvm_get_dev_info_output *nvm_dev_info) 3365 { 3366 struct hwrm_nvm_get_dev_info_output *resp; 3367 struct hwrm_nvm_get_dev_info_input *req; 3368 int rc; 3369 3370 if (BNXT_VF(bp)) 3371 return -EOPNOTSUPP; 3372 3373 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO); 3374 if (rc) 3375 return rc; 3376 3377 resp = hwrm_req_hold(bp, req); 3378 rc = hwrm_req_send(bp, req); 3379 if (!rc) 3380 memcpy(nvm_dev_info, resp, sizeof(*resp)); 3381 hwrm_req_drop(bp, req); 3382 return rc; 3383 } 3384 3385 static void bnxt_print_admin_err(struct bnxt *bp) 3386 { 3387 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 3388 } 3389 3390 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 3391 u16 ext, u16 *index, u32 *item_length, 3392 u32 *data_length); 3393 3394 int bnxt_flash_nvram(struct net_device *dev, u16 dir_type, 3395 u16 dir_ordinal, u16 dir_ext, u16 dir_attr, 3396 u32 dir_item_len, const u8 *data, 3397 size_t data_len) 3398 { 3399 struct bnxt *bp = netdev_priv(dev); 3400 struct hwrm_nvm_write_input *req; 3401 int rc; 3402 3403 rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE); 3404 if (rc) 3405 return rc; 3406 3407 if (data_len && data) { 3408 dma_addr_t dma_handle; 3409 u8 *kmem; 3410 3411 kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle); 3412 if (!kmem) { 3413 hwrm_req_drop(bp, req); 3414 return -ENOMEM; 3415 } 3416 3417 req->dir_data_length = cpu_to_le32(data_len); 3418 3419 memcpy(kmem, data, data_len); 3420 req->host_src_addr = cpu_to_le64(dma_handle); 3421 } 3422 3423 hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout); 3424 req->dir_type = cpu_to_le16(dir_type); 3425 req->dir_ordinal = cpu_to_le16(dir_ordinal); 3426 req->dir_ext = cpu_to_le16(dir_ext); 3427 req->dir_attr = cpu_to_le16(dir_attr); 3428 req->dir_item_length = cpu_to_le32(dir_item_len); 3429 rc = hwrm_req_send(bp, req); 3430 3431 if (rc == -EACCES) 3432 bnxt_print_admin_err(bp); 3433 return rc; 3434 } 3435 3436 int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type, 3437 u8 self_reset, u8 flags) 3438 { 3439 struct bnxt *bp = netdev_priv(dev); 3440 struct hwrm_fw_reset_input *req; 3441 int rc; 3442 3443 if (!bnxt_hwrm_reset_permitted(bp)) { 3444 netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver"); 3445 return -EPERM; 3446 } 3447 3448 rc = hwrm_req_init(bp, req, HWRM_FW_RESET); 3449 if (rc) 3450 return rc; 3451 3452 req->embedded_proc_type = proc_type; 3453 req->selfrst_status = self_reset; 3454 req->flags = flags; 3455 3456 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) { 3457 rc = hwrm_req_send_silent(bp, req); 3458 } else { 3459 rc = hwrm_req_send(bp, req); 3460 if (rc == -EACCES) 3461 bnxt_print_admin_err(bp); 3462 } 3463 return rc; 3464 } 3465 3466 static int bnxt_firmware_reset(struct net_device *dev, 3467 enum bnxt_nvm_directory_type dir_type) 3468 { 3469 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE; 3470 u8 proc_type, flags = 0; 3471 3472 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 3473 /* (e.g. when firmware isn't already running) */ 3474 switch (dir_type) { 3475 case BNX_DIR_TYPE_CHIMP_PATCH: 3476 case BNX_DIR_TYPE_BOOTCODE: 3477 case BNX_DIR_TYPE_BOOTCODE_2: 3478 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 3479 /* Self-reset ChiMP upon next PCIe reset: */ 3480 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 3481 break; 3482 case BNX_DIR_TYPE_APE_FW: 3483 case BNX_DIR_TYPE_APE_PATCH: 3484 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 3485 /* Self-reset APE upon next PCIe reset: */ 3486 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 3487 break; 3488 case BNX_DIR_TYPE_KONG_FW: 3489 case BNX_DIR_TYPE_KONG_PATCH: 3490 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 3491 break; 3492 case BNX_DIR_TYPE_BONO_FW: 3493 case BNX_DIR_TYPE_BONO_PATCH: 3494 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 3495 break; 3496 default: 3497 return -EINVAL; 3498 } 3499 3500 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags); 3501 } 3502 3503 static int bnxt_firmware_reset_chip(struct net_device *dev) 3504 { 3505 struct bnxt *bp = netdev_priv(dev); 3506 u8 flags = 0; 3507 3508 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 3509 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 3510 3511 return bnxt_hwrm_firmware_reset(dev, 3512 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP, 3513 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP, 3514 flags); 3515 } 3516 3517 static int bnxt_firmware_reset_ap(struct net_device *dev) 3518 { 3519 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP, 3520 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE, 3521 0); 3522 } 3523 3524 static int bnxt_flash_firmware(struct net_device *dev, 3525 u16 dir_type, 3526 const u8 *fw_data, 3527 size_t fw_size) 3528 { 3529 int rc = 0; 3530 u16 code_type; 3531 u32 stored_crc; 3532 u32 calculated_crc; 3533 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 3534 3535 switch (dir_type) { 3536 case BNX_DIR_TYPE_BOOTCODE: 3537 case BNX_DIR_TYPE_BOOTCODE_2: 3538 code_type = CODE_BOOT; 3539 break; 3540 case BNX_DIR_TYPE_CHIMP_PATCH: 3541 code_type = CODE_CHIMP_PATCH; 3542 break; 3543 case BNX_DIR_TYPE_APE_FW: 3544 code_type = CODE_MCTP_PASSTHRU; 3545 break; 3546 case BNX_DIR_TYPE_APE_PATCH: 3547 code_type = CODE_APE_PATCH; 3548 break; 3549 case BNX_DIR_TYPE_KONG_FW: 3550 code_type = CODE_KONG_FW; 3551 break; 3552 case BNX_DIR_TYPE_KONG_PATCH: 3553 code_type = CODE_KONG_PATCH; 3554 break; 3555 case BNX_DIR_TYPE_BONO_FW: 3556 code_type = CODE_BONO_FW; 3557 break; 3558 case BNX_DIR_TYPE_BONO_PATCH: 3559 code_type = CODE_BONO_PATCH; 3560 break; 3561 default: 3562 netdev_err(dev, "Unsupported directory entry type: %u\n", 3563 dir_type); 3564 return -EINVAL; 3565 } 3566 if (fw_size < sizeof(struct bnxt_fw_header)) { 3567 netdev_err(dev, "Invalid firmware file size: %u\n", 3568 (unsigned int)fw_size); 3569 return -EINVAL; 3570 } 3571 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 3572 netdev_err(dev, "Invalid firmware signature: %08X\n", 3573 le32_to_cpu(header->signature)); 3574 return -EINVAL; 3575 } 3576 if (header->code_type != code_type) { 3577 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 3578 code_type, header->code_type); 3579 return -EINVAL; 3580 } 3581 if (header->device != DEVICE_CUMULUS_FAMILY) { 3582 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 3583 DEVICE_CUMULUS_FAMILY, header->device); 3584 return -EINVAL; 3585 } 3586 /* Confirm the CRC32 checksum of the file: */ 3587 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 3588 sizeof(stored_crc))); 3589 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 3590 if (calculated_crc != stored_crc) { 3591 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 3592 (unsigned long)stored_crc, 3593 (unsigned long)calculated_crc); 3594 return -EINVAL; 3595 } 3596 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3597 0, 0, 0, fw_data, fw_size); 3598 if (rc == 0) /* Firmware update successful */ 3599 rc = bnxt_firmware_reset(dev, dir_type); 3600 3601 return rc; 3602 } 3603 3604 static int bnxt_flash_microcode(struct net_device *dev, 3605 u16 dir_type, 3606 const u8 *fw_data, 3607 size_t fw_size) 3608 { 3609 struct bnxt_ucode_trailer *trailer; 3610 u32 calculated_crc; 3611 u32 stored_crc; 3612 int rc = 0; 3613 3614 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 3615 netdev_err(dev, "Invalid microcode file size: %u\n", 3616 (unsigned int)fw_size); 3617 return -EINVAL; 3618 } 3619 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 3620 sizeof(*trailer))); 3621 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 3622 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 3623 le32_to_cpu(trailer->sig)); 3624 return -EINVAL; 3625 } 3626 if (le16_to_cpu(trailer->dir_type) != dir_type) { 3627 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 3628 dir_type, le16_to_cpu(trailer->dir_type)); 3629 return -EINVAL; 3630 } 3631 if (le16_to_cpu(trailer->trailer_length) < 3632 sizeof(struct bnxt_ucode_trailer)) { 3633 netdev_err(dev, "Invalid microcode trailer length: %d\n", 3634 le16_to_cpu(trailer->trailer_length)); 3635 return -EINVAL; 3636 } 3637 3638 /* Confirm the CRC32 checksum of the file: */ 3639 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 3640 sizeof(stored_crc))); 3641 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 3642 if (calculated_crc != stored_crc) { 3643 netdev_err(dev, 3644 "CRC32 (%08lX) does not match calculated: %08lX\n", 3645 (unsigned long)stored_crc, 3646 (unsigned long)calculated_crc); 3647 return -EINVAL; 3648 } 3649 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3650 0, 0, 0, fw_data, fw_size); 3651 3652 return rc; 3653 } 3654 3655 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 3656 { 3657 switch (dir_type) { 3658 case BNX_DIR_TYPE_CHIMP_PATCH: 3659 case BNX_DIR_TYPE_BOOTCODE: 3660 case BNX_DIR_TYPE_BOOTCODE_2: 3661 case BNX_DIR_TYPE_APE_FW: 3662 case BNX_DIR_TYPE_APE_PATCH: 3663 case BNX_DIR_TYPE_KONG_FW: 3664 case BNX_DIR_TYPE_KONG_PATCH: 3665 case BNX_DIR_TYPE_BONO_FW: 3666 case BNX_DIR_TYPE_BONO_PATCH: 3667 return true; 3668 } 3669 3670 return false; 3671 } 3672 3673 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 3674 { 3675 switch (dir_type) { 3676 case BNX_DIR_TYPE_AVS: 3677 case BNX_DIR_TYPE_EXP_ROM_MBA: 3678 case BNX_DIR_TYPE_PCIE: 3679 case BNX_DIR_TYPE_TSCF_UCODE: 3680 case BNX_DIR_TYPE_EXT_PHY: 3681 case BNX_DIR_TYPE_CCM: 3682 case BNX_DIR_TYPE_ISCSI_BOOT: 3683 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 3684 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 3685 return true; 3686 } 3687 3688 return false; 3689 } 3690 3691 static bool bnxt_dir_type_is_executable(u16 dir_type) 3692 { 3693 return bnxt_dir_type_is_ape_bin_format(dir_type) || 3694 bnxt_dir_type_is_other_exec_format(dir_type); 3695 } 3696 3697 static int bnxt_flash_firmware_from_file(struct net_device *dev, 3698 u16 dir_type, 3699 const char *filename) 3700 { 3701 const struct firmware *fw; 3702 int rc; 3703 3704 rc = request_firmware(&fw, filename, &dev->dev); 3705 if (rc != 0) { 3706 netdev_err(dev, "Error %d requesting firmware file: %s\n", 3707 rc, filename); 3708 return rc; 3709 } 3710 if (bnxt_dir_type_is_ape_bin_format(dir_type)) 3711 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 3712 else if (bnxt_dir_type_is_other_exec_format(dir_type)) 3713 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 3714 else 3715 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3716 0, 0, 0, fw->data, fw->size); 3717 release_firmware(fw); 3718 return rc; 3719 } 3720 3721 #define MSG_INTEGRITY_ERR "PKG install error : Data integrity on NVM" 3722 #define MSG_INVALID_PKG "PKG install error : Invalid package" 3723 #define MSG_AUTHENTICATION_ERR "PKG install error : Authentication error" 3724 #define MSG_INVALID_DEV "PKG install error : Invalid device" 3725 #define MSG_INTERNAL_ERR "PKG install error : Internal error" 3726 #define MSG_NO_PKG_UPDATE_AREA_ERR "PKG update area not created in nvram" 3727 #define MSG_NO_SPACE_ERR "PKG insufficient update area in nvram" 3728 #define MSG_RESIZE_UPDATE_ERR "Resize UPDATE entry error" 3729 #define MSG_ANTI_ROLLBACK_ERR "HWRM_NVM_INSTALL_UPDATE failure due to Anti-rollback detected" 3730 #define MSG_GENERIC_FAILURE_ERR "HWRM_NVM_INSTALL_UPDATE failure" 3731 3732 static int nvm_update_err_to_stderr(struct net_device *dev, u8 result, 3733 struct netlink_ext_ack *extack) 3734 { 3735 switch (result) { 3736 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER: 3737 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER: 3738 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR: 3739 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR: 3740 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND: 3741 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED: 3742 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTEGRITY_ERR); 3743 return -EINVAL; 3744 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE: 3745 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER: 3746 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE: 3747 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM: 3748 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH: 3749 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST: 3750 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER: 3751 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM: 3752 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM: 3753 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH: 3754 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE: 3755 case NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM: 3756 case NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM: 3757 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_PKG); 3758 return -ENOPKG; 3759 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR: 3760 BNXT_NVM_ERR_MSG(dev, extack, MSG_AUTHENTICATION_ERR); 3761 return -EPERM; 3762 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV: 3763 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID: 3764 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR: 3765 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID: 3766 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM: 3767 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_DEV); 3768 return -EOPNOTSUPP; 3769 default: 3770 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTERNAL_ERR); 3771 return -EIO; 3772 } 3773 } 3774 3775 #define BNXT_PKG_DMA_SIZE 0x40000 3776 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE)) 3777 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST)) 3778 3779 static int bnxt_resize_update_entry(struct net_device *dev, size_t fw_size, 3780 struct netlink_ext_ack *extack) 3781 { 3782 u32 item_len; 3783 int rc; 3784 3785 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 3786 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, NULL, 3787 &item_len, NULL); 3788 if (rc) { 3789 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 3790 return rc; 3791 } 3792 3793 if (fw_size > item_len) { 3794 rc = bnxt_flash_nvram(dev, BNX_DIR_TYPE_UPDATE, 3795 BNX_DIR_ORDINAL_FIRST, 0, 1, 3796 round_up(fw_size, 4096), NULL, 0); 3797 if (rc) { 3798 BNXT_NVM_ERR_MSG(dev, extack, MSG_RESIZE_UPDATE_ERR); 3799 return rc; 3800 } 3801 } 3802 return 0; 3803 } 3804 3805 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw, 3806 u32 install_type, struct netlink_ext_ack *extack) 3807 { 3808 struct hwrm_nvm_install_update_input *install; 3809 struct hwrm_nvm_install_update_output *resp; 3810 struct hwrm_nvm_modify_input *modify; 3811 struct bnxt *bp = netdev_priv(dev); 3812 bool defrag_attempted = false; 3813 dma_addr_t dma_handle; 3814 u8 *kmem = NULL; 3815 u32 modify_len; 3816 u32 item_len; 3817 u8 cmd_err; 3818 u16 index; 3819 int rc; 3820 3821 /* resize before flashing larger image than available space */ 3822 rc = bnxt_resize_update_entry(dev, fw->size, extack); 3823 if (rc) 3824 return rc; 3825 3826 bnxt_hwrm_fw_set_time(bp); 3827 3828 rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY); 3829 if (rc) 3830 return rc; 3831 3832 /* Try allocating a large DMA buffer first. Older fw will 3833 * cause excessive NVRAM erases when using small blocks. 3834 */ 3835 modify_len = roundup_pow_of_two(fw->size); 3836 modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE); 3837 while (1) { 3838 kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle); 3839 if (!kmem && modify_len > PAGE_SIZE) 3840 modify_len /= 2; 3841 else 3842 break; 3843 } 3844 if (!kmem) { 3845 hwrm_req_drop(bp, modify); 3846 return -ENOMEM; 3847 } 3848 3849 rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE); 3850 if (rc) { 3851 hwrm_req_drop(bp, modify); 3852 return rc; 3853 } 3854 3855 hwrm_req_timeout(bp, modify, bp->hwrm_cmd_max_timeout); 3856 hwrm_req_timeout(bp, install, bp->hwrm_cmd_max_timeout); 3857 3858 hwrm_req_hold(bp, modify); 3859 modify->host_src_addr = cpu_to_le64(dma_handle); 3860 3861 resp = hwrm_req_hold(bp, install); 3862 if ((install_type & 0xffff) == 0) 3863 install_type >>= 16; 3864 install->install_type = cpu_to_le32(install_type); 3865 3866 do { 3867 u32 copied = 0, len = modify_len; 3868 3869 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 3870 BNX_DIR_ORDINAL_FIRST, 3871 BNX_DIR_EXT_NONE, 3872 &index, &item_len, NULL); 3873 if (rc) { 3874 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 3875 break; 3876 } 3877 if (fw->size > item_len) { 3878 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_SPACE_ERR); 3879 rc = -EFBIG; 3880 break; 3881 } 3882 3883 modify->dir_idx = cpu_to_le16(index); 3884 3885 if (fw->size > modify_len) 3886 modify->flags = BNXT_NVM_MORE_FLAG; 3887 while (copied < fw->size) { 3888 u32 balance = fw->size - copied; 3889 3890 if (balance <= modify_len) { 3891 len = balance; 3892 if (copied) 3893 modify->flags |= BNXT_NVM_LAST_FLAG; 3894 } 3895 memcpy(kmem, fw->data + copied, len); 3896 modify->len = cpu_to_le32(len); 3897 modify->offset = cpu_to_le32(copied); 3898 rc = hwrm_req_send(bp, modify); 3899 if (rc) 3900 goto pkg_abort; 3901 copied += len; 3902 } 3903 3904 rc = hwrm_req_send_silent(bp, install); 3905 if (!rc) 3906 break; 3907 3908 if (defrag_attempted) { 3909 /* We have tried to defragment already in the previous 3910 * iteration. Return with the result for INSTALL_UPDATE 3911 */ 3912 break; 3913 } 3914 3915 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 3916 3917 switch (cmd_err) { 3918 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK: 3919 BNXT_NVM_ERR_MSG(dev, extack, MSG_ANTI_ROLLBACK_ERR); 3920 rc = -EALREADY; 3921 break; 3922 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR: 3923 install->flags = 3924 cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 3925 3926 rc = hwrm_req_send_silent(bp, install); 3927 if (!rc) 3928 break; 3929 3930 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 3931 3932 if (cmd_err == NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) { 3933 /* FW has cleared NVM area, driver will create 3934 * UPDATE directory and try the flash again 3935 */ 3936 defrag_attempted = true; 3937 install->flags = 0; 3938 rc = bnxt_flash_nvram(bp->dev, 3939 BNX_DIR_TYPE_UPDATE, 3940 BNX_DIR_ORDINAL_FIRST, 3941 0, 0, item_len, NULL, 0); 3942 if (!rc) 3943 break; 3944 } 3945 fallthrough; 3946 default: 3947 BNXT_NVM_ERR_MSG(dev, extack, MSG_GENERIC_FAILURE_ERR); 3948 } 3949 } while (defrag_attempted && !rc); 3950 3951 pkg_abort: 3952 hwrm_req_drop(bp, modify); 3953 hwrm_req_drop(bp, install); 3954 3955 if (resp->result) { 3956 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 3957 (s8)resp->result, (int)resp->problem_item); 3958 rc = nvm_update_err_to_stderr(dev, resp->result, extack); 3959 } 3960 if (rc == -EACCES) 3961 bnxt_print_admin_err(bp); 3962 return rc; 3963 } 3964 3965 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename, 3966 u32 install_type, struct netlink_ext_ack *extack) 3967 { 3968 const struct firmware *fw; 3969 int rc; 3970 3971 rc = request_firmware(&fw, filename, &dev->dev); 3972 if (rc != 0) { 3973 netdev_err(dev, "PKG error %d requesting file: %s\n", 3974 rc, filename); 3975 return rc; 3976 } 3977 3978 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type, extack); 3979 3980 release_firmware(fw); 3981 3982 return rc; 3983 } 3984 3985 static int bnxt_flash_device(struct net_device *dev, 3986 struct ethtool_flash *flash) 3987 { 3988 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 3989 netdev_err(dev, "flashdev not supported from a virtual function\n"); 3990 return -EINVAL; 3991 } 3992 3993 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 3994 flash->region > 0xffff) 3995 return bnxt_flash_package_from_file(dev, flash->data, 3996 flash->region, NULL); 3997 3998 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 3999 } 4000 4001 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 4002 { 4003 struct hwrm_nvm_get_dir_info_output *output; 4004 struct hwrm_nvm_get_dir_info_input *req; 4005 struct bnxt *bp = netdev_priv(dev); 4006 int rc; 4007 4008 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO); 4009 if (rc) 4010 return rc; 4011 4012 output = hwrm_req_hold(bp, req); 4013 rc = hwrm_req_send(bp, req); 4014 if (!rc) { 4015 *entries = le32_to_cpu(output->entries); 4016 *length = le32_to_cpu(output->entry_length); 4017 } 4018 hwrm_req_drop(bp, req); 4019 return rc; 4020 } 4021 4022 static int bnxt_get_eeprom_len(struct net_device *dev) 4023 { 4024 struct bnxt *bp = netdev_priv(dev); 4025 4026 if (BNXT_VF(bp)) 4027 return 0; 4028 4029 /* The -1 return value allows the entire 32-bit range of offsets to be 4030 * passed via the ethtool command-line utility. 4031 */ 4032 return -1; 4033 } 4034 4035 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 4036 { 4037 struct bnxt *bp = netdev_priv(dev); 4038 int rc; 4039 u32 dir_entries; 4040 u32 entry_length; 4041 u8 *buf; 4042 size_t buflen; 4043 dma_addr_t dma_handle; 4044 struct hwrm_nvm_get_dir_entries_input *req; 4045 4046 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 4047 if (rc != 0) 4048 return rc; 4049 4050 if (!dir_entries || !entry_length) 4051 return -EIO; 4052 4053 /* Insert 2 bytes of directory info (count and size of entries) */ 4054 if (len < 2) 4055 return -EINVAL; 4056 4057 *data++ = dir_entries; 4058 *data++ = entry_length; 4059 len -= 2; 4060 memset(data, 0xff, len); 4061 4062 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES); 4063 if (rc) 4064 return rc; 4065 4066 buflen = mul_u32_u32(dir_entries, entry_length); 4067 buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle); 4068 if (!buf) { 4069 hwrm_req_drop(bp, req); 4070 return -ENOMEM; 4071 } 4072 req->host_dest_addr = cpu_to_le64(dma_handle); 4073 4074 hwrm_req_hold(bp, req); /* hold the slice */ 4075 rc = hwrm_req_send(bp, req); 4076 if (rc == 0) 4077 memcpy(data, buf, len > buflen ? buflen : len); 4078 hwrm_req_drop(bp, req); 4079 return rc; 4080 } 4081 4082 int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 4083 u32 length, u8 *data) 4084 { 4085 struct bnxt *bp = netdev_priv(dev); 4086 int rc; 4087 u8 *buf; 4088 dma_addr_t dma_handle; 4089 struct hwrm_nvm_read_input *req; 4090 4091 if (!length) 4092 return -EINVAL; 4093 4094 rc = hwrm_req_init(bp, req, HWRM_NVM_READ); 4095 if (rc) 4096 return rc; 4097 4098 buf = hwrm_req_dma_slice(bp, req, length, &dma_handle); 4099 if (!buf) { 4100 hwrm_req_drop(bp, req); 4101 return -ENOMEM; 4102 } 4103 4104 req->host_dest_addr = cpu_to_le64(dma_handle); 4105 req->dir_idx = cpu_to_le16(index); 4106 req->offset = cpu_to_le32(offset); 4107 req->len = cpu_to_le32(length); 4108 4109 hwrm_req_hold(bp, req); /* hold the slice */ 4110 rc = hwrm_req_send(bp, req); 4111 if (rc == 0) 4112 memcpy(data, buf, length); 4113 hwrm_req_drop(bp, req); 4114 return rc; 4115 } 4116 4117 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 4118 u16 ext, u16 *index, u32 *item_length, 4119 u32 *data_length) 4120 { 4121 struct hwrm_nvm_find_dir_entry_output *output; 4122 struct hwrm_nvm_find_dir_entry_input *req; 4123 struct bnxt *bp = netdev_priv(dev); 4124 int rc; 4125 4126 rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY); 4127 if (rc) 4128 return rc; 4129 4130 req->enables = 0; 4131 req->dir_idx = 0; 4132 req->dir_type = cpu_to_le16(type); 4133 req->dir_ordinal = cpu_to_le16(ordinal); 4134 req->dir_ext = cpu_to_le16(ext); 4135 req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 4136 output = hwrm_req_hold(bp, req); 4137 rc = hwrm_req_send_silent(bp, req); 4138 if (rc == 0) { 4139 if (index) 4140 *index = le16_to_cpu(output->dir_idx); 4141 if (item_length) 4142 *item_length = le32_to_cpu(output->dir_item_length); 4143 if (data_length) 4144 *data_length = le32_to_cpu(output->dir_data_length); 4145 } 4146 hwrm_req_drop(bp, req); 4147 return rc; 4148 } 4149 4150 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 4151 { 4152 char *retval = NULL; 4153 char *p; 4154 char *value; 4155 int field = 0; 4156 4157 if (datalen < 1) 4158 return NULL; 4159 /* null-terminate the log data (removing last '\n'): */ 4160 data[datalen - 1] = 0; 4161 for (p = data; *p != 0; p++) { 4162 field = 0; 4163 retval = NULL; 4164 while (*p != 0 && *p != '\n') { 4165 value = p; 4166 while (*p != 0 && *p != '\t' && *p != '\n') 4167 p++; 4168 if (field == desired_field) 4169 retval = value; 4170 if (*p != '\t') 4171 break; 4172 *p = 0; 4173 field++; 4174 p++; 4175 } 4176 if (*p == 0) 4177 break; 4178 *p = 0; 4179 } 4180 return retval; 4181 } 4182 4183 int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size) 4184 { 4185 struct bnxt *bp = netdev_priv(dev); 4186 u16 index = 0; 4187 char *pkgver; 4188 u32 pkglen; 4189 u8 *pkgbuf; 4190 int rc; 4191 4192 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 4193 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 4194 &index, NULL, &pkglen); 4195 if (rc) 4196 return rc; 4197 4198 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 4199 if (!pkgbuf) { 4200 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 4201 pkglen); 4202 return -ENOMEM; 4203 } 4204 4205 rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf); 4206 if (rc) 4207 goto err; 4208 4209 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 4210 pkglen); 4211 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) 4212 strscpy(ver, pkgver, size); 4213 else 4214 rc = -ENOENT; 4215 4216 err: 4217 kfree(pkgbuf); 4218 4219 return rc; 4220 } 4221 4222 static void bnxt_get_pkgver(struct net_device *dev) 4223 { 4224 struct bnxt *bp = netdev_priv(dev); 4225 char buf[FW_VER_STR_LEN - 5]; 4226 int len; 4227 4228 if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) { 4229 len = strlen(bp->fw_ver_str); 4230 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len, 4231 "/pkg %s", buf); 4232 } 4233 } 4234 4235 static int bnxt_get_eeprom(struct net_device *dev, 4236 struct ethtool_eeprom *eeprom, 4237 u8 *data) 4238 { 4239 u32 index; 4240 u32 offset; 4241 4242 if (eeprom->offset == 0) /* special offset value to get directory */ 4243 return bnxt_get_nvram_directory(dev, eeprom->len, data); 4244 4245 index = eeprom->offset >> 24; 4246 offset = eeprom->offset & 0xffffff; 4247 4248 if (index == 0) { 4249 netdev_err(dev, "unsupported index value: %d\n", index); 4250 return -EINVAL; 4251 } 4252 4253 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 4254 } 4255 4256 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 4257 { 4258 struct hwrm_nvm_erase_dir_entry_input *req; 4259 struct bnxt *bp = netdev_priv(dev); 4260 int rc; 4261 4262 rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY); 4263 if (rc) 4264 return rc; 4265 4266 req->dir_idx = cpu_to_le16(index); 4267 return hwrm_req_send(bp, req); 4268 } 4269 4270 static int bnxt_set_eeprom(struct net_device *dev, 4271 struct ethtool_eeprom *eeprom, 4272 u8 *data) 4273 { 4274 struct bnxt *bp = netdev_priv(dev); 4275 u8 index, dir_op; 4276 u16 type, ext, ordinal, attr; 4277 4278 if (!BNXT_PF(bp)) { 4279 netdev_err(dev, "NVM write not supported from a virtual function\n"); 4280 return -EINVAL; 4281 } 4282 4283 type = eeprom->magic >> 16; 4284 4285 if (type == 0xffff) { /* special value for directory operations */ 4286 index = eeprom->magic & 0xff; 4287 dir_op = eeprom->magic >> 8; 4288 if (index == 0) 4289 return -EINVAL; 4290 switch (dir_op) { 4291 case 0x0e: /* erase */ 4292 if (eeprom->offset != ~eeprom->magic) 4293 return -EINVAL; 4294 return bnxt_erase_nvram_directory(dev, index - 1); 4295 default: 4296 return -EINVAL; 4297 } 4298 } 4299 4300 /* Create or re-write an NVM item: */ 4301 if (bnxt_dir_type_is_executable(type)) 4302 return -EOPNOTSUPP; 4303 ext = eeprom->magic & 0xffff; 4304 ordinal = eeprom->offset >> 16; 4305 attr = eeprom->offset & 0xffff; 4306 4307 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data, 4308 eeprom->len); 4309 } 4310 4311 static int bnxt_set_eee(struct net_device *dev, struct ethtool_keee *edata) 4312 { 4313 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 4314 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp); 4315 struct bnxt *bp = netdev_priv(dev); 4316 struct ethtool_keee *eee = &bp->eee; 4317 struct bnxt_link_info *link_info = &bp->link_info; 4318 int rc = 0; 4319 4320 if (!BNXT_PHY_CFG_ABLE(bp)) 4321 return -EOPNOTSUPP; 4322 4323 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 4324 return -EOPNOTSUPP; 4325 4326 mutex_lock(&bp->link_lock); 4327 _bnxt_fw_to_linkmode(advertising, link_info->advertising); 4328 if (!edata->eee_enabled) 4329 goto eee_ok; 4330 4331 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 4332 netdev_warn(dev, "EEE requires autoneg\n"); 4333 rc = -EINVAL; 4334 goto eee_exit; 4335 } 4336 if (edata->tx_lpi_enabled) { 4337 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 4338 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 4339 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 4340 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 4341 rc = -EINVAL; 4342 goto eee_exit; 4343 } else if (!bp->lpi_tmr_hi) { 4344 edata->tx_lpi_timer = eee->tx_lpi_timer; 4345 } 4346 } 4347 if (linkmode_empty(edata->advertised)) { 4348 linkmode_and(edata->advertised, advertising, eee->supported); 4349 } else if (linkmode_andnot(tmp, edata->advertised, advertising)) { 4350 netdev_warn(dev, "EEE advertised must be a subset of autoneg advertised speeds\n"); 4351 rc = -EINVAL; 4352 goto eee_exit; 4353 } 4354 4355 linkmode_copy(eee->advertised, edata->advertised); 4356 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 4357 eee->tx_lpi_timer = edata->tx_lpi_timer; 4358 eee_ok: 4359 eee->eee_enabled = edata->eee_enabled; 4360 4361 if (netif_running(dev)) 4362 rc = bnxt_hwrm_set_link_setting(bp, false, true); 4363 4364 eee_exit: 4365 mutex_unlock(&bp->link_lock); 4366 return rc; 4367 } 4368 4369 static int bnxt_get_eee(struct net_device *dev, struct ethtool_keee *edata) 4370 { 4371 struct bnxt *bp = netdev_priv(dev); 4372 4373 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 4374 return -EOPNOTSUPP; 4375 4376 *edata = bp->eee; 4377 if (!bp->eee.eee_enabled) { 4378 /* Preserve tx_lpi_timer so that the last value will be used 4379 * by default when it is re-enabled. 4380 */ 4381 linkmode_zero(edata->advertised); 4382 edata->tx_lpi_enabled = 0; 4383 } 4384 4385 if (!bp->eee.eee_active) 4386 linkmode_zero(edata->lp_advertised); 4387 4388 return 0; 4389 } 4390 4391 static int bnxt_set_tunable(struct net_device *dev, 4392 const struct ethtool_tunable *tuna, 4393 const void *data) 4394 { 4395 struct bnxt *bp = netdev_priv(dev); 4396 u32 rx_copybreak; 4397 4398 switch (tuna->id) { 4399 case ETHTOOL_RX_COPYBREAK: 4400 rx_copybreak = *(u32 *)data; 4401 if (rx_copybreak > BNXT_MAX_RX_COPYBREAK) 4402 return -ERANGE; 4403 if (rx_copybreak != bp->rx_copybreak) { 4404 if (netif_running(dev)) 4405 return -EBUSY; 4406 bp->rx_copybreak = rx_copybreak; 4407 } 4408 return 0; 4409 default: 4410 return -EOPNOTSUPP; 4411 } 4412 } 4413 4414 static int bnxt_get_tunable(struct net_device *dev, 4415 const struct ethtool_tunable *tuna, void *data) 4416 { 4417 struct bnxt *bp = netdev_priv(dev); 4418 4419 switch (tuna->id) { 4420 case ETHTOOL_RX_COPYBREAK: 4421 *(u32 *)data = bp->rx_copybreak; 4422 break; 4423 default: 4424 return -EOPNOTSUPP; 4425 } 4426 4427 return 0; 4428 } 4429 4430 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 4431 u16 page_number, u8 bank, 4432 u16 start_addr, u16 data_length, 4433 u8 *buf) 4434 { 4435 struct hwrm_port_phy_i2c_read_output *output; 4436 struct hwrm_port_phy_i2c_read_input *req; 4437 int rc, byte_offset = 0; 4438 4439 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ); 4440 if (rc) 4441 return rc; 4442 4443 output = hwrm_req_hold(bp, req); 4444 req->i2c_slave_addr = i2c_addr; 4445 req->page_number = cpu_to_le16(page_number); 4446 req->port_id = cpu_to_le16(bp->pf.port_id); 4447 do { 4448 u16 xfer_size; 4449 4450 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 4451 data_length -= xfer_size; 4452 req->page_offset = cpu_to_le16(start_addr + byte_offset); 4453 req->data_length = xfer_size; 4454 req->enables = 4455 cpu_to_le32((start_addr + byte_offset ? 4456 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 4457 0) | 4458 (bank ? 4459 PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER : 4460 0)); 4461 rc = hwrm_req_send(bp, req); 4462 if (!rc) 4463 memcpy(buf + byte_offset, output->data, xfer_size); 4464 byte_offset += xfer_size; 4465 } while (!rc && data_length > 0); 4466 hwrm_req_drop(bp, req); 4467 4468 return rc; 4469 } 4470 4471 static int bnxt_get_module_info(struct net_device *dev, 4472 struct ethtool_modinfo *modinfo) 4473 { 4474 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 4475 struct bnxt *bp = netdev_priv(dev); 4476 int rc; 4477 4478 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 4479 return -EPERM; 4480 4481 /* No point in going further if phy status indicates 4482 * module is not inserted or if it is powered down or 4483 * if it is of type 10GBase-T 4484 */ 4485 if (bp->link_info.module_status > 4486 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 4487 return -EOPNOTSUPP; 4488 4489 /* This feature is not supported in older firmware versions */ 4490 if (bp->hwrm_spec_code < 0x10202) 4491 return -EOPNOTSUPP; 4492 4493 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 0, 4494 SFF_DIAG_SUPPORT_OFFSET + 1, 4495 data); 4496 if (!rc) { 4497 u8 module_id = data[0]; 4498 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 4499 4500 switch (module_id) { 4501 case SFF_MODULE_ID_SFP: 4502 modinfo->type = ETH_MODULE_SFF_8472; 4503 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 4504 if (!diag_supported) 4505 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 4506 break; 4507 case SFF_MODULE_ID_QSFP: 4508 case SFF_MODULE_ID_QSFP_PLUS: 4509 modinfo->type = ETH_MODULE_SFF_8436; 4510 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 4511 break; 4512 case SFF_MODULE_ID_QSFP28: 4513 modinfo->type = ETH_MODULE_SFF_8636; 4514 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 4515 break; 4516 default: 4517 rc = -EOPNOTSUPP; 4518 break; 4519 } 4520 } 4521 return rc; 4522 } 4523 4524 static int bnxt_get_module_eeprom(struct net_device *dev, 4525 struct ethtool_eeprom *eeprom, 4526 u8 *data) 4527 { 4528 struct bnxt *bp = netdev_priv(dev); 4529 u16 start = eeprom->offset, length = eeprom->len; 4530 int rc = 0; 4531 4532 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 4533 return -EPERM; 4534 4535 memset(data, 0, eeprom->len); 4536 4537 /* Read A0 portion of the EEPROM */ 4538 if (start < ETH_MODULE_SFF_8436_LEN) { 4539 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 4540 length = ETH_MODULE_SFF_8436_LEN - start; 4541 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 4542 start, length, data); 4543 if (rc) 4544 return rc; 4545 start += length; 4546 data += length; 4547 length = eeprom->len - length; 4548 } 4549 4550 /* Read A2 portion of the EEPROM */ 4551 if (length) { 4552 start -= ETH_MODULE_SFF_8436_LEN; 4553 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 0, 4554 start, length, data); 4555 } 4556 return rc; 4557 } 4558 4559 static int bnxt_get_module_status(struct bnxt *bp, struct netlink_ext_ack *extack) 4560 { 4561 if (bp->link_info.module_status <= 4562 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 4563 return 0; 4564 4565 switch (bp->link_info.module_status) { 4566 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 4567 NL_SET_ERR_MSG_MOD(extack, "Transceiver module is powering down"); 4568 break; 4569 case PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED: 4570 NL_SET_ERR_MSG_MOD(extack, "Transceiver module not inserted"); 4571 break; 4572 case PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT: 4573 NL_SET_ERR_MSG_MOD(extack, "Transceiver module disabled due to current fault"); 4574 break; 4575 default: 4576 NL_SET_ERR_MSG_MOD(extack, "Unknown error"); 4577 break; 4578 } 4579 return -EINVAL; 4580 } 4581 4582 static int 4583 bnxt_mod_eeprom_by_page_precheck(struct bnxt *bp, 4584 const struct ethtool_module_eeprom *page_data, 4585 struct netlink_ext_ack *extack) 4586 { 4587 int rc; 4588 4589 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { 4590 NL_SET_ERR_MSG_MOD(extack, 4591 "Module read/write not permitted on untrusted VF"); 4592 return -EPERM; 4593 } 4594 4595 rc = bnxt_get_module_status(bp, extack); 4596 if (rc) 4597 return rc; 4598 4599 if (bp->hwrm_spec_code < 0x10202) { 4600 NL_SET_ERR_MSG_MOD(extack, "Firmware version too old"); 4601 return -EINVAL; 4602 } 4603 4604 if (page_data->bank && !(bp->phy_flags & BNXT_PHY_FL_BANK_SEL)) { 4605 NL_SET_ERR_MSG_MOD(extack, "Firmware not capable for bank selection"); 4606 return -EINVAL; 4607 } 4608 return 0; 4609 } 4610 4611 static int bnxt_get_module_eeprom_by_page(struct net_device *dev, 4612 const struct ethtool_module_eeprom *page_data, 4613 struct netlink_ext_ack *extack) 4614 { 4615 struct bnxt *bp = netdev_priv(dev); 4616 int rc; 4617 4618 rc = bnxt_mod_eeprom_by_page_precheck(bp, page_data, extack); 4619 if (rc) 4620 return rc; 4621 4622 rc = bnxt_read_sfp_module_eeprom_info(bp, page_data->i2c_address << 1, 4623 page_data->page, page_data->bank, 4624 page_data->offset, 4625 page_data->length, 4626 page_data->data); 4627 if (rc) { 4628 NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom read failed"); 4629 return rc; 4630 } 4631 return page_data->length; 4632 } 4633 4634 static int bnxt_write_sfp_module_eeprom_info(struct bnxt *bp, 4635 const struct ethtool_module_eeprom *page) 4636 { 4637 struct hwrm_port_phy_i2c_write_input *req; 4638 int bytes_written = 0; 4639 int rc; 4640 4641 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_WRITE); 4642 if (rc) 4643 return rc; 4644 4645 hwrm_req_hold(bp, req); 4646 req->i2c_slave_addr = page->i2c_address << 1; 4647 req->page_number = cpu_to_le16(page->page); 4648 req->bank_number = page->bank; 4649 req->port_id = cpu_to_le16(bp->pf.port_id); 4650 req->enables = cpu_to_le32(PORT_PHY_I2C_WRITE_REQ_ENABLES_PAGE_OFFSET | 4651 PORT_PHY_I2C_WRITE_REQ_ENABLES_BANK_NUMBER); 4652 4653 while (bytes_written < page->length) { 4654 u16 xfer_size; 4655 4656 xfer_size = min_t(u16, page->length - bytes_written, 4657 BNXT_MAX_PHY_I2C_RESP_SIZE); 4658 req->page_offset = cpu_to_le16(page->offset + bytes_written); 4659 req->data_length = xfer_size; 4660 memcpy(req->data, page->data + bytes_written, xfer_size); 4661 rc = hwrm_req_send(bp, req); 4662 if (rc) 4663 break; 4664 bytes_written += xfer_size; 4665 } 4666 4667 hwrm_req_drop(bp, req); 4668 return rc; 4669 } 4670 4671 static int bnxt_set_module_eeprom_by_page(struct net_device *dev, 4672 const struct ethtool_module_eeprom *page_data, 4673 struct netlink_ext_ack *extack) 4674 { 4675 struct bnxt *bp = netdev_priv(dev); 4676 int rc; 4677 4678 rc = bnxt_mod_eeprom_by_page_precheck(bp, page_data, extack); 4679 if (rc) 4680 return rc; 4681 4682 rc = bnxt_write_sfp_module_eeprom_info(bp, page_data); 4683 if (rc) { 4684 NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom write failed"); 4685 return rc; 4686 } 4687 return page_data->length; 4688 } 4689 4690 static int bnxt_nway_reset(struct net_device *dev) 4691 { 4692 int rc = 0; 4693 4694 struct bnxt *bp = netdev_priv(dev); 4695 struct bnxt_link_info *link_info = &bp->link_info; 4696 4697 if (!BNXT_PHY_CFG_ABLE(bp)) 4698 return -EOPNOTSUPP; 4699 4700 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 4701 return -EINVAL; 4702 4703 if (netif_running(dev)) 4704 rc = bnxt_hwrm_set_link_setting(bp, true, false); 4705 4706 return rc; 4707 } 4708 4709 static int bnxt_set_phys_id(struct net_device *dev, 4710 enum ethtool_phys_id_state state) 4711 { 4712 struct hwrm_port_led_cfg_input *req; 4713 struct bnxt *bp = netdev_priv(dev); 4714 struct bnxt_pf_info *pf = &bp->pf; 4715 struct bnxt_led_cfg *led_cfg; 4716 u8 led_state; 4717 __le16 duration; 4718 int rc, i; 4719 4720 if (!bp->num_leds || BNXT_VF(bp)) 4721 return -EOPNOTSUPP; 4722 4723 if (state == ETHTOOL_ID_ACTIVE) { 4724 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 4725 duration = cpu_to_le16(500); 4726 } else if (state == ETHTOOL_ID_INACTIVE) { 4727 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 4728 duration = cpu_to_le16(0); 4729 } else { 4730 return -EINVAL; 4731 } 4732 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG); 4733 if (rc) 4734 return rc; 4735 4736 req->port_id = cpu_to_le16(pf->port_id); 4737 req->num_leds = bp->num_leds; 4738 led_cfg = (struct bnxt_led_cfg *)&req->led0_id; 4739 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 4740 req->enables |= BNXT_LED_DFLT_ENABLES(i); 4741 led_cfg->led_id = bp->leds[i].led_id; 4742 led_cfg->led_state = led_state; 4743 led_cfg->led_blink_on = duration; 4744 led_cfg->led_blink_off = duration; 4745 led_cfg->led_group_id = bp->leds[i].led_group_id; 4746 } 4747 return hwrm_req_send(bp, req); 4748 } 4749 4750 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 4751 { 4752 struct hwrm_selftest_irq_input *req; 4753 int rc; 4754 4755 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ); 4756 if (rc) 4757 return rc; 4758 4759 req->cmpl_ring = cpu_to_le16(cmpl_ring); 4760 return hwrm_req_send(bp, req); 4761 } 4762 4763 static int bnxt_test_irq(struct bnxt *bp) 4764 { 4765 int i; 4766 4767 for (i = 0; i < bp->cp_nr_rings; i++) { 4768 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 4769 int rc; 4770 4771 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 4772 if (rc) 4773 return rc; 4774 } 4775 return 0; 4776 } 4777 4778 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 4779 { 4780 struct hwrm_port_mac_cfg_input *req; 4781 int rc; 4782 4783 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 4784 if (rc) 4785 return rc; 4786 4787 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 4788 if (enable) 4789 req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 4790 else 4791 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 4792 return hwrm_req_send(bp, req); 4793 } 4794 4795 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 4796 { 4797 struct hwrm_port_phy_qcaps_output *resp; 4798 struct hwrm_port_phy_qcaps_input *req; 4799 int rc; 4800 4801 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS); 4802 if (rc) 4803 return rc; 4804 4805 resp = hwrm_req_hold(bp, req); 4806 rc = hwrm_req_send(bp, req); 4807 if (!rc) 4808 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 4809 4810 hwrm_req_drop(bp, req); 4811 return rc; 4812 } 4813 4814 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 4815 struct hwrm_port_phy_cfg_input *req) 4816 { 4817 struct bnxt_link_info *link_info = &bp->link_info; 4818 u16 fw_advertising; 4819 u16 fw_speed; 4820 int rc; 4821 4822 if (!link_info->autoneg || 4823 (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK)) 4824 return 0; 4825 4826 rc = bnxt_query_force_speeds(bp, &fw_advertising); 4827 if (rc) 4828 return rc; 4829 4830 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 4831 if (BNXT_LINK_IS_UP(bp)) 4832 fw_speed = bp->link_info.link_speed; 4833 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 4834 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 4835 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 4836 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 4837 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 4838 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 4839 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 4840 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 4841 4842 req->force_link_speed = cpu_to_le16(fw_speed); 4843 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 4844 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 4845 rc = hwrm_req_send(bp, req); 4846 req->flags = 0; 4847 req->force_link_speed = cpu_to_le16(0); 4848 return rc; 4849 } 4850 4851 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 4852 { 4853 struct hwrm_port_phy_cfg_input *req; 4854 int rc; 4855 4856 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 4857 if (rc) 4858 return rc; 4859 4860 /* prevent bnxt_disable_an_for_lpbk() from consuming the request */ 4861 hwrm_req_hold(bp, req); 4862 4863 if (enable) { 4864 bnxt_disable_an_for_lpbk(bp, req); 4865 if (ext) 4866 req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 4867 else 4868 req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 4869 } else { 4870 req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 4871 } 4872 req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 4873 rc = hwrm_req_send(bp, req); 4874 hwrm_req_drop(bp, req); 4875 return rc; 4876 } 4877 4878 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 4879 u32 raw_cons, int pkt_size) 4880 { 4881 struct bnxt_napi *bnapi = cpr->bnapi; 4882 struct bnxt_rx_ring_info *rxr; 4883 struct bnxt_sw_rx_bd *rx_buf; 4884 struct rx_cmp *rxcmp; 4885 u16 cp_cons, cons; 4886 u8 *data; 4887 u32 len; 4888 int i; 4889 4890 rxr = bnapi->rx_ring; 4891 cp_cons = RING_CMP(raw_cons); 4892 rxcmp = (struct rx_cmp *) 4893 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 4894 cons = rxcmp->rx_cmp_opaque; 4895 rx_buf = &rxr->rx_buf_ring[cons]; 4896 data = rx_buf->data_ptr; 4897 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 4898 if (len != pkt_size) 4899 return -EIO; 4900 i = ETH_ALEN; 4901 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 4902 return -EIO; 4903 i += ETH_ALEN; 4904 for ( ; i < pkt_size; i++) { 4905 if (data[i] != (u8)(i & 0xff)) 4906 return -EIO; 4907 } 4908 return 0; 4909 } 4910 4911 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 4912 int pkt_size) 4913 { 4914 struct tx_cmp *txcmp; 4915 int rc = -EIO; 4916 u32 raw_cons; 4917 u32 cons; 4918 int i; 4919 4920 raw_cons = cpr->cp_raw_cons; 4921 for (i = 0; i < 200; i++) { 4922 cons = RING_CMP(raw_cons); 4923 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 4924 4925 if (!TX_CMP_VALID(txcmp, raw_cons)) { 4926 udelay(5); 4927 continue; 4928 } 4929 4930 /* The valid test of the entry must be done first before 4931 * reading any further. 4932 */ 4933 dma_rmb(); 4934 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP || 4935 TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_V3_CMP) { 4936 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 4937 raw_cons = NEXT_RAW_CMP(raw_cons); 4938 raw_cons = NEXT_RAW_CMP(raw_cons); 4939 break; 4940 } 4941 raw_cons = NEXT_RAW_CMP(raw_cons); 4942 } 4943 cpr->cp_raw_cons = raw_cons; 4944 return rc; 4945 } 4946 4947 static int bnxt_run_loopback(struct bnxt *bp) 4948 { 4949 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 4950 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 4951 struct bnxt_cp_ring_info *cpr; 4952 int pkt_size, i = 0; 4953 struct sk_buff *skb; 4954 dma_addr_t map; 4955 u8 *data; 4956 int rc; 4957 4958 cpr = &rxr->bnapi->cp_ring; 4959 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) 4960 cpr = rxr->rx_cpr; 4961 pkt_size = min(bp->dev->mtu + ETH_HLEN, max(BNXT_DEFAULT_RX_COPYBREAK, 4962 bp->rx_copybreak)); 4963 skb = netdev_alloc_skb(bp->dev, pkt_size); 4964 if (!skb) 4965 return -ENOMEM; 4966 data = skb_put(skb, pkt_size); 4967 ether_addr_copy(&data[i], bp->dev->dev_addr); 4968 i += ETH_ALEN; 4969 ether_addr_copy(&data[i], bp->dev->dev_addr); 4970 i += ETH_ALEN; 4971 for ( ; i < pkt_size; i++) 4972 data[i] = (u8)(i & 0xff); 4973 4974 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 4975 DMA_TO_DEVICE); 4976 if (dma_mapping_error(&bp->pdev->dev, map)) { 4977 dev_kfree_skb(skb); 4978 return -EIO; 4979 } 4980 bnxt_xmit_bd(bp, txr, map, pkt_size, NULL); 4981 4982 /* Sync BD data before updating doorbell */ 4983 wmb(); 4984 4985 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 4986 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 4987 4988 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE); 4989 dev_kfree_skb(skb); 4990 return rc; 4991 } 4992 4993 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 4994 { 4995 struct hwrm_selftest_exec_output *resp; 4996 struct hwrm_selftest_exec_input *req; 4997 int rc; 4998 4999 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC); 5000 if (rc) 5001 return rc; 5002 5003 hwrm_req_timeout(bp, req, bp->test_info->timeout); 5004 req->flags = test_mask; 5005 5006 resp = hwrm_req_hold(bp, req); 5007 rc = hwrm_req_send(bp, req); 5008 *test_results = resp->test_success; 5009 hwrm_req_drop(bp, req); 5010 return rc; 5011 } 5012 5013 #define BNXT_DRV_TESTS 4 5014 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 5015 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 5016 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 5017 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 5018 5019 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 5020 u64 *buf) 5021 { 5022 struct bnxt *bp = netdev_priv(dev); 5023 bool do_ext_lpbk = false; 5024 bool offline = false; 5025 u8 test_results = 0; 5026 u8 test_mask = 0; 5027 int rc = 0, i; 5028 5029 if (!bp->num_tests || !BNXT_PF(bp)) 5030 return; 5031 5032 memset(buf, 0, sizeof(u64) * bp->num_tests); 5033 if (etest->flags & ETH_TEST_FL_OFFLINE && 5034 bnxt_ulp_registered(bp->edev)) { 5035 etest->flags |= ETH_TEST_FL_FAILED; 5036 netdev_warn(dev, "Offline tests cannot be run with RoCE driver loaded\n"); 5037 return; 5038 } 5039 5040 if (!netif_running(dev)) { 5041 etest->flags |= ETH_TEST_FL_FAILED; 5042 return; 5043 } 5044 5045 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 5046 (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK)) 5047 do_ext_lpbk = true; 5048 5049 if (etest->flags & ETH_TEST_FL_OFFLINE) { 5050 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) { 5051 etest->flags |= ETH_TEST_FL_FAILED; 5052 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n"); 5053 return; 5054 } 5055 offline = true; 5056 } 5057 5058 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 5059 u8 bit_val = 1 << i; 5060 5061 if (!(bp->test_info->offline_mask & bit_val)) 5062 test_mask |= bit_val; 5063 else if (offline) 5064 test_mask |= bit_val; 5065 } 5066 if (!offline) { 5067 bnxt_run_fw_tests(bp, test_mask, &test_results); 5068 } else { 5069 bnxt_close_nic(bp, true, false); 5070 bnxt_run_fw_tests(bp, test_mask, &test_results); 5071 5072 rc = bnxt_half_open_nic(bp); 5073 if (rc) { 5074 etest->flags |= ETH_TEST_FL_FAILED; 5075 return; 5076 } 5077 buf[BNXT_MACLPBK_TEST_IDX] = 1; 5078 if (bp->mac_flags & BNXT_MAC_FL_NO_MAC_LPBK) 5079 goto skip_mac_loopback; 5080 5081 bnxt_hwrm_mac_loopback(bp, true); 5082 msleep(250); 5083 if (bnxt_run_loopback(bp)) 5084 etest->flags |= ETH_TEST_FL_FAILED; 5085 else 5086 buf[BNXT_MACLPBK_TEST_IDX] = 0; 5087 5088 bnxt_hwrm_mac_loopback(bp, false); 5089 skip_mac_loopback: 5090 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 5091 if (bp->phy_flags & BNXT_PHY_FL_NO_PHY_LPBK) 5092 goto skip_phy_loopback; 5093 5094 bnxt_hwrm_phy_loopback(bp, true, false); 5095 msleep(1000); 5096 if (bnxt_run_loopback(bp)) 5097 etest->flags |= ETH_TEST_FL_FAILED; 5098 else 5099 buf[BNXT_PHYLPBK_TEST_IDX] = 0; 5100 skip_phy_loopback: 5101 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 5102 if (do_ext_lpbk) { 5103 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 5104 bnxt_hwrm_phy_loopback(bp, true, true); 5105 msleep(1000); 5106 if (bnxt_run_loopback(bp)) 5107 etest->flags |= ETH_TEST_FL_FAILED; 5108 else 5109 buf[BNXT_EXTLPBK_TEST_IDX] = 0; 5110 } 5111 bnxt_hwrm_phy_loopback(bp, false, false); 5112 bnxt_half_close_nic(bp); 5113 rc = bnxt_open_nic(bp, true, true); 5114 } 5115 if (rc || bnxt_test_irq(bp)) { 5116 buf[BNXT_IRQ_TEST_IDX] = 1; 5117 etest->flags |= ETH_TEST_FL_FAILED; 5118 } 5119 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 5120 u8 bit_val = 1 << i; 5121 5122 if ((test_mask & bit_val) && !(test_results & bit_val)) { 5123 buf[i] = 1; 5124 etest->flags |= ETH_TEST_FL_FAILED; 5125 } 5126 } 5127 } 5128 5129 static int bnxt_reset(struct net_device *dev, u32 *flags) 5130 { 5131 struct bnxt *bp = netdev_priv(dev); 5132 bool reload = false; 5133 u32 req = *flags; 5134 5135 if (!req) 5136 return -EINVAL; 5137 5138 if (!BNXT_PF(bp)) { 5139 netdev_err(dev, "Reset is not supported from a VF\n"); 5140 return -EOPNOTSUPP; 5141 } 5142 5143 if (pci_vfs_assigned(bp->pdev) && 5144 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) { 5145 netdev_err(dev, 5146 "Reset not allowed when VFs are assigned to VMs\n"); 5147 return -EBUSY; 5148 } 5149 5150 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) { 5151 /* This feature is not supported in older firmware versions */ 5152 if (bp->hwrm_spec_code >= 0x10803) { 5153 if (!bnxt_firmware_reset_chip(dev)) { 5154 netdev_info(dev, "Firmware reset request successful.\n"); 5155 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) 5156 reload = true; 5157 *flags &= ~BNXT_FW_RESET_CHIP; 5158 } 5159 } else if (req == BNXT_FW_RESET_CHIP) { 5160 return -EOPNOTSUPP; /* only request, fail hard */ 5161 } 5162 } 5163 5164 if (!BNXT_CHIP_P4_PLUS(bp) && (req & BNXT_FW_RESET_AP)) { 5165 /* This feature is not supported in older firmware versions */ 5166 if (bp->hwrm_spec_code >= 0x10803) { 5167 if (!bnxt_firmware_reset_ap(dev)) { 5168 netdev_info(dev, "Reset application processor successful.\n"); 5169 reload = true; 5170 *flags &= ~BNXT_FW_RESET_AP; 5171 } 5172 } else if (req == BNXT_FW_RESET_AP) { 5173 return -EOPNOTSUPP; /* only request, fail hard */ 5174 } 5175 } 5176 5177 if (reload) 5178 netdev_info(dev, "Reload driver to complete reset\n"); 5179 5180 return 0; 5181 } 5182 5183 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump) 5184 { 5185 struct bnxt *bp = netdev_priv(dev); 5186 5187 if (dump->flag > BNXT_DUMP_LIVE_WITH_CTX_L1_CACHE) { 5188 netdev_info(dev, 5189 "Supports only Live(0), Crash(1), Driver(2), Live with cached context(3) dumps.\n"); 5190 return -EINVAL; 5191 } 5192 5193 if (dump->flag == BNXT_DUMP_CRASH) { 5194 if (bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR && 5195 (!IS_ENABLED(CONFIG_TEE_BNXT_FW))) { 5196 netdev_info(dev, 5197 "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n"); 5198 return -EOPNOTSUPP; 5199 } else if (!(bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR)) { 5200 netdev_info(dev, "Crash dump collection from host memory is not supported on this interface.\n"); 5201 return -EOPNOTSUPP; 5202 } 5203 } 5204 5205 bp->dump_flag = dump->flag; 5206 return 0; 5207 } 5208 5209 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 5210 { 5211 struct bnxt *bp = netdev_priv(dev); 5212 5213 if (bp->hwrm_spec_code < 0x10801) 5214 return -EOPNOTSUPP; 5215 5216 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 5217 bp->ver_resp.hwrm_fw_min_8b << 16 | 5218 bp->ver_resp.hwrm_fw_bld_8b << 8 | 5219 bp->ver_resp.hwrm_fw_rsvd_8b; 5220 5221 dump->flag = bp->dump_flag; 5222 dump->len = bnxt_get_coredump_length(bp, bp->dump_flag); 5223 return 0; 5224 } 5225 5226 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 5227 void *buf) 5228 { 5229 struct bnxt *bp = netdev_priv(dev); 5230 5231 if (bp->hwrm_spec_code < 0x10801) 5232 return -EOPNOTSUPP; 5233 5234 memset(buf, 0, dump->len); 5235 5236 dump->flag = bp->dump_flag; 5237 return bnxt_get_coredump(bp, dump->flag, buf, &dump->len); 5238 } 5239 5240 static int bnxt_get_ts_info(struct net_device *dev, 5241 struct kernel_ethtool_ts_info *info) 5242 { 5243 struct bnxt *bp = netdev_priv(dev); 5244 struct bnxt_ptp_cfg *ptp; 5245 5246 ptp = bp->ptp_cfg; 5247 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE; 5248 5249 if (!ptp) 5250 return 0; 5251 5252 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | 5253 SOF_TIMESTAMPING_RX_HARDWARE | 5254 SOF_TIMESTAMPING_RAW_HARDWARE; 5255 if (ptp->ptp_clock) 5256 info->phc_index = ptp_clock_index(ptp->ptp_clock); 5257 5258 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 5259 5260 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 5261 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 5262 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 5263 5264 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) 5265 info->rx_filters |= (1 << HWTSTAMP_FILTER_ALL); 5266 return 0; 5267 } 5268 5269 void bnxt_ethtool_init(struct bnxt *bp) 5270 { 5271 struct hwrm_selftest_qlist_output *resp; 5272 struct hwrm_selftest_qlist_input *req; 5273 struct bnxt_test_info *test_info; 5274 struct net_device *dev = bp->dev; 5275 int i, rc; 5276 5277 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 5278 bnxt_get_pkgver(dev); 5279 5280 bp->num_tests = 0; 5281 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp)) 5282 return; 5283 5284 test_info = bp->test_info; 5285 if (!test_info) { 5286 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL); 5287 if (!test_info) 5288 return; 5289 bp->test_info = test_info; 5290 } 5291 5292 if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST)) 5293 return; 5294 5295 resp = hwrm_req_hold(bp, req); 5296 rc = hwrm_req_send_silent(bp, req); 5297 if (rc) 5298 goto ethtool_init_exit; 5299 5300 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 5301 if (bp->num_tests > BNXT_MAX_TEST) 5302 bp->num_tests = BNXT_MAX_TEST; 5303 5304 test_info->offline_mask = resp->offline_tests; 5305 test_info->timeout = le16_to_cpu(resp->test_timeout); 5306 if (!test_info->timeout) 5307 test_info->timeout = HWRM_CMD_TIMEOUT; 5308 for (i = 0; i < bp->num_tests; i++) { 5309 char *str = test_info->string[i]; 5310 char *fw_str = resp->test_name[i]; 5311 5312 if (i == BNXT_MACLPBK_TEST_IDX) { 5313 strcpy(str, "Mac loopback test (offline)"); 5314 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 5315 strcpy(str, "Phy loopback test (offline)"); 5316 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 5317 strcpy(str, "Ext loopback test (offline)"); 5318 } else if (i == BNXT_IRQ_TEST_IDX) { 5319 strcpy(str, "Interrupt_test (offline)"); 5320 } else { 5321 snprintf(str, ETH_GSTRING_LEN, "%s test (%s)", 5322 fw_str, test_info->offline_mask & (1 << i) ? 5323 "offline" : "online"); 5324 } 5325 } 5326 5327 ethtool_init_exit: 5328 hwrm_req_drop(bp, req); 5329 } 5330 5331 static void bnxt_get_eth_phy_stats(struct net_device *dev, 5332 struct ethtool_eth_phy_stats *phy_stats) 5333 { 5334 struct bnxt *bp = netdev_priv(dev); 5335 u64 *rx; 5336 5337 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 5338 return; 5339 5340 rx = bp->rx_port_stats_ext.sw_stats; 5341 phy_stats->SymbolErrorDuringCarrier = 5342 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err)); 5343 } 5344 5345 static void bnxt_get_eth_mac_stats(struct net_device *dev, 5346 struct ethtool_eth_mac_stats *mac_stats) 5347 { 5348 struct bnxt *bp = netdev_priv(dev); 5349 u64 *rx, *tx; 5350 5351 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5352 return; 5353 5354 rx = bp->port_stats.sw_stats; 5355 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 5356 5357 mac_stats->FramesReceivedOK = 5358 BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames); 5359 mac_stats->FramesTransmittedOK = 5360 BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames); 5361 mac_stats->FrameCheckSequenceErrors = 5362 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames); 5363 mac_stats->AlignmentErrors = 5364 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames); 5365 mac_stats->OutOfRangeLengthField = 5366 BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames); 5367 } 5368 5369 static void bnxt_get_eth_ctrl_stats(struct net_device *dev, 5370 struct ethtool_eth_ctrl_stats *ctrl_stats) 5371 { 5372 struct bnxt *bp = netdev_priv(dev); 5373 u64 *rx; 5374 5375 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5376 return; 5377 5378 rx = bp->port_stats.sw_stats; 5379 ctrl_stats->MACControlFramesReceived = 5380 BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames); 5381 } 5382 5383 static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = { 5384 { 0, 64 }, 5385 { 65, 127 }, 5386 { 128, 255 }, 5387 { 256, 511 }, 5388 { 512, 1023 }, 5389 { 1024, 1518 }, 5390 { 1519, 2047 }, 5391 { 2048, 4095 }, 5392 { 4096, 9216 }, 5393 { 9217, 16383 }, 5394 {} 5395 }; 5396 5397 static void bnxt_get_rmon_stats(struct net_device *dev, 5398 struct ethtool_rmon_stats *rmon_stats, 5399 const struct ethtool_rmon_hist_range **ranges) 5400 { 5401 struct bnxt *bp = netdev_priv(dev); 5402 u64 *rx, *tx; 5403 5404 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5405 return; 5406 5407 rx = bp->port_stats.sw_stats; 5408 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 5409 5410 rmon_stats->jabbers = 5411 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames); 5412 rmon_stats->oversize_pkts = 5413 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames); 5414 rmon_stats->undersize_pkts = 5415 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames); 5416 5417 rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames); 5418 rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames); 5419 rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames); 5420 rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames); 5421 rmon_stats->hist[4] = 5422 BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames); 5423 rmon_stats->hist[5] = 5424 BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames); 5425 rmon_stats->hist[6] = 5426 BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames); 5427 rmon_stats->hist[7] = 5428 BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames); 5429 rmon_stats->hist[8] = 5430 BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames); 5431 rmon_stats->hist[9] = 5432 BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames); 5433 5434 rmon_stats->hist_tx[0] = 5435 BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames); 5436 rmon_stats->hist_tx[1] = 5437 BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames); 5438 rmon_stats->hist_tx[2] = 5439 BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames); 5440 rmon_stats->hist_tx[3] = 5441 BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames); 5442 rmon_stats->hist_tx[4] = 5443 BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames); 5444 rmon_stats->hist_tx[5] = 5445 BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames); 5446 rmon_stats->hist_tx[6] = 5447 BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames); 5448 rmon_stats->hist_tx[7] = 5449 BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames); 5450 rmon_stats->hist_tx[8] = 5451 BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames); 5452 rmon_stats->hist_tx[9] = 5453 BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames); 5454 5455 *ranges = bnxt_rmon_ranges; 5456 } 5457 5458 static void bnxt_get_ptp_stats(struct net_device *dev, 5459 struct ethtool_ts_stats *ts_stats) 5460 { 5461 struct bnxt *bp = netdev_priv(dev); 5462 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 5463 5464 if (ptp) { 5465 ts_stats->pkts = ptp->stats.ts_pkts; 5466 ts_stats->lost = ptp->stats.ts_lost; 5467 ts_stats->err = atomic64_read(&ptp->stats.ts_err); 5468 } 5469 } 5470 5471 static void bnxt_get_link_ext_stats(struct net_device *dev, 5472 struct ethtool_link_ext_stats *stats) 5473 { 5474 struct bnxt *bp = netdev_priv(dev); 5475 u64 *rx; 5476 5477 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 5478 return; 5479 5480 rx = bp->rx_port_stats_ext.sw_stats; 5481 stats->link_down_events = 5482 *(rx + BNXT_RX_STATS_EXT_OFFSET(link_down_events)); 5483 } 5484 5485 void bnxt_ethtool_free(struct bnxt *bp) 5486 { 5487 kfree(bp->test_info); 5488 bp->test_info = NULL; 5489 } 5490 5491 const struct ethtool_ops bnxt_ethtool_ops = { 5492 .cap_link_lanes_supported = 1, 5493 .rxfh_per_ctx_key = 1, 5494 .rxfh_max_num_contexts = BNXT_MAX_ETH_RSS_CTX + 1, 5495 .rxfh_indir_space = BNXT_MAX_RSS_TABLE_ENTRIES_P5, 5496 .rxfh_priv_size = sizeof(struct bnxt_rss_ctx), 5497 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 5498 ETHTOOL_COALESCE_MAX_FRAMES | 5499 ETHTOOL_COALESCE_USECS_IRQ | 5500 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 5501 ETHTOOL_COALESCE_STATS_BLOCK_USECS | 5502 ETHTOOL_COALESCE_USE_ADAPTIVE_RX | 5503 ETHTOOL_COALESCE_USE_CQE, 5504 .supported_ring_params = ETHTOOL_RING_USE_TCP_DATA_SPLIT | 5505 ETHTOOL_RING_USE_HDS_THRS, 5506 .get_link_ksettings = bnxt_get_link_ksettings, 5507 .set_link_ksettings = bnxt_set_link_ksettings, 5508 .get_fec_stats = bnxt_get_fec_stats, 5509 .get_fecparam = bnxt_get_fecparam, 5510 .set_fecparam = bnxt_set_fecparam, 5511 .get_pause_stats = bnxt_get_pause_stats, 5512 .get_pauseparam = bnxt_get_pauseparam, 5513 .set_pauseparam = bnxt_set_pauseparam, 5514 .get_drvinfo = bnxt_get_drvinfo, 5515 .get_regs_len = bnxt_get_regs_len, 5516 .get_regs = bnxt_get_regs, 5517 .get_wol = bnxt_get_wol, 5518 .set_wol = bnxt_set_wol, 5519 .get_coalesce = bnxt_get_coalesce, 5520 .set_coalesce = bnxt_set_coalesce, 5521 .get_msglevel = bnxt_get_msglevel, 5522 .set_msglevel = bnxt_set_msglevel, 5523 .get_sset_count = bnxt_get_sset_count, 5524 .get_strings = bnxt_get_strings, 5525 .get_ethtool_stats = bnxt_get_ethtool_stats, 5526 .set_ringparam = bnxt_set_ringparam, 5527 .get_ringparam = bnxt_get_ringparam, 5528 .get_channels = bnxt_get_channels, 5529 .set_channels = bnxt_set_channels, 5530 .get_rxnfc = bnxt_get_rxnfc, 5531 .set_rxnfc = bnxt_set_rxnfc, 5532 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 5533 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 5534 .get_rxfh = bnxt_get_rxfh, 5535 .set_rxfh = bnxt_set_rxfh, 5536 .get_rxfh_fields = bnxt_get_rxfh_fields, 5537 .set_rxfh_fields = bnxt_set_rxfh_fields, 5538 .create_rxfh_context = bnxt_create_rxfh_context, 5539 .modify_rxfh_context = bnxt_modify_rxfh_context, 5540 .remove_rxfh_context = bnxt_remove_rxfh_context, 5541 .flash_device = bnxt_flash_device, 5542 .get_eeprom_len = bnxt_get_eeprom_len, 5543 .get_eeprom = bnxt_get_eeprom, 5544 .set_eeprom = bnxt_set_eeprom, 5545 .get_link = bnxt_get_link, 5546 .get_link_ext_stats = bnxt_get_link_ext_stats, 5547 .get_eee = bnxt_get_eee, 5548 .set_eee = bnxt_set_eee, 5549 .get_tunable = bnxt_get_tunable, 5550 .set_tunable = bnxt_set_tunable, 5551 .get_module_info = bnxt_get_module_info, 5552 .get_module_eeprom = bnxt_get_module_eeprom, 5553 .get_module_eeprom_by_page = bnxt_get_module_eeprom_by_page, 5554 .set_module_eeprom_by_page = bnxt_set_module_eeprom_by_page, 5555 .nway_reset = bnxt_nway_reset, 5556 .set_phys_id = bnxt_set_phys_id, 5557 .self_test = bnxt_self_test, 5558 .get_ts_info = bnxt_get_ts_info, 5559 .reset = bnxt_reset, 5560 .set_dump = bnxt_set_dump, 5561 .get_dump_flag = bnxt_get_dump_flag, 5562 .get_dump_data = bnxt_get_dump_data, 5563 .get_eth_phy_stats = bnxt_get_eth_phy_stats, 5564 .get_eth_mac_stats = bnxt_get_eth_mac_stats, 5565 .get_eth_ctrl_stats = bnxt_get_eth_ctrl_stats, 5566 .get_rmon_stats = bnxt_get_rmon_stats, 5567 .get_ts_stats = bnxt_get_ptp_stats, 5568 }; 5569