1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/bitops.h> 12 #include <linux/ctype.h> 13 #include <linux/stringify.h> 14 #include <linux/ethtool.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/linkmode.h> 17 #include <linux/interrupt.h> 18 #include <linux/pci.h> 19 #include <linux/etherdevice.h> 20 #include <linux/crc32.h> 21 #include <linux/firmware.h> 22 #include <linux/utsname.h> 23 #include <linux/time.h> 24 #include <linux/ptp_clock_kernel.h> 25 #include <linux/net_tstamp.h> 26 #include <linux/timecounter.h> 27 #include <net/netlink.h> 28 #include "bnxt_hsi.h" 29 #include "bnxt.h" 30 #include "bnxt_hwrm.h" 31 #include "bnxt_ulp.h" 32 #include "bnxt_xdp.h" 33 #include "bnxt_ptp.h" 34 #include "bnxt_ethtool.h" 35 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 36 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 37 #include "bnxt_coredump.h" 38 39 #define BNXT_NVM_ERR_MSG(dev, extack, msg) \ 40 do { \ 41 if (extack) \ 42 NL_SET_ERR_MSG_MOD(extack, msg); \ 43 netdev_err(dev, "%s\n", msg); \ 44 } while (0) 45 46 static u32 bnxt_get_msglevel(struct net_device *dev) 47 { 48 struct bnxt *bp = netdev_priv(dev); 49 50 return bp->msg_enable; 51 } 52 53 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 54 { 55 struct bnxt *bp = netdev_priv(dev); 56 57 bp->msg_enable = value; 58 } 59 60 static int bnxt_get_coalesce(struct net_device *dev, 61 struct ethtool_coalesce *coal, 62 struct kernel_ethtool_coalesce *kernel_coal, 63 struct netlink_ext_ack *extack) 64 { 65 struct bnxt *bp = netdev_priv(dev); 66 struct bnxt_coal *hw_coal; 67 u16 mult; 68 69 memset(coal, 0, sizeof(*coal)); 70 71 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 72 73 hw_coal = &bp->rx_coal; 74 mult = hw_coal->bufs_per_record; 75 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 76 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 77 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 78 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 79 if (hw_coal->flags & 80 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 81 kernel_coal->use_cqe_mode_rx = true; 82 83 hw_coal = &bp->tx_coal; 84 mult = hw_coal->bufs_per_record; 85 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 86 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 87 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 88 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 89 if (hw_coal->flags & 90 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 91 kernel_coal->use_cqe_mode_tx = true; 92 93 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 94 95 return 0; 96 } 97 98 static int bnxt_set_coalesce(struct net_device *dev, 99 struct ethtool_coalesce *coal, 100 struct kernel_ethtool_coalesce *kernel_coal, 101 struct netlink_ext_ack *extack) 102 { 103 struct bnxt *bp = netdev_priv(dev); 104 bool update_stats = false; 105 struct bnxt_coal *hw_coal; 106 int rc = 0; 107 u16 mult; 108 109 if (coal->use_adaptive_rx_coalesce) { 110 bp->flags |= BNXT_FLAG_DIM; 111 } else { 112 if (bp->flags & BNXT_FLAG_DIM) { 113 bp->flags &= ~(BNXT_FLAG_DIM); 114 goto reset_coalesce; 115 } 116 } 117 118 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) && 119 !(bp->coal_cap.cmpl_params & 120 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)) 121 return -EOPNOTSUPP; 122 123 hw_coal = &bp->rx_coal; 124 mult = hw_coal->bufs_per_record; 125 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 126 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 127 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 128 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 129 hw_coal->flags &= 130 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 131 if (kernel_coal->use_cqe_mode_rx) 132 hw_coal->flags |= 133 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 134 135 hw_coal = &bp->tx_coal; 136 mult = hw_coal->bufs_per_record; 137 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 138 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 139 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 140 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 141 hw_coal->flags &= 142 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 143 if (kernel_coal->use_cqe_mode_tx) 144 hw_coal->flags |= 145 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 146 147 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 148 u32 stats_ticks = coal->stats_block_coalesce_usecs; 149 150 /* Allow 0, which means disable. */ 151 if (stats_ticks) 152 stats_ticks = clamp_t(u32, stats_ticks, 153 BNXT_MIN_STATS_COAL_TICKS, 154 BNXT_MAX_STATS_COAL_TICKS); 155 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 156 bp->stats_coal_ticks = stats_ticks; 157 if (bp->stats_coal_ticks) 158 bp->current_interval = 159 bp->stats_coal_ticks * HZ / 1000000; 160 else 161 bp->current_interval = BNXT_TIMER_INTERVAL; 162 update_stats = true; 163 } 164 165 reset_coalesce: 166 if (test_bit(BNXT_STATE_OPEN, &bp->state)) { 167 if (update_stats) { 168 bnxt_close_nic(bp, true, false); 169 rc = bnxt_open_nic(bp, true, false); 170 } else { 171 rc = bnxt_hwrm_set_coal(bp); 172 } 173 } 174 175 return rc; 176 } 177 178 static const char * const bnxt_ring_rx_stats_str[] = { 179 "rx_ucast_packets", 180 "rx_mcast_packets", 181 "rx_bcast_packets", 182 "rx_discards", 183 "rx_errors", 184 "rx_ucast_bytes", 185 "rx_mcast_bytes", 186 "rx_bcast_bytes", 187 }; 188 189 static const char * const bnxt_ring_tx_stats_str[] = { 190 "tx_ucast_packets", 191 "tx_mcast_packets", 192 "tx_bcast_packets", 193 "tx_errors", 194 "tx_discards", 195 "tx_ucast_bytes", 196 "tx_mcast_bytes", 197 "tx_bcast_bytes", 198 }; 199 200 static const char * const bnxt_ring_tpa_stats_str[] = { 201 "tpa_packets", 202 "tpa_bytes", 203 "tpa_events", 204 "tpa_aborts", 205 }; 206 207 static const char * const bnxt_ring_tpa2_stats_str[] = { 208 "rx_tpa_eligible_pkt", 209 "rx_tpa_eligible_bytes", 210 "rx_tpa_pkt", 211 "rx_tpa_bytes", 212 "rx_tpa_errors", 213 "rx_tpa_events", 214 }; 215 216 static const char * const bnxt_rx_sw_stats_str[] = { 217 "rx_l4_csum_errors", 218 "rx_resets", 219 "rx_buf_errors", 220 }; 221 222 static const char * const bnxt_cmn_sw_stats_str[] = { 223 "missed_irqs", 224 }; 225 226 #define BNXT_RX_STATS_ENTRY(counter) \ 227 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 228 229 #define BNXT_TX_STATS_ENTRY(counter) \ 230 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 231 232 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 233 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 234 235 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 236 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 237 238 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 239 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 240 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 241 242 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 243 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 244 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 245 246 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 247 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 248 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 249 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 250 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 251 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 252 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 253 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 254 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 255 256 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 257 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 258 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 259 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 260 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 261 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 262 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 263 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 264 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 265 266 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 267 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 268 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 269 270 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 271 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 272 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 273 274 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 275 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 276 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 277 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 278 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 279 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 280 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 281 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 282 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 283 284 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 285 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 286 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 287 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 288 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 289 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 290 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 291 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 292 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 293 294 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 295 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 296 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 297 298 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 299 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 300 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 301 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 302 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 303 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 304 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 305 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 306 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 307 308 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 309 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 310 __stringify(counter##_pri##n) } 311 312 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 313 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 314 __stringify(counter##_pri##n) } 315 316 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 317 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 318 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 319 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 320 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 321 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 322 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 323 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 324 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 325 326 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 327 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 328 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 329 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 330 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 331 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 332 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 333 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 334 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 335 336 enum { 337 RX_TOTAL_DISCARDS, 338 TX_TOTAL_DISCARDS, 339 RX_NETPOLL_DISCARDS, 340 }; 341 342 static const char *const bnxt_ring_err_stats_arr[] = { 343 "rx_total_l4_csum_errors", 344 "rx_total_resets", 345 "rx_total_buf_errors", 346 "rx_total_oom_discards", 347 "rx_total_netpoll_discards", 348 "rx_total_ring_discards", 349 "tx_total_resets", 350 "tx_total_ring_discards", 351 "total_missed_irqs", 352 }; 353 354 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str) 355 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str) 356 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str) 357 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str) 358 359 static const struct { 360 long offset; 361 char string[ETH_GSTRING_LEN]; 362 } bnxt_port_stats_arr[] = { 363 BNXT_RX_STATS_ENTRY(rx_64b_frames), 364 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 365 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 366 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 367 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 368 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 369 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 370 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 371 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 372 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 373 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 374 BNXT_RX_STATS_ENTRY(rx_total_frames), 375 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 376 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 377 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 378 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 379 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 380 BNXT_RX_STATS_ENTRY(rx_pause_frames), 381 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 382 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 383 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 384 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 385 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 386 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 387 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 388 BNXT_RX_STATS_ENTRY(rx_good_frames), 389 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 390 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 391 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 392 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 393 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 394 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 395 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 396 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 397 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 398 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 399 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 400 BNXT_RX_STATS_ENTRY(rx_bytes), 401 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 402 BNXT_RX_STATS_ENTRY(rx_runt_frames), 403 BNXT_RX_STATS_ENTRY(rx_stat_discard), 404 BNXT_RX_STATS_ENTRY(rx_stat_err), 405 406 BNXT_TX_STATS_ENTRY(tx_64b_frames), 407 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 408 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 409 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 410 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 411 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 412 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 413 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 414 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 415 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 416 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 417 BNXT_TX_STATS_ENTRY(tx_good_frames), 418 BNXT_TX_STATS_ENTRY(tx_total_frames), 419 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 420 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 421 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 422 BNXT_TX_STATS_ENTRY(tx_pause_frames), 423 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 424 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 425 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 426 BNXT_TX_STATS_ENTRY(tx_err), 427 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 428 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 429 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 430 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 431 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 432 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 433 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 434 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 435 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 436 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 437 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 438 BNXT_TX_STATS_ENTRY(tx_total_collisions), 439 BNXT_TX_STATS_ENTRY(tx_bytes), 440 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 441 BNXT_TX_STATS_ENTRY(tx_stat_discard), 442 BNXT_TX_STATS_ENTRY(tx_stat_error), 443 }; 444 445 static const struct { 446 long offset; 447 char string[ETH_GSTRING_LEN]; 448 } bnxt_port_stats_ext_arr[] = { 449 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 450 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 451 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 452 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 453 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 454 BNXT_RX_STATS_EXT_COS_ENTRIES, 455 BNXT_RX_STATS_EXT_PFC_ENTRIES, 456 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 457 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 458 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 459 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 460 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 461 BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks), 462 BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks), 463 BNXT_RX_STATS_EXT_ENTRY(rx_filter_miss), 464 }; 465 466 static const struct { 467 long offset; 468 char string[ETH_GSTRING_LEN]; 469 } bnxt_tx_port_stats_ext_arr[] = { 470 BNXT_TX_STATS_EXT_COS_ENTRIES, 471 BNXT_TX_STATS_EXT_PFC_ENTRIES, 472 }; 473 474 static const struct { 475 long base_off; 476 char string[ETH_GSTRING_LEN]; 477 } bnxt_rx_bytes_pri_arr[] = { 478 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 479 }; 480 481 static const struct { 482 long base_off; 483 char string[ETH_GSTRING_LEN]; 484 } bnxt_rx_pkts_pri_arr[] = { 485 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 486 }; 487 488 static const struct { 489 long base_off; 490 char string[ETH_GSTRING_LEN]; 491 } bnxt_tx_bytes_pri_arr[] = { 492 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 493 }; 494 495 static const struct { 496 long base_off; 497 char string[ETH_GSTRING_LEN]; 498 } bnxt_tx_pkts_pri_arr[] = { 499 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 500 }; 501 502 #define BNXT_NUM_RING_ERR_STATS ARRAY_SIZE(bnxt_ring_err_stats_arr) 503 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 504 #define BNXT_NUM_STATS_PRI \ 505 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 506 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 507 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 508 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 509 510 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 511 { 512 if (BNXT_SUPPORTS_TPA(bp)) { 513 if (bp->max_tpa_v2) { 514 if (BNXT_CHIP_P5(bp)) 515 return BNXT_NUM_TPA_RING_STATS_P5; 516 return BNXT_NUM_TPA_RING_STATS_P7; 517 } 518 return BNXT_NUM_TPA_RING_STATS; 519 } 520 return 0; 521 } 522 523 static int bnxt_get_num_ring_stats(struct bnxt *bp) 524 { 525 int rx, tx, cmn; 526 527 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS + 528 bnxt_get_num_tpa_ring_stats(bp); 529 tx = NUM_RING_TX_HW_STATS; 530 cmn = NUM_RING_CMN_SW_STATS; 531 return rx * bp->rx_nr_rings + 532 tx * (bp->tx_nr_rings_xdp + bp->tx_nr_rings_per_tc) + 533 cmn * bp->cp_nr_rings; 534 } 535 536 static int bnxt_get_num_stats(struct bnxt *bp) 537 { 538 int num_stats = bnxt_get_num_ring_stats(bp); 539 int len; 540 541 num_stats += BNXT_NUM_RING_ERR_STATS; 542 543 if (bp->flags & BNXT_FLAG_PORT_STATS) 544 num_stats += BNXT_NUM_PORT_STATS; 545 546 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 547 len = min_t(int, bp->fw_rx_stats_ext_size, 548 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 549 num_stats += len; 550 len = min_t(int, bp->fw_tx_stats_ext_size, 551 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 552 num_stats += len; 553 if (bp->pri2cos_valid) 554 num_stats += BNXT_NUM_STATS_PRI; 555 } 556 557 return num_stats; 558 } 559 560 static int bnxt_get_sset_count(struct net_device *dev, int sset) 561 { 562 struct bnxt *bp = netdev_priv(dev); 563 564 switch (sset) { 565 case ETH_SS_STATS: 566 return bnxt_get_num_stats(bp); 567 case ETH_SS_TEST: 568 if (!bp->num_tests) 569 return -EOPNOTSUPP; 570 return bp->num_tests; 571 default: 572 return -EOPNOTSUPP; 573 } 574 } 575 576 static bool is_rx_ring(struct bnxt *bp, int ring_num) 577 { 578 return ring_num < bp->rx_nr_rings; 579 } 580 581 static bool is_tx_ring(struct bnxt *bp, int ring_num) 582 { 583 int tx_base = 0; 584 585 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 586 tx_base = bp->rx_nr_rings; 587 588 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings)) 589 return true; 590 return false; 591 } 592 593 static void bnxt_get_ethtool_stats(struct net_device *dev, 594 struct ethtool_stats *stats, u64 *buf) 595 { 596 struct bnxt_total_ring_err_stats ring_err_stats = {0}; 597 struct bnxt *bp = netdev_priv(dev); 598 u64 *curr, *prev; 599 u32 tpa_stats; 600 u32 i, j = 0; 601 602 if (!bp->bnapi) { 603 j += bnxt_get_num_ring_stats(bp); 604 goto skip_ring_stats; 605 } 606 607 tpa_stats = bnxt_get_num_tpa_ring_stats(bp); 608 for (i = 0; i < bp->cp_nr_rings; i++) { 609 struct bnxt_napi *bnapi = bp->bnapi[i]; 610 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 611 u64 *sw_stats = cpr->stats.sw_stats; 612 u64 *sw; 613 int k; 614 615 if (is_rx_ring(bp, i)) { 616 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++) 617 buf[j] = sw_stats[k]; 618 } 619 if (is_tx_ring(bp, i)) { 620 k = NUM_RING_RX_HW_STATS; 621 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 622 j++, k++) 623 buf[j] = sw_stats[k]; 624 } 625 if (!tpa_stats || !is_rx_ring(bp, i)) 626 goto skip_tpa_ring_stats; 627 628 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 629 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS + 630 tpa_stats; j++, k++) 631 buf[j] = sw_stats[k]; 632 633 skip_tpa_ring_stats: 634 sw = (u64 *)&cpr->sw_stats.rx; 635 if (is_rx_ring(bp, i)) { 636 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++) 637 buf[j] = sw[k]; 638 } 639 640 sw = (u64 *)&cpr->sw_stats.cmn; 641 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++) 642 buf[j] = sw[k]; 643 } 644 645 bnxt_get_ring_err_stats(bp, &ring_err_stats); 646 647 skip_ring_stats: 648 curr = &ring_err_stats.rx_total_l4_csum_errors; 649 prev = &bp->ring_err_stats_prev.rx_total_l4_csum_errors; 650 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++, j++, curr++, prev++) 651 buf[j] = *curr + *prev; 652 653 if (bp->flags & BNXT_FLAG_PORT_STATS) { 654 u64 *port_stats = bp->port_stats.sw_stats; 655 656 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) 657 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset); 658 } 659 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 660 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats; 661 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats; 662 u32 len; 663 664 len = min_t(u32, bp->fw_rx_stats_ext_size, 665 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 666 for (i = 0; i < len; i++, j++) { 667 buf[j] = *(rx_port_stats_ext + 668 bnxt_port_stats_ext_arr[i].offset); 669 } 670 len = min_t(u32, bp->fw_tx_stats_ext_size, 671 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 672 for (i = 0; i < len; i++, j++) { 673 buf[j] = *(tx_port_stats_ext + 674 bnxt_tx_port_stats_ext_arr[i].offset); 675 } 676 if (bp->pri2cos_valid) { 677 for (i = 0; i < 8; i++, j++) { 678 long n = bnxt_rx_bytes_pri_arr[i].base_off + 679 bp->pri2cos_idx[i]; 680 681 buf[j] = *(rx_port_stats_ext + n); 682 } 683 for (i = 0; i < 8; i++, j++) { 684 long n = bnxt_rx_pkts_pri_arr[i].base_off + 685 bp->pri2cos_idx[i]; 686 687 buf[j] = *(rx_port_stats_ext + n); 688 } 689 for (i = 0; i < 8; i++, j++) { 690 long n = bnxt_tx_bytes_pri_arr[i].base_off + 691 bp->pri2cos_idx[i]; 692 693 buf[j] = *(tx_port_stats_ext + n); 694 } 695 for (i = 0; i < 8; i++, j++) { 696 long n = bnxt_tx_pkts_pri_arr[i].base_off + 697 bp->pri2cos_idx[i]; 698 699 buf[j] = *(tx_port_stats_ext + n); 700 } 701 } 702 } 703 } 704 705 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 706 { 707 struct bnxt *bp = netdev_priv(dev); 708 static const char * const *str; 709 u32 i, j, num_str; 710 711 switch (stringset) { 712 case ETH_SS_STATS: 713 for (i = 0; i < bp->cp_nr_rings; i++) { 714 if (is_rx_ring(bp, i)) { 715 num_str = NUM_RING_RX_HW_STATS; 716 for (j = 0; j < num_str; j++) { 717 sprintf(buf, "[%d]: %s", i, 718 bnxt_ring_rx_stats_str[j]); 719 buf += ETH_GSTRING_LEN; 720 } 721 } 722 if (is_tx_ring(bp, i)) { 723 num_str = NUM_RING_TX_HW_STATS; 724 for (j = 0; j < num_str; j++) { 725 sprintf(buf, "[%d]: %s", i, 726 bnxt_ring_tx_stats_str[j]); 727 buf += ETH_GSTRING_LEN; 728 } 729 } 730 num_str = bnxt_get_num_tpa_ring_stats(bp); 731 if (!num_str || !is_rx_ring(bp, i)) 732 goto skip_tpa_stats; 733 734 if (bp->max_tpa_v2) 735 str = bnxt_ring_tpa2_stats_str; 736 else 737 str = bnxt_ring_tpa_stats_str; 738 739 for (j = 0; j < num_str; j++) { 740 sprintf(buf, "[%d]: %s", i, str[j]); 741 buf += ETH_GSTRING_LEN; 742 } 743 skip_tpa_stats: 744 if (is_rx_ring(bp, i)) { 745 num_str = NUM_RING_RX_SW_STATS; 746 for (j = 0; j < num_str; j++) { 747 sprintf(buf, "[%d]: %s", i, 748 bnxt_rx_sw_stats_str[j]); 749 buf += ETH_GSTRING_LEN; 750 } 751 } 752 num_str = NUM_RING_CMN_SW_STATS; 753 for (j = 0; j < num_str; j++) { 754 sprintf(buf, "[%d]: %s", i, 755 bnxt_cmn_sw_stats_str[j]); 756 buf += ETH_GSTRING_LEN; 757 } 758 } 759 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++) { 760 strscpy(buf, bnxt_ring_err_stats_arr[i], ETH_GSTRING_LEN); 761 buf += ETH_GSTRING_LEN; 762 } 763 764 if (bp->flags & BNXT_FLAG_PORT_STATS) { 765 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 766 strcpy(buf, bnxt_port_stats_arr[i].string); 767 buf += ETH_GSTRING_LEN; 768 } 769 } 770 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 771 u32 len; 772 773 len = min_t(u32, bp->fw_rx_stats_ext_size, 774 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 775 for (i = 0; i < len; i++) { 776 strcpy(buf, bnxt_port_stats_ext_arr[i].string); 777 buf += ETH_GSTRING_LEN; 778 } 779 len = min_t(u32, bp->fw_tx_stats_ext_size, 780 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 781 for (i = 0; i < len; i++) { 782 strcpy(buf, 783 bnxt_tx_port_stats_ext_arr[i].string); 784 buf += ETH_GSTRING_LEN; 785 } 786 if (bp->pri2cos_valid) { 787 for (i = 0; i < 8; i++) { 788 strcpy(buf, 789 bnxt_rx_bytes_pri_arr[i].string); 790 buf += ETH_GSTRING_LEN; 791 } 792 for (i = 0; i < 8; i++) { 793 strcpy(buf, 794 bnxt_rx_pkts_pri_arr[i].string); 795 buf += ETH_GSTRING_LEN; 796 } 797 for (i = 0; i < 8; i++) { 798 strcpy(buf, 799 bnxt_tx_bytes_pri_arr[i].string); 800 buf += ETH_GSTRING_LEN; 801 } 802 for (i = 0; i < 8; i++) { 803 strcpy(buf, 804 bnxt_tx_pkts_pri_arr[i].string); 805 buf += ETH_GSTRING_LEN; 806 } 807 } 808 } 809 break; 810 case ETH_SS_TEST: 811 if (bp->num_tests) 812 memcpy(buf, bp->test_info->string, 813 bp->num_tests * ETH_GSTRING_LEN); 814 break; 815 default: 816 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 817 stringset); 818 break; 819 } 820 } 821 822 static void bnxt_get_ringparam(struct net_device *dev, 823 struct ethtool_ringparam *ering, 824 struct kernel_ethtool_ringparam *kernel_ering, 825 struct netlink_ext_ack *extack) 826 { 827 struct bnxt *bp = netdev_priv(dev); 828 829 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 830 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA; 831 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 832 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_ENABLED; 833 } else { 834 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 835 ering->rx_jumbo_max_pending = 0; 836 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_DISABLED; 837 } 838 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 839 840 ering->rx_pending = bp->rx_ring_size; 841 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 842 ering->tx_pending = bp->tx_ring_size; 843 } 844 845 static int bnxt_set_ringparam(struct net_device *dev, 846 struct ethtool_ringparam *ering, 847 struct kernel_ethtool_ringparam *kernel_ering, 848 struct netlink_ext_ack *extack) 849 { 850 struct bnxt *bp = netdev_priv(dev); 851 852 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 853 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 854 (ering->tx_pending < BNXT_MIN_TX_DESC_CNT)) 855 return -EINVAL; 856 857 if (netif_running(dev)) 858 bnxt_close_nic(bp, false, false); 859 860 bp->rx_ring_size = ering->rx_pending; 861 bp->tx_ring_size = ering->tx_pending; 862 bnxt_set_ring_params(bp); 863 864 if (netif_running(dev)) 865 return bnxt_open_nic(bp, false, false); 866 867 return 0; 868 } 869 870 static void bnxt_get_channels(struct net_device *dev, 871 struct ethtool_channels *channel) 872 { 873 struct bnxt *bp = netdev_priv(dev); 874 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 875 int max_rx_rings, max_tx_rings, tcs; 876 int max_tx_sch_inputs, tx_grps; 877 878 /* Get the most up-to-date max_tx_sch_inputs. */ 879 if (netif_running(dev) && BNXT_NEW_RM(bp)) 880 bnxt_hwrm_func_resc_qcaps(bp, false); 881 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 882 883 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 884 if (max_tx_sch_inputs) 885 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 886 887 tcs = bp->num_tc; 888 tx_grps = max(tcs, 1); 889 if (bp->tx_nr_rings_xdp) 890 tx_grps++; 891 max_tx_rings /= tx_grps; 892 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 893 894 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 895 max_rx_rings = 0; 896 max_tx_rings = 0; 897 } 898 if (max_tx_sch_inputs) 899 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 900 901 if (tcs > 1) 902 max_tx_rings /= tcs; 903 904 channel->max_rx = max_rx_rings; 905 channel->max_tx = max_tx_rings; 906 channel->max_other = 0; 907 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 908 channel->combined_count = bp->rx_nr_rings; 909 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 910 channel->combined_count--; 911 } else { 912 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 913 channel->rx_count = bp->rx_nr_rings; 914 channel->tx_count = bp->tx_nr_rings_per_tc; 915 } 916 } 917 } 918 919 static int bnxt_set_channels(struct net_device *dev, 920 struct ethtool_channels *channel) 921 { 922 struct bnxt *bp = netdev_priv(dev); 923 int req_tx_rings, req_rx_rings, tcs; 924 bool sh = false; 925 int tx_xdp = 0; 926 int rc = 0; 927 int tx_cp; 928 929 if (channel->other_count) 930 return -EINVAL; 931 932 if (!channel->combined_count && 933 (!channel->rx_count || !channel->tx_count)) 934 return -EINVAL; 935 936 if (channel->combined_count && 937 (channel->rx_count || channel->tx_count)) 938 return -EINVAL; 939 940 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 941 channel->tx_count)) 942 return -EINVAL; 943 944 if (channel->combined_count) 945 sh = true; 946 947 tcs = bp->num_tc; 948 949 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 950 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 951 if (bp->tx_nr_rings_xdp) { 952 if (!sh) { 953 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 954 return -EINVAL; 955 } 956 tx_xdp = req_rx_rings; 957 } 958 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 959 if (rc) { 960 netdev_warn(dev, "Unable to allocate the requested rings\n"); 961 return rc; 962 } 963 964 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) != 965 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) && 966 netif_is_rxfh_configured(dev)) { 967 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n"); 968 return -EINVAL; 969 } 970 971 bnxt_clear_usr_fltrs(bp, true); 972 if (BNXT_SUPPORTS_MULTI_RSS_CTX(bp)) 973 bnxt_clear_rss_ctxs(bp, false); 974 if (netif_running(dev)) { 975 if (BNXT_PF(bp)) { 976 /* TODO CHIMP_FW: Send message to all VF's 977 * before PF unload 978 */ 979 } 980 bnxt_close_nic(bp, true, false); 981 } 982 983 if (sh) { 984 bp->flags |= BNXT_FLAG_SHARED_RINGS; 985 bp->rx_nr_rings = channel->combined_count; 986 bp->tx_nr_rings_per_tc = channel->combined_count; 987 } else { 988 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 989 bp->rx_nr_rings = channel->rx_count; 990 bp->tx_nr_rings_per_tc = channel->tx_count; 991 } 992 bp->tx_nr_rings_xdp = tx_xdp; 993 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 994 if (tcs > 1) 995 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 996 997 tx_cp = bnxt_num_tx_to_cp(bp, bp->tx_nr_rings); 998 bp->cp_nr_rings = sh ? max_t(int, tx_cp, bp->rx_nr_rings) : 999 tx_cp + bp->rx_nr_rings; 1000 1001 /* After changing number of rx channels, update NTUPLE feature. */ 1002 netdev_update_features(dev); 1003 if (netif_running(dev)) { 1004 rc = bnxt_open_nic(bp, true, false); 1005 if ((!rc) && BNXT_PF(bp)) { 1006 /* TODO CHIMP_FW: Send message to all VF's 1007 * to renable 1008 */ 1009 } 1010 } else { 1011 rc = bnxt_reserve_rings(bp, true); 1012 } 1013 1014 return rc; 1015 } 1016 1017 static u32 bnxt_get_all_fltr_ids_rcu(struct bnxt *bp, struct hlist_head tbl[], 1018 int tbl_size, u32 *ids, u32 start, 1019 u32 id_cnt) 1020 { 1021 int i, j = start; 1022 1023 if (j >= id_cnt) 1024 return j; 1025 for (i = 0; i < tbl_size; i++) { 1026 struct hlist_head *head; 1027 struct bnxt_filter_base *fltr; 1028 1029 head = &tbl[i]; 1030 hlist_for_each_entry_rcu(fltr, head, hash) { 1031 if (!fltr->flags || 1032 test_bit(BNXT_FLTR_FW_DELETED, &fltr->state)) 1033 continue; 1034 ids[j++] = fltr->sw_id; 1035 if (j == id_cnt) 1036 return j; 1037 } 1038 } 1039 return j; 1040 } 1041 1042 static struct bnxt_filter_base *bnxt_get_one_fltr_rcu(struct bnxt *bp, 1043 struct hlist_head tbl[], 1044 int tbl_size, u32 id) 1045 { 1046 int i; 1047 1048 for (i = 0; i < tbl_size; i++) { 1049 struct hlist_head *head; 1050 struct bnxt_filter_base *fltr; 1051 1052 head = &tbl[i]; 1053 hlist_for_each_entry_rcu(fltr, head, hash) { 1054 if (fltr->flags && fltr->sw_id == id) 1055 return fltr; 1056 } 1057 } 1058 return NULL; 1059 } 1060 1061 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 1062 u32 *rule_locs) 1063 { 1064 u32 count; 1065 1066 cmd->data = bp->ntp_fltr_count; 1067 rcu_read_lock(); 1068 count = bnxt_get_all_fltr_ids_rcu(bp, bp->l2_fltr_hash_tbl, 1069 BNXT_L2_FLTR_HASH_SIZE, rule_locs, 0, 1070 cmd->rule_cnt); 1071 cmd->rule_cnt = bnxt_get_all_fltr_ids_rcu(bp, bp->ntp_fltr_hash_tbl, 1072 BNXT_NTP_FLTR_HASH_SIZE, 1073 rule_locs, count, 1074 cmd->rule_cnt); 1075 rcu_read_unlock(); 1076 1077 return 0; 1078 } 1079 1080 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1081 { 1082 struct ethtool_rx_flow_spec *fs = 1083 (struct ethtool_rx_flow_spec *)&cmd->fs; 1084 struct bnxt_filter_base *fltr_base; 1085 struct bnxt_ntuple_filter *fltr; 1086 struct bnxt_flow_masks *fmasks; 1087 struct flow_keys *fkeys; 1088 int rc = -EINVAL; 1089 1090 if (fs->location >= bp->max_fltr) 1091 return rc; 1092 1093 rcu_read_lock(); 1094 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl, 1095 BNXT_L2_FLTR_HASH_SIZE, 1096 fs->location); 1097 if (fltr_base) { 1098 struct ethhdr *h_ether = &fs->h_u.ether_spec; 1099 struct ethhdr *m_ether = &fs->m_u.ether_spec; 1100 struct bnxt_l2_filter *l2_fltr; 1101 struct bnxt_l2_key *l2_key; 1102 1103 l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base); 1104 l2_key = &l2_fltr->l2_key; 1105 fs->flow_type = ETHER_FLOW; 1106 ether_addr_copy(h_ether->h_dest, l2_key->dst_mac_addr); 1107 eth_broadcast_addr(m_ether->h_dest); 1108 if (l2_key->vlan) { 1109 struct ethtool_flow_ext *m_ext = &fs->m_ext; 1110 struct ethtool_flow_ext *h_ext = &fs->h_ext; 1111 1112 fs->flow_type |= FLOW_EXT; 1113 m_ext->vlan_tci = htons(0xfff); 1114 h_ext->vlan_tci = htons(l2_key->vlan); 1115 } 1116 if (fltr_base->flags & BNXT_ACT_RING_DST) 1117 fs->ring_cookie = fltr_base->rxq; 1118 if (fltr_base->flags & BNXT_ACT_FUNC_DST) 1119 fs->ring_cookie = (u64)(fltr_base->vf_idx + 1) << 1120 ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 1121 rcu_read_unlock(); 1122 return 0; 1123 } 1124 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl, 1125 BNXT_NTP_FLTR_HASH_SIZE, 1126 fs->location); 1127 if (!fltr_base) { 1128 rcu_read_unlock(); 1129 return rc; 1130 } 1131 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base); 1132 1133 fkeys = &fltr->fkeys; 1134 fmasks = &fltr->fmasks; 1135 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 1136 if (fkeys->basic.ip_proto == IPPROTO_ICMP || 1137 fkeys->basic.ip_proto == IPPROTO_RAW) { 1138 fs->flow_type = IP_USER_FLOW; 1139 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 1140 if (fkeys->basic.ip_proto == IPPROTO_ICMP) 1141 fs->h_u.usr_ip4_spec.proto = IPPROTO_ICMP; 1142 else 1143 fs->h_u.usr_ip4_spec.proto = IPPROTO_RAW; 1144 fs->m_u.usr_ip4_spec.proto = BNXT_IP_PROTO_FULL_MASK; 1145 } else if (fkeys->basic.ip_proto == IPPROTO_TCP) { 1146 fs->flow_type = TCP_V4_FLOW; 1147 } else if (fkeys->basic.ip_proto == IPPROTO_UDP) { 1148 fs->flow_type = UDP_V4_FLOW; 1149 } else { 1150 goto fltr_err; 1151 } 1152 1153 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 1154 fs->m_u.tcp_ip4_spec.ip4src = fmasks->addrs.v4addrs.src; 1155 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 1156 fs->m_u.tcp_ip4_spec.ip4dst = fmasks->addrs.v4addrs.dst; 1157 if (fs->flow_type == TCP_V4_FLOW || 1158 fs->flow_type == UDP_V4_FLOW) { 1159 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 1160 fs->m_u.tcp_ip4_spec.psrc = fmasks->ports.src; 1161 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 1162 fs->m_u.tcp_ip4_spec.pdst = fmasks->ports.dst; 1163 } 1164 } else { 1165 if (fkeys->basic.ip_proto == IPPROTO_ICMPV6 || 1166 fkeys->basic.ip_proto == IPPROTO_RAW) { 1167 fs->flow_type = IPV6_USER_FLOW; 1168 if (fkeys->basic.ip_proto == IPPROTO_ICMPV6) 1169 fs->h_u.usr_ip6_spec.l4_proto = IPPROTO_ICMPV6; 1170 else 1171 fs->h_u.usr_ip6_spec.l4_proto = IPPROTO_RAW; 1172 fs->m_u.usr_ip6_spec.l4_proto = BNXT_IP_PROTO_FULL_MASK; 1173 } else if (fkeys->basic.ip_proto == IPPROTO_TCP) { 1174 fs->flow_type = TCP_V6_FLOW; 1175 } else if (fkeys->basic.ip_proto == IPPROTO_UDP) { 1176 fs->flow_type = UDP_V6_FLOW; 1177 } else { 1178 goto fltr_err; 1179 } 1180 1181 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 1182 fkeys->addrs.v6addrs.src; 1183 *(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6src[0] = 1184 fmasks->addrs.v6addrs.src; 1185 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 1186 fkeys->addrs.v6addrs.dst; 1187 *(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6dst[0] = 1188 fmasks->addrs.v6addrs.dst; 1189 if (fs->flow_type == TCP_V6_FLOW || 1190 fs->flow_type == UDP_V6_FLOW) { 1191 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 1192 fs->m_u.tcp_ip6_spec.psrc = fmasks->ports.src; 1193 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 1194 fs->m_u.tcp_ip6_spec.pdst = fmasks->ports.dst; 1195 } 1196 } 1197 1198 if (fltr->base.flags & BNXT_ACT_DROP) 1199 fs->ring_cookie = RX_CLS_FLOW_DISC; 1200 else 1201 fs->ring_cookie = fltr->base.rxq; 1202 rc = 0; 1203 1204 fltr_err: 1205 rcu_read_unlock(); 1206 1207 return rc; 1208 } 1209 1210 static struct bnxt_rss_ctx *bnxt_get_rss_ctx_from_index(struct bnxt *bp, 1211 u32 index) 1212 { 1213 struct bnxt_rss_ctx *rss_ctx, *tmp; 1214 1215 list_for_each_entry_safe(rss_ctx, tmp, &bp->rss_ctx_list, list) 1216 if (rss_ctx->index == index) 1217 return rss_ctx; 1218 return NULL; 1219 } 1220 1221 static int bnxt_alloc_rss_ctx_rss_table(struct bnxt *bp, 1222 struct bnxt_rss_ctx *rss_ctx) 1223 { 1224 int size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5); 1225 struct bnxt_vnic_info *vnic = &rss_ctx->vnic; 1226 1227 vnic->rss_table_size = size + HW_HASH_KEY_SIZE; 1228 vnic->rss_table = dma_alloc_coherent(&bp->pdev->dev, 1229 vnic->rss_table_size, 1230 &vnic->rss_table_dma_addr, 1231 GFP_KERNEL); 1232 if (!vnic->rss_table) 1233 return -ENOMEM; 1234 1235 vnic->rss_hash_key = ((void *)vnic->rss_table) + size; 1236 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; 1237 return 0; 1238 } 1239 1240 static int bnxt_add_l2_cls_rule(struct bnxt *bp, 1241 struct ethtool_rx_flow_spec *fs) 1242 { 1243 u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1244 u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1245 struct ethhdr *h_ether = &fs->h_u.ether_spec; 1246 struct ethhdr *m_ether = &fs->m_u.ether_spec; 1247 struct bnxt_l2_filter *fltr; 1248 struct bnxt_l2_key key; 1249 u16 vnic_id; 1250 u8 flags; 1251 int rc; 1252 1253 if (BNXT_CHIP_P5_PLUS(bp)) 1254 return -EOPNOTSUPP; 1255 1256 if (!is_broadcast_ether_addr(m_ether->h_dest)) 1257 return -EINVAL; 1258 ether_addr_copy(key.dst_mac_addr, h_ether->h_dest); 1259 key.vlan = 0; 1260 if (fs->flow_type & FLOW_EXT) { 1261 struct ethtool_flow_ext *m_ext = &fs->m_ext; 1262 struct ethtool_flow_ext *h_ext = &fs->h_ext; 1263 1264 if (m_ext->vlan_tci != htons(0xfff) || !h_ext->vlan_tci) 1265 return -EINVAL; 1266 key.vlan = ntohs(h_ext->vlan_tci); 1267 } 1268 1269 if (vf) { 1270 flags = BNXT_ACT_FUNC_DST; 1271 vnic_id = 0xffff; 1272 vf--; 1273 } else { 1274 flags = BNXT_ACT_RING_DST; 1275 vnic_id = bp->vnic_info[ring + 1].fw_vnic_id; 1276 } 1277 fltr = bnxt_alloc_new_l2_filter(bp, &key, flags); 1278 if (IS_ERR(fltr)) 1279 return PTR_ERR(fltr); 1280 1281 fltr->base.fw_vnic_id = vnic_id; 1282 fltr->base.rxq = ring; 1283 fltr->base.vf_idx = vf; 1284 rc = bnxt_hwrm_l2_filter_alloc(bp, fltr); 1285 if (rc) 1286 bnxt_del_l2_filter(bp, fltr); 1287 else 1288 fs->location = fltr->base.sw_id; 1289 return rc; 1290 } 1291 1292 static bool bnxt_verify_ntuple_ip4_flow(struct ethtool_usrip4_spec *ip_spec, 1293 struct ethtool_usrip4_spec *ip_mask) 1294 { 1295 if (ip_mask->l4_4_bytes || ip_mask->tos || 1296 ip_spec->ip_ver != ETH_RX_NFC_IP4 || 1297 ip_mask->proto != BNXT_IP_PROTO_FULL_MASK || 1298 (ip_spec->proto != IPPROTO_RAW && ip_spec->proto != IPPROTO_ICMP)) 1299 return false; 1300 return true; 1301 } 1302 1303 static bool bnxt_verify_ntuple_ip6_flow(struct ethtool_usrip6_spec *ip_spec, 1304 struct ethtool_usrip6_spec *ip_mask) 1305 { 1306 if (ip_mask->l4_4_bytes || ip_mask->tclass || 1307 ip_mask->l4_proto != BNXT_IP_PROTO_FULL_MASK || 1308 (ip_spec->l4_proto != IPPROTO_RAW && 1309 ip_spec->l4_proto != IPPROTO_ICMPV6)) 1310 return false; 1311 return true; 1312 } 1313 1314 static int bnxt_add_ntuple_cls_rule(struct bnxt *bp, 1315 struct ethtool_rxnfc *cmd) 1316 { 1317 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1318 struct bnxt_ntuple_filter *new_fltr, *fltr; 1319 u32 flow_type = fs->flow_type & 0xff; 1320 struct bnxt_l2_filter *l2_fltr; 1321 struct bnxt_flow_masks *fmasks; 1322 struct flow_keys *fkeys; 1323 u32 idx, ring; 1324 int rc; 1325 u8 vf; 1326 1327 if (!bp->vnic_info) 1328 return -EAGAIN; 1329 1330 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1331 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1332 if ((fs->flow_type & (FLOW_MAC_EXT | FLOW_EXT)) || vf) 1333 return -EOPNOTSUPP; 1334 1335 if (flow_type == IP_USER_FLOW) { 1336 if (!bnxt_verify_ntuple_ip4_flow(&fs->h_u.usr_ip4_spec, 1337 &fs->m_u.usr_ip4_spec)) 1338 return -EOPNOTSUPP; 1339 } 1340 1341 if (flow_type == IPV6_USER_FLOW) { 1342 if (!bnxt_verify_ntuple_ip6_flow(&fs->h_u.usr_ip6_spec, 1343 &fs->m_u.usr_ip6_spec)) 1344 return -EOPNOTSUPP; 1345 } 1346 1347 new_fltr = kzalloc(sizeof(*new_fltr), GFP_KERNEL); 1348 if (!new_fltr) 1349 return -ENOMEM; 1350 1351 l2_fltr = bp->vnic_info[BNXT_VNIC_DEFAULT].l2_filters[0]; 1352 atomic_inc(&l2_fltr->refcnt); 1353 new_fltr->l2_fltr = l2_fltr; 1354 fmasks = &new_fltr->fmasks; 1355 fkeys = &new_fltr->fkeys; 1356 1357 rc = -EOPNOTSUPP; 1358 switch (flow_type) { 1359 case IP_USER_FLOW: { 1360 struct ethtool_usrip4_spec *ip_spec = &fs->h_u.usr_ip4_spec; 1361 struct ethtool_usrip4_spec *ip_mask = &fs->m_u.usr_ip4_spec; 1362 1363 fkeys->basic.ip_proto = ip_spec->proto; 1364 fkeys->basic.n_proto = htons(ETH_P_IP); 1365 fkeys->addrs.v4addrs.src = ip_spec->ip4src; 1366 fmasks->addrs.v4addrs.src = ip_mask->ip4src; 1367 fkeys->addrs.v4addrs.dst = ip_spec->ip4dst; 1368 fmasks->addrs.v4addrs.dst = ip_mask->ip4dst; 1369 break; 1370 } 1371 case TCP_V4_FLOW: 1372 case UDP_V4_FLOW: { 1373 struct ethtool_tcpip4_spec *ip_spec = &fs->h_u.tcp_ip4_spec; 1374 struct ethtool_tcpip4_spec *ip_mask = &fs->m_u.tcp_ip4_spec; 1375 1376 fkeys->basic.ip_proto = IPPROTO_TCP; 1377 if (flow_type == UDP_V4_FLOW) 1378 fkeys->basic.ip_proto = IPPROTO_UDP; 1379 fkeys->basic.n_proto = htons(ETH_P_IP); 1380 fkeys->addrs.v4addrs.src = ip_spec->ip4src; 1381 fmasks->addrs.v4addrs.src = ip_mask->ip4src; 1382 fkeys->addrs.v4addrs.dst = ip_spec->ip4dst; 1383 fmasks->addrs.v4addrs.dst = ip_mask->ip4dst; 1384 fkeys->ports.src = ip_spec->psrc; 1385 fmasks->ports.src = ip_mask->psrc; 1386 fkeys->ports.dst = ip_spec->pdst; 1387 fmasks->ports.dst = ip_mask->pdst; 1388 break; 1389 } 1390 case IPV6_USER_FLOW: { 1391 struct ethtool_usrip6_spec *ip_spec = &fs->h_u.usr_ip6_spec; 1392 struct ethtool_usrip6_spec *ip_mask = &fs->m_u.usr_ip6_spec; 1393 1394 fkeys->basic.ip_proto = ip_spec->l4_proto; 1395 fkeys->basic.n_proto = htons(ETH_P_IPV6); 1396 fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src; 1397 fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src; 1398 fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst; 1399 fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst; 1400 break; 1401 } 1402 case TCP_V6_FLOW: 1403 case UDP_V6_FLOW: { 1404 struct ethtool_tcpip6_spec *ip_spec = &fs->h_u.tcp_ip6_spec; 1405 struct ethtool_tcpip6_spec *ip_mask = &fs->m_u.tcp_ip6_spec; 1406 1407 fkeys->basic.ip_proto = IPPROTO_TCP; 1408 if (flow_type == UDP_V6_FLOW) 1409 fkeys->basic.ip_proto = IPPROTO_UDP; 1410 fkeys->basic.n_proto = htons(ETH_P_IPV6); 1411 1412 fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src; 1413 fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src; 1414 fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst; 1415 fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst; 1416 fkeys->ports.src = ip_spec->psrc; 1417 fmasks->ports.src = ip_mask->psrc; 1418 fkeys->ports.dst = ip_spec->pdst; 1419 fmasks->ports.dst = ip_mask->pdst; 1420 break; 1421 } 1422 default: 1423 rc = -EOPNOTSUPP; 1424 goto ntuple_err; 1425 } 1426 if (!memcmp(&BNXT_FLOW_MASK_NONE, fmasks, sizeof(*fmasks))) 1427 goto ntuple_err; 1428 1429 idx = bnxt_get_ntp_filter_idx(bp, fkeys, NULL); 1430 rcu_read_lock(); 1431 fltr = bnxt_lookup_ntp_filter_from_idx(bp, new_fltr, idx); 1432 if (fltr) { 1433 rcu_read_unlock(); 1434 rc = -EEXIST; 1435 goto ntuple_err; 1436 } 1437 rcu_read_unlock(); 1438 1439 new_fltr->base.flags = BNXT_ACT_NO_AGING; 1440 if (fs->flow_type & FLOW_RSS) { 1441 struct bnxt_rss_ctx *rss_ctx; 1442 1443 new_fltr->base.fw_vnic_id = 0; 1444 new_fltr->base.flags |= BNXT_ACT_RSS_CTX; 1445 rss_ctx = bnxt_get_rss_ctx_from_index(bp, cmd->rss_context); 1446 if (rss_ctx) { 1447 new_fltr->base.fw_vnic_id = rss_ctx->index; 1448 } else { 1449 rc = -EINVAL; 1450 goto ntuple_err; 1451 } 1452 } 1453 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1454 new_fltr->base.flags |= BNXT_ACT_DROP; 1455 else 1456 new_fltr->base.rxq = ring; 1457 __set_bit(BNXT_FLTR_VALID, &new_fltr->base.state); 1458 rc = bnxt_insert_ntp_filter(bp, new_fltr, idx); 1459 if (!rc) { 1460 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, new_fltr); 1461 if (rc) { 1462 bnxt_del_ntp_filter(bp, new_fltr); 1463 return rc; 1464 } 1465 fs->location = new_fltr->base.sw_id; 1466 return 0; 1467 } 1468 1469 ntuple_err: 1470 atomic_dec(&l2_fltr->refcnt); 1471 kfree(new_fltr); 1472 return rc; 1473 } 1474 1475 static int bnxt_srxclsrlins(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1476 { 1477 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1478 u32 ring, flow_type; 1479 int rc; 1480 u8 vf; 1481 1482 if (!netif_running(bp->dev)) 1483 return -EAGAIN; 1484 if (!(bp->flags & BNXT_FLAG_RFS)) 1485 return -EPERM; 1486 if (fs->location != RX_CLS_LOC_ANY) 1487 return -EINVAL; 1488 1489 flow_type = fs->flow_type; 1490 if ((flow_type == IP_USER_FLOW || 1491 flow_type == IPV6_USER_FLOW) && 1492 !(bp->fw_cap & BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO)) 1493 return -EOPNOTSUPP; 1494 if (flow_type & FLOW_MAC_EXT) 1495 return -EINVAL; 1496 flow_type &= ~FLOW_EXT; 1497 1498 if (fs->ring_cookie == RX_CLS_FLOW_DISC && flow_type != ETHER_FLOW) 1499 return bnxt_add_ntuple_cls_rule(bp, cmd); 1500 1501 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1502 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1503 if (BNXT_VF(bp) && vf) 1504 return -EINVAL; 1505 if (BNXT_PF(bp) && vf > bp->pf.active_vfs) 1506 return -EINVAL; 1507 if (!vf && ring >= bp->rx_nr_rings) 1508 return -EINVAL; 1509 1510 if (flow_type == ETHER_FLOW) 1511 rc = bnxt_add_l2_cls_rule(bp, fs); 1512 else 1513 rc = bnxt_add_ntuple_cls_rule(bp, cmd); 1514 return rc; 1515 } 1516 1517 static int bnxt_srxclsrldel(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1518 { 1519 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1520 struct bnxt_filter_base *fltr_base; 1521 struct bnxt_ntuple_filter *fltr; 1522 u32 id = fs->location; 1523 1524 rcu_read_lock(); 1525 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl, 1526 BNXT_L2_FLTR_HASH_SIZE, id); 1527 if (fltr_base) { 1528 struct bnxt_l2_filter *l2_fltr; 1529 1530 l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base); 1531 rcu_read_unlock(); 1532 bnxt_hwrm_l2_filter_free(bp, l2_fltr); 1533 bnxt_del_l2_filter(bp, l2_fltr); 1534 return 0; 1535 } 1536 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl, 1537 BNXT_NTP_FLTR_HASH_SIZE, id); 1538 if (!fltr_base) { 1539 rcu_read_unlock(); 1540 return -ENOENT; 1541 } 1542 1543 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base); 1544 if (!(fltr->base.flags & BNXT_ACT_NO_AGING)) { 1545 rcu_read_unlock(); 1546 return -EINVAL; 1547 } 1548 rcu_read_unlock(); 1549 bnxt_hwrm_cfa_ntuple_filter_free(bp, fltr); 1550 bnxt_del_ntp_filter(bp, fltr); 1551 return 0; 1552 } 1553 1554 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1555 { 1556 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1557 return RXH_IP_SRC | RXH_IP_DST; 1558 return 0; 1559 } 1560 1561 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1562 { 1563 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1564 return RXH_IP_SRC | RXH_IP_DST; 1565 return 0; 1566 } 1567 1568 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1569 { 1570 cmd->data = 0; 1571 switch (cmd->flow_type) { 1572 case TCP_V4_FLOW: 1573 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1574 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1575 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1576 cmd->data |= get_ethtool_ipv4_rss(bp); 1577 break; 1578 case UDP_V4_FLOW: 1579 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1580 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1581 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1582 fallthrough; 1583 case AH_ESP_V4_FLOW: 1584 if (bp->rss_hash_cfg & 1585 (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1586 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4)) 1587 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1588 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1589 fallthrough; 1590 case SCTP_V4_FLOW: 1591 case AH_V4_FLOW: 1592 case ESP_V4_FLOW: 1593 case IPV4_FLOW: 1594 cmd->data |= get_ethtool_ipv4_rss(bp); 1595 break; 1596 1597 case TCP_V6_FLOW: 1598 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1599 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1600 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1601 cmd->data |= get_ethtool_ipv6_rss(bp); 1602 break; 1603 case UDP_V6_FLOW: 1604 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1605 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1606 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1607 fallthrough; 1608 case AH_ESP_V6_FLOW: 1609 if (bp->rss_hash_cfg & 1610 (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1611 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6)) 1612 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1613 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1614 fallthrough; 1615 case SCTP_V6_FLOW: 1616 case AH_V6_FLOW: 1617 case ESP_V6_FLOW: 1618 case IPV6_FLOW: 1619 cmd->data |= get_ethtool_ipv6_rss(bp); 1620 break; 1621 } 1622 return 0; 1623 } 1624 1625 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1626 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1627 1628 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1629 { 1630 u32 rss_hash_cfg = bp->rss_hash_cfg; 1631 int tuple, rc = 0; 1632 1633 if (cmd->data == RXH_4TUPLE) 1634 tuple = 4; 1635 else if (cmd->data == RXH_2TUPLE) 1636 tuple = 2; 1637 else if (!cmd->data) 1638 tuple = 0; 1639 else 1640 return -EINVAL; 1641 1642 if (cmd->flow_type == TCP_V4_FLOW) { 1643 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1644 if (tuple == 4) 1645 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1646 } else if (cmd->flow_type == UDP_V4_FLOW) { 1647 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP)) 1648 return -EINVAL; 1649 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1650 if (tuple == 4) 1651 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1652 } else if (cmd->flow_type == TCP_V6_FLOW) { 1653 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1654 if (tuple == 4) 1655 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1656 } else if (cmd->flow_type == UDP_V6_FLOW) { 1657 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP)) 1658 return -EINVAL; 1659 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1660 if (tuple == 4) 1661 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1662 } else if (cmd->flow_type == AH_ESP_V4_FLOW) { 1663 if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V4_RSS_CAP) || 1664 !(bp->rss_cap & BNXT_RSS_CAP_ESP_V4_RSS_CAP))) 1665 return -EINVAL; 1666 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1667 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4); 1668 if (tuple == 4) 1669 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1670 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4; 1671 } else if (cmd->flow_type == AH_ESP_V6_FLOW) { 1672 if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V6_RSS_CAP) || 1673 !(bp->rss_cap & BNXT_RSS_CAP_ESP_V6_RSS_CAP))) 1674 return -EINVAL; 1675 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1676 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6); 1677 if (tuple == 4) 1678 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1679 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6; 1680 } else if (tuple == 4) { 1681 return -EINVAL; 1682 } 1683 1684 switch (cmd->flow_type) { 1685 case TCP_V4_FLOW: 1686 case UDP_V4_FLOW: 1687 case SCTP_V4_FLOW: 1688 case AH_ESP_V4_FLOW: 1689 case AH_V4_FLOW: 1690 case ESP_V4_FLOW: 1691 case IPV4_FLOW: 1692 if (tuple == 2) 1693 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1694 else if (!tuple) 1695 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1696 break; 1697 1698 case TCP_V6_FLOW: 1699 case UDP_V6_FLOW: 1700 case SCTP_V6_FLOW: 1701 case AH_ESP_V6_FLOW: 1702 case AH_V6_FLOW: 1703 case ESP_V6_FLOW: 1704 case IPV6_FLOW: 1705 if (tuple == 2) 1706 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1707 else if (!tuple) 1708 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1709 break; 1710 } 1711 1712 if (bp->rss_hash_cfg == rss_hash_cfg) 1713 return 0; 1714 1715 if (bp->rss_cap & BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA) 1716 bp->rss_hash_delta = bp->rss_hash_cfg ^ rss_hash_cfg; 1717 bp->rss_hash_cfg = rss_hash_cfg; 1718 if (netif_running(bp->dev)) { 1719 bnxt_close_nic(bp, false, false); 1720 rc = bnxt_open_nic(bp, false, false); 1721 } 1722 return rc; 1723 } 1724 1725 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1726 u32 *rule_locs) 1727 { 1728 struct bnxt *bp = netdev_priv(dev); 1729 int rc = 0; 1730 1731 switch (cmd->cmd) { 1732 case ETHTOOL_GRXRINGS: 1733 cmd->data = bp->rx_nr_rings; 1734 break; 1735 1736 case ETHTOOL_GRXCLSRLCNT: 1737 cmd->rule_cnt = bp->ntp_fltr_count; 1738 cmd->data = bp->max_fltr | RX_CLS_LOC_SPECIAL; 1739 break; 1740 1741 case ETHTOOL_GRXCLSRLALL: 1742 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1743 break; 1744 1745 case ETHTOOL_GRXCLSRULE: 1746 rc = bnxt_grxclsrule(bp, cmd); 1747 break; 1748 1749 case ETHTOOL_GRXFH: 1750 rc = bnxt_grxfh(bp, cmd); 1751 break; 1752 1753 default: 1754 rc = -EOPNOTSUPP; 1755 break; 1756 } 1757 1758 return rc; 1759 } 1760 1761 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1762 { 1763 struct bnxt *bp = netdev_priv(dev); 1764 int rc; 1765 1766 switch (cmd->cmd) { 1767 case ETHTOOL_SRXFH: 1768 rc = bnxt_srxfh(bp, cmd); 1769 break; 1770 1771 case ETHTOOL_SRXCLSRLINS: 1772 rc = bnxt_srxclsrlins(bp, cmd); 1773 break; 1774 1775 case ETHTOOL_SRXCLSRLDEL: 1776 rc = bnxt_srxclsrldel(bp, cmd); 1777 break; 1778 1779 default: 1780 rc = -EOPNOTSUPP; 1781 break; 1782 } 1783 return rc; 1784 } 1785 1786 u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1787 { 1788 struct bnxt *bp = netdev_priv(dev); 1789 1790 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) 1791 return bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) * 1792 BNXT_RSS_TABLE_ENTRIES_P5; 1793 return HW_HASH_INDEX_SIZE; 1794 } 1795 1796 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1797 { 1798 return HW_HASH_KEY_SIZE; 1799 } 1800 1801 static int bnxt_get_rxfh(struct net_device *dev, 1802 struct ethtool_rxfh_param *rxfh) 1803 { 1804 u32 rss_context = rxfh->rss_context; 1805 struct bnxt_rss_ctx *rss_ctx = NULL; 1806 struct bnxt *bp = netdev_priv(dev); 1807 u16 *indir_tbl = bp->rss_indir_tbl; 1808 struct bnxt_vnic_info *vnic; 1809 u32 i, tbl_size; 1810 1811 rxfh->hfunc = ETH_RSS_HASH_TOP; 1812 1813 if (!bp->vnic_info) 1814 return 0; 1815 1816 vnic = &bp->vnic_info[BNXT_VNIC_DEFAULT]; 1817 if (rxfh->rss_context) { 1818 rss_ctx = bnxt_get_rss_ctx_from_index(bp, rss_context); 1819 if (!rss_ctx) 1820 return -EINVAL; 1821 indir_tbl = rss_ctx->rss_indir_tbl; 1822 vnic = &rss_ctx->vnic; 1823 } 1824 1825 if (rxfh->indir && indir_tbl) { 1826 tbl_size = bnxt_get_rxfh_indir_size(dev); 1827 for (i = 0; i < tbl_size; i++) 1828 rxfh->indir[i] = indir_tbl[i]; 1829 } 1830 1831 if (rxfh->key && vnic->rss_hash_key) 1832 memcpy(rxfh->key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1833 1834 return 0; 1835 } 1836 1837 static void bnxt_modify_rss(struct bnxt *bp, struct bnxt_rss_ctx *rss_ctx, 1838 struct ethtool_rxfh_param *rxfh) 1839 { 1840 if (rxfh->key) { 1841 if (rss_ctx) { 1842 memcpy(rss_ctx->vnic.rss_hash_key, rxfh->key, 1843 HW_HASH_KEY_SIZE); 1844 } else { 1845 memcpy(bp->rss_hash_key, rxfh->key, HW_HASH_KEY_SIZE); 1846 bp->rss_hash_key_updated = true; 1847 } 1848 } 1849 if (rxfh->indir) { 1850 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(bp->dev); 1851 u16 *indir_tbl = bp->rss_indir_tbl; 1852 1853 if (rss_ctx) 1854 indir_tbl = rss_ctx->rss_indir_tbl; 1855 for (i = 0; i < tbl_size; i++) 1856 indir_tbl[i] = rxfh->indir[i]; 1857 pad = bp->rss_indir_tbl_entries - tbl_size; 1858 if (pad) 1859 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16)); 1860 } 1861 } 1862 1863 static int bnxt_set_rxfh_context(struct bnxt *bp, 1864 struct ethtool_rxfh_param *rxfh, 1865 struct netlink_ext_ack *extack) 1866 { 1867 u32 *rss_context = &rxfh->rss_context; 1868 struct bnxt_rss_ctx *rss_ctx; 1869 struct bnxt_vnic_info *vnic; 1870 bool modify = false; 1871 int bit_id; 1872 int rc; 1873 1874 if (!BNXT_SUPPORTS_MULTI_RSS_CTX(bp)) { 1875 NL_SET_ERR_MSG_MOD(extack, "RSS contexts not supported"); 1876 return -EOPNOTSUPP; 1877 } 1878 1879 if (*rss_context != ETH_RXFH_CONTEXT_ALLOC) { 1880 rss_ctx = bnxt_get_rss_ctx_from_index(bp, *rss_context); 1881 if (!rss_ctx) { 1882 NL_SET_ERR_MSG_FMT_MOD(extack, "RSS context %u not found", 1883 *rss_context); 1884 return -EINVAL; 1885 } 1886 if (*rss_context && rxfh->rss_delete) { 1887 bnxt_del_one_rss_ctx(bp, rss_ctx, true); 1888 return 0; 1889 } 1890 modify = true; 1891 vnic = &rss_ctx->vnic; 1892 goto modify_context; 1893 } 1894 1895 if (bp->num_rss_ctx >= BNXT_MAX_ETH_RSS_CTX) { 1896 NL_SET_ERR_MSG_FMT_MOD(extack, "Out of RSS contexts, maximum %u", 1897 BNXT_MAX_ETH_RSS_CTX); 1898 return -EINVAL; 1899 } 1900 1901 if (!bnxt_rfs_capable(bp, true)) { 1902 NL_SET_ERR_MSG_MOD(extack, "Out hardware resources"); 1903 return -ENOMEM; 1904 } 1905 1906 rss_ctx = bnxt_alloc_rss_ctx(bp); 1907 if (!rss_ctx) 1908 return -ENOMEM; 1909 1910 vnic = &rss_ctx->vnic; 1911 vnic->flags |= BNXT_VNIC_RSSCTX_FLAG; 1912 vnic->vnic_id = BNXT_VNIC_ID_INVALID; 1913 rc = bnxt_alloc_rss_ctx_rss_table(bp, rss_ctx); 1914 if (rc) 1915 goto out; 1916 1917 rc = bnxt_alloc_rss_indir_tbl(bp, rss_ctx); 1918 if (rc) 1919 goto out; 1920 1921 bnxt_set_dflt_rss_indir_tbl(bp, rss_ctx); 1922 memcpy(vnic->rss_hash_key, bp->rss_hash_key, HW_HASH_KEY_SIZE); 1923 1924 rc = bnxt_hwrm_vnic_alloc(bp, vnic, 0, bp->rx_nr_rings); 1925 if (rc) { 1926 NL_SET_ERR_MSG_MOD(extack, "Unable to allocate VNIC"); 1927 goto out; 1928 } 1929 1930 rc = bnxt_hwrm_vnic_set_tpa(bp, vnic, bp->flags & BNXT_FLAG_TPA); 1931 if (rc) { 1932 NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA"); 1933 goto out; 1934 } 1935 modify_context: 1936 bnxt_modify_rss(bp, rss_ctx, rxfh); 1937 1938 if (modify) 1939 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic); 1940 1941 rc = __bnxt_setup_vnic_p5(bp, vnic); 1942 if (rc) { 1943 NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA"); 1944 goto out; 1945 } 1946 1947 bit_id = bitmap_find_free_region(bp->rss_ctx_bmap, 1948 BNXT_RSS_CTX_BMAP_LEN, 0); 1949 if (bit_id < 0) { 1950 rc = -ENOMEM; 1951 goto out; 1952 } 1953 rss_ctx->index = (u16)bit_id; 1954 *rss_context = rss_ctx->index; 1955 1956 return 0; 1957 out: 1958 bnxt_del_one_rss_ctx(bp, rss_ctx, true); 1959 return rc; 1960 } 1961 1962 static int bnxt_set_rxfh(struct net_device *dev, 1963 struct ethtool_rxfh_param *rxfh, 1964 struct netlink_ext_ack *extack) 1965 { 1966 struct bnxt *bp = netdev_priv(dev); 1967 int rc = 0; 1968 1969 if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP) 1970 return -EOPNOTSUPP; 1971 1972 if (rxfh->rss_context) 1973 return bnxt_set_rxfh_context(bp, rxfh, extack); 1974 1975 bnxt_modify_rss(bp, NULL, rxfh); 1976 1977 bnxt_clear_usr_fltrs(bp, false); 1978 if (netif_running(bp->dev)) { 1979 bnxt_close_nic(bp, false, false); 1980 rc = bnxt_open_nic(bp, false, false); 1981 } 1982 return rc; 1983 } 1984 1985 static void bnxt_get_drvinfo(struct net_device *dev, 1986 struct ethtool_drvinfo *info) 1987 { 1988 struct bnxt *bp = netdev_priv(dev); 1989 1990 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 1991 strscpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 1992 strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1993 info->n_stats = bnxt_get_num_stats(bp); 1994 info->testinfo_len = bp->num_tests; 1995 /* TODO CHIMP_FW: eeprom dump details */ 1996 info->eedump_len = 0; 1997 /* TODO CHIMP FW: reg dump details */ 1998 info->regdump_len = 0; 1999 } 2000 2001 static int bnxt_get_regs_len(struct net_device *dev) 2002 { 2003 struct bnxt *bp = netdev_priv(dev); 2004 int reg_len; 2005 2006 if (!BNXT_PF(bp)) 2007 return -EOPNOTSUPP; 2008 2009 reg_len = BNXT_PXP_REG_LEN; 2010 2011 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED) 2012 reg_len += sizeof(struct pcie_ctx_hw_stats); 2013 2014 return reg_len; 2015 } 2016 2017 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs, 2018 void *_p) 2019 { 2020 struct pcie_ctx_hw_stats *hw_pcie_stats; 2021 struct hwrm_pcie_qstats_input *req; 2022 struct bnxt *bp = netdev_priv(dev); 2023 dma_addr_t hw_pcie_stats_addr; 2024 int rc; 2025 2026 regs->version = 0; 2027 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p); 2028 2029 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 2030 return; 2031 2032 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS)) 2033 return; 2034 2035 hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats), 2036 &hw_pcie_stats_addr); 2037 if (!hw_pcie_stats) { 2038 hwrm_req_drop(bp, req); 2039 return; 2040 } 2041 2042 regs->version = 1; 2043 hwrm_req_hold(bp, req); /* hold on to slice */ 2044 req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats)); 2045 req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr); 2046 rc = hwrm_req_send(bp, req); 2047 if (!rc) { 2048 __le64 *src = (__le64 *)hw_pcie_stats; 2049 u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN); 2050 int i; 2051 2052 for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++) 2053 dst[i] = le64_to_cpu(src[i]); 2054 } 2055 hwrm_req_drop(bp, req); 2056 } 2057 2058 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2059 { 2060 struct bnxt *bp = netdev_priv(dev); 2061 2062 wol->supported = 0; 2063 wol->wolopts = 0; 2064 memset(&wol->sopass, 0, sizeof(wol->sopass)); 2065 if (bp->flags & BNXT_FLAG_WOL_CAP) { 2066 wol->supported = WAKE_MAGIC; 2067 if (bp->wol) 2068 wol->wolopts = WAKE_MAGIC; 2069 } 2070 } 2071 2072 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2073 { 2074 struct bnxt *bp = netdev_priv(dev); 2075 2076 if (wol->wolopts & ~WAKE_MAGIC) 2077 return -EINVAL; 2078 2079 if (wol->wolopts & WAKE_MAGIC) { 2080 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 2081 return -EINVAL; 2082 if (!bp->wol) { 2083 if (bnxt_hwrm_alloc_wol_fltr(bp)) 2084 return -EBUSY; 2085 bp->wol = 1; 2086 } 2087 } else { 2088 if (bp->wol) { 2089 if (bnxt_hwrm_free_wol_fltr(bp)) 2090 return -EBUSY; 2091 bp->wol = 0; 2092 } 2093 } 2094 return 0; 2095 } 2096 2097 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 2098 void _bnxt_fw_to_linkmode(unsigned long *mode, u16 fw_speeds) 2099 { 2100 linkmode_zero(mode); 2101 2102 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 2103 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode); 2104 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 2105 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode); 2106 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 2107 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT, mode); 2108 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 2109 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode); 2110 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 2111 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode); 2112 } 2113 2114 enum bnxt_media_type { 2115 BNXT_MEDIA_UNKNOWN = 0, 2116 BNXT_MEDIA_TP, 2117 BNXT_MEDIA_CR, 2118 BNXT_MEDIA_SR, 2119 BNXT_MEDIA_LR_ER_FR, 2120 BNXT_MEDIA_KR, 2121 BNXT_MEDIA_KX, 2122 BNXT_MEDIA_X, 2123 __BNXT_MEDIA_END, 2124 }; 2125 2126 static const enum bnxt_media_type bnxt_phy_types[] = { 2127 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR] = BNXT_MEDIA_CR, 2128 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4] = BNXT_MEDIA_KR, 2129 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR] = BNXT_MEDIA_LR_ER_FR, 2130 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR] = BNXT_MEDIA_SR, 2131 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2] = BNXT_MEDIA_KR, 2132 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX] = BNXT_MEDIA_KX, 2133 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR] = BNXT_MEDIA_KR, 2134 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASET] = BNXT_MEDIA_TP, 2135 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE] = BNXT_MEDIA_TP, 2136 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L] = BNXT_MEDIA_CR, 2137 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S] = BNXT_MEDIA_CR, 2138 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N] = BNXT_MEDIA_CR, 2139 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR] = BNXT_MEDIA_SR, 2140 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4] = BNXT_MEDIA_CR, 2141 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4] = BNXT_MEDIA_SR, 2142 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2143 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2144 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10] = BNXT_MEDIA_SR, 2145 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4] = BNXT_MEDIA_CR, 2146 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4] = BNXT_MEDIA_SR, 2147 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2148 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2149 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE] = BNXT_MEDIA_SR, 2150 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET] = BNXT_MEDIA_TP, 2151 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX] = BNXT_MEDIA_X, 2152 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX] = BNXT_MEDIA_X, 2153 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4] = BNXT_MEDIA_CR, 2154 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4] = BNXT_MEDIA_SR, 2155 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2156 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2157 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR] = BNXT_MEDIA_CR, 2158 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR] = BNXT_MEDIA_SR, 2159 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR] = BNXT_MEDIA_LR_ER_FR, 2160 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER] = BNXT_MEDIA_LR_ER_FR, 2161 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2] = BNXT_MEDIA_CR, 2162 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2] = BNXT_MEDIA_SR, 2163 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2] = BNXT_MEDIA_LR_ER_FR, 2164 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2] = BNXT_MEDIA_LR_ER_FR, 2165 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR] = BNXT_MEDIA_CR, 2166 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR] = BNXT_MEDIA_SR, 2167 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR] = BNXT_MEDIA_LR_ER_FR, 2168 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER] = BNXT_MEDIA_LR_ER_FR, 2169 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2] = BNXT_MEDIA_CR, 2170 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2] = BNXT_MEDIA_SR, 2171 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2] = BNXT_MEDIA_LR_ER_FR, 2172 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2] = BNXT_MEDIA_LR_ER_FR, 2173 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8] = BNXT_MEDIA_CR, 2174 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8] = BNXT_MEDIA_SR, 2175 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8] = BNXT_MEDIA_LR_ER_FR, 2176 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8] = BNXT_MEDIA_LR_ER_FR, 2177 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4] = BNXT_MEDIA_CR, 2178 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4] = BNXT_MEDIA_SR, 2179 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2180 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2181 }; 2182 2183 static enum bnxt_media_type 2184 bnxt_get_media(struct bnxt_link_info *link_info) 2185 { 2186 switch (link_info->media_type) { 2187 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP: 2188 return BNXT_MEDIA_TP; 2189 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC: 2190 return BNXT_MEDIA_CR; 2191 default: 2192 if (link_info->phy_type < ARRAY_SIZE(bnxt_phy_types)) 2193 return bnxt_phy_types[link_info->phy_type]; 2194 return BNXT_MEDIA_UNKNOWN; 2195 } 2196 } 2197 2198 enum bnxt_link_speed_indices { 2199 BNXT_LINK_SPEED_UNKNOWN = 0, 2200 BNXT_LINK_SPEED_100MB_IDX, 2201 BNXT_LINK_SPEED_1GB_IDX, 2202 BNXT_LINK_SPEED_10GB_IDX, 2203 BNXT_LINK_SPEED_25GB_IDX, 2204 BNXT_LINK_SPEED_40GB_IDX, 2205 BNXT_LINK_SPEED_50GB_IDX, 2206 BNXT_LINK_SPEED_100GB_IDX, 2207 BNXT_LINK_SPEED_200GB_IDX, 2208 BNXT_LINK_SPEED_400GB_IDX, 2209 __BNXT_LINK_SPEED_END 2210 }; 2211 2212 static enum bnxt_link_speed_indices bnxt_fw_speed_idx(u16 speed) 2213 { 2214 switch (speed) { 2215 case BNXT_LINK_SPEED_100MB: return BNXT_LINK_SPEED_100MB_IDX; 2216 case BNXT_LINK_SPEED_1GB: return BNXT_LINK_SPEED_1GB_IDX; 2217 case BNXT_LINK_SPEED_10GB: return BNXT_LINK_SPEED_10GB_IDX; 2218 case BNXT_LINK_SPEED_25GB: return BNXT_LINK_SPEED_25GB_IDX; 2219 case BNXT_LINK_SPEED_40GB: return BNXT_LINK_SPEED_40GB_IDX; 2220 case BNXT_LINK_SPEED_50GB: 2221 case BNXT_LINK_SPEED_50GB_PAM4: 2222 return BNXT_LINK_SPEED_50GB_IDX; 2223 case BNXT_LINK_SPEED_100GB: 2224 case BNXT_LINK_SPEED_100GB_PAM4: 2225 case BNXT_LINK_SPEED_100GB_PAM4_112: 2226 return BNXT_LINK_SPEED_100GB_IDX; 2227 case BNXT_LINK_SPEED_200GB: 2228 case BNXT_LINK_SPEED_200GB_PAM4: 2229 case BNXT_LINK_SPEED_200GB_PAM4_112: 2230 return BNXT_LINK_SPEED_200GB_IDX; 2231 case BNXT_LINK_SPEED_400GB: 2232 case BNXT_LINK_SPEED_400GB_PAM4: 2233 case BNXT_LINK_SPEED_400GB_PAM4_112: 2234 return BNXT_LINK_SPEED_400GB_IDX; 2235 default: return BNXT_LINK_SPEED_UNKNOWN; 2236 } 2237 } 2238 2239 static const enum ethtool_link_mode_bit_indices 2240 bnxt_link_modes[__BNXT_LINK_SPEED_END][BNXT_SIG_MODE_MAX][__BNXT_MEDIA_END] = { 2241 [BNXT_LINK_SPEED_100MB_IDX] = { 2242 { 2243 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_100baseT_Full_BIT, 2244 }, 2245 }, 2246 [BNXT_LINK_SPEED_1GB_IDX] = { 2247 { 2248 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 2249 /* historically baseT, but DAC is more correctly baseX */ 2250 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 2251 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2252 [BNXT_MEDIA_X] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 2253 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2254 }, 2255 }, 2256 [BNXT_LINK_SPEED_10GB_IDX] = { 2257 { 2258 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 2259 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 2260 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 2261 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 2262 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 2263 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 2264 }, 2265 }, 2266 [BNXT_LINK_SPEED_25GB_IDX] = { 2267 { 2268 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 2269 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 2270 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 2271 }, 2272 }, 2273 [BNXT_LINK_SPEED_40GB_IDX] = { 2274 { 2275 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 2276 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 2277 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 2278 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 2279 }, 2280 }, 2281 [BNXT_LINK_SPEED_50GB_IDX] = { 2282 [BNXT_SIG_MODE_NRZ] = { 2283 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 2284 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 2285 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 2286 }, 2287 [BNXT_SIG_MODE_PAM4] = { 2288 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 2289 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 2290 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 2291 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 2292 }, 2293 }, 2294 [BNXT_LINK_SPEED_100GB_IDX] = { 2295 [BNXT_SIG_MODE_NRZ] = { 2296 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 2297 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 2298 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 2299 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 2300 }, 2301 [BNXT_SIG_MODE_PAM4] = { 2302 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 2303 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 2304 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 2305 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 2306 }, 2307 [BNXT_SIG_MODE_PAM4_112] = { 2308 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR_Full_BIT, 2309 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR_Full_BIT, 2310 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR_Full_BIT, 2311 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT, 2312 }, 2313 }, 2314 [BNXT_LINK_SPEED_200GB_IDX] = { 2315 [BNXT_SIG_MODE_PAM4] = { 2316 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT, 2317 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 2318 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 2319 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 2320 }, 2321 [BNXT_SIG_MODE_PAM4_112] = { 2322 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT, 2323 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT, 2324 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT, 2325 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT, 2326 }, 2327 }, 2328 [BNXT_LINK_SPEED_400GB_IDX] = { 2329 [BNXT_SIG_MODE_PAM4] = { 2330 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT, 2331 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT, 2332 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT, 2333 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT, 2334 }, 2335 [BNXT_SIG_MODE_PAM4_112] = { 2336 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT, 2337 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT, 2338 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT, 2339 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT, 2340 }, 2341 }, 2342 }; 2343 2344 #define BNXT_LINK_MODE_UNKNOWN -1 2345 2346 static enum ethtool_link_mode_bit_indices 2347 bnxt_get_link_mode(struct bnxt_link_info *link_info) 2348 { 2349 enum ethtool_link_mode_bit_indices link_mode; 2350 enum bnxt_link_speed_indices speed; 2351 enum bnxt_media_type media; 2352 u8 sig_mode; 2353 2354 if (link_info->phy_link_status != BNXT_LINK_LINK) 2355 return BNXT_LINK_MODE_UNKNOWN; 2356 2357 media = bnxt_get_media(link_info); 2358 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 2359 speed = bnxt_fw_speed_idx(link_info->link_speed); 2360 sig_mode = link_info->active_fec_sig_mode & 2361 PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK; 2362 } else { 2363 speed = bnxt_fw_speed_idx(link_info->req_link_speed); 2364 sig_mode = link_info->req_signal_mode; 2365 } 2366 if (sig_mode >= BNXT_SIG_MODE_MAX) 2367 return BNXT_LINK_MODE_UNKNOWN; 2368 2369 /* Note ETHTOOL_LINK_MODE_10baseT_Half_BIT == 0 is a legal Linux 2370 * link mode, but since no such devices exist, the zeroes in the 2371 * map can be conveniently used to represent unknown link modes. 2372 */ 2373 link_mode = bnxt_link_modes[speed][sig_mode][media]; 2374 if (!link_mode) 2375 return BNXT_LINK_MODE_UNKNOWN; 2376 2377 switch (link_mode) { 2378 case ETHTOOL_LINK_MODE_100baseT_Full_BIT: 2379 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2380 link_mode = ETHTOOL_LINK_MODE_100baseT_Half_BIT; 2381 break; 2382 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT: 2383 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2384 link_mode = ETHTOOL_LINK_MODE_1000baseT_Half_BIT; 2385 break; 2386 default: 2387 break; 2388 } 2389 2390 return link_mode; 2391 } 2392 2393 static void bnxt_get_ethtool_modes(struct bnxt_link_info *link_info, 2394 struct ethtool_link_ksettings *lk_ksettings) 2395 { 2396 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2397 2398 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) { 2399 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2400 lk_ksettings->link_modes.supported); 2401 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2402 lk_ksettings->link_modes.supported); 2403 } 2404 2405 if (link_info->support_auto_speeds || link_info->support_auto_speeds2 || 2406 link_info->support_pam4_auto_speeds) 2407 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2408 lk_ksettings->link_modes.supported); 2409 2410 if (~link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 2411 return; 2412 2413 if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_RX) 2414 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2415 lk_ksettings->link_modes.advertising); 2416 if (hweight8(link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) == 1) 2417 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2418 lk_ksettings->link_modes.advertising); 2419 if (link_info->lp_pause & BNXT_LINK_PAUSE_RX) 2420 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2421 lk_ksettings->link_modes.lp_advertising); 2422 if (hweight8(link_info->lp_pause & BNXT_LINK_PAUSE_BOTH) == 1) 2423 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2424 lk_ksettings->link_modes.lp_advertising); 2425 } 2426 2427 static const u16 bnxt_nrz_speed_masks[] = { 2428 [BNXT_LINK_SPEED_100MB_IDX] = BNXT_LINK_SPEED_MSK_100MB, 2429 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEED_MSK_1GB, 2430 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEED_MSK_10GB, 2431 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEED_MSK_25GB, 2432 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEED_MSK_40GB, 2433 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEED_MSK_50GB, 2434 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEED_MSK_100GB, 2435 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2436 }; 2437 2438 static const u16 bnxt_pam4_speed_masks[] = { 2439 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_50GB, 2440 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_100GB, 2441 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_200GB, 2442 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2443 }; 2444 2445 static const u16 bnxt_nrz_speeds2_masks[] = { 2446 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEEDS2_MSK_1GB, 2447 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEEDS2_MSK_10GB, 2448 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEEDS2_MSK_25GB, 2449 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEEDS2_MSK_40GB, 2450 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB, 2451 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB, 2452 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2453 }; 2454 2455 static const u16 bnxt_pam4_speeds2_masks[] = { 2456 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB_PAM4, 2457 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4, 2458 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4, 2459 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4, 2460 }; 2461 2462 static const u16 bnxt_pam4_112_speeds2_masks[] = { 2463 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112, 2464 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112, 2465 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112, 2466 }; 2467 2468 static enum bnxt_link_speed_indices 2469 bnxt_encoding_speed_idx(u8 sig_mode, u16 phy_flags, u16 speed_msk) 2470 { 2471 const u16 *speeds; 2472 int idx, len; 2473 2474 switch (sig_mode) { 2475 case BNXT_SIG_MODE_NRZ: 2476 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2477 speeds = bnxt_nrz_speeds2_masks; 2478 len = ARRAY_SIZE(bnxt_nrz_speeds2_masks); 2479 } else { 2480 speeds = bnxt_nrz_speed_masks; 2481 len = ARRAY_SIZE(bnxt_nrz_speed_masks); 2482 } 2483 break; 2484 case BNXT_SIG_MODE_PAM4: 2485 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2486 speeds = bnxt_pam4_speeds2_masks; 2487 len = ARRAY_SIZE(bnxt_pam4_speeds2_masks); 2488 } else { 2489 speeds = bnxt_pam4_speed_masks; 2490 len = ARRAY_SIZE(bnxt_pam4_speed_masks); 2491 } 2492 break; 2493 case BNXT_SIG_MODE_PAM4_112: 2494 speeds = bnxt_pam4_112_speeds2_masks; 2495 len = ARRAY_SIZE(bnxt_pam4_112_speeds2_masks); 2496 break; 2497 default: 2498 return BNXT_LINK_SPEED_UNKNOWN; 2499 } 2500 2501 for (idx = 0; idx < len; idx++) { 2502 if (speeds[idx] == speed_msk) 2503 return idx; 2504 } 2505 2506 return BNXT_LINK_SPEED_UNKNOWN; 2507 } 2508 2509 #define BNXT_FW_SPEED_MSK_BITS 16 2510 2511 static void 2512 __bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media, 2513 u8 sig_mode, u16 phy_flags, unsigned long *et_mask) 2514 { 2515 enum ethtool_link_mode_bit_indices link_mode; 2516 enum bnxt_link_speed_indices speed; 2517 u8 bit; 2518 2519 for_each_set_bit(bit, &fw_mask, BNXT_FW_SPEED_MSK_BITS) { 2520 speed = bnxt_encoding_speed_idx(sig_mode, phy_flags, 1 << bit); 2521 if (!speed) 2522 continue; 2523 2524 link_mode = bnxt_link_modes[speed][sig_mode][media]; 2525 if (!link_mode) 2526 continue; 2527 2528 linkmode_set_bit(link_mode, et_mask); 2529 } 2530 } 2531 2532 static void 2533 bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media, 2534 u8 sig_mode, u16 phy_flags, unsigned long *et_mask) 2535 { 2536 if (media) { 2537 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags, 2538 et_mask); 2539 return; 2540 } 2541 2542 /* list speeds for all media if unknown */ 2543 for (media = 1; media < __BNXT_MEDIA_END; media++) 2544 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags, 2545 et_mask); 2546 } 2547 2548 static void 2549 bnxt_get_all_ethtool_support_speeds(struct bnxt_link_info *link_info, 2550 enum bnxt_media_type media, 2551 struct ethtool_link_ksettings *lk_ksettings) 2552 { 2553 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2554 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0; 2555 u16 phy_flags = bp->phy_flags; 2556 2557 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2558 sp_nrz = link_info->support_speeds2; 2559 sp_pam4 = link_info->support_speeds2; 2560 sp_pam4_112 = link_info->support_speeds2; 2561 } else { 2562 sp_nrz = link_info->support_speeds; 2563 sp_pam4 = link_info->support_pam4_speeds; 2564 } 2565 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags, 2566 lk_ksettings->link_modes.supported); 2567 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags, 2568 lk_ksettings->link_modes.supported); 2569 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112, 2570 phy_flags, lk_ksettings->link_modes.supported); 2571 } 2572 2573 static void 2574 bnxt_get_all_ethtool_adv_speeds(struct bnxt_link_info *link_info, 2575 enum bnxt_media_type media, 2576 struct ethtool_link_ksettings *lk_ksettings) 2577 { 2578 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2579 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0; 2580 u16 phy_flags = bp->phy_flags; 2581 2582 sp_nrz = link_info->advertising; 2583 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2584 sp_pam4 = link_info->advertising; 2585 sp_pam4_112 = link_info->advertising; 2586 } else { 2587 sp_pam4 = link_info->advertising_pam4; 2588 } 2589 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags, 2590 lk_ksettings->link_modes.advertising); 2591 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags, 2592 lk_ksettings->link_modes.advertising); 2593 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112, 2594 phy_flags, lk_ksettings->link_modes.advertising); 2595 } 2596 2597 static void 2598 bnxt_get_all_ethtool_lp_speeds(struct bnxt_link_info *link_info, 2599 enum bnxt_media_type media, 2600 struct ethtool_link_ksettings *lk_ksettings) 2601 { 2602 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2603 u16 phy_flags = bp->phy_flags; 2604 2605 bnxt_get_ethtool_speeds(link_info->lp_auto_link_speeds, media, 2606 BNXT_SIG_MODE_NRZ, phy_flags, 2607 lk_ksettings->link_modes.lp_advertising); 2608 bnxt_get_ethtool_speeds(link_info->lp_auto_pam4_link_speeds, media, 2609 BNXT_SIG_MODE_PAM4, phy_flags, 2610 lk_ksettings->link_modes.lp_advertising); 2611 } 2612 2613 static void bnxt_update_speed(u32 *delta, bool installed_media, u16 *speeds, 2614 u16 speed_msk, const unsigned long *et_mask, 2615 enum ethtool_link_mode_bit_indices mode) 2616 { 2617 bool mode_desired = linkmode_test_bit(mode, et_mask); 2618 2619 if (!mode) 2620 return; 2621 2622 /* enabled speeds for installed media should override */ 2623 if (installed_media && mode_desired) { 2624 *speeds |= speed_msk; 2625 *delta |= speed_msk; 2626 return; 2627 } 2628 2629 /* many to one mapping, only allow one change per fw_speed bit */ 2630 if (!(*delta & speed_msk) && (mode_desired == !(*speeds & speed_msk))) { 2631 *speeds ^= speed_msk; 2632 *delta |= speed_msk; 2633 } 2634 } 2635 2636 static void bnxt_set_ethtool_speeds(struct bnxt_link_info *link_info, 2637 const unsigned long *et_mask) 2638 { 2639 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2640 u16 const *sp_msks, *sp_pam4_msks, *sp_pam4_112_msks; 2641 enum bnxt_media_type media = bnxt_get_media(link_info); 2642 u16 *adv, *adv_pam4, *adv_pam4_112 = NULL; 2643 u32 delta_pam4_112 = 0; 2644 u32 delta_pam4 = 0; 2645 u32 delta_nrz = 0; 2646 int i, m; 2647 2648 adv = &link_info->advertising; 2649 if (bp->phy_flags & BNXT_PHY_FL_SPEEDS2) { 2650 adv_pam4 = &link_info->advertising; 2651 adv_pam4_112 = &link_info->advertising; 2652 sp_msks = bnxt_nrz_speeds2_masks; 2653 sp_pam4_msks = bnxt_pam4_speeds2_masks; 2654 sp_pam4_112_msks = bnxt_pam4_112_speeds2_masks; 2655 } else { 2656 adv_pam4 = &link_info->advertising_pam4; 2657 sp_msks = bnxt_nrz_speed_masks; 2658 sp_pam4_msks = bnxt_pam4_speed_masks; 2659 } 2660 for (i = 1; i < __BNXT_LINK_SPEED_END; i++) { 2661 /* accept any legal media from user */ 2662 for (m = 1; m < __BNXT_MEDIA_END; m++) { 2663 bnxt_update_speed(&delta_nrz, m == media, 2664 adv, sp_msks[i], et_mask, 2665 bnxt_link_modes[i][BNXT_SIG_MODE_NRZ][m]); 2666 bnxt_update_speed(&delta_pam4, m == media, 2667 adv_pam4, sp_pam4_msks[i], et_mask, 2668 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4][m]); 2669 if (!adv_pam4_112) 2670 continue; 2671 2672 bnxt_update_speed(&delta_pam4_112, m == media, 2673 adv_pam4_112, sp_pam4_112_msks[i], et_mask, 2674 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4_112][m]); 2675 } 2676 } 2677 } 2678 2679 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info, 2680 struct ethtool_link_ksettings *lk_ksettings) 2681 { 2682 u16 fec_cfg = link_info->fec_cfg; 2683 2684 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) { 2685 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 2686 lk_ksettings->link_modes.advertising); 2687 return; 2688 } 2689 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 2690 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 2691 lk_ksettings->link_modes.advertising); 2692 if (fec_cfg & BNXT_FEC_ENC_RS) 2693 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 2694 lk_ksettings->link_modes.advertising); 2695 if (fec_cfg & BNXT_FEC_ENC_LLRS) 2696 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 2697 lk_ksettings->link_modes.advertising); 2698 } 2699 2700 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info, 2701 struct ethtool_link_ksettings *lk_ksettings) 2702 { 2703 u16 fec_cfg = link_info->fec_cfg; 2704 2705 if (fec_cfg & BNXT_FEC_NONE) { 2706 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 2707 lk_ksettings->link_modes.supported); 2708 return; 2709 } 2710 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP) 2711 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 2712 lk_ksettings->link_modes.supported); 2713 if (fec_cfg & BNXT_FEC_ENC_RS_CAP) 2714 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 2715 lk_ksettings->link_modes.supported); 2716 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP) 2717 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 2718 lk_ksettings->link_modes.supported); 2719 } 2720 2721 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 2722 { 2723 switch (fw_link_speed) { 2724 case BNXT_LINK_SPEED_100MB: 2725 return SPEED_100; 2726 case BNXT_LINK_SPEED_1GB: 2727 return SPEED_1000; 2728 case BNXT_LINK_SPEED_2_5GB: 2729 return SPEED_2500; 2730 case BNXT_LINK_SPEED_10GB: 2731 return SPEED_10000; 2732 case BNXT_LINK_SPEED_20GB: 2733 return SPEED_20000; 2734 case BNXT_LINK_SPEED_25GB: 2735 return SPEED_25000; 2736 case BNXT_LINK_SPEED_40GB: 2737 return SPEED_40000; 2738 case BNXT_LINK_SPEED_50GB: 2739 case BNXT_LINK_SPEED_50GB_PAM4: 2740 return SPEED_50000; 2741 case BNXT_LINK_SPEED_100GB: 2742 case BNXT_LINK_SPEED_100GB_PAM4: 2743 case BNXT_LINK_SPEED_100GB_PAM4_112: 2744 return SPEED_100000; 2745 case BNXT_LINK_SPEED_200GB: 2746 case BNXT_LINK_SPEED_200GB_PAM4: 2747 case BNXT_LINK_SPEED_200GB_PAM4_112: 2748 return SPEED_200000; 2749 case BNXT_LINK_SPEED_400GB: 2750 case BNXT_LINK_SPEED_400GB_PAM4: 2751 case BNXT_LINK_SPEED_400GB_PAM4_112: 2752 return SPEED_400000; 2753 default: 2754 return SPEED_UNKNOWN; 2755 } 2756 } 2757 2758 static void bnxt_get_default_speeds(struct ethtool_link_ksettings *lk_ksettings, 2759 struct bnxt_link_info *link_info) 2760 { 2761 struct ethtool_link_settings *base = &lk_ksettings->base; 2762 2763 if (link_info->link_state == BNXT_LINK_STATE_UP) { 2764 base->speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 2765 base->duplex = DUPLEX_HALF; 2766 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2767 base->duplex = DUPLEX_FULL; 2768 lk_ksettings->lanes = link_info->active_lanes; 2769 } else if (!link_info->autoneg) { 2770 base->speed = bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 2771 base->duplex = DUPLEX_HALF; 2772 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 2773 base->duplex = DUPLEX_FULL; 2774 } 2775 } 2776 2777 static int bnxt_get_link_ksettings(struct net_device *dev, 2778 struct ethtool_link_ksettings *lk_ksettings) 2779 { 2780 struct ethtool_link_settings *base = &lk_ksettings->base; 2781 enum ethtool_link_mode_bit_indices link_mode; 2782 struct bnxt *bp = netdev_priv(dev); 2783 struct bnxt_link_info *link_info; 2784 enum bnxt_media_type media; 2785 2786 ethtool_link_ksettings_zero_link_mode(lk_ksettings, lp_advertising); 2787 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 2788 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 2789 base->duplex = DUPLEX_UNKNOWN; 2790 base->speed = SPEED_UNKNOWN; 2791 link_info = &bp->link_info; 2792 2793 mutex_lock(&bp->link_lock); 2794 bnxt_get_ethtool_modes(link_info, lk_ksettings); 2795 media = bnxt_get_media(link_info); 2796 bnxt_get_all_ethtool_support_speeds(link_info, media, lk_ksettings); 2797 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings); 2798 link_mode = bnxt_get_link_mode(link_info); 2799 if (link_mode != BNXT_LINK_MODE_UNKNOWN) 2800 ethtool_params_from_link_mode(lk_ksettings, link_mode); 2801 else 2802 bnxt_get_default_speeds(lk_ksettings, link_info); 2803 2804 if (link_info->autoneg) { 2805 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings); 2806 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2807 lk_ksettings->link_modes.advertising); 2808 base->autoneg = AUTONEG_ENABLE; 2809 bnxt_get_all_ethtool_adv_speeds(link_info, media, lk_ksettings); 2810 if (link_info->phy_link_status == BNXT_LINK_LINK) 2811 bnxt_get_all_ethtool_lp_speeds(link_info, media, 2812 lk_ksettings); 2813 } else { 2814 base->autoneg = AUTONEG_DISABLE; 2815 } 2816 2817 base->port = PORT_NONE; 2818 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 2819 base->port = PORT_TP; 2820 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2821 lk_ksettings->link_modes.supported); 2822 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2823 lk_ksettings->link_modes.advertising); 2824 } else { 2825 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 2826 lk_ksettings->link_modes.supported); 2827 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 2828 lk_ksettings->link_modes.advertising); 2829 2830 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC) 2831 base->port = PORT_DA; 2832 else 2833 base->port = PORT_FIBRE; 2834 } 2835 base->phy_address = link_info->phy_addr; 2836 mutex_unlock(&bp->link_lock); 2837 2838 return 0; 2839 } 2840 2841 static int 2842 bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed, u32 lanes) 2843 { 2844 struct bnxt *bp = netdev_priv(dev); 2845 struct bnxt_link_info *link_info = &bp->link_info; 2846 u16 support_pam4_spds = link_info->support_pam4_speeds; 2847 u16 support_spds2 = link_info->support_speeds2; 2848 u16 support_spds = link_info->support_speeds; 2849 u8 sig_mode = BNXT_SIG_MODE_NRZ; 2850 u32 lanes_needed = 1; 2851 u16 fw_speed = 0; 2852 2853 switch (ethtool_speed) { 2854 case SPEED_100: 2855 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 2856 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB; 2857 break; 2858 case SPEED_1000: 2859 if ((support_spds & BNXT_LINK_SPEED_MSK_1GB) || 2860 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_1GB)) 2861 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 2862 break; 2863 case SPEED_2500: 2864 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 2865 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB; 2866 break; 2867 case SPEED_10000: 2868 if ((support_spds & BNXT_LINK_SPEED_MSK_10GB) || 2869 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_10GB)) 2870 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 2871 break; 2872 case SPEED_20000: 2873 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) { 2874 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB; 2875 lanes_needed = 2; 2876 } 2877 break; 2878 case SPEED_25000: 2879 if ((support_spds & BNXT_LINK_SPEED_MSK_25GB) || 2880 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_25GB)) 2881 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 2882 break; 2883 case SPEED_40000: 2884 if ((support_spds & BNXT_LINK_SPEED_MSK_40GB) || 2885 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_40GB)) { 2886 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 2887 lanes_needed = 4; 2888 } 2889 break; 2890 case SPEED_50000: 2891 if (((support_spds & BNXT_LINK_SPEED_MSK_50GB) || 2892 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB)) && 2893 lanes != 1) { 2894 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 2895 lanes_needed = 2; 2896 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) { 2897 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB; 2898 sig_mode = BNXT_SIG_MODE_PAM4; 2899 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB_PAM4) { 2900 fw_speed = BNXT_LINK_SPEED_50GB_PAM4; 2901 sig_mode = BNXT_SIG_MODE_PAM4; 2902 } 2903 break; 2904 case SPEED_100000: 2905 if (((support_spds & BNXT_LINK_SPEED_MSK_100GB) || 2906 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB)) && 2907 lanes != 2 && lanes != 1) { 2908 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB; 2909 lanes_needed = 4; 2910 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) { 2911 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB; 2912 sig_mode = BNXT_SIG_MODE_PAM4; 2913 lanes_needed = 2; 2914 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4) && 2915 lanes != 1) { 2916 fw_speed = BNXT_LINK_SPEED_100GB_PAM4; 2917 sig_mode = BNXT_SIG_MODE_PAM4; 2918 lanes_needed = 2; 2919 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112) { 2920 fw_speed = BNXT_LINK_SPEED_100GB_PAM4_112; 2921 sig_mode = BNXT_SIG_MODE_PAM4_112; 2922 } 2923 break; 2924 case SPEED_200000: 2925 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) { 2926 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB; 2927 sig_mode = BNXT_SIG_MODE_PAM4; 2928 lanes_needed = 4; 2929 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4) && 2930 lanes != 2) { 2931 fw_speed = BNXT_LINK_SPEED_200GB_PAM4; 2932 sig_mode = BNXT_SIG_MODE_PAM4; 2933 lanes_needed = 4; 2934 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112) { 2935 fw_speed = BNXT_LINK_SPEED_200GB_PAM4_112; 2936 sig_mode = BNXT_SIG_MODE_PAM4_112; 2937 lanes_needed = 2; 2938 } 2939 break; 2940 case SPEED_400000: 2941 if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4) && 2942 lanes != 4) { 2943 fw_speed = BNXT_LINK_SPEED_400GB_PAM4; 2944 sig_mode = BNXT_SIG_MODE_PAM4; 2945 lanes_needed = 8; 2946 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112) { 2947 fw_speed = BNXT_LINK_SPEED_400GB_PAM4_112; 2948 sig_mode = BNXT_SIG_MODE_PAM4_112; 2949 lanes_needed = 4; 2950 } 2951 break; 2952 } 2953 2954 if (!fw_speed) { 2955 netdev_err(dev, "unsupported speed!\n"); 2956 return -EINVAL; 2957 } 2958 2959 if (lanes && lanes != lanes_needed) { 2960 netdev_err(dev, "unsupported number of lanes for speed\n"); 2961 return -EINVAL; 2962 } 2963 2964 if (link_info->req_link_speed == fw_speed && 2965 link_info->req_signal_mode == sig_mode && 2966 link_info->autoneg == 0) 2967 return -EALREADY; 2968 2969 link_info->req_link_speed = fw_speed; 2970 link_info->req_signal_mode = sig_mode; 2971 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 2972 link_info->autoneg = 0; 2973 link_info->advertising = 0; 2974 link_info->advertising_pam4 = 0; 2975 2976 return 0; 2977 } 2978 2979 u16 bnxt_get_fw_auto_link_speeds(const unsigned long *mode) 2980 { 2981 u16 fw_speed_mask = 0; 2982 2983 if (linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode) || 2984 linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mode)) 2985 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 2986 2987 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode) || 2988 linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, mode)) 2989 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 2990 2991 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode)) 2992 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 2993 2994 if (linkmode_test_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode)) 2995 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 2996 2997 return fw_speed_mask; 2998 } 2999 3000 static int bnxt_set_link_ksettings(struct net_device *dev, 3001 const struct ethtool_link_ksettings *lk_ksettings) 3002 { 3003 struct bnxt *bp = netdev_priv(dev); 3004 struct bnxt_link_info *link_info = &bp->link_info; 3005 const struct ethtool_link_settings *base = &lk_ksettings->base; 3006 bool set_pause = false; 3007 u32 speed, lanes = 0; 3008 int rc = 0; 3009 3010 if (!BNXT_PHY_CFG_ABLE(bp)) 3011 return -EOPNOTSUPP; 3012 3013 mutex_lock(&bp->link_lock); 3014 if (base->autoneg == AUTONEG_ENABLE) { 3015 bnxt_set_ethtool_speeds(link_info, 3016 lk_ksettings->link_modes.advertising); 3017 link_info->autoneg |= BNXT_AUTONEG_SPEED; 3018 if (!link_info->advertising && !link_info->advertising_pam4) { 3019 link_info->advertising = link_info->support_auto_speeds; 3020 link_info->advertising_pam4 = 3021 link_info->support_pam4_auto_speeds; 3022 } 3023 /* any change to autoneg will cause link change, therefore the 3024 * driver should put back the original pause setting in autoneg 3025 */ 3026 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 3027 set_pause = true; 3028 } else { 3029 u8 phy_type = link_info->phy_type; 3030 3031 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 3032 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 3033 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 3034 netdev_err(dev, "10GBase-T devices must autoneg\n"); 3035 rc = -EINVAL; 3036 goto set_setting_exit; 3037 } 3038 if (base->duplex == DUPLEX_HALF) { 3039 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 3040 rc = -EINVAL; 3041 goto set_setting_exit; 3042 } 3043 speed = base->speed; 3044 lanes = lk_ksettings->lanes; 3045 rc = bnxt_force_link_speed(dev, speed, lanes); 3046 if (rc) { 3047 if (rc == -EALREADY) 3048 rc = 0; 3049 goto set_setting_exit; 3050 } 3051 } 3052 3053 if (netif_running(dev)) 3054 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 3055 3056 set_setting_exit: 3057 mutex_unlock(&bp->link_lock); 3058 return rc; 3059 } 3060 3061 static int bnxt_get_fecparam(struct net_device *dev, 3062 struct ethtool_fecparam *fec) 3063 { 3064 struct bnxt *bp = netdev_priv(dev); 3065 struct bnxt_link_info *link_info; 3066 u8 active_fec; 3067 u16 fec_cfg; 3068 3069 link_info = &bp->link_info; 3070 fec_cfg = link_info->fec_cfg; 3071 active_fec = link_info->active_fec_sig_mode & 3072 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK; 3073 if (fec_cfg & BNXT_FEC_NONE) { 3074 fec->fec = ETHTOOL_FEC_NONE; 3075 fec->active_fec = ETHTOOL_FEC_NONE; 3076 return 0; 3077 } 3078 if (fec_cfg & BNXT_FEC_AUTONEG) 3079 fec->fec |= ETHTOOL_FEC_AUTO; 3080 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 3081 fec->fec |= ETHTOOL_FEC_BASER; 3082 if (fec_cfg & BNXT_FEC_ENC_RS) 3083 fec->fec |= ETHTOOL_FEC_RS; 3084 if (fec_cfg & BNXT_FEC_ENC_LLRS) 3085 fec->fec |= ETHTOOL_FEC_LLRS; 3086 3087 switch (active_fec) { 3088 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE: 3089 fec->active_fec |= ETHTOOL_FEC_BASER; 3090 break; 3091 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE: 3092 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE: 3093 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE: 3094 fec->active_fec |= ETHTOOL_FEC_RS; 3095 break; 3096 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE: 3097 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE: 3098 fec->active_fec |= ETHTOOL_FEC_LLRS; 3099 break; 3100 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE: 3101 fec->active_fec |= ETHTOOL_FEC_OFF; 3102 break; 3103 } 3104 return 0; 3105 } 3106 3107 static void bnxt_get_fec_stats(struct net_device *dev, 3108 struct ethtool_fec_stats *fec_stats) 3109 { 3110 struct bnxt *bp = netdev_priv(dev); 3111 u64 *rx; 3112 3113 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 3114 return; 3115 3116 rx = bp->rx_port_stats_ext.sw_stats; 3117 fec_stats->corrected_bits.total = 3118 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits)); 3119 3120 if (bp->fw_rx_stats_ext_size <= BNXT_RX_STATS_EXT_NUM_LEGACY) 3121 return; 3122 3123 fec_stats->corrected_blocks.total = 3124 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)); 3125 fec_stats->uncorrectable_blocks.total = 3126 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_uncorrectable_blocks)); 3127 } 3128 3129 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info, 3130 u32 fec) 3131 { 3132 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE; 3133 3134 if (fec & ETHTOOL_FEC_BASER) 3135 fw_fec |= BNXT_FEC_BASE_R_ON(link_info); 3136 else if (fec & ETHTOOL_FEC_RS) 3137 fw_fec |= BNXT_FEC_RS_ON(link_info); 3138 else if (fec & ETHTOOL_FEC_LLRS) 3139 fw_fec |= BNXT_FEC_LLRS_ON; 3140 return fw_fec; 3141 } 3142 3143 static int bnxt_set_fecparam(struct net_device *dev, 3144 struct ethtool_fecparam *fecparam) 3145 { 3146 struct hwrm_port_phy_cfg_input *req; 3147 struct bnxt *bp = netdev_priv(dev); 3148 struct bnxt_link_info *link_info; 3149 u32 new_cfg, fec = fecparam->fec; 3150 u16 fec_cfg; 3151 int rc; 3152 3153 link_info = &bp->link_info; 3154 fec_cfg = link_info->fec_cfg; 3155 if (fec_cfg & BNXT_FEC_NONE) 3156 return -EOPNOTSUPP; 3157 3158 if (fec & ETHTOOL_FEC_OFF) { 3159 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE | 3160 BNXT_FEC_ALL_OFF(link_info); 3161 goto apply_fec; 3162 } 3163 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) || 3164 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) || 3165 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) || 3166 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP))) 3167 return -EINVAL; 3168 3169 if (fec & ETHTOOL_FEC_AUTO) { 3170 if (!link_info->autoneg) 3171 return -EINVAL; 3172 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE; 3173 } else { 3174 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec); 3175 } 3176 3177 apply_fec: 3178 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 3179 if (rc) 3180 return rc; 3181 req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 3182 rc = hwrm_req_send(bp, req); 3183 /* update current settings */ 3184 if (!rc) { 3185 mutex_lock(&bp->link_lock); 3186 bnxt_update_link(bp, false); 3187 mutex_unlock(&bp->link_lock); 3188 } 3189 return rc; 3190 } 3191 3192 static void bnxt_get_pauseparam(struct net_device *dev, 3193 struct ethtool_pauseparam *epause) 3194 { 3195 struct bnxt *bp = netdev_priv(dev); 3196 struct bnxt_link_info *link_info = &bp->link_info; 3197 3198 if (BNXT_VF(bp)) 3199 return; 3200 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 3201 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 3202 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 3203 } 3204 3205 static void bnxt_get_pause_stats(struct net_device *dev, 3206 struct ethtool_pause_stats *epstat) 3207 { 3208 struct bnxt *bp = netdev_priv(dev); 3209 u64 *rx, *tx; 3210 3211 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 3212 return; 3213 3214 rx = bp->port_stats.sw_stats; 3215 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 3216 3217 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames); 3218 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames); 3219 } 3220 3221 static int bnxt_set_pauseparam(struct net_device *dev, 3222 struct ethtool_pauseparam *epause) 3223 { 3224 int rc = 0; 3225 struct bnxt *bp = netdev_priv(dev); 3226 struct bnxt_link_info *link_info = &bp->link_info; 3227 3228 if (!BNXT_PHY_CFG_ABLE(bp) || (bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 3229 return -EOPNOTSUPP; 3230 3231 mutex_lock(&bp->link_lock); 3232 if (epause->autoneg) { 3233 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 3234 rc = -EINVAL; 3235 goto pause_exit; 3236 } 3237 3238 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 3239 link_info->req_flow_ctrl = 0; 3240 } else { 3241 /* when transition from auto pause to force pause, 3242 * force a link change 3243 */ 3244 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 3245 link_info->force_link_chng = true; 3246 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 3247 link_info->req_flow_ctrl = 0; 3248 } 3249 if (epause->rx_pause) 3250 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 3251 3252 if (epause->tx_pause) 3253 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 3254 3255 if (netif_running(dev)) 3256 rc = bnxt_hwrm_set_pause(bp); 3257 3258 pause_exit: 3259 mutex_unlock(&bp->link_lock); 3260 return rc; 3261 } 3262 3263 static u32 bnxt_get_link(struct net_device *dev) 3264 { 3265 struct bnxt *bp = netdev_priv(dev); 3266 3267 /* TODO: handle MF, VF, driver close case */ 3268 return BNXT_LINK_IS_UP(bp); 3269 } 3270 3271 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp, 3272 struct hwrm_nvm_get_dev_info_output *nvm_dev_info) 3273 { 3274 struct hwrm_nvm_get_dev_info_output *resp; 3275 struct hwrm_nvm_get_dev_info_input *req; 3276 int rc; 3277 3278 if (BNXT_VF(bp)) 3279 return -EOPNOTSUPP; 3280 3281 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO); 3282 if (rc) 3283 return rc; 3284 3285 resp = hwrm_req_hold(bp, req); 3286 rc = hwrm_req_send(bp, req); 3287 if (!rc) 3288 memcpy(nvm_dev_info, resp, sizeof(*resp)); 3289 hwrm_req_drop(bp, req); 3290 return rc; 3291 } 3292 3293 static void bnxt_print_admin_err(struct bnxt *bp) 3294 { 3295 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 3296 } 3297 3298 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 3299 u16 ext, u16 *index, u32 *item_length, 3300 u32 *data_length); 3301 3302 int bnxt_flash_nvram(struct net_device *dev, u16 dir_type, 3303 u16 dir_ordinal, u16 dir_ext, u16 dir_attr, 3304 u32 dir_item_len, const u8 *data, 3305 size_t data_len) 3306 { 3307 struct bnxt *bp = netdev_priv(dev); 3308 struct hwrm_nvm_write_input *req; 3309 int rc; 3310 3311 rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE); 3312 if (rc) 3313 return rc; 3314 3315 if (data_len && data) { 3316 dma_addr_t dma_handle; 3317 u8 *kmem; 3318 3319 kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle); 3320 if (!kmem) { 3321 hwrm_req_drop(bp, req); 3322 return -ENOMEM; 3323 } 3324 3325 req->dir_data_length = cpu_to_le32(data_len); 3326 3327 memcpy(kmem, data, data_len); 3328 req->host_src_addr = cpu_to_le64(dma_handle); 3329 } 3330 3331 hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout); 3332 req->dir_type = cpu_to_le16(dir_type); 3333 req->dir_ordinal = cpu_to_le16(dir_ordinal); 3334 req->dir_ext = cpu_to_le16(dir_ext); 3335 req->dir_attr = cpu_to_le16(dir_attr); 3336 req->dir_item_length = cpu_to_le32(dir_item_len); 3337 rc = hwrm_req_send(bp, req); 3338 3339 if (rc == -EACCES) 3340 bnxt_print_admin_err(bp); 3341 return rc; 3342 } 3343 3344 int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type, 3345 u8 self_reset, u8 flags) 3346 { 3347 struct bnxt *bp = netdev_priv(dev); 3348 struct hwrm_fw_reset_input *req; 3349 int rc; 3350 3351 if (!bnxt_hwrm_reset_permitted(bp)) { 3352 netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver"); 3353 return -EPERM; 3354 } 3355 3356 rc = hwrm_req_init(bp, req, HWRM_FW_RESET); 3357 if (rc) 3358 return rc; 3359 3360 req->embedded_proc_type = proc_type; 3361 req->selfrst_status = self_reset; 3362 req->flags = flags; 3363 3364 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) { 3365 rc = hwrm_req_send_silent(bp, req); 3366 } else { 3367 rc = hwrm_req_send(bp, req); 3368 if (rc == -EACCES) 3369 bnxt_print_admin_err(bp); 3370 } 3371 return rc; 3372 } 3373 3374 static int bnxt_firmware_reset(struct net_device *dev, 3375 enum bnxt_nvm_directory_type dir_type) 3376 { 3377 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE; 3378 u8 proc_type, flags = 0; 3379 3380 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 3381 /* (e.g. when firmware isn't already running) */ 3382 switch (dir_type) { 3383 case BNX_DIR_TYPE_CHIMP_PATCH: 3384 case BNX_DIR_TYPE_BOOTCODE: 3385 case BNX_DIR_TYPE_BOOTCODE_2: 3386 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 3387 /* Self-reset ChiMP upon next PCIe reset: */ 3388 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 3389 break; 3390 case BNX_DIR_TYPE_APE_FW: 3391 case BNX_DIR_TYPE_APE_PATCH: 3392 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 3393 /* Self-reset APE upon next PCIe reset: */ 3394 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 3395 break; 3396 case BNX_DIR_TYPE_KONG_FW: 3397 case BNX_DIR_TYPE_KONG_PATCH: 3398 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 3399 break; 3400 case BNX_DIR_TYPE_BONO_FW: 3401 case BNX_DIR_TYPE_BONO_PATCH: 3402 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 3403 break; 3404 default: 3405 return -EINVAL; 3406 } 3407 3408 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags); 3409 } 3410 3411 static int bnxt_firmware_reset_chip(struct net_device *dev) 3412 { 3413 struct bnxt *bp = netdev_priv(dev); 3414 u8 flags = 0; 3415 3416 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 3417 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 3418 3419 return bnxt_hwrm_firmware_reset(dev, 3420 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP, 3421 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP, 3422 flags); 3423 } 3424 3425 static int bnxt_firmware_reset_ap(struct net_device *dev) 3426 { 3427 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP, 3428 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE, 3429 0); 3430 } 3431 3432 static int bnxt_flash_firmware(struct net_device *dev, 3433 u16 dir_type, 3434 const u8 *fw_data, 3435 size_t fw_size) 3436 { 3437 int rc = 0; 3438 u16 code_type; 3439 u32 stored_crc; 3440 u32 calculated_crc; 3441 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 3442 3443 switch (dir_type) { 3444 case BNX_DIR_TYPE_BOOTCODE: 3445 case BNX_DIR_TYPE_BOOTCODE_2: 3446 code_type = CODE_BOOT; 3447 break; 3448 case BNX_DIR_TYPE_CHIMP_PATCH: 3449 code_type = CODE_CHIMP_PATCH; 3450 break; 3451 case BNX_DIR_TYPE_APE_FW: 3452 code_type = CODE_MCTP_PASSTHRU; 3453 break; 3454 case BNX_DIR_TYPE_APE_PATCH: 3455 code_type = CODE_APE_PATCH; 3456 break; 3457 case BNX_DIR_TYPE_KONG_FW: 3458 code_type = CODE_KONG_FW; 3459 break; 3460 case BNX_DIR_TYPE_KONG_PATCH: 3461 code_type = CODE_KONG_PATCH; 3462 break; 3463 case BNX_DIR_TYPE_BONO_FW: 3464 code_type = CODE_BONO_FW; 3465 break; 3466 case BNX_DIR_TYPE_BONO_PATCH: 3467 code_type = CODE_BONO_PATCH; 3468 break; 3469 default: 3470 netdev_err(dev, "Unsupported directory entry type: %u\n", 3471 dir_type); 3472 return -EINVAL; 3473 } 3474 if (fw_size < sizeof(struct bnxt_fw_header)) { 3475 netdev_err(dev, "Invalid firmware file size: %u\n", 3476 (unsigned int)fw_size); 3477 return -EINVAL; 3478 } 3479 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 3480 netdev_err(dev, "Invalid firmware signature: %08X\n", 3481 le32_to_cpu(header->signature)); 3482 return -EINVAL; 3483 } 3484 if (header->code_type != code_type) { 3485 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 3486 code_type, header->code_type); 3487 return -EINVAL; 3488 } 3489 if (header->device != DEVICE_CUMULUS_FAMILY) { 3490 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 3491 DEVICE_CUMULUS_FAMILY, header->device); 3492 return -EINVAL; 3493 } 3494 /* Confirm the CRC32 checksum of the file: */ 3495 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 3496 sizeof(stored_crc))); 3497 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 3498 if (calculated_crc != stored_crc) { 3499 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 3500 (unsigned long)stored_crc, 3501 (unsigned long)calculated_crc); 3502 return -EINVAL; 3503 } 3504 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3505 0, 0, 0, fw_data, fw_size); 3506 if (rc == 0) /* Firmware update successful */ 3507 rc = bnxt_firmware_reset(dev, dir_type); 3508 3509 return rc; 3510 } 3511 3512 static int bnxt_flash_microcode(struct net_device *dev, 3513 u16 dir_type, 3514 const u8 *fw_data, 3515 size_t fw_size) 3516 { 3517 struct bnxt_ucode_trailer *trailer; 3518 u32 calculated_crc; 3519 u32 stored_crc; 3520 int rc = 0; 3521 3522 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 3523 netdev_err(dev, "Invalid microcode file size: %u\n", 3524 (unsigned int)fw_size); 3525 return -EINVAL; 3526 } 3527 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 3528 sizeof(*trailer))); 3529 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 3530 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 3531 le32_to_cpu(trailer->sig)); 3532 return -EINVAL; 3533 } 3534 if (le16_to_cpu(trailer->dir_type) != dir_type) { 3535 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 3536 dir_type, le16_to_cpu(trailer->dir_type)); 3537 return -EINVAL; 3538 } 3539 if (le16_to_cpu(trailer->trailer_length) < 3540 sizeof(struct bnxt_ucode_trailer)) { 3541 netdev_err(dev, "Invalid microcode trailer length: %d\n", 3542 le16_to_cpu(trailer->trailer_length)); 3543 return -EINVAL; 3544 } 3545 3546 /* Confirm the CRC32 checksum of the file: */ 3547 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 3548 sizeof(stored_crc))); 3549 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 3550 if (calculated_crc != stored_crc) { 3551 netdev_err(dev, 3552 "CRC32 (%08lX) does not match calculated: %08lX\n", 3553 (unsigned long)stored_crc, 3554 (unsigned long)calculated_crc); 3555 return -EINVAL; 3556 } 3557 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3558 0, 0, 0, fw_data, fw_size); 3559 3560 return rc; 3561 } 3562 3563 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 3564 { 3565 switch (dir_type) { 3566 case BNX_DIR_TYPE_CHIMP_PATCH: 3567 case BNX_DIR_TYPE_BOOTCODE: 3568 case BNX_DIR_TYPE_BOOTCODE_2: 3569 case BNX_DIR_TYPE_APE_FW: 3570 case BNX_DIR_TYPE_APE_PATCH: 3571 case BNX_DIR_TYPE_KONG_FW: 3572 case BNX_DIR_TYPE_KONG_PATCH: 3573 case BNX_DIR_TYPE_BONO_FW: 3574 case BNX_DIR_TYPE_BONO_PATCH: 3575 return true; 3576 } 3577 3578 return false; 3579 } 3580 3581 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 3582 { 3583 switch (dir_type) { 3584 case BNX_DIR_TYPE_AVS: 3585 case BNX_DIR_TYPE_EXP_ROM_MBA: 3586 case BNX_DIR_TYPE_PCIE: 3587 case BNX_DIR_TYPE_TSCF_UCODE: 3588 case BNX_DIR_TYPE_EXT_PHY: 3589 case BNX_DIR_TYPE_CCM: 3590 case BNX_DIR_TYPE_ISCSI_BOOT: 3591 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 3592 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 3593 return true; 3594 } 3595 3596 return false; 3597 } 3598 3599 static bool bnxt_dir_type_is_executable(u16 dir_type) 3600 { 3601 return bnxt_dir_type_is_ape_bin_format(dir_type) || 3602 bnxt_dir_type_is_other_exec_format(dir_type); 3603 } 3604 3605 static int bnxt_flash_firmware_from_file(struct net_device *dev, 3606 u16 dir_type, 3607 const char *filename) 3608 { 3609 const struct firmware *fw; 3610 int rc; 3611 3612 rc = request_firmware(&fw, filename, &dev->dev); 3613 if (rc != 0) { 3614 netdev_err(dev, "Error %d requesting firmware file: %s\n", 3615 rc, filename); 3616 return rc; 3617 } 3618 if (bnxt_dir_type_is_ape_bin_format(dir_type)) 3619 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 3620 else if (bnxt_dir_type_is_other_exec_format(dir_type)) 3621 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 3622 else 3623 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3624 0, 0, 0, fw->data, fw->size); 3625 release_firmware(fw); 3626 return rc; 3627 } 3628 3629 #define MSG_INTEGRITY_ERR "PKG install error : Data integrity on NVM" 3630 #define MSG_INVALID_PKG "PKG install error : Invalid package" 3631 #define MSG_AUTHENTICATION_ERR "PKG install error : Authentication error" 3632 #define MSG_INVALID_DEV "PKG install error : Invalid device" 3633 #define MSG_INTERNAL_ERR "PKG install error : Internal error" 3634 #define MSG_NO_PKG_UPDATE_AREA_ERR "PKG update area not created in nvram" 3635 #define MSG_NO_SPACE_ERR "PKG insufficient update area in nvram" 3636 #define MSG_RESIZE_UPDATE_ERR "Resize UPDATE entry error" 3637 #define MSG_ANTI_ROLLBACK_ERR "HWRM_NVM_INSTALL_UPDATE failure due to Anti-rollback detected" 3638 #define MSG_GENERIC_FAILURE_ERR "HWRM_NVM_INSTALL_UPDATE failure" 3639 3640 static int nvm_update_err_to_stderr(struct net_device *dev, u8 result, 3641 struct netlink_ext_ack *extack) 3642 { 3643 switch (result) { 3644 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER: 3645 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER: 3646 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR: 3647 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR: 3648 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND: 3649 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED: 3650 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTEGRITY_ERR); 3651 return -EINVAL; 3652 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE: 3653 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER: 3654 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE: 3655 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM: 3656 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH: 3657 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST: 3658 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER: 3659 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM: 3660 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM: 3661 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH: 3662 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE: 3663 case NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM: 3664 case NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM: 3665 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_PKG); 3666 return -ENOPKG; 3667 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR: 3668 BNXT_NVM_ERR_MSG(dev, extack, MSG_AUTHENTICATION_ERR); 3669 return -EPERM; 3670 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV: 3671 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID: 3672 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR: 3673 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID: 3674 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM: 3675 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_DEV); 3676 return -EOPNOTSUPP; 3677 default: 3678 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTERNAL_ERR); 3679 return -EIO; 3680 } 3681 } 3682 3683 #define BNXT_PKG_DMA_SIZE 0x40000 3684 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE)) 3685 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST)) 3686 3687 static int bnxt_resize_update_entry(struct net_device *dev, size_t fw_size, 3688 struct netlink_ext_ack *extack) 3689 { 3690 u32 item_len; 3691 int rc; 3692 3693 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 3694 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, NULL, 3695 &item_len, NULL); 3696 if (rc) { 3697 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 3698 return rc; 3699 } 3700 3701 if (fw_size > item_len) { 3702 rc = bnxt_flash_nvram(dev, BNX_DIR_TYPE_UPDATE, 3703 BNX_DIR_ORDINAL_FIRST, 0, 1, 3704 round_up(fw_size, 4096), NULL, 0); 3705 if (rc) { 3706 BNXT_NVM_ERR_MSG(dev, extack, MSG_RESIZE_UPDATE_ERR); 3707 return rc; 3708 } 3709 } 3710 return 0; 3711 } 3712 3713 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw, 3714 u32 install_type, struct netlink_ext_ack *extack) 3715 { 3716 struct hwrm_nvm_install_update_input *install; 3717 struct hwrm_nvm_install_update_output *resp; 3718 struct hwrm_nvm_modify_input *modify; 3719 struct bnxt *bp = netdev_priv(dev); 3720 bool defrag_attempted = false; 3721 dma_addr_t dma_handle; 3722 u8 *kmem = NULL; 3723 u32 modify_len; 3724 u32 item_len; 3725 u8 cmd_err; 3726 u16 index; 3727 int rc; 3728 3729 /* resize before flashing larger image than available space */ 3730 rc = bnxt_resize_update_entry(dev, fw->size, extack); 3731 if (rc) 3732 return rc; 3733 3734 bnxt_hwrm_fw_set_time(bp); 3735 3736 rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY); 3737 if (rc) 3738 return rc; 3739 3740 /* Try allocating a large DMA buffer first. Older fw will 3741 * cause excessive NVRAM erases when using small blocks. 3742 */ 3743 modify_len = roundup_pow_of_two(fw->size); 3744 modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE); 3745 while (1) { 3746 kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle); 3747 if (!kmem && modify_len > PAGE_SIZE) 3748 modify_len /= 2; 3749 else 3750 break; 3751 } 3752 if (!kmem) { 3753 hwrm_req_drop(bp, modify); 3754 return -ENOMEM; 3755 } 3756 3757 rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE); 3758 if (rc) { 3759 hwrm_req_drop(bp, modify); 3760 return rc; 3761 } 3762 3763 hwrm_req_timeout(bp, modify, bp->hwrm_cmd_max_timeout); 3764 hwrm_req_timeout(bp, install, bp->hwrm_cmd_max_timeout); 3765 3766 hwrm_req_hold(bp, modify); 3767 modify->host_src_addr = cpu_to_le64(dma_handle); 3768 3769 resp = hwrm_req_hold(bp, install); 3770 if ((install_type & 0xffff) == 0) 3771 install_type >>= 16; 3772 install->install_type = cpu_to_le32(install_type); 3773 3774 do { 3775 u32 copied = 0, len = modify_len; 3776 3777 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 3778 BNX_DIR_ORDINAL_FIRST, 3779 BNX_DIR_EXT_NONE, 3780 &index, &item_len, NULL); 3781 if (rc) { 3782 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 3783 break; 3784 } 3785 if (fw->size > item_len) { 3786 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_SPACE_ERR); 3787 rc = -EFBIG; 3788 break; 3789 } 3790 3791 modify->dir_idx = cpu_to_le16(index); 3792 3793 if (fw->size > modify_len) 3794 modify->flags = BNXT_NVM_MORE_FLAG; 3795 while (copied < fw->size) { 3796 u32 balance = fw->size - copied; 3797 3798 if (balance <= modify_len) { 3799 len = balance; 3800 if (copied) 3801 modify->flags |= BNXT_NVM_LAST_FLAG; 3802 } 3803 memcpy(kmem, fw->data + copied, len); 3804 modify->len = cpu_to_le32(len); 3805 modify->offset = cpu_to_le32(copied); 3806 rc = hwrm_req_send(bp, modify); 3807 if (rc) 3808 goto pkg_abort; 3809 copied += len; 3810 } 3811 3812 rc = hwrm_req_send_silent(bp, install); 3813 if (!rc) 3814 break; 3815 3816 if (defrag_attempted) { 3817 /* We have tried to defragment already in the previous 3818 * iteration. Return with the result for INSTALL_UPDATE 3819 */ 3820 break; 3821 } 3822 3823 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 3824 3825 switch (cmd_err) { 3826 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK: 3827 BNXT_NVM_ERR_MSG(dev, extack, MSG_ANTI_ROLLBACK_ERR); 3828 rc = -EALREADY; 3829 break; 3830 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR: 3831 install->flags = 3832 cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 3833 3834 rc = hwrm_req_send_silent(bp, install); 3835 if (!rc) 3836 break; 3837 3838 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 3839 3840 if (cmd_err == NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) { 3841 /* FW has cleared NVM area, driver will create 3842 * UPDATE directory and try the flash again 3843 */ 3844 defrag_attempted = true; 3845 install->flags = 0; 3846 rc = bnxt_flash_nvram(bp->dev, 3847 BNX_DIR_TYPE_UPDATE, 3848 BNX_DIR_ORDINAL_FIRST, 3849 0, 0, item_len, NULL, 0); 3850 if (!rc) 3851 break; 3852 } 3853 fallthrough; 3854 default: 3855 BNXT_NVM_ERR_MSG(dev, extack, MSG_GENERIC_FAILURE_ERR); 3856 } 3857 } while (defrag_attempted && !rc); 3858 3859 pkg_abort: 3860 hwrm_req_drop(bp, modify); 3861 hwrm_req_drop(bp, install); 3862 3863 if (resp->result) { 3864 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 3865 (s8)resp->result, (int)resp->problem_item); 3866 rc = nvm_update_err_to_stderr(dev, resp->result, extack); 3867 } 3868 if (rc == -EACCES) 3869 bnxt_print_admin_err(bp); 3870 return rc; 3871 } 3872 3873 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename, 3874 u32 install_type, struct netlink_ext_ack *extack) 3875 { 3876 const struct firmware *fw; 3877 int rc; 3878 3879 rc = request_firmware(&fw, filename, &dev->dev); 3880 if (rc != 0) { 3881 netdev_err(dev, "PKG error %d requesting file: %s\n", 3882 rc, filename); 3883 return rc; 3884 } 3885 3886 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type, extack); 3887 3888 release_firmware(fw); 3889 3890 return rc; 3891 } 3892 3893 static int bnxt_flash_device(struct net_device *dev, 3894 struct ethtool_flash *flash) 3895 { 3896 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 3897 netdev_err(dev, "flashdev not supported from a virtual function\n"); 3898 return -EINVAL; 3899 } 3900 3901 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 3902 flash->region > 0xffff) 3903 return bnxt_flash_package_from_file(dev, flash->data, 3904 flash->region, NULL); 3905 3906 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 3907 } 3908 3909 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 3910 { 3911 struct hwrm_nvm_get_dir_info_output *output; 3912 struct hwrm_nvm_get_dir_info_input *req; 3913 struct bnxt *bp = netdev_priv(dev); 3914 int rc; 3915 3916 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO); 3917 if (rc) 3918 return rc; 3919 3920 output = hwrm_req_hold(bp, req); 3921 rc = hwrm_req_send(bp, req); 3922 if (!rc) { 3923 *entries = le32_to_cpu(output->entries); 3924 *length = le32_to_cpu(output->entry_length); 3925 } 3926 hwrm_req_drop(bp, req); 3927 return rc; 3928 } 3929 3930 static int bnxt_get_eeprom_len(struct net_device *dev) 3931 { 3932 struct bnxt *bp = netdev_priv(dev); 3933 3934 if (BNXT_VF(bp)) 3935 return 0; 3936 3937 /* The -1 return value allows the entire 32-bit range of offsets to be 3938 * passed via the ethtool command-line utility. 3939 */ 3940 return -1; 3941 } 3942 3943 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 3944 { 3945 struct bnxt *bp = netdev_priv(dev); 3946 int rc; 3947 u32 dir_entries; 3948 u32 entry_length; 3949 u8 *buf; 3950 size_t buflen; 3951 dma_addr_t dma_handle; 3952 struct hwrm_nvm_get_dir_entries_input *req; 3953 3954 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 3955 if (rc != 0) 3956 return rc; 3957 3958 if (!dir_entries || !entry_length) 3959 return -EIO; 3960 3961 /* Insert 2 bytes of directory info (count and size of entries) */ 3962 if (len < 2) 3963 return -EINVAL; 3964 3965 *data++ = dir_entries; 3966 *data++ = entry_length; 3967 len -= 2; 3968 memset(data, 0xff, len); 3969 3970 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES); 3971 if (rc) 3972 return rc; 3973 3974 buflen = mul_u32_u32(dir_entries, entry_length); 3975 buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle); 3976 if (!buf) { 3977 hwrm_req_drop(bp, req); 3978 return -ENOMEM; 3979 } 3980 req->host_dest_addr = cpu_to_le64(dma_handle); 3981 3982 hwrm_req_hold(bp, req); /* hold the slice */ 3983 rc = hwrm_req_send(bp, req); 3984 if (rc == 0) 3985 memcpy(data, buf, len > buflen ? buflen : len); 3986 hwrm_req_drop(bp, req); 3987 return rc; 3988 } 3989 3990 int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 3991 u32 length, u8 *data) 3992 { 3993 struct bnxt *bp = netdev_priv(dev); 3994 int rc; 3995 u8 *buf; 3996 dma_addr_t dma_handle; 3997 struct hwrm_nvm_read_input *req; 3998 3999 if (!length) 4000 return -EINVAL; 4001 4002 rc = hwrm_req_init(bp, req, HWRM_NVM_READ); 4003 if (rc) 4004 return rc; 4005 4006 buf = hwrm_req_dma_slice(bp, req, length, &dma_handle); 4007 if (!buf) { 4008 hwrm_req_drop(bp, req); 4009 return -ENOMEM; 4010 } 4011 4012 req->host_dest_addr = cpu_to_le64(dma_handle); 4013 req->dir_idx = cpu_to_le16(index); 4014 req->offset = cpu_to_le32(offset); 4015 req->len = cpu_to_le32(length); 4016 4017 hwrm_req_hold(bp, req); /* hold the slice */ 4018 rc = hwrm_req_send(bp, req); 4019 if (rc == 0) 4020 memcpy(data, buf, length); 4021 hwrm_req_drop(bp, req); 4022 return rc; 4023 } 4024 4025 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 4026 u16 ext, u16 *index, u32 *item_length, 4027 u32 *data_length) 4028 { 4029 struct hwrm_nvm_find_dir_entry_output *output; 4030 struct hwrm_nvm_find_dir_entry_input *req; 4031 struct bnxt *bp = netdev_priv(dev); 4032 int rc; 4033 4034 rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY); 4035 if (rc) 4036 return rc; 4037 4038 req->enables = 0; 4039 req->dir_idx = 0; 4040 req->dir_type = cpu_to_le16(type); 4041 req->dir_ordinal = cpu_to_le16(ordinal); 4042 req->dir_ext = cpu_to_le16(ext); 4043 req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 4044 output = hwrm_req_hold(bp, req); 4045 rc = hwrm_req_send_silent(bp, req); 4046 if (rc == 0) { 4047 if (index) 4048 *index = le16_to_cpu(output->dir_idx); 4049 if (item_length) 4050 *item_length = le32_to_cpu(output->dir_item_length); 4051 if (data_length) 4052 *data_length = le32_to_cpu(output->dir_data_length); 4053 } 4054 hwrm_req_drop(bp, req); 4055 return rc; 4056 } 4057 4058 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 4059 { 4060 char *retval = NULL; 4061 char *p; 4062 char *value; 4063 int field = 0; 4064 4065 if (datalen < 1) 4066 return NULL; 4067 /* null-terminate the log data (removing last '\n'): */ 4068 data[datalen - 1] = 0; 4069 for (p = data; *p != 0; p++) { 4070 field = 0; 4071 retval = NULL; 4072 while (*p != 0 && *p != '\n') { 4073 value = p; 4074 while (*p != 0 && *p != '\t' && *p != '\n') 4075 p++; 4076 if (field == desired_field) 4077 retval = value; 4078 if (*p != '\t') 4079 break; 4080 *p = 0; 4081 field++; 4082 p++; 4083 } 4084 if (*p == 0) 4085 break; 4086 *p = 0; 4087 } 4088 return retval; 4089 } 4090 4091 int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size) 4092 { 4093 struct bnxt *bp = netdev_priv(dev); 4094 u16 index = 0; 4095 char *pkgver; 4096 u32 pkglen; 4097 u8 *pkgbuf; 4098 int rc; 4099 4100 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 4101 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 4102 &index, NULL, &pkglen); 4103 if (rc) 4104 return rc; 4105 4106 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 4107 if (!pkgbuf) { 4108 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 4109 pkglen); 4110 return -ENOMEM; 4111 } 4112 4113 rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf); 4114 if (rc) 4115 goto err; 4116 4117 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 4118 pkglen); 4119 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) 4120 strscpy(ver, pkgver, size); 4121 else 4122 rc = -ENOENT; 4123 4124 err: 4125 kfree(pkgbuf); 4126 4127 return rc; 4128 } 4129 4130 static void bnxt_get_pkgver(struct net_device *dev) 4131 { 4132 struct bnxt *bp = netdev_priv(dev); 4133 char buf[FW_VER_STR_LEN]; 4134 int len; 4135 4136 if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) { 4137 len = strlen(bp->fw_ver_str); 4138 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1, 4139 "/pkg %s", buf); 4140 } 4141 } 4142 4143 static int bnxt_get_eeprom(struct net_device *dev, 4144 struct ethtool_eeprom *eeprom, 4145 u8 *data) 4146 { 4147 u32 index; 4148 u32 offset; 4149 4150 if (eeprom->offset == 0) /* special offset value to get directory */ 4151 return bnxt_get_nvram_directory(dev, eeprom->len, data); 4152 4153 index = eeprom->offset >> 24; 4154 offset = eeprom->offset & 0xffffff; 4155 4156 if (index == 0) { 4157 netdev_err(dev, "unsupported index value: %d\n", index); 4158 return -EINVAL; 4159 } 4160 4161 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 4162 } 4163 4164 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 4165 { 4166 struct hwrm_nvm_erase_dir_entry_input *req; 4167 struct bnxt *bp = netdev_priv(dev); 4168 int rc; 4169 4170 rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY); 4171 if (rc) 4172 return rc; 4173 4174 req->dir_idx = cpu_to_le16(index); 4175 return hwrm_req_send(bp, req); 4176 } 4177 4178 static int bnxt_set_eeprom(struct net_device *dev, 4179 struct ethtool_eeprom *eeprom, 4180 u8 *data) 4181 { 4182 struct bnxt *bp = netdev_priv(dev); 4183 u8 index, dir_op; 4184 u16 type, ext, ordinal, attr; 4185 4186 if (!BNXT_PF(bp)) { 4187 netdev_err(dev, "NVM write not supported from a virtual function\n"); 4188 return -EINVAL; 4189 } 4190 4191 type = eeprom->magic >> 16; 4192 4193 if (type == 0xffff) { /* special value for directory operations */ 4194 index = eeprom->magic & 0xff; 4195 dir_op = eeprom->magic >> 8; 4196 if (index == 0) 4197 return -EINVAL; 4198 switch (dir_op) { 4199 case 0x0e: /* erase */ 4200 if (eeprom->offset != ~eeprom->magic) 4201 return -EINVAL; 4202 return bnxt_erase_nvram_directory(dev, index - 1); 4203 default: 4204 return -EINVAL; 4205 } 4206 } 4207 4208 /* Create or re-write an NVM item: */ 4209 if (bnxt_dir_type_is_executable(type)) 4210 return -EOPNOTSUPP; 4211 ext = eeprom->magic & 0xffff; 4212 ordinal = eeprom->offset >> 16; 4213 attr = eeprom->offset & 0xffff; 4214 4215 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data, 4216 eeprom->len); 4217 } 4218 4219 static int bnxt_set_eee(struct net_device *dev, struct ethtool_keee *edata) 4220 { 4221 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 4222 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp); 4223 struct bnxt *bp = netdev_priv(dev); 4224 struct ethtool_keee *eee = &bp->eee; 4225 struct bnxt_link_info *link_info = &bp->link_info; 4226 int rc = 0; 4227 4228 if (!BNXT_PHY_CFG_ABLE(bp)) 4229 return -EOPNOTSUPP; 4230 4231 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 4232 return -EOPNOTSUPP; 4233 4234 mutex_lock(&bp->link_lock); 4235 _bnxt_fw_to_linkmode(advertising, link_info->advertising); 4236 if (!edata->eee_enabled) 4237 goto eee_ok; 4238 4239 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 4240 netdev_warn(dev, "EEE requires autoneg\n"); 4241 rc = -EINVAL; 4242 goto eee_exit; 4243 } 4244 if (edata->tx_lpi_enabled) { 4245 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 4246 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 4247 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 4248 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 4249 rc = -EINVAL; 4250 goto eee_exit; 4251 } else if (!bp->lpi_tmr_hi) { 4252 edata->tx_lpi_timer = eee->tx_lpi_timer; 4253 } 4254 } 4255 if (linkmode_empty(edata->advertised)) { 4256 linkmode_and(edata->advertised, advertising, eee->supported); 4257 } else if (linkmode_andnot(tmp, edata->advertised, advertising)) { 4258 netdev_warn(dev, "EEE advertised must be a subset of autoneg advertised speeds\n"); 4259 rc = -EINVAL; 4260 goto eee_exit; 4261 } 4262 4263 linkmode_copy(eee->advertised, edata->advertised); 4264 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 4265 eee->tx_lpi_timer = edata->tx_lpi_timer; 4266 eee_ok: 4267 eee->eee_enabled = edata->eee_enabled; 4268 4269 if (netif_running(dev)) 4270 rc = bnxt_hwrm_set_link_setting(bp, false, true); 4271 4272 eee_exit: 4273 mutex_unlock(&bp->link_lock); 4274 return rc; 4275 } 4276 4277 static int bnxt_get_eee(struct net_device *dev, struct ethtool_keee *edata) 4278 { 4279 struct bnxt *bp = netdev_priv(dev); 4280 4281 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 4282 return -EOPNOTSUPP; 4283 4284 *edata = bp->eee; 4285 if (!bp->eee.eee_enabled) { 4286 /* Preserve tx_lpi_timer so that the last value will be used 4287 * by default when it is re-enabled. 4288 */ 4289 linkmode_zero(edata->advertised); 4290 edata->tx_lpi_enabled = 0; 4291 } 4292 4293 if (!bp->eee.eee_active) 4294 linkmode_zero(edata->lp_advertised); 4295 4296 return 0; 4297 } 4298 4299 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 4300 u16 page_number, u8 bank, 4301 u16 start_addr, u16 data_length, 4302 u8 *buf) 4303 { 4304 struct hwrm_port_phy_i2c_read_output *output; 4305 struct hwrm_port_phy_i2c_read_input *req; 4306 int rc, byte_offset = 0; 4307 4308 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ); 4309 if (rc) 4310 return rc; 4311 4312 output = hwrm_req_hold(bp, req); 4313 req->i2c_slave_addr = i2c_addr; 4314 req->page_number = cpu_to_le16(page_number); 4315 req->port_id = cpu_to_le16(bp->pf.port_id); 4316 do { 4317 u16 xfer_size; 4318 4319 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 4320 data_length -= xfer_size; 4321 req->page_offset = cpu_to_le16(start_addr + byte_offset); 4322 req->data_length = xfer_size; 4323 req->enables = 4324 cpu_to_le32((start_addr + byte_offset ? 4325 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 4326 0) | 4327 (bank ? 4328 PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER : 4329 0)); 4330 rc = hwrm_req_send(bp, req); 4331 if (!rc) 4332 memcpy(buf + byte_offset, output->data, xfer_size); 4333 byte_offset += xfer_size; 4334 } while (!rc && data_length > 0); 4335 hwrm_req_drop(bp, req); 4336 4337 return rc; 4338 } 4339 4340 static int bnxt_get_module_info(struct net_device *dev, 4341 struct ethtool_modinfo *modinfo) 4342 { 4343 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 4344 struct bnxt *bp = netdev_priv(dev); 4345 int rc; 4346 4347 /* No point in going further if phy status indicates 4348 * module is not inserted or if it is powered down or 4349 * if it is of type 10GBase-T 4350 */ 4351 if (bp->link_info.module_status > 4352 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 4353 return -EOPNOTSUPP; 4354 4355 /* This feature is not supported in older firmware versions */ 4356 if (bp->hwrm_spec_code < 0x10202) 4357 return -EOPNOTSUPP; 4358 4359 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 0, 4360 SFF_DIAG_SUPPORT_OFFSET + 1, 4361 data); 4362 if (!rc) { 4363 u8 module_id = data[0]; 4364 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 4365 4366 switch (module_id) { 4367 case SFF_MODULE_ID_SFP: 4368 modinfo->type = ETH_MODULE_SFF_8472; 4369 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 4370 if (!diag_supported) 4371 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 4372 break; 4373 case SFF_MODULE_ID_QSFP: 4374 case SFF_MODULE_ID_QSFP_PLUS: 4375 modinfo->type = ETH_MODULE_SFF_8436; 4376 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 4377 break; 4378 case SFF_MODULE_ID_QSFP28: 4379 modinfo->type = ETH_MODULE_SFF_8636; 4380 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 4381 break; 4382 default: 4383 rc = -EOPNOTSUPP; 4384 break; 4385 } 4386 } 4387 return rc; 4388 } 4389 4390 static int bnxt_get_module_eeprom(struct net_device *dev, 4391 struct ethtool_eeprom *eeprom, 4392 u8 *data) 4393 { 4394 struct bnxt *bp = netdev_priv(dev); 4395 u16 start = eeprom->offset, length = eeprom->len; 4396 int rc = 0; 4397 4398 memset(data, 0, eeprom->len); 4399 4400 /* Read A0 portion of the EEPROM */ 4401 if (start < ETH_MODULE_SFF_8436_LEN) { 4402 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 4403 length = ETH_MODULE_SFF_8436_LEN - start; 4404 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 4405 start, length, data); 4406 if (rc) 4407 return rc; 4408 start += length; 4409 data += length; 4410 length = eeprom->len - length; 4411 } 4412 4413 /* Read A2 portion of the EEPROM */ 4414 if (length) { 4415 start -= ETH_MODULE_SFF_8436_LEN; 4416 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 0, 4417 start, length, data); 4418 } 4419 return rc; 4420 } 4421 4422 static int bnxt_get_module_status(struct bnxt *bp, struct netlink_ext_ack *extack) 4423 { 4424 if (bp->link_info.module_status <= 4425 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 4426 return 0; 4427 4428 switch (bp->link_info.module_status) { 4429 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 4430 NL_SET_ERR_MSG_MOD(extack, "Transceiver module is powering down"); 4431 break; 4432 case PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED: 4433 NL_SET_ERR_MSG_MOD(extack, "Transceiver module not inserted"); 4434 break; 4435 case PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT: 4436 NL_SET_ERR_MSG_MOD(extack, "Transceiver module disabled due to current fault"); 4437 break; 4438 default: 4439 NL_SET_ERR_MSG_MOD(extack, "Unknown error"); 4440 break; 4441 } 4442 return -EINVAL; 4443 } 4444 4445 static int bnxt_get_module_eeprom_by_page(struct net_device *dev, 4446 const struct ethtool_module_eeprom *page_data, 4447 struct netlink_ext_ack *extack) 4448 { 4449 struct bnxt *bp = netdev_priv(dev); 4450 int rc; 4451 4452 rc = bnxt_get_module_status(bp, extack); 4453 if (rc) 4454 return rc; 4455 4456 if (bp->hwrm_spec_code < 0x10202) { 4457 NL_SET_ERR_MSG_MOD(extack, "Firmware version too old"); 4458 return -EINVAL; 4459 } 4460 4461 if (page_data->bank && !(bp->phy_flags & BNXT_PHY_FL_BANK_SEL)) { 4462 NL_SET_ERR_MSG_MOD(extack, "Firmware not capable for bank selection"); 4463 return -EINVAL; 4464 } 4465 4466 rc = bnxt_read_sfp_module_eeprom_info(bp, page_data->i2c_address << 1, 4467 page_data->page, page_data->bank, 4468 page_data->offset, 4469 page_data->length, 4470 page_data->data); 4471 if (rc) { 4472 NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom read failed"); 4473 return rc; 4474 } 4475 return page_data->length; 4476 } 4477 4478 static int bnxt_nway_reset(struct net_device *dev) 4479 { 4480 int rc = 0; 4481 4482 struct bnxt *bp = netdev_priv(dev); 4483 struct bnxt_link_info *link_info = &bp->link_info; 4484 4485 if (!BNXT_PHY_CFG_ABLE(bp)) 4486 return -EOPNOTSUPP; 4487 4488 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 4489 return -EINVAL; 4490 4491 if (netif_running(dev)) 4492 rc = bnxt_hwrm_set_link_setting(bp, true, false); 4493 4494 return rc; 4495 } 4496 4497 static int bnxt_set_phys_id(struct net_device *dev, 4498 enum ethtool_phys_id_state state) 4499 { 4500 struct hwrm_port_led_cfg_input *req; 4501 struct bnxt *bp = netdev_priv(dev); 4502 struct bnxt_pf_info *pf = &bp->pf; 4503 struct bnxt_led_cfg *led_cfg; 4504 u8 led_state; 4505 __le16 duration; 4506 int rc, i; 4507 4508 if (!bp->num_leds || BNXT_VF(bp)) 4509 return -EOPNOTSUPP; 4510 4511 if (state == ETHTOOL_ID_ACTIVE) { 4512 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 4513 duration = cpu_to_le16(500); 4514 } else if (state == ETHTOOL_ID_INACTIVE) { 4515 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 4516 duration = cpu_to_le16(0); 4517 } else { 4518 return -EINVAL; 4519 } 4520 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG); 4521 if (rc) 4522 return rc; 4523 4524 req->port_id = cpu_to_le16(pf->port_id); 4525 req->num_leds = bp->num_leds; 4526 led_cfg = (struct bnxt_led_cfg *)&req->led0_id; 4527 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 4528 req->enables |= BNXT_LED_DFLT_ENABLES(i); 4529 led_cfg->led_id = bp->leds[i].led_id; 4530 led_cfg->led_state = led_state; 4531 led_cfg->led_blink_on = duration; 4532 led_cfg->led_blink_off = duration; 4533 led_cfg->led_group_id = bp->leds[i].led_group_id; 4534 } 4535 return hwrm_req_send(bp, req); 4536 } 4537 4538 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 4539 { 4540 struct hwrm_selftest_irq_input *req; 4541 int rc; 4542 4543 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ); 4544 if (rc) 4545 return rc; 4546 4547 req->cmpl_ring = cpu_to_le16(cmpl_ring); 4548 return hwrm_req_send(bp, req); 4549 } 4550 4551 static int bnxt_test_irq(struct bnxt *bp) 4552 { 4553 int i; 4554 4555 for (i = 0; i < bp->cp_nr_rings; i++) { 4556 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 4557 int rc; 4558 4559 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 4560 if (rc) 4561 return rc; 4562 } 4563 return 0; 4564 } 4565 4566 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 4567 { 4568 struct hwrm_port_mac_cfg_input *req; 4569 int rc; 4570 4571 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 4572 if (rc) 4573 return rc; 4574 4575 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 4576 if (enable) 4577 req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 4578 else 4579 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 4580 return hwrm_req_send(bp, req); 4581 } 4582 4583 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 4584 { 4585 struct hwrm_port_phy_qcaps_output *resp; 4586 struct hwrm_port_phy_qcaps_input *req; 4587 int rc; 4588 4589 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS); 4590 if (rc) 4591 return rc; 4592 4593 resp = hwrm_req_hold(bp, req); 4594 rc = hwrm_req_send(bp, req); 4595 if (!rc) 4596 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 4597 4598 hwrm_req_drop(bp, req); 4599 return rc; 4600 } 4601 4602 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 4603 struct hwrm_port_phy_cfg_input *req) 4604 { 4605 struct bnxt_link_info *link_info = &bp->link_info; 4606 u16 fw_advertising; 4607 u16 fw_speed; 4608 int rc; 4609 4610 if (!link_info->autoneg || 4611 (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK)) 4612 return 0; 4613 4614 rc = bnxt_query_force_speeds(bp, &fw_advertising); 4615 if (rc) 4616 return rc; 4617 4618 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 4619 if (BNXT_LINK_IS_UP(bp)) 4620 fw_speed = bp->link_info.link_speed; 4621 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 4622 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 4623 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 4624 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 4625 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 4626 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 4627 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 4628 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 4629 4630 req->force_link_speed = cpu_to_le16(fw_speed); 4631 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 4632 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 4633 rc = hwrm_req_send(bp, req); 4634 req->flags = 0; 4635 req->force_link_speed = cpu_to_le16(0); 4636 return rc; 4637 } 4638 4639 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 4640 { 4641 struct hwrm_port_phy_cfg_input *req; 4642 int rc; 4643 4644 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 4645 if (rc) 4646 return rc; 4647 4648 /* prevent bnxt_disable_an_for_lpbk() from consuming the request */ 4649 hwrm_req_hold(bp, req); 4650 4651 if (enable) { 4652 bnxt_disable_an_for_lpbk(bp, req); 4653 if (ext) 4654 req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 4655 else 4656 req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 4657 } else { 4658 req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 4659 } 4660 req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 4661 rc = hwrm_req_send(bp, req); 4662 hwrm_req_drop(bp, req); 4663 return rc; 4664 } 4665 4666 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 4667 u32 raw_cons, int pkt_size) 4668 { 4669 struct bnxt_napi *bnapi = cpr->bnapi; 4670 struct bnxt_rx_ring_info *rxr; 4671 struct bnxt_sw_rx_bd *rx_buf; 4672 struct rx_cmp *rxcmp; 4673 u16 cp_cons, cons; 4674 u8 *data; 4675 u32 len; 4676 int i; 4677 4678 rxr = bnapi->rx_ring; 4679 cp_cons = RING_CMP(raw_cons); 4680 rxcmp = (struct rx_cmp *) 4681 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 4682 cons = rxcmp->rx_cmp_opaque; 4683 rx_buf = &rxr->rx_buf_ring[cons]; 4684 data = rx_buf->data_ptr; 4685 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 4686 if (len != pkt_size) 4687 return -EIO; 4688 i = ETH_ALEN; 4689 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 4690 return -EIO; 4691 i += ETH_ALEN; 4692 for ( ; i < pkt_size; i++) { 4693 if (data[i] != (u8)(i & 0xff)) 4694 return -EIO; 4695 } 4696 return 0; 4697 } 4698 4699 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 4700 int pkt_size) 4701 { 4702 struct tx_cmp *txcmp; 4703 int rc = -EIO; 4704 u32 raw_cons; 4705 u32 cons; 4706 int i; 4707 4708 raw_cons = cpr->cp_raw_cons; 4709 for (i = 0; i < 200; i++) { 4710 cons = RING_CMP(raw_cons); 4711 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 4712 4713 if (!TX_CMP_VALID(txcmp, raw_cons)) { 4714 udelay(5); 4715 continue; 4716 } 4717 4718 /* The valid test of the entry must be done first before 4719 * reading any further. 4720 */ 4721 dma_rmb(); 4722 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP || 4723 TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_V3_CMP) { 4724 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 4725 raw_cons = NEXT_RAW_CMP(raw_cons); 4726 raw_cons = NEXT_RAW_CMP(raw_cons); 4727 break; 4728 } 4729 raw_cons = NEXT_RAW_CMP(raw_cons); 4730 } 4731 cpr->cp_raw_cons = raw_cons; 4732 return rc; 4733 } 4734 4735 static int bnxt_run_loopback(struct bnxt *bp) 4736 { 4737 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 4738 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 4739 struct bnxt_cp_ring_info *cpr; 4740 int pkt_size, i = 0; 4741 struct sk_buff *skb; 4742 dma_addr_t map; 4743 u8 *data; 4744 int rc; 4745 4746 cpr = &rxr->bnapi->cp_ring; 4747 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) 4748 cpr = rxr->rx_cpr; 4749 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh); 4750 skb = netdev_alloc_skb(bp->dev, pkt_size); 4751 if (!skb) 4752 return -ENOMEM; 4753 data = skb_put(skb, pkt_size); 4754 ether_addr_copy(&data[i], bp->dev->dev_addr); 4755 i += ETH_ALEN; 4756 ether_addr_copy(&data[i], bp->dev->dev_addr); 4757 i += ETH_ALEN; 4758 for ( ; i < pkt_size; i++) 4759 data[i] = (u8)(i & 0xff); 4760 4761 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 4762 DMA_TO_DEVICE); 4763 if (dma_mapping_error(&bp->pdev->dev, map)) { 4764 dev_kfree_skb(skb); 4765 return -EIO; 4766 } 4767 bnxt_xmit_bd(bp, txr, map, pkt_size, NULL); 4768 4769 /* Sync BD data before updating doorbell */ 4770 wmb(); 4771 4772 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 4773 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 4774 4775 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE); 4776 dev_kfree_skb(skb); 4777 return rc; 4778 } 4779 4780 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 4781 { 4782 struct hwrm_selftest_exec_output *resp; 4783 struct hwrm_selftest_exec_input *req; 4784 int rc; 4785 4786 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC); 4787 if (rc) 4788 return rc; 4789 4790 hwrm_req_timeout(bp, req, bp->test_info->timeout); 4791 req->flags = test_mask; 4792 4793 resp = hwrm_req_hold(bp, req); 4794 rc = hwrm_req_send(bp, req); 4795 *test_results = resp->test_success; 4796 hwrm_req_drop(bp, req); 4797 return rc; 4798 } 4799 4800 #define BNXT_DRV_TESTS 4 4801 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 4802 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 4803 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 4804 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 4805 4806 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 4807 u64 *buf) 4808 { 4809 struct bnxt *bp = netdev_priv(dev); 4810 bool do_ext_lpbk = false; 4811 bool offline = false; 4812 u8 test_results = 0; 4813 u8 test_mask = 0; 4814 int rc = 0, i; 4815 4816 if (!bp->num_tests || !BNXT_PF(bp)) 4817 return; 4818 memset(buf, 0, sizeof(u64) * bp->num_tests); 4819 if (!netif_running(dev)) { 4820 etest->flags |= ETH_TEST_FL_FAILED; 4821 return; 4822 } 4823 4824 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 4825 (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK)) 4826 do_ext_lpbk = true; 4827 4828 if (etest->flags & ETH_TEST_FL_OFFLINE) { 4829 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) { 4830 etest->flags |= ETH_TEST_FL_FAILED; 4831 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n"); 4832 return; 4833 } 4834 offline = true; 4835 } 4836 4837 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 4838 u8 bit_val = 1 << i; 4839 4840 if (!(bp->test_info->offline_mask & bit_val)) 4841 test_mask |= bit_val; 4842 else if (offline) 4843 test_mask |= bit_val; 4844 } 4845 if (!offline) { 4846 bnxt_run_fw_tests(bp, test_mask, &test_results); 4847 } else { 4848 bnxt_ulp_stop(bp); 4849 bnxt_close_nic(bp, true, false); 4850 bnxt_run_fw_tests(bp, test_mask, &test_results); 4851 4852 buf[BNXT_MACLPBK_TEST_IDX] = 1; 4853 bnxt_hwrm_mac_loopback(bp, true); 4854 msleep(250); 4855 rc = bnxt_half_open_nic(bp); 4856 if (rc) { 4857 bnxt_hwrm_mac_loopback(bp, false); 4858 etest->flags |= ETH_TEST_FL_FAILED; 4859 bnxt_ulp_start(bp, rc); 4860 return; 4861 } 4862 if (bnxt_run_loopback(bp)) 4863 etest->flags |= ETH_TEST_FL_FAILED; 4864 else 4865 buf[BNXT_MACLPBK_TEST_IDX] = 0; 4866 4867 bnxt_hwrm_mac_loopback(bp, false); 4868 bnxt_hwrm_phy_loopback(bp, true, false); 4869 msleep(1000); 4870 if (bnxt_run_loopback(bp)) { 4871 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 4872 etest->flags |= ETH_TEST_FL_FAILED; 4873 } 4874 if (do_ext_lpbk) { 4875 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 4876 bnxt_hwrm_phy_loopback(bp, true, true); 4877 msleep(1000); 4878 if (bnxt_run_loopback(bp)) { 4879 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 4880 etest->flags |= ETH_TEST_FL_FAILED; 4881 } 4882 } 4883 bnxt_hwrm_phy_loopback(bp, false, false); 4884 bnxt_half_close_nic(bp); 4885 rc = bnxt_open_nic(bp, true, true); 4886 bnxt_ulp_start(bp, rc); 4887 } 4888 if (rc || bnxt_test_irq(bp)) { 4889 buf[BNXT_IRQ_TEST_IDX] = 1; 4890 etest->flags |= ETH_TEST_FL_FAILED; 4891 } 4892 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 4893 u8 bit_val = 1 << i; 4894 4895 if ((test_mask & bit_val) && !(test_results & bit_val)) { 4896 buf[i] = 1; 4897 etest->flags |= ETH_TEST_FL_FAILED; 4898 } 4899 } 4900 } 4901 4902 static int bnxt_reset(struct net_device *dev, u32 *flags) 4903 { 4904 struct bnxt *bp = netdev_priv(dev); 4905 bool reload = false; 4906 u32 req = *flags; 4907 4908 if (!req) 4909 return -EINVAL; 4910 4911 if (!BNXT_PF(bp)) { 4912 netdev_err(dev, "Reset is not supported from a VF\n"); 4913 return -EOPNOTSUPP; 4914 } 4915 4916 if (pci_vfs_assigned(bp->pdev) && 4917 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) { 4918 netdev_err(dev, 4919 "Reset not allowed when VFs are assigned to VMs\n"); 4920 return -EBUSY; 4921 } 4922 4923 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) { 4924 /* This feature is not supported in older firmware versions */ 4925 if (bp->hwrm_spec_code >= 0x10803) { 4926 if (!bnxt_firmware_reset_chip(dev)) { 4927 netdev_info(dev, "Firmware reset request successful.\n"); 4928 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) 4929 reload = true; 4930 *flags &= ~BNXT_FW_RESET_CHIP; 4931 } 4932 } else if (req == BNXT_FW_RESET_CHIP) { 4933 return -EOPNOTSUPP; /* only request, fail hard */ 4934 } 4935 } 4936 4937 if (!BNXT_CHIP_P4_PLUS(bp) && (req & BNXT_FW_RESET_AP)) { 4938 /* This feature is not supported in older firmware versions */ 4939 if (bp->hwrm_spec_code >= 0x10803) { 4940 if (!bnxt_firmware_reset_ap(dev)) { 4941 netdev_info(dev, "Reset application processor successful.\n"); 4942 reload = true; 4943 *flags &= ~BNXT_FW_RESET_AP; 4944 } 4945 } else if (req == BNXT_FW_RESET_AP) { 4946 return -EOPNOTSUPP; /* only request, fail hard */ 4947 } 4948 } 4949 4950 if (reload) 4951 netdev_info(dev, "Reload driver to complete reset\n"); 4952 4953 return 0; 4954 } 4955 4956 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump) 4957 { 4958 struct bnxt *bp = netdev_priv(dev); 4959 4960 if (dump->flag > BNXT_DUMP_CRASH) { 4961 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n"); 4962 return -EINVAL; 4963 } 4964 4965 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) { 4966 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n"); 4967 return -EOPNOTSUPP; 4968 } 4969 4970 bp->dump_flag = dump->flag; 4971 return 0; 4972 } 4973 4974 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 4975 { 4976 struct bnxt *bp = netdev_priv(dev); 4977 4978 if (bp->hwrm_spec_code < 0x10801) 4979 return -EOPNOTSUPP; 4980 4981 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 4982 bp->ver_resp.hwrm_fw_min_8b << 16 | 4983 bp->ver_resp.hwrm_fw_bld_8b << 8 | 4984 bp->ver_resp.hwrm_fw_rsvd_8b; 4985 4986 dump->flag = bp->dump_flag; 4987 dump->len = bnxt_get_coredump_length(bp, bp->dump_flag); 4988 return 0; 4989 } 4990 4991 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 4992 void *buf) 4993 { 4994 struct bnxt *bp = netdev_priv(dev); 4995 4996 if (bp->hwrm_spec_code < 0x10801) 4997 return -EOPNOTSUPP; 4998 4999 memset(buf, 0, dump->len); 5000 5001 dump->flag = bp->dump_flag; 5002 return bnxt_get_coredump(bp, dump->flag, buf, &dump->len); 5003 } 5004 5005 static int bnxt_get_ts_info(struct net_device *dev, 5006 struct ethtool_ts_info *info) 5007 { 5008 struct bnxt *bp = netdev_priv(dev); 5009 struct bnxt_ptp_cfg *ptp; 5010 5011 ptp = bp->ptp_cfg; 5012 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 5013 SOF_TIMESTAMPING_RX_SOFTWARE | 5014 SOF_TIMESTAMPING_SOFTWARE; 5015 5016 info->phc_index = -1; 5017 if (!ptp) 5018 return 0; 5019 5020 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | 5021 SOF_TIMESTAMPING_RX_HARDWARE | 5022 SOF_TIMESTAMPING_RAW_HARDWARE; 5023 if (ptp->ptp_clock) 5024 info->phc_index = ptp_clock_index(ptp->ptp_clock); 5025 5026 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 5027 5028 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 5029 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 5030 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 5031 5032 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) 5033 info->rx_filters |= (1 << HWTSTAMP_FILTER_ALL); 5034 return 0; 5035 } 5036 5037 void bnxt_ethtool_init(struct bnxt *bp) 5038 { 5039 struct hwrm_selftest_qlist_output *resp; 5040 struct hwrm_selftest_qlist_input *req; 5041 struct bnxt_test_info *test_info; 5042 struct net_device *dev = bp->dev; 5043 int i, rc; 5044 5045 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 5046 bnxt_get_pkgver(dev); 5047 5048 bp->num_tests = 0; 5049 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp)) 5050 return; 5051 5052 test_info = bp->test_info; 5053 if (!test_info) { 5054 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL); 5055 if (!test_info) 5056 return; 5057 bp->test_info = test_info; 5058 } 5059 5060 if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST)) 5061 return; 5062 5063 resp = hwrm_req_hold(bp, req); 5064 rc = hwrm_req_send_silent(bp, req); 5065 if (rc) 5066 goto ethtool_init_exit; 5067 5068 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 5069 if (bp->num_tests > BNXT_MAX_TEST) 5070 bp->num_tests = BNXT_MAX_TEST; 5071 5072 test_info->offline_mask = resp->offline_tests; 5073 test_info->timeout = le16_to_cpu(resp->test_timeout); 5074 if (!test_info->timeout) 5075 test_info->timeout = HWRM_CMD_TIMEOUT; 5076 for (i = 0; i < bp->num_tests; i++) { 5077 char *str = test_info->string[i]; 5078 char *fw_str = resp->test_name[i]; 5079 5080 if (i == BNXT_MACLPBK_TEST_IDX) { 5081 strcpy(str, "Mac loopback test (offline)"); 5082 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 5083 strcpy(str, "Phy loopback test (offline)"); 5084 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 5085 strcpy(str, "Ext loopback test (offline)"); 5086 } else if (i == BNXT_IRQ_TEST_IDX) { 5087 strcpy(str, "Interrupt_test (offline)"); 5088 } else { 5089 snprintf(str, ETH_GSTRING_LEN, "%s test (%s)", 5090 fw_str, test_info->offline_mask & (1 << i) ? 5091 "offline" : "online"); 5092 } 5093 } 5094 5095 ethtool_init_exit: 5096 hwrm_req_drop(bp, req); 5097 } 5098 5099 static void bnxt_get_eth_phy_stats(struct net_device *dev, 5100 struct ethtool_eth_phy_stats *phy_stats) 5101 { 5102 struct bnxt *bp = netdev_priv(dev); 5103 u64 *rx; 5104 5105 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 5106 return; 5107 5108 rx = bp->rx_port_stats_ext.sw_stats; 5109 phy_stats->SymbolErrorDuringCarrier = 5110 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err)); 5111 } 5112 5113 static void bnxt_get_eth_mac_stats(struct net_device *dev, 5114 struct ethtool_eth_mac_stats *mac_stats) 5115 { 5116 struct bnxt *bp = netdev_priv(dev); 5117 u64 *rx, *tx; 5118 5119 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5120 return; 5121 5122 rx = bp->port_stats.sw_stats; 5123 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 5124 5125 mac_stats->FramesReceivedOK = 5126 BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames); 5127 mac_stats->FramesTransmittedOK = 5128 BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames); 5129 mac_stats->FrameCheckSequenceErrors = 5130 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames); 5131 mac_stats->AlignmentErrors = 5132 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames); 5133 mac_stats->OutOfRangeLengthField = 5134 BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames); 5135 } 5136 5137 static void bnxt_get_eth_ctrl_stats(struct net_device *dev, 5138 struct ethtool_eth_ctrl_stats *ctrl_stats) 5139 { 5140 struct bnxt *bp = netdev_priv(dev); 5141 u64 *rx; 5142 5143 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5144 return; 5145 5146 rx = bp->port_stats.sw_stats; 5147 ctrl_stats->MACControlFramesReceived = 5148 BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames); 5149 } 5150 5151 static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = { 5152 { 0, 64 }, 5153 { 65, 127 }, 5154 { 128, 255 }, 5155 { 256, 511 }, 5156 { 512, 1023 }, 5157 { 1024, 1518 }, 5158 { 1519, 2047 }, 5159 { 2048, 4095 }, 5160 { 4096, 9216 }, 5161 { 9217, 16383 }, 5162 {} 5163 }; 5164 5165 static void bnxt_get_rmon_stats(struct net_device *dev, 5166 struct ethtool_rmon_stats *rmon_stats, 5167 const struct ethtool_rmon_hist_range **ranges) 5168 { 5169 struct bnxt *bp = netdev_priv(dev); 5170 u64 *rx, *tx; 5171 5172 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5173 return; 5174 5175 rx = bp->port_stats.sw_stats; 5176 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 5177 5178 rmon_stats->jabbers = 5179 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames); 5180 rmon_stats->oversize_pkts = 5181 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames); 5182 rmon_stats->undersize_pkts = 5183 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames); 5184 5185 rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames); 5186 rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames); 5187 rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames); 5188 rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames); 5189 rmon_stats->hist[4] = 5190 BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames); 5191 rmon_stats->hist[5] = 5192 BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames); 5193 rmon_stats->hist[6] = 5194 BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames); 5195 rmon_stats->hist[7] = 5196 BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames); 5197 rmon_stats->hist[8] = 5198 BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames); 5199 rmon_stats->hist[9] = 5200 BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames); 5201 5202 rmon_stats->hist_tx[0] = 5203 BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames); 5204 rmon_stats->hist_tx[1] = 5205 BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames); 5206 rmon_stats->hist_tx[2] = 5207 BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames); 5208 rmon_stats->hist_tx[3] = 5209 BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames); 5210 rmon_stats->hist_tx[4] = 5211 BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames); 5212 rmon_stats->hist_tx[5] = 5213 BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames); 5214 rmon_stats->hist_tx[6] = 5215 BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames); 5216 rmon_stats->hist_tx[7] = 5217 BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames); 5218 rmon_stats->hist_tx[8] = 5219 BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames); 5220 rmon_stats->hist_tx[9] = 5221 BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames); 5222 5223 *ranges = bnxt_rmon_ranges; 5224 } 5225 5226 static void bnxt_get_link_ext_stats(struct net_device *dev, 5227 struct ethtool_link_ext_stats *stats) 5228 { 5229 struct bnxt *bp = netdev_priv(dev); 5230 u64 *rx; 5231 5232 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 5233 return; 5234 5235 rx = bp->rx_port_stats_ext.sw_stats; 5236 stats->link_down_events = 5237 *(rx + BNXT_RX_STATS_EXT_OFFSET(link_down_events)); 5238 } 5239 5240 void bnxt_ethtool_free(struct bnxt *bp) 5241 { 5242 kfree(bp->test_info); 5243 bp->test_info = NULL; 5244 } 5245 5246 const struct ethtool_ops bnxt_ethtool_ops = { 5247 .cap_link_lanes_supported = 1, 5248 .cap_rss_ctx_supported = 1, 5249 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 5250 ETHTOOL_COALESCE_MAX_FRAMES | 5251 ETHTOOL_COALESCE_USECS_IRQ | 5252 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 5253 ETHTOOL_COALESCE_STATS_BLOCK_USECS | 5254 ETHTOOL_COALESCE_USE_ADAPTIVE_RX | 5255 ETHTOOL_COALESCE_USE_CQE, 5256 .get_link_ksettings = bnxt_get_link_ksettings, 5257 .set_link_ksettings = bnxt_set_link_ksettings, 5258 .get_fec_stats = bnxt_get_fec_stats, 5259 .get_fecparam = bnxt_get_fecparam, 5260 .set_fecparam = bnxt_set_fecparam, 5261 .get_pause_stats = bnxt_get_pause_stats, 5262 .get_pauseparam = bnxt_get_pauseparam, 5263 .set_pauseparam = bnxt_set_pauseparam, 5264 .get_drvinfo = bnxt_get_drvinfo, 5265 .get_regs_len = bnxt_get_regs_len, 5266 .get_regs = bnxt_get_regs, 5267 .get_wol = bnxt_get_wol, 5268 .set_wol = bnxt_set_wol, 5269 .get_coalesce = bnxt_get_coalesce, 5270 .set_coalesce = bnxt_set_coalesce, 5271 .get_msglevel = bnxt_get_msglevel, 5272 .set_msglevel = bnxt_set_msglevel, 5273 .get_sset_count = bnxt_get_sset_count, 5274 .get_strings = bnxt_get_strings, 5275 .get_ethtool_stats = bnxt_get_ethtool_stats, 5276 .set_ringparam = bnxt_set_ringparam, 5277 .get_ringparam = bnxt_get_ringparam, 5278 .get_channels = bnxt_get_channels, 5279 .set_channels = bnxt_set_channels, 5280 .get_rxnfc = bnxt_get_rxnfc, 5281 .set_rxnfc = bnxt_set_rxnfc, 5282 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 5283 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 5284 .get_rxfh = bnxt_get_rxfh, 5285 .set_rxfh = bnxt_set_rxfh, 5286 .flash_device = bnxt_flash_device, 5287 .get_eeprom_len = bnxt_get_eeprom_len, 5288 .get_eeprom = bnxt_get_eeprom, 5289 .set_eeprom = bnxt_set_eeprom, 5290 .get_link = bnxt_get_link, 5291 .get_link_ext_stats = bnxt_get_link_ext_stats, 5292 .get_eee = bnxt_get_eee, 5293 .set_eee = bnxt_set_eee, 5294 .get_module_info = bnxt_get_module_info, 5295 .get_module_eeprom = bnxt_get_module_eeprom, 5296 .get_module_eeprom_by_page = bnxt_get_module_eeprom_by_page, 5297 .nway_reset = bnxt_nway_reset, 5298 .set_phys_id = bnxt_set_phys_id, 5299 .self_test = bnxt_self_test, 5300 .get_ts_info = bnxt_get_ts_info, 5301 .reset = bnxt_reset, 5302 .set_dump = bnxt_set_dump, 5303 .get_dump_flag = bnxt_get_dump_flag, 5304 .get_dump_data = bnxt_get_dump_data, 5305 .get_eth_phy_stats = bnxt_get_eth_phy_stats, 5306 .get_eth_mac_stats = bnxt_get_eth_mac_stats, 5307 .get_eth_ctrl_stats = bnxt_get_eth_ctrl_stats, 5308 .get_rmon_stats = bnxt_get_rmon_stats, 5309 }; 5310