1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/bitops.h> 12 #include <linux/ctype.h> 13 #include <linux/stringify.h> 14 #include <linux/ethtool.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/linkmode.h> 17 #include <linux/interrupt.h> 18 #include <linux/pci.h> 19 #include <linux/etherdevice.h> 20 #include <linux/crc32.h> 21 #include <linux/firmware.h> 22 #include <linux/utsname.h> 23 #include <linux/time.h> 24 #include <linux/ptp_clock_kernel.h> 25 #include <linux/net_tstamp.h> 26 #include <linux/timecounter.h> 27 #include <net/netlink.h> 28 #include "bnxt_hsi.h" 29 #include "bnxt.h" 30 #include "bnxt_hwrm.h" 31 #include "bnxt_ulp.h" 32 #include "bnxt_xdp.h" 33 #include "bnxt_ptp.h" 34 #include "bnxt_ethtool.h" 35 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 36 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 37 #include "bnxt_coredump.h" 38 39 #define BNXT_NVM_ERR_MSG(dev, extack, msg) \ 40 do { \ 41 if (extack) \ 42 NL_SET_ERR_MSG_MOD(extack, msg); \ 43 netdev_err(dev, "%s\n", msg); \ 44 } while (0) 45 46 static u32 bnxt_get_msglevel(struct net_device *dev) 47 { 48 struct bnxt *bp = netdev_priv(dev); 49 50 return bp->msg_enable; 51 } 52 53 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 54 { 55 struct bnxt *bp = netdev_priv(dev); 56 57 bp->msg_enable = value; 58 } 59 60 static int bnxt_get_coalesce(struct net_device *dev, 61 struct ethtool_coalesce *coal, 62 struct kernel_ethtool_coalesce *kernel_coal, 63 struct netlink_ext_ack *extack) 64 { 65 struct bnxt *bp = netdev_priv(dev); 66 struct bnxt_coal *hw_coal; 67 u16 mult; 68 69 memset(coal, 0, sizeof(*coal)); 70 71 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 72 73 hw_coal = &bp->rx_coal; 74 mult = hw_coal->bufs_per_record; 75 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 76 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 77 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 78 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 79 if (hw_coal->flags & 80 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 81 kernel_coal->use_cqe_mode_rx = true; 82 83 hw_coal = &bp->tx_coal; 84 mult = hw_coal->bufs_per_record; 85 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 86 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 87 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 88 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 89 if (hw_coal->flags & 90 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 91 kernel_coal->use_cqe_mode_tx = true; 92 93 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 94 95 return 0; 96 } 97 98 static int bnxt_set_coalesce(struct net_device *dev, 99 struct ethtool_coalesce *coal, 100 struct kernel_ethtool_coalesce *kernel_coal, 101 struct netlink_ext_ack *extack) 102 { 103 struct bnxt *bp = netdev_priv(dev); 104 bool update_stats = false; 105 struct bnxt_coal *hw_coal; 106 int rc = 0; 107 u16 mult; 108 109 if (coal->use_adaptive_rx_coalesce) { 110 bp->flags |= BNXT_FLAG_DIM; 111 } else { 112 if (bp->flags & BNXT_FLAG_DIM) { 113 bp->flags &= ~(BNXT_FLAG_DIM); 114 goto reset_coalesce; 115 } 116 } 117 118 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) && 119 !(bp->coal_cap.cmpl_params & 120 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)) 121 return -EOPNOTSUPP; 122 123 hw_coal = &bp->rx_coal; 124 mult = hw_coal->bufs_per_record; 125 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 126 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 127 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 128 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 129 hw_coal->flags &= 130 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 131 if (kernel_coal->use_cqe_mode_rx) 132 hw_coal->flags |= 133 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 134 135 hw_coal = &bp->tx_coal; 136 mult = hw_coal->bufs_per_record; 137 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 138 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 139 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 140 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 141 hw_coal->flags &= 142 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 143 if (kernel_coal->use_cqe_mode_tx) 144 hw_coal->flags |= 145 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 146 147 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 148 u32 stats_ticks = coal->stats_block_coalesce_usecs; 149 150 /* Allow 0, which means disable. */ 151 if (stats_ticks) 152 stats_ticks = clamp_t(u32, stats_ticks, 153 BNXT_MIN_STATS_COAL_TICKS, 154 BNXT_MAX_STATS_COAL_TICKS); 155 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 156 bp->stats_coal_ticks = stats_ticks; 157 if (bp->stats_coal_ticks) 158 bp->current_interval = 159 bp->stats_coal_ticks * HZ / 1000000; 160 else 161 bp->current_interval = BNXT_TIMER_INTERVAL; 162 update_stats = true; 163 } 164 165 reset_coalesce: 166 if (test_bit(BNXT_STATE_OPEN, &bp->state)) { 167 if (update_stats) { 168 bnxt_close_nic(bp, true, false); 169 rc = bnxt_open_nic(bp, true, false); 170 } else { 171 rc = bnxt_hwrm_set_coal(bp); 172 } 173 } 174 175 return rc; 176 } 177 178 static const char * const bnxt_ring_rx_stats_str[] = { 179 "rx_ucast_packets", 180 "rx_mcast_packets", 181 "rx_bcast_packets", 182 "rx_discards", 183 "rx_errors", 184 "rx_ucast_bytes", 185 "rx_mcast_bytes", 186 "rx_bcast_bytes", 187 }; 188 189 static const char * const bnxt_ring_tx_stats_str[] = { 190 "tx_ucast_packets", 191 "tx_mcast_packets", 192 "tx_bcast_packets", 193 "tx_errors", 194 "tx_discards", 195 "tx_ucast_bytes", 196 "tx_mcast_bytes", 197 "tx_bcast_bytes", 198 }; 199 200 static const char * const bnxt_ring_tpa_stats_str[] = { 201 "tpa_packets", 202 "tpa_bytes", 203 "tpa_events", 204 "tpa_aborts", 205 }; 206 207 static const char * const bnxt_ring_tpa2_stats_str[] = { 208 "rx_tpa_eligible_pkt", 209 "rx_tpa_eligible_bytes", 210 "rx_tpa_pkt", 211 "rx_tpa_bytes", 212 "rx_tpa_errors", 213 "rx_tpa_events", 214 }; 215 216 static const char * const bnxt_rx_sw_stats_str[] = { 217 "rx_l4_csum_errors", 218 "rx_resets", 219 "rx_buf_errors", 220 }; 221 222 static const char * const bnxt_cmn_sw_stats_str[] = { 223 "missed_irqs", 224 }; 225 226 #define BNXT_RX_STATS_ENTRY(counter) \ 227 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 228 229 #define BNXT_TX_STATS_ENTRY(counter) \ 230 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 231 232 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 233 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 234 235 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 236 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 237 238 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 239 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 240 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 241 242 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 243 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 244 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 245 246 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 247 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 248 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 249 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 250 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 251 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 252 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 253 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 254 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 255 256 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 257 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 258 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 259 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 260 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 261 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 262 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 263 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 264 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 265 266 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 267 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 268 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 269 270 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 271 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 272 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 273 274 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 275 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 276 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 277 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 278 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 279 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 280 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 281 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 282 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 283 284 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 285 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 286 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 287 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 288 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 289 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 290 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 291 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 292 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 293 294 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 295 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 296 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 297 298 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 299 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 300 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 301 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 302 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 303 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 304 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 305 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 306 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 307 308 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 309 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 310 __stringify(counter##_pri##n) } 311 312 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 313 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 314 __stringify(counter##_pri##n) } 315 316 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 317 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 318 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 319 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 320 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 321 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 322 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 323 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 324 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 325 326 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 327 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 328 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 329 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 330 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 331 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 332 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 333 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 334 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 335 336 enum { 337 RX_TOTAL_DISCARDS, 338 TX_TOTAL_DISCARDS, 339 RX_NETPOLL_DISCARDS, 340 }; 341 342 static const char *const bnxt_ring_err_stats_arr[] = { 343 "rx_total_l4_csum_errors", 344 "rx_total_resets", 345 "rx_total_buf_errors", 346 "rx_total_oom_discards", 347 "rx_total_netpoll_discards", 348 "rx_total_ring_discards", 349 "tx_total_resets", 350 "tx_total_ring_discards", 351 "total_missed_irqs", 352 }; 353 354 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str) 355 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str) 356 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str) 357 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str) 358 359 static const struct { 360 long offset; 361 char string[ETH_GSTRING_LEN]; 362 } bnxt_port_stats_arr[] = { 363 BNXT_RX_STATS_ENTRY(rx_64b_frames), 364 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 365 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 366 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 367 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 368 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 369 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 370 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 371 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 372 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 373 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 374 BNXT_RX_STATS_ENTRY(rx_total_frames), 375 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 376 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 377 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 378 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 379 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 380 BNXT_RX_STATS_ENTRY(rx_pause_frames), 381 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 382 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 383 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 384 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 385 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 386 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 387 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 388 BNXT_RX_STATS_ENTRY(rx_good_frames), 389 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 390 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 391 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 392 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 393 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 394 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 395 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 396 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 397 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 398 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 399 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 400 BNXT_RX_STATS_ENTRY(rx_bytes), 401 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 402 BNXT_RX_STATS_ENTRY(rx_runt_frames), 403 BNXT_RX_STATS_ENTRY(rx_stat_discard), 404 BNXT_RX_STATS_ENTRY(rx_stat_err), 405 406 BNXT_TX_STATS_ENTRY(tx_64b_frames), 407 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 408 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 409 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 410 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 411 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 412 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 413 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 414 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 415 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 416 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 417 BNXT_TX_STATS_ENTRY(tx_good_frames), 418 BNXT_TX_STATS_ENTRY(tx_total_frames), 419 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 420 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 421 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 422 BNXT_TX_STATS_ENTRY(tx_pause_frames), 423 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 424 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 425 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 426 BNXT_TX_STATS_ENTRY(tx_err), 427 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 428 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 429 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 430 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 431 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 432 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 433 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 434 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 435 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 436 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 437 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 438 BNXT_TX_STATS_ENTRY(tx_total_collisions), 439 BNXT_TX_STATS_ENTRY(tx_bytes), 440 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 441 BNXT_TX_STATS_ENTRY(tx_stat_discard), 442 BNXT_TX_STATS_ENTRY(tx_stat_error), 443 }; 444 445 static const struct { 446 long offset; 447 char string[ETH_GSTRING_LEN]; 448 } bnxt_port_stats_ext_arr[] = { 449 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 450 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 451 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 452 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 453 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 454 BNXT_RX_STATS_EXT_COS_ENTRIES, 455 BNXT_RX_STATS_EXT_PFC_ENTRIES, 456 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 457 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 458 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 459 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 460 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 461 BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks), 462 BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks), 463 BNXT_RX_STATS_EXT_ENTRY(rx_filter_miss), 464 }; 465 466 static const struct { 467 long offset; 468 char string[ETH_GSTRING_LEN]; 469 } bnxt_tx_port_stats_ext_arr[] = { 470 BNXT_TX_STATS_EXT_COS_ENTRIES, 471 BNXT_TX_STATS_EXT_PFC_ENTRIES, 472 }; 473 474 static const struct { 475 long base_off; 476 char string[ETH_GSTRING_LEN]; 477 } bnxt_rx_bytes_pri_arr[] = { 478 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 479 }; 480 481 static const struct { 482 long base_off; 483 char string[ETH_GSTRING_LEN]; 484 } bnxt_rx_pkts_pri_arr[] = { 485 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 486 }; 487 488 static const struct { 489 long base_off; 490 char string[ETH_GSTRING_LEN]; 491 } bnxt_tx_bytes_pri_arr[] = { 492 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 493 }; 494 495 static const struct { 496 long base_off; 497 char string[ETH_GSTRING_LEN]; 498 } bnxt_tx_pkts_pri_arr[] = { 499 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 500 }; 501 502 #define BNXT_NUM_RING_ERR_STATS ARRAY_SIZE(bnxt_ring_err_stats_arr) 503 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 504 #define BNXT_NUM_STATS_PRI \ 505 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 506 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 507 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 508 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 509 510 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 511 { 512 if (BNXT_SUPPORTS_TPA(bp)) { 513 if (bp->max_tpa_v2) { 514 if (BNXT_CHIP_P5(bp)) 515 return BNXT_NUM_TPA_RING_STATS_P5; 516 return BNXT_NUM_TPA_RING_STATS_P7; 517 } 518 return BNXT_NUM_TPA_RING_STATS; 519 } 520 return 0; 521 } 522 523 static int bnxt_get_num_ring_stats(struct bnxt *bp) 524 { 525 int rx, tx, cmn; 526 527 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS + 528 bnxt_get_num_tpa_ring_stats(bp); 529 tx = NUM_RING_TX_HW_STATS; 530 cmn = NUM_RING_CMN_SW_STATS; 531 return rx * bp->rx_nr_rings + 532 tx * (bp->tx_nr_rings_xdp + bp->tx_nr_rings_per_tc) + 533 cmn * bp->cp_nr_rings; 534 } 535 536 static int bnxt_get_num_stats(struct bnxt *bp) 537 { 538 int num_stats = bnxt_get_num_ring_stats(bp); 539 int len; 540 541 num_stats += BNXT_NUM_RING_ERR_STATS; 542 543 if (bp->flags & BNXT_FLAG_PORT_STATS) 544 num_stats += BNXT_NUM_PORT_STATS; 545 546 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 547 len = min_t(int, bp->fw_rx_stats_ext_size, 548 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 549 num_stats += len; 550 len = min_t(int, bp->fw_tx_stats_ext_size, 551 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 552 num_stats += len; 553 if (bp->pri2cos_valid) 554 num_stats += BNXT_NUM_STATS_PRI; 555 } 556 557 return num_stats; 558 } 559 560 static int bnxt_get_sset_count(struct net_device *dev, int sset) 561 { 562 struct bnxt *bp = netdev_priv(dev); 563 564 switch (sset) { 565 case ETH_SS_STATS: 566 return bnxt_get_num_stats(bp); 567 case ETH_SS_TEST: 568 if (!bp->num_tests) 569 return -EOPNOTSUPP; 570 return bp->num_tests; 571 default: 572 return -EOPNOTSUPP; 573 } 574 } 575 576 static bool is_rx_ring(struct bnxt *bp, int ring_num) 577 { 578 return ring_num < bp->rx_nr_rings; 579 } 580 581 static bool is_tx_ring(struct bnxt *bp, int ring_num) 582 { 583 int tx_base = 0; 584 585 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 586 tx_base = bp->rx_nr_rings; 587 588 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings)) 589 return true; 590 return false; 591 } 592 593 static void bnxt_get_ethtool_stats(struct net_device *dev, 594 struct ethtool_stats *stats, u64 *buf) 595 { 596 struct bnxt_total_ring_err_stats ring_err_stats = {0}; 597 struct bnxt *bp = netdev_priv(dev); 598 u64 *curr, *prev; 599 u32 tpa_stats; 600 u32 i, j = 0; 601 602 if (!bp->bnapi) { 603 j += bnxt_get_num_ring_stats(bp); 604 goto skip_ring_stats; 605 } 606 607 tpa_stats = bnxt_get_num_tpa_ring_stats(bp); 608 for (i = 0; i < bp->cp_nr_rings; i++) { 609 struct bnxt_napi *bnapi = bp->bnapi[i]; 610 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 611 u64 *sw_stats = cpr->stats.sw_stats; 612 u64 *sw; 613 int k; 614 615 if (is_rx_ring(bp, i)) { 616 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++) 617 buf[j] = sw_stats[k]; 618 } 619 if (is_tx_ring(bp, i)) { 620 k = NUM_RING_RX_HW_STATS; 621 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 622 j++, k++) 623 buf[j] = sw_stats[k]; 624 } 625 if (!tpa_stats || !is_rx_ring(bp, i)) 626 goto skip_tpa_ring_stats; 627 628 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 629 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS + 630 tpa_stats; j++, k++) 631 buf[j] = sw_stats[k]; 632 633 skip_tpa_ring_stats: 634 sw = (u64 *)&cpr->sw_stats->rx; 635 if (is_rx_ring(bp, i)) { 636 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++) 637 buf[j] = sw[k]; 638 } 639 640 sw = (u64 *)&cpr->sw_stats->cmn; 641 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++) 642 buf[j] = sw[k]; 643 } 644 645 bnxt_get_ring_err_stats(bp, &ring_err_stats); 646 647 skip_ring_stats: 648 curr = &ring_err_stats.rx_total_l4_csum_errors; 649 prev = &bp->ring_err_stats_prev.rx_total_l4_csum_errors; 650 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++, j++, curr++, prev++) 651 buf[j] = *curr + *prev; 652 653 if (bp->flags & BNXT_FLAG_PORT_STATS) { 654 u64 *port_stats = bp->port_stats.sw_stats; 655 656 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) 657 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset); 658 } 659 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 660 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats; 661 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats; 662 u32 len; 663 664 len = min_t(u32, bp->fw_rx_stats_ext_size, 665 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 666 for (i = 0; i < len; i++, j++) { 667 buf[j] = *(rx_port_stats_ext + 668 bnxt_port_stats_ext_arr[i].offset); 669 } 670 len = min_t(u32, bp->fw_tx_stats_ext_size, 671 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 672 for (i = 0; i < len; i++, j++) { 673 buf[j] = *(tx_port_stats_ext + 674 bnxt_tx_port_stats_ext_arr[i].offset); 675 } 676 if (bp->pri2cos_valid) { 677 for (i = 0; i < 8; i++, j++) { 678 long n = bnxt_rx_bytes_pri_arr[i].base_off + 679 bp->pri2cos_idx[i]; 680 681 buf[j] = *(rx_port_stats_ext + n); 682 } 683 for (i = 0; i < 8; i++, j++) { 684 long n = bnxt_rx_pkts_pri_arr[i].base_off + 685 bp->pri2cos_idx[i]; 686 687 buf[j] = *(rx_port_stats_ext + n); 688 } 689 for (i = 0; i < 8; i++, j++) { 690 long n = bnxt_tx_bytes_pri_arr[i].base_off + 691 bp->pri2cos_idx[i]; 692 693 buf[j] = *(tx_port_stats_ext + n); 694 } 695 for (i = 0; i < 8; i++, j++) { 696 long n = bnxt_tx_pkts_pri_arr[i].base_off + 697 bp->pri2cos_idx[i]; 698 699 buf[j] = *(tx_port_stats_ext + n); 700 } 701 } 702 } 703 } 704 705 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 706 { 707 struct bnxt *bp = netdev_priv(dev); 708 u32 i, j, num_str; 709 const char *str; 710 711 switch (stringset) { 712 case ETH_SS_STATS: 713 for (i = 0; i < bp->cp_nr_rings; i++) { 714 if (is_rx_ring(bp, i)) 715 for (j = 0; j < NUM_RING_RX_HW_STATS; j++) { 716 str = bnxt_ring_rx_stats_str[j]; 717 ethtool_sprintf(&buf, "[%d]: %s", i, 718 str); 719 } 720 if (is_tx_ring(bp, i)) 721 for (j = 0; j < NUM_RING_TX_HW_STATS; j++) { 722 str = bnxt_ring_tx_stats_str[j]; 723 ethtool_sprintf(&buf, "[%d]: %s", i, 724 str); 725 } 726 num_str = bnxt_get_num_tpa_ring_stats(bp); 727 if (!num_str || !is_rx_ring(bp, i)) 728 goto skip_tpa_stats; 729 730 if (bp->max_tpa_v2) 731 for (j = 0; j < num_str; j++) { 732 str = bnxt_ring_tpa2_stats_str[j]; 733 ethtool_sprintf(&buf, "[%d]: %s", i, 734 str); 735 } 736 else 737 for (j = 0; j < num_str; j++) { 738 str = bnxt_ring_tpa_stats_str[j]; 739 ethtool_sprintf(&buf, "[%d]: %s", i, 740 str); 741 } 742 skip_tpa_stats: 743 if (is_rx_ring(bp, i)) 744 for (j = 0; j < NUM_RING_RX_SW_STATS; j++) { 745 str = bnxt_rx_sw_stats_str[j]; 746 ethtool_sprintf(&buf, "[%d]: %s", i, 747 str); 748 } 749 for (j = 0; j < NUM_RING_CMN_SW_STATS; j++) { 750 str = bnxt_cmn_sw_stats_str[j]; 751 ethtool_sprintf(&buf, "[%d]: %s", i, str); 752 } 753 } 754 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++) 755 ethtool_puts(&buf, bnxt_ring_err_stats_arr[i]); 756 757 if (bp->flags & BNXT_FLAG_PORT_STATS) 758 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 759 str = bnxt_port_stats_arr[i].string; 760 ethtool_puts(&buf, str); 761 } 762 763 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 764 u32 len; 765 766 len = min_t(u32, bp->fw_rx_stats_ext_size, 767 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 768 for (i = 0; i < len; i++) { 769 str = bnxt_port_stats_ext_arr[i].string; 770 ethtool_puts(&buf, str); 771 } 772 773 len = min_t(u32, bp->fw_tx_stats_ext_size, 774 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 775 for (i = 0; i < len; i++) { 776 str = bnxt_tx_port_stats_ext_arr[i].string; 777 ethtool_puts(&buf, str); 778 } 779 780 if (bp->pri2cos_valid) { 781 for (i = 0; i < 8; i++) { 782 str = bnxt_rx_bytes_pri_arr[i].string; 783 ethtool_puts(&buf, str); 784 } 785 786 for (i = 0; i < 8; i++) { 787 str = bnxt_rx_pkts_pri_arr[i].string; 788 ethtool_puts(&buf, str); 789 } 790 791 for (i = 0; i < 8; i++) { 792 str = bnxt_tx_bytes_pri_arr[i].string; 793 ethtool_puts(&buf, str); 794 } 795 796 for (i = 0; i < 8; i++) { 797 str = bnxt_tx_pkts_pri_arr[i].string; 798 ethtool_puts(&buf, str); 799 } 800 } 801 } 802 break; 803 case ETH_SS_TEST: 804 if (bp->num_tests) 805 for (i = 0; i < bp->num_tests; i++) 806 ethtool_puts(&buf, bp->test_info->string[i]); 807 break; 808 default: 809 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 810 stringset); 811 break; 812 } 813 } 814 815 static void bnxt_get_ringparam(struct net_device *dev, 816 struct ethtool_ringparam *ering, 817 struct kernel_ethtool_ringparam *kernel_ering, 818 struct netlink_ext_ack *extack) 819 { 820 struct bnxt *bp = netdev_priv(dev); 821 822 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 823 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA; 824 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 825 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_ENABLED; 826 } else { 827 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 828 ering->rx_jumbo_max_pending = 0; 829 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_DISABLED; 830 } 831 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 832 833 ering->rx_pending = bp->rx_ring_size; 834 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 835 ering->tx_pending = bp->tx_ring_size; 836 } 837 838 static int bnxt_set_ringparam(struct net_device *dev, 839 struct ethtool_ringparam *ering, 840 struct kernel_ethtool_ringparam *kernel_ering, 841 struct netlink_ext_ack *extack) 842 { 843 struct bnxt *bp = netdev_priv(dev); 844 845 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 846 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 847 (ering->tx_pending < BNXT_MIN_TX_DESC_CNT)) 848 return -EINVAL; 849 850 if (netif_running(dev)) 851 bnxt_close_nic(bp, false, false); 852 853 bp->rx_ring_size = ering->rx_pending; 854 bp->tx_ring_size = ering->tx_pending; 855 bnxt_set_ring_params(bp); 856 857 if (netif_running(dev)) 858 return bnxt_open_nic(bp, false, false); 859 860 return 0; 861 } 862 863 static void bnxt_get_channels(struct net_device *dev, 864 struct ethtool_channels *channel) 865 { 866 struct bnxt *bp = netdev_priv(dev); 867 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 868 int max_rx_rings, max_tx_rings, tcs; 869 int max_tx_sch_inputs, tx_grps; 870 871 /* Get the most up-to-date max_tx_sch_inputs. */ 872 if (netif_running(dev) && BNXT_NEW_RM(bp)) 873 bnxt_hwrm_func_resc_qcaps(bp, false); 874 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 875 876 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 877 if (max_tx_sch_inputs) 878 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 879 880 tcs = bp->num_tc; 881 tx_grps = max(tcs, 1); 882 if (bp->tx_nr_rings_xdp) 883 tx_grps++; 884 max_tx_rings /= tx_grps; 885 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 886 887 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 888 max_rx_rings = 0; 889 max_tx_rings = 0; 890 } 891 if (max_tx_sch_inputs) 892 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 893 894 if (tcs > 1) 895 max_tx_rings /= tcs; 896 897 channel->max_rx = max_rx_rings; 898 channel->max_tx = max_tx_rings; 899 channel->max_other = 0; 900 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 901 channel->combined_count = bp->rx_nr_rings; 902 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 903 channel->combined_count--; 904 } else { 905 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 906 channel->rx_count = bp->rx_nr_rings; 907 channel->tx_count = bp->tx_nr_rings_per_tc; 908 } 909 } 910 } 911 912 static int bnxt_set_channels(struct net_device *dev, 913 struct ethtool_channels *channel) 914 { 915 struct bnxt *bp = netdev_priv(dev); 916 int req_tx_rings, req_rx_rings, tcs; 917 bool sh = false; 918 int tx_xdp = 0; 919 int rc = 0; 920 int tx_cp; 921 922 if (channel->other_count) 923 return -EINVAL; 924 925 if (!channel->combined_count && 926 (!channel->rx_count || !channel->tx_count)) 927 return -EINVAL; 928 929 if (channel->combined_count && 930 (channel->rx_count || channel->tx_count)) 931 return -EINVAL; 932 933 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 934 channel->tx_count)) 935 return -EINVAL; 936 937 if (channel->combined_count) 938 sh = true; 939 940 tcs = bp->num_tc; 941 942 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 943 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 944 if (bp->tx_nr_rings_xdp) { 945 if (!sh) { 946 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 947 return -EINVAL; 948 } 949 tx_xdp = req_rx_rings; 950 } 951 952 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) != 953 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) && 954 netif_is_rxfh_configured(dev)) { 955 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n"); 956 return -EINVAL; 957 } 958 959 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 960 if (rc) { 961 netdev_warn(dev, "Unable to allocate the requested rings\n"); 962 return rc; 963 } 964 965 if (netif_running(dev)) { 966 if (BNXT_PF(bp)) { 967 /* TODO CHIMP_FW: Send message to all VF's 968 * before PF unload 969 */ 970 } 971 bnxt_close_nic(bp, true, false); 972 } 973 974 if (sh) { 975 bp->flags |= BNXT_FLAG_SHARED_RINGS; 976 bp->rx_nr_rings = channel->combined_count; 977 bp->tx_nr_rings_per_tc = channel->combined_count; 978 } else { 979 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 980 bp->rx_nr_rings = channel->rx_count; 981 bp->tx_nr_rings_per_tc = channel->tx_count; 982 } 983 bp->tx_nr_rings_xdp = tx_xdp; 984 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 985 if (tcs > 1) 986 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 987 988 tx_cp = bnxt_num_tx_to_cp(bp, bp->tx_nr_rings); 989 bp->cp_nr_rings = sh ? max_t(int, tx_cp, bp->rx_nr_rings) : 990 tx_cp + bp->rx_nr_rings; 991 992 /* After changing number of rx channels, update NTUPLE feature. */ 993 netdev_update_features(dev); 994 if (netif_running(dev)) { 995 rc = bnxt_open_nic(bp, true, false); 996 if ((!rc) && BNXT_PF(bp)) { 997 /* TODO CHIMP_FW: Send message to all VF's 998 * to renable 999 */ 1000 } 1001 } else { 1002 rc = bnxt_reserve_rings(bp, true); 1003 } 1004 1005 return rc; 1006 } 1007 1008 static u32 bnxt_get_all_fltr_ids_rcu(struct bnxt *bp, struct hlist_head tbl[], 1009 int tbl_size, u32 *ids, u32 start, 1010 u32 id_cnt) 1011 { 1012 int i, j = start; 1013 1014 if (j >= id_cnt) 1015 return j; 1016 for (i = 0; i < tbl_size; i++) { 1017 struct hlist_head *head; 1018 struct bnxt_filter_base *fltr; 1019 1020 head = &tbl[i]; 1021 hlist_for_each_entry_rcu(fltr, head, hash) { 1022 if (!fltr->flags || 1023 test_bit(BNXT_FLTR_FW_DELETED, &fltr->state)) 1024 continue; 1025 ids[j++] = fltr->sw_id; 1026 if (j == id_cnt) 1027 return j; 1028 } 1029 } 1030 return j; 1031 } 1032 1033 static struct bnxt_filter_base *bnxt_get_one_fltr_rcu(struct bnxt *bp, 1034 struct hlist_head tbl[], 1035 int tbl_size, u32 id) 1036 { 1037 int i; 1038 1039 for (i = 0; i < tbl_size; i++) { 1040 struct hlist_head *head; 1041 struct bnxt_filter_base *fltr; 1042 1043 head = &tbl[i]; 1044 hlist_for_each_entry_rcu(fltr, head, hash) { 1045 if (fltr->flags && fltr->sw_id == id) 1046 return fltr; 1047 } 1048 } 1049 return NULL; 1050 } 1051 1052 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 1053 u32 *rule_locs) 1054 { 1055 u32 count; 1056 1057 cmd->data = bp->ntp_fltr_count; 1058 rcu_read_lock(); 1059 count = bnxt_get_all_fltr_ids_rcu(bp, bp->l2_fltr_hash_tbl, 1060 BNXT_L2_FLTR_HASH_SIZE, rule_locs, 0, 1061 cmd->rule_cnt); 1062 cmd->rule_cnt = bnxt_get_all_fltr_ids_rcu(bp, bp->ntp_fltr_hash_tbl, 1063 BNXT_NTP_FLTR_HASH_SIZE, 1064 rule_locs, count, 1065 cmd->rule_cnt); 1066 rcu_read_unlock(); 1067 1068 return 0; 1069 } 1070 1071 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1072 { 1073 struct ethtool_rx_flow_spec *fs = 1074 (struct ethtool_rx_flow_spec *)&cmd->fs; 1075 struct bnxt_filter_base *fltr_base; 1076 struct bnxt_ntuple_filter *fltr; 1077 struct bnxt_flow_masks *fmasks; 1078 struct flow_keys *fkeys; 1079 int rc = -EINVAL; 1080 1081 if (fs->location >= bp->max_fltr) 1082 return rc; 1083 1084 rcu_read_lock(); 1085 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl, 1086 BNXT_L2_FLTR_HASH_SIZE, 1087 fs->location); 1088 if (fltr_base) { 1089 struct ethhdr *h_ether = &fs->h_u.ether_spec; 1090 struct ethhdr *m_ether = &fs->m_u.ether_spec; 1091 struct bnxt_l2_filter *l2_fltr; 1092 struct bnxt_l2_key *l2_key; 1093 1094 l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base); 1095 l2_key = &l2_fltr->l2_key; 1096 fs->flow_type = ETHER_FLOW; 1097 ether_addr_copy(h_ether->h_dest, l2_key->dst_mac_addr); 1098 eth_broadcast_addr(m_ether->h_dest); 1099 if (l2_key->vlan) { 1100 struct ethtool_flow_ext *m_ext = &fs->m_ext; 1101 struct ethtool_flow_ext *h_ext = &fs->h_ext; 1102 1103 fs->flow_type |= FLOW_EXT; 1104 m_ext->vlan_tci = htons(0xfff); 1105 h_ext->vlan_tci = htons(l2_key->vlan); 1106 } 1107 if (fltr_base->flags & BNXT_ACT_RING_DST) 1108 fs->ring_cookie = fltr_base->rxq; 1109 if (fltr_base->flags & BNXT_ACT_FUNC_DST) 1110 fs->ring_cookie = (u64)(fltr_base->vf_idx + 1) << 1111 ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 1112 rcu_read_unlock(); 1113 return 0; 1114 } 1115 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl, 1116 BNXT_NTP_FLTR_HASH_SIZE, 1117 fs->location); 1118 if (!fltr_base) { 1119 rcu_read_unlock(); 1120 return rc; 1121 } 1122 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base); 1123 1124 fkeys = &fltr->fkeys; 1125 fmasks = &fltr->fmasks; 1126 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 1127 if (fkeys->basic.ip_proto == IPPROTO_ICMP || 1128 fkeys->basic.ip_proto == IPPROTO_RAW) { 1129 fs->flow_type = IP_USER_FLOW; 1130 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 1131 if (fkeys->basic.ip_proto == IPPROTO_ICMP) 1132 fs->h_u.usr_ip4_spec.proto = IPPROTO_ICMP; 1133 else 1134 fs->h_u.usr_ip4_spec.proto = IPPROTO_RAW; 1135 fs->m_u.usr_ip4_spec.proto = BNXT_IP_PROTO_FULL_MASK; 1136 } else if (fkeys->basic.ip_proto == IPPROTO_TCP) { 1137 fs->flow_type = TCP_V4_FLOW; 1138 } else if (fkeys->basic.ip_proto == IPPROTO_UDP) { 1139 fs->flow_type = UDP_V4_FLOW; 1140 } else { 1141 goto fltr_err; 1142 } 1143 1144 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 1145 fs->m_u.tcp_ip4_spec.ip4src = fmasks->addrs.v4addrs.src; 1146 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 1147 fs->m_u.tcp_ip4_spec.ip4dst = fmasks->addrs.v4addrs.dst; 1148 if (fs->flow_type == TCP_V4_FLOW || 1149 fs->flow_type == UDP_V4_FLOW) { 1150 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 1151 fs->m_u.tcp_ip4_spec.psrc = fmasks->ports.src; 1152 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 1153 fs->m_u.tcp_ip4_spec.pdst = fmasks->ports.dst; 1154 } 1155 } else { 1156 if (fkeys->basic.ip_proto == IPPROTO_ICMPV6 || 1157 fkeys->basic.ip_proto == IPPROTO_RAW) { 1158 fs->flow_type = IPV6_USER_FLOW; 1159 if (fkeys->basic.ip_proto == IPPROTO_ICMPV6) 1160 fs->h_u.usr_ip6_spec.l4_proto = IPPROTO_ICMPV6; 1161 else 1162 fs->h_u.usr_ip6_spec.l4_proto = IPPROTO_RAW; 1163 fs->m_u.usr_ip6_spec.l4_proto = BNXT_IP_PROTO_FULL_MASK; 1164 } else if (fkeys->basic.ip_proto == IPPROTO_TCP) { 1165 fs->flow_type = TCP_V6_FLOW; 1166 } else if (fkeys->basic.ip_proto == IPPROTO_UDP) { 1167 fs->flow_type = UDP_V6_FLOW; 1168 } else { 1169 goto fltr_err; 1170 } 1171 1172 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 1173 fkeys->addrs.v6addrs.src; 1174 *(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6src[0] = 1175 fmasks->addrs.v6addrs.src; 1176 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 1177 fkeys->addrs.v6addrs.dst; 1178 *(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6dst[0] = 1179 fmasks->addrs.v6addrs.dst; 1180 if (fs->flow_type == TCP_V6_FLOW || 1181 fs->flow_type == UDP_V6_FLOW) { 1182 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 1183 fs->m_u.tcp_ip6_spec.psrc = fmasks->ports.src; 1184 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 1185 fs->m_u.tcp_ip6_spec.pdst = fmasks->ports.dst; 1186 } 1187 } 1188 1189 if (fltr->base.flags & BNXT_ACT_DROP) 1190 fs->ring_cookie = RX_CLS_FLOW_DISC; 1191 else 1192 fs->ring_cookie = fltr->base.rxq; 1193 rc = 0; 1194 1195 fltr_err: 1196 rcu_read_unlock(); 1197 1198 return rc; 1199 } 1200 1201 static struct bnxt_rss_ctx *bnxt_get_rss_ctx_from_index(struct bnxt *bp, 1202 u32 index) 1203 { 1204 struct ethtool_rxfh_context *ctx; 1205 1206 ctx = xa_load(&bp->dev->ethtool->rss_ctx, index); 1207 if (!ctx) 1208 return NULL; 1209 return ethtool_rxfh_context_priv(ctx); 1210 } 1211 1212 static int bnxt_alloc_vnic_rss_table(struct bnxt *bp, 1213 struct bnxt_vnic_info *vnic) 1214 { 1215 int size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5); 1216 1217 vnic->rss_table_size = size + HW_HASH_KEY_SIZE; 1218 vnic->rss_table = dma_alloc_coherent(&bp->pdev->dev, 1219 vnic->rss_table_size, 1220 &vnic->rss_table_dma_addr, 1221 GFP_KERNEL); 1222 if (!vnic->rss_table) 1223 return -ENOMEM; 1224 1225 vnic->rss_hash_key = ((void *)vnic->rss_table) + size; 1226 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; 1227 return 0; 1228 } 1229 1230 static int bnxt_add_l2_cls_rule(struct bnxt *bp, 1231 struct ethtool_rx_flow_spec *fs) 1232 { 1233 u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1234 u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1235 struct ethhdr *h_ether = &fs->h_u.ether_spec; 1236 struct ethhdr *m_ether = &fs->m_u.ether_spec; 1237 struct bnxt_l2_filter *fltr; 1238 struct bnxt_l2_key key; 1239 u16 vnic_id; 1240 u8 flags; 1241 int rc; 1242 1243 if (BNXT_CHIP_P5_PLUS(bp)) 1244 return -EOPNOTSUPP; 1245 1246 if (!is_broadcast_ether_addr(m_ether->h_dest)) 1247 return -EINVAL; 1248 ether_addr_copy(key.dst_mac_addr, h_ether->h_dest); 1249 key.vlan = 0; 1250 if (fs->flow_type & FLOW_EXT) { 1251 struct ethtool_flow_ext *m_ext = &fs->m_ext; 1252 struct ethtool_flow_ext *h_ext = &fs->h_ext; 1253 1254 if (m_ext->vlan_tci != htons(0xfff) || !h_ext->vlan_tci) 1255 return -EINVAL; 1256 key.vlan = ntohs(h_ext->vlan_tci); 1257 } 1258 1259 if (vf) { 1260 flags = BNXT_ACT_FUNC_DST; 1261 vnic_id = 0xffff; 1262 vf--; 1263 } else { 1264 flags = BNXT_ACT_RING_DST; 1265 vnic_id = bp->vnic_info[ring + 1].fw_vnic_id; 1266 } 1267 fltr = bnxt_alloc_new_l2_filter(bp, &key, flags); 1268 if (IS_ERR(fltr)) 1269 return PTR_ERR(fltr); 1270 1271 fltr->base.fw_vnic_id = vnic_id; 1272 fltr->base.rxq = ring; 1273 fltr->base.vf_idx = vf; 1274 rc = bnxt_hwrm_l2_filter_alloc(bp, fltr); 1275 if (rc) 1276 bnxt_del_l2_filter(bp, fltr); 1277 else 1278 fs->location = fltr->base.sw_id; 1279 return rc; 1280 } 1281 1282 static bool bnxt_verify_ntuple_ip4_flow(struct ethtool_usrip4_spec *ip_spec, 1283 struct ethtool_usrip4_spec *ip_mask) 1284 { 1285 if (ip_mask->l4_4_bytes || ip_mask->tos || 1286 ip_spec->ip_ver != ETH_RX_NFC_IP4 || 1287 ip_mask->proto != BNXT_IP_PROTO_FULL_MASK || 1288 (ip_spec->proto != IPPROTO_RAW && ip_spec->proto != IPPROTO_ICMP)) 1289 return false; 1290 return true; 1291 } 1292 1293 static bool bnxt_verify_ntuple_ip6_flow(struct ethtool_usrip6_spec *ip_spec, 1294 struct ethtool_usrip6_spec *ip_mask) 1295 { 1296 if (ip_mask->l4_4_bytes || ip_mask->tclass || 1297 ip_mask->l4_proto != BNXT_IP_PROTO_FULL_MASK || 1298 (ip_spec->l4_proto != IPPROTO_RAW && 1299 ip_spec->l4_proto != IPPROTO_ICMPV6)) 1300 return false; 1301 return true; 1302 } 1303 1304 static int bnxt_add_ntuple_cls_rule(struct bnxt *bp, 1305 struct ethtool_rxnfc *cmd) 1306 { 1307 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1308 struct bnxt_ntuple_filter *new_fltr, *fltr; 1309 u32 flow_type = fs->flow_type & 0xff; 1310 struct bnxt_l2_filter *l2_fltr; 1311 struct bnxt_flow_masks *fmasks; 1312 struct flow_keys *fkeys; 1313 u32 idx, ring; 1314 int rc; 1315 u8 vf; 1316 1317 if (!bp->vnic_info) 1318 return -EAGAIN; 1319 1320 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1321 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1322 if ((fs->flow_type & (FLOW_MAC_EXT | FLOW_EXT)) || vf) 1323 return -EOPNOTSUPP; 1324 1325 if (flow_type == IP_USER_FLOW) { 1326 if (!bnxt_verify_ntuple_ip4_flow(&fs->h_u.usr_ip4_spec, 1327 &fs->m_u.usr_ip4_spec)) 1328 return -EOPNOTSUPP; 1329 } 1330 1331 if (flow_type == IPV6_USER_FLOW) { 1332 if (!bnxt_verify_ntuple_ip6_flow(&fs->h_u.usr_ip6_spec, 1333 &fs->m_u.usr_ip6_spec)) 1334 return -EOPNOTSUPP; 1335 } 1336 1337 new_fltr = kzalloc(sizeof(*new_fltr), GFP_KERNEL); 1338 if (!new_fltr) 1339 return -ENOMEM; 1340 1341 l2_fltr = bp->vnic_info[BNXT_VNIC_DEFAULT].l2_filters[0]; 1342 atomic_inc(&l2_fltr->refcnt); 1343 new_fltr->l2_fltr = l2_fltr; 1344 fmasks = &new_fltr->fmasks; 1345 fkeys = &new_fltr->fkeys; 1346 1347 rc = -EOPNOTSUPP; 1348 switch (flow_type) { 1349 case IP_USER_FLOW: { 1350 struct ethtool_usrip4_spec *ip_spec = &fs->h_u.usr_ip4_spec; 1351 struct ethtool_usrip4_spec *ip_mask = &fs->m_u.usr_ip4_spec; 1352 1353 fkeys->basic.ip_proto = ip_spec->proto; 1354 fkeys->basic.n_proto = htons(ETH_P_IP); 1355 fkeys->addrs.v4addrs.src = ip_spec->ip4src; 1356 fmasks->addrs.v4addrs.src = ip_mask->ip4src; 1357 fkeys->addrs.v4addrs.dst = ip_spec->ip4dst; 1358 fmasks->addrs.v4addrs.dst = ip_mask->ip4dst; 1359 break; 1360 } 1361 case TCP_V4_FLOW: 1362 case UDP_V4_FLOW: { 1363 struct ethtool_tcpip4_spec *ip_spec = &fs->h_u.tcp_ip4_spec; 1364 struct ethtool_tcpip4_spec *ip_mask = &fs->m_u.tcp_ip4_spec; 1365 1366 fkeys->basic.ip_proto = IPPROTO_TCP; 1367 if (flow_type == UDP_V4_FLOW) 1368 fkeys->basic.ip_proto = IPPROTO_UDP; 1369 fkeys->basic.n_proto = htons(ETH_P_IP); 1370 fkeys->addrs.v4addrs.src = ip_spec->ip4src; 1371 fmasks->addrs.v4addrs.src = ip_mask->ip4src; 1372 fkeys->addrs.v4addrs.dst = ip_spec->ip4dst; 1373 fmasks->addrs.v4addrs.dst = ip_mask->ip4dst; 1374 fkeys->ports.src = ip_spec->psrc; 1375 fmasks->ports.src = ip_mask->psrc; 1376 fkeys->ports.dst = ip_spec->pdst; 1377 fmasks->ports.dst = ip_mask->pdst; 1378 break; 1379 } 1380 case IPV6_USER_FLOW: { 1381 struct ethtool_usrip6_spec *ip_spec = &fs->h_u.usr_ip6_spec; 1382 struct ethtool_usrip6_spec *ip_mask = &fs->m_u.usr_ip6_spec; 1383 1384 fkeys->basic.ip_proto = ip_spec->l4_proto; 1385 fkeys->basic.n_proto = htons(ETH_P_IPV6); 1386 fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src; 1387 fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src; 1388 fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst; 1389 fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst; 1390 break; 1391 } 1392 case TCP_V6_FLOW: 1393 case UDP_V6_FLOW: { 1394 struct ethtool_tcpip6_spec *ip_spec = &fs->h_u.tcp_ip6_spec; 1395 struct ethtool_tcpip6_spec *ip_mask = &fs->m_u.tcp_ip6_spec; 1396 1397 fkeys->basic.ip_proto = IPPROTO_TCP; 1398 if (flow_type == UDP_V6_FLOW) 1399 fkeys->basic.ip_proto = IPPROTO_UDP; 1400 fkeys->basic.n_proto = htons(ETH_P_IPV6); 1401 1402 fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src; 1403 fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src; 1404 fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst; 1405 fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst; 1406 fkeys->ports.src = ip_spec->psrc; 1407 fmasks->ports.src = ip_mask->psrc; 1408 fkeys->ports.dst = ip_spec->pdst; 1409 fmasks->ports.dst = ip_mask->pdst; 1410 break; 1411 } 1412 default: 1413 rc = -EOPNOTSUPP; 1414 goto ntuple_err; 1415 } 1416 if (!memcmp(&BNXT_FLOW_MASK_NONE, fmasks, sizeof(*fmasks))) 1417 goto ntuple_err; 1418 1419 idx = bnxt_get_ntp_filter_idx(bp, fkeys, NULL); 1420 rcu_read_lock(); 1421 fltr = bnxt_lookup_ntp_filter_from_idx(bp, new_fltr, idx); 1422 if (fltr) { 1423 rcu_read_unlock(); 1424 rc = -EEXIST; 1425 goto ntuple_err; 1426 } 1427 rcu_read_unlock(); 1428 1429 new_fltr->base.flags = BNXT_ACT_NO_AGING; 1430 if (fs->flow_type & FLOW_RSS) { 1431 struct bnxt_rss_ctx *rss_ctx; 1432 1433 new_fltr->base.fw_vnic_id = 0; 1434 new_fltr->base.flags |= BNXT_ACT_RSS_CTX; 1435 rss_ctx = bnxt_get_rss_ctx_from_index(bp, cmd->rss_context); 1436 if (rss_ctx) { 1437 new_fltr->base.fw_vnic_id = rss_ctx->index; 1438 } else { 1439 rc = -EINVAL; 1440 goto ntuple_err; 1441 } 1442 } 1443 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1444 new_fltr->base.flags |= BNXT_ACT_DROP; 1445 else 1446 new_fltr->base.rxq = ring; 1447 __set_bit(BNXT_FLTR_VALID, &new_fltr->base.state); 1448 rc = bnxt_insert_ntp_filter(bp, new_fltr, idx); 1449 if (!rc) { 1450 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, new_fltr); 1451 if (rc) { 1452 bnxt_del_ntp_filter(bp, new_fltr); 1453 return rc; 1454 } 1455 fs->location = new_fltr->base.sw_id; 1456 return 0; 1457 } 1458 1459 ntuple_err: 1460 atomic_dec(&l2_fltr->refcnt); 1461 kfree(new_fltr); 1462 return rc; 1463 } 1464 1465 static int bnxt_srxclsrlins(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1466 { 1467 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1468 u32 ring, flow_type; 1469 int rc; 1470 u8 vf; 1471 1472 if (!netif_running(bp->dev)) 1473 return -EAGAIN; 1474 if (!(bp->flags & BNXT_FLAG_RFS)) 1475 return -EPERM; 1476 if (fs->location != RX_CLS_LOC_ANY) 1477 return -EINVAL; 1478 1479 flow_type = fs->flow_type; 1480 if ((flow_type == IP_USER_FLOW || 1481 flow_type == IPV6_USER_FLOW) && 1482 !(bp->fw_cap & BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO)) 1483 return -EOPNOTSUPP; 1484 if (flow_type & FLOW_MAC_EXT) 1485 return -EINVAL; 1486 flow_type &= ~FLOW_EXT; 1487 1488 if (fs->ring_cookie == RX_CLS_FLOW_DISC && flow_type != ETHER_FLOW) 1489 return bnxt_add_ntuple_cls_rule(bp, cmd); 1490 1491 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1492 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1493 if (BNXT_VF(bp) && vf) 1494 return -EINVAL; 1495 if (BNXT_PF(bp) && vf > bp->pf.active_vfs) 1496 return -EINVAL; 1497 if (!vf && ring >= bp->rx_nr_rings) 1498 return -EINVAL; 1499 1500 if (flow_type == ETHER_FLOW) 1501 rc = bnxt_add_l2_cls_rule(bp, fs); 1502 else 1503 rc = bnxt_add_ntuple_cls_rule(bp, cmd); 1504 return rc; 1505 } 1506 1507 static int bnxt_srxclsrldel(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1508 { 1509 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1510 struct bnxt_filter_base *fltr_base; 1511 struct bnxt_ntuple_filter *fltr; 1512 u32 id = fs->location; 1513 1514 rcu_read_lock(); 1515 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl, 1516 BNXT_L2_FLTR_HASH_SIZE, id); 1517 if (fltr_base) { 1518 struct bnxt_l2_filter *l2_fltr; 1519 1520 l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base); 1521 rcu_read_unlock(); 1522 bnxt_hwrm_l2_filter_free(bp, l2_fltr); 1523 bnxt_del_l2_filter(bp, l2_fltr); 1524 return 0; 1525 } 1526 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl, 1527 BNXT_NTP_FLTR_HASH_SIZE, id); 1528 if (!fltr_base) { 1529 rcu_read_unlock(); 1530 return -ENOENT; 1531 } 1532 1533 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base); 1534 if (!(fltr->base.flags & BNXT_ACT_NO_AGING)) { 1535 rcu_read_unlock(); 1536 return -EINVAL; 1537 } 1538 rcu_read_unlock(); 1539 bnxt_hwrm_cfa_ntuple_filter_free(bp, fltr); 1540 bnxt_del_ntp_filter(bp, fltr); 1541 return 0; 1542 } 1543 1544 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1545 { 1546 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1547 return RXH_IP_SRC | RXH_IP_DST; 1548 return 0; 1549 } 1550 1551 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1552 { 1553 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1554 return RXH_IP_SRC | RXH_IP_DST; 1555 return 0; 1556 } 1557 1558 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1559 { 1560 cmd->data = 0; 1561 switch (cmd->flow_type) { 1562 case TCP_V4_FLOW: 1563 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1564 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1565 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1566 cmd->data |= get_ethtool_ipv4_rss(bp); 1567 break; 1568 case UDP_V4_FLOW: 1569 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1570 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1571 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1572 fallthrough; 1573 case AH_ESP_V4_FLOW: 1574 if (bp->rss_hash_cfg & 1575 (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1576 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4)) 1577 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1578 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1579 fallthrough; 1580 case SCTP_V4_FLOW: 1581 case AH_V4_FLOW: 1582 case ESP_V4_FLOW: 1583 case IPV4_FLOW: 1584 cmd->data |= get_ethtool_ipv4_rss(bp); 1585 break; 1586 1587 case TCP_V6_FLOW: 1588 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1589 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1590 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1591 cmd->data |= get_ethtool_ipv6_rss(bp); 1592 break; 1593 case UDP_V6_FLOW: 1594 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1595 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1596 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1597 fallthrough; 1598 case AH_ESP_V6_FLOW: 1599 if (bp->rss_hash_cfg & 1600 (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1601 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6)) 1602 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1603 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1604 fallthrough; 1605 case SCTP_V6_FLOW: 1606 case AH_V6_FLOW: 1607 case ESP_V6_FLOW: 1608 case IPV6_FLOW: 1609 cmd->data |= get_ethtool_ipv6_rss(bp); 1610 break; 1611 } 1612 return 0; 1613 } 1614 1615 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1616 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1617 1618 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1619 { 1620 u32 rss_hash_cfg = bp->rss_hash_cfg; 1621 int tuple, rc = 0; 1622 1623 if (cmd->data == RXH_4TUPLE) 1624 tuple = 4; 1625 else if (cmd->data == RXH_2TUPLE) 1626 tuple = 2; 1627 else if (!cmd->data) 1628 tuple = 0; 1629 else 1630 return -EINVAL; 1631 1632 if (cmd->flow_type == TCP_V4_FLOW) { 1633 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1634 if (tuple == 4) 1635 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1636 } else if (cmd->flow_type == UDP_V4_FLOW) { 1637 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP)) 1638 return -EINVAL; 1639 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1640 if (tuple == 4) 1641 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1642 } else if (cmd->flow_type == TCP_V6_FLOW) { 1643 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1644 if (tuple == 4) 1645 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1646 } else if (cmd->flow_type == UDP_V6_FLOW) { 1647 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP)) 1648 return -EINVAL; 1649 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1650 if (tuple == 4) 1651 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1652 } else if (cmd->flow_type == AH_ESP_V4_FLOW) { 1653 if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V4_RSS_CAP) || 1654 !(bp->rss_cap & BNXT_RSS_CAP_ESP_V4_RSS_CAP))) 1655 return -EINVAL; 1656 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1657 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4); 1658 if (tuple == 4) 1659 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1660 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4; 1661 } else if (cmd->flow_type == AH_ESP_V6_FLOW) { 1662 if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V6_RSS_CAP) || 1663 !(bp->rss_cap & BNXT_RSS_CAP_ESP_V6_RSS_CAP))) 1664 return -EINVAL; 1665 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1666 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6); 1667 if (tuple == 4) 1668 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1669 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6; 1670 } else if (tuple == 4) { 1671 return -EINVAL; 1672 } 1673 1674 switch (cmd->flow_type) { 1675 case TCP_V4_FLOW: 1676 case UDP_V4_FLOW: 1677 case SCTP_V4_FLOW: 1678 case AH_ESP_V4_FLOW: 1679 case AH_V4_FLOW: 1680 case ESP_V4_FLOW: 1681 case IPV4_FLOW: 1682 if (tuple == 2) 1683 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1684 else if (!tuple) 1685 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1686 break; 1687 1688 case TCP_V6_FLOW: 1689 case UDP_V6_FLOW: 1690 case SCTP_V6_FLOW: 1691 case AH_ESP_V6_FLOW: 1692 case AH_V6_FLOW: 1693 case ESP_V6_FLOW: 1694 case IPV6_FLOW: 1695 if (tuple == 2) 1696 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1697 else if (!tuple) 1698 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1699 break; 1700 } 1701 1702 if (bp->rss_hash_cfg == rss_hash_cfg) 1703 return 0; 1704 1705 if (bp->rss_cap & BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA) 1706 bp->rss_hash_delta = bp->rss_hash_cfg ^ rss_hash_cfg; 1707 bp->rss_hash_cfg = rss_hash_cfg; 1708 if (netif_running(bp->dev)) { 1709 bnxt_close_nic(bp, false, false); 1710 rc = bnxt_open_nic(bp, false, false); 1711 } 1712 return rc; 1713 } 1714 1715 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1716 u32 *rule_locs) 1717 { 1718 struct bnxt *bp = netdev_priv(dev); 1719 int rc = 0; 1720 1721 switch (cmd->cmd) { 1722 case ETHTOOL_GRXRINGS: 1723 cmd->data = bp->rx_nr_rings; 1724 break; 1725 1726 case ETHTOOL_GRXCLSRLCNT: 1727 cmd->rule_cnt = bp->ntp_fltr_count; 1728 cmd->data = bp->max_fltr | RX_CLS_LOC_SPECIAL; 1729 break; 1730 1731 case ETHTOOL_GRXCLSRLALL: 1732 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1733 break; 1734 1735 case ETHTOOL_GRXCLSRULE: 1736 rc = bnxt_grxclsrule(bp, cmd); 1737 break; 1738 1739 case ETHTOOL_GRXFH: 1740 rc = bnxt_grxfh(bp, cmd); 1741 break; 1742 1743 default: 1744 rc = -EOPNOTSUPP; 1745 break; 1746 } 1747 1748 return rc; 1749 } 1750 1751 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1752 { 1753 struct bnxt *bp = netdev_priv(dev); 1754 int rc; 1755 1756 switch (cmd->cmd) { 1757 case ETHTOOL_SRXFH: 1758 rc = bnxt_srxfh(bp, cmd); 1759 break; 1760 1761 case ETHTOOL_SRXCLSRLINS: 1762 rc = bnxt_srxclsrlins(bp, cmd); 1763 break; 1764 1765 case ETHTOOL_SRXCLSRLDEL: 1766 rc = bnxt_srxclsrldel(bp, cmd); 1767 break; 1768 1769 default: 1770 rc = -EOPNOTSUPP; 1771 break; 1772 } 1773 return rc; 1774 } 1775 1776 u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1777 { 1778 struct bnxt *bp = netdev_priv(dev); 1779 1780 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) 1781 return bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) * 1782 BNXT_RSS_TABLE_ENTRIES_P5; 1783 return HW_HASH_INDEX_SIZE; 1784 } 1785 1786 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1787 { 1788 return HW_HASH_KEY_SIZE; 1789 } 1790 1791 static int bnxt_get_rxfh(struct net_device *dev, 1792 struct ethtool_rxfh_param *rxfh) 1793 { 1794 struct bnxt_rss_ctx *rss_ctx = NULL; 1795 struct bnxt *bp = netdev_priv(dev); 1796 u32 *indir_tbl = bp->rss_indir_tbl; 1797 struct bnxt_vnic_info *vnic; 1798 u32 i, tbl_size; 1799 1800 rxfh->hfunc = ETH_RSS_HASH_TOP; 1801 1802 if (!bp->vnic_info) 1803 return 0; 1804 1805 vnic = &bp->vnic_info[BNXT_VNIC_DEFAULT]; 1806 if (rxfh->rss_context) { 1807 struct ethtool_rxfh_context *ctx; 1808 1809 ctx = xa_load(&bp->dev->ethtool->rss_ctx, rxfh->rss_context); 1810 if (!ctx) 1811 return -EINVAL; 1812 indir_tbl = ethtool_rxfh_context_indir(ctx); 1813 rss_ctx = ethtool_rxfh_context_priv(ctx); 1814 vnic = &rss_ctx->vnic; 1815 } 1816 1817 if (rxfh->indir && indir_tbl) { 1818 tbl_size = bnxt_get_rxfh_indir_size(dev); 1819 for (i = 0; i < tbl_size; i++) 1820 rxfh->indir[i] = indir_tbl[i]; 1821 } 1822 1823 if (rxfh->key && vnic->rss_hash_key) 1824 memcpy(rxfh->key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1825 1826 return 0; 1827 } 1828 1829 static void bnxt_modify_rss(struct bnxt *bp, struct ethtool_rxfh_context *ctx, 1830 struct bnxt_rss_ctx *rss_ctx, 1831 const struct ethtool_rxfh_param *rxfh) 1832 { 1833 if (rxfh->key) { 1834 if (rss_ctx) { 1835 memcpy(rss_ctx->vnic.rss_hash_key, rxfh->key, 1836 HW_HASH_KEY_SIZE); 1837 } else { 1838 memcpy(bp->rss_hash_key, rxfh->key, HW_HASH_KEY_SIZE); 1839 bp->rss_hash_key_updated = true; 1840 } 1841 } 1842 if (rxfh->indir) { 1843 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(bp->dev); 1844 u32 *indir_tbl = bp->rss_indir_tbl; 1845 1846 if (rss_ctx) 1847 indir_tbl = ethtool_rxfh_context_indir(ctx); 1848 for (i = 0; i < tbl_size; i++) 1849 indir_tbl[i] = rxfh->indir[i]; 1850 pad = bp->rss_indir_tbl_entries - tbl_size; 1851 if (pad) 1852 memset(&indir_tbl[i], 0, pad * sizeof(*indir_tbl)); 1853 } 1854 } 1855 1856 static int bnxt_rxfh_context_check(struct bnxt *bp, 1857 const struct ethtool_rxfh_param *rxfh, 1858 struct netlink_ext_ack *extack) 1859 { 1860 if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP) { 1861 NL_SET_ERR_MSG_MOD(extack, "RSS hash function not supported"); 1862 return -EOPNOTSUPP; 1863 } 1864 1865 if (!BNXT_SUPPORTS_MULTI_RSS_CTX(bp)) { 1866 NL_SET_ERR_MSG_MOD(extack, "RSS contexts not supported"); 1867 return -EOPNOTSUPP; 1868 } 1869 1870 if (!netif_running(bp->dev)) { 1871 NL_SET_ERR_MSG_MOD(extack, "Unable to set RSS contexts when interface is down"); 1872 return -EAGAIN; 1873 } 1874 1875 return 0; 1876 } 1877 1878 static int bnxt_create_rxfh_context(struct net_device *dev, 1879 struct ethtool_rxfh_context *ctx, 1880 const struct ethtool_rxfh_param *rxfh, 1881 struct netlink_ext_ack *extack) 1882 { 1883 struct bnxt *bp = netdev_priv(dev); 1884 struct bnxt_rss_ctx *rss_ctx; 1885 struct bnxt_vnic_info *vnic; 1886 int rc; 1887 1888 rc = bnxt_rxfh_context_check(bp, rxfh, extack); 1889 if (rc) 1890 return rc; 1891 1892 if (bp->num_rss_ctx >= BNXT_MAX_ETH_RSS_CTX) { 1893 NL_SET_ERR_MSG_FMT_MOD(extack, "Out of RSS contexts, maximum %u", 1894 BNXT_MAX_ETH_RSS_CTX); 1895 return -EINVAL; 1896 } 1897 1898 if (!bnxt_rfs_capable(bp, true)) { 1899 NL_SET_ERR_MSG_MOD(extack, "Out hardware resources"); 1900 return -ENOMEM; 1901 } 1902 1903 rss_ctx = ethtool_rxfh_context_priv(ctx); 1904 1905 bp->num_rss_ctx++; 1906 1907 vnic = &rss_ctx->vnic; 1908 vnic->rss_ctx = ctx; 1909 vnic->flags |= BNXT_VNIC_RSSCTX_FLAG; 1910 vnic->vnic_id = BNXT_VNIC_ID_INVALID; 1911 rc = bnxt_alloc_vnic_rss_table(bp, vnic); 1912 if (rc) 1913 goto out; 1914 1915 /* Populate defaults in the context */ 1916 bnxt_set_dflt_rss_indir_tbl(bp, ctx); 1917 ctx->hfunc = ETH_RSS_HASH_TOP; 1918 memcpy(vnic->rss_hash_key, bp->rss_hash_key, HW_HASH_KEY_SIZE); 1919 memcpy(ethtool_rxfh_context_key(ctx), 1920 bp->rss_hash_key, HW_HASH_KEY_SIZE); 1921 1922 rc = bnxt_hwrm_vnic_alloc(bp, vnic, 0, bp->rx_nr_rings); 1923 if (rc) { 1924 NL_SET_ERR_MSG_MOD(extack, "Unable to allocate VNIC"); 1925 goto out; 1926 } 1927 1928 rc = bnxt_hwrm_vnic_set_tpa(bp, vnic, bp->flags & BNXT_FLAG_TPA); 1929 if (rc) { 1930 NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA"); 1931 goto out; 1932 } 1933 bnxt_modify_rss(bp, ctx, rss_ctx, rxfh); 1934 1935 rc = __bnxt_setup_vnic_p5(bp, vnic); 1936 if (rc) { 1937 NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA"); 1938 goto out; 1939 } 1940 1941 rss_ctx->index = rxfh->rss_context; 1942 return 0; 1943 out: 1944 bnxt_del_one_rss_ctx(bp, rss_ctx, true); 1945 return rc; 1946 } 1947 1948 static int bnxt_modify_rxfh_context(struct net_device *dev, 1949 struct ethtool_rxfh_context *ctx, 1950 const struct ethtool_rxfh_param *rxfh, 1951 struct netlink_ext_ack *extack) 1952 { 1953 struct bnxt *bp = netdev_priv(dev); 1954 struct bnxt_rss_ctx *rss_ctx; 1955 int rc; 1956 1957 rc = bnxt_rxfh_context_check(bp, rxfh, extack); 1958 if (rc) 1959 return rc; 1960 1961 rss_ctx = ethtool_rxfh_context_priv(ctx); 1962 1963 bnxt_modify_rss(bp, ctx, rss_ctx, rxfh); 1964 1965 return bnxt_hwrm_vnic_rss_cfg_p5(bp, &rss_ctx->vnic); 1966 } 1967 1968 static int bnxt_remove_rxfh_context(struct net_device *dev, 1969 struct ethtool_rxfh_context *ctx, 1970 u32 rss_context, 1971 struct netlink_ext_ack *extack) 1972 { 1973 struct bnxt *bp = netdev_priv(dev); 1974 struct bnxt_rss_ctx *rss_ctx; 1975 1976 rss_ctx = ethtool_rxfh_context_priv(ctx); 1977 1978 bnxt_del_one_rss_ctx(bp, rss_ctx, true); 1979 return 0; 1980 } 1981 1982 static int bnxt_set_rxfh(struct net_device *dev, 1983 struct ethtool_rxfh_param *rxfh, 1984 struct netlink_ext_ack *extack) 1985 { 1986 struct bnxt *bp = netdev_priv(dev); 1987 int rc = 0; 1988 1989 if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP) 1990 return -EOPNOTSUPP; 1991 1992 bnxt_modify_rss(bp, NULL, NULL, rxfh); 1993 1994 if (netif_running(bp->dev)) { 1995 bnxt_close_nic(bp, false, false); 1996 rc = bnxt_open_nic(bp, false, false); 1997 } 1998 return rc; 1999 } 2000 2001 static void bnxt_get_drvinfo(struct net_device *dev, 2002 struct ethtool_drvinfo *info) 2003 { 2004 struct bnxt *bp = netdev_priv(dev); 2005 2006 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 2007 strscpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 2008 strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 2009 info->n_stats = bnxt_get_num_stats(bp); 2010 info->testinfo_len = bp->num_tests; 2011 /* TODO CHIMP_FW: eeprom dump details */ 2012 info->eedump_len = 0; 2013 /* TODO CHIMP FW: reg dump details */ 2014 info->regdump_len = 0; 2015 } 2016 2017 static int bnxt_get_regs_len(struct net_device *dev) 2018 { 2019 struct bnxt *bp = netdev_priv(dev); 2020 int reg_len; 2021 2022 if (!BNXT_PF(bp)) 2023 return -EOPNOTSUPP; 2024 2025 reg_len = BNXT_PXP_REG_LEN; 2026 2027 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED) 2028 reg_len += sizeof(struct pcie_ctx_hw_stats); 2029 2030 return reg_len; 2031 } 2032 2033 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs, 2034 void *_p) 2035 { 2036 struct pcie_ctx_hw_stats *hw_pcie_stats; 2037 struct hwrm_pcie_qstats_input *req; 2038 struct bnxt *bp = netdev_priv(dev); 2039 dma_addr_t hw_pcie_stats_addr; 2040 int rc; 2041 2042 regs->version = 0; 2043 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p); 2044 2045 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 2046 return; 2047 2048 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS)) 2049 return; 2050 2051 hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats), 2052 &hw_pcie_stats_addr); 2053 if (!hw_pcie_stats) { 2054 hwrm_req_drop(bp, req); 2055 return; 2056 } 2057 2058 regs->version = 1; 2059 hwrm_req_hold(bp, req); /* hold on to slice */ 2060 req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats)); 2061 req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr); 2062 rc = hwrm_req_send(bp, req); 2063 if (!rc) { 2064 __le64 *src = (__le64 *)hw_pcie_stats; 2065 u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN); 2066 int i; 2067 2068 for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++) 2069 dst[i] = le64_to_cpu(src[i]); 2070 } 2071 hwrm_req_drop(bp, req); 2072 } 2073 2074 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2075 { 2076 struct bnxt *bp = netdev_priv(dev); 2077 2078 wol->supported = 0; 2079 wol->wolopts = 0; 2080 memset(&wol->sopass, 0, sizeof(wol->sopass)); 2081 if (bp->flags & BNXT_FLAG_WOL_CAP) { 2082 wol->supported = WAKE_MAGIC; 2083 if (bp->wol) 2084 wol->wolopts = WAKE_MAGIC; 2085 } 2086 } 2087 2088 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2089 { 2090 struct bnxt *bp = netdev_priv(dev); 2091 2092 if (wol->wolopts & ~WAKE_MAGIC) 2093 return -EINVAL; 2094 2095 if (wol->wolopts & WAKE_MAGIC) { 2096 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 2097 return -EINVAL; 2098 if (!bp->wol) { 2099 if (bnxt_hwrm_alloc_wol_fltr(bp)) 2100 return -EBUSY; 2101 bp->wol = 1; 2102 } 2103 } else { 2104 if (bp->wol) { 2105 if (bnxt_hwrm_free_wol_fltr(bp)) 2106 return -EBUSY; 2107 bp->wol = 0; 2108 } 2109 } 2110 return 0; 2111 } 2112 2113 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 2114 void _bnxt_fw_to_linkmode(unsigned long *mode, u16 fw_speeds) 2115 { 2116 linkmode_zero(mode); 2117 2118 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 2119 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode); 2120 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 2121 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode); 2122 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 2123 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT, mode); 2124 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 2125 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode); 2126 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 2127 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode); 2128 } 2129 2130 enum bnxt_media_type { 2131 BNXT_MEDIA_UNKNOWN = 0, 2132 BNXT_MEDIA_TP, 2133 BNXT_MEDIA_CR, 2134 BNXT_MEDIA_SR, 2135 BNXT_MEDIA_LR_ER_FR, 2136 BNXT_MEDIA_KR, 2137 BNXT_MEDIA_KX, 2138 BNXT_MEDIA_X, 2139 __BNXT_MEDIA_END, 2140 }; 2141 2142 static const enum bnxt_media_type bnxt_phy_types[] = { 2143 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR] = BNXT_MEDIA_CR, 2144 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4] = BNXT_MEDIA_KR, 2145 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR] = BNXT_MEDIA_LR_ER_FR, 2146 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR] = BNXT_MEDIA_SR, 2147 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2] = BNXT_MEDIA_KR, 2148 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX] = BNXT_MEDIA_KX, 2149 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR] = BNXT_MEDIA_KR, 2150 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASET] = BNXT_MEDIA_TP, 2151 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE] = BNXT_MEDIA_TP, 2152 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L] = BNXT_MEDIA_CR, 2153 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S] = BNXT_MEDIA_CR, 2154 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N] = BNXT_MEDIA_CR, 2155 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR] = BNXT_MEDIA_SR, 2156 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4] = BNXT_MEDIA_CR, 2157 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4] = BNXT_MEDIA_SR, 2158 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2159 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2160 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10] = BNXT_MEDIA_SR, 2161 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4] = BNXT_MEDIA_CR, 2162 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4] = BNXT_MEDIA_SR, 2163 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2164 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2165 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE] = BNXT_MEDIA_SR, 2166 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET] = BNXT_MEDIA_TP, 2167 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX] = BNXT_MEDIA_X, 2168 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX] = BNXT_MEDIA_X, 2169 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4] = BNXT_MEDIA_CR, 2170 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4] = BNXT_MEDIA_SR, 2171 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2172 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2173 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR] = BNXT_MEDIA_CR, 2174 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR] = BNXT_MEDIA_SR, 2175 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR] = BNXT_MEDIA_LR_ER_FR, 2176 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER] = BNXT_MEDIA_LR_ER_FR, 2177 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2] = BNXT_MEDIA_CR, 2178 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2] = BNXT_MEDIA_SR, 2179 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2] = BNXT_MEDIA_LR_ER_FR, 2180 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2] = BNXT_MEDIA_LR_ER_FR, 2181 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR] = BNXT_MEDIA_CR, 2182 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR] = BNXT_MEDIA_SR, 2183 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR] = BNXT_MEDIA_LR_ER_FR, 2184 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER] = BNXT_MEDIA_LR_ER_FR, 2185 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2] = BNXT_MEDIA_CR, 2186 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2] = BNXT_MEDIA_SR, 2187 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2] = BNXT_MEDIA_LR_ER_FR, 2188 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2] = BNXT_MEDIA_LR_ER_FR, 2189 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8] = BNXT_MEDIA_CR, 2190 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8] = BNXT_MEDIA_SR, 2191 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8] = BNXT_MEDIA_LR_ER_FR, 2192 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8] = BNXT_MEDIA_LR_ER_FR, 2193 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4] = BNXT_MEDIA_CR, 2194 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4] = BNXT_MEDIA_SR, 2195 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2196 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2197 }; 2198 2199 static enum bnxt_media_type 2200 bnxt_get_media(struct bnxt_link_info *link_info) 2201 { 2202 switch (link_info->media_type) { 2203 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP: 2204 return BNXT_MEDIA_TP; 2205 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC: 2206 return BNXT_MEDIA_CR; 2207 default: 2208 if (link_info->phy_type < ARRAY_SIZE(bnxt_phy_types)) 2209 return bnxt_phy_types[link_info->phy_type]; 2210 return BNXT_MEDIA_UNKNOWN; 2211 } 2212 } 2213 2214 enum bnxt_link_speed_indices { 2215 BNXT_LINK_SPEED_UNKNOWN = 0, 2216 BNXT_LINK_SPEED_100MB_IDX, 2217 BNXT_LINK_SPEED_1GB_IDX, 2218 BNXT_LINK_SPEED_10GB_IDX, 2219 BNXT_LINK_SPEED_25GB_IDX, 2220 BNXT_LINK_SPEED_40GB_IDX, 2221 BNXT_LINK_SPEED_50GB_IDX, 2222 BNXT_LINK_SPEED_100GB_IDX, 2223 BNXT_LINK_SPEED_200GB_IDX, 2224 BNXT_LINK_SPEED_400GB_IDX, 2225 __BNXT_LINK_SPEED_END 2226 }; 2227 2228 static enum bnxt_link_speed_indices bnxt_fw_speed_idx(u16 speed) 2229 { 2230 switch (speed) { 2231 case BNXT_LINK_SPEED_100MB: return BNXT_LINK_SPEED_100MB_IDX; 2232 case BNXT_LINK_SPEED_1GB: return BNXT_LINK_SPEED_1GB_IDX; 2233 case BNXT_LINK_SPEED_10GB: return BNXT_LINK_SPEED_10GB_IDX; 2234 case BNXT_LINK_SPEED_25GB: return BNXT_LINK_SPEED_25GB_IDX; 2235 case BNXT_LINK_SPEED_40GB: return BNXT_LINK_SPEED_40GB_IDX; 2236 case BNXT_LINK_SPEED_50GB: 2237 case BNXT_LINK_SPEED_50GB_PAM4: 2238 return BNXT_LINK_SPEED_50GB_IDX; 2239 case BNXT_LINK_SPEED_100GB: 2240 case BNXT_LINK_SPEED_100GB_PAM4: 2241 case BNXT_LINK_SPEED_100GB_PAM4_112: 2242 return BNXT_LINK_SPEED_100GB_IDX; 2243 case BNXT_LINK_SPEED_200GB: 2244 case BNXT_LINK_SPEED_200GB_PAM4: 2245 case BNXT_LINK_SPEED_200GB_PAM4_112: 2246 return BNXT_LINK_SPEED_200GB_IDX; 2247 case BNXT_LINK_SPEED_400GB: 2248 case BNXT_LINK_SPEED_400GB_PAM4: 2249 case BNXT_LINK_SPEED_400GB_PAM4_112: 2250 return BNXT_LINK_SPEED_400GB_IDX; 2251 default: return BNXT_LINK_SPEED_UNKNOWN; 2252 } 2253 } 2254 2255 static const enum ethtool_link_mode_bit_indices 2256 bnxt_link_modes[__BNXT_LINK_SPEED_END][BNXT_SIG_MODE_MAX][__BNXT_MEDIA_END] = { 2257 [BNXT_LINK_SPEED_100MB_IDX] = { 2258 { 2259 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_100baseT_Full_BIT, 2260 }, 2261 }, 2262 [BNXT_LINK_SPEED_1GB_IDX] = { 2263 { 2264 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 2265 /* historically baseT, but DAC is more correctly baseX */ 2266 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 2267 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2268 [BNXT_MEDIA_X] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 2269 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2270 }, 2271 }, 2272 [BNXT_LINK_SPEED_10GB_IDX] = { 2273 { 2274 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 2275 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 2276 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 2277 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 2278 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 2279 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 2280 }, 2281 }, 2282 [BNXT_LINK_SPEED_25GB_IDX] = { 2283 { 2284 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 2285 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 2286 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 2287 }, 2288 }, 2289 [BNXT_LINK_SPEED_40GB_IDX] = { 2290 { 2291 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 2292 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 2293 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 2294 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 2295 }, 2296 }, 2297 [BNXT_LINK_SPEED_50GB_IDX] = { 2298 [BNXT_SIG_MODE_NRZ] = { 2299 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 2300 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 2301 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 2302 }, 2303 [BNXT_SIG_MODE_PAM4] = { 2304 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 2305 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 2306 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 2307 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 2308 }, 2309 }, 2310 [BNXT_LINK_SPEED_100GB_IDX] = { 2311 [BNXT_SIG_MODE_NRZ] = { 2312 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 2313 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 2314 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 2315 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 2316 }, 2317 [BNXT_SIG_MODE_PAM4] = { 2318 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 2319 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 2320 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 2321 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 2322 }, 2323 [BNXT_SIG_MODE_PAM4_112] = { 2324 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR_Full_BIT, 2325 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR_Full_BIT, 2326 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR_Full_BIT, 2327 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT, 2328 }, 2329 }, 2330 [BNXT_LINK_SPEED_200GB_IDX] = { 2331 [BNXT_SIG_MODE_PAM4] = { 2332 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT, 2333 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 2334 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 2335 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 2336 }, 2337 [BNXT_SIG_MODE_PAM4_112] = { 2338 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT, 2339 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT, 2340 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT, 2341 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT, 2342 }, 2343 }, 2344 [BNXT_LINK_SPEED_400GB_IDX] = { 2345 [BNXT_SIG_MODE_PAM4] = { 2346 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT, 2347 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT, 2348 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT, 2349 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT, 2350 }, 2351 [BNXT_SIG_MODE_PAM4_112] = { 2352 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT, 2353 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT, 2354 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT, 2355 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT, 2356 }, 2357 }, 2358 }; 2359 2360 #define BNXT_LINK_MODE_UNKNOWN -1 2361 2362 static enum ethtool_link_mode_bit_indices 2363 bnxt_get_link_mode(struct bnxt_link_info *link_info) 2364 { 2365 enum ethtool_link_mode_bit_indices link_mode; 2366 enum bnxt_link_speed_indices speed; 2367 enum bnxt_media_type media; 2368 u8 sig_mode; 2369 2370 if (link_info->phy_link_status != BNXT_LINK_LINK) 2371 return BNXT_LINK_MODE_UNKNOWN; 2372 2373 media = bnxt_get_media(link_info); 2374 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 2375 speed = bnxt_fw_speed_idx(link_info->link_speed); 2376 sig_mode = link_info->active_fec_sig_mode & 2377 PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK; 2378 } else { 2379 speed = bnxt_fw_speed_idx(link_info->req_link_speed); 2380 sig_mode = link_info->req_signal_mode; 2381 } 2382 if (sig_mode >= BNXT_SIG_MODE_MAX) 2383 return BNXT_LINK_MODE_UNKNOWN; 2384 2385 /* Note ETHTOOL_LINK_MODE_10baseT_Half_BIT == 0 is a legal Linux 2386 * link mode, but since no such devices exist, the zeroes in the 2387 * map can be conveniently used to represent unknown link modes. 2388 */ 2389 link_mode = bnxt_link_modes[speed][sig_mode][media]; 2390 if (!link_mode) 2391 return BNXT_LINK_MODE_UNKNOWN; 2392 2393 switch (link_mode) { 2394 case ETHTOOL_LINK_MODE_100baseT_Full_BIT: 2395 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2396 link_mode = ETHTOOL_LINK_MODE_100baseT_Half_BIT; 2397 break; 2398 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT: 2399 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2400 link_mode = ETHTOOL_LINK_MODE_1000baseT_Half_BIT; 2401 break; 2402 default: 2403 break; 2404 } 2405 2406 return link_mode; 2407 } 2408 2409 static void bnxt_get_ethtool_modes(struct bnxt_link_info *link_info, 2410 struct ethtool_link_ksettings *lk_ksettings) 2411 { 2412 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2413 2414 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) { 2415 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2416 lk_ksettings->link_modes.supported); 2417 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2418 lk_ksettings->link_modes.supported); 2419 } 2420 2421 if (link_info->support_auto_speeds || link_info->support_auto_speeds2 || 2422 link_info->support_pam4_auto_speeds) 2423 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2424 lk_ksettings->link_modes.supported); 2425 2426 if (~link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 2427 return; 2428 2429 if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_RX) 2430 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2431 lk_ksettings->link_modes.advertising); 2432 if (hweight8(link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) == 1) 2433 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2434 lk_ksettings->link_modes.advertising); 2435 if (link_info->lp_pause & BNXT_LINK_PAUSE_RX) 2436 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2437 lk_ksettings->link_modes.lp_advertising); 2438 if (hweight8(link_info->lp_pause & BNXT_LINK_PAUSE_BOTH) == 1) 2439 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2440 lk_ksettings->link_modes.lp_advertising); 2441 } 2442 2443 static const u16 bnxt_nrz_speed_masks[] = { 2444 [BNXT_LINK_SPEED_100MB_IDX] = BNXT_LINK_SPEED_MSK_100MB, 2445 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEED_MSK_1GB, 2446 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEED_MSK_10GB, 2447 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEED_MSK_25GB, 2448 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEED_MSK_40GB, 2449 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEED_MSK_50GB, 2450 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEED_MSK_100GB, 2451 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2452 }; 2453 2454 static const u16 bnxt_pam4_speed_masks[] = { 2455 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_50GB, 2456 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_100GB, 2457 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_200GB, 2458 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2459 }; 2460 2461 static const u16 bnxt_nrz_speeds2_masks[] = { 2462 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEEDS2_MSK_1GB, 2463 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEEDS2_MSK_10GB, 2464 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEEDS2_MSK_25GB, 2465 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEEDS2_MSK_40GB, 2466 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB, 2467 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB, 2468 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2469 }; 2470 2471 static const u16 bnxt_pam4_speeds2_masks[] = { 2472 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB_PAM4, 2473 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4, 2474 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4, 2475 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4, 2476 }; 2477 2478 static const u16 bnxt_pam4_112_speeds2_masks[] = { 2479 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112, 2480 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112, 2481 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112, 2482 }; 2483 2484 static enum bnxt_link_speed_indices 2485 bnxt_encoding_speed_idx(u8 sig_mode, u16 phy_flags, u16 speed_msk) 2486 { 2487 const u16 *speeds; 2488 int idx, len; 2489 2490 switch (sig_mode) { 2491 case BNXT_SIG_MODE_NRZ: 2492 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2493 speeds = bnxt_nrz_speeds2_masks; 2494 len = ARRAY_SIZE(bnxt_nrz_speeds2_masks); 2495 } else { 2496 speeds = bnxt_nrz_speed_masks; 2497 len = ARRAY_SIZE(bnxt_nrz_speed_masks); 2498 } 2499 break; 2500 case BNXT_SIG_MODE_PAM4: 2501 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2502 speeds = bnxt_pam4_speeds2_masks; 2503 len = ARRAY_SIZE(bnxt_pam4_speeds2_masks); 2504 } else { 2505 speeds = bnxt_pam4_speed_masks; 2506 len = ARRAY_SIZE(bnxt_pam4_speed_masks); 2507 } 2508 break; 2509 case BNXT_SIG_MODE_PAM4_112: 2510 speeds = bnxt_pam4_112_speeds2_masks; 2511 len = ARRAY_SIZE(bnxt_pam4_112_speeds2_masks); 2512 break; 2513 default: 2514 return BNXT_LINK_SPEED_UNKNOWN; 2515 } 2516 2517 for (idx = 0; idx < len; idx++) { 2518 if (speeds[idx] == speed_msk) 2519 return idx; 2520 } 2521 2522 return BNXT_LINK_SPEED_UNKNOWN; 2523 } 2524 2525 #define BNXT_FW_SPEED_MSK_BITS 16 2526 2527 static void 2528 __bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media, 2529 u8 sig_mode, u16 phy_flags, unsigned long *et_mask) 2530 { 2531 enum ethtool_link_mode_bit_indices link_mode; 2532 enum bnxt_link_speed_indices speed; 2533 u8 bit; 2534 2535 for_each_set_bit(bit, &fw_mask, BNXT_FW_SPEED_MSK_BITS) { 2536 speed = bnxt_encoding_speed_idx(sig_mode, phy_flags, 1 << bit); 2537 if (!speed) 2538 continue; 2539 2540 link_mode = bnxt_link_modes[speed][sig_mode][media]; 2541 if (!link_mode) 2542 continue; 2543 2544 linkmode_set_bit(link_mode, et_mask); 2545 } 2546 } 2547 2548 static void 2549 bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media, 2550 u8 sig_mode, u16 phy_flags, unsigned long *et_mask) 2551 { 2552 if (media) { 2553 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags, 2554 et_mask); 2555 return; 2556 } 2557 2558 /* list speeds for all media if unknown */ 2559 for (media = 1; media < __BNXT_MEDIA_END; media++) 2560 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags, 2561 et_mask); 2562 } 2563 2564 static void 2565 bnxt_get_all_ethtool_support_speeds(struct bnxt_link_info *link_info, 2566 enum bnxt_media_type media, 2567 struct ethtool_link_ksettings *lk_ksettings) 2568 { 2569 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2570 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0; 2571 u16 phy_flags = bp->phy_flags; 2572 2573 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2574 sp_nrz = link_info->support_speeds2; 2575 sp_pam4 = link_info->support_speeds2; 2576 sp_pam4_112 = link_info->support_speeds2; 2577 } else { 2578 sp_nrz = link_info->support_speeds; 2579 sp_pam4 = link_info->support_pam4_speeds; 2580 } 2581 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags, 2582 lk_ksettings->link_modes.supported); 2583 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags, 2584 lk_ksettings->link_modes.supported); 2585 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112, 2586 phy_flags, lk_ksettings->link_modes.supported); 2587 } 2588 2589 static void 2590 bnxt_get_all_ethtool_adv_speeds(struct bnxt_link_info *link_info, 2591 enum bnxt_media_type media, 2592 struct ethtool_link_ksettings *lk_ksettings) 2593 { 2594 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2595 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0; 2596 u16 phy_flags = bp->phy_flags; 2597 2598 sp_nrz = link_info->advertising; 2599 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2600 sp_pam4 = link_info->advertising; 2601 sp_pam4_112 = link_info->advertising; 2602 } else { 2603 sp_pam4 = link_info->advertising_pam4; 2604 } 2605 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags, 2606 lk_ksettings->link_modes.advertising); 2607 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags, 2608 lk_ksettings->link_modes.advertising); 2609 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112, 2610 phy_flags, lk_ksettings->link_modes.advertising); 2611 } 2612 2613 static void 2614 bnxt_get_all_ethtool_lp_speeds(struct bnxt_link_info *link_info, 2615 enum bnxt_media_type media, 2616 struct ethtool_link_ksettings *lk_ksettings) 2617 { 2618 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2619 u16 phy_flags = bp->phy_flags; 2620 2621 bnxt_get_ethtool_speeds(link_info->lp_auto_link_speeds, media, 2622 BNXT_SIG_MODE_NRZ, phy_flags, 2623 lk_ksettings->link_modes.lp_advertising); 2624 bnxt_get_ethtool_speeds(link_info->lp_auto_pam4_link_speeds, media, 2625 BNXT_SIG_MODE_PAM4, phy_flags, 2626 lk_ksettings->link_modes.lp_advertising); 2627 } 2628 2629 static void bnxt_update_speed(u32 *delta, bool installed_media, u16 *speeds, 2630 u16 speed_msk, const unsigned long *et_mask, 2631 enum ethtool_link_mode_bit_indices mode) 2632 { 2633 bool mode_desired = linkmode_test_bit(mode, et_mask); 2634 2635 if (!mode) 2636 return; 2637 2638 /* enabled speeds for installed media should override */ 2639 if (installed_media && mode_desired) { 2640 *speeds |= speed_msk; 2641 *delta |= speed_msk; 2642 return; 2643 } 2644 2645 /* many to one mapping, only allow one change per fw_speed bit */ 2646 if (!(*delta & speed_msk) && (mode_desired == !(*speeds & speed_msk))) { 2647 *speeds ^= speed_msk; 2648 *delta |= speed_msk; 2649 } 2650 } 2651 2652 static void bnxt_set_ethtool_speeds(struct bnxt_link_info *link_info, 2653 const unsigned long *et_mask) 2654 { 2655 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2656 u16 const *sp_msks, *sp_pam4_msks, *sp_pam4_112_msks; 2657 enum bnxt_media_type media = bnxt_get_media(link_info); 2658 u16 *adv, *adv_pam4, *adv_pam4_112 = NULL; 2659 u32 delta_pam4_112 = 0; 2660 u32 delta_pam4 = 0; 2661 u32 delta_nrz = 0; 2662 int i, m; 2663 2664 adv = &link_info->advertising; 2665 if (bp->phy_flags & BNXT_PHY_FL_SPEEDS2) { 2666 adv_pam4 = &link_info->advertising; 2667 adv_pam4_112 = &link_info->advertising; 2668 sp_msks = bnxt_nrz_speeds2_masks; 2669 sp_pam4_msks = bnxt_pam4_speeds2_masks; 2670 sp_pam4_112_msks = bnxt_pam4_112_speeds2_masks; 2671 } else { 2672 adv_pam4 = &link_info->advertising_pam4; 2673 sp_msks = bnxt_nrz_speed_masks; 2674 sp_pam4_msks = bnxt_pam4_speed_masks; 2675 } 2676 for (i = 1; i < __BNXT_LINK_SPEED_END; i++) { 2677 /* accept any legal media from user */ 2678 for (m = 1; m < __BNXT_MEDIA_END; m++) { 2679 bnxt_update_speed(&delta_nrz, m == media, 2680 adv, sp_msks[i], et_mask, 2681 bnxt_link_modes[i][BNXT_SIG_MODE_NRZ][m]); 2682 bnxt_update_speed(&delta_pam4, m == media, 2683 adv_pam4, sp_pam4_msks[i], et_mask, 2684 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4][m]); 2685 if (!adv_pam4_112) 2686 continue; 2687 2688 bnxt_update_speed(&delta_pam4_112, m == media, 2689 adv_pam4_112, sp_pam4_112_msks[i], et_mask, 2690 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4_112][m]); 2691 } 2692 } 2693 } 2694 2695 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info, 2696 struct ethtool_link_ksettings *lk_ksettings) 2697 { 2698 u16 fec_cfg = link_info->fec_cfg; 2699 2700 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) { 2701 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 2702 lk_ksettings->link_modes.advertising); 2703 return; 2704 } 2705 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 2706 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 2707 lk_ksettings->link_modes.advertising); 2708 if (fec_cfg & BNXT_FEC_ENC_RS) 2709 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 2710 lk_ksettings->link_modes.advertising); 2711 if (fec_cfg & BNXT_FEC_ENC_LLRS) 2712 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 2713 lk_ksettings->link_modes.advertising); 2714 } 2715 2716 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info, 2717 struct ethtool_link_ksettings *lk_ksettings) 2718 { 2719 u16 fec_cfg = link_info->fec_cfg; 2720 2721 if (fec_cfg & BNXT_FEC_NONE) { 2722 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 2723 lk_ksettings->link_modes.supported); 2724 return; 2725 } 2726 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP) 2727 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 2728 lk_ksettings->link_modes.supported); 2729 if (fec_cfg & BNXT_FEC_ENC_RS_CAP) 2730 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 2731 lk_ksettings->link_modes.supported); 2732 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP) 2733 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 2734 lk_ksettings->link_modes.supported); 2735 } 2736 2737 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 2738 { 2739 switch (fw_link_speed) { 2740 case BNXT_LINK_SPEED_100MB: 2741 return SPEED_100; 2742 case BNXT_LINK_SPEED_1GB: 2743 return SPEED_1000; 2744 case BNXT_LINK_SPEED_2_5GB: 2745 return SPEED_2500; 2746 case BNXT_LINK_SPEED_10GB: 2747 return SPEED_10000; 2748 case BNXT_LINK_SPEED_20GB: 2749 return SPEED_20000; 2750 case BNXT_LINK_SPEED_25GB: 2751 return SPEED_25000; 2752 case BNXT_LINK_SPEED_40GB: 2753 return SPEED_40000; 2754 case BNXT_LINK_SPEED_50GB: 2755 case BNXT_LINK_SPEED_50GB_PAM4: 2756 return SPEED_50000; 2757 case BNXT_LINK_SPEED_100GB: 2758 case BNXT_LINK_SPEED_100GB_PAM4: 2759 case BNXT_LINK_SPEED_100GB_PAM4_112: 2760 return SPEED_100000; 2761 case BNXT_LINK_SPEED_200GB: 2762 case BNXT_LINK_SPEED_200GB_PAM4: 2763 case BNXT_LINK_SPEED_200GB_PAM4_112: 2764 return SPEED_200000; 2765 case BNXT_LINK_SPEED_400GB: 2766 case BNXT_LINK_SPEED_400GB_PAM4: 2767 case BNXT_LINK_SPEED_400GB_PAM4_112: 2768 return SPEED_400000; 2769 default: 2770 return SPEED_UNKNOWN; 2771 } 2772 } 2773 2774 static void bnxt_get_default_speeds(struct ethtool_link_ksettings *lk_ksettings, 2775 struct bnxt_link_info *link_info) 2776 { 2777 struct ethtool_link_settings_hdr *base = &lk_ksettings->base; 2778 2779 if (link_info->link_state == BNXT_LINK_STATE_UP) { 2780 base->speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 2781 base->duplex = DUPLEX_HALF; 2782 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2783 base->duplex = DUPLEX_FULL; 2784 lk_ksettings->lanes = link_info->active_lanes; 2785 } else if (!link_info->autoneg) { 2786 base->speed = bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 2787 base->duplex = DUPLEX_HALF; 2788 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 2789 base->duplex = DUPLEX_FULL; 2790 } 2791 } 2792 2793 static int bnxt_get_link_ksettings(struct net_device *dev, 2794 struct ethtool_link_ksettings *lk_ksettings) 2795 { 2796 struct ethtool_link_settings_hdr *base = &lk_ksettings->base; 2797 enum ethtool_link_mode_bit_indices link_mode; 2798 struct bnxt *bp = netdev_priv(dev); 2799 struct bnxt_link_info *link_info; 2800 enum bnxt_media_type media; 2801 2802 ethtool_link_ksettings_zero_link_mode(lk_ksettings, lp_advertising); 2803 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 2804 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 2805 base->duplex = DUPLEX_UNKNOWN; 2806 base->speed = SPEED_UNKNOWN; 2807 link_info = &bp->link_info; 2808 2809 mutex_lock(&bp->link_lock); 2810 bnxt_get_ethtool_modes(link_info, lk_ksettings); 2811 media = bnxt_get_media(link_info); 2812 bnxt_get_all_ethtool_support_speeds(link_info, media, lk_ksettings); 2813 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings); 2814 link_mode = bnxt_get_link_mode(link_info); 2815 if (link_mode != BNXT_LINK_MODE_UNKNOWN) 2816 ethtool_params_from_link_mode(lk_ksettings, link_mode); 2817 else 2818 bnxt_get_default_speeds(lk_ksettings, link_info); 2819 2820 if (link_info->autoneg) { 2821 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings); 2822 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2823 lk_ksettings->link_modes.advertising); 2824 base->autoneg = AUTONEG_ENABLE; 2825 bnxt_get_all_ethtool_adv_speeds(link_info, media, lk_ksettings); 2826 if (link_info->phy_link_status == BNXT_LINK_LINK) 2827 bnxt_get_all_ethtool_lp_speeds(link_info, media, 2828 lk_ksettings); 2829 } else { 2830 base->autoneg = AUTONEG_DISABLE; 2831 } 2832 2833 base->port = PORT_NONE; 2834 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 2835 base->port = PORT_TP; 2836 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2837 lk_ksettings->link_modes.supported); 2838 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2839 lk_ksettings->link_modes.advertising); 2840 } else { 2841 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 2842 lk_ksettings->link_modes.supported); 2843 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 2844 lk_ksettings->link_modes.advertising); 2845 2846 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC) 2847 base->port = PORT_DA; 2848 else 2849 base->port = PORT_FIBRE; 2850 } 2851 base->phy_address = link_info->phy_addr; 2852 mutex_unlock(&bp->link_lock); 2853 2854 return 0; 2855 } 2856 2857 static int 2858 bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed, u32 lanes) 2859 { 2860 struct bnxt *bp = netdev_priv(dev); 2861 struct bnxt_link_info *link_info = &bp->link_info; 2862 u16 support_pam4_spds = link_info->support_pam4_speeds; 2863 u16 support_spds2 = link_info->support_speeds2; 2864 u16 support_spds = link_info->support_speeds; 2865 u8 sig_mode = BNXT_SIG_MODE_NRZ; 2866 u32 lanes_needed = 1; 2867 u16 fw_speed = 0; 2868 2869 switch (ethtool_speed) { 2870 case SPEED_100: 2871 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 2872 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB; 2873 break; 2874 case SPEED_1000: 2875 if ((support_spds & BNXT_LINK_SPEED_MSK_1GB) || 2876 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_1GB)) 2877 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 2878 break; 2879 case SPEED_2500: 2880 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 2881 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB; 2882 break; 2883 case SPEED_10000: 2884 if ((support_spds & BNXT_LINK_SPEED_MSK_10GB) || 2885 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_10GB)) 2886 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 2887 break; 2888 case SPEED_20000: 2889 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) { 2890 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB; 2891 lanes_needed = 2; 2892 } 2893 break; 2894 case SPEED_25000: 2895 if ((support_spds & BNXT_LINK_SPEED_MSK_25GB) || 2896 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_25GB)) 2897 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 2898 break; 2899 case SPEED_40000: 2900 if ((support_spds & BNXT_LINK_SPEED_MSK_40GB) || 2901 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_40GB)) { 2902 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 2903 lanes_needed = 4; 2904 } 2905 break; 2906 case SPEED_50000: 2907 if (((support_spds & BNXT_LINK_SPEED_MSK_50GB) || 2908 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB)) && 2909 lanes != 1) { 2910 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 2911 lanes_needed = 2; 2912 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) { 2913 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB; 2914 sig_mode = BNXT_SIG_MODE_PAM4; 2915 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB_PAM4) { 2916 fw_speed = BNXT_LINK_SPEED_50GB_PAM4; 2917 sig_mode = BNXT_SIG_MODE_PAM4; 2918 } 2919 break; 2920 case SPEED_100000: 2921 if (((support_spds & BNXT_LINK_SPEED_MSK_100GB) || 2922 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB)) && 2923 lanes != 2 && lanes != 1) { 2924 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB; 2925 lanes_needed = 4; 2926 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) { 2927 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB; 2928 sig_mode = BNXT_SIG_MODE_PAM4; 2929 lanes_needed = 2; 2930 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4) && 2931 lanes != 1) { 2932 fw_speed = BNXT_LINK_SPEED_100GB_PAM4; 2933 sig_mode = BNXT_SIG_MODE_PAM4; 2934 lanes_needed = 2; 2935 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112) { 2936 fw_speed = BNXT_LINK_SPEED_100GB_PAM4_112; 2937 sig_mode = BNXT_SIG_MODE_PAM4_112; 2938 } 2939 break; 2940 case SPEED_200000: 2941 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) { 2942 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB; 2943 sig_mode = BNXT_SIG_MODE_PAM4; 2944 lanes_needed = 4; 2945 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4) && 2946 lanes != 2) { 2947 fw_speed = BNXT_LINK_SPEED_200GB_PAM4; 2948 sig_mode = BNXT_SIG_MODE_PAM4; 2949 lanes_needed = 4; 2950 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112) { 2951 fw_speed = BNXT_LINK_SPEED_200GB_PAM4_112; 2952 sig_mode = BNXT_SIG_MODE_PAM4_112; 2953 lanes_needed = 2; 2954 } 2955 break; 2956 case SPEED_400000: 2957 if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4) && 2958 lanes != 4) { 2959 fw_speed = BNXT_LINK_SPEED_400GB_PAM4; 2960 sig_mode = BNXT_SIG_MODE_PAM4; 2961 lanes_needed = 8; 2962 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112) { 2963 fw_speed = BNXT_LINK_SPEED_400GB_PAM4_112; 2964 sig_mode = BNXT_SIG_MODE_PAM4_112; 2965 lanes_needed = 4; 2966 } 2967 break; 2968 } 2969 2970 if (!fw_speed) { 2971 netdev_err(dev, "unsupported speed!\n"); 2972 return -EINVAL; 2973 } 2974 2975 if (lanes && lanes != lanes_needed) { 2976 netdev_err(dev, "unsupported number of lanes for speed\n"); 2977 return -EINVAL; 2978 } 2979 2980 if (link_info->req_link_speed == fw_speed && 2981 link_info->req_signal_mode == sig_mode && 2982 link_info->autoneg == 0) 2983 return -EALREADY; 2984 2985 link_info->req_link_speed = fw_speed; 2986 link_info->req_signal_mode = sig_mode; 2987 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 2988 link_info->autoneg = 0; 2989 link_info->advertising = 0; 2990 link_info->advertising_pam4 = 0; 2991 2992 return 0; 2993 } 2994 2995 u16 bnxt_get_fw_auto_link_speeds(const unsigned long *mode) 2996 { 2997 u16 fw_speed_mask = 0; 2998 2999 if (linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode) || 3000 linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mode)) 3001 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 3002 3003 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode) || 3004 linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, mode)) 3005 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 3006 3007 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode)) 3008 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 3009 3010 if (linkmode_test_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode)) 3011 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 3012 3013 return fw_speed_mask; 3014 } 3015 3016 static int bnxt_set_link_ksettings(struct net_device *dev, 3017 const struct ethtool_link_ksettings *lk_ksettings) 3018 { 3019 const struct ethtool_link_settings_hdr *base = &lk_ksettings->base; 3020 struct bnxt *bp = netdev_priv(dev); 3021 struct bnxt_link_info *link_info = &bp->link_info; 3022 bool set_pause = false; 3023 u32 speed, lanes = 0; 3024 int rc = 0; 3025 3026 if (!BNXT_PHY_CFG_ABLE(bp)) 3027 return -EOPNOTSUPP; 3028 3029 mutex_lock(&bp->link_lock); 3030 if (base->autoneg == AUTONEG_ENABLE) { 3031 bnxt_set_ethtool_speeds(link_info, 3032 lk_ksettings->link_modes.advertising); 3033 link_info->autoneg |= BNXT_AUTONEG_SPEED; 3034 if (!link_info->advertising && !link_info->advertising_pam4) { 3035 link_info->advertising = link_info->support_auto_speeds; 3036 link_info->advertising_pam4 = 3037 link_info->support_pam4_auto_speeds; 3038 } 3039 /* any change to autoneg will cause link change, therefore the 3040 * driver should put back the original pause setting in autoneg 3041 */ 3042 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 3043 set_pause = true; 3044 } else { 3045 u8 phy_type = link_info->phy_type; 3046 3047 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 3048 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 3049 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 3050 netdev_err(dev, "10GBase-T devices must autoneg\n"); 3051 rc = -EINVAL; 3052 goto set_setting_exit; 3053 } 3054 if (base->duplex == DUPLEX_HALF) { 3055 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 3056 rc = -EINVAL; 3057 goto set_setting_exit; 3058 } 3059 speed = base->speed; 3060 lanes = lk_ksettings->lanes; 3061 rc = bnxt_force_link_speed(dev, speed, lanes); 3062 if (rc) { 3063 if (rc == -EALREADY) 3064 rc = 0; 3065 goto set_setting_exit; 3066 } 3067 } 3068 3069 if (netif_running(dev)) 3070 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 3071 3072 set_setting_exit: 3073 mutex_unlock(&bp->link_lock); 3074 return rc; 3075 } 3076 3077 static int bnxt_get_fecparam(struct net_device *dev, 3078 struct ethtool_fecparam *fec) 3079 { 3080 struct bnxt *bp = netdev_priv(dev); 3081 struct bnxt_link_info *link_info; 3082 u8 active_fec; 3083 u16 fec_cfg; 3084 3085 link_info = &bp->link_info; 3086 fec_cfg = link_info->fec_cfg; 3087 active_fec = link_info->active_fec_sig_mode & 3088 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK; 3089 if (fec_cfg & BNXT_FEC_NONE) { 3090 fec->fec = ETHTOOL_FEC_NONE; 3091 fec->active_fec = ETHTOOL_FEC_NONE; 3092 return 0; 3093 } 3094 if (fec_cfg & BNXT_FEC_AUTONEG) 3095 fec->fec |= ETHTOOL_FEC_AUTO; 3096 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 3097 fec->fec |= ETHTOOL_FEC_BASER; 3098 if (fec_cfg & BNXT_FEC_ENC_RS) 3099 fec->fec |= ETHTOOL_FEC_RS; 3100 if (fec_cfg & BNXT_FEC_ENC_LLRS) 3101 fec->fec |= ETHTOOL_FEC_LLRS; 3102 3103 switch (active_fec) { 3104 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE: 3105 fec->active_fec |= ETHTOOL_FEC_BASER; 3106 break; 3107 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE: 3108 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE: 3109 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE: 3110 fec->active_fec |= ETHTOOL_FEC_RS; 3111 break; 3112 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE: 3113 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE: 3114 fec->active_fec |= ETHTOOL_FEC_LLRS; 3115 break; 3116 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE: 3117 fec->active_fec |= ETHTOOL_FEC_OFF; 3118 break; 3119 } 3120 return 0; 3121 } 3122 3123 static void bnxt_get_fec_stats(struct net_device *dev, 3124 struct ethtool_fec_stats *fec_stats) 3125 { 3126 struct bnxt *bp = netdev_priv(dev); 3127 u64 *rx; 3128 3129 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 3130 return; 3131 3132 rx = bp->rx_port_stats_ext.sw_stats; 3133 fec_stats->corrected_bits.total = 3134 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits)); 3135 3136 if (bp->fw_rx_stats_ext_size <= BNXT_RX_STATS_EXT_NUM_LEGACY) 3137 return; 3138 3139 fec_stats->corrected_blocks.total = 3140 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)); 3141 fec_stats->uncorrectable_blocks.total = 3142 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_uncorrectable_blocks)); 3143 } 3144 3145 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info, 3146 u32 fec) 3147 { 3148 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE; 3149 3150 if (fec & ETHTOOL_FEC_BASER) 3151 fw_fec |= BNXT_FEC_BASE_R_ON(link_info); 3152 else if (fec & ETHTOOL_FEC_RS) 3153 fw_fec |= BNXT_FEC_RS_ON(link_info); 3154 else if (fec & ETHTOOL_FEC_LLRS) 3155 fw_fec |= BNXT_FEC_LLRS_ON; 3156 return fw_fec; 3157 } 3158 3159 static int bnxt_set_fecparam(struct net_device *dev, 3160 struct ethtool_fecparam *fecparam) 3161 { 3162 struct hwrm_port_phy_cfg_input *req; 3163 struct bnxt *bp = netdev_priv(dev); 3164 struct bnxt_link_info *link_info; 3165 u32 new_cfg, fec = fecparam->fec; 3166 u16 fec_cfg; 3167 int rc; 3168 3169 link_info = &bp->link_info; 3170 fec_cfg = link_info->fec_cfg; 3171 if (fec_cfg & BNXT_FEC_NONE) 3172 return -EOPNOTSUPP; 3173 3174 if (fec & ETHTOOL_FEC_OFF) { 3175 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE | 3176 BNXT_FEC_ALL_OFF(link_info); 3177 goto apply_fec; 3178 } 3179 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) || 3180 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) || 3181 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) || 3182 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP))) 3183 return -EINVAL; 3184 3185 if (fec & ETHTOOL_FEC_AUTO) { 3186 if (!link_info->autoneg) 3187 return -EINVAL; 3188 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE; 3189 } else { 3190 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec); 3191 } 3192 3193 apply_fec: 3194 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 3195 if (rc) 3196 return rc; 3197 req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 3198 rc = hwrm_req_send(bp, req); 3199 /* update current settings */ 3200 if (!rc) { 3201 mutex_lock(&bp->link_lock); 3202 bnxt_update_link(bp, false); 3203 mutex_unlock(&bp->link_lock); 3204 } 3205 return rc; 3206 } 3207 3208 static void bnxt_get_pauseparam(struct net_device *dev, 3209 struct ethtool_pauseparam *epause) 3210 { 3211 struct bnxt *bp = netdev_priv(dev); 3212 struct bnxt_link_info *link_info = &bp->link_info; 3213 3214 if (BNXT_VF(bp)) 3215 return; 3216 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 3217 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 3218 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 3219 } 3220 3221 static void bnxt_get_pause_stats(struct net_device *dev, 3222 struct ethtool_pause_stats *epstat) 3223 { 3224 struct bnxt *bp = netdev_priv(dev); 3225 u64 *rx, *tx; 3226 3227 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 3228 return; 3229 3230 rx = bp->port_stats.sw_stats; 3231 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 3232 3233 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames); 3234 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames); 3235 } 3236 3237 static int bnxt_set_pauseparam(struct net_device *dev, 3238 struct ethtool_pauseparam *epause) 3239 { 3240 int rc = 0; 3241 struct bnxt *bp = netdev_priv(dev); 3242 struct bnxt_link_info *link_info = &bp->link_info; 3243 3244 if (!BNXT_PHY_CFG_ABLE(bp) || (bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 3245 return -EOPNOTSUPP; 3246 3247 mutex_lock(&bp->link_lock); 3248 if (epause->autoneg) { 3249 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 3250 rc = -EINVAL; 3251 goto pause_exit; 3252 } 3253 3254 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 3255 link_info->req_flow_ctrl = 0; 3256 } else { 3257 /* when transition from auto pause to force pause, 3258 * force a link change 3259 */ 3260 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 3261 link_info->force_link_chng = true; 3262 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 3263 link_info->req_flow_ctrl = 0; 3264 } 3265 if (epause->rx_pause) 3266 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 3267 3268 if (epause->tx_pause) 3269 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 3270 3271 if (netif_running(dev)) 3272 rc = bnxt_hwrm_set_pause(bp); 3273 3274 pause_exit: 3275 mutex_unlock(&bp->link_lock); 3276 return rc; 3277 } 3278 3279 static u32 bnxt_get_link(struct net_device *dev) 3280 { 3281 struct bnxt *bp = netdev_priv(dev); 3282 3283 /* TODO: handle MF, VF, driver close case */ 3284 return BNXT_LINK_IS_UP(bp); 3285 } 3286 3287 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp, 3288 struct hwrm_nvm_get_dev_info_output *nvm_dev_info) 3289 { 3290 struct hwrm_nvm_get_dev_info_output *resp; 3291 struct hwrm_nvm_get_dev_info_input *req; 3292 int rc; 3293 3294 if (BNXT_VF(bp)) 3295 return -EOPNOTSUPP; 3296 3297 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO); 3298 if (rc) 3299 return rc; 3300 3301 resp = hwrm_req_hold(bp, req); 3302 rc = hwrm_req_send(bp, req); 3303 if (!rc) 3304 memcpy(nvm_dev_info, resp, sizeof(*resp)); 3305 hwrm_req_drop(bp, req); 3306 return rc; 3307 } 3308 3309 static void bnxt_print_admin_err(struct bnxt *bp) 3310 { 3311 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 3312 } 3313 3314 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 3315 u16 ext, u16 *index, u32 *item_length, 3316 u32 *data_length); 3317 3318 int bnxt_flash_nvram(struct net_device *dev, u16 dir_type, 3319 u16 dir_ordinal, u16 dir_ext, u16 dir_attr, 3320 u32 dir_item_len, const u8 *data, 3321 size_t data_len) 3322 { 3323 struct bnxt *bp = netdev_priv(dev); 3324 struct hwrm_nvm_write_input *req; 3325 int rc; 3326 3327 rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE); 3328 if (rc) 3329 return rc; 3330 3331 if (data_len && data) { 3332 dma_addr_t dma_handle; 3333 u8 *kmem; 3334 3335 kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle); 3336 if (!kmem) { 3337 hwrm_req_drop(bp, req); 3338 return -ENOMEM; 3339 } 3340 3341 req->dir_data_length = cpu_to_le32(data_len); 3342 3343 memcpy(kmem, data, data_len); 3344 req->host_src_addr = cpu_to_le64(dma_handle); 3345 } 3346 3347 hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout); 3348 req->dir_type = cpu_to_le16(dir_type); 3349 req->dir_ordinal = cpu_to_le16(dir_ordinal); 3350 req->dir_ext = cpu_to_le16(dir_ext); 3351 req->dir_attr = cpu_to_le16(dir_attr); 3352 req->dir_item_length = cpu_to_le32(dir_item_len); 3353 rc = hwrm_req_send(bp, req); 3354 3355 if (rc == -EACCES) 3356 bnxt_print_admin_err(bp); 3357 return rc; 3358 } 3359 3360 int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type, 3361 u8 self_reset, u8 flags) 3362 { 3363 struct bnxt *bp = netdev_priv(dev); 3364 struct hwrm_fw_reset_input *req; 3365 int rc; 3366 3367 if (!bnxt_hwrm_reset_permitted(bp)) { 3368 netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver"); 3369 return -EPERM; 3370 } 3371 3372 rc = hwrm_req_init(bp, req, HWRM_FW_RESET); 3373 if (rc) 3374 return rc; 3375 3376 req->embedded_proc_type = proc_type; 3377 req->selfrst_status = self_reset; 3378 req->flags = flags; 3379 3380 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) { 3381 rc = hwrm_req_send_silent(bp, req); 3382 } else { 3383 rc = hwrm_req_send(bp, req); 3384 if (rc == -EACCES) 3385 bnxt_print_admin_err(bp); 3386 } 3387 return rc; 3388 } 3389 3390 static int bnxt_firmware_reset(struct net_device *dev, 3391 enum bnxt_nvm_directory_type dir_type) 3392 { 3393 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE; 3394 u8 proc_type, flags = 0; 3395 3396 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 3397 /* (e.g. when firmware isn't already running) */ 3398 switch (dir_type) { 3399 case BNX_DIR_TYPE_CHIMP_PATCH: 3400 case BNX_DIR_TYPE_BOOTCODE: 3401 case BNX_DIR_TYPE_BOOTCODE_2: 3402 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 3403 /* Self-reset ChiMP upon next PCIe reset: */ 3404 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 3405 break; 3406 case BNX_DIR_TYPE_APE_FW: 3407 case BNX_DIR_TYPE_APE_PATCH: 3408 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 3409 /* Self-reset APE upon next PCIe reset: */ 3410 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 3411 break; 3412 case BNX_DIR_TYPE_KONG_FW: 3413 case BNX_DIR_TYPE_KONG_PATCH: 3414 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 3415 break; 3416 case BNX_DIR_TYPE_BONO_FW: 3417 case BNX_DIR_TYPE_BONO_PATCH: 3418 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 3419 break; 3420 default: 3421 return -EINVAL; 3422 } 3423 3424 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags); 3425 } 3426 3427 static int bnxt_firmware_reset_chip(struct net_device *dev) 3428 { 3429 struct bnxt *bp = netdev_priv(dev); 3430 u8 flags = 0; 3431 3432 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 3433 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 3434 3435 return bnxt_hwrm_firmware_reset(dev, 3436 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP, 3437 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP, 3438 flags); 3439 } 3440 3441 static int bnxt_firmware_reset_ap(struct net_device *dev) 3442 { 3443 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP, 3444 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE, 3445 0); 3446 } 3447 3448 static int bnxt_flash_firmware(struct net_device *dev, 3449 u16 dir_type, 3450 const u8 *fw_data, 3451 size_t fw_size) 3452 { 3453 int rc = 0; 3454 u16 code_type; 3455 u32 stored_crc; 3456 u32 calculated_crc; 3457 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 3458 3459 switch (dir_type) { 3460 case BNX_DIR_TYPE_BOOTCODE: 3461 case BNX_DIR_TYPE_BOOTCODE_2: 3462 code_type = CODE_BOOT; 3463 break; 3464 case BNX_DIR_TYPE_CHIMP_PATCH: 3465 code_type = CODE_CHIMP_PATCH; 3466 break; 3467 case BNX_DIR_TYPE_APE_FW: 3468 code_type = CODE_MCTP_PASSTHRU; 3469 break; 3470 case BNX_DIR_TYPE_APE_PATCH: 3471 code_type = CODE_APE_PATCH; 3472 break; 3473 case BNX_DIR_TYPE_KONG_FW: 3474 code_type = CODE_KONG_FW; 3475 break; 3476 case BNX_DIR_TYPE_KONG_PATCH: 3477 code_type = CODE_KONG_PATCH; 3478 break; 3479 case BNX_DIR_TYPE_BONO_FW: 3480 code_type = CODE_BONO_FW; 3481 break; 3482 case BNX_DIR_TYPE_BONO_PATCH: 3483 code_type = CODE_BONO_PATCH; 3484 break; 3485 default: 3486 netdev_err(dev, "Unsupported directory entry type: %u\n", 3487 dir_type); 3488 return -EINVAL; 3489 } 3490 if (fw_size < sizeof(struct bnxt_fw_header)) { 3491 netdev_err(dev, "Invalid firmware file size: %u\n", 3492 (unsigned int)fw_size); 3493 return -EINVAL; 3494 } 3495 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 3496 netdev_err(dev, "Invalid firmware signature: %08X\n", 3497 le32_to_cpu(header->signature)); 3498 return -EINVAL; 3499 } 3500 if (header->code_type != code_type) { 3501 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 3502 code_type, header->code_type); 3503 return -EINVAL; 3504 } 3505 if (header->device != DEVICE_CUMULUS_FAMILY) { 3506 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 3507 DEVICE_CUMULUS_FAMILY, header->device); 3508 return -EINVAL; 3509 } 3510 /* Confirm the CRC32 checksum of the file: */ 3511 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 3512 sizeof(stored_crc))); 3513 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 3514 if (calculated_crc != stored_crc) { 3515 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 3516 (unsigned long)stored_crc, 3517 (unsigned long)calculated_crc); 3518 return -EINVAL; 3519 } 3520 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3521 0, 0, 0, fw_data, fw_size); 3522 if (rc == 0) /* Firmware update successful */ 3523 rc = bnxt_firmware_reset(dev, dir_type); 3524 3525 return rc; 3526 } 3527 3528 static int bnxt_flash_microcode(struct net_device *dev, 3529 u16 dir_type, 3530 const u8 *fw_data, 3531 size_t fw_size) 3532 { 3533 struct bnxt_ucode_trailer *trailer; 3534 u32 calculated_crc; 3535 u32 stored_crc; 3536 int rc = 0; 3537 3538 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 3539 netdev_err(dev, "Invalid microcode file size: %u\n", 3540 (unsigned int)fw_size); 3541 return -EINVAL; 3542 } 3543 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 3544 sizeof(*trailer))); 3545 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 3546 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 3547 le32_to_cpu(trailer->sig)); 3548 return -EINVAL; 3549 } 3550 if (le16_to_cpu(trailer->dir_type) != dir_type) { 3551 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 3552 dir_type, le16_to_cpu(trailer->dir_type)); 3553 return -EINVAL; 3554 } 3555 if (le16_to_cpu(trailer->trailer_length) < 3556 sizeof(struct bnxt_ucode_trailer)) { 3557 netdev_err(dev, "Invalid microcode trailer length: %d\n", 3558 le16_to_cpu(trailer->trailer_length)); 3559 return -EINVAL; 3560 } 3561 3562 /* Confirm the CRC32 checksum of the file: */ 3563 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 3564 sizeof(stored_crc))); 3565 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 3566 if (calculated_crc != stored_crc) { 3567 netdev_err(dev, 3568 "CRC32 (%08lX) does not match calculated: %08lX\n", 3569 (unsigned long)stored_crc, 3570 (unsigned long)calculated_crc); 3571 return -EINVAL; 3572 } 3573 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3574 0, 0, 0, fw_data, fw_size); 3575 3576 return rc; 3577 } 3578 3579 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 3580 { 3581 switch (dir_type) { 3582 case BNX_DIR_TYPE_CHIMP_PATCH: 3583 case BNX_DIR_TYPE_BOOTCODE: 3584 case BNX_DIR_TYPE_BOOTCODE_2: 3585 case BNX_DIR_TYPE_APE_FW: 3586 case BNX_DIR_TYPE_APE_PATCH: 3587 case BNX_DIR_TYPE_KONG_FW: 3588 case BNX_DIR_TYPE_KONG_PATCH: 3589 case BNX_DIR_TYPE_BONO_FW: 3590 case BNX_DIR_TYPE_BONO_PATCH: 3591 return true; 3592 } 3593 3594 return false; 3595 } 3596 3597 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 3598 { 3599 switch (dir_type) { 3600 case BNX_DIR_TYPE_AVS: 3601 case BNX_DIR_TYPE_EXP_ROM_MBA: 3602 case BNX_DIR_TYPE_PCIE: 3603 case BNX_DIR_TYPE_TSCF_UCODE: 3604 case BNX_DIR_TYPE_EXT_PHY: 3605 case BNX_DIR_TYPE_CCM: 3606 case BNX_DIR_TYPE_ISCSI_BOOT: 3607 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 3608 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 3609 return true; 3610 } 3611 3612 return false; 3613 } 3614 3615 static bool bnxt_dir_type_is_executable(u16 dir_type) 3616 { 3617 return bnxt_dir_type_is_ape_bin_format(dir_type) || 3618 bnxt_dir_type_is_other_exec_format(dir_type); 3619 } 3620 3621 static int bnxt_flash_firmware_from_file(struct net_device *dev, 3622 u16 dir_type, 3623 const char *filename) 3624 { 3625 const struct firmware *fw; 3626 int rc; 3627 3628 rc = request_firmware(&fw, filename, &dev->dev); 3629 if (rc != 0) { 3630 netdev_err(dev, "Error %d requesting firmware file: %s\n", 3631 rc, filename); 3632 return rc; 3633 } 3634 if (bnxt_dir_type_is_ape_bin_format(dir_type)) 3635 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 3636 else if (bnxt_dir_type_is_other_exec_format(dir_type)) 3637 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 3638 else 3639 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3640 0, 0, 0, fw->data, fw->size); 3641 release_firmware(fw); 3642 return rc; 3643 } 3644 3645 #define MSG_INTEGRITY_ERR "PKG install error : Data integrity on NVM" 3646 #define MSG_INVALID_PKG "PKG install error : Invalid package" 3647 #define MSG_AUTHENTICATION_ERR "PKG install error : Authentication error" 3648 #define MSG_INVALID_DEV "PKG install error : Invalid device" 3649 #define MSG_INTERNAL_ERR "PKG install error : Internal error" 3650 #define MSG_NO_PKG_UPDATE_AREA_ERR "PKG update area not created in nvram" 3651 #define MSG_NO_SPACE_ERR "PKG insufficient update area in nvram" 3652 #define MSG_RESIZE_UPDATE_ERR "Resize UPDATE entry error" 3653 #define MSG_ANTI_ROLLBACK_ERR "HWRM_NVM_INSTALL_UPDATE failure due to Anti-rollback detected" 3654 #define MSG_GENERIC_FAILURE_ERR "HWRM_NVM_INSTALL_UPDATE failure" 3655 3656 static int nvm_update_err_to_stderr(struct net_device *dev, u8 result, 3657 struct netlink_ext_ack *extack) 3658 { 3659 switch (result) { 3660 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER: 3661 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER: 3662 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR: 3663 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR: 3664 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND: 3665 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED: 3666 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTEGRITY_ERR); 3667 return -EINVAL; 3668 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE: 3669 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER: 3670 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE: 3671 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM: 3672 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH: 3673 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST: 3674 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER: 3675 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM: 3676 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM: 3677 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH: 3678 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE: 3679 case NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM: 3680 case NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM: 3681 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_PKG); 3682 return -ENOPKG; 3683 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR: 3684 BNXT_NVM_ERR_MSG(dev, extack, MSG_AUTHENTICATION_ERR); 3685 return -EPERM; 3686 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV: 3687 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID: 3688 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR: 3689 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID: 3690 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM: 3691 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_DEV); 3692 return -EOPNOTSUPP; 3693 default: 3694 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTERNAL_ERR); 3695 return -EIO; 3696 } 3697 } 3698 3699 #define BNXT_PKG_DMA_SIZE 0x40000 3700 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE)) 3701 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST)) 3702 3703 static int bnxt_resize_update_entry(struct net_device *dev, size_t fw_size, 3704 struct netlink_ext_ack *extack) 3705 { 3706 u32 item_len; 3707 int rc; 3708 3709 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 3710 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, NULL, 3711 &item_len, NULL); 3712 if (rc) { 3713 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 3714 return rc; 3715 } 3716 3717 if (fw_size > item_len) { 3718 rc = bnxt_flash_nvram(dev, BNX_DIR_TYPE_UPDATE, 3719 BNX_DIR_ORDINAL_FIRST, 0, 1, 3720 round_up(fw_size, 4096), NULL, 0); 3721 if (rc) { 3722 BNXT_NVM_ERR_MSG(dev, extack, MSG_RESIZE_UPDATE_ERR); 3723 return rc; 3724 } 3725 } 3726 return 0; 3727 } 3728 3729 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw, 3730 u32 install_type, struct netlink_ext_ack *extack) 3731 { 3732 struct hwrm_nvm_install_update_input *install; 3733 struct hwrm_nvm_install_update_output *resp; 3734 struct hwrm_nvm_modify_input *modify; 3735 struct bnxt *bp = netdev_priv(dev); 3736 bool defrag_attempted = false; 3737 dma_addr_t dma_handle; 3738 u8 *kmem = NULL; 3739 u32 modify_len; 3740 u32 item_len; 3741 u8 cmd_err; 3742 u16 index; 3743 int rc; 3744 3745 /* resize before flashing larger image than available space */ 3746 rc = bnxt_resize_update_entry(dev, fw->size, extack); 3747 if (rc) 3748 return rc; 3749 3750 bnxt_hwrm_fw_set_time(bp); 3751 3752 rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY); 3753 if (rc) 3754 return rc; 3755 3756 /* Try allocating a large DMA buffer first. Older fw will 3757 * cause excessive NVRAM erases when using small blocks. 3758 */ 3759 modify_len = roundup_pow_of_two(fw->size); 3760 modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE); 3761 while (1) { 3762 kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle); 3763 if (!kmem && modify_len > PAGE_SIZE) 3764 modify_len /= 2; 3765 else 3766 break; 3767 } 3768 if (!kmem) { 3769 hwrm_req_drop(bp, modify); 3770 return -ENOMEM; 3771 } 3772 3773 rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE); 3774 if (rc) { 3775 hwrm_req_drop(bp, modify); 3776 return rc; 3777 } 3778 3779 hwrm_req_timeout(bp, modify, bp->hwrm_cmd_max_timeout); 3780 hwrm_req_timeout(bp, install, bp->hwrm_cmd_max_timeout); 3781 3782 hwrm_req_hold(bp, modify); 3783 modify->host_src_addr = cpu_to_le64(dma_handle); 3784 3785 resp = hwrm_req_hold(bp, install); 3786 if ((install_type & 0xffff) == 0) 3787 install_type >>= 16; 3788 install->install_type = cpu_to_le32(install_type); 3789 3790 do { 3791 u32 copied = 0, len = modify_len; 3792 3793 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 3794 BNX_DIR_ORDINAL_FIRST, 3795 BNX_DIR_EXT_NONE, 3796 &index, &item_len, NULL); 3797 if (rc) { 3798 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 3799 break; 3800 } 3801 if (fw->size > item_len) { 3802 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_SPACE_ERR); 3803 rc = -EFBIG; 3804 break; 3805 } 3806 3807 modify->dir_idx = cpu_to_le16(index); 3808 3809 if (fw->size > modify_len) 3810 modify->flags = BNXT_NVM_MORE_FLAG; 3811 while (copied < fw->size) { 3812 u32 balance = fw->size - copied; 3813 3814 if (balance <= modify_len) { 3815 len = balance; 3816 if (copied) 3817 modify->flags |= BNXT_NVM_LAST_FLAG; 3818 } 3819 memcpy(kmem, fw->data + copied, len); 3820 modify->len = cpu_to_le32(len); 3821 modify->offset = cpu_to_le32(copied); 3822 rc = hwrm_req_send(bp, modify); 3823 if (rc) 3824 goto pkg_abort; 3825 copied += len; 3826 } 3827 3828 rc = hwrm_req_send_silent(bp, install); 3829 if (!rc) 3830 break; 3831 3832 if (defrag_attempted) { 3833 /* We have tried to defragment already in the previous 3834 * iteration. Return with the result for INSTALL_UPDATE 3835 */ 3836 break; 3837 } 3838 3839 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 3840 3841 switch (cmd_err) { 3842 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK: 3843 BNXT_NVM_ERR_MSG(dev, extack, MSG_ANTI_ROLLBACK_ERR); 3844 rc = -EALREADY; 3845 break; 3846 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR: 3847 install->flags = 3848 cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 3849 3850 rc = hwrm_req_send_silent(bp, install); 3851 if (!rc) 3852 break; 3853 3854 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 3855 3856 if (cmd_err == NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) { 3857 /* FW has cleared NVM area, driver will create 3858 * UPDATE directory and try the flash again 3859 */ 3860 defrag_attempted = true; 3861 install->flags = 0; 3862 rc = bnxt_flash_nvram(bp->dev, 3863 BNX_DIR_TYPE_UPDATE, 3864 BNX_DIR_ORDINAL_FIRST, 3865 0, 0, item_len, NULL, 0); 3866 if (!rc) 3867 break; 3868 } 3869 fallthrough; 3870 default: 3871 BNXT_NVM_ERR_MSG(dev, extack, MSG_GENERIC_FAILURE_ERR); 3872 } 3873 } while (defrag_attempted && !rc); 3874 3875 pkg_abort: 3876 hwrm_req_drop(bp, modify); 3877 hwrm_req_drop(bp, install); 3878 3879 if (resp->result) { 3880 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 3881 (s8)resp->result, (int)resp->problem_item); 3882 rc = nvm_update_err_to_stderr(dev, resp->result, extack); 3883 } 3884 if (rc == -EACCES) 3885 bnxt_print_admin_err(bp); 3886 return rc; 3887 } 3888 3889 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename, 3890 u32 install_type, struct netlink_ext_ack *extack) 3891 { 3892 const struct firmware *fw; 3893 int rc; 3894 3895 rc = request_firmware(&fw, filename, &dev->dev); 3896 if (rc != 0) { 3897 netdev_err(dev, "PKG error %d requesting file: %s\n", 3898 rc, filename); 3899 return rc; 3900 } 3901 3902 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type, extack); 3903 3904 release_firmware(fw); 3905 3906 return rc; 3907 } 3908 3909 static int bnxt_flash_device(struct net_device *dev, 3910 struct ethtool_flash *flash) 3911 { 3912 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 3913 netdev_err(dev, "flashdev not supported from a virtual function\n"); 3914 return -EINVAL; 3915 } 3916 3917 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 3918 flash->region > 0xffff) 3919 return bnxt_flash_package_from_file(dev, flash->data, 3920 flash->region, NULL); 3921 3922 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 3923 } 3924 3925 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 3926 { 3927 struct hwrm_nvm_get_dir_info_output *output; 3928 struct hwrm_nvm_get_dir_info_input *req; 3929 struct bnxt *bp = netdev_priv(dev); 3930 int rc; 3931 3932 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO); 3933 if (rc) 3934 return rc; 3935 3936 output = hwrm_req_hold(bp, req); 3937 rc = hwrm_req_send(bp, req); 3938 if (!rc) { 3939 *entries = le32_to_cpu(output->entries); 3940 *length = le32_to_cpu(output->entry_length); 3941 } 3942 hwrm_req_drop(bp, req); 3943 return rc; 3944 } 3945 3946 static int bnxt_get_eeprom_len(struct net_device *dev) 3947 { 3948 struct bnxt *bp = netdev_priv(dev); 3949 3950 if (BNXT_VF(bp)) 3951 return 0; 3952 3953 /* The -1 return value allows the entire 32-bit range of offsets to be 3954 * passed via the ethtool command-line utility. 3955 */ 3956 return -1; 3957 } 3958 3959 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 3960 { 3961 struct bnxt *bp = netdev_priv(dev); 3962 int rc; 3963 u32 dir_entries; 3964 u32 entry_length; 3965 u8 *buf; 3966 size_t buflen; 3967 dma_addr_t dma_handle; 3968 struct hwrm_nvm_get_dir_entries_input *req; 3969 3970 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 3971 if (rc != 0) 3972 return rc; 3973 3974 if (!dir_entries || !entry_length) 3975 return -EIO; 3976 3977 /* Insert 2 bytes of directory info (count and size of entries) */ 3978 if (len < 2) 3979 return -EINVAL; 3980 3981 *data++ = dir_entries; 3982 *data++ = entry_length; 3983 len -= 2; 3984 memset(data, 0xff, len); 3985 3986 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES); 3987 if (rc) 3988 return rc; 3989 3990 buflen = mul_u32_u32(dir_entries, entry_length); 3991 buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle); 3992 if (!buf) { 3993 hwrm_req_drop(bp, req); 3994 return -ENOMEM; 3995 } 3996 req->host_dest_addr = cpu_to_le64(dma_handle); 3997 3998 hwrm_req_hold(bp, req); /* hold the slice */ 3999 rc = hwrm_req_send(bp, req); 4000 if (rc == 0) 4001 memcpy(data, buf, len > buflen ? buflen : len); 4002 hwrm_req_drop(bp, req); 4003 return rc; 4004 } 4005 4006 int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 4007 u32 length, u8 *data) 4008 { 4009 struct bnxt *bp = netdev_priv(dev); 4010 int rc; 4011 u8 *buf; 4012 dma_addr_t dma_handle; 4013 struct hwrm_nvm_read_input *req; 4014 4015 if (!length) 4016 return -EINVAL; 4017 4018 rc = hwrm_req_init(bp, req, HWRM_NVM_READ); 4019 if (rc) 4020 return rc; 4021 4022 buf = hwrm_req_dma_slice(bp, req, length, &dma_handle); 4023 if (!buf) { 4024 hwrm_req_drop(bp, req); 4025 return -ENOMEM; 4026 } 4027 4028 req->host_dest_addr = cpu_to_le64(dma_handle); 4029 req->dir_idx = cpu_to_le16(index); 4030 req->offset = cpu_to_le32(offset); 4031 req->len = cpu_to_le32(length); 4032 4033 hwrm_req_hold(bp, req); /* hold the slice */ 4034 rc = hwrm_req_send(bp, req); 4035 if (rc == 0) 4036 memcpy(data, buf, length); 4037 hwrm_req_drop(bp, req); 4038 return rc; 4039 } 4040 4041 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 4042 u16 ext, u16 *index, u32 *item_length, 4043 u32 *data_length) 4044 { 4045 struct hwrm_nvm_find_dir_entry_output *output; 4046 struct hwrm_nvm_find_dir_entry_input *req; 4047 struct bnxt *bp = netdev_priv(dev); 4048 int rc; 4049 4050 rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY); 4051 if (rc) 4052 return rc; 4053 4054 req->enables = 0; 4055 req->dir_idx = 0; 4056 req->dir_type = cpu_to_le16(type); 4057 req->dir_ordinal = cpu_to_le16(ordinal); 4058 req->dir_ext = cpu_to_le16(ext); 4059 req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 4060 output = hwrm_req_hold(bp, req); 4061 rc = hwrm_req_send_silent(bp, req); 4062 if (rc == 0) { 4063 if (index) 4064 *index = le16_to_cpu(output->dir_idx); 4065 if (item_length) 4066 *item_length = le32_to_cpu(output->dir_item_length); 4067 if (data_length) 4068 *data_length = le32_to_cpu(output->dir_data_length); 4069 } 4070 hwrm_req_drop(bp, req); 4071 return rc; 4072 } 4073 4074 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 4075 { 4076 char *retval = NULL; 4077 char *p; 4078 char *value; 4079 int field = 0; 4080 4081 if (datalen < 1) 4082 return NULL; 4083 /* null-terminate the log data (removing last '\n'): */ 4084 data[datalen - 1] = 0; 4085 for (p = data; *p != 0; p++) { 4086 field = 0; 4087 retval = NULL; 4088 while (*p != 0 && *p != '\n') { 4089 value = p; 4090 while (*p != 0 && *p != '\t' && *p != '\n') 4091 p++; 4092 if (field == desired_field) 4093 retval = value; 4094 if (*p != '\t') 4095 break; 4096 *p = 0; 4097 field++; 4098 p++; 4099 } 4100 if (*p == 0) 4101 break; 4102 *p = 0; 4103 } 4104 return retval; 4105 } 4106 4107 int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size) 4108 { 4109 struct bnxt *bp = netdev_priv(dev); 4110 u16 index = 0; 4111 char *pkgver; 4112 u32 pkglen; 4113 u8 *pkgbuf; 4114 int rc; 4115 4116 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 4117 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 4118 &index, NULL, &pkglen); 4119 if (rc) 4120 return rc; 4121 4122 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 4123 if (!pkgbuf) { 4124 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 4125 pkglen); 4126 return -ENOMEM; 4127 } 4128 4129 rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf); 4130 if (rc) 4131 goto err; 4132 4133 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 4134 pkglen); 4135 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) 4136 strscpy(ver, pkgver, size); 4137 else 4138 rc = -ENOENT; 4139 4140 err: 4141 kfree(pkgbuf); 4142 4143 return rc; 4144 } 4145 4146 static void bnxt_get_pkgver(struct net_device *dev) 4147 { 4148 struct bnxt *bp = netdev_priv(dev); 4149 char buf[FW_VER_STR_LEN]; 4150 int len; 4151 4152 if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) { 4153 len = strlen(bp->fw_ver_str); 4154 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len, 4155 "/pkg %s", buf); 4156 } 4157 } 4158 4159 static int bnxt_get_eeprom(struct net_device *dev, 4160 struct ethtool_eeprom *eeprom, 4161 u8 *data) 4162 { 4163 u32 index; 4164 u32 offset; 4165 4166 if (eeprom->offset == 0) /* special offset value to get directory */ 4167 return bnxt_get_nvram_directory(dev, eeprom->len, data); 4168 4169 index = eeprom->offset >> 24; 4170 offset = eeprom->offset & 0xffffff; 4171 4172 if (index == 0) { 4173 netdev_err(dev, "unsupported index value: %d\n", index); 4174 return -EINVAL; 4175 } 4176 4177 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 4178 } 4179 4180 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 4181 { 4182 struct hwrm_nvm_erase_dir_entry_input *req; 4183 struct bnxt *bp = netdev_priv(dev); 4184 int rc; 4185 4186 rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY); 4187 if (rc) 4188 return rc; 4189 4190 req->dir_idx = cpu_to_le16(index); 4191 return hwrm_req_send(bp, req); 4192 } 4193 4194 static int bnxt_set_eeprom(struct net_device *dev, 4195 struct ethtool_eeprom *eeprom, 4196 u8 *data) 4197 { 4198 struct bnxt *bp = netdev_priv(dev); 4199 u8 index, dir_op; 4200 u16 type, ext, ordinal, attr; 4201 4202 if (!BNXT_PF(bp)) { 4203 netdev_err(dev, "NVM write not supported from a virtual function\n"); 4204 return -EINVAL; 4205 } 4206 4207 type = eeprom->magic >> 16; 4208 4209 if (type == 0xffff) { /* special value for directory operations */ 4210 index = eeprom->magic & 0xff; 4211 dir_op = eeprom->magic >> 8; 4212 if (index == 0) 4213 return -EINVAL; 4214 switch (dir_op) { 4215 case 0x0e: /* erase */ 4216 if (eeprom->offset != ~eeprom->magic) 4217 return -EINVAL; 4218 return bnxt_erase_nvram_directory(dev, index - 1); 4219 default: 4220 return -EINVAL; 4221 } 4222 } 4223 4224 /* Create or re-write an NVM item: */ 4225 if (bnxt_dir_type_is_executable(type)) 4226 return -EOPNOTSUPP; 4227 ext = eeprom->magic & 0xffff; 4228 ordinal = eeprom->offset >> 16; 4229 attr = eeprom->offset & 0xffff; 4230 4231 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data, 4232 eeprom->len); 4233 } 4234 4235 static int bnxt_set_eee(struct net_device *dev, struct ethtool_keee *edata) 4236 { 4237 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 4238 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp); 4239 struct bnxt *bp = netdev_priv(dev); 4240 struct ethtool_keee *eee = &bp->eee; 4241 struct bnxt_link_info *link_info = &bp->link_info; 4242 int rc = 0; 4243 4244 if (!BNXT_PHY_CFG_ABLE(bp)) 4245 return -EOPNOTSUPP; 4246 4247 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 4248 return -EOPNOTSUPP; 4249 4250 mutex_lock(&bp->link_lock); 4251 _bnxt_fw_to_linkmode(advertising, link_info->advertising); 4252 if (!edata->eee_enabled) 4253 goto eee_ok; 4254 4255 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 4256 netdev_warn(dev, "EEE requires autoneg\n"); 4257 rc = -EINVAL; 4258 goto eee_exit; 4259 } 4260 if (edata->tx_lpi_enabled) { 4261 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 4262 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 4263 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 4264 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 4265 rc = -EINVAL; 4266 goto eee_exit; 4267 } else if (!bp->lpi_tmr_hi) { 4268 edata->tx_lpi_timer = eee->tx_lpi_timer; 4269 } 4270 } 4271 if (linkmode_empty(edata->advertised)) { 4272 linkmode_and(edata->advertised, advertising, eee->supported); 4273 } else if (linkmode_andnot(tmp, edata->advertised, advertising)) { 4274 netdev_warn(dev, "EEE advertised must be a subset of autoneg advertised speeds\n"); 4275 rc = -EINVAL; 4276 goto eee_exit; 4277 } 4278 4279 linkmode_copy(eee->advertised, edata->advertised); 4280 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 4281 eee->tx_lpi_timer = edata->tx_lpi_timer; 4282 eee_ok: 4283 eee->eee_enabled = edata->eee_enabled; 4284 4285 if (netif_running(dev)) 4286 rc = bnxt_hwrm_set_link_setting(bp, false, true); 4287 4288 eee_exit: 4289 mutex_unlock(&bp->link_lock); 4290 return rc; 4291 } 4292 4293 static int bnxt_get_eee(struct net_device *dev, struct ethtool_keee *edata) 4294 { 4295 struct bnxt *bp = netdev_priv(dev); 4296 4297 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 4298 return -EOPNOTSUPP; 4299 4300 *edata = bp->eee; 4301 if (!bp->eee.eee_enabled) { 4302 /* Preserve tx_lpi_timer so that the last value will be used 4303 * by default when it is re-enabled. 4304 */ 4305 linkmode_zero(edata->advertised); 4306 edata->tx_lpi_enabled = 0; 4307 } 4308 4309 if (!bp->eee.eee_active) 4310 linkmode_zero(edata->lp_advertised); 4311 4312 return 0; 4313 } 4314 4315 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 4316 u16 page_number, u8 bank, 4317 u16 start_addr, u16 data_length, 4318 u8 *buf) 4319 { 4320 struct hwrm_port_phy_i2c_read_output *output; 4321 struct hwrm_port_phy_i2c_read_input *req; 4322 int rc, byte_offset = 0; 4323 4324 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ); 4325 if (rc) 4326 return rc; 4327 4328 output = hwrm_req_hold(bp, req); 4329 req->i2c_slave_addr = i2c_addr; 4330 req->page_number = cpu_to_le16(page_number); 4331 req->port_id = cpu_to_le16(bp->pf.port_id); 4332 do { 4333 u16 xfer_size; 4334 4335 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 4336 data_length -= xfer_size; 4337 req->page_offset = cpu_to_le16(start_addr + byte_offset); 4338 req->data_length = xfer_size; 4339 req->enables = 4340 cpu_to_le32((start_addr + byte_offset ? 4341 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 4342 0) | 4343 (bank ? 4344 PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER : 4345 0)); 4346 rc = hwrm_req_send(bp, req); 4347 if (!rc) 4348 memcpy(buf + byte_offset, output->data, xfer_size); 4349 byte_offset += xfer_size; 4350 } while (!rc && data_length > 0); 4351 hwrm_req_drop(bp, req); 4352 4353 return rc; 4354 } 4355 4356 static int bnxt_get_module_info(struct net_device *dev, 4357 struct ethtool_modinfo *modinfo) 4358 { 4359 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 4360 struct bnxt *bp = netdev_priv(dev); 4361 int rc; 4362 4363 /* No point in going further if phy status indicates 4364 * module is not inserted or if it is powered down or 4365 * if it is of type 10GBase-T 4366 */ 4367 if (bp->link_info.module_status > 4368 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 4369 return -EOPNOTSUPP; 4370 4371 /* This feature is not supported in older firmware versions */ 4372 if (bp->hwrm_spec_code < 0x10202) 4373 return -EOPNOTSUPP; 4374 4375 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 0, 4376 SFF_DIAG_SUPPORT_OFFSET + 1, 4377 data); 4378 if (!rc) { 4379 u8 module_id = data[0]; 4380 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 4381 4382 switch (module_id) { 4383 case SFF_MODULE_ID_SFP: 4384 modinfo->type = ETH_MODULE_SFF_8472; 4385 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 4386 if (!diag_supported) 4387 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 4388 break; 4389 case SFF_MODULE_ID_QSFP: 4390 case SFF_MODULE_ID_QSFP_PLUS: 4391 modinfo->type = ETH_MODULE_SFF_8436; 4392 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 4393 break; 4394 case SFF_MODULE_ID_QSFP28: 4395 modinfo->type = ETH_MODULE_SFF_8636; 4396 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 4397 break; 4398 default: 4399 rc = -EOPNOTSUPP; 4400 break; 4401 } 4402 } 4403 return rc; 4404 } 4405 4406 static int bnxt_get_module_eeprom(struct net_device *dev, 4407 struct ethtool_eeprom *eeprom, 4408 u8 *data) 4409 { 4410 struct bnxt *bp = netdev_priv(dev); 4411 u16 start = eeprom->offset, length = eeprom->len; 4412 int rc = 0; 4413 4414 memset(data, 0, eeprom->len); 4415 4416 /* Read A0 portion of the EEPROM */ 4417 if (start < ETH_MODULE_SFF_8436_LEN) { 4418 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 4419 length = ETH_MODULE_SFF_8436_LEN - start; 4420 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 4421 start, length, data); 4422 if (rc) 4423 return rc; 4424 start += length; 4425 data += length; 4426 length = eeprom->len - length; 4427 } 4428 4429 /* Read A2 portion of the EEPROM */ 4430 if (length) { 4431 start -= ETH_MODULE_SFF_8436_LEN; 4432 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 0, 4433 start, length, data); 4434 } 4435 return rc; 4436 } 4437 4438 static int bnxt_get_module_status(struct bnxt *bp, struct netlink_ext_ack *extack) 4439 { 4440 if (bp->link_info.module_status <= 4441 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 4442 return 0; 4443 4444 switch (bp->link_info.module_status) { 4445 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 4446 NL_SET_ERR_MSG_MOD(extack, "Transceiver module is powering down"); 4447 break; 4448 case PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED: 4449 NL_SET_ERR_MSG_MOD(extack, "Transceiver module not inserted"); 4450 break; 4451 case PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT: 4452 NL_SET_ERR_MSG_MOD(extack, "Transceiver module disabled due to current fault"); 4453 break; 4454 default: 4455 NL_SET_ERR_MSG_MOD(extack, "Unknown error"); 4456 break; 4457 } 4458 return -EINVAL; 4459 } 4460 4461 static int bnxt_get_module_eeprom_by_page(struct net_device *dev, 4462 const struct ethtool_module_eeprom *page_data, 4463 struct netlink_ext_ack *extack) 4464 { 4465 struct bnxt *bp = netdev_priv(dev); 4466 int rc; 4467 4468 rc = bnxt_get_module_status(bp, extack); 4469 if (rc) 4470 return rc; 4471 4472 if (bp->hwrm_spec_code < 0x10202) { 4473 NL_SET_ERR_MSG_MOD(extack, "Firmware version too old"); 4474 return -EINVAL; 4475 } 4476 4477 if (page_data->bank && !(bp->phy_flags & BNXT_PHY_FL_BANK_SEL)) { 4478 NL_SET_ERR_MSG_MOD(extack, "Firmware not capable for bank selection"); 4479 return -EINVAL; 4480 } 4481 4482 rc = bnxt_read_sfp_module_eeprom_info(bp, page_data->i2c_address << 1, 4483 page_data->page, page_data->bank, 4484 page_data->offset, 4485 page_data->length, 4486 page_data->data); 4487 if (rc) { 4488 NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom read failed"); 4489 return rc; 4490 } 4491 return page_data->length; 4492 } 4493 4494 static int bnxt_nway_reset(struct net_device *dev) 4495 { 4496 int rc = 0; 4497 4498 struct bnxt *bp = netdev_priv(dev); 4499 struct bnxt_link_info *link_info = &bp->link_info; 4500 4501 if (!BNXT_PHY_CFG_ABLE(bp)) 4502 return -EOPNOTSUPP; 4503 4504 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 4505 return -EINVAL; 4506 4507 if (netif_running(dev)) 4508 rc = bnxt_hwrm_set_link_setting(bp, true, false); 4509 4510 return rc; 4511 } 4512 4513 static int bnxt_set_phys_id(struct net_device *dev, 4514 enum ethtool_phys_id_state state) 4515 { 4516 struct hwrm_port_led_cfg_input *req; 4517 struct bnxt *bp = netdev_priv(dev); 4518 struct bnxt_pf_info *pf = &bp->pf; 4519 struct bnxt_led_cfg *led_cfg; 4520 u8 led_state; 4521 __le16 duration; 4522 int rc, i; 4523 4524 if (!bp->num_leds || BNXT_VF(bp)) 4525 return -EOPNOTSUPP; 4526 4527 if (state == ETHTOOL_ID_ACTIVE) { 4528 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 4529 duration = cpu_to_le16(500); 4530 } else if (state == ETHTOOL_ID_INACTIVE) { 4531 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 4532 duration = cpu_to_le16(0); 4533 } else { 4534 return -EINVAL; 4535 } 4536 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG); 4537 if (rc) 4538 return rc; 4539 4540 req->port_id = cpu_to_le16(pf->port_id); 4541 req->num_leds = bp->num_leds; 4542 led_cfg = (struct bnxt_led_cfg *)&req->led0_id; 4543 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 4544 req->enables |= BNXT_LED_DFLT_ENABLES(i); 4545 led_cfg->led_id = bp->leds[i].led_id; 4546 led_cfg->led_state = led_state; 4547 led_cfg->led_blink_on = duration; 4548 led_cfg->led_blink_off = duration; 4549 led_cfg->led_group_id = bp->leds[i].led_group_id; 4550 } 4551 return hwrm_req_send(bp, req); 4552 } 4553 4554 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 4555 { 4556 struct hwrm_selftest_irq_input *req; 4557 int rc; 4558 4559 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ); 4560 if (rc) 4561 return rc; 4562 4563 req->cmpl_ring = cpu_to_le16(cmpl_ring); 4564 return hwrm_req_send(bp, req); 4565 } 4566 4567 static int bnxt_test_irq(struct bnxt *bp) 4568 { 4569 int i; 4570 4571 for (i = 0; i < bp->cp_nr_rings; i++) { 4572 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 4573 int rc; 4574 4575 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 4576 if (rc) 4577 return rc; 4578 } 4579 return 0; 4580 } 4581 4582 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 4583 { 4584 struct hwrm_port_mac_cfg_input *req; 4585 int rc; 4586 4587 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 4588 if (rc) 4589 return rc; 4590 4591 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 4592 if (enable) 4593 req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 4594 else 4595 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 4596 return hwrm_req_send(bp, req); 4597 } 4598 4599 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 4600 { 4601 struct hwrm_port_phy_qcaps_output *resp; 4602 struct hwrm_port_phy_qcaps_input *req; 4603 int rc; 4604 4605 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS); 4606 if (rc) 4607 return rc; 4608 4609 resp = hwrm_req_hold(bp, req); 4610 rc = hwrm_req_send(bp, req); 4611 if (!rc) 4612 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 4613 4614 hwrm_req_drop(bp, req); 4615 return rc; 4616 } 4617 4618 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 4619 struct hwrm_port_phy_cfg_input *req) 4620 { 4621 struct bnxt_link_info *link_info = &bp->link_info; 4622 u16 fw_advertising; 4623 u16 fw_speed; 4624 int rc; 4625 4626 if (!link_info->autoneg || 4627 (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK)) 4628 return 0; 4629 4630 rc = bnxt_query_force_speeds(bp, &fw_advertising); 4631 if (rc) 4632 return rc; 4633 4634 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 4635 if (BNXT_LINK_IS_UP(bp)) 4636 fw_speed = bp->link_info.link_speed; 4637 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 4638 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 4639 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 4640 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 4641 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 4642 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 4643 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 4644 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 4645 4646 req->force_link_speed = cpu_to_le16(fw_speed); 4647 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 4648 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 4649 rc = hwrm_req_send(bp, req); 4650 req->flags = 0; 4651 req->force_link_speed = cpu_to_le16(0); 4652 return rc; 4653 } 4654 4655 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 4656 { 4657 struct hwrm_port_phy_cfg_input *req; 4658 int rc; 4659 4660 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 4661 if (rc) 4662 return rc; 4663 4664 /* prevent bnxt_disable_an_for_lpbk() from consuming the request */ 4665 hwrm_req_hold(bp, req); 4666 4667 if (enable) { 4668 bnxt_disable_an_for_lpbk(bp, req); 4669 if (ext) 4670 req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 4671 else 4672 req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 4673 } else { 4674 req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 4675 } 4676 req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 4677 rc = hwrm_req_send(bp, req); 4678 hwrm_req_drop(bp, req); 4679 return rc; 4680 } 4681 4682 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 4683 u32 raw_cons, int pkt_size) 4684 { 4685 struct bnxt_napi *bnapi = cpr->bnapi; 4686 struct bnxt_rx_ring_info *rxr; 4687 struct bnxt_sw_rx_bd *rx_buf; 4688 struct rx_cmp *rxcmp; 4689 u16 cp_cons, cons; 4690 u8 *data; 4691 u32 len; 4692 int i; 4693 4694 rxr = bnapi->rx_ring; 4695 cp_cons = RING_CMP(raw_cons); 4696 rxcmp = (struct rx_cmp *) 4697 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 4698 cons = rxcmp->rx_cmp_opaque; 4699 rx_buf = &rxr->rx_buf_ring[cons]; 4700 data = rx_buf->data_ptr; 4701 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 4702 if (len != pkt_size) 4703 return -EIO; 4704 i = ETH_ALEN; 4705 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 4706 return -EIO; 4707 i += ETH_ALEN; 4708 for ( ; i < pkt_size; i++) { 4709 if (data[i] != (u8)(i & 0xff)) 4710 return -EIO; 4711 } 4712 return 0; 4713 } 4714 4715 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 4716 int pkt_size) 4717 { 4718 struct tx_cmp *txcmp; 4719 int rc = -EIO; 4720 u32 raw_cons; 4721 u32 cons; 4722 int i; 4723 4724 raw_cons = cpr->cp_raw_cons; 4725 for (i = 0; i < 200; i++) { 4726 cons = RING_CMP(raw_cons); 4727 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 4728 4729 if (!TX_CMP_VALID(txcmp, raw_cons)) { 4730 udelay(5); 4731 continue; 4732 } 4733 4734 /* The valid test of the entry must be done first before 4735 * reading any further. 4736 */ 4737 dma_rmb(); 4738 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP || 4739 TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_V3_CMP) { 4740 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 4741 raw_cons = NEXT_RAW_CMP(raw_cons); 4742 raw_cons = NEXT_RAW_CMP(raw_cons); 4743 break; 4744 } 4745 raw_cons = NEXT_RAW_CMP(raw_cons); 4746 } 4747 cpr->cp_raw_cons = raw_cons; 4748 return rc; 4749 } 4750 4751 static int bnxt_run_loopback(struct bnxt *bp) 4752 { 4753 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 4754 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 4755 struct bnxt_cp_ring_info *cpr; 4756 int pkt_size, i = 0; 4757 struct sk_buff *skb; 4758 dma_addr_t map; 4759 u8 *data; 4760 int rc; 4761 4762 cpr = &rxr->bnapi->cp_ring; 4763 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) 4764 cpr = rxr->rx_cpr; 4765 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh); 4766 skb = netdev_alloc_skb(bp->dev, pkt_size); 4767 if (!skb) 4768 return -ENOMEM; 4769 data = skb_put(skb, pkt_size); 4770 ether_addr_copy(&data[i], bp->dev->dev_addr); 4771 i += ETH_ALEN; 4772 ether_addr_copy(&data[i], bp->dev->dev_addr); 4773 i += ETH_ALEN; 4774 for ( ; i < pkt_size; i++) 4775 data[i] = (u8)(i & 0xff); 4776 4777 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 4778 DMA_TO_DEVICE); 4779 if (dma_mapping_error(&bp->pdev->dev, map)) { 4780 dev_kfree_skb(skb); 4781 return -EIO; 4782 } 4783 bnxt_xmit_bd(bp, txr, map, pkt_size, NULL); 4784 4785 /* Sync BD data before updating doorbell */ 4786 wmb(); 4787 4788 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 4789 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 4790 4791 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE); 4792 dev_kfree_skb(skb); 4793 return rc; 4794 } 4795 4796 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 4797 { 4798 struct hwrm_selftest_exec_output *resp; 4799 struct hwrm_selftest_exec_input *req; 4800 int rc; 4801 4802 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC); 4803 if (rc) 4804 return rc; 4805 4806 hwrm_req_timeout(bp, req, bp->test_info->timeout); 4807 req->flags = test_mask; 4808 4809 resp = hwrm_req_hold(bp, req); 4810 rc = hwrm_req_send(bp, req); 4811 *test_results = resp->test_success; 4812 hwrm_req_drop(bp, req); 4813 return rc; 4814 } 4815 4816 #define BNXT_DRV_TESTS 4 4817 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 4818 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 4819 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 4820 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 4821 4822 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 4823 u64 *buf) 4824 { 4825 struct bnxt *bp = netdev_priv(dev); 4826 bool do_ext_lpbk = false; 4827 bool offline = false; 4828 u8 test_results = 0; 4829 u8 test_mask = 0; 4830 int rc = 0, i; 4831 4832 if (!bp->num_tests || !BNXT_PF(bp)) 4833 return; 4834 4835 if (etest->flags & ETH_TEST_FL_OFFLINE && 4836 bnxt_ulp_registered(bp->edev)) { 4837 etest->flags |= ETH_TEST_FL_FAILED; 4838 netdev_warn(dev, "Offline tests cannot be run with RoCE driver loaded\n"); 4839 return; 4840 } 4841 4842 memset(buf, 0, sizeof(u64) * bp->num_tests); 4843 if (!netif_running(dev)) { 4844 etest->flags |= ETH_TEST_FL_FAILED; 4845 return; 4846 } 4847 4848 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 4849 (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK)) 4850 do_ext_lpbk = true; 4851 4852 if (etest->flags & ETH_TEST_FL_OFFLINE) { 4853 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) { 4854 etest->flags |= ETH_TEST_FL_FAILED; 4855 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n"); 4856 return; 4857 } 4858 offline = true; 4859 } 4860 4861 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 4862 u8 bit_val = 1 << i; 4863 4864 if (!(bp->test_info->offline_mask & bit_val)) 4865 test_mask |= bit_val; 4866 else if (offline) 4867 test_mask |= bit_val; 4868 } 4869 if (!offline) { 4870 bnxt_run_fw_tests(bp, test_mask, &test_results); 4871 } else { 4872 bnxt_close_nic(bp, true, false); 4873 bnxt_run_fw_tests(bp, test_mask, &test_results); 4874 4875 buf[BNXT_MACLPBK_TEST_IDX] = 1; 4876 bnxt_hwrm_mac_loopback(bp, true); 4877 msleep(250); 4878 rc = bnxt_half_open_nic(bp); 4879 if (rc) { 4880 bnxt_hwrm_mac_loopback(bp, false); 4881 etest->flags |= ETH_TEST_FL_FAILED; 4882 return; 4883 } 4884 if (bnxt_run_loopback(bp)) 4885 etest->flags |= ETH_TEST_FL_FAILED; 4886 else 4887 buf[BNXT_MACLPBK_TEST_IDX] = 0; 4888 4889 bnxt_hwrm_mac_loopback(bp, false); 4890 bnxt_hwrm_phy_loopback(bp, true, false); 4891 msleep(1000); 4892 if (bnxt_run_loopback(bp)) { 4893 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 4894 etest->flags |= ETH_TEST_FL_FAILED; 4895 } 4896 if (do_ext_lpbk) { 4897 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 4898 bnxt_hwrm_phy_loopback(bp, true, true); 4899 msleep(1000); 4900 if (bnxt_run_loopback(bp)) { 4901 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 4902 etest->flags |= ETH_TEST_FL_FAILED; 4903 } 4904 } 4905 bnxt_hwrm_phy_loopback(bp, false, false); 4906 bnxt_half_close_nic(bp); 4907 rc = bnxt_open_nic(bp, true, true); 4908 } 4909 if (rc || bnxt_test_irq(bp)) { 4910 buf[BNXT_IRQ_TEST_IDX] = 1; 4911 etest->flags |= ETH_TEST_FL_FAILED; 4912 } 4913 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 4914 u8 bit_val = 1 << i; 4915 4916 if ((test_mask & bit_val) && !(test_results & bit_val)) { 4917 buf[i] = 1; 4918 etest->flags |= ETH_TEST_FL_FAILED; 4919 } 4920 } 4921 } 4922 4923 static int bnxt_reset(struct net_device *dev, u32 *flags) 4924 { 4925 struct bnxt *bp = netdev_priv(dev); 4926 bool reload = false; 4927 u32 req = *flags; 4928 4929 if (!req) 4930 return -EINVAL; 4931 4932 if (!BNXT_PF(bp)) { 4933 netdev_err(dev, "Reset is not supported from a VF\n"); 4934 return -EOPNOTSUPP; 4935 } 4936 4937 if (pci_vfs_assigned(bp->pdev) && 4938 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) { 4939 netdev_err(dev, 4940 "Reset not allowed when VFs are assigned to VMs\n"); 4941 return -EBUSY; 4942 } 4943 4944 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) { 4945 /* This feature is not supported in older firmware versions */ 4946 if (bp->hwrm_spec_code >= 0x10803) { 4947 if (!bnxt_firmware_reset_chip(dev)) { 4948 netdev_info(dev, "Firmware reset request successful.\n"); 4949 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) 4950 reload = true; 4951 *flags &= ~BNXT_FW_RESET_CHIP; 4952 } 4953 } else if (req == BNXT_FW_RESET_CHIP) { 4954 return -EOPNOTSUPP; /* only request, fail hard */ 4955 } 4956 } 4957 4958 if (!BNXT_CHIP_P4_PLUS(bp) && (req & BNXT_FW_RESET_AP)) { 4959 /* This feature is not supported in older firmware versions */ 4960 if (bp->hwrm_spec_code >= 0x10803) { 4961 if (!bnxt_firmware_reset_ap(dev)) { 4962 netdev_info(dev, "Reset application processor successful.\n"); 4963 reload = true; 4964 *flags &= ~BNXT_FW_RESET_AP; 4965 } 4966 } else if (req == BNXT_FW_RESET_AP) { 4967 return -EOPNOTSUPP; /* only request, fail hard */ 4968 } 4969 } 4970 4971 if (reload) 4972 netdev_info(dev, "Reload driver to complete reset\n"); 4973 4974 return 0; 4975 } 4976 4977 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump) 4978 { 4979 struct bnxt *bp = netdev_priv(dev); 4980 4981 if (dump->flag > BNXT_DUMP_CRASH) { 4982 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n"); 4983 return -EINVAL; 4984 } 4985 4986 if (dump->flag == BNXT_DUMP_CRASH) { 4987 if (bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR && 4988 (!IS_ENABLED(CONFIG_TEE_BNXT_FW))) { 4989 netdev_info(dev, 4990 "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n"); 4991 return -EOPNOTSUPP; 4992 } else if (!(bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR)) { 4993 netdev_info(dev, "Crash dump collection from host memory is not supported on this interface.\n"); 4994 return -EOPNOTSUPP; 4995 } 4996 } 4997 4998 bp->dump_flag = dump->flag; 4999 return 0; 5000 } 5001 5002 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 5003 { 5004 struct bnxt *bp = netdev_priv(dev); 5005 5006 if (bp->hwrm_spec_code < 0x10801) 5007 return -EOPNOTSUPP; 5008 5009 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 5010 bp->ver_resp.hwrm_fw_min_8b << 16 | 5011 bp->ver_resp.hwrm_fw_bld_8b << 8 | 5012 bp->ver_resp.hwrm_fw_rsvd_8b; 5013 5014 dump->flag = bp->dump_flag; 5015 dump->len = bnxt_get_coredump_length(bp, bp->dump_flag); 5016 return 0; 5017 } 5018 5019 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 5020 void *buf) 5021 { 5022 struct bnxt *bp = netdev_priv(dev); 5023 5024 if (bp->hwrm_spec_code < 0x10801) 5025 return -EOPNOTSUPP; 5026 5027 memset(buf, 0, dump->len); 5028 5029 dump->flag = bp->dump_flag; 5030 return bnxt_get_coredump(bp, dump->flag, buf, &dump->len); 5031 } 5032 5033 static int bnxt_get_ts_info(struct net_device *dev, 5034 struct kernel_ethtool_ts_info *info) 5035 { 5036 struct bnxt *bp = netdev_priv(dev); 5037 struct bnxt_ptp_cfg *ptp; 5038 5039 ptp = bp->ptp_cfg; 5040 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE; 5041 5042 if (!ptp) 5043 return 0; 5044 5045 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | 5046 SOF_TIMESTAMPING_RX_HARDWARE | 5047 SOF_TIMESTAMPING_RAW_HARDWARE; 5048 if (ptp->ptp_clock) 5049 info->phc_index = ptp_clock_index(ptp->ptp_clock); 5050 5051 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 5052 5053 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 5054 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 5055 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 5056 5057 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) 5058 info->rx_filters |= (1 << HWTSTAMP_FILTER_ALL); 5059 return 0; 5060 } 5061 5062 void bnxt_ethtool_init(struct bnxt *bp) 5063 { 5064 struct hwrm_selftest_qlist_output *resp; 5065 struct hwrm_selftest_qlist_input *req; 5066 struct bnxt_test_info *test_info; 5067 struct net_device *dev = bp->dev; 5068 int i, rc; 5069 5070 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 5071 bnxt_get_pkgver(dev); 5072 5073 bp->num_tests = 0; 5074 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp)) 5075 return; 5076 5077 test_info = bp->test_info; 5078 if (!test_info) { 5079 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL); 5080 if (!test_info) 5081 return; 5082 bp->test_info = test_info; 5083 } 5084 5085 if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST)) 5086 return; 5087 5088 resp = hwrm_req_hold(bp, req); 5089 rc = hwrm_req_send_silent(bp, req); 5090 if (rc) 5091 goto ethtool_init_exit; 5092 5093 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 5094 if (bp->num_tests > BNXT_MAX_TEST) 5095 bp->num_tests = BNXT_MAX_TEST; 5096 5097 test_info->offline_mask = resp->offline_tests; 5098 test_info->timeout = le16_to_cpu(resp->test_timeout); 5099 if (!test_info->timeout) 5100 test_info->timeout = HWRM_CMD_TIMEOUT; 5101 for (i = 0; i < bp->num_tests; i++) { 5102 char *str = test_info->string[i]; 5103 char *fw_str = resp->test_name[i]; 5104 5105 if (i == BNXT_MACLPBK_TEST_IDX) { 5106 strcpy(str, "Mac loopback test (offline)"); 5107 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 5108 strcpy(str, "Phy loopback test (offline)"); 5109 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 5110 strcpy(str, "Ext loopback test (offline)"); 5111 } else if (i == BNXT_IRQ_TEST_IDX) { 5112 strcpy(str, "Interrupt_test (offline)"); 5113 } else { 5114 snprintf(str, ETH_GSTRING_LEN, "%s test (%s)", 5115 fw_str, test_info->offline_mask & (1 << i) ? 5116 "offline" : "online"); 5117 } 5118 } 5119 5120 ethtool_init_exit: 5121 hwrm_req_drop(bp, req); 5122 } 5123 5124 static void bnxt_get_eth_phy_stats(struct net_device *dev, 5125 struct ethtool_eth_phy_stats *phy_stats) 5126 { 5127 struct bnxt *bp = netdev_priv(dev); 5128 u64 *rx; 5129 5130 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 5131 return; 5132 5133 rx = bp->rx_port_stats_ext.sw_stats; 5134 phy_stats->SymbolErrorDuringCarrier = 5135 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err)); 5136 } 5137 5138 static void bnxt_get_eth_mac_stats(struct net_device *dev, 5139 struct ethtool_eth_mac_stats *mac_stats) 5140 { 5141 struct bnxt *bp = netdev_priv(dev); 5142 u64 *rx, *tx; 5143 5144 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5145 return; 5146 5147 rx = bp->port_stats.sw_stats; 5148 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 5149 5150 mac_stats->FramesReceivedOK = 5151 BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames); 5152 mac_stats->FramesTransmittedOK = 5153 BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames); 5154 mac_stats->FrameCheckSequenceErrors = 5155 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames); 5156 mac_stats->AlignmentErrors = 5157 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames); 5158 mac_stats->OutOfRangeLengthField = 5159 BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames); 5160 } 5161 5162 static void bnxt_get_eth_ctrl_stats(struct net_device *dev, 5163 struct ethtool_eth_ctrl_stats *ctrl_stats) 5164 { 5165 struct bnxt *bp = netdev_priv(dev); 5166 u64 *rx; 5167 5168 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5169 return; 5170 5171 rx = bp->port_stats.sw_stats; 5172 ctrl_stats->MACControlFramesReceived = 5173 BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames); 5174 } 5175 5176 static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = { 5177 { 0, 64 }, 5178 { 65, 127 }, 5179 { 128, 255 }, 5180 { 256, 511 }, 5181 { 512, 1023 }, 5182 { 1024, 1518 }, 5183 { 1519, 2047 }, 5184 { 2048, 4095 }, 5185 { 4096, 9216 }, 5186 { 9217, 16383 }, 5187 {} 5188 }; 5189 5190 static void bnxt_get_rmon_stats(struct net_device *dev, 5191 struct ethtool_rmon_stats *rmon_stats, 5192 const struct ethtool_rmon_hist_range **ranges) 5193 { 5194 struct bnxt *bp = netdev_priv(dev); 5195 u64 *rx, *tx; 5196 5197 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5198 return; 5199 5200 rx = bp->port_stats.sw_stats; 5201 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 5202 5203 rmon_stats->jabbers = 5204 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames); 5205 rmon_stats->oversize_pkts = 5206 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames); 5207 rmon_stats->undersize_pkts = 5208 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames); 5209 5210 rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames); 5211 rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames); 5212 rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames); 5213 rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames); 5214 rmon_stats->hist[4] = 5215 BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames); 5216 rmon_stats->hist[5] = 5217 BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames); 5218 rmon_stats->hist[6] = 5219 BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames); 5220 rmon_stats->hist[7] = 5221 BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames); 5222 rmon_stats->hist[8] = 5223 BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames); 5224 rmon_stats->hist[9] = 5225 BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames); 5226 5227 rmon_stats->hist_tx[0] = 5228 BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames); 5229 rmon_stats->hist_tx[1] = 5230 BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames); 5231 rmon_stats->hist_tx[2] = 5232 BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames); 5233 rmon_stats->hist_tx[3] = 5234 BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames); 5235 rmon_stats->hist_tx[4] = 5236 BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames); 5237 rmon_stats->hist_tx[5] = 5238 BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames); 5239 rmon_stats->hist_tx[6] = 5240 BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames); 5241 rmon_stats->hist_tx[7] = 5242 BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames); 5243 rmon_stats->hist_tx[8] = 5244 BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames); 5245 rmon_stats->hist_tx[9] = 5246 BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames); 5247 5248 *ranges = bnxt_rmon_ranges; 5249 } 5250 5251 static void bnxt_get_ptp_stats(struct net_device *dev, 5252 struct ethtool_ts_stats *ts_stats) 5253 { 5254 struct bnxt *bp = netdev_priv(dev); 5255 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 5256 5257 if (ptp) { 5258 ts_stats->pkts = ptp->stats.ts_pkts; 5259 ts_stats->lost = ptp->stats.ts_lost; 5260 ts_stats->err = atomic64_read(&ptp->stats.ts_err); 5261 } 5262 } 5263 5264 static void bnxt_get_link_ext_stats(struct net_device *dev, 5265 struct ethtool_link_ext_stats *stats) 5266 { 5267 struct bnxt *bp = netdev_priv(dev); 5268 u64 *rx; 5269 5270 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 5271 return; 5272 5273 rx = bp->rx_port_stats_ext.sw_stats; 5274 stats->link_down_events = 5275 *(rx + BNXT_RX_STATS_EXT_OFFSET(link_down_events)); 5276 } 5277 5278 void bnxt_ethtool_free(struct bnxt *bp) 5279 { 5280 kfree(bp->test_info); 5281 bp->test_info = NULL; 5282 } 5283 5284 const struct ethtool_ops bnxt_ethtool_ops = { 5285 .cap_link_lanes_supported = 1, 5286 .rxfh_per_ctx_key = 1, 5287 .rxfh_max_num_contexts = BNXT_MAX_ETH_RSS_CTX + 1, 5288 .rxfh_indir_space = BNXT_MAX_RSS_TABLE_ENTRIES_P5, 5289 .rxfh_priv_size = sizeof(struct bnxt_rss_ctx), 5290 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 5291 ETHTOOL_COALESCE_MAX_FRAMES | 5292 ETHTOOL_COALESCE_USECS_IRQ | 5293 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 5294 ETHTOOL_COALESCE_STATS_BLOCK_USECS | 5295 ETHTOOL_COALESCE_USE_ADAPTIVE_RX | 5296 ETHTOOL_COALESCE_USE_CQE, 5297 .get_link_ksettings = bnxt_get_link_ksettings, 5298 .set_link_ksettings = bnxt_set_link_ksettings, 5299 .get_fec_stats = bnxt_get_fec_stats, 5300 .get_fecparam = bnxt_get_fecparam, 5301 .set_fecparam = bnxt_set_fecparam, 5302 .get_pause_stats = bnxt_get_pause_stats, 5303 .get_pauseparam = bnxt_get_pauseparam, 5304 .set_pauseparam = bnxt_set_pauseparam, 5305 .get_drvinfo = bnxt_get_drvinfo, 5306 .get_regs_len = bnxt_get_regs_len, 5307 .get_regs = bnxt_get_regs, 5308 .get_wol = bnxt_get_wol, 5309 .set_wol = bnxt_set_wol, 5310 .get_coalesce = bnxt_get_coalesce, 5311 .set_coalesce = bnxt_set_coalesce, 5312 .get_msglevel = bnxt_get_msglevel, 5313 .set_msglevel = bnxt_set_msglevel, 5314 .get_sset_count = bnxt_get_sset_count, 5315 .get_strings = bnxt_get_strings, 5316 .get_ethtool_stats = bnxt_get_ethtool_stats, 5317 .set_ringparam = bnxt_set_ringparam, 5318 .get_ringparam = bnxt_get_ringparam, 5319 .get_channels = bnxt_get_channels, 5320 .set_channels = bnxt_set_channels, 5321 .get_rxnfc = bnxt_get_rxnfc, 5322 .set_rxnfc = bnxt_set_rxnfc, 5323 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 5324 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 5325 .get_rxfh = bnxt_get_rxfh, 5326 .set_rxfh = bnxt_set_rxfh, 5327 .create_rxfh_context = bnxt_create_rxfh_context, 5328 .modify_rxfh_context = bnxt_modify_rxfh_context, 5329 .remove_rxfh_context = bnxt_remove_rxfh_context, 5330 .flash_device = bnxt_flash_device, 5331 .get_eeprom_len = bnxt_get_eeprom_len, 5332 .get_eeprom = bnxt_get_eeprom, 5333 .set_eeprom = bnxt_set_eeprom, 5334 .get_link = bnxt_get_link, 5335 .get_link_ext_stats = bnxt_get_link_ext_stats, 5336 .get_eee = bnxt_get_eee, 5337 .set_eee = bnxt_set_eee, 5338 .get_module_info = bnxt_get_module_info, 5339 .get_module_eeprom = bnxt_get_module_eeprom, 5340 .get_module_eeprom_by_page = bnxt_get_module_eeprom_by_page, 5341 .nway_reset = bnxt_nway_reset, 5342 .set_phys_id = bnxt_set_phys_id, 5343 .self_test = bnxt_self_test, 5344 .get_ts_info = bnxt_get_ts_info, 5345 .reset = bnxt_reset, 5346 .set_dump = bnxt_set_dump, 5347 .get_dump_flag = bnxt_get_dump_flag, 5348 .get_dump_data = bnxt_get_dump_data, 5349 .get_eth_phy_stats = bnxt_get_eth_phy_stats, 5350 .get_eth_mac_stats = bnxt_get_eth_mac_stats, 5351 .get_eth_ctrl_stats = bnxt_get_eth_ctrl_stats, 5352 .get_rmon_stats = bnxt_get_rmon_stats, 5353 .get_ts_stats = bnxt_get_ptp_stats, 5354 }; 5355