1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/bitops.h> 12 #include <linux/ctype.h> 13 #include <linux/stringify.h> 14 #include <linux/ethtool.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/linkmode.h> 17 #include <linux/interrupt.h> 18 #include <linux/pci.h> 19 #include <linux/etherdevice.h> 20 #include <linux/crc32.h> 21 #include <linux/firmware.h> 22 #include <linux/utsname.h> 23 #include <linux/time.h> 24 #include <linux/ptp_clock_kernel.h> 25 #include <linux/net_tstamp.h> 26 #include <linux/timecounter.h> 27 #include <net/netlink.h> 28 #include "bnxt_hsi.h" 29 #include "bnxt.h" 30 #include "bnxt_hwrm.h" 31 #include "bnxt_ulp.h" 32 #include "bnxt_xdp.h" 33 #include "bnxt_ptp.h" 34 #include "bnxt_ethtool.h" 35 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 36 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 37 #include "bnxt_coredump.h" 38 39 #define BNXT_NVM_ERR_MSG(dev, extack, msg) \ 40 do { \ 41 if (extack) \ 42 NL_SET_ERR_MSG_MOD(extack, msg); \ 43 netdev_err(dev, "%s\n", msg); \ 44 } while (0) 45 46 static u32 bnxt_get_msglevel(struct net_device *dev) 47 { 48 struct bnxt *bp = netdev_priv(dev); 49 50 return bp->msg_enable; 51 } 52 53 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 54 { 55 struct bnxt *bp = netdev_priv(dev); 56 57 bp->msg_enable = value; 58 } 59 60 static int bnxt_get_coalesce(struct net_device *dev, 61 struct ethtool_coalesce *coal, 62 struct kernel_ethtool_coalesce *kernel_coal, 63 struct netlink_ext_ack *extack) 64 { 65 struct bnxt *bp = netdev_priv(dev); 66 struct bnxt_coal *hw_coal; 67 u16 mult; 68 69 memset(coal, 0, sizeof(*coal)); 70 71 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 72 73 hw_coal = &bp->rx_coal; 74 mult = hw_coal->bufs_per_record; 75 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 76 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 77 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 78 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 79 if (hw_coal->flags & 80 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 81 kernel_coal->use_cqe_mode_rx = true; 82 83 hw_coal = &bp->tx_coal; 84 mult = hw_coal->bufs_per_record; 85 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 86 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 87 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 88 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 89 if (hw_coal->flags & 90 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 91 kernel_coal->use_cqe_mode_tx = true; 92 93 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 94 95 return 0; 96 } 97 98 static int bnxt_set_coalesce(struct net_device *dev, 99 struct ethtool_coalesce *coal, 100 struct kernel_ethtool_coalesce *kernel_coal, 101 struct netlink_ext_ack *extack) 102 { 103 struct bnxt *bp = netdev_priv(dev); 104 bool update_stats = false; 105 struct bnxt_coal *hw_coal; 106 int rc = 0; 107 u16 mult; 108 109 if (coal->use_adaptive_rx_coalesce) { 110 bp->flags |= BNXT_FLAG_DIM; 111 } else { 112 if (bp->flags & BNXT_FLAG_DIM) { 113 bp->flags &= ~(BNXT_FLAG_DIM); 114 goto reset_coalesce; 115 } 116 } 117 118 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) && 119 !(bp->coal_cap.cmpl_params & 120 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)) 121 return -EOPNOTSUPP; 122 123 hw_coal = &bp->rx_coal; 124 mult = hw_coal->bufs_per_record; 125 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 126 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 127 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 128 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 129 hw_coal->flags &= 130 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 131 if (kernel_coal->use_cqe_mode_rx) 132 hw_coal->flags |= 133 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 134 135 hw_coal = &bp->tx_coal; 136 mult = hw_coal->bufs_per_record; 137 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 138 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 139 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 140 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 141 hw_coal->flags &= 142 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 143 if (kernel_coal->use_cqe_mode_tx) 144 hw_coal->flags |= 145 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 146 147 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 148 u32 stats_ticks = coal->stats_block_coalesce_usecs; 149 150 /* Allow 0, which means disable. */ 151 if (stats_ticks) 152 stats_ticks = clamp_t(u32, stats_ticks, 153 BNXT_MIN_STATS_COAL_TICKS, 154 BNXT_MAX_STATS_COAL_TICKS); 155 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 156 bp->stats_coal_ticks = stats_ticks; 157 if (bp->stats_coal_ticks) 158 bp->current_interval = 159 bp->stats_coal_ticks * HZ / 1000000; 160 else 161 bp->current_interval = BNXT_TIMER_INTERVAL; 162 update_stats = true; 163 } 164 165 reset_coalesce: 166 if (test_bit(BNXT_STATE_OPEN, &bp->state)) { 167 if (update_stats) { 168 bnxt_close_nic(bp, true, false); 169 rc = bnxt_open_nic(bp, true, false); 170 } else { 171 rc = bnxt_hwrm_set_coal(bp); 172 } 173 } 174 175 return rc; 176 } 177 178 static const char * const bnxt_ring_rx_stats_str[] = { 179 "rx_ucast_packets", 180 "rx_mcast_packets", 181 "rx_bcast_packets", 182 "rx_discards", 183 "rx_errors", 184 "rx_ucast_bytes", 185 "rx_mcast_bytes", 186 "rx_bcast_bytes", 187 }; 188 189 static const char * const bnxt_ring_tx_stats_str[] = { 190 "tx_ucast_packets", 191 "tx_mcast_packets", 192 "tx_bcast_packets", 193 "tx_errors", 194 "tx_discards", 195 "tx_ucast_bytes", 196 "tx_mcast_bytes", 197 "tx_bcast_bytes", 198 }; 199 200 static const char * const bnxt_ring_tpa_stats_str[] = { 201 "tpa_packets", 202 "tpa_bytes", 203 "tpa_events", 204 "tpa_aborts", 205 }; 206 207 static const char * const bnxt_ring_tpa2_stats_str[] = { 208 "rx_tpa_eligible_pkt", 209 "rx_tpa_eligible_bytes", 210 "rx_tpa_pkt", 211 "rx_tpa_bytes", 212 "rx_tpa_errors", 213 "rx_tpa_events", 214 }; 215 216 static const char * const bnxt_rx_sw_stats_str[] = { 217 "rx_l4_csum_errors", 218 "rx_resets", 219 "rx_buf_errors", 220 }; 221 222 static const char * const bnxt_cmn_sw_stats_str[] = { 223 "missed_irqs", 224 }; 225 226 #define BNXT_RX_STATS_ENTRY(counter) \ 227 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 228 229 #define BNXT_TX_STATS_ENTRY(counter) \ 230 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 231 232 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 233 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 234 235 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 236 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 237 238 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 239 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 240 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 241 242 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 243 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 244 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 245 246 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 247 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 248 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 249 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 250 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 251 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 252 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 253 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 254 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 255 256 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 257 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 258 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 259 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 260 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 261 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 262 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 263 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 264 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 265 266 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 267 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 268 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 269 270 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 271 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 272 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 273 274 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 275 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 276 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 277 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 278 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 279 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 280 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 281 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 282 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 283 284 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 285 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 286 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 287 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 288 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 289 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 290 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 291 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 292 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 293 294 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 295 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 296 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 297 298 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 299 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 300 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 301 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 302 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 303 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 304 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 305 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 306 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 307 308 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 309 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 310 __stringify(counter##_pri##n) } 311 312 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 313 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 314 __stringify(counter##_pri##n) } 315 316 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 317 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 318 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 319 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 320 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 321 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 322 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 323 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 324 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 325 326 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 327 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 328 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 329 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 330 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 331 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 332 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 333 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 334 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 335 336 enum { 337 RX_TOTAL_DISCARDS, 338 TX_TOTAL_DISCARDS, 339 RX_NETPOLL_DISCARDS, 340 }; 341 342 static const char *const bnxt_ring_err_stats_arr[] = { 343 "rx_total_l4_csum_errors", 344 "rx_total_resets", 345 "rx_total_buf_errors", 346 "rx_total_oom_discards", 347 "rx_total_netpoll_discards", 348 "rx_total_ring_discards", 349 "tx_total_resets", 350 "tx_total_ring_discards", 351 "total_missed_irqs", 352 }; 353 354 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str) 355 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str) 356 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str) 357 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str) 358 359 static const struct { 360 long offset; 361 char string[ETH_GSTRING_LEN]; 362 } bnxt_port_stats_arr[] = { 363 BNXT_RX_STATS_ENTRY(rx_64b_frames), 364 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 365 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 366 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 367 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 368 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 369 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 370 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 371 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 372 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 373 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 374 BNXT_RX_STATS_ENTRY(rx_total_frames), 375 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 376 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 377 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 378 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 379 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 380 BNXT_RX_STATS_ENTRY(rx_pause_frames), 381 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 382 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 383 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 384 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 385 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 386 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 387 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 388 BNXT_RX_STATS_ENTRY(rx_good_frames), 389 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 390 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 391 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 392 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 393 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 394 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 395 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 396 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 397 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 398 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 399 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 400 BNXT_RX_STATS_ENTRY(rx_bytes), 401 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 402 BNXT_RX_STATS_ENTRY(rx_runt_frames), 403 BNXT_RX_STATS_ENTRY(rx_stat_discard), 404 BNXT_RX_STATS_ENTRY(rx_stat_err), 405 406 BNXT_TX_STATS_ENTRY(tx_64b_frames), 407 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 408 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 409 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 410 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 411 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 412 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 413 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 414 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 415 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 416 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 417 BNXT_TX_STATS_ENTRY(tx_good_frames), 418 BNXT_TX_STATS_ENTRY(tx_total_frames), 419 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 420 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 421 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 422 BNXT_TX_STATS_ENTRY(tx_pause_frames), 423 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 424 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 425 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 426 BNXT_TX_STATS_ENTRY(tx_err), 427 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 428 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 429 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 430 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 431 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 432 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 433 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 434 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 435 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 436 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 437 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 438 BNXT_TX_STATS_ENTRY(tx_total_collisions), 439 BNXT_TX_STATS_ENTRY(tx_bytes), 440 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 441 BNXT_TX_STATS_ENTRY(tx_stat_discard), 442 BNXT_TX_STATS_ENTRY(tx_stat_error), 443 }; 444 445 static const struct { 446 long offset; 447 char string[ETH_GSTRING_LEN]; 448 } bnxt_port_stats_ext_arr[] = { 449 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 450 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 451 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 452 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 453 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 454 BNXT_RX_STATS_EXT_COS_ENTRIES, 455 BNXT_RX_STATS_EXT_PFC_ENTRIES, 456 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 457 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 458 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 459 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 460 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 461 BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks), 462 BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks), 463 BNXT_RX_STATS_EXT_ENTRY(rx_filter_miss), 464 }; 465 466 static const struct { 467 long offset; 468 char string[ETH_GSTRING_LEN]; 469 } bnxt_tx_port_stats_ext_arr[] = { 470 BNXT_TX_STATS_EXT_COS_ENTRIES, 471 BNXT_TX_STATS_EXT_PFC_ENTRIES, 472 }; 473 474 static const struct { 475 long base_off; 476 char string[ETH_GSTRING_LEN]; 477 } bnxt_rx_bytes_pri_arr[] = { 478 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 479 }; 480 481 static const struct { 482 long base_off; 483 char string[ETH_GSTRING_LEN]; 484 } bnxt_rx_pkts_pri_arr[] = { 485 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 486 }; 487 488 static const struct { 489 long base_off; 490 char string[ETH_GSTRING_LEN]; 491 } bnxt_tx_bytes_pri_arr[] = { 492 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 493 }; 494 495 static const struct { 496 long base_off; 497 char string[ETH_GSTRING_LEN]; 498 } bnxt_tx_pkts_pri_arr[] = { 499 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 500 }; 501 502 #define BNXT_NUM_RING_ERR_STATS ARRAY_SIZE(bnxt_ring_err_stats_arr) 503 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 504 #define BNXT_NUM_STATS_PRI \ 505 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 506 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 507 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 508 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 509 510 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 511 { 512 if (BNXT_SUPPORTS_TPA(bp)) { 513 if (bp->max_tpa_v2) { 514 if (BNXT_CHIP_P5(bp)) 515 return BNXT_NUM_TPA_RING_STATS_P5; 516 return BNXT_NUM_TPA_RING_STATS_P7; 517 } 518 return BNXT_NUM_TPA_RING_STATS; 519 } 520 return 0; 521 } 522 523 static int bnxt_get_num_ring_stats(struct bnxt *bp) 524 { 525 int rx, tx, cmn; 526 527 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS + 528 bnxt_get_num_tpa_ring_stats(bp); 529 tx = NUM_RING_TX_HW_STATS; 530 cmn = NUM_RING_CMN_SW_STATS; 531 return rx * bp->rx_nr_rings + 532 tx * (bp->tx_nr_rings_xdp + bp->tx_nr_rings_per_tc) + 533 cmn * bp->cp_nr_rings; 534 } 535 536 static int bnxt_get_num_stats(struct bnxt *bp) 537 { 538 int num_stats = bnxt_get_num_ring_stats(bp); 539 int len; 540 541 num_stats += BNXT_NUM_RING_ERR_STATS; 542 543 if (bp->flags & BNXT_FLAG_PORT_STATS) 544 num_stats += BNXT_NUM_PORT_STATS; 545 546 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 547 len = min_t(int, bp->fw_rx_stats_ext_size, 548 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 549 num_stats += len; 550 len = min_t(int, bp->fw_tx_stats_ext_size, 551 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 552 num_stats += len; 553 if (bp->pri2cos_valid) 554 num_stats += BNXT_NUM_STATS_PRI; 555 } 556 557 return num_stats; 558 } 559 560 static int bnxt_get_sset_count(struct net_device *dev, int sset) 561 { 562 struct bnxt *bp = netdev_priv(dev); 563 564 switch (sset) { 565 case ETH_SS_STATS: 566 return bnxt_get_num_stats(bp); 567 case ETH_SS_TEST: 568 if (!bp->num_tests) 569 return -EOPNOTSUPP; 570 return bp->num_tests; 571 default: 572 return -EOPNOTSUPP; 573 } 574 } 575 576 static bool is_rx_ring(struct bnxt *bp, int ring_num) 577 { 578 return ring_num < bp->rx_nr_rings; 579 } 580 581 static bool is_tx_ring(struct bnxt *bp, int ring_num) 582 { 583 int tx_base = 0; 584 585 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 586 tx_base = bp->rx_nr_rings; 587 588 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings)) 589 return true; 590 return false; 591 } 592 593 static void bnxt_get_ethtool_stats(struct net_device *dev, 594 struct ethtool_stats *stats, u64 *buf) 595 { 596 struct bnxt_total_ring_err_stats ring_err_stats = {0}; 597 struct bnxt *bp = netdev_priv(dev); 598 u64 *curr, *prev; 599 u32 tpa_stats; 600 u32 i, j = 0; 601 602 if (!bp->bnapi) { 603 j += bnxt_get_num_ring_stats(bp); 604 goto skip_ring_stats; 605 } 606 607 tpa_stats = bnxt_get_num_tpa_ring_stats(bp); 608 for (i = 0; i < bp->cp_nr_rings; i++) { 609 struct bnxt_napi *bnapi = bp->bnapi[i]; 610 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 611 u64 *sw_stats = cpr->stats.sw_stats; 612 u64 *sw; 613 int k; 614 615 if (is_rx_ring(bp, i)) { 616 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++) 617 buf[j] = sw_stats[k]; 618 } 619 if (is_tx_ring(bp, i)) { 620 k = NUM_RING_RX_HW_STATS; 621 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 622 j++, k++) 623 buf[j] = sw_stats[k]; 624 } 625 if (!tpa_stats || !is_rx_ring(bp, i)) 626 goto skip_tpa_ring_stats; 627 628 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 629 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS + 630 tpa_stats; j++, k++) 631 buf[j] = sw_stats[k]; 632 633 skip_tpa_ring_stats: 634 sw = (u64 *)&cpr->sw_stats->rx; 635 if (is_rx_ring(bp, i)) { 636 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++) 637 buf[j] = sw[k]; 638 } 639 640 sw = (u64 *)&cpr->sw_stats->cmn; 641 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++) 642 buf[j] = sw[k]; 643 } 644 645 bnxt_get_ring_err_stats(bp, &ring_err_stats); 646 647 skip_ring_stats: 648 curr = &ring_err_stats.rx_total_l4_csum_errors; 649 prev = &bp->ring_err_stats_prev.rx_total_l4_csum_errors; 650 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++, j++, curr++, prev++) 651 buf[j] = *curr + *prev; 652 653 if (bp->flags & BNXT_FLAG_PORT_STATS) { 654 u64 *port_stats = bp->port_stats.sw_stats; 655 656 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) 657 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset); 658 } 659 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 660 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats; 661 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats; 662 u32 len; 663 664 len = min_t(u32, bp->fw_rx_stats_ext_size, 665 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 666 for (i = 0; i < len; i++, j++) { 667 buf[j] = *(rx_port_stats_ext + 668 bnxt_port_stats_ext_arr[i].offset); 669 } 670 len = min_t(u32, bp->fw_tx_stats_ext_size, 671 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 672 for (i = 0; i < len; i++, j++) { 673 buf[j] = *(tx_port_stats_ext + 674 bnxt_tx_port_stats_ext_arr[i].offset); 675 } 676 if (bp->pri2cos_valid) { 677 for (i = 0; i < 8; i++, j++) { 678 long n = bnxt_rx_bytes_pri_arr[i].base_off + 679 bp->pri2cos_idx[i]; 680 681 buf[j] = *(rx_port_stats_ext + n); 682 } 683 for (i = 0; i < 8; i++, j++) { 684 long n = bnxt_rx_pkts_pri_arr[i].base_off + 685 bp->pri2cos_idx[i]; 686 687 buf[j] = *(rx_port_stats_ext + n); 688 } 689 for (i = 0; i < 8; i++, j++) { 690 long n = bnxt_tx_bytes_pri_arr[i].base_off + 691 bp->pri2cos_idx[i]; 692 693 buf[j] = *(tx_port_stats_ext + n); 694 } 695 for (i = 0; i < 8; i++, j++) { 696 long n = bnxt_tx_pkts_pri_arr[i].base_off + 697 bp->pri2cos_idx[i]; 698 699 buf[j] = *(tx_port_stats_ext + n); 700 } 701 } 702 } 703 } 704 705 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 706 { 707 struct bnxt *bp = netdev_priv(dev); 708 u32 i, j, num_str; 709 const char *str; 710 711 switch (stringset) { 712 case ETH_SS_STATS: 713 for (i = 0; i < bp->cp_nr_rings; i++) { 714 if (is_rx_ring(bp, i)) 715 for (j = 0; j < NUM_RING_RX_HW_STATS; j++) { 716 str = bnxt_ring_rx_stats_str[j]; 717 ethtool_sprintf(&buf, "[%d]: %s", i, 718 str); 719 } 720 if (is_tx_ring(bp, i)) 721 for (j = 0; j < NUM_RING_TX_HW_STATS; j++) { 722 str = bnxt_ring_tx_stats_str[j]; 723 ethtool_sprintf(&buf, "[%d]: %s", i, 724 str); 725 } 726 num_str = bnxt_get_num_tpa_ring_stats(bp); 727 if (!num_str || !is_rx_ring(bp, i)) 728 goto skip_tpa_stats; 729 730 if (bp->max_tpa_v2) 731 for (j = 0; j < num_str; j++) { 732 str = bnxt_ring_tpa2_stats_str[j]; 733 ethtool_sprintf(&buf, "[%d]: %s", i, 734 str); 735 } 736 else 737 for (j = 0; j < num_str; j++) { 738 str = bnxt_ring_tpa_stats_str[j]; 739 ethtool_sprintf(&buf, "[%d]: %s", i, 740 str); 741 } 742 skip_tpa_stats: 743 if (is_rx_ring(bp, i)) 744 for (j = 0; j < NUM_RING_RX_SW_STATS; j++) { 745 str = bnxt_rx_sw_stats_str[j]; 746 ethtool_sprintf(&buf, "[%d]: %s", i, 747 str); 748 } 749 for (j = 0; j < NUM_RING_CMN_SW_STATS; j++) { 750 str = bnxt_cmn_sw_stats_str[j]; 751 ethtool_sprintf(&buf, "[%d]: %s", i, str); 752 } 753 } 754 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++) 755 ethtool_puts(&buf, bnxt_ring_err_stats_arr[i]); 756 757 if (bp->flags & BNXT_FLAG_PORT_STATS) 758 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 759 str = bnxt_port_stats_arr[i].string; 760 ethtool_puts(&buf, str); 761 } 762 763 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 764 u32 len; 765 766 len = min_t(u32, bp->fw_rx_stats_ext_size, 767 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 768 for (i = 0; i < len; i++) { 769 str = bnxt_port_stats_ext_arr[i].string; 770 ethtool_puts(&buf, str); 771 } 772 773 len = min_t(u32, bp->fw_tx_stats_ext_size, 774 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 775 for (i = 0; i < len; i++) { 776 str = bnxt_tx_port_stats_ext_arr[i].string; 777 ethtool_puts(&buf, str); 778 } 779 780 if (bp->pri2cos_valid) { 781 for (i = 0; i < 8; i++) { 782 str = bnxt_rx_bytes_pri_arr[i].string; 783 ethtool_puts(&buf, str); 784 } 785 786 for (i = 0; i < 8; i++) { 787 str = bnxt_rx_pkts_pri_arr[i].string; 788 ethtool_puts(&buf, str); 789 } 790 791 for (i = 0; i < 8; i++) { 792 str = bnxt_tx_bytes_pri_arr[i].string; 793 ethtool_puts(&buf, str); 794 } 795 796 for (i = 0; i < 8; i++) { 797 str = bnxt_tx_pkts_pri_arr[i].string; 798 ethtool_puts(&buf, str); 799 } 800 } 801 } 802 break; 803 case ETH_SS_TEST: 804 if (bp->num_tests) 805 for (i = 0; i < bp->num_tests; i++) 806 ethtool_puts(&buf, bp->test_info->string[i]); 807 break; 808 default: 809 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 810 stringset); 811 break; 812 } 813 } 814 815 static void bnxt_get_ringparam(struct net_device *dev, 816 struct ethtool_ringparam *ering, 817 struct kernel_ethtool_ringparam *kernel_ering, 818 struct netlink_ext_ack *extack) 819 { 820 struct bnxt *bp = netdev_priv(dev); 821 822 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 823 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA; 824 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 825 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_ENABLED; 826 } else { 827 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 828 ering->rx_jumbo_max_pending = 0; 829 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_DISABLED; 830 } 831 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 832 833 ering->rx_pending = bp->rx_ring_size; 834 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 835 ering->tx_pending = bp->tx_ring_size; 836 } 837 838 static int bnxt_set_ringparam(struct net_device *dev, 839 struct ethtool_ringparam *ering, 840 struct kernel_ethtool_ringparam *kernel_ering, 841 struct netlink_ext_ack *extack) 842 { 843 struct bnxt *bp = netdev_priv(dev); 844 845 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 846 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 847 (ering->tx_pending < BNXT_MIN_TX_DESC_CNT)) 848 return -EINVAL; 849 850 if (netif_running(dev)) 851 bnxt_close_nic(bp, false, false); 852 853 bp->rx_ring_size = ering->rx_pending; 854 bp->tx_ring_size = ering->tx_pending; 855 bnxt_set_ring_params(bp); 856 857 if (netif_running(dev)) 858 return bnxt_open_nic(bp, false, false); 859 860 return 0; 861 } 862 863 static void bnxt_get_channels(struct net_device *dev, 864 struct ethtool_channels *channel) 865 { 866 struct bnxt *bp = netdev_priv(dev); 867 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 868 int max_rx_rings, max_tx_rings, tcs; 869 int max_tx_sch_inputs, tx_grps; 870 871 /* Get the most up-to-date max_tx_sch_inputs. */ 872 if (netif_running(dev) && BNXT_NEW_RM(bp)) 873 bnxt_hwrm_func_resc_qcaps(bp, false); 874 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 875 876 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 877 if (max_tx_sch_inputs) 878 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 879 880 tcs = bp->num_tc; 881 tx_grps = max(tcs, 1); 882 if (bp->tx_nr_rings_xdp) 883 tx_grps++; 884 max_tx_rings /= tx_grps; 885 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 886 887 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 888 max_rx_rings = 0; 889 max_tx_rings = 0; 890 } 891 if (max_tx_sch_inputs) 892 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 893 894 if (tcs > 1) 895 max_tx_rings /= tcs; 896 897 channel->max_rx = max_rx_rings; 898 channel->max_tx = max_tx_rings; 899 channel->max_other = 0; 900 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 901 channel->combined_count = bp->rx_nr_rings; 902 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 903 channel->combined_count--; 904 } else { 905 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 906 channel->rx_count = bp->rx_nr_rings; 907 channel->tx_count = bp->tx_nr_rings_per_tc; 908 } 909 } 910 } 911 912 static int bnxt_set_channels(struct net_device *dev, 913 struct ethtool_channels *channel) 914 { 915 struct bnxt *bp = netdev_priv(dev); 916 int req_tx_rings, req_rx_rings, tcs; 917 bool sh = false; 918 int tx_xdp = 0; 919 int rc = 0; 920 int tx_cp; 921 922 if (channel->other_count) 923 return -EINVAL; 924 925 if (!channel->combined_count && 926 (!channel->rx_count || !channel->tx_count)) 927 return -EINVAL; 928 929 if (channel->combined_count && 930 (channel->rx_count || channel->tx_count)) 931 return -EINVAL; 932 933 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 934 channel->tx_count)) 935 return -EINVAL; 936 937 if (channel->combined_count) 938 sh = true; 939 940 tcs = bp->num_tc; 941 942 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 943 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 944 if (bp->tx_nr_rings_xdp) { 945 if (!sh) { 946 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 947 return -EINVAL; 948 } 949 tx_xdp = req_rx_rings; 950 } 951 952 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) != 953 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) && 954 netif_is_rxfh_configured(dev)) { 955 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n"); 956 return -EINVAL; 957 } 958 959 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 960 if (rc) { 961 netdev_warn(dev, "Unable to allocate the requested rings\n"); 962 return rc; 963 } 964 965 if (netif_running(dev)) { 966 if (BNXT_PF(bp)) { 967 /* TODO CHIMP_FW: Send message to all VF's 968 * before PF unload 969 */ 970 } 971 bnxt_close_nic(bp, true, false); 972 } 973 974 if (sh) { 975 bp->flags |= BNXT_FLAG_SHARED_RINGS; 976 bp->rx_nr_rings = channel->combined_count; 977 bp->tx_nr_rings_per_tc = channel->combined_count; 978 } else { 979 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 980 bp->rx_nr_rings = channel->rx_count; 981 bp->tx_nr_rings_per_tc = channel->tx_count; 982 } 983 bp->tx_nr_rings_xdp = tx_xdp; 984 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 985 if (tcs > 1) 986 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 987 988 tx_cp = bnxt_num_tx_to_cp(bp, bp->tx_nr_rings); 989 bp->cp_nr_rings = sh ? max_t(int, tx_cp, bp->rx_nr_rings) : 990 tx_cp + bp->rx_nr_rings; 991 992 /* After changing number of rx channels, update NTUPLE feature. */ 993 netdev_update_features(dev); 994 if (netif_running(dev)) { 995 rc = bnxt_open_nic(bp, true, false); 996 if ((!rc) && BNXT_PF(bp)) { 997 /* TODO CHIMP_FW: Send message to all VF's 998 * to renable 999 */ 1000 } 1001 } else { 1002 rc = bnxt_reserve_rings(bp, true); 1003 } 1004 1005 return rc; 1006 } 1007 1008 static u32 bnxt_get_all_fltr_ids_rcu(struct bnxt *bp, struct hlist_head tbl[], 1009 int tbl_size, u32 *ids, u32 start, 1010 u32 id_cnt) 1011 { 1012 int i, j = start; 1013 1014 if (j >= id_cnt) 1015 return j; 1016 for (i = 0; i < tbl_size; i++) { 1017 struct hlist_head *head; 1018 struct bnxt_filter_base *fltr; 1019 1020 head = &tbl[i]; 1021 hlist_for_each_entry_rcu(fltr, head, hash) { 1022 if (!fltr->flags || 1023 test_bit(BNXT_FLTR_FW_DELETED, &fltr->state)) 1024 continue; 1025 ids[j++] = fltr->sw_id; 1026 if (j == id_cnt) 1027 return j; 1028 } 1029 } 1030 return j; 1031 } 1032 1033 static struct bnxt_filter_base *bnxt_get_one_fltr_rcu(struct bnxt *bp, 1034 struct hlist_head tbl[], 1035 int tbl_size, u32 id) 1036 { 1037 int i; 1038 1039 for (i = 0; i < tbl_size; i++) { 1040 struct hlist_head *head; 1041 struct bnxt_filter_base *fltr; 1042 1043 head = &tbl[i]; 1044 hlist_for_each_entry_rcu(fltr, head, hash) { 1045 if (fltr->flags && fltr->sw_id == id) 1046 return fltr; 1047 } 1048 } 1049 return NULL; 1050 } 1051 1052 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 1053 u32 *rule_locs) 1054 { 1055 u32 count; 1056 1057 cmd->data = bp->ntp_fltr_count; 1058 rcu_read_lock(); 1059 count = bnxt_get_all_fltr_ids_rcu(bp, bp->l2_fltr_hash_tbl, 1060 BNXT_L2_FLTR_HASH_SIZE, rule_locs, 0, 1061 cmd->rule_cnt); 1062 cmd->rule_cnt = bnxt_get_all_fltr_ids_rcu(bp, bp->ntp_fltr_hash_tbl, 1063 BNXT_NTP_FLTR_HASH_SIZE, 1064 rule_locs, count, 1065 cmd->rule_cnt); 1066 rcu_read_unlock(); 1067 1068 return 0; 1069 } 1070 1071 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1072 { 1073 struct ethtool_rx_flow_spec *fs = 1074 (struct ethtool_rx_flow_spec *)&cmd->fs; 1075 struct bnxt_filter_base *fltr_base; 1076 struct bnxt_ntuple_filter *fltr; 1077 struct bnxt_flow_masks *fmasks; 1078 struct flow_keys *fkeys; 1079 int rc = -EINVAL; 1080 1081 if (fs->location >= bp->max_fltr) 1082 return rc; 1083 1084 rcu_read_lock(); 1085 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl, 1086 BNXT_L2_FLTR_HASH_SIZE, 1087 fs->location); 1088 if (fltr_base) { 1089 struct ethhdr *h_ether = &fs->h_u.ether_spec; 1090 struct ethhdr *m_ether = &fs->m_u.ether_spec; 1091 struct bnxt_l2_filter *l2_fltr; 1092 struct bnxt_l2_key *l2_key; 1093 1094 l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base); 1095 l2_key = &l2_fltr->l2_key; 1096 fs->flow_type = ETHER_FLOW; 1097 ether_addr_copy(h_ether->h_dest, l2_key->dst_mac_addr); 1098 eth_broadcast_addr(m_ether->h_dest); 1099 if (l2_key->vlan) { 1100 struct ethtool_flow_ext *m_ext = &fs->m_ext; 1101 struct ethtool_flow_ext *h_ext = &fs->h_ext; 1102 1103 fs->flow_type |= FLOW_EXT; 1104 m_ext->vlan_tci = htons(0xfff); 1105 h_ext->vlan_tci = htons(l2_key->vlan); 1106 } 1107 if (fltr_base->flags & BNXT_ACT_RING_DST) 1108 fs->ring_cookie = fltr_base->rxq; 1109 if (fltr_base->flags & BNXT_ACT_FUNC_DST) 1110 fs->ring_cookie = (u64)(fltr_base->vf_idx + 1) << 1111 ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 1112 rcu_read_unlock(); 1113 return 0; 1114 } 1115 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl, 1116 BNXT_NTP_FLTR_HASH_SIZE, 1117 fs->location); 1118 if (!fltr_base) { 1119 rcu_read_unlock(); 1120 return rc; 1121 } 1122 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base); 1123 1124 fkeys = &fltr->fkeys; 1125 fmasks = &fltr->fmasks; 1126 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 1127 if (fkeys->basic.ip_proto == BNXT_IP_PROTO_WILDCARD) { 1128 fs->flow_type = IP_USER_FLOW; 1129 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 1130 fs->h_u.usr_ip4_spec.proto = BNXT_IP_PROTO_WILDCARD; 1131 fs->m_u.usr_ip4_spec.proto = 0; 1132 } else if (fkeys->basic.ip_proto == IPPROTO_ICMP) { 1133 fs->flow_type = IP_USER_FLOW; 1134 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 1135 fs->h_u.usr_ip4_spec.proto = IPPROTO_ICMP; 1136 fs->m_u.usr_ip4_spec.proto = BNXT_IP_PROTO_FULL_MASK; 1137 } else if (fkeys->basic.ip_proto == IPPROTO_TCP) { 1138 fs->flow_type = TCP_V4_FLOW; 1139 } else if (fkeys->basic.ip_proto == IPPROTO_UDP) { 1140 fs->flow_type = UDP_V4_FLOW; 1141 } else { 1142 goto fltr_err; 1143 } 1144 1145 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 1146 fs->m_u.tcp_ip4_spec.ip4src = fmasks->addrs.v4addrs.src; 1147 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 1148 fs->m_u.tcp_ip4_spec.ip4dst = fmasks->addrs.v4addrs.dst; 1149 if (fs->flow_type == TCP_V4_FLOW || 1150 fs->flow_type == UDP_V4_FLOW) { 1151 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 1152 fs->m_u.tcp_ip4_spec.psrc = fmasks->ports.src; 1153 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 1154 fs->m_u.tcp_ip4_spec.pdst = fmasks->ports.dst; 1155 } 1156 } else { 1157 if (fkeys->basic.ip_proto == BNXT_IP_PROTO_WILDCARD) { 1158 fs->flow_type = IPV6_USER_FLOW; 1159 fs->h_u.usr_ip6_spec.l4_proto = BNXT_IP_PROTO_WILDCARD; 1160 fs->m_u.usr_ip6_spec.l4_proto = 0; 1161 } else if (fkeys->basic.ip_proto == IPPROTO_ICMPV6) { 1162 fs->flow_type = IPV6_USER_FLOW; 1163 fs->h_u.usr_ip6_spec.l4_proto = IPPROTO_ICMPV6; 1164 fs->m_u.usr_ip6_spec.l4_proto = BNXT_IP_PROTO_FULL_MASK; 1165 } else if (fkeys->basic.ip_proto == IPPROTO_TCP) { 1166 fs->flow_type = TCP_V6_FLOW; 1167 } else if (fkeys->basic.ip_proto == IPPROTO_UDP) { 1168 fs->flow_type = UDP_V6_FLOW; 1169 } else { 1170 goto fltr_err; 1171 } 1172 1173 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 1174 fkeys->addrs.v6addrs.src; 1175 *(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6src[0] = 1176 fmasks->addrs.v6addrs.src; 1177 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 1178 fkeys->addrs.v6addrs.dst; 1179 *(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6dst[0] = 1180 fmasks->addrs.v6addrs.dst; 1181 if (fs->flow_type == TCP_V6_FLOW || 1182 fs->flow_type == UDP_V6_FLOW) { 1183 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 1184 fs->m_u.tcp_ip6_spec.psrc = fmasks->ports.src; 1185 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 1186 fs->m_u.tcp_ip6_spec.pdst = fmasks->ports.dst; 1187 } 1188 } 1189 1190 if (fltr->base.flags & BNXT_ACT_DROP) { 1191 fs->ring_cookie = RX_CLS_FLOW_DISC; 1192 } else if (fltr->base.flags & BNXT_ACT_RSS_CTX) { 1193 fs->flow_type |= FLOW_RSS; 1194 cmd->rss_context = fltr->base.fw_vnic_id; 1195 } else { 1196 fs->ring_cookie = fltr->base.rxq; 1197 } 1198 rc = 0; 1199 1200 fltr_err: 1201 rcu_read_unlock(); 1202 1203 return rc; 1204 } 1205 1206 static struct bnxt_rss_ctx *bnxt_get_rss_ctx_from_index(struct bnxt *bp, 1207 u32 index) 1208 { 1209 struct ethtool_rxfh_context *ctx; 1210 1211 ctx = xa_load(&bp->dev->ethtool->rss_ctx, index); 1212 if (!ctx) 1213 return NULL; 1214 return ethtool_rxfh_context_priv(ctx); 1215 } 1216 1217 static int bnxt_alloc_vnic_rss_table(struct bnxt *bp, 1218 struct bnxt_vnic_info *vnic) 1219 { 1220 int size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5); 1221 1222 vnic->rss_table_size = size + HW_HASH_KEY_SIZE; 1223 vnic->rss_table = dma_alloc_coherent(&bp->pdev->dev, 1224 vnic->rss_table_size, 1225 &vnic->rss_table_dma_addr, 1226 GFP_KERNEL); 1227 if (!vnic->rss_table) 1228 return -ENOMEM; 1229 1230 vnic->rss_hash_key = ((void *)vnic->rss_table) + size; 1231 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; 1232 return 0; 1233 } 1234 1235 static int bnxt_add_l2_cls_rule(struct bnxt *bp, 1236 struct ethtool_rx_flow_spec *fs) 1237 { 1238 u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1239 u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1240 struct ethhdr *h_ether = &fs->h_u.ether_spec; 1241 struct ethhdr *m_ether = &fs->m_u.ether_spec; 1242 struct bnxt_l2_filter *fltr; 1243 struct bnxt_l2_key key; 1244 u16 vnic_id; 1245 u8 flags; 1246 int rc; 1247 1248 if (BNXT_CHIP_P5_PLUS(bp)) 1249 return -EOPNOTSUPP; 1250 1251 if (!is_broadcast_ether_addr(m_ether->h_dest)) 1252 return -EINVAL; 1253 ether_addr_copy(key.dst_mac_addr, h_ether->h_dest); 1254 key.vlan = 0; 1255 if (fs->flow_type & FLOW_EXT) { 1256 struct ethtool_flow_ext *m_ext = &fs->m_ext; 1257 struct ethtool_flow_ext *h_ext = &fs->h_ext; 1258 1259 if (m_ext->vlan_tci != htons(0xfff) || !h_ext->vlan_tci) 1260 return -EINVAL; 1261 key.vlan = ntohs(h_ext->vlan_tci); 1262 } 1263 1264 if (vf) { 1265 flags = BNXT_ACT_FUNC_DST; 1266 vnic_id = 0xffff; 1267 vf--; 1268 } else { 1269 flags = BNXT_ACT_RING_DST; 1270 vnic_id = bp->vnic_info[ring + 1].fw_vnic_id; 1271 } 1272 fltr = bnxt_alloc_new_l2_filter(bp, &key, flags); 1273 if (IS_ERR(fltr)) 1274 return PTR_ERR(fltr); 1275 1276 fltr->base.fw_vnic_id = vnic_id; 1277 fltr->base.rxq = ring; 1278 fltr->base.vf_idx = vf; 1279 rc = bnxt_hwrm_l2_filter_alloc(bp, fltr); 1280 if (rc) 1281 bnxt_del_l2_filter(bp, fltr); 1282 else 1283 fs->location = fltr->base.sw_id; 1284 return rc; 1285 } 1286 1287 static bool bnxt_verify_ntuple_ip4_flow(struct ethtool_usrip4_spec *ip_spec, 1288 struct ethtool_usrip4_spec *ip_mask) 1289 { 1290 u8 mproto = ip_mask->proto; 1291 u8 sproto = ip_spec->proto; 1292 1293 if (ip_mask->l4_4_bytes || ip_mask->tos || 1294 ip_spec->ip_ver != ETH_RX_NFC_IP4 || 1295 (mproto && (mproto != BNXT_IP_PROTO_FULL_MASK || sproto != IPPROTO_ICMP))) 1296 return false; 1297 return true; 1298 } 1299 1300 static bool bnxt_verify_ntuple_ip6_flow(struct ethtool_usrip6_spec *ip_spec, 1301 struct ethtool_usrip6_spec *ip_mask) 1302 { 1303 u8 mproto = ip_mask->l4_proto; 1304 u8 sproto = ip_spec->l4_proto; 1305 1306 if (ip_mask->l4_4_bytes || ip_mask->tclass || 1307 (mproto && (mproto != BNXT_IP_PROTO_FULL_MASK || sproto != IPPROTO_ICMPV6))) 1308 return false; 1309 return true; 1310 } 1311 1312 static int bnxt_add_ntuple_cls_rule(struct bnxt *bp, 1313 struct ethtool_rxnfc *cmd) 1314 { 1315 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1316 struct bnxt_ntuple_filter *new_fltr, *fltr; 1317 u32 flow_type = fs->flow_type & 0xff; 1318 struct bnxt_l2_filter *l2_fltr; 1319 struct bnxt_flow_masks *fmasks; 1320 struct flow_keys *fkeys; 1321 u32 idx, ring; 1322 int rc; 1323 u8 vf; 1324 1325 if (!bp->vnic_info) 1326 return -EAGAIN; 1327 1328 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1329 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1330 if ((fs->flow_type & (FLOW_MAC_EXT | FLOW_EXT)) || vf) 1331 return -EOPNOTSUPP; 1332 1333 if (flow_type == IP_USER_FLOW) { 1334 if (!bnxt_verify_ntuple_ip4_flow(&fs->h_u.usr_ip4_spec, 1335 &fs->m_u.usr_ip4_spec)) 1336 return -EOPNOTSUPP; 1337 } 1338 1339 if (flow_type == IPV6_USER_FLOW) { 1340 if (!bnxt_verify_ntuple_ip6_flow(&fs->h_u.usr_ip6_spec, 1341 &fs->m_u.usr_ip6_spec)) 1342 return -EOPNOTSUPP; 1343 } 1344 1345 new_fltr = kzalloc(sizeof(*new_fltr), GFP_KERNEL); 1346 if (!new_fltr) 1347 return -ENOMEM; 1348 1349 l2_fltr = bp->vnic_info[BNXT_VNIC_DEFAULT].l2_filters[0]; 1350 atomic_inc(&l2_fltr->refcnt); 1351 new_fltr->l2_fltr = l2_fltr; 1352 fmasks = &new_fltr->fmasks; 1353 fkeys = &new_fltr->fkeys; 1354 1355 rc = -EOPNOTSUPP; 1356 switch (flow_type) { 1357 case IP_USER_FLOW: { 1358 struct ethtool_usrip4_spec *ip_spec = &fs->h_u.usr_ip4_spec; 1359 struct ethtool_usrip4_spec *ip_mask = &fs->m_u.usr_ip4_spec; 1360 1361 fkeys->basic.ip_proto = ip_mask->proto ? ip_spec->proto 1362 : BNXT_IP_PROTO_WILDCARD; 1363 fkeys->basic.n_proto = htons(ETH_P_IP); 1364 fkeys->addrs.v4addrs.src = ip_spec->ip4src; 1365 fmasks->addrs.v4addrs.src = ip_mask->ip4src; 1366 fkeys->addrs.v4addrs.dst = ip_spec->ip4dst; 1367 fmasks->addrs.v4addrs.dst = ip_mask->ip4dst; 1368 break; 1369 } 1370 case TCP_V4_FLOW: 1371 case UDP_V4_FLOW: { 1372 struct ethtool_tcpip4_spec *ip_spec = &fs->h_u.tcp_ip4_spec; 1373 struct ethtool_tcpip4_spec *ip_mask = &fs->m_u.tcp_ip4_spec; 1374 1375 fkeys->basic.ip_proto = IPPROTO_TCP; 1376 if (flow_type == UDP_V4_FLOW) 1377 fkeys->basic.ip_proto = IPPROTO_UDP; 1378 fkeys->basic.n_proto = htons(ETH_P_IP); 1379 fkeys->addrs.v4addrs.src = ip_spec->ip4src; 1380 fmasks->addrs.v4addrs.src = ip_mask->ip4src; 1381 fkeys->addrs.v4addrs.dst = ip_spec->ip4dst; 1382 fmasks->addrs.v4addrs.dst = ip_mask->ip4dst; 1383 fkeys->ports.src = ip_spec->psrc; 1384 fmasks->ports.src = ip_mask->psrc; 1385 fkeys->ports.dst = ip_spec->pdst; 1386 fmasks->ports.dst = ip_mask->pdst; 1387 break; 1388 } 1389 case IPV6_USER_FLOW: { 1390 struct ethtool_usrip6_spec *ip_spec = &fs->h_u.usr_ip6_spec; 1391 struct ethtool_usrip6_spec *ip_mask = &fs->m_u.usr_ip6_spec; 1392 1393 fkeys->basic.ip_proto = ip_mask->l4_proto ? ip_spec->l4_proto 1394 : BNXT_IP_PROTO_WILDCARD; 1395 fkeys->basic.n_proto = htons(ETH_P_IPV6); 1396 fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src; 1397 fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src; 1398 fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst; 1399 fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst; 1400 break; 1401 } 1402 case TCP_V6_FLOW: 1403 case UDP_V6_FLOW: { 1404 struct ethtool_tcpip6_spec *ip_spec = &fs->h_u.tcp_ip6_spec; 1405 struct ethtool_tcpip6_spec *ip_mask = &fs->m_u.tcp_ip6_spec; 1406 1407 fkeys->basic.ip_proto = IPPROTO_TCP; 1408 if (flow_type == UDP_V6_FLOW) 1409 fkeys->basic.ip_proto = IPPROTO_UDP; 1410 fkeys->basic.n_proto = htons(ETH_P_IPV6); 1411 1412 fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src; 1413 fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src; 1414 fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst; 1415 fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst; 1416 fkeys->ports.src = ip_spec->psrc; 1417 fmasks->ports.src = ip_mask->psrc; 1418 fkeys->ports.dst = ip_spec->pdst; 1419 fmasks->ports.dst = ip_mask->pdst; 1420 break; 1421 } 1422 default: 1423 rc = -EOPNOTSUPP; 1424 goto ntuple_err; 1425 } 1426 if (!memcmp(&BNXT_FLOW_MASK_NONE, fmasks, sizeof(*fmasks))) 1427 goto ntuple_err; 1428 1429 idx = bnxt_get_ntp_filter_idx(bp, fkeys, NULL); 1430 rcu_read_lock(); 1431 fltr = bnxt_lookup_ntp_filter_from_idx(bp, new_fltr, idx); 1432 if (fltr) { 1433 rcu_read_unlock(); 1434 rc = -EEXIST; 1435 goto ntuple_err; 1436 } 1437 rcu_read_unlock(); 1438 1439 new_fltr->base.flags = BNXT_ACT_NO_AGING; 1440 if (fs->flow_type & FLOW_RSS) { 1441 struct bnxt_rss_ctx *rss_ctx; 1442 1443 new_fltr->base.fw_vnic_id = 0; 1444 new_fltr->base.flags |= BNXT_ACT_RSS_CTX; 1445 rss_ctx = bnxt_get_rss_ctx_from_index(bp, cmd->rss_context); 1446 if (rss_ctx) { 1447 new_fltr->base.fw_vnic_id = rss_ctx->index; 1448 } else { 1449 rc = -EINVAL; 1450 goto ntuple_err; 1451 } 1452 } 1453 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1454 new_fltr->base.flags |= BNXT_ACT_DROP; 1455 else 1456 new_fltr->base.rxq = ring; 1457 __set_bit(BNXT_FLTR_VALID, &new_fltr->base.state); 1458 rc = bnxt_insert_ntp_filter(bp, new_fltr, idx); 1459 if (!rc) { 1460 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, new_fltr); 1461 if (rc) { 1462 bnxt_del_ntp_filter(bp, new_fltr); 1463 return rc; 1464 } 1465 fs->location = new_fltr->base.sw_id; 1466 return 0; 1467 } 1468 1469 ntuple_err: 1470 atomic_dec(&l2_fltr->refcnt); 1471 kfree(new_fltr); 1472 return rc; 1473 } 1474 1475 static int bnxt_srxclsrlins(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1476 { 1477 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1478 u32 ring, flow_type; 1479 int rc; 1480 u8 vf; 1481 1482 if (!netif_running(bp->dev)) 1483 return -EAGAIN; 1484 if (!(bp->flags & BNXT_FLAG_RFS)) 1485 return -EPERM; 1486 if (fs->location != RX_CLS_LOC_ANY) 1487 return -EINVAL; 1488 1489 flow_type = fs->flow_type; 1490 if ((flow_type == IP_USER_FLOW || 1491 flow_type == IPV6_USER_FLOW) && 1492 !(bp->fw_cap & BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO)) 1493 return -EOPNOTSUPP; 1494 if (flow_type & FLOW_MAC_EXT) 1495 return -EINVAL; 1496 flow_type &= ~FLOW_EXT; 1497 1498 if (fs->ring_cookie == RX_CLS_FLOW_DISC && flow_type != ETHER_FLOW) 1499 return bnxt_add_ntuple_cls_rule(bp, cmd); 1500 1501 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1502 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1503 if (BNXT_VF(bp) && vf) 1504 return -EINVAL; 1505 if (BNXT_PF(bp) && vf > bp->pf.active_vfs) 1506 return -EINVAL; 1507 if (!vf && ring >= bp->rx_nr_rings) 1508 return -EINVAL; 1509 1510 if (flow_type == ETHER_FLOW) 1511 rc = bnxt_add_l2_cls_rule(bp, fs); 1512 else 1513 rc = bnxt_add_ntuple_cls_rule(bp, cmd); 1514 return rc; 1515 } 1516 1517 static int bnxt_srxclsrldel(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1518 { 1519 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1520 struct bnxt_filter_base *fltr_base; 1521 struct bnxt_ntuple_filter *fltr; 1522 u32 id = fs->location; 1523 1524 rcu_read_lock(); 1525 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl, 1526 BNXT_L2_FLTR_HASH_SIZE, id); 1527 if (fltr_base) { 1528 struct bnxt_l2_filter *l2_fltr; 1529 1530 l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base); 1531 rcu_read_unlock(); 1532 bnxt_hwrm_l2_filter_free(bp, l2_fltr); 1533 bnxt_del_l2_filter(bp, l2_fltr); 1534 return 0; 1535 } 1536 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl, 1537 BNXT_NTP_FLTR_HASH_SIZE, id); 1538 if (!fltr_base) { 1539 rcu_read_unlock(); 1540 return -ENOENT; 1541 } 1542 1543 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base); 1544 if (!(fltr->base.flags & BNXT_ACT_NO_AGING)) { 1545 rcu_read_unlock(); 1546 return -EINVAL; 1547 } 1548 rcu_read_unlock(); 1549 bnxt_hwrm_cfa_ntuple_filter_free(bp, fltr); 1550 bnxt_del_ntp_filter(bp, fltr); 1551 return 0; 1552 } 1553 1554 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1555 { 1556 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1557 return RXH_IP_SRC | RXH_IP_DST; 1558 return 0; 1559 } 1560 1561 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1562 { 1563 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1564 return RXH_IP_SRC | RXH_IP_DST; 1565 return 0; 1566 } 1567 1568 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1569 { 1570 cmd->data = 0; 1571 switch (cmd->flow_type) { 1572 case TCP_V4_FLOW: 1573 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1574 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1575 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1576 cmd->data |= get_ethtool_ipv4_rss(bp); 1577 break; 1578 case UDP_V4_FLOW: 1579 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1580 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1581 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1582 fallthrough; 1583 case AH_ESP_V4_FLOW: 1584 if (bp->rss_hash_cfg & 1585 (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1586 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4)) 1587 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1588 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1589 fallthrough; 1590 case SCTP_V4_FLOW: 1591 case AH_V4_FLOW: 1592 case ESP_V4_FLOW: 1593 case IPV4_FLOW: 1594 cmd->data |= get_ethtool_ipv4_rss(bp); 1595 break; 1596 1597 case TCP_V6_FLOW: 1598 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1599 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1600 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1601 cmd->data |= get_ethtool_ipv6_rss(bp); 1602 break; 1603 case UDP_V6_FLOW: 1604 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1605 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1606 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1607 fallthrough; 1608 case AH_ESP_V6_FLOW: 1609 if (bp->rss_hash_cfg & 1610 (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1611 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6)) 1612 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1613 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1614 fallthrough; 1615 case SCTP_V6_FLOW: 1616 case AH_V6_FLOW: 1617 case ESP_V6_FLOW: 1618 case IPV6_FLOW: 1619 cmd->data |= get_ethtool_ipv6_rss(bp); 1620 break; 1621 } 1622 return 0; 1623 } 1624 1625 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1626 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1627 1628 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1629 { 1630 u32 rss_hash_cfg = bp->rss_hash_cfg; 1631 int tuple, rc = 0; 1632 1633 if (cmd->data == RXH_4TUPLE) 1634 tuple = 4; 1635 else if (cmd->data == RXH_2TUPLE) 1636 tuple = 2; 1637 else if (!cmd->data) 1638 tuple = 0; 1639 else 1640 return -EINVAL; 1641 1642 if (cmd->flow_type == TCP_V4_FLOW) { 1643 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1644 if (tuple == 4) 1645 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1646 } else if (cmd->flow_type == UDP_V4_FLOW) { 1647 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP)) 1648 return -EINVAL; 1649 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1650 if (tuple == 4) 1651 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1652 } else if (cmd->flow_type == TCP_V6_FLOW) { 1653 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1654 if (tuple == 4) 1655 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1656 } else if (cmd->flow_type == UDP_V6_FLOW) { 1657 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP)) 1658 return -EINVAL; 1659 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1660 if (tuple == 4) 1661 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1662 } else if (cmd->flow_type == AH_ESP_V4_FLOW) { 1663 if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V4_RSS_CAP) || 1664 !(bp->rss_cap & BNXT_RSS_CAP_ESP_V4_RSS_CAP))) 1665 return -EINVAL; 1666 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1667 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4); 1668 if (tuple == 4) 1669 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1670 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4; 1671 } else if (cmd->flow_type == AH_ESP_V6_FLOW) { 1672 if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V6_RSS_CAP) || 1673 !(bp->rss_cap & BNXT_RSS_CAP_ESP_V6_RSS_CAP))) 1674 return -EINVAL; 1675 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1676 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6); 1677 if (tuple == 4) 1678 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1679 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6; 1680 } else if (tuple == 4) { 1681 return -EINVAL; 1682 } 1683 1684 switch (cmd->flow_type) { 1685 case TCP_V4_FLOW: 1686 case UDP_V4_FLOW: 1687 case SCTP_V4_FLOW: 1688 case AH_ESP_V4_FLOW: 1689 case AH_V4_FLOW: 1690 case ESP_V4_FLOW: 1691 case IPV4_FLOW: 1692 if (tuple == 2) 1693 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1694 else if (!tuple) 1695 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1696 break; 1697 1698 case TCP_V6_FLOW: 1699 case UDP_V6_FLOW: 1700 case SCTP_V6_FLOW: 1701 case AH_ESP_V6_FLOW: 1702 case AH_V6_FLOW: 1703 case ESP_V6_FLOW: 1704 case IPV6_FLOW: 1705 if (tuple == 2) 1706 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1707 else if (!tuple) 1708 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1709 break; 1710 } 1711 1712 if (bp->rss_hash_cfg == rss_hash_cfg) 1713 return 0; 1714 1715 if (bp->rss_cap & BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA) 1716 bp->rss_hash_delta = bp->rss_hash_cfg ^ rss_hash_cfg; 1717 bp->rss_hash_cfg = rss_hash_cfg; 1718 if (netif_running(bp->dev)) { 1719 bnxt_close_nic(bp, false, false); 1720 rc = bnxt_open_nic(bp, false, false); 1721 } 1722 return rc; 1723 } 1724 1725 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1726 u32 *rule_locs) 1727 { 1728 struct bnxt *bp = netdev_priv(dev); 1729 int rc = 0; 1730 1731 switch (cmd->cmd) { 1732 case ETHTOOL_GRXRINGS: 1733 cmd->data = bp->rx_nr_rings; 1734 break; 1735 1736 case ETHTOOL_GRXCLSRLCNT: 1737 cmd->rule_cnt = bp->ntp_fltr_count; 1738 cmd->data = bp->max_fltr | RX_CLS_LOC_SPECIAL; 1739 break; 1740 1741 case ETHTOOL_GRXCLSRLALL: 1742 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1743 break; 1744 1745 case ETHTOOL_GRXCLSRULE: 1746 rc = bnxt_grxclsrule(bp, cmd); 1747 break; 1748 1749 case ETHTOOL_GRXFH: 1750 rc = bnxt_grxfh(bp, cmd); 1751 break; 1752 1753 default: 1754 rc = -EOPNOTSUPP; 1755 break; 1756 } 1757 1758 return rc; 1759 } 1760 1761 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1762 { 1763 struct bnxt *bp = netdev_priv(dev); 1764 int rc; 1765 1766 switch (cmd->cmd) { 1767 case ETHTOOL_SRXFH: 1768 rc = bnxt_srxfh(bp, cmd); 1769 break; 1770 1771 case ETHTOOL_SRXCLSRLINS: 1772 rc = bnxt_srxclsrlins(bp, cmd); 1773 break; 1774 1775 case ETHTOOL_SRXCLSRLDEL: 1776 rc = bnxt_srxclsrldel(bp, cmd); 1777 break; 1778 1779 default: 1780 rc = -EOPNOTSUPP; 1781 break; 1782 } 1783 return rc; 1784 } 1785 1786 u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1787 { 1788 struct bnxt *bp = netdev_priv(dev); 1789 1790 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) 1791 return bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) * 1792 BNXT_RSS_TABLE_ENTRIES_P5; 1793 return HW_HASH_INDEX_SIZE; 1794 } 1795 1796 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1797 { 1798 return HW_HASH_KEY_SIZE; 1799 } 1800 1801 static int bnxt_get_rxfh(struct net_device *dev, 1802 struct ethtool_rxfh_param *rxfh) 1803 { 1804 struct bnxt_rss_ctx *rss_ctx = NULL; 1805 struct bnxt *bp = netdev_priv(dev); 1806 u32 *indir_tbl = bp->rss_indir_tbl; 1807 struct bnxt_vnic_info *vnic; 1808 u32 i, tbl_size; 1809 1810 rxfh->hfunc = ETH_RSS_HASH_TOP; 1811 1812 if (!bp->vnic_info) 1813 return 0; 1814 1815 vnic = &bp->vnic_info[BNXT_VNIC_DEFAULT]; 1816 if (rxfh->rss_context) { 1817 struct ethtool_rxfh_context *ctx; 1818 1819 ctx = xa_load(&bp->dev->ethtool->rss_ctx, rxfh->rss_context); 1820 if (!ctx) 1821 return -EINVAL; 1822 indir_tbl = ethtool_rxfh_context_indir(ctx); 1823 rss_ctx = ethtool_rxfh_context_priv(ctx); 1824 vnic = &rss_ctx->vnic; 1825 } 1826 1827 if (rxfh->indir && indir_tbl) { 1828 tbl_size = bnxt_get_rxfh_indir_size(dev); 1829 for (i = 0; i < tbl_size; i++) 1830 rxfh->indir[i] = indir_tbl[i]; 1831 } 1832 1833 if (rxfh->key && vnic->rss_hash_key) 1834 memcpy(rxfh->key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1835 1836 return 0; 1837 } 1838 1839 static void bnxt_modify_rss(struct bnxt *bp, struct ethtool_rxfh_context *ctx, 1840 struct bnxt_rss_ctx *rss_ctx, 1841 const struct ethtool_rxfh_param *rxfh) 1842 { 1843 if (rxfh->key) { 1844 if (rss_ctx) { 1845 memcpy(rss_ctx->vnic.rss_hash_key, rxfh->key, 1846 HW_HASH_KEY_SIZE); 1847 } else { 1848 memcpy(bp->rss_hash_key, rxfh->key, HW_HASH_KEY_SIZE); 1849 bp->rss_hash_key_updated = true; 1850 } 1851 } 1852 if (rxfh->indir) { 1853 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(bp->dev); 1854 u32 *indir_tbl = bp->rss_indir_tbl; 1855 1856 if (rss_ctx) 1857 indir_tbl = ethtool_rxfh_context_indir(ctx); 1858 for (i = 0; i < tbl_size; i++) 1859 indir_tbl[i] = rxfh->indir[i]; 1860 pad = bp->rss_indir_tbl_entries - tbl_size; 1861 if (pad) 1862 memset(&indir_tbl[i], 0, pad * sizeof(*indir_tbl)); 1863 } 1864 } 1865 1866 static int bnxt_rxfh_context_check(struct bnxt *bp, 1867 const struct ethtool_rxfh_param *rxfh, 1868 struct netlink_ext_ack *extack) 1869 { 1870 if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP) { 1871 NL_SET_ERR_MSG_MOD(extack, "RSS hash function not supported"); 1872 return -EOPNOTSUPP; 1873 } 1874 1875 if (!BNXT_SUPPORTS_MULTI_RSS_CTX(bp)) { 1876 NL_SET_ERR_MSG_MOD(extack, "RSS contexts not supported"); 1877 return -EOPNOTSUPP; 1878 } 1879 1880 if (!netif_running(bp->dev)) { 1881 NL_SET_ERR_MSG_MOD(extack, "Unable to set RSS contexts when interface is down"); 1882 return -EAGAIN; 1883 } 1884 1885 return 0; 1886 } 1887 1888 static int bnxt_create_rxfh_context(struct net_device *dev, 1889 struct ethtool_rxfh_context *ctx, 1890 const struct ethtool_rxfh_param *rxfh, 1891 struct netlink_ext_ack *extack) 1892 { 1893 struct bnxt *bp = netdev_priv(dev); 1894 struct bnxt_rss_ctx *rss_ctx; 1895 struct bnxt_vnic_info *vnic; 1896 int rc; 1897 1898 rc = bnxt_rxfh_context_check(bp, rxfh, extack); 1899 if (rc) 1900 return rc; 1901 1902 if (bp->num_rss_ctx >= BNXT_MAX_ETH_RSS_CTX) { 1903 NL_SET_ERR_MSG_FMT_MOD(extack, "Out of RSS contexts, maximum %u", 1904 BNXT_MAX_ETH_RSS_CTX); 1905 return -EINVAL; 1906 } 1907 1908 if (!bnxt_rfs_capable(bp, true)) { 1909 NL_SET_ERR_MSG_MOD(extack, "Out hardware resources"); 1910 return -ENOMEM; 1911 } 1912 1913 rss_ctx = ethtool_rxfh_context_priv(ctx); 1914 1915 bp->num_rss_ctx++; 1916 1917 vnic = &rss_ctx->vnic; 1918 vnic->rss_ctx = ctx; 1919 vnic->flags |= BNXT_VNIC_RSSCTX_FLAG; 1920 vnic->vnic_id = BNXT_VNIC_ID_INVALID; 1921 rc = bnxt_alloc_vnic_rss_table(bp, vnic); 1922 if (rc) 1923 goto out; 1924 1925 /* Populate defaults in the context */ 1926 bnxt_set_dflt_rss_indir_tbl(bp, ctx); 1927 ctx->hfunc = ETH_RSS_HASH_TOP; 1928 memcpy(vnic->rss_hash_key, bp->rss_hash_key, HW_HASH_KEY_SIZE); 1929 memcpy(ethtool_rxfh_context_key(ctx), 1930 bp->rss_hash_key, HW_HASH_KEY_SIZE); 1931 1932 rc = bnxt_hwrm_vnic_alloc(bp, vnic, 0, bp->rx_nr_rings); 1933 if (rc) { 1934 NL_SET_ERR_MSG_MOD(extack, "Unable to allocate VNIC"); 1935 goto out; 1936 } 1937 1938 rc = bnxt_hwrm_vnic_set_tpa(bp, vnic, bp->flags & BNXT_FLAG_TPA); 1939 if (rc) { 1940 NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA"); 1941 goto out; 1942 } 1943 bnxt_modify_rss(bp, ctx, rss_ctx, rxfh); 1944 1945 rc = __bnxt_setup_vnic_p5(bp, vnic); 1946 if (rc) { 1947 NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA"); 1948 goto out; 1949 } 1950 1951 rss_ctx->index = rxfh->rss_context; 1952 return 0; 1953 out: 1954 bnxt_del_one_rss_ctx(bp, rss_ctx, true); 1955 return rc; 1956 } 1957 1958 static int bnxt_modify_rxfh_context(struct net_device *dev, 1959 struct ethtool_rxfh_context *ctx, 1960 const struct ethtool_rxfh_param *rxfh, 1961 struct netlink_ext_ack *extack) 1962 { 1963 struct bnxt *bp = netdev_priv(dev); 1964 struct bnxt_rss_ctx *rss_ctx; 1965 int rc; 1966 1967 rc = bnxt_rxfh_context_check(bp, rxfh, extack); 1968 if (rc) 1969 return rc; 1970 1971 rss_ctx = ethtool_rxfh_context_priv(ctx); 1972 1973 bnxt_modify_rss(bp, ctx, rss_ctx, rxfh); 1974 1975 return bnxt_hwrm_vnic_rss_cfg_p5(bp, &rss_ctx->vnic); 1976 } 1977 1978 static int bnxt_remove_rxfh_context(struct net_device *dev, 1979 struct ethtool_rxfh_context *ctx, 1980 u32 rss_context, 1981 struct netlink_ext_ack *extack) 1982 { 1983 struct bnxt *bp = netdev_priv(dev); 1984 struct bnxt_rss_ctx *rss_ctx; 1985 1986 rss_ctx = ethtool_rxfh_context_priv(ctx); 1987 1988 bnxt_del_one_rss_ctx(bp, rss_ctx, true); 1989 return 0; 1990 } 1991 1992 static int bnxt_set_rxfh(struct net_device *dev, 1993 struct ethtool_rxfh_param *rxfh, 1994 struct netlink_ext_ack *extack) 1995 { 1996 struct bnxt *bp = netdev_priv(dev); 1997 int rc = 0; 1998 1999 if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP) 2000 return -EOPNOTSUPP; 2001 2002 bnxt_modify_rss(bp, NULL, NULL, rxfh); 2003 2004 if (netif_running(bp->dev)) { 2005 bnxt_close_nic(bp, false, false); 2006 rc = bnxt_open_nic(bp, false, false); 2007 } 2008 return rc; 2009 } 2010 2011 static void bnxt_get_drvinfo(struct net_device *dev, 2012 struct ethtool_drvinfo *info) 2013 { 2014 struct bnxt *bp = netdev_priv(dev); 2015 2016 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 2017 strscpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 2018 strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 2019 info->n_stats = bnxt_get_num_stats(bp); 2020 info->testinfo_len = bp->num_tests; 2021 /* TODO CHIMP_FW: eeprom dump details */ 2022 info->eedump_len = 0; 2023 /* TODO CHIMP FW: reg dump details */ 2024 info->regdump_len = 0; 2025 } 2026 2027 static int bnxt_get_regs_len(struct net_device *dev) 2028 { 2029 struct bnxt *bp = netdev_priv(dev); 2030 int reg_len; 2031 2032 if (!BNXT_PF(bp)) 2033 return -EOPNOTSUPP; 2034 2035 reg_len = BNXT_PXP_REG_LEN; 2036 2037 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED) 2038 reg_len += sizeof(struct pcie_ctx_hw_stats); 2039 2040 return reg_len; 2041 } 2042 2043 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs, 2044 void *_p) 2045 { 2046 struct pcie_ctx_hw_stats *hw_pcie_stats; 2047 struct hwrm_pcie_qstats_input *req; 2048 struct bnxt *bp = netdev_priv(dev); 2049 dma_addr_t hw_pcie_stats_addr; 2050 int rc; 2051 2052 regs->version = 0; 2053 if (!(bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_REG_ACCESS_RESTRICTED)) 2054 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p); 2055 2056 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 2057 return; 2058 2059 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS)) 2060 return; 2061 2062 hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats), 2063 &hw_pcie_stats_addr); 2064 if (!hw_pcie_stats) { 2065 hwrm_req_drop(bp, req); 2066 return; 2067 } 2068 2069 regs->version = 1; 2070 hwrm_req_hold(bp, req); /* hold on to slice */ 2071 req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats)); 2072 req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr); 2073 rc = hwrm_req_send(bp, req); 2074 if (!rc) { 2075 __le64 *src = (__le64 *)hw_pcie_stats; 2076 u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN); 2077 int i; 2078 2079 for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++) 2080 dst[i] = le64_to_cpu(src[i]); 2081 } 2082 hwrm_req_drop(bp, req); 2083 } 2084 2085 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2086 { 2087 struct bnxt *bp = netdev_priv(dev); 2088 2089 wol->supported = 0; 2090 wol->wolopts = 0; 2091 memset(&wol->sopass, 0, sizeof(wol->sopass)); 2092 if (bp->flags & BNXT_FLAG_WOL_CAP) { 2093 wol->supported = WAKE_MAGIC; 2094 if (bp->wol) 2095 wol->wolopts = WAKE_MAGIC; 2096 } 2097 } 2098 2099 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2100 { 2101 struct bnxt *bp = netdev_priv(dev); 2102 2103 if (wol->wolopts & ~WAKE_MAGIC) 2104 return -EINVAL; 2105 2106 if (wol->wolopts & WAKE_MAGIC) { 2107 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 2108 return -EINVAL; 2109 if (!bp->wol) { 2110 if (bnxt_hwrm_alloc_wol_fltr(bp)) 2111 return -EBUSY; 2112 bp->wol = 1; 2113 } 2114 } else { 2115 if (bp->wol) { 2116 if (bnxt_hwrm_free_wol_fltr(bp)) 2117 return -EBUSY; 2118 bp->wol = 0; 2119 } 2120 } 2121 return 0; 2122 } 2123 2124 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 2125 void _bnxt_fw_to_linkmode(unsigned long *mode, u16 fw_speeds) 2126 { 2127 linkmode_zero(mode); 2128 2129 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 2130 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode); 2131 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 2132 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode); 2133 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 2134 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT, mode); 2135 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 2136 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode); 2137 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 2138 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode); 2139 } 2140 2141 enum bnxt_media_type { 2142 BNXT_MEDIA_UNKNOWN = 0, 2143 BNXT_MEDIA_TP, 2144 BNXT_MEDIA_CR, 2145 BNXT_MEDIA_SR, 2146 BNXT_MEDIA_LR_ER_FR, 2147 BNXT_MEDIA_KR, 2148 BNXT_MEDIA_KX, 2149 BNXT_MEDIA_X, 2150 __BNXT_MEDIA_END, 2151 }; 2152 2153 static const enum bnxt_media_type bnxt_phy_types[] = { 2154 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR] = BNXT_MEDIA_CR, 2155 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4] = BNXT_MEDIA_KR, 2156 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR] = BNXT_MEDIA_LR_ER_FR, 2157 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR] = BNXT_MEDIA_SR, 2158 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2] = BNXT_MEDIA_KR, 2159 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX] = BNXT_MEDIA_KX, 2160 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR] = BNXT_MEDIA_KR, 2161 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASET] = BNXT_MEDIA_TP, 2162 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE] = BNXT_MEDIA_TP, 2163 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L] = BNXT_MEDIA_CR, 2164 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S] = BNXT_MEDIA_CR, 2165 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N] = BNXT_MEDIA_CR, 2166 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR] = BNXT_MEDIA_SR, 2167 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4] = BNXT_MEDIA_CR, 2168 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4] = BNXT_MEDIA_SR, 2169 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2170 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2171 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10] = BNXT_MEDIA_SR, 2172 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4] = BNXT_MEDIA_CR, 2173 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4] = BNXT_MEDIA_SR, 2174 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2175 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2176 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE] = BNXT_MEDIA_SR, 2177 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET] = BNXT_MEDIA_TP, 2178 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX] = BNXT_MEDIA_X, 2179 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX] = BNXT_MEDIA_X, 2180 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4] = BNXT_MEDIA_CR, 2181 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4] = BNXT_MEDIA_SR, 2182 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2183 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2184 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR] = BNXT_MEDIA_CR, 2185 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR] = BNXT_MEDIA_SR, 2186 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR] = BNXT_MEDIA_LR_ER_FR, 2187 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER] = BNXT_MEDIA_LR_ER_FR, 2188 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2] = BNXT_MEDIA_CR, 2189 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2] = BNXT_MEDIA_SR, 2190 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2] = BNXT_MEDIA_LR_ER_FR, 2191 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2] = BNXT_MEDIA_LR_ER_FR, 2192 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR] = BNXT_MEDIA_CR, 2193 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR] = BNXT_MEDIA_SR, 2194 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR] = BNXT_MEDIA_LR_ER_FR, 2195 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER] = BNXT_MEDIA_LR_ER_FR, 2196 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2] = BNXT_MEDIA_CR, 2197 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2] = BNXT_MEDIA_SR, 2198 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2] = BNXT_MEDIA_LR_ER_FR, 2199 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2] = BNXT_MEDIA_LR_ER_FR, 2200 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8] = BNXT_MEDIA_CR, 2201 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8] = BNXT_MEDIA_SR, 2202 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8] = BNXT_MEDIA_LR_ER_FR, 2203 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8] = BNXT_MEDIA_LR_ER_FR, 2204 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4] = BNXT_MEDIA_CR, 2205 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4] = BNXT_MEDIA_SR, 2206 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2207 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2208 }; 2209 2210 static enum bnxt_media_type 2211 bnxt_get_media(struct bnxt_link_info *link_info) 2212 { 2213 switch (link_info->media_type) { 2214 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP: 2215 return BNXT_MEDIA_TP; 2216 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC: 2217 return BNXT_MEDIA_CR; 2218 default: 2219 if (link_info->phy_type < ARRAY_SIZE(bnxt_phy_types)) 2220 return bnxt_phy_types[link_info->phy_type]; 2221 return BNXT_MEDIA_UNKNOWN; 2222 } 2223 } 2224 2225 enum bnxt_link_speed_indices { 2226 BNXT_LINK_SPEED_UNKNOWN = 0, 2227 BNXT_LINK_SPEED_100MB_IDX, 2228 BNXT_LINK_SPEED_1GB_IDX, 2229 BNXT_LINK_SPEED_10GB_IDX, 2230 BNXT_LINK_SPEED_25GB_IDX, 2231 BNXT_LINK_SPEED_40GB_IDX, 2232 BNXT_LINK_SPEED_50GB_IDX, 2233 BNXT_LINK_SPEED_100GB_IDX, 2234 BNXT_LINK_SPEED_200GB_IDX, 2235 BNXT_LINK_SPEED_400GB_IDX, 2236 __BNXT_LINK_SPEED_END 2237 }; 2238 2239 static enum bnxt_link_speed_indices bnxt_fw_speed_idx(u16 speed) 2240 { 2241 switch (speed) { 2242 case BNXT_LINK_SPEED_100MB: return BNXT_LINK_SPEED_100MB_IDX; 2243 case BNXT_LINK_SPEED_1GB: return BNXT_LINK_SPEED_1GB_IDX; 2244 case BNXT_LINK_SPEED_10GB: return BNXT_LINK_SPEED_10GB_IDX; 2245 case BNXT_LINK_SPEED_25GB: return BNXT_LINK_SPEED_25GB_IDX; 2246 case BNXT_LINK_SPEED_40GB: return BNXT_LINK_SPEED_40GB_IDX; 2247 case BNXT_LINK_SPEED_50GB: 2248 case BNXT_LINK_SPEED_50GB_PAM4: 2249 return BNXT_LINK_SPEED_50GB_IDX; 2250 case BNXT_LINK_SPEED_100GB: 2251 case BNXT_LINK_SPEED_100GB_PAM4: 2252 case BNXT_LINK_SPEED_100GB_PAM4_112: 2253 return BNXT_LINK_SPEED_100GB_IDX; 2254 case BNXT_LINK_SPEED_200GB: 2255 case BNXT_LINK_SPEED_200GB_PAM4: 2256 case BNXT_LINK_SPEED_200GB_PAM4_112: 2257 return BNXT_LINK_SPEED_200GB_IDX; 2258 case BNXT_LINK_SPEED_400GB: 2259 case BNXT_LINK_SPEED_400GB_PAM4: 2260 case BNXT_LINK_SPEED_400GB_PAM4_112: 2261 return BNXT_LINK_SPEED_400GB_IDX; 2262 default: return BNXT_LINK_SPEED_UNKNOWN; 2263 } 2264 } 2265 2266 static const enum ethtool_link_mode_bit_indices 2267 bnxt_link_modes[__BNXT_LINK_SPEED_END][BNXT_SIG_MODE_MAX][__BNXT_MEDIA_END] = { 2268 [BNXT_LINK_SPEED_100MB_IDX] = { 2269 { 2270 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_100baseT_Full_BIT, 2271 }, 2272 }, 2273 [BNXT_LINK_SPEED_1GB_IDX] = { 2274 { 2275 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 2276 /* historically baseT, but DAC is more correctly baseX */ 2277 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 2278 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2279 [BNXT_MEDIA_X] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 2280 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2281 }, 2282 }, 2283 [BNXT_LINK_SPEED_10GB_IDX] = { 2284 { 2285 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 2286 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 2287 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 2288 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 2289 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 2290 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 2291 }, 2292 }, 2293 [BNXT_LINK_SPEED_25GB_IDX] = { 2294 { 2295 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 2296 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 2297 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 2298 }, 2299 }, 2300 [BNXT_LINK_SPEED_40GB_IDX] = { 2301 { 2302 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 2303 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 2304 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 2305 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 2306 }, 2307 }, 2308 [BNXT_LINK_SPEED_50GB_IDX] = { 2309 [BNXT_SIG_MODE_NRZ] = { 2310 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 2311 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 2312 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 2313 }, 2314 [BNXT_SIG_MODE_PAM4] = { 2315 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 2316 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 2317 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 2318 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 2319 }, 2320 }, 2321 [BNXT_LINK_SPEED_100GB_IDX] = { 2322 [BNXT_SIG_MODE_NRZ] = { 2323 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 2324 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 2325 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 2326 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 2327 }, 2328 [BNXT_SIG_MODE_PAM4] = { 2329 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 2330 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 2331 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 2332 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 2333 }, 2334 [BNXT_SIG_MODE_PAM4_112] = { 2335 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR_Full_BIT, 2336 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR_Full_BIT, 2337 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR_Full_BIT, 2338 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT, 2339 }, 2340 }, 2341 [BNXT_LINK_SPEED_200GB_IDX] = { 2342 [BNXT_SIG_MODE_PAM4] = { 2343 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT, 2344 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 2345 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 2346 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 2347 }, 2348 [BNXT_SIG_MODE_PAM4_112] = { 2349 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT, 2350 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT, 2351 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT, 2352 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT, 2353 }, 2354 }, 2355 [BNXT_LINK_SPEED_400GB_IDX] = { 2356 [BNXT_SIG_MODE_PAM4] = { 2357 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT, 2358 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT, 2359 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT, 2360 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT, 2361 }, 2362 [BNXT_SIG_MODE_PAM4_112] = { 2363 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT, 2364 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT, 2365 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT, 2366 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT, 2367 }, 2368 }, 2369 }; 2370 2371 #define BNXT_LINK_MODE_UNKNOWN -1 2372 2373 static enum ethtool_link_mode_bit_indices 2374 bnxt_get_link_mode(struct bnxt_link_info *link_info) 2375 { 2376 enum ethtool_link_mode_bit_indices link_mode; 2377 enum bnxt_link_speed_indices speed; 2378 enum bnxt_media_type media; 2379 u8 sig_mode; 2380 2381 if (link_info->phy_link_status != BNXT_LINK_LINK) 2382 return BNXT_LINK_MODE_UNKNOWN; 2383 2384 media = bnxt_get_media(link_info); 2385 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 2386 speed = bnxt_fw_speed_idx(link_info->link_speed); 2387 sig_mode = link_info->active_fec_sig_mode & 2388 PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK; 2389 } else { 2390 speed = bnxt_fw_speed_idx(link_info->req_link_speed); 2391 sig_mode = link_info->req_signal_mode; 2392 } 2393 if (sig_mode >= BNXT_SIG_MODE_MAX) 2394 return BNXT_LINK_MODE_UNKNOWN; 2395 2396 /* Note ETHTOOL_LINK_MODE_10baseT_Half_BIT == 0 is a legal Linux 2397 * link mode, but since no such devices exist, the zeroes in the 2398 * map can be conveniently used to represent unknown link modes. 2399 */ 2400 link_mode = bnxt_link_modes[speed][sig_mode][media]; 2401 if (!link_mode) 2402 return BNXT_LINK_MODE_UNKNOWN; 2403 2404 switch (link_mode) { 2405 case ETHTOOL_LINK_MODE_100baseT_Full_BIT: 2406 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2407 link_mode = ETHTOOL_LINK_MODE_100baseT_Half_BIT; 2408 break; 2409 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT: 2410 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2411 link_mode = ETHTOOL_LINK_MODE_1000baseT_Half_BIT; 2412 break; 2413 default: 2414 break; 2415 } 2416 2417 return link_mode; 2418 } 2419 2420 static void bnxt_get_ethtool_modes(struct bnxt_link_info *link_info, 2421 struct ethtool_link_ksettings *lk_ksettings) 2422 { 2423 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2424 2425 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) { 2426 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2427 lk_ksettings->link_modes.supported); 2428 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2429 lk_ksettings->link_modes.supported); 2430 } 2431 2432 if (link_info->support_auto_speeds || link_info->support_auto_speeds2 || 2433 link_info->support_pam4_auto_speeds) 2434 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2435 lk_ksettings->link_modes.supported); 2436 2437 if (~link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 2438 return; 2439 2440 if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_RX) 2441 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2442 lk_ksettings->link_modes.advertising); 2443 if (hweight8(link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) == 1) 2444 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2445 lk_ksettings->link_modes.advertising); 2446 if (link_info->lp_pause & BNXT_LINK_PAUSE_RX) 2447 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2448 lk_ksettings->link_modes.lp_advertising); 2449 if (hweight8(link_info->lp_pause & BNXT_LINK_PAUSE_BOTH) == 1) 2450 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2451 lk_ksettings->link_modes.lp_advertising); 2452 } 2453 2454 static const u16 bnxt_nrz_speed_masks[] = { 2455 [BNXT_LINK_SPEED_100MB_IDX] = BNXT_LINK_SPEED_MSK_100MB, 2456 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEED_MSK_1GB, 2457 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEED_MSK_10GB, 2458 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEED_MSK_25GB, 2459 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEED_MSK_40GB, 2460 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEED_MSK_50GB, 2461 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEED_MSK_100GB, 2462 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2463 }; 2464 2465 static const u16 bnxt_pam4_speed_masks[] = { 2466 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_50GB, 2467 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_100GB, 2468 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_200GB, 2469 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2470 }; 2471 2472 static const u16 bnxt_nrz_speeds2_masks[] = { 2473 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEEDS2_MSK_1GB, 2474 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEEDS2_MSK_10GB, 2475 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEEDS2_MSK_25GB, 2476 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEEDS2_MSK_40GB, 2477 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB, 2478 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB, 2479 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2480 }; 2481 2482 static const u16 bnxt_pam4_speeds2_masks[] = { 2483 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB_PAM4, 2484 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4, 2485 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4, 2486 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4, 2487 }; 2488 2489 static const u16 bnxt_pam4_112_speeds2_masks[] = { 2490 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112, 2491 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112, 2492 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112, 2493 }; 2494 2495 static enum bnxt_link_speed_indices 2496 bnxt_encoding_speed_idx(u8 sig_mode, u16 phy_flags, u16 speed_msk) 2497 { 2498 const u16 *speeds; 2499 int idx, len; 2500 2501 switch (sig_mode) { 2502 case BNXT_SIG_MODE_NRZ: 2503 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2504 speeds = bnxt_nrz_speeds2_masks; 2505 len = ARRAY_SIZE(bnxt_nrz_speeds2_masks); 2506 } else { 2507 speeds = bnxt_nrz_speed_masks; 2508 len = ARRAY_SIZE(bnxt_nrz_speed_masks); 2509 } 2510 break; 2511 case BNXT_SIG_MODE_PAM4: 2512 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2513 speeds = bnxt_pam4_speeds2_masks; 2514 len = ARRAY_SIZE(bnxt_pam4_speeds2_masks); 2515 } else { 2516 speeds = bnxt_pam4_speed_masks; 2517 len = ARRAY_SIZE(bnxt_pam4_speed_masks); 2518 } 2519 break; 2520 case BNXT_SIG_MODE_PAM4_112: 2521 speeds = bnxt_pam4_112_speeds2_masks; 2522 len = ARRAY_SIZE(bnxt_pam4_112_speeds2_masks); 2523 break; 2524 default: 2525 return BNXT_LINK_SPEED_UNKNOWN; 2526 } 2527 2528 for (idx = 0; idx < len; idx++) { 2529 if (speeds[idx] == speed_msk) 2530 return idx; 2531 } 2532 2533 return BNXT_LINK_SPEED_UNKNOWN; 2534 } 2535 2536 #define BNXT_FW_SPEED_MSK_BITS 16 2537 2538 static void 2539 __bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media, 2540 u8 sig_mode, u16 phy_flags, unsigned long *et_mask) 2541 { 2542 enum ethtool_link_mode_bit_indices link_mode; 2543 enum bnxt_link_speed_indices speed; 2544 u8 bit; 2545 2546 for_each_set_bit(bit, &fw_mask, BNXT_FW_SPEED_MSK_BITS) { 2547 speed = bnxt_encoding_speed_idx(sig_mode, phy_flags, 1 << bit); 2548 if (!speed) 2549 continue; 2550 2551 link_mode = bnxt_link_modes[speed][sig_mode][media]; 2552 if (!link_mode) 2553 continue; 2554 2555 linkmode_set_bit(link_mode, et_mask); 2556 } 2557 } 2558 2559 static void 2560 bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media, 2561 u8 sig_mode, u16 phy_flags, unsigned long *et_mask) 2562 { 2563 if (media) { 2564 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags, 2565 et_mask); 2566 return; 2567 } 2568 2569 /* list speeds for all media if unknown */ 2570 for (media = 1; media < __BNXT_MEDIA_END; media++) 2571 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags, 2572 et_mask); 2573 } 2574 2575 static void 2576 bnxt_get_all_ethtool_support_speeds(struct bnxt_link_info *link_info, 2577 enum bnxt_media_type media, 2578 struct ethtool_link_ksettings *lk_ksettings) 2579 { 2580 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2581 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0; 2582 u16 phy_flags = bp->phy_flags; 2583 2584 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2585 sp_nrz = link_info->support_speeds2; 2586 sp_pam4 = link_info->support_speeds2; 2587 sp_pam4_112 = link_info->support_speeds2; 2588 } else { 2589 sp_nrz = link_info->support_speeds; 2590 sp_pam4 = link_info->support_pam4_speeds; 2591 } 2592 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags, 2593 lk_ksettings->link_modes.supported); 2594 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags, 2595 lk_ksettings->link_modes.supported); 2596 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112, 2597 phy_flags, lk_ksettings->link_modes.supported); 2598 } 2599 2600 static void 2601 bnxt_get_all_ethtool_adv_speeds(struct bnxt_link_info *link_info, 2602 enum bnxt_media_type media, 2603 struct ethtool_link_ksettings *lk_ksettings) 2604 { 2605 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2606 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0; 2607 u16 phy_flags = bp->phy_flags; 2608 2609 sp_nrz = link_info->advertising; 2610 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2611 sp_pam4 = link_info->advertising; 2612 sp_pam4_112 = link_info->advertising; 2613 } else { 2614 sp_pam4 = link_info->advertising_pam4; 2615 } 2616 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags, 2617 lk_ksettings->link_modes.advertising); 2618 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags, 2619 lk_ksettings->link_modes.advertising); 2620 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112, 2621 phy_flags, lk_ksettings->link_modes.advertising); 2622 } 2623 2624 static void 2625 bnxt_get_all_ethtool_lp_speeds(struct bnxt_link_info *link_info, 2626 enum bnxt_media_type media, 2627 struct ethtool_link_ksettings *lk_ksettings) 2628 { 2629 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2630 u16 phy_flags = bp->phy_flags; 2631 2632 bnxt_get_ethtool_speeds(link_info->lp_auto_link_speeds, media, 2633 BNXT_SIG_MODE_NRZ, phy_flags, 2634 lk_ksettings->link_modes.lp_advertising); 2635 bnxt_get_ethtool_speeds(link_info->lp_auto_pam4_link_speeds, media, 2636 BNXT_SIG_MODE_PAM4, phy_flags, 2637 lk_ksettings->link_modes.lp_advertising); 2638 } 2639 2640 static void bnxt_update_speed(u32 *delta, bool installed_media, u16 *speeds, 2641 u16 speed_msk, const unsigned long *et_mask, 2642 enum ethtool_link_mode_bit_indices mode) 2643 { 2644 bool mode_desired = linkmode_test_bit(mode, et_mask); 2645 2646 if (!mode) 2647 return; 2648 2649 /* enabled speeds for installed media should override */ 2650 if (installed_media && mode_desired) { 2651 *speeds |= speed_msk; 2652 *delta |= speed_msk; 2653 return; 2654 } 2655 2656 /* many to one mapping, only allow one change per fw_speed bit */ 2657 if (!(*delta & speed_msk) && (mode_desired == !(*speeds & speed_msk))) { 2658 *speeds ^= speed_msk; 2659 *delta |= speed_msk; 2660 } 2661 } 2662 2663 static void bnxt_set_ethtool_speeds(struct bnxt_link_info *link_info, 2664 const unsigned long *et_mask) 2665 { 2666 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2667 u16 const *sp_msks, *sp_pam4_msks, *sp_pam4_112_msks; 2668 enum bnxt_media_type media = bnxt_get_media(link_info); 2669 u16 *adv, *adv_pam4, *adv_pam4_112 = NULL; 2670 u32 delta_pam4_112 = 0; 2671 u32 delta_pam4 = 0; 2672 u32 delta_nrz = 0; 2673 int i, m; 2674 2675 adv = &link_info->advertising; 2676 if (bp->phy_flags & BNXT_PHY_FL_SPEEDS2) { 2677 adv_pam4 = &link_info->advertising; 2678 adv_pam4_112 = &link_info->advertising; 2679 sp_msks = bnxt_nrz_speeds2_masks; 2680 sp_pam4_msks = bnxt_pam4_speeds2_masks; 2681 sp_pam4_112_msks = bnxt_pam4_112_speeds2_masks; 2682 } else { 2683 adv_pam4 = &link_info->advertising_pam4; 2684 sp_msks = bnxt_nrz_speed_masks; 2685 sp_pam4_msks = bnxt_pam4_speed_masks; 2686 } 2687 for (i = 1; i < __BNXT_LINK_SPEED_END; i++) { 2688 /* accept any legal media from user */ 2689 for (m = 1; m < __BNXT_MEDIA_END; m++) { 2690 bnxt_update_speed(&delta_nrz, m == media, 2691 adv, sp_msks[i], et_mask, 2692 bnxt_link_modes[i][BNXT_SIG_MODE_NRZ][m]); 2693 bnxt_update_speed(&delta_pam4, m == media, 2694 adv_pam4, sp_pam4_msks[i], et_mask, 2695 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4][m]); 2696 if (!adv_pam4_112) 2697 continue; 2698 2699 bnxt_update_speed(&delta_pam4_112, m == media, 2700 adv_pam4_112, sp_pam4_112_msks[i], et_mask, 2701 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4_112][m]); 2702 } 2703 } 2704 } 2705 2706 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info, 2707 struct ethtool_link_ksettings *lk_ksettings) 2708 { 2709 u16 fec_cfg = link_info->fec_cfg; 2710 2711 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) { 2712 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 2713 lk_ksettings->link_modes.advertising); 2714 return; 2715 } 2716 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 2717 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 2718 lk_ksettings->link_modes.advertising); 2719 if (fec_cfg & BNXT_FEC_ENC_RS) 2720 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 2721 lk_ksettings->link_modes.advertising); 2722 if (fec_cfg & BNXT_FEC_ENC_LLRS) 2723 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 2724 lk_ksettings->link_modes.advertising); 2725 } 2726 2727 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info, 2728 struct ethtool_link_ksettings *lk_ksettings) 2729 { 2730 u16 fec_cfg = link_info->fec_cfg; 2731 2732 if (fec_cfg & BNXT_FEC_NONE) { 2733 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 2734 lk_ksettings->link_modes.supported); 2735 return; 2736 } 2737 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP) 2738 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 2739 lk_ksettings->link_modes.supported); 2740 if (fec_cfg & BNXT_FEC_ENC_RS_CAP) 2741 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 2742 lk_ksettings->link_modes.supported); 2743 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP) 2744 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 2745 lk_ksettings->link_modes.supported); 2746 } 2747 2748 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 2749 { 2750 switch (fw_link_speed) { 2751 case BNXT_LINK_SPEED_100MB: 2752 return SPEED_100; 2753 case BNXT_LINK_SPEED_1GB: 2754 return SPEED_1000; 2755 case BNXT_LINK_SPEED_2_5GB: 2756 return SPEED_2500; 2757 case BNXT_LINK_SPEED_10GB: 2758 return SPEED_10000; 2759 case BNXT_LINK_SPEED_20GB: 2760 return SPEED_20000; 2761 case BNXT_LINK_SPEED_25GB: 2762 return SPEED_25000; 2763 case BNXT_LINK_SPEED_40GB: 2764 return SPEED_40000; 2765 case BNXT_LINK_SPEED_50GB: 2766 case BNXT_LINK_SPEED_50GB_PAM4: 2767 return SPEED_50000; 2768 case BNXT_LINK_SPEED_100GB: 2769 case BNXT_LINK_SPEED_100GB_PAM4: 2770 case BNXT_LINK_SPEED_100GB_PAM4_112: 2771 return SPEED_100000; 2772 case BNXT_LINK_SPEED_200GB: 2773 case BNXT_LINK_SPEED_200GB_PAM4: 2774 case BNXT_LINK_SPEED_200GB_PAM4_112: 2775 return SPEED_200000; 2776 case BNXT_LINK_SPEED_400GB: 2777 case BNXT_LINK_SPEED_400GB_PAM4: 2778 case BNXT_LINK_SPEED_400GB_PAM4_112: 2779 return SPEED_400000; 2780 default: 2781 return SPEED_UNKNOWN; 2782 } 2783 } 2784 2785 static void bnxt_get_default_speeds(struct ethtool_link_ksettings *lk_ksettings, 2786 struct bnxt_link_info *link_info) 2787 { 2788 struct ethtool_link_settings *base = &lk_ksettings->base; 2789 2790 if (link_info->link_state == BNXT_LINK_STATE_UP) { 2791 base->speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 2792 base->duplex = DUPLEX_HALF; 2793 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2794 base->duplex = DUPLEX_FULL; 2795 lk_ksettings->lanes = link_info->active_lanes; 2796 } else if (!link_info->autoneg) { 2797 base->speed = bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 2798 base->duplex = DUPLEX_HALF; 2799 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 2800 base->duplex = DUPLEX_FULL; 2801 } 2802 } 2803 2804 static int bnxt_get_link_ksettings(struct net_device *dev, 2805 struct ethtool_link_ksettings *lk_ksettings) 2806 { 2807 struct ethtool_link_settings *base = &lk_ksettings->base; 2808 enum ethtool_link_mode_bit_indices link_mode; 2809 struct bnxt *bp = netdev_priv(dev); 2810 struct bnxt_link_info *link_info; 2811 enum bnxt_media_type media; 2812 2813 ethtool_link_ksettings_zero_link_mode(lk_ksettings, lp_advertising); 2814 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 2815 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 2816 base->duplex = DUPLEX_UNKNOWN; 2817 base->speed = SPEED_UNKNOWN; 2818 link_info = &bp->link_info; 2819 2820 mutex_lock(&bp->link_lock); 2821 bnxt_get_ethtool_modes(link_info, lk_ksettings); 2822 media = bnxt_get_media(link_info); 2823 bnxt_get_all_ethtool_support_speeds(link_info, media, lk_ksettings); 2824 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings); 2825 link_mode = bnxt_get_link_mode(link_info); 2826 if (link_mode != BNXT_LINK_MODE_UNKNOWN) 2827 ethtool_params_from_link_mode(lk_ksettings, link_mode); 2828 else 2829 bnxt_get_default_speeds(lk_ksettings, link_info); 2830 2831 if (link_info->autoneg) { 2832 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings); 2833 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2834 lk_ksettings->link_modes.advertising); 2835 base->autoneg = AUTONEG_ENABLE; 2836 bnxt_get_all_ethtool_adv_speeds(link_info, media, lk_ksettings); 2837 if (link_info->phy_link_status == BNXT_LINK_LINK) 2838 bnxt_get_all_ethtool_lp_speeds(link_info, media, 2839 lk_ksettings); 2840 } else { 2841 base->autoneg = AUTONEG_DISABLE; 2842 } 2843 2844 base->port = PORT_NONE; 2845 if (media == BNXT_MEDIA_TP) { 2846 base->port = PORT_TP; 2847 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2848 lk_ksettings->link_modes.supported); 2849 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2850 lk_ksettings->link_modes.advertising); 2851 } else if (media == BNXT_MEDIA_KR) { 2852 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, 2853 lk_ksettings->link_modes.supported); 2854 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, 2855 lk_ksettings->link_modes.advertising); 2856 } else { 2857 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 2858 lk_ksettings->link_modes.supported); 2859 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 2860 lk_ksettings->link_modes.advertising); 2861 2862 if (media == BNXT_MEDIA_CR) 2863 base->port = PORT_DA; 2864 else 2865 base->port = PORT_FIBRE; 2866 } 2867 base->phy_address = link_info->phy_addr; 2868 mutex_unlock(&bp->link_lock); 2869 2870 return 0; 2871 } 2872 2873 static int 2874 bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed, u32 lanes) 2875 { 2876 struct bnxt *bp = netdev_priv(dev); 2877 struct bnxt_link_info *link_info = &bp->link_info; 2878 u16 support_pam4_spds = link_info->support_pam4_speeds; 2879 u16 support_spds2 = link_info->support_speeds2; 2880 u16 support_spds = link_info->support_speeds; 2881 u8 sig_mode = BNXT_SIG_MODE_NRZ; 2882 u32 lanes_needed = 1; 2883 u16 fw_speed = 0; 2884 2885 switch (ethtool_speed) { 2886 case SPEED_100: 2887 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 2888 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB; 2889 break; 2890 case SPEED_1000: 2891 if ((support_spds & BNXT_LINK_SPEED_MSK_1GB) || 2892 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_1GB)) 2893 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 2894 break; 2895 case SPEED_2500: 2896 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 2897 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB; 2898 break; 2899 case SPEED_10000: 2900 if ((support_spds & BNXT_LINK_SPEED_MSK_10GB) || 2901 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_10GB)) 2902 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 2903 break; 2904 case SPEED_20000: 2905 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) { 2906 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB; 2907 lanes_needed = 2; 2908 } 2909 break; 2910 case SPEED_25000: 2911 if ((support_spds & BNXT_LINK_SPEED_MSK_25GB) || 2912 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_25GB)) 2913 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 2914 break; 2915 case SPEED_40000: 2916 if ((support_spds & BNXT_LINK_SPEED_MSK_40GB) || 2917 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_40GB)) { 2918 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 2919 lanes_needed = 4; 2920 } 2921 break; 2922 case SPEED_50000: 2923 if (((support_spds & BNXT_LINK_SPEED_MSK_50GB) || 2924 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB)) && 2925 lanes != 1) { 2926 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 2927 lanes_needed = 2; 2928 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) { 2929 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB; 2930 sig_mode = BNXT_SIG_MODE_PAM4; 2931 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB_PAM4) { 2932 fw_speed = BNXT_LINK_SPEED_50GB_PAM4; 2933 sig_mode = BNXT_SIG_MODE_PAM4; 2934 } 2935 break; 2936 case SPEED_100000: 2937 if (((support_spds & BNXT_LINK_SPEED_MSK_100GB) || 2938 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB)) && 2939 lanes != 2 && lanes != 1) { 2940 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB; 2941 lanes_needed = 4; 2942 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) { 2943 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB; 2944 sig_mode = BNXT_SIG_MODE_PAM4; 2945 lanes_needed = 2; 2946 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4) && 2947 lanes != 1) { 2948 fw_speed = BNXT_LINK_SPEED_100GB_PAM4; 2949 sig_mode = BNXT_SIG_MODE_PAM4; 2950 lanes_needed = 2; 2951 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112) { 2952 fw_speed = BNXT_LINK_SPEED_100GB_PAM4_112; 2953 sig_mode = BNXT_SIG_MODE_PAM4_112; 2954 } 2955 break; 2956 case SPEED_200000: 2957 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) { 2958 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB; 2959 sig_mode = BNXT_SIG_MODE_PAM4; 2960 lanes_needed = 4; 2961 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4) && 2962 lanes != 2) { 2963 fw_speed = BNXT_LINK_SPEED_200GB_PAM4; 2964 sig_mode = BNXT_SIG_MODE_PAM4; 2965 lanes_needed = 4; 2966 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112) { 2967 fw_speed = BNXT_LINK_SPEED_200GB_PAM4_112; 2968 sig_mode = BNXT_SIG_MODE_PAM4_112; 2969 lanes_needed = 2; 2970 } 2971 break; 2972 case SPEED_400000: 2973 if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4) && 2974 lanes != 4) { 2975 fw_speed = BNXT_LINK_SPEED_400GB_PAM4; 2976 sig_mode = BNXT_SIG_MODE_PAM4; 2977 lanes_needed = 8; 2978 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112) { 2979 fw_speed = BNXT_LINK_SPEED_400GB_PAM4_112; 2980 sig_mode = BNXT_SIG_MODE_PAM4_112; 2981 lanes_needed = 4; 2982 } 2983 break; 2984 } 2985 2986 if (!fw_speed) { 2987 netdev_err(dev, "unsupported speed!\n"); 2988 return -EINVAL; 2989 } 2990 2991 if (lanes && lanes != lanes_needed) { 2992 netdev_err(dev, "unsupported number of lanes for speed\n"); 2993 return -EINVAL; 2994 } 2995 2996 if (link_info->req_link_speed == fw_speed && 2997 link_info->req_signal_mode == sig_mode && 2998 link_info->autoneg == 0) 2999 return -EALREADY; 3000 3001 link_info->req_link_speed = fw_speed; 3002 link_info->req_signal_mode = sig_mode; 3003 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 3004 link_info->autoneg = 0; 3005 link_info->advertising = 0; 3006 link_info->advertising_pam4 = 0; 3007 3008 return 0; 3009 } 3010 3011 u16 bnxt_get_fw_auto_link_speeds(const unsigned long *mode) 3012 { 3013 u16 fw_speed_mask = 0; 3014 3015 if (linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode) || 3016 linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mode)) 3017 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 3018 3019 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode) || 3020 linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, mode)) 3021 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 3022 3023 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode)) 3024 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 3025 3026 if (linkmode_test_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode)) 3027 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 3028 3029 return fw_speed_mask; 3030 } 3031 3032 static int bnxt_set_link_ksettings(struct net_device *dev, 3033 const struct ethtool_link_ksettings *lk_ksettings) 3034 { 3035 struct bnxt *bp = netdev_priv(dev); 3036 struct bnxt_link_info *link_info = &bp->link_info; 3037 const struct ethtool_link_settings *base = &lk_ksettings->base; 3038 bool set_pause = false; 3039 u32 speed, lanes = 0; 3040 int rc = 0; 3041 3042 if (!BNXT_PHY_CFG_ABLE(bp)) 3043 return -EOPNOTSUPP; 3044 3045 mutex_lock(&bp->link_lock); 3046 if (base->autoneg == AUTONEG_ENABLE) { 3047 bnxt_set_ethtool_speeds(link_info, 3048 lk_ksettings->link_modes.advertising); 3049 link_info->autoneg |= BNXT_AUTONEG_SPEED; 3050 if (!link_info->advertising && !link_info->advertising_pam4) { 3051 link_info->advertising = link_info->support_auto_speeds; 3052 link_info->advertising_pam4 = 3053 link_info->support_pam4_auto_speeds; 3054 } 3055 /* any change to autoneg will cause link change, therefore the 3056 * driver should put back the original pause setting in autoneg 3057 */ 3058 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 3059 set_pause = true; 3060 } else { 3061 u8 phy_type = link_info->phy_type; 3062 3063 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 3064 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 3065 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 3066 netdev_err(dev, "10GBase-T devices must autoneg\n"); 3067 rc = -EINVAL; 3068 goto set_setting_exit; 3069 } 3070 if (base->duplex == DUPLEX_HALF) { 3071 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 3072 rc = -EINVAL; 3073 goto set_setting_exit; 3074 } 3075 speed = base->speed; 3076 lanes = lk_ksettings->lanes; 3077 rc = bnxt_force_link_speed(dev, speed, lanes); 3078 if (rc) { 3079 if (rc == -EALREADY) 3080 rc = 0; 3081 goto set_setting_exit; 3082 } 3083 } 3084 3085 if (netif_running(dev)) 3086 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 3087 3088 set_setting_exit: 3089 mutex_unlock(&bp->link_lock); 3090 return rc; 3091 } 3092 3093 static int bnxt_get_fecparam(struct net_device *dev, 3094 struct ethtool_fecparam *fec) 3095 { 3096 struct bnxt *bp = netdev_priv(dev); 3097 struct bnxt_link_info *link_info; 3098 u8 active_fec; 3099 u16 fec_cfg; 3100 3101 link_info = &bp->link_info; 3102 fec_cfg = link_info->fec_cfg; 3103 active_fec = link_info->active_fec_sig_mode & 3104 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK; 3105 if (fec_cfg & BNXT_FEC_NONE) { 3106 fec->fec = ETHTOOL_FEC_NONE; 3107 fec->active_fec = ETHTOOL_FEC_NONE; 3108 return 0; 3109 } 3110 if (fec_cfg & BNXT_FEC_AUTONEG) 3111 fec->fec |= ETHTOOL_FEC_AUTO; 3112 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 3113 fec->fec |= ETHTOOL_FEC_BASER; 3114 if (fec_cfg & BNXT_FEC_ENC_RS) 3115 fec->fec |= ETHTOOL_FEC_RS; 3116 if (fec_cfg & BNXT_FEC_ENC_LLRS) 3117 fec->fec |= ETHTOOL_FEC_LLRS; 3118 3119 switch (active_fec) { 3120 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE: 3121 fec->active_fec |= ETHTOOL_FEC_BASER; 3122 break; 3123 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE: 3124 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE: 3125 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE: 3126 fec->active_fec |= ETHTOOL_FEC_RS; 3127 break; 3128 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE: 3129 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE: 3130 fec->active_fec |= ETHTOOL_FEC_LLRS; 3131 break; 3132 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE: 3133 fec->active_fec |= ETHTOOL_FEC_OFF; 3134 break; 3135 } 3136 return 0; 3137 } 3138 3139 static void bnxt_get_fec_stats(struct net_device *dev, 3140 struct ethtool_fec_stats *fec_stats) 3141 { 3142 struct bnxt *bp = netdev_priv(dev); 3143 u64 *rx; 3144 3145 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 3146 return; 3147 3148 rx = bp->rx_port_stats_ext.sw_stats; 3149 fec_stats->corrected_bits.total = 3150 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits)); 3151 3152 if (bp->fw_rx_stats_ext_size <= BNXT_RX_STATS_EXT_NUM_LEGACY) 3153 return; 3154 3155 fec_stats->corrected_blocks.total = 3156 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)); 3157 fec_stats->uncorrectable_blocks.total = 3158 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_uncorrectable_blocks)); 3159 } 3160 3161 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info, 3162 u32 fec) 3163 { 3164 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE; 3165 3166 if (fec & ETHTOOL_FEC_BASER) 3167 fw_fec |= BNXT_FEC_BASE_R_ON(link_info); 3168 else if (fec & ETHTOOL_FEC_RS) 3169 fw_fec |= BNXT_FEC_RS_ON(link_info); 3170 else if (fec & ETHTOOL_FEC_LLRS) 3171 fw_fec |= BNXT_FEC_LLRS_ON; 3172 return fw_fec; 3173 } 3174 3175 static int bnxt_set_fecparam(struct net_device *dev, 3176 struct ethtool_fecparam *fecparam) 3177 { 3178 struct hwrm_port_phy_cfg_input *req; 3179 struct bnxt *bp = netdev_priv(dev); 3180 struct bnxt_link_info *link_info; 3181 u32 new_cfg, fec = fecparam->fec; 3182 u16 fec_cfg; 3183 int rc; 3184 3185 link_info = &bp->link_info; 3186 fec_cfg = link_info->fec_cfg; 3187 if (fec_cfg & BNXT_FEC_NONE) 3188 return -EOPNOTSUPP; 3189 3190 if (fec & ETHTOOL_FEC_OFF) { 3191 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE | 3192 BNXT_FEC_ALL_OFF(link_info); 3193 goto apply_fec; 3194 } 3195 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) || 3196 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) || 3197 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) || 3198 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP))) 3199 return -EINVAL; 3200 3201 if (fec & ETHTOOL_FEC_AUTO) { 3202 if (!link_info->autoneg) 3203 return -EINVAL; 3204 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE; 3205 } else { 3206 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec); 3207 } 3208 3209 apply_fec: 3210 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 3211 if (rc) 3212 return rc; 3213 req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 3214 rc = hwrm_req_send(bp, req); 3215 /* update current settings */ 3216 if (!rc) { 3217 mutex_lock(&bp->link_lock); 3218 bnxt_update_link(bp, false); 3219 mutex_unlock(&bp->link_lock); 3220 } 3221 return rc; 3222 } 3223 3224 static void bnxt_get_pauseparam(struct net_device *dev, 3225 struct ethtool_pauseparam *epause) 3226 { 3227 struct bnxt *bp = netdev_priv(dev); 3228 struct bnxt_link_info *link_info = &bp->link_info; 3229 3230 if (BNXT_VF(bp)) 3231 return; 3232 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 3233 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 3234 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 3235 } 3236 3237 static void bnxt_get_pause_stats(struct net_device *dev, 3238 struct ethtool_pause_stats *epstat) 3239 { 3240 struct bnxt *bp = netdev_priv(dev); 3241 u64 *rx, *tx; 3242 3243 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 3244 return; 3245 3246 rx = bp->port_stats.sw_stats; 3247 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 3248 3249 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames); 3250 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames); 3251 } 3252 3253 static int bnxt_set_pauseparam(struct net_device *dev, 3254 struct ethtool_pauseparam *epause) 3255 { 3256 int rc = 0; 3257 struct bnxt *bp = netdev_priv(dev); 3258 struct bnxt_link_info *link_info = &bp->link_info; 3259 3260 if (!BNXT_PHY_CFG_ABLE(bp) || (bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 3261 return -EOPNOTSUPP; 3262 3263 mutex_lock(&bp->link_lock); 3264 if (epause->autoneg) { 3265 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 3266 rc = -EINVAL; 3267 goto pause_exit; 3268 } 3269 3270 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 3271 link_info->req_flow_ctrl = 0; 3272 } else { 3273 /* when transition from auto pause to force pause, 3274 * force a link change 3275 */ 3276 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 3277 link_info->force_link_chng = true; 3278 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 3279 link_info->req_flow_ctrl = 0; 3280 } 3281 if (epause->rx_pause) 3282 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 3283 3284 if (epause->tx_pause) 3285 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 3286 3287 if (netif_running(dev)) 3288 rc = bnxt_hwrm_set_pause(bp); 3289 3290 pause_exit: 3291 mutex_unlock(&bp->link_lock); 3292 return rc; 3293 } 3294 3295 static u32 bnxt_get_link(struct net_device *dev) 3296 { 3297 struct bnxt *bp = netdev_priv(dev); 3298 3299 /* TODO: handle MF, VF, driver close case */ 3300 return BNXT_LINK_IS_UP(bp); 3301 } 3302 3303 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp, 3304 struct hwrm_nvm_get_dev_info_output *nvm_dev_info) 3305 { 3306 struct hwrm_nvm_get_dev_info_output *resp; 3307 struct hwrm_nvm_get_dev_info_input *req; 3308 int rc; 3309 3310 if (BNXT_VF(bp)) 3311 return -EOPNOTSUPP; 3312 3313 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO); 3314 if (rc) 3315 return rc; 3316 3317 resp = hwrm_req_hold(bp, req); 3318 rc = hwrm_req_send(bp, req); 3319 if (!rc) 3320 memcpy(nvm_dev_info, resp, sizeof(*resp)); 3321 hwrm_req_drop(bp, req); 3322 return rc; 3323 } 3324 3325 static void bnxt_print_admin_err(struct bnxt *bp) 3326 { 3327 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 3328 } 3329 3330 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 3331 u16 ext, u16 *index, u32 *item_length, 3332 u32 *data_length); 3333 3334 int bnxt_flash_nvram(struct net_device *dev, u16 dir_type, 3335 u16 dir_ordinal, u16 dir_ext, u16 dir_attr, 3336 u32 dir_item_len, const u8 *data, 3337 size_t data_len) 3338 { 3339 struct bnxt *bp = netdev_priv(dev); 3340 struct hwrm_nvm_write_input *req; 3341 int rc; 3342 3343 rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE); 3344 if (rc) 3345 return rc; 3346 3347 if (data_len && data) { 3348 dma_addr_t dma_handle; 3349 u8 *kmem; 3350 3351 kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle); 3352 if (!kmem) { 3353 hwrm_req_drop(bp, req); 3354 return -ENOMEM; 3355 } 3356 3357 req->dir_data_length = cpu_to_le32(data_len); 3358 3359 memcpy(kmem, data, data_len); 3360 req->host_src_addr = cpu_to_le64(dma_handle); 3361 } 3362 3363 hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout); 3364 req->dir_type = cpu_to_le16(dir_type); 3365 req->dir_ordinal = cpu_to_le16(dir_ordinal); 3366 req->dir_ext = cpu_to_le16(dir_ext); 3367 req->dir_attr = cpu_to_le16(dir_attr); 3368 req->dir_item_length = cpu_to_le32(dir_item_len); 3369 rc = hwrm_req_send(bp, req); 3370 3371 if (rc == -EACCES) 3372 bnxt_print_admin_err(bp); 3373 return rc; 3374 } 3375 3376 int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type, 3377 u8 self_reset, u8 flags) 3378 { 3379 struct bnxt *bp = netdev_priv(dev); 3380 struct hwrm_fw_reset_input *req; 3381 int rc; 3382 3383 if (!bnxt_hwrm_reset_permitted(bp)) { 3384 netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver"); 3385 return -EPERM; 3386 } 3387 3388 rc = hwrm_req_init(bp, req, HWRM_FW_RESET); 3389 if (rc) 3390 return rc; 3391 3392 req->embedded_proc_type = proc_type; 3393 req->selfrst_status = self_reset; 3394 req->flags = flags; 3395 3396 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) { 3397 rc = hwrm_req_send_silent(bp, req); 3398 } else { 3399 rc = hwrm_req_send(bp, req); 3400 if (rc == -EACCES) 3401 bnxt_print_admin_err(bp); 3402 } 3403 return rc; 3404 } 3405 3406 static int bnxt_firmware_reset(struct net_device *dev, 3407 enum bnxt_nvm_directory_type dir_type) 3408 { 3409 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE; 3410 u8 proc_type, flags = 0; 3411 3412 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 3413 /* (e.g. when firmware isn't already running) */ 3414 switch (dir_type) { 3415 case BNX_DIR_TYPE_CHIMP_PATCH: 3416 case BNX_DIR_TYPE_BOOTCODE: 3417 case BNX_DIR_TYPE_BOOTCODE_2: 3418 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 3419 /* Self-reset ChiMP upon next PCIe reset: */ 3420 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 3421 break; 3422 case BNX_DIR_TYPE_APE_FW: 3423 case BNX_DIR_TYPE_APE_PATCH: 3424 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 3425 /* Self-reset APE upon next PCIe reset: */ 3426 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 3427 break; 3428 case BNX_DIR_TYPE_KONG_FW: 3429 case BNX_DIR_TYPE_KONG_PATCH: 3430 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 3431 break; 3432 case BNX_DIR_TYPE_BONO_FW: 3433 case BNX_DIR_TYPE_BONO_PATCH: 3434 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 3435 break; 3436 default: 3437 return -EINVAL; 3438 } 3439 3440 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags); 3441 } 3442 3443 static int bnxt_firmware_reset_chip(struct net_device *dev) 3444 { 3445 struct bnxt *bp = netdev_priv(dev); 3446 u8 flags = 0; 3447 3448 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 3449 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 3450 3451 return bnxt_hwrm_firmware_reset(dev, 3452 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP, 3453 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP, 3454 flags); 3455 } 3456 3457 static int bnxt_firmware_reset_ap(struct net_device *dev) 3458 { 3459 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP, 3460 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE, 3461 0); 3462 } 3463 3464 static int bnxt_flash_firmware(struct net_device *dev, 3465 u16 dir_type, 3466 const u8 *fw_data, 3467 size_t fw_size) 3468 { 3469 int rc = 0; 3470 u16 code_type; 3471 u32 stored_crc; 3472 u32 calculated_crc; 3473 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 3474 3475 switch (dir_type) { 3476 case BNX_DIR_TYPE_BOOTCODE: 3477 case BNX_DIR_TYPE_BOOTCODE_2: 3478 code_type = CODE_BOOT; 3479 break; 3480 case BNX_DIR_TYPE_CHIMP_PATCH: 3481 code_type = CODE_CHIMP_PATCH; 3482 break; 3483 case BNX_DIR_TYPE_APE_FW: 3484 code_type = CODE_MCTP_PASSTHRU; 3485 break; 3486 case BNX_DIR_TYPE_APE_PATCH: 3487 code_type = CODE_APE_PATCH; 3488 break; 3489 case BNX_DIR_TYPE_KONG_FW: 3490 code_type = CODE_KONG_FW; 3491 break; 3492 case BNX_DIR_TYPE_KONG_PATCH: 3493 code_type = CODE_KONG_PATCH; 3494 break; 3495 case BNX_DIR_TYPE_BONO_FW: 3496 code_type = CODE_BONO_FW; 3497 break; 3498 case BNX_DIR_TYPE_BONO_PATCH: 3499 code_type = CODE_BONO_PATCH; 3500 break; 3501 default: 3502 netdev_err(dev, "Unsupported directory entry type: %u\n", 3503 dir_type); 3504 return -EINVAL; 3505 } 3506 if (fw_size < sizeof(struct bnxt_fw_header)) { 3507 netdev_err(dev, "Invalid firmware file size: %u\n", 3508 (unsigned int)fw_size); 3509 return -EINVAL; 3510 } 3511 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 3512 netdev_err(dev, "Invalid firmware signature: %08X\n", 3513 le32_to_cpu(header->signature)); 3514 return -EINVAL; 3515 } 3516 if (header->code_type != code_type) { 3517 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 3518 code_type, header->code_type); 3519 return -EINVAL; 3520 } 3521 if (header->device != DEVICE_CUMULUS_FAMILY) { 3522 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 3523 DEVICE_CUMULUS_FAMILY, header->device); 3524 return -EINVAL; 3525 } 3526 /* Confirm the CRC32 checksum of the file: */ 3527 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 3528 sizeof(stored_crc))); 3529 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 3530 if (calculated_crc != stored_crc) { 3531 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 3532 (unsigned long)stored_crc, 3533 (unsigned long)calculated_crc); 3534 return -EINVAL; 3535 } 3536 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3537 0, 0, 0, fw_data, fw_size); 3538 if (rc == 0) /* Firmware update successful */ 3539 rc = bnxt_firmware_reset(dev, dir_type); 3540 3541 return rc; 3542 } 3543 3544 static int bnxt_flash_microcode(struct net_device *dev, 3545 u16 dir_type, 3546 const u8 *fw_data, 3547 size_t fw_size) 3548 { 3549 struct bnxt_ucode_trailer *trailer; 3550 u32 calculated_crc; 3551 u32 stored_crc; 3552 int rc = 0; 3553 3554 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 3555 netdev_err(dev, "Invalid microcode file size: %u\n", 3556 (unsigned int)fw_size); 3557 return -EINVAL; 3558 } 3559 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 3560 sizeof(*trailer))); 3561 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 3562 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 3563 le32_to_cpu(trailer->sig)); 3564 return -EINVAL; 3565 } 3566 if (le16_to_cpu(trailer->dir_type) != dir_type) { 3567 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 3568 dir_type, le16_to_cpu(trailer->dir_type)); 3569 return -EINVAL; 3570 } 3571 if (le16_to_cpu(trailer->trailer_length) < 3572 sizeof(struct bnxt_ucode_trailer)) { 3573 netdev_err(dev, "Invalid microcode trailer length: %d\n", 3574 le16_to_cpu(trailer->trailer_length)); 3575 return -EINVAL; 3576 } 3577 3578 /* Confirm the CRC32 checksum of the file: */ 3579 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 3580 sizeof(stored_crc))); 3581 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 3582 if (calculated_crc != stored_crc) { 3583 netdev_err(dev, 3584 "CRC32 (%08lX) does not match calculated: %08lX\n", 3585 (unsigned long)stored_crc, 3586 (unsigned long)calculated_crc); 3587 return -EINVAL; 3588 } 3589 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3590 0, 0, 0, fw_data, fw_size); 3591 3592 return rc; 3593 } 3594 3595 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 3596 { 3597 switch (dir_type) { 3598 case BNX_DIR_TYPE_CHIMP_PATCH: 3599 case BNX_DIR_TYPE_BOOTCODE: 3600 case BNX_DIR_TYPE_BOOTCODE_2: 3601 case BNX_DIR_TYPE_APE_FW: 3602 case BNX_DIR_TYPE_APE_PATCH: 3603 case BNX_DIR_TYPE_KONG_FW: 3604 case BNX_DIR_TYPE_KONG_PATCH: 3605 case BNX_DIR_TYPE_BONO_FW: 3606 case BNX_DIR_TYPE_BONO_PATCH: 3607 return true; 3608 } 3609 3610 return false; 3611 } 3612 3613 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 3614 { 3615 switch (dir_type) { 3616 case BNX_DIR_TYPE_AVS: 3617 case BNX_DIR_TYPE_EXP_ROM_MBA: 3618 case BNX_DIR_TYPE_PCIE: 3619 case BNX_DIR_TYPE_TSCF_UCODE: 3620 case BNX_DIR_TYPE_EXT_PHY: 3621 case BNX_DIR_TYPE_CCM: 3622 case BNX_DIR_TYPE_ISCSI_BOOT: 3623 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 3624 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 3625 return true; 3626 } 3627 3628 return false; 3629 } 3630 3631 static bool bnxt_dir_type_is_executable(u16 dir_type) 3632 { 3633 return bnxt_dir_type_is_ape_bin_format(dir_type) || 3634 bnxt_dir_type_is_other_exec_format(dir_type); 3635 } 3636 3637 static int bnxt_flash_firmware_from_file(struct net_device *dev, 3638 u16 dir_type, 3639 const char *filename) 3640 { 3641 const struct firmware *fw; 3642 int rc; 3643 3644 rc = request_firmware(&fw, filename, &dev->dev); 3645 if (rc != 0) { 3646 netdev_err(dev, "Error %d requesting firmware file: %s\n", 3647 rc, filename); 3648 return rc; 3649 } 3650 if (bnxt_dir_type_is_ape_bin_format(dir_type)) 3651 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 3652 else if (bnxt_dir_type_is_other_exec_format(dir_type)) 3653 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 3654 else 3655 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3656 0, 0, 0, fw->data, fw->size); 3657 release_firmware(fw); 3658 return rc; 3659 } 3660 3661 #define MSG_INTEGRITY_ERR "PKG install error : Data integrity on NVM" 3662 #define MSG_INVALID_PKG "PKG install error : Invalid package" 3663 #define MSG_AUTHENTICATION_ERR "PKG install error : Authentication error" 3664 #define MSG_INVALID_DEV "PKG install error : Invalid device" 3665 #define MSG_INTERNAL_ERR "PKG install error : Internal error" 3666 #define MSG_NO_PKG_UPDATE_AREA_ERR "PKG update area not created in nvram" 3667 #define MSG_NO_SPACE_ERR "PKG insufficient update area in nvram" 3668 #define MSG_RESIZE_UPDATE_ERR "Resize UPDATE entry error" 3669 #define MSG_ANTI_ROLLBACK_ERR "HWRM_NVM_INSTALL_UPDATE failure due to Anti-rollback detected" 3670 #define MSG_GENERIC_FAILURE_ERR "HWRM_NVM_INSTALL_UPDATE failure" 3671 3672 static int nvm_update_err_to_stderr(struct net_device *dev, u8 result, 3673 struct netlink_ext_ack *extack) 3674 { 3675 switch (result) { 3676 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER: 3677 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER: 3678 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR: 3679 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR: 3680 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND: 3681 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED: 3682 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTEGRITY_ERR); 3683 return -EINVAL; 3684 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE: 3685 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER: 3686 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE: 3687 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM: 3688 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH: 3689 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST: 3690 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER: 3691 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM: 3692 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM: 3693 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH: 3694 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE: 3695 case NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM: 3696 case NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM: 3697 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_PKG); 3698 return -ENOPKG; 3699 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR: 3700 BNXT_NVM_ERR_MSG(dev, extack, MSG_AUTHENTICATION_ERR); 3701 return -EPERM; 3702 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV: 3703 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID: 3704 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR: 3705 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID: 3706 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM: 3707 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_DEV); 3708 return -EOPNOTSUPP; 3709 default: 3710 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTERNAL_ERR); 3711 return -EIO; 3712 } 3713 } 3714 3715 #define BNXT_PKG_DMA_SIZE 0x40000 3716 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE)) 3717 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST)) 3718 3719 static int bnxt_resize_update_entry(struct net_device *dev, size_t fw_size, 3720 struct netlink_ext_ack *extack) 3721 { 3722 u32 item_len; 3723 int rc; 3724 3725 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 3726 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, NULL, 3727 &item_len, NULL); 3728 if (rc) { 3729 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 3730 return rc; 3731 } 3732 3733 if (fw_size > item_len) { 3734 rc = bnxt_flash_nvram(dev, BNX_DIR_TYPE_UPDATE, 3735 BNX_DIR_ORDINAL_FIRST, 0, 1, 3736 round_up(fw_size, 4096), NULL, 0); 3737 if (rc) { 3738 BNXT_NVM_ERR_MSG(dev, extack, MSG_RESIZE_UPDATE_ERR); 3739 return rc; 3740 } 3741 } 3742 return 0; 3743 } 3744 3745 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw, 3746 u32 install_type, struct netlink_ext_ack *extack) 3747 { 3748 struct hwrm_nvm_install_update_input *install; 3749 struct hwrm_nvm_install_update_output *resp; 3750 struct hwrm_nvm_modify_input *modify; 3751 struct bnxt *bp = netdev_priv(dev); 3752 bool defrag_attempted = false; 3753 dma_addr_t dma_handle; 3754 u8 *kmem = NULL; 3755 u32 modify_len; 3756 u32 item_len; 3757 u8 cmd_err; 3758 u16 index; 3759 int rc; 3760 3761 /* resize before flashing larger image than available space */ 3762 rc = bnxt_resize_update_entry(dev, fw->size, extack); 3763 if (rc) 3764 return rc; 3765 3766 bnxt_hwrm_fw_set_time(bp); 3767 3768 rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY); 3769 if (rc) 3770 return rc; 3771 3772 /* Try allocating a large DMA buffer first. Older fw will 3773 * cause excessive NVRAM erases when using small blocks. 3774 */ 3775 modify_len = roundup_pow_of_two(fw->size); 3776 modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE); 3777 while (1) { 3778 kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle); 3779 if (!kmem && modify_len > PAGE_SIZE) 3780 modify_len /= 2; 3781 else 3782 break; 3783 } 3784 if (!kmem) { 3785 hwrm_req_drop(bp, modify); 3786 return -ENOMEM; 3787 } 3788 3789 rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE); 3790 if (rc) { 3791 hwrm_req_drop(bp, modify); 3792 return rc; 3793 } 3794 3795 hwrm_req_timeout(bp, modify, bp->hwrm_cmd_max_timeout); 3796 hwrm_req_timeout(bp, install, bp->hwrm_cmd_max_timeout); 3797 3798 hwrm_req_hold(bp, modify); 3799 modify->host_src_addr = cpu_to_le64(dma_handle); 3800 3801 resp = hwrm_req_hold(bp, install); 3802 if ((install_type & 0xffff) == 0) 3803 install_type >>= 16; 3804 install->install_type = cpu_to_le32(install_type); 3805 3806 do { 3807 u32 copied = 0, len = modify_len; 3808 3809 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 3810 BNX_DIR_ORDINAL_FIRST, 3811 BNX_DIR_EXT_NONE, 3812 &index, &item_len, NULL); 3813 if (rc) { 3814 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 3815 break; 3816 } 3817 if (fw->size > item_len) { 3818 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_SPACE_ERR); 3819 rc = -EFBIG; 3820 break; 3821 } 3822 3823 modify->dir_idx = cpu_to_le16(index); 3824 3825 if (fw->size > modify_len) 3826 modify->flags = BNXT_NVM_MORE_FLAG; 3827 while (copied < fw->size) { 3828 u32 balance = fw->size - copied; 3829 3830 if (balance <= modify_len) { 3831 len = balance; 3832 if (copied) 3833 modify->flags |= BNXT_NVM_LAST_FLAG; 3834 } 3835 memcpy(kmem, fw->data + copied, len); 3836 modify->len = cpu_to_le32(len); 3837 modify->offset = cpu_to_le32(copied); 3838 rc = hwrm_req_send(bp, modify); 3839 if (rc) 3840 goto pkg_abort; 3841 copied += len; 3842 } 3843 3844 rc = hwrm_req_send_silent(bp, install); 3845 if (!rc) 3846 break; 3847 3848 if (defrag_attempted) { 3849 /* We have tried to defragment already in the previous 3850 * iteration. Return with the result for INSTALL_UPDATE 3851 */ 3852 break; 3853 } 3854 3855 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 3856 3857 switch (cmd_err) { 3858 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK: 3859 BNXT_NVM_ERR_MSG(dev, extack, MSG_ANTI_ROLLBACK_ERR); 3860 rc = -EALREADY; 3861 break; 3862 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR: 3863 install->flags = 3864 cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 3865 3866 rc = hwrm_req_send_silent(bp, install); 3867 if (!rc) 3868 break; 3869 3870 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 3871 3872 if (cmd_err == NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) { 3873 /* FW has cleared NVM area, driver will create 3874 * UPDATE directory and try the flash again 3875 */ 3876 defrag_attempted = true; 3877 install->flags = 0; 3878 rc = bnxt_flash_nvram(bp->dev, 3879 BNX_DIR_TYPE_UPDATE, 3880 BNX_DIR_ORDINAL_FIRST, 3881 0, 0, item_len, NULL, 0); 3882 if (!rc) 3883 break; 3884 } 3885 fallthrough; 3886 default: 3887 BNXT_NVM_ERR_MSG(dev, extack, MSG_GENERIC_FAILURE_ERR); 3888 } 3889 } while (defrag_attempted && !rc); 3890 3891 pkg_abort: 3892 hwrm_req_drop(bp, modify); 3893 hwrm_req_drop(bp, install); 3894 3895 if (resp->result) { 3896 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 3897 (s8)resp->result, (int)resp->problem_item); 3898 rc = nvm_update_err_to_stderr(dev, resp->result, extack); 3899 } 3900 if (rc == -EACCES) 3901 bnxt_print_admin_err(bp); 3902 return rc; 3903 } 3904 3905 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename, 3906 u32 install_type, struct netlink_ext_ack *extack) 3907 { 3908 const struct firmware *fw; 3909 int rc; 3910 3911 rc = request_firmware(&fw, filename, &dev->dev); 3912 if (rc != 0) { 3913 netdev_err(dev, "PKG error %d requesting file: %s\n", 3914 rc, filename); 3915 return rc; 3916 } 3917 3918 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type, extack); 3919 3920 release_firmware(fw); 3921 3922 return rc; 3923 } 3924 3925 static int bnxt_flash_device(struct net_device *dev, 3926 struct ethtool_flash *flash) 3927 { 3928 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 3929 netdev_err(dev, "flashdev not supported from a virtual function\n"); 3930 return -EINVAL; 3931 } 3932 3933 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 3934 flash->region > 0xffff) 3935 return bnxt_flash_package_from_file(dev, flash->data, 3936 flash->region, NULL); 3937 3938 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 3939 } 3940 3941 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 3942 { 3943 struct hwrm_nvm_get_dir_info_output *output; 3944 struct hwrm_nvm_get_dir_info_input *req; 3945 struct bnxt *bp = netdev_priv(dev); 3946 int rc; 3947 3948 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO); 3949 if (rc) 3950 return rc; 3951 3952 output = hwrm_req_hold(bp, req); 3953 rc = hwrm_req_send(bp, req); 3954 if (!rc) { 3955 *entries = le32_to_cpu(output->entries); 3956 *length = le32_to_cpu(output->entry_length); 3957 } 3958 hwrm_req_drop(bp, req); 3959 return rc; 3960 } 3961 3962 static int bnxt_get_eeprom_len(struct net_device *dev) 3963 { 3964 struct bnxt *bp = netdev_priv(dev); 3965 3966 if (BNXT_VF(bp)) 3967 return 0; 3968 3969 /* The -1 return value allows the entire 32-bit range of offsets to be 3970 * passed via the ethtool command-line utility. 3971 */ 3972 return -1; 3973 } 3974 3975 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 3976 { 3977 struct bnxt *bp = netdev_priv(dev); 3978 int rc; 3979 u32 dir_entries; 3980 u32 entry_length; 3981 u8 *buf; 3982 size_t buflen; 3983 dma_addr_t dma_handle; 3984 struct hwrm_nvm_get_dir_entries_input *req; 3985 3986 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 3987 if (rc != 0) 3988 return rc; 3989 3990 if (!dir_entries || !entry_length) 3991 return -EIO; 3992 3993 /* Insert 2 bytes of directory info (count and size of entries) */ 3994 if (len < 2) 3995 return -EINVAL; 3996 3997 *data++ = dir_entries; 3998 *data++ = entry_length; 3999 len -= 2; 4000 memset(data, 0xff, len); 4001 4002 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES); 4003 if (rc) 4004 return rc; 4005 4006 buflen = mul_u32_u32(dir_entries, entry_length); 4007 buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle); 4008 if (!buf) { 4009 hwrm_req_drop(bp, req); 4010 return -ENOMEM; 4011 } 4012 req->host_dest_addr = cpu_to_le64(dma_handle); 4013 4014 hwrm_req_hold(bp, req); /* hold the slice */ 4015 rc = hwrm_req_send(bp, req); 4016 if (rc == 0) 4017 memcpy(data, buf, len > buflen ? buflen : len); 4018 hwrm_req_drop(bp, req); 4019 return rc; 4020 } 4021 4022 int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 4023 u32 length, u8 *data) 4024 { 4025 struct bnxt *bp = netdev_priv(dev); 4026 int rc; 4027 u8 *buf; 4028 dma_addr_t dma_handle; 4029 struct hwrm_nvm_read_input *req; 4030 4031 if (!length) 4032 return -EINVAL; 4033 4034 rc = hwrm_req_init(bp, req, HWRM_NVM_READ); 4035 if (rc) 4036 return rc; 4037 4038 buf = hwrm_req_dma_slice(bp, req, length, &dma_handle); 4039 if (!buf) { 4040 hwrm_req_drop(bp, req); 4041 return -ENOMEM; 4042 } 4043 4044 req->host_dest_addr = cpu_to_le64(dma_handle); 4045 req->dir_idx = cpu_to_le16(index); 4046 req->offset = cpu_to_le32(offset); 4047 req->len = cpu_to_le32(length); 4048 4049 hwrm_req_hold(bp, req); /* hold the slice */ 4050 rc = hwrm_req_send(bp, req); 4051 if (rc == 0) 4052 memcpy(data, buf, length); 4053 hwrm_req_drop(bp, req); 4054 return rc; 4055 } 4056 4057 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 4058 u16 ext, u16 *index, u32 *item_length, 4059 u32 *data_length) 4060 { 4061 struct hwrm_nvm_find_dir_entry_output *output; 4062 struct hwrm_nvm_find_dir_entry_input *req; 4063 struct bnxt *bp = netdev_priv(dev); 4064 int rc; 4065 4066 rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY); 4067 if (rc) 4068 return rc; 4069 4070 req->enables = 0; 4071 req->dir_idx = 0; 4072 req->dir_type = cpu_to_le16(type); 4073 req->dir_ordinal = cpu_to_le16(ordinal); 4074 req->dir_ext = cpu_to_le16(ext); 4075 req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 4076 output = hwrm_req_hold(bp, req); 4077 rc = hwrm_req_send_silent(bp, req); 4078 if (rc == 0) { 4079 if (index) 4080 *index = le16_to_cpu(output->dir_idx); 4081 if (item_length) 4082 *item_length = le32_to_cpu(output->dir_item_length); 4083 if (data_length) 4084 *data_length = le32_to_cpu(output->dir_data_length); 4085 } 4086 hwrm_req_drop(bp, req); 4087 return rc; 4088 } 4089 4090 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 4091 { 4092 char *retval = NULL; 4093 char *p; 4094 char *value; 4095 int field = 0; 4096 4097 if (datalen < 1) 4098 return NULL; 4099 /* null-terminate the log data (removing last '\n'): */ 4100 data[datalen - 1] = 0; 4101 for (p = data; *p != 0; p++) { 4102 field = 0; 4103 retval = NULL; 4104 while (*p != 0 && *p != '\n') { 4105 value = p; 4106 while (*p != 0 && *p != '\t' && *p != '\n') 4107 p++; 4108 if (field == desired_field) 4109 retval = value; 4110 if (*p != '\t') 4111 break; 4112 *p = 0; 4113 field++; 4114 p++; 4115 } 4116 if (*p == 0) 4117 break; 4118 *p = 0; 4119 } 4120 return retval; 4121 } 4122 4123 int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size) 4124 { 4125 struct bnxt *bp = netdev_priv(dev); 4126 u16 index = 0; 4127 char *pkgver; 4128 u32 pkglen; 4129 u8 *pkgbuf; 4130 int rc; 4131 4132 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 4133 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 4134 &index, NULL, &pkglen); 4135 if (rc) 4136 return rc; 4137 4138 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 4139 if (!pkgbuf) { 4140 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 4141 pkglen); 4142 return -ENOMEM; 4143 } 4144 4145 rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf); 4146 if (rc) 4147 goto err; 4148 4149 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 4150 pkglen); 4151 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) 4152 strscpy(ver, pkgver, size); 4153 else 4154 rc = -ENOENT; 4155 4156 err: 4157 kfree(pkgbuf); 4158 4159 return rc; 4160 } 4161 4162 static void bnxt_get_pkgver(struct net_device *dev) 4163 { 4164 struct bnxt *bp = netdev_priv(dev); 4165 char buf[FW_VER_STR_LEN]; 4166 int len; 4167 4168 if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) { 4169 len = strlen(bp->fw_ver_str); 4170 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len, 4171 "/pkg %s", buf); 4172 } 4173 } 4174 4175 static int bnxt_get_eeprom(struct net_device *dev, 4176 struct ethtool_eeprom *eeprom, 4177 u8 *data) 4178 { 4179 u32 index; 4180 u32 offset; 4181 4182 if (eeprom->offset == 0) /* special offset value to get directory */ 4183 return bnxt_get_nvram_directory(dev, eeprom->len, data); 4184 4185 index = eeprom->offset >> 24; 4186 offset = eeprom->offset & 0xffffff; 4187 4188 if (index == 0) { 4189 netdev_err(dev, "unsupported index value: %d\n", index); 4190 return -EINVAL; 4191 } 4192 4193 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 4194 } 4195 4196 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 4197 { 4198 struct hwrm_nvm_erase_dir_entry_input *req; 4199 struct bnxt *bp = netdev_priv(dev); 4200 int rc; 4201 4202 rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY); 4203 if (rc) 4204 return rc; 4205 4206 req->dir_idx = cpu_to_le16(index); 4207 return hwrm_req_send(bp, req); 4208 } 4209 4210 static int bnxt_set_eeprom(struct net_device *dev, 4211 struct ethtool_eeprom *eeprom, 4212 u8 *data) 4213 { 4214 struct bnxt *bp = netdev_priv(dev); 4215 u8 index, dir_op; 4216 u16 type, ext, ordinal, attr; 4217 4218 if (!BNXT_PF(bp)) { 4219 netdev_err(dev, "NVM write not supported from a virtual function\n"); 4220 return -EINVAL; 4221 } 4222 4223 type = eeprom->magic >> 16; 4224 4225 if (type == 0xffff) { /* special value for directory operations */ 4226 index = eeprom->magic & 0xff; 4227 dir_op = eeprom->magic >> 8; 4228 if (index == 0) 4229 return -EINVAL; 4230 switch (dir_op) { 4231 case 0x0e: /* erase */ 4232 if (eeprom->offset != ~eeprom->magic) 4233 return -EINVAL; 4234 return bnxt_erase_nvram_directory(dev, index - 1); 4235 default: 4236 return -EINVAL; 4237 } 4238 } 4239 4240 /* Create or re-write an NVM item: */ 4241 if (bnxt_dir_type_is_executable(type)) 4242 return -EOPNOTSUPP; 4243 ext = eeprom->magic & 0xffff; 4244 ordinal = eeprom->offset >> 16; 4245 attr = eeprom->offset & 0xffff; 4246 4247 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data, 4248 eeprom->len); 4249 } 4250 4251 static int bnxt_set_eee(struct net_device *dev, struct ethtool_keee *edata) 4252 { 4253 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 4254 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp); 4255 struct bnxt *bp = netdev_priv(dev); 4256 struct ethtool_keee *eee = &bp->eee; 4257 struct bnxt_link_info *link_info = &bp->link_info; 4258 int rc = 0; 4259 4260 if (!BNXT_PHY_CFG_ABLE(bp)) 4261 return -EOPNOTSUPP; 4262 4263 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 4264 return -EOPNOTSUPP; 4265 4266 mutex_lock(&bp->link_lock); 4267 _bnxt_fw_to_linkmode(advertising, link_info->advertising); 4268 if (!edata->eee_enabled) 4269 goto eee_ok; 4270 4271 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 4272 netdev_warn(dev, "EEE requires autoneg\n"); 4273 rc = -EINVAL; 4274 goto eee_exit; 4275 } 4276 if (edata->tx_lpi_enabled) { 4277 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 4278 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 4279 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 4280 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 4281 rc = -EINVAL; 4282 goto eee_exit; 4283 } else if (!bp->lpi_tmr_hi) { 4284 edata->tx_lpi_timer = eee->tx_lpi_timer; 4285 } 4286 } 4287 if (linkmode_empty(edata->advertised)) { 4288 linkmode_and(edata->advertised, advertising, eee->supported); 4289 } else if (linkmode_andnot(tmp, edata->advertised, advertising)) { 4290 netdev_warn(dev, "EEE advertised must be a subset of autoneg advertised speeds\n"); 4291 rc = -EINVAL; 4292 goto eee_exit; 4293 } 4294 4295 linkmode_copy(eee->advertised, edata->advertised); 4296 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 4297 eee->tx_lpi_timer = edata->tx_lpi_timer; 4298 eee_ok: 4299 eee->eee_enabled = edata->eee_enabled; 4300 4301 if (netif_running(dev)) 4302 rc = bnxt_hwrm_set_link_setting(bp, false, true); 4303 4304 eee_exit: 4305 mutex_unlock(&bp->link_lock); 4306 return rc; 4307 } 4308 4309 static int bnxt_get_eee(struct net_device *dev, struct ethtool_keee *edata) 4310 { 4311 struct bnxt *bp = netdev_priv(dev); 4312 4313 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 4314 return -EOPNOTSUPP; 4315 4316 *edata = bp->eee; 4317 if (!bp->eee.eee_enabled) { 4318 /* Preserve tx_lpi_timer so that the last value will be used 4319 * by default when it is re-enabled. 4320 */ 4321 linkmode_zero(edata->advertised); 4322 edata->tx_lpi_enabled = 0; 4323 } 4324 4325 if (!bp->eee.eee_active) 4326 linkmode_zero(edata->lp_advertised); 4327 4328 return 0; 4329 } 4330 4331 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 4332 u16 page_number, u8 bank, 4333 u16 start_addr, u16 data_length, 4334 u8 *buf) 4335 { 4336 struct hwrm_port_phy_i2c_read_output *output; 4337 struct hwrm_port_phy_i2c_read_input *req; 4338 int rc, byte_offset = 0; 4339 4340 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ); 4341 if (rc) 4342 return rc; 4343 4344 output = hwrm_req_hold(bp, req); 4345 req->i2c_slave_addr = i2c_addr; 4346 req->page_number = cpu_to_le16(page_number); 4347 req->port_id = cpu_to_le16(bp->pf.port_id); 4348 do { 4349 u16 xfer_size; 4350 4351 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 4352 data_length -= xfer_size; 4353 req->page_offset = cpu_to_le16(start_addr + byte_offset); 4354 req->data_length = xfer_size; 4355 req->enables = 4356 cpu_to_le32((start_addr + byte_offset ? 4357 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 4358 0) | 4359 (bank ? 4360 PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER : 4361 0)); 4362 rc = hwrm_req_send(bp, req); 4363 if (!rc) 4364 memcpy(buf + byte_offset, output->data, xfer_size); 4365 byte_offset += xfer_size; 4366 } while (!rc && data_length > 0); 4367 hwrm_req_drop(bp, req); 4368 4369 return rc; 4370 } 4371 4372 static int bnxt_get_module_info(struct net_device *dev, 4373 struct ethtool_modinfo *modinfo) 4374 { 4375 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 4376 struct bnxt *bp = netdev_priv(dev); 4377 int rc; 4378 4379 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 4380 return -EPERM; 4381 4382 /* No point in going further if phy status indicates 4383 * module is not inserted or if it is powered down or 4384 * if it is of type 10GBase-T 4385 */ 4386 if (bp->link_info.module_status > 4387 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 4388 return -EOPNOTSUPP; 4389 4390 /* This feature is not supported in older firmware versions */ 4391 if (bp->hwrm_spec_code < 0x10202) 4392 return -EOPNOTSUPP; 4393 4394 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 0, 4395 SFF_DIAG_SUPPORT_OFFSET + 1, 4396 data); 4397 if (!rc) { 4398 u8 module_id = data[0]; 4399 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 4400 4401 switch (module_id) { 4402 case SFF_MODULE_ID_SFP: 4403 modinfo->type = ETH_MODULE_SFF_8472; 4404 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 4405 if (!diag_supported) 4406 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 4407 break; 4408 case SFF_MODULE_ID_QSFP: 4409 case SFF_MODULE_ID_QSFP_PLUS: 4410 modinfo->type = ETH_MODULE_SFF_8436; 4411 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 4412 break; 4413 case SFF_MODULE_ID_QSFP28: 4414 modinfo->type = ETH_MODULE_SFF_8636; 4415 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 4416 break; 4417 default: 4418 rc = -EOPNOTSUPP; 4419 break; 4420 } 4421 } 4422 return rc; 4423 } 4424 4425 static int bnxt_get_module_eeprom(struct net_device *dev, 4426 struct ethtool_eeprom *eeprom, 4427 u8 *data) 4428 { 4429 struct bnxt *bp = netdev_priv(dev); 4430 u16 start = eeprom->offset, length = eeprom->len; 4431 int rc = 0; 4432 4433 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 4434 return -EPERM; 4435 4436 memset(data, 0, eeprom->len); 4437 4438 /* Read A0 portion of the EEPROM */ 4439 if (start < ETH_MODULE_SFF_8436_LEN) { 4440 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 4441 length = ETH_MODULE_SFF_8436_LEN - start; 4442 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 4443 start, length, data); 4444 if (rc) 4445 return rc; 4446 start += length; 4447 data += length; 4448 length = eeprom->len - length; 4449 } 4450 4451 /* Read A2 portion of the EEPROM */ 4452 if (length) { 4453 start -= ETH_MODULE_SFF_8436_LEN; 4454 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 0, 4455 start, length, data); 4456 } 4457 return rc; 4458 } 4459 4460 static int bnxt_get_module_status(struct bnxt *bp, struct netlink_ext_ack *extack) 4461 { 4462 if (bp->link_info.module_status <= 4463 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 4464 return 0; 4465 4466 switch (bp->link_info.module_status) { 4467 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 4468 NL_SET_ERR_MSG_MOD(extack, "Transceiver module is powering down"); 4469 break; 4470 case PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED: 4471 NL_SET_ERR_MSG_MOD(extack, "Transceiver module not inserted"); 4472 break; 4473 case PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT: 4474 NL_SET_ERR_MSG_MOD(extack, "Transceiver module disabled due to current fault"); 4475 break; 4476 default: 4477 NL_SET_ERR_MSG_MOD(extack, "Unknown error"); 4478 break; 4479 } 4480 return -EINVAL; 4481 } 4482 4483 static int bnxt_get_module_eeprom_by_page(struct net_device *dev, 4484 const struct ethtool_module_eeprom *page_data, 4485 struct netlink_ext_ack *extack) 4486 { 4487 struct bnxt *bp = netdev_priv(dev); 4488 int rc; 4489 4490 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { 4491 NL_SET_ERR_MSG_MOD(extack, 4492 "Module read not permitted on untrusted VF"); 4493 return -EPERM; 4494 } 4495 4496 rc = bnxt_get_module_status(bp, extack); 4497 if (rc) 4498 return rc; 4499 4500 if (bp->hwrm_spec_code < 0x10202) { 4501 NL_SET_ERR_MSG_MOD(extack, "Firmware version too old"); 4502 return -EINVAL; 4503 } 4504 4505 if (page_data->bank && !(bp->phy_flags & BNXT_PHY_FL_BANK_SEL)) { 4506 NL_SET_ERR_MSG_MOD(extack, "Firmware not capable for bank selection"); 4507 return -EINVAL; 4508 } 4509 4510 rc = bnxt_read_sfp_module_eeprom_info(bp, page_data->i2c_address << 1, 4511 page_data->page, page_data->bank, 4512 page_data->offset, 4513 page_data->length, 4514 page_data->data); 4515 if (rc) { 4516 NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom read failed"); 4517 return rc; 4518 } 4519 return page_data->length; 4520 } 4521 4522 static int bnxt_nway_reset(struct net_device *dev) 4523 { 4524 int rc = 0; 4525 4526 struct bnxt *bp = netdev_priv(dev); 4527 struct bnxt_link_info *link_info = &bp->link_info; 4528 4529 if (!BNXT_PHY_CFG_ABLE(bp)) 4530 return -EOPNOTSUPP; 4531 4532 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 4533 return -EINVAL; 4534 4535 if (netif_running(dev)) 4536 rc = bnxt_hwrm_set_link_setting(bp, true, false); 4537 4538 return rc; 4539 } 4540 4541 static int bnxt_set_phys_id(struct net_device *dev, 4542 enum ethtool_phys_id_state state) 4543 { 4544 struct hwrm_port_led_cfg_input *req; 4545 struct bnxt *bp = netdev_priv(dev); 4546 struct bnxt_pf_info *pf = &bp->pf; 4547 struct bnxt_led_cfg *led_cfg; 4548 u8 led_state; 4549 __le16 duration; 4550 int rc, i; 4551 4552 if (!bp->num_leds || BNXT_VF(bp)) 4553 return -EOPNOTSUPP; 4554 4555 if (state == ETHTOOL_ID_ACTIVE) { 4556 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 4557 duration = cpu_to_le16(500); 4558 } else if (state == ETHTOOL_ID_INACTIVE) { 4559 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 4560 duration = cpu_to_le16(0); 4561 } else { 4562 return -EINVAL; 4563 } 4564 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG); 4565 if (rc) 4566 return rc; 4567 4568 req->port_id = cpu_to_le16(pf->port_id); 4569 req->num_leds = bp->num_leds; 4570 led_cfg = (struct bnxt_led_cfg *)&req->led0_id; 4571 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 4572 req->enables |= BNXT_LED_DFLT_ENABLES(i); 4573 led_cfg->led_id = bp->leds[i].led_id; 4574 led_cfg->led_state = led_state; 4575 led_cfg->led_blink_on = duration; 4576 led_cfg->led_blink_off = duration; 4577 led_cfg->led_group_id = bp->leds[i].led_group_id; 4578 } 4579 return hwrm_req_send(bp, req); 4580 } 4581 4582 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 4583 { 4584 struct hwrm_selftest_irq_input *req; 4585 int rc; 4586 4587 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ); 4588 if (rc) 4589 return rc; 4590 4591 req->cmpl_ring = cpu_to_le16(cmpl_ring); 4592 return hwrm_req_send(bp, req); 4593 } 4594 4595 static int bnxt_test_irq(struct bnxt *bp) 4596 { 4597 int i; 4598 4599 for (i = 0; i < bp->cp_nr_rings; i++) { 4600 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 4601 int rc; 4602 4603 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 4604 if (rc) 4605 return rc; 4606 } 4607 return 0; 4608 } 4609 4610 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 4611 { 4612 struct hwrm_port_mac_cfg_input *req; 4613 int rc; 4614 4615 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 4616 if (rc) 4617 return rc; 4618 4619 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 4620 if (enable) 4621 req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 4622 else 4623 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 4624 return hwrm_req_send(bp, req); 4625 } 4626 4627 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 4628 { 4629 struct hwrm_port_phy_qcaps_output *resp; 4630 struct hwrm_port_phy_qcaps_input *req; 4631 int rc; 4632 4633 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS); 4634 if (rc) 4635 return rc; 4636 4637 resp = hwrm_req_hold(bp, req); 4638 rc = hwrm_req_send(bp, req); 4639 if (!rc) 4640 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 4641 4642 hwrm_req_drop(bp, req); 4643 return rc; 4644 } 4645 4646 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 4647 struct hwrm_port_phy_cfg_input *req) 4648 { 4649 struct bnxt_link_info *link_info = &bp->link_info; 4650 u16 fw_advertising; 4651 u16 fw_speed; 4652 int rc; 4653 4654 if (!link_info->autoneg || 4655 (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK)) 4656 return 0; 4657 4658 rc = bnxt_query_force_speeds(bp, &fw_advertising); 4659 if (rc) 4660 return rc; 4661 4662 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 4663 if (BNXT_LINK_IS_UP(bp)) 4664 fw_speed = bp->link_info.link_speed; 4665 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 4666 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 4667 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 4668 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 4669 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 4670 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 4671 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 4672 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 4673 4674 req->force_link_speed = cpu_to_le16(fw_speed); 4675 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 4676 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 4677 rc = hwrm_req_send(bp, req); 4678 req->flags = 0; 4679 req->force_link_speed = cpu_to_le16(0); 4680 return rc; 4681 } 4682 4683 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 4684 { 4685 struct hwrm_port_phy_cfg_input *req; 4686 int rc; 4687 4688 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 4689 if (rc) 4690 return rc; 4691 4692 /* prevent bnxt_disable_an_for_lpbk() from consuming the request */ 4693 hwrm_req_hold(bp, req); 4694 4695 if (enable) { 4696 bnxt_disable_an_for_lpbk(bp, req); 4697 if (ext) 4698 req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 4699 else 4700 req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 4701 } else { 4702 req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 4703 } 4704 req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 4705 rc = hwrm_req_send(bp, req); 4706 hwrm_req_drop(bp, req); 4707 return rc; 4708 } 4709 4710 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 4711 u32 raw_cons, int pkt_size) 4712 { 4713 struct bnxt_napi *bnapi = cpr->bnapi; 4714 struct bnxt_rx_ring_info *rxr; 4715 struct bnxt_sw_rx_bd *rx_buf; 4716 struct rx_cmp *rxcmp; 4717 u16 cp_cons, cons; 4718 u8 *data; 4719 u32 len; 4720 int i; 4721 4722 rxr = bnapi->rx_ring; 4723 cp_cons = RING_CMP(raw_cons); 4724 rxcmp = (struct rx_cmp *) 4725 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 4726 cons = rxcmp->rx_cmp_opaque; 4727 rx_buf = &rxr->rx_buf_ring[cons]; 4728 data = rx_buf->data_ptr; 4729 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 4730 if (len != pkt_size) 4731 return -EIO; 4732 i = ETH_ALEN; 4733 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 4734 return -EIO; 4735 i += ETH_ALEN; 4736 for ( ; i < pkt_size; i++) { 4737 if (data[i] != (u8)(i & 0xff)) 4738 return -EIO; 4739 } 4740 return 0; 4741 } 4742 4743 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 4744 int pkt_size) 4745 { 4746 struct tx_cmp *txcmp; 4747 int rc = -EIO; 4748 u32 raw_cons; 4749 u32 cons; 4750 int i; 4751 4752 raw_cons = cpr->cp_raw_cons; 4753 for (i = 0; i < 200; i++) { 4754 cons = RING_CMP(raw_cons); 4755 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 4756 4757 if (!TX_CMP_VALID(txcmp, raw_cons)) { 4758 udelay(5); 4759 continue; 4760 } 4761 4762 /* The valid test of the entry must be done first before 4763 * reading any further. 4764 */ 4765 dma_rmb(); 4766 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP || 4767 TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_V3_CMP) { 4768 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 4769 raw_cons = NEXT_RAW_CMP(raw_cons); 4770 raw_cons = NEXT_RAW_CMP(raw_cons); 4771 break; 4772 } 4773 raw_cons = NEXT_RAW_CMP(raw_cons); 4774 } 4775 cpr->cp_raw_cons = raw_cons; 4776 return rc; 4777 } 4778 4779 static int bnxt_run_loopback(struct bnxt *bp) 4780 { 4781 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 4782 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 4783 struct bnxt_cp_ring_info *cpr; 4784 int pkt_size, i = 0; 4785 struct sk_buff *skb; 4786 dma_addr_t map; 4787 u8 *data; 4788 int rc; 4789 4790 cpr = &rxr->bnapi->cp_ring; 4791 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) 4792 cpr = rxr->rx_cpr; 4793 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh); 4794 skb = netdev_alloc_skb(bp->dev, pkt_size); 4795 if (!skb) 4796 return -ENOMEM; 4797 data = skb_put(skb, pkt_size); 4798 ether_addr_copy(&data[i], bp->dev->dev_addr); 4799 i += ETH_ALEN; 4800 ether_addr_copy(&data[i], bp->dev->dev_addr); 4801 i += ETH_ALEN; 4802 for ( ; i < pkt_size; i++) 4803 data[i] = (u8)(i & 0xff); 4804 4805 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 4806 DMA_TO_DEVICE); 4807 if (dma_mapping_error(&bp->pdev->dev, map)) { 4808 dev_kfree_skb(skb); 4809 return -EIO; 4810 } 4811 bnxt_xmit_bd(bp, txr, map, pkt_size, NULL); 4812 4813 /* Sync BD data before updating doorbell */ 4814 wmb(); 4815 4816 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 4817 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 4818 4819 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE); 4820 dev_kfree_skb(skb); 4821 return rc; 4822 } 4823 4824 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 4825 { 4826 struct hwrm_selftest_exec_output *resp; 4827 struct hwrm_selftest_exec_input *req; 4828 int rc; 4829 4830 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC); 4831 if (rc) 4832 return rc; 4833 4834 hwrm_req_timeout(bp, req, bp->test_info->timeout); 4835 req->flags = test_mask; 4836 4837 resp = hwrm_req_hold(bp, req); 4838 rc = hwrm_req_send(bp, req); 4839 *test_results = resp->test_success; 4840 hwrm_req_drop(bp, req); 4841 return rc; 4842 } 4843 4844 #define BNXT_DRV_TESTS 4 4845 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 4846 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 4847 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 4848 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 4849 4850 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 4851 u64 *buf) 4852 { 4853 struct bnxt *bp = netdev_priv(dev); 4854 bool do_ext_lpbk = false; 4855 bool offline = false; 4856 u8 test_results = 0; 4857 u8 test_mask = 0; 4858 int rc = 0, i; 4859 4860 if (!bp->num_tests || !BNXT_PF(bp)) 4861 return; 4862 4863 if (etest->flags & ETH_TEST_FL_OFFLINE && 4864 bnxt_ulp_registered(bp->edev)) { 4865 etest->flags |= ETH_TEST_FL_FAILED; 4866 netdev_warn(dev, "Offline tests cannot be run with RoCE driver loaded\n"); 4867 return; 4868 } 4869 4870 memset(buf, 0, sizeof(u64) * bp->num_tests); 4871 if (!netif_running(dev)) { 4872 etest->flags |= ETH_TEST_FL_FAILED; 4873 return; 4874 } 4875 4876 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 4877 (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK)) 4878 do_ext_lpbk = true; 4879 4880 if (etest->flags & ETH_TEST_FL_OFFLINE) { 4881 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) { 4882 etest->flags |= ETH_TEST_FL_FAILED; 4883 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n"); 4884 return; 4885 } 4886 offline = true; 4887 } 4888 4889 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 4890 u8 bit_val = 1 << i; 4891 4892 if (!(bp->test_info->offline_mask & bit_val)) 4893 test_mask |= bit_val; 4894 else if (offline) 4895 test_mask |= bit_val; 4896 } 4897 if (!offline) { 4898 bnxt_run_fw_tests(bp, test_mask, &test_results); 4899 } else { 4900 bnxt_close_nic(bp, true, false); 4901 bnxt_run_fw_tests(bp, test_mask, &test_results); 4902 4903 rc = bnxt_half_open_nic(bp); 4904 if (rc) { 4905 etest->flags |= ETH_TEST_FL_FAILED; 4906 return; 4907 } 4908 buf[BNXT_MACLPBK_TEST_IDX] = 1; 4909 if (bp->mac_flags & BNXT_MAC_FL_NO_MAC_LPBK) 4910 goto skip_mac_loopback; 4911 4912 bnxt_hwrm_mac_loopback(bp, true); 4913 msleep(250); 4914 if (bnxt_run_loopback(bp)) 4915 etest->flags |= ETH_TEST_FL_FAILED; 4916 else 4917 buf[BNXT_MACLPBK_TEST_IDX] = 0; 4918 4919 bnxt_hwrm_mac_loopback(bp, false); 4920 skip_mac_loopback: 4921 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 4922 if (bp->phy_flags & BNXT_PHY_FL_NO_PHY_LPBK) 4923 goto skip_phy_loopback; 4924 4925 bnxt_hwrm_phy_loopback(bp, true, false); 4926 msleep(1000); 4927 if (bnxt_run_loopback(bp)) 4928 etest->flags |= ETH_TEST_FL_FAILED; 4929 else 4930 buf[BNXT_PHYLPBK_TEST_IDX] = 0; 4931 skip_phy_loopback: 4932 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 4933 if (do_ext_lpbk) { 4934 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 4935 bnxt_hwrm_phy_loopback(bp, true, true); 4936 msleep(1000); 4937 if (bnxt_run_loopback(bp)) 4938 etest->flags |= ETH_TEST_FL_FAILED; 4939 else 4940 buf[BNXT_EXTLPBK_TEST_IDX] = 0; 4941 } 4942 bnxt_hwrm_phy_loopback(bp, false, false); 4943 bnxt_half_close_nic(bp); 4944 rc = bnxt_open_nic(bp, true, true); 4945 } 4946 if (rc || bnxt_test_irq(bp)) { 4947 buf[BNXT_IRQ_TEST_IDX] = 1; 4948 etest->flags |= ETH_TEST_FL_FAILED; 4949 } 4950 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 4951 u8 bit_val = 1 << i; 4952 4953 if ((test_mask & bit_val) && !(test_results & bit_val)) { 4954 buf[i] = 1; 4955 etest->flags |= ETH_TEST_FL_FAILED; 4956 } 4957 } 4958 } 4959 4960 static int bnxt_reset(struct net_device *dev, u32 *flags) 4961 { 4962 struct bnxt *bp = netdev_priv(dev); 4963 bool reload = false; 4964 u32 req = *flags; 4965 4966 if (!req) 4967 return -EINVAL; 4968 4969 if (!BNXT_PF(bp)) { 4970 netdev_err(dev, "Reset is not supported from a VF\n"); 4971 return -EOPNOTSUPP; 4972 } 4973 4974 if (pci_vfs_assigned(bp->pdev) && 4975 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) { 4976 netdev_err(dev, 4977 "Reset not allowed when VFs are assigned to VMs\n"); 4978 return -EBUSY; 4979 } 4980 4981 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) { 4982 /* This feature is not supported in older firmware versions */ 4983 if (bp->hwrm_spec_code >= 0x10803) { 4984 if (!bnxt_firmware_reset_chip(dev)) { 4985 netdev_info(dev, "Firmware reset request successful.\n"); 4986 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) 4987 reload = true; 4988 *flags &= ~BNXT_FW_RESET_CHIP; 4989 } 4990 } else if (req == BNXT_FW_RESET_CHIP) { 4991 return -EOPNOTSUPP; /* only request, fail hard */ 4992 } 4993 } 4994 4995 if (!BNXT_CHIP_P4_PLUS(bp) && (req & BNXT_FW_RESET_AP)) { 4996 /* This feature is not supported in older firmware versions */ 4997 if (bp->hwrm_spec_code >= 0x10803) { 4998 if (!bnxt_firmware_reset_ap(dev)) { 4999 netdev_info(dev, "Reset application processor successful.\n"); 5000 reload = true; 5001 *flags &= ~BNXT_FW_RESET_AP; 5002 } 5003 } else if (req == BNXT_FW_RESET_AP) { 5004 return -EOPNOTSUPP; /* only request, fail hard */ 5005 } 5006 } 5007 5008 if (reload) 5009 netdev_info(dev, "Reload driver to complete reset\n"); 5010 5011 return 0; 5012 } 5013 5014 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump) 5015 { 5016 struct bnxt *bp = netdev_priv(dev); 5017 5018 if (dump->flag > BNXT_DUMP_DRIVER) { 5019 netdev_info(dev, "Supports only Live(0), Crash(1), Driver(2) dumps.\n"); 5020 return -EINVAL; 5021 } 5022 5023 if (dump->flag == BNXT_DUMP_CRASH) { 5024 if (bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR && 5025 (!IS_ENABLED(CONFIG_TEE_BNXT_FW))) { 5026 netdev_info(dev, 5027 "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n"); 5028 return -EOPNOTSUPP; 5029 } else if (!(bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR)) { 5030 netdev_info(dev, "Crash dump collection from host memory is not supported on this interface.\n"); 5031 return -EOPNOTSUPP; 5032 } 5033 } 5034 5035 bp->dump_flag = dump->flag; 5036 return 0; 5037 } 5038 5039 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 5040 { 5041 struct bnxt *bp = netdev_priv(dev); 5042 5043 if (bp->hwrm_spec_code < 0x10801) 5044 return -EOPNOTSUPP; 5045 5046 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 5047 bp->ver_resp.hwrm_fw_min_8b << 16 | 5048 bp->ver_resp.hwrm_fw_bld_8b << 8 | 5049 bp->ver_resp.hwrm_fw_rsvd_8b; 5050 5051 dump->flag = bp->dump_flag; 5052 dump->len = bnxt_get_coredump_length(bp, bp->dump_flag); 5053 return 0; 5054 } 5055 5056 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 5057 void *buf) 5058 { 5059 struct bnxt *bp = netdev_priv(dev); 5060 5061 if (bp->hwrm_spec_code < 0x10801) 5062 return -EOPNOTSUPP; 5063 5064 memset(buf, 0, dump->len); 5065 5066 dump->flag = bp->dump_flag; 5067 return bnxt_get_coredump(bp, dump->flag, buf, &dump->len); 5068 } 5069 5070 static int bnxt_get_ts_info(struct net_device *dev, 5071 struct kernel_ethtool_ts_info *info) 5072 { 5073 struct bnxt *bp = netdev_priv(dev); 5074 struct bnxt_ptp_cfg *ptp; 5075 5076 ptp = bp->ptp_cfg; 5077 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE; 5078 5079 if (!ptp) 5080 return 0; 5081 5082 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | 5083 SOF_TIMESTAMPING_RX_HARDWARE | 5084 SOF_TIMESTAMPING_RAW_HARDWARE; 5085 if (ptp->ptp_clock) 5086 info->phc_index = ptp_clock_index(ptp->ptp_clock); 5087 5088 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 5089 5090 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 5091 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 5092 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 5093 5094 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) 5095 info->rx_filters |= (1 << HWTSTAMP_FILTER_ALL); 5096 return 0; 5097 } 5098 5099 void bnxt_ethtool_init(struct bnxt *bp) 5100 { 5101 struct hwrm_selftest_qlist_output *resp; 5102 struct hwrm_selftest_qlist_input *req; 5103 struct bnxt_test_info *test_info; 5104 struct net_device *dev = bp->dev; 5105 int i, rc; 5106 5107 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 5108 bnxt_get_pkgver(dev); 5109 5110 bp->num_tests = 0; 5111 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp)) 5112 return; 5113 5114 test_info = bp->test_info; 5115 if (!test_info) { 5116 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL); 5117 if (!test_info) 5118 return; 5119 bp->test_info = test_info; 5120 } 5121 5122 if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST)) 5123 return; 5124 5125 resp = hwrm_req_hold(bp, req); 5126 rc = hwrm_req_send_silent(bp, req); 5127 if (rc) 5128 goto ethtool_init_exit; 5129 5130 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 5131 if (bp->num_tests > BNXT_MAX_TEST) 5132 bp->num_tests = BNXT_MAX_TEST; 5133 5134 test_info->offline_mask = resp->offline_tests; 5135 test_info->timeout = le16_to_cpu(resp->test_timeout); 5136 if (!test_info->timeout) 5137 test_info->timeout = HWRM_CMD_TIMEOUT; 5138 for (i = 0; i < bp->num_tests; i++) { 5139 char *str = test_info->string[i]; 5140 char *fw_str = resp->test_name[i]; 5141 5142 if (i == BNXT_MACLPBK_TEST_IDX) { 5143 strcpy(str, "Mac loopback test (offline)"); 5144 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 5145 strcpy(str, "Phy loopback test (offline)"); 5146 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 5147 strcpy(str, "Ext loopback test (offline)"); 5148 } else if (i == BNXT_IRQ_TEST_IDX) { 5149 strcpy(str, "Interrupt_test (offline)"); 5150 } else { 5151 snprintf(str, ETH_GSTRING_LEN, "%s test (%s)", 5152 fw_str, test_info->offline_mask & (1 << i) ? 5153 "offline" : "online"); 5154 } 5155 } 5156 5157 ethtool_init_exit: 5158 hwrm_req_drop(bp, req); 5159 } 5160 5161 static void bnxt_get_eth_phy_stats(struct net_device *dev, 5162 struct ethtool_eth_phy_stats *phy_stats) 5163 { 5164 struct bnxt *bp = netdev_priv(dev); 5165 u64 *rx; 5166 5167 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 5168 return; 5169 5170 rx = bp->rx_port_stats_ext.sw_stats; 5171 phy_stats->SymbolErrorDuringCarrier = 5172 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err)); 5173 } 5174 5175 static void bnxt_get_eth_mac_stats(struct net_device *dev, 5176 struct ethtool_eth_mac_stats *mac_stats) 5177 { 5178 struct bnxt *bp = netdev_priv(dev); 5179 u64 *rx, *tx; 5180 5181 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5182 return; 5183 5184 rx = bp->port_stats.sw_stats; 5185 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 5186 5187 mac_stats->FramesReceivedOK = 5188 BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames); 5189 mac_stats->FramesTransmittedOK = 5190 BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames); 5191 mac_stats->FrameCheckSequenceErrors = 5192 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames); 5193 mac_stats->AlignmentErrors = 5194 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames); 5195 mac_stats->OutOfRangeLengthField = 5196 BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames); 5197 } 5198 5199 static void bnxt_get_eth_ctrl_stats(struct net_device *dev, 5200 struct ethtool_eth_ctrl_stats *ctrl_stats) 5201 { 5202 struct bnxt *bp = netdev_priv(dev); 5203 u64 *rx; 5204 5205 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5206 return; 5207 5208 rx = bp->port_stats.sw_stats; 5209 ctrl_stats->MACControlFramesReceived = 5210 BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames); 5211 } 5212 5213 static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = { 5214 { 0, 64 }, 5215 { 65, 127 }, 5216 { 128, 255 }, 5217 { 256, 511 }, 5218 { 512, 1023 }, 5219 { 1024, 1518 }, 5220 { 1519, 2047 }, 5221 { 2048, 4095 }, 5222 { 4096, 9216 }, 5223 { 9217, 16383 }, 5224 {} 5225 }; 5226 5227 static void bnxt_get_rmon_stats(struct net_device *dev, 5228 struct ethtool_rmon_stats *rmon_stats, 5229 const struct ethtool_rmon_hist_range **ranges) 5230 { 5231 struct bnxt *bp = netdev_priv(dev); 5232 u64 *rx, *tx; 5233 5234 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5235 return; 5236 5237 rx = bp->port_stats.sw_stats; 5238 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 5239 5240 rmon_stats->jabbers = 5241 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames); 5242 rmon_stats->oversize_pkts = 5243 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames); 5244 rmon_stats->undersize_pkts = 5245 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames); 5246 5247 rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames); 5248 rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames); 5249 rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames); 5250 rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames); 5251 rmon_stats->hist[4] = 5252 BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames); 5253 rmon_stats->hist[5] = 5254 BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames); 5255 rmon_stats->hist[6] = 5256 BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames); 5257 rmon_stats->hist[7] = 5258 BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames); 5259 rmon_stats->hist[8] = 5260 BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames); 5261 rmon_stats->hist[9] = 5262 BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames); 5263 5264 rmon_stats->hist_tx[0] = 5265 BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames); 5266 rmon_stats->hist_tx[1] = 5267 BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames); 5268 rmon_stats->hist_tx[2] = 5269 BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames); 5270 rmon_stats->hist_tx[3] = 5271 BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames); 5272 rmon_stats->hist_tx[4] = 5273 BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames); 5274 rmon_stats->hist_tx[5] = 5275 BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames); 5276 rmon_stats->hist_tx[6] = 5277 BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames); 5278 rmon_stats->hist_tx[7] = 5279 BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames); 5280 rmon_stats->hist_tx[8] = 5281 BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames); 5282 rmon_stats->hist_tx[9] = 5283 BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames); 5284 5285 *ranges = bnxt_rmon_ranges; 5286 } 5287 5288 static void bnxt_get_ptp_stats(struct net_device *dev, 5289 struct ethtool_ts_stats *ts_stats) 5290 { 5291 struct bnxt *bp = netdev_priv(dev); 5292 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 5293 5294 if (ptp) { 5295 ts_stats->pkts = ptp->stats.ts_pkts; 5296 ts_stats->lost = ptp->stats.ts_lost; 5297 ts_stats->err = atomic64_read(&ptp->stats.ts_err); 5298 } 5299 } 5300 5301 static void bnxt_get_link_ext_stats(struct net_device *dev, 5302 struct ethtool_link_ext_stats *stats) 5303 { 5304 struct bnxt *bp = netdev_priv(dev); 5305 u64 *rx; 5306 5307 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 5308 return; 5309 5310 rx = bp->rx_port_stats_ext.sw_stats; 5311 stats->link_down_events = 5312 *(rx + BNXT_RX_STATS_EXT_OFFSET(link_down_events)); 5313 } 5314 5315 void bnxt_ethtool_free(struct bnxt *bp) 5316 { 5317 kfree(bp->test_info); 5318 bp->test_info = NULL; 5319 } 5320 5321 const struct ethtool_ops bnxt_ethtool_ops = { 5322 .cap_link_lanes_supported = 1, 5323 .rxfh_per_ctx_key = 1, 5324 .rxfh_max_num_contexts = BNXT_MAX_ETH_RSS_CTX + 1, 5325 .rxfh_indir_space = BNXT_MAX_RSS_TABLE_ENTRIES_P5, 5326 .rxfh_priv_size = sizeof(struct bnxt_rss_ctx), 5327 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 5328 ETHTOOL_COALESCE_MAX_FRAMES | 5329 ETHTOOL_COALESCE_USECS_IRQ | 5330 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 5331 ETHTOOL_COALESCE_STATS_BLOCK_USECS | 5332 ETHTOOL_COALESCE_USE_ADAPTIVE_RX | 5333 ETHTOOL_COALESCE_USE_CQE, 5334 .get_link_ksettings = bnxt_get_link_ksettings, 5335 .set_link_ksettings = bnxt_set_link_ksettings, 5336 .get_fec_stats = bnxt_get_fec_stats, 5337 .get_fecparam = bnxt_get_fecparam, 5338 .set_fecparam = bnxt_set_fecparam, 5339 .get_pause_stats = bnxt_get_pause_stats, 5340 .get_pauseparam = bnxt_get_pauseparam, 5341 .set_pauseparam = bnxt_set_pauseparam, 5342 .get_drvinfo = bnxt_get_drvinfo, 5343 .get_regs_len = bnxt_get_regs_len, 5344 .get_regs = bnxt_get_regs, 5345 .get_wol = bnxt_get_wol, 5346 .set_wol = bnxt_set_wol, 5347 .get_coalesce = bnxt_get_coalesce, 5348 .set_coalesce = bnxt_set_coalesce, 5349 .get_msglevel = bnxt_get_msglevel, 5350 .set_msglevel = bnxt_set_msglevel, 5351 .get_sset_count = bnxt_get_sset_count, 5352 .get_strings = bnxt_get_strings, 5353 .get_ethtool_stats = bnxt_get_ethtool_stats, 5354 .set_ringparam = bnxt_set_ringparam, 5355 .get_ringparam = bnxt_get_ringparam, 5356 .get_channels = bnxt_get_channels, 5357 .set_channels = bnxt_set_channels, 5358 .get_rxnfc = bnxt_get_rxnfc, 5359 .set_rxnfc = bnxt_set_rxnfc, 5360 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 5361 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 5362 .get_rxfh = bnxt_get_rxfh, 5363 .set_rxfh = bnxt_set_rxfh, 5364 .create_rxfh_context = bnxt_create_rxfh_context, 5365 .modify_rxfh_context = bnxt_modify_rxfh_context, 5366 .remove_rxfh_context = bnxt_remove_rxfh_context, 5367 .flash_device = bnxt_flash_device, 5368 .get_eeprom_len = bnxt_get_eeprom_len, 5369 .get_eeprom = bnxt_get_eeprom, 5370 .set_eeprom = bnxt_set_eeprom, 5371 .get_link = bnxt_get_link, 5372 .get_link_ext_stats = bnxt_get_link_ext_stats, 5373 .get_eee = bnxt_get_eee, 5374 .set_eee = bnxt_set_eee, 5375 .get_module_info = bnxt_get_module_info, 5376 .get_module_eeprom = bnxt_get_module_eeprom, 5377 .get_module_eeprom_by_page = bnxt_get_module_eeprom_by_page, 5378 .nway_reset = bnxt_nway_reset, 5379 .set_phys_id = bnxt_set_phys_id, 5380 .self_test = bnxt_self_test, 5381 .get_ts_info = bnxt_get_ts_info, 5382 .reset = bnxt_reset, 5383 .set_dump = bnxt_set_dump, 5384 .get_dump_flag = bnxt_get_dump_flag, 5385 .get_dump_data = bnxt_get_dump_data, 5386 .get_eth_phy_stats = bnxt_get_eth_phy_stats, 5387 .get_eth_mac_stats = bnxt_get_eth_mac_stats, 5388 .get_eth_ctrl_stats = bnxt_get_eth_ctrl_stats, 5389 .get_rmon_stats = bnxt_get_rmon_stats, 5390 .get_ts_stats = bnxt_get_ptp_stats, 5391 }; 5392