1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/bitops.h> 12 #include <linux/ctype.h> 13 #include <linux/stringify.h> 14 #include <linux/ethtool.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/linkmode.h> 17 #include <linux/interrupt.h> 18 #include <linux/pci.h> 19 #include <linux/etherdevice.h> 20 #include <linux/crc32.h> 21 #include <linux/firmware.h> 22 #include <linux/utsname.h> 23 #include <linux/time.h> 24 #include <linux/ptp_clock_kernel.h> 25 #include <linux/net_tstamp.h> 26 #include <linux/timecounter.h> 27 #include <net/netdev_queues.h> 28 #include <net/netlink.h> 29 #include <linux/bnxt/hsi.h> 30 #include "bnxt.h" 31 #include "bnxt_hwrm.h" 32 #include "bnxt_ulp.h" 33 #include "bnxt_xdp.h" 34 #include "bnxt_ptp.h" 35 #include "bnxt_ethtool.h" 36 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 37 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 38 #include "bnxt_coredump.h" 39 40 #define BNXT_NVM_ERR_MSG(dev, extack, msg) \ 41 do { \ 42 if (extack) \ 43 NL_SET_ERR_MSG_MOD(extack, msg); \ 44 netdev_err(dev, "%s\n", msg); \ 45 } while (0) 46 47 static u32 bnxt_get_msglevel(struct net_device *dev) 48 { 49 struct bnxt *bp = netdev_priv(dev); 50 51 return bp->msg_enable; 52 } 53 54 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 55 { 56 struct bnxt *bp = netdev_priv(dev); 57 58 bp->msg_enable = value; 59 } 60 61 static int bnxt_get_coalesce(struct net_device *dev, 62 struct ethtool_coalesce *coal, 63 struct kernel_ethtool_coalesce *kernel_coal, 64 struct netlink_ext_ack *extack) 65 { 66 struct bnxt *bp = netdev_priv(dev); 67 struct bnxt_coal *hw_coal; 68 u16 mult; 69 70 memset(coal, 0, sizeof(*coal)); 71 72 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 73 74 hw_coal = &bp->rx_coal; 75 mult = hw_coal->bufs_per_record; 76 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 77 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 78 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 79 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 80 if (hw_coal->flags & 81 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 82 kernel_coal->use_cqe_mode_rx = true; 83 84 hw_coal = &bp->tx_coal; 85 mult = hw_coal->bufs_per_record; 86 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 87 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 88 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 89 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 90 if (hw_coal->flags & 91 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 92 kernel_coal->use_cqe_mode_tx = true; 93 94 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 95 96 return 0; 97 } 98 99 static int bnxt_set_coalesce(struct net_device *dev, 100 struct ethtool_coalesce *coal, 101 struct kernel_ethtool_coalesce *kernel_coal, 102 struct netlink_ext_ack *extack) 103 { 104 struct bnxt *bp = netdev_priv(dev); 105 bool update_stats = false; 106 struct bnxt_coal *hw_coal; 107 int rc = 0; 108 u16 mult; 109 110 if (coal->use_adaptive_rx_coalesce) { 111 bp->flags |= BNXT_FLAG_DIM; 112 } else { 113 if (bp->flags & BNXT_FLAG_DIM) { 114 bp->flags &= ~(BNXT_FLAG_DIM); 115 goto reset_coalesce; 116 } 117 } 118 119 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) && 120 !(bp->coal_cap.cmpl_params & 121 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)) 122 return -EOPNOTSUPP; 123 124 hw_coal = &bp->rx_coal; 125 mult = hw_coal->bufs_per_record; 126 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 127 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 128 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 129 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 130 hw_coal->flags &= 131 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 132 if (kernel_coal->use_cqe_mode_rx) 133 hw_coal->flags |= 134 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 135 136 hw_coal = &bp->tx_coal; 137 mult = hw_coal->bufs_per_record; 138 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 139 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 140 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 141 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 142 hw_coal->flags &= 143 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 144 if (kernel_coal->use_cqe_mode_tx) 145 hw_coal->flags |= 146 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 147 148 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 149 u32 stats_ticks = coal->stats_block_coalesce_usecs; 150 151 /* Allow 0, which means disable. */ 152 if (stats_ticks) 153 stats_ticks = clamp_t(u32, stats_ticks, 154 BNXT_MIN_STATS_COAL_TICKS, 155 BNXT_MAX_STATS_COAL_TICKS); 156 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 157 bp->stats_coal_ticks = stats_ticks; 158 if (bp->stats_coal_ticks) 159 bp->current_interval = 160 bp->stats_coal_ticks * HZ / 1000000; 161 else 162 bp->current_interval = BNXT_TIMER_INTERVAL; 163 update_stats = true; 164 } 165 166 reset_coalesce: 167 if (test_bit(BNXT_STATE_OPEN, &bp->state)) { 168 if (update_stats) { 169 bnxt_close_nic(bp, true, false); 170 rc = bnxt_open_nic(bp, true, false); 171 } else { 172 rc = bnxt_hwrm_set_coal(bp); 173 } 174 } 175 176 return rc; 177 } 178 179 static const char * const bnxt_ring_rx_stats_str[] = { 180 "rx_ucast_packets", 181 "rx_mcast_packets", 182 "rx_bcast_packets", 183 "rx_discards", 184 "rx_errors", 185 "rx_ucast_bytes", 186 "rx_mcast_bytes", 187 "rx_bcast_bytes", 188 }; 189 190 static const char * const bnxt_ring_tx_stats_str[] = { 191 "tx_ucast_packets", 192 "tx_mcast_packets", 193 "tx_bcast_packets", 194 "tx_errors", 195 "tx_discards", 196 "tx_ucast_bytes", 197 "tx_mcast_bytes", 198 "tx_bcast_bytes", 199 }; 200 201 static const char * const bnxt_ring_tpa_stats_str[] = { 202 "tpa_packets", 203 "tpa_bytes", 204 "tpa_events", 205 "tpa_aborts", 206 }; 207 208 static const char * const bnxt_ring_tpa2_stats_str[] = { 209 "rx_tpa_eligible_pkt", 210 "rx_tpa_eligible_bytes", 211 "rx_tpa_pkt", 212 "rx_tpa_bytes", 213 "rx_tpa_errors", 214 "rx_tpa_events", 215 }; 216 217 static const char * const bnxt_rx_sw_stats_str[] = { 218 "rx_l4_csum_errors", 219 "rx_resets", 220 "rx_buf_errors", 221 }; 222 223 static const char * const bnxt_cmn_sw_stats_str[] = { 224 "missed_irqs", 225 }; 226 227 #define BNXT_RX_STATS_ENTRY(counter) \ 228 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 229 230 #define BNXT_TX_STATS_ENTRY(counter) \ 231 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 232 233 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 234 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 235 236 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 237 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 238 239 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 240 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 241 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 242 243 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 244 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 245 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 246 247 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 248 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 249 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 250 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 251 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 252 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 253 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 254 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 255 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 256 257 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 258 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 259 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 260 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 261 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 262 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 263 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 264 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 265 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 266 267 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 268 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 269 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 270 271 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 272 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 273 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 274 275 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 276 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 277 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 278 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 279 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 280 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 281 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 282 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 283 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 284 285 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 286 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 287 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 288 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 289 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 290 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 291 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 292 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 293 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 294 295 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 296 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 297 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 298 299 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 300 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 301 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 302 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 303 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 304 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 305 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 306 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 307 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 308 309 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 310 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 311 __stringify(counter##_pri##n) } 312 313 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 314 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 315 __stringify(counter##_pri##n) } 316 317 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 318 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 319 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 320 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 321 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 322 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 323 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 324 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 325 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 326 327 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 328 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 329 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 330 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 331 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 332 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 333 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 334 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 335 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 336 337 enum { 338 RX_TOTAL_DISCARDS, 339 TX_TOTAL_DISCARDS, 340 RX_NETPOLL_DISCARDS, 341 }; 342 343 static const char *const bnxt_ring_err_stats_arr[] = { 344 "rx_total_l4_csum_errors", 345 "rx_total_resets", 346 "rx_total_buf_errors", 347 "rx_total_oom_discards", 348 "rx_total_netpoll_discards", 349 "rx_total_ring_discards", 350 "tx_total_resets", 351 "tx_total_ring_discards", 352 "total_missed_irqs", 353 }; 354 355 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str) 356 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str) 357 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str) 358 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str) 359 360 static const struct { 361 long offset; 362 char string[ETH_GSTRING_LEN]; 363 } bnxt_port_stats_arr[] = { 364 BNXT_RX_STATS_ENTRY(rx_64b_frames), 365 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 366 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 367 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 368 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 369 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 370 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 371 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 372 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 373 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 374 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 375 BNXT_RX_STATS_ENTRY(rx_total_frames), 376 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 377 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 378 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 379 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 380 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 381 BNXT_RX_STATS_ENTRY(rx_pause_frames), 382 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 383 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 384 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 385 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 386 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 387 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 388 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 389 BNXT_RX_STATS_ENTRY(rx_good_frames), 390 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 391 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 392 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 393 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 394 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 395 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 396 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 397 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 398 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 399 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 400 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 401 BNXT_RX_STATS_ENTRY(rx_bytes), 402 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 403 BNXT_RX_STATS_ENTRY(rx_runt_frames), 404 BNXT_RX_STATS_ENTRY(rx_stat_discard), 405 BNXT_RX_STATS_ENTRY(rx_stat_err), 406 407 BNXT_TX_STATS_ENTRY(tx_64b_frames), 408 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 409 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 410 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 411 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 412 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 413 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 414 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 415 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 416 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 417 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 418 BNXT_TX_STATS_ENTRY(tx_good_frames), 419 BNXT_TX_STATS_ENTRY(tx_total_frames), 420 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 421 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 422 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 423 BNXT_TX_STATS_ENTRY(tx_pause_frames), 424 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 425 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 426 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 427 BNXT_TX_STATS_ENTRY(tx_err), 428 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 429 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 430 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 431 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 432 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 433 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 434 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 435 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 436 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 437 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 438 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 439 BNXT_TX_STATS_ENTRY(tx_total_collisions), 440 BNXT_TX_STATS_ENTRY(tx_bytes), 441 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 442 BNXT_TX_STATS_ENTRY(tx_stat_discard), 443 BNXT_TX_STATS_ENTRY(tx_stat_error), 444 }; 445 446 static const struct { 447 long offset; 448 char string[ETH_GSTRING_LEN]; 449 } bnxt_port_stats_ext_arr[] = { 450 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 451 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 452 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 453 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 454 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 455 BNXT_RX_STATS_EXT_COS_ENTRIES, 456 BNXT_RX_STATS_EXT_PFC_ENTRIES, 457 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 458 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 459 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 460 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 461 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 462 BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks), 463 BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks), 464 BNXT_RX_STATS_EXT_ENTRY(rx_filter_miss), 465 }; 466 467 static const struct { 468 long offset; 469 char string[ETH_GSTRING_LEN]; 470 } bnxt_tx_port_stats_ext_arr[] = { 471 BNXT_TX_STATS_EXT_COS_ENTRIES, 472 BNXT_TX_STATS_EXT_PFC_ENTRIES, 473 }; 474 475 static const struct { 476 long base_off; 477 char string[ETH_GSTRING_LEN]; 478 } bnxt_rx_bytes_pri_arr[] = { 479 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 480 }; 481 482 static const struct { 483 long base_off; 484 char string[ETH_GSTRING_LEN]; 485 } bnxt_rx_pkts_pri_arr[] = { 486 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 487 }; 488 489 static const struct { 490 long base_off; 491 char string[ETH_GSTRING_LEN]; 492 } bnxt_tx_bytes_pri_arr[] = { 493 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 494 }; 495 496 static const struct { 497 long base_off; 498 char string[ETH_GSTRING_LEN]; 499 } bnxt_tx_pkts_pri_arr[] = { 500 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 501 }; 502 503 #define BNXT_NUM_RING_ERR_STATS ARRAY_SIZE(bnxt_ring_err_stats_arr) 504 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 505 #define BNXT_NUM_STATS_PRI \ 506 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 507 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 508 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 509 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 510 511 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 512 { 513 if (BNXT_SUPPORTS_TPA(bp)) { 514 if (bp->max_tpa_v2) { 515 if (BNXT_CHIP_P5(bp)) 516 return BNXT_NUM_TPA_RING_STATS_P5; 517 return BNXT_NUM_TPA_RING_STATS_P7; 518 } 519 return BNXT_NUM_TPA_RING_STATS; 520 } 521 return 0; 522 } 523 524 static int bnxt_get_num_ring_stats(struct bnxt *bp) 525 { 526 int rx, tx, cmn; 527 528 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS + 529 bnxt_get_num_tpa_ring_stats(bp); 530 tx = NUM_RING_TX_HW_STATS; 531 cmn = NUM_RING_CMN_SW_STATS; 532 return rx * bp->rx_nr_rings + 533 tx * (bp->tx_nr_rings_xdp + bp->tx_nr_rings_per_tc) + 534 cmn * bp->cp_nr_rings; 535 } 536 537 static int bnxt_get_num_stats(struct bnxt *bp) 538 { 539 int num_stats = bnxt_get_num_ring_stats(bp); 540 int len; 541 542 num_stats += BNXT_NUM_RING_ERR_STATS; 543 544 if (bp->flags & BNXT_FLAG_PORT_STATS) 545 num_stats += BNXT_NUM_PORT_STATS; 546 547 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 548 len = min_t(int, bp->fw_rx_stats_ext_size, 549 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 550 num_stats += len; 551 len = min_t(int, bp->fw_tx_stats_ext_size, 552 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 553 num_stats += len; 554 if (bp->pri2cos_valid) 555 num_stats += BNXT_NUM_STATS_PRI; 556 } 557 558 return num_stats; 559 } 560 561 static int bnxt_get_sset_count(struct net_device *dev, int sset) 562 { 563 struct bnxt *bp = netdev_priv(dev); 564 565 switch (sset) { 566 case ETH_SS_STATS: 567 return bnxt_get_num_stats(bp); 568 case ETH_SS_TEST: 569 if (!bp->num_tests) 570 return -EOPNOTSUPP; 571 return bp->num_tests; 572 default: 573 return -EOPNOTSUPP; 574 } 575 } 576 577 static bool is_rx_ring(struct bnxt *bp, int ring_num) 578 { 579 return ring_num < bp->rx_nr_rings; 580 } 581 582 static bool is_tx_ring(struct bnxt *bp, int ring_num) 583 { 584 int tx_base = 0; 585 586 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 587 tx_base = bp->rx_nr_rings; 588 589 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings)) 590 return true; 591 return false; 592 } 593 594 static void bnxt_get_ethtool_stats(struct net_device *dev, 595 struct ethtool_stats *stats, u64 *buf) 596 { 597 struct bnxt_total_ring_err_stats ring_err_stats = {0}; 598 struct bnxt *bp = netdev_priv(dev); 599 u64 *curr, *prev; 600 u32 tpa_stats; 601 u32 i, j = 0; 602 603 if (!bp->bnapi) { 604 j += bnxt_get_num_ring_stats(bp); 605 goto skip_ring_stats; 606 } 607 608 tpa_stats = bnxt_get_num_tpa_ring_stats(bp); 609 for (i = 0; i < bp->cp_nr_rings; i++) { 610 struct bnxt_napi *bnapi = bp->bnapi[i]; 611 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 612 u64 *sw_stats = cpr->stats.sw_stats; 613 u64 *sw; 614 int k; 615 616 if (is_rx_ring(bp, i)) { 617 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++) 618 buf[j] = sw_stats[k]; 619 } 620 if (is_tx_ring(bp, i)) { 621 k = NUM_RING_RX_HW_STATS; 622 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 623 j++, k++) 624 buf[j] = sw_stats[k]; 625 } 626 if (!tpa_stats || !is_rx_ring(bp, i)) 627 goto skip_tpa_ring_stats; 628 629 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 630 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS + 631 tpa_stats; j++, k++) 632 buf[j] = sw_stats[k]; 633 634 skip_tpa_ring_stats: 635 sw = (u64 *)&cpr->sw_stats->rx; 636 if (is_rx_ring(bp, i)) { 637 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++) 638 buf[j] = sw[k]; 639 } 640 641 sw = (u64 *)&cpr->sw_stats->cmn; 642 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++) 643 buf[j] = sw[k]; 644 } 645 646 bnxt_get_ring_err_stats(bp, &ring_err_stats); 647 648 skip_ring_stats: 649 curr = &ring_err_stats.rx_total_l4_csum_errors; 650 prev = &bp->ring_err_stats_prev.rx_total_l4_csum_errors; 651 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++, j++, curr++, prev++) 652 buf[j] = *curr + *prev; 653 654 if (bp->flags & BNXT_FLAG_PORT_STATS) { 655 u64 *port_stats = bp->port_stats.sw_stats; 656 657 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) 658 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset); 659 } 660 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 661 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats; 662 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats; 663 u32 len; 664 665 len = min_t(u32, bp->fw_rx_stats_ext_size, 666 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 667 for (i = 0; i < len; i++, j++) { 668 buf[j] = *(rx_port_stats_ext + 669 bnxt_port_stats_ext_arr[i].offset); 670 } 671 len = min_t(u32, bp->fw_tx_stats_ext_size, 672 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 673 for (i = 0; i < len; i++, j++) { 674 buf[j] = *(tx_port_stats_ext + 675 bnxt_tx_port_stats_ext_arr[i].offset); 676 } 677 if (bp->pri2cos_valid) { 678 for (i = 0; i < 8; i++, j++) { 679 long n = bnxt_rx_bytes_pri_arr[i].base_off + 680 bp->pri2cos_idx[i]; 681 682 buf[j] = *(rx_port_stats_ext + n); 683 } 684 for (i = 0; i < 8; i++, j++) { 685 long n = bnxt_rx_pkts_pri_arr[i].base_off + 686 bp->pri2cos_idx[i]; 687 688 buf[j] = *(rx_port_stats_ext + n); 689 } 690 for (i = 0; i < 8; i++, j++) { 691 u8 cos_idx = bp->pri2cos_idx[i]; 692 long n; 693 694 n = bnxt_tx_bytes_pri_arr[i].base_off + cos_idx; 695 buf[j] = *(tx_port_stats_ext + n); 696 if (bp->cos0_cos1_shared && !cos_idx) 697 buf[j] += *(tx_port_stats_ext + n + 1); 698 } 699 for (i = 0; i < 8; i++, j++) { 700 u8 cos_idx = bp->pri2cos_idx[i]; 701 long n; 702 703 n = bnxt_tx_pkts_pri_arr[i].base_off + cos_idx; 704 buf[j] = *(tx_port_stats_ext + n); 705 if (bp->cos0_cos1_shared && !cos_idx) 706 buf[j] += *(tx_port_stats_ext + n + 1); 707 } 708 } 709 } 710 } 711 712 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 713 { 714 struct bnxt *bp = netdev_priv(dev); 715 u32 i, j, num_str; 716 const char *str; 717 718 switch (stringset) { 719 case ETH_SS_STATS: 720 for (i = 0; i < bp->cp_nr_rings; i++) { 721 if (is_rx_ring(bp, i)) 722 for (j = 0; j < NUM_RING_RX_HW_STATS; j++) { 723 str = bnxt_ring_rx_stats_str[j]; 724 ethtool_sprintf(&buf, "[%d]: %s", i, 725 str); 726 } 727 if (is_tx_ring(bp, i)) 728 for (j = 0; j < NUM_RING_TX_HW_STATS; j++) { 729 str = bnxt_ring_tx_stats_str[j]; 730 ethtool_sprintf(&buf, "[%d]: %s", i, 731 str); 732 } 733 num_str = bnxt_get_num_tpa_ring_stats(bp); 734 if (!num_str || !is_rx_ring(bp, i)) 735 goto skip_tpa_stats; 736 737 if (bp->max_tpa_v2) 738 for (j = 0; j < num_str; j++) { 739 str = bnxt_ring_tpa2_stats_str[j]; 740 ethtool_sprintf(&buf, "[%d]: %s", i, 741 str); 742 } 743 else 744 for (j = 0; j < num_str; j++) { 745 str = bnxt_ring_tpa_stats_str[j]; 746 ethtool_sprintf(&buf, "[%d]: %s", i, 747 str); 748 } 749 skip_tpa_stats: 750 if (is_rx_ring(bp, i)) 751 for (j = 0; j < NUM_RING_RX_SW_STATS; j++) { 752 str = bnxt_rx_sw_stats_str[j]; 753 ethtool_sprintf(&buf, "[%d]: %s", i, 754 str); 755 } 756 for (j = 0; j < NUM_RING_CMN_SW_STATS; j++) { 757 str = bnxt_cmn_sw_stats_str[j]; 758 ethtool_sprintf(&buf, "[%d]: %s", i, str); 759 } 760 } 761 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++) 762 ethtool_puts(&buf, bnxt_ring_err_stats_arr[i]); 763 764 if (bp->flags & BNXT_FLAG_PORT_STATS) 765 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 766 str = bnxt_port_stats_arr[i].string; 767 ethtool_puts(&buf, str); 768 } 769 770 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 771 u32 len; 772 773 len = min_t(u32, bp->fw_rx_stats_ext_size, 774 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 775 for (i = 0; i < len; i++) { 776 str = bnxt_port_stats_ext_arr[i].string; 777 ethtool_puts(&buf, str); 778 } 779 780 len = min_t(u32, bp->fw_tx_stats_ext_size, 781 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 782 for (i = 0; i < len; i++) { 783 str = bnxt_tx_port_stats_ext_arr[i].string; 784 ethtool_puts(&buf, str); 785 } 786 787 if (bp->pri2cos_valid) { 788 for (i = 0; i < 8; i++) { 789 str = bnxt_rx_bytes_pri_arr[i].string; 790 ethtool_puts(&buf, str); 791 } 792 793 for (i = 0; i < 8; i++) { 794 str = bnxt_rx_pkts_pri_arr[i].string; 795 ethtool_puts(&buf, str); 796 } 797 798 for (i = 0; i < 8; i++) { 799 str = bnxt_tx_bytes_pri_arr[i].string; 800 ethtool_puts(&buf, str); 801 } 802 803 for (i = 0; i < 8; i++) { 804 str = bnxt_tx_pkts_pri_arr[i].string; 805 ethtool_puts(&buf, str); 806 } 807 } 808 } 809 break; 810 case ETH_SS_TEST: 811 if (bp->num_tests) 812 for (i = 0; i < bp->num_tests; i++) 813 ethtool_puts(&buf, bp->test_info->string[i]); 814 break; 815 default: 816 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 817 stringset); 818 break; 819 } 820 } 821 822 static void bnxt_get_ringparam(struct net_device *dev, 823 struct ethtool_ringparam *ering, 824 struct kernel_ethtool_ringparam *kernel_ering, 825 struct netlink_ext_ack *extack) 826 { 827 struct bnxt *bp = netdev_priv(dev); 828 829 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 830 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA; 831 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 832 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_ENABLED; 833 } else { 834 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 835 ering->rx_jumbo_max_pending = 0; 836 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_DISABLED; 837 } 838 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 839 840 ering->rx_pending = bp->rx_ring_size; 841 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 842 ering->tx_pending = bp->tx_ring_size; 843 844 kernel_ering->hds_thresh_max = BNXT_HDS_THRESHOLD_MAX; 845 } 846 847 static int bnxt_set_ringparam(struct net_device *dev, 848 struct ethtool_ringparam *ering, 849 struct kernel_ethtool_ringparam *kernel_ering, 850 struct netlink_ext_ack *extack) 851 { 852 u8 tcp_data_split = kernel_ering->tcp_data_split; 853 struct bnxt *bp = netdev_priv(dev); 854 u8 hds_config_mod; 855 856 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 857 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 858 (ering->tx_pending < BNXT_MIN_TX_DESC_CNT)) 859 return -EINVAL; 860 861 hds_config_mod = tcp_data_split != dev->cfg->hds_config; 862 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_DISABLED && hds_config_mod) 863 return -EINVAL; 864 865 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_ENABLED && 866 hds_config_mod && BNXT_RX_PAGE_MODE(bp)) { 867 NL_SET_ERR_MSG_MOD(extack, "tcp-data-split is disallowed when XDP is attached"); 868 return -EINVAL; 869 } 870 871 if (netif_running(dev)) 872 bnxt_close_nic(bp, false, false); 873 874 if (hds_config_mod) { 875 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_ENABLED) 876 bp->flags |= BNXT_FLAG_HDS; 877 else if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_UNKNOWN) 878 bp->flags &= ~BNXT_FLAG_HDS; 879 } 880 881 bp->rx_ring_size = ering->rx_pending; 882 bp->tx_ring_size = ering->tx_pending; 883 bnxt_set_ring_params(bp); 884 885 if (netif_running(dev)) 886 return bnxt_open_nic(bp, false, false); 887 888 return 0; 889 } 890 891 static void bnxt_get_channels(struct net_device *dev, 892 struct ethtool_channels *channel) 893 { 894 struct bnxt *bp = netdev_priv(dev); 895 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 896 int max_rx_rings, max_tx_rings, tcs; 897 int max_tx_sch_inputs, tx_grps; 898 899 /* Get the most up-to-date max_tx_sch_inputs. */ 900 if (netif_running(dev) && BNXT_NEW_RM(bp)) 901 bnxt_hwrm_func_resc_qcaps(bp, false); 902 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 903 904 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 905 if (max_tx_sch_inputs) 906 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 907 908 tcs = bp->num_tc; 909 tx_grps = max(tcs, 1); 910 if (bp->tx_nr_rings_xdp) 911 tx_grps++; 912 max_tx_rings /= tx_grps; 913 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 914 915 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 916 max_rx_rings = 0; 917 max_tx_rings = 0; 918 } 919 if (max_tx_sch_inputs) 920 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 921 922 if (tcs > 1) 923 max_tx_rings /= tcs; 924 925 channel->max_rx = max_rx_rings; 926 channel->max_tx = max_tx_rings; 927 channel->max_other = 0; 928 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 929 channel->combined_count = bp->rx_nr_rings; 930 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 931 channel->combined_count--; 932 } else { 933 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 934 channel->rx_count = bp->rx_nr_rings; 935 channel->tx_count = bp->tx_nr_rings_per_tc; 936 } 937 } 938 } 939 940 static int bnxt_set_channels(struct net_device *dev, 941 struct ethtool_channels *channel) 942 { 943 struct bnxt *bp = netdev_priv(dev); 944 int req_tx_rings, req_rx_rings, tcs; 945 bool sh = false; 946 int tx_xdp = 0; 947 int rc = 0; 948 int tx_cp; 949 950 if (channel->other_count) 951 return -EINVAL; 952 953 if (!channel->combined_count && 954 (!channel->rx_count || !channel->tx_count)) 955 return -EINVAL; 956 957 if (channel->combined_count && 958 (channel->rx_count || channel->tx_count)) 959 return -EINVAL; 960 961 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 962 channel->tx_count)) 963 return -EINVAL; 964 965 if (channel->combined_count) 966 sh = true; 967 968 tcs = bp->num_tc; 969 970 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 971 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 972 if (bp->tx_nr_rings_xdp) { 973 if (!sh) { 974 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 975 return -EINVAL; 976 } 977 tx_xdp = req_rx_rings; 978 } 979 980 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) != 981 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) && 982 netif_is_rxfh_configured(dev)) { 983 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n"); 984 return -EINVAL; 985 } 986 987 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 988 if (rc) { 989 netdev_warn(dev, "Unable to allocate the requested rings\n"); 990 return rc; 991 } 992 993 if (netif_running(dev)) { 994 if (BNXT_PF(bp)) { 995 /* TODO CHIMP_FW: Send message to all VF's 996 * before PF unload 997 */ 998 } 999 bnxt_close_nic(bp, true, false); 1000 } 1001 1002 if (sh) { 1003 bp->flags |= BNXT_FLAG_SHARED_RINGS; 1004 bp->rx_nr_rings = channel->combined_count; 1005 bp->tx_nr_rings_per_tc = channel->combined_count; 1006 } else { 1007 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 1008 bp->rx_nr_rings = channel->rx_count; 1009 bp->tx_nr_rings_per_tc = channel->tx_count; 1010 } 1011 bp->tx_nr_rings_xdp = tx_xdp; 1012 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 1013 if (tcs > 1) 1014 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 1015 1016 tx_cp = bnxt_num_tx_to_cp(bp, bp->tx_nr_rings); 1017 bp->cp_nr_rings = sh ? max_t(int, tx_cp, bp->rx_nr_rings) : 1018 tx_cp + bp->rx_nr_rings; 1019 1020 /* After changing number of rx channels, update NTUPLE feature. */ 1021 netdev_update_features(dev); 1022 if (netif_running(dev)) { 1023 rc = bnxt_open_nic(bp, true, false); 1024 if ((!rc) && BNXT_PF(bp)) { 1025 /* TODO CHIMP_FW: Send message to all VF's 1026 * to renable 1027 */ 1028 } 1029 } else { 1030 rc = bnxt_reserve_rings(bp, true); 1031 } 1032 1033 return rc; 1034 } 1035 1036 static u32 bnxt_get_all_fltr_ids_rcu(struct bnxt *bp, struct hlist_head tbl[], 1037 int tbl_size, u32 *ids, u32 start, 1038 u32 id_cnt) 1039 { 1040 int i, j = start; 1041 1042 if (j >= id_cnt) 1043 return j; 1044 for (i = 0; i < tbl_size; i++) { 1045 struct hlist_head *head; 1046 struct bnxt_filter_base *fltr; 1047 1048 head = &tbl[i]; 1049 hlist_for_each_entry_rcu(fltr, head, hash) { 1050 if (!fltr->flags || 1051 test_bit(BNXT_FLTR_FW_DELETED, &fltr->state)) 1052 continue; 1053 ids[j++] = fltr->sw_id; 1054 if (j == id_cnt) 1055 return j; 1056 } 1057 } 1058 return j; 1059 } 1060 1061 static struct bnxt_filter_base *bnxt_get_one_fltr_rcu(struct bnxt *bp, 1062 struct hlist_head tbl[], 1063 int tbl_size, u32 id) 1064 { 1065 int i; 1066 1067 for (i = 0; i < tbl_size; i++) { 1068 struct hlist_head *head; 1069 struct bnxt_filter_base *fltr; 1070 1071 head = &tbl[i]; 1072 hlist_for_each_entry_rcu(fltr, head, hash) { 1073 if (fltr->flags && fltr->sw_id == id) 1074 return fltr; 1075 } 1076 } 1077 return NULL; 1078 } 1079 1080 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 1081 u32 *rule_locs) 1082 { 1083 u32 count; 1084 1085 cmd->data = bp->ntp_fltr_count; 1086 rcu_read_lock(); 1087 count = bnxt_get_all_fltr_ids_rcu(bp, bp->l2_fltr_hash_tbl, 1088 BNXT_L2_FLTR_HASH_SIZE, rule_locs, 0, 1089 cmd->rule_cnt); 1090 cmd->rule_cnt = bnxt_get_all_fltr_ids_rcu(bp, bp->ntp_fltr_hash_tbl, 1091 BNXT_NTP_FLTR_HASH_SIZE, 1092 rule_locs, count, 1093 cmd->rule_cnt); 1094 rcu_read_unlock(); 1095 1096 return 0; 1097 } 1098 1099 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1100 { 1101 struct ethtool_rx_flow_spec *fs = 1102 (struct ethtool_rx_flow_spec *)&cmd->fs; 1103 struct bnxt_filter_base *fltr_base; 1104 struct bnxt_ntuple_filter *fltr; 1105 struct bnxt_flow_masks *fmasks; 1106 struct flow_keys *fkeys; 1107 int rc = -EINVAL; 1108 1109 if (fs->location >= bp->max_fltr) 1110 return rc; 1111 1112 rcu_read_lock(); 1113 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl, 1114 BNXT_L2_FLTR_HASH_SIZE, 1115 fs->location); 1116 if (fltr_base) { 1117 struct ethhdr *h_ether = &fs->h_u.ether_spec; 1118 struct ethhdr *m_ether = &fs->m_u.ether_spec; 1119 struct bnxt_l2_filter *l2_fltr; 1120 struct bnxt_l2_key *l2_key; 1121 1122 l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base); 1123 l2_key = &l2_fltr->l2_key; 1124 fs->flow_type = ETHER_FLOW; 1125 ether_addr_copy(h_ether->h_dest, l2_key->dst_mac_addr); 1126 eth_broadcast_addr(m_ether->h_dest); 1127 if (l2_key->vlan) { 1128 struct ethtool_flow_ext *m_ext = &fs->m_ext; 1129 struct ethtool_flow_ext *h_ext = &fs->h_ext; 1130 1131 fs->flow_type |= FLOW_EXT; 1132 m_ext->vlan_tci = htons(0xfff); 1133 h_ext->vlan_tci = htons(l2_key->vlan); 1134 } 1135 if (fltr_base->flags & BNXT_ACT_RING_DST) 1136 fs->ring_cookie = fltr_base->rxq; 1137 if (fltr_base->flags & BNXT_ACT_FUNC_DST) 1138 fs->ring_cookie = (u64)(fltr_base->vf_idx + 1) << 1139 ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 1140 rcu_read_unlock(); 1141 return 0; 1142 } 1143 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl, 1144 BNXT_NTP_FLTR_HASH_SIZE, 1145 fs->location); 1146 if (!fltr_base) { 1147 rcu_read_unlock(); 1148 return rc; 1149 } 1150 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base); 1151 1152 fkeys = &fltr->fkeys; 1153 fmasks = &fltr->fmasks; 1154 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 1155 if (fkeys->basic.ip_proto == BNXT_IP_PROTO_WILDCARD) { 1156 fs->flow_type = IP_USER_FLOW; 1157 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 1158 fs->h_u.usr_ip4_spec.proto = BNXT_IP_PROTO_WILDCARD; 1159 fs->m_u.usr_ip4_spec.proto = 0; 1160 } else if (fkeys->basic.ip_proto == IPPROTO_ICMP) { 1161 fs->flow_type = IP_USER_FLOW; 1162 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 1163 fs->h_u.usr_ip4_spec.proto = IPPROTO_ICMP; 1164 fs->m_u.usr_ip4_spec.proto = BNXT_IP_PROTO_FULL_MASK; 1165 } else if (fkeys->basic.ip_proto == IPPROTO_TCP) { 1166 fs->flow_type = TCP_V4_FLOW; 1167 } else if (fkeys->basic.ip_proto == IPPROTO_UDP) { 1168 fs->flow_type = UDP_V4_FLOW; 1169 } else { 1170 goto fltr_err; 1171 } 1172 1173 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 1174 fs->m_u.tcp_ip4_spec.ip4src = fmasks->addrs.v4addrs.src; 1175 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 1176 fs->m_u.tcp_ip4_spec.ip4dst = fmasks->addrs.v4addrs.dst; 1177 if (fs->flow_type == TCP_V4_FLOW || 1178 fs->flow_type == UDP_V4_FLOW) { 1179 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 1180 fs->m_u.tcp_ip4_spec.psrc = fmasks->ports.src; 1181 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 1182 fs->m_u.tcp_ip4_spec.pdst = fmasks->ports.dst; 1183 } 1184 } else { 1185 if (fkeys->basic.ip_proto == BNXT_IP_PROTO_WILDCARD) { 1186 fs->flow_type = IPV6_USER_FLOW; 1187 fs->h_u.usr_ip6_spec.l4_proto = BNXT_IP_PROTO_WILDCARD; 1188 fs->m_u.usr_ip6_spec.l4_proto = 0; 1189 } else if (fkeys->basic.ip_proto == IPPROTO_ICMPV6) { 1190 fs->flow_type = IPV6_USER_FLOW; 1191 fs->h_u.usr_ip6_spec.l4_proto = IPPROTO_ICMPV6; 1192 fs->m_u.usr_ip6_spec.l4_proto = BNXT_IP_PROTO_FULL_MASK; 1193 } else if (fkeys->basic.ip_proto == IPPROTO_TCP) { 1194 fs->flow_type = TCP_V6_FLOW; 1195 } else if (fkeys->basic.ip_proto == IPPROTO_UDP) { 1196 fs->flow_type = UDP_V6_FLOW; 1197 } else { 1198 goto fltr_err; 1199 } 1200 1201 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 1202 fkeys->addrs.v6addrs.src; 1203 *(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6src[0] = 1204 fmasks->addrs.v6addrs.src; 1205 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 1206 fkeys->addrs.v6addrs.dst; 1207 *(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6dst[0] = 1208 fmasks->addrs.v6addrs.dst; 1209 if (fs->flow_type == TCP_V6_FLOW || 1210 fs->flow_type == UDP_V6_FLOW) { 1211 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 1212 fs->m_u.tcp_ip6_spec.psrc = fmasks->ports.src; 1213 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 1214 fs->m_u.tcp_ip6_spec.pdst = fmasks->ports.dst; 1215 } 1216 } 1217 1218 if (fltr->base.flags & BNXT_ACT_DROP) { 1219 fs->ring_cookie = RX_CLS_FLOW_DISC; 1220 } else if (fltr->base.flags & BNXT_ACT_RSS_CTX) { 1221 fs->flow_type |= FLOW_RSS; 1222 cmd->rss_context = fltr->base.fw_vnic_id; 1223 } else { 1224 fs->ring_cookie = fltr->base.rxq; 1225 } 1226 rc = 0; 1227 1228 fltr_err: 1229 rcu_read_unlock(); 1230 1231 return rc; 1232 } 1233 1234 static struct bnxt_rss_ctx *bnxt_get_rss_ctx_from_index(struct bnxt *bp, 1235 u32 index) 1236 { 1237 struct ethtool_rxfh_context *ctx; 1238 1239 ctx = xa_load(&bp->dev->ethtool->rss_ctx, index); 1240 if (!ctx) 1241 return NULL; 1242 return ethtool_rxfh_context_priv(ctx); 1243 } 1244 1245 static int bnxt_alloc_vnic_rss_table(struct bnxt *bp, 1246 struct bnxt_vnic_info *vnic) 1247 { 1248 int size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5); 1249 1250 vnic->rss_table_size = size + HW_HASH_KEY_SIZE; 1251 vnic->rss_table = dma_alloc_coherent(&bp->pdev->dev, 1252 vnic->rss_table_size, 1253 &vnic->rss_table_dma_addr, 1254 GFP_KERNEL); 1255 if (!vnic->rss_table) 1256 return -ENOMEM; 1257 1258 vnic->rss_hash_key = ((void *)vnic->rss_table) + size; 1259 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; 1260 return 0; 1261 } 1262 1263 static int bnxt_add_l2_cls_rule(struct bnxt *bp, 1264 struct ethtool_rx_flow_spec *fs) 1265 { 1266 u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1267 u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1268 struct ethhdr *h_ether = &fs->h_u.ether_spec; 1269 struct ethhdr *m_ether = &fs->m_u.ether_spec; 1270 struct bnxt_l2_filter *fltr; 1271 struct bnxt_l2_key key; 1272 u16 vnic_id; 1273 u8 flags; 1274 int rc; 1275 1276 if (BNXT_CHIP_P5_PLUS(bp)) 1277 return -EOPNOTSUPP; 1278 1279 if (!is_broadcast_ether_addr(m_ether->h_dest)) 1280 return -EINVAL; 1281 ether_addr_copy(key.dst_mac_addr, h_ether->h_dest); 1282 key.vlan = 0; 1283 if (fs->flow_type & FLOW_EXT) { 1284 struct ethtool_flow_ext *m_ext = &fs->m_ext; 1285 struct ethtool_flow_ext *h_ext = &fs->h_ext; 1286 1287 if (m_ext->vlan_tci != htons(0xfff) || !h_ext->vlan_tci) 1288 return -EINVAL; 1289 key.vlan = ntohs(h_ext->vlan_tci); 1290 } 1291 1292 if (vf) { 1293 flags = BNXT_ACT_FUNC_DST; 1294 vnic_id = 0xffff; 1295 vf--; 1296 } else { 1297 flags = BNXT_ACT_RING_DST; 1298 vnic_id = bp->vnic_info[ring + 1].fw_vnic_id; 1299 } 1300 fltr = bnxt_alloc_new_l2_filter(bp, &key, flags); 1301 if (IS_ERR(fltr)) 1302 return PTR_ERR(fltr); 1303 1304 fltr->base.fw_vnic_id = vnic_id; 1305 fltr->base.rxq = ring; 1306 fltr->base.vf_idx = vf; 1307 rc = bnxt_hwrm_l2_filter_alloc(bp, fltr); 1308 if (rc) 1309 bnxt_del_l2_filter(bp, fltr); 1310 else 1311 fs->location = fltr->base.sw_id; 1312 return rc; 1313 } 1314 1315 static bool bnxt_verify_ntuple_ip4_flow(struct ethtool_usrip4_spec *ip_spec, 1316 struct ethtool_usrip4_spec *ip_mask) 1317 { 1318 u8 mproto = ip_mask->proto; 1319 u8 sproto = ip_spec->proto; 1320 1321 if (ip_mask->l4_4_bytes || ip_mask->tos || 1322 ip_spec->ip_ver != ETH_RX_NFC_IP4 || 1323 (mproto && (mproto != BNXT_IP_PROTO_FULL_MASK || sproto != IPPROTO_ICMP))) 1324 return false; 1325 return true; 1326 } 1327 1328 static bool bnxt_verify_ntuple_ip6_flow(struct ethtool_usrip6_spec *ip_spec, 1329 struct ethtool_usrip6_spec *ip_mask) 1330 { 1331 u8 mproto = ip_mask->l4_proto; 1332 u8 sproto = ip_spec->l4_proto; 1333 1334 if (ip_mask->l4_4_bytes || ip_mask->tclass || 1335 (mproto && (mproto != BNXT_IP_PROTO_FULL_MASK || sproto != IPPROTO_ICMPV6))) 1336 return false; 1337 return true; 1338 } 1339 1340 static int bnxt_add_ntuple_cls_rule(struct bnxt *bp, 1341 struct ethtool_rxnfc *cmd) 1342 { 1343 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1344 struct bnxt_ntuple_filter *new_fltr, *fltr; 1345 u32 flow_type = fs->flow_type & 0xff; 1346 struct bnxt_l2_filter *l2_fltr; 1347 struct bnxt_flow_masks *fmasks; 1348 struct flow_keys *fkeys; 1349 u32 idx, ring; 1350 int rc; 1351 u8 vf; 1352 1353 if (!bp->vnic_info) 1354 return -EAGAIN; 1355 1356 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1357 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1358 if ((fs->flow_type & (FLOW_MAC_EXT | FLOW_EXT)) || vf) 1359 return -EOPNOTSUPP; 1360 1361 if (flow_type == IP_USER_FLOW) { 1362 if (!bnxt_verify_ntuple_ip4_flow(&fs->h_u.usr_ip4_spec, 1363 &fs->m_u.usr_ip4_spec)) 1364 return -EOPNOTSUPP; 1365 } 1366 1367 if (flow_type == IPV6_USER_FLOW) { 1368 if (!bnxt_verify_ntuple_ip6_flow(&fs->h_u.usr_ip6_spec, 1369 &fs->m_u.usr_ip6_spec)) 1370 return -EOPNOTSUPP; 1371 } 1372 1373 new_fltr = kzalloc(sizeof(*new_fltr), GFP_KERNEL); 1374 if (!new_fltr) 1375 return -ENOMEM; 1376 1377 l2_fltr = bp->vnic_info[BNXT_VNIC_DEFAULT].l2_filters[0]; 1378 atomic_inc(&l2_fltr->refcnt); 1379 new_fltr->l2_fltr = l2_fltr; 1380 fmasks = &new_fltr->fmasks; 1381 fkeys = &new_fltr->fkeys; 1382 1383 rc = -EOPNOTSUPP; 1384 switch (flow_type) { 1385 case IP_USER_FLOW: { 1386 struct ethtool_usrip4_spec *ip_spec = &fs->h_u.usr_ip4_spec; 1387 struct ethtool_usrip4_spec *ip_mask = &fs->m_u.usr_ip4_spec; 1388 1389 fkeys->basic.ip_proto = ip_mask->proto ? ip_spec->proto 1390 : BNXT_IP_PROTO_WILDCARD; 1391 fkeys->basic.n_proto = htons(ETH_P_IP); 1392 fkeys->addrs.v4addrs.src = ip_spec->ip4src; 1393 fmasks->addrs.v4addrs.src = ip_mask->ip4src; 1394 fkeys->addrs.v4addrs.dst = ip_spec->ip4dst; 1395 fmasks->addrs.v4addrs.dst = ip_mask->ip4dst; 1396 break; 1397 } 1398 case TCP_V4_FLOW: 1399 case UDP_V4_FLOW: { 1400 struct ethtool_tcpip4_spec *ip_spec = &fs->h_u.tcp_ip4_spec; 1401 struct ethtool_tcpip4_spec *ip_mask = &fs->m_u.tcp_ip4_spec; 1402 1403 fkeys->basic.ip_proto = IPPROTO_TCP; 1404 if (flow_type == UDP_V4_FLOW) 1405 fkeys->basic.ip_proto = IPPROTO_UDP; 1406 fkeys->basic.n_proto = htons(ETH_P_IP); 1407 fkeys->addrs.v4addrs.src = ip_spec->ip4src; 1408 fmasks->addrs.v4addrs.src = ip_mask->ip4src; 1409 fkeys->addrs.v4addrs.dst = ip_spec->ip4dst; 1410 fmasks->addrs.v4addrs.dst = ip_mask->ip4dst; 1411 fkeys->ports.src = ip_spec->psrc; 1412 fmasks->ports.src = ip_mask->psrc; 1413 fkeys->ports.dst = ip_spec->pdst; 1414 fmasks->ports.dst = ip_mask->pdst; 1415 break; 1416 } 1417 case IPV6_USER_FLOW: { 1418 struct ethtool_usrip6_spec *ip_spec = &fs->h_u.usr_ip6_spec; 1419 struct ethtool_usrip6_spec *ip_mask = &fs->m_u.usr_ip6_spec; 1420 1421 fkeys->basic.ip_proto = ip_mask->l4_proto ? ip_spec->l4_proto 1422 : BNXT_IP_PROTO_WILDCARD; 1423 fkeys->basic.n_proto = htons(ETH_P_IPV6); 1424 fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src; 1425 fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src; 1426 fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst; 1427 fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst; 1428 break; 1429 } 1430 case TCP_V6_FLOW: 1431 case UDP_V6_FLOW: { 1432 struct ethtool_tcpip6_spec *ip_spec = &fs->h_u.tcp_ip6_spec; 1433 struct ethtool_tcpip6_spec *ip_mask = &fs->m_u.tcp_ip6_spec; 1434 1435 fkeys->basic.ip_proto = IPPROTO_TCP; 1436 if (flow_type == UDP_V6_FLOW) 1437 fkeys->basic.ip_proto = IPPROTO_UDP; 1438 fkeys->basic.n_proto = htons(ETH_P_IPV6); 1439 1440 fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src; 1441 fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src; 1442 fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst; 1443 fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst; 1444 fkeys->ports.src = ip_spec->psrc; 1445 fmasks->ports.src = ip_mask->psrc; 1446 fkeys->ports.dst = ip_spec->pdst; 1447 fmasks->ports.dst = ip_mask->pdst; 1448 break; 1449 } 1450 default: 1451 rc = -EOPNOTSUPP; 1452 goto ntuple_err; 1453 } 1454 if (!memcmp(&BNXT_FLOW_MASK_NONE, fmasks, sizeof(*fmasks))) 1455 goto ntuple_err; 1456 1457 idx = bnxt_get_ntp_filter_idx(bp, fkeys, NULL); 1458 rcu_read_lock(); 1459 fltr = bnxt_lookup_ntp_filter_from_idx(bp, new_fltr, idx); 1460 if (fltr) { 1461 rcu_read_unlock(); 1462 rc = -EEXIST; 1463 goto ntuple_err; 1464 } 1465 rcu_read_unlock(); 1466 1467 new_fltr->base.flags = BNXT_ACT_NO_AGING; 1468 if (fs->flow_type & FLOW_RSS) { 1469 struct bnxt_rss_ctx *rss_ctx; 1470 1471 new_fltr->base.fw_vnic_id = 0; 1472 new_fltr->base.flags |= BNXT_ACT_RSS_CTX; 1473 rss_ctx = bnxt_get_rss_ctx_from_index(bp, cmd->rss_context); 1474 if (rss_ctx) { 1475 new_fltr->base.fw_vnic_id = rss_ctx->index; 1476 } else { 1477 rc = -EINVAL; 1478 goto ntuple_err; 1479 } 1480 } 1481 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1482 new_fltr->base.flags |= BNXT_ACT_DROP; 1483 else 1484 new_fltr->base.rxq = ring; 1485 __set_bit(BNXT_FLTR_VALID, &new_fltr->base.state); 1486 rc = bnxt_insert_ntp_filter(bp, new_fltr, idx); 1487 if (!rc) { 1488 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, new_fltr); 1489 if (rc) { 1490 bnxt_del_ntp_filter(bp, new_fltr); 1491 return rc; 1492 } 1493 fs->location = new_fltr->base.sw_id; 1494 return 0; 1495 } 1496 1497 ntuple_err: 1498 atomic_dec(&l2_fltr->refcnt); 1499 kfree(new_fltr); 1500 return rc; 1501 } 1502 1503 static int bnxt_srxclsrlins(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1504 { 1505 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1506 u32 ring, flow_type; 1507 int rc; 1508 u8 vf; 1509 1510 if (!netif_running(bp->dev)) 1511 return -EAGAIN; 1512 if (!(bp->flags & BNXT_FLAG_RFS)) 1513 return -EPERM; 1514 if (fs->location != RX_CLS_LOC_ANY) 1515 return -EINVAL; 1516 1517 flow_type = fs->flow_type; 1518 if ((flow_type == IP_USER_FLOW || 1519 flow_type == IPV6_USER_FLOW) && 1520 !(bp->fw_cap & BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO)) 1521 return -EOPNOTSUPP; 1522 if (flow_type & FLOW_MAC_EXT) 1523 return -EINVAL; 1524 flow_type &= ~FLOW_EXT; 1525 1526 if (fs->ring_cookie == RX_CLS_FLOW_DISC && flow_type != ETHER_FLOW) 1527 return bnxt_add_ntuple_cls_rule(bp, cmd); 1528 1529 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1530 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1531 if (BNXT_VF(bp) && vf) 1532 return -EINVAL; 1533 if (BNXT_PF(bp) && vf > bp->pf.active_vfs) 1534 return -EINVAL; 1535 if (!vf && ring >= bp->rx_nr_rings) 1536 return -EINVAL; 1537 1538 if (flow_type == ETHER_FLOW) 1539 rc = bnxt_add_l2_cls_rule(bp, fs); 1540 else 1541 rc = bnxt_add_ntuple_cls_rule(bp, cmd); 1542 return rc; 1543 } 1544 1545 static int bnxt_srxclsrldel(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1546 { 1547 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1548 struct bnxt_filter_base *fltr_base; 1549 struct bnxt_ntuple_filter *fltr; 1550 u32 id = fs->location; 1551 1552 rcu_read_lock(); 1553 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl, 1554 BNXT_L2_FLTR_HASH_SIZE, id); 1555 if (fltr_base) { 1556 struct bnxt_l2_filter *l2_fltr; 1557 1558 l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base); 1559 rcu_read_unlock(); 1560 bnxt_hwrm_l2_filter_free(bp, l2_fltr); 1561 bnxt_del_l2_filter(bp, l2_fltr); 1562 return 0; 1563 } 1564 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl, 1565 BNXT_NTP_FLTR_HASH_SIZE, id); 1566 if (!fltr_base) { 1567 rcu_read_unlock(); 1568 return -ENOENT; 1569 } 1570 1571 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base); 1572 if (!(fltr->base.flags & BNXT_ACT_NO_AGING)) { 1573 rcu_read_unlock(); 1574 return -EINVAL; 1575 } 1576 rcu_read_unlock(); 1577 bnxt_hwrm_cfa_ntuple_filter_free(bp, fltr); 1578 bnxt_del_ntp_filter(bp, fltr); 1579 return 0; 1580 } 1581 1582 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1583 { 1584 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1585 return RXH_IP_SRC | RXH_IP_DST; 1586 return 0; 1587 } 1588 1589 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1590 { 1591 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1592 return RXH_IP_SRC | RXH_IP_DST; 1593 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL) 1594 return RXH_IP_SRC | RXH_IP_DST | RXH_IP6_FL; 1595 return 0; 1596 } 1597 1598 static int bnxt_get_rxfh_fields(struct net_device *dev, 1599 struct ethtool_rxfh_fields *cmd) 1600 { 1601 struct bnxt *bp = netdev_priv(dev); 1602 1603 cmd->data = 0; 1604 switch (cmd->flow_type) { 1605 case TCP_V4_FLOW: 1606 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1607 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1608 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1609 cmd->data |= get_ethtool_ipv4_rss(bp); 1610 break; 1611 case UDP_V4_FLOW: 1612 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1613 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1614 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1615 fallthrough; 1616 case AH_ESP_V4_FLOW: 1617 if (bp->rss_hash_cfg & 1618 (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1619 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4)) 1620 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1621 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1622 fallthrough; 1623 case SCTP_V4_FLOW: 1624 case AH_V4_FLOW: 1625 case ESP_V4_FLOW: 1626 case IPV4_FLOW: 1627 cmd->data |= get_ethtool_ipv4_rss(bp); 1628 break; 1629 1630 case TCP_V6_FLOW: 1631 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1632 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1633 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1634 cmd->data |= get_ethtool_ipv6_rss(bp); 1635 break; 1636 case UDP_V6_FLOW: 1637 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1638 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1639 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1640 fallthrough; 1641 case AH_ESP_V6_FLOW: 1642 if (bp->rss_hash_cfg & 1643 (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1644 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6)) 1645 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1646 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1647 fallthrough; 1648 case SCTP_V6_FLOW: 1649 case AH_V6_FLOW: 1650 case ESP_V6_FLOW: 1651 case IPV6_FLOW: 1652 cmd->data |= get_ethtool_ipv6_rss(bp); 1653 break; 1654 } 1655 return 0; 1656 } 1657 1658 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1659 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1660 1661 static int bnxt_set_rxfh_fields(struct net_device *dev, 1662 const struct ethtool_rxfh_fields *cmd, 1663 struct netlink_ext_ack *extack) 1664 { 1665 struct bnxt *bp = netdev_priv(dev); 1666 int tuple, rc = 0; 1667 u32 rss_hash_cfg; 1668 1669 rss_hash_cfg = bp->rss_hash_cfg; 1670 1671 if (cmd->data == RXH_4TUPLE) 1672 tuple = 4; 1673 else if (cmd->data == RXH_2TUPLE || 1674 cmd->data == (RXH_2TUPLE | RXH_IP6_FL)) 1675 tuple = 2; 1676 else if (!cmd->data) 1677 tuple = 0; 1678 else 1679 return -EINVAL; 1680 1681 if (cmd->data & RXH_IP6_FL && 1682 !(bp->rss_cap & BNXT_RSS_CAP_IPV6_FLOW_LABEL_RSS_CAP)) 1683 return -EINVAL; 1684 1685 if (cmd->flow_type == TCP_V4_FLOW) { 1686 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1687 if (tuple == 4) 1688 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1689 } else if (cmd->flow_type == UDP_V4_FLOW) { 1690 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP)) 1691 return -EINVAL; 1692 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1693 if (tuple == 4) 1694 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1695 } else if (cmd->flow_type == TCP_V6_FLOW) { 1696 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1697 if (tuple == 4) 1698 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1699 } else if (cmd->flow_type == UDP_V6_FLOW) { 1700 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP)) 1701 return -EINVAL; 1702 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1703 if (tuple == 4) 1704 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1705 } else if (cmd->flow_type == AH_ESP_V4_FLOW) { 1706 if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V4_RSS_CAP) || 1707 !(bp->rss_cap & BNXT_RSS_CAP_ESP_V4_RSS_CAP))) 1708 return -EINVAL; 1709 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1710 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4); 1711 if (tuple == 4) 1712 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1713 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4; 1714 } else if (cmd->flow_type == AH_ESP_V6_FLOW) { 1715 if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V6_RSS_CAP) || 1716 !(bp->rss_cap & BNXT_RSS_CAP_ESP_V6_RSS_CAP))) 1717 return -EINVAL; 1718 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1719 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6); 1720 if (tuple == 4) 1721 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1722 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6; 1723 } else if (tuple == 4) { 1724 return -EINVAL; 1725 } 1726 1727 switch (cmd->flow_type) { 1728 case TCP_V4_FLOW: 1729 case UDP_V4_FLOW: 1730 case SCTP_V4_FLOW: 1731 case AH_ESP_V4_FLOW: 1732 case AH_V4_FLOW: 1733 case ESP_V4_FLOW: 1734 case IPV4_FLOW: 1735 if (tuple == 2) 1736 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1737 else if (!tuple) 1738 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1739 break; 1740 1741 case TCP_V6_FLOW: 1742 case UDP_V6_FLOW: 1743 case SCTP_V6_FLOW: 1744 case AH_ESP_V6_FLOW: 1745 case AH_V6_FLOW: 1746 case ESP_V6_FLOW: 1747 case IPV6_FLOW: 1748 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 | 1749 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL); 1750 if (!tuple) 1751 break; 1752 if (cmd->data & RXH_IP6_FL) 1753 rss_hash_cfg |= 1754 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL; 1755 else if (tuple == 2) 1756 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1757 break; 1758 } 1759 1760 if (bp->rss_hash_cfg == rss_hash_cfg) 1761 return 0; 1762 1763 if (bp->rss_cap & BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA) 1764 bp->rss_hash_delta = bp->rss_hash_cfg ^ rss_hash_cfg; 1765 bp->rss_hash_cfg = rss_hash_cfg; 1766 if (netif_running(bp->dev)) { 1767 bnxt_close_nic(bp, false, false); 1768 rc = bnxt_open_nic(bp, false, false); 1769 } 1770 return rc; 1771 } 1772 1773 static u32 bnxt_get_rx_ring_count(struct net_device *dev) 1774 { 1775 struct bnxt *bp = netdev_priv(dev); 1776 1777 return bp->rx_nr_rings; 1778 } 1779 1780 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1781 u32 *rule_locs) 1782 { 1783 struct bnxt *bp = netdev_priv(dev); 1784 int rc = 0; 1785 1786 switch (cmd->cmd) { 1787 case ETHTOOL_GRXCLSRLCNT: 1788 cmd->rule_cnt = bp->ntp_fltr_count; 1789 cmd->data = bp->max_fltr | RX_CLS_LOC_SPECIAL; 1790 break; 1791 1792 case ETHTOOL_GRXCLSRLALL: 1793 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1794 break; 1795 1796 case ETHTOOL_GRXCLSRULE: 1797 rc = bnxt_grxclsrule(bp, cmd); 1798 break; 1799 1800 default: 1801 rc = -EOPNOTSUPP; 1802 break; 1803 } 1804 1805 return rc; 1806 } 1807 1808 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1809 { 1810 struct bnxt *bp = netdev_priv(dev); 1811 int rc; 1812 1813 switch (cmd->cmd) { 1814 case ETHTOOL_SRXCLSRLINS: 1815 rc = bnxt_srxclsrlins(bp, cmd); 1816 break; 1817 1818 case ETHTOOL_SRXCLSRLDEL: 1819 rc = bnxt_srxclsrldel(bp, cmd); 1820 break; 1821 1822 default: 1823 rc = -EOPNOTSUPP; 1824 break; 1825 } 1826 return rc; 1827 } 1828 1829 u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1830 { 1831 struct bnxt *bp = netdev_priv(dev); 1832 1833 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) 1834 return bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) * 1835 BNXT_RSS_TABLE_ENTRIES_P5; 1836 return HW_HASH_INDEX_SIZE; 1837 } 1838 1839 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1840 { 1841 return HW_HASH_KEY_SIZE; 1842 } 1843 1844 static int bnxt_get_rxfh(struct net_device *dev, 1845 struct ethtool_rxfh_param *rxfh) 1846 { 1847 struct bnxt_rss_ctx *rss_ctx = NULL; 1848 struct bnxt *bp = netdev_priv(dev); 1849 u32 *indir_tbl = bp->rss_indir_tbl; 1850 struct bnxt_vnic_info *vnic; 1851 u32 i, tbl_size; 1852 1853 rxfh->hfunc = ETH_RSS_HASH_TOP; 1854 1855 if (!bp->vnic_info) 1856 return 0; 1857 1858 vnic = &bp->vnic_info[BNXT_VNIC_DEFAULT]; 1859 if (rxfh->rss_context) { 1860 struct ethtool_rxfh_context *ctx; 1861 1862 ctx = xa_load(&bp->dev->ethtool->rss_ctx, rxfh->rss_context); 1863 if (!ctx) 1864 return -EINVAL; 1865 indir_tbl = ethtool_rxfh_context_indir(ctx); 1866 rss_ctx = ethtool_rxfh_context_priv(ctx); 1867 vnic = &rss_ctx->vnic; 1868 } 1869 1870 if (rxfh->indir && indir_tbl) { 1871 tbl_size = bnxt_get_rxfh_indir_size(dev); 1872 for (i = 0; i < tbl_size; i++) 1873 rxfh->indir[i] = indir_tbl[i]; 1874 } 1875 1876 if (rxfh->key && vnic->rss_hash_key) 1877 memcpy(rxfh->key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1878 1879 return 0; 1880 } 1881 1882 static void bnxt_modify_rss(struct bnxt *bp, struct ethtool_rxfh_context *ctx, 1883 struct bnxt_rss_ctx *rss_ctx, 1884 const struct ethtool_rxfh_param *rxfh) 1885 { 1886 if (rxfh->key) { 1887 if (rss_ctx) { 1888 memcpy(rss_ctx->vnic.rss_hash_key, rxfh->key, 1889 HW_HASH_KEY_SIZE); 1890 } else { 1891 memcpy(bp->rss_hash_key, rxfh->key, HW_HASH_KEY_SIZE); 1892 bp->rss_hash_key_updated = true; 1893 } 1894 } 1895 if (rxfh->indir) { 1896 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(bp->dev); 1897 u32 *indir_tbl = bp->rss_indir_tbl; 1898 1899 if (rss_ctx) 1900 indir_tbl = ethtool_rxfh_context_indir(ctx); 1901 for (i = 0; i < tbl_size; i++) 1902 indir_tbl[i] = rxfh->indir[i]; 1903 pad = bp->rss_indir_tbl_entries - tbl_size; 1904 if (pad) 1905 memset(&indir_tbl[i], 0, pad * sizeof(*indir_tbl)); 1906 } 1907 } 1908 1909 static int bnxt_rxfh_context_check(struct bnxt *bp, 1910 const struct ethtool_rxfh_param *rxfh, 1911 struct netlink_ext_ack *extack) 1912 { 1913 if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP) { 1914 NL_SET_ERR_MSG_MOD(extack, "RSS hash function not supported"); 1915 return -EOPNOTSUPP; 1916 } 1917 1918 if (!BNXT_SUPPORTS_MULTI_RSS_CTX(bp)) { 1919 NL_SET_ERR_MSG_MOD(extack, "RSS contexts not supported"); 1920 return -EOPNOTSUPP; 1921 } 1922 1923 if (!netif_running(bp->dev)) { 1924 NL_SET_ERR_MSG_MOD(extack, "Unable to set RSS contexts when interface is down"); 1925 return -EAGAIN; 1926 } 1927 1928 return 0; 1929 } 1930 1931 static int bnxt_create_rxfh_context(struct net_device *dev, 1932 struct ethtool_rxfh_context *ctx, 1933 const struct ethtool_rxfh_param *rxfh, 1934 struct netlink_ext_ack *extack) 1935 { 1936 struct bnxt *bp = netdev_priv(dev); 1937 struct bnxt_rss_ctx *rss_ctx; 1938 struct bnxt_vnic_info *vnic; 1939 int rc; 1940 1941 rc = bnxt_rxfh_context_check(bp, rxfh, extack); 1942 if (rc) 1943 return rc; 1944 1945 if (bp->num_rss_ctx >= BNXT_MAX_ETH_RSS_CTX) { 1946 NL_SET_ERR_MSG_FMT_MOD(extack, "Out of RSS contexts, maximum %u", 1947 BNXT_MAX_ETH_RSS_CTX); 1948 return -EINVAL; 1949 } 1950 1951 if (!bnxt_rfs_capable(bp, true)) { 1952 NL_SET_ERR_MSG_MOD(extack, "Out hardware resources"); 1953 return -ENOMEM; 1954 } 1955 1956 rss_ctx = ethtool_rxfh_context_priv(ctx); 1957 1958 bp->num_rss_ctx++; 1959 1960 vnic = &rss_ctx->vnic; 1961 vnic->rss_ctx = ctx; 1962 vnic->flags |= BNXT_VNIC_RSSCTX_FLAG; 1963 vnic->vnic_id = BNXT_VNIC_ID_INVALID; 1964 rc = bnxt_alloc_vnic_rss_table(bp, vnic); 1965 if (rc) 1966 goto out; 1967 1968 /* Populate defaults in the context */ 1969 bnxt_set_dflt_rss_indir_tbl(bp, ctx); 1970 ctx->hfunc = ETH_RSS_HASH_TOP; 1971 memcpy(vnic->rss_hash_key, bp->rss_hash_key, HW_HASH_KEY_SIZE); 1972 memcpy(ethtool_rxfh_context_key(ctx), 1973 bp->rss_hash_key, HW_HASH_KEY_SIZE); 1974 1975 rc = bnxt_hwrm_vnic_alloc(bp, vnic, 0, bp->rx_nr_rings); 1976 if (rc) { 1977 NL_SET_ERR_MSG_MOD(extack, "Unable to allocate VNIC"); 1978 goto out; 1979 } 1980 1981 rc = bnxt_hwrm_vnic_set_tpa(bp, vnic, bp->flags & BNXT_FLAG_TPA); 1982 if (rc) { 1983 NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA"); 1984 goto out; 1985 } 1986 bnxt_modify_rss(bp, ctx, rss_ctx, rxfh); 1987 1988 rc = __bnxt_setup_vnic_p5(bp, vnic); 1989 if (rc) { 1990 NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA"); 1991 goto out; 1992 } 1993 1994 rss_ctx->index = rxfh->rss_context; 1995 return 0; 1996 out: 1997 bnxt_del_one_rss_ctx(bp, rss_ctx, true); 1998 return rc; 1999 } 2000 2001 static int bnxt_modify_rxfh_context(struct net_device *dev, 2002 struct ethtool_rxfh_context *ctx, 2003 const struct ethtool_rxfh_param *rxfh, 2004 struct netlink_ext_ack *extack) 2005 { 2006 struct bnxt *bp = netdev_priv(dev); 2007 struct bnxt_rss_ctx *rss_ctx; 2008 int rc; 2009 2010 rc = bnxt_rxfh_context_check(bp, rxfh, extack); 2011 if (rc) 2012 return rc; 2013 2014 rss_ctx = ethtool_rxfh_context_priv(ctx); 2015 2016 bnxt_modify_rss(bp, ctx, rss_ctx, rxfh); 2017 2018 return bnxt_hwrm_vnic_rss_cfg_p5(bp, &rss_ctx->vnic); 2019 } 2020 2021 static int bnxt_remove_rxfh_context(struct net_device *dev, 2022 struct ethtool_rxfh_context *ctx, 2023 u32 rss_context, 2024 struct netlink_ext_ack *extack) 2025 { 2026 struct bnxt *bp = netdev_priv(dev); 2027 struct bnxt_rss_ctx *rss_ctx; 2028 2029 rss_ctx = ethtool_rxfh_context_priv(ctx); 2030 2031 bnxt_del_one_rss_ctx(bp, rss_ctx, true); 2032 return 0; 2033 } 2034 2035 static int bnxt_set_rxfh(struct net_device *dev, 2036 struct ethtool_rxfh_param *rxfh, 2037 struct netlink_ext_ack *extack) 2038 { 2039 struct bnxt *bp = netdev_priv(dev); 2040 int rc = 0; 2041 2042 if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP) 2043 return -EOPNOTSUPP; 2044 2045 bnxt_modify_rss(bp, NULL, NULL, rxfh); 2046 2047 if (netif_running(bp->dev)) { 2048 bnxt_close_nic(bp, false, false); 2049 rc = bnxt_open_nic(bp, false, false); 2050 } 2051 return rc; 2052 } 2053 2054 static void bnxt_get_drvinfo(struct net_device *dev, 2055 struct ethtool_drvinfo *info) 2056 { 2057 struct bnxt *bp = netdev_priv(dev); 2058 2059 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 2060 strscpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 2061 strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 2062 info->n_stats = bnxt_get_num_stats(bp); 2063 info->testinfo_len = bp->num_tests; 2064 /* TODO CHIMP_FW: eeprom dump details */ 2065 info->eedump_len = 0; 2066 /* TODO CHIMP FW: reg dump details */ 2067 info->regdump_len = 0; 2068 } 2069 2070 static int bnxt_get_regs_len(struct net_device *dev) 2071 { 2072 struct bnxt *bp = netdev_priv(dev); 2073 2074 if (!BNXT_PF(bp)) 2075 return -EOPNOTSUPP; 2076 2077 return BNXT_PXP_REG_LEN + bp->pcie_stat_len; 2078 } 2079 2080 static void * 2081 __bnxt_hwrm_pcie_qstats(struct bnxt *bp, struct hwrm_pcie_qstats_input *req) 2082 { 2083 struct pcie_ctx_hw_stats_v2 *hw_pcie_stats; 2084 dma_addr_t hw_pcie_stats_addr; 2085 int rc; 2086 2087 hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats), 2088 &hw_pcie_stats_addr); 2089 if (!hw_pcie_stats) 2090 return NULL; 2091 2092 req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats)); 2093 req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr); 2094 rc = hwrm_req_send(bp, req); 2095 2096 return rc ? NULL : hw_pcie_stats; 2097 } 2098 2099 #define BNXT_PCIE_32B_ENTRY(start, end) \ 2100 { offsetof(struct pcie_ctx_hw_stats_v2, start),\ 2101 offsetof(struct pcie_ctx_hw_stats_v2, end) } 2102 2103 static const struct { 2104 u16 start; 2105 u16 end; 2106 } bnxt_pcie_32b_entries[] = { 2107 BNXT_PCIE_32B_ENTRY(pcie_ltssm_histogram[0], pcie_ltssm_histogram[3]), 2108 BNXT_PCIE_32B_ENTRY(pcie_tl_credit_nph_histogram[0], unused_1), 2109 BNXT_PCIE_32B_ENTRY(pcie_rd_latency_histogram[0], unused_2), 2110 }; 2111 2112 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs, 2113 void *_p) 2114 { 2115 struct hwrm_pcie_qstats_output *resp; 2116 struct hwrm_pcie_qstats_input *req; 2117 struct bnxt *bp = netdev_priv(dev); 2118 u8 *src; 2119 2120 regs->version = 0; 2121 if (!(bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_REG_ACCESS_RESTRICTED)) 2122 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p); 2123 2124 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 2125 return; 2126 2127 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS)) 2128 return; 2129 2130 resp = hwrm_req_hold(bp, req); 2131 src = __bnxt_hwrm_pcie_qstats(bp, req); 2132 if (src) { 2133 u8 *dst = (u8 *)(_p + BNXT_PXP_REG_LEN); 2134 int i, j, len; 2135 2136 len = min(bp->pcie_stat_len, le16_to_cpu(resp->pcie_stat_size)); 2137 if (len <= sizeof(struct pcie_ctx_hw_stats)) 2138 regs->version = 1; 2139 else if (len < sizeof(struct pcie_ctx_hw_stats_v2)) 2140 regs->version = 2; 2141 else 2142 regs->version = 3; 2143 2144 for (i = 0, j = 0; i < len; ) { 2145 if (i >= bnxt_pcie_32b_entries[j].start && 2146 i <= bnxt_pcie_32b_entries[j].end) { 2147 u32 *dst32 = (u32 *)(dst + i); 2148 2149 *dst32 = le32_to_cpu(*(__le32 *)(src + i)); 2150 i += 4; 2151 if (i > bnxt_pcie_32b_entries[j].end && 2152 j < ARRAY_SIZE(bnxt_pcie_32b_entries) - 1) 2153 j++; 2154 } else { 2155 u64 *dst64 = (u64 *)(dst + i); 2156 2157 *dst64 = le64_to_cpu(*(__le64 *)(src + i)); 2158 i += 8; 2159 } 2160 } 2161 } 2162 hwrm_req_drop(bp, req); 2163 } 2164 2165 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2166 { 2167 struct bnxt *bp = netdev_priv(dev); 2168 2169 wol->supported = 0; 2170 wol->wolopts = 0; 2171 memset(&wol->sopass, 0, sizeof(wol->sopass)); 2172 if (bp->flags & BNXT_FLAG_WOL_CAP) { 2173 wol->supported = WAKE_MAGIC; 2174 if (bp->wol) 2175 wol->wolopts = WAKE_MAGIC; 2176 } 2177 } 2178 2179 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2180 { 2181 struct bnxt *bp = netdev_priv(dev); 2182 2183 if (wol->wolopts & ~WAKE_MAGIC) 2184 return -EINVAL; 2185 2186 if (wol->wolopts & WAKE_MAGIC) { 2187 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 2188 return -EINVAL; 2189 if (!bp->wol) { 2190 if (bnxt_hwrm_alloc_wol_fltr(bp)) 2191 return -EBUSY; 2192 bp->wol = 1; 2193 } 2194 } else { 2195 if (bp->wol) { 2196 if (bnxt_hwrm_free_wol_fltr(bp)) 2197 return -EBUSY; 2198 bp->wol = 0; 2199 } 2200 } 2201 return 0; 2202 } 2203 2204 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 2205 void _bnxt_fw_to_linkmode(unsigned long *mode, u16 fw_speeds) 2206 { 2207 linkmode_zero(mode); 2208 2209 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 2210 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode); 2211 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 2212 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode); 2213 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 2214 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT, mode); 2215 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 2216 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode); 2217 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 2218 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode); 2219 } 2220 2221 enum bnxt_media_type { 2222 BNXT_MEDIA_UNKNOWN = 0, 2223 BNXT_MEDIA_TP, 2224 BNXT_MEDIA_CR, 2225 BNXT_MEDIA_SR, 2226 BNXT_MEDIA_LR_ER_FR, 2227 BNXT_MEDIA_KR, 2228 BNXT_MEDIA_KX, 2229 BNXT_MEDIA_X, 2230 __BNXT_MEDIA_END, 2231 }; 2232 2233 static const enum bnxt_media_type bnxt_phy_types[] = { 2234 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR] = BNXT_MEDIA_CR, 2235 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4] = BNXT_MEDIA_KR, 2236 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR] = BNXT_MEDIA_LR_ER_FR, 2237 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR] = BNXT_MEDIA_SR, 2238 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2] = BNXT_MEDIA_KR, 2239 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX] = BNXT_MEDIA_KX, 2240 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR] = BNXT_MEDIA_KR, 2241 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASET] = BNXT_MEDIA_TP, 2242 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE] = BNXT_MEDIA_TP, 2243 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L] = BNXT_MEDIA_CR, 2244 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S] = BNXT_MEDIA_CR, 2245 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N] = BNXT_MEDIA_CR, 2246 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR] = BNXT_MEDIA_SR, 2247 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4] = BNXT_MEDIA_CR, 2248 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4] = BNXT_MEDIA_SR, 2249 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2250 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2251 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10] = BNXT_MEDIA_SR, 2252 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4] = BNXT_MEDIA_CR, 2253 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4] = BNXT_MEDIA_SR, 2254 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2255 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2256 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE] = BNXT_MEDIA_SR, 2257 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET] = BNXT_MEDIA_TP, 2258 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX] = BNXT_MEDIA_X, 2259 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX] = BNXT_MEDIA_X, 2260 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4] = BNXT_MEDIA_CR, 2261 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4] = BNXT_MEDIA_SR, 2262 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2263 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2264 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR] = BNXT_MEDIA_CR, 2265 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR] = BNXT_MEDIA_SR, 2266 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR] = BNXT_MEDIA_LR_ER_FR, 2267 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER] = BNXT_MEDIA_LR_ER_FR, 2268 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2] = BNXT_MEDIA_CR, 2269 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2] = BNXT_MEDIA_SR, 2270 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2] = BNXT_MEDIA_LR_ER_FR, 2271 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2] = BNXT_MEDIA_LR_ER_FR, 2272 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR] = BNXT_MEDIA_CR, 2273 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR] = BNXT_MEDIA_SR, 2274 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR] = BNXT_MEDIA_LR_ER_FR, 2275 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER] = BNXT_MEDIA_LR_ER_FR, 2276 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2] = BNXT_MEDIA_CR, 2277 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2] = BNXT_MEDIA_SR, 2278 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2] = BNXT_MEDIA_LR_ER_FR, 2279 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2] = BNXT_MEDIA_LR_ER_FR, 2280 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8] = BNXT_MEDIA_CR, 2281 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8] = BNXT_MEDIA_SR, 2282 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8] = BNXT_MEDIA_LR_ER_FR, 2283 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8] = BNXT_MEDIA_LR_ER_FR, 2284 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4] = BNXT_MEDIA_CR, 2285 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4] = BNXT_MEDIA_SR, 2286 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2287 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2288 }; 2289 2290 static enum bnxt_media_type 2291 bnxt_get_media(struct bnxt_link_info *link_info) 2292 { 2293 switch (link_info->media_type) { 2294 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP: 2295 return BNXT_MEDIA_TP; 2296 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC: 2297 return BNXT_MEDIA_CR; 2298 default: 2299 if (link_info->phy_type < ARRAY_SIZE(bnxt_phy_types)) 2300 return bnxt_phy_types[link_info->phy_type]; 2301 return BNXT_MEDIA_UNKNOWN; 2302 } 2303 } 2304 2305 enum bnxt_link_speed_indices { 2306 BNXT_LINK_SPEED_UNKNOWN = 0, 2307 BNXT_LINK_SPEED_100MB_IDX, 2308 BNXT_LINK_SPEED_1GB_IDX, 2309 BNXT_LINK_SPEED_10GB_IDX, 2310 BNXT_LINK_SPEED_25GB_IDX, 2311 BNXT_LINK_SPEED_40GB_IDX, 2312 BNXT_LINK_SPEED_50GB_IDX, 2313 BNXT_LINK_SPEED_100GB_IDX, 2314 BNXT_LINK_SPEED_200GB_IDX, 2315 BNXT_LINK_SPEED_400GB_IDX, 2316 __BNXT_LINK_SPEED_END 2317 }; 2318 2319 static enum bnxt_link_speed_indices bnxt_fw_speed_idx(u16 speed) 2320 { 2321 switch (speed) { 2322 case BNXT_LINK_SPEED_100MB: return BNXT_LINK_SPEED_100MB_IDX; 2323 case BNXT_LINK_SPEED_1GB: return BNXT_LINK_SPEED_1GB_IDX; 2324 case BNXT_LINK_SPEED_10GB: return BNXT_LINK_SPEED_10GB_IDX; 2325 case BNXT_LINK_SPEED_25GB: return BNXT_LINK_SPEED_25GB_IDX; 2326 case BNXT_LINK_SPEED_40GB: return BNXT_LINK_SPEED_40GB_IDX; 2327 case BNXT_LINK_SPEED_50GB: 2328 case BNXT_LINK_SPEED_50GB_PAM4: 2329 return BNXT_LINK_SPEED_50GB_IDX; 2330 case BNXT_LINK_SPEED_100GB: 2331 case BNXT_LINK_SPEED_100GB_PAM4: 2332 case BNXT_LINK_SPEED_100GB_PAM4_112: 2333 return BNXT_LINK_SPEED_100GB_IDX; 2334 case BNXT_LINK_SPEED_200GB: 2335 case BNXT_LINK_SPEED_200GB_PAM4: 2336 case BNXT_LINK_SPEED_200GB_PAM4_112: 2337 return BNXT_LINK_SPEED_200GB_IDX; 2338 case BNXT_LINK_SPEED_400GB: 2339 case BNXT_LINK_SPEED_400GB_PAM4: 2340 case BNXT_LINK_SPEED_400GB_PAM4_112: 2341 return BNXT_LINK_SPEED_400GB_IDX; 2342 default: return BNXT_LINK_SPEED_UNKNOWN; 2343 } 2344 } 2345 2346 static const enum ethtool_link_mode_bit_indices 2347 bnxt_link_modes[__BNXT_LINK_SPEED_END][BNXT_SIG_MODE_MAX][__BNXT_MEDIA_END] = { 2348 [BNXT_LINK_SPEED_100MB_IDX] = { 2349 { 2350 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_100baseT_Full_BIT, 2351 }, 2352 }, 2353 [BNXT_LINK_SPEED_1GB_IDX] = { 2354 { 2355 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 2356 /* historically baseT, but DAC is more correctly baseX */ 2357 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 2358 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2359 [BNXT_MEDIA_X] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 2360 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2361 }, 2362 }, 2363 [BNXT_LINK_SPEED_10GB_IDX] = { 2364 { 2365 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 2366 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 2367 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 2368 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 2369 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 2370 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 2371 }, 2372 }, 2373 [BNXT_LINK_SPEED_25GB_IDX] = { 2374 { 2375 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 2376 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 2377 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 2378 }, 2379 }, 2380 [BNXT_LINK_SPEED_40GB_IDX] = { 2381 { 2382 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 2383 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 2384 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 2385 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 2386 }, 2387 }, 2388 [BNXT_LINK_SPEED_50GB_IDX] = { 2389 [BNXT_SIG_MODE_NRZ] = { 2390 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 2391 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 2392 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 2393 }, 2394 [BNXT_SIG_MODE_PAM4] = { 2395 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 2396 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 2397 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 2398 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 2399 }, 2400 }, 2401 [BNXT_LINK_SPEED_100GB_IDX] = { 2402 [BNXT_SIG_MODE_NRZ] = { 2403 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 2404 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 2405 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 2406 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 2407 }, 2408 [BNXT_SIG_MODE_PAM4] = { 2409 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 2410 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 2411 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 2412 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 2413 }, 2414 [BNXT_SIG_MODE_PAM4_112] = { 2415 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR_Full_BIT, 2416 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR_Full_BIT, 2417 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR_Full_BIT, 2418 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT, 2419 }, 2420 }, 2421 [BNXT_LINK_SPEED_200GB_IDX] = { 2422 [BNXT_SIG_MODE_PAM4] = { 2423 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT, 2424 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 2425 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 2426 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 2427 }, 2428 [BNXT_SIG_MODE_PAM4_112] = { 2429 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT, 2430 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT, 2431 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT, 2432 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT, 2433 }, 2434 }, 2435 [BNXT_LINK_SPEED_400GB_IDX] = { 2436 [BNXT_SIG_MODE_PAM4] = { 2437 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT, 2438 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT, 2439 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT, 2440 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT, 2441 }, 2442 [BNXT_SIG_MODE_PAM4_112] = { 2443 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT, 2444 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT, 2445 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT, 2446 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT, 2447 }, 2448 }, 2449 }; 2450 2451 #define BNXT_LINK_MODE_UNKNOWN -1 2452 2453 static enum ethtool_link_mode_bit_indices 2454 bnxt_get_link_mode(struct bnxt_link_info *link_info) 2455 { 2456 enum ethtool_link_mode_bit_indices link_mode; 2457 enum bnxt_link_speed_indices speed; 2458 enum bnxt_media_type media; 2459 u8 sig_mode; 2460 2461 if (link_info->phy_link_status != BNXT_LINK_LINK) 2462 return BNXT_LINK_MODE_UNKNOWN; 2463 2464 media = bnxt_get_media(link_info); 2465 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 2466 speed = bnxt_fw_speed_idx(link_info->link_speed); 2467 sig_mode = link_info->active_fec_sig_mode & 2468 PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK; 2469 } else { 2470 speed = bnxt_fw_speed_idx(link_info->req_link_speed); 2471 sig_mode = link_info->req_signal_mode; 2472 } 2473 if (sig_mode >= BNXT_SIG_MODE_MAX) 2474 return BNXT_LINK_MODE_UNKNOWN; 2475 2476 /* Note ETHTOOL_LINK_MODE_10baseT_Half_BIT == 0 is a legal Linux 2477 * link mode, but since no such devices exist, the zeroes in the 2478 * map can be conveniently used to represent unknown link modes. 2479 */ 2480 link_mode = bnxt_link_modes[speed][sig_mode][media]; 2481 if (!link_mode) 2482 return BNXT_LINK_MODE_UNKNOWN; 2483 2484 switch (link_mode) { 2485 case ETHTOOL_LINK_MODE_100baseT_Full_BIT: 2486 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2487 link_mode = ETHTOOL_LINK_MODE_100baseT_Half_BIT; 2488 break; 2489 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT: 2490 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2491 link_mode = ETHTOOL_LINK_MODE_1000baseT_Half_BIT; 2492 break; 2493 default: 2494 break; 2495 } 2496 2497 return link_mode; 2498 } 2499 2500 static void bnxt_get_ethtool_modes(struct bnxt_link_info *link_info, 2501 struct ethtool_link_ksettings *lk_ksettings) 2502 { 2503 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2504 2505 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) { 2506 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2507 lk_ksettings->link_modes.supported); 2508 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2509 lk_ksettings->link_modes.supported); 2510 } 2511 2512 if (link_info->support_auto_speeds || link_info->support_auto_speeds2 || 2513 link_info->support_pam4_auto_speeds) 2514 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2515 lk_ksettings->link_modes.supported); 2516 2517 if (~link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 2518 return; 2519 2520 if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_RX) 2521 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2522 lk_ksettings->link_modes.advertising); 2523 if (hweight8(link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) == 1) 2524 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2525 lk_ksettings->link_modes.advertising); 2526 if (link_info->lp_pause & BNXT_LINK_PAUSE_RX) 2527 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2528 lk_ksettings->link_modes.lp_advertising); 2529 if (hweight8(link_info->lp_pause & BNXT_LINK_PAUSE_BOTH) == 1) 2530 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2531 lk_ksettings->link_modes.lp_advertising); 2532 } 2533 2534 static const u16 bnxt_nrz_speed_masks[] = { 2535 [BNXT_LINK_SPEED_100MB_IDX] = BNXT_LINK_SPEED_MSK_100MB, 2536 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEED_MSK_1GB, 2537 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEED_MSK_10GB, 2538 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEED_MSK_25GB, 2539 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEED_MSK_40GB, 2540 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEED_MSK_50GB, 2541 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEED_MSK_100GB, 2542 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2543 }; 2544 2545 static const u16 bnxt_pam4_speed_masks[] = { 2546 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_50GB, 2547 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_100GB, 2548 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_200GB, 2549 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2550 }; 2551 2552 static const u16 bnxt_nrz_speeds2_masks[] = { 2553 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEEDS2_MSK_1GB, 2554 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEEDS2_MSK_10GB, 2555 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEEDS2_MSK_25GB, 2556 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEEDS2_MSK_40GB, 2557 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB, 2558 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB, 2559 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2560 }; 2561 2562 static const u16 bnxt_pam4_speeds2_masks[] = { 2563 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB_PAM4, 2564 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4, 2565 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4, 2566 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4, 2567 }; 2568 2569 static const u16 bnxt_pam4_112_speeds2_masks[] = { 2570 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112, 2571 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112, 2572 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112, 2573 }; 2574 2575 static enum bnxt_link_speed_indices 2576 bnxt_encoding_speed_idx(u8 sig_mode, u16 phy_flags, u16 speed_msk) 2577 { 2578 const u16 *speeds; 2579 int idx, len; 2580 2581 switch (sig_mode) { 2582 case BNXT_SIG_MODE_NRZ: 2583 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2584 speeds = bnxt_nrz_speeds2_masks; 2585 len = ARRAY_SIZE(bnxt_nrz_speeds2_masks); 2586 } else { 2587 speeds = bnxt_nrz_speed_masks; 2588 len = ARRAY_SIZE(bnxt_nrz_speed_masks); 2589 } 2590 break; 2591 case BNXT_SIG_MODE_PAM4: 2592 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2593 speeds = bnxt_pam4_speeds2_masks; 2594 len = ARRAY_SIZE(bnxt_pam4_speeds2_masks); 2595 } else { 2596 speeds = bnxt_pam4_speed_masks; 2597 len = ARRAY_SIZE(bnxt_pam4_speed_masks); 2598 } 2599 break; 2600 case BNXT_SIG_MODE_PAM4_112: 2601 speeds = bnxt_pam4_112_speeds2_masks; 2602 len = ARRAY_SIZE(bnxt_pam4_112_speeds2_masks); 2603 break; 2604 default: 2605 return BNXT_LINK_SPEED_UNKNOWN; 2606 } 2607 2608 for (idx = 0; idx < len; idx++) { 2609 if (speeds[idx] == speed_msk) 2610 return idx; 2611 } 2612 2613 return BNXT_LINK_SPEED_UNKNOWN; 2614 } 2615 2616 #define BNXT_FW_SPEED_MSK_BITS 16 2617 2618 static void 2619 __bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media, 2620 u8 sig_mode, u16 phy_flags, unsigned long *et_mask) 2621 { 2622 enum ethtool_link_mode_bit_indices link_mode; 2623 enum bnxt_link_speed_indices speed; 2624 u8 bit; 2625 2626 for_each_set_bit(bit, &fw_mask, BNXT_FW_SPEED_MSK_BITS) { 2627 speed = bnxt_encoding_speed_idx(sig_mode, phy_flags, 1 << bit); 2628 if (!speed) 2629 continue; 2630 2631 link_mode = bnxt_link_modes[speed][sig_mode][media]; 2632 if (!link_mode) 2633 continue; 2634 2635 linkmode_set_bit(link_mode, et_mask); 2636 } 2637 } 2638 2639 static void 2640 bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media, 2641 u8 sig_mode, u16 phy_flags, unsigned long *et_mask) 2642 { 2643 if (media) { 2644 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags, 2645 et_mask); 2646 return; 2647 } 2648 2649 /* list speeds for all media if unknown */ 2650 for (media = 1; media < __BNXT_MEDIA_END; media++) 2651 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags, 2652 et_mask); 2653 } 2654 2655 static void 2656 bnxt_get_all_ethtool_support_speeds(struct bnxt_link_info *link_info, 2657 enum bnxt_media_type media, 2658 struct ethtool_link_ksettings *lk_ksettings) 2659 { 2660 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2661 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0; 2662 u16 phy_flags = bp->phy_flags; 2663 2664 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2665 sp_nrz = link_info->support_speeds2; 2666 sp_pam4 = link_info->support_speeds2; 2667 sp_pam4_112 = link_info->support_speeds2; 2668 } else { 2669 sp_nrz = link_info->support_speeds; 2670 sp_pam4 = link_info->support_pam4_speeds; 2671 } 2672 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags, 2673 lk_ksettings->link_modes.supported); 2674 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags, 2675 lk_ksettings->link_modes.supported); 2676 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112, 2677 phy_flags, lk_ksettings->link_modes.supported); 2678 } 2679 2680 static void 2681 bnxt_get_all_ethtool_adv_speeds(struct bnxt_link_info *link_info, 2682 enum bnxt_media_type media, 2683 struct ethtool_link_ksettings *lk_ksettings) 2684 { 2685 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2686 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0; 2687 u16 phy_flags = bp->phy_flags; 2688 2689 sp_nrz = link_info->advertising; 2690 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2691 sp_pam4 = link_info->advertising; 2692 sp_pam4_112 = link_info->advertising; 2693 } else { 2694 sp_pam4 = link_info->advertising_pam4; 2695 } 2696 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags, 2697 lk_ksettings->link_modes.advertising); 2698 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags, 2699 lk_ksettings->link_modes.advertising); 2700 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112, 2701 phy_flags, lk_ksettings->link_modes.advertising); 2702 } 2703 2704 static void 2705 bnxt_get_all_ethtool_lp_speeds(struct bnxt_link_info *link_info, 2706 enum bnxt_media_type media, 2707 struct ethtool_link_ksettings *lk_ksettings) 2708 { 2709 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2710 u16 phy_flags = bp->phy_flags; 2711 2712 bnxt_get_ethtool_speeds(link_info->lp_auto_link_speeds, media, 2713 BNXT_SIG_MODE_NRZ, phy_flags, 2714 lk_ksettings->link_modes.lp_advertising); 2715 bnxt_get_ethtool_speeds(link_info->lp_auto_pam4_link_speeds, media, 2716 BNXT_SIG_MODE_PAM4, phy_flags, 2717 lk_ksettings->link_modes.lp_advertising); 2718 } 2719 2720 static void bnxt_update_speed(u32 *delta, bool installed_media, u16 *speeds, 2721 u16 speed_msk, const unsigned long *et_mask, 2722 enum ethtool_link_mode_bit_indices mode) 2723 { 2724 bool mode_desired = linkmode_test_bit(mode, et_mask); 2725 2726 if (!mode) 2727 return; 2728 2729 /* enabled speeds for installed media should override */ 2730 if (installed_media && mode_desired) { 2731 *speeds |= speed_msk; 2732 *delta |= speed_msk; 2733 return; 2734 } 2735 2736 /* many to one mapping, only allow one change per fw_speed bit */ 2737 if (!(*delta & speed_msk) && (mode_desired == !(*speeds & speed_msk))) { 2738 *speeds ^= speed_msk; 2739 *delta |= speed_msk; 2740 } 2741 } 2742 2743 static void bnxt_set_ethtool_speeds(struct bnxt_link_info *link_info, 2744 const unsigned long *et_mask) 2745 { 2746 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2747 u16 const *sp_msks, *sp_pam4_msks, *sp_pam4_112_msks; 2748 enum bnxt_media_type media = bnxt_get_media(link_info); 2749 u16 *adv, *adv_pam4, *adv_pam4_112 = NULL; 2750 u32 delta_pam4_112 = 0; 2751 u32 delta_pam4 = 0; 2752 u32 delta_nrz = 0; 2753 int i, m; 2754 2755 adv = &link_info->advertising; 2756 if (bp->phy_flags & BNXT_PHY_FL_SPEEDS2) { 2757 adv_pam4 = &link_info->advertising; 2758 adv_pam4_112 = &link_info->advertising; 2759 sp_msks = bnxt_nrz_speeds2_masks; 2760 sp_pam4_msks = bnxt_pam4_speeds2_masks; 2761 sp_pam4_112_msks = bnxt_pam4_112_speeds2_masks; 2762 } else { 2763 adv_pam4 = &link_info->advertising_pam4; 2764 sp_msks = bnxt_nrz_speed_masks; 2765 sp_pam4_msks = bnxt_pam4_speed_masks; 2766 } 2767 for (i = 1; i < __BNXT_LINK_SPEED_END; i++) { 2768 /* accept any legal media from user */ 2769 for (m = 1; m < __BNXT_MEDIA_END; m++) { 2770 bnxt_update_speed(&delta_nrz, m == media, 2771 adv, sp_msks[i], et_mask, 2772 bnxt_link_modes[i][BNXT_SIG_MODE_NRZ][m]); 2773 bnxt_update_speed(&delta_pam4, m == media, 2774 adv_pam4, sp_pam4_msks[i], et_mask, 2775 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4][m]); 2776 if (!adv_pam4_112) 2777 continue; 2778 2779 bnxt_update_speed(&delta_pam4_112, m == media, 2780 adv_pam4_112, sp_pam4_112_msks[i], et_mask, 2781 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4_112][m]); 2782 } 2783 } 2784 } 2785 2786 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info, 2787 struct ethtool_link_ksettings *lk_ksettings) 2788 { 2789 u16 fec_cfg = link_info->fec_cfg; 2790 2791 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) { 2792 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 2793 lk_ksettings->link_modes.advertising); 2794 return; 2795 } 2796 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 2797 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 2798 lk_ksettings->link_modes.advertising); 2799 if (fec_cfg & BNXT_FEC_ENC_RS) 2800 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 2801 lk_ksettings->link_modes.advertising); 2802 if (fec_cfg & BNXT_FEC_ENC_LLRS) 2803 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 2804 lk_ksettings->link_modes.advertising); 2805 } 2806 2807 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info, 2808 struct ethtool_link_ksettings *lk_ksettings) 2809 { 2810 u16 fec_cfg = link_info->fec_cfg; 2811 2812 if (fec_cfg & BNXT_FEC_NONE) { 2813 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 2814 lk_ksettings->link_modes.supported); 2815 return; 2816 } 2817 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP) 2818 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 2819 lk_ksettings->link_modes.supported); 2820 if (fec_cfg & BNXT_FEC_ENC_RS_CAP) 2821 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 2822 lk_ksettings->link_modes.supported); 2823 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP) 2824 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 2825 lk_ksettings->link_modes.supported); 2826 } 2827 2828 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 2829 { 2830 switch (fw_link_speed) { 2831 case BNXT_LINK_SPEED_100MB: 2832 return SPEED_100; 2833 case BNXT_LINK_SPEED_1GB: 2834 return SPEED_1000; 2835 case BNXT_LINK_SPEED_2_5GB: 2836 return SPEED_2500; 2837 case BNXT_LINK_SPEED_10GB: 2838 return SPEED_10000; 2839 case BNXT_LINK_SPEED_20GB: 2840 return SPEED_20000; 2841 case BNXT_LINK_SPEED_25GB: 2842 return SPEED_25000; 2843 case BNXT_LINK_SPEED_40GB: 2844 return SPEED_40000; 2845 case BNXT_LINK_SPEED_50GB: 2846 case BNXT_LINK_SPEED_50GB_PAM4: 2847 return SPEED_50000; 2848 case BNXT_LINK_SPEED_100GB: 2849 case BNXT_LINK_SPEED_100GB_PAM4: 2850 case BNXT_LINK_SPEED_100GB_PAM4_112: 2851 return SPEED_100000; 2852 case BNXT_LINK_SPEED_200GB: 2853 case BNXT_LINK_SPEED_200GB_PAM4: 2854 case BNXT_LINK_SPEED_200GB_PAM4_112: 2855 return SPEED_200000; 2856 case BNXT_LINK_SPEED_400GB: 2857 case BNXT_LINK_SPEED_400GB_PAM4: 2858 case BNXT_LINK_SPEED_400GB_PAM4_112: 2859 return SPEED_400000; 2860 default: 2861 return SPEED_UNKNOWN; 2862 } 2863 } 2864 2865 static void bnxt_get_default_speeds(struct ethtool_link_ksettings *lk_ksettings, 2866 struct bnxt_link_info *link_info) 2867 { 2868 struct ethtool_link_settings *base = &lk_ksettings->base; 2869 2870 if (link_info->link_state == BNXT_LINK_STATE_UP) { 2871 base->speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 2872 base->duplex = DUPLEX_HALF; 2873 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2874 base->duplex = DUPLEX_FULL; 2875 lk_ksettings->lanes = link_info->active_lanes; 2876 } else if (!link_info->autoneg) { 2877 base->speed = bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 2878 base->duplex = DUPLEX_HALF; 2879 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 2880 base->duplex = DUPLEX_FULL; 2881 } 2882 } 2883 2884 static int bnxt_get_link_ksettings(struct net_device *dev, 2885 struct ethtool_link_ksettings *lk_ksettings) 2886 { 2887 struct ethtool_link_settings *base = &lk_ksettings->base; 2888 enum ethtool_link_mode_bit_indices link_mode; 2889 struct bnxt *bp = netdev_priv(dev); 2890 struct bnxt_link_info *link_info; 2891 enum bnxt_media_type media; 2892 2893 ethtool_link_ksettings_zero_link_mode(lk_ksettings, lp_advertising); 2894 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 2895 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 2896 base->duplex = DUPLEX_UNKNOWN; 2897 base->speed = SPEED_UNKNOWN; 2898 link_info = &bp->link_info; 2899 2900 mutex_lock(&bp->link_lock); 2901 bnxt_get_ethtool_modes(link_info, lk_ksettings); 2902 media = bnxt_get_media(link_info); 2903 bnxt_get_all_ethtool_support_speeds(link_info, media, lk_ksettings); 2904 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings); 2905 link_mode = bnxt_get_link_mode(link_info); 2906 if (link_mode != BNXT_LINK_MODE_UNKNOWN) 2907 ethtool_params_from_link_mode(lk_ksettings, link_mode); 2908 else 2909 bnxt_get_default_speeds(lk_ksettings, link_info); 2910 2911 if (link_info->autoneg) { 2912 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings); 2913 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2914 lk_ksettings->link_modes.advertising); 2915 base->autoneg = AUTONEG_ENABLE; 2916 bnxt_get_all_ethtool_adv_speeds(link_info, media, lk_ksettings); 2917 if (link_info->phy_link_status == BNXT_LINK_LINK) 2918 bnxt_get_all_ethtool_lp_speeds(link_info, media, 2919 lk_ksettings); 2920 } else { 2921 base->autoneg = AUTONEG_DISABLE; 2922 } 2923 2924 base->port = PORT_NONE; 2925 if (media == BNXT_MEDIA_TP) { 2926 base->port = PORT_TP; 2927 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2928 lk_ksettings->link_modes.supported); 2929 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2930 lk_ksettings->link_modes.advertising); 2931 } else if (media == BNXT_MEDIA_KR) { 2932 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, 2933 lk_ksettings->link_modes.supported); 2934 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, 2935 lk_ksettings->link_modes.advertising); 2936 } else { 2937 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 2938 lk_ksettings->link_modes.supported); 2939 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 2940 lk_ksettings->link_modes.advertising); 2941 2942 if (media == BNXT_MEDIA_CR) 2943 base->port = PORT_DA; 2944 else 2945 base->port = PORT_FIBRE; 2946 } 2947 base->phy_address = link_info->phy_addr; 2948 mutex_unlock(&bp->link_lock); 2949 2950 return 0; 2951 } 2952 2953 static int 2954 bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed, u32 lanes) 2955 { 2956 struct bnxt *bp = netdev_priv(dev); 2957 struct bnxt_link_info *link_info = &bp->link_info; 2958 u16 support_pam4_spds = link_info->support_pam4_speeds; 2959 u16 support_spds2 = link_info->support_speeds2; 2960 u16 support_spds = link_info->support_speeds; 2961 u8 sig_mode = BNXT_SIG_MODE_NRZ; 2962 u32 lanes_needed = 1; 2963 u16 fw_speed = 0; 2964 2965 switch (ethtool_speed) { 2966 case SPEED_100: 2967 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 2968 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB; 2969 break; 2970 case SPEED_1000: 2971 if ((support_spds & BNXT_LINK_SPEED_MSK_1GB) || 2972 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_1GB)) 2973 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 2974 break; 2975 case SPEED_2500: 2976 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 2977 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB; 2978 break; 2979 case SPEED_10000: 2980 if ((support_spds & BNXT_LINK_SPEED_MSK_10GB) || 2981 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_10GB)) 2982 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 2983 break; 2984 case SPEED_20000: 2985 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) { 2986 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB; 2987 lanes_needed = 2; 2988 } 2989 break; 2990 case SPEED_25000: 2991 if ((support_spds & BNXT_LINK_SPEED_MSK_25GB) || 2992 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_25GB)) 2993 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 2994 break; 2995 case SPEED_40000: 2996 if ((support_spds & BNXT_LINK_SPEED_MSK_40GB) || 2997 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_40GB)) { 2998 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 2999 lanes_needed = 4; 3000 } 3001 break; 3002 case SPEED_50000: 3003 if (((support_spds & BNXT_LINK_SPEED_MSK_50GB) || 3004 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB)) && 3005 lanes != 1) { 3006 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 3007 lanes_needed = 2; 3008 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) { 3009 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB; 3010 sig_mode = BNXT_SIG_MODE_PAM4; 3011 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB_PAM4) { 3012 fw_speed = BNXT_LINK_SPEED_50GB_PAM4; 3013 sig_mode = BNXT_SIG_MODE_PAM4; 3014 } 3015 break; 3016 case SPEED_100000: 3017 if (((support_spds & BNXT_LINK_SPEED_MSK_100GB) || 3018 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB)) && 3019 lanes != 2 && lanes != 1) { 3020 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB; 3021 lanes_needed = 4; 3022 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) { 3023 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB; 3024 sig_mode = BNXT_SIG_MODE_PAM4; 3025 lanes_needed = 2; 3026 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4) && 3027 lanes != 1) { 3028 fw_speed = BNXT_LINK_SPEED_100GB_PAM4; 3029 sig_mode = BNXT_SIG_MODE_PAM4; 3030 lanes_needed = 2; 3031 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112) { 3032 fw_speed = BNXT_LINK_SPEED_100GB_PAM4_112; 3033 sig_mode = BNXT_SIG_MODE_PAM4_112; 3034 } 3035 break; 3036 case SPEED_200000: 3037 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) { 3038 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB; 3039 sig_mode = BNXT_SIG_MODE_PAM4; 3040 lanes_needed = 4; 3041 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4) && 3042 lanes != 2) { 3043 fw_speed = BNXT_LINK_SPEED_200GB_PAM4; 3044 sig_mode = BNXT_SIG_MODE_PAM4; 3045 lanes_needed = 4; 3046 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112) { 3047 fw_speed = BNXT_LINK_SPEED_200GB_PAM4_112; 3048 sig_mode = BNXT_SIG_MODE_PAM4_112; 3049 lanes_needed = 2; 3050 } 3051 break; 3052 case SPEED_400000: 3053 if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4) && 3054 lanes != 4) { 3055 fw_speed = BNXT_LINK_SPEED_400GB_PAM4; 3056 sig_mode = BNXT_SIG_MODE_PAM4; 3057 lanes_needed = 8; 3058 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112) { 3059 fw_speed = BNXT_LINK_SPEED_400GB_PAM4_112; 3060 sig_mode = BNXT_SIG_MODE_PAM4_112; 3061 lanes_needed = 4; 3062 } 3063 break; 3064 } 3065 3066 if (!fw_speed) { 3067 netdev_err(dev, "unsupported speed!\n"); 3068 return -EINVAL; 3069 } 3070 3071 if (lanes && lanes != lanes_needed) { 3072 netdev_err(dev, "unsupported number of lanes for speed\n"); 3073 return -EINVAL; 3074 } 3075 3076 if (link_info->req_link_speed == fw_speed && 3077 link_info->req_signal_mode == sig_mode && 3078 link_info->autoneg == 0) 3079 return -EALREADY; 3080 3081 link_info->req_link_speed = fw_speed; 3082 link_info->req_signal_mode = sig_mode; 3083 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 3084 link_info->autoneg = 0; 3085 link_info->advertising = 0; 3086 link_info->advertising_pam4 = 0; 3087 3088 return 0; 3089 } 3090 3091 u16 bnxt_get_fw_auto_link_speeds(const unsigned long *mode) 3092 { 3093 u16 fw_speed_mask = 0; 3094 3095 if (linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode) || 3096 linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mode)) 3097 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 3098 3099 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode) || 3100 linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, mode)) 3101 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 3102 3103 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode)) 3104 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 3105 3106 if (linkmode_test_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode)) 3107 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 3108 3109 return fw_speed_mask; 3110 } 3111 3112 static int bnxt_set_link_ksettings(struct net_device *dev, 3113 const struct ethtool_link_ksettings *lk_ksettings) 3114 { 3115 struct bnxt *bp = netdev_priv(dev); 3116 struct bnxt_link_info *link_info = &bp->link_info; 3117 const struct ethtool_link_settings *base = &lk_ksettings->base; 3118 bool set_pause = false; 3119 u32 speed, lanes = 0; 3120 int rc = 0; 3121 3122 if (!BNXT_PHY_CFG_ABLE(bp)) 3123 return -EOPNOTSUPP; 3124 3125 mutex_lock(&bp->link_lock); 3126 if (base->autoneg == AUTONEG_ENABLE) { 3127 bnxt_set_ethtool_speeds(link_info, 3128 lk_ksettings->link_modes.advertising); 3129 link_info->autoneg |= BNXT_AUTONEG_SPEED; 3130 if (!link_info->advertising && !link_info->advertising_pam4) { 3131 link_info->advertising = link_info->support_auto_speeds; 3132 link_info->advertising_pam4 = 3133 link_info->support_pam4_auto_speeds; 3134 } 3135 /* any change to autoneg will cause link change, therefore the 3136 * driver should put back the original pause setting in autoneg 3137 */ 3138 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 3139 set_pause = true; 3140 } else { 3141 u8 phy_type = link_info->phy_type; 3142 3143 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 3144 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 3145 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 3146 netdev_err(dev, "10GBase-T devices must autoneg\n"); 3147 rc = -EINVAL; 3148 goto set_setting_exit; 3149 } 3150 if (base->duplex == DUPLEX_HALF) { 3151 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 3152 rc = -EINVAL; 3153 goto set_setting_exit; 3154 } 3155 speed = base->speed; 3156 lanes = lk_ksettings->lanes; 3157 rc = bnxt_force_link_speed(dev, speed, lanes); 3158 if (rc) { 3159 if (rc == -EALREADY) 3160 rc = 0; 3161 goto set_setting_exit; 3162 } 3163 } 3164 3165 if (netif_running(dev)) 3166 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 3167 3168 set_setting_exit: 3169 mutex_unlock(&bp->link_lock); 3170 return rc; 3171 } 3172 3173 static int bnxt_get_fecparam(struct net_device *dev, 3174 struct ethtool_fecparam *fec) 3175 { 3176 struct bnxt *bp = netdev_priv(dev); 3177 struct bnxt_link_info *link_info; 3178 u8 active_fec; 3179 u16 fec_cfg; 3180 3181 link_info = &bp->link_info; 3182 fec_cfg = link_info->fec_cfg; 3183 active_fec = link_info->active_fec_sig_mode & 3184 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK; 3185 if (fec_cfg & BNXT_FEC_NONE) { 3186 fec->fec = ETHTOOL_FEC_NONE; 3187 fec->active_fec = ETHTOOL_FEC_NONE; 3188 return 0; 3189 } 3190 if (fec_cfg & BNXT_FEC_AUTONEG) 3191 fec->fec |= ETHTOOL_FEC_AUTO; 3192 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 3193 fec->fec |= ETHTOOL_FEC_BASER; 3194 if (fec_cfg & BNXT_FEC_ENC_RS) 3195 fec->fec |= ETHTOOL_FEC_RS; 3196 if (fec_cfg & BNXT_FEC_ENC_LLRS) 3197 fec->fec |= ETHTOOL_FEC_LLRS; 3198 3199 switch (active_fec) { 3200 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE: 3201 fec->active_fec |= ETHTOOL_FEC_BASER; 3202 break; 3203 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE: 3204 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE: 3205 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE: 3206 fec->active_fec |= ETHTOOL_FEC_RS; 3207 break; 3208 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE: 3209 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE: 3210 fec->active_fec |= ETHTOOL_FEC_LLRS; 3211 break; 3212 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE: 3213 fec->active_fec |= ETHTOOL_FEC_OFF; 3214 break; 3215 } 3216 return 0; 3217 } 3218 3219 static void bnxt_get_fec_stats(struct net_device *dev, 3220 struct ethtool_fec_stats *fec_stats, 3221 struct ethtool_fec_hist *hist) 3222 { 3223 struct bnxt *bp = netdev_priv(dev); 3224 u64 *rx; 3225 3226 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 3227 return; 3228 3229 rx = bp->rx_port_stats_ext.sw_stats; 3230 fec_stats->corrected_bits.total = 3231 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits)); 3232 3233 if (bp->fw_rx_stats_ext_size <= BNXT_RX_STATS_EXT_NUM_LEGACY) 3234 return; 3235 3236 fec_stats->corrected_blocks.total = 3237 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)); 3238 fec_stats->uncorrectable_blocks.total = 3239 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_uncorrectable_blocks)); 3240 } 3241 3242 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info, 3243 u32 fec) 3244 { 3245 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE; 3246 3247 if (fec & ETHTOOL_FEC_BASER) 3248 fw_fec |= BNXT_FEC_BASE_R_ON(link_info); 3249 else if (fec & ETHTOOL_FEC_RS) 3250 fw_fec |= BNXT_FEC_RS_ON(link_info); 3251 else if (fec & ETHTOOL_FEC_LLRS) 3252 fw_fec |= BNXT_FEC_LLRS_ON; 3253 return fw_fec; 3254 } 3255 3256 static int bnxt_set_fecparam(struct net_device *dev, 3257 struct ethtool_fecparam *fecparam) 3258 { 3259 struct hwrm_port_phy_cfg_input *req; 3260 struct bnxt *bp = netdev_priv(dev); 3261 struct bnxt_link_info *link_info; 3262 u32 new_cfg, fec = fecparam->fec; 3263 u16 fec_cfg; 3264 int rc; 3265 3266 link_info = &bp->link_info; 3267 fec_cfg = link_info->fec_cfg; 3268 if (fec_cfg & BNXT_FEC_NONE) 3269 return -EOPNOTSUPP; 3270 3271 if (fec & ETHTOOL_FEC_OFF) { 3272 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE | 3273 BNXT_FEC_ALL_OFF(link_info); 3274 goto apply_fec; 3275 } 3276 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) || 3277 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) || 3278 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) || 3279 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP))) 3280 return -EINVAL; 3281 3282 if (fec & ETHTOOL_FEC_AUTO) { 3283 if (!link_info->autoneg) 3284 return -EINVAL; 3285 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE; 3286 } else { 3287 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec); 3288 } 3289 3290 apply_fec: 3291 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 3292 if (rc) 3293 return rc; 3294 req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 3295 rc = hwrm_req_send(bp, req); 3296 /* update current settings */ 3297 if (!rc) { 3298 mutex_lock(&bp->link_lock); 3299 bnxt_update_link(bp, false); 3300 mutex_unlock(&bp->link_lock); 3301 } 3302 return rc; 3303 } 3304 3305 static void bnxt_get_pauseparam(struct net_device *dev, 3306 struct ethtool_pauseparam *epause) 3307 { 3308 struct bnxt *bp = netdev_priv(dev); 3309 struct bnxt_link_info *link_info = &bp->link_info; 3310 3311 if (BNXT_VF(bp)) 3312 return; 3313 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 3314 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 3315 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 3316 } 3317 3318 static void bnxt_get_pause_stats(struct net_device *dev, 3319 struct ethtool_pause_stats *epstat) 3320 { 3321 struct bnxt *bp = netdev_priv(dev); 3322 u64 *rx, *tx; 3323 3324 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 3325 return; 3326 3327 rx = bp->port_stats.sw_stats; 3328 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 3329 3330 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames); 3331 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames); 3332 } 3333 3334 static int bnxt_set_pauseparam(struct net_device *dev, 3335 struct ethtool_pauseparam *epause) 3336 { 3337 int rc = 0; 3338 struct bnxt *bp = netdev_priv(dev); 3339 struct bnxt_link_info *link_info = &bp->link_info; 3340 3341 if (!BNXT_PHY_CFG_ABLE(bp) || (bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 3342 return -EOPNOTSUPP; 3343 3344 mutex_lock(&bp->link_lock); 3345 if (epause->autoneg) { 3346 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 3347 rc = -EINVAL; 3348 goto pause_exit; 3349 } 3350 3351 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 3352 link_info->req_flow_ctrl = 0; 3353 } else { 3354 /* when transition from auto pause to force pause, 3355 * force a link change 3356 */ 3357 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 3358 link_info->force_link_chng = true; 3359 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 3360 link_info->req_flow_ctrl = 0; 3361 } 3362 if (epause->rx_pause) 3363 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 3364 3365 if (epause->tx_pause) 3366 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 3367 3368 if (netif_running(dev)) 3369 rc = bnxt_hwrm_set_pause(bp); 3370 3371 pause_exit: 3372 mutex_unlock(&bp->link_lock); 3373 return rc; 3374 } 3375 3376 static u32 bnxt_get_link(struct net_device *dev) 3377 { 3378 struct bnxt *bp = netdev_priv(dev); 3379 3380 /* TODO: handle MF, VF, driver close case */ 3381 return BNXT_LINK_IS_UP(bp); 3382 } 3383 3384 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp, 3385 struct hwrm_nvm_get_dev_info_output *nvm_dev_info) 3386 { 3387 struct hwrm_nvm_get_dev_info_output *resp; 3388 struct hwrm_nvm_get_dev_info_input *req; 3389 int rc; 3390 3391 if (BNXT_VF(bp)) 3392 return -EOPNOTSUPP; 3393 3394 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO); 3395 if (rc) 3396 return rc; 3397 3398 resp = hwrm_req_hold(bp, req); 3399 rc = hwrm_req_send(bp, req); 3400 if (!rc) 3401 memcpy(nvm_dev_info, resp, sizeof(*resp)); 3402 hwrm_req_drop(bp, req); 3403 return rc; 3404 } 3405 3406 static void bnxt_print_admin_err(struct bnxt *bp) 3407 { 3408 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 3409 } 3410 3411 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 3412 u16 ext, u16 *index, u32 *item_length, 3413 u32 *data_length); 3414 3415 int bnxt_flash_nvram(struct net_device *dev, u16 dir_type, 3416 u16 dir_ordinal, u16 dir_ext, u16 dir_attr, 3417 u32 dir_item_len, const u8 *data, 3418 size_t data_len) 3419 { 3420 struct bnxt *bp = netdev_priv(dev); 3421 struct hwrm_nvm_write_input *req; 3422 int rc; 3423 3424 rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE); 3425 if (rc) 3426 return rc; 3427 3428 if (data_len && data) { 3429 dma_addr_t dma_handle; 3430 u8 *kmem; 3431 3432 kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle); 3433 if (!kmem) { 3434 hwrm_req_drop(bp, req); 3435 return -ENOMEM; 3436 } 3437 3438 req->dir_data_length = cpu_to_le32(data_len); 3439 3440 memcpy(kmem, data, data_len); 3441 req->host_src_addr = cpu_to_le64(dma_handle); 3442 } 3443 3444 hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout); 3445 req->dir_type = cpu_to_le16(dir_type); 3446 req->dir_ordinal = cpu_to_le16(dir_ordinal); 3447 req->dir_ext = cpu_to_le16(dir_ext); 3448 req->dir_attr = cpu_to_le16(dir_attr); 3449 req->dir_item_length = cpu_to_le32(dir_item_len); 3450 rc = hwrm_req_send(bp, req); 3451 3452 if (rc == -EACCES) 3453 bnxt_print_admin_err(bp); 3454 return rc; 3455 } 3456 3457 int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type, 3458 u8 self_reset, u8 flags) 3459 { 3460 struct bnxt *bp = netdev_priv(dev); 3461 struct hwrm_fw_reset_input *req; 3462 int rc; 3463 3464 if (!bnxt_hwrm_reset_permitted(bp)) { 3465 netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver"); 3466 return -EPERM; 3467 } 3468 3469 rc = hwrm_req_init(bp, req, HWRM_FW_RESET); 3470 if (rc) 3471 return rc; 3472 3473 req->embedded_proc_type = proc_type; 3474 req->selfrst_status = self_reset; 3475 req->flags = flags; 3476 3477 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) { 3478 rc = hwrm_req_send_silent(bp, req); 3479 } else { 3480 rc = hwrm_req_send(bp, req); 3481 if (rc == -EACCES) 3482 bnxt_print_admin_err(bp); 3483 } 3484 return rc; 3485 } 3486 3487 static int bnxt_firmware_reset(struct net_device *dev, 3488 enum bnxt_nvm_directory_type dir_type) 3489 { 3490 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE; 3491 u8 proc_type, flags = 0; 3492 3493 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 3494 /* (e.g. when firmware isn't already running) */ 3495 switch (dir_type) { 3496 case BNX_DIR_TYPE_CHIMP_PATCH: 3497 case BNX_DIR_TYPE_BOOTCODE: 3498 case BNX_DIR_TYPE_BOOTCODE_2: 3499 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 3500 /* Self-reset ChiMP upon next PCIe reset: */ 3501 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 3502 break; 3503 case BNX_DIR_TYPE_APE_FW: 3504 case BNX_DIR_TYPE_APE_PATCH: 3505 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 3506 /* Self-reset APE upon next PCIe reset: */ 3507 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 3508 break; 3509 case BNX_DIR_TYPE_KONG_FW: 3510 case BNX_DIR_TYPE_KONG_PATCH: 3511 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 3512 break; 3513 case BNX_DIR_TYPE_BONO_FW: 3514 case BNX_DIR_TYPE_BONO_PATCH: 3515 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 3516 break; 3517 default: 3518 return -EINVAL; 3519 } 3520 3521 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags); 3522 } 3523 3524 static int bnxt_firmware_reset_chip(struct net_device *dev) 3525 { 3526 struct bnxt *bp = netdev_priv(dev); 3527 u8 flags = 0; 3528 3529 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 3530 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 3531 3532 return bnxt_hwrm_firmware_reset(dev, 3533 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP, 3534 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP, 3535 flags); 3536 } 3537 3538 static int bnxt_firmware_reset_ap(struct net_device *dev) 3539 { 3540 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP, 3541 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE, 3542 0); 3543 } 3544 3545 static int bnxt_flash_firmware(struct net_device *dev, 3546 u16 dir_type, 3547 const u8 *fw_data, 3548 size_t fw_size) 3549 { 3550 int rc = 0; 3551 u16 code_type; 3552 u32 stored_crc; 3553 u32 calculated_crc; 3554 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 3555 3556 switch (dir_type) { 3557 case BNX_DIR_TYPE_BOOTCODE: 3558 case BNX_DIR_TYPE_BOOTCODE_2: 3559 code_type = CODE_BOOT; 3560 break; 3561 case BNX_DIR_TYPE_CHIMP_PATCH: 3562 code_type = CODE_CHIMP_PATCH; 3563 break; 3564 case BNX_DIR_TYPE_APE_FW: 3565 code_type = CODE_MCTP_PASSTHRU; 3566 break; 3567 case BNX_DIR_TYPE_APE_PATCH: 3568 code_type = CODE_APE_PATCH; 3569 break; 3570 case BNX_DIR_TYPE_KONG_FW: 3571 code_type = CODE_KONG_FW; 3572 break; 3573 case BNX_DIR_TYPE_KONG_PATCH: 3574 code_type = CODE_KONG_PATCH; 3575 break; 3576 case BNX_DIR_TYPE_BONO_FW: 3577 code_type = CODE_BONO_FW; 3578 break; 3579 case BNX_DIR_TYPE_BONO_PATCH: 3580 code_type = CODE_BONO_PATCH; 3581 break; 3582 default: 3583 netdev_err(dev, "Unsupported directory entry type: %u\n", 3584 dir_type); 3585 return -EINVAL; 3586 } 3587 if (fw_size < sizeof(struct bnxt_fw_header)) { 3588 netdev_err(dev, "Invalid firmware file size: %u\n", 3589 (unsigned int)fw_size); 3590 return -EINVAL; 3591 } 3592 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 3593 netdev_err(dev, "Invalid firmware signature: %08X\n", 3594 le32_to_cpu(header->signature)); 3595 return -EINVAL; 3596 } 3597 if (header->code_type != code_type) { 3598 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 3599 code_type, header->code_type); 3600 return -EINVAL; 3601 } 3602 if (header->device != DEVICE_CUMULUS_FAMILY) { 3603 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 3604 DEVICE_CUMULUS_FAMILY, header->device); 3605 return -EINVAL; 3606 } 3607 /* Confirm the CRC32 checksum of the file: */ 3608 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 3609 sizeof(stored_crc))); 3610 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 3611 if (calculated_crc != stored_crc) { 3612 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 3613 (unsigned long)stored_crc, 3614 (unsigned long)calculated_crc); 3615 return -EINVAL; 3616 } 3617 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3618 0, 0, 0, fw_data, fw_size); 3619 if (rc == 0) /* Firmware update successful */ 3620 rc = bnxt_firmware_reset(dev, dir_type); 3621 3622 return rc; 3623 } 3624 3625 static int bnxt_flash_microcode(struct net_device *dev, 3626 u16 dir_type, 3627 const u8 *fw_data, 3628 size_t fw_size) 3629 { 3630 struct bnxt_ucode_trailer *trailer; 3631 u32 calculated_crc; 3632 u32 stored_crc; 3633 int rc = 0; 3634 3635 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 3636 netdev_err(dev, "Invalid microcode file size: %u\n", 3637 (unsigned int)fw_size); 3638 return -EINVAL; 3639 } 3640 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 3641 sizeof(*trailer))); 3642 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 3643 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 3644 le32_to_cpu(trailer->sig)); 3645 return -EINVAL; 3646 } 3647 if (le16_to_cpu(trailer->dir_type) != dir_type) { 3648 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 3649 dir_type, le16_to_cpu(trailer->dir_type)); 3650 return -EINVAL; 3651 } 3652 if (le16_to_cpu(trailer->trailer_length) < 3653 sizeof(struct bnxt_ucode_trailer)) { 3654 netdev_err(dev, "Invalid microcode trailer length: %d\n", 3655 le16_to_cpu(trailer->trailer_length)); 3656 return -EINVAL; 3657 } 3658 3659 /* Confirm the CRC32 checksum of the file: */ 3660 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 3661 sizeof(stored_crc))); 3662 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 3663 if (calculated_crc != stored_crc) { 3664 netdev_err(dev, 3665 "CRC32 (%08lX) does not match calculated: %08lX\n", 3666 (unsigned long)stored_crc, 3667 (unsigned long)calculated_crc); 3668 return -EINVAL; 3669 } 3670 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3671 0, 0, 0, fw_data, fw_size); 3672 3673 return rc; 3674 } 3675 3676 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 3677 { 3678 switch (dir_type) { 3679 case BNX_DIR_TYPE_CHIMP_PATCH: 3680 case BNX_DIR_TYPE_BOOTCODE: 3681 case BNX_DIR_TYPE_BOOTCODE_2: 3682 case BNX_DIR_TYPE_APE_FW: 3683 case BNX_DIR_TYPE_APE_PATCH: 3684 case BNX_DIR_TYPE_KONG_FW: 3685 case BNX_DIR_TYPE_KONG_PATCH: 3686 case BNX_DIR_TYPE_BONO_FW: 3687 case BNX_DIR_TYPE_BONO_PATCH: 3688 return true; 3689 } 3690 3691 return false; 3692 } 3693 3694 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 3695 { 3696 switch (dir_type) { 3697 case BNX_DIR_TYPE_AVS: 3698 case BNX_DIR_TYPE_EXP_ROM_MBA: 3699 case BNX_DIR_TYPE_PCIE: 3700 case BNX_DIR_TYPE_TSCF_UCODE: 3701 case BNX_DIR_TYPE_EXT_PHY: 3702 case BNX_DIR_TYPE_CCM: 3703 case BNX_DIR_TYPE_ISCSI_BOOT: 3704 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 3705 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 3706 return true; 3707 } 3708 3709 return false; 3710 } 3711 3712 static bool bnxt_dir_type_is_executable(u16 dir_type) 3713 { 3714 return bnxt_dir_type_is_ape_bin_format(dir_type) || 3715 bnxt_dir_type_is_other_exec_format(dir_type); 3716 } 3717 3718 static int bnxt_flash_firmware_from_file(struct net_device *dev, 3719 u16 dir_type, 3720 const char *filename) 3721 { 3722 const struct firmware *fw; 3723 int rc; 3724 3725 rc = request_firmware(&fw, filename, &dev->dev); 3726 if (rc != 0) { 3727 netdev_err(dev, "Error %d requesting firmware file: %s\n", 3728 rc, filename); 3729 return rc; 3730 } 3731 if (bnxt_dir_type_is_ape_bin_format(dir_type)) 3732 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 3733 else if (bnxt_dir_type_is_other_exec_format(dir_type)) 3734 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 3735 else 3736 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3737 0, 0, 0, fw->data, fw->size); 3738 release_firmware(fw); 3739 return rc; 3740 } 3741 3742 #define MSG_INTEGRITY_ERR "PKG install error : Data integrity on NVM" 3743 #define MSG_INVALID_PKG "PKG install error : Invalid package" 3744 #define MSG_AUTHENTICATION_ERR "PKG install error : Authentication error" 3745 #define MSG_INVALID_DEV "PKG install error : Invalid device" 3746 #define MSG_INTERNAL_ERR "PKG install error : Internal error" 3747 #define MSG_NO_PKG_UPDATE_AREA_ERR "PKG update area not created in nvram" 3748 #define MSG_NO_SPACE_ERR "PKG insufficient update area in nvram" 3749 #define MSG_RESIZE_UPDATE_ERR "Resize UPDATE entry error" 3750 #define MSG_ANTI_ROLLBACK_ERR "HWRM_NVM_INSTALL_UPDATE failure due to Anti-rollback detected" 3751 #define MSG_GENERIC_FAILURE_ERR "HWRM_NVM_INSTALL_UPDATE failure" 3752 3753 static int nvm_update_err_to_stderr(struct net_device *dev, u8 result, 3754 struct netlink_ext_ack *extack) 3755 { 3756 switch (result) { 3757 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER: 3758 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER: 3759 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR: 3760 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR: 3761 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND: 3762 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED: 3763 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTEGRITY_ERR); 3764 return -EINVAL; 3765 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE: 3766 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER: 3767 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE: 3768 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM: 3769 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH: 3770 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST: 3771 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER: 3772 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM: 3773 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM: 3774 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH: 3775 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE: 3776 case NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM: 3777 case NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM: 3778 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_PKG); 3779 return -ENOPKG; 3780 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR: 3781 BNXT_NVM_ERR_MSG(dev, extack, MSG_AUTHENTICATION_ERR); 3782 return -EPERM; 3783 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV: 3784 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID: 3785 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR: 3786 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID: 3787 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM: 3788 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_DEV); 3789 return -EOPNOTSUPP; 3790 default: 3791 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTERNAL_ERR); 3792 return -EIO; 3793 } 3794 } 3795 3796 #define BNXT_PKG_DMA_SIZE 0x40000 3797 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE)) 3798 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST)) 3799 3800 static int bnxt_resize_update_entry(struct net_device *dev, size_t fw_size, 3801 struct netlink_ext_ack *extack) 3802 { 3803 u32 item_len; 3804 int rc; 3805 3806 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 3807 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, NULL, 3808 &item_len, NULL); 3809 if (rc) { 3810 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 3811 return rc; 3812 } 3813 3814 if (fw_size > item_len) { 3815 rc = bnxt_flash_nvram(dev, BNX_DIR_TYPE_UPDATE, 3816 BNX_DIR_ORDINAL_FIRST, 0, 1, 3817 round_up(fw_size, 4096), NULL, 0); 3818 if (rc) { 3819 BNXT_NVM_ERR_MSG(dev, extack, MSG_RESIZE_UPDATE_ERR); 3820 return rc; 3821 } 3822 } 3823 return 0; 3824 } 3825 3826 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw, 3827 u32 install_type, struct netlink_ext_ack *extack) 3828 { 3829 struct hwrm_nvm_install_update_input *install; 3830 struct hwrm_nvm_install_update_output *resp; 3831 struct hwrm_nvm_modify_input *modify; 3832 struct bnxt *bp = netdev_priv(dev); 3833 bool defrag_attempted = false; 3834 dma_addr_t dma_handle; 3835 u8 *kmem = NULL; 3836 u32 modify_len; 3837 u32 item_len; 3838 u8 cmd_err; 3839 u16 index; 3840 int rc; 3841 3842 /* resize before flashing larger image than available space */ 3843 rc = bnxt_resize_update_entry(dev, fw->size, extack); 3844 if (rc) 3845 return rc; 3846 3847 bnxt_hwrm_fw_set_time(bp); 3848 3849 rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY); 3850 if (rc) 3851 return rc; 3852 3853 /* Try allocating a large DMA buffer first. Older fw will 3854 * cause excessive NVRAM erases when using small blocks. 3855 */ 3856 modify_len = roundup_pow_of_two(fw->size); 3857 modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE); 3858 while (1) { 3859 kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle); 3860 if (!kmem && modify_len > PAGE_SIZE) 3861 modify_len /= 2; 3862 else 3863 break; 3864 } 3865 if (!kmem) { 3866 hwrm_req_drop(bp, modify); 3867 return -ENOMEM; 3868 } 3869 3870 rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE); 3871 if (rc) { 3872 hwrm_req_drop(bp, modify); 3873 return rc; 3874 } 3875 3876 hwrm_req_timeout(bp, modify, bp->hwrm_cmd_max_timeout); 3877 hwrm_req_timeout(bp, install, bp->hwrm_cmd_max_timeout); 3878 3879 hwrm_req_hold(bp, modify); 3880 modify->host_src_addr = cpu_to_le64(dma_handle); 3881 3882 resp = hwrm_req_hold(bp, install); 3883 if ((install_type & 0xffff) == 0) 3884 install_type >>= 16; 3885 install->install_type = cpu_to_le32(install_type); 3886 3887 do { 3888 u32 copied = 0, len = modify_len; 3889 3890 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 3891 BNX_DIR_ORDINAL_FIRST, 3892 BNX_DIR_EXT_NONE, 3893 &index, &item_len, NULL); 3894 if (rc) { 3895 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 3896 break; 3897 } 3898 if (fw->size > item_len) { 3899 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_SPACE_ERR); 3900 rc = -EFBIG; 3901 break; 3902 } 3903 3904 modify->dir_idx = cpu_to_le16(index); 3905 3906 if (fw->size > modify_len) 3907 modify->flags = BNXT_NVM_MORE_FLAG; 3908 while (copied < fw->size) { 3909 u32 balance = fw->size - copied; 3910 3911 if (balance <= modify_len) { 3912 len = balance; 3913 if (copied) 3914 modify->flags |= BNXT_NVM_LAST_FLAG; 3915 } 3916 memcpy(kmem, fw->data + copied, len); 3917 modify->len = cpu_to_le32(len); 3918 modify->offset = cpu_to_le32(copied); 3919 rc = hwrm_req_send(bp, modify); 3920 if (rc) 3921 goto pkg_abort; 3922 copied += len; 3923 } 3924 3925 rc = hwrm_req_send_silent(bp, install); 3926 if (!rc) 3927 break; 3928 3929 if (defrag_attempted) { 3930 /* We have tried to defragment already in the previous 3931 * iteration. Return with the result for INSTALL_UPDATE 3932 */ 3933 break; 3934 } 3935 3936 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 3937 3938 switch (cmd_err) { 3939 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK: 3940 BNXT_NVM_ERR_MSG(dev, extack, MSG_ANTI_ROLLBACK_ERR); 3941 rc = -EALREADY; 3942 break; 3943 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR: 3944 install->flags = 3945 cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 3946 3947 rc = hwrm_req_send_silent(bp, install); 3948 if (!rc) 3949 break; 3950 3951 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 3952 3953 if (cmd_err == NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) { 3954 /* FW has cleared NVM area, driver will create 3955 * UPDATE directory and try the flash again 3956 */ 3957 defrag_attempted = true; 3958 install->flags = 0; 3959 rc = bnxt_flash_nvram(bp->dev, 3960 BNX_DIR_TYPE_UPDATE, 3961 BNX_DIR_ORDINAL_FIRST, 3962 0, 0, item_len, NULL, 0); 3963 if (!rc) 3964 break; 3965 } 3966 fallthrough; 3967 default: 3968 BNXT_NVM_ERR_MSG(dev, extack, MSG_GENERIC_FAILURE_ERR); 3969 } 3970 } while (defrag_attempted && !rc); 3971 3972 pkg_abort: 3973 hwrm_req_drop(bp, modify); 3974 hwrm_req_drop(bp, install); 3975 3976 if (resp->result) { 3977 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 3978 (s8)resp->result, (int)resp->problem_item); 3979 rc = nvm_update_err_to_stderr(dev, resp->result, extack); 3980 } 3981 if (rc == -EACCES) 3982 bnxt_print_admin_err(bp); 3983 return rc; 3984 } 3985 3986 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename, 3987 u32 install_type, struct netlink_ext_ack *extack) 3988 { 3989 const struct firmware *fw; 3990 int rc; 3991 3992 rc = request_firmware(&fw, filename, &dev->dev); 3993 if (rc != 0) { 3994 netdev_err(dev, "PKG error %d requesting file: %s\n", 3995 rc, filename); 3996 return rc; 3997 } 3998 3999 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type, extack); 4000 4001 release_firmware(fw); 4002 4003 return rc; 4004 } 4005 4006 static int bnxt_flash_device(struct net_device *dev, 4007 struct ethtool_flash *flash) 4008 { 4009 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 4010 netdev_err(dev, "flashdev not supported from a virtual function\n"); 4011 return -EINVAL; 4012 } 4013 4014 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 4015 flash->region > 0xffff) 4016 return bnxt_flash_package_from_file(dev, flash->data, 4017 flash->region, NULL); 4018 4019 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 4020 } 4021 4022 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 4023 { 4024 struct hwrm_nvm_get_dir_info_output *output; 4025 struct hwrm_nvm_get_dir_info_input *req; 4026 struct bnxt *bp = netdev_priv(dev); 4027 int rc; 4028 4029 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO); 4030 if (rc) 4031 return rc; 4032 4033 output = hwrm_req_hold(bp, req); 4034 rc = hwrm_req_send(bp, req); 4035 if (!rc) { 4036 *entries = le32_to_cpu(output->entries); 4037 *length = le32_to_cpu(output->entry_length); 4038 } 4039 hwrm_req_drop(bp, req); 4040 return rc; 4041 } 4042 4043 static int bnxt_get_eeprom_len(struct net_device *dev) 4044 { 4045 struct bnxt *bp = netdev_priv(dev); 4046 4047 if (BNXT_VF(bp)) 4048 return 0; 4049 4050 /* The -1 return value allows the entire 32-bit range of offsets to be 4051 * passed via the ethtool command-line utility. 4052 */ 4053 return -1; 4054 } 4055 4056 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 4057 { 4058 struct bnxt *bp = netdev_priv(dev); 4059 int rc; 4060 u32 dir_entries; 4061 u32 entry_length; 4062 u8 *buf; 4063 size_t buflen; 4064 dma_addr_t dma_handle; 4065 struct hwrm_nvm_get_dir_entries_input *req; 4066 4067 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 4068 if (rc != 0) 4069 return rc; 4070 4071 if (!dir_entries || !entry_length) 4072 return -EIO; 4073 4074 /* Insert 2 bytes of directory info (count and size of entries) */ 4075 if (len < 2) 4076 return -EINVAL; 4077 4078 *data++ = dir_entries; 4079 *data++ = entry_length; 4080 len -= 2; 4081 memset(data, 0xff, len); 4082 4083 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES); 4084 if (rc) 4085 return rc; 4086 4087 buflen = mul_u32_u32(dir_entries, entry_length); 4088 buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle); 4089 if (!buf) { 4090 hwrm_req_drop(bp, req); 4091 return -ENOMEM; 4092 } 4093 req->host_dest_addr = cpu_to_le64(dma_handle); 4094 4095 hwrm_req_hold(bp, req); /* hold the slice */ 4096 rc = hwrm_req_send(bp, req); 4097 if (rc == 0) 4098 memcpy(data, buf, len > buflen ? buflen : len); 4099 hwrm_req_drop(bp, req); 4100 return rc; 4101 } 4102 4103 int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 4104 u32 length, u8 *data) 4105 { 4106 struct bnxt *bp = netdev_priv(dev); 4107 int rc; 4108 u8 *buf; 4109 dma_addr_t dma_handle; 4110 struct hwrm_nvm_read_input *req; 4111 4112 if (!length) 4113 return -EINVAL; 4114 4115 rc = hwrm_req_init(bp, req, HWRM_NVM_READ); 4116 if (rc) 4117 return rc; 4118 4119 buf = hwrm_req_dma_slice(bp, req, length, &dma_handle); 4120 if (!buf) { 4121 hwrm_req_drop(bp, req); 4122 return -ENOMEM; 4123 } 4124 4125 req->host_dest_addr = cpu_to_le64(dma_handle); 4126 req->dir_idx = cpu_to_le16(index); 4127 req->offset = cpu_to_le32(offset); 4128 req->len = cpu_to_le32(length); 4129 4130 hwrm_req_hold(bp, req); /* hold the slice */ 4131 rc = hwrm_req_send(bp, req); 4132 if (rc == 0) 4133 memcpy(data, buf, length); 4134 hwrm_req_drop(bp, req); 4135 return rc; 4136 } 4137 4138 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 4139 u16 ext, u16 *index, u32 *item_length, 4140 u32 *data_length) 4141 { 4142 struct hwrm_nvm_find_dir_entry_output *output; 4143 struct hwrm_nvm_find_dir_entry_input *req; 4144 struct bnxt *bp = netdev_priv(dev); 4145 int rc; 4146 4147 rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY); 4148 if (rc) 4149 return rc; 4150 4151 req->enables = 0; 4152 req->dir_idx = 0; 4153 req->dir_type = cpu_to_le16(type); 4154 req->dir_ordinal = cpu_to_le16(ordinal); 4155 req->dir_ext = cpu_to_le16(ext); 4156 req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 4157 output = hwrm_req_hold(bp, req); 4158 rc = hwrm_req_send_silent(bp, req); 4159 if (rc == 0) { 4160 if (index) 4161 *index = le16_to_cpu(output->dir_idx); 4162 if (item_length) 4163 *item_length = le32_to_cpu(output->dir_item_length); 4164 if (data_length) 4165 *data_length = le32_to_cpu(output->dir_data_length); 4166 } 4167 hwrm_req_drop(bp, req); 4168 return rc; 4169 } 4170 4171 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 4172 { 4173 char *retval = NULL; 4174 char *p; 4175 char *value; 4176 int field = 0; 4177 4178 if (datalen < 1) 4179 return NULL; 4180 /* null-terminate the log data (removing last '\n'): */ 4181 data[datalen - 1] = 0; 4182 for (p = data; *p != 0; p++) { 4183 field = 0; 4184 retval = NULL; 4185 while (*p != 0 && *p != '\n') { 4186 value = p; 4187 while (*p != 0 && *p != '\t' && *p != '\n') 4188 p++; 4189 if (field == desired_field) 4190 retval = value; 4191 if (*p != '\t') 4192 break; 4193 *p = 0; 4194 field++; 4195 p++; 4196 } 4197 if (*p == 0) 4198 break; 4199 *p = 0; 4200 } 4201 return retval; 4202 } 4203 4204 int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size) 4205 { 4206 struct bnxt *bp = netdev_priv(dev); 4207 u16 index = 0; 4208 char *pkgver; 4209 u32 pkglen; 4210 u8 *pkgbuf; 4211 int rc; 4212 4213 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 4214 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 4215 &index, NULL, &pkglen); 4216 if (rc) 4217 return rc; 4218 4219 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 4220 if (!pkgbuf) { 4221 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 4222 pkglen); 4223 return -ENOMEM; 4224 } 4225 4226 rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf); 4227 if (rc) 4228 goto err; 4229 4230 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 4231 pkglen); 4232 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) 4233 strscpy(ver, pkgver, size); 4234 else 4235 rc = -ENOENT; 4236 4237 err: 4238 kfree(pkgbuf); 4239 4240 return rc; 4241 } 4242 4243 static void bnxt_get_pkgver(struct net_device *dev) 4244 { 4245 struct bnxt *bp = netdev_priv(dev); 4246 char buf[FW_VER_STR_LEN - 5]; 4247 int len; 4248 4249 if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) { 4250 len = strlen(bp->fw_ver_str); 4251 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len, 4252 "/pkg %s", buf); 4253 } 4254 } 4255 4256 static int bnxt_get_eeprom(struct net_device *dev, 4257 struct ethtool_eeprom *eeprom, 4258 u8 *data) 4259 { 4260 u32 index; 4261 u32 offset; 4262 4263 if (eeprom->offset == 0) /* special offset value to get directory */ 4264 return bnxt_get_nvram_directory(dev, eeprom->len, data); 4265 4266 index = eeprom->offset >> 24; 4267 offset = eeprom->offset & 0xffffff; 4268 4269 if (index == 0) { 4270 netdev_err(dev, "unsupported index value: %d\n", index); 4271 return -EINVAL; 4272 } 4273 4274 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 4275 } 4276 4277 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 4278 { 4279 struct hwrm_nvm_erase_dir_entry_input *req; 4280 struct bnxt *bp = netdev_priv(dev); 4281 int rc; 4282 4283 rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY); 4284 if (rc) 4285 return rc; 4286 4287 req->dir_idx = cpu_to_le16(index); 4288 return hwrm_req_send(bp, req); 4289 } 4290 4291 static int bnxt_set_eeprom(struct net_device *dev, 4292 struct ethtool_eeprom *eeprom, 4293 u8 *data) 4294 { 4295 struct bnxt *bp = netdev_priv(dev); 4296 u8 index, dir_op; 4297 u16 type, ext, ordinal, attr; 4298 4299 if (!BNXT_PF(bp)) { 4300 netdev_err(dev, "NVM write not supported from a virtual function\n"); 4301 return -EINVAL; 4302 } 4303 4304 type = eeprom->magic >> 16; 4305 4306 if (type == 0xffff) { /* special value for directory operations */ 4307 index = eeprom->magic & 0xff; 4308 dir_op = eeprom->magic >> 8; 4309 if (index == 0) 4310 return -EINVAL; 4311 switch (dir_op) { 4312 case 0x0e: /* erase */ 4313 if (eeprom->offset != ~eeprom->magic) 4314 return -EINVAL; 4315 return bnxt_erase_nvram_directory(dev, index - 1); 4316 default: 4317 return -EINVAL; 4318 } 4319 } 4320 4321 /* Create or re-write an NVM item: */ 4322 if (bnxt_dir_type_is_executable(type)) 4323 return -EOPNOTSUPP; 4324 ext = eeprom->magic & 0xffff; 4325 ordinal = eeprom->offset >> 16; 4326 attr = eeprom->offset & 0xffff; 4327 4328 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data, 4329 eeprom->len); 4330 } 4331 4332 static int bnxt_set_eee(struct net_device *dev, struct ethtool_keee *edata) 4333 { 4334 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 4335 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp); 4336 struct bnxt *bp = netdev_priv(dev); 4337 struct ethtool_keee *eee = &bp->eee; 4338 struct bnxt_link_info *link_info = &bp->link_info; 4339 int rc = 0; 4340 4341 if (!BNXT_PHY_CFG_ABLE(bp)) 4342 return -EOPNOTSUPP; 4343 4344 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 4345 return -EOPNOTSUPP; 4346 4347 mutex_lock(&bp->link_lock); 4348 _bnxt_fw_to_linkmode(advertising, link_info->advertising); 4349 if (!edata->eee_enabled) 4350 goto eee_ok; 4351 4352 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 4353 netdev_warn(dev, "EEE requires autoneg\n"); 4354 rc = -EINVAL; 4355 goto eee_exit; 4356 } 4357 if (edata->tx_lpi_enabled) { 4358 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 4359 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 4360 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 4361 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 4362 rc = -EINVAL; 4363 goto eee_exit; 4364 } else if (!bp->lpi_tmr_hi) { 4365 edata->tx_lpi_timer = eee->tx_lpi_timer; 4366 } 4367 } 4368 if (linkmode_empty(edata->advertised)) { 4369 linkmode_and(edata->advertised, advertising, eee->supported); 4370 } else if (linkmode_andnot(tmp, edata->advertised, advertising)) { 4371 netdev_warn(dev, "EEE advertised must be a subset of autoneg advertised speeds\n"); 4372 rc = -EINVAL; 4373 goto eee_exit; 4374 } 4375 4376 linkmode_copy(eee->advertised, edata->advertised); 4377 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 4378 eee->tx_lpi_timer = edata->tx_lpi_timer; 4379 eee_ok: 4380 eee->eee_enabled = edata->eee_enabled; 4381 4382 if (netif_running(dev)) 4383 rc = bnxt_hwrm_set_link_setting(bp, false, true); 4384 4385 eee_exit: 4386 mutex_unlock(&bp->link_lock); 4387 return rc; 4388 } 4389 4390 static int bnxt_get_eee(struct net_device *dev, struct ethtool_keee *edata) 4391 { 4392 struct bnxt *bp = netdev_priv(dev); 4393 4394 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 4395 return -EOPNOTSUPP; 4396 4397 *edata = bp->eee; 4398 if (!bp->eee.eee_enabled) { 4399 /* Preserve tx_lpi_timer so that the last value will be used 4400 * by default when it is re-enabled. 4401 */ 4402 linkmode_zero(edata->advertised); 4403 edata->tx_lpi_enabled = 0; 4404 } 4405 4406 if (!bp->eee.eee_active) 4407 linkmode_zero(edata->lp_advertised); 4408 4409 return 0; 4410 } 4411 4412 static int bnxt_hwrm_pfcwd_qcfg(struct bnxt *bp, u16 *val) 4413 { 4414 struct hwrm_queue_pfcwd_timeout_qcfg_output *resp; 4415 struct hwrm_queue_pfcwd_timeout_qcfg_input *req; 4416 int rc; 4417 4418 rc = hwrm_req_init(bp, req, HWRM_QUEUE_PFCWD_TIMEOUT_QCFG); 4419 if (rc) 4420 return rc; 4421 resp = hwrm_req_hold(bp, req); 4422 rc = hwrm_req_send(bp, req); 4423 if (!rc) 4424 *val = le16_to_cpu(resp->pfcwd_timeout_value); 4425 hwrm_req_drop(bp, req); 4426 return rc; 4427 } 4428 4429 static int bnxt_hwrm_pfcwd_cfg(struct bnxt *bp, u16 val) 4430 { 4431 struct hwrm_queue_pfcwd_timeout_cfg_input *req; 4432 int rc; 4433 4434 rc = hwrm_req_init(bp, req, HWRM_QUEUE_PFCWD_TIMEOUT_CFG); 4435 if (rc) 4436 return rc; 4437 req->pfcwd_timeout_value = cpu_to_le16(val); 4438 rc = hwrm_req_send(bp, req); 4439 return rc; 4440 } 4441 4442 static int bnxt_set_tunable(struct net_device *dev, 4443 const struct ethtool_tunable *tuna, 4444 const void *data) 4445 { 4446 struct bnxt *bp = netdev_priv(dev); 4447 u32 rx_copybreak, val; 4448 4449 switch (tuna->id) { 4450 case ETHTOOL_RX_COPYBREAK: 4451 rx_copybreak = *(u32 *)data; 4452 if (rx_copybreak > BNXT_MAX_RX_COPYBREAK) 4453 return -ERANGE; 4454 if (rx_copybreak != bp->rx_copybreak) { 4455 if (netif_running(dev)) 4456 return -EBUSY; 4457 bp->rx_copybreak = rx_copybreak; 4458 } 4459 return 0; 4460 case ETHTOOL_PFC_PREVENTION_TOUT: 4461 if (BNXT_VF(bp) || !bp->max_pfcwd_tmo_ms) 4462 return -EOPNOTSUPP; 4463 4464 val = *(u16 *)data; 4465 if (val > bp->max_pfcwd_tmo_ms && 4466 val != PFC_STORM_PREVENTION_AUTO) 4467 return -EINVAL; 4468 return bnxt_hwrm_pfcwd_cfg(bp, val); 4469 default: 4470 return -EOPNOTSUPP; 4471 } 4472 } 4473 4474 static int bnxt_get_tunable(struct net_device *dev, 4475 const struct ethtool_tunable *tuna, void *data) 4476 { 4477 struct bnxt *bp = netdev_priv(dev); 4478 4479 switch (tuna->id) { 4480 case ETHTOOL_RX_COPYBREAK: 4481 *(u32 *)data = bp->rx_copybreak; 4482 break; 4483 case ETHTOOL_PFC_PREVENTION_TOUT: 4484 if (!bp->max_pfcwd_tmo_ms) 4485 return -EOPNOTSUPP; 4486 return bnxt_hwrm_pfcwd_qcfg(bp, data); 4487 default: 4488 return -EOPNOTSUPP; 4489 } 4490 4491 return 0; 4492 } 4493 4494 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 4495 u16 page_number, u8 bank, 4496 u16 start_addr, u16 data_length, 4497 u8 *buf) 4498 { 4499 struct hwrm_port_phy_i2c_read_output *output; 4500 struct hwrm_port_phy_i2c_read_input *req; 4501 int rc, byte_offset = 0; 4502 4503 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ); 4504 if (rc) 4505 return rc; 4506 4507 output = hwrm_req_hold(bp, req); 4508 req->i2c_slave_addr = i2c_addr; 4509 req->page_number = cpu_to_le16(page_number); 4510 req->port_id = cpu_to_le16(bp->pf.port_id); 4511 do { 4512 u16 xfer_size; 4513 4514 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 4515 data_length -= xfer_size; 4516 req->page_offset = cpu_to_le16(start_addr + byte_offset); 4517 req->data_length = xfer_size; 4518 req->enables = 4519 cpu_to_le32((start_addr + byte_offset ? 4520 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 4521 0) | 4522 (bank ? 4523 PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER : 4524 0)); 4525 rc = hwrm_req_send(bp, req); 4526 if (!rc) 4527 memcpy(buf + byte_offset, output->data, xfer_size); 4528 byte_offset += xfer_size; 4529 } while (!rc && data_length > 0); 4530 hwrm_req_drop(bp, req); 4531 4532 return rc; 4533 } 4534 4535 static int bnxt_get_module_info(struct net_device *dev, 4536 struct ethtool_modinfo *modinfo) 4537 { 4538 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 4539 struct bnxt *bp = netdev_priv(dev); 4540 int rc; 4541 4542 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 4543 return -EPERM; 4544 4545 /* No point in going further if phy status indicates 4546 * module is not inserted or if it is powered down or 4547 * if it is of type 10GBase-T 4548 */ 4549 if (bp->link_info.module_status > 4550 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 4551 return -EOPNOTSUPP; 4552 4553 /* This feature is not supported in older firmware versions */ 4554 if (bp->hwrm_spec_code < 0x10202) 4555 return -EOPNOTSUPP; 4556 4557 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 0, 4558 SFF_DIAG_SUPPORT_OFFSET + 1, 4559 data); 4560 if (!rc) { 4561 u8 module_id = data[0]; 4562 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 4563 4564 switch (module_id) { 4565 case SFF_MODULE_ID_SFP: 4566 modinfo->type = ETH_MODULE_SFF_8472; 4567 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 4568 if (!diag_supported) 4569 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 4570 break; 4571 case SFF_MODULE_ID_QSFP: 4572 case SFF_MODULE_ID_QSFP_PLUS: 4573 modinfo->type = ETH_MODULE_SFF_8436; 4574 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 4575 break; 4576 case SFF_MODULE_ID_QSFP28: 4577 modinfo->type = ETH_MODULE_SFF_8636; 4578 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 4579 break; 4580 default: 4581 rc = -EOPNOTSUPP; 4582 break; 4583 } 4584 } 4585 return rc; 4586 } 4587 4588 static int bnxt_get_module_eeprom(struct net_device *dev, 4589 struct ethtool_eeprom *eeprom, 4590 u8 *data) 4591 { 4592 struct bnxt *bp = netdev_priv(dev); 4593 u16 start = eeprom->offset, length = eeprom->len; 4594 int rc = 0; 4595 4596 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 4597 return -EPERM; 4598 4599 memset(data, 0, eeprom->len); 4600 4601 /* Read A0 portion of the EEPROM */ 4602 if (start < ETH_MODULE_SFF_8436_LEN) { 4603 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 4604 length = ETH_MODULE_SFF_8436_LEN - start; 4605 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 4606 start, length, data); 4607 if (rc) 4608 return rc; 4609 start += length; 4610 data += length; 4611 length = eeprom->len - length; 4612 } 4613 4614 /* Read A2 portion of the EEPROM */ 4615 if (length) { 4616 start -= ETH_MODULE_SFF_8436_LEN; 4617 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 0, 4618 start, length, data); 4619 } 4620 return rc; 4621 } 4622 4623 static int bnxt_get_module_status(struct bnxt *bp, struct netlink_ext_ack *extack) 4624 { 4625 if (bp->link_info.module_status <= 4626 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 4627 return 0; 4628 4629 if (bp->link_info.phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 4630 bp->link_info.phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE){ 4631 NL_SET_ERR_MSG_MOD(extack, "Operation not supported as PHY type is Base-T"); 4632 return -EOPNOTSUPP; 4633 } 4634 switch (bp->link_info.module_status) { 4635 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 4636 NL_SET_ERR_MSG_MOD(extack, "Transceiver module is powering down"); 4637 break; 4638 case PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED: 4639 NL_SET_ERR_MSG_MOD(extack, "Transceiver module not inserted"); 4640 break; 4641 case PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT: 4642 NL_SET_ERR_MSG_MOD(extack, "Transceiver module disabled due to current fault"); 4643 break; 4644 default: 4645 NL_SET_ERR_MSG_MOD(extack, "Unknown error"); 4646 break; 4647 } 4648 return -EINVAL; 4649 } 4650 4651 static int 4652 bnxt_mod_eeprom_by_page_precheck(struct bnxt *bp, 4653 const struct ethtool_module_eeprom *page_data, 4654 struct netlink_ext_ack *extack) 4655 { 4656 int rc; 4657 4658 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { 4659 NL_SET_ERR_MSG_MOD(extack, 4660 "Module read/write not permitted on untrusted VF"); 4661 return -EPERM; 4662 } 4663 4664 rc = bnxt_get_module_status(bp, extack); 4665 if (rc) 4666 return rc; 4667 4668 if (bp->hwrm_spec_code < 0x10202) { 4669 NL_SET_ERR_MSG_MOD(extack, "Firmware version too old"); 4670 return -EINVAL; 4671 } 4672 4673 if (page_data->bank && !(bp->phy_flags & BNXT_PHY_FL_BANK_SEL)) { 4674 NL_SET_ERR_MSG_MOD(extack, "Firmware not capable for bank selection"); 4675 return -EINVAL; 4676 } 4677 return 0; 4678 } 4679 4680 static int bnxt_get_module_eeprom_by_page(struct net_device *dev, 4681 const struct ethtool_module_eeprom *page_data, 4682 struct netlink_ext_ack *extack) 4683 { 4684 struct bnxt *bp = netdev_priv(dev); 4685 int rc; 4686 4687 rc = bnxt_mod_eeprom_by_page_precheck(bp, page_data, extack); 4688 if (rc) 4689 return rc; 4690 4691 rc = bnxt_read_sfp_module_eeprom_info(bp, page_data->i2c_address << 1, 4692 page_data->page, page_data->bank, 4693 page_data->offset, 4694 page_data->length, 4695 page_data->data); 4696 if (rc) { 4697 NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom read failed"); 4698 return rc; 4699 } 4700 return page_data->length; 4701 } 4702 4703 static int bnxt_write_sfp_module_eeprom_info(struct bnxt *bp, 4704 const struct ethtool_module_eeprom *page) 4705 { 4706 struct hwrm_port_phy_i2c_write_input *req; 4707 int bytes_written = 0; 4708 int rc; 4709 4710 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_WRITE); 4711 if (rc) 4712 return rc; 4713 4714 hwrm_req_hold(bp, req); 4715 req->i2c_slave_addr = page->i2c_address << 1; 4716 req->page_number = cpu_to_le16(page->page); 4717 req->bank_number = page->bank; 4718 req->port_id = cpu_to_le16(bp->pf.port_id); 4719 req->enables = cpu_to_le32(PORT_PHY_I2C_WRITE_REQ_ENABLES_PAGE_OFFSET | 4720 PORT_PHY_I2C_WRITE_REQ_ENABLES_BANK_NUMBER); 4721 4722 while (bytes_written < page->length) { 4723 u16 xfer_size; 4724 4725 xfer_size = min_t(u16, page->length - bytes_written, 4726 BNXT_MAX_PHY_I2C_RESP_SIZE); 4727 req->page_offset = cpu_to_le16(page->offset + bytes_written); 4728 req->data_length = xfer_size; 4729 memcpy(req->data, page->data + bytes_written, xfer_size); 4730 rc = hwrm_req_send(bp, req); 4731 if (rc) 4732 break; 4733 bytes_written += xfer_size; 4734 } 4735 4736 hwrm_req_drop(bp, req); 4737 return rc; 4738 } 4739 4740 static int bnxt_set_module_eeprom_by_page(struct net_device *dev, 4741 const struct ethtool_module_eeprom *page_data, 4742 struct netlink_ext_ack *extack) 4743 { 4744 struct bnxt *bp = netdev_priv(dev); 4745 int rc; 4746 4747 rc = bnxt_mod_eeprom_by_page_precheck(bp, page_data, extack); 4748 if (rc) 4749 return rc; 4750 4751 rc = bnxt_write_sfp_module_eeprom_info(bp, page_data); 4752 if (rc) { 4753 NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom write failed"); 4754 return rc; 4755 } 4756 return page_data->length; 4757 } 4758 4759 static int bnxt_nway_reset(struct net_device *dev) 4760 { 4761 int rc = 0; 4762 4763 struct bnxt *bp = netdev_priv(dev); 4764 struct bnxt_link_info *link_info = &bp->link_info; 4765 4766 if (!BNXT_PHY_CFG_ABLE(bp)) 4767 return -EOPNOTSUPP; 4768 4769 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 4770 return -EINVAL; 4771 4772 if (netif_running(dev)) 4773 rc = bnxt_hwrm_set_link_setting(bp, true, false); 4774 4775 return rc; 4776 } 4777 4778 static int bnxt_set_phys_id(struct net_device *dev, 4779 enum ethtool_phys_id_state state) 4780 { 4781 struct hwrm_port_led_cfg_input *req; 4782 struct bnxt *bp = netdev_priv(dev); 4783 struct bnxt_pf_info *pf = &bp->pf; 4784 struct bnxt_led_cfg *led_cfg; 4785 u8 led_state; 4786 __le16 duration; 4787 int rc, i; 4788 4789 if (!bp->num_leds || BNXT_VF(bp)) 4790 return -EOPNOTSUPP; 4791 4792 if (state == ETHTOOL_ID_ACTIVE) { 4793 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 4794 duration = cpu_to_le16(500); 4795 } else if (state == ETHTOOL_ID_INACTIVE) { 4796 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 4797 duration = cpu_to_le16(0); 4798 } else { 4799 return -EINVAL; 4800 } 4801 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG); 4802 if (rc) 4803 return rc; 4804 4805 req->port_id = cpu_to_le16(pf->port_id); 4806 req->num_leds = bp->num_leds; 4807 led_cfg = (struct bnxt_led_cfg *)&req->led0_id; 4808 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 4809 req->enables |= BNXT_LED_DFLT_ENABLES(i); 4810 led_cfg->led_id = bp->leds[i].led_id; 4811 led_cfg->led_state = led_state; 4812 led_cfg->led_blink_on = duration; 4813 led_cfg->led_blink_off = duration; 4814 led_cfg->led_group_id = bp->leds[i].led_group_id; 4815 } 4816 return hwrm_req_send(bp, req); 4817 } 4818 4819 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 4820 { 4821 struct hwrm_selftest_irq_input *req; 4822 int rc; 4823 4824 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ); 4825 if (rc) 4826 return rc; 4827 4828 req->cmpl_ring = cpu_to_le16(cmpl_ring); 4829 return hwrm_req_send(bp, req); 4830 } 4831 4832 static int bnxt_test_irq(struct bnxt *bp) 4833 { 4834 int i; 4835 4836 for (i = 0; i < bp->cp_nr_rings; i++) { 4837 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 4838 int rc; 4839 4840 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 4841 if (rc) 4842 return rc; 4843 } 4844 return 0; 4845 } 4846 4847 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 4848 { 4849 struct hwrm_port_mac_cfg_input *req; 4850 int rc; 4851 4852 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 4853 if (rc) 4854 return rc; 4855 4856 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 4857 if (enable) 4858 req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 4859 else 4860 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 4861 return hwrm_req_send(bp, req); 4862 } 4863 4864 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 4865 { 4866 struct hwrm_port_phy_qcaps_output *resp; 4867 struct hwrm_port_phy_qcaps_input *req; 4868 int rc; 4869 4870 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS); 4871 if (rc) 4872 return rc; 4873 4874 resp = hwrm_req_hold(bp, req); 4875 rc = hwrm_req_send(bp, req); 4876 if (!rc) 4877 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 4878 4879 hwrm_req_drop(bp, req); 4880 return rc; 4881 } 4882 4883 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 4884 struct hwrm_port_phy_cfg_input *req) 4885 { 4886 struct bnxt_link_info *link_info = &bp->link_info; 4887 u16 fw_advertising; 4888 u16 fw_speed; 4889 int rc; 4890 4891 if (!link_info->autoneg || 4892 (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK)) 4893 return 0; 4894 4895 rc = bnxt_query_force_speeds(bp, &fw_advertising); 4896 if (rc) 4897 return rc; 4898 4899 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 4900 if (BNXT_LINK_IS_UP(bp)) 4901 fw_speed = bp->link_info.link_speed; 4902 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 4903 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 4904 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 4905 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 4906 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 4907 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 4908 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 4909 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 4910 4911 req->force_link_speed = cpu_to_le16(fw_speed); 4912 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 4913 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 4914 rc = hwrm_req_send(bp, req); 4915 req->flags = 0; 4916 req->force_link_speed = cpu_to_le16(0); 4917 return rc; 4918 } 4919 4920 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 4921 { 4922 struct hwrm_port_phy_cfg_input *req; 4923 int rc; 4924 4925 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 4926 if (rc) 4927 return rc; 4928 4929 /* prevent bnxt_disable_an_for_lpbk() from consuming the request */ 4930 hwrm_req_hold(bp, req); 4931 4932 if (enable) { 4933 bnxt_disable_an_for_lpbk(bp, req); 4934 if (ext) 4935 req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 4936 else 4937 req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 4938 } else { 4939 req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 4940 } 4941 req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 4942 rc = hwrm_req_send(bp, req); 4943 hwrm_req_drop(bp, req); 4944 return rc; 4945 } 4946 4947 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 4948 u32 raw_cons, int pkt_size) 4949 { 4950 struct bnxt_napi *bnapi = cpr->bnapi; 4951 struct bnxt_rx_ring_info *rxr; 4952 struct bnxt_sw_rx_bd *rx_buf; 4953 struct rx_cmp *rxcmp; 4954 u16 cp_cons, cons; 4955 u8 *data; 4956 u32 len; 4957 int i; 4958 4959 rxr = bnapi->rx_ring; 4960 cp_cons = RING_CMP(raw_cons); 4961 rxcmp = (struct rx_cmp *) 4962 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 4963 cons = rxcmp->rx_cmp_opaque; 4964 rx_buf = &rxr->rx_buf_ring[cons]; 4965 data = rx_buf->data_ptr; 4966 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 4967 if (len != pkt_size) 4968 return -EIO; 4969 i = ETH_ALEN; 4970 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 4971 return -EIO; 4972 i += ETH_ALEN; 4973 for ( ; i < pkt_size; i++) { 4974 if (data[i] != (u8)(i & 0xff)) 4975 return -EIO; 4976 } 4977 return 0; 4978 } 4979 4980 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 4981 int pkt_size) 4982 { 4983 struct tx_cmp *txcmp; 4984 int rc = -EIO; 4985 u32 raw_cons; 4986 u32 cons; 4987 int i; 4988 4989 raw_cons = cpr->cp_raw_cons; 4990 for (i = 0; i < 200; i++) { 4991 cons = RING_CMP(raw_cons); 4992 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 4993 4994 if (!TX_CMP_VALID(txcmp, raw_cons)) { 4995 udelay(5); 4996 continue; 4997 } 4998 4999 /* The valid test of the entry must be done first before 5000 * reading any further. 5001 */ 5002 dma_rmb(); 5003 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP || 5004 TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_V3_CMP) { 5005 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 5006 raw_cons = NEXT_RAW_CMP(raw_cons); 5007 raw_cons = NEXT_RAW_CMP(raw_cons); 5008 break; 5009 } 5010 raw_cons = NEXT_RAW_CMP(raw_cons); 5011 } 5012 cpr->cp_raw_cons = raw_cons; 5013 return rc; 5014 } 5015 5016 static int bnxt_run_loopback(struct bnxt *bp) 5017 { 5018 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 5019 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 5020 struct bnxt_cp_ring_info *cpr; 5021 int pkt_size, i = 0; 5022 struct sk_buff *skb; 5023 dma_addr_t map; 5024 u8 *data; 5025 int rc; 5026 5027 cpr = &rxr->bnapi->cp_ring; 5028 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) 5029 cpr = rxr->rx_cpr; 5030 pkt_size = min(bp->dev->mtu + ETH_HLEN, max(BNXT_DEFAULT_RX_COPYBREAK, 5031 bp->rx_copybreak)); 5032 skb = netdev_alloc_skb(bp->dev, pkt_size); 5033 if (!skb) 5034 return -ENOMEM; 5035 data = skb_put(skb, pkt_size); 5036 ether_addr_copy(&data[i], bp->dev->dev_addr); 5037 i += ETH_ALEN; 5038 ether_addr_copy(&data[i], bp->dev->dev_addr); 5039 i += ETH_ALEN; 5040 for ( ; i < pkt_size; i++) 5041 data[i] = (u8)(i & 0xff); 5042 5043 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 5044 DMA_TO_DEVICE); 5045 if (dma_mapping_error(&bp->pdev->dev, map)) { 5046 dev_kfree_skb(skb); 5047 return -EIO; 5048 } 5049 bnxt_xmit_bd(bp, txr, map, pkt_size, NULL); 5050 5051 /* Sync BD data before updating doorbell */ 5052 wmb(); 5053 5054 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 5055 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 5056 5057 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE); 5058 dev_kfree_skb(skb); 5059 return rc; 5060 } 5061 5062 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 5063 { 5064 struct hwrm_selftest_exec_output *resp; 5065 struct hwrm_selftest_exec_input *req; 5066 int rc; 5067 5068 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC); 5069 if (rc) 5070 return rc; 5071 5072 hwrm_req_timeout(bp, req, bp->test_info->timeout); 5073 req->flags = test_mask; 5074 5075 resp = hwrm_req_hold(bp, req); 5076 rc = hwrm_req_send(bp, req); 5077 *test_results = resp->test_success; 5078 hwrm_req_drop(bp, req); 5079 return rc; 5080 } 5081 5082 #define BNXT_DRV_TESTS 4 5083 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 5084 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 5085 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 5086 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 5087 5088 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 5089 u64 *buf) 5090 { 5091 struct bnxt *bp = netdev_priv(dev); 5092 bool do_ext_lpbk = false; 5093 bool offline = false; 5094 u8 test_results = 0; 5095 u8 test_mask = 0; 5096 int rc = 0, i; 5097 5098 if (!bp->num_tests || !BNXT_PF(bp)) 5099 return; 5100 5101 memset(buf, 0, sizeof(u64) * bp->num_tests); 5102 if (etest->flags & ETH_TEST_FL_OFFLINE && 5103 bnxt_ulp_registered(bp->edev)) { 5104 etest->flags |= ETH_TEST_FL_FAILED; 5105 netdev_warn(dev, "Offline tests cannot be run with RoCE driver loaded\n"); 5106 return; 5107 } 5108 5109 if (!netif_running(dev)) { 5110 etest->flags |= ETH_TEST_FL_FAILED; 5111 return; 5112 } 5113 5114 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 5115 (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK)) 5116 do_ext_lpbk = true; 5117 5118 if (etest->flags & ETH_TEST_FL_OFFLINE) { 5119 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) { 5120 etest->flags |= ETH_TEST_FL_FAILED; 5121 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n"); 5122 return; 5123 } 5124 offline = true; 5125 } 5126 5127 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 5128 u8 bit_val = 1 << i; 5129 5130 if (!(bp->test_info->offline_mask & bit_val)) 5131 test_mask |= bit_val; 5132 else if (offline) 5133 test_mask |= bit_val; 5134 } 5135 if (!offline) { 5136 bnxt_run_fw_tests(bp, test_mask, &test_results); 5137 } else { 5138 bnxt_close_nic(bp, true, false); 5139 bnxt_run_fw_tests(bp, test_mask, &test_results); 5140 5141 rc = bnxt_half_open_nic(bp); 5142 if (rc) { 5143 etest->flags |= ETH_TEST_FL_FAILED; 5144 return; 5145 } 5146 buf[BNXT_MACLPBK_TEST_IDX] = 1; 5147 if (bp->mac_flags & BNXT_MAC_FL_NO_MAC_LPBK) 5148 goto skip_mac_loopback; 5149 5150 bnxt_hwrm_mac_loopback(bp, true); 5151 msleep(250); 5152 if (bnxt_run_loopback(bp)) 5153 etest->flags |= ETH_TEST_FL_FAILED; 5154 else 5155 buf[BNXT_MACLPBK_TEST_IDX] = 0; 5156 5157 bnxt_hwrm_mac_loopback(bp, false); 5158 skip_mac_loopback: 5159 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 5160 if (bp->phy_flags & BNXT_PHY_FL_NO_PHY_LPBK) 5161 goto skip_phy_loopback; 5162 5163 bnxt_hwrm_phy_loopback(bp, true, false); 5164 msleep(1000); 5165 if (bnxt_run_loopback(bp)) 5166 etest->flags |= ETH_TEST_FL_FAILED; 5167 else 5168 buf[BNXT_PHYLPBK_TEST_IDX] = 0; 5169 skip_phy_loopback: 5170 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 5171 if (do_ext_lpbk) { 5172 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 5173 bnxt_hwrm_phy_loopback(bp, true, true); 5174 msleep(1000); 5175 if (bnxt_run_loopback(bp)) 5176 etest->flags |= ETH_TEST_FL_FAILED; 5177 else 5178 buf[BNXT_EXTLPBK_TEST_IDX] = 0; 5179 } 5180 bnxt_hwrm_phy_loopback(bp, false, false); 5181 bnxt_half_close_nic(bp); 5182 rc = bnxt_open_nic(bp, true, true); 5183 } 5184 if (rc || bnxt_test_irq(bp)) { 5185 buf[BNXT_IRQ_TEST_IDX] = 1; 5186 etest->flags |= ETH_TEST_FL_FAILED; 5187 } 5188 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 5189 u8 bit_val = 1 << i; 5190 5191 if ((test_mask & bit_val) && !(test_results & bit_val)) { 5192 buf[i] = 1; 5193 etest->flags |= ETH_TEST_FL_FAILED; 5194 } 5195 } 5196 } 5197 5198 static int bnxt_reset(struct net_device *dev, u32 *flags) 5199 { 5200 struct bnxt *bp = netdev_priv(dev); 5201 bool reload = false; 5202 u32 req = *flags; 5203 5204 if (!req) 5205 return -EINVAL; 5206 5207 if (!BNXT_PF(bp)) { 5208 netdev_err(dev, "Reset is not supported from a VF\n"); 5209 return -EOPNOTSUPP; 5210 } 5211 5212 if (pci_vfs_assigned(bp->pdev) && 5213 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) { 5214 netdev_err(dev, 5215 "Reset not allowed when VFs are assigned to VMs\n"); 5216 return -EBUSY; 5217 } 5218 5219 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) { 5220 /* This feature is not supported in older firmware versions */ 5221 if (bp->hwrm_spec_code >= 0x10803) { 5222 if (!bnxt_firmware_reset_chip(dev)) { 5223 netdev_info(dev, "Firmware reset request successful.\n"); 5224 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) 5225 reload = true; 5226 *flags &= ~BNXT_FW_RESET_CHIP; 5227 } 5228 } else if (req == BNXT_FW_RESET_CHIP) { 5229 return -EOPNOTSUPP; /* only request, fail hard */ 5230 } 5231 } 5232 5233 if (!BNXT_CHIP_P4_PLUS(bp) && (req & BNXT_FW_RESET_AP)) { 5234 /* This feature is not supported in older firmware versions */ 5235 if (bp->hwrm_spec_code >= 0x10803) { 5236 if (!bnxt_firmware_reset_ap(dev)) { 5237 netdev_info(dev, "Reset application processor successful.\n"); 5238 reload = true; 5239 *flags &= ~BNXT_FW_RESET_AP; 5240 } 5241 } else if (req == BNXT_FW_RESET_AP) { 5242 return -EOPNOTSUPP; /* only request, fail hard */ 5243 } 5244 } 5245 5246 if (reload) 5247 netdev_info(dev, "Reload driver to complete reset\n"); 5248 5249 return 0; 5250 } 5251 5252 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump) 5253 { 5254 struct bnxt *bp = netdev_priv(dev); 5255 5256 if (dump->flag > BNXT_DUMP_LIVE_WITH_CTX_L1_CACHE) { 5257 netdev_info(dev, 5258 "Supports only Live(0), Crash(1), Driver(2), Live with cached context(3) dumps.\n"); 5259 return -EINVAL; 5260 } 5261 5262 if (dump->flag == BNXT_DUMP_CRASH) { 5263 if (bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR && 5264 (!IS_ENABLED(CONFIG_TEE_BNXT_FW))) { 5265 netdev_info(dev, 5266 "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n"); 5267 return -EOPNOTSUPP; 5268 } else if (!(bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR)) { 5269 netdev_info(dev, "Crash dump collection from host memory is not supported on this interface.\n"); 5270 return -EOPNOTSUPP; 5271 } 5272 } 5273 5274 bp->dump_flag = dump->flag; 5275 return 0; 5276 } 5277 5278 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 5279 { 5280 struct bnxt *bp = netdev_priv(dev); 5281 5282 if (bp->hwrm_spec_code < 0x10801) 5283 return -EOPNOTSUPP; 5284 5285 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 5286 bp->ver_resp.hwrm_fw_min_8b << 16 | 5287 bp->ver_resp.hwrm_fw_bld_8b << 8 | 5288 bp->ver_resp.hwrm_fw_rsvd_8b; 5289 5290 dump->flag = bp->dump_flag; 5291 dump->len = bnxt_get_coredump_length(bp, bp->dump_flag); 5292 return 0; 5293 } 5294 5295 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 5296 void *buf) 5297 { 5298 struct bnxt *bp = netdev_priv(dev); 5299 5300 if (bp->hwrm_spec_code < 0x10801) 5301 return -EOPNOTSUPP; 5302 5303 memset(buf, 0, dump->len); 5304 5305 dump->flag = bp->dump_flag; 5306 return bnxt_get_coredump(bp, dump->flag, buf, &dump->len); 5307 } 5308 5309 static int bnxt_get_ts_info(struct net_device *dev, 5310 struct kernel_ethtool_ts_info *info) 5311 { 5312 struct bnxt *bp = netdev_priv(dev); 5313 struct bnxt_ptp_cfg *ptp; 5314 5315 ptp = bp->ptp_cfg; 5316 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE; 5317 5318 if (!ptp) 5319 return 0; 5320 5321 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | 5322 SOF_TIMESTAMPING_RX_HARDWARE | 5323 SOF_TIMESTAMPING_RAW_HARDWARE; 5324 if (ptp->ptp_clock) 5325 info->phc_index = ptp_clock_index(ptp->ptp_clock); 5326 5327 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 5328 5329 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 5330 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 5331 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 5332 5333 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) 5334 info->rx_filters |= (1 << HWTSTAMP_FILTER_ALL); 5335 return 0; 5336 } 5337 5338 static void bnxt_hwrm_pcie_qstats(struct bnxt *bp) 5339 { 5340 struct hwrm_pcie_qstats_output *resp; 5341 struct hwrm_pcie_qstats_input *req; 5342 5343 bp->pcie_stat_len = 0; 5344 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 5345 return; 5346 5347 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS)) 5348 return; 5349 5350 resp = hwrm_req_hold(bp, req); 5351 if (__bnxt_hwrm_pcie_qstats(bp, req)) 5352 bp->pcie_stat_len = min_t(u16, 5353 le16_to_cpu(resp->pcie_stat_size), 5354 sizeof(struct pcie_ctx_hw_stats_v2)); 5355 hwrm_req_drop(bp, req); 5356 } 5357 5358 void bnxt_ethtool_init(struct bnxt *bp) 5359 { 5360 struct hwrm_selftest_qlist_output *resp; 5361 struct hwrm_selftest_qlist_input *req; 5362 struct bnxt_test_info *test_info; 5363 struct net_device *dev = bp->dev; 5364 int i, rc; 5365 5366 bnxt_hwrm_pcie_qstats(bp); 5367 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 5368 bnxt_get_pkgver(dev); 5369 5370 bp->num_tests = 0; 5371 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp)) 5372 return; 5373 5374 test_info = bp->test_info; 5375 if (!test_info) { 5376 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL); 5377 if (!test_info) 5378 return; 5379 bp->test_info = test_info; 5380 } 5381 5382 if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST)) 5383 return; 5384 5385 resp = hwrm_req_hold(bp, req); 5386 rc = hwrm_req_send_silent(bp, req); 5387 if (rc) 5388 goto ethtool_init_exit; 5389 5390 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 5391 if (bp->num_tests > BNXT_MAX_TEST) 5392 bp->num_tests = BNXT_MAX_TEST; 5393 5394 test_info->offline_mask = resp->offline_tests; 5395 test_info->timeout = le16_to_cpu(resp->test_timeout); 5396 if (!test_info->timeout) 5397 test_info->timeout = HWRM_CMD_TIMEOUT; 5398 for (i = 0; i < bp->num_tests; i++) { 5399 char *str = test_info->string[i]; 5400 char *fw_str = resp->test_name[i]; 5401 5402 if (i == BNXT_MACLPBK_TEST_IDX) { 5403 strcpy(str, "Mac loopback test (offline)"); 5404 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 5405 strcpy(str, "Phy loopback test (offline)"); 5406 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 5407 strcpy(str, "Ext loopback test (offline)"); 5408 } else if (i == BNXT_IRQ_TEST_IDX) { 5409 strcpy(str, "Interrupt_test (offline)"); 5410 } else { 5411 snprintf(str, ETH_GSTRING_LEN, "%s test (%s)", 5412 fw_str, test_info->offline_mask & (1 << i) ? 5413 "offline" : "online"); 5414 } 5415 } 5416 5417 ethtool_init_exit: 5418 hwrm_req_drop(bp, req); 5419 } 5420 5421 static void bnxt_get_eth_phy_stats(struct net_device *dev, 5422 struct ethtool_eth_phy_stats *phy_stats) 5423 { 5424 struct bnxt *bp = netdev_priv(dev); 5425 u64 *rx; 5426 5427 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 5428 return; 5429 5430 rx = bp->rx_port_stats_ext.sw_stats; 5431 phy_stats->SymbolErrorDuringCarrier = 5432 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err)); 5433 } 5434 5435 static void bnxt_get_eth_mac_stats(struct net_device *dev, 5436 struct ethtool_eth_mac_stats *mac_stats) 5437 { 5438 struct bnxt *bp = netdev_priv(dev); 5439 u64 *rx, *tx; 5440 5441 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5442 return; 5443 5444 rx = bp->port_stats.sw_stats; 5445 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 5446 5447 mac_stats->FramesReceivedOK = 5448 BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames); 5449 mac_stats->FramesTransmittedOK = 5450 BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames); 5451 mac_stats->FrameCheckSequenceErrors = 5452 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames); 5453 mac_stats->AlignmentErrors = 5454 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames); 5455 mac_stats->OutOfRangeLengthField = 5456 BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames); 5457 } 5458 5459 static void bnxt_get_eth_ctrl_stats(struct net_device *dev, 5460 struct ethtool_eth_ctrl_stats *ctrl_stats) 5461 { 5462 struct bnxt *bp = netdev_priv(dev); 5463 u64 *rx; 5464 5465 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5466 return; 5467 5468 rx = bp->port_stats.sw_stats; 5469 ctrl_stats->MACControlFramesReceived = 5470 BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames); 5471 } 5472 5473 static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = { 5474 { 0, 64 }, 5475 { 65, 127 }, 5476 { 128, 255 }, 5477 { 256, 511 }, 5478 { 512, 1023 }, 5479 { 1024, 1518 }, 5480 { 1519, 2047 }, 5481 { 2048, 4095 }, 5482 { 4096, 9216 }, 5483 { 9217, 16383 }, 5484 {} 5485 }; 5486 5487 static void bnxt_get_rmon_stats(struct net_device *dev, 5488 struct ethtool_rmon_stats *rmon_stats, 5489 const struct ethtool_rmon_hist_range **ranges) 5490 { 5491 struct bnxt *bp = netdev_priv(dev); 5492 u64 *rx, *tx; 5493 5494 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5495 return; 5496 5497 rx = bp->port_stats.sw_stats; 5498 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 5499 5500 rmon_stats->jabbers = 5501 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames); 5502 rmon_stats->oversize_pkts = 5503 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames); 5504 rmon_stats->undersize_pkts = 5505 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames); 5506 5507 rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames); 5508 rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames); 5509 rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames); 5510 rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames); 5511 rmon_stats->hist[4] = 5512 BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames); 5513 rmon_stats->hist[5] = 5514 BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames); 5515 rmon_stats->hist[6] = 5516 BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames); 5517 rmon_stats->hist[7] = 5518 BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames); 5519 rmon_stats->hist[8] = 5520 BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames); 5521 rmon_stats->hist[9] = 5522 BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames); 5523 5524 rmon_stats->hist_tx[0] = 5525 BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames); 5526 rmon_stats->hist_tx[1] = 5527 BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames); 5528 rmon_stats->hist_tx[2] = 5529 BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames); 5530 rmon_stats->hist_tx[3] = 5531 BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames); 5532 rmon_stats->hist_tx[4] = 5533 BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames); 5534 rmon_stats->hist_tx[5] = 5535 BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames); 5536 rmon_stats->hist_tx[6] = 5537 BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames); 5538 rmon_stats->hist_tx[7] = 5539 BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames); 5540 rmon_stats->hist_tx[8] = 5541 BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames); 5542 rmon_stats->hist_tx[9] = 5543 BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames); 5544 5545 *ranges = bnxt_rmon_ranges; 5546 } 5547 5548 static void bnxt_get_ptp_stats(struct net_device *dev, 5549 struct ethtool_ts_stats *ts_stats) 5550 { 5551 struct bnxt *bp = netdev_priv(dev); 5552 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 5553 5554 if (ptp) { 5555 ts_stats->pkts = ptp->stats.ts_pkts; 5556 ts_stats->lost = ptp->stats.ts_lost; 5557 ts_stats->err = atomic64_read(&ptp->stats.ts_err); 5558 } 5559 } 5560 5561 static void bnxt_get_link_ext_stats(struct net_device *dev, 5562 struct ethtool_link_ext_stats *stats) 5563 { 5564 struct bnxt *bp = netdev_priv(dev); 5565 u64 *rx; 5566 5567 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 5568 return; 5569 5570 rx = bp->rx_port_stats_ext.sw_stats; 5571 stats->link_down_events = 5572 *(rx + BNXT_RX_STATS_EXT_OFFSET(link_down_events)); 5573 } 5574 5575 void bnxt_ethtool_free(struct bnxt *bp) 5576 { 5577 kfree(bp->test_info); 5578 bp->test_info = NULL; 5579 } 5580 5581 const struct ethtool_ops bnxt_ethtool_ops = { 5582 .cap_link_lanes_supported = 1, 5583 .rxfh_per_ctx_key = 1, 5584 .rxfh_max_num_contexts = BNXT_MAX_ETH_RSS_CTX + 1, 5585 .rxfh_indir_space = BNXT_MAX_RSS_TABLE_ENTRIES_P5, 5586 .rxfh_priv_size = sizeof(struct bnxt_rss_ctx), 5587 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 5588 ETHTOOL_COALESCE_MAX_FRAMES | 5589 ETHTOOL_COALESCE_USECS_IRQ | 5590 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 5591 ETHTOOL_COALESCE_STATS_BLOCK_USECS | 5592 ETHTOOL_COALESCE_USE_ADAPTIVE_RX | 5593 ETHTOOL_COALESCE_USE_CQE, 5594 .supported_ring_params = ETHTOOL_RING_USE_TCP_DATA_SPLIT | 5595 ETHTOOL_RING_USE_HDS_THRS, 5596 .get_link_ksettings = bnxt_get_link_ksettings, 5597 .set_link_ksettings = bnxt_set_link_ksettings, 5598 .get_fec_stats = bnxt_get_fec_stats, 5599 .get_fecparam = bnxt_get_fecparam, 5600 .set_fecparam = bnxt_set_fecparam, 5601 .get_pause_stats = bnxt_get_pause_stats, 5602 .get_pauseparam = bnxt_get_pauseparam, 5603 .set_pauseparam = bnxt_set_pauseparam, 5604 .get_drvinfo = bnxt_get_drvinfo, 5605 .get_regs_len = bnxt_get_regs_len, 5606 .get_regs = bnxt_get_regs, 5607 .get_wol = bnxt_get_wol, 5608 .set_wol = bnxt_set_wol, 5609 .get_coalesce = bnxt_get_coalesce, 5610 .set_coalesce = bnxt_set_coalesce, 5611 .get_msglevel = bnxt_get_msglevel, 5612 .set_msglevel = bnxt_set_msglevel, 5613 .get_sset_count = bnxt_get_sset_count, 5614 .get_strings = bnxt_get_strings, 5615 .get_ethtool_stats = bnxt_get_ethtool_stats, 5616 .set_ringparam = bnxt_set_ringparam, 5617 .get_ringparam = bnxt_get_ringparam, 5618 .get_channels = bnxt_get_channels, 5619 .set_channels = bnxt_set_channels, 5620 .get_rxnfc = bnxt_get_rxnfc, 5621 .set_rxnfc = bnxt_set_rxnfc, 5622 .get_rx_ring_count = bnxt_get_rx_ring_count, 5623 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 5624 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 5625 .get_rxfh = bnxt_get_rxfh, 5626 .set_rxfh = bnxt_set_rxfh, 5627 .get_rxfh_fields = bnxt_get_rxfh_fields, 5628 .set_rxfh_fields = bnxt_set_rxfh_fields, 5629 .create_rxfh_context = bnxt_create_rxfh_context, 5630 .modify_rxfh_context = bnxt_modify_rxfh_context, 5631 .remove_rxfh_context = bnxt_remove_rxfh_context, 5632 .flash_device = bnxt_flash_device, 5633 .get_eeprom_len = bnxt_get_eeprom_len, 5634 .get_eeprom = bnxt_get_eeprom, 5635 .set_eeprom = bnxt_set_eeprom, 5636 .get_link = bnxt_get_link, 5637 .get_link_ext_stats = bnxt_get_link_ext_stats, 5638 .get_eee = bnxt_get_eee, 5639 .set_eee = bnxt_set_eee, 5640 .get_tunable = bnxt_get_tunable, 5641 .set_tunable = bnxt_set_tunable, 5642 .get_module_info = bnxt_get_module_info, 5643 .get_module_eeprom = bnxt_get_module_eeprom, 5644 .get_module_eeprom_by_page = bnxt_get_module_eeprom_by_page, 5645 .set_module_eeprom_by_page = bnxt_set_module_eeprom_by_page, 5646 .nway_reset = bnxt_nway_reset, 5647 .set_phys_id = bnxt_set_phys_id, 5648 .self_test = bnxt_self_test, 5649 .get_ts_info = bnxt_get_ts_info, 5650 .reset = bnxt_reset, 5651 .set_dump = bnxt_set_dump, 5652 .get_dump_flag = bnxt_get_dump_flag, 5653 .get_dump_data = bnxt_get_dump_data, 5654 .get_eth_phy_stats = bnxt_get_eth_phy_stats, 5655 .get_eth_mac_stats = bnxt_get_eth_mac_stats, 5656 .get_eth_ctrl_stats = bnxt_get_eth_ctrl_stats, 5657 .get_rmon_stats = bnxt_get_rmon_stats, 5658 .get_ts_stats = bnxt_get_ptp_stats, 5659 }; 5660