1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/bitops.h> 12 #include <linux/ctype.h> 13 #include <linux/stringify.h> 14 #include <linux/ethtool.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/linkmode.h> 17 #include <linux/interrupt.h> 18 #include <linux/pci.h> 19 #include <linux/etherdevice.h> 20 #include <linux/crc32.h> 21 #include <linux/firmware.h> 22 #include <linux/utsname.h> 23 #include <linux/time.h> 24 #include <linux/ptp_clock_kernel.h> 25 #include <linux/net_tstamp.h> 26 #include <linux/timecounter.h> 27 #include <net/netlink.h> 28 #include "bnxt_hsi.h" 29 #include "bnxt.h" 30 #include "bnxt_hwrm.h" 31 #include "bnxt_ulp.h" 32 #include "bnxt_xdp.h" 33 #include "bnxt_ptp.h" 34 #include "bnxt_ethtool.h" 35 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 36 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 37 #include "bnxt_coredump.h" 38 39 #define BNXT_NVM_ERR_MSG(dev, extack, msg) \ 40 do { \ 41 if (extack) \ 42 NL_SET_ERR_MSG_MOD(extack, msg); \ 43 netdev_err(dev, "%s\n", msg); \ 44 } while (0) 45 46 static u32 bnxt_get_msglevel(struct net_device *dev) 47 { 48 struct bnxt *bp = netdev_priv(dev); 49 50 return bp->msg_enable; 51 } 52 53 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 54 { 55 struct bnxt *bp = netdev_priv(dev); 56 57 bp->msg_enable = value; 58 } 59 60 static int bnxt_get_coalesce(struct net_device *dev, 61 struct ethtool_coalesce *coal, 62 struct kernel_ethtool_coalesce *kernel_coal, 63 struct netlink_ext_ack *extack) 64 { 65 struct bnxt *bp = netdev_priv(dev); 66 struct bnxt_coal *hw_coal; 67 u16 mult; 68 69 memset(coal, 0, sizeof(*coal)); 70 71 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 72 73 hw_coal = &bp->rx_coal; 74 mult = hw_coal->bufs_per_record; 75 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 76 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 77 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 78 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 79 if (hw_coal->flags & 80 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 81 kernel_coal->use_cqe_mode_rx = true; 82 83 hw_coal = &bp->tx_coal; 84 mult = hw_coal->bufs_per_record; 85 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 86 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 87 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 88 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 89 if (hw_coal->flags & 90 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 91 kernel_coal->use_cqe_mode_tx = true; 92 93 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 94 95 return 0; 96 } 97 98 static int bnxt_set_coalesce(struct net_device *dev, 99 struct ethtool_coalesce *coal, 100 struct kernel_ethtool_coalesce *kernel_coal, 101 struct netlink_ext_ack *extack) 102 { 103 struct bnxt *bp = netdev_priv(dev); 104 bool update_stats = false; 105 struct bnxt_coal *hw_coal; 106 int rc = 0; 107 u16 mult; 108 109 if (coal->use_adaptive_rx_coalesce) { 110 bp->flags |= BNXT_FLAG_DIM; 111 } else { 112 if (bp->flags & BNXT_FLAG_DIM) { 113 bp->flags &= ~(BNXT_FLAG_DIM); 114 goto reset_coalesce; 115 } 116 } 117 118 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) && 119 !(bp->coal_cap.cmpl_params & 120 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)) 121 return -EOPNOTSUPP; 122 123 hw_coal = &bp->rx_coal; 124 mult = hw_coal->bufs_per_record; 125 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 126 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 127 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 128 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 129 hw_coal->flags &= 130 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 131 if (kernel_coal->use_cqe_mode_rx) 132 hw_coal->flags |= 133 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 134 135 hw_coal = &bp->tx_coal; 136 mult = hw_coal->bufs_per_record; 137 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 138 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 139 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 140 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 141 hw_coal->flags &= 142 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 143 if (kernel_coal->use_cqe_mode_tx) 144 hw_coal->flags |= 145 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 146 147 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 148 u32 stats_ticks = coal->stats_block_coalesce_usecs; 149 150 /* Allow 0, which means disable. */ 151 if (stats_ticks) 152 stats_ticks = clamp_t(u32, stats_ticks, 153 BNXT_MIN_STATS_COAL_TICKS, 154 BNXT_MAX_STATS_COAL_TICKS); 155 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 156 bp->stats_coal_ticks = stats_ticks; 157 if (bp->stats_coal_ticks) 158 bp->current_interval = 159 bp->stats_coal_ticks * HZ / 1000000; 160 else 161 bp->current_interval = BNXT_TIMER_INTERVAL; 162 update_stats = true; 163 } 164 165 reset_coalesce: 166 if (test_bit(BNXT_STATE_OPEN, &bp->state)) { 167 if (update_stats) { 168 bnxt_close_nic(bp, true, false); 169 rc = bnxt_open_nic(bp, true, false); 170 } else { 171 rc = bnxt_hwrm_set_coal(bp); 172 } 173 } 174 175 return rc; 176 } 177 178 static const char * const bnxt_ring_rx_stats_str[] = { 179 "rx_ucast_packets", 180 "rx_mcast_packets", 181 "rx_bcast_packets", 182 "rx_discards", 183 "rx_errors", 184 "rx_ucast_bytes", 185 "rx_mcast_bytes", 186 "rx_bcast_bytes", 187 }; 188 189 static const char * const bnxt_ring_tx_stats_str[] = { 190 "tx_ucast_packets", 191 "tx_mcast_packets", 192 "tx_bcast_packets", 193 "tx_errors", 194 "tx_discards", 195 "tx_ucast_bytes", 196 "tx_mcast_bytes", 197 "tx_bcast_bytes", 198 }; 199 200 static const char * const bnxt_ring_tpa_stats_str[] = { 201 "tpa_packets", 202 "tpa_bytes", 203 "tpa_events", 204 "tpa_aborts", 205 }; 206 207 static const char * const bnxt_ring_tpa2_stats_str[] = { 208 "rx_tpa_eligible_pkt", 209 "rx_tpa_eligible_bytes", 210 "rx_tpa_pkt", 211 "rx_tpa_bytes", 212 "rx_tpa_errors", 213 "rx_tpa_events", 214 }; 215 216 static const char * const bnxt_rx_sw_stats_str[] = { 217 "rx_l4_csum_errors", 218 "rx_resets", 219 "rx_buf_errors", 220 }; 221 222 static const char * const bnxt_cmn_sw_stats_str[] = { 223 "missed_irqs", 224 }; 225 226 #define BNXT_RX_STATS_ENTRY(counter) \ 227 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 228 229 #define BNXT_TX_STATS_ENTRY(counter) \ 230 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 231 232 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 233 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 234 235 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 236 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 237 238 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 239 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 240 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 241 242 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 243 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 244 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 245 246 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 247 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 248 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 249 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 250 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 251 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 252 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 253 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 254 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 255 256 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 257 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 258 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 259 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 260 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 261 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 262 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 263 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 264 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 265 266 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 267 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 268 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 269 270 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 271 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 272 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 273 274 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 275 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 276 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 277 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 278 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 279 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 280 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 281 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 282 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 283 284 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 285 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 286 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 287 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 288 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 289 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 290 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 291 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 292 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 293 294 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 295 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 296 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 297 298 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 299 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 300 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 301 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 302 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 303 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 304 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 305 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 306 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 307 308 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 309 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 310 __stringify(counter##_pri##n) } 311 312 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 313 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 314 __stringify(counter##_pri##n) } 315 316 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 317 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 318 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 319 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 320 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 321 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 322 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 323 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 324 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 325 326 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 327 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 328 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 329 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 330 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 331 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 332 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 333 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 334 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 335 336 enum { 337 RX_TOTAL_DISCARDS, 338 TX_TOTAL_DISCARDS, 339 RX_NETPOLL_DISCARDS, 340 }; 341 342 static const char *const bnxt_ring_err_stats_arr[] = { 343 "rx_total_l4_csum_errors", 344 "rx_total_resets", 345 "rx_total_buf_errors", 346 "rx_total_oom_discards", 347 "rx_total_netpoll_discards", 348 "rx_total_ring_discards", 349 "tx_total_resets", 350 "tx_total_ring_discards", 351 "total_missed_irqs", 352 }; 353 354 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str) 355 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str) 356 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str) 357 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str) 358 359 static const struct { 360 long offset; 361 char string[ETH_GSTRING_LEN]; 362 } bnxt_port_stats_arr[] = { 363 BNXT_RX_STATS_ENTRY(rx_64b_frames), 364 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 365 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 366 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 367 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 368 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 369 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 370 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 371 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 372 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 373 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 374 BNXT_RX_STATS_ENTRY(rx_total_frames), 375 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 376 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 377 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 378 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 379 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 380 BNXT_RX_STATS_ENTRY(rx_pause_frames), 381 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 382 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 383 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 384 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 385 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 386 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 387 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 388 BNXT_RX_STATS_ENTRY(rx_good_frames), 389 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 390 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 391 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 392 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 393 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 394 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 395 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 396 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 397 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 398 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 399 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 400 BNXT_RX_STATS_ENTRY(rx_bytes), 401 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 402 BNXT_RX_STATS_ENTRY(rx_runt_frames), 403 BNXT_RX_STATS_ENTRY(rx_stat_discard), 404 BNXT_RX_STATS_ENTRY(rx_stat_err), 405 406 BNXT_TX_STATS_ENTRY(tx_64b_frames), 407 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 408 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 409 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 410 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 411 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 412 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 413 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 414 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 415 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 416 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 417 BNXT_TX_STATS_ENTRY(tx_good_frames), 418 BNXT_TX_STATS_ENTRY(tx_total_frames), 419 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 420 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 421 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 422 BNXT_TX_STATS_ENTRY(tx_pause_frames), 423 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 424 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 425 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 426 BNXT_TX_STATS_ENTRY(tx_err), 427 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 428 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 429 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 430 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 431 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 432 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 433 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 434 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 435 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 436 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 437 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 438 BNXT_TX_STATS_ENTRY(tx_total_collisions), 439 BNXT_TX_STATS_ENTRY(tx_bytes), 440 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 441 BNXT_TX_STATS_ENTRY(tx_stat_discard), 442 BNXT_TX_STATS_ENTRY(tx_stat_error), 443 }; 444 445 static const struct { 446 long offset; 447 char string[ETH_GSTRING_LEN]; 448 } bnxt_port_stats_ext_arr[] = { 449 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 450 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 451 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 452 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 453 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 454 BNXT_RX_STATS_EXT_COS_ENTRIES, 455 BNXT_RX_STATS_EXT_PFC_ENTRIES, 456 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 457 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 458 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 459 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 460 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 461 BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks), 462 BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks), 463 BNXT_RX_STATS_EXT_ENTRY(rx_filter_miss), 464 }; 465 466 static const struct { 467 long offset; 468 char string[ETH_GSTRING_LEN]; 469 } bnxt_tx_port_stats_ext_arr[] = { 470 BNXT_TX_STATS_EXT_COS_ENTRIES, 471 BNXT_TX_STATS_EXT_PFC_ENTRIES, 472 }; 473 474 static const struct { 475 long base_off; 476 char string[ETH_GSTRING_LEN]; 477 } bnxt_rx_bytes_pri_arr[] = { 478 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 479 }; 480 481 static const struct { 482 long base_off; 483 char string[ETH_GSTRING_LEN]; 484 } bnxt_rx_pkts_pri_arr[] = { 485 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 486 }; 487 488 static const struct { 489 long base_off; 490 char string[ETH_GSTRING_LEN]; 491 } bnxt_tx_bytes_pri_arr[] = { 492 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 493 }; 494 495 static const struct { 496 long base_off; 497 char string[ETH_GSTRING_LEN]; 498 } bnxt_tx_pkts_pri_arr[] = { 499 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 500 }; 501 502 #define BNXT_NUM_RING_ERR_STATS ARRAY_SIZE(bnxt_ring_err_stats_arr) 503 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 504 #define BNXT_NUM_STATS_PRI \ 505 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 506 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 507 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 508 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 509 510 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 511 { 512 if (BNXT_SUPPORTS_TPA(bp)) { 513 if (bp->max_tpa_v2) { 514 if (BNXT_CHIP_P5(bp)) 515 return BNXT_NUM_TPA_RING_STATS_P5; 516 return BNXT_NUM_TPA_RING_STATS_P7; 517 } 518 return BNXT_NUM_TPA_RING_STATS; 519 } 520 return 0; 521 } 522 523 static int bnxt_get_num_ring_stats(struct bnxt *bp) 524 { 525 int rx, tx, cmn; 526 527 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS + 528 bnxt_get_num_tpa_ring_stats(bp); 529 tx = NUM_RING_TX_HW_STATS; 530 cmn = NUM_RING_CMN_SW_STATS; 531 return rx * bp->rx_nr_rings + 532 tx * (bp->tx_nr_rings_xdp + bp->tx_nr_rings_per_tc) + 533 cmn * bp->cp_nr_rings; 534 } 535 536 static int bnxt_get_num_stats(struct bnxt *bp) 537 { 538 int num_stats = bnxt_get_num_ring_stats(bp); 539 int len; 540 541 num_stats += BNXT_NUM_RING_ERR_STATS; 542 543 if (bp->flags & BNXT_FLAG_PORT_STATS) 544 num_stats += BNXT_NUM_PORT_STATS; 545 546 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 547 len = min_t(int, bp->fw_rx_stats_ext_size, 548 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 549 num_stats += len; 550 len = min_t(int, bp->fw_tx_stats_ext_size, 551 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 552 num_stats += len; 553 if (bp->pri2cos_valid) 554 num_stats += BNXT_NUM_STATS_PRI; 555 } 556 557 return num_stats; 558 } 559 560 static int bnxt_get_sset_count(struct net_device *dev, int sset) 561 { 562 struct bnxt *bp = netdev_priv(dev); 563 564 switch (sset) { 565 case ETH_SS_STATS: 566 return bnxt_get_num_stats(bp); 567 case ETH_SS_TEST: 568 if (!bp->num_tests) 569 return -EOPNOTSUPP; 570 return bp->num_tests; 571 default: 572 return -EOPNOTSUPP; 573 } 574 } 575 576 static bool is_rx_ring(struct bnxt *bp, int ring_num) 577 { 578 return ring_num < bp->rx_nr_rings; 579 } 580 581 static bool is_tx_ring(struct bnxt *bp, int ring_num) 582 { 583 int tx_base = 0; 584 585 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 586 tx_base = bp->rx_nr_rings; 587 588 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings)) 589 return true; 590 return false; 591 } 592 593 static void bnxt_get_ethtool_stats(struct net_device *dev, 594 struct ethtool_stats *stats, u64 *buf) 595 { 596 struct bnxt_total_ring_err_stats ring_err_stats = {0}; 597 struct bnxt *bp = netdev_priv(dev); 598 u64 *curr, *prev; 599 u32 tpa_stats; 600 u32 i, j = 0; 601 602 if (!bp->bnapi) { 603 j += bnxt_get_num_ring_stats(bp); 604 goto skip_ring_stats; 605 } 606 607 tpa_stats = bnxt_get_num_tpa_ring_stats(bp); 608 for (i = 0; i < bp->cp_nr_rings; i++) { 609 struct bnxt_napi *bnapi = bp->bnapi[i]; 610 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 611 u64 *sw_stats = cpr->stats.sw_stats; 612 u64 *sw; 613 int k; 614 615 if (is_rx_ring(bp, i)) { 616 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++) 617 buf[j] = sw_stats[k]; 618 } 619 if (is_tx_ring(bp, i)) { 620 k = NUM_RING_RX_HW_STATS; 621 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 622 j++, k++) 623 buf[j] = sw_stats[k]; 624 } 625 if (!tpa_stats || !is_rx_ring(bp, i)) 626 goto skip_tpa_ring_stats; 627 628 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 629 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS + 630 tpa_stats; j++, k++) 631 buf[j] = sw_stats[k]; 632 633 skip_tpa_ring_stats: 634 sw = (u64 *)&cpr->sw_stats->rx; 635 if (is_rx_ring(bp, i)) { 636 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++) 637 buf[j] = sw[k]; 638 } 639 640 sw = (u64 *)&cpr->sw_stats->cmn; 641 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++) 642 buf[j] = sw[k]; 643 } 644 645 bnxt_get_ring_err_stats(bp, &ring_err_stats); 646 647 skip_ring_stats: 648 curr = &ring_err_stats.rx_total_l4_csum_errors; 649 prev = &bp->ring_err_stats_prev.rx_total_l4_csum_errors; 650 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++, j++, curr++, prev++) 651 buf[j] = *curr + *prev; 652 653 if (bp->flags & BNXT_FLAG_PORT_STATS) { 654 u64 *port_stats = bp->port_stats.sw_stats; 655 656 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) 657 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset); 658 } 659 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 660 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats; 661 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats; 662 u32 len; 663 664 len = min_t(u32, bp->fw_rx_stats_ext_size, 665 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 666 for (i = 0; i < len; i++, j++) { 667 buf[j] = *(rx_port_stats_ext + 668 bnxt_port_stats_ext_arr[i].offset); 669 } 670 len = min_t(u32, bp->fw_tx_stats_ext_size, 671 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 672 for (i = 0; i < len; i++, j++) { 673 buf[j] = *(tx_port_stats_ext + 674 bnxt_tx_port_stats_ext_arr[i].offset); 675 } 676 if (bp->pri2cos_valid) { 677 for (i = 0; i < 8; i++, j++) { 678 long n = bnxt_rx_bytes_pri_arr[i].base_off + 679 bp->pri2cos_idx[i]; 680 681 buf[j] = *(rx_port_stats_ext + n); 682 } 683 for (i = 0; i < 8; i++, j++) { 684 long n = bnxt_rx_pkts_pri_arr[i].base_off + 685 bp->pri2cos_idx[i]; 686 687 buf[j] = *(rx_port_stats_ext + n); 688 } 689 for (i = 0; i < 8; i++, j++) { 690 long n = bnxt_tx_bytes_pri_arr[i].base_off + 691 bp->pri2cos_idx[i]; 692 693 buf[j] = *(tx_port_stats_ext + n); 694 } 695 for (i = 0; i < 8; i++, j++) { 696 long n = bnxt_tx_pkts_pri_arr[i].base_off + 697 bp->pri2cos_idx[i]; 698 699 buf[j] = *(tx_port_stats_ext + n); 700 } 701 } 702 } 703 } 704 705 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 706 { 707 struct bnxt *bp = netdev_priv(dev); 708 u32 i, j, num_str; 709 const char *str; 710 711 switch (stringset) { 712 case ETH_SS_STATS: 713 for (i = 0; i < bp->cp_nr_rings; i++) { 714 if (is_rx_ring(bp, i)) 715 for (j = 0; j < NUM_RING_RX_HW_STATS; j++) { 716 str = bnxt_ring_rx_stats_str[j]; 717 ethtool_sprintf(&buf, "[%d]: %s", i, 718 str); 719 } 720 if (is_tx_ring(bp, i)) 721 for (j = 0; j < NUM_RING_TX_HW_STATS; j++) { 722 str = bnxt_ring_tx_stats_str[j]; 723 ethtool_sprintf(&buf, "[%d]: %s", i, 724 str); 725 } 726 num_str = bnxt_get_num_tpa_ring_stats(bp); 727 if (!num_str || !is_rx_ring(bp, i)) 728 goto skip_tpa_stats; 729 730 if (bp->max_tpa_v2) 731 for (j = 0; j < num_str; j++) { 732 str = bnxt_ring_tpa2_stats_str[j]; 733 ethtool_sprintf(&buf, "[%d]: %s", i, 734 str); 735 } 736 else 737 for (j = 0; j < num_str; j++) { 738 str = bnxt_ring_tpa_stats_str[j]; 739 ethtool_sprintf(&buf, "[%d]: %s", i, 740 str); 741 } 742 skip_tpa_stats: 743 if (is_rx_ring(bp, i)) 744 for (j = 0; j < NUM_RING_RX_SW_STATS; j++) { 745 str = bnxt_rx_sw_stats_str[j]; 746 ethtool_sprintf(&buf, "[%d]: %s", i, 747 str); 748 } 749 for (j = 0; j < NUM_RING_CMN_SW_STATS; j++) { 750 str = bnxt_cmn_sw_stats_str[j]; 751 ethtool_sprintf(&buf, "[%d]: %s", i, str); 752 } 753 } 754 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++) 755 ethtool_puts(&buf, bnxt_ring_err_stats_arr[i]); 756 757 if (bp->flags & BNXT_FLAG_PORT_STATS) 758 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 759 str = bnxt_port_stats_arr[i].string; 760 ethtool_puts(&buf, str); 761 } 762 763 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 764 u32 len; 765 766 len = min_t(u32, bp->fw_rx_stats_ext_size, 767 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 768 for (i = 0; i < len; i++) { 769 str = bnxt_port_stats_ext_arr[i].string; 770 ethtool_puts(&buf, str); 771 } 772 773 len = min_t(u32, bp->fw_tx_stats_ext_size, 774 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 775 for (i = 0; i < len; i++) { 776 str = bnxt_tx_port_stats_ext_arr[i].string; 777 ethtool_puts(&buf, str); 778 } 779 780 if (bp->pri2cos_valid) { 781 for (i = 0; i < 8; i++) { 782 str = bnxt_rx_bytes_pri_arr[i].string; 783 ethtool_puts(&buf, str); 784 } 785 786 for (i = 0; i < 8; i++) { 787 str = bnxt_rx_pkts_pri_arr[i].string; 788 ethtool_puts(&buf, str); 789 } 790 791 for (i = 0; i < 8; i++) { 792 str = bnxt_tx_bytes_pri_arr[i].string; 793 ethtool_puts(&buf, str); 794 } 795 796 for (i = 0; i < 8; i++) { 797 str = bnxt_tx_pkts_pri_arr[i].string; 798 ethtool_puts(&buf, str); 799 } 800 } 801 } 802 break; 803 case ETH_SS_TEST: 804 if (bp->num_tests) 805 for (i = 0; i < bp->num_tests; i++) 806 ethtool_puts(&buf, bp->test_info->string[i]); 807 break; 808 default: 809 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 810 stringset); 811 break; 812 } 813 } 814 815 static void bnxt_get_ringparam(struct net_device *dev, 816 struct ethtool_ringparam *ering, 817 struct kernel_ethtool_ringparam *kernel_ering, 818 struct netlink_ext_ack *extack) 819 { 820 struct bnxt *bp = netdev_priv(dev); 821 822 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 823 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA; 824 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 825 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_ENABLED; 826 } else { 827 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 828 ering->rx_jumbo_max_pending = 0; 829 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_DISABLED; 830 } 831 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 832 833 ering->rx_pending = bp->rx_ring_size; 834 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 835 ering->tx_pending = bp->tx_ring_size; 836 } 837 838 static int bnxt_set_ringparam(struct net_device *dev, 839 struct ethtool_ringparam *ering, 840 struct kernel_ethtool_ringparam *kernel_ering, 841 struct netlink_ext_ack *extack) 842 { 843 struct bnxt *bp = netdev_priv(dev); 844 845 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 846 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 847 (ering->tx_pending < BNXT_MIN_TX_DESC_CNT)) 848 return -EINVAL; 849 850 if (netif_running(dev)) 851 bnxt_close_nic(bp, false, false); 852 853 bp->rx_ring_size = ering->rx_pending; 854 bp->tx_ring_size = ering->tx_pending; 855 bnxt_set_ring_params(bp); 856 857 if (netif_running(dev)) 858 return bnxt_open_nic(bp, false, false); 859 860 return 0; 861 } 862 863 static void bnxt_get_channels(struct net_device *dev, 864 struct ethtool_channels *channel) 865 { 866 struct bnxt *bp = netdev_priv(dev); 867 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 868 int max_rx_rings, max_tx_rings, tcs; 869 int max_tx_sch_inputs, tx_grps; 870 871 /* Get the most up-to-date max_tx_sch_inputs. */ 872 if (netif_running(dev) && BNXT_NEW_RM(bp)) 873 bnxt_hwrm_func_resc_qcaps(bp, false); 874 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 875 876 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 877 if (max_tx_sch_inputs) 878 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 879 880 tcs = bp->num_tc; 881 tx_grps = max(tcs, 1); 882 if (bp->tx_nr_rings_xdp) 883 tx_grps++; 884 max_tx_rings /= tx_grps; 885 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 886 887 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 888 max_rx_rings = 0; 889 max_tx_rings = 0; 890 } 891 if (max_tx_sch_inputs) 892 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 893 894 if (tcs > 1) 895 max_tx_rings /= tcs; 896 897 channel->max_rx = max_rx_rings; 898 channel->max_tx = max_tx_rings; 899 channel->max_other = 0; 900 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 901 channel->combined_count = bp->rx_nr_rings; 902 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 903 channel->combined_count--; 904 } else { 905 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 906 channel->rx_count = bp->rx_nr_rings; 907 channel->tx_count = bp->tx_nr_rings_per_tc; 908 } 909 } 910 } 911 912 static int bnxt_set_channels(struct net_device *dev, 913 struct ethtool_channels *channel) 914 { 915 struct bnxt *bp = netdev_priv(dev); 916 int req_tx_rings, req_rx_rings, tcs; 917 bool sh = false; 918 int tx_xdp = 0; 919 int rc = 0; 920 int tx_cp; 921 922 if (channel->other_count) 923 return -EINVAL; 924 925 if (!channel->combined_count && 926 (!channel->rx_count || !channel->tx_count)) 927 return -EINVAL; 928 929 if (channel->combined_count && 930 (channel->rx_count || channel->tx_count)) 931 return -EINVAL; 932 933 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 934 channel->tx_count)) 935 return -EINVAL; 936 937 if (channel->combined_count) 938 sh = true; 939 940 tcs = bp->num_tc; 941 942 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 943 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 944 if (bp->tx_nr_rings_xdp) { 945 if (!sh) { 946 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 947 return -EINVAL; 948 } 949 tx_xdp = req_rx_rings; 950 } 951 952 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) != 953 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) && 954 netif_is_rxfh_configured(dev)) { 955 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n"); 956 return -EINVAL; 957 } 958 959 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 960 if (rc) { 961 netdev_warn(dev, "Unable to allocate the requested rings\n"); 962 return rc; 963 } 964 965 if (netif_running(dev)) { 966 if (BNXT_PF(bp)) { 967 /* TODO CHIMP_FW: Send message to all VF's 968 * before PF unload 969 */ 970 } 971 bnxt_close_nic(bp, true, false); 972 } 973 974 if (sh) { 975 bp->flags |= BNXT_FLAG_SHARED_RINGS; 976 bp->rx_nr_rings = channel->combined_count; 977 bp->tx_nr_rings_per_tc = channel->combined_count; 978 } else { 979 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 980 bp->rx_nr_rings = channel->rx_count; 981 bp->tx_nr_rings_per_tc = channel->tx_count; 982 } 983 bp->tx_nr_rings_xdp = tx_xdp; 984 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 985 if (tcs > 1) 986 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 987 988 tx_cp = bnxt_num_tx_to_cp(bp, bp->tx_nr_rings); 989 bp->cp_nr_rings = sh ? max_t(int, tx_cp, bp->rx_nr_rings) : 990 tx_cp + bp->rx_nr_rings; 991 992 /* After changing number of rx channels, update NTUPLE feature. */ 993 netdev_update_features(dev); 994 if (netif_running(dev)) { 995 rc = bnxt_open_nic(bp, true, false); 996 if ((!rc) && BNXT_PF(bp)) { 997 /* TODO CHIMP_FW: Send message to all VF's 998 * to renable 999 */ 1000 } 1001 } else { 1002 rc = bnxt_reserve_rings(bp, true); 1003 } 1004 1005 return rc; 1006 } 1007 1008 static u32 bnxt_get_all_fltr_ids_rcu(struct bnxt *bp, struct hlist_head tbl[], 1009 int tbl_size, u32 *ids, u32 start, 1010 u32 id_cnt) 1011 { 1012 int i, j = start; 1013 1014 if (j >= id_cnt) 1015 return j; 1016 for (i = 0; i < tbl_size; i++) { 1017 struct hlist_head *head; 1018 struct bnxt_filter_base *fltr; 1019 1020 head = &tbl[i]; 1021 hlist_for_each_entry_rcu(fltr, head, hash) { 1022 if (!fltr->flags || 1023 test_bit(BNXT_FLTR_FW_DELETED, &fltr->state)) 1024 continue; 1025 ids[j++] = fltr->sw_id; 1026 if (j == id_cnt) 1027 return j; 1028 } 1029 } 1030 return j; 1031 } 1032 1033 static struct bnxt_filter_base *bnxt_get_one_fltr_rcu(struct bnxt *bp, 1034 struct hlist_head tbl[], 1035 int tbl_size, u32 id) 1036 { 1037 int i; 1038 1039 for (i = 0; i < tbl_size; i++) { 1040 struct hlist_head *head; 1041 struct bnxt_filter_base *fltr; 1042 1043 head = &tbl[i]; 1044 hlist_for_each_entry_rcu(fltr, head, hash) { 1045 if (fltr->flags && fltr->sw_id == id) 1046 return fltr; 1047 } 1048 } 1049 return NULL; 1050 } 1051 1052 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 1053 u32 *rule_locs) 1054 { 1055 u32 count; 1056 1057 cmd->data = bp->ntp_fltr_count; 1058 rcu_read_lock(); 1059 count = bnxt_get_all_fltr_ids_rcu(bp, bp->l2_fltr_hash_tbl, 1060 BNXT_L2_FLTR_HASH_SIZE, rule_locs, 0, 1061 cmd->rule_cnt); 1062 cmd->rule_cnt = bnxt_get_all_fltr_ids_rcu(bp, bp->ntp_fltr_hash_tbl, 1063 BNXT_NTP_FLTR_HASH_SIZE, 1064 rule_locs, count, 1065 cmd->rule_cnt); 1066 rcu_read_unlock(); 1067 1068 return 0; 1069 } 1070 1071 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1072 { 1073 struct ethtool_rx_flow_spec *fs = 1074 (struct ethtool_rx_flow_spec *)&cmd->fs; 1075 struct bnxt_filter_base *fltr_base; 1076 struct bnxt_ntuple_filter *fltr; 1077 struct bnxt_flow_masks *fmasks; 1078 struct flow_keys *fkeys; 1079 int rc = -EINVAL; 1080 1081 if (fs->location >= bp->max_fltr) 1082 return rc; 1083 1084 rcu_read_lock(); 1085 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl, 1086 BNXT_L2_FLTR_HASH_SIZE, 1087 fs->location); 1088 if (fltr_base) { 1089 struct ethhdr *h_ether = &fs->h_u.ether_spec; 1090 struct ethhdr *m_ether = &fs->m_u.ether_spec; 1091 struct bnxt_l2_filter *l2_fltr; 1092 struct bnxt_l2_key *l2_key; 1093 1094 l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base); 1095 l2_key = &l2_fltr->l2_key; 1096 fs->flow_type = ETHER_FLOW; 1097 ether_addr_copy(h_ether->h_dest, l2_key->dst_mac_addr); 1098 eth_broadcast_addr(m_ether->h_dest); 1099 if (l2_key->vlan) { 1100 struct ethtool_flow_ext *m_ext = &fs->m_ext; 1101 struct ethtool_flow_ext *h_ext = &fs->h_ext; 1102 1103 fs->flow_type |= FLOW_EXT; 1104 m_ext->vlan_tci = htons(0xfff); 1105 h_ext->vlan_tci = htons(l2_key->vlan); 1106 } 1107 if (fltr_base->flags & BNXT_ACT_RING_DST) 1108 fs->ring_cookie = fltr_base->rxq; 1109 if (fltr_base->flags & BNXT_ACT_FUNC_DST) 1110 fs->ring_cookie = (u64)(fltr_base->vf_idx + 1) << 1111 ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 1112 rcu_read_unlock(); 1113 return 0; 1114 } 1115 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl, 1116 BNXT_NTP_FLTR_HASH_SIZE, 1117 fs->location); 1118 if (!fltr_base) { 1119 rcu_read_unlock(); 1120 return rc; 1121 } 1122 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base); 1123 1124 fkeys = &fltr->fkeys; 1125 fmasks = &fltr->fmasks; 1126 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 1127 if (fkeys->basic.ip_proto == BNXT_IP_PROTO_WILDCARD) { 1128 fs->flow_type = IP_USER_FLOW; 1129 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 1130 fs->h_u.usr_ip4_spec.proto = BNXT_IP_PROTO_WILDCARD; 1131 fs->m_u.usr_ip4_spec.proto = 0; 1132 } else if (fkeys->basic.ip_proto == IPPROTO_ICMP) { 1133 fs->flow_type = IP_USER_FLOW; 1134 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 1135 fs->h_u.usr_ip4_spec.proto = IPPROTO_ICMP; 1136 fs->m_u.usr_ip4_spec.proto = BNXT_IP_PROTO_FULL_MASK; 1137 } else if (fkeys->basic.ip_proto == IPPROTO_TCP) { 1138 fs->flow_type = TCP_V4_FLOW; 1139 } else if (fkeys->basic.ip_proto == IPPROTO_UDP) { 1140 fs->flow_type = UDP_V4_FLOW; 1141 } else { 1142 goto fltr_err; 1143 } 1144 1145 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 1146 fs->m_u.tcp_ip4_spec.ip4src = fmasks->addrs.v4addrs.src; 1147 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 1148 fs->m_u.tcp_ip4_spec.ip4dst = fmasks->addrs.v4addrs.dst; 1149 if (fs->flow_type == TCP_V4_FLOW || 1150 fs->flow_type == UDP_V4_FLOW) { 1151 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 1152 fs->m_u.tcp_ip4_spec.psrc = fmasks->ports.src; 1153 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 1154 fs->m_u.tcp_ip4_spec.pdst = fmasks->ports.dst; 1155 } 1156 } else { 1157 if (fkeys->basic.ip_proto == BNXT_IP_PROTO_WILDCARD) { 1158 fs->flow_type = IPV6_USER_FLOW; 1159 fs->h_u.usr_ip6_spec.l4_proto = BNXT_IP_PROTO_WILDCARD; 1160 fs->m_u.usr_ip6_spec.l4_proto = 0; 1161 } else if (fkeys->basic.ip_proto == IPPROTO_ICMPV6) { 1162 fs->flow_type = IPV6_USER_FLOW; 1163 fs->h_u.usr_ip6_spec.l4_proto = IPPROTO_ICMPV6; 1164 fs->m_u.usr_ip6_spec.l4_proto = BNXT_IP_PROTO_FULL_MASK; 1165 } else if (fkeys->basic.ip_proto == IPPROTO_TCP) { 1166 fs->flow_type = TCP_V6_FLOW; 1167 } else if (fkeys->basic.ip_proto == IPPROTO_UDP) { 1168 fs->flow_type = UDP_V6_FLOW; 1169 } else { 1170 goto fltr_err; 1171 } 1172 1173 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 1174 fkeys->addrs.v6addrs.src; 1175 *(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6src[0] = 1176 fmasks->addrs.v6addrs.src; 1177 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 1178 fkeys->addrs.v6addrs.dst; 1179 *(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6dst[0] = 1180 fmasks->addrs.v6addrs.dst; 1181 if (fs->flow_type == TCP_V6_FLOW || 1182 fs->flow_type == UDP_V6_FLOW) { 1183 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 1184 fs->m_u.tcp_ip6_spec.psrc = fmasks->ports.src; 1185 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 1186 fs->m_u.tcp_ip6_spec.pdst = fmasks->ports.dst; 1187 } 1188 } 1189 1190 if (fltr->base.flags & BNXT_ACT_DROP) { 1191 fs->ring_cookie = RX_CLS_FLOW_DISC; 1192 } else if (fltr->base.flags & BNXT_ACT_RSS_CTX) { 1193 fs->flow_type |= FLOW_RSS; 1194 cmd->rss_context = fltr->base.fw_vnic_id; 1195 } else { 1196 fs->ring_cookie = fltr->base.rxq; 1197 } 1198 rc = 0; 1199 1200 fltr_err: 1201 rcu_read_unlock(); 1202 1203 return rc; 1204 } 1205 1206 static struct bnxt_rss_ctx *bnxt_get_rss_ctx_from_index(struct bnxt *bp, 1207 u32 index) 1208 { 1209 struct ethtool_rxfh_context *ctx; 1210 1211 ctx = xa_load(&bp->dev->ethtool->rss_ctx, index); 1212 if (!ctx) 1213 return NULL; 1214 return ethtool_rxfh_context_priv(ctx); 1215 } 1216 1217 static int bnxt_alloc_vnic_rss_table(struct bnxt *bp, 1218 struct bnxt_vnic_info *vnic) 1219 { 1220 int size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5); 1221 1222 vnic->rss_table_size = size + HW_HASH_KEY_SIZE; 1223 vnic->rss_table = dma_alloc_coherent(&bp->pdev->dev, 1224 vnic->rss_table_size, 1225 &vnic->rss_table_dma_addr, 1226 GFP_KERNEL); 1227 if (!vnic->rss_table) 1228 return -ENOMEM; 1229 1230 vnic->rss_hash_key = ((void *)vnic->rss_table) + size; 1231 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; 1232 return 0; 1233 } 1234 1235 static int bnxt_add_l2_cls_rule(struct bnxt *bp, 1236 struct ethtool_rx_flow_spec *fs) 1237 { 1238 u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1239 u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1240 struct ethhdr *h_ether = &fs->h_u.ether_spec; 1241 struct ethhdr *m_ether = &fs->m_u.ether_spec; 1242 struct bnxt_l2_filter *fltr; 1243 struct bnxt_l2_key key; 1244 u16 vnic_id; 1245 u8 flags; 1246 int rc; 1247 1248 if (BNXT_CHIP_P5_PLUS(bp)) 1249 return -EOPNOTSUPP; 1250 1251 if (!is_broadcast_ether_addr(m_ether->h_dest)) 1252 return -EINVAL; 1253 ether_addr_copy(key.dst_mac_addr, h_ether->h_dest); 1254 key.vlan = 0; 1255 if (fs->flow_type & FLOW_EXT) { 1256 struct ethtool_flow_ext *m_ext = &fs->m_ext; 1257 struct ethtool_flow_ext *h_ext = &fs->h_ext; 1258 1259 if (m_ext->vlan_tci != htons(0xfff) || !h_ext->vlan_tci) 1260 return -EINVAL; 1261 key.vlan = ntohs(h_ext->vlan_tci); 1262 } 1263 1264 if (vf) { 1265 flags = BNXT_ACT_FUNC_DST; 1266 vnic_id = 0xffff; 1267 vf--; 1268 } else { 1269 flags = BNXT_ACT_RING_DST; 1270 vnic_id = bp->vnic_info[ring + 1].fw_vnic_id; 1271 } 1272 fltr = bnxt_alloc_new_l2_filter(bp, &key, flags); 1273 if (IS_ERR(fltr)) 1274 return PTR_ERR(fltr); 1275 1276 fltr->base.fw_vnic_id = vnic_id; 1277 fltr->base.rxq = ring; 1278 fltr->base.vf_idx = vf; 1279 rc = bnxt_hwrm_l2_filter_alloc(bp, fltr); 1280 if (rc) 1281 bnxt_del_l2_filter(bp, fltr); 1282 else 1283 fs->location = fltr->base.sw_id; 1284 return rc; 1285 } 1286 1287 static bool bnxt_verify_ntuple_ip4_flow(struct ethtool_usrip4_spec *ip_spec, 1288 struct ethtool_usrip4_spec *ip_mask) 1289 { 1290 u8 mproto = ip_mask->proto; 1291 u8 sproto = ip_spec->proto; 1292 1293 if (ip_mask->l4_4_bytes || ip_mask->tos || 1294 ip_spec->ip_ver != ETH_RX_NFC_IP4 || 1295 (mproto && (mproto != BNXT_IP_PROTO_FULL_MASK || sproto != IPPROTO_ICMP))) 1296 return false; 1297 return true; 1298 } 1299 1300 static bool bnxt_verify_ntuple_ip6_flow(struct ethtool_usrip6_spec *ip_spec, 1301 struct ethtool_usrip6_spec *ip_mask) 1302 { 1303 u8 mproto = ip_mask->l4_proto; 1304 u8 sproto = ip_spec->l4_proto; 1305 1306 if (ip_mask->l4_4_bytes || ip_mask->tclass || 1307 (mproto && (mproto != BNXT_IP_PROTO_FULL_MASK || sproto != IPPROTO_ICMPV6))) 1308 return false; 1309 return true; 1310 } 1311 1312 static int bnxt_add_ntuple_cls_rule(struct bnxt *bp, 1313 struct ethtool_rxnfc *cmd) 1314 { 1315 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1316 struct bnxt_ntuple_filter *new_fltr, *fltr; 1317 u32 flow_type = fs->flow_type & 0xff; 1318 struct bnxt_l2_filter *l2_fltr; 1319 struct bnxt_flow_masks *fmasks; 1320 struct flow_keys *fkeys; 1321 u32 idx, ring; 1322 int rc; 1323 u8 vf; 1324 1325 if (!bp->vnic_info) 1326 return -EAGAIN; 1327 1328 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1329 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1330 if ((fs->flow_type & (FLOW_MAC_EXT | FLOW_EXT)) || vf) 1331 return -EOPNOTSUPP; 1332 1333 if (flow_type == IP_USER_FLOW) { 1334 if (!bnxt_verify_ntuple_ip4_flow(&fs->h_u.usr_ip4_spec, 1335 &fs->m_u.usr_ip4_spec)) 1336 return -EOPNOTSUPP; 1337 } 1338 1339 if (flow_type == IPV6_USER_FLOW) { 1340 if (!bnxt_verify_ntuple_ip6_flow(&fs->h_u.usr_ip6_spec, 1341 &fs->m_u.usr_ip6_spec)) 1342 return -EOPNOTSUPP; 1343 } 1344 1345 new_fltr = kzalloc(sizeof(*new_fltr), GFP_KERNEL); 1346 if (!new_fltr) 1347 return -ENOMEM; 1348 1349 l2_fltr = bp->vnic_info[BNXT_VNIC_DEFAULT].l2_filters[0]; 1350 atomic_inc(&l2_fltr->refcnt); 1351 new_fltr->l2_fltr = l2_fltr; 1352 fmasks = &new_fltr->fmasks; 1353 fkeys = &new_fltr->fkeys; 1354 1355 rc = -EOPNOTSUPP; 1356 switch (flow_type) { 1357 case IP_USER_FLOW: { 1358 struct ethtool_usrip4_spec *ip_spec = &fs->h_u.usr_ip4_spec; 1359 struct ethtool_usrip4_spec *ip_mask = &fs->m_u.usr_ip4_spec; 1360 1361 fkeys->basic.ip_proto = ip_mask->proto ? ip_spec->proto 1362 : BNXT_IP_PROTO_WILDCARD; 1363 fkeys->basic.n_proto = htons(ETH_P_IP); 1364 fkeys->addrs.v4addrs.src = ip_spec->ip4src; 1365 fmasks->addrs.v4addrs.src = ip_mask->ip4src; 1366 fkeys->addrs.v4addrs.dst = ip_spec->ip4dst; 1367 fmasks->addrs.v4addrs.dst = ip_mask->ip4dst; 1368 break; 1369 } 1370 case TCP_V4_FLOW: 1371 case UDP_V4_FLOW: { 1372 struct ethtool_tcpip4_spec *ip_spec = &fs->h_u.tcp_ip4_spec; 1373 struct ethtool_tcpip4_spec *ip_mask = &fs->m_u.tcp_ip4_spec; 1374 1375 fkeys->basic.ip_proto = IPPROTO_TCP; 1376 if (flow_type == UDP_V4_FLOW) 1377 fkeys->basic.ip_proto = IPPROTO_UDP; 1378 fkeys->basic.n_proto = htons(ETH_P_IP); 1379 fkeys->addrs.v4addrs.src = ip_spec->ip4src; 1380 fmasks->addrs.v4addrs.src = ip_mask->ip4src; 1381 fkeys->addrs.v4addrs.dst = ip_spec->ip4dst; 1382 fmasks->addrs.v4addrs.dst = ip_mask->ip4dst; 1383 fkeys->ports.src = ip_spec->psrc; 1384 fmasks->ports.src = ip_mask->psrc; 1385 fkeys->ports.dst = ip_spec->pdst; 1386 fmasks->ports.dst = ip_mask->pdst; 1387 break; 1388 } 1389 case IPV6_USER_FLOW: { 1390 struct ethtool_usrip6_spec *ip_spec = &fs->h_u.usr_ip6_spec; 1391 struct ethtool_usrip6_spec *ip_mask = &fs->m_u.usr_ip6_spec; 1392 1393 fkeys->basic.ip_proto = ip_mask->l4_proto ? ip_spec->l4_proto 1394 : BNXT_IP_PROTO_WILDCARD; 1395 fkeys->basic.n_proto = htons(ETH_P_IPV6); 1396 fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src; 1397 fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src; 1398 fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst; 1399 fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst; 1400 break; 1401 } 1402 case TCP_V6_FLOW: 1403 case UDP_V6_FLOW: { 1404 struct ethtool_tcpip6_spec *ip_spec = &fs->h_u.tcp_ip6_spec; 1405 struct ethtool_tcpip6_spec *ip_mask = &fs->m_u.tcp_ip6_spec; 1406 1407 fkeys->basic.ip_proto = IPPROTO_TCP; 1408 if (flow_type == UDP_V6_FLOW) 1409 fkeys->basic.ip_proto = IPPROTO_UDP; 1410 fkeys->basic.n_proto = htons(ETH_P_IPV6); 1411 1412 fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src; 1413 fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src; 1414 fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst; 1415 fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst; 1416 fkeys->ports.src = ip_spec->psrc; 1417 fmasks->ports.src = ip_mask->psrc; 1418 fkeys->ports.dst = ip_spec->pdst; 1419 fmasks->ports.dst = ip_mask->pdst; 1420 break; 1421 } 1422 default: 1423 rc = -EOPNOTSUPP; 1424 goto ntuple_err; 1425 } 1426 if (!memcmp(&BNXT_FLOW_MASK_NONE, fmasks, sizeof(*fmasks))) 1427 goto ntuple_err; 1428 1429 idx = bnxt_get_ntp_filter_idx(bp, fkeys, NULL); 1430 rcu_read_lock(); 1431 fltr = bnxt_lookup_ntp_filter_from_idx(bp, new_fltr, idx); 1432 if (fltr) { 1433 rcu_read_unlock(); 1434 rc = -EEXIST; 1435 goto ntuple_err; 1436 } 1437 rcu_read_unlock(); 1438 1439 new_fltr->base.flags = BNXT_ACT_NO_AGING; 1440 if (fs->flow_type & FLOW_RSS) { 1441 struct bnxt_rss_ctx *rss_ctx; 1442 1443 new_fltr->base.fw_vnic_id = 0; 1444 new_fltr->base.flags |= BNXT_ACT_RSS_CTX; 1445 rss_ctx = bnxt_get_rss_ctx_from_index(bp, cmd->rss_context); 1446 if (rss_ctx) { 1447 new_fltr->base.fw_vnic_id = rss_ctx->index; 1448 } else { 1449 rc = -EINVAL; 1450 goto ntuple_err; 1451 } 1452 } 1453 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1454 new_fltr->base.flags |= BNXT_ACT_DROP; 1455 else 1456 new_fltr->base.rxq = ring; 1457 __set_bit(BNXT_FLTR_VALID, &new_fltr->base.state); 1458 rc = bnxt_insert_ntp_filter(bp, new_fltr, idx); 1459 if (!rc) { 1460 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, new_fltr); 1461 if (rc) { 1462 bnxt_del_ntp_filter(bp, new_fltr); 1463 return rc; 1464 } 1465 fs->location = new_fltr->base.sw_id; 1466 return 0; 1467 } 1468 1469 ntuple_err: 1470 atomic_dec(&l2_fltr->refcnt); 1471 kfree(new_fltr); 1472 return rc; 1473 } 1474 1475 static int bnxt_srxclsrlins(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1476 { 1477 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1478 u32 ring, flow_type; 1479 int rc; 1480 u8 vf; 1481 1482 if (!netif_running(bp->dev)) 1483 return -EAGAIN; 1484 if (!(bp->flags & BNXT_FLAG_RFS)) 1485 return -EPERM; 1486 if (fs->location != RX_CLS_LOC_ANY) 1487 return -EINVAL; 1488 1489 flow_type = fs->flow_type; 1490 if ((flow_type == IP_USER_FLOW || 1491 flow_type == IPV6_USER_FLOW) && 1492 !(bp->fw_cap & BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO)) 1493 return -EOPNOTSUPP; 1494 if (flow_type & FLOW_MAC_EXT) 1495 return -EINVAL; 1496 flow_type &= ~FLOW_EXT; 1497 1498 if (fs->ring_cookie == RX_CLS_FLOW_DISC && flow_type != ETHER_FLOW) 1499 return bnxt_add_ntuple_cls_rule(bp, cmd); 1500 1501 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1502 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1503 if (BNXT_VF(bp) && vf) 1504 return -EINVAL; 1505 if (BNXT_PF(bp) && vf > bp->pf.active_vfs) 1506 return -EINVAL; 1507 if (!vf && ring >= bp->rx_nr_rings) 1508 return -EINVAL; 1509 1510 if (flow_type == ETHER_FLOW) 1511 rc = bnxt_add_l2_cls_rule(bp, fs); 1512 else 1513 rc = bnxt_add_ntuple_cls_rule(bp, cmd); 1514 return rc; 1515 } 1516 1517 static int bnxt_srxclsrldel(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1518 { 1519 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1520 struct bnxt_filter_base *fltr_base; 1521 struct bnxt_ntuple_filter *fltr; 1522 u32 id = fs->location; 1523 1524 rcu_read_lock(); 1525 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl, 1526 BNXT_L2_FLTR_HASH_SIZE, id); 1527 if (fltr_base) { 1528 struct bnxt_l2_filter *l2_fltr; 1529 1530 l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base); 1531 rcu_read_unlock(); 1532 bnxt_hwrm_l2_filter_free(bp, l2_fltr); 1533 bnxt_del_l2_filter(bp, l2_fltr); 1534 return 0; 1535 } 1536 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl, 1537 BNXT_NTP_FLTR_HASH_SIZE, id); 1538 if (!fltr_base) { 1539 rcu_read_unlock(); 1540 return -ENOENT; 1541 } 1542 1543 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base); 1544 if (!(fltr->base.flags & BNXT_ACT_NO_AGING)) { 1545 rcu_read_unlock(); 1546 return -EINVAL; 1547 } 1548 rcu_read_unlock(); 1549 bnxt_hwrm_cfa_ntuple_filter_free(bp, fltr); 1550 bnxt_del_ntp_filter(bp, fltr); 1551 return 0; 1552 } 1553 1554 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1555 { 1556 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1557 return RXH_IP_SRC | RXH_IP_DST; 1558 return 0; 1559 } 1560 1561 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1562 { 1563 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1564 return RXH_IP_SRC | RXH_IP_DST; 1565 return 0; 1566 } 1567 1568 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1569 { 1570 cmd->data = 0; 1571 switch (cmd->flow_type) { 1572 case TCP_V4_FLOW: 1573 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1574 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1575 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1576 cmd->data |= get_ethtool_ipv4_rss(bp); 1577 break; 1578 case UDP_V4_FLOW: 1579 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1580 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1581 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1582 fallthrough; 1583 case AH_ESP_V4_FLOW: 1584 if (bp->rss_hash_cfg & 1585 (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1586 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4)) 1587 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1588 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1589 fallthrough; 1590 case SCTP_V4_FLOW: 1591 case AH_V4_FLOW: 1592 case ESP_V4_FLOW: 1593 case IPV4_FLOW: 1594 cmd->data |= get_ethtool_ipv4_rss(bp); 1595 break; 1596 1597 case TCP_V6_FLOW: 1598 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1599 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1600 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1601 cmd->data |= get_ethtool_ipv6_rss(bp); 1602 break; 1603 case UDP_V6_FLOW: 1604 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1605 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1606 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1607 fallthrough; 1608 case AH_ESP_V6_FLOW: 1609 if (bp->rss_hash_cfg & 1610 (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1611 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6)) 1612 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1613 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1614 fallthrough; 1615 case SCTP_V6_FLOW: 1616 case AH_V6_FLOW: 1617 case ESP_V6_FLOW: 1618 case IPV6_FLOW: 1619 cmd->data |= get_ethtool_ipv6_rss(bp); 1620 break; 1621 } 1622 return 0; 1623 } 1624 1625 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1626 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1627 1628 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1629 { 1630 u32 rss_hash_cfg = bp->rss_hash_cfg; 1631 int tuple, rc = 0; 1632 1633 if (cmd->data == RXH_4TUPLE) 1634 tuple = 4; 1635 else if (cmd->data == RXH_2TUPLE) 1636 tuple = 2; 1637 else if (!cmd->data) 1638 tuple = 0; 1639 else 1640 return -EINVAL; 1641 1642 if (cmd->flow_type == TCP_V4_FLOW) { 1643 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1644 if (tuple == 4) 1645 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1646 } else if (cmd->flow_type == UDP_V4_FLOW) { 1647 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP)) 1648 return -EINVAL; 1649 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1650 if (tuple == 4) 1651 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1652 } else if (cmd->flow_type == TCP_V6_FLOW) { 1653 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1654 if (tuple == 4) 1655 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1656 } else if (cmd->flow_type == UDP_V6_FLOW) { 1657 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP)) 1658 return -EINVAL; 1659 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1660 if (tuple == 4) 1661 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1662 } else if (cmd->flow_type == AH_ESP_V4_FLOW) { 1663 if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V4_RSS_CAP) || 1664 !(bp->rss_cap & BNXT_RSS_CAP_ESP_V4_RSS_CAP))) 1665 return -EINVAL; 1666 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1667 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4); 1668 if (tuple == 4) 1669 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1670 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4; 1671 } else if (cmd->flow_type == AH_ESP_V6_FLOW) { 1672 if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V6_RSS_CAP) || 1673 !(bp->rss_cap & BNXT_RSS_CAP_ESP_V6_RSS_CAP))) 1674 return -EINVAL; 1675 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1676 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6); 1677 if (tuple == 4) 1678 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1679 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6; 1680 } else if (tuple == 4) { 1681 return -EINVAL; 1682 } 1683 1684 switch (cmd->flow_type) { 1685 case TCP_V4_FLOW: 1686 case UDP_V4_FLOW: 1687 case SCTP_V4_FLOW: 1688 case AH_ESP_V4_FLOW: 1689 case AH_V4_FLOW: 1690 case ESP_V4_FLOW: 1691 case IPV4_FLOW: 1692 if (tuple == 2) 1693 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1694 else if (!tuple) 1695 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1696 break; 1697 1698 case TCP_V6_FLOW: 1699 case UDP_V6_FLOW: 1700 case SCTP_V6_FLOW: 1701 case AH_ESP_V6_FLOW: 1702 case AH_V6_FLOW: 1703 case ESP_V6_FLOW: 1704 case IPV6_FLOW: 1705 if (tuple == 2) 1706 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1707 else if (!tuple) 1708 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1709 break; 1710 } 1711 1712 if (bp->rss_hash_cfg == rss_hash_cfg) 1713 return 0; 1714 1715 if (bp->rss_cap & BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA) 1716 bp->rss_hash_delta = bp->rss_hash_cfg ^ rss_hash_cfg; 1717 bp->rss_hash_cfg = rss_hash_cfg; 1718 if (netif_running(bp->dev)) { 1719 bnxt_close_nic(bp, false, false); 1720 rc = bnxt_open_nic(bp, false, false); 1721 } 1722 return rc; 1723 } 1724 1725 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1726 u32 *rule_locs) 1727 { 1728 struct bnxt *bp = netdev_priv(dev); 1729 int rc = 0; 1730 1731 switch (cmd->cmd) { 1732 case ETHTOOL_GRXRINGS: 1733 cmd->data = bp->rx_nr_rings; 1734 break; 1735 1736 case ETHTOOL_GRXCLSRLCNT: 1737 cmd->rule_cnt = bp->ntp_fltr_count; 1738 cmd->data = bp->max_fltr | RX_CLS_LOC_SPECIAL; 1739 break; 1740 1741 case ETHTOOL_GRXCLSRLALL: 1742 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1743 break; 1744 1745 case ETHTOOL_GRXCLSRULE: 1746 rc = bnxt_grxclsrule(bp, cmd); 1747 break; 1748 1749 case ETHTOOL_GRXFH: 1750 rc = bnxt_grxfh(bp, cmd); 1751 break; 1752 1753 default: 1754 rc = -EOPNOTSUPP; 1755 break; 1756 } 1757 1758 return rc; 1759 } 1760 1761 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1762 { 1763 struct bnxt *bp = netdev_priv(dev); 1764 int rc; 1765 1766 switch (cmd->cmd) { 1767 case ETHTOOL_SRXFH: 1768 rc = bnxt_srxfh(bp, cmd); 1769 break; 1770 1771 case ETHTOOL_SRXCLSRLINS: 1772 rc = bnxt_srxclsrlins(bp, cmd); 1773 break; 1774 1775 case ETHTOOL_SRXCLSRLDEL: 1776 rc = bnxt_srxclsrldel(bp, cmd); 1777 break; 1778 1779 default: 1780 rc = -EOPNOTSUPP; 1781 break; 1782 } 1783 return rc; 1784 } 1785 1786 u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1787 { 1788 struct bnxt *bp = netdev_priv(dev); 1789 1790 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) 1791 return bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) * 1792 BNXT_RSS_TABLE_ENTRIES_P5; 1793 return HW_HASH_INDEX_SIZE; 1794 } 1795 1796 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1797 { 1798 return HW_HASH_KEY_SIZE; 1799 } 1800 1801 static int bnxt_get_rxfh(struct net_device *dev, 1802 struct ethtool_rxfh_param *rxfh) 1803 { 1804 struct bnxt_rss_ctx *rss_ctx = NULL; 1805 struct bnxt *bp = netdev_priv(dev); 1806 u32 *indir_tbl = bp->rss_indir_tbl; 1807 struct bnxt_vnic_info *vnic; 1808 u32 i, tbl_size; 1809 1810 rxfh->hfunc = ETH_RSS_HASH_TOP; 1811 1812 if (!bp->vnic_info) 1813 return 0; 1814 1815 vnic = &bp->vnic_info[BNXT_VNIC_DEFAULT]; 1816 if (rxfh->rss_context) { 1817 struct ethtool_rxfh_context *ctx; 1818 1819 ctx = xa_load(&bp->dev->ethtool->rss_ctx, rxfh->rss_context); 1820 if (!ctx) 1821 return -EINVAL; 1822 indir_tbl = ethtool_rxfh_context_indir(ctx); 1823 rss_ctx = ethtool_rxfh_context_priv(ctx); 1824 vnic = &rss_ctx->vnic; 1825 } 1826 1827 if (rxfh->indir && indir_tbl) { 1828 tbl_size = bnxt_get_rxfh_indir_size(dev); 1829 for (i = 0; i < tbl_size; i++) 1830 rxfh->indir[i] = indir_tbl[i]; 1831 } 1832 1833 if (rxfh->key && vnic->rss_hash_key) 1834 memcpy(rxfh->key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1835 1836 return 0; 1837 } 1838 1839 static void bnxt_modify_rss(struct bnxt *bp, struct ethtool_rxfh_context *ctx, 1840 struct bnxt_rss_ctx *rss_ctx, 1841 const struct ethtool_rxfh_param *rxfh) 1842 { 1843 if (rxfh->key) { 1844 if (rss_ctx) { 1845 memcpy(rss_ctx->vnic.rss_hash_key, rxfh->key, 1846 HW_HASH_KEY_SIZE); 1847 } else { 1848 memcpy(bp->rss_hash_key, rxfh->key, HW_HASH_KEY_SIZE); 1849 bp->rss_hash_key_updated = true; 1850 } 1851 } 1852 if (rxfh->indir) { 1853 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(bp->dev); 1854 u32 *indir_tbl = bp->rss_indir_tbl; 1855 1856 if (rss_ctx) 1857 indir_tbl = ethtool_rxfh_context_indir(ctx); 1858 for (i = 0; i < tbl_size; i++) 1859 indir_tbl[i] = rxfh->indir[i]; 1860 pad = bp->rss_indir_tbl_entries - tbl_size; 1861 if (pad) 1862 memset(&indir_tbl[i], 0, pad * sizeof(*indir_tbl)); 1863 } 1864 } 1865 1866 static int bnxt_rxfh_context_check(struct bnxt *bp, 1867 const struct ethtool_rxfh_param *rxfh, 1868 struct netlink_ext_ack *extack) 1869 { 1870 if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP) { 1871 NL_SET_ERR_MSG_MOD(extack, "RSS hash function not supported"); 1872 return -EOPNOTSUPP; 1873 } 1874 1875 if (!BNXT_SUPPORTS_MULTI_RSS_CTX(bp)) { 1876 NL_SET_ERR_MSG_MOD(extack, "RSS contexts not supported"); 1877 return -EOPNOTSUPP; 1878 } 1879 1880 if (!netif_running(bp->dev)) { 1881 NL_SET_ERR_MSG_MOD(extack, "Unable to set RSS contexts when interface is down"); 1882 return -EAGAIN; 1883 } 1884 1885 return 0; 1886 } 1887 1888 static int bnxt_create_rxfh_context(struct net_device *dev, 1889 struct ethtool_rxfh_context *ctx, 1890 const struct ethtool_rxfh_param *rxfh, 1891 struct netlink_ext_ack *extack) 1892 { 1893 struct bnxt *bp = netdev_priv(dev); 1894 struct bnxt_rss_ctx *rss_ctx; 1895 struct bnxt_vnic_info *vnic; 1896 int rc; 1897 1898 rc = bnxt_rxfh_context_check(bp, rxfh, extack); 1899 if (rc) 1900 return rc; 1901 1902 if (bp->num_rss_ctx >= BNXT_MAX_ETH_RSS_CTX) { 1903 NL_SET_ERR_MSG_FMT_MOD(extack, "Out of RSS contexts, maximum %u", 1904 BNXT_MAX_ETH_RSS_CTX); 1905 return -EINVAL; 1906 } 1907 1908 if (!bnxt_rfs_capable(bp, true)) { 1909 NL_SET_ERR_MSG_MOD(extack, "Out hardware resources"); 1910 return -ENOMEM; 1911 } 1912 1913 rss_ctx = ethtool_rxfh_context_priv(ctx); 1914 1915 bp->num_rss_ctx++; 1916 1917 vnic = &rss_ctx->vnic; 1918 vnic->rss_ctx = ctx; 1919 vnic->flags |= BNXT_VNIC_RSSCTX_FLAG; 1920 vnic->vnic_id = BNXT_VNIC_ID_INVALID; 1921 rc = bnxt_alloc_vnic_rss_table(bp, vnic); 1922 if (rc) 1923 goto out; 1924 1925 /* Populate defaults in the context */ 1926 bnxt_set_dflt_rss_indir_tbl(bp, ctx); 1927 ctx->hfunc = ETH_RSS_HASH_TOP; 1928 memcpy(vnic->rss_hash_key, bp->rss_hash_key, HW_HASH_KEY_SIZE); 1929 memcpy(ethtool_rxfh_context_key(ctx), 1930 bp->rss_hash_key, HW_HASH_KEY_SIZE); 1931 1932 rc = bnxt_hwrm_vnic_alloc(bp, vnic, 0, bp->rx_nr_rings); 1933 if (rc) { 1934 NL_SET_ERR_MSG_MOD(extack, "Unable to allocate VNIC"); 1935 goto out; 1936 } 1937 1938 rc = bnxt_hwrm_vnic_set_tpa(bp, vnic, bp->flags & BNXT_FLAG_TPA); 1939 if (rc) { 1940 NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA"); 1941 goto out; 1942 } 1943 bnxt_modify_rss(bp, ctx, rss_ctx, rxfh); 1944 1945 rc = __bnxt_setup_vnic_p5(bp, vnic); 1946 if (rc) { 1947 NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA"); 1948 goto out; 1949 } 1950 1951 rss_ctx->index = rxfh->rss_context; 1952 return 0; 1953 out: 1954 bnxt_del_one_rss_ctx(bp, rss_ctx, true); 1955 return rc; 1956 } 1957 1958 static int bnxt_modify_rxfh_context(struct net_device *dev, 1959 struct ethtool_rxfh_context *ctx, 1960 const struct ethtool_rxfh_param *rxfh, 1961 struct netlink_ext_ack *extack) 1962 { 1963 struct bnxt *bp = netdev_priv(dev); 1964 struct bnxt_rss_ctx *rss_ctx; 1965 int rc; 1966 1967 rc = bnxt_rxfh_context_check(bp, rxfh, extack); 1968 if (rc) 1969 return rc; 1970 1971 rss_ctx = ethtool_rxfh_context_priv(ctx); 1972 1973 bnxt_modify_rss(bp, ctx, rss_ctx, rxfh); 1974 1975 return bnxt_hwrm_vnic_rss_cfg_p5(bp, &rss_ctx->vnic); 1976 } 1977 1978 static int bnxt_remove_rxfh_context(struct net_device *dev, 1979 struct ethtool_rxfh_context *ctx, 1980 u32 rss_context, 1981 struct netlink_ext_ack *extack) 1982 { 1983 struct bnxt *bp = netdev_priv(dev); 1984 struct bnxt_rss_ctx *rss_ctx; 1985 1986 rss_ctx = ethtool_rxfh_context_priv(ctx); 1987 1988 bnxt_del_one_rss_ctx(bp, rss_ctx, true); 1989 return 0; 1990 } 1991 1992 static int bnxt_set_rxfh(struct net_device *dev, 1993 struct ethtool_rxfh_param *rxfh, 1994 struct netlink_ext_ack *extack) 1995 { 1996 struct bnxt *bp = netdev_priv(dev); 1997 int rc = 0; 1998 1999 if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP) 2000 return -EOPNOTSUPP; 2001 2002 bnxt_modify_rss(bp, NULL, NULL, rxfh); 2003 2004 if (netif_running(bp->dev)) { 2005 bnxt_close_nic(bp, false, false); 2006 rc = bnxt_open_nic(bp, false, false); 2007 } 2008 return rc; 2009 } 2010 2011 static void bnxt_get_drvinfo(struct net_device *dev, 2012 struct ethtool_drvinfo *info) 2013 { 2014 struct bnxt *bp = netdev_priv(dev); 2015 2016 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 2017 strscpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 2018 strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 2019 info->n_stats = bnxt_get_num_stats(bp); 2020 info->testinfo_len = bp->num_tests; 2021 /* TODO CHIMP_FW: eeprom dump details */ 2022 info->eedump_len = 0; 2023 /* TODO CHIMP FW: reg dump details */ 2024 info->regdump_len = 0; 2025 } 2026 2027 static int bnxt_get_regs_len(struct net_device *dev) 2028 { 2029 struct bnxt *bp = netdev_priv(dev); 2030 int reg_len; 2031 2032 if (!BNXT_PF(bp)) 2033 return -EOPNOTSUPP; 2034 2035 reg_len = BNXT_PXP_REG_LEN; 2036 2037 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED) 2038 reg_len += sizeof(struct pcie_ctx_hw_stats); 2039 2040 return reg_len; 2041 } 2042 2043 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs, 2044 void *_p) 2045 { 2046 struct pcie_ctx_hw_stats *hw_pcie_stats; 2047 struct hwrm_pcie_qstats_input *req; 2048 struct bnxt *bp = netdev_priv(dev); 2049 dma_addr_t hw_pcie_stats_addr; 2050 int rc; 2051 2052 regs->version = 0; 2053 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p); 2054 2055 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 2056 return; 2057 2058 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS)) 2059 return; 2060 2061 hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats), 2062 &hw_pcie_stats_addr); 2063 if (!hw_pcie_stats) { 2064 hwrm_req_drop(bp, req); 2065 return; 2066 } 2067 2068 regs->version = 1; 2069 hwrm_req_hold(bp, req); /* hold on to slice */ 2070 req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats)); 2071 req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr); 2072 rc = hwrm_req_send(bp, req); 2073 if (!rc) { 2074 __le64 *src = (__le64 *)hw_pcie_stats; 2075 u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN); 2076 int i; 2077 2078 for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++) 2079 dst[i] = le64_to_cpu(src[i]); 2080 } 2081 hwrm_req_drop(bp, req); 2082 } 2083 2084 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2085 { 2086 struct bnxt *bp = netdev_priv(dev); 2087 2088 wol->supported = 0; 2089 wol->wolopts = 0; 2090 memset(&wol->sopass, 0, sizeof(wol->sopass)); 2091 if (bp->flags & BNXT_FLAG_WOL_CAP) { 2092 wol->supported = WAKE_MAGIC; 2093 if (bp->wol) 2094 wol->wolopts = WAKE_MAGIC; 2095 } 2096 } 2097 2098 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2099 { 2100 struct bnxt *bp = netdev_priv(dev); 2101 2102 if (wol->wolopts & ~WAKE_MAGIC) 2103 return -EINVAL; 2104 2105 if (wol->wolopts & WAKE_MAGIC) { 2106 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 2107 return -EINVAL; 2108 if (!bp->wol) { 2109 if (bnxt_hwrm_alloc_wol_fltr(bp)) 2110 return -EBUSY; 2111 bp->wol = 1; 2112 } 2113 } else { 2114 if (bp->wol) { 2115 if (bnxt_hwrm_free_wol_fltr(bp)) 2116 return -EBUSY; 2117 bp->wol = 0; 2118 } 2119 } 2120 return 0; 2121 } 2122 2123 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 2124 void _bnxt_fw_to_linkmode(unsigned long *mode, u16 fw_speeds) 2125 { 2126 linkmode_zero(mode); 2127 2128 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 2129 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode); 2130 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 2131 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode); 2132 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 2133 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT, mode); 2134 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 2135 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode); 2136 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 2137 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode); 2138 } 2139 2140 enum bnxt_media_type { 2141 BNXT_MEDIA_UNKNOWN = 0, 2142 BNXT_MEDIA_TP, 2143 BNXT_MEDIA_CR, 2144 BNXT_MEDIA_SR, 2145 BNXT_MEDIA_LR_ER_FR, 2146 BNXT_MEDIA_KR, 2147 BNXT_MEDIA_KX, 2148 BNXT_MEDIA_X, 2149 __BNXT_MEDIA_END, 2150 }; 2151 2152 static const enum bnxt_media_type bnxt_phy_types[] = { 2153 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR] = BNXT_MEDIA_CR, 2154 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4] = BNXT_MEDIA_KR, 2155 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR] = BNXT_MEDIA_LR_ER_FR, 2156 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR] = BNXT_MEDIA_SR, 2157 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2] = BNXT_MEDIA_KR, 2158 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX] = BNXT_MEDIA_KX, 2159 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR] = BNXT_MEDIA_KR, 2160 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASET] = BNXT_MEDIA_TP, 2161 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE] = BNXT_MEDIA_TP, 2162 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L] = BNXT_MEDIA_CR, 2163 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S] = BNXT_MEDIA_CR, 2164 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N] = BNXT_MEDIA_CR, 2165 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR] = BNXT_MEDIA_SR, 2166 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4] = BNXT_MEDIA_CR, 2167 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4] = BNXT_MEDIA_SR, 2168 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2169 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2170 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10] = BNXT_MEDIA_SR, 2171 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4] = BNXT_MEDIA_CR, 2172 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4] = BNXT_MEDIA_SR, 2173 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2174 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2175 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE] = BNXT_MEDIA_SR, 2176 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET] = BNXT_MEDIA_TP, 2177 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX] = BNXT_MEDIA_X, 2178 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX] = BNXT_MEDIA_X, 2179 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4] = BNXT_MEDIA_CR, 2180 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4] = BNXT_MEDIA_SR, 2181 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2182 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2183 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR] = BNXT_MEDIA_CR, 2184 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR] = BNXT_MEDIA_SR, 2185 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR] = BNXT_MEDIA_LR_ER_FR, 2186 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER] = BNXT_MEDIA_LR_ER_FR, 2187 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2] = BNXT_MEDIA_CR, 2188 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2] = BNXT_MEDIA_SR, 2189 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2] = BNXT_MEDIA_LR_ER_FR, 2190 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2] = BNXT_MEDIA_LR_ER_FR, 2191 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR] = BNXT_MEDIA_CR, 2192 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR] = BNXT_MEDIA_SR, 2193 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR] = BNXT_MEDIA_LR_ER_FR, 2194 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER] = BNXT_MEDIA_LR_ER_FR, 2195 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2] = BNXT_MEDIA_CR, 2196 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2] = BNXT_MEDIA_SR, 2197 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2] = BNXT_MEDIA_LR_ER_FR, 2198 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2] = BNXT_MEDIA_LR_ER_FR, 2199 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8] = BNXT_MEDIA_CR, 2200 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8] = BNXT_MEDIA_SR, 2201 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8] = BNXT_MEDIA_LR_ER_FR, 2202 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8] = BNXT_MEDIA_LR_ER_FR, 2203 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4] = BNXT_MEDIA_CR, 2204 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4] = BNXT_MEDIA_SR, 2205 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2206 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2207 }; 2208 2209 static enum bnxt_media_type 2210 bnxt_get_media(struct bnxt_link_info *link_info) 2211 { 2212 switch (link_info->media_type) { 2213 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP: 2214 return BNXT_MEDIA_TP; 2215 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC: 2216 return BNXT_MEDIA_CR; 2217 default: 2218 if (link_info->phy_type < ARRAY_SIZE(bnxt_phy_types)) 2219 return bnxt_phy_types[link_info->phy_type]; 2220 return BNXT_MEDIA_UNKNOWN; 2221 } 2222 } 2223 2224 enum bnxt_link_speed_indices { 2225 BNXT_LINK_SPEED_UNKNOWN = 0, 2226 BNXT_LINK_SPEED_100MB_IDX, 2227 BNXT_LINK_SPEED_1GB_IDX, 2228 BNXT_LINK_SPEED_10GB_IDX, 2229 BNXT_LINK_SPEED_25GB_IDX, 2230 BNXT_LINK_SPEED_40GB_IDX, 2231 BNXT_LINK_SPEED_50GB_IDX, 2232 BNXT_LINK_SPEED_100GB_IDX, 2233 BNXT_LINK_SPEED_200GB_IDX, 2234 BNXT_LINK_SPEED_400GB_IDX, 2235 __BNXT_LINK_SPEED_END 2236 }; 2237 2238 static enum bnxt_link_speed_indices bnxt_fw_speed_idx(u16 speed) 2239 { 2240 switch (speed) { 2241 case BNXT_LINK_SPEED_100MB: return BNXT_LINK_SPEED_100MB_IDX; 2242 case BNXT_LINK_SPEED_1GB: return BNXT_LINK_SPEED_1GB_IDX; 2243 case BNXT_LINK_SPEED_10GB: return BNXT_LINK_SPEED_10GB_IDX; 2244 case BNXT_LINK_SPEED_25GB: return BNXT_LINK_SPEED_25GB_IDX; 2245 case BNXT_LINK_SPEED_40GB: return BNXT_LINK_SPEED_40GB_IDX; 2246 case BNXT_LINK_SPEED_50GB: 2247 case BNXT_LINK_SPEED_50GB_PAM4: 2248 return BNXT_LINK_SPEED_50GB_IDX; 2249 case BNXT_LINK_SPEED_100GB: 2250 case BNXT_LINK_SPEED_100GB_PAM4: 2251 case BNXT_LINK_SPEED_100GB_PAM4_112: 2252 return BNXT_LINK_SPEED_100GB_IDX; 2253 case BNXT_LINK_SPEED_200GB: 2254 case BNXT_LINK_SPEED_200GB_PAM4: 2255 case BNXT_LINK_SPEED_200GB_PAM4_112: 2256 return BNXT_LINK_SPEED_200GB_IDX; 2257 case BNXT_LINK_SPEED_400GB: 2258 case BNXT_LINK_SPEED_400GB_PAM4: 2259 case BNXT_LINK_SPEED_400GB_PAM4_112: 2260 return BNXT_LINK_SPEED_400GB_IDX; 2261 default: return BNXT_LINK_SPEED_UNKNOWN; 2262 } 2263 } 2264 2265 static const enum ethtool_link_mode_bit_indices 2266 bnxt_link_modes[__BNXT_LINK_SPEED_END][BNXT_SIG_MODE_MAX][__BNXT_MEDIA_END] = { 2267 [BNXT_LINK_SPEED_100MB_IDX] = { 2268 { 2269 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_100baseT_Full_BIT, 2270 }, 2271 }, 2272 [BNXT_LINK_SPEED_1GB_IDX] = { 2273 { 2274 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 2275 /* historically baseT, but DAC is more correctly baseX */ 2276 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 2277 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2278 [BNXT_MEDIA_X] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 2279 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2280 }, 2281 }, 2282 [BNXT_LINK_SPEED_10GB_IDX] = { 2283 { 2284 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 2285 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 2286 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 2287 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 2288 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 2289 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 2290 }, 2291 }, 2292 [BNXT_LINK_SPEED_25GB_IDX] = { 2293 { 2294 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 2295 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 2296 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 2297 }, 2298 }, 2299 [BNXT_LINK_SPEED_40GB_IDX] = { 2300 { 2301 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 2302 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 2303 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 2304 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 2305 }, 2306 }, 2307 [BNXT_LINK_SPEED_50GB_IDX] = { 2308 [BNXT_SIG_MODE_NRZ] = { 2309 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 2310 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 2311 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 2312 }, 2313 [BNXT_SIG_MODE_PAM4] = { 2314 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 2315 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 2316 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 2317 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 2318 }, 2319 }, 2320 [BNXT_LINK_SPEED_100GB_IDX] = { 2321 [BNXT_SIG_MODE_NRZ] = { 2322 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 2323 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 2324 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 2325 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 2326 }, 2327 [BNXT_SIG_MODE_PAM4] = { 2328 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 2329 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 2330 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 2331 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 2332 }, 2333 [BNXT_SIG_MODE_PAM4_112] = { 2334 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR_Full_BIT, 2335 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR_Full_BIT, 2336 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR_Full_BIT, 2337 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT, 2338 }, 2339 }, 2340 [BNXT_LINK_SPEED_200GB_IDX] = { 2341 [BNXT_SIG_MODE_PAM4] = { 2342 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT, 2343 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 2344 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 2345 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 2346 }, 2347 [BNXT_SIG_MODE_PAM4_112] = { 2348 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT, 2349 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT, 2350 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT, 2351 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT, 2352 }, 2353 }, 2354 [BNXT_LINK_SPEED_400GB_IDX] = { 2355 [BNXT_SIG_MODE_PAM4] = { 2356 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT, 2357 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT, 2358 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT, 2359 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT, 2360 }, 2361 [BNXT_SIG_MODE_PAM4_112] = { 2362 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT, 2363 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT, 2364 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT, 2365 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT, 2366 }, 2367 }, 2368 }; 2369 2370 #define BNXT_LINK_MODE_UNKNOWN -1 2371 2372 static enum ethtool_link_mode_bit_indices 2373 bnxt_get_link_mode(struct bnxt_link_info *link_info) 2374 { 2375 enum ethtool_link_mode_bit_indices link_mode; 2376 enum bnxt_link_speed_indices speed; 2377 enum bnxt_media_type media; 2378 u8 sig_mode; 2379 2380 if (link_info->phy_link_status != BNXT_LINK_LINK) 2381 return BNXT_LINK_MODE_UNKNOWN; 2382 2383 media = bnxt_get_media(link_info); 2384 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 2385 speed = bnxt_fw_speed_idx(link_info->link_speed); 2386 sig_mode = link_info->active_fec_sig_mode & 2387 PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK; 2388 } else { 2389 speed = bnxt_fw_speed_idx(link_info->req_link_speed); 2390 sig_mode = link_info->req_signal_mode; 2391 } 2392 if (sig_mode >= BNXT_SIG_MODE_MAX) 2393 return BNXT_LINK_MODE_UNKNOWN; 2394 2395 /* Note ETHTOOL_LINK_MODE_10baseT_Half_BIT == 0 is a legal Linux 2396 * link mode, but since no such devices exist, the zeroes in the 2397 * map can be conveniently used to represent unknown link modes. 2398 */ 2399 link_mode = bnxt_link_modes[speed][sig_mode][media]; 2400 if (!link_mode) 2401 return BNXT_LINK_MODE_UNKNOWN; 2402 2403 switch (link_mode) { 2404 case ETHTOOL_LINK_MODE_100baseT_Full_BIT: 2405 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2406 link_mode = ETHTOOL_LINK_MODE_100baseT_Half_BIT; 2407 break; 2408 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT: 2409 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2410 link_mode = ETHTOOL_LINK_MODE_1000baseT_Half_BIT; 2411 break; 2412 default: 2413 break; 2414 } 2415 2416 return link_mode; 2417 } 2418 2419 static void bnxt_get_ethtool_modes(struct bnxt_link_info *link_info, 2420 struct ethtool_link_ksettings *lk_ksettings) 2421 { 2422 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2423 2424 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) { 2425 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2426 lk_ksettings->link_modes.supported); 2427 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2428 lk_ksettings->link_modes.supported); 2429 } 2430 2431 if (link_info->support_auto_speeds || link_info->support_auto_speeds2 || 2432 link_info->support_pam4_auto_speeds) 2433 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2434 lk_ksettings->link_modes.supported); 2435 2436 if (~link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 2437 return; 2438 2439 if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_RX) 2440 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2441 lk_ksettings->link_modes.advertising); 2442 if (hweight8(link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) == 1) 2443 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2444 lk_ksettings->link_modes.advertising); 2445 if (link_info->lp_pause & BNXT_LINK_PAUSE_RX) 2446 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2447 lk_ksettings->link_modes.lp_advertising); 2448 if (hweight8(link_info->lp_pause & BNXT_LINK_PAUSE_BOTH) == 1) 2449 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2450 lk_ksettings->link_modes.lp_advertising); 2451 } 2452 2453 static const u16 bnxt_nrz_speed_masks[] = { 2454 [BNXT_LINK_SPEED_100MB_IDX] = BNXT_LINK_SPEED_MSK_100MB, 2455 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEED_MSK_1GB, 2456 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEED_MSK_10GB, 2457 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEED_MSK_25GB, 2458 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEED_MSK_40GB, 2459 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEED_MSK_50GB, 2460 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEED_MSK_100GB, 2461 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2462 }; 2463 2464 static const u16 bnxt_pam4_speed_masks[] = { 2465 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_50GB, 2466 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_100GB, 2467 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_200GB, 2468 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2469 }; 2470 2471 static const u16 bnxt_nrz_speeds2_masks[] = { 2472 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEEDS2_MSK_1GB, 2473 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEEDS2_MSK_10GB, 2474 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEEDS2_MSK_25GB, 2475 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEEDS2_MSK_40GB, 2476 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB, 2477 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB, 2478 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2479 }; 2480 2481 static const u16 bnxt_pam4_speeds2_masks[] = { 2482 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB_PAM4, 2483 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4, 2484 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4, 2485 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4, 2486 }; 2487 2488 static const u16 bnxt_pam4_112_speeds2_masks[] = { 2489 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112, 2490 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112, 2491 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112, 2492 }; 2493 2494 static enum bnxt_link_speed_indices 2495 bnxt_encoding_speed_idx(u8 sig_mode, u16 phy_flags, u16 speed_msk) 2496 { 2497 const u16 *speeds; 2498 int idx, len; 2499 2500 switch (sig_mode) { 2501 case BNXT_SIG_MODE_NRZ: 2502 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2503 speeds = bnxt_nrz_speeds2_masks; 2504 len = ARRAY_SIZE(bnxt_nrz_speeds2_masks); 2505 } else { 2506 speeds = bnxt_nrz_speed_masks; 2507 len = ARRAY_SIZE(bnxt_nrz_speed_masks); 2508 } 2509 break; 2510 case BNXT_SIG_MODE_PAM4: 2511 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2512 speeds = bnxt_pam4_speeds2_masks; 2513 len = ARRAY_SIZE(bnxt_pam4_speeds2_masks); 2514 } else { 2515 speeds = bnxt_pam4_speed_masks; 2516 len = ARRAY_SIZE(bnxt_pam4_speed_masks); 2517 } 2518 break; 2519 case BNXT_SIG_MODE_PAM4_112: 2520 speeds = bnxt_pam4_112_speeds2_masks; 2521 len = ARRAY_SIZE(bnxt_pam4_112_speeds2_masks); 2522 break; 2523 default: 2524 return BNXT_LINK_SPEED_UNKNOWN; 2525 } 2526 2527 for (idx = 0; idx < len; idx++) { 2528 if (speeds[idx] == speed_msk) 2529 return idx; 2530 } 2531 2532 return BNXT_LINK_SPEED_UNKNOWN; 2533 } 2534 2535 #define BNXT_FW_SPEED_MSK_BITS 16 2536 2537 static void 2538 __bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media, 2539 u8 sig_mode, u16 phy_flags, unsigned long *et_mask) 2540 { 2541 enum ethtool_link_mode_bit_indices link_mode; 2542 enum bnxt_link_speed_indices speed; 2543 u8 bit; 2544 2545 for_each_set_bit(bit, &fw_mask, BNXT_FW_SPEED_MSK_BITS) { 2546 speed = bnxt_encoding_speed_idx(sig_mode, phy_flags, 1 << bit); 2547 if (!speed) 2548 continue; 2549 2550 link_mode = bnxt_link_modes[speed][sig_mode][media]; 2551 if (!link_mode) 2552 continue; 2553 2554 linkmode_set_bit(link_mode, et_mask); 2555 } 2556 } 2557 2558 static void 2559 bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media, 2560 u8 sig_mode, u16 phy_flags, unsigned long *et_mask) 2561 { 2562 if (media) { 2563 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags, 2564 et_mask); 2565 return; 2566 } 2567 2568 /* list speeds for all media if unknown */ 2569 for (media = 1; media < __BNXT_MEDIA_END; media++) 2570 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags, 2571 et_mask); 2572 } 2573 2574 static void 2575 bnxt_get_all_ethtool_support_speeds(struct bnxt_link_info *link_info, 2576 enum bnxt_media_type media, 2577 struct ethtool_link_ksettings *lk_ksettings) 2578 { 2579 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2580 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0; 2581 u16 phy_flags = bp->phy_flags; 2582 2583 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2584 sp_nrz = link_info->support_speeds2; 2585 sp_pam4 = link_info->support_speeds2; 2586 sp_pam4_112 = link_info->support_speeds2; 2587 } else { 2588 sp_nrz = link_info->support_speeds; 2589 sp_pam4 = link_info->support_pam4_speeds; 2590 } 2591 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags, 2592 lk_ksettings->link_modes.supported); 2593 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags, 2594 lk_ksettings->link_modes.supported); 2595 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112, 2596 phy_flags, lk_ksettings->link_modes.supported); 2597 } 2598 2599 static void 2600 bnxt_get_all_ethtool_adv_speeds(struct bnxt_link_info *link_info, 2601 enum bnxt_media_type media, 2602 struct ethtool_link_ksettings *lk_ksettings) 2603 { 2604 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2605 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0; 2606 u16 phy_flags = bp->phy_flags; 2607 2608 sp_nrz = link_info->advertising; 2609 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2610 sp_pam4 = link_info->advertising; 2611 sp_pam4_112 = link_info->advertising; 2612 } else { 2613 sp_pam4 = link_info->advertising_pam4; 2614 } 2615 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags, 2616 lk_ksettings->link_modes.advertising); 2617 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags, 2618 lk_ksettings->link_modes.advertising); 2619 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112, 2620 phy_flags, lk_ksettings->link_modes.advertising); 2621 } 2622 2623 static void 2624 bnxt_get_all_ethtool_lp_speeds(struct bnxt_link_info *link_info, 2625 enum bnxt_media_type media, 2626 struct ethtool_link_ksettings *lk_ksettings) 2627 { 2628 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2629 u16 phy_flags = bp->phy_flags; 2630 2631 bnxt_get_ethtool_speeds(link_info->lp_auto_link_speeds, media, 2632 BNXT_SIG_MODE_NRZ, phy_flags, 2633 lk_ksettings->link_modes.lp_advertising); 2634 bnxt_get_ethtool_speeds(link_info->lp_auto_pam4_link_speeds, media, 2635 BNXT_SIG_MODE_PAM4, phy_flags, 2636 lk_ksettings->link_modes.lp_advertising); 2637 } 2638 2639 static void bnxt_update_speed(u32 *delta, bool installed_media, u16 *speeds, 2640 u16 speed_msk, const unsigned long *et_mask, 2641 enum ethtool_link_mode_bit_indices mode) 2642 { 2643 bool mode_desired = linkmode_test_bit(mode, et_mask); 2644 2645 if (!mode) 2646 return; 2647 2648 /* enabled speeds for installed media should override */ 2649 if (installed_media && mode_desired) { 2650 *speeds |= speed_msk; 2651 *delta |= speed_msk; 2652 return; 2653 } 2654 2655 /* many to one mapping, only allow one change per fw_speed bit */ 2656 if (!(*delta & speed_msk) && (mode_desired == !(*speeds & speed_msk))) { 2657 *speeds ^= speed_msk; 2658 *delta |= speed_msk; 2659 } 2660 } 2661 2662 static void bnxt_set_ethtool_speeds(struct bnxt_link_info *link_info, 2663 const unsigned long *et_mask) 2664 { 2665 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2666 u16 const *sp_msks, *sp_pam4_msks, *sp_pam4_112_msks; 2667 enum bnxt_media_type media = bnxt_get_media(link_info); 2668 u16 *adv, *adv_pam4, *adv_pam4_112 = NULL; 2669 u32 delta_pam4_112 = 0; 2670 u32 delta_pam4 = 0; 2671 u32 delta_nrz = 0; 2672 int i, m; 2673 2674 adv = &link_info->advertising; 2675 if (bp->phy_flags & BNXT_PHY_FL_SPEEDS2) { 2676 adv_pam4 = &link_info->advertising; 2677 adv_pam4_112 = &link_info->advertising; 2678 sp_msks = bnxt_nrz_speeds2_masks; 2679 sp_pam4_msks = bnxt_pam4_speeds2_masks; 2680 sp_pam4_112_msks = bnxt_pam4_112_speeds2_masks; 2681 } else { 2682 adv_pam4 = &link_info->advertising_pam4; 2683 sp_msks = bnxt_nrz_speed_masks; 2684 sp_pam4_msks = bnxt_pam4_speed_masks; 2685 } 2686 for (i = 1; i < __BNXT_LINK_SPEED_END; i++) { 2687 /* accept any legal media from user */ 2688 for (m = 1; m < __BNXT_MEDIA_END; m++) { 2689 bnxt_update_speed(&delta_nrz, m == media, 2690 adv, sp_msks[i], et_mask, 2691 bnxt_link_modes[i][BNXT_SIG_MODE_NRZ][m]); 2692 bnxt_update_speed(&delta_pam4, m == media, 2693 adv_pam4, sp_pam4_msks[i], et_mask, 2694 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4][m]); 2695 if (!adv_pam4_112) 2696 continue; 2697 2698 bnxt_update_speed(&delta_pam4_112, m == media, 2699 adv_pam4_112, sp_pam4_112_msks[i], et_mask, 2700 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4_112][m]); 2701 } 2702 } 2703 } 2704 2705 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info, 2706 struct ethtool_link_ksettings *lk_ksettings) 2707 { 2708 u16 fec_cfg = link_info->fec_cfg; 2709 2710 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) { 2711 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 2712 lk_ksettings->link_modes.advertising); 2713 return; 2714 } 2715 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 2716 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 2717 lk_ksettings->link_modes.advertising); 2718 if (fec_cfg & BNXT_FEC_ENC_RS) 2719 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 2720 lk_ksettings->link_modes.advertising); 2721 if (fec_cfg & BNXT_FEC_ENC_LLRS) 2722 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 2723 lk_ksettings->link_modes.advertising); 2724 } 2725 2726 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info, 2727 struct ethtool_link_ksettings *lk_ksettings) 2728 { 2729 u16 fec_cfg = link_info->fec_cfg; 2730 2731 if (fec_cfg & BNXT_FEC_NONE) { 2732 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 2733 lk_ksettings->link_modes.supported); 2734 return; 2735 } 2736 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP) 2737 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 2738 lk_ksettings->link_modes.supported); 2739 if (fec_cfg & BNXT_FEC_ENC_RS_CAP) 2740 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 2741 lk_ksettings->link_modes.supported); 2742 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP) 2743 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 2744 lk_ksettings->link_modes.supported); 2745 } 2746 2747 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 2748 { 2749 switch (fw_link_speed) { 2750 case BNXT_LINK_SPEED_100MB: 2751 return SPEED_100; 2752 case BNXT_LINK_SPEED_1GB: 2753 return SPEED_1000; 2754 case BNXT_LINK_SPEED_2_5GB: 2755 return SPEED_2500; 2756 case BNXT_LINK_SPEED_10GB: 2757 return SPEED_10000; 2758 case BNXT_LINK_SPEED_20GB: 2759 return SPEED_20000; 2760 case BNXT_LINK_SPEED_25GB: 2761 return SPEED_25000; 2762 case BNXT_LINK_SPEED_40GB: 2763 return SPEED_40000; 2764 case BNXT_LINK_SPEED_50GB: 2765 case BNXT_LINK_SPEED_50GB_PAM4: 2766 return SPEED_50000; 2767 case BNXT_LINK_SPEED_100GB: 2768 case BNXT_LINK_SPEED_100GB_PAM4: 2769 case BNXT_LINK_SPEED_100GB_PAM4_112: 2770 return SPEED_100000; 2771 case BNXT_LINK_SPEED_200GB: 2772 case BNXT_LINK_SPEED_200GB_PAM4: 2773 case BNXT_LINK_SPEED_200GB_PAM4_112: 2774 return SPEED_200000; 2775 case BNXT_LINK_SPEED_400GB: 2776 case BNXT_LINK_SPEED_400GB_PAM4: 2777 case BNXT_LINK_SPEED_400GB_PAM4_112: 2778 return SPEED_400000; 2779 default: 2780 return SPEED_UNKNOWN; 2781 } 2782 } 2783 2784 static void bnxt_get_default_speeds(struct ethtool_link_ksettings *lk_ksettings, 2785 struct bnxt_link_info *link_info) 2786 { 2787 struct ethtool_link_settings *base = &lk_ksettings->base; 2788 2789 if (link_info->link_state == BNXT_LINK_STATE_UP) { 2790 base->speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 2791 base->duplex = DUPLEX_HALF; 2792 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2793 base->duplex = DUPLEX_FULL; 2794 lk_ksettings->lanes = link_info->active_lanes; 2795 } else if (!link_info->autoneg) { 2796 base->speed = bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 2797 base->duplex = DUPLEX_HALF; 2798 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 2799 base->duplex = DUPLEX_FULL; 2800 } 2801 } 2802 2803 static int bnxt_get_link_ksettings(struct net_device *dev, 2804 struct ethtool_link_ksettings *lk_ksettings) 2805 { 2806 struct ethtool_link_settings *base = &lk_ksettings->base; 2807 enum ethtool_link_mode_bit_indices link_mode; 2808 struct bnxt *bp = netdev_priv(dev); 2809 struct bnxt_link_info *link_info; 2810 enum bnxt_media_type media; 2811 2812 ethtool_link_ksettings_zero_link_mode(lk_ksettings, lp_advertising); 2813 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 2814 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 2815 base->duplex = DUPLEX_UNKNOWN; 2816 base->speed = SPEED_UNKNOWN; 2817 link_info = &bp->link_info; 2818 2819 mutex_lock(&bp->link_lock); 2820 bnxt_get_ethtool_modes(link_info, lk_ksettings); 2821 media = bnxt_get_media(link_info); 2822 bnxt_get_all_ethtool_support_speeds(link_info, media, lk_ksettings); 2823 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings); 2824 link_mode = bnxt_get_link_mode(link_info); 2825 if (link_mode != BNXT_LINK_MODE_UNKNOWN) 2826 ethtool_params_from_link_mode(lk_ksettings, link_mode); 2827 else 2828 bnxt_get_default_speeds(lk_ksettings, link_info); 2829 2830 if (link_info->autoneg) { 2831 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings); 2832 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2833 lk_ksettings->link_modes.advertising); 2834 base->autoneg = AUTONEG_ENABLE; 2835 bnxt_get_all_ethtool_adv_speeds(link_info, media, lk_ksettings); 2836 if (link_info->phy_link_status == BNXT_LINK_LINK) 2837 bnxt_get_all_ethtool_lp_speeds(link_info, media, 2838 lk_ksettings); 2839 } else { 2840 base->autoneg = AUTONEG_DISABLE; 2841 } 2842 2843 base->port = PORT_NONE; 2844 if (media == BNXT_MEDIA_TP) { 2845 base->port = PORT_TP; 2846 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2847 lk_ksettings->link_modes.supported); 2848 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2849 lk_ksettings->link_modes.advertising); 2850 } else if (media == BNXT_MEDIA_KR) { 2851 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, 2852 lk_ksettings->link_modes.supported); 2853 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, 2854 lk_ksettings->link_modes.advertising); 2855 } else { 2856 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 2857 lk_ksettings->link_modes.supported); 2858 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 2859 lk_ksettings->link_modes.advertising); 2860 2861 if (media == BNXT_MEDIA_CR) 2862 base->port = PORT_DA; 2863 else 2864 base->port = PORT_FIBRE; 2865 } 2866 base->phy_address = link_info->phy_addr; 2867 mutex_unlock(&bp->link_lock); 2868 2869 return 0; 2870 } 2871 2872 static int 2873 bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed, u32 lanes) 2874 { 2875 struct bnxt *bp = netdev_priv(dev); 2876 struct bnxt_link_info *link_info = &bp->link_info; 2877 u16 support_pam4_spds = link_info->support_pam4_speeds; 2878 u16 support_spds2 = link_info->support_speeds2; 2879 u16 support_spds = link_info->support_speeds; 2880 u8 sig_mode = BNXT_SIG_MODE_NRZ; 2881 u32 lanes_needed = 1; 2882 u16 fw_speed = 0; 2883 2884 switch (ethtool_speed) { 2885 case SPEED_100: 2886 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 2887 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB; 2888 break; 2889 case SPEED_1000: 2890 if ((support_spds & BNXT_LINK_SPEED_MSK_1GB) || 2891 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_1GB)) 2892 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 2893 break; 2894 case SPEED_2500: 2895 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 2896 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB; 2897 break; 2898 case SPEED_10000: 2899 if ((support_spds & BNXT_LINK_SPEED_MSK_10GB) || 2900 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_10GB)) 2901 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 2902 break; 2903 case SPEED_20000: 2904 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) { 2905 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB; 2906 lanes_needed = 2; 2907 } 2908 break; 2909 case SPEED_25000: 2910 if ((support_spds & BNXT_LINK_SPEED_MSK_25GB) || 2911 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_25GB)) 2912 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 2913 break; 2914 case SPEED_40000: 2915 if ((support_spds & BNXT_LINK_SPEED_MSK_40GB) || 2916 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_40GB)) { 2917 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 2918 lanes_needed = 4; 2919 } 2920 break; 2921 case SPEED_50000: 2922 if (((support_spds & BNXT_LINK_SPEED_MSK_50GB) || 2923 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB)) && 2924 lanes != 1) { 2925 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 2926 lanes_needed = 2; 2927 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) { 2928 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB; 2929 sig_mode = BNXT_SIG_MODE_PAM4; 2930 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB_PAM4) { 2931 fw_speed = BNXT_LINK_SPEED_50GB_PAM4; 2932 sig_mode = BNXT_SIG_MODE_PAM4; 2933 } 2934 break; 2935 case SPEED_100000: 2936 if (((support_spds & BNXT_LINK_SPEED_MSK_100GB) || 2937 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB)) && 2938 lanes != 2 && lanes != 1) { 2939 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB; 2940 lanes_needed = 4; 2941 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) { 2942 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB; 2943 sig_mode = BNXT_SIG_MODE_PAM4; 2944 lanes_needed = 2; 2945 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4) && 2946 lanes != 1) { 2947 fw_speed = BNXT_LINK_SPEED_100GB_PAM4; 2948 sig_mode = BNXT_SIG_MODE_PAM4; 2949 lanes_needed = 2; 2950 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112) { 2951 fw_speed = BNXT_LINK_SPEED_100GB_PAM4_112; 2952 sig_mode = BNXT_SIG_MODE_PAM4_112; 2953 } 2954 break; 2955 case SPEED_200000: 2956 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) { 2957 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB; 2958 sig_mode = BNXT_SIG_MODE_PAM4; 2959 lanes_needed = 4; 2960 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4) && 2961 lanes != 2) { 2962 fw_speed = BNXT_LINK_SPEED_200GB_PAM4; 2963 sig_mode = BNXT_SIG_MODE_PAM4; 2964 lanes_needed = 4; 2965 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112) { 2966 fw_speed = BNXT_LINK_SPEED_200GB_PAM4_112; 2967 sig_mode = BNXT_SIG_MODE_PAM4_112; 2968 lanes_needed = 2; 2969 } 2970 break; 2971 case SPEED_400000: 2972 if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4) && 2973 lanes != 4) { 2974 fw_speed = BNXT_LINK_SPEED_400GB_PAM4; 2975 sig_mode = BNXT_SIG_MODE_PAM4; 2976 lanes_needed = 8; 2977 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112) { 2978 fw_speed = BNXT_LINK_SPEED_400GB_PAM4_112; 2979 sig_mode = BNXT_SIG_MODE_PAM4_112; 2980 lanes_needed = 4; 2981 } 2982 break; 2983 } 2984 2985 if (!fw_speed) { 2986 netdev_err(dev, "unsupported speed!\n"); 2987 return -EINVAL; 2988 } 2989 2990 if (lanes && lanes != lanes_needed) { 2991 netdev_err(dev, "unsupported number of lanes for speed\n"); 2992 return -EINVAL; 2993 } 2994 2995 if (link_info->req_link_speed == fw_speed && 2996 link_info->req_signal_mode == sig_mode && 2997 link_info->autoneg == 0) 2998 return -EALREADY; 2999 3000 link_info->req_link_speed = fw_speed; 3001 link_info->req_signal_mode = sig_mode; 3002 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 3003 link_info->autoneg = 0; 3004 link_info->advertising = 0; 3005 link_info->advertising_pam4 = 0; 3006 3007 return 0; 3008 } 3009 3010 u16 bnxt_get_fw_auto_link_speeds(const unsigned long *mode) 3011 { 3012 u16 fw_speed_mask = 0; 3013 3014 if (linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode) || 3015 linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mode)) 3016 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 3017 3018 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode) || 3019 linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, mode)) 3020 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 3021 3022 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode)) 3023 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 3024 3025 if (linkmode_test_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode)) 3026 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 3027 3028 return fw_speed_mask; 3029 } 3030 3031 static int bnxt_set_link_ksettings(struct net_device *dev, 3032 const struct ethtool_link_ksettings *lk_ksettings) 3033 { 3034 struct bnxt *bp = netdev_priv(dev); 3035 struct bnxt_link_info *link_info = &bp->link_info; 3036 const struct ethtool_link_settings *base = &lk_ksettings->base; 3037 bool set_pause = false; 3038 u32 speed, lanes = 0; 3039 int rc = 0; 3040 3041 if (!BNXT_PHY_CFG_ABLE(bp)) 3042 return -EOPNOTSUPP; 3043 3044 mutex_lock(&bp->link_lock); 3045 if (base->autoneg == AUTONEG_ENABLE) { 3046 bnxt_set_ethtool_speeds(link_info, 3047 lk_ksettings->link_modes.advertising); 3048 link_info->autoneg |= BNXT_AUTONEG_SPEED; 3049 if (!link_info->advertising && !link_info->advertising_pam4) { 3050 link_info->advertising = link_info->support_auto_speeds; 3051 link_info->advertising_pam4 = 3052 link_info->support_pam4_auto_speeds; 3053 } 3054 /* any change to autoneg will cause link change, therefore the 3055 * driver should put back the original pause setting in autoneg 3056 */ 3057 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 3058 set_pause = true; 3059 } else { 3060 u8 phy_type = link_info->phy_type; 3061 3062 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 3063 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 3064 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 3065 netdev_err(dev, "10GBase-T devices must autoneg\n"); 3066 rc = -EINVAL; 3067 goto set_setting_exit; 3068 } 3069 if (base->duplex == DUPLEX_HALF) { 3070 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 3071 rc = -EINVAL; 3072 goto set_setting_exit; 3073 } 3074 speed = base->speed; 3075 lanes = lk_ksettings->lanes; 3076 rc = bnxt_force_link_speed(dev, speed, lanes); 3077 if (rc) { 3078 if (rc == -EALREADY) 3079 rc = 0; 3080 goto set_setting_exit; 3081 } 3082 } 3083 3084 if (netif_running(dev)) 3085 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 3086 3087 set_setting_exit: 3088 mutex_unlock(&bp->link_lock); 3089 return rc; 3090 } 3091 3092 static int bnxt_get_fecparam(struct net_device *dev, 3093 struct ethtool_fecparam *fec) 3094 { 3095 struct bnxt *bp = netdev_priv(dev); 3096 struct bnxt_link_info *link_info; 3097 u8 active_fec; 3098 u16 fec_cfg; 3099 3100 link_info = &bp->link_info; 3101 fec_cfg = link_info->fec_cfg; 3102 active_fec = link_info->active_fec_sig_mode & 3103 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK; 3104 if (fec_cfg & BNXT_FEC_NONE) { 3105 fec->fec = ETHTOOL_FEC_NONE; 3106 fec->active_fec = ETHTOOL_FEC_NONE; 3107 return 0; 3108 } 3109 if (fec_cfg & BNXT_FEC_AUTONEG) 3110 fec->fec |= ETHTOOL_FEC_AUTO; 3111 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 3112 fec->fec |= ETHTOOL_FEC_BASER; 3113 if (fec_cfg & BNXT_FEC_ENC_RS) 3114 fec->fec |= ETHTOOL_FEC_RS; 3115 if (fec_cfg & BNXT_FEC_ENC_LLRS) 3116 fec->fec |= ETHTOOL_FEC_LLRS; 3117 3118 switch (active_fec) { 3119 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE: 3120 fec->active_fec |= ETHTOOL_FEC_BASER; 3121 break; 3122 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE: 3123 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE: 3124 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE: 3125 fec->active_fec |= ETHTOOL_FEC_RS; 3126 break; 3127 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE: 3128 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE: 3129 fec->active_fec |= ETHTOOL_FEC_LLRS; 3130 break; 3131 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE: 3132 fec->active_fec |= ETHTOOL_FEC_OFF; 3133 break; 3134 } 3135 return 0; 3136 } 3137 3138 static void bnxt_get_fec_stats(struct net_device *dev, 3139 struct ethtool_fec_stats *fec_stats) 3140 { 3141 struct bnxt *bp = netdev_priv(dev); 3142 u64 *rx; 3143 3144 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 3145 return; 3146 3147 rx = bp->rx_port_stats_ext.sw_stats; 3148 fec_stats->corrected_bits.total = 3149 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits)); 3150 3151 if (bp->fw_rx_stats_ext_size <= BNXT_RX_STATS_EXT_NUM_LEGACY) 3152 return; 3153 3154 fec_stats->corrected_blocks.total = 3155 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)); 3156 fec_stats->uncorrectable_blocks.total = 3157 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_uncorrectable_blocks)); 3158 } 3159 3160 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info, 3161 u32 fec) 3162 { 3163 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE; 3164 3165 if (fec & ETHTOOL_FEC_BASER) 3166 fw_fec |= BNXT_FEC_BASE_R_ON(link_info); 3167 else if (fec & ETHTOOL_FEC_RS) 3168 fw_fec |= BNXT_FEC_RS_ON(link_info); 3169 else if (fec & ETHTOOL_FEC_LLRS) 3170 fw_fec |= BNXT_FEC_LLRS_ON; 3171 return fw_fec; 3172 } 3173 3174 static int bnxt_set_fecparam(struct net_device *dev, 3175 struct ethtool_fecparam *fecparam) 3176 { 3177 struct hwrm_port_phy_cfg_input *req; 3178 struct bnxt *bp = netdev_priv(dev); 3179 struct bnxt_link_info *link_info; 3180 u32 new_cfg, fec = fecparam->fec; 3181 u16 fec_cfg; 3182 int rc; 3183 3184 link_info = &bp->link_info; 3185 fec_cfg = link_info->fec_cfg; 3186 if (fec_cfg & BNXT_FEC_NONE) 3187 return -EOPNOTSUPP; 3188 3189 if (fec & ETHTOOL_FEC_OFF) { 3190 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE | 3191 BNXT_FEC_ALL_OFF(link_info); 3192 goto apply_fec; 3193 } 3194 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) || 3195 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) || 3196 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) || 3197 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP))) 3198 return -EINVAL; 3199 3200 if (fec & ETHTOOL_FEC_AUTO) { 3201 if (!link_info->autoneg) 3202 return -EINVAL; 3203 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE; 3204 } else { 3205 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec); 3206 } 3207 3208 apply_fec: 3209 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 3210 if (rc) 3211 return rc; 3212 req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 3213 rc = hwrm_req_send(bp, req); 3214 /* update current settings */ 3215 if (!rc) { 3216 mutex_lock(&bp->link_lock); 3217 bnxt_update_link(bp, false); 3218 mutex_unlock(&bp->link_lock); 3219 } 3220 return rc; 3221 } 3222 3223 static void bnxt_get_pauseparam(struct net_device *dev, 3224 struct ethtool_pauseparam *epause) 3225 { 3226 struct bnxt *bp = netdev_priv(dev); 3227 struct bnxt_link_info *link_info = &bp->link_info; 3228 3229 if (BNXT_VF(bp)) 3230 return; 3231 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 3232 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 3233 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 3234 } 3235 3236 static void bnxt_get_pause_stats(struct net_device *dev, 3237 struct ethtool_pause_stats *epstat) 3238 { 3239 struct bnxt *bp = netdev_priv(dev); 3240 u64 *rx, *tx; 3241 3242 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 3243 return; 3244 3245 rx = bp->port_stats.sw_stats; 3246 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 3247 3248 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames); 3249 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames); 3250 } 3251 3252 static int bnxt_set_pauseparam(struct net_device *dev, 3253 struct ethtool_pauseparam *epause) 3254 { 3255 int rc = 0; 3256 struct bnxt *bp = netdev_priv(dev); 3257 struct bnxt_link_info *link_info = &bp->link_info; 3258 3259 if (!BNXT_PHY_CFG_ABLE(bp) || (bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 3260 return -EOPNOTSUPP; 3261 3262 mutex_lock(&bp->link_lock); 3263 if (epause->autoneg) { 3264 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 3265 rc = -EINVAL; 3266 goto pause_exit; 3267 } 3268 3269 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 3270 link_info->req_flow_ctrl = 0; 3271 } else { 3272 /* when transition from auto pause to force pause, 3273 * force a link change 3274 */ 3275 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 3276 link_info->force_link_chng = true; 3277 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 3278 link_info->req_flow_ctrl = 0; 3279 } 3280 if (epause->rx_pause) 3281 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 3282 3283 if (epause->tx_pause) 3284 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 3285 3286 if (netif_running(dev)) 3287 rc = bnxt_hwrm_set_pause(bp); 3288 3289 pause_exit: 3290 mutex_unlock(&bp->link_lock); 3291 return rc; 3292 } 3293 3294 static u32 bnxt_get_link(struct net_device *dev) 3295 { 3296 struct bnxt *bp = netdev_priv(dev); 3297 3298 /* TODO: handle MF, VF, driver close case */ 3299 return BNXT_LINK_IS_UP(bp); 3300 } 3301 3302 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp, 3303 struct hwrm_nvm_get_dev_info_output *nvm_dev_info) 3304 { 3305 struct hwrm_nvm_get_dev_info_output *resp; 3306 struct hwrm_nvm_get_dev_info_input *req; 3307 int rc; 3308 3309 if (BNXT_VF(bp)) 3310 return -EOPNOTSUPP; 3311 3312 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO); 3313 if (rc) 3314 return rc; 3315 3316 resp = hwrm_req_hold(bp, req); 3317 rc = hwrm_req_send(bp, req); 3318 if (!rc) 3319 memcpy(nvm_dev_info, resp, sizeof(*resp)); 3320 hwrm_req_drop(bp, req); 3321 return rc; 3322 } 3323 3324 static void bnxt_print_admin_err(struct bnxt *bp) 3325 { 3326 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 3327 } 3328 3329 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 3330 u16 ext, u16 *index, u32 *item_length, 3331 u32 *data_length); 3332 3333 int bnxt_flash_nvram(struct net_device *dev, u16 dir_type, 3334 u16 dir_ordinal, u16 dir_ext, u16 dir_attr, 3335 u32 dir_item_len, const u8 *data, 3336 size_t data_len) 3337 { 3338 struct bnxt *bp = netdev_priv(dev); 3339 struct hwrm_nvm_write_input *req; 3340 int rc; 3341 3342 rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE); 3343 if (rc) 3344 return rc; 3345 3346 if (data_len && data) { 3347 dma_addr_t dma_handle; 3348 u8 *kmem; 3349 3350 kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle); 3351 if (!kmem) { 3352 hwrm_req_drop(bp, req); 3353 return -ENOMEM; 3354 } 3355 3356 req->dir_data_length = cpu_to_le32(data_len); 3357 3358 memcpy(kmem, data, data_len); 3359 req->host_src_addr = cpu_to_le64(dma_handle); 3360 } 3361 3362 hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout); 3363 req->dir_type = cpu_to_le16(dir_type); 3364 req->dir_ordinal = cpu_to_le16(dir_ordinal); 3365 req->dir_ext = cpu_to_le16(dir_ext); 3366 req->dir_attr = cpu_to_le16(dir_attr); 3367 req->dir_item_length = cpu_to_le32(dir_item_len); 3368 rc = hwrm_req_send(bp, req); 3369 3370 if (rc == -EACCES) 3371 bnxt_print_admin_err(bp); 3372 return rc; 3373 } 3374 3375 int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type, 3376 u8 self_reset, u8 flags) 3377 { 3378 struct bnxt *bp = netdev_priv(dev); 3379 struct hwrm_fw_reset_input *req; 3380 int rc; 3381 3382 if (!bnxt_hwrm_reset_permitted(bp)) { 3383 netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver"); 3384 return -EPERM; 3385 } 3386 3387 rc = hwrm_req_init(bp, req, HWRM_FW_RESET); 3388 if (rc) 3389 return rc; 3390 3391 req->embedded_proc_type = proc_type; 3392 req->selfrst_status = self_reset; 3393 req->flags = flags; 3394 3395 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) { 3396 rc = hwrm_req_send_silent(bp, req); 3397 } else { 3398 rc = hwrm_req_send(bp, req); 3399 if (rc == -EACCES) 3400 bnxt_print_admin_err(bp); 3401 } 3402 return rc; 3403 } 3404 3405 static int bnxt_firmware_reset(struct net_device *dev, 3406 enum bnxt_nvm_directory_type dir_type) 3407 { 3408 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE; 3409 u8 proc_type, flags = 0; 3410 3411 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 3412 /* (e.g. when firmware isn't already running) */ 3413 switch (dir_type) { 3414 case BNX_DIR_TYPE_CHIMP_PATCH: 3415 case BNX_DIR_TYPE_BOOTCODE: 3416 case BNX_DIR_TYPE_BOOTCODE_2: 3417 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 3418 /* Self-reset ChiMP upon next PCIe reset: */ 3419 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 3420 break; 3421 case BNX_DIR_TYPE_APE_FW: 3422 case BNX_DIR_TYPE_APE_PATCH: 3423 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 3424 /* Self-reset APE upon next PCIe reset: */ 3425 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 3426 break; 3427 case BNX_DIR_TYPE_KONG_FW: 3428 case BNX_DIR_TYPE_KONG_PATCH: 3429 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 3430 break; 3431 case BNX_DIR_TYPE_BONO_FW: 3432 case BNX_DIR_TYPE_BONO_PATCH: 3433 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 3434 break; 3435 default: 3436 return -EINVAL; 3437 } 3438 3439 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags); 3440 } 3441 3442 static int bnxt_firmware_reset_chip(struct net_device *dev) 3443 { 3444 struct bnxt *bp = netdev_priv(dev); 3445 u8 flags = 0; 3446 3447 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 3448 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 3449 3450 return bnxt_hwrm_firmware_reset(dev, 3451 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP, 3452 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP, 3453 flags); 3454 } 3455 3456 static int bnxt_firmware_reset_ap(struct net_device *dev) 3457 { 3458 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP, 3459 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE, 3460 0); 3461 } 3462 3463 static int bnxt_flash_firmware(struct net_device *dev, 3464 u16 dir_type, 3465 const u8 *fw_data, 3466 size_t fw_size) 3467 { 3468 int rc = 0; 3469 u16 code_type; 3470 u32 stored_crc; 3471 u32 calculated_crc; 3472 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 3473 3474 switch (dir_type) { 3475 case BNX_DIR_TYPE_BOOTCODE: 3476 case BNX_DIR_TYPE_BOOTCODE_2: 3477 code_type = CODE_BOOT; 3478 break; 3479 case BNX_DIR_TYPE_CHIMP_PATCH: 3480 code_type = CODE_CHIMP_PATCH; 3481 break; 3482 case BNX_DIR_TYPE_APE_FW: 3483 code_type = CODE_MCTP_PASSTHRU; 3484 break; 3485 case BNX_DIR_TYPE_APE_PATCH: 3486 code_type = CODE_APE_PATCH; 3487 break; 3488 case BNX_DIR_TYPE_KONG_FW: 3489 code_type = CODE_KONG_FW; 3490 break; 3491 case BNX_DIR_TYPE_KONG_PATCH: 3492 code_type = CODE_KONG_PATCH; 3493 break; 3494 case BNX_DIR_TYPE_BONO_FW: 3495 code_type = CODE_BONO_FW; 3496 break; 3497 case BNX_DIR_TYPE_BONO_PATCH: 3498 code_type = CODE_BONO_PATCH; 3499 break; 3500 default: 3501 netdev_err(dev, "Unsupported directory entry type: %u\n", 3502 dir_type); 3503 return -EINVAL; 3504 } 3505 if (fw_size < sizeof(struct bnxt_fw_header)) { 3506 netdev_err(dev, "Invalid firmware file size: %u\n", 3507 (unsigned int)fw_size); 3508 return -EINVAL; 3509 } 3510 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 3511 netdev_err(dev, "Invalid firmware signature: %08X\n", 3512 le32_to_cpu(header->signature)); 3513 return -EINVAL; 3514 } 3515 if (header->code_type != code_type) { 3516 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 3517 code_type, header->code_type); 3518 return -EINVAL; 3519 } 3520 if (header->device != DEVICE_CUMULUS_FAMILY) { 3521 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 3522 DEVICE_CUMULUS_FAMILY, header->device); 3523 return -EINVAL; 3524 } 3525 /* Confirm the CRC32 checksum of the file: */ 3526 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 3527 sizeof(stored_crc))); 3528 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 3529 if (calculated_crc != stored_crc) { 3530 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 3531 (unsigned long)stored_crc, 3532 (unsigned long)calculated_crc); 3533 return -EINVAL; 3534 } 3535 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3536 0, 0, 0, fw_data, fw_size); 3537 if (rc == 0) /* Firmware update successful */ 3538 rc = bnxt_firmware_reset(dev, dir_type); 3539 3540 return rc; 3541 } 3542 3543 static int bnxt_flash_microcode(struct net_device *dev, 3544 u16 dir_type, 3545 const u8 *fw_data, 3546 size_t fw_size) 3547 { 3548 struct bnxt_ucode_trailer *trailer; 3549 u32 calculated_crc; 3550 u32 stored_crc; 3551 int rc = 0; 3552 3553 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 3554 netdev_err(dev, "Invalid microcode file size: %u\n", 3555 (unsigned int)fw_size); 3556 return -EINVAL; 3557 } 3558 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 3559 sizeof(*trailer))); 3560 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 3561 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 3562 le32_to_cpu(trailer->sig)); 3563 return -EINVAL; 3564 } 3565 if (le16_to_cpu(trailer->dir_type) != dir_type) { 3566 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 3567 dir_type, le16_to_cpu(trailer->dir_type)); 3568 return -EINVAL; 3569 } 3570 if (le16_to_cpu(trailer->trailer_length) < 3571 sizeof(struct bnxt_ucode_trailer)) { 3572 netdev_err(dev, "Invalid microcode trailer length: %d\n", 3573 le16_to_cpu(trailer->trailer_length)); 3574 return -EINVAL; 3575 } 3576 3577 /* Confirm the CRC32 checksum of the file: */ 3578 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 3579 sizeof(stored_crc))); 3580 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 3581 if (calculated_crc != stored_crc) { 3582 netdev_err(dev, 3583 "CRC32 (%08lX) does not match calculated: %08lX\n", 3584 (unsigned long)stored_crc, 3585 (unsigned long)calculated_crc); 3586 return -EINVAL; 3587 } 3588 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3589 0, 0, 0, fw_data, fw_size); 3590 3591 return rc; 3592 } 3593 3594 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 3595 { 3596 switch (dir_type) { 3597 case BNX_DIR_TYPE_CHIMP_PATCH: 3598 case BNX_DIR_TYPE_BOOTCODE: 3599 case BNX_DIR_TYPE_BOOTCODE_2: 3600 case BNX_DIR_TYPE_APE_FW: 3601 case BNX_DIR_TYPE_APE_PATCH: 3602 case BNX_DIR_TYPE_KONG_FW: 3603 case BNX_DIR_TYPE_KONG_PATCH: 3604 case BNX_DIR_TYPE_BONO_FW: 3605 case BNX_DIR_TYPE_BONO_PATCH: 3606 return true; 3607 } 3608 3609 return false; 3610 } 3611 3612 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 3613 { 3614 switch (dir_type) { 3615 case BNX_DIR_TYPE_AVS: 3616 case BNX_DIR_TYPE_EXP_ROM_MBA: 3617 case BNX_DIR_TYPE_PCIE: 3618 case BNX_DIR_TYPE_TSCF_UCODE: 3619 case BNX_DIR_TYPE_EXT_PHY: 3620 case BNX_DIR_TYPE_CCM: 3621 case BNX_DIR_TYPE_ISCSI_BOOT: 3622 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 3623 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 3624 return true; 3625 } 3626 3627 return false; 3628 } 3629 3630 static bool bnxt_dir_type_is_executable(u16 dir_type) 3631 { 3632 return bnxt_dir_type_is_ape_bin_format(dir_type) || 3633 bnxt_dir_type_is_other_exec_format(dir_type); 3634 } 3635 3636 static int bnxt_flash_firmware_from_file(struct net_device *dev, 3637 u16 dir_type, 3638 const char *filename) 3639 { 3640 const struct firmware *fw; 3641 int rc; 3642 3643 rc = request_firmware(&fw, filename, &dev->dev); 3644 if (rc != 0) { 3645 netdev_err(dev, "Error %d requesting firmware file: %s\n", 3646 rc, filename); 3647 return rc; 3648 } 3649 if (bnxt_dir_type_is_ape_bin_format(dir_type)) 3650 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 3651 else if (bnxt_dir_type_is_other_exec_format(dir_type)) 3652 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 3653 else 3654 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3655 0, 0, 0, fw->data, fw->size); 3656 release_firmware(fw); 3657 return rc; 3658 } 3659 3660 #define MSG_INTEGRITY_ERR "PKG install error : Data integrity on NVM" 3661 #define MSG_INVALID_PKG "PKG install error : Invalid package" 3662 #define MSG_AUTHENTICATION_ERR "PKG install error : Authentication error" 3663 #define MSG_INVALID_DEV "PKG install error : Invalid device" 3664 #define MSG_INTERNAL_ERR "PKG install error : Internal error" 3665 #define MSG_NO_PKG_UPDATE_AREA_ERR "PKG update area not created in nvram" 3666 #define MSG_NO_SPACE_ERR "PKG insufficient update area in nvram" 3667 #define MSG_RESIZE_UPDATE_ERR "Resize UPDATE entry error" 3668 #define MSG_ANTI_ROLLBACK_ERR "HWRM_NVM_INSTALL_UPDATE failure due to Anti-rollback detected" 3669 #define MSG_GENERIC_FAILURE_ERR "HWRM_NVM_INSTALL_UPDATE failure" 3670 3671 static int nvm_update_err_to_stderr(struct net_device *dev, u8 result, 3672 struct netlink_ext_ack *extack) 3673 { 3674 switch (result) { 3675 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER: 3676 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER: 3677 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR: 3678 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR: 3679 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND: 3680 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED: 3681 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTEGRITY_ERR); 3682 return -EINVAL; 3683 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE: 3684 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER: 3685 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE: 3686 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM: 3687 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH: 3688 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST: 3689 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER: 3690 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM: 3691 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM: 3692 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH: 3693 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE: 3694 case NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM: 3695 case NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM: 3696 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_PKG); 3697 return -ENOPKG; 3698 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR: 3699 BNXT_NVM_ERR_MSG(dev, extack, MSG_AUTHENTICATION_ERR); 3700 return -EPERM; 3701 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV: 3702 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID: 3703 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR: 3704 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID: 3705 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM: 3706 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_DEV); 3707 return -EOPNOTSUPP; 3708 default: 3709 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTERNAL_ERR); 3710 return -EIO; 3711 } 3712 } 3713 3714 #define BNXT_PKG_DMA_SIZE 0x40000 3715 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE)) 3716 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST)) 3717 3718 static int bnxt_resize_update_entry(struct net_device *dev, size_t fw_size, 3719 struct netlink_ext_ack *extack) 3720 { 3721 u32 item_len; 3722 int rc; 3723 3724 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 3725 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, NULL, 3726 &item_len, NULL); 3727 if (rc) { 3728 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 3729 return rc; 3730 } 3731 3732 if (fw_size > item_len) { 3733 rc = bnxt_flash_nvram(dev, BNX_DIR_TYPE_UPDATE, 3734 BNX_DIR_ORDINAL_FIRST, 0, 1, 3735 round_up(fw_size, 4096), NULL, 0); 3736 if (rc) { 3737 BNXT_NVM_ERR_MSG(dev, extack, MSG_RESIZE_UPDATE_ERR); 3738 return rc; 3739 } 3740 } 3741 return 0; 3742 } 3743 3744 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw, 3745 u32 install_type, struct netlink_ext_ack *extack) 3746 { 3747 struct hwrm_nvm_install_update_input *install; 3748 struct hwrm_nvm_install_update_output *resp; 3749 struct hwrm_nvm_modify_input *modify; 3750 struct bnxt *bp = netdev_priv(dev); 3751 bool defrag_attempted = false; 3752 dma_addr_t dma_handle; 3753 u8 *kmem = NULL; 3754 u32 modify_len; 3755 u32 item_len; 3756 u8 cmd_err; 3757 u16 index; 3758 int rc; 3759 3760 /* resize before flashing larger image than available space */ 3761 rc = bnxt_resize_update_entry(dev, fw->size, extack); 3762 if (rc) 3763 return rc; 3764 3765 bnxt_hwrm_fw_set_time(bp); 3766 3767 rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY); 3768 if (rc) 3769 return rc; 3770 3771 /* Try allocating a large DMA buffer first. Older fw will 3772 * cause excessive NVRAM erases when using small blocks. 3773 */ 3774 modify_len = roundup_pow_of_two(fw->size); 3775 modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE); 3776 while (1) { 3777 kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle); 3778 if (!kmem && modify_len > PAGE_SIZE) 3779 modify_len /= 2; 3780 else 3781 break; 3782 } 3783 if (!kmem) { 3784 hwrm_req_drop(bp, modify); 3785 return -ENOMEM; 3786 } 3787 3788 rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE); 3789 if (rc) { 3790 hwrm_req_drop(bp, modify); 3791 return rc; 3792 } 3793 3794 hwrm_req_timeout(bp, modify, bp->hwrm_cmd_max_timeout); 3795 hwrm_req_timeout(bp, install, bp->hwrm_cmd_max_timeout); 3796 3797 hwrm_req_hold(bp, modify); 3798 modify->host_src_addr = cpu_to_le64(dma_handle); 3799 3800 resp = hwrm_req_hold(bp, install); 3801 if ((install_type & 0xffff) == 0) 3802 install_type >>= 16; 3803 install->install_type = cpu_to_le32(install_type); 3804 3805 do { 3806 u32 copied = 0, len = modify_len; 3807 3808 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 3809 BNX_DIR_ORDINAL_FIRST, 3810 BNX_DIR_EXT_NONE, 3811 &index, &item_len, NULL); 3812 if (rc) { 3813 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 3814 break; 3815 } 3816 if (fw->size > item_len) { 3817 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_SPACE_ERR); 3818 rc = -EFBIG; 3819 break; 3820 } 3821 3822 modify->dir_idx = cpu_to_le16(index); 3823 3824 if (fw->size > modify_len) 3825 modify->flags = BNXT_NVM_MORE_FLAG; 3826 while (copied < fw->size) { 3827 u32 balance = fw->size - copied; 3828 3829 if (balance <= modify_len) { 3830 len = balance; 3831 if (copied) 3832 modify->flags |= BNXT_NVM_LAST_FLAG; 3833 } 3834 memcpy(kmem, fw->data + copied, len); 3835 modify->len = cpu_to_le32(len); 3836 modify->offset = cpu_to_le32(copied); 3837 rc = hwrm_req_send(bp, modify); 3838 if (rc) 3839 goto pkg_abort; 3840 copied += len; 3841 } 3842 3843 rc = hwrm_req_send_silent(bp, install); 3844 if (!rc) 3845 break; 3846 3847 if (defrag_attempted) { 3848 /* We have tried to defragment already in the previous 3849 * iteration. Return with the result for INSTALL_UPDATE 3850 */ 3851 break; 3852 } 3853 3854 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 3855 3856 switch (cmd_err) { 3857 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK: 3858 BNXT_NVM_ERR_MSG(dev, extack, MSG_ANTI_ROLLBACK_ERR); 3859 rc = -EALREADY; 3860 break; 3861 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR: 3862 install->flags = 3863 cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 3864 3865 rc = hwrm_req_send_silent(bp, install); 3866 if (!rc) 3867 break; 3868 3869 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 3870 3871 if (cmd_err == NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) { 3872 /* FW has cleared NVM area, driver will create 3873 * UPDATE directory and try the flash again 3874 */ 3875 defrag_attempted = true; 3876 install->flags = 0; 3877 rc = bnxt_flash_nvram(bp->dev, 3878 BNX_DIR_TYPE_UPDATE, 3879 BNX_DIR_ORDINAL_FIRST, 3880 0, 0, item_len, NULL, 0); 3881 if (!rc) 3882 break; 3883 } 3884 fallthrough; 3885 default: 3886 BNXT_NVM_ERR_MSG(dev, extack, MSG_GENERIC_FAILURE_ERR); 3887 } 3888 } while (defrag_attempted && !rc); 3889 3890 pkg_abort: 3891 hwrm_req_drop(bp, modify); 3892 hwrm_req_drop(bp, install); 3893 3894 if (resp->result) { 3895 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 3896 (s8)resp->result, (int)resp->problem_item); 3897 rc = nvm_update_err_to_stderr(dev, resp->result, extack); 3898 } 3899 if (rc == -EACCES) 3900 bnxt_print_admin_err(bp); 3901 return rc; 3902 } 3903 3904 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename, 3905 u32 install_type, struct netlink_ext_ack *extack) 3906 { 3907 const struct firmware *fw; 3908 int rc; 3909 3910 rc = request_firmware(&fw, filename, &dev->dev); 3911 if (rc != 0) { 3912 netdev_err(dev, "PKG error %d requesting file: %s\n", 3913 rc, filename); 3914 return rc; 3915 } 3916 3917 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type, extack); 3918 3919 release_firmware(fw); 3920 3921 return rc; 3922 } 3923 3924 static int bnxt_flash_device(struct net_device *dev, 3925 struct ethtool_flash *flash) 3926 { 3927 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 3928 netdev_err(dev, "flashdev not supported from a virtual function\n"); 3929 return -EINVAL; 3930 } 3931 3932 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 3933 flash->region > 0xffff) 3934 return bnxt_flash_package_from_file(dev, flash->data, 3935 flash->region, NULL); 3936 3937 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 3938 } 3939 3940 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 3941 { 3942 struct hwrm_nvm_get_dir_info_output *output; 3943 struct hwrm_nvm_get_dir_info_input *req; 3944 struct bnxt *bp = netdev_priv(dev); 3945 int rc; 3946 3947 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO); 3948 if (rc) 3949 return rc; 3950 3951 output = hwrm_req_hold(bp, req); 3952 rc = hwrm_req_send(bp, req); 3953 if (!rc) { 3954 *entries = le32_to_cpu(output->entries); 3955 *length = le32_to_cpu(output->entry_length); 3956 } 3957 hwrm_req_drop(bp, req); 3958 return rc; 3959 } 3960 3961 static int bnxt_get_eeprom_len(struct net_device *dev) 3962 { 3963 struct bnxt *bp = netdev_priv(dev); 3964 3965 if (BNXT_VF(bp)) 3966 return 0; 3967 3968 /* The -1 return value allows the entire 32-bit range of offsets to be 3969 * passed via the ethtool command-line utility. 3970 */ 3971 return -1; 3972 } 3973 3974 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 3975 { 3976 struct bnxt *bp = netdev_priv(dev); 3977 int rc; 3978 u32 dir_entries; 3979 u32 entry_length; 3980 u8 *buf; 3981 size_t buflen; 3982 dma_addr_t dma_handle; 3983 struct hwrm_nvm_get_dir_entries_input *req; 3984 3985 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 3986 if (rc != 0) 3987 return rc; 3988 3989 if (!dir_entries || !entry_length) 3990 return -EIO; 3991 3992 /* Insert 2 bytes of directory info (count and size of entries) */ 3993 if (len < 2) 3994 return -EINVAL; 3995 3996 *data++ = dir_entries; 3997 *data++ = entry_length; 3998 len -= 2; 3999 memset(data, 0xff, len); 4000 4001 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES); 4002 if (rc) 4003 return rc; 4004 4005 buflen = mul_u32_u32(dir_entries, entry_length); 4006 buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle); 4007 if (!buf) { 4008 hwrm_req_drop(bp, req); 4009 return -ENOMEM; 4010 } 4011 req->host_dest_addr = cpu_to_le64(dma_handle); 4012 4013 hwrm_req_hold(bp, req); /* hold the slice */ 4014 rc = hwrm_req_send(bp, req); 4015 if (rc == 0) 4016 memcpy(data, buf, len > buflen ? buflen : len); 4017 hwrm_req_drop(bp, req); 4018 return rc; 4019 } 4020 4021 int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 4022 u32 length, u8 *data) 4023 { 4024 struct bnxt *bp = netdev_priv(dev); 4025 int rc; 4026 u8 *buf; 4027 dma_addr_t dma_handle; 4028 struct hwrm_nvm_read_input *req; 4029 4030 if (!length) 4031 return -EINVAL; 4032 4033 rc = hwrm_req_init(bp, req, HWRM_NVM_READ); 4034 if (rc) 4035 return rc; 4036 4037 buf = hwrm_req_dma_slice(bp, req, length, &dma_handle); 4038 if (!buf) { 4039 hwrm_req_drop(bp, req); 4040 return -ENOMEM; 4041 } 4042 4043 req->host_dest_addr = cpu_to_le64(dma_handle); 4044 req->dir_idx = cpu_to_le16(index); 4045 req->offset = cpu_to_le32(offset); 4046 req->len = cpu_to_le32(length); 4047 4048 hwrm_req_hold(bp, req); /* hold the slice */ 4049 rc = hwrm_req_send(bp, req); 4050 if (rc == 0) 4051 memcpy(data, buf, length); 4052 hwrm_req_drop(bp, req); 4053 return rc; 4054 } 4055 4056 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 4057 u16 ext, u16 *index, u32 *item_length, 4058 u32 *data_length) 4059 { 4060 struct hwrm_nvm_find_dir_entry_output *output; 4061 struct hwrm_nvm_find_dir_entry_input *req; 4062 struct bnxt *bp = netdev_priv(dev); 4063 int rc; 4064 4065 rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY); 4066 if (rc) 4067 return rc; 4068 4069 req->enables = 0; 4070 req->dir_idx = 0; 4071 req->dir_type = cpu_to_le16(type); 4072 req->dir_ordinal = cpu_to_le16(ordinal); 4073 req->dir_ext = cpu_to_le16(ext); 4074 req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 4075 output = hwrm_req_hold(bp, req); 4076 rc = hwrm_req_send_silent(bp, req); 4077 if (rc == 0) { 4078 if (index) 4079 *index = le16_to_cpu(output->dir_idx); 4080 if (item_length) 4081 *item_length = le32_to_cpu(output->dir_item_length); 4082 if (data_length) 4083 *data_length = le32_to_cpu(output->dir_data_length); 4084 } 4085 hwrm_req_drop(bp, req); 4086 return rc; 4087 } 4088 4089 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 4090 { 4091 char *retval = NULL; 4092 char *p; 4093 char *value; 4094 int field = 0; 4095 4096 if (datalen < 1) 4097 return NULL; 4098 /* null-terminate the log data (removing last '\n'): */ 4099 data[datalen - 1] = 0; 4100 for (p = data; *p != 0; p++) { 4101 field = 0; 4102 retval = NULL; 4103 while (*p != 0 && *p != '\n') { 4104 value = p; 4105 while (*p != 0 && *p != '\t' && *p != '\n') 4106 p++; 4107 if (field == desired_field) 4108 retval = value; 4109 if (*p != '\t') 4110 break; 4111 *p = 0; 4112 field++; 4113 p++; 4114 } 4115 if (*p == 0) 4116 break; 4117 *p = 0; 4118 } 4119 return retval; 4120 } 4121 4122 int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size) 4123 { 4124 struct bnxt *bp = netdev_priv(dev); 4125 u16 index = 0; 4126 char *pkgver; 4127 u32 pkglen; 4128 u8 *pkgbuf; 4129 int rc; 4130 4131 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 4132 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 4133 &index, NULL, &pkglen); 4134 if (rc) 4135 return rc; 4136 4137 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 4138 if (!pkgbuf) { 4139 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 4140 pkglen); 4141 return -ENOMEM; 4142 } 4143 4144 rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf); 4145 if (rc) 4146 goto err; 4147 4148 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 4149 pkglen); 4150 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) 4151 strscpy(ver, pkgver, size); 4152 else 4153 rc = -ENOENT; 4154 4155 err: 4156 kfree(pkgbuf); 4157 4158 return rc; 4159 } 4160 4161 static void bnxt_get_pkgver(struct net_device *dev) 4162 { 4163 struct bnxt *bp = netdev_priv(dev); 4164 char buf[FW_VER_STR_LEN]; 4165 int len; 4166 4167 if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) { 4168 len = strlen(bp->fw_ver_str); 4169 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len, 4170 "/pkg %s", buf); 4171 } 4172 } 4173 4174 static int bnxt_get_eeprom(struct net_device *dev, 4175 struct ethtool_eeprom *eeprom, 4176 u8 *data) 4177 { 4178 u32 index; 4179 u32 offset; 4180 4181 if (eeprom->offset == 0) /* special offset value to get directory */ 4182 return bnxt_get_nvram_directory(dev, eeprom->len, data); 4183 4184 index = eeprom->offset >> 24; 4185 offset = eeprom->offset & 0xffffff; 4186 4187 if (index == 0) { 4188 netdev_err(dev, "unsupported index value: %d\n", index); 4189 return -EINVAL; 4190 } 4191 4192 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 4193 } 4194 4195 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 4196 { 4197 struct hwrm_nvm_erase_dir_entry_input *req; 4198 struct bnxt *bp = netdev_priv(dev); 4199 int rc; 4200 4201 rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY); 4202 if (rc) 4203 return rc; 4204 4205 req->dir_idx = cpu_to_le16(index); 4206 return hwrm_req_send(bp, req); 4207 } 4208 4209 static int bnxt_set_eeprom(struct net_device *dev, 4210 struct ethtool_eeprom *eeprom, 4211 u8 *data) 4212 { 4213 struct bnxt *bp = netdev_priv(dev); 4214 u8 index, dir_op; 4215 u16 type, ext, ordinal, attr; 4216 4217 if (!BNXT_PF(bp)) { 4218 netdev_err(dev, "NVM write not supported from a virtual function\n"); 4219 return -EINVAL; 4220 } 4221 4222 type = eeprom->magic >> 16; 4223 4224 if (type == 0xffff) { /* special value for directory operations */ 4225 index = eeprom->magic & 0xff; 4226 dir_op = eeprom->magic >> 8; 4227 if (index == 0) 4228 return -EINVAL; 4229 switch (dir_op) { 4230 case 0x0e: /* erase */ 4231 if (eeprom->offset != ~eeprom->magic) 4232 return -EINVAL; 4233 return bnxt_erase_nvram_directory(dev, index - 1); 4234 default: 4235 return -EINVAL; 4236 } 4237 } 4238 4239 /* Create or re-write an NVM item: */ 4240 if (bnxt_dir_type_is_executable(type)) 4241 return -EOPNOTSUPP; 4242 ext = eeprom->magic & 0xffff; 4243 ordinal = eeprom->offset >> 16; 4244 attr = eeprom->offset & 0xffff; 4245 4246 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data, 4247 eeprom->len); 4248 } 4249 4250 static int bnxt_set_eee(struct net_device *dev, struct ethtool_keee *edata) 4251 { 4252 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 4253 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp); 4254 struct bnxt *bp = netdev_priv(dev); 4255 struct ethtool_keee *eee = &bp->eee; 4256 struct bnxt_link_info *link_info = &bp->link_info; 4257 int rc = 0; 4258 4259 if (!BNXT_PHY_CFG_ABLE(bp)) 4260 return -EOPNOTSUPP; 4261 4262 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 4263 return -EOPNOTSUPP; 4264 4265 mutex_lock(&bp->link_lock); 4266 _bnxt_fw_to_linkmode(advertising, link_info->advertising); 4267 if (!edata->eee_enabled) 4268 goto eee_ok; 4269 4270 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 4271 netdev_warn(dev, "EEE requires autoneg\n"); 4272 rc = -EINVAL; 4273 goto eee_exit; 4274 } 4275 if (edata->tx_lpi_enabled) { 4276 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 4277 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 4278 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 4279 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 4280 rc = -EINVAL; 4281 goto eee_exit; 4282 } else if (!bp->lpi_tmr_hi) { 4283 edata->tx_lpi_timer = eee->tx_lpi_timer; 4284 } 4285 } 4286 if (linkmode_empty(edata->advertised)) { 4287 linkmode_and(edata->advertised, advertising, eee->supported); 4288 } else if (linkmode_andnot(tmp, edata->advertised, advertising)) { 4289 netdev_warn(dev, "EEE advertised must be a subset of autoneg advertised speeds\n"); 4290 rc = -EINVAL; 4291 goto eee_exit; 4292 } 4293 4294 linkmode_copy(eee->advertised, edata->advertised); 4295 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 4296 eee->tx_lpi_timer = edata->tx_lpi_timer; 4297 eee_ok: 4298 eee->eee_enabled = edata->eee_enabled; 4299 4300 if (netif_running(dev)) 4301 rc = bnxt_hwrm_set_link_setting(bp, false, true); 4302 4303 eee_exit: 4304 mutex_unlock(&bp->link_lock); 4305 return rc; 4306 } 4307 4308 static int bnxt_get_eee(struct net_device *dev, struct ethtool_keee *edata) 4309 { 4310 struct bnxt *bp = netdev_priv(dev); 4311 4312 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 4313 return -EOPNOTSUPP; 4314 4315 *edata = bp->eee; 4316 if (!bp->eee.eee_enabled) { 4317 /* Preserve tx_lpi_timer so that the last value will be used 4318 * by default when it is re-enabled. 4319 */ 4320 linkmode_zero(edata->advertised); 4321 edata->tx_lpi_enabled = 0; 4322 } 4323 4324 if (!bp->eee.eee_active) 4325 linkmode_zero(edata->lp_advertised); 4326 4327 return 0; 4328 } 4329 4330 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 4331 u16 page_number, u8 bank, 4332 u16 start_addr, u16 data_length, 4333 u8 *buf) 4334 { 4335 struct hwrm_port_phy_i2c_read_output *output; 4336 struct hwrm_port_phy_i2c_read_input *req; 4337 int rc, byte_offset = 0; 4338 4339 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ); 4340 if (rc) 4341 return rc; 4342 4343 output = hwrm_req_hold(bp, req); 4344 req->i2c_slave_addr = i2c_addr; 4345 req->page_number = cpu_to_le16(page_number); 4346 req->port_id = cpu_to_le16(bp->pf.port_id); 4347 do { 4348 u16 xfer_size; 4349 4350 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 4351 data_length -= xfer_size; 4352 req->page_offset = cpu_to_le16(start_addr + byte_offset); 4353 req->data_length = xfer_size; 4354 req->enables = 4355 cpu_to_le32((start_addr + byte_offset ? 4356 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 4357 0) | 4358 (bank ? 4359 PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER : 4360 0)); 4361 rc = hwrm_req_send(bp, req); 4362 if (!rc) 4363 memcpy(buf + byte_offset, output->data, xfer_size); 4364 byte_offset += xfer_size; 4365 } while (!rc && data_length > 0); 4366 hwrm_req_drop(bp, req); 4367 4368 return rc; 4369 } 4370 4371 static int bnxt_get_module_info(struct net_device *dev, 4372 struct ethtool_modinfo *modinfo) 4373 { 4374 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 4375 struct bnxt *bp = netdev_priv(dev); 4376 int rc; 4377 4378 /* No point in going further if phy status indicates 4379 * module is not inserted or if it is powered down or 4380 * if it is of type 10GBase-T 4381 */ 4382 if (bp->link_info.module_status > 4383 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 4384 return -EOPNOTSUPP; 4385 4386 /* This feature is not supported in older firmware versions */ 4387 if (bp->hwrm_spec_code < 0x10202) 4388 return -EOPNOTSUPP; 4389 4390 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 0, 4391 SFF_DIAG_SUPPORT_OFFSET + 1, 4392 data); 4393 if (!rc) { 4394 u8 module_id = data[0]; 4395 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 4396 4397 switch (module_id) { 4398 case SFF_MODULE_ID_SFP: 4399 modinfo->type = ETH_MODULE_SFF_8472; 4400 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 4401 if (!diag_supported) 4402 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 4403 break; 4404 case SFF_MODULE_ID_QSFP: 4405 case SFF_MODULE_ID_QSFP_PLUS: 4406 modinfo->type = ETH_MODULE_SFF_8436; 4407 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 4408 break; 4409 case SFF_MODULE_ID_QSFP28: 4410 modinfo->type = ETH_MODULE_SFF_8636; 4411 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 4412 break; 4413 default: 4414 rc = -EOPNOTSUPP; 4415 break; 4416 } 4417 } 4418 return rc; 4419 } 4420 4421 static int bnxt_get_module_eeprom(struct net_device *dev, 4422 struct ethtool_eeprom *eeprom, 4423 u8 *data) 4424 { 4425 struct bnxt *bp = netdev_priv(dev); 4426 u16 start = eeprom->offset, length = eeprom->len; 4427 int rc = 0; 4428 4429 memset(data, 0, eeprom->len); 4430 4431 /* Read A0 portion of the EEPROM */ 4432 if (start < ETH_MODULE_SFF_8436_LEN) { 4433 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 4434 length = ETH_MODULE_SFF_8436_LEN - start; 4435 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 4436 start, length, data); 4437 if (rc) 4438 return rc; 4439 start += length; 4440 data += length; 4441 length = eeprom->len - length; 4442 } 4443 4444 /* Read A2 portion of the EEPROM */ 4445 if (length) { 4446 start -= ETH_MODULE_SFF_8436_LEN; 4447 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 0, 4448 start, length, data); 4449 } 4450 return rc; 4451 } 4452 4453 static int bnxt_get_module_status(struct bnxt *bp, struct netlink_ext_ack *extack) 4454 { 4455 if (bp->link_info.module_status <= 4456 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 4457 return 0; 4458 4459 switch (bp->link_info.module_status) { 4460 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 4461 NL_SET_ERR_MSG_MOD(extack, "Transceiver module is powering down"); 4462 break; 4463 case PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED: 4464 NL_SET_ERR_MSG_MOD(extack, "Transceiver module not inserted"); 4465 break; 4466 case PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT: 4467 NL_SET_ERR_MSG_MOD(extack, "Transceiver module disabled due to current fault"); 4468 break; 4469 default: 4470 NL_SET_ERR_MSG_MOD(extack, "Unknown error"); 4471 break; 4472 } 4473 return -EINVAL; 4474 } 4475 4476 static int bnxt_get_module_eeprom_by_page(struct net_device *dev, 4477 const struct ethtool_module_eeprom *page_data, 4478 struct netlink_ext_ack *extack) 4479 { 4480 struct bnxt *bp = netdev_priv(dev); 4481 int rc; 4482 4483 rc = bnxt_get_module_status(bp, extack); 4484 if (rc) 4485 return rc; 4486 4487 if (bp->hwrm_spec_code < 0x10202) { 4488 NL_SET_ERR_MSG_MOD(extack, "Firmware version too old"); 4489 return -EINVAL; 4490 } 4491 4492 if (page_data->bank && !(bp->phy_flags & BNXT_PHY_FL_BANK_SEL)) { 4493 NL_SET_ERR_MSG_MOD(extack, "Firmware not capable for bank selection"); 4494 return -EINVAL; 4495 } 4496 4497 rc = bnxt_read_sfp_module_eeprom_info(bp, page_data->i2c_address << 1, 4498 page_data->page, page_data->bank, 4499 page_data->offset, 4500 page_data->length, 4501 page_data->data); 4502 if (rc) { 4503 NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom read failed"); 4504 return rc; 4505 } 4506 return page_data->length; 4507 } 4508 4509 static int bnxt_nway_reset(struct net_device *dev) 4510 { 4511 int rc = 0; 4512 4513 struct bnxt *bp = netdev_priv(dev); 4514 struct bnxt_link_info *link_info = &bp->link_info; 4515 4516 if (!BNXT_PHY_CFG_ABLE(bp)) 4517 return -EOPNOTSUPP; 4518 4519 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 4520 return -EINVAL; 4521 4522 if (netif_running(dev)) 4523 rc = bnxt_hwrm_set_link_setting(bp, true, false); 4524 4525 return rc; 4526 } 4527 4528 static int bnxt_set_phys_id(struct net_device *dev, 4529 enum ethtool_phys_id_state state) 4530 { 4531 struct hwrm_port_led_cfg_input *req; 4532 struct bnxt *bp = netdev_priv(dev); 4533 struct bnxt_pf_info *pf = &bp->pf; 4534 struct bnxt_led_cfg *led_cfg; 4535 u8 led_state; 4536 __le16 duration; 4537 int rc, i; 4538 4539 if (!bp->num_leds || BNXT_VF(bp)) 4540 return -EOPNOTSUPP; 4541 4542 if (state == ETHTOOL_ID_ACTIVE) { 4543 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 4544 duration = cpu_to_le16(500); 4545 } else if (state == ETHTOOL_ID_INACTIVE) { 4546 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 4547 duration = cpu_to_le16(0); 4548 } else { 4549 return -EINVAL; 4550 } 4551 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG); 4552 if (rc) 4553 return rc; 4554 4555 req->port_id = cpu_to_le16(pf->port_id); 4556 req->num_leds = bp->num_leds; 4557 led_cfg = (struct bnxt_led_cfg *)&req->led0_id; 4558 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 4559 req->enables |= BNXT_LED_DFLT_ENABLES(i); 4560 led_cfg->led_id = bp->leds[i].led_id; 4561 led_cfg->led_state = led_state; 4562 led_cfg->led_blink_on = duration; 4563 led_cfg->led_blink_off = duration; 4564 led_cfg->led_group_id = bp->leds[i].led_group_id; 4565 } 4566 return hwrm_req_send(bp, req); 4567 } 4568 4569 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 4570 { 4571 struct hwrm_selftest_irq_input *req; 4572 int rc; 4573 4574 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ); 4575 if (rc) 4576 return rc; 4577 4578 req->cmpl_ring = cpu_to_le16(cmpl_ring); 4579 return hwrm_req_send(bp, req); 4580 } 4581 4582 static int bnxt_test_irq(struct bnxt *bp) 4583 { 4584 int i; 4585 4586 for (i = 0; i < bp->cp_nr_rings; i++) { 4587 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 4588 int rc; 4589 4590 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 4591 if (rc) 4592 return rc; 4593 } 4594 return 0; 4595 } 4596 4597 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 4598 { 4599 struct hwrm_port_mac_cfg_input *req; 4600 int rc; 4601 4602 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 4603 if (rc) 4604 return rc; 4605 4606 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 4607 if (enable) 4608 req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 4609 else 4610 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 4611 return hwrm_req_send(bp, req); 4612 } 4613 4614 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 4615 { 4616 struct hwrm_port_phy_qcaps_output *resp; 4617 struct hwrm_port_phy_qcaps_input *req; 4618 int rc; 4619 4620 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS); 4621 if (rc) 4622 return rc; 4623 4624 resp = hwrm_req_hold(bp, req); 4625 rc = hwrm_req_send(bp, req); 4626 if (!rc) 4627 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 4628 4629 hwrm_req_drop(bp, req); 4630 return rc; 4631 } 4632 4633 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 4634 struct hwrm_port_phy_cfg_input *req) 4635 { 4636 struct bnxt_link_info *link_info = &bp->link_info; 4637 u16 fw_advertising; 4638 u16 fw_speed; 4639 int rc; 4640 4641 if (!link_info->autoneg || 4642 (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK)) 4643 return 0; 4644 4645 rc = bnxt_query_force_speeds(bp, &fw_advertising); 4646 if (rc) 4647 return rc; 4648 4649 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 4650 if (BNXT_LINK_IS_UP(bp)) 4651 fw_speed = bp->link_info.link_speed; 4652 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 4653 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 4654 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 4655 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 4656 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 4657 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 4658 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 4659 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 4660 4661 req->force_link_speed = cpu_to_le16(fw_speed); 4662 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 4663 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 4664 rc = hwrm_req_send(bp, req); 4665 req->flags = 0; 4666 req->force_link_speed = cpu_to_le16(0); 4667 return rc; 4668 } 4669 4670 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 4671 { 4672 struct hwrm_port_phy_cfg_input *req; 4673 int rc; 4674 4675 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 4676 if (rc) 4677 return rc; 4678 4679 /* prevent bnxt_disable_an_for_lpbk() from consuming the request */ 4680 hwrm_req_hold(bp, req); 4681 4682 if (enable) { 4683 bnxt_disable_an_for_lpbk(bp, req); 4684 if (ext) 4685 req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 4686 else 4687 req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 4688 } else { 4689 req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 4690 } 4691 req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 4692 rc = hwrm_req_send(bp, req); 4693 hwrm_req_drop(bp, req); 4694 return rc; 4695 } 4696 4697 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 4698 u32 raw_cons, int pkt_size) 4699 { 4700 struct bnxt_napi *bnapi = cpr->bnapi; 4701 struct bnxt_rx_ring_info *rxr; 4702 struct bnxt_sw_rx_bd *rx_buf; 4703 struct rx_cmp *rxcmp; 4704 u16 cp_cons, cons; 4705 u8 *data; 4706 u32 len; 4707 int i; 4708 4709 rxr = bnapi->rx_ring; 4710 cp_cons = RING_CMP(raw_cons); 4711 rxcmp = (struct rx_cmp *) 4712 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 4713 cons = rxcmp->rx_cmp_opaque; 4714 rx_buf = &rxr->rx_buf_ring[cons]; 4715 data = rx_buf->data_ptr; 4716 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 4717 if (len != pkt_size) 4718 return -EIO; 4719 i = ETH_ALEN; 4720 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 4721 return -EIO; 4722 i += ETH_ALEN; 4723 for ( ; i < pkt_size; i++) { 4724 if (data[i] != (u8)(i & 0xff)) 4725 return -EIO; 4726 } 4727 return 0; 4728 } 4729 4730 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 4731 int pkt_size) 4732 { 4733 struct tx_cmp *txcmp; 4734 int rc = -EIO; 4735 u32 raw_cons; 4736 u32 cons; 4737 int i; 4738 4739 raw_cons = cpr->cp_raw_cons; 4740 for (i = 0; i < 200; i++) { 4741 cons = RING_CMP(raw_cons); 4742 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 4743 4744 if (!TX_CMP_VALID(txcmp, raw_cons)) { 4745 udelay(5); 4746 continue; 4747 } 4748 4749 /* The valid test of the entry must be done first before 4750 * reading any further. 4751 */ 4752 dma_rmb(); 4753 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP || 4754 TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_V3_CMP) { 4755 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 4756 raw_cons = NEXT_RAW_CMP(raw_cons); 4757 raw_cons = NEXT_RAW_CMP(raw_cons); 4758 break; 4759 } 4760 raw_cons = NEXT_RAW_CMP(raw_cons); 4761 } 4762 cpr->cp_raw_cons = raw_cons; 4763 return rc; 4764 } 4765 4766 static int bnxt_run_loopback(struct bnxt *bp) 4767 { 4768 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 4769 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 4770 struct bnxt_cp_ring_info *cpr; 4771 int pkt_size, i = 0; 4772 struct sk_buff *skb; 4773 dma_addr_t map; 4774 u8 *data; 4775 int rc; 4776 4777 cpr = &rxr->bnapi->cp_ring; 4778 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) 4779 cpr = rxr->rx_cpr; 4780 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh); 4781 skb = netdev_alloc_skb(bp->dev, pkt_size); 4782 if (!skb) 4783 return -ENOMEM; 4784 data = skb_put(skb, pkt_size); 4785 ether_addr_copy(&data[i], bp->dev->dev_addr); 4786 i += ETH_ALEN; 4787 ether_addr_copy(&data[i], bp->dev->dev_addr); 4788 i += ETH_ALEN; 4789 for ( ; i < pkt_size; i++) 4790 data[i] = (u8)(i & 0xff); 4791 4792 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 4793 DMA_TO_DEVICE); 4794 if (dma_mapping_error(&bp->pdev->dev, map)) { 4795 dev_kfree_skb(skb); 4796 return -EIO; 4797 } 4798 bnxt_xmit_bd(bp, txr, map, pkt_size, NULL); 4799 4800 /* Sync BD data before updating doorbell */ 4801 wmb(); 4802 4803 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 4804 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 4805 4806 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE); 4807 dev_kfree_skb(skb); 4808 return rc; 4809 } 4810 4811 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 4812 { 4813 struct hwrm_selftest_exec_output *resp; 4814 struct hwrm_selftest_exec_input *req; 4815 int rc; 4816 4817 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC); 4818 if (rc) 4819 return rc; 4820 4821 hwrm_req_timeout(bp, req, bp->test_info->timeout); 4822 req->flags = test_mask; 4823 4824 resp = hwrm_req_hold(bp, req); 4825 rc = hwrm_req_send(bp, req); 4826 *test_results = resp->test_success; 4827 hwrm_req_drop(bp, req); 4828 return rc; 4829 } 4830 4831 #define BNXT_DRV_TESTS 4 4832 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 4833 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 4834 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 4835 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 4836 4837 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 4838 u64 *buf) 4839 { 4840 struct bnxt *bp = netdev_priv(dev); 4841 bool do_ext_lpbk = false; 4842 bool offline = false; 4843 u8 test_results = 0; 4844 u8 test_mask = 0; 4845 int rc = 0, i; 4846 4847 if (!bp->num_tests || !BNXT_PF(bp)) 4848 return; 4849 4850 if (etest->flags & ETH_TEST_FL_OFFLINE && 4851 bnxt_ulp_registered(bp->edev)) { 4852 etest->flags |= ETH_TEST_FL_FAILED; 4853 netdev_warn(dev, "Offline tests cannot be run with RoCE driver loaded\n"); 4854 return; 4855 } 4856 4857 memset(buf, 0, sizeof(u64) * bp->num_tests); 4858 if (!netif_running(dev)) { 4859 etest->flags |= ETH_TEST_FL_FAILED; 4860 return; 4861 } 4862 4863 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 4864 (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK)) 4865 do_ext_lpbk = true; 4866 4867 if (etest->flags & ETH_TEST_FL_OFFLINE) { 4868 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) { 4869 etest->flags |= ETH_TEST_FL_FAILED; 4870 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n"); 4871 return; 4872 } 4873 offline = true; 4874 } 4875 4876 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 4877 u8 bit_val = 1 << i; 4878 4879 if (!(bp->test_info->offline_mask & bit_val)) 4880 test_mask |= bit_val; 4881 else if (offline) 4882 test_mask |= bit_val; 4883 } 4884 if (!offline) { 4885 bnxt_run_fw_tests(bp, test_mask, &test_results); 4886 } else { 4887 bnxt_close_nic(bp, true, false); 4888 bnxt_run_fw_tests(bp, test_mask, &test_results); 4889 4890 buf[BNXT_MACLPBK_TEST_IDX] = 1; 4891 bnxt_hwrm_mac_loopback(bp, true); 4892 msleep(250); 4893 rc = bnxt_half_open_nic(bp); 4894 if (rc) { 4895 bnxt_hwrm_mac_loopback(bp, false); 4896 etest->flags |= ETH_TEST_FL_FAILED; 4897 return; 4898 } 4899 if (bnxt_run_loopback(bp)) 4900 etest->flags |= ETH_TEST_FL_FAILED; 4901 else 4902 buf[BNXT_MACLPBK_TEST_IDX] = 0; 4903 4904 bnxt_hwrm_mac_loopback(bp, false); 4905 bnxt_hwrm_phy_loopback(bp, true, false); 4906 msleep(1000); 4907 if (bnxt_run_loopback(bp)) { 4908 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 4909 etest->flags |= ETH_TEST_FL_FAILED; 4910 } 4911 if (do_ext_lpbk) { 4912 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 4913 bnxt_hwrm_phy_loopback(bp, true, true); 4914 msleep(1000); 4915 if (bnxt_run_loopback(bp)) { 4916 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 4917 etest->flags |= ETH_TEST_FL_FAILED; 4918 } 4919 } 4920 bnxt_hwrm_phy_loopback(bp, false, false); 4921 bnxt_half_close_nic(bp); 4922 rc = bnxt_open_nic(bp, true, true); 4923 } 4924 if (rc || bnxt_test_irq(bp)) { 4925 buf[BNXT_IRQ_TEST_IDX] = 1; 4926 etest->flags |= ETH_TEST_FL_FAILED; 4927 } 4928 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 4929 u8 bit_val = 1 << i; 4930 4931 if ((test_mask & bit_val) && !(test_results & bit_val)) { 4932 buf[i] = 1; 4933 etest->flags |= ETH_TEST_FL_FAILED; 4934 } 4935 } 4936 } 4937 4938 static int bnxt_reset(struct net_device *dev, u32 *flags) 4939 { 4940 struct bnxt *bp = netdev_priv(dev); 4941 bool reload = false; 4942 u32 req = *flags; 4943 4944 if (!req) 4945 return -EINVAL; 4946 4947 if (!BNXT_PF(bp)) { 4948 netdev_err(dev, "Reset is not supported from a VF\n"); 4949 return -EOPNOTSUPP; 4950 } 4951 4952 if (pci_vfs_assigned(bp->pdev) && 4953 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) { 4954 netdev_err(dev, 4955 "Reset not allowed when VFs are assigned to VMs\n"); 4956 return -EBUSY; 4957 } 4958 4959 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) { 4960 /* This feature is not supported in older firmware versions */ 4961 if (bp->hwrm_spec_code >= 0x10803) { 4962 if (!bnxt_firmware_reset_chip(dev)) { 4963 netdev_info(dev, "Firmware reset request successful.\n"); 4964 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) 4965 reload = true; 4966 *flags &= ~BNXT_FW_RESET_CHIP; 4967 } 4968 } else if (req == BNXT_FW_RESET_CHIP) { 4969 return -EOPNOTSUPP; /* only request, fail hard */ 4970 } 4971 } 4972 4973 if (!BNXT_CHIP_P4_PLUS(bp) && (req & BNXT_FW_RESET_AP)) { 4974 /* This feature is not supported in older firmware versions */ 4975 if (bp->hwrm_spec_code >= 0x10803) { 4976 if (!bnxt_firmware_reset_ap(dev)) { 4977 netdev_info(dev, "Reset application processor successful.\n"); 4978 reload = true; 4979 *flags &= ~BNXT_FW_RESET_AP; 4980 } 4981 } else if (req == BNXT_FW_RESET_AP) { 4982 return -EOPNOTSUPP; /* only request, fail hard */ 4983 } 4984 } 4985 4986 if (reload) 4987 netdev_info(dev, "Reload driver to complete reset\n"); 4988 4989 return 0; 4990 } 4991 4992 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump) 4993 { 4994 struct bnxt *bp = netdev_priv(dev); 4995 4996 if (dump->flag > BNXT_DUMP_DRIVER) { 4997 netdev_info(dev, "Supports only Live(0), Crash(1), Driver(2) dumps.\n"); 4998 return -EINVAL; 4999 } 5000 5001 if (dump->flag == BNXT_DUMP_CRASH) { 5002 if (bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR && 5003 (!IS_ENABLED(CONFIG_TEE_BNXT_FW))) { 5004 netdev_info(dev, 5005 "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n"); 5006 return -EOPNOTSUPP; 5007 } else if (!(bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR)) { 5008 netdev_info(dev, "Crash dump collection from host memory is not supported on this interface.\n"); 5009 return -EOPNOTSUPP; 5010 } 5011 } 5012 5013 bp->dump_flag = dump->flag; 5014 return 0; 5015 } 5016 5017 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 5018 { 5019 struct bnxt *bp = netdev_priv(dev); 5020 5021 if (bp->hwrm_spec_code < 0x10801) 5022 return -EOPNOTSUPP; 5023 5024 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 5025 bp->ver_resp.hwrm_fw_min_8b << 16 | 5026 bp->ver_resp.hwrm_fw_bld_8b << 8 | 5027 bp->ver_resp.hwrm_fw_rsvd_8b; 5028 5029 dump->flag = bp->dump_flag; 5030 dump->len = bnxt_get_coredump_length(bp, bp->dump_flag); 5031 return 0; 5032 } 5033 5034 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 5035 void *buf) 5036 { 5037 struct bnxt *bp = netdev_priv(dev); 5038 5039 if (bp->hwrm_spec_code < 0x10801) 5040 return -EOPNOTSUPP; 5041 5042 memset(buf, 0, dump->len); 5043 5044 dump->flag = bp->dump_flag; 5045 return bnxt_get_coredump(bp, dump->flag, buf, &dump->len); 5046 } 5047 5048 static int bnxt_get_ts_info(struct net_device *dev, 5049 struct kernel_ethtool_ts_info *info) 5050 { 5051 struct bnxt *bp = netdev_priv(dev); 5052 struct bnxt_ptp_cfg *ptp; 5053 5054 ptp = bp->ptp_cfg; 5055 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE; 5056 5057 if (!ptp) 5058 return 0; 5059 5060 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | 5061 SOF_TIMESTAMPING_RX_HARDWARE | 5062 SOF_TIMESTAMPING_RAW_HARDWARE; 5063 if (ptp->ptp_clock) 5064 info->phc_index = ptp_clock_index(ptp->ptp_clock); 5065 5066 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 5067 5068 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 5069 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 5070 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 5071 5072 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) 5073 info->rx_filters |= (1 << HWTSTAMP_FILTER_ALL); 5074 return 0; 5075 } 5076 5077 void bnxt_ethtool_init(struct bnxt *bp) 5078 { 5079 struct hwrm_selftest_qlist_output *resp; 5080 struct hwrm_selftest_qlist_input *req; 5081 struct bnxt_test_info *test_info; 5082 struct net_device *dev = bp->dev; 5083 int i, rc; 5084 5085 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 5086 bnxt_get_pkgver(dev); 5087 5088 bp->num_tests = 0; 5089 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp)) 5090 return; 5091 5092 test_info = bp->test_info; 5093 if (!test_info) { 5094 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL); 5095 if (!test_info) 5096 return; 5097 bp->test_info = test_info; 5098 } 5099 5100 if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST)) 5101 return; 5102 5103 resp = hwrm_req_hold(bp, req); 5104 rc = hwrm_req_send_silent(bp, req); 5105 if (rc) 5106 goto ethtool_init_exit; 5107 5108 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 5109 if (bp->num_tests > BNXT_MAX_TEST) 5110 bp->num_tests = BNXT_MAX_TEST; 5111 5112 test_info->offline_mask = resp->offline_tests; 5113 test_info->timeout = le16_to_cpu(resp->test_timeout); 5114 if (!test_info->timeout) 5115 test_info->timeout = HWRM_CMD_TIMEOUT; 5116 for (i = 0; i < bp->num_tests; i++) { 5117 char *str = test_info->string[i]; 5118 char *fw_str = resp->test_name[i]; 5119 5120 if (i == BNXT_MACLPBK_TEST_IDX) { 5121 strcpy(str, "Mac loopback test (offline)"); 5122 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 5123 strcpy(str, "Phy loopback test (offline)"); 5124 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 5125 strcpy(str, "Ext loopback test (offline)"); 5126 } else if (i == BNXT_IRQ_TEST_IDX) { 5127 strcpy(str, "Interrupt_test (offline)"); 5128 } else { 5129 snprintf(str, ETH_GSTRING_LEN, "%s test (%s)", 5130 fw_str, test_info->offline_mask & (1 << i) ? 5131 "offline" : "online"); 5132 } 5133 } 5134 5135 ethtool_init_exit: 5136 hwrm_req_drop(bp, req); 5137 } 5138 5139 static void bnxt_get_eth_phy_stats(struct net_device *dev, 5140 struct ethtool_eth_phy_stats *phy_stats) 5141 { 5142 struct bnxt *bp = netdev_priv(dev); 5143 u64 *rx; 5144 5145 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 5146 return; 5147 5148 rx = bp->rx_port_stats_ext.sw_stats; 5149 phy_stats->SymbolErrorDuringCarrier = 5150 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err)); 5151 } 5152 5153 static void bnxt_get_eth_mac_stats(struct net_device *dev, 5154 struct ethtool_eth_mac_stats *mac_stats) 5155 { 5156 struct bnxt *bp = netdev_priv(dev); 5157 u64 *rx, *tx; 5158 5159 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5160 return; 5161 5162 rx = bp->port_stats.sw_stats; 5163 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 5164 5165 mac_stats->FramesReceivedOK = 5166 BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames); 5167 mac_stats->FramesTransmittedOK = 5168 BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames); 5169 mac_stats->FrameCheckSequenceErrors = 5170 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames); 5171 mac_stats->AlignmentErrors = 5172 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames); 5173 mac_stats->OutOfRangeLengthField = 5174 BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames); 5175 } 5176 5177 static void bnxt_get_eth_ctrl_stats(struct net_device *dev, 5178 struct ethtool_eth_ctrl_stats *ctrl_stats) 5179 { 5180 struct bnxt *bp = netdev_priv(dev); 5181 u64 *rx; 5182 5183 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5184 return; 5185 5186 rx = bp->port_stats.sw_stats; 5187 ctrl_stats->MACControlFramesReceived = 5188 BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames); 5189 } 5190 5191 static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = { 5192 { 0, 64 }, 5193 { 65, 127 }, 5194 { 128, 255 }, 5195 { 256, 511 }, 5196 { 512, 1023 }, 5197 { 1024, 1518 }, 5198 { 1519, 2047 }, 5199 { 2048, 4095 }, 5200 { 4096, 9216 }, 5201 { 9217, 16383 }, 5202 {} 5203 }; 5204 5205 static void bnxt_get_rmon_stats(struct net_device *dev, 5206 struct ethtool_rmon_stats *rmon_stats, 5207 const struct ethtool_rmon_hist_range **ranges) 5208 { 5209 struct bnxt *bp = netdev_priv(dev); 5210 u64 *rx, *tx; 5211 5212 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5213 return; 5214 5215 rx = bp->port_stats.sw_stats; 5216 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 5217 5218 rmon_stats->jabbers = 5219 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames); 5220 rmon_stats->oversize_pkts = 5221 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames); 5222 rmon_stats->undersize_pkts = 5223 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames); 5224 5225 rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames); 5226 rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames); 5227 rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames); 5228 rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames); 5229 rmon_stats->hist[4] = 5230 BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames); 5231 rmon_stats->hist[5] = 5232 BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames); 5233 rmon_stats->hist[6] = 5234 BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames); 5235 rmon_stats->hist[7] = 5236 BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames); 5237 rmon_stats->hist[8] = 5238 BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames); 5239 rmon_stats->hist[9] = 5240 BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames); 5241 5242 rmon_stats->hist_tx[0] = 5243 BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames); 5244 rmon_stats->hist_tx[1] = 5245 BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames); 5246 rmon_stats->hist_tx[2] = 5247 BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames); 5248 rmon_stats->hist_tx[3] = 5249 BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames); 5250 rmon_stats->hist_tx[4] = 5251 BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames); 5252 rmon_stats->hist_tx[5] = 5253 BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames); 5254 rmon_stats->hist_tx[6] = 5255 BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames); 5256 rmon_stats->hist_tx[7] = 5257 BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames); 5258 rmon_stats->hist_tx[8] = 5259 BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames); 5260 rmon_stats->hist_tx[9] = 5261 BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames); 5262 5263 *ranges = bnxt_rmon_ranges; 5264 } 5265 5266 static void bnxt_get_ptp_stats(struct net_device *dev, 5267 struct ethtool_ts_stats *ts_stats) 5268 { 5269 struct bnxt *bp = netdev_priv(dev); 5270 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 5271 5272 if (ptp) { 5273 ts_stats->pkts = ptp->stats.ts_pkts; 5274 ts_stats->lost = ptp->stats.ts_lost; 5275 ts_stats->err = atomic64_read(&ptp->stats.ts_err); 5276 } 5277 } 5278 5279 static void bnxt_get_link_ext_stats(struct net_device *dev, 5280 struct ethtool_link_ext_stats *stats) 5281 { 5282 struct bnxt *bp = netdev_priv(dev); 5283 u64 *rx; 5284 5285 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 5286 return; 5287 5288 rx = bp->rx_port_stats_ext.sw_stats; 5289 stats->link_down_events = 5290 *(rx + BNXT_RX_STATS_EXT_OFFSET(link_down_events)); 5291 } 5292 5293 void bnxt_ethtool_free(struct bnxt *bp) 5294 { 5295 kfree(bp->test_info); 5296 bp->test_info = NULL; 5297 } 5298 5299 const struct ethtool_ops bnxt_ethtool_ops = { 5300 .cap_link_lanes_supported = 1, 5301 .rxfh_per_ctx_key = 1, 5302 .rxfh_max_num_contexts = BNXT_MAX_ETH_RSS_CTX + 1, 5303 .rxfh_indir_space = BNXT_MAX_RSS_TABLE_ENTRIES_P5, 5304 .rxfh_priv_size = sizeof(struct bnxt_rss_ctx), 5305 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 5306 ETHTOOL_COALESCE_MAX_FRAMES | 5307 ETHTOOL_COALESCE_USECS_IRQ | 5308 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 5309 ETHTOOL_COALESCE_STATS_BLOCK_USECS | 5310 ETHTOOL_COALESCE_USE_ADAPTIVE_RX | 5311 ETHTOOL_COALESCE_USE_CQE, 5312 .get_link_ksettings = bnxt_get_link_ksettings, 5313 .set_link_ksettings = bnxt_set_link_ksettings, 5314 .get_fec_stats = bnxt_get_fec_stats, 5315 .get_fecparam = bnxt_get_fecparam, 5316 .set_fecparam = bnxt_set_fecparam, 5317 .get_pause_stats = bnxt_get_pause_stats, 5318 .get_pauseparam = bnxt_get_pauseparam, 5319 .set_pauseparam = bnxt_set_pauseparam, 5320 .get_drvinfo = bnxt_get_drvinfo, 5321 .get_regs_len = bnxt_get_regs_len, 5322 .get_regs = bnxt_get_regs, 5323 .get_wol = bnxt_get_wol, 5324 .set_wol = bnxt_set_wol, 5325 .get_coalesce = bnxt_get_coalesce, 5326 .set_coalesce = bnxt_set_coalesce, 5327 .get_msglevel = bnxt_get_msglevel, 5328 .set_msglevel = bnxt_set_msglevel, 5329 .get_sset_count = bnxt_get_sset_count, 5330 .get_strings = bnxt_get_strings, 5331 .get_ethtool_stats = bnxt_get_ethtool_stats, 5332 .set_ringparam = bnxt_set_ringparam, 5333 .get_ringparam = bnxt_get_ringparam, 5334 .get_channels = bnxt_get_channels, 5335 .set_channels = bnxt_set_channels, 5336 .get_rxnfc = bnxt_get_rxnfc, 5337 .set_rxnfc = bnxt_set_rxnfc, 5338 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 5339 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 5340 .get_rxfh = bnxt_get_rxfh, 5341 .set_rxfh = bnxt_set_rxfh, 5342 .create_rxfh_context = bnxt_create_rxfh_context, 5343 .modify_rxfh_context = bnxt_modify_rxfh_context, 5344 .remove_rxfh_context = bnxt_remove_rxfh_context, 5345 .flash_device = bnxt_flash_device, 5346 .get_eeprom_len = bnxt_get_eeprom_len, 5347 .get_eeprom = bnxt_get_eeprom, 5348 .set_eeprom = bnxt_set_eeprom, 5349 .get_link = bnxt_get_link, 5350 .get_link_ext_stats = bnxt_get_link_ext_stats, 5351 .get_eee = bnxt_get_eee, 5352 .set_eee = bnxt_set_eee, 5353 .get_module_info = bnxt_get_module_info, 5354 .get_module_eeprom = bnxt_get_module_eeprom, 5355 .get_module_eeprom_by_page = bnxt_get_module_eeprom_by_page, 5356 .nway_reset = bnxt_nway_reset, 5357 .set_phys_id = bnxt_set_phys_id, 5358 .self_test = bnxt_self_test, 5359 .get_ts_info = bnxt_get_ts_info, 5360 .reset = bnxt_reset, 5361 .set_dump = bnxt_set_dump, 5362 .get_dump_flag = bnxt_get_dump_flag, 5363 .get_dump_data = bnxt_get_dump_data, 5364 .get_eth_phy_stats = bnxt_get_eth_phy_stats, 5365 .get_eth_mac_stats = bnxt_get_eth_mac_stats, 5366 .get_eth_ctrl_stats = bnxt_get_eth_ctrl_stats, 5367 .get_rmon_stats = bnxt_get_rmon_stats, 5368 .get_ts_stats = bnxt_get_ptp_stats, 5369 }; 5370