1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/bitops.h> 12 #include <linux/ctype.h> 13 #include <linux/stringify.h> 14 #include <linux/ethtool.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/linkmode.h> 17 #include <linux/interrupt.h> 18 #include <linux/pci.h> 19 #include <linux/etherdevice.h> 20 #include <linux/crc32.h> 21 #include <linux/firmware.h> 22 #include <linux/utsname.h> 23 #include <linux/time.h> 24 #include <linux/ptp_clock_kernel.h> 25 #include <linux/net_tstamp.h> 26 #include <linux/timecounter.h> 27 #include <net/netlink.h> 28 #include "bnxt_hsi.h" 29 #include "bnxt.h" 30 #include "bnxt_hwrm.h" 31 #include "bnxt_ulp.h" 32 #include "bnxt_xdp.h" 33 #include "bnxt_ptp.h" 34 #include "bnxt_ethtool.h" 35 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 36 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 37 #include "bnxt_coredump.h" 38 39 #define BNXT_NVM_ERR_MSG(dev, extack, msg) \ 40 do { \ 41 if (extack) \ 42 NL_SET_ERR_MSG_MOD(extack, msg); \ 43 netdev_err(dev, "%s\n", msg); \ 44 } while (0) 45 46 static u32 bnxt_get_msglevel(struct net_device *dev) 47 { 48 struct bnxt *bp = netdev_priv(dev); 49 50 return bp->msg_enable; 51 } 52 53 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 54 { 55 struct bnxt *bp = netdev_priv(dev); 56 57 bp->msg_enable = value; 58 } 59 60 static int bnxt_get_coalesce(struct net_device *dev, 61 struct ethtool_coalesce *coal, 62 struct kernel_ethtool_coalesce *kernel_coal, 63 struct netlink_ext_ack *extack) 64 { 65 struct bnxt *bp = netdev_priv(dev); 66 struct bnxt_coal *hw_coal; 67 u16 mult; 68 69 memset(coal, 0, sizeof(*coal)); 70 71 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 72 73 hw_coal = &bp->rx_coal; 74 mult = hw_coal->bufs_per_record; 75 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 76 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 77 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 78 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 79 if (hw_coal->flags & 80 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 81 kernel_coal->use_cqe_mode_rx = true; 82 83 hw_coal = &bp->tx_coal; 84 mult = hw_coal->bufs_per_record; 85 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 86 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 87 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 88 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 89 if (hw_coal->flags & 90 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 91 kernel_coal->use_cqe_mode_tx = true; 92 93 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 94 95 return 0; 96 } 97 98 static int bnxt_set_coalesce(struct net_device *dev, 99 struct ethtool_coalesce *coal, 100 struct kernel_ethtool_coalesce *kernel_coal, 101 struct netlink_ext_ack *extack) 102 { 103 struct bnxt *bp = netdev_priv(dev); 104 bool update_stats = false; 105 struct bnxt_coal *hw_coal; 106 int rc = 0; 107 u16 mult; 108 109 if (coal->use_adaptive_rx_coalesce) { 110 bp->flags |= BNXT_FLAG_DIM; 111 } else { 112 if (bp->flags & BNXT_FLAG_DIM) { 113 bp->flags &= ~(BNXT_FLAG_DIM); 114 goto reset_coalesce; 115 } 116 } 117 118 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) && 119 !(bp->coal_cap.cmpl_params & 120 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)) 121 return -EOPNOTSUPP; 122 123 hw_coal = &bp->rx_coal; 124 mult = hw_coal->bufs_per_record; 125 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 126 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 127 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 128 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 129 hw_coal->flags &= 130 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 131 if (kernel_coal->use_cqe_mode_rx) 132 hw_coal->flags |= 133 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 134 135 hw_coal = &bp->tx_coal; 136 mult = hw_coal->bufs_per_record; 137 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 138 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 139 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 140 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 141 hw_coal->flags &= 142 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 143 if (kernel_coal->use_cqe_mode_tx) 144 hw_coal->flags |= 145 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 146 147 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 148 u32 stats_ticks = coal->stats_block_coalesce_usecs; 149 150 /* Allow 0, which means disable. */ 151 if (stats_ticks) 152 stats_ticks = clamp_t(u32, stats_ticks, 153 BNXT_MIN_STATS_COAL_TICKS, 154 BNXT_MAX_STATS_COAL_TICKS); 155 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 156 bp->stats_coal_ticks = stats_ticks; 157 if (bp->stats_coal_ticks) 158 bp->current_interval = 159 bp->stats_coal_ticks * HZ / 1000000; 160 else 161 bp->current_interval = BNXT_TIMER_INTERVAL; 162 update_stats = true; 163 } 164 165 reset_coalesce: 166 if (test_bit(BNXT_STATE_OPEN, &bp->state)) { 167 if (update_stats) { 168 bnxt_close_nic(bp, true, false); 169 rc = bnxt_open_nic(bp, true, false); 170 } else { 171 rc = bnxt_hwrm_set_coal(bp); 172 } 173 } 174 175 return rc; 176 } 177 178 static const char * const bnxt_ring_rx_stats_str[] = { 179 "rx_ucast_packets", 180 "rx_mcast_packets", 181 "rx_bcast_packets", 182 "rx_discards", 183 "rx_errors", 184 "rx_ucast_bytes", 185 "rx_mcast_bytes", 186 "rx_bcast_bytes", 187 }; 188 189 static const char * const bnxt_ring_tx_stats_str[] = { 190 "tx_ucast_packets", 191 "tx_mcast_packets", 192 "tx_bcast_packets", 193 "tx_errors", 194 "tx_discards", 195 "tx_ucast_bytes", 196 "tx_mcast_bytes", 197 "tx_bcast_bytes", 198 }; 199 200 static const char * const bnxt_ring_tpa_stats_str[] = { 201 "tpa_packets", 202 "tpa_bytes", 203 "tpa_events", 204 "tpa_aborts", 205 }; 206 207 static const char * const bnxt_ring_tpa2_stats_str[] = { 208 "rx_tpa_eligible_pkt", 209 "rx_tpa_eligible_bytes", 210 "rx_tpa_pkt", 211 "rx_tpa_bytes", 212 "rx_tpa_errors", 213 "rx_tpa_events", 214 }; 215 216 static const char * const bnxt_rx_sw_stats_str[] = { 217 "rx_l4_csum_errors", 218 "rx_resets", 219 "rx_buf_errors", 220 }; 221 222 static const char * const bnxt_cmn_sw_stats_str[] = { 223 "missed_irqs", 224 }; 225 226 #define BNXT_RX_STATS_ENTRY(counter) \ 227 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 228 229 #define BNXT_TX_STATS_ENTRY(counter) \ 230 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 231 232 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 233 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 234 235 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 236 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 237 238 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 239 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 240 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 241 242 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 243 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 244 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 245 246 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 247 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 248 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 249 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 250 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 251 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 252 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 253 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 254 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 255 256 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 257 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 258 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 259 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 260 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 261 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 262 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 263 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 264 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 265 266 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 267 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 268 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 269 270 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 271 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 272 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 273 274 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 275 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 276 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 277 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 278 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 279 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 280 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 281 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 282 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 283 284 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 285 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 286 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 287 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 288 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 289 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 290 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 291 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 292 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 293 294 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 295 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 296 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 297 298 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 299 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 300 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 301 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 302 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 303 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 304 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 305 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 306 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 307 308 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 309 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 310 __stringify(counter##_pri##n) } 311 312 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 313 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 314 __stringify(counter##_pri##n) } 315 316 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 317 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 318 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 319 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 320 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 321 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 322 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 323 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 324 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 325 326 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 327 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 328 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 329 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 330 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 331 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 332 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 333 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 334 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 335 336 enum { 337 RX_TOTAL_DISCARDS, 338 TX_TOTAL_DISCARDS, 339 RX_NETPOLL_DISCARDS, 340 }; 341 342 static const char *const bnxt_ring_err_stats_arr[] = { 343 "rx_total_l4_csum_errors", 344 "rx_total_resets", 345 "rx_total_buf_errors", 346 "rx_total_oom_discards", 347 "rx_total_netpoll_discards", 348 "rx_total_ring_discards", 349 "tx_total_resets", 350 "tx_total_ring_discards", 351 "total_missed_irqs", 352 }; 353 354 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str) 355 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str) 356 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str) 357 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str) 358 359 static const struct { 360 long offset; 361 char string[ETH_GSTRING_LEN]; 362 } bnxt_port_stats_arr[] = { 363 BNXT_RX_STATS_ENTRY(rx_64b_frames), 364 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 365 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 366 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 367 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 368 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 369 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 370 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 371 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 372 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 373 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 374 BNXT_RX_STATS_ENTRY(rx_total_frames), 375 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 376 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 377 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 378 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 379 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 380 BNXT_RX_STATS_ENTRY(rx_pause_frames), 381 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 382 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 383 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 384 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 385 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 386 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 387 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 388 BNXT_RX_STATS_ENTRY(rx_good_frames), 389 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 390 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 391 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 392 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 393 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 394 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 395 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 396 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 397 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 398 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 399 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 400 BNXT_RX_STATS_ENTRY(rx_bytes), 401 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 402 BNXT_RX_STATS_ENTRY(rx_runt_frames), 403 BNXT_RX_STATS_ENTRY(rx_stat_discard), 404 BNXT_RX_STATS_ENTRY(rx_stat_err), 405 406 BNXT_TX_STATS_ENTRY(tx_64b_frames), 407 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 408 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 409 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 410 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 411 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 412 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 413 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 414 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 415 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 416 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 417 BNXT_TX_STATS_ENTRY(tx_good_frames), 418 BNXT_TX_STATS_ENTRY(tx_total_frames), 419 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 420 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 421 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 422 BNXT_TX_STATS_ENTRY(tx_pause_frames), 423 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 424 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 425 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 426 BNXT_TX_STATS_ENTRY(tx_err), 427 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 428 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 429 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 430 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 431 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 432 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 433 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 434 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 435 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 436 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 437 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 438 BNXT_TX_STATS_ENTRY(tx_total_collisions), 439 BNXT_TX_STATS_ENTRY(tx_bytes), 440 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 441 BNXT_TX_STATS_ENTRY(tx_stat_discard), 442 BNXT_TX_STATS_ENTRY(tx_stat_error), 443 }; 444 445 static const struct { 446 long offset; 447 char string[ETH_GSTRING_LEN]; 448 } bnxt_port_stats_ext_arr[] = { 449 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 450 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 451 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 452 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 453 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 454 BNXT_RX_STATS_EXT_COS_ENTRIES, 455 BNXT_RX_STATS_EXT_PFC_ENTRIES, 456 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 457 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 458 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 459 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 460 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 461 BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks), 462 BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks), 463 BNXT_RX_STATS_EXT_ENTRY(rx_filter_miss), 464 }; 465 466 static const struct { 467 long offset; 468 char string[ETH_GSTRING_LEN]; 469 } bnxt_tx_port_stats_ext_arr[] = { 470 BNXT_TX_STATS_EXT_COS_ENTRIES, 471 BNXT_TX_STATS_EXT_PFC_ENTRIES, 472 }; 473 474 static const struct { 475 long base_off; 476 char string[ETH_GSTRING_LEN]; 477 } bnxt_rx_bytes_pri_arr[] = { 478 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 479 }; 480 481 static const struct { 482 long base_off; 483 char string[ETH_GSTRING_LEN]; 484 } bnxt_rx_pkts_pri_arr[] = { 485 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 486 }; 487 488 static const struct { 489 long base_off; 490 char string[ETH_GSTRING_LEN]; 491 } bnxt_tx_bytes_pri_arr[] = { 492 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 493 }; 494 495 static const struct { 496 long base_off; 497 char string[ETH_GSTRING_LEN]; 498 } bnxt_tx_pkts_pri_arr[] = { 499 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 500 }; 501 502 #define BNXT_NUM_RING_ERR_STATS ARRAY_SIZE(bnxt_ring_err_stats_arr) 503 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 504 #define BNXT_NUM_STATS_PRI \ 505 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 506 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 507 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 508 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 509 510 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 511 { 512 if (BNXT_SUPPORTS_TPA(bp)) { 513 if (bp->max_tpa_v2) { 514 if (BNXT_CHIP_P5(bp)) 515 return BNXT_NUM_TPA_RING_STATS_P5; 516 return BNXT_NUM_TPA_RING_STATS_P7; 517 } 518 return BNXT_NUM_TPA_RING_STATS; 519 } 520 return 0; 521 } 522 523 static int bnxt_get_num_ring_stats(struct bnxt *bp) 524 { 525 int rx, tx, cmn; 526 527 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS + 528 bnxt_get_num_tpa_ring_stats(bp); 529 tx = NUM_RING_TX_HW_STATS; 530 cmn = NUM_RING_CMN_SW_STATS; 531 return rx * bp->rx_nr_rings + 532 tx * (bp->tx_nr_rings_xdp + bp->tx_nr_rings_per_tc) + 533 cmn * bp->cp_nr_rings; 534 } 535 536 static int bnxt_get_num_stats(struct bnxt *bp) 537 { 538 int num_stats = bnxt_get_num_ring_stats(bp); 539 int len; 540 541 num_stats += BNXT_NUM_RING_ERR_STATS; 542 543 if (bp->flags & BNXT_FLAG_PORT_STATS) 544 num_stats += BNXT_NUM_PORT_STATS; 545 546 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 547 len = min_t(int, bp->fw_rx_stats_ext_size, 548 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 549 num_stats += len; 550 len = min_t(int, bp->fw_tx_stats_ext_size, 551 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 552 num_stats += len; 553 if (bp->pri2cos_valid) 554 num_stats += BNXT_NUM_STATS_PRI; 555 } 556 557 return num_stats; 558 } 559 560 static int bnxt_get_sset_count(struct net_device *dev, int sset) 561 { 562 struct bnxt *bp = netdev_priv(dev); 563 564 switch (sset) { 565 case ETH_SS_STATS: 566 return bnxt_get_num_stats(bp); 567 case ETH_SS_TEST: 568 if (!bp->num_tests) 569 return -EOPNOTSUPP; 570 return bp->num_tests; 571 default: 572 return -EOPNOTSUPP; 573 } 574 } 575 576 static bool is_rx_ring(struct bnxt *bp, int ring_num) 577 { 578 return ring_num < bp->rx_nr_rings; 579 } 580 581 static bool is_tx_ring(struct bnxt *bp, int ring_num) 582 { 583 int tx_base = 0; 584 585 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 586 tx_base = bp->rx_nr_rings; 587 588 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings)) 589 return true; 590 return false; 591 } 592 593 static void bnxt_get_ethtool_stats(struct net_device *dev, 594 struct ethtool_stats *stats, u64 *buf) 595 { 596 struct bnxt_total_ring_err_stats ring_err_stats = {0}; 597 struct bnxt *bp = netdev_priv(dev); 598 u64 *curr, *prev; 599 u32 tpa_stats; 600 u32 i, j = 0; 601 602 if (!bp->bnapi) { 603 j += bnxt_get_num_ring_stats(bp); 604 goto skip_ring_stats; 605 } 606 607 tpa_stats = bnxt_get_num_tpa_ring_stats(bp); 608 for (i = 0; i < bp->cp_nr_rings; i++) { 609 struct bnxt_napi *bnapi = bp->bnapi[i]; 610 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 611 u64 *sw_stats = cpr->stats.sw_stats; 612 u64 *sw; 613 int k; 614 615 if (is_rx_ring(bp, i)) { 616 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++) 617 buf[j] = sw_stats[k]; 618 } 619 if (is_tx_ring(bp, i)) { 620 k = NUM_RING_RX_HW_STATS; 621 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 622 j++, k++) 623 buf[j] = sw_stats[k]; 624 } 625 if (!tpa_stats || !is_rx_ring(bp, i)) 626 goto skip_tpa_ring_stats; 627 628 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 629 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS + 630 tpa_stats; j++, k++) 631 buf[j] = sw_stats[k]; 632 633 skip_tpa_ring_stats: 634 sw = (u64 *)&cpr->sw_stats->rx; 635 if (is_rx_ring(bp, i)) { 636 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++) 637 buf[j] = sw[k]; 638 } 639 640 sw = (u64 *)&cpr->sw_stats->cmn; 641 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++) 642 buf[j] = sw[k]; 643 } 644 645 bnxt_get_ring_err_stats(bp, &ring_err_stats); 646 647 skip_ring_stats: 648 curr = &ring_err_stats.rx_total_l4_csum_errors; 649 prev = &bp->ring_err_stats_prev.rx_total_l4_csum_errors; 650 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++, j++, curr++, prev++) 651 buf[j] = *curr + *prev; 652 653 if (bp->flags & BNXT_FLAG_PORT_STATS) { 654 u64 *port_stats = bp->port_stats.sw_stats; 655 656 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) 657 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset); 658 } 659 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 660 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats; 661 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats; 662 u32 len; 663 664 len = min_t(u32, bp->fw_rx_stats_ext_size, 665 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 666 for (i = 0; i < len; i++, j++) { 667 buf[j] = *(rx_port_stats_ext + 668 bnxt_port_stats_ext_arr[i].offset); 669 } 670 len = min_t(u32, bp->fw_tx_stats_ext_size, 671 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 672 for (i = 0; i < len; i++, j++) { 673 buf[j] = *(tx_port_stats_ext + 674 bnxt_tx_port_stats_ext_arr[i].offset); 675 } 676 if (bp->pri2cos_valid) { 677 for (i = 0; i < 8; i++, j++) { 678 long n = bnxt_rx_bytes_pri_arr[i].base_off + 679 bp->pri2cos_idx[i]; 680 681 buf[j] = *(rx_port_stats_ext + n); 682 } 683 for (i = 0; i < 8; i++, j++) { 684 long n = bnxt_rx_pkts_pri_arr[i].base_off + 685 bp->pri2cos_idx[i]; 686 687 buf[j] = *(rx_port_stats_ext + n); 688 } 689 for (i = 0; i < 8; i++, j++) { 690 long n = bnxt_tx_bytes_pri_arr[i].base_off + 691 bp->pri2cos_idx[i]; 692 693 buf[j] = *(tx_port_stats_ext + n); 694 } 695 for (i = 0; i < 8; i++, j++) { 696 long n = bnxt_tx_pkts_pri_arr[i].base_off + 697 bp->pri2cos_idx[i]; 698 699 buf[j] = *(tx_port_stats_ext + n); 700 } 701 } 702 } 703 } 704 705 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 706 { 707 struct bnxt *bp = netdev_priv(dev); 708 static const char * const *str; 709 u32 i, j, num_str; 710 711 switch (stringset) { 712 case ETH_SS_STATS: 713 for (i = 0; i < bp->cp_nr_rings; i++) { 714 if (is_rx_ring(bp, i)) { 715 num_str = NUM_RING_RX_HW_STATS; 716 for (j = 0; j < num_str; j++) { 717 sprintf(buf, "[%d]: %s", i, 718 bnxt_ring_rx_stats_str[j]); 719 buf += ETH_GSTRING_LEN; 720 } 721 } 722 if (is_tx_ring(bp, i)) { 723 num_str = NUM_RING_TX_HW_STATS; 724 for (j = 0; j < num_str; j++) { 725 sprintf(buf, "[%d]: %s", i, 726 bnxt_ring_tx_stats_str[j]); 727 buf += ETH_GSTRING_LEN; 728 } 729 } 730 num_str = bnxt_get_num_tpa_ring_stats(bp); 731 if (!num_str || !is_rx_ring(bp, i)) 732 goto skip_tpa_stats; 733 734 if (bp->max_tpa_v2) 735 str = bnxt_ring_tpa2_stats_str; 736 else 737 str = bnxt_ring_tpa_stats_str; 738 739 for (j = 0; j < num_str; j++) { 740 sprintf(buf, "[%d]: %s", i, str[j]); 741 buf += ETH_GSTRING_LEN; 742 } 743 skip_tpa_stats: 744 if (is_rx_ring(bp, i)) { 745 num_str = NUM_RING_RX_SW_STATS; 746 for (j = 0; j < num_str; j++) { 747 sprintf(buf, "[%d]: %s", i, 748 bnxt_rx_sw_stats_str[j]); 749 buf += ETH_GSTRING_LEN; 750 } 751 } 752 num_str = NUM_RING_CMN_SW_STATS; 753 for (j = 0; j < num_str; j++) { 754 sprintf(buf, "[%d]: %s", i, 755 bnxt_cmn_sw_stats_str[j]); 756 buf += ETH_GSTRING_LEN; 757 } 758 } 759 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++) { 760 strscpy(buf, bnxt_ring_err_stats_arr[i], ETH_GSTRING_LEN); 761 buf += ETH_GSTRING_LEN; 762 } 763 764 if (bp->flags & BNXT_FLAG_PORT_STATS) { 765 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 766 strcpy(buf, bnxt_port_stats_arr[i].string); 767 buf += ETH_GSTRING_LEN; 768 } 769 } 770 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 771 u32 len; 772 773 len = min_t(u32, bp->fw_rx_stats_ext_size, 774 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 775 for (i = 0; i < len; i++) { 776 strcpy(buf, bnxt_port_stats_ext_arr[i].string); 777 buf += ETH_GSTRING_LEN; 778 } 779 len = min_t(u32, bp->fw_tx_stats_ext_size, 780 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 781 for (i = 0; i < len; i++) { 782 strcpy(buf, 783 bnxt_tx_port_stats_ext_arr[i].string); 784 buf += ETH_GSTRING_LEN; 785 } 786 if (bp->pri2cos_valid) { 787 for (i = 0; i < 8; i++) { 788 strcpy(buf, 789 bnxt_rx_bytes_pri_arr[i].string); 790 buf += ETH_GSTRING_LEN; 791 } 792 for (i = 0; i < 8; i++) { 793 strcpy(buf, 794 bnxt_rx_pkts_pri_arr[i].string); 795 buf += ETH_GSTRING_LEN; 796 } 797 for (i = 0; i < 8; i++) { 798 strcpy(buf, 799 bnxt_tx_bytes_pri_arr[i].string); 800 buf += ETH_GSTRING_LEN; 801 } 802 for (i = 0; i < 8; i++) { 803 strcpy(buf, 804 bnxt_tx_pkts_pri_arr[i].string); 805 buf += ETH_GSTRING_LEN; 806 } 807 } 808 } 809 break; 810 case ETH_SS_TEST: 811 if (bp->num_tests) 812 memcpy(buf, bp->test_info->string, 813 bp->num_tests * ETH_GSTRING_LEN); 814 break; 815 default: 816 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 817 stringset); 818 break; 819 } 820 } 821 822 static void bnxt_get_ringparam(struct net_device *dev, 823 struct ethtool_ringparam *ering, 824 struct kernel_ethtool_ringparam *kernel_ering, 825 struct netlink_ext_ack *extack) 826 { 827 struct bnxt *bp = netdev_priv(dev); 828 829 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 830 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA; 831 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 832 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_ENABLED; 833 } else { 834 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 835 ering->rx_jumbo_max_pending = 0; 836 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_DISABLED; 837 } 838 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 839 840 ering->rx_pending = bp->rx_ring_size; 841 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 842 ering->tx_pending = bp->tx_ring_size; 843 } 844 845 static int bnxt_set_ringparam(struct net_device *dev, 846 struct ethtool_ringparam *ering, 847 struct kernel_ethtool_ringparam *kernel_ering, 848 struct netlink_ext_ack *extack) 849 { 850 struct bnxt *bp = netdev_priv(dev); 851 852 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 853 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 854 (ering->tx_pending < BNXT_MIN_TX_DESC_CNT)) 855 return -EINVAL; 856 857 if (netif_running(dev)) 858 bnxt_close_nic(bp, false, false); 859 860 bp->rx_ring_size = ering->rx_pending; 861 bp->tx_ring_size = ering->tx_pending; 862 bnxt_set_ring_params(bp); 863 864 if (netif_running(dev)) 865 return bnxt_open_nic(bp, false, false); 866 867 return 0; 868 } 869 870 static void bnxt_get_channels(struct net_device *dev, 871 struct ethtool_channels *channel) 872 { 873 struct bnxt *bp = netdev_priv(dev); 874 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 875 int max_rx_rings, max_tx_rings, tcs; 876 int max_tx_sch_inputs, tx_grps; 877 878 /* Get the most up-to-date max_tx_sch_inputs. */ 879 if (netif_running(dev) && BNXT_NEW_RM(bp)) 880 bnxt_hwrm_func_resc_qcaps(bp, false); 881 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 882 883 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 884 if (max_tx_sch_inputs) 885 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 886 887 tcs = bp->num_tc; 888 tx_grps = max(tcs, 1); 889 if (bp->tx_nr_rings_xdp) 890 tx_grps++; 891 max_tx_rings /= tx_grps; 892 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 893 894 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 895 max_rx_rings = 0; 896 max_tx_rings = 0; 897 } 898 if (max_tx_sch_inputs) 899 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 900 901 if (tcs > 1) 902 max_tx_rings /= tcs; 903 904 channel->max_rx = max_rx_rings; 905 channel->max_tx = max_tx_rings; 906 channel->max_other = 0; 907 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 908 channel->combined_count = bp->rx_nr_rings; 909 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 910 channel->combined_count--; 911 } else { 912 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 913 channel->rx_count = bp->rx_nr_rings; 914 channel->tx_count = bp->tx_nr_rings_per_tc; 915 } 916 } 917 } 918 919 static int bnxt_set_channels(struct net_device *dev, 920 struct ethtool_channels *channel) 921 { 922 struct bnxt *bp = netdev_priv(dev); 923 int req_tx_rings, req_rx_rings, tcs; 924 bool sh = false; 925 int tx_xdp = 0; 926 int rc = 0; 927 int tx_cp; 928 929 if (channel->other_count) 930 return -EINVAL; 931 932 if (!channel->combined_count && 933 (!channel->rx_count || !channel->tx_count)) 934 return -EINVAL; 935 936 if (channel->combined_count && 937 (channel->rx_count || channel->tx_count)) 938 return -EINVAL; 939 940 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 941 channel->tx_count)) 942 return -EINVAL; 943 944 if (channel->combined_count) 945 sh = true; 946 947 tcs = bp->num_tc; 948 949 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 950 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 951 if (bp->tx_nr_rings_xdp) { 952 if (!sh) { 953 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 954 return -EINVAL; 955 } 956 tx_xdp = req_rx_rings; 957 } 958 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 959 if (rc) { 960 netdev_warn(dev, "Unable to allocate the requested rings\n"); 961 return rc; 962 } 963 964 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) != 965 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) && 966 netif_is_rxfh_configured(dev)) { 967 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n"); 968 return -EINVAL; 969 } 970 971 bnxt_clear_usr_fltrs(bp, true); 972 if (BNXT_SUPPORTS_MULTI_RSS_CTX(bp)) 973 bnxt_clear_rss_ctxs(bp); 974 if (netif_running(dev)) { 975 if (BNXT_PF(bp)) { 976 /* TODO CHIMP_FW: Send message to all VF's 977 * before PF unload 978 */ 979 } 980 bnxt_close_nic(bp, true, false); 981 } 982 983 if (sh) { 984 bp->flags |= BNXT_FLAG_SHARED_RINGS; 985 bp->rx_nr_rings = channel->combined_count; 986 bp->tx_nr_rings_per_tc = channel->combined_count; 987 } else { 988 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 989 bp->rx_nr_rings = channel->rx_count; 990 bp->tx_nr_rings_per_tc = channel->tx_count; 991 } 992 bp->tx_nr_rings_xdp = tx_xdp; 993 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 994 if (tcs > 1) 995 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 996 997 tx_cp = bnxt_num_tx_to_cp(bp, bp->tx_nr_rings); 998 bp->cp_nr_rings = sh ? max_t(int, tx_cp, bp->rx_nr_rings) : 999 tx_cp + bp->rx_nr_rings; 1000 1001 /* After changing number of rx channels, update NTUPLE feature. */ 1002 netdev_update_features(dev); 1003 if (netif_running(dev)) { 1004 rc = bnxt_open_nic(bp, true, false); 1005 if ((!rc) && BNXT_PF(bp)) { 1006 /* TODO CHIMP_FW: Send message to all VF's 1007 * to renable 1008 */ 1009 } 1010 } else { 1011 rc = bnxt_reserve_rings(bp, true); 1012 } 1013 1014 return rc; 1015 } 1016 1017 static u32 bnxt_get_all_fltr_ids_rcu(struct bnxt *bp, struct hlist_head tbl[], 1018 int tbl_size, u32 *ids, u32 start, 1019 u32 id_cnt) 1020 { 1021 int i, j = start; 1022 1023 if (j >= id_cnt) 1024 return j; 1025 for (i = 0; i < tbl_size; i++) { 1026 struct hlist_head *head; 1027 struct bnxt_filter_base *fltr; 1028 1029 head = &tbl[i]; 1030 hlist_for_each_entry_rcu(fltr, head, hash) { 1031 if (!fltr->flags || 1032 test_bit(BNXT_FLTR_FW_DELETED, &fltr->state)) 1033 continue; 1034 ids[j++] = fltr->sw_id; 1035 if (j == id_cnt) 1036 return j; 1037 } 1038 } 1039 return j; 1040 } 1041 1042 static struct bnxt_filter_base *bnxt_get_one_fltr_rcu(struct bnxt *bp, 1043 struct hlist_head tbl[], 1044 int tbl_size, u32 id) 1045 { 1046 int i; 1047 1048 for (i = 0; i < tbl_size; i++) { 1049 struct hlist_head *head; 1050 struct bnxt_filter_base *fltr; 1051 1052 head = &tbl[i]; 1053 hlist_for_each_entry_rcu(fltr, head, hash) { 1054 if (fltr->flags && fltr->sw_id == id) 1055 return fltr; 1056 } 1057 } 1058 return NULL; 1059 } 1060 1061 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 1062 u32 *rule_locs) 1063 { 1064 u32 count; 1065 1066 cmd->data = bp->ntp_fltr_count; 1067 rcu_read_lock(); 1068 count = bnxt_get_all_fltr_ids_rcu(bp, bp->l2_fltr_hash_tbl, 1069 BNXT_L2_FLTR_HASH_SIZE, rule_locs, 0, 1070 cmd->rule_cnt); 1071 cmd->rule_cnt = bnxt_get_all_fltr_ids_rcu(bp, bp->ntp_fltr_hash_tbl, 1072 BNXT_NTP_FLTR_HASH_SIZE, 1073 rule_locs, count, 1074 cmd->rule_cnt); 1075 rcu_read_unlock(); 1076 1077 return 0; 1078 } 1079 1080 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1081 { 1082 struct ethtool_rx_flow_spec *fs = 1083 (struct ethtool_rx_flow_spec *)&cmd->fs; 1084 struct bnxt_filter_base *fltr_base; 1085 struct bnxt_ntuple_filter *fltr; 1086 struct bnxt_flow_masks *fmasks; 1087 struct flow_keys *fkeys; 1088 int rc = -EINVAL; 1089 1090 if (fs->location >= bp->max_fltr) 1091 return rc; 1092 1093 rcu_read_lock(); 1094 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl, 1095 BNXT_L2_FLTR_HASH_SIZE, 1096 fs->location); 1097 if (fltr_base) { 1098 struct ethhdr *h_ether = &fs->h_u.ether_spec; 1099 struct ethhdr *m_ether = &fs->m_u.ether_spec; 1100 struct bnxt_l2_filter *l2_fltr; 1101 struct bnxt_l2_key *l2_key; 1102 1103 l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base); 1104 l2_key = &l2_fltr->l2_key; 1105 fs->flow_type = ETHER_FLOW; 1106 ether_addr_copy(h_ether->h_dest, l2_key->dst_mac_addr); 1107 eth_broadcast_addr(m_ether->h_dest); 1108 if (l2_key->vlan) { 1109 struct ethtool_flow_ext *m_ext = &fs->m_ext; 1110 struct ethtool_flow_ext *h_ext = &fs->h_ext; 1111 1112 fs->flow_type |= FLOW_EXT; 1113 m_ext->vlan_tci = htons(0xfff); 1114 h_ext->vlan_tci = htons(l2_key->vlan); 1115 } 1116 if (fltr_base->flags & BNXT_ACT_RING_DST) 1117 fs->ring_cookie = fltr_base->rxq; 1118 if (fltr_base->flags & BNXT_ACT_FUNC_DST) 1119 fs->ring_cookie = (u64)(fltr_base->vf_idx + 1) << 1120 ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 1121 rcu_read_unlock(); 1122 return 0; 1123 } 1124 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl, 1125 BNXT_NTP_FLTR_HASH_SIZE, 1126 fs->location); 1127 if (!fltr_base) { 1128 rcu_read_unlock(); 1129 return rc; 1130 } 1131 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base); 1132 1133 fkeys = &fltr->fkeys; 1134 fmasks = &fltr->fmasks; 1135 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 1136 if (fkeys->basic.ip_proto == IPPROTO_ICMP || 1137 fkeys->basic.ip_proto == IPPROTO_RAW) { 1138 fs->flow_type = IP_USER_FLOW; 1139 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 1140 if (fkeys->basic.ip_proto == IPPROTO_ICMP) 1141 fs->h_u.usr_ip4_spec.proto = IPPROTO_ICMP; 1142 else 1143 fs->h_u.usr_ip4_spec.proto = IPPROTO_RAW; 1144 fs->m_u.usr_ip4_spec.proto = BNXT_IP_PROTO_FULL_MASK; 1145 } else if (fkeys->basic.ip_proto == IPPROTO_TCP) { 1146 fs->flow_type = TCP_V4_FLOW; 1147 } else if (fkeys->basic.ip_proto == IPPROTO_UDP) { 1148 fs->flow_type = UDP_V4_FLOW; 1149 } else { 1150 goto fltr_err; 1151 } 1152 1153 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 1154 fs->m_u.tcp_ip4_spec.ip4src = fmasks->addrs.v4addrs.src; 1155 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 1156 fs->m_u.tcp_ip4_spec.ip4dst = fmasks->addrs.v4addrs.dst; 1157 if (fs->flow_type == TCP_V4_FLOW || 1158 fs->flow_type == UDP_V4_FLOW) { 1159 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 1160 fs->m_u.tcp_ip4_spec.psrc = fmasks->ports.src; 1161 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 1162 fs->m_u.tcp_ip4_spec.pdst = fmasks->ports.dst; 1163 } 1164 } else { 1165 if (fkeys->basic.ip_proto == IPPROTO_ICMPV6 || 1166 fkeys->basic.ip_proto == IPPROTO_RAW) { 1167 fs->flow_type = IPV6_USER_FLOW; 1168 if (fkeys->basic.ip_proto == IPPROTO_ICMPV6) 1169 fs->h_u.usr_ip6_spec.l4_proto = IPPROTO_ICMPV6; 1170 else 1171 fs->h_u.usr_ip6_spec.l4_proto = IPPROTO_RAW; 1172 fs->m_u.usr_ip6_spec.l4_proto = BNXT_IP_PROTO_FULL_MASK; 1173 } else if (fkeys->basic.ip_proto == IPPROTO_TCP) { 1174 fs->flow_type = TCP_V6_FLOW; 1175 } else if (fkeys->basic.ip_proto == IPPROTO_UDP) { 1176 fs->flow_type = UDP_V6_FLOW; 1177 } else { 1178 goto fltr_err; 1179 } 1180 1181 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 1182 fkeys->addrs.v6addrs.src; 1183 *(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6src[0] = 1184 fmasks->addrs.v6addrs.src; 1185 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 1186 fkeys->addrs.v6addrs.dst; 1187 *(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6dst[0] = 1188 fmasks->addrs.v6addrs.dst; 1189 if (fs->flow_type == TCP_V6_FLOW || 1190 fs->flow_type == UDP_V6_FLOW) { 1191 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 1192 fs->m_u.tcp_ip6_spec.psrc = fmasks->ports.src; 1193 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 1194 fs->m_u.tcp_ip6_spec.pdst = fmasks->ports.dst; 1195 } 1196 } 1197 1198 if (fltr->base.flags & BNXT_ACT_DROP) 1199 fs->ring_cookie = RX_CLS_FLOW_DISC; 1200 else 1201 fs->ring_cookie = fltr->base.rxq; 1202 rc = 0; 1203 1204 fltr_err: 1205 rcu_read_unlock(); 1206 1207 return rc; 1208 } 1209 1210 static struct bnxt_rss_ctx *bnxt_get_rss_ctx_from_index(struct bnxt *bp, 1211 u32 index) 1212 { 1213 struct ethtool_rxfh_context *ctx; 1214 1215 ctx = xa_load(&bp->dev->ethtool->rss_ctx, index); 1216 if (!ctx) 1217 return NULL; 1218 return ethtool_rxfh_context_priv(ctx); 1219 } 1220 1221 static int bnxt_alloc_vnic_rss_table(struct bnxt *bp, 1222 struct bnxt_vnic_info *vnic) 1223 { 1224 int size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5); 1225 1226 vnic->rss_table_size = size + HW_HASH_KEY_SIZE; 1227 vnic->rss_table = dma_alloc_coherent(&bp->pdev->dev, 1228 vnic->rss_table_size, 1229 &vnic->rss_table_dma_addr, 1230 GFP_KERNEL); 1231 if (!vnic->rss_table) 1232 return -ENOMEM; 1233 1234 vnic->rss_hash_key = ((void *)vnic->rss_table) + size; 1235 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; 1236 return 0; 1237 } 1238 1239 static int bnxt_add_l2_cls_rule(struct bnxt *bp, 1240 struct ethtool_rx_flow_spec *fs) 1241 { 1242 u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1243 u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1244 struct ethhdr *h_ether = &fs->h_u.ether_spec; 1245 struct ethhdr *m_ether = &fs->m_u.ether_spec; 1246 struct bnxt_l2_filter *fltr; 1247 struct bnxt_l2_key key; 1248 u16 vnic_id; 1249 u8 flags; 1250 int rc; 1251 1252 if (BNXT_CHIP_P5_PLUS(bp)) 1253 return -EOPNOTSUPP; 1254 1255 if (!is_broadcast_ether_addr(m_ether->h_dest)) 1256 return -EINVAL; 1257 ether_addr_copy(key.dst_mac_addr, h_ether->h_dest); 1258 key.vlan = 0; 1259 if (fs->flow_type & FLOW_EXT) { 1260 struct ethtool_flow_ext *m_ext = &fs->m_ext; 1261 struct ethtool_flow_ext *h_ext = &fs->h_ext; 1262 1263 if (m_ext->vlan_tci != htons(0xfff) || !h_ext->vlan_tci) 1264 return -EINVAL; 1265 key.vlan = ntohs(h_ext->vlan_tci); 1266 } 1267 1268 if (vf) { 1269 flags = BNXT_ACT_FUNC_DST; 1270 vnic_id = 0xffff; 1271 vf--; 1272 } else { 1273 flags = BNXT_ACT_RING_DST; 1274 vnic_id = bp->vnic_info[ring + 1].fw_vnic_id; 1275 } 1276 fltr = bnxt_alloc_new_l2_filter(bp, &key, flags); 1277 if (IS_ERR(fltr)) 1278 return PTR_ERR(fltr); 1279 1280 fltr->base.fw_vnic_id = vnic_id; 1281 fltr->base.rxq = ring; 1282 fltr->base.vf_idx = vf; 1283 rc = bnxt_hwrm_l2_filter_alloc(bp, fltr); 1284 if (rc) 1285 bnxt_del_l2_filter(bp, fltr); 1286 else 1287 fs->location = fltr->base.sw_id; 1288 return rc; 1289 } 1290 1291 static bool bnxt_verify_ntuple_ip4_flow(struct ethtool_usrip4_spec *ip_spec, 1292 struct ethtool_usrip4_spec *ip_mask) 1293 { 1294 if (ip_mask->l4_4_bytes || ip_mask->tos || 1295 ip_spec->ip_ver != ETH_RX_NFC_IP4 || 1296 ip_mask->proto != BNXT_IP_PROTO_FULL_MASK || 1297 (ip_spec->proto != IPPROTO_RAW && ip_spec->proto != IPPROTO_ICMP)) 1298 return false; 1299 return true; 1300 } 1301 1302 static bool bnxt_verify_ntuple_ip6_flow(struct ethtool_usrip6_spec *ip_spec, 1303 struct ethtool_usrip6_spec *ip_mask) 1304 { 1305 if (ip_mask->l4_4_bytes || ip_mask->tclass || 1306 ip_mask->l4_proto != BNXT_IP_PROTO_FULL_MASK || 1307 (ip_spec->l4_proto != IPPROTO_RAW && 1308 ip_spec->l4_proto != IPPROTO_ICMPV6)) 1309 return false; 1310 return true; 1311 } 1312 1313 static int bnxt_add_ntuple_cls_rule(struct bnxt *bp, 1314 struct ethtool_rxnfc *cmd) 1315 { 1316 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1317 struct bnxt_ntuple_filter *new_fltr, *fltr; 1318 u32 flow_type = fs->flow_type & 0xff; 1319 struct bnxt_l2_filter *l2_fltr; 1320 struct bnxt_flow_masks *fmasks; 1321 struct flow_keys *fkeys; 1322 u32 idx, ring; 1323 int rc; 1324 u8 vf; 1325 1326 if (!bp->vnic_info) 1327 return -EAGAIN; 1328 1329 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1330 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1331 if ((fs->flow_type & (FLOW_MAC_EXT | FLOW_EXT)) || vf) 1332 return -EOPNOTSUPP; 1333 1334 if (flow_type == IP_USER_FLOW) { 1335 if (!bnxt_verify_ntuple_ip4_flow(&fs->h_u.usr_ip4_spec, 1336 &fs->m_u.usr_ip4_spec)) 1337 return -EOPNOTSUPP; 1338 } 1339 1340 if (flow_type == IPV6_USER_FLOW) { 1341 if (!bnxt_verify_ntuple_ip6_flow(&fs->h_u.usr_ip6_spec, 1342 &fs->m_u.usr_ip6_spec)) 1343 return -EOPNOTSUPP; 1344 } 1345 1346 new_fltr = kzalloc(sizeof(*new_fltr), GFP_KERNEL); 1347 if (!new_fltr) 1348 return -ENOMEM; 1349 1350 l2_fltr = bp->vnic_info[BNXT_VNIC_DEFAULT].l2_filters[0]; 1351 atomic_inc(&l2_fltr->refcnt); 1352 new_fltr->l2_fltr = l2_fltr; 1353 fmasks = &new_fltr->fmasks; 1354 fkeys = &new_fltr->fkeys; 1355 1356 rc = -EOPNOTSUPP; 1357 switch (flow_type) { 1358 case IP_USER_FLOW: { 1359 struct ethtool_usrip4_spec *ip_spec = &fs->h_u.usr_ip4_spec; 1360 struct ethtool_usrip4_spec *ip_mask = &fs->m_u.usr_ip4_spec; 1361 1362 fkeys->basic.ip_proto = ip_spec->proto; 1363 fkeys->basic.n_proto = htons(ETH_P_IP); 1364 fkeys->addrs.v4addrs.src = ip_spec->ip4src; 1365 fmasks->addrs.v4addrs.src = ip_mask->ip4src; 1366 fkeys->addrs.v4addrs.dst = ip_spec->ip4dst; 1367 fmasks->addrs.v4addrs.dst = ip_mask->ip4dst; 1368 break; 1369 } 1370 case TCP_V4_FLOW: 1371 case UDP_V4_FLOW: { 1372 struct ethtool_tcpip4_spec *ip_spec = &fs->h_u.tcp_ip4_spec; 1373 struct ethtool_tcpip4_spec *ip_mask = &fs->m_u.tcp_ip4_spec; 1374 1375 fkeys->basic.ip_proto = IPPROTO_TCP; 1376 if (flow_type == UDP_V4_FLOW) 1377 fkeys->basic.ip_proto = IPPROTO_UDP; 1378 fkeys->basic.n_proto = htons(ETH_P_IP); 1379 fkeys->addrs.v4addrs.src = ip_spec->ip4src; 1380 fmasks->addrs.v4addrs.src = ip_mask->ip4src; 1381 fkeys->addrs.v4addrs.dst = ip_spec->ip4dst; 1382 fmasks->addrs.v4addrs.dst = ip_mask->ip4dst; 1383 fkeys->ports.src = ip_spec->psrc; 1384 fmasks->ports.src = ip_mask->psrc; 1385 fkeys->ports.dst = ip_spec->pdst; 1386 fmasks->ports.dst = ip_mask->pdst; 1387 break; 1388 } 1389 case IPV6_USER_FLOW: { 1390 struct ethtool_usrip6_spec *ip_spec = &fs->h_u.usr_ip6_spec; 1391 struct ethtool_usrip6_spec *ip_mask = &fs->m_u.usr_ip6_spec; 1392 1393 fkeys->basic.ip_proto = ip_spec->l4_proto; 1394 fkeys->basic.n_proto = htons(ETH_P_IPV6); 1395 fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src; 1396 fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src; 1397 fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst; 1398 fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst; 1399 break; 1400 } 1401 case TCP_V6_FLOW: 1402 case UDP_V6_FLOW: { 1403 struct ethtool_tcpip6_spec *ip_spec = &fs->h_u.tcp_ip6_spec; 1404 struct ethtool_tcpip6_spec *ip_mask = &fs->m_u.tcp_ip6_spec; 1405 1406 fkeys->basic.ip_proto = IPPROTO_TCP; 1407 if (flow_type == UDP_V6_FLOW) 1408 fkeys->basic.ip_proto = IPPROTO_UDP; 1409 fkeys->basic.n_proto = htons(ETH_P_IPV6); 1410 1411 fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src; 1412 fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src; 1413 fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst; 1414 fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst; 1415 fkeys->ports.src = ip_spec->psrc; 1416 fmasks->ports.src = ip_mask->psrc; 1417 fkeys->ports.dst = ip_spec->pdst; 1418 fmasks->ports.dst = ip_mask->pdst; 1419 break; 1420 } 1421 default: 1422 rc = -EOPNOTSUPP; 1423 goto ntuple_err; 1424 } 1425 if (!memcmp(&BNXT_FLOW_MASK_NONE, fmasks, sizeof(*fmasks))) 1426 goto ntuple_err; 1427 1428 idx = bnxt_get_ntp_filter_idx(bp, fkeys, NULL); 1429 rcu_read_lock(); 1430 fltr = bnxt_lookup_ntp_filter_from_idx(bp, new_fltr, idx); 1431 if (fltr) { 1432 rcu_read_unlock(); 1433 rc = -EEXIST; 1434 goto ntuple_err; 1435 } 1436 rcu_read_unlock(); 1437 1438 new_fltr->base.flags = BNXT_ACT_NO_AGING; 1439 if (fs->flow_type & FLOW_RSS) { 1440 struct bnxt_rss_ctx *rss_ctx; 1441 1442 new_fltr->base.fw_vnic_id = 0; 1443 new_fltr->base.flags |= BNXT_ACT_RSS_CTX; 1444 rss_ctx = bnxt_get_rss_ctx_from_index(bp, cmd->rss_context); 1445 if (rss_ctx) { 1446 new_fltr->base.fw_vnic_id = rss_ctx->index; 1447 } else { 1448 rc = -EINVAL; 1449 goto ntuple_err; 1450 } 1451 } 1452 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1453 new_fltr->base.flags |= BNXT_ACT_DROP; 1454 else 1455 new_fltr->base.rxq = ring; 1456 __set_bit(BNXT_FLTR_VALID, &new_fltr->base.state); 1457 rc = bnxt_insert_ntp_filter(bp, new_fltr, idx); 1458 if (!rc) { 1459 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, new_fltr); 1460 if (rc) { 1461 bnxt_del_ntp_filter(bp, new_fltr); 1462 return rc; 1463 } 1464 fs->location = new_fltr->base.sw_id; 1465 return 0; 1466 } 1467 1468 ntuple_err: 1469 atomic_dec(&l2_fltr->refcnt); 1470 kfree(new_fltr); 1471 return rc; 1472 } 1473 1474 static int bnxt_srxclsrlins(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1475 { 1476 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1477 u32 ring, flow_type; 1478 int rc; 1479 u8 vf; 1480 1481 if (!netif_running(bp->dev)) 1482 return -EAGAIN; 1483 if (!(bp->flags & BNXT_FLAG_RFS)) 1484 return -EPERM; 1485 if (fs->location != RX_CLS_LOC_ANY) 1486 return -EINVAL; 1487 1488 flow_type = fs->flow_type; 1489 if ((flow_type == IP_USER_FLOW || 1490 flow_type == IPV6_USER_FLOW) && 1491 !(bp->fw_cap & BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO)) 1492 return -EOPNOTSUPP; 1493 if (flow_type & FLOW_MAC_EXT) 1494 return -EINVAL; 1495 flow_type &= ~FLOW_EXT; 1496 1497 if (fs->ring_cookie == RX_CLS_FLOW_DISC && flow_type != ETHER_FLOW) 1498 return bnxt_add_ntuple_cls_rule(bp, cmd); 1499 1500 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1501 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1502 if (BNXT_VF(bp) && vf) 1503 return -EINVAL; 1504 if (BNXT_PF(bp) && vf > bp->pf.active_vfs) 1505 return -EINVAL; 1506 if (!vf && ring >= bp->rx_nr_rings) 1507 return -EINVAL; 1508 1509 if (flow_type == ETHER_FLOW) 1510 rc = bnxt_add_l2_cls_rule(bp, fs); 1511 else 1512 rc = bnxt_add_ntuple_cls_rule(bp, cmd); 1513 return rc; 1514 } 1515 1516 static int bnxt_srxclsrldel(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1517 { 1518 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1519 struct bnxt_filter_base *fltr_base; 1520 struct bnxt_ntuple_filter *fltr; 1521 u32 id = fs->location; 1522 1523 rcu_read_lock(); 1524 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl, 1525 BNXT_L2_FLTR_HASH_SIZE, id); 1526 if (fltr_base) { 1527 struct bnxt_l2_filter *l2_fltr; 1528 1529 l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base); 1530 rcu_read_unlock(); 1531 bnxt_hwrm_l2_filter_free(bp, l2_fltr); 1532 bnxt_del_l2_filter(bp, l2_fltr); 1533 return 0; 1534 } 1535 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl, 1536 BNXT_NTP_FLTR_HASH_SIZE, id); 1537 if (!fltr_base) { 1538 rcu_read_unlock(); 1539 return -ENOENT; 1540 } 1541 1542 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base); 1543 if (!(fltr->base.flags & BNXT_ACT_NO_AGING)) { 1544 rcu_read_unlock(); 1545 return -EINVAL; 1546 } 1547 rcu_read_unlock(); 1548 bnxt_hwrm_cfa_ntuple_filter_free(bp, fltr); 1549 bnxt_del_ntp_filter(bp, fltr); 1550 return 0; 1551 } 1552 1553 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1554 { 1555 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1556 return RXH_IP_SRC | RXH_IP_DST; 1557 return 0; 1558 } 1559 1560 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1561 { 1562 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1563 return RXH_IP_SRC | RXH_IP_DST; 1564 return 0; 1565 } 1566 1567 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1568 { 1569 cmd->data = 0; 1570 switch (cmd->flow_type) { 1571 case TCP_V4_FLOW: 1572 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1573 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1574 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1575 cmd->data |= get_ethtool_ipv4_rss(bp); 1576 break; 1577 case UDP_V4_FLOW: 1578 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1579 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1580 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1581 fallthrough; 1582 case AH_ESP_V4_FLOW: 1583 if (bp->rss_hash_cfg & 1584 (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1585 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4)) 1586 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1587 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1588 fallthrough; 1589 case SCTP_V4_FLOW: 1590 case AH_V4_FLOW: 1591 case ESP_V4_FLOW: 1592 case IPV4_FLOW: 1593 cmd->data |= get_ethtool_ipv4_rss(bp); 1594 break; 1595 1596 case TCP_V6_FLOW: 1597 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1598 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1599 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1600 cmd->data |= get_ethtool_ipv6_rss(bp); 1601 break; 1602 case UDP_V6_FLOW: 1603 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1604 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1605 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1606 fallthrough; 1607 case AH_ESP_V6_FLOW: 1608 if (bp->rss_hash_cfg & 1609 (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1610 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6)) 1611 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1612 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1613 fallthrough; 1614 case SCTP_V6_FLOW: 1615 case AH_V6_FLOW: 1616 case ESP_V6_FLOW: 1617 case IPV6_FLOW: 1618 cmd->data |= get_ethtool_ipv6_rss(bp); 1619 break; 1620 } 1621 return 0; 1622 } 1623 1624 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1625 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1626 1627 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1628 { 1629 u32 rss_hash_cfg = bp->rss_hash_cfg; 1630 int tuple, rc = 0; 1631 1632 if (cmd->data == RXH_4TUPLE) 1633 tuple = 4; 1634 else if (cmd->data == RXH_2TUPLE) 1635 tuple = 2; 1636 else if (!cmd->data) 1637 tuple = 0; 1638 else 1639 return -EINVAL; 1640 1641 if (cmd->flow_type == TCP_V4_FLOW) { 1642 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1643 if (tuple == 4) 1644 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1645 } else if (cmd->flow_type == UDP_V4_FLOW) { 1646 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP)) 1647 return -EINVAL; 1648 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1649 if (tuple == 4) 1650 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1651 } else if (cmd->flow_type == TCP_V6_FLOW) { 1652 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1653 if (tuple == 4) 1654 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1655 } else if (cmd->flow_type == UDP_V6_FLOW) { 1656 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP)) 1657 return -EINVAL; 1658 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1659 if (tuple == 4) 1660 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1661 } else if (cmd->flow_type == AH_ESP_V4_FLOW) { 1662 if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V4_RSS_CAP) || 1663 !(bp->rss_cap & BNXT_RSS_CAP_ESP_V4_RSS_CAP))) 1664 return -EINVAL; 1665 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1666 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4); 1667 if (tuple == 4) 1668 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1669 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4; 1670 } else if (cmd->flow_type == AH_ESP_V6_FLOW) { 1671 if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V6_RSS_CAP) || 1672 !(bp->rss_cap & BNXT_RSS_CAP_ESP_V6_RSS_CAP))) 1673 return -EINVAL; 1674 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1675 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6); 1676 if (tuple == 4) 1677 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1678 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6; 1679 } else if (tuple == 4) { 1680 return -EINVAL; 1681 } 1682 1683 switch (cmd->flow_type) { 1684 case TCP_V4_FLOW: 1685 case UDP_V4_FLOW: 1686 case SCTP_V4_FLOW: 1687 case AH_ESP_V4_FLOW: 1688 case AH_V4_FLOW: 1689 case ESP_V4_FLOW: 1690 case IPV4_FLOW: 1691 if (tuple == 2) 1692 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1693 else if (!tuple) 1694 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1695 break; 1696 1697 case TCP_V6_FLOW: 1698 case UDP_V6_FLOW: 1699 case SCTP_V6_FLOW: 1700 case AH_ESP_V6_FLOW: 1701 case AH_V6_FLOW: 1702 case ESP_V6_FLOW: 1703 case IPV6_FLOW: 1704 if (tuple == 2) 1705 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1706 else if (!tuple) 1707 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1708 break; 1709 } 1710 1711 if (bp->rss_hash_cfg == rss_hash_cfg) 1712 return 0; 1713 1714 if (bp->rss_cap & BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA) 1715 bp->rss_hash_delta = bp->rss_hash_cfg ^ rss_hash_cfg; 1716 bp->rss_hash_cfg = rss_hash_cfg; 1717 if (netif_running(bp->dev)) { 1718 bnxt_close_nic(bp, false, false); 1719 rc = bnxt_open_nic(bp, false, false); 1720 } 1721 return rc; 1722 } 1723 1724 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1725 u32 *rule_locs) 1726 { 1727 struct bnxt *bp = netdev_priv(dev); 1728 int rc = 0; 1729 1730 switch (cmd->cmd) { 1731 case ETHTOOL_GRXRINGS: 1732 cmd->data = bp->rx_nr_rings; 1733 break; 1734 1735 case ETHTOOL_GRXCLSRLCNT: 1736 cmd->rule_cnt = bp->ntp_fltr_count; 1737 cmd->data = bp->max_fltr | RX_CLS_LOC_SPECIAL; 1738 break; 1739 1740 case ETHTOOL_GRXCLSRLALL: 1741 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1742 break; 1743 1744 case ETHTOOL_GRXCLSRULE: 1745 rc = bnxt_grxclsrule(bp, cmd); 1746 break; 1747 1748 case ETHTOOL_GRXFH: 1749 rc = bnxt_grxfh(bp, cmd); 1750 break; 1751 1752 default: 1753 rc = -EOPNOTSUPP; 1754 break; 1755 } 1756 1757 return rc; 1758 } 1759 1760 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1761 { 1762 struct bnxt *bp = netdev_priv(dev); 1763 int rc; 1764 1765 switch (cmd->cmd) { 1766 case ETHTOOL_SRXFH: 1767 rc = bnxt_srxfh(bp, cmd); 1768 break; 1769 1770 case ETHTOOL_SRXCLSRLINS: 1771 rc = bnxt_srxclsrlins(bp, cmd); 1772 break; 1773 1774 case ETHTOOL_SRXCLSRLDEL: 1775 rc = bnxt_srxclsrldel(bp, cmd); 1776 break; 1777 1778 default: 1779 rc = -EOPNOTSUPP; 1780 break; 1781 } 1782 return rc; 1783 } 1784 1785 u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1786 { 1787 struct bnxt *bp = netdev_priv(dev); 1788 1789 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) 1790 return bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) * 1791 BNXT_RSS_TABLE_ENTRIES_P5; 1792 return HW_HASH_INDEX_SIZE; 1793 } 1794 1795 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1796 { 1797 return HW_HASH_KEY_SIZE; 1798 } 1799 1800 static int bnxt_get_rxfh(struct net_device *dev, 1801 struct ethtool_rxfh_param *rxfh) 1802 { 1803 struct bnxt_rss_ctx *rss_ctx = NULL; 1804 struct bnxt *bp = netdev_priv(dev); 1805 u32 *indir_tbl = bp->rss_indir_tbl; 1806 struct bnxt_vnic_info *vnic; 1807 u32 i, tbl_size; 1808 1809 rxfh->hfunc = ETH_RSS_HASH_TOP; 1810 1811 if (!bp->vnic_info) 1812 return 0; 1813 1814 vnic = &bp->vnic_info[BNXT_VNIC_DEFAULT]; 1815 if (rxfh->rss_context) { 1816 struct ethtool_rxfh_context *ctx; 1817 1818 ctx = xa_load(&bp->dev->ethtool->rss_ctx, rxfh->rss_context); 1819 if (!ctx) 1820 return -EINVAL; 1821 indir_tbl = ethtool_rxfh_context_indir(ctx); 1822 rss_ctx = ethtool_rxfh_context_priv(ctx); 1823 vnic = &rss_ctx->vnic; 1824 } 1825 1826 if (rxfh->indir && indir_tbl) { 1827 tbl_size = bnxt_get_rxfh_indir_size(dev); 1828 for (i = 0; i < tbl_size; i++) 1829 rxfh->indir[i] = indir_tbl[i]; 1830 } 1831 1832 if (rxfh->key && vnic->rss_hash_key) 1833 memcpy(rxfh->key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1834 1835 return 0; 1836 } 1837 1838 static void bnxt_modify_rss(struct bnxt *bp, struct ethtool_rxfh_context *ctx, 1839 struct bnxt_rss_ctx *rss_ctx, 1840 const struct ethtool_rxfh_param *rxfh) 1841 { 1842 if (rxfh->key) { 1843 if (rss_ctx) { 1844 memcpy(rss_ctx->vnic.rss_hash_key, rxfh->key, 1845 HW_HASH_KEY_SIZE); 1846 } else { 1847 memcpy(bp->rss_hash_key, rxfh->key, HW_HASH_KEY_SIZE); 1848 bp->rss_hash_key_updated = true; 1849 } 1850 } 1851 if (rxfh->indir) { 1852 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(bp->dev); 1853 u32 *indir_tbl = bp->rss_indir_tbl; 1854 1855 if (rss_ctx) 1856 indir_tbl = ethtool_rxfh_context_indir(ctx); 1857 for (i = 0; i < tbl_size; i++) 1858 indir_tbl[i] = rxfh->indir[i]; 1859 pad = bp->rss_indir_tbl_entries - tbl_size; 1860 if (pad) 1861 memset(&indir_tbl[i], 0, pad * sizeof(*indir_tbl)); 1862 } 1863 } 1864 1865 static int bnxt_rxfh_context_check(struct bnxt *bp, 1866 const struct ethtool_rxfh_param *rxfh, 1867 struct netlink_ext_ack *extack) 1868 { 1869 if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP) { 1870 NL_SET_ERR_MSG_MOD(extack, "RSS hash function not supported"); 1871 return -EOPNOTSUPP; 1872 } 1873 1874 if (!BNXT_SUPPORTS_MULTI_RSS_CTX(bp)) { 1875 NL_SET_ERR_MSG_MOD(extack, "RSS contexts not supported"); 1876 return -EOPNOTSUPP; 1877 } 1878 1879 if (!netif_running(bp->dev)) { 1880 NL_SET_ERR_MSG_MOD(extack, "Unable to set RSS contexts when interface is down"); 1881 return -EAGAIN; 1882 } 1883 1884 return 0; 1885 } 1886 1887 static int bnxt_create_rxfh_context(struct net_device *dev, 1888 struct ethtool_rxfh_context *ctx, 1889 const struct ethtool_rxfh_param *rxfh, 1890 struct netlink_ext_ack *extack) 1891 { 1892 struct bnxt *bp = netdev_priv(dev); 1893 struct bnxt_rss_ctx *rss_ctx; 1894 struct bnxt_vnic_info *vnic; 1895 int rc; 1896 1897 rc = bnxt_rxfh_context_check(bp, rxfh, extack); 1898 if (rc) 1899 return rc; 1900 1901 if (bp->num_rss_ctx >= BNXT_MAX_ETH_RSS_CTX) { 1902 NL_SET_ERR_MSG_FMT_MOD(extack, "Out of RSS contexts, maximum %u", 1903 BNXT_MAX_ETH_RSS_CTX); 1904 return -EINVAL; 1905 } 1906 1907 if (!bnxt_rfs_capable(bp, true)) { 1908 NL_SET_ERR_MSG_MOD(extack, "Out hardware resources"); 1909 return -ENOMEM; 1910 } 1911 1912 rss_ctx = ethtool_rxfh_context_priv(ctx); 1913 1914 bp->num_rss_ctx++; 1915 1916 vnic = &rss_ctx->vnic; 1917 vnic->rss_ctx = ctx; 1918 vnic->flags |= BNXT_VNIC_RSSCTX_FLAG; 1919 vnic->vnic_id = BNXT_VNIC_ID_INVALID; 1920 rc = bnxt_alloc_vnic_rss_table(bp, vnic); 1921 if (rc) 1922 goto out; 1923 1924 /* Populate defaults in the context */ 1925 bnxt_set_dflt_rss_indir_tbl(bp, ctx); 1926 ctx->hfunc = ETH_RSS_HASH_TOP; 1927 memcpy(vnic->rss_hash_key, bp->rss_hash_key, HW_HASH_KEY_SIZE); 1928 memcpy(ethtool_rxfh_context_key(ctx), 1929 bp->rss_hash_key, HW_HASH_KEY_SIZE); 1930 1931 rc = bnxt_hwrm_vnic_alloc(bp, vnic, 0, bp->rx_nr_rings); 1932 if (rc) { 1933 NL_SET_ERR_MSG_MOD(extack, "Unable to allocate VNIC"); 1934 goto out; 1935 } 1936 1937 rc = bnxt_hwrm_vnic_set_tpa(bp, vnic, bp->flags & BNXT_FLAG_TPA); 1938 if (rc) { 1939 NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA"); 1940 goto out; 1941 } 1942 bnxt_modify_rss(bp, ctx, rss_ctx, rxfh); 1943 1944 rc = __bnxt_setup_vnic_p5(bp, vnic); 1945 if (rc) { 1946 NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA"); 1947 goto out; 1948 } 1949 1950 rss_ctx->index = rxfh->rss_context; 1951 return 0; 1952 out: 1953 bnxt_del_one_rss_ctx(bp, rss_ctx, true); 1954 return rc; 1955 } 1956 1957 static int bnxt_modify_rxfh_context(struct net_device *dev, 1958 struct ethtool_rxfh_context *ctx, 1959 const struct ethtool_rxfh_param *rxfh, 1960 struct netlink_ext_ack *extack) 1961 { 1962 struct bnxt *bp = netdev_priv(dev); 1963 struct bnxt_rss_ctx *rss_ctx; 1964 int rc; 1965 1966 rc = bnxt_rxfh_context_check(bp, rxfh, extack); 1967 if (rc) 1968 return rc; 1969 1970 rss_ctx = ethtool_rxfh_context_priv(ctx); 1971 1972 bnxt_modify_rss(bp, ctx, rss_ctx, rxfh); 1973 1974 return bnxt_hwrm_vnic_rss_cfg_p5(bp, &rss_ctx->vnic); 1975 } 1976 1977 static int bnxt_remove_rxfh_context(struct net_device *dev, 1978 struct ethtool_rxfh_context *ctx, 1979 u32 rss_context, 1980 struct netlink_ext_ack *extack) 1981 { 1982 struct bnxt *bp = netdev_priv(dev); 1983 struct bnxt_rss_ctx *rss_ctx; 1984 1985 rss_ctx = ethtool_rxfh_context_priv(ctx); 1986 1987 bnxt_del_one_rss_ctx(bp, rss_ctx, true); 1988 return 0; 1989 } 1990 1991 static int bnxt_set_rxfh(struct net_device *dev, 1992 struct ethtool_rxfh_param *rxfh, 1993 struct netlink_ext_ack *extack) 1994 { 1995 struct bnxt *bp = netdev_priv(dev); 1996 int rc = 0; 1997 1998 if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP) 1999 return -EOPNOTSUPP; 2000 2001 bnxt_modify_rss(bp, NULL, NULL, rxfh); 2002 2003 bnxt_clear_usr_fltrs(bp, false); 2004 if (netif_running(bp->dev)) { 2005 bnxt_close_nic(bp, false, false); 2006 rc = bnxt_open_nic(bp, false, false); 2007 } 2008 return rc; 2009 } 2010 2011 static void bnxt_get_drvinfo(struct net_device *dev, 2012 struct ethtool_drvinfo *info) 2013 { 2014 struct bnxt *bp = netdev_priv(dev); 2015 2016 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 2017 strscpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 2018 strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 2019 info->n_stats = bnxt_get_num_stats(bp); 2020 info->testinfo_len = bp->num_tests; 2021 /* TODO CHIMP_FW: eeprom dump details */ 2022 info->eedump_len = 0; 2023 /* TODO CHIMP FW: reg dump details */ 2024 info->regdump_len = 0; 2025 } 2026 2027 static int bnxt_get_regs_len(struct net_device *dev) 2028 { 2029 struct bnxt *bp = netdev_priv(dev); 2030 int reg_len; 2031 2032 if (!BNXT_PF(bp)) 2033 return -EOPNOTSUPP; 2034 2035 reg_len = BNXT_PXP_REG_LEN; 2036 2037 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED) 2038 reg_len += sizeof(struct pcie_ctx_hw_stats); 2039 2040 return reg_len; 2041 } 2042 2043 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs, 2044 void *_p) 2045 { 2046 struct pcie_ctx_hw_stats *hw_pcie_stats; 2047 struct hwrm_pcie_qstats_input *req; 2048 struct bnxt *bp = netdev_priv(dev); 2049 dma_addr_t hw_pcie_stats_addr; 2050 int rc; 2051 2052 regs->version = 0; 2053 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p); 2054 2055 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 2056 return; 2057 2058 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS)) 2059 return; 2060 2061 hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats), 2062 &hw_pcie_stats_addr); 2063 if (!hw_pcie_stats) { 2064 hwrm_req_drop(bp, req); 2065 return; 2066 } 2067 2068 regs->version = 1; 2069 hwrm_req_hold(bp, req); /* hold on to slice */ 2070 req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats)); 2071 req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr); 2072 rc = hwrm_req_send(bp, req); 2073 if (!rc) { 2074 __le64 *src = (__le64 *)hw_pcie_stats; 2075 u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN); 2076 int i; 2077 2078 for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++) 2079 dst[i] = le64_to_cpu(src[i]); 2080 } 2081 hwrm_req_drop(bp, req); 2082 } 2083 2084 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2085 { 2086 struct bnxt *bp = netdev_priv(dev); 2087 2088 wol->supported = 0; 2089 wol->wolopts = 0; 2090 memset(&wol->sopass, 0, sizeof(wol->sopass)); 2091 if (bp->flags & BNXT_FLAG_WOL_CAP) { 2092 wol->supported = WAKE_MAGIC; 2093 if (bp->wol) 2094 wol->wolopts = WAKE_MAGIC; 2095 } 2096 } 2097 2098 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2099 { 2100 struct bnxt *bp = netdev_priv(dev); 2101 2102 if (wol->wolopts & ~WAKE_MAGIC) 2103 return -EINVAL; 2104 2105 if (wol->wolopts & WAKE_MAGIC) { 2106 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 2107 return -EINVAL; 2108 if (!bp->wol) { 2109 if (bnxt_hwrm_alloc_wol_fltr(bp)) 2110 return -EBUSY; 2111 bp->wol = 1; 2112 } 2113 } else { 2114 if (bp->wol) { 2115 if (bnxt_hwrm_free_wol_fltr(bp)) 2116 return -EBUSY; 2117 bp->wol = 0; 2118 } 2119 } 2120 return 0; 2121 } 2122 2123 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 2124 void _bnxt_fw_to_linkmode(unsigned long *mode, u16 fw_speeds) 2125 { 2126 linkmode_zero(mode); 2127 2128 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 2129 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode); 2130 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 2131 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode); 2132 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 2133 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT, mode); 2134 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 2135 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode); 2136 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 2137 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode); 2138 } 2139 2140 enum bnxt_media_type { 2141 BNXT_MEDIA_UNKNOWN = 0, 2142 BNXT_MEDIA_TP, 2143 BNXT_MEDIA_CR, 2144 BNXT_MEDIA_SR, 2145 BNXT_MEDIA_LR_ER_FR, 2146 BNXT_MEDIA_KR, 2147 BNXT_MEDIA_KX, 2148 BNXT_MEDIA_X, 2149 __BNXT_MEDIA_END, 2150 }; 2151 2152 static const enum bnxt_media_type bnxt_phy_types[] = { 2153 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR] = BNXT_MEDIA_CR, 2154 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4] = BNXT_MEDIA_KR, 2155 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR] = BNXT_MEDIA_LR_ER_FR, 2156 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR] = BNXT_MEDIA_SR, 2157 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2] = BNXT_MEDIA_KR, 2158 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX] = BNXT_MEDIA_KX, 2159 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR] = BNXT_MEDIA_KR, 2160 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASET] = BNXT_MEDIA_TP, 2161 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE] = BNXT_MEDIA_TP, 2162 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L] = BNXT_MEDIA_CR, 2163 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S] = BNXT_MEDIA_CR, 2164 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N] = BNXT_MEDIA_CR, 2165 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR] = BNXT_MEDIA_SR, 2166 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4] = BNXT_MEDIA_CR, 2167 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4] = BNXT_MEDIA_SR, 2168 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2169 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2170 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10] = BNXT_MEDIA_SR, 2171 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4] = BNXT_MEDIA_CR, 2172 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4] = BNXT_MEDIA_SR, 2173 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2174 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2175 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE] = BNXT_MEDIA_SR, 2176 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET] = BNXT_MEDIA_TP, 2177 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX] = BNXT_MEDIA_X, 2178 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX] = BNXT_MEDIA_X, 2179 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4] = BNXT_MEDIA_CR, 2180 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4] = BNXT_MEDIA_SR, 2181 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2182 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2183 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR] = BNXT_MEDIA_CR, 2184 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR] = BNXT_MEDIA_SR, 2185 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR] = BNXT_MEDIA_LR_ER_FR, 2186 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER] = BNXT_MEDIA_LR_ER_FR, 2187 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2] = BNXT_MEDIA_CR, 2188 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2] = BNXT_MEDIA_SR, 2189 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2] = BNXT_MEDIA_LR_ER_FR, 2190 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2] = BNXT_MEDIA_LR_ER_FR, 2191 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR] = BNXT_MEDIA_CR, 2192 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR] = BNXT_MEDIA_SR, 2193 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR] = BNXT_MEDIA_LR_ER_FR, 2194 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER] = BNXT_MEDIA_LR_ER_FR, 2195 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2] = BNXT_MEDIA_CR, 2196 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2] = BNXT_MEDIA_SR, 2197 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2] = BNXT_MEDIA_LR_ER_FR, 2198 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2] = BNXT_MEDIA_LR_ER_FR, 2199 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8] = BNXT_MEDIA_CR, 2200 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8] = BNXT_MEDIA_SR, 2201 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8] = BNXT_MEDIA_LR_ER_FR, 2202 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8] = BNXT_MEDIA_LR_ER_FR, 2203 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4] = BNXT_MEDIA_CR, 2204 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4] = BNXT_MEDIA_SR, 2205 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2206 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2207 }; 2208 2209 static enum bnxt_media_type 2210 bnxt_get_media(struct bnxt_link_info *link_info) 2211 { 2212 switch (link_info->media_type) { 2213 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP: 2214 return BNXT_MEDIA_TP; 2215 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC: 2216 return BNXT_MEDIA_CR; 2217 default: 2218 if (link_info->phy_type < ARRAY_SIZE(bnxt_phy_types)) 2219 return bnxt_phy_types[link_info->phy_type]; 2220 return BNXT_MEDIA_UNKNOWN; 2221 } 2222 } 2223 2224 enum bnxt_link_speed_indices { 2225 BNXT_LINK_SPEED_UNKNOWN = 0, 2226 BNXT_LINK_SPEED_100MB_IDX, 2227 BNXT_LINK_SPEED_1GB_IDX, 2228 BNXT_LINK_SPEED_10GB_IDX, 2229 BNXT_LINK_SPEED_25GB_IDX, 2230 BNXT_LINK_SPEED_40GB_IDX, 2231 BNXT_LINK_SPEED_50GB_IDX, 2232 BNXT_LINK_SPEED_100GB_IDX, 2233 BNXT_LINK_SPEED_200GB_IDX, 2234 BNXT_LINK_SPEED_400GB_IDX, 2235 __BNXT_LINK_SPEED_END 2236 }; 2237 2238 static enum bnxt_link_speed_indices bnxt_fw_speed_idx(u16 speed) 2239 { 2240 switch (speed) { 2241 case BNXT_LINK_SPEED_100MB: return BNXT_LINK_SPEED_100MB_IDX; 2242 case BNXT_LINK_SPEED_1GB: return BNXT_LINK_SPEED_1GB_IDX; 2243 case BNXT_LINK_SPEED_10GB: return BNXT_LINK_SPEED_10GB_IDX; 2244 case BNXT_LINK_SPEED_25GB: return BNXT_LINK_SPEED_25GB_IDX; 2245 case BNXT_LINK_SPEED_40GB: return BNXT_LINK_SPEED_40GB_IDX; 2246 case BNXT_LINK_SPEED_50GB: 2247 case BNXT_LINK_SPEED_50GB_PAM4: 2248 return BNXT_LINK_SPEED_50GB_IDX; 2249 case BNXT_LINK_SPEED_100GB: 2250 case BNXT_LINK_SPEED_100GB_PAM4: 2251 case BNXT_LINK_SPEED_100GB_PAM4_112: 2252 return BNXT_LINK_SPEED_100GB_IDX; 2253 case BNXT_LINK_SPEED_200GB: 2254 case BNXT_LINK_SPEED_200GB_PAM4: 2255 case BNXT_LINK_SPEED_200GB_PAM4_112: 2256 return BNXT_LINK_SPEED_200GB_IDX; 2257 case BNXT_LINK_SPEED_400GB: 2258 case BNXT_LINK_SPEED_400GB_PAM4: 2259 case BNXT_LINK_SPEED_400GB_PAM4_112: 2260 return BNXT_LINK_SPEED_400GB_IDX; 2261 default: return BNXT_LINK_SPEED_UNKNOWN; 2262 } 2263 } 2264 2265 static const enum ethtool_link_mode_bit_indices 2266 bnxt_link_modes[__BNXT_LINK_SPEED_END][BNXT_SIG_MODE_MAX][__BNXT_MEDIA_END] = { 2267 [BNXT_LINK_SPEED_100MB_IDX] = { 2268 { 2269 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_100baseT_Full_BIT, 2270 }, 2271 }, 2272 [BNXT_LINK_SPEED_1GB_IDX] = { 2273 { 2274 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 2275 /* historically baseT, but DAC is more correctly baseX */ 2276 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 2277 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2278 [BNXT_MEDIA_X] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 2279 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2280 }, 2281 }, 2282 [BNXT_LINK_SPEED_10GB_IDX] = { 2283 { 2284 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 2285 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 2286 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 2287 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 2288 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 2289 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 2290 }, 2291 }, 2292 [BNXT_LINK_SPEED_25GB_IDX] = { 2293 { 2294 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 2295 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 2296 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 2297 }, 2298 }, 2299 [BNXT_LINK_SPEED_40GB_IDX] = { 2300 { 2301 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 2302 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 2303 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 2304 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 2305 }, 2306 }, 2307 [BNXT_LINK_SPEED_50GB_IDX] = { 2308 [BNXT_SIG_MODE_NRZ] = { 2309 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 2310 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 2311 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 2312 }, 2313 [BNXT_SIG_MODE_PAM4] = { 2314 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 2315 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 2316 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 2317 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 2318 }, 2319 }, 2320 [BNXT_LINK_SPEED_100GB_IDX] = { 2321 [BNXT_SIG_MODE_NRZ] = { 2322 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 2323 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 2324 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 2325 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 2326 }, 2327 [BNXT_SIG_MODE_PAM4] = { 2328 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 2329 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 2330 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 2331 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 2332 }, 2333 [BNXT_SIG_MODE_PAM4_112] = { 2334 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR_Full_BIT, 2335 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR_Full_BIT, 2336 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR_Full_BIT, 2337 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT, 2338 }, 2339 }, 2340 [BNXT_LINK_SPEED_200GB_IDX] = { 2341 [BNXT_SIG_MODE_PAM4] = { 2342 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT, 2343 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 2344 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 2345 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 2346 }, 2347 [BNXT_SIG_MODE_PAM4_112] = { 2348 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT, 2349 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT, 2350 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT, 2351 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT, 2352 }, 2353 }, 2354 [BNXT_LINK_SPEED_400GB_IDX] = { 2355 [BNXT_SIG_MODE_PAM4] = { 2356 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT, 2357 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT, 2358 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT, 2359 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT, 2360 }, 2361 [BNXT_SIG_MODE_PAM4_112] = { 2362 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT, 2363 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT, 2364 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT, 2365 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT, 2366 }, 2367 }, 2368 }; 2369 2370 #define BNXT_LINK_MODE_UNKNOWN -1 2371 2372 static enum ethtool_link_mode_bit_indices 2373 bnxt_get_link_mode(struct bnxt_link_info *link_info) 2374 { 2375 enum ethtool_link_mode_bit_indices link_mode; 2376 enum bnxt_link_speed_indices speed; 2377 enum bnxt_media_type media; 2378 u8 sig_mode; 2379 2380 if (link_info->phy_link_status != BNXT_LINK_LINK) 2381 return BNXT_LINK_MODE_UNKNOWN; 2382 2383 media = bnxt_get_media(link_info); 2384 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 2385 speed = bnxt_fw_speed_idx(link_info->link_speed); 2386 sig_mode = link_info->active_fec_sig_mode & 2387 PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK; 2388 } else { 2389 speed = bnxt_fw_speed_idx(link_info->req_link_speed); 2390 sig_mode = link_info->req_signal_mode; 2391 } 2392 if (sig_mode >= BNXT_SIG_MODE_MAX) 2393 return BNXT_LINK_MODE_UNKNOWN; 2394 2395 /* Note ETHTOOL_LINK_MODE_10baseT_Half_BIT == 0 is a legal Linux 2396 * link mode, but since no such devices exist, the zeroes in the 2397 * map can be conveniently used to represent unknown link modes. 2398 */ 2399 link_mode = bnxt_link_modes[speed][sig_mode][media]; 2400 if (!link_mode) 2401 return BNXT_LINK_MODE_UNKNOWN; 2402 2403 switch (link_mode) { 2404 case ETHTOOL_LINK_MODE_100baseT_Full_BIT: 2405 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2406 link_mode = ETHTOOL_LINK_MODE_100baseT_Half_BIT; 2407 break; 2408 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT: 2409 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2410 link_mode = ETHTOOL_LINK_MODE_1000baseT_Half_BIT; 2411 break; 2412 default: 2413 break; 2414 } 2415 2416 return link_mode; 2417 } 2418 2419 static void bnxt_get_ethtool_modes(struct bnxt_link_info *link_info, 2420 struct ethtool_link_ksettings *lk_ksettings) 2421 { 2422 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2423 2424 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) { 2425 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2426 lk_ksettings->link_modes.supported); 2427 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2428 lk_ksettings->link_modes.supported); 2429 } 2430 2431 if (link_info->support_auto_speeds || link_info->support_auto_speeds2 || 2432 link_info->support_pam4_auto_speeds) 2433 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2434 lk_ksettings->link_modes.supported); 2435 2436 if (~link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 2437 return; 2438 2439 if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_RX) 2440 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2441 lk_ksettings->link_modes.advertising); 2442 if (hweight8(link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) == 1) 2443 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2444 lk_ksettings->link_modes.advertising); 2445 if (link_info->lp_pause & BNXT_LINK_PAUSE_RX) 2446 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2447 lk_ksettings->link_modes.lp_advertising); 2448 if (hweight8(link_info->lp_pause & BNXT_LINK_PAUSE_BOTH) == 1) 2449 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2450 lk_ksettings->link_modes.lp_advertising); 2451 } 2452 2453 static const u16 bnxt_nrz_speed_masks[] = { 2454 [BNXT_LINK_SPEED_100MB_IDX] = BNXT_LINK_SPEED_MSK_100MB, 2455 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEED_MSK_1GB, 2456 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEED_MSK_10GB, 2457 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEED_MSK_25GB, 2458 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEED_MSK_40GB, 2459 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEED_MSK_50GB, 2460 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEED_MSK_100GB, 2461 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2462 }; 2463 2464 static const u16 bnxt_pam4_speed_masks[] = { 2465 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_50GB, 2466 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_100GB, 2467 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_200GB, 2468 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2469 }; 2470 2471 static const u16 bnxt_nrz_speeds2_masks[] = { 2472 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEEDS2_MSK_1GB, 2473 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEEDS2_MSK_10GB, 2474 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEEDS2_MSK_25GB, 2475 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEEDS2_MSK_40GB, 2476 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB, 2477 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB, 2478 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2479 }; 2480 2481 static const u16 bnxt_pam4_speeds2_masks[] = { 2482 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB_PAM4, 2483 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4, 2484 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4, 2485 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4, 2486 }; 2487 2488 static const u16 bnxt_pam4_112_speeds2_masks[] = { 2489 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112, 2490 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112, 2491 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112, 2492 }; 2493 2494 static enum bnxt_link_speed_indices 2495 bnxt_encoding_speed_idx(u8 sig_mode, u16 phy_flags, u16 speed_msk) 2496 { 2497 const u16 *speeds; 2498 int idx, len; 2499 2500 switch (sig_mode) { 2501 case BNXT_SIG_MODE_NRZ: 2502 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2503 speeds = bnxt_nrz_speeds2_masks; 2504 len = ARRAY_SIZE(bnxt_nrz_speeds2_masks); 2505 } else { 2506 speeds = bnxt_nrz_speed_masks; 2507 len = ARRAY_SIZE(bnxt_nrz_speed_masks); 2508 } 2509 break; 2510 case BNXT_SIG_MODE_PAM4: 2511 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2512 speeds = bnxt_pam4_speeds2_masks; 2513 len = ARRAY_SIZE(bnxt_pam4_speeds2_masks); 2514 } else { 2515 speeds = bnxt_pam4_speed_masks; 2516 len = ARRAY_SIZE(bnxt_pam4_speed_masks); 2517 } 2518 break; 2519 case BNXT_SIG_MODE_PAM4_112: 2520 speeds = bnxt_pam4_112_speeds2_masks; 2521 len = ARRAY_SIZE(bnxt_pam4_112_speeds2_masks); 2522 break; 2523 default: 2524 return BNXT_LINK_SPEED_UNKNOWN; 2525 } 2526 2527 for (idx = 0; idx < len; idx++) { 2528 if (speeds[idx] == speed_msk) 2529 return idx; 2530 } 2531 2532 return BNXT_LINK_SPEED_UNKNOWN; 2533 } 2534 2535 #define BNXT_FW_SPEED_MSK_BITS 16 2536 2537 static void 2538 __bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media, 2539 u8 sig_mode, u16 phy_flags, unsigned long *et_mask) 2540 { 2541 enum ethtool_link_mode_bit_indices link_mode; 2542 enum bnxt_link_speed_indices speed; 2543 u8 bit; 2544 2545 for_each_set_bit(bit, &fw_mask, BNXT_FW_SPEED_MSK_BITS) { 2546 speed = bnxt_encoding_speed_idx(sig_mode, phy_flags, 1 << bit); 2547 if (!speed) 2548 continue; 2549 2550 link_mode = bnxt_link_modes[speed][sig_mode][media]; 2551 if (!link_mode) 2552 continue; 2553 2554 linkmode_set_bit(link_mode, et_mask); 2555 } 2556 } 2557 2558 static void 2559 bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media, 2560 u8 sig_mode, u16 phy_flags, unsigned long *et_mask) 2561 { 2562 if (media) { 2563 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags, 2564 et_mask); 2565 return; 2566 } 2567 2568 /* list speeds for all media if unknown */ 2569 for (media = 1; media < __BNXT_MEDIA_END; media++) 2570 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags, 2571 et_mask); 2572 } 2573 2574 static void 2575 bnxt_get_all_ethtool_support_speeds(struct bnxt_link_info *link_info, 2576 enum bnxt_media_type media, 2577 struct ethtool_link_ksettings *lk_ksettings) 2578 { 2579 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2580 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0; 2581 u16 phy_flags = bp->phy_flags; 2582 2583 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2584 sp_nrz = link_info->support_speeds2; 2585 sp_pam4 = link_info->support_speeds2; 2586 sp_pam4_112 = link_info->support_speeds2; 2587 } else { 2588 sp_nrz = link_info->support_speeds; 2589 sp_pam4 = link_info->support_pam4_speeds; 2590 } 2591 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags, 2592 lk_ksettings->link_modes.supported); 2593 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags, 2594 lk_ksettings->link_modes.supported); 2595 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112, 2596 phy_flags, lk_ksettings->link_modes.supported); 2597 } 2598 2599 static void 2600 bnxt_get_all_ethtool_adv_speeds(struct bnxt_link_info *link_info, 2601 enum bnxt_media_type media, 2602 struct ethtool_link_ksettings *lk_ksettings) 2603 { 2604 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2605 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0; 2606 u16 phy_flags = bp->phy_flags; 2607 2608 sp_nrz = link_info->advertising; 2609 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2610 sp_pam4 = link_info->advertising; 2611 sp_pam4_112 = link_info->advertising; 2612 } else { 2613 sp_pam4 = link_info->advertising_pam4; 2614 } 2615 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags, 2616 lk_ksettings->link_modes.advertising); 2617 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags, 2618 lk_ksettings->link_modes.advertising); 2619 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112, 2620 phy_flags, lk_ksettings->link_modes.advertising); 2621 } 2622 2623 static void 2624 bnxt_get_all_ethtool_lp_speeds(struct bnxt_link_info *link_info, 2625 enum bnxt_media_type media, 2626 struct ethtool_link_ksettings *lk_ksettings) 2627 { 2628 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2629 u16 phy_flags = bp->phy_flags; 2630 2631 bnxt_get_ethtool_speeds(link_info->lp_auto_link_speeds, media, 2632 BNXT_SIG_MODE_NRZ, phy_flags, 2633 lk_ksettings->link_modes.lp_advertising); 2634 bnxt_get_ethtool_speeds(link_info->lp_auto_pam4_link_speeds, media, 2635 BNXT_SIG_MODE_PAM4, phy_flags, 2636 lk_ksettings->link_modes.lp_advertising); 2637 } 2638 2639 static void bnxt_update_speed(u32 *delta, bool installed_media, u16 *speeds, 2640 u16 speed_msk, const unsigned long *et_mask, 2641 enum ethtool_link_mode_bit_indices mode) 2642 { 2643 bool mode_desired = linkmode_test_bit(mode, et_mask); 2644 2645 if (!mode) 2646 return; 2647 2648 /* enabled speeds for installed media should override */ 2649 if (installed_media && mode_desired) { 2650 *speeds |= speed_msk; 2651 *delta |= speed_msk; 2652 return; 2653 } 2654 2655 /* many to one mapping, only allow one change per fw_speed bit */ 2656 if (!(*delta & speed_msk) && (mode_desired == !(*speeds & speed_msk))) { 2657 *speeds ^= speed_msk; 2658 *delta |= speed_msk; 2659 } 2660 } 2661 2662 static void bnxt_set_ethtool_speeds(struct bnxt_link_info *link_info, 2663 const unsigned long *et_mask) 2664 { 2665 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2666 u16 const *sp_msks, *sp_pam4_msks, *sp_pam4_112_msks; 2667 enum bnxt_media_type media = bnxt_get_media(link_info); 2668 u16 *adv, *adv_pam4, *adv_pam4_112 = NULL; 2669 u32 delta_pam4_112 = 0; 2670 u32 delta_pam4 = 0; 2671 u32 delta_nrz = 0; 2672 int i, m; 2673 2674 adv = &link_info->advertising; 2675 if (bp->phy_flags & BNXT_PHY_FL_SPEEDS2) { 2676 adv_pam4 = &link_info->advertising; 2677 adv_pam4_112 = &link_info->advertising; 2678 sp_msks = bnxt_nrz_speeds2_masks; 2679 sp_pam4_msks = bnxt_pam4_speeds2_masks; 2680 sp_pam4_112_msks = bnxt_pam4_112_speeds2_masks; 2681 } else { 2682 adv_pam4 = &link_info->advertising_pam4; 2683 sp_msks = bnxt_nrz_speed_masks; 2684 sp_pam4_msks = bnxt_pam4_speed_masks; 2685 } 2686 for (i = 1; i < __BNXT_LINK_SPEED_END; i++) { 2687 /* accept any legal media from user */ 2688 for (m = 1; m < __BNXT_MEDIA_END; m++) { 2689 bnxt_update_speed(&delta_nrz, m == media, 2690 adv, sp_msks[i], et_mask, 2691 bnxt_link_modes[i][BNXT_SIG_MODE_NRZ][m]); 2692 bnxt_update_speed(&delta_pam4, m == media, 2693 adv_pam4, sp_pam4_msks[i], et_mask, 2694 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4][m]); 2695 if (!adv_pam4_112) 2696 continue; 2697 2698 bnxt_update_speed(&delta_pam4_112, m == media, 2699 adv_pam4_112, sp_pam4_112_msks[i], et_mask, 2700 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4_112][m]); 2701 } 2702 } 2703 } 2704 2705 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info, 2706 struct ethtool_link_ksettings *lk_ksettings) 2707 { 2708 u16 fec_cfg = link_info->fec_cfg; 2709 2710 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) { 2711 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 2712 lk_ksettings->link_modes.advertising); 2713 return; 2714 } 2715 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 2716 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 2717 lk_ksettings->link_modes.advertising); 2718 if (fec_cfg & BNXT_FEC_ENC_RS) 2719 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 2720 lk_ksettings->link_modes.advertising); 2721 if (fec_cfg & BNXT_FEC_ENC_LLRS) 2722 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 2723 lk_ksettings->link_modes.advertising); 2724 } 2725 2726 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info, 2727 struct ethtool_link_ksettings *lk_ksettings) 2728 { 2729 u16 fec_cfg = link_info->fec_cfg; 2730 2731 if (fec_cfg & BNXT_FEC_NONE) { 2732 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 2733 lk_ksettings->link_modes.supported); 2734 return; 2735 } 2736 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP) 2737 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 2738 lk_ksettings->link_modes.supported); 2739 if (fec_cfg & BNXT_FEC_ENC_RS_CAP) 2740 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 2741 lk_ksettings->link_modes.supported); 2742 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP) 2743 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 2744 lk_ksettings->link_modes.supported); 2745 } 2746 2747 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 2748 { 2749 switch (fw_link_speed) { 2750 case BNXT_LINK_SPEED_100MB: 2751 return SPEED_100; 2752 case BNXT_LINK_SPEED_1GB: 2753 return SPEED_1000; 2754 case BNXT_LINK_SPEED_2_5GB: 2755 return SPEED_2500; 2756 case BNXT_LINK_SPEED_10GB: 2757 return SPEED_10000; 2758 case BNXT_LINK_SPEED_20GB: 2759 return SPEED_20000; 2760 case BNXT_LINK_SPEED_25GB: 2761 return SPEED_25000; 2762 case BNXT_LINK_SPEED_40GB: 2763 return SPEED_40000; 2764 case BNXT_LINK_SPEED_50GB: 2765 case BNXT_LINK_SPEED_50GB_PAM4: 2766 return SPEED_50000; 2767 case BNXT_LINK_SPEED_100GB: 2768 case BNXT_LINK_SPEED_100GB_PAM4: 2769 case BNXT_LINK_SPEED_100GB_PAM4_112: 2770 return SPEED_100000; 2771 case BNXT_LINK_SPEED_200GB: 2772 case BNXT_LINK_SPEED_200GB_PAM4: 2773 case BNXT_LINK_SPEED_200GB_PAM4_112: 2774 return SPEED_200000; 2775 case BNXT_LINK_SPEED_400GB: 2776 case BNXT_LINK_SPEED_400GB_PAM4: 2777 case BNXT_LINK_SPEED_400GB_PAM4_112: 2778 return SPEED_400000; 2779 default: 2780 return SPEED_UNKNOWN; 2781 } 2782 } 2783 2784 static void bnxt_get_default_speeds(struct ethtool_link_ksettings *lk_ksettings, 2785 struct bnxt_link_info *link_info) 2786 { 2787 struct ethtool_link_settings *base = &lk_ksettings->base; 2788 2789 if (link_info->link_state == BNXT_LINK_STATE_UP) { 2790 base->speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 2791 base->duplex = DUPLEX_HALF; 2792 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2793 base->duplex = DUPLEX_FULL; 2794 lk_ksettings->lanes = link_info->active_lanes; 2795 } else if (!link_info->autoneg) { 2796 base->speed = bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 2797 base->duplex = DUPLEX_HALF; 2798 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 2799 base->duplex = DUPLEX_FULL; 2800 } 2801 } 2802 2803 static int bnxt_get_link_ksettings(struct net_device *dev, 2804 struct ethtool_link_ksettings *lk_ksettings) 2805 { 2806 struct ethtool_link_settings *base = &lk_ksettings->base; 2807 enum ethtool_link_mode_bit_indices link_mode; 2808 struct bnxt *bp = netdev_priv(dev); 2809 struct bnxt_link_info *link_info; 2810 enum bnxt_media_type media; 2811 2812 ethtool_link_ksettings_zero_link_mode(lk_ksettings, lp_advertising); 2813 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 2814 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 2815 base->duplex = DUPLEX_UNKNOWN; 2816 base->speed = SPEED_UNKNOWN; 2817 link_info = &bp->link_info; 2818 2819 mutex_lock(&bp->link_lock); 2820 bnxt_get_ethtool_modes(link_info, lk_ksettings); 2821 media = bnxt_get_media(link_info); 2822 bnxt_get_all_ethtool_support_speeds(link_info, media, lk_ksettings); 2823 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings); 2824 link_mode = bnxt_get_link_mode(link_info); 2825 if (link_mode != BNXT_LINK_MODE_UNKNOWN) 2826 ethtool_params_from_link_mode(lk_ksettings, link_mode); 2827 else 2828 bnxt_get_default_speeds(lk_ksettings, link_info); 2829 2830 if (link_info->autoneg) { 2831 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings); 2832 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2833 lk_ksettings->link_modes.advertising); 2834 base->autoneg = AUTONEG_ENABLE; 2835 bnxt_get_all_ethtool_adv_speeds(link_info, media, lk_ksettings); 2836 if (link_info->phy_link_status == BNXT_LINK_LINK) 2837 bnxt_get_all_ethtool_lp_speeds(link_info, media, 2838 lk_ksettings); 2839 } else { 2840 base->autoneg = AUTONEG_DISABLE; 2841 } 2842 2843 base->port = PORT_NONE; 2844 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 2845 base->port = PORT_TP; 2846 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2847 lk_ksettings->link_modes.supported); 2848 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2849 lk_ksettings->link_modes.advertising); 2850 } else { 2851 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 2852 lk_ksettings->link_modes.supported); 2853 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 2854 lk_ksettings->link_modes.advertising); 2855 2856 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC) 2857 base->port = PORT_DA; 2858 else 2859 base->port = PORT_FIBRE; 2860 } 2861 base->phy_address = link_info->phy_addr; 2862 mutex_unlock(&bp->link_lock); 2863 2864 return 0; 2865 } 2866 2867 static int 2868 bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed, u32 lanes) 2869 { 2870 struct bnxt *bp = netdev_priv(dev); 2871 struct bnxt_link_info *link_info = &bp->link_info; 2872 u16 support_pam4_spds = link_info->support_pam4_speeds; 2873 u16 support_spds2 = link_info->support_speeds2; 2874 u16 support_spds = link_info->support_speeds; 2875 u8 sig_mode = BNXT_SIG_MODE_NRZ; 2876 u32 lanes_needed = 1; 2877 u16 fw_speed = 0; 2878 2879 switch (ethtool_speed) { 2880 case SPEED_100: 2881 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 2882 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB; 2883 break; 2884 case SPEED_1000: 2885 if ((support_spds & BNXT_LINK_SPEED_MSK_1GB) || 2886 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_1GB)) 2887 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 2888 break; 2889 case SPEED_2500: 2890 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 2891 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB; 2892 break; 2893 case SPEED_10000: 2894 if ((support_spds & BNXT_LINK_SPEED_MSK_10GB) || 2895 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_10GB)) 2896 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 2897 break; 2898 case SPEED_20000: 2899 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) { 2900 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB; 2901 lanes_needed = 2; 2902 } 2903 break; 2904 case SPEED_25000: 2905 if ((support_spds & BNXT_LINK_SPEED_MSK_25GB) || 2906 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_25GB)) 2907 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 2908 break; 2909 case SPEED_40000: 2910 if ((support_spds & BNXT_LINK_SPEED_MSK_40GB) || 2911 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_40GB)) { 2912 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 2913 lanes_needed = 4; 2914 } 2915 break; 2916 case SPEED_50000: 2917 if (((support_spds & BNXT_LINK_SPEED_MSK_50GB) || 2918 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB)) && 2919 lanes != 1) { 2920 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 2921 lanes_needed = 2; 2922 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) { 2923 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB; 2924 sig_mode = BNXT_SIG_MODE_PAM4; 2925 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB_PAM4) { 2926 fw_speed = BNXT_LINK_SPEED_50GB_PAM4; 2927 sig_mode = BNXT_SIG_MODE_PAM4; 2928 } 2929 break; 2930 case SPEED_100000: 2931 if (((support_spds & BNXT_LINK_SPEED_MSK_100GB) || 2932 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB)) && 2933 lanes != 2 && lanes != 1) { 2934 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB; 2935 lanes_needed = 4; 2936 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) { 2937 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB; 2938 sig_mode = BNXT_SIG_MODE_PAM4; 2939 lanes_needed = 2; 2940 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4) && 2941 lanes != 1) { 2942 fw_speed = BNXT_LINK_SPEED_100GB_PAM4; 2943 sig_mode = BNXT_SIG_MODE_PAM4; 2944 lanes_needed = 2; 2945 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112) { 2946 fw_speed = BNXT_LINK_SPEED_100GB_PAM4_112; 2947 sig_mode = BNXT_SIG_MODE_PAM4_112; 2948 } 2949 break; 2950 case SPEED_200000: 2951 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) { 2952 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB; 2953 sig_mode = BNXT_SIG_MODE_PAM4; 2954 lanes_needed = 4; 2955 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4) && 2956 lanes != 2) { 2957 fw_speed = BNXT_LINK_SPEED_200GB_PAM4; 2958 sig_mode = BNXT_SIG_MODE_PAM4; 2959 lanes_needed = 4; 2960 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112) { 2961 fw_speed = BNXT_LINK_SPEED_200GB_PAM4_112; 2962 sig_mode = BNXT_SIG_MODE_PAM4_112; 2963 lanes_needed = 2; 2964 } 2965 break; 2966 case SPEED_400000: 2967 if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4) && 2968 lanes != 4) { 2969 fw_speed = BNXT_LINK_SPEED_400GB_PAM4; 2970 sig_mode = BNXT_SIG_MODE_PAM4; 2971 lanes_needed = 8; 2972 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112) { 2973 fw_speed = BNXT_LINK_SPEED_400GB_PAM4_112; 2974 sig_mode = BNXT_SIG_MODE_PAM4_112; 2975 lanes_needed = 4; 2976 } 2977 break; 2978 } 2979 2980 if (!fw_speed) { 2981 netdev_err(dev, "unsupported speed!\n"); 2982 return -EINVAL; 2983 } 2984 2985 if (lanes && lanes != lanes_needed) { 2986 netdev_err(dev, "unsupported number of lanes for speed\n"); 2987 return -EINVAL; 2988 } 2989 2990 if (link_info->req_link_speed == fw_speed && 2991 link_info->req_signal_mode == sig_mode && 2992 link_info->autoneg == 0) 2993 return -EALREADY; 2994 2995 link_info->req_link_speed = fw_speed; 2996 link_info->req_signal_mode = sig_mode; 2997 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 2998 link_info->autoneg = 0; 2999 link_info->advertising = 0; 3000 link_info->advertising_pam4 = 0; 3001 3002 return 0; 3003 } 3004 3005 u16 bnxt_get_fw_auto_link_speeds(const unsigned long *mode) 3006 { 3007 u16 fw_speed_mask = 0; 3008 3009 if (linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode) || 3010 linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mode)) 3011 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 3012 3013 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode) || 3014 linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, mode)) 3015 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 3016 3017 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode)) 3018 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 3019 3020 if (linkmode_test_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode)) 3021 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 3022 3023 return fw_speed_mask; 3024 } 3025 3026 static int bnxt_set_link_ksettings(struct net_device *dev, 3027 const struct ethtool_link_ksettings *lk_ksettings) 3028 { 3029 struct bnxt *bp = netdev_priv(dev); 3030 struct bnxt_link_info *link_info = &bp->link_info; 3031 const struct ethtool_link_settings *base = &lk_ksettings->base; 3032 bool set_pause = false; 3033 u32 speed, lanes = 0; 3034 int rc = 0; 3035 3036 if (!BNXT_PHY_CFG_ABLE(bp)) 3037 return -EOPNOTSUPP; 3038 3039 mutex_lock(&bp->link_lock); 3040 if (base->autoneg == AUTONEG_ENABLE) { 3041 bnxt_set_ethtool_speeds(link_info, 3042 lk_ksettings->link_modes.advertising); 3043 link_info->autoneg |= BNXT_AUTONEG_SPEED; 3044 if (!link_info->advertising && !link_info->advertising_pam4) { 3045 link_info->advertising = link_info->support_auto_speeds; 3046 link_info->advertising_pam4 = 3047 link_info->support_pam4_auto_speeds; 3048 } 3049 /* any change to autoneg will cause link change, therefore the 3050 * driver should put back the original pause setting in autoneg 3051 */ 3052 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 3053 set_pause = true; 3054 } else { 3055 u8 phy_type = link_info->phy_type; 3056 3057 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 3058 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 3059 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 3060 netdev_err(dev, "10GBase-T devices must autoneg\n"); 3061 rc = -EINVAL; 3062 goto set_setting_exit; 3063 } 3064 if (base->duplex == DUPLEX_HALF) { 3065 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 3066 rc = -EINVAL; 3067 goto set_setting_exit; 3068 } 3069 speed = base->speed; 3070 lanes = lk_ksettings->lanes; 3071 rc = bnxt_force_link_speed(dev, speed, lanes); 3072 if (rc) { 3073 if (rc == -EALREADY) 3074 rc = 0; 3075 goto set_setting_exit; 3076 } 3077 } 3078 3079 if (netif_running(dev)) 3080 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 3081 3082 set_setting_exit: 3083 mutex_unlock(&bp->link_lock); 3084 return rc; 3085 } 3086 3087 static int bnxt_get_fecparam(struct net_device *dev, 3088 struct ethtool_fecparam *fec) 3089 { 3090 struct bnxt *bp = netdev_priv(dev); 3091 struct bnxt_link_info *link_info; 3092 u8 active_fec; 3093 u16 fec_cfg; 3094 3095 link_info = &bp->link_info; 3096 fec_cfg = link_info->fec_cfg; 3097 active_fec = link_info->active_fec_sig_mode & 3098 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK; 3099 if (fec_cfg & BNXT_FEC_NONE) { 3100 fec->fec = ETHTOOL_FEC_NONE; 3101 fec->active_fec = ETHTOOL_FEC_NONE; 3102 return 0; 3103 } 3104 if (fec_cfg & BNXT_FEC_AUTONEG) 3105 fec->fec |= ETHTOOL_FEC_AUTO; 3106 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 3107 fec->fec |= ETHTOOL_FEC_BASER; 3108 if (fec_cfg & BNXT_FEC_ENC_RS) 3109 fec->fec |= ETHTOOL_FEC_RS; 3110 if (fec_cfg & BNXT_FEC_ENC_LLRS) 3111 fec->fec |= ETHTOOL_FEC_LLRS; 3112 3113 switch (active_fec) { 3114 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE: 3115 fec->active_fec |= ETHTOOL_FEC_BASER; 3116 break; 3117 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE: 3118 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE: 3119 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE: 3120 fec->active_fec |= ETHTOOL_FEC_RS; 3121 break; 3122 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE: 3123 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE: 3124 fec->active_fec |= ETHTOOL_FEC_LLRS; 3125 break; 3126 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE: 3127 fec->active_fec |= ETHTOOL_FEC_OFF; 3128 break; 3129 } 3130 return 0; 3131 } 3132 3133 static void bnxt_get_fec_stats(struct net_device *dev, 3134 struct ethtool_fec_stats *fec_stats) 3135 { 3136 struct bnxt *bp = netdev_priv(dev); 3137 u64 *rx; 3138 3139 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 3140 return; 3141 3142 rx = bp->rx_port_stats_ext.sw_stats; 3143 fec_stats->corrected_bits.total = 3144 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits)); 3145 3146 if (bp->fw_rx_stats_ext_size <= BNXT_RX_STATS_EXT_NUM_LEGACY) 3147 return; 3148 3149 fec_stats->corrected_blocks.total = 3150 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)); 3151 fec_stats->uncorrectable_blocks.total = 3152 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_uncorrectable_blocks)); 3153 } 3154 3155 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info, 3156 u32 fec) 3157 { 3158 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE; 3159 3160 if (fec & ETHTOOL_FEC_BASER) 3161 fw_fec |= BNXT_FEC_BASE_R_ON(link_info); 3162 else if (fec & ETHTOOL_FEC_RS) 3163 fw_fec |= BNXT_FEC_RS_ON(link_info); 3164 else if (fec & ETHTOOL_FEC_LLRS) 3165 fw_fec |= BNXT_FEC_LLRS_ON; 3166 return fw_fec; 3167 } 3168 3169 static int bnxt_set_fecparam(struct net_device *dev, 3170 struct ethtool_fecparam *fecparam) 3171 { 3172 struct hwrm_port_phy_cfg_input *req; 3173 struct bnxt *bp = netdev_priv(dev); 3174 struct bnxt_link_info *link_info; 3175 u32 new_cfg, fec = fecparam->fec; 3176 u16 fec_cfg; 3177 int rc; 3178 3179 link_info = &bp->link_info; 3180 fec_cfg = link_info->fec_cfg; 3181 if (fec_cfg & BNXT_FEC_NONE) 3182 return -EOPNOTSUPP; 3183 3184 if (fec & ETHTOOL_FEC_OFF) { 3185 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE | 3186 BNXT_FEC_ALL_OFF(link_info); 3187 goto apply_fec; 3188 } 3189 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) || 3190 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) || 3191 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) || 3192 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP))) 3193 return -EINVAL; 3194 3195 if (fec & ETHTOOL_FEC_AUTO) { 3196 if (!link_info->autoneg) 3197 return -EINVAL; 3198 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE; 3199 } else { 3200 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec); 3201 } 3202 3203 apply_fec: 3204 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 3205 if (rc) 3206 return rc; 3207 req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 3208 rc = hwrm_req_send(bp, req); 3209 /* update current settings */ 3210 if (!rc) { 3211 mutex_lock(&bp->link_lock); 3212 bnxt_update_link(bp, false); 3213 mutex_unlock(&bp->link_lock); 3214 } 3215 return rc; 3216 } 3217 3218 static void bnxt_get_pauseparam(struct net_device *dev, 3219 struct ethtool_pauseparam *epause) 3220 { 3221 struct bnxt *bp = netdev_priv(dev); 3222 struct bnxt_link_info *link_info = &bp->link_info; 3223 3224 if (BNXT_VF(bp)) 3225 return; 3226 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 3227 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 3228 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 3229 } 3230 3231 static void bnxt_get_pause_stats(struct net_device *dev, 3232 struct ethtool_pause_stats *epstat) 3233 { 3234 struct bnxt *bp = netdev_priv(dev); 3235 u64 *rx, *tx; 3236 3237 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 3238 return; 3239 3240 rx = bp->port_stats.sw_stats; 3241 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 3242 3243 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames); 3244 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames); 3245 } 3246 3247 static int bnxt_set_pauseparam(struct net_device *dev, 3248 struct ethtool_pauseparam *epause) 3249 { 3250 int rc = 0; 3251 struct bnxt *bp = netdev_priv(dev); 3252 struct bnxt_link_info *link_info = &bp->link_info; 3253 3254 if (!BNXT_PHY_CFG_ABLE(bp) || (bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 3255 return -EOPNOTSUPP; 3256 3257 mutex_lock(&bp->link_lock); 3258 if (epause->autoneg) { 3259 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 3260 rc = -EINVAL; 3261 goto pause_exit; 3262 } 3263 3264 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 3265 link_info->req_flow_ctrl = 0; 3266 } else { 3267 /* when transition from auto pause to force pause, 3268 * force a link change 3269 */ 3270 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 3271 link_info->force_link_chng = true; 3272 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 3273 link_info->req_flow_ctrl = 0; 3274 } 3275 if (epause->rx_pause) 3276 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 3277 3278 if (epause->tx_pause) 3279 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 3280 3281 if (netif_running(dev)) 3282 rc = bnxt_hwrm_set_pause(bp); 3283 3284 pause_exit: 3285 mutex_unlock(&bp->link_lock); 3286 return rc; 3287 } 3288 3289 static u32 bnxt_get_link(struct net_device *dev) 3290 { 3291 struct bnxt *bp = netdev_priv(dev); 3292 3293 /* TODO: handle MF, VF, driver close case */ 3294 return BNXT_LINK_IS_UP(bp); 3295 } 3296 3297 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp, 3298 struct hwrm_nvm_get_dev_info_output *nvm_dev_info) 3299 { 3300 struct hwrm_nvm_get_dev_info_output *resp; 3301 struct hwrm_nvm_get_dev_info_input *req; 3302 int rc; 3303 3304 if (BNXT_VF(bp)) 3305 return -EOPNOTSUPP; 3306 3307 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO); 3308 if (rc) 3309 return rc; 3310 3311 resp = hwrm_req_hold(bp, req); 3312 rc = hwrm_req_send(bp, req); 3313 if (!rc) 3314 memcpy(nvm_dev_info, resp, sizeof(*resp)); 3315 hwrm_req_drop(bp, req); 3316 return rc; 3317 } 3318 3319 static void bnxt_print_admin_err(struct bnxt *bp) 3320 { 3321 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 3322 } 3323 3324 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 3325 u16 ext, u16 *index, u32 *item_length, 3326 u32 *data_length); 3327 3328 int bnxt_flash_nvram(struct net_device *dev, u16 dir_type, 3329 u16 dir_ordinal, u16 dir_ext, u16 dir_attr, 3330 u32 dir_item_len, const u8 *data, 3331 size_t data_len) 3332 { 3333 struct bnxt *bp = netdev_priv(dev); 3334 struct hwrm_nvm_write_input *req; 3335 int rc; 3336 3337 rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE); 3338 if (rc) 3339 return rc; 3340 3341 if (data_len && data) { 3342 dma_addr_t dma_handle; 3343 u8 *kmem; 3344 3345 kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle); 3346 if (!kmem) { 3347 hwrm_req_drop(bp, req); 3348 return -ENOMEM; 3349 } 3350 3351 req->dir_data_length = cpu_to_le32(data_len); 3352 3353 memcpy(kmem, data, data_len); 3354 req->host_src_addr = cpu_to_le64(dma_handle); 3355 } 3356 3357 hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout); 3358 req->dir_type = cpu_to_le16(dir_type); 3359 req->dir_ordinal = cpu_to_le16(dir_ordinal); 3360 req->dir_ext = cpu_to_le16(dir_ext); 3361 req->dir_attr = cpu_to_le16(dir_attr); 3362 req->dir_item_length = cpu_to_le32(dir_item_len); 3363 rc = hwrm_req_send(bp, req); 3364 3365 if (rc == -EACCES) 3366 bnxt_print_admin_err(bp); 3367 return rc; 3368 } 3369 3370 int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type, 3371 u8 self_reset, u8 flags) 3372 { 3373 struct bnxt *bp = netdev_priv(dev); 3374 struct hwrm_fw_reset_input *req; 3375 int rc; 3376 3377 if (!bnxt_hwrm_reset_permitted(bp)) { 3378 netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver"); 3379 return -EPERM; 3380 } 3381 3382 rc = hwrm_req_init(bp, req, HWRM_FW_RESET); 3383 if (rc) 3384 return rc; 3385 3386 req->embedded_proc_type = proc_type; 3387 req->selfrst_status = self_reset; 3388 req->flags = flags; 3389 3390 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) { 3391 rc = hwrm_req_send_silent(bp, req); 3392 } else { 3393 rc = hwrm_req_send(bp, req); 3394 if (rc == -EACCES) 3395 bnxt_print_admin_err(bp); 3396 } 3397 return rc; 3398 } 3399 3400 static int bnxt_firmware_reset(struct net_device *dev, 3401 enum bnxt_nvm_directory_type dir_type) 3402 { 3403 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE; 3404 u8 proc_type, flags = 0; 3405 3406 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 3407 /* (e.g. when firmware isn't already running) */ 3408 switch (dir_type) { 3409 case BNX_DIR_TYPE_CHIMP_PATCH: 3410 case BNX_DIR_TYPE_BOOTCODE: 3411 case BNX_DIR_TYPE_BOOTCODE_2: 3412 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 3413 /* Self-reset ChiMP upon next PCIe reset: */ 3414 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 3415 break; 3416 case BNX_DIR_TYPE_APE_FW: 3417 case BNX_DIR_TYPE_APE_PATCH: 3418 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 3419 /* Self-reset APE upon next PCIe reset: */ 3420 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 3421 break; 3422 case BNX_DIR_TYPE_KONG_FW: 3423 case BNX_DIR_TYPE_KONG_PATCH: 3424 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 3425 break; 3426 case BNX_DIR_TYPE_BONO_FW: 3427 case BNX_DIR_TYPE_BONO_PATCH: 3428 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 3429 break; 3430 default: 3431 return -EINVAL; 3432 } 3433 3434 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags); 3435 } 3436 3437 static int bnxt_firmware_reset_chip(struct net_device *dev) 3438 { 3439 struct bnxt *bp = netdev_priv(dev); 3440 u8 flags = 0; 3441 3442 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 3443 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 3444 3445 return bnxt_hwrm_firmware_reset(dev, 3446 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP, 3447 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP, 3448 flags); 3449 } 3450 3451 static int bnxt_firmware_reset_ap(struct net_device *dev) 3452 { 3453 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP, 3454 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE, 3455 0); 3456 } 3457 3458 static int bnxt_flash_firmware(struct net_device *dev, 3459 u16 dir_type, 3460 const u8 *fw_data, 3461 size_t fw_size) 3462 { 3463 int rc = 0; 3464 u16 code_type; 3465 u32 stored_crc; 3466 u32 calculated_crc; 3467 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 3468 3469 switch (dir_type) { 3470 case BNX_DIR_TYPE_BOOTCODE: 3471 case BNX_DIR_TYPE_BOOTCODE_2: 3472 code_type = CODE_BOOT; 3473 break; 3474 case BNX_DIR_TYPE_CHIMP_PATCH: 3475 code_type = CODE_CHIMP_PATCH; 3476 break; 3477 case BNX_DIR_TYPE_APE_FW: 3478 code_type = CODE_MCTP_PASSTHRU; 3479 break; 3480 case BNX_DIR_TYPE_APE_PATCH: 3481 code_type = CODE_APE_PATCH; 3482 break; 3483 case BNX_DIR_TYPE_KONG_FW: 3484 code_type = CODE_KONG_FW; 3485 break; 3486 case BNX_DIR_TYPE_KONG_PATCH: 3487 code_type = CODE_KONG_PATCH; 3488 break; 3489 case BNX_DIR_TYPE_BONO_FW: 3490 code_type = CODE_BONO_FW; 3491 break; 3492 case BNX_DIR_TYPE_BONO_PATCH: 3493 code_type = CODE_BONO_PATCH; 3494 break; 3495 default: 3496 netdev_err(dev, "Unsupported directory entry type: %u\n", 3497 dir_type); 3498 return -EINVAL; 3499 } 3500 if (fw_size < sizeof(struct bnxt_fw_header)) { 3501 netdev_err(dev, "Invalid firmware file size: %u\n", 3502 (unsigned int)fw_size); 3503 return -EINVAL; 3504 } 3505 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 3506 netdev_err(dev, "Invalid firmware signature: %08X\n", 3507 le32_to_cpu(header->signature)); 3508 return -EINVAL; 3509 } 3510 if (header->code_type != code_type) { 3511 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 3512 code_type, header->code_type); 3513 return -EINVAL; 3514 } 3515 if (header->device != DEVICE_CUMULUS_FAMILY) { 3516 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 3517 DEVICE_CUMULUS_FAMILY, header->device); 3518 return -EINVAL; 3519 } 3520 /* Confirm the CRC32 checksum of the file: */ 3521 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 3522 sizeof(stored_crc))); 3523 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 3524 if (calculated_crc != stored_crc) { 3525 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 3526 (unsigned long)stored_crc, 3527 (unsigned long)calculated_crc); 3528 return -EINVAL; 3529 } 3530 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3531 0, 0, 0, fw_data, fw_size); 3532 if (rc == 0) /* Firmware update successful */ 3533 rc = bnxt_firmware_reset(dev, dir_type); 3534 3535 return rc; 3536 } 3537 3538 static int bnxt_flash_microcode(struct net_device *dev, 3539 u16 dir_type, 3540 const u8 *fw_data, 3541 size_t fw_size) 3542 { 3543 struct bnxt_ucode_trailer *trailer; 3544 u32 calculated_crc; 3545 u32 stored_crc; 3546 int rc = 0; 3547 3548 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 3549 netdev_err(dev, "Invalid microcode file size: %u\n", 3550 (unsigned int)fw_size); 3551 return -EINVAL; 3552 } 3553 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 3554 sizeof(*trailer))); 3555 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 3556 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 3557 le32_to_cpu(trailer->sig)); 3558 return -EINVAL; 3559 } 3560 if (le16_to_cpu(trailer->dir_type) != dir_type) { 3561 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 3562 dir_type, le16_to_cpu(trailer->dir_type)); 3563 return -EINVAL; 3564 } 3565 if (le16_to_cpu(trailer->trailer_length) < 3566 sizeof(struct bnxt_ucode_trailer)) { 3567 netdev_err(dev, "Invalid microcode trailer length: %d\n", 3568 le16_to_cpu(trailer->trailer_length)); 3569 return -EINVAL; 3570 } 3571 3572 /* Confirm the CRC32 checksum of the file: */ 3573 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 3574 sizeof(stored_crc))); 3575 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 3576 if (calculated_crc != stored_crc) { 3577 netdev_err(dev, 3578 "CRC32 (%08lX) does not match calculated: %08lX\n", 3579 (unsigned long)stored_crc, 3580 (unsigned long)calculated_crc); 3581 return -EINVAL; 3582 } 3583 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3584 0, 0, 0, fw_data, fw_size); 3585 3586 return rc; 3587 } 3588 3589 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 3590 { 3591 switch (dir_type) { 3592 case BNX_DIR_TYPE_CHIMP_PATCH: 3593 case BNX_DIR_TYPE_BOOTCODE: 3594 case BNX_DIR_TYPE_BOOTCODE_2: 3595 case BNX_DIR_TYPE_APE_FW: 3596 case BNX_DIR_TYPE_APE_PATCH: 3597 case BNX_DIR_TYPE_KONG_FW: 3598 case BNX_DIR_TYPE_KONG_PATCH: 3599 case BNX_DIR_TYPE_BONO_FW: 3600 case BNX_DIR_TYPE_BONO_PATCH: 3601 return true; 3602 } 3603 3604 return false; 3605 } 3606 3607 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 3608 { 3609 switch (dir_type) { 3610 case BNX_DIR_TYPE_AVS: 3611 case BNX_DIR_TYPE_EXP_ROM_MBA: 3612 case BNX_DIR_TYPE_PCIE: 3613 case BNX_DIR_TYPE_TSCF_UCODE: 3614 case BNX_DIR_TYPE_EXT_PHY: 3615 case BNX_DIR_TYPE_CCM: 3616 case BNX_DIR_TYPE_ISCSI_BOOT: 3617 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 3618 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 3619 return true; 3620 } 3621 3622 return false; 3623 } 3624 3625 static bool bnxt_dir_type_is_executable(u16 dir_type) 3626 { 3627 return bnxt_dir_type_is_ape_bin_format(dir_type) || 3628 bnxt_dir_type_is_other_exec_format(dir_type); 3629 } 3630 3631 static int bnxt_flash_firmware_from_file(struct net_device *dev, 3632 u16 dir_type, 3633 const char *filename) 3634 { 3635 const struct firmware *fw; 3636 int rc; 3637 3638 rc = request_firmware(&fw, filename, &dev->dev); 3639 if (rc != 0) { 3640 netdev_err(dev, "Error %d requesting firmware file: %s\n", 3641 rc, filename); 3642 return rc; 3643 } 3644 if (bnxt_dir_type_is_ape_bin_format(dir_type)) 3645 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 3646 else if (bnxt_dir_type_is_other_exec_format(dir_type)) 3647 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 3648 else 3649 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3650 0, 0, 0, fw->data, fw->size); 3651 release_firmware(fw); 3652 return rc; 3653 } 3654 3655 #define MSG_INTEGRITY_ERR "PKG install error : Data integrity on NVM" 3656 #define MSG_INVALID_PKG "PKG install error : Invalid package" 3657 #define MSG_AUTHENTICATION_ERR "PKG install error : Authentication error" 3658 #define MSG_INVALID_DEV "PKG install error : Invalid device" 3659 #define MSG_INTERNAL_ERR "PKG install error : Internal error" 3660 #define MSG_NO_PKG_UPDATE_AREA_ERR "PKG update area not created in nvram" 3661 #define MSG_NO_SPACE_ERR "PKG insufficient update area in nvram" 3662 #define MSG_RESIZE_UPDATE_ERR "Resize UPDATE entry error" 3663 #define MSG_ANTI_ROLLBACK_ERR "HWRM_NVM_INSTALL_UPDATE failure due to Anti-rollback detected" 3664 #define MSG_GENERIC_FAILURE_ERR "HWRM_NVM_INSTALL_UPDATE failure" 3665 3666 static int nvm_update_err_to_stderr(struct net_device *dev, u8 result, 3667 struct netlink_ext_ack *extack) 3668 { 3669 switch (result) { 3670 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER: 3671 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER: 3672 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR: 3673 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR: 3674 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND: 3675 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED: 3676 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTEGRITY_ERR); 3677 return -EINVAL; 3678 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE: 3679 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER: 3680 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE: 3681 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM: 3682 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH: 3683 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST: 3684 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER: 3685 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM: 3686 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM: 3687 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH: 3688 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE: 3689 case NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM: 3690 case NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM: 3691 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_PKG); 3692 return -ENOPKG; 3693 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR: 3694 BNXT_NVM_ERR_MSG(dev, extack, MSG_AUTHENTICATION_ERR); 3695 return -EPERM; 3696 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV: 3697 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID: 3698 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR: 3699 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID: 3700 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM: 3701 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_DEV); 3702 return -EOPNOTSUPP; 3703 default: 3704 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTERNAL_ERR); 3705 return -EIO; 3706 } 3707 } 3708 3709 #define BNXT_PKG_DMA_SIZE 0x40000 3710 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE)) 3711 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST)) 3712 3713 static int bnxt_resize_update_entry(struct net_device *dev, size_t fw_size, 3714 struct netlink_ext_ack *extack) 3715 { 3716 u32 item_len; 3717 int rc; 3718 3719 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 3720 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, NULL, 3721 &item_len, NULL); 3722 if (rc) { 3723 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 3724 return rc; 3725 } 3726 3727 if (fw_size > item_len) { 3728 rc = bnxt_flash_nvram(dev, BNX_DIR_TYPE_UPDATE, 3729 BNX_DIR_ORDINAL_FIRST, 0, 1, 3730 round_up(fw_size, 4096), NULL, 0); 3731 if (rc) { 3732 BNXT_NVM_ERR_MSG(dev, extack, MSG_RESIZE_UPDATE_ERR); 3733 return rc; 3734 } 3735 } 3736 return 0; 3737 } 3738 3739 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw, 3740 u32 install_type, struct netlink_ext_ack *extack) 3741 { 3742 struct hwrm_nvm_install_update_input *install; 3743 struct hwrm_nvm_install_update_output *resp; 3744 struct hwrm_nvm_modify_input *modify; 3745 struct bnxt *bp = netdev_priv(dev); 3746 bool defrag_attempted = false; 3747 dma_addr_t dma_handle; 3748 u8 *kmem = NULL; 3749 u32 modify_len; 3750 u32 item_len; 3751 u8 cmd_err; 3752 u16 index; 3753 int rc; 3754 3755 /* resize before flashing larger image than available space */ 3756 rc = bnxt_resize_update_entry(dev, fw->size, extack); 3757 if (rc) 3758 return rc; 3759 3760 bnxt_hwrm_fw_set_time(bp); 3761 3762 rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY); 3763 if (rc) 3764 return rc; 3765 3766 /* Try allocating a large DMA buffer first. Older fw will 3767 * cause excessive NVRAM erases when using small blocks. 3768 */ 3769 modify_len = roundup_pow_of_two(fw->size); 3770 modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE); 3771 while (1) { 3772 kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle); 3773 if (!kmem && modify_len > PAGE_SIZE) 3774 modify_len /= 2; 3775 else 3776 break; 3777 } 3778 if (!kmem) { 3779 hwrm_req_drop(bp, modify); 3780 return -ENOMEM; 3781 } 3782 3783 rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE); 3784 if (rc) { 3785 hwrm_req_drop(bp, modify); 3786 return rc; 3787 } 3788 3789 hwrm_req_timeout(bp, modify, bp->hwrm_cmd_max_timeout); 3790 hwrm_req_timeout(bp, install, bp->hwrm_cmd_max_timeout); 3791 3792 hwrm_req_hold(bp, modify); 3793 modify->host_src_addr = cpu_to_le64(dma_handle); 3794 3795 resp = hwrm_req_hold(bp, install); 3796 if ((install_type & 0xffff) == 0) 3797 install_type >>= 16; 3798 install->install_type = cpu_to_le32(install_type); 3799 3800 do { 3801 u32 copied = 0, len = modify_len; 3802 3803 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 3804 BNX_DIR_ORDINAL_FIRST, 3805 BNX_DIR_EXT_NONE, 3806 &index, &item_len, NULL); 3807 if (rc) { 3808 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 3809 break; 3810 } 3811 if (fw->size > item_len) { 3812 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_SPACE_ERR); 3813 rc = -EFBIG; 3814 break; 3815 } 3816 3817 modify->dir_idx = cpu_to_le16(index); 3818 3819 if (fw->size > modify_len) 3820 modify->flags = BNXT_NVM_MORE_FLAG; 3821 while (copied < fw->size) { 3822 u32 balance = fw->size - copied; 3823 3824 if (balance <= modify_len) { 3825 len = balance; 3826 if (copied) 3827 modify->flags |= BNXT_NVM_LAST_FLAG; 3828 } 3829 memcpy(kmem, fw->data + copied, len); 3830 modify->len = cpu_to_le32(len); 3831 modify->offset = cpu_to_le32(copied); 3832 rc = hwrm_req_send(bp, modify); 3833 if (rc) 3834 goto pkg_abort; 3835 copied += len; 3836 } 3837 3838 rc = hwrm_req_send_silent(bp, install); 3839 if (!rc) 3840 break; 3841 3842 if (defrag_attempted) { 3843 /* We have tried to defragment already in the previous 3844 * iteration. Return with the result for INSTALL_UPDATE 3845 */ 3846 break; 3847 } 3848 3849 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 3850 3851 switch (cmd_err) { 3852 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK: 3853 BNXT_NVM_ERR_MSG(dev, extack, MSG_ANTI_ROLLBACK_ERR); 3854 rc = -EALREADY; 3855 break; 3856 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR: 3857 install->flags = 3858 cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 3859 3860 rc = hwrm_req_send_silent(bp, install); 3861 if (!rc) 3862 break; 3863 3864 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 3865 3866 if (cmd_err == NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) { 3867 /* FW has cleared NVM area, driver will create 3868 * UPDATE directory and try the flash again 3869 */ 3870 defrag_attempted = true; 3871 install->flags = 0; 3872 rc = bnxt_flash_nvram(bp->dev, 3873 BNX_DIR_TYPE_UPDATE, 3874 BNX_DIR_ORDINAL_FIRST, 3875 0, 0, item_len, NULL, 0); 3876 if (!rc) 3877 break; 3878 } 3879 fallthrough; 3880 default: 3881 BNXT_NVM_ERR_MSG(dev, extack, MSG_GENERIC_FAILURE_ERR); 3882 } 3883 } while (defrag_attempted && !rc); 3884 3885 pkg_abort: 3886 hwrm_req_drop(bp, modify); 3887 hwrm_req_drop(bp, install); 3888 3889 if (resp->result) { 3890 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 3891 (s8)resp->result, (int)resp->problem_item); 3892 rc = nvm_update_err_to_stderr(dev, resp->result, extack); 3893 } 3894 if (rc == -EACCES) 3895 bnxt_print_admin_err(bp); 3896 return rc; 3897 } 3898 3899 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename, 3900 u32 install_type, struct netlink_ext_ack *extack) 3901 { 3902 const struct firmware *fw; 3903 int rc; 3904 3905 rc = request_firmware(&fw, filename, &dev->dev); 3906 if (rc != 0) { 3907 netdev_err(dev, "PKG error %d requesting file: %s\n", 3908 rc, filename); 3909 return rc; 3910 } 3911 3912 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type, extack); 3913 3914 release_firmware(fw); 3915 3916 return rc; 3917 } 3918 3919 static int bnxt_flash_device(struct net_device *dev, 3920 struct ethtool_flash *flash) 3921 { 3922 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 3923 netdev_err(dev, "flashdev not supported from a virtual function\n"); 3924 return -EINVAL; 3925 } 3926 3927 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 3928 flash->region > 0xffff) 3929 return bnxt_flash_package_from_file(dev, flash->data, 3930 flash->region, NULL); 3931 3932 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 3933 } 3934 3935 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 3936 { 3937 struct hwrm_nvm_get_dir_info_output *output; 3938 struct hwrm_nvm_get_dir_info_input *req; 3939 struct bnxt *bp = netdev_priv(dev); 3940 int rc; 3941 3942 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO); 3943 if (rc) 3944 return rc; 3945 3946 output = hwrm_req_hold(bp, req); 3947 rc = hwrm_req_send(bp, req); 3948 if (!rc) { 3949 *entries = le32_to_cpu(output->entries); 3950 *length = le32_to_cpu(output->entry_length); 3951 } 3952 hwrm_req_drop(bp, req); 3953 return rc; 3954 } 3955 3956 static int bnxt_get_eeprom_len(struct net_device *dev) 3957 { 3958 struct bnxt *bp = netdev_priv(dev); 3959 3960 if (BNXT_VF(bp)) 3961 return 0; 3962 3963 /* The -1 return value allows the entire 32-bit range of offsets to be 3964 * passed via the ethtool command-line utility. 3965 */ 3966 return -1; 3967 } 3968 3969 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 3970 { 3971 struct bnxt *bp = netdev_priv(dev); 3972 int rc; 3973 u32 dir_entries; 3974 u32 entry_length; 3975 u8 *buf; 3976 size_t buflen; 3977 dma_addr_t dma_handle; 3978 struct hwrm_nvm_get_dir_entries_input *req; 3979 3980 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 3981 if (rc != 0) 3982 return rc; 3983 3984 if (!dir_entries || !entry_length) 3985 return -EIO; 3986 3987 /* Insert 2 bytes of directory info (count and size of entries) */ 3988 if (len < 2) 3989 return -EINVAL; 3990 3991 *data++ = dir_entries; 3992 *data++ = entry_length; 3993 len -= 2; 3994 memset(data, 0xff, len); 3995 3996 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES); 3997 if (rc) 3998 return rc; 3999 4000 buflen = mul_u32_u32(dir_entries, entry_length); 4001 buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle); 4002 if (!buf) { 4003 hwrm_req_drop(bp, req); 4004 return -ENOMEM; 4005 } 4006 req->host_dest_addr = cpu_to_le64(dma_handle); 4007 4008 hwrm_req_hold(bp, req); /* hold the slice */ 4009 rc = hwrm_req_send(bp, req); 4010 if (rc == 0) 4011 memcpy(data, buf, len > buflen ? buflen : len); 4012 hwrm_req_drop(bp, req); 4013 return rc; 4014 } 4015 4016 int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 4017 u32 length, u8 *data) 4018 { 4019 struct bnxt *bp = netdev_priv(dev); 4020 int rc; 4021 u8 *buf; 4022 dma_addr_t dma_handle; 4023 struct hwrm_nvm_read_input *req; 4024 4025 if (!length) 4026 return -EINVAL; 4027 4028 rc = hwrm_req_init(bp, req, HWRM_NVM_READ); 4029 if (rc) 4030 return rc; 4031 4032 buf = hwrm_req_dma_slice(bp, req, length, &dma_handle); 4033 if (!buf) { 4034 hwrm_req_drop(bp, req); 4035 return -ENOMEM; 4036 } 4037 4038 req->host_dest_addr = cpu_to_le64(dma_handle); 4039 req->dir_idx = cpu_to_le16(index); 4040 req->offset = cpu_to_le32(offset); 4041 req->len = cpu_to_le32(length); 4042 4043 hwrm_req_hold(bp, req); /* hold the slice */ 4044 rc = hwrm_req_send(bp, req); 4045 if (rc == 0) 4046 memcpy(data, buf, length); 4047 hwrm_req_drop(bp, req); 4048 return rc; 4049 } 4050 4051 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 4052 u16 ext, u16 *index, u32 *item_length, 4053 u32 *data_length) 4054 { 4055 struct hwrm_nvm_find_dir_entry_output *output; 4056 struct hwrm_nvm_find_dir_entry_input *req; 4057 struct bnxt *bp = netdev_priv(dev); 4058 int rc; 4059 4060 rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY); 4061 if (rc) 4062 return rc; 4063 4064 req->enables = 0; 4065 req->dir_idx = 0; 4066 req->dir_type = cpu_to_le16(type); 4067 req->dir_ordinal = cpu_to_le16(ordinal); 4068 req->dir_ext = cpu_to_le16(ext); 4069 req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 4070 output = hwrm_req_hold(bp, req); 4071 rc = hwrm_req_send_silent(bp, req); 4072 if (rc == 0) { 4073 if (index) 4074 *index = le16_to_cpu(output->dir_idx); 4075 if (item_length) 4076 *item_length = le32_to_cpu(output->dir_item_length); 4077 if (data_length) 4078 *data_length = le32_to_cpu(output->dir_data_length); 4079 } 4080 hwrm_req_drop(bp, req); 4081 return rc; 4082 } 4083 4084 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 4085 { 4086 char *retval = NULL; 4087 char *p; 4088 char *value; 4089 int field = 0; 4090 4091 if (datalen < 1) 4092 return NULL; 4093 /* null-terminate the log data (removing last '\n'): */ 4094 data[datalen - 1] = 0; 4095 for (p = data; *p != 0; p++) { 4096 field = 0; 4097 retval = NULL; 4098 while (*p != 0 && *p != '\n') { 4099 value = p; 4100 while (*p != 0 && *p != '\t' && *p != '\n') 4101 p++; 4102 if (field == desired_field) 4103 retval = value; 4104 if (*p != '\t') 4105 break; 4106 *p = 0; 4107 field++; 4108 p++; 4109 } 4110 if (*p == 0) 4111 break; 4112 *p = 0; 4113 } 4114 return retval; 4115 } 4116 4117 int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size) 4118 { 4119 struct bnxt *bp = netdev_priv(dev); 4120 u16 index = 0; 4121 char *pkgver; 4122 u32 pkglen; 4123 u8 *pkgbuf; 4124 int rc; 4125 4126 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 4127 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 4128 &index, NULL, &pkglen); 4129 if (rc) 4130 return rc; 4131 4132 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 4133 if (!pkgbuf) { 4134 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 4135 pkglen); 4136 return -ENOMEM; 4137 } 4138 4139 rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf); 4140 if (rc) 4141 goto err; 4142 4143 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 4144 pkglen); 4145 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) 4146 strscpy(ver, pkgver, size); 4147 else 4148 rc = -ENOENT; 4149 4150 err: 4151 kfree(pkgbuf); 4152 4153 return rc; 4154 } 4155 4156 static void bnxt_get_pkgver(struct net_device *dev) 4157 { 4158 struct bnxt *bp = netdev_priv(dev); 4159 char buf[FW_VER_STR_LEN]; 4160 int len; 4161 4162 if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) { 4163 len = strlen(bp->fw_ver_str); 4164 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1, 4165 "/pkg %s", buf); 4166 } 4167 } 4168 4169 static int bnxt_get_eeprom(struct net_device *dev, 4170 struct ethtool_eeprom *eeprom, 4171 u8 *data) 4172 { 4173 u32 index; 4174 u32 offset; 4175 4176 if (eeprom->offset == 0) /* special offset value to get directory */ 4177 return bnxt_get_nvram_directory(dev, eeprom->len, data); 4178 4179 index = eeprom->offset >> 24; 4180 offset = eeprom->offset & 0xffffff; 4181 4182 if (index == 0) { 4183 netdev_err(dev, "unsupported index value: %d\n", index); 4184 return -EINVAL; 4185 } 4186 4187 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 4188 } 4189 4190 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 4191 { 4192 struct hwrm_nvm_erase_dir_entry_input *req; 4193 struct bnxt *bp = netdev_priv(dev); 4194 int rc; 4195 4196 rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY); 4197 if (rc) 4198 return rc; 4199 4200 req->dir_idx = cpu_to_le16(index); 4201 return hwrm_req_send(bp, req); 4202 } 4203 4204 static int bnxt_set_eeprom(struct net_device *dev, 4205 struct ethtool_eeprom *eeprom, 4206 u8 *data) 4207 { 4208 struct bnxt *bp = netdev_priv(dev); 4209 u8 index, dir_op; 4210 u16 type, ext, ordinal, attr; 4211 4212 if (!BNXT_PF(bp)) { 4213 netdev_err(dev, "NVM write not supported from a virtual function\n"); 4214 return -EINVAL; 4215 } 4216 4217 type = eeprom->magic >> 16; 4218 4219 if (type == 0xffff) { /* special value for directory operations */ 4220 index = eeprom->magic & 0xff; 4221 dir_op = eeprom->magic >> 8; 4222 if (index == 0) 4223 return -EINVAL; 4224 switch (dir_op) { 4225 case 0x0e: /* erase */ 4226 if (eeprom->offset != ~eeprom->magic) 4227 return -EINVAL; 4228 return bnxt_erase_nvram_directory(dev, index - 1); 4229 default: 4230 return -EINVAL; 4231 } 4232 } 4233 4234 /* Create or re-write an NVM item: */ 4235 if (bnxt_dir_type_is_executable(type)) 4236 return -EOPNOTSUPP; 4237 ext = eeprom->magic & 0xffff; 4238 ordinal = eeprom->offset >> 16; 4239 attr = eeprom->offset & 0xffff; 4240 4241 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data, 4242 eeprom->len); 4243 } 4244 4245 static int bnxt_set_eee(struct net_device *dev, struct ethtool_keee *edata) 4246 { 4247 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 4248 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp); 4249 struct bnxt *bp = netdev_priv(dev); 4250 struct ethtool_keee *eee = &bp->eee; 4251 struct bnxt_link_info *link_info = &bp->link_info; 4252 int rc = 0; 4253 4254 if (!BNXT_PHY_CFG_ABLE(bp)) 4255 return -EOPNOTSUPP; 4256 4257 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 4258 return -EOPNOTSUPP; 4259 4260 mutex_lock(&bp->link_lock); 4261 _bnxt_fw_to_linkmode(advertising, link_info->advertising); 4262 if (!edata->eee_enabled) 4263 goto eee_ok; 4264 4265 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 4266 netdev_warn(dev, "EEE requires autoneg\n"); 4267 rc = -EINVAL; 4268 goto eee_exit; 4269 } 4270 if (edata->tx_lpi_enabled) { 4271 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 4272 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 4273 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 4274 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 4275 rc = -EINVAL; 4276 goto eee_exit; 4277 } else if (!bp->lpi_tmr_hi) { 4278 edata->tx_lpi_timer = eee->tx_lpi_timer; 4279 } 4280 } 4281 if (linkmode_empty(edata->advertised)) { 4282 linkmode_and(edata->advertised, advertising, eee->supported); 4283 } else if (linkmode_andnot(tmp, edata->advertised, advertising)) { 4284 netdev_warn(dev, "EEE advertised must be a subset of autoneg advertised speeds\n"); 4285 rc = -EINVAL; 4286 goto eee_exit; 4287 } 4288 4289 linkmode_copy(eee->advertised, edata->advertised); 4290 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 4291 eee->tx_lpi_timer = edata->tx_lpi_timer; 4292 eee_ok: 4293 eee->eee_enabled = edata->eee_enabled; 4294 4295 if (netif_running(dev)) 4296 rc = bnxt_hwrm_set_link_setting(bp, false, true); 4297 4298 eee_exit: 4299 mutex_unlock(&bp->link_lock); 4300 return rc; 4301 } 4302 4303 static int bnxt_get_eee(struct net_device *dev, struct ethtool_keee *edata) 4304 { 4305 struct bnxt *bp = netdev_priv(dev); 4306 4307 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 4308 return -EOPNOTSUPP; 4309 4310 *edata = bp->eee; 4311 if (!bp->eee.eee_enabled) { 4312 /* Preserve tx_lpi_timer so that the last value will be used 4313 * by default when it is re-enabled. 4314 */ 4315 linkmode_zero(edata->advertised); 4316 edata->tx_lpi_enabled = 0; 4317 } 4318 4319 if (!bp->eee.eee_active) 4320 linkmode_zero(edata->lp_advertised); 4321 4322 return 0; 4323 } 4324 4325 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 4326 u16 page_number, u8 bank, 4327 u16 start_addr, u16 data_length, 4328 u8 *buf) 4329 { 4330 struct hwrm_port_phy_i2c_read_output *output; 4331 struct hwrm_port_phy_i2c_read_input *req; 4332 int rc, byte_offset = 0; 4333 4334 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ); 4335 if (rc) 4336 return rc; 4337 4338 output = hwrm_req_hold(bp, req); 4339 req->i2c_slave_addr = i2c_addr; 4340 req->page_number = cpu_to_le16(page_number); 4341 req->port_id = cpu_to_le16(bp->pf.port_id); 4342 do { 4343 u16 xfer_size; 4344 4345 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 4346 data_length -= xfer_size; 4347 req->page_offset = cpu_to_le16(start_addr + byte_offset); 4348 req->data_length = xfer_size; 4349 req->enables = 4350 cpu_to_le32((start_addr + byte_offset ? 4351 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 4352 0) | 4353 (bank ? 4354 PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER : 4355 0)); 4356 rc = hwrm_req_send(bp, req); 4357 if (!rc) 4358 memcpy(buf + byte_offset, output->data, xfer_size); 4359 byte_offset += xfer_size; 4360 } while (!rc && data_length > 0); 4361 hwrm_req_drop(bp, req); 4362 4363 return rc; 4364 } 4365 4366 static int bnxt_get_module_info(struct net_device *dev, 4367 struct ethtool_modinfo *modinfo) 4368 { 4369 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 4370 struct bnxt *bp = netdev_priv(dev); 4371 int rc; 4372 4373 /* No point in going further if phy status indicates 4374 * module is not inserted or if it is powered down or 4375 * if it is of type 10GBase-T 4376 */ 4377 if (bp->link_info.module_status > 4378 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 4379 return -EOPNOTSUPP; 4380 4381 /* This feature is not supported in older firmware versions */ 4382 if (bp->hwrm_spec_code < 0x10202) 4383 return -EOPNOTSUPP; 4384 4385 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 0, 4386 SFF_DIAG_SUPPORT_OFFSET + 1, 4387 data); 4388 if (!rc) { 4389 u8 module_id = data[0]; 4390 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 4391 4392 switch (module_id) { 4393 case SFF_MODULE_ID_SFP: 4394 modinfo->type = ETH_MODULE_SFF_8472; 4395 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 4396 if (!diag_supported) 4397 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 4398 break; 4399 case SFF_MODULE_ID_QSFP: 4400 case SFF_MODULE_ID_QSFP_PLUS: 4401 modinfo->type = ETH_MODULE_SFF_8436; 4402 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 4403 break; 4404 case SFF_MODULE_ID_QSFP28: 4405 modinfo->type = ETH_MODULE_SFF_8636; 4406 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 4407 break; 4408 default: 4409 rc = -EOPNOTSUPP; 4410 break; 4411 } 4412 } 4413 return rc; 4414 } 4415 4416 static int bnxt_get_module_eeprom(struct net_device *dev, 4417 struct ethtool_eeprom *eeprom, 4418 u8 *data) 4419 { 4420 struct bnxt *bp = netdev_priv(dev); 4421 u16 start = eeprom->offset, length = eeprom->len; 4422 int rc = 0; 4423 4424 memset(data, 0, eeprom->len); 4425 4426 /* Read A0 portion of the EEPROM */ 4427 if (start < ETH_MODULE_SFF_8436_LEN) { 4428 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 4429 length = ETH_MODULE_SFF_8436_LEN - start; 4430 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 4431 start, length, data); 4432 if (rc) 4433 return rc; 4434 start += length; 4435 data += length; 4436 length = eeprom->len - length; 4437 } 4438 4439 /* Read A2 portion of the EEPROM */ 4440 if (length) { 4441 start -= ETH_MODULE_SFF_8436_LEN; 4442 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 0, 4443 start, length, data); 4444 } 4445 return rc; 4446 } 4447 4448 static int bnxt_get_module_status(struct bnxt *bp, struct netlink_ext_ack *extack) 4449 { 4450 if (bp->link_info.module_status <= 4451 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 4452 return 0; 4453 4454 switch (bp->link_info.module_status) { 4455 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 4456 NL_SET_ERR_MSG_MOD(extack, "Transceiver module is powering down"); 4457 break; 4458 case PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED: 4459 NL_SET_ERR_MSG_MOD(extack, "Transceiver module not inserted"); 4460 break; 4461 case PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT: 4462 NL_SET_ERR_MSG_MOD(extack, "Transceiver module disabled due to current fault"); 4463 break; 4464 default: 4465 NL_SET_ERR_MSG_MOD(extack, "Unknown error"); 4466 break; 4467 } 4468 return -EINVAL; 4469 } 4470 4471 static int bnxt_get_module_eeprom_by_page(struct net_device *dev, 4472 const struct ethtool_module_eeprom *page_data, 4473 struct netlink_ext_ack *extack) 4474 { 4475 struct bnxt *bp = netdev_priv(dev); 4476 int rc; 4477 4478 rc = bnxt_get_module_status(bp, extack); 4479 if (rc) 4480 return rc; 4481 4482 if (bp->hwrm_spec_code < 0x10202) { 4483 NL_SET_ERR_MSG_MOD(extack, "Firmware version too old"); 4484 return -EINVAL; 4485 } 4486 4487 if (page_data->bank && !(bp->phy_flags & BNXT_PHY_FL_BANK_SEL)) { 4488 NL_SET_ERR_MSG_MOD(extack, "Firmware not capable for bank selection"); 4489 return -EINVAL; 4490 } 4491 4492 rc = bnxt_read_sfp_module_eeprom_info(bp, page_data->i2c_address << 1, 4493 page_data->page, page_data->bank, 4494 page_data->offset, 4495 page_data->length, 4496 page_data->data); 4497 if (rc) { 4498 NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom read failed"); 4499 return rc; 4500 } 4501 return page_data->length; 4502 } 4503 4504 static int bnxt_nway_reset(struct net_device *dev) 4505 { 4506 int rc = 0; 4507 4508 struct bnxt *bp = netdev_priv(dev); 4509 struct bnxt_link_info *link_info = &bp->link_info; 4510 4511 if (!BNXT_PHY_CFG_ABLE(bp)) 4512 return -EOPNOTSUPP; 4513 4514 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 4515 return -EINVAL; 4516 4517 if (netif_running(dev)) 4518 rc = bnxt_hwrm_set_link_setting(bp, true, false); 4519 4520 return rc; 4521 } 4522 4523 static int bnxt_set_phys_id(struct net_device *dev, 4524 enum ethtool_phys_id_state state) 4525 { 4526 struct hwrm_port_led_cfg_input *req; 4527 struct bnxt *bp = netdev_priv(dev); 4528 struct bnxt_pf_info *pf = &bp->pf; 4529 struct bnxt_led_cfg *led_cfg; 4530 u8 led_state; 4531 __le16 duration; 4532 int rc, i; 4533 4534 if (!bp->num_leds || BNXT_VF(bp)) 4535 return -EOPNOTSUPP; 4536 4537 if (state == ETHTOOL_ID_ACTIVE) { 4538 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 4539 duration = cpu_to_le16(500); 4540 } else if (state == ETHTOOL_ID_INACTIVE) { 4541 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 4542 duration = cpu_to_le16(0); 4543 } else { 4544 return -EINVAL; 4545 } 4546 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG); 4547 if (rc) 4548 return rc; 4549 4550 req->port_id = cpu_to_le16(pf->port_id); 4551 req->num_leds = bp->num_leds; 4552 led_cfg = (struct bnxt_led_cfg *)&req->led0_id; 4553 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 4554 req->enables |= BNXT_LED_DFLT_ENABLES(i); 4555 led_cfg->led_id = bp->leds[i].led_id; 4556 led_cfg->led_state = led_state; 4557 led_cfg->led_blink_on = duration; 4558 led_cfg->led_blink_off = duration; 4559 led_cfg->led_group_id = bp->leds[i].led_group_id; 4560 } 4561 return hwrm_req_send(bp, req); 4562 } 4563 4564 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 4565 { 4566 struct hwrm_selftest_irq_input *req; 4567 int rc; 4568 4569 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ); 4570 if (rc) 4571 return rc; 4572 4573 req->cmpl_ring = cpu_to_le16(cmpl_ring); 4574 return hwrm_req_send(bp, req); 4575 } 4576 4577 static int bnxt_test_irq(struct bnxt *bp) 4578 { 4579 int i; 4580 4581 for (i = 0; i < bp->cp_nr_rings; i++) { 4582 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 4583 int rc; 4584 4585 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 4586 if (rc) 4587 return rc; 4588 } 4589 return 0; 4590 } 4591 4592 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 4593 { 4594 struct hwrm_port_mac_cfg_input *req; 4595 int rc; 4596 4597 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 4598 if (rc) 4599 return rc; 4600 4601 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 4602 if (enable) 4603 req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 4604 else 4605 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 4606 return hwrm_req_send(bp, req); 4607 } 4608 4609 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 4610 { 4611 struct hwrm_port_phy_qcaps_output *resp; 4612 struct hwrm_port_phy_qcaps_input *req; 4613 int rc; 4614 4615 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS); 4616 if (rc) 4617 return rc; 4618 4619 resp = hwrm_req_hold(bp, req); 4620 rc = hwrm_req_send(bp, req); 4621 if (!rc) 4622 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 4623 4624 hwrm_req_drop(bp, req); 4625 return rc; 4626 } 4627 4628 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 4629 struct hwrm_port_phy_cfg_input *req) 4630 { 4631 struct bnxt_link_info *link_info = &bp->link_info; 4632 u16 fw_advertising; 4633 u16 fw_speed; 4634 int rc; 4635 4636 if (!link_info->autoneg || 4637 (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK)) 4638 return 0; 4639 4640 rc = bnxt_query_force_speeds(bp, &fw_advertising); 4641 if (rc) 4642 return rc; 4643 4644 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 4645 if (BNXT_LINK_IS_UP(bp)) 4646 fw_speed = bp->link_info.link_speed; 4647 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 4648 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 4649 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 4650 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 4651 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 4652 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 4653 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 4654 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 4655 4656 req->force_link_speed = cpu_to_le16(fw_speed); 4657 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 4658 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 4659 rc = hwrm_req_send(bp, req); 4660 req->flags = 0; 4661 req->force_link_speed = cpu_to_le16(0); 4662 return rc; 4663 } 4664 4665 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 4666 { 4667 struct hwrm_port_phy_cfg_input *req; 4668 int rc; 4669 4670 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 4671 if (rc) 4672 return rc; 4673 4674 /* prevent bnxt_disable_an_for_lpbk() from consuming the request */ 4675 hwrm_req_hold(bp, req); 4676 4677 if (enable) { 4678 bnxt_disable_an_for_lpbk(bp, req); 4679 if (ext) 4680 req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 4681 else 4682 req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 4683 } else { 4684 req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 4685 } 4686 req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 4687 rc = hwrm_req_send(bp, req); 4688 hwrm_req_drop(bp, req); 4689 return rc; 4690 } 4691 4692 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 4693 u32 raw_cons, int pkt_size) 4694 { 4695 struct bnxt_napi *bnapi = cpr->bnapi; 4696 struct bnxt_rx_ring_info *rxr; 4697 struct bnxt_sw_rx_bd *rx_buf; 4698 struct rx_cmp *rxcmp; 4699 u16 cp_cons, cons; 4700 u8 *data; 4701 u32 len; 4702 int i; 4703 4704 rxr = bnapi->rx_ring; 4705 cp_cons = RING_CMP(raw_cons); 4706 rxcmp = (struct rx_cmp *) 4707 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 4708 cons = rxcmp->rx_cmp_opaque; 4709 rx_buf = &rxr->rx_buf_ring[cons]; 4710 data = rx_buf->data_ptr; 4711 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 4712 if (len != pkt_size) 4713 return -EIO; 4714 i = ETH_ALEN; 4715 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 4716 return -EIO; 4717 i += ETH_ALEN; 4718 for ( ; i < pkt_size; i++) { 4719 if (data[i] != (u8)(i & 0xff)) 4720 return -EIO; 4721 } 4722 return 0; 4723 } 4724 4725 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 4726 int pkt_size) 4727 { 4728 struct tx_cmp *txcmp; 4729 int rc = -EIO; 4730 u32 raw_cons; 4731 u32 cons; 4732 int i; 4733 4734 raw_cons = cpr->cp_raw_cons; 4735 for (i = 0; i < 200; i++) { 4736 cons = RING_CMP(raw_cons); 4737 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 4738 4739 if (!TX_CMP_VALID(txcmp, raw_cons)) { 4740 udelay(5); 4741 continue; 4742 } 4743 4744 /* The valid test of the entry must be done first before 4745 * reading any further. 4746 */ 4747 dma_rmb(); 4748 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP || 4749 TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_V3_CMP) { 4750 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 4751 raw_cons = NEXT_RAW_CMP(raw_cons); 4752 raw_cons = NEXT_RAW_CMP(raw_cons); 4753 break; 4754 } 4755 raw_cons = NEXT_RAW_CMP(raw_cons); 4756 } 4757 cpr->cp_raw_cons = raw_cons; 4758 return rc; 4759 } 4760 4761 static int bnxt_run_loopback(struct bnxt *bp) 4762 { 4763 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 4764 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 4765 struct bnxt_cp_ring_info *cpr; 4766 int pkt_size, i = 0; 4767 struct sk_buff *skb; 4768 dma_addr_t map; 4769 u8 *data; 4770 int rc; 4771 4772 cpr = &rxr->bnapi->cp_ring; 4773 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) 4774 cpr = rxr->rx_cpr; 4775 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh); 4776 skb = netdev_alloc_skb(bp->dev, pkt_size); 4777 if (!skb) 4778 return -ENOMEM; 4779 data = skb_put(skb, pkt_size); 4780 ether_addr_copy(&data[i], bp->dev->dev_addr); 4781 i += ETH_ALEN; 4782 ether_addr_copy(&data[i], bp->dev->dev_addr); 4783 i += ETH_ALEN; 4784 for ( ; i < pkt_size; i++) 4785 data[i] = (u8)(i & 0xff); 4786 4787 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 4788 DMA_TO_DEVICE); 4789 if (dma_mapping_error(&bp->pdev->dev, map)) { 4790 dev_kfree_skb(skb); 4791 return -EIO; 4792 } 4793 bnxt_xmit_bd(bp, txr, map, pkt_size, NULL); 4794 4795 /* Sync BD data before updating doorbell */ 4796 wmb(); 4797 4798 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 4799 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 4800 4801 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE); 4802 dev_kfree_skb(skb); 4803 return rc; 4804 } 4805 4806 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 4807 { 4808 struct hwrm_selftest_exec_output *resp; 4809 struct hwrm_selftest_exec_input *req; 4810 int rc; 4811 4812 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC); 4813 if (rc) 4814 return rc; 4815 4816 hwrm_req_timeout(bp, req, bp->test_info->timeout); 4817 req->flags = test_mask; 4818 4819 resp = hwrm_req_hold(bp, req); 4820 rc = hwrm_req_send(bp, req); 4821 *test_results = resp->test_success; 4822 hwrm_req_drop(bp, req); 4823 return rc; 4824 } 4825 4826 #define BNXT_DRV_TESTS 4 4827 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 4828 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 4829 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 4830 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 4831 4832 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 4833 u64 *buf) 4834 { 4835 struct bnxt *bp = netdev_priv(dev); 4836 bool do_ext_lpbk = false; 4837 bool offline = false; 4838 u8 test_results = 0; 4839 u8 test_mask = 0; 4840 int rc = 0, i; 4841 4842 if (!bp->num_tests || !BNXT_PF(bp)) 4843 return; 4844 4845 if (etest->flags & ETH_TEST_FL_OFFLINE && 4846 bnxt_ulp_registered(bp->edev)) { 4847 etest->flags |= ETH_TEST_FL_FAILED; 4848 netdev_warn(dev, "Offline tests cannot be run with RoCE driver loaded\n"); 4849 return; 4850 } 4851 4852 memset(buf, 0, sizeof(u64) * bp->num_tests); 4853 if (!netif_running(dev)) { 4854 etest->flags |= ETH_TEST_FL_FAILED; 4855 return; 4856 } 4857 4858 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 4859 (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK)) 4860 do_ext_lpbk = true; 4861 4862 if (etest->flags & ETH_TEST_FL_OFFLINE) { 4863 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) { 4864 etest->flags |= ETH_TEST_FL_FAILED; 4865 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n"); 4866 return; 4867 } 4868 offline = true; 4869 } 4870 4871 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 4872 u8 bit_val = 1 << i; 4873 4874 if (!(bp->test_info->offline_mask & bit_val)) 4875 test_mask |= bit_val; 4876 else if (offline) 4877 test_mask |= bit_val; 4878 } 4879 if (!offline) { 4880 bnxt_run_fw_tests(bp, test_mask, &test_results); 4881 } else { 4882 bnxt_close_nic(bp, true, false); 4883 bnxt_run_fw_tests(bp, test_mask, &test_results); 4884 4885 buf[BNXT_MACLPBK_TEST_IDX] = 1; 4886 bnxt_hwrm_mac_loopback(bp, true); 4887 msleep(250); 4888 rc = bnxt_half_open_nic(bp); 4889 if (rc) { 4890 bnxt_hwrm_mac_loopback(bp, false); 4891 etest->flags |= ETH_TEST_FL_FAILED; 4892 return; 4893 } 4894 if (bnxt_run_loopback(bp)) 4895 etest->flags |= ETH_TEST_FL_FAILED; 4896 else 4897 buf[BNXT_MACLPBK_TEST_IDX] = 0; 4898 4899 bnxt_hwrm_mac_loopback(bp, false); 4900 bnxt_hwrm_phy_loopback(bp, true, false); 4901 msleep(1000); 4902 if (bnxt_run_loopback(bp)) { 4903 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 4904 etest->flags |= ETH_TEST_FL_FAILED; 4905 } 4906 if (do_ext_lpbk) { 4907 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 4908 bnxt_hwrm_phy_loopback(bp, true, true); 4909 msleep(1000); 4910 if (bnxt_run_loopback(bp)) { 4911 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 4912 etest->flags |= ETH_TEST_FL_FAILED; 4913 } 4914 } 4915 bnxt_hwrm_phy_loopback(bp, false, false); 4916 bnxt_half_close_nic(bp); 4917 rc = bnxt_open_nic(bp, true, true); 4918 } 4919 if (rc || bnxt_test_irq(bp)) { 4920 buf[BNXT_IRQ_TEST_IDX] = 1; 4921 etest->flags |= ETH_TEST_FL_FAILED; 4922 } 4923 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 4924 u8 bit_val = 1 << i; 4925 4926 if ((test_mask & bit_val) && !(test_results & bit_val)) { 4927 buf[i] = 1; 4928 etest->flags |= ETH_TEST_FL_FAILED; 4929 } 4930 } 4931 } 4932 4933 static int bnxt_reset(struct net_device *dev, u32 *flags) 4934 { 4935 struct bnxt *bp = netdev_priv(dev); 4936 bool reload = false; 4937 u32 req = *flags; 4938 4939 if (!req) 4940 return -EINVAL; 4941 4942 if (!BNXT_PF(bp)) { 4943 netdev_err(dev, "Reset is not supported from a VF\n"); 4944 return -EOPNOTSUPP; 4945 } 4946 4947 if (pci_vfs_assigned(bp->pdev) && 4948 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) { 4949 netdev_err(dev, 4950 "Reset not allowed when VFs are assigned to VMs\n"); 4951 return -EBUSY; 4952 } 4953 4954 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) { 4955 /* This feature is not supported in older firmware versions */ 4956 if (bp->hwrm_spec_code >= 0x10803) { 4957 if (!bnxt_firmware_reset_chip(dev)) { 4958 netdev_info(dev, "Firmware reset request successful.\n"); 4959 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) 4960 reload = true; 4961 *flags &= ~BNXT_FW_RESET_CHIP; 4962 } 4963 } else if (req == BNXT_FW_RESET_CHIP) { 4964 return -EOPNOTSUPP; /* only request, fail hard */ 4965 } 4966 } 4967 4968 if (!BNXT_CHIP_P4_PLUS(bp) && (req & BNXT_FW_RESET_AP)) { 4969 /* This feature is not supported in older firmware versions */ 4970 if (bp->hwrm_spec_code >= 0x10803) { 4971 if (!bnxt_firmware_reset_ap(dev)) { 4972 netdev_info(dev, "Reset application processor successful.\n"); 4973 reload = true; 4974 *flags &= ~BNXT_FW_RESET_AP; 4975 } 4976 } else if (req == BNXT_FW_RESET_AP) { 4977 return -EOPNOTSUPP; /* only request, fail hard */ 4978 } 4979 } 4980 4981 if (reload) 4982 netdev_info(dev, "Reload driver to complete reset\n"); 4983 4984 return 0; 4985 } 4986 4987 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump) 4988 { 4989 struct bnxt *bp = netdev_priv(dev); 4990 4991 if (dump->flag > BNXT_DUMP_CRASH) { 4992 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n"); 4993 return -EINVAL; 4994 } 4995 4996 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) { 4997 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n"); 4998 return -EOPNOTSUPP; 4999 } 5000 5001 bp->dump_flag = dump->flag; 5002 return 0; 5003 } 5004 5005 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 5006 { 5007 struct bnxt *bp = netdev_priv(dev); 5008 5009 if (bp->hwrm_spec_code < 0x10801) 5010 return -EOPNOTSUPP; 5011 5012 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 5013 bp->ver_resp.hwrm_fw_min_8b << 16 | 5014 bp->ver_resp.hwrm_fw_bld_8b << 8 | 5015 bp->ver_resp.hwrm_fw_rsvd_8b; 5016 5017 dump->flag = bp->dump_flag; 5018 dump->len = bnxt_get_coredump_length(bp, bp->dump_flag); 5019 return 0; 5020 } 5021 5022 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 5023 void *buf) 5024 { 5025 struct bnxt *bp = netdev_priv(dev); 5026 5027 if (bp->hwrm_spec_code < 0x10801) 5028 return -EOPNOTSUPP; 5029 5030 memset(buf, 0, dump->len); 5031 5032 dump->flag = bp->dump_flag; 5033 return bnxt_get_coredump(bp, dump->flag, buf, &dump->len); 5034 } 5035 5036 static int bnxt_get_ts_info(struct net_device *dev, 5037 struct kernel_ethtool_ts_info *info) 5038 { 5039 struct bnxt *bp = netdev_priv(dev); 5040 struct bnxt_ptp_cfg *ptp; 5041 5042 ptp = bp->ptp_cfg; 5043 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 5044 SOF_TIMESTAMPING_RX_SOFTWARE | 5045 SOF_TIMESTAMPING_SOFTWARE; 5046 5047 info->phc_index = -1; 5048 if (!ptp) 5049 return 0; 5050 5051 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | 5052 SOF_TIMESTAMPING_RX_HARDWARE | 5053 SOF_TIMESTAMPING_RAW_HARDWARE; 5054 if (ptp->ptp_clock) 5055 info->phc_index = ptp_clock_index(ptp->ptp_clock); 5056 5057 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 5058 5059 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 5060 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 5061 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 5062 5063 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) 5064 info->rx_filters |= (1 << HWTSTAMP_FILTER_ALL); 5065 return 0; 5066 } 5067 5068 void bnxt_ethtool_init(struct bnxt *bp) 5069 { 5070 struct hwrm_selftest_qlist_output *resp; 5071 struct hwrm_selftest_qlist_input *req; 5072 struct bnxt_test_info *test_info; 5073 struct net_device *dev = bp->dev; 5074 int i, rc; 5075 5076 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 5077 bnxt_get_pkgver(dev); 5078 5079 bp->num_tests = 0; 5080 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp)) 5081 return; 5082 5083 test_info = bp->test_info; 5084 if (!test_info) { 5085 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL); 5086 if (!test_info) 5087 return; 5088 bp->test_info = test_info; 5089 } 5090 5091 if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST)) 5092 return; 5093 5094 resp = hwrm_req_hold(bp, req); 5095 rc = hwrm_req_send_silent(bp, req); 5096 if (rc) 5097 goto ethtool_init_exit; 5098 5099 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 5100 if (bp->num_tests > BNXT_MAX_TEST) 5101 bp->num_tests = BNXT_MAX_TEST; 5102 5103 test_info->offline_mask = resp->offline_tests; 5104 test_info->timeout = le16_to_cpu(resp->test_timeout); 5105 if (!test_info->timeout) 5106 test_info->timeout = HWRM_CMD_TIMEOUT; 5107 for (i = 0; i < bp->num_tests; i++) { 5108 char *str = test_info->string[i]; 5109 char *fw_str = resp->test_name[i]; 5110 5111 if (i == BNXT_MACLPBK_TEST_IDX) { 5112 strcpy(str, "Mac loopback test (offline)"); 5113 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 5114 strcpy(str, "Phy loopback test (offline)"); 5115 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 5116 strcpy(str, "Ext loopback test (offline)"); 5117 } else if (i == BNXT_IRQ_TEST_IDX) { 5118 strcpy(str, "Interrupt_test (offline)"); 5119 } else { 5120 snprintf(str, ETH_GSTRING_LEN, "%s test (%s)", 5121 fw_str, test_info->offline_mask & (1 << i) ? 5122 "offline" : "online"); 5123 } 5124 } 5125 5126 ethtool_init_exit: 5127 hwrm_req_drop(bp, req); 5128 } 5129 5130 static void bnxt_get_eth_phy_stats(struct net_device *dev, 5131 struct ethtool_eth_phy_stats *phy_stats) 5132 { 5133 struct bnxt *bp = netdev_priv(dev); 5134 u64 *rx; 5135 5136 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 5137 return; 5138 5139 rx = bp->rx_port_stats_ext.sw_stats; 5140 phy_stats->SymbolErrorDuringCarrier = 5141 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err)); 5142 } 5143 5144 static void bnxt_get_eth_mac_stats(struct net_device *dev, 5145 struct ethtool_eth_mac_stats *mac_stats) 5146 { 5147 struct bnxt *bp = netdev_priv(dev); 5148 u64 *rx, *tx; 5149 5150 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5151 return; 5152 5153 rx = bp->port_stats.sw_stats; 5154 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 5155 5156 mac_stats->FramesReceivedOK = 5157 BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames); 5158 mac_stats->FramesTransmittedOK = 5159 BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames); 5160 mac_stats->FrameCheckSequenceErrors = 5161 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames); 5162 mac_stats->AlignmentErrors = 5163 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames); 5164 mac_stats->OutOfRangeLengthField = 5165 BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames); 5166 } 5167 5168 static void bnxt_get_eth_ctrl_stats(struct net_device *dev, 5169 struct ethtool_eth_ctrl_stats *ctrl_stats) 5170 { 5171 struct bnxt *bp = netdev_priv(dev); 5172 u64 *rx; 5173 5174 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5175 return; 5176 5177 rx = bp->port_stats.sw_stats; 5178 ctrl_stats->MACControlFramesReceived = 5179 BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames); 5180 } 5181 5182 static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = { 5183 { 0, 64 }, 5184 { 65, 127 }, 5185 { 128, 255 }, 5186 { 256, 511 }, 5187 { 512, 1023 }, 5188 { 1024, 1518 }, 5189 { 1519, 2047 }, 5190 { 2048, 4095 }, 5191 { 4096, 9216 }, 5192 { 9217, 16383 }, 5193 {} 5194 }; 5195 5196 static void bnxt_get_rmon_stats(struct net_device *dev, 5197 struct ethtool_rmon_stats *rmon_stats, 5198 const struct ethtool_rmon_hist_range **ranges) 5199 { 5200 struct bnxt *bp = netdev_priv(dev); 5201 u64 *rx, *tx; 5202 5203 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5204 return; 5205 5206 rx = bp->port_stats.sw_stats; 5207 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 5208 5209 rmon_stats->jabbers = 5210 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames); 5211 rmon_stats->oversize_pkts = 5212 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames); 5213 rmon_stats->undersize_pkts = 5214 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames); 5215 5216 rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames); 5217 rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames); 5218 rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames); 5219 rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames); 5220 rmon_stats->hist[4] = 5221 BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames); 5222 rmon_stats->hist[5] = 5223 BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames); 5224 rmon_stats->hist[6] = 5225 BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames); 5226 rmon_stats->hist[7] = 5227 BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames); 5228 rmon_stats->hist[8] = 5229 BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames); 5230 rmon_stats->hist[9] = 5231 BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames); 5232 5233 rmon_stats->hist_tx[0] = 5234 BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames); 5235 rmon_stats->hist_tx[1] = 5236 BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames); 5237 rmon_stats->hist_tx[2] = 5238 BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames); 5239 rmon_stats->hist_tx[3] = 5240 BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames); 5241 rmon_stats->hist_tx[4] = 5242 BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames); 5243 rmon_stats->hist_tx[5] = 5244 BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames); 5245 rmon_stats->hist_tx[6] = 5246 BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames); 5247 rmon_stats->hist_tx[7] = 5248 BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames); 5249 rmon_stats->hist_tx[8] = 5250 BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames); 5251 rmon_stats->hist_tx[9] = 5252 BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames); 5253 5254 *ranges = bnxt_rmon_ranges; 5255 } 5256 5257 static void bnxt_get_ptp_stats(struct net_device *dev, 5258 struct ethtool_ts_stats *ts_stats) 5259 { 5260 struct bnxt *bp = netdev_priv(dev); 5261 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 5262 5263 if (ptp) { 5264 ts_stats->pkts = ptp->stats.ts_pkts; 5265 ts_stats->lost = ptp->stats.ts_lost; 5266 ts_stats->err = atomic64_read(&ptp->stats.ts_err); 5267 } 5268 } 5269 5270 static void bnxt_get_link_ext_stats(struct net_device *dev, 5271 struct ethtool_link_ext_stats *stats) 5272 { 5273 struct bnxt *bp = netdev_priv(dev); 5274 u64 *rx; 5275 5276 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 5277 return; 5278 5279 rx = bp->rx_port_stats_ext.sw_stats; 5280 stats->link_down_events = 5281 *(rx + BNXT_RX_STATS_EXT_OFFSET(link_down_events)); 5282 } 5283 5284 void bnxt_ethtool_free(struct bnxt *bp) 5285 { 5286 kfree(bp->test_info); 5287 bp->test_info = NULL; 5288 } 5289 5290 const struct ethtool_ops bnxt_ethtool_ops = { 5291 .cap_link_lanes_supported = 1, 5292 .cap_rss_ctx_supported = 1, 5293 .rxfh_max_num_contexts = BNXT_MAX_ETH_RSS_CTX + 1, 5294 .rxfh_indir_space = BNXT_MAX_RSS_TABLE_ENTRIES_P5, 5295 .rxfh_priv_size = sizeof(struct bnxt_rss_ctx), 5296 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 5297 ETHTOOL_COALESCE_MAX_FRAMES | 5298 ETHTOOL_COALESCE_USECS_IRQ | 5299 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 5300 ETHTOOL_COALESCE_STATS_BLOCK_USECS | 5301 ETHTOOL_COALESCE_USE_ADAPTIVE_RX | 5302 ETHTOOL_COALESCE_USE_CQE, 5303 .get_link_ksettings = bnxt_get_link_ksettings, 5304 .set_link_ksettings = bnxt_set_link_ksettings, 5305 .get_fec_stats = bnxt_get_fec_stats, 5306 .get_fecparam = bnxt_get_fecparam, 5307 .set_fecparam = bnxt_set_fecparam, 5308 .get_pause_stats = bnxt_get_pause_stats, 5309 .get_pauseparam = bnxt_get_pauseparam, 5310 .set_pauseparam = bnxt_set_pauseparam, 5311 .get_drvinfo = bnxt_get_drvinfo, 5312 .get_regs_len = bnxt_get_regs_len, 5313 .get_regs = bnxt_get_regs, 5314 .get_wol = bnxt_get_wol, 5315 .set_wol = bnxt_set_wol, 5316 .get_coalesce = bnxt_get_coalesce, 5317 .set_coalesce = bnxt_set_coalesce, 5318 .get_msglevel = bnxt_get_msglevel, 5319 .set_msglevel = bnxt_set_msglevel, 5320 .get_sset_count = bnxt_get_sset_count, 5321 .get_strings = bnxt_get_strings, 5322 .get_ethtool_stats = bnxt_get_ethtool_stats, 5323 .set_ringparam = bnxt_set_ringparam, 5324 .get_ringparam = bnxt_get_ringparam, 5325 .get_channels = bnxt_get_channels, 5326 .set_channels = bnxt_set_channels, 5327 .get_rxnfc = bnxt_get_rxnfc, 5328 .set_rxnfc = bnxt_set_rxnfc, 5329 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 5330 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 5331 .get_rxfh = bnxt_get_rxfh, 5332 .set_rxfh = bnxt_set_rxfh, 5333 .create_rxfh_context = bnxt_create_rxfh_context, 5334 .modify_rxfh_context = bnxt_modify_rxfh_context, 5335 .remove_rxfh_context = bnxt_remove_rxfh_context, 5336 .flash_device = bnxt_flash_device, 5337 .get_eeprom_len = bnxt_get_eeprom_len, 5338 .get_eeprom = bnxt_get_eeprom, 5339 .set_eeprom = bnxt_set_eeprom, 5340 .get_link = bnxt_get_link, 5341 .get_link_ext_stats = bnxt_get_link_ext_stats, 5342 .get_eee = bnxt_get_eee, 5343 .set_eee = bnxt_set_eee, 5344 .get_module_info = bnxt_get_module_info, 5345 .get_module_eeprom = bnxt_get_module_eeprom, 5346 .get_module_eeprom_by_page = bnxt_get_module_eeprom_by_page, 5347 .nway_reset = bnxt_nway_reset, 5348 .set_phys_id = bnxt_set_phys_id, 5349 .self_test = bnxt_self_test, 5350 .get_ts_info = bnxt_get_ts_info, 5351 .reset = bnxt_reset, 5352 .set_dump = bnxt_set_dump, 5353 .get_dump_flag = bnxt_get_dump_flag, 5354 .get_dump_data = bnxt_get_dump_data, 5355 .get_eth_phy_stats = bnxt_get_eth_phy_stats, 5356 .get_eth_mac_stats = bnxt_get_eth_mac_stats, 5357 .get_eth_ctrl_stats = bnxt_get_eth_ctrl_stats, 5358 .get_rmon_stats = bnxt_get_rmon_stats, 5359 .get_ts_stats = bnxt_get_ptp_stats, 5360 }; 5361