1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/bitops.h> 12 #include <linux/ctype.h> 13 #include <linux/stringify.h> 14 #include <linux/ethtool.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/linkmode.h> 17 #include <linux/interrupt.h> 18 #include <linux/pci.h> 19 #include <linux/etherdevice.h> 20 #include <linux/crc32.h> 21 #include <linux/firmware.h> 22 #include <linux/utsname.h> 23 #include <linux/time.h> 24 #include <linux/ptp_clock_kernel.h> 25 #include <linux/net_tstamp.h> 26 #include <linux/timecounter.h> 27 #include <net/netlink.h> 28 #include "bnxt_hsi.h" 29 #include "bnxt.h" 30 #include "bnxt_hwrm.h" 31 #include "bnxt_ulp.h" 32 #include "bnxt_xdp.h" 33 #include "bnxt_ptp.h" 34 #include "bnxt_ethtool.h" 35 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 36 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 37 #include "bnxt_coredump.h" 38 39 #define BNXT_NVM_ERR_MSG(dev, extack, msg) \ 40 do { \ 41 if (extack) \ 42 NL_SET_ERR_MSG_MOD(extack, msg); \ 43 netdev_err(dev, "%s\n", msg); \ 44 } while (0) 45 46 static u32 bnxt_get_msglevel(struct net_device *dev) 47 { 48 struct bnxt *bp = netdev_priv(dev); 49 50 return bp->msg_enable; 51 } 52 53 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 54 { 55 struct bnxt *bp = netdev_priv(dev); 56 57 bp->msg_enable = value; 58 } 59 60 static int bnxt_get_coalesce(struct net_device *dev, 61 struct ethtool_coalesce *coal, 62 struct kernel_ethtool_coalesce *kernel_coal, 63 struct netlink_ext_ack *extack) 64 { 65 struct bnxt *bp = netdev_priv(dev); 66 struct bnxt_coal *hw_coal; 67 u16 mult; 68 69 memset(coal, 0, sizeof(*coal)); 70 71 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 72 73 hw_coal = &bp->rx_coal; 74 mult = hw_coal->bufs_per_record; 75 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 76 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 77 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 78 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 79 if (hw_coal->flags & 80 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 81 kernel_coal->use_cqe_mode_rx = true; 82 83 hw_coal = &bp->tx_coal; 84 mult = hw_coal->bufs_per_record; 85 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 86 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 87 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 88 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 89 if (hw_coal->flags & 90 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 91 kernel_coal->use_cqe_mode_tx = true; 92 93 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 94 95 return 0; 96 } 97 98 static int bnxt_set_coalesce(struct net_device *dev, 99 struct ethtool_coalesce *coal, 100 struct kernel_ethtool_coalesce *kernel_coal, 101 struct netlink_ext_ack *extack) 102 { 103 struct bnxt *bp = netdev_priv(dev); 104 bool update_stats = false; 105 struct bnxt_coal *hw_coal; 106 int rc = 0; 107 u16 mult; 108 109 if (coal->use_adaptive_rx_coalesce) { 110 bp->flags |= BNXT_FLAG_DIM; 111 } else { 112 if (bp->flags & BNXT_FLAG_DIM) { 113 bp->flags &= ~(BNXT_FLAG_DIM); 114 goto reset_coalesce; 115 } 116 } 117 118 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) && 119 !(bp->coal_cap.cmpl_params & 120 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)) 121 return -EOPNOTSUPP; 122 123 hw_coal = &bp->rx_coal; 124 mult = hw_coal->bufs_per_record; 125 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 126 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 127 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 128 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 129 hw_coal->flags &= 130 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 131 if (kernel_coal->use_cqe_mode_rx) 132 hw_coal->flags |= 133 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 134 135 hw_coal = &bp->tx_coal; 136 mult = hw_coal->bufs_per_record; 137 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 138 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 139 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 140 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 141 hw_coal->flags &= 142 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 143 if (kernel_coal->use_cqe_mode_tx) 144 hw_coal->flags |= 145 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 146 147 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 148 u32 stats_ticks = coal->stats_block_coalesce_usecs; 149 150 /* Allow 0, which means disable. */ 151 if (stats_ticks) 152 stats_ticks = clamp_t(u32, stats_ticks, 153 BNXT_MIN_STATS_COAL_TICKS, 154 BNXT_MAX_STATS_COAL_TICKS); 155 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 156 bp->stats_coal_ticks = stats_ticks; 157 if (bp->stats_coal_ticks) 158 bp->current_interval = 159 bp->stats_coal_ticks * HZ / 1000000; 160 else 161 bp->current_interval = BNXT_TIMER_INTERVAL; 162 update_stats = true; 163 } 164 165 reset_coalesce: 166 if (test_bit(BNXT_STATE_OPEN, &bp->state)) { 167 if (update_stats) { 168 bnxt_close_nic(bp, true, false); 169 rc = bnxt_open_nic(bp, true, false); 170 } else { 171 rc = bnxt_hwrm_set_coal(bp); 172 } 173 } 174 175 return rc; 176 } 177 178 static const char * const bnxt_ring_rx_stats_str[] = { 179 "rx_ucast_packets", 180 "rx_mcast_packets", 181 "rx_bcast_packets", 182 "rx_discards", 183 "rx_errors", 184 "rx_ucast_bytes", 185 "rx_mcast_bytes", 186 "rx_bcast_bytes", 187 }; 188 189 static const char * const bnxt_ring_tx_stats_str[] = { 190 "tx_ucast_packets", 191 "tx_mcast_packets", 192 "tx_bcast_packets", 193 "tx_errors", 194 "tx_discards", 195 "tx_ucast_bytes", 196 "tx_mcast_bytes", 197 "tx_bcast_bytes", 198 }; 199 200 static const char * const bnxt_ring_tpa_stats_str[] = { 201 "tpa_packets", 202 "tpa_bytes", 203 "tpa_events", 204 "tpa_aborts", 205 }; 206 207 static const char * const bnxt_ring_tpa2_stats_str[] = { 208 "rx_tpa_eligible_pkt", 209 "rx_tpa_eligible_bytes", 210 "rx_tpa_pkt", 211 "rx_tpa_bytes", 212 "rx_tpa_errors", 213 "rx_tpa_events", 214 }; 215 216 static const char * const bnxt_rx_sw_stats_str[] = { 217 "rx_l4_csum_errors", 218 "rx_resets", 219 "rx_buf_errors", 220 }; 221 222 static const char * const bnxt_cmn_sw_stats_str[] = { 223 "missed_irqs", 224 }; 225 226 #define BNXT_RX_STATS_ENTRY(counter) \ 227 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 228 229 #define BNXT_TX_STATS_ENTRY(counter) \ 230 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 231 232 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 233 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 234 235 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 236 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 237 238 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 239 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 240 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 241 242 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 243 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 244 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 245 246 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 247 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 248 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 249 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 250 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 251 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 252 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 253 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 254 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 255 256 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 257 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 258 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 259 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 260 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 261 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 262 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 263 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 264 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 265 266 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 267 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 268 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 269 270 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 271 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 272 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 273 274 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 275 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 276 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 277 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 278 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 279 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 280 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 281 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 282 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 283 284 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 285 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 286 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 287 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 288 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 289 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 290 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 291 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 292 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 293 294 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 295 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 296 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 297 298 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 299 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 300 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 301 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 302 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 303 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 304 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 305 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 306 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 307 308 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 309 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 310 __stringify(counter##_pri##n) } 311 312 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 313 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 314 __stringify(counter##_pri##n) } 315 316 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 317 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 318 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 319 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 320 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 321 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 322 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 323 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 324 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 325 326 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 327 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 328 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 329 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 330 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 331 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 332 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 333 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 334 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 335 336 enum { 337 RX_TOTAL_DISCARDS, 338 TX_TOTAL_DISCARDS, 339 RX_NETPOLL_DISCARDS, 340 }; 341 342 static const char *const bnxt_ring_err_stats_arr[] = { 343 "rx_total_l4_csum_errors", 344 "rx_total_resets", 345 "rx_total_buf_errors", 346 "rx_total_oom_discards", 347 "rx_total_netpoll_discards", 348 "rx_total_ring_discards", 349 "tx_total_resets", 350 "tx_total_ring_discards", 351 "total_missed_irqs", 352 }; 353 354 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str) 355 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str) 356 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str) 357 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str) 358 359 static const struct { 360 long offset; 361 char string[ETH_GSTRING_LEN]; 362 } bnxt_port_stats_arr[] = { 363 BNXT_RX_STATS_ENTRY(rx_64b_frames), 364 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 365 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 366 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 367 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 368 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 369 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 370 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 371 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 372 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 373 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 374 BNXT_RX_STATS_ENTRY(rx_total_frames), 375 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 376 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 377 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 378 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 379 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 380 BNXT_RX_STATS_ENTRY(rx_pause_frames), 381 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 382 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 383 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 384 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 385 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 386 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 387 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 388 BNXT_RX_STATS_ENTRY(rx_good_frames), 389 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 390 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 391 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 392 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 393 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 394 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 395 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 396 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 397 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 398 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 399 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 400 BNXT_RX_STATS_ENTRY(rx_bytes), 401 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 402 BNXT_RX_STATS_ENTRY(rx_runt_frames), 403 BNXT_RX_STATS_ENTRY(rx_stat_discard), 404 BNXT_RX_STATS_ENTRY(rx_stat_err), 405 406 BNXT_TX_STATS_ENTRY(tx_64b_frames), 407 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 408 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 409 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 410 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 411 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 412 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 413 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 414 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 415 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 416 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 417 BNXT_TX_STATS_ENTRY(tx_good_frames), 418 BNXT_TX_STATS_ENTRY(tx_total_frames), 419 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 420 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 421 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 422 BNXT_TX_STATS_ENTRY(tx_pause_frames), 423 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 424 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 425 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 426 BNXT_TX_STATS_ENTRY(tx_err), 427 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 428 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 429 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 430 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 431 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 432 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 433 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 434 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 435 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 436 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 437 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 438 BNXT_TX_STATS_ENTRY(tx_total_collisions), 439 BNXT_TX_STATS_ENTRY(tx_bytes), 440 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 441 BNXT_TX_STATS_ENTRY(tx_stat_discard), 442 BNXT_TX_STATS_ENTRY(tx_stat_error), 443 }; 444 445 static const struct { 446 long offset; 447 char string[ETH_GSTRING_LEN]; 448 } bnxt_port_stats_ext_arr[] = { 449 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 450 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 451 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 452 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 453 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 454 BNXT_RX_STATS_EXT_COS_ENTRIES, 455 BNXT_RX_STATS_EXT_PFC_ENTRIES, 456 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 457 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 458 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 459 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 460 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 461 BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks), 462 BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks), 463 }; 464 465 static const struct { 466 long offset; 467 char string[ETH_GSTRING_LEN]; 468 } bnxt_tx_port_stats_ext_arr[] = { 469 BNXT_TX_STATS_EXT_COS_ENTRIES, 470 BNXT_TX_STATS_EXT_PFC_ENTRIES, 471 }; 472 473 static const struct { 474 long base_off; 475 char string[ETH_GSTRING_LEN]; 476 } bnxt_rx_bytes_pri_arr[] = { 477 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 478 }; 479 480 static const struct { 481 long base_off; 482 char string[ETH_GSTRING_LEN]; 483 } bnxt_rx_pkts_pri_arr[] = { 484 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 485 }; 486 487 static const struct { 488 long base_off; 489 char string[ETH_GSTRING_LEN]; 490 } bnxt_tx_bytes_pri_arr[] = { 491 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 492 }; 493 494 static const struct { 495 long base_off; 496 char string[ETH_GSTRING_LEN]; 497 } bnxt_tx_pkts_pri_arr[] = { 498 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 499 }; 500 501 #define BNXT_NUM_RING_ERR_STATS ARRAY_SIZE(bnxt_ring_err_stats_arr) 502 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 503 #define BNXT_NUM_STATS_PRI \ 504 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 505 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 506 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 507 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 508 509 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 510 { 511 if (BNXT_SUPPORTS_TPA(bp)) { 512 if (bp->max_tpa_v2) { 513 if (BNXT_CHIP_P5_THOR(bp)) 514 return BNXT_NUM_TPA_RING_STATS_P5; 515 return BNXT_NUM_TPA_RING_STATS_P5_SR2; 516 } 517 return BNXT_NUM_TPA_RING_STATS; 518 } 519 return 0; 520 } 521 522 static int bnxt_get_num_ring_stats(struct bnxt *bp) 523 { 524 int rx, tx, cmn; 525 526 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS + 527 bnxt_get_num_tpa_ring_stats(bp); 528 tx = NUM_RING_TX_HW_STATS; 529 cmn = NUM_RING_CMN_SW_STATS; 530 return rx * bp->rx_nr_rings + tx * bp->tx_nr_rings + 531 cmn * bp->cp_nr_rings; 532 } 533 534 static int bnxt_get_num_stats(struct bnxt *bp) 535 { 536 int num_stats = bnxt_get_num_ring_stats(bp); 537 int len; 538 539 num_stats += BNXT_NUM_RING_ERR_STATS; 540 541 if (bp->flags & BNXT_FLAG_PORT_STATS) 542 num_stats += BNXT_NUM_PORT_STATS; 543 544 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 545 len = min_t(int, bp->fw_rx_stats_ext_size, 546 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 547 num_stats += len; 548 len = min_t(int, bp->fw_tx_stats_ext_size, 549 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 550 num_stats += len; 551 if (bp->pri2cos_valid) 552 num_stats += BNXT_NUM_STATS_PRI; 553 } 554 555 return num_stats; 556 } 557 558 static int bnxt_get_sset_count(struct net_device *dev, int sset) 559 { 560 struct bnxt *bp = netdev_priv(dev); 561 562 switch (sset) { 563 case ETH_SS_STATS: 564 return bnxt_get_num_stats(bp); 565 case ETH_SS_TEST: 566 if (!bp->num_tests) 567 return -EOPNOTSUPP; 568 return bp->num_tests; 569 default: 570 return -EOPNOTSUPP; 571 } 572 } 573 574 static bool is_rx_ring(struct bnxt *bp, int ring_num) 575 { 576 return ring_num < bp->rx_nr_rings; 577 } 578 579 static bool is_tx_ring(struct bnxt *bp, int ring_num) 580 { 581 int tx_base = 0; 582 583 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 584 tx_base = bp->rx_nr_rings; 585 586 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings)) 587 return true; 588 return false; 589 } 590 591 static void bnxt_get_ethtool_stats(struct net_device *dev, 592 struct ethtool_stats *stats, u64 *buf) 593 { 594 struct bnxt_total_ring_err_stats ring_err_stats = {0}; 595 struct bnxt *bp = netdev_priv(dev); 596 u64 *curr, *prev; 597 u32 tpa_stats; 598 u32 i, j = 0; 599 600 if (!bp->bnapi) { 601 j += bnxt_get_num_ring_stats(bp); 602 goto skip_ring_stats; 603 } 604 605 tpa_stats = bnxt_get_num_tpa_ring_stats(bp); 606 for (i = 0; i < bp->cp_nr_rings; i++) { 607 struct bnxt_napi *bnapi = bp->bnapi[i]; 608 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 609 u64 *sw_stats = cpr->stats.sw_stats; 610 u64 *sw; 611 int k; 612 613 if (is_rx_ring(bp, i)) { 614 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++) 615 buf[j] = sw_stats[k]; 616 } 617 if (is_tx_ring(bp, i)) { 618 k = NUM_RING_RX_HW_STATS; 619 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 620 j++, k++) 621 buf[j] = sw_stats[k]; 622 } 623 if (!tpa_stats || !is_rx_ring(bp, i)) 624 goto skip_tpa_ring_stats; 625 626 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 627 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS + 628 tpa_stats; j++, k++) 629 buf[j] = sw_stats[k]; 630 631 skip_tpa_ring_stats: 632 sw = (u64 *)&cpr->sw_stats.rx; 633 if (is_rx_ring(bp, i)) { 634 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++) 635 buf[j] = sw[k]; 636 } 637 638 sw = (u64 *)&cpr->sw_stats.cmn; 639 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++) 640 buf[j] = sw[k]; 641 } 642 643 bnxt_get_ring_err_stats(bp, &ring_err_stats); 644 645 skip_ring_stats: 646 curr = &ring_err_stats.rx_total_l4_csum_errors; 647 prev = &bp->ring_err_stats_prev.rx_total_l4_csum_errors; 648 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++, j++, curr++, prev++) 649 buf[j] = *curr + *prev; 650 651 if (bp->flags & BNXT_FLAG_PORT_STATS) { 652 u64 *port_stats = bp->port_stats.sw_stats; 653 654 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) 655 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset); 656 } 657 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 658 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats; 659 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats; 660 u32 len; 661 662 len = min_t(u32, bp->fw_rx_stats_ext_size, 663 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 664 for (i = 0; i < len; i++, j++) { 665 buf[j] = *(rx_port_stats_ext + 666 bnxt_port_stats_ext_arr[i].offset); 667 } 668 len = min_t(u32, bp->fw_tx_stats_ext_size, 669 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 670 for (i = 0; i < len; i++, j++) { 671 buf[j] = *(tx_port_stats_ext + 672 bnxt_tx_port_stats_ext_arr[i].offset); 673 } 674 if (bp->pri2cos_valid) { 675 for (i = 0; i < 8; i++, j++) { 676 long n = bnxt_rx_bytes_pri_arr[i].base_off + 677 bp->pri2cos_idx[i]; 678 679 buf[j] = *(rx_port_stats_ext + n); 680 } 681 for (i = 0; i < 8; i++, j++) { 682 long n = bnxt_rx_pkts_pri_arr[i].base_off + 683 bp->pri2cos_idx[i]; 684 685 buf[j] = *(rx_port_stats_ext + n); 686 } 687 for (i = 0; i < 8; i++, j++) { 688 long n = bnxt_tx_bytes_pri_arr[i].base_off + 689 bp->pri2cos_idx[i]; 690 691 buf[j] = *(tx_port_stats_ext + n); 692 } 693 for (i = 0; i < 8; i++, j++) { 694 long n = bnxt_tx_pkts_pri_arr[i].base_off + 695 bp->pri2cos_idx[i]; 696 697 buf[j] = *(tx_port_stats_ext + n); 698 } 699 } 700 } 701 } 702 703 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 704 { 705 struct bnxt *bp = netdev_priv(dev); 706 static const char * const *str; 707 u32 i, j, num_str; 708 709 switch (stringset) { 710 case ETH_SS_STATS: 711 for (i = 0; i < bp->cp_nr_rings; i++) { 712 if (is_rx_ring(bp, i)) { 713 num_str = NUM_RING_RX_HW_STATS; 714 for (j = 0; j < num_str; j++) { 715 sprintf(buf, "[%d]: %s", i, 716 bnxt_ring_rx_stats_str[j]); 717 buf += ETH_GSTRING_LEN; 718 } 719 } 720 if (is_tx_ring(bp, i)) { 721 num_str = NUM_RING_TX_HW_STATS; 722 for (j = 0; j < num_str; j++) { 723 sprintf(buf, "[%d]: %s", i, 724 bnxt_ring_tx_stats_str[j]); 725 buf += ETH_GSTRING_LEN; 726 } 727 } 728 num_str = bnxt_get_num_tpa_ring_stats(bp); 729 if (!num_str || !is_rx_ring(bp, i)) 730 goto skip_tpa_stats; 731 732 if (bp->max_tpa_v2) 733 str = bnxt_ring_tpa2_stats_str; 734 else 735 str = bnxt_ring_tpa_stats_str; 736 737 for (j = 0; j < num_str; j++) { 738 sprintf(buf, "[%d]: %s", i, str[j]); 739 buf += ETH_GSTRING_LEN; 740 } 741 skip_tpa_stats: 742 if (is_rx_ring(bp, i)) { 743 num_str = NUM_RING_RX_SW_STATS; 744 for (j = 0; j < num_str; j++) { 745 sprintf(buf, "[%d]: %s", i, 746 bnxt_rx_sw_stats_str[j]); 747 buf += ETH_GSTRING_LEN; 748 } 749 } 750 num_str = NUM_RING_CMN_SW_STATS; 751 for (j = 0; j < num_str; j++) { 752 sprintf(buf, "[%d]: %s", i, 753 bnxt_cmn_sw_stats_str[j]); 754 buf += ETH_GSTRING_LEN; 755 } 756 } 757 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++) { 758 strscpy(buf, bnxt_ring_err_stats_arr[i], ETH_GSTRING_LEN); 759 buf += ETH_GSTRING_LEN; 760 } 761 762 if (bp->flags & BNXT_FLAG_PORT_STATS) { 763 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 764 strcpy(buf, bnxt_port_stats_arr[i].string); 765 buf += ETH_GSTRING_LEN; 766 } 767 } 768 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 769 u32 len; 770 771 len = min_t(u32, bp->fw_rx_stats_ext_size, 772 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 773 for (i = 0; i < len; i++) { 774 strcpy(buf, bnxt_port_stats_ext_arr[i].string); 775 buf += ETH_GSTRING_LEN; 776 } 777 len = min_t(u32, bp->fw_tx_stats_ext_size, 778 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 779 for (i = 0; i < len; i++) { 780 strcpy(buf, 781 bnxt_tx_port_stats_ext_arr[i].string); 782 buf += ETH_GSTRING_LEN; 783 } 784 if (bp->pri2cos_valid) { 785 for (i = 0; i < 8; i++) { 786 strcpy(buf, 787 bnxt_rx_bytes_pri_arr[i].string); 788 buf += ETH_GSTRING_LEN; 789 } 790 for (i = 0; i < 8; i++) { 791 strcpy(buf, 792 bnxt_rx_pkts_pri_arr[i].string); 793 buf += ETH_GSTRING_LEN; 794 } 795 for (i = 0; i < 8; i++) { 796 strcpy(buf, 797 bnxt_tx_bytes_pri_arr[i].string); 798 buf += ETH_GSTRING_LEN; 799 } 800 for (i = 0; i < 8; i++) { 801 strcpy(buf, 802 bnxt_tx_pkts_pri_arr[i].string); 803 buf += ETH_GSTRING_LEN; 804 } 805 } 806 } 807 break; 808 case ETH_SS_TEST: 809 if (bp->num_tests) 810 memcpy(buf, bp->test_info->string, 811 bp->num_tests * ETH_GSTRING_LEN); 812 break; 813 default: 814 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 815 stringset); 816 break; 817 } 818 } 819 820 static void bnxt_get_ringparam(struct net_device *dev, 821 struct ethtool_ringparam *ering, 822 struct kernel_ethtool_ringparam *kernel_ering, 823 struct netlink_ext_ack *extack) 824 { 825 struct bnxt *bp = netdev_priv(dev); 826 827 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 828 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA; 829 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 830 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_ENABLED; 831 } else { 832 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 833 ering->rx_jumbo_max_pending = 0; 834 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_DISABLED; 835 } 836 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 837 838 ering->rx_pending = bp->rx_ring_size; 839 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 840 ering->tx_pending = bp->tx_ring_size; 841 } 842 843 static int bnxt_set_ringparam(struct net_device *dev, 844 struct ethtool_ringparam *ering, 845 struct kernel_ethtool_ringparam *kernel_ering, 846 struct netlink_ext_ack *extack) 847 { 848 struct bnxt *bp = netdev_priv(dev); 849 850 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 851 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 852 (ering->tx_pending < BNXT_MIN_TX_DESC_CNT)) 853 return -EINVAL; 854 855 if (netif_running(dev)) 856 bnxt_close_nic(bp, false, false); 857 858 bp->rx_ring_size = ering->rx_pending; 859 bp->tx_ring_size = ering->tx_pending; 860 bnxt_set_ring_params(bp); 861 862 if (netif_running(dev)) 863 return bnxt_open_nic(bp, false, false); 864 865 return 0; 866 } 867 868 static void bnxt_get_channels(struct net_device *dev, 869 struct ethtool_channels *channel) 870 { 871 struct bnxt *bp = netdev_priv(dev); 872 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 873 int max_rx_rings, max_tx_rings, tcs; 874 int max_tx_sch_inputs, tx_grps; 875 876 /* Get the most up-to-date max_tx_sch_inputs. */ 877 if (netif_running(dev) && BNXT_NEW_RM(bp)) 878 bnxt_hwrm_func_resc_qcaps(bp, false); 879 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 880 881 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 882 if (max_tx_sch_inputs) 883 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 884 885 tcs = netdev_get_num_tc(dev); 886 tx_grps = max(tcs, 1); 887 if (bp->tx_nr_rings_xdp) 888 tx_grps++; 889 max_tx_rings /= tx_grps; 890 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 891 892 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 893 max_rx_rings = 0; 894 max_tx_rings = 0; 895 } 896 if (max_tx_sch_inputs) 897 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 898 899 if (tcs > 1) 900 max_tx_rings /= tcs; 901 902 channel->max_rx = max_rx_rings; 903 channel->max_tx = max_tx_rings; 904 channel->max_other = 0; 905 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 906 channel->combined_count = bp->rx_nr_rings; 907 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 908 channel->combined_count--; 909 } else { 910 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 911 channel->rx_count = bp->rx_nr_rings; 912 channel->tx_count = bp->tx_nr_rings_per_tc; 913 } 914 } 915 } 916 917 static int bnxt_set_channels(struct net_device *dev, 918 struct ethtool_channels *channel) 919 { 920 struct bnxt *bp = netdev_priv(dev); 921 int req_tx_rings, req_rx_rings, tcs; 922 bool sh = false; 923 int tx_xdp = 0; 924 int rc = 0; 925 926 if (channel->other_count) 927 return -EINVAL; 928 929 if (!channel->combined_count && 930 (!channel->rx_count || !channel->tx_count)) 931 return -EINVAL; 932 933 if (channel->combined_count && 934 (channel->rx_count || channel->tx_count)) 935 return -EINVAL; 936 937 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 938 channel->tx_count)) 939 return -EINVAL; 940 941 if (channel->combined_count) 942 sh = true; 943 944 tcs = netdev_get_num_tc(dev); 945 946 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 947 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 948 if (bp->tx_nr_rings_xdp) { 949 if (!sh) { 950 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 951 return -EINVAL; 952 } 953 tx_xdp = req_rx_rings; 954 } 955 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 956 if (rc) { 957 netdev_warn(dev, "Unable to allocate the requested rings\n"); 958 return rc; 959 } 960 961 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) != 962 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) && 963 netif_is_rxfh_configured(dev)) { 964 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n"); 965 return -EINVAL; 966 } 967 968 if (netif_running(dev)) { 969 if (BNXT_PF(bp)) { 970 /* TODO CHIMP_FW: Send message to all VF's 971 * before PF unload 972 */ 973 } 974 bnxt_close_nic(bp, true, false); 975 } 976 977 if (sh) { 978 bp->flags |= BNXT_FLAG_SHARED_RINGS; 979 bp->rx_nr_rings = channel->combined_count; 980 bp->tx_nr_rings_per_tc = channel->combined_count; 981 } else { 982 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 983 bp->rx_nr_rings = channel->rx_count; 984 bp->tx_nr_rings_per_tc = channel->tx_count; 985 } 986 bp->tx_nr_rings_xdp = tx_xdp; 987 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 988 if (tcs > 1) 989 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 990 991 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 992 bp->tx_nr_rings + bp->rx_nr_rings; 993 994 /* After changing number of rx channels, update NTUPLE feature. */ 995 netdev_update_features(dev); 996 if (netif_running(dev)) { 997 rc = bnxt_open_nic(bp, true, false); 998 if ((!rc) && BNXT_PF(bp)) { 999 /* TODO CHIMP_FW: Send message to all VF's 1000 * to renable 1001 */ 1002 } 1003 } else { 1004 rc = bnxt_reserve_rings(bp, true); 1005 } 1006 1007 return rc; 1008 } 1009 1010 #ifdef CONFIG_RFS_ACCEL 1011 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 1012 u32 *rule_locs) 1013 { 1014 int i, j = 0; 1015 1016 cmd->data = bp->ntp_fltr_count; 1017 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 1018 struct hlist_head *head; 1019 struct bnxt_ntuple_filter *fltr; 1020 1021 head = &bp->ntp_fltr_hash_tbl[i]; 1022 rcu_read_lock(); 1023 hlist_for_each_entry_rcu(fltr, head, hash) { 1024 if (j == cmd->rule_cnt) 1025 break; 1026 rule_locs[j++] = fltr->sw_id; 1027 } 1028 rcu_read_unlock(); 1029 if (j == cmd->rule_cnt) 1030 break; 1031 } 1032 cmd->rule_cnt = j; 1033 return 0; 1034 } 1035 1036 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1037 { 1038 struct ethtool_rx_flow_spec *fs = 1039 (struct ethtool_rx_flow_spec *)&cmd->fs; 1040 struct bnxt_ntuple_filter *fltr; 1041 struct flow_keys *fkeys; 1042 int i, rc = -EINVAL; 1043 1044 if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR) 1045 return rc; 1046 1047 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 1048 struct hlist_head *head; 1049 1050 head = &bp->ntp_fltr_hash_tbl[i]; 1051 rcu_read_lock(); 1052 hlist_for_each_entry_rcu(fltr, head, hash) { 1053 if (fltr->sw_id == fs->location) 1054 goto fltr_found; 1055 } 1056 rcu_read_unlock(); 1057 } 1058 return rc; 1059 1060 fltr_found: 1061 fkeys = &fltr->fkeys; 1062 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 1063 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1064 fs->flow_type = TCP_V4_FLOW; 1065 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1066 fs->flow_type = UDP_V4_FLOW; 1067 else 1068 goto fltr_err; 1069 1070 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 1071 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0); 1072 1073 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 1074 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0); 1075 1076 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 1077 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0); 1078 1079 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 1080 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0); 1081 } else { 1082 int i; 1083 1084 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1085 fs->flow_type = TCP_V6_FLOW; 1086 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1087 fs->flow_type = UDP_V6_FLOW; 1088 else 1089 goto fltr_err; 1090 1091 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 1092 fkeys->addrs.v6addrs.src; 1093 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 1094 fkeys->addrs.v6addrs.dst; 1095 for (i = 0; i < 4; i++) { 1096 fs->m_u.tcp_ip6_spec.ip6src[i] = cpu_to_be32(~0); 1097 fs->m_u.tcp_ip6_spec.ip6dst[i] = cpu_to_be32(~0); 1098 } 1099 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 1100 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0); 1101 1102 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 1103 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0); 1104 } 1105 1106 fs->ring_cookie = fltr->rxq; 1107 rc = 0; 1108 1109 fltr_err: 1110 rcu_read_unlock(); 1111 1112 return rc; 1113 } 1114 #endif 1115 1116 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1117 { 1118 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1119 return RXH_IP_SRC | RXH_IP_DST; 1120 return 0; 1121 } 1122 1123 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1124 { 1125 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1126 return RXH_IP_SRC | RXH_IP_DST; 1127 return 0; 1128 } 1129 1130 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1131 { 1132 cmd->data = 0; 1133 switch (cmd->flow_type) { 1134 case TCP_V4_FLOW: 1135 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1136 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1137 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1138 cmd->data |= get_ethtool_ipv4_rss(bp); 1139 break; 1140 case UDP_V4_FLOW: 1141 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1142 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1143 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1144 fallthrough; 1145 case SCTP_V4_FLOW: 1146 case AH_ESP_V4_FLOW: 1147 case AH_V4_FLOW: 1148 case ESP_V4_FLOW: 1149 case IPV4_FLOW: 1150 cmd->data |= get_ethtool_ipv4_rss(bp); 1151 break; 1152 1153 case TCP_V6_FLOW: 1154 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1155 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1156 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1157 cmd->data |= get_ethtool_ipv6_rss(bp); 1158 break; 1159 case UDP_V6_FLOW: 1160 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1161 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1162 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1163 fallthrough; 1164 case SCTP_V6_FLOW: 1165 case AH_ESP_V6_FLOW: 1166 case AH_V6_FLOW: 1167 case ESP_V6_FLOW: 1168 case IPV6_FLOW: 1169 cmd->data |= get_ethtool_ipv6_rss(bp); 1170 break; 1171 } 1172 return 0; 1173 } 1174 1175 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1176 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1177 1178 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1179 { 1180 u32 rss_hash_cfg = bp->rss_hash_cfg; 1181 int tuple, rc = 0; 1182 1183 if (cmd->data == RXH_4TUPLE) 1184 tuple = 4; 1185 else if (cmd->data == RXH_2TUPLE) 1186 tuple = 2; 1187 else if (!cmd->data) 1188 tuple = 0; 1189 else 1190 return -EINVAL; 1191 1192 if (cmd->flow_type == TCP_V4_FLOW) { 1193 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1194 if (tuple == 4) 1195 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1196 } else if (cmd->flow_type == UDP_V4_FLOW) { 1197 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1198 return -EINVAL; 1199 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1200 if (tuple == 4) 1201 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1202 } else if (cmd->flow_type == TCP_V6_FLOW) { 1203 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1204 if (tuple == 4) 1205 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1206 } else if (cmd->flow_type == UDP_V6_FLOW) { 1207 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1208 return -EINVAL; 1209 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1210 if (tuple == 4) 1211 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1212 } else if (tuple == 4) { 1213 return -EINVAL; 1214 } 1215 1216 switch (cmd->flow_type) { 1217 case TCP_V4_FLOW: 1218 case UDP_V4_FLOW: 1219 case SCTP_V4_FLOW: 1220 case AH_ESP_V4_FLOW: 1221 case AH_V4_FLOW: 1222 case ESP_V4_FLOW: 1223 case IPV4_FLOW: 1224 if (tuple == 2) 1225 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1226 else if (!tuple) 1227 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1228 break; 1229 1230 case TCP_V6_FLOW: 1231 case UDP_V6_FLOW: 1232 case SCTP_V6_FLOW: 1233 case AH_ESP_V6_FLOW: 1234 case AH_V6_FLOW: 1235 case ESP_V6_FLOW: 1236 case IPV6_FLOW: 1237 if (tuple == 2) 1238 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1239 else if (!tuple) 1240 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1241 break; 1242 } 1243 1244 if (bp->rss_hash_cfg == rss_hash_cfg) 1245 return 0; 1246 1247 if (bp->fw_cap & BNXT_FW_CAP_RSS_HASH_TYPE_DELTA) 1248 bp->rss_hash_delta = bp->rss_hash_cfg ^ rss_hash_cfg; 1249 bp->rss_hash_cfg = rss_hash_cfg; 1250 if (netif_running(bp->dev)) { 1251 bnxt_close_nic(bp, false, false); 1252 rc = bnxt_open_nic(bp, false, false); 1253 } 1254 return rc; 1255 } 1256 1257 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1258 u32 *rule_locs) 1259 { 1260 struct bnxt *bp = netdev_priv(dev); 1261 int rc = 0; 1262 1263 switch (cmd->cmd) { 1264 #ifdef CONFIG_RFS_ACCEL 1265 case ETHTOOL_GRXRINGS: 1266 cmd->data = bp->rx_nr_rings; 1267 break; 1268 1269 case ETHTOOL_GRXCLSRLCNT: 1270 cmd->rule_cnt = bp->ntp_fltr_count; 1271 cmd->data = BNXT_NTP_FLTR_MAX_FLTR; 1272 break; 1273 1274 case ETHTOOL_GRXCLSRLALL: 1275 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1276 break; 1277 1278 case ETHTOOL_GRXCLSRULE: 1279 rc = bnxt_grxclsrule(bp, cmd); 1280 break; 1281 #endif 1282 1283 case ETHTOOL_GRXFH: 1284 rc = bnxt_grxfh(bp, cmd); 1285 break; 1286 1287 default: 1288 rc = -EOPNOTSUPP; 1289 break; 1290 } 1291 1292 return rc; 1293 } 1294 1295 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1296 { 1297 struct bnxt *bp = netdev_priv(dev); 1298 int rc; 1299 1300 switch (cmd->cmd) { 1301 case ETHTOOL_SRXFH: 1302 rc = bnxt_srxfh(bp, cmd); 1303 break; 1304 1305 default: 1306 rc = -EOPNOTSUPP; 1307 break; 1308 } 1309 return rc; 1310 } 1311 1312 u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1313 { 1314 struct bnxt *bp = netdev_priv(dev); 1315 1316 if (bp->flags & BNXT_FLAG_CHIP_P5) 1317 return ALIGN(bp->rx_nr_rings, BNXT_RSS_TABLE_ENTRIES_P5); 1318 return HW_HASH_INDEX_SIZE; 1319 } 1320 1321 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1322 { 1323 return HW_HASH_KEY_SIZE; 1324 } 1325 1326 static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 1327 u8 *hfunc) 1328 { 1329 struct bnxt *bp = netdev_priv(dev); 1330 struct bnxt_vnic_info *vnic; 1331 u32 i, tbl_size; 1332 1333 if (hfunc) 1334 *hfunc = ETH_RSS_HASH_TOP; 1335 1336 if (!bp->vnic_info) 1337 return 0; 1338 1339 vnic = &bp->vnic_info[0]; 1340 if (indir && bp->rss_indir_tbl) { 1341 tbl_size = bnxt_get_rxfh_indir_size(dev); 1342 for (i = 0; i < tbl_size; i++) 1343 indir[i] = bp->rss_indir_tbl[i]; 1344 } 1345 1346 if (key && vnic->rss_hash_key) 1347 memcpy(key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1348 1349 return 0; 1350 } 1351 1352 static int bnxt_set_rxfh(struct net_device *dev, const u32 *indir, 1353 const u8 *key, const u8 hfunc) 1354 { 1355 struct bnxt *bp = netdev_priv(dev); 1356 int rc = 0; 1357 1358 if (hfunc && hfunc != ETH_RSS_HASH_TOP) 1359 return -EOPNOTSUPP; 1360 1361 if (key) 1362 return -EOPNOTSUPP; 1363 1364 if (indir) { 1365 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(dev); 1366 1367 for (i = 0; i < tbl_size; i++) 1368 bp->rss_indir_tbl[i] = indir[i]; 1369 pad = bp->rss_indir_tbl_entries - tbl_size; 1370 if (pad) 1371 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16)); 1372 } 1373 1374 if (netif_running(bp->dev)) { 1375 bnxt_close_nic(bp, false, false); 1376 rc = bnxt_open_nic(bp, false, false); 1377 } 1378 return rc; 1379 } 1380 1381 static void bnxt_get_drvinfo(struct net_device *dev, 1382 struct ethtool_drvinfo *info) 1383 { 1384 struct bnxt *bp = netdev_priv(dev); 1385 1386 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 1387 strscpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 1388 strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1389 info->n_stats = bnxt_get_num_stats(bp); 1390 info->testinfo_len = bp->num_tests; 1391 /* TODO CHIMP_FW: eeprom dump details */ 1392 info->eedump_len = 0; 1393 /* TODO CHIMP FW: reg dump details */ 1394 info->regdump_len = 0; 1395 } 1396 1397 static int bnxt_get_regs_len(struct net_device *dev) 1398 { 1399 struct bnxt *bp = netdev_priv(dev); 1400 int reg_len; 1401 1402 if (!BNXT_PF(bp)) 1403 return -EOPNOTSUPP; 1404 1405 reg_len = BNXT_PXP_REG_LEN; 1406 1407 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED) 1408 reg_len += sizeof(struct pcie_ctx_hw_stats); 1409 1410 return reg_len; 1411 } 1412 1413 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1414 void *_p) 1415 { 1416 struct pcie_ctx_hw_stats *hw_pcie_stats; 1417 struct hwrm_pcie_qstats_input *req; 1418 struct bnxt *bp = netdev_priv(dev); 1419 dma_addr_t hw_pcie_stats_addr; 1420 int rc; 1421 1422 regs->version = 0; 1423 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p); 1424 1425 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 1426 return; 1427 1428 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS)) 1429 return; 1430 1431 hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats), 1432 &hw_pcie_stats_addr); 1433 if (!hw_pcie_stats) { 1434 hwrm_req_drop(bp, req); 1435 return; 1436 } 1437 1438 regs->version = 1; 1439 hwrm_req_hold(bp, req); /* hold on to slice */ 1440 req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats)); 1441 req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr); 1442 rc = hwrm_req_send(bp, req); 1443 if (!rc) { 1444 __le64 *src = (__le64 *)hw_pcie_stats; 1445 u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN); 1446 int i; 1447 1448 for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++) 1449 dst[i] = le64_to_cpu(src[i]); 1450 } 1451 hwrm_req_drop(bp, req); 1452 } 1453 1454 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1455 { 1456 struct bnxt *bp = netdev_priv(dev); 1457 1458 wol->supported = 0; 1459 wol->wolopts = 0; 1460 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1461 if (bp->flags & BNXT_FLAG_WOL_CAP) { 1462 wol->supported = WAKE_MAGIC; 1463 if (bp->wol) 1464 wol->wolopts = WAKE_MAGIC; 1465 } 1466 } 1467 1468 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1469 { 1470 struct bnxt *bp = netdev_priv(dev); 1471 1472 if (wol->wolopts & ~WAKE_MAGIC) 1473 return -EINVAL; 1474 1475 if (wol->wolopts & WAKE_MAGIC) { 1476 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 1477 return -EINVAL; 1478 if (!bp->wol) { 1479 if (bnxt_hwrm_alloc_wol_fltr(bp)) 1480 return -EBUSY; 1481 bp->wol = 1; 1482 } 1483 } else { 1484 if (bp->wol) { 1485 if (bnxt_hwrm_free_wol_fltr(bp)) 1486 return -EBUSY; 1487 bp->wol = 0; 1488 } 1489 } 1490 return 0; 1491 } 1492 1493 u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause) 1494 { 1495 u32 speed_mask = 0; 1496 1497 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 1498 /* set the advertised speeds */ 1499 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 1500 speed_mask |= ADVERTISED_100baseT_Full; 1501 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 1502 speed_mask |= ADVERTISED_1000baseT_Full; 1503 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 1504 speed_mask |= ADVERTISED_2500baseX_Full; 1505 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 1506 speed_mask |= ADVERTISED_10000baseT_Full; 1507 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 1508 speed_mask |= ADVERTISED_40000baseCR4_Full; 1509 1510 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH) 1511 speed_mask |= ADVERTISED_Pause; 1512 else if (fw_pause & BNXT_LINK_PAUSE_TX) 1513 speed_mask |= ADVERTISED_Asym_Pause; 1514 else if (fw_pause & BNXT_LINK_PAUSE_RX) 1515 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; 1516 1517 return speed_mask; 1518 } 1519 1520 enum bnxt_media_type { 1521 BNXT_MEDIA_UNKNOWN = 0, 1522 BNXT_MEDIA_TP, 1523 BNXT_MEDIA_CR, 1524 BNXT_MEDIA_SR, 1525 BNXT_MEDIA_LR_ER_FR, 1526 BNXT_MEDIA_KR, 1527 BNXT_MEDIA_KX, 1528 BNXT_MEDIA_X, 1529 __BNXT_MEDIA_END, 1530 }; 1531 1532 static const enum bnxt_media_type bnxt_phy_types[] = { 1533 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR] = BNXT_MEDIA_CR, 1534 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4] = BNXT_MEDIA_KR, 1535 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR] = BNXT_MEDIA_LR_ER_FR, 1536 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR] = BNXT_MEDIA_SR, 1537 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2] = BNXT_MEDIA_KR, 1538 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX] = BNXT_MEDIA_KX, 1539 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR] = BNXT_MEDIA_KR, 1540 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASET] = BNXT_MEDIA_TP, 1541 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE] = BNXT_MEDIA_TP, 1542 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L] = BNXT_MEDIA_CR, 1543 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S] = BNXT_MEDIA_CR, 1544 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N] = BNXT_MEDIA_CR, 1545 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR] = BNXT_MEDIA_SR, 1546 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4] = BNXT_MEDIA_CR, 1547 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4] = BNXT_MEDIA_SR, 1548 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 1549 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 1550 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10] = BNXT_MEDIA_SR, 1551 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4] = BNXT_MEDIA_CR, 1552 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4] = BNXT_MEDIA_SR, 1553 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 1554 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 1555 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE] = BNXT_MEDIA_SR, 1556 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET] = BNXT_MEDIA_TP, 1557 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX] = BNXT_MEDIA_X, 1558 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX] = BNXT_MEDIA_X, 1559 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4] = BNXT_MEDIA_CR, 1560 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4] = BNXT_MEDIA_SR, 1561 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 1562 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 1563 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR] = BNXT_MEDIA_CR, 1564 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR] = BNXT_MEDIA_SR, 1565 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR] = BNXT_MEDIA_LR_ER_FR, 1566 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER] = BNXT_MEDIA_LR_ER_FR, 1567 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2] = BNXT_MEDIA_CR, 1568 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2] = BNXT_MEDIA_SR, 1569 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2] = BNXT_MEDIA_LR_ER_FR, 1570 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2] = BNXT_MEDIA_LR_ER_FR, 1571 }; 1572 1573 static enum bnxt_media_type 1574 bnxt_get_media(struct bnxt_link_info *link_info) 1575 { 1576 switch (link_info->media_type) { 1577 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP: 1578 return BNXT_MEDIA_TP; 1579 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC: 1580 return BNXT_MEDIA_CR; 1581 default: 1582 if (link_info->phy_type < ARRAY_SIZE(bnxt_phy_types)) 1583 return bnxt_phy_types[link_info->phy_type]; 1584 return BNXT_MEDIA_UNKNOWN; 1585 } 1586 } 1587 1588 enum bnxt_link_speed_indices { 1589 BNXT_LINK_SPEED_UNKNOWN = 0, 1590 BNXT_LINK_SPEED_100MB_IDX, 1591 BNXT_LINK_SPEED_1GB_IDX, 1592 BNXT_LINK_SPEED_10GB_IDX, 1593 BNXT_LINK_SPEED_25GB_IDX, 1594 BNXT_LINK_SPEED_40GB_IDX, 1595 BNXT_LINK_SPEED_50GB_IDX, 1596 BNXT_LINK_SPEED_100GB_IDX, 1597 BNXT_LINK_SPEED_200GB_IDX, 1598 __BNXT_LINK_SPEED_END 1599 }; 1600 1601 static enum bnxt_link_speed_indices bnxt_fw_speed_idx(u16 speed) 1602 { 1603 switch (speed) { 1604 case BNXT_LINK_SPEED_100MB: return BNXT_LINK_SPEED_100MB_IDX; 1605 case BNXT_LINK_SPEED_1GB: return BNXT_LINK_SPEED_1GB_IDX; 1606 case BNXT_LINK_SPEED_10GB: return BNXT_LINK_SPEED_10GB_IDX; 1607 case BNXT_LINK_SPEED_25GB: return BNXT_LINK_SPEED_25GB_IDX; 1608 case BNXT_LINK_SPEED_40GB: return BNXT_LINK_SPEED_40GB_IDX; 1609 case BNXT_LINK_SPEED_50GB: return BNXT_LINK_SPEED_50GB_IDX; 1610 case BNXT_LINK_SPEED_100GB: return BNXT_LINK_SPEED_100GB_IDX; 1611 case BNXT_LINK_SPEED_200GB: return BNXT_LINK_SPEED_200GB_IDX; 1612 default: return BNXT_LINK_SPEED_UNKNOWN; 1613 } 1614 } 1615 1616 static const enum ethtool_link_mode_bit_indices 1617 bnxt_link_modes[__BNXT_LINK_SPEED_END][BNXT_SIG_MODE_MAX][__BNXT_MEDIA_END] = { 1618 [BNXT_LINK_SPEED_100MB_IDX] = { 1619 { 1620 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1621 }, 1622 }, 1623 [BNXT_LINK_SPEED_1GB_IDX] = { 1624 { 1625 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1626 /* historically baseT, but DAC is more correctly baseX */ 1627 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1628 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 1629 [BNXT_MEDIA_X] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1630 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 1631 }, 1632 }, 1633 [BNXT_LINK_SPEED_10GB_IDX] = { 1634 { 1635 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1636 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 1637 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 1638 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 1639 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 1640 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 1641 }, 1642 }, 1643 [BNXT_LINK_SPEED_25GB_IDX] = { 1644 { 1645 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 1646 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 1647 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 1648 }, 1649 }, 1650 [BNXT_LINK_SPEED_40GB_IDX] = { 1651 { 1652 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 1653 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 1654 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 1655 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 1656 }, 1657 }, 1658 [BNXT_LINK_SPEED_50GB_IDX] = { 1659 [BNXT_SIG_MODE_NRZ] = { 1660 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 1661 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 1662 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 1663 }, 1664 [BNXT_SIG_MODE_PAM4] = { 1665 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 1666 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 1667 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 1668 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 1669 }, 1670 }, 1671 [BNXT_LINK_SPEED_100GB_IDX] = { 1672 [BNXT_SIG_MODE_NRZ] = { 1673 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 1674 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 1675 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 1676 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 1677 }, 1678 [BNXT_SIG_MODE_PAM4] = { 1679 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 1680 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 1681 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 1682 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 1683 }, 1684 }, 1685 [BNXT_LINK_SPEED_200GB_IDX] = { 1686 [BNXT_SIG_MODE_PAM4] = { 1687 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT, 1688 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 1689 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 1690 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 1691 }, 1692 }, 1693 }; 1694 1695 #define BNXT_LINK_MODE_UNKNOWN -1 1696 1697 static enum ethtool_link_mode_bit_indices 1698 bnxt_get_link_mode(struct bnxt_link_info *link_info) 1699 { 1700 enum ethtool_link_mode_bit_indices link_mode; 1701 enum bnxt_link_speed_indices speed; 1702 enum bnxt_media_type media; 1703 u8 sig_mode; 1704 1705 if (link_info->phy_link_status != BNXT_LINK_LINK) 1706 return BNXT_LINK_MODE_UNKNOWN; 1707 1708 media = bnxt_get_media(link_info); 1709 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 1710 speed = bnxt_fw_speed_idx(link_info->link_speed); 1711 sig_mode = link_info->active_fec_sig_mode & 1712 PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK; 1713 } else { 1714 speed = bnxt_fw_speed_idx(link_info->req_link_speed); 1715 sig_mode = link_info->req_signal_mode; 1716 } 1717 if (sig_mode >= BNXT_SIG_MODE_MAX) 1718 return BNXT_LINK_MODE_UNKNOWN; 1719 1720 /* Note ETHTOOL_LINK_MODE_10baseT_Half_BIT == 0 is a legal Linux 1721 * link mode, but since no such devices exist, the zeroes in the 1722 * map can be conveniently used to represent unknown link modes. 1723 */ 1724 link_mode = bnxt_link_modes[speed][sig_mode][media]; 1725 if (!link_mode) 1726 return BNXT_LINK_MODE_UNKNOWN; 1727 1728 switch (link_mode) { 1729 case ETHTOOL_LINK_MODE_100baseT_Full_BIT: 1730 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL) 1731 link_mode = ETHTOOL_LINK_MODE_100baseT_Half_BIT; 1732 break; 1733 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT: 1734 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL) 1735 link_mode = ETHTOOL_LINK_MODE_1000baseT_Half_BIT; 1736 break; 1737 default: 1738 break; 1739 } 1740 1741 return link_mode; 1742 } 1743 1744 static void bnxt_get_ethtool_modes(struct bnxt_link_info *link_info, 1745 struct ethtool_link_ksettings *lk_ksettings) 1746 { 1747 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 1748 1749 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) { 1750 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 1751 lk_ksettings->link_modes.supported); 1752 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 1753 lk_ksettings->link_modes.supported); 1754 } 1755 1756 if (link_info->support_auto_speeds || link_info->support_pam4_auto_speeds) 1757 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 1758 lk_ksettings->link_modes.supported); 1759 1760 if (~link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1761 return; 1762 1763 if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_RX) 1764 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 1765 lk_ksettings->link_modes.advertising); 1766 if (hweight8(link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) == 1) 1767 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 1768 lk_ksettings->link_modes.advertising); 1769 if (link_info->lp_pause & BNXT_LINK_PAUSE_RX) 1770 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 1771 lk_ksettings->link_modes.lp_advertising); 1772 if (hweight8(link_info->lp_pause & BNXT_LINK_PAUSE_BOTH) == 1) 1773 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 1774 lk_ksettings->link_modes.lp_advertising); 1775 } 1776 1777 static const u16 bnxt_nrz_speed_masks[] = { 1778 [BNXT_LINK_SPEED_100MB_IDX] = BNXT_LINK_SPEED_MSK_100MB, 1779 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEED_MSK_1GB, 1780 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEED_MSK_10GB, 1781 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEED_MSK_25GB, 1782 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEED_MSK_40GB, 1783 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEED_MSK_50GB, 1784 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEED_MSK_100GB, 1785 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 1786 }; 1787 1788 static const u16 bnxt_pam4_speed_masks[] = { 1789 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_50GB, 1790 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_100GB, 1791 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_200GB, 1792 }; 1793 1794 static enum bnxt_link_speed_indices 1795 bnxt_encoding_speed_idx(u8 sig_mode, u16 speed_msk) 1796 { 1797 const u16 *speeds; 1798 int idx, len; 1799 1800 switch (sig_mode) { 1801 case BNXT_SIG_MODE_NRZ: 1802 speeds = bnxt_nrz_speed_masks; 1803 len = ARRAY_SIZE(bnxt_nrz_speed_masks); 1804 break; 1805 case BNXT_SIG_MODE_PAM4: 1806 speeds = bnxt_pam4_speed_masks; 1807 len = ARRAY_SIZE(bnxt_pam4_speed_masks); 1808 break; 1809 default: 1810 return BNXT_LINK_SPEED_UNKNOWN; 1811 } 1812 1813 for (idx = 0; idx < len; idx++) { 1814 if (speeds[idx] == speed_msk) 1815 return idx; 1816 } 1817 1818 return BNXT_LINK_SPEED_UNKNOWN; 1819 } 1820 1821 #define BNXT_FW_SPEED_MSK_BITS 16 1822 1823 static void 1824 __bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media, 1825 u8 sig_mode, unsigned long *et_mask) 1826 { 1827 enum ethtool_link_mode_bit_indices link_mode; 1828 enum bnxt_link_speed_indices speed; 1829 u8 bit; 1830 1831 for_each_set_bit(bit, &fw_mask, BNXT_FW_SPEED_MSK_BITS) { 1832 speed = bnxt_encoding_speed_idx(sig_mode, 1 << bit); 1833 if (!speed) 1834 continue; 1835 1836 link_mode = bnxt_link_modes[speed][sig_mode][media]; 1837 if (!link_mode) 1838 continue; 1839 1840 linkmode_set_bit(link_mode, et_mask); 1841 } 1842 } 1843 1844 static void 1845 bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media, 1846 u8 sig_mode, unsigned long *et_mask) 1847 { 1848 if (media) { 1849 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, et_mask); 1850 return; 1851 } 1852 1853 /* list speeds for all media if unknown */ 1854 for (media = 1; media < __BNXT_MEDIA_END; media++) 1855 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, et_mask); 1856 } 1857 1858 static void bnxt_update_speed(u32 *delta, bool installed_media, u16 *speeds, 1859 u16 speed_msk, const unsigned long *et_mask, 1860 enum ethtool_link_mode_bit_indices mode) 1861 { 1862 bool mode_desired = linkmode_test_bit(mode, et_mask); 1863 1864 if (!mode) 1865 return; 1866 1867 /* enabled speeds for installed media should override */ 1868 if (installed_media && mode_desired) { 1869 *speeds |= speed_msk; 1870 *delta |= speed_msk; 1871 return; 1872 } 1873 1874 /* many to one mapping, only allow one change per fw_speed bit */ 1875 if (!(*delta & speed_msk) && (mode_desired == !(*speeds & speed_msk))) { 1876 *speeds ^= speed_msk; 1877 *delta |= speed_msk; 1878 } 1879 } 1880 1881 static void bnxt_set_ethtool_speeds(struct bnxt_link_info *link_info, 1882 const unsigned long *et_mask) 1883 { 1884 enum bnxt_media_type media = bnxt_get_media(link_info); 1885 u32 delta_pam4 = 0; 1886 u32 delta_nrz = 0; 1887 int i, m; 1888 1889 for (i = 1; i < __BNXT_LINK_SPEED_END; i++) { 1890 /* accept any legal media from user */ 1891 for (m = 1; m < __BNXT_MEDIA_END; m++) { 1892 bnxt_update_speed(&delta_nrz, m == media, 1893 &link_info->advertising, 1894 bnxt_nrz_speed_masks[i], et_mask, 1895 bnxt_link_modes[i][BNXT_SIG_MODE_NRZ][m]); 1896 bnxt_update_speed(&delta_pam4, m == media, 1897 &link_info->advertising_pam4, 1898 bnxt_pam4_speed_masks[i], et_mask, 1899 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4][m]); 1900 } 1901 } 1902 } 1903 1904 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info, 1905 struct ethtool_link_ksettings *lk_ksettings) 1906 { 1907 u16 fec_cfg = link_info->fec_cfg; 1908 1909 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) { 1910 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1911 lk_ksettings->link_modes.advertising); 1912 return; 1913 } 1914 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 1915 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1916 lk_ksettings->link_modes.advertising); 1917 if (fec_cfg & BNXT_FEC_ENC_RS) 1918 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1919 lk_ksettings->link_modes.advertising); 1920 if (fec_cfg & BNXT_FEC_ENC_LLRS) 1921 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1922 lk_ksettings->link_modes.advertising); 1923 } 1924 1925 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info, 1926 struct ethtool_link_ksettings *lk_ksettings) 1927 { 1928 u16 fec_cfg = link_info->fec_cfg; 1929 1930 if (fec_cfg & BNXT_FEC_NONE) { 1931 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1932 lk_ksettings->link_modes.supported); 1933 return; 1934 } 1935 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP) 1936 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1937 lk_ksettings->link_modes.supported); 1938 if (fec_cfg & BNXT_FEC_ENC_RS_CAP) 1939 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1940 lk_ksettings->link_modes.supported); 1941 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP) 1942 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1943 lk_ksettings->link_modes.supported); 1944 } 1945 1946 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 1947 { 1948 switch (fw_link_speed) { 1949 case BNXT_LINK_SPEED_100MB: 1950 return SPEED_100; 1951 case BNXT_LINK_SPEED_1GB: 1952 return SPEED_1000; 1953 case BNXT_LINK_SPEED_2_5GB: 1954 return SPEED_2500; 1955 case BNXT_LINK_SPEED_10GB: 1956 return SPEED_10000; 1957 case BNXT_LINK_SPEED_20GB: 1958 return SPEED_20000; 1959 case BNXT_LINK_SPEED_25GB: 1960 return SPEED_25000; 1961 case BNXT_LINK_SPEED_40GB: 1962 return SPEED_40000; 1963 case BNXT_LINK_SPEED_50GB: 1964 return SPEED_50000; 1965 case BNXT_LINK_SPEED_100GB: 1966 return SPEED_100000; 1967 case BNXT_LINK_SPEED_200GB: 1968 return SPEED_200000; 1969 default: 1970 return SPEED_UNKNOWN; 1971 } 1972 } 1973 1974 static void bnxt_get_default_speeds(struct ethtool_link_ksettings *lk_ksettings, 1975 struct bnxt_link_info *link_info) 1976 { 1977 struct ethtool_link_settings *base = &lk_ksettings->base; 1978 1979 if (link_info->link_state == BNXT_LINK_STATE_UP) { 1980 base->speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 1981 base->duplex = DUPLEX_HALF; 1982 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 1983 base->duplex = DUPLEX_FULL; 1984 } else if (!link_info->autoneg) { 1985 base->speed = bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 1986 base->duplex = DUPLEX_HALF; 1987 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 1988 base->duplex = DUPLEX_FULL; 1989 } 1990 } 1991 1992 static int bnxt_get_link_ksettings(struct net_device *dev, 1993 struct ethtool_link_ksettings *lk_ksettings) 1994 { 1995 struct ethtool_link_settings *base = &lk_ksettings->base; 1996 enum ethtool_link_mode_bit_indices link_mode; 1997 struct bnxt *bp = netdev_priv(dev); 1998 struct bnxt_link_info *link_info; 1999 enum bnxt_media_type media; 2000 2001 ethtool_link_ksettings_zero_link_mode(lk_ksettings, lp_advertising); 2002 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 2003 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 2004 base->duplex = DUPLEX_UNKNOWN; 2005 base->speed = SPEED_UNKNOWN; 2006 link_info = &bp->link_info; 2007 2008 mutex_lock(&bp->link_lock); 2009 bnxt_get_ethtool_modes(link_info, lk_ksettings); 2010 media = bnxt_get_media(link_info); 2011 bnxt_get_ethtool_speeds(link_info->support_speeds, 2012 media, BNXT_SIG_MODE_NRZ, 2013 lk_ksettings->link_modes.supported); 2014 bnxt_get_ethtool_speeds(link_info->support_pam4_speeds, 2015 media, BNXT_SIG_MODE_PAM4, 2016 lk_ksettings->link_modes.supported); 2017 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings); 2018 link_mode = bnxt_get_link_mode(link_info); 2019 if (link_mode != BNXT_LINK_MODE_UNKNOWN) 2020 ethtool_params_from_link_mode(lk_ksettings, link_mode); 2021 else 2022 bnxt_get_default_speeds(lk_ksettings, link_info); 2023 2024 if (link_info->autoneg) { 2025 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings); 2026 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2027 lk_ksettings->link_modes.advertising); 2028 base->autoneg = AUTONEG_ENABLE; 2029 bnxt_get_ethtool_speeds(link_info->advertising, 2030 media, BNXT_SIG_MODE_NRZ, 2031 lk_ksettings->link_modes.advertising); 2032 bnxt_get_ethtool_speeds(link_info->advertising_pam4, 2033 media, BNXT_SIG_MODE_PAM4, 2034 lk_ksettings->link_modes.advertising); 2035 if (link_info->phy_link_status == BNXT_LINK_LINK) { 2036 bnxt_get_ethtool_speeds(link_info->lp_auto_link_speeds, 2037 media, BNXT_SIG_MODE_NRZ, 2038 lk_ksettings->link_modes.lp_advertising); 2039 bnxt_get_ethtool_speeds(link_info->lp_auto_pam4_link_speeds, 2040 media, BNXT_SIG_MODE_PAM4, 2041 lk_ksettings->link_modes.lp_advertising); 2042 } 2043 } else { 2044 base->autoneg = AUTONEG_DISABLE; 2045 } 2046 2047 base->port = PORT_NONE; 2048 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 2049 base->port = PORT_TP; 2050 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2051 lk_ksettings->link_modes.supported); 2052 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2053 lk_ksettings->link_modes.advertising); 2054 } else { 2055 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 2056 lk_ksettings->link_modes.supported); 2057 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 2058 lk_ksettings->link_modes.advertising); 2059 2060 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC) 2061 base->port = PORT_DA; 2062 else 2063 base->port = PORT_FIBRE; 2064 } 2065 base->phy_address = link_info->phy_addr; 2066 mutex_unlock(&bp->link_lock); 2067 2068 return 0; 2069 } 2070 2071 static int 2072 bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed, u32 lanes) 2073 { 2074 struct bnxt *bp = netdev_priv(dev); 2075 struct bnxt_link_info *link_info = &bp->link_info; 2076 u16 support_pam4_spds = link_info->support_pam4_speeds; 2077 u16 support_spds = link_info->support_speeds; 2078 u8 sig_mode = BNXT_SIG_MODE_NRZ; 2079 u32 lanes_needed = 1; 2080 u16 fw_speed = 0; 2081 2082 switch (ethtool_speed) { 2083 case SPEED_100: 2084 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 2085 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB; 2086 break; 2087 case SPEED_1000: 2088 if (support_spds & BNXT_LINK_SPEED_MSK_1GB) 2089 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 2090 break; 2091 case SPEED_2500: 2092 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 2093 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB; 2094 break; 2095 case SPEED_10000: 2096 if (support_spds & BNXT_LINK_SPEED_MSK_10GB) 2097 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 2098 break; 2099 case SPEED_20000: 2100 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) { 2101 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB; 2102 lanes_needed = 2; 2103 } 2104 break; 2105 case SPEED_25000: 2106 if (support_spds & BNXT_LINK_SPEED_MSK_25GB) 2107 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 2108 break; 2109 case SPEED_40000: 2110 if (support_spds & BNXT_LINK_SPEED_MSK_40GB) { 2111 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 2112 lanes_needed = 4; 2113 } 2114 break; 2115 case SPEED_50000: 2116 if ((support_spds & BNXT_LINK_SPEED_MSK_50GB) && lanes != 1) { 2117 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 2118 lanes_needed = 2; 2119 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) { 2120 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB; 2121 sig_mode = BNXT_SIG_MODE_PAM4; 2122 } 2123 break; 2124 case SPEED_100000: 2125 if ((support_spds & BNXT_LINK_SPEED_MSK_100GB) && 2126 lanes != 2 && lanes != 1) { 2127 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB; 2128 lanes_needed = 4; 2129 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) { 2130 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB; 2131 sig_mode = BNXT_SIG_MODE_PAM4; 2132 lanes_needed = 2; 2133 } 2134 break; 2135 case SPEED_200000: 2136 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) { 2137 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB; 2138 sig_mode = BNXT_SIG_MODE_PAM4; 2139 lanes_needed = 4; 2140 } 2141 break; 2142 } 2143 2144 if (!fw_speed) { 2145 netdev_err(dev, "unsupported speed!\n"); 2146 return -EINVAL; 2147 } 2148 2149 if (lanes && lanes != lanes_needed) { 2150 netdev_err(dev, "unsupported number of lanes for speed\n"); 2151 return -EINVAL; 2152 } 2153 2154 if (link_info->req_link_speed == fw_speed && 2155 link_info->req_signal_mode == sig_mode && 2156 link_info->autoneg == 0) 2157 return -EALREADY; 2158 2159 link_info->req_link_speed = fw_speed; 2160 link_info->req_signal_mode = sig_mode; 2161 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 2162 link_info->autoneg = 0; 2163 link_info->advertising = 0; 2164 link_info->advertising_pam4 = 0; 2165 2166 return 0; 2167 } 2168 2169 u16 bnxt_get_fw_auto_link_speeds(u32 advertising) 2170 { 2171 u16 fw_speed_mask = 0; 2172 2173 /* only support autoneg at speed 100, 1000, and 10000 */ 2174 if (advertising & (ADVERTISED_100baseT_Full | 2175 ADVERTISED_100baseT_Half)) { 2176 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 2177 } 2178 if (advertising & (ADVERTISED_1000baseT_Full | 2179 ADVERTISED_1000baseT_Half)) { 2180 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 2181 } 2182 if (advertising & ADVERTISED_10000baseT_Full) 2183 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 2184 2185 if (advertising & ADVERTISED_40000baseCR4_Full) 2186 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 2187 2188 return fw_speed_mask; 2189 } 2190 2191 static int bnxt_set_link_ksettings(struct net_device *dev, 2192 const struct ethtool_link_ksettings *lk_ksettings) 2193 { 2194 struct bnxt *bp = netdev_priv(dev); 2195 struct bnxt_link_info *link_info = &bp->link_info; 2196 const struct ethtool_link_settings *base = &lk_ksettings->base; 2197 bool set_pause = false; 2198 u32 speed, lanes = 0; 2199 int rc = 0; 2200 2201 if (!BNXT_PHY_CFG_ABLE(bp)) 2202 return -EOPNOTSUPP; 2203 2204 mutex_lock(&bp->link_lock); 2205 if (base->autoneg == AUTONEG_ENABLE) { 2206 bnxt_set_ethtool_speeds(link_info, 2207 lk_ksettings->link_modes.advertising); 2208 link_info->autoneg |= BNXT_AUTONEG_SPEED; 2209 if (!link_info->advertising && !link_info->advertising_pam4) { 2210 link_info->advertising = link_info->support_auto_speeds; 2211 link_info->advertising_pam4 = 2212 link_info->support_pam4_auto_speeds; 2213 } 2214 /* any change to autoneg will cause link change, therefore the 2215 * driver should put back the original pause setting in autoneg 2216 */ 2217 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 2218 set_pause = true; 2219 } else { 2220 u8 phy_type = link_info->phy_type; 2221 2222 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 2223 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 2224 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 2225 netdev_err(dev, "10GBase-T devices must autoneg\n"); 2226 rc = -EINVAL; 2227 goto set_setting_exit; 2228 } 2229 if (base->duplex == DUPLEX_HALF) { 2230 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 2231 rc = -EINVAL; 2232 goto set_setting_exit; 2233 } 2234 speed = base->speed; 2235 lanes = lk_ksettings->lanes; 2236 rc = bnxt_force_link_speed(dev, speed, lanes); 2237 if (rc) { 2238 if (rc == -EALREADY) 2239 rc = 0; 2240 goto set_setting_exit; 2241 } 2242 } 2243 2244 if (netif_running(dev)) 2245 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 2246 2247 set_setting_exit: 2248 mutex_unlock(&bp->link_lock); 2249 return rc; 2250 } 2251 2252 static int bnxt_get_fecparam(struct net_device *dev, 2253 struct ethtool_fecparam *fec) 2254 { 2255 struct bnxt *bp = netdev_priv(dev); 2256 struct bnxt_link_info *link_info; 2257 u8 active_fec; 2258 u16 fec_cfg; 2259 2260 link_info = &bp->link_info; 2261 fec_cfg = link_info->fec_cfg; 2262 active_fec = link_info->active_fec_sig_mode & 2263 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK; 2264 if (fec_cfg & BNXT_FEC_NONE) { 2265 fec->fec = ETHTOOL_FEC_NONE; 2266 fec->active_fec = ETHTOOL_FEC_NONE; 2267 return 0; 2268 } 2269 if (fec_cfg & BNXT_FEC_AUTONEG) 2270 fec->fec |= ETHTOOL_FEC_AUTO; 2271 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 2272 fec->fec |= ETHTOOL_FEC_BASER; 2273 if (fec_cfg & BNXT_FEC_ENC_RS) 2274 fec->fec |= ETHTOOL_FEC_RS; 2275 if (fec_cfg & BNXT_FEC_ENC_LLRS) 2276 fec->fec |= ETHTOOL_FEC_LLRS; 2277 2278 switch (active_fec) { 2279 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE: 2280 fec->active_fec |= ETHTOOL_FEC_BASER; 2281 break; 2282 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE: 2283 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE: 2284 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE: 2285 fec->active_fec |= ETHTOOL_FEC_RS; 2286 break; 2287 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE: 2288 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE: 2289 fec->active_fec |= ETHTOOL_FEC_LLRS; 2290 break; 2291 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE: 2292 fec->active_fec |= ETHTOOL_FEC_OFF; 2293 break; 2294 } 2295 return 0; 2296 } 2297 2298 static void bnxt_get_fec_stats(struct net_device *dev, 2299 struct ethtool_fec_stats *fec_stats) 2300 { 2301 struct bnxt *bp = netdev_priv(dev); 2302 u64 *rx; 2303 2304 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 2305 return; 2306 2307 rx = bp->rx_port_stats_ext.sw_stats; 2308 fec_stats->corrected_bits.total = 2309 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits)); 2310 2311 if (bp->fw_rx_stats_ext_size <= BNXT_RX_STATS_EXT_NUM_LEGACY) 2312 return; 2313 2314 fec_stats->corrected_blocks.total = 2315 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)); 2316 fec_stats->uncorrectable_blocks.total = 2317 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_uncorrectable_blocks)); 2318 } 2319 2320 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info, 2321 u32 fec) 2322 { 2323 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE; 2324 2325 if (fec & ETHTOOL_FEC_BASER) 2326 fw_fec |= BNXT_FEC_BASE_R_ON(link_info); 2327 else if (fec & ETHTOOL_FEC_RS) 2328 fw_fec |= BNXT_FEC_RS_ON(link_info); 2329 else if (fec & ETHTOOL_FEC_LLRS) 2330 fw_fec |= BNXT_FEC_LLRS_ON; 2331 return fw_fec; 2332 } 2333 2334 static int bnxt_set_fecparam(struct net_device *dev, 2335 struct ethtool_fecparam *fecparam) 2336 { 2337 struct hwrm_port_phy_cfg_input *req; 2338 struct bnxt *bp = netdev_priv(dev); 2339 struct bnxt_link_info *link_info; 2340 u32 new_cfg, fec = fecparam->fec; 2341 u16 fec_cfg; 2342 int rc; 2343 2344 link_info = &bp->link_info; 2345 fec_cfg = link_info->fec_cfg; 2346 if (fec_cfg & BNXT_FEC_NONE) 2347 return -EOPNOTSUPP; 2348 2349 if (fec & ETHTOOL_FEC_OFF) { 2350 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE | 2351 BNXT_FEC_ALL_OFF(link_info); 2352 goto apply_fec; 2353 } 2354 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) || 2355 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) || 2356 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) || 2357 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP))) 2358 return -EINVAL; 2359 2360 if (fec & ETHTOOL_FEC_AUTO) { 2361 if (!link_info->autoneg) 2362 return -EINVAL; 2363 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE; 2364 } else { 2365 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec); 2366 } 2367 2368 apply_fec: 2369 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 2370 if (rc) 2371 return rc; 2372 req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 2373 rc = hwrm_req_send(bp, req); 2374 /* update current settings */ 2375 if (!rc) { 2376 mutex_lock(&bp->link_lock); 2377 bnxt_update_link(bp, false); 2378 mutex_unlock(&bp->link_lock); 2379 } 2380 return rc; 2381 } 2382 2383 static void bnxt_get_pauseparam(struct net_device *dev, 2384 struct ethtool_pauseparam *epause) 2385 { 2386 struct bnxt *bp = netdev_priv(dev); 2387 struct bnxt_link_info *link_info = &bp->link_info; 2388 2389 if (BNXT_VF(bp)) 2390 return; 2391 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 2392 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 2393 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 2394 } 2395 2396 static void bnxt_get_pause_stats(struct net_device *dev, 2397 struct ethtool_pause_stats *epstat) 2398 { 2399 struct bnxt *bp = netdev_priv(dev); 2400 u64 *rx, *tx; 2401 2402 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 2403 return; 2404 2405 rx = bp->port_stats.sw_stats; 2406 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 2407 2408 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames); 2409 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames); 2410 } 2411 2412 static int bnxt_set_pauseparam(struct net_device *dev, 2413 struct ethtool_pauseparam *epause) 2414 { 2415 int rc = 0; 2416 struct bnxt *bp = netdev_priv(dev); 2417 struct bnxt_link_info *link_info = &bp->link_info; 2418 2419 if (!BNXT_PHY_CFG_ABLE(bp) || (bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 2420 return -EOPNOTSUPP; 2421 2422 mutex_lock(&bp->link_lock); 2423 if (epause->autoneg) { 2424 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 2425 rc = -EINVAL; 2426 goto pause_exit; 2427 } 2428 2429 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 2430 link_info->req_flow_ctrl = 0; 2431 } else { 2432 /* when transition from auto pause to force pause, 2433 * force a link change 2434 */ 2435 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 2436 link_info->force_link_chng = true; 2437 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 2438 link_info->req_flow_ctrl = 0; 2439 } 2440 if (epause->rx_pause) 2441 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 2442 2443 if (epause->tx_pause) 2444 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 2445 2446 if (netif_running(dev)) 2447 rc = bnxt_hwrm_set_pause(bp); 2448 2449 pause_exit: 2450 mutex_unlock(&bp->link_lock); 2451 return rc; 2452 } 2453 2454 static u32 bnxt_get_link(struct net_device *dev) 2455 { 2456 struct bnxt *bp = netdev_priv(dev); 2457 2458 /* TODO: handle MF, VF, driver close case */ 2459 return BNXT_LINK_IS_UP(bp); 2460 } 2461 2462 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp, 2463 struct hwrm_nvm_get_dev_info_output *nvm_dev_info) 2464 { 2465 struct hwrm_nvm_get_dev_info_output *resp; 2466 struct hwrm_nvm_get_dev_info_input *req; 2467 int rc; 2468 2469 if (BNXT_VF(bp)) 2470 return -EOPNOTSUPP; 2471 2472 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO); 2473 if (rc) 2474 return rc; 2475 2476 resp = hwrm_req_hold(bp, req); 2477 rc = hwrm_req_send(bp, req); 2478 if (!rc) 2479 memcpy(nvm_dev_info, resp, sizeof(*resp)); 2480 hwrm_req_drop(bp, req); 2481 return rc; 2482 } 2483 2484 static void bnxt_print_admin_err(struct bnxt *bp) 2485 { 2486 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 2487 } 2488 2489 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 2490 u16 ext, u16 *index, u32 *item_length, 2491 u32 *data_length); 2492 2493 int bnxt_flash_nvram(struct net_device *dev, u16 dir_type, 2494 u16 dir_ordinal, u16 dir_ext, u16 dir_attr, 2495 u32 dir_item_len, const u8 *data, 2496 size_t data_len) 2497 { 2498 struct bnxt *bp = netdev_priv(dev); 2499 struct hwrm_nvm_write_input *req; 2500 int rc; 2501 2502 rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE); 2503 if (rc) 2504 return rc; 2505 2506 if (data_len && data) { 2507 dma_addr_t dma_handle; 2508 u8 *kmem; 2509 2510 kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle); 2511 if (!kmem) { 2512 hwrm_req_drop(bp, req); 2513 return -ENOMEM; 2514 } 2515 2516 req->dir_data_length = cpu_to_le32(data_len); 2517 2518 memcpy(kmem, data, data_len); 2519 req->host_src_addr = cpu_to_le64(dma_handle); 2520 } 2521 2522 hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout); 2523 req->dir_type = cpu_to_le16(dir_type); 2524 req->dir_ordinal = cpu_to_le16(dir_ordinal); 2525 req->dir_ext = cpu_to_le16(dir_ext); 2526 req->dir_attr = cpu_to_le16(dir_attr); 2527 req->dir_item_length = cpu_to_le32(dir_item_len); 2528 rc = hwrm_req_send(bp, req); 2529 2530 if (rc == -EACCES) 2531 bnxt_print_admin_err(bp); 2532 return rc; 2533 } 2534 2535 int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type, 2536 u8 self_reset, u8 flags) 2537 { 2538 struct bnxt *bp = netdev_priv(dev); 2539 struct hwrm_fw_reset_input *req; 2540 int rc; 2541 2542 if (!bnxt_hwrm_reset_permitted(bp)) { 2543 netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver"); 2544 return -EPERM; 2545 } 2546 2547 rc = hwrm_req_init(bp, req, HWRM_FW_RESET); 2548 if (rc) 2549 return rc; 2550 2551 req->embedded_proc_type = proc_type; 2552 req->selfrst_status = self_reset; 2553 req->flags = flags; 2554 2555 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) { 2556 rc = hwrm_req_send_silent(bp, req); 2557 } else { 2558 rc = hwrm_req_send(bp, req); 2559 if (rc == -EACCES) 2560 bnxt_print_admin_err(bp); 2561 } 2562 return rc; 2563 } 2564 2565 static int bnxt_firmware_reset(struct net_device *dev, 2566 enum bnxt_nvm_directory_type dir_type) 2567 { 2568 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE; 2569 u8 proc_type, flags = 0; 2570 2571 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 2572 /* (e.g. when firmware isn't already running) */ 2573 switch (dir_type) { 2574 case BNX_DIR_TYPE_CHIMP_PATCH: 2575 case BNX_DIR_TYPE_BOOTCODE: 2576 case BNX_DIR_TYPE_BOOTCODE_2: 2577 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 2578 /* Self-reset ChiMP upon next PCIe reset: */ 2579 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 2580 break; 2581 case BNX_DIR_TYPE_APE_FW: 2582 case BNX_DIR_TYPE_APE_PATCH: 2583 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 2584 /* Self-reset APE upon next PCIe reset: */ 2585 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 2586 break; 2587 case BNX_DIR_TYPE_KONG_FW: 2588 case BNX_DIR_TYPE_KONG_PATCH: 2589 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 2590 break; 2591 case BNX_DIR_TYPE_BONO_FW: 2592 case BNX_DIR_TYPE_BONO_PATCH: 2593 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 2594 break; 2595 default: 2596 return -EINVAL; 2597 } 2598 2599 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags); 2600 } 2601 2602 static int bnxt_firmware_reset_chip(struct net_device *dev) 2603 { 2604 struct bnxt *bp = netdev_priv(dev); 2605 u8 flags = 0; 2606 2607 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 2608 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 2609 2610 return bnxt_hwrm_firmware_reset(dev, 2611 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP, 2612 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP, 2613 flags); 2614 } 2615 2616 static int bnxt_firmware_reset_ap(struct net_device *dev) 2617 { 2618 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP, 2619 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE, 2620 0); 2621 } 2622 2623 static int bnxt_flash_firmware(struct net_device *dev, 2624 u16 dir_type, 2625 const u8 *fw_data, 2626 size_t fw_size) 2627 { 2628 int rc = 0; 2629 u16 code_type; 2630 u32 stored_crc; 2631 u32 calculated_crc; 2632 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 2633 2634 switch (dir_type) { 2635 case BNX_DIR_TYPE_BOOTCODE: 2636 case BNX_DIR_TYPE_BOOTCODE_2: 2637 code_type = CODE_BOOT; 2638 break; 2639 case BNX_DIR_TYPE_CHIMP_PATCH: 2640 code_type = CODE_CHIMP_PATCH; 2641 break; 2642 case BNX_DIR_TYPE_APE_FW: 2643 code_type = CODE_MCTP_PASSTHRU; 2644 break; 2645 case BNX_DIR_TYPE_APE_PATCH: 2646 code_type = CODE_APE_PATCH; 2647 break; 2648 case BNX_DIR_TYPE_KONG_FW: 2649 code_type = CODE_KONG_FW; 2650 break; 2651 case BNX_DIR_TYPE_KONG_PATCH: 2652 code_type = CODE_KONG_PATCH; 2653 break; 2654 case BNX_DIR_TYPE_BONO_FW: 2655 code_type = CODE_BONO_FW; 2656 break; 2657 case BNX_DIR_TYPE_BONO_PATCH: 2658 code_type = CODE_BONO_PATCH; 2659 break; 2660 default: 2661 netdev_err(dev, "Unsupported directory entry type: %u\n", 2662 dir_type); 2663 return -EINVAL; 2664 } 2665 if (fw_size < sizeof(struct bnxt_fw_header)) { 2666 netdev_err(dev, "Invalid firmware file size: %u\n", 2667 (unsigned int)fw_size); 2668 return -EINVAL; 2669 } 2670 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 2671 netdev_err(dev, "Invalid firmware signature: %08X\n", 2672 le32_to_cpu(header->signature)); 2673 return -EINVAL; 2674 } 2675 if (header->code_type != code_type) { 2676 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 2677 code_type, header->code_type); 2678 return -EINVAL; 2679 } 2680 if (header->device != DEVICE_CUMULUS_FAMILY) { 2681 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 2682 DEVICE_CUMULUS_FAMILY, header->device); 2683 return -EINVAL; 2684 } 2685 /* Confirm the CRC32 checksum of the file: */ 2686 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 2687 sizeof(stored_crc))); 2688 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 2689 if (calculated_crc != stored_crc) { 2690 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 2691 (unsigned long)stored_crc, 2692 (unsigned long)calculated_crc); 2693 return -EINVAL; 2694 } 2695 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2696 0, 0, 0, fw_data, fw_size); 2697 if (rc == 0) /* Firmware update successful */ 2698 rc = bnxt_firmware_reset(dev, dir_type); 2699 2700 return rc; 2701 } 2702 2703 static int bnxt_flash_microcode(struct net_device *dev, 2704 u16 dir_type, 2705 const u8 *fw_data, 2706 size_t fw_size) 2707 { 2708 struct bnxt_ucode_trailer *trailer; 2709 u32 calculated_crc; 2710 u32 stored_crc; 2711 int rc = 0; 2712 2713 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 2714 netdev_err(dev, "Invalid microcode file size: %u\n", 2715 (unsigned int)fw_size); 2716 return -EINVAL; 2717 } 2718 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 2719 sizeof(*trailer))); 2720 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 2721 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 2722 le32_to_cpu(trailer->sig)); 2723 return -EINVAL; 2724 } 2725 if (le16_to_cpu(trailer->dir_type) != dir_type) { 2726 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 2727 dir_type, le16_to_cpu(trailer->dir_type)); 2728 return -EINVAL; 2729 } 2730 if (le16_to_cpu(trailer->trailer_length) < 2731 sizeof(struct bnxt_ucode_trailer)) { 2732 netdev_err(dev, "Invalid microcode trailer length: %d\n", 2733 le16_to_cpu(trailer->trailer_length)); 2734 return -EINVAL; 2735 } 2736 2737 /* Confirm the CRC32 checksum of the file: */ 2738 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 2739 sizeof(stored_crc))); 2740 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 2741 if (calculated_crc != stored_crc) { 2742 netdev_err(dev, 2743 "CRC32 (%08lX) does not match calculated: %08lX\n", 2744 (unsigned long)stored_crc, 2745 (unsigned long)calculated_crc); 2746 return -EINVAL; 2747 } 2748 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2749 0, 0, 0, fw_data, fw_size); 2750 2751 return rc; 2752 } 2753 2754 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 2755 { 2756 switch (dir_type) { 2757 case BNX_DIR_TYPE_CHIMP_PATCH: 2758 case BNX_DIR_TYPE_BOOTCODE: 2759 case BNX_DIR_TYPE_BOOTCODE_2: 2760 case BNX_DIR_TYPE_APE_FW: 2761 case BNX_DIR_TYPE_APE_PATCH: 2762 case BNX_DIR_TYPE_KONG_FW: 2763 case BNX_DIR_TYPE_KONG_PATCH: 2764 case BNX_DIR_TYPE_BONO_FW: 2765 case BNX_DIR_TYPE_BONO_PATCH: 2766 return true; 2767 } 2768 2769 return false; 2770 } 2771 2772 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 2773 { 2774 switch (dir_type) { 2775 case BNX_DIR_TYPE_AVS: 2776 case BNX_DIR_TYPE_EXP_ROM_MBA: 2777 case BNX_DIR_TYPE_PCIE: 2778 case BNX_DIR_TYPE_TSCF_UCODE: 2779 case BNX_DIR_TYPE_EXT_PHY: 2780 case BNX_DIR_TYPE_CCM: 2781 case BNX_DIR_TYPE_ISCSI_BOOT: 2782 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 2783 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 2784 return true; 2785 } 2786 2787 return false; 2788 } 2789 2790 static bool bnxt_dir_type_is_executable(u16 dir_type) 2791 { 2792 return bnxt_dir_type_is_ape_bin_format(dir_type) || 2793 bnxt_dir_type_is_other_exec_format(dir_type); 2794 } 2795 2796 static int bnxt_flash_firmware_from_file(struct net_device *dev, 2797 u16 dir_type, 2798 const char *filename) 2799 { 2800 const struct firmware *fw; 2801 int rc; 2802 2803 rc = request_firmware(&fw, filename, &dev->dev); 2804 if (rc != 0) { 2805 netdev_err(dev, "Error %d requesting firmware file: %s\n", 2806 rc, filename); 2807 return rc; 2808 } 2809 if (bnxt_dir_type_is_ape_bin_format(dir_type)) 2810 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 2811 else if (bnxt_dir_type_is_other_exec_format(dir_type)) 2812 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 2813 else 2814 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2815 0, 0, 0, fw->data, fw->size); 2816 release_firmware(fw); 2817 return rc; 2818 } 2819 2820 #define MSG_INTEGRITY_ERR "PKG install error : Data integrity on NVM" 2821 #define MSG_INVALID_PKG "PKG install error : Invalid package" 2822 #define MSG_AUTHENTICATION_ERR "PKG install error : Authentication error" 2823 #define MSG_INVALID_DEV "PKG install error : Invalid device" 2824 #define MSG_INTERNAL_ERR "PKG install error : Internal error" 2825 #define MSG_NO_PKG_UPDATE_AREA_ERR "PKG update area not created in nvram" 2826 #define MSG_NO_SPACE_ERR "PKG insufficient update area in nvram" 2827 #define MSG_RESIZE_UPDATE_ERR "Resize UPDATE entry error" 2828 #define MSG_ANTI_ROLLBACK_ERR "HWRM_NVM_INSTALL_UPDATE failure due to Anti-rollback detected" 2829 #define MSG_GENERIC_FAILURE_ERR "HWRM_NVM_INSTALL_UPDATE failure" 2830 2831 static int nvm_update_err_to_stderr(struct net_device *dev, u8 result, 2832 struct netlink_ext_ack *extack) 2833 { 2834 switch (result) { 2835 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER: 2836 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER: 2837 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR: 2838 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR: 2839 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND: 2840 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED: 2841 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTEGRITY_ERR); 2842 return -EINVAL; 2843 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE: 2844 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER: 2845 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE: 2846 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM: 2847 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH: 2848 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST: 2849 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER: 2850 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM: 2851 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM: 2852 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH: 2853 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE: 2854 case NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM: 2855 case NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM: 2856 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_PKG); 2857 return -ENOPKG; 2858 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR: 2859 BNXT_NVM_ERR_MSG(dev, extack, MSG_AUTHENTICATION_ERR); 2860 return -EPERM; 2861 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV: 2862 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID: 2863 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR: 2864 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID: 2865 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM: 2866 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_DEV); 2867 return -EOPNOTSUPP; 2868 default: 2869 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTERNAL_ERR); 2870 return -EIO; 2871 } 2872 } 2873 2874 #define BNXT_PKG_DMA_SIZE 0x40000 2875 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE)) 2876 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST)) 2877 2878 static int bnxt_resize_update_entry(struct net_device *dev, size_t fw_size, 2879 struct netlink_ext_ack *extack) 2880 { 2881 u32 item_len; 2882 int rc; 2883 2884 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 2885 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, NULL, 2886 &item_len, NULL); 2887 if (rc) { 2888 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 2889 return rc; 2890 } 2891 2892 if (fw_size > item_len) { 2893 rc = bnxt_flash_nvram(dev, BNX_DIR_TYPE_UPDATE, 2894 BNX_DIR_ORDINAL_FIRST, 0, 1, 2895 round_up(fw_size, 4096), NULL, 0); 2896 if (rc) { 2897 BNXT_NVM_ERR_MSG(dev, extack, MSG_RESIZE_UPDATE_ERR); 2898 return rc; 2899 } 2900 } 2901 return 0; 2902 } 2903 2904 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw, 2905 u32 install_type, struct netlink_ext_ack *extack) 2906 { 2907 struct hwrm_nvm_install_update_input *install; 2908 struct hwrm_nvm_install_update_output *resp; 2909 struct hwrm_nvm_modify_input *modify; 2910 struct bnxt *bp = netdev_priv(dev); 2911 bool defrag_attempted = false; 2912 dma_addr_t dma_handle; 2913 u8 *kmem = NULL; 2914 u32 modify_len; 2915 u32 item_len; 2916 u8 cmd_err; 2917 u16 index; 2918 int rc; 2919 2920 /* resize before flashing larger image than available space */ 2921 rc = bnxt_resize_update_entry(dev, fw->size, extack); 2922 if (rc) 2923 return rc; 2924 2925 bnxt_hwrm_fw_set_time(bp); 2926 2927 rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY); 2928 if (rc) 2929 return rc; 2930 2931 /* Try allocating a large DMA buffer first. Older fw will 2932 * cause excessive NVRAM erases when using small blocks. 2933 */ 2934 modify_len = roundup_pow_of_two(fw->size); 2935 modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE); 2936 while (1) { 2937 kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle); 2938 if (!kmem && modify_len > PAGE_SIZE) 2939 modify_len /= 2; 2940 else 2941 break; 2942 } 2943 if (!kmem) { 2944 hwrm_req_drop(bp, modify); 2945 return -ENOMEM; 2946 } 2947 2948 rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE); 2949 if (rc) { 2950 hwrm_req_drop(bp, modify); 2951 return rc; 2952 } 2953 2954 hwrm_req_timeout(bp, modify, bp->hwrm_cmd_max_timeout); 2955 hwrm_req_timeout(bp, install, bp->hwrm_cmd_max_timeout); 2956 2957 hwrm_req_hold(bp, modify); 2958 modify->host_src_addr = cpu_to_le64(dma_handle); 2959 2960 resp = hwrm_req_hold(bp, install); 2961 if ((install_type & 0xffff) == 0) 2962 install_type >>= 16; 2963 install->install_type = cpu_to_le32(install_type); 2964 2965 do { 2966 u32 copied = 0, len = modify_len; 2967 2968 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 2969 BNX_DIR_ORDINAL_FIRST, 2970 BNX_DIR_EXT_NONE, 2971 &index, &item_len, NULL); 2972 if (rc) { 2973 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 2974 break; 2975 } 2976 if (fw->size > item_len) { 2977 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_SPACE_ERR); 2978 rc = -EFBIG; 2979 break; 2980 } 2981 2982 modify->dir_idx = cpu_to_le16(index); 2983 2984 if (fw->size > modify_len) 2985 modify->flags = BNXT_NVM_MORE_FLAG; 2986 while (copied < fw->size) { 2987 u32 balance = fw->size - copied; 2988 2989 if (balance <= modify_len) { 2990 len = balance; 2991 if (copied) 2992 modify->flags |= BNXT_NVM_LAST_FLAG; 2993 } 2994 memcpy(kmem, fw->data + copied, len); 2995 modify->len = cpu_to_le32(len); 2996 modify->offset = cpu_to_le32(copied); 2997 rc = hwrm_req_send(bp, modify); 2998 if (rc) 2999 goto pkg_abort; 3000 copied += len; 3001 } 3002 3003 rc = hwrm_req_send_silent(bp, install); 3004 if (!rc) 3005 break; 3006 3007 if (defrag_attempted) { 3008 /* We have tried to defragment already in the previous 3009 * iteration. Return with the result for INSTALL_UPDATE 3010 */ 3011 break; 3012 } 3013 3014 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 3015 3016 switch (cmd_err) { 3017 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK: 3018 BNXT_NVM_ERR_MSG(dev, extack, MSG_ANTI_ROLLBACK_ERR); 3019 rc = -EALREADY; 3020 break; 3021 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR: 3022 install->flags = 3023 cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 3024 3025 rc = hwrm_req_send_silent(bp, install); 3026 if (!rc) 3027 break; 3028 3029 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 3030 3031 if (cmd_err == NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) { 3032 /* FW has cleared NVM area, driver will create 3033 * UPDATE directory and try the flash again 3034 */ 3035 defrag_attempted = true; 3036 install->flags = 0; 3037 rc = bnxt_flash_nvram(bp->dev, 3038 BNX_DIR_TYPE_UPDATE, 3039 BNX_DIR_ORDINAL_FIRST, 3040 0, 0, item_len, NULL, 0); 3041 if (!rc) 3042 break; 3043 } 3044 fallthrough; 3045 default: 3046 BNXT_NVM_ERR_MSG(dev, extack, MSG_GENERIC_FAILURE_ERR); 3047 } 3048 } while (defrag_attempted && !rc); 3049 3050 pkg_abort: 3051 hwrm_req_drop(bp, modify); 3052 hwrm_req_drop(bp, install); 3053 3054 if (resp->result) { 3055 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 3056 (s8)resp->result, (int)resp->problem_item); 3057 rc = nvm_update_err_to_stderr(dev, resp->result, extack); 3058 } 3059 if (rc == -EACCES) 3060 bnxt_print_admin_err(bp); 3061 return rc; 3062 } 3063 3064 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename, 3065 u32 install_type, struct netlink_ext_ack *extack) 3066 { 3067 const struct firmware *fw; 3068 int rc; 3069 3070 rc = request_firmware(&fw, filename, &dev->dev); 3071 if (rc != 0) { 3072 netdev_err(dev, "PKG error %d requesting file: %s\n", 3073 rc, filename); 3074 return rc; 3075 } 3076 3077 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type, extack); 3078 3079 release_firmware(fw); 3080 3081 return rc; 3082 } 3083 3084 static int bnxt_flash_device(struct net_device *dev, 3085 struct ethtool_flash *flash) 3086 { 3087 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 3088 netdev_err(dev, "flashdev not supported from a virtual function\n"); 3089 return -EINVAL; 3090 } 3091 3092 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 3093 flash->region > 0xffff) 3094 return bnxt_flash_package_from_file(dev, flash->data, 3095 flash->region, NULL); 3096 3097 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 3098 } 3099 3100 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 3101 { 3102 struct hwrm_nvm_get_dir_info_output *output; 3103 struct hwrm_nvm_get_dir_info_input *req; 3104 struct bnxt *bp = netdev_priv(dev); 3105 int rc; 3106 3107 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO); 3108 if (rc) 3109 return rc; 3110 3111 output = hwrm_req_hold(bp, req); 3112 rc = hwrm_req_send(bp, req); 3113 if (!rc) { 3114 *entries = le32_to_cpu(output->entries); 3115 *length = le32_to_cpu(output->entry_length); 3116 } 3117 hwrm_req_drop(bp, req); 3118 return rc; 3119 } 3120 3121 static int bnxt_get_eeprom_len(struct net_device *dev) 3122 { 3123 struct bnxt *bp = netdev_priv(dev); 3124 3125 if (BNXT_VF(bp)) 3126 return 0; 3127 3128 /* The -1 return value allows the entire 32-bit range of offsets to be 3129 * passed via the ethtool command-line utility. 3130 */ 3131 return -1; 3132 } 3133 3134 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 3135 { 3136 struct bnxt *bp = netdev_priv(dev); 3137 int rc; 3138 u32 dir_entries; 3139 u32 entry_length; 3140 u8 *buf; 3141 size_t buflen; 3142 dma_addr_t dma_handle; 3143 struct hwrm_nvm_get_dir_entries_input *req; 3144 3145 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 3146 if (rc != 0) 3147 return rc; 3148 3149 if (!dir_entries || !entry_length) 3150 return -EIO; 3151 3152 /* Insert 2 bytes of directory info (count and size of entries) */ 3153 if (len < 2) 3154 return -EINVAL; 3155 3156 *data++ = dir_entries; 3157 *data++ = entry_length; 3158 len -= 2; 3159 memset(data, 0xff, len); 3160 3161 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES); 3162 if (rc) 3163 return rc; 3164 3165 buflen = mul_u32_u32(dir_entries, entry_length); 3166 buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle); 3167 if (!buf) { 3168 hwrm_req_drop(bp, req); 3169 return -ENOMEM; 3170 } 3171 req->host_dest_addr = cpu_to_le64(dma_handle); 3172 3173 hwrm_req_hold(bp, req); /* hold the slice */ 3174 rc = hwrm_req_send(bp, req); 3175 if (rc == 0) 3176 memcpy(data, buf, len > buflen ? buflen : len); 3177 hwrm_req_drop(bp, req); 3178 return rc; 3179 } 3180 3181 int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 3182 u32 length, u8 *data) 3183 { 3184 struct bnxt *bp = netdev_priv(dev); 3185 int rc; 3186 u8 *buf; 3187 dma_addr_t dma_handle; 3188 struct hwrm_nvm_read_input *req; 3189 3190 if (!length) 3191 return -EINVAL; 3192 3193 rc = hwrm_req_init(bp, req, HWRM_NVM_READ); 3194 if (rc) 3195 return rc; 3196 3197 buf = hwrm_req_dma_slice(bp, req, length, &dma_handle); 3198 if (!buf) { 3199 hwrm_req_drop(bp, req); 3200 return -ENOMEM; 3201 } 3202 3203 req->host_dest_addr = cpu_to_le64(dma_handle); 3204 req->dir_idx = cpu_to_le16(index); 3205 req->offset = cpu_to_le32(offset); 3206 req->len = cpu_to_le32(length); 3207 3208 hwrm_req_hold(bp, req); /* hold the slice */ 3209 rc = hwrm_req_send(bp, req); 3210 if (rc == 0) 3211 memcpy(data, buf, length); 3212 hwrm_req_drop(bp, req); 3213 return rc; 3214 } 3215 3216 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 3217 u16 ext, u16 *index, u32 *item_length, 3218 u32 *data_length) 3219 { 3220 struct hwrm_nvm_find_dir_entry_output *output; 3221 struct hwrm_nvm_find_dir_entry_input *req; 3222 struct bnxt *bp = netdev_priv(dev); 3223 int rc; 3224 3225 rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY); 3226 if (rc) 3227 return rc; 3228 3229 req->enables = 0; 3230 req->dir_idx = 0; 3231 req->dir_type = cpu_to_le16(type); 3232 req->dir_ordinal = cpu_to_le16(ordinal); 3233 req->dir_ext = cpu_to_le16(ext); 3234 req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 3235 output = hwrm_req_hold(bp, req); 3236 rc = hwrm_req_send_silent(bp, req); 3237 if (rc == 0) { 3238 if (index) 3239 *index = le16_to_cpu(output->dir_idx); 3240 if (item_length) 3241 *item_length = le32_to_cpu(output->dir_item_length); 3242 if (data_length) 3243 *data_length = le32_to_cpu(output->dir_data_length); 3244 } 3245 hwrm_req_drop(bp, req); 3246 return rc; 3247 } 3248 3249 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 3250 { 3251 char *retval = NULL; 3252 char *p; 3253 char *value; 3254 int field = 0; 3255 3256 if (datalen < 1) 3257 return NULL; 3258 /* null-terminate the log data (removing last '\n'): */ 3259 data[datalen - 1] = 0; 3260 for (p = data; *p != 0; p++) { 3261 field = 0; 3262 retval = NULL; 3263 while (*p != 0 && *p != '\n') { 3264 value = p; 3265 while (*p != 0 && *p != '\t' && *p != '\n') 3266 p++; 3267 if (field == desired_field) 3268 retval = value; 3269 if (*p != '\t') 3270 break; 3271 *p = 0; 3272 field++; 3273 p++; 3274 } 3275 if (*p == 0) 3276 break; 3277 *p = 0; 3278 } 3279 return retval; 3280 } 3281 3282 int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size) 3283 { 3284 struct bnxt *bp = netdev_priv(dev); 3285 u16 index = 0; 3286 char *pkgver; 3287 u32 pkglen; 3288 u8 *pkgbuf; 3289 int rc; 3290 3291 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 3292 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 3293 &index, NULL, &pkglen); 3294 if (rc) 3295 return rc; 3296 3297 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 3298 if (!pkgbuf) { 3299 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 3300 pkglen); 3301 return -ENOMEM; 3302 } 3303 3304 rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf); 3305 if (rc) 3306 goto err; 3307 3308 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 3309 pkglen); 3310 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) 3311 strscpy(ver, pkgver, size); 3312 else 3313 rc = -ENOENT; 3314 3315 err: 3316 kfree(pkgbuf); 3317 3318 return rc; 3319 } 3320 3321 static void bnxt_get_pkgver(struct net_device *dev) 3322 { 3323 struct bnxt *bp = netdev_priv(dev); 3324 char buf[FW_VER_STR_LEN]; 3325 int len; 3326 3327 if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) { 3328 len = strlen(bp->fw_ver_str); 3329 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1, 3330 "/pkg %s", buf); 3331 } 3332 } 3333 3334 static int bnxt_get_eeprom(struct net_device *dev, 3335 struct ethtool_eeprom *eeprom, 3336 u8 *data) 3337 { 3338 u32 index; 3339 u32 offset; 3340 3341 if (eeprom->offset == 0) /* special offset value to get directory */ 3342 return bnxt_get_nvram_directory(dev, eeprom->len, data); 3343 3344 index = eeprom->offset >> 24; 3345 offset = eeprom->offset & 0xffffff; 3346 3347 if (index == 0) { 3348 netdev_err(dev, "unsupported index value: %d\n", index); 3349 return -EINVAL; 3350 } 3351 3352 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 3353 } 3354 3355 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 3356 { 3357 struct hwrm_nvm_erase_dir_entry_input *req; 3358 struct bnxt *bp = netdev_priv(dev); 3359 int rc; 3360 3361 rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY); 3362 if (rc) 3363 return rc; 3364 3365 req->dir_idx = cpu_to_le16(index); 3366 return hwrm_req_send(bp, req); 3367 } 3368 3369 static int bnxt_set_eeprom(struct net_device *dev, 3370 struct ethtool_eeprom *eeprom, 3371 u8 *data) 3372 { 3373 struct bnxt *bp = netdev_priv(dev); 3374 u8 index, dir_op; 3375 u16 type, ext, ordinal, attr; 3376 3377 if (!BNXT_PF(bp)) { 3378 netdev_err(dev, "NVM write not supported from a virtual function\n"); 3379 return -EINVAL; 3380 } 3381 3382 type = eeprom->magic >> 16; 3383 3384 if (type == 0xffff) { /* special value for directory operations */ 3385 index = eeprom->magic & 0xff; 3386 dir_op = eeprom->magic >> 8; 3387 if (index == 0) 3388 return -EINVAL; 3389 switch (dir_op) { 3390 case 0x0e: /* erase */ 3391 if (eeprom->offset != ~eeprom->magic) 3392 return -EINVAL; 3393 return bnxt_erase_nvram_directory(dev, index - 1); 3394 default: 3395 return -EINVAL; 3396 } 3397 } 3398 3399 /* Create or re-write an NVM item: */ 3400 if (bnxt_dir_type_is_executable(type)) 3401 return -EOPNOTSUPP; 3402 ext = eeprom->magic & 0xffff; 3403 ordinal = eeprom->offset >> 16; 3404 attr = eeprom->offset & 0xffff; 3405 3406 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data, 3407 eeprom->len); 3408 } 3409 3410 static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata) 3411 { 3412 struct bnxt *bp = netdev_priv(dev); 3413 struct ethtool_eee *eee = &bp->eee; 3414 struct bnxt_link_info *link_info = &bp->link_info; 3415 u32 advertising; 3416 int rc = 0; 3417 3418 if (!BNXT_PHY_CFG_ABLE(bp)) 3419 return -EOPNOTSUPP; 3420 3421 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 3422 return -EOPNOTSUPP; 3423 3424 mutex_lock(&bp->link_lock); 3425 advertising = _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 3426 if (!edata->eee_enabled) 3427 goto eee_ok; 3428 3429 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 3430 netdev_warn(dev, "EEE requires autoneg\n"); 3431 rc = -EINVAL; 3432 goto eee_exit; 3433 } 3434 if (edata->tx_lpi_enabled) { 3435 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 3436 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 3437 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 3438 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 3439 rc = -EINVAL; 3440 goto eee_exit; 3441 } else if (!bp->lpi_tmr_hi) { 3442 edata->tx_lpi_timer = eee->tx_lpi_timer; 3443 } 3444 } 3445 if (!edata->advertised) { 3446 edata->advertised = advertising & eee->supported; 3447 } else if (edata->advertised & ~advertising) { 3448 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n", 3449 edata->advertised, advertising); 3450 rc = -EINVAL; 3451 goto eee_exit; 3452 } 3453 3454 eee->advertised = edata->advertised; 3455 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 3456 eee->tx_lpi_timer = edata->tx_lpi_timer; 3457 eee_ok: 3458 eee->eee_enabled = edata->eee_enabled; 3459 3460 if (netif_running(dev)) 3461 rc = bnxt_hwrm_set_link_setting(bp, false, true); 3462 3463 eee_exit: 3464 mutex_unlock(&bp->link_lock); 3465 return rc; 3466 } 3467 3468 static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata) 3469 { 3470 struct bnxt *bp = netdev_priv(dev); 3471 3472 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 3473 return -EOPNOTSUPP; 3474 3475 *edata = bp->eee; 3476 if (!bp->eee.eee_enabled) { 3477 /* Preserve tx_lpi_timer so that the last value will be used 3478 * by default when it is re-enabled. 3479 */ 3480 edata->advertised = 0; 3481 edata->tx_lpi_enabled = 0; 3482 } 3483 3484 if (!bp->eee.eee_active) 3485 edata->lp_advertised = 0; 3486 3487 return 0; 3488 } 3489 3490 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 3491 u16 page_number, u8 bank, 3492 u16 start_addr, u16 data_length, 3493 u8 *buf) 3494 { 3495 struct hwrm_port_phy_i2c_read_output *output; 3496 struct hwrm_port_phy_i2c_read_input *req; 3497 int rc, byte_offset = 0; 3498 3499 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ); 3500 if (rc) 3501 return rc; 3502 3503 output = hwrm_req_hold(bp, req); 3504 req->i2c_slave_addr = i2c_addr; 3505 req->page_number = cpu_to_le16(page_number); 3506 req->port_id = cpu_to_le16(bp->pf.port_id); 3507 do { 3508 u16 xfer_size; 3509 3510 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 3511 data_length -= xfer_size; 3512 req->page_offset = cpu_to_le16(start_addr + byte_offset); 3513 req->data_length = xfer_size; 3514 req->enables = 3515 cpu_to_le32((start_addr + byte_offset ? 3516 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 3517 0) | 3518 (bank ? 3519 PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER : 3520 0)); 3521 rc = hwrm_req_send(bp, req); 3522 if (!rc) 3523 memcpy(buf + byte_offset, output->data, xfer_size); 3524 byte_offset += xfer_size; 3525 } while (!rc && data_length > 0); 3526 hwrm_req_drop(bp, req); 3527 3528 return rc; 3529 } 3530 3531 static int bnxt_get_module_info(struct net_device *dev, 3532 struct ethtool_modinfo *modinfo) 3533 { 3534 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 3535 struct bnxt *bp = netdev_priv(dev); 3536 int rc; 3537 3538 /* No point in going further if phy status indicates 3539 * module is not inserted or if it is powered down or 3540 * if it is of type 10GBase-T 3541 */ 3542 if (bp->link_info.module_status > 3543 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 3544 return -EOPNOTSUPP; 3545 3546 /* This feature is not supported in older firmware versions */ 3547 if (bp->hwrm_spec_code < 0x10202) 3548 return -EOPNOTSUPP; 3549 3550 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 0, 3551 SFF_DIAG_SUPPORT_OFFSET + 1, 3552 data); 3553 if (!rc) { 3554 u8 module_id = data[0]; 3555 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 3556 3557 switch (module_id) { 3558 case SFF_MODULE_ID_SFP: 3559 modinfo->type = ETH_MODULE_SFF_8472; 3560 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 3561 if (!diag_supported) 3562 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 3563 break; 3564 case SFF_MODULE_ID_QSFP: 3565 case SFF_MODULE_ID_QSFP_PLUS: 3566 modinfo->type = ETH_MODULE_SFF_8436; 3567 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 3568 break; 3569 case SFF_MODULE_ID_QSFP28: 3570 modinfo->type = ETH_MODULE_SFF_8636; 3571 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 3572 break; 3573 default: 3574 rc = -EOPNOTSUPP; 3575 break; 3576 } 3577 } 3578 return rc; 3579 } 3580 3581 static int bnxt_get_module_eeprom(struct net_device *dev, 3582 struct ethtool_eeprom *eeprom, 3583 u8 *data) 3584 { 3585 struct bnxt *bp = netdev_priv(dev); 3586 u16 start = eeprom->offset, length = eeprom->len; 3587 int rc = 0; 3588 3589 memset(data, 0, eeprom->len); 3590 3591 /* Read A0 portion of the EEPROM */ 3592 if (start < ETH_MODULE_SFF_8436_LEN) { 3593 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 3594 length = ETH_MODULE_SFF_8436_LEN - start; 3595 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 3596 start, length, data); 3597 if (rc) 3598 return rc; 3599 start += length; 3600 data += length; 3601 length = eeprom->len - length; 3602 } 3603 3604 /* Read A2 portion of the EEPROM */ 3605 if (length) { 3606 start -= ETH_MODULE_SFF_8436_LEN; 3607 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 0, 3608 start, length, data); 3609 } 3610 return rc; 3611 } 3612 3613 static int bnxt_get_module_status(struct bnxt *bp, struct netlink_ext_ack *extack) 3614 { 3615 if (bp->link_info.module_status <= 3616 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 3617 return 0; 3618 3619 switch (bp->link_info.module_status) { 3620 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 3621 NL_SET_ERR_MSG_MOD(extack, "Transceiver module is powering down"); 3622 break; 3623 case PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED: 3624 NL_SET_ERR_MSG_MOD(extack, "Transceiver module not inserted"); 3625 break; 3626 case PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT: 3627 NL_SET_ERR_MSG_MOD(extack, "Transceiver module disabled due to current fault"); 3628 break; 3629 default: 3630 NL_SET_ERR_MSG_MOD(extack, "Unknown error"); 3631 break; 3632 } 3633 return -EINVAL; 3634 } 3635 3636 static int bnxt_get_module_eeprom_by_page(struct net_device *dev, 3637 const struct ethtool_module_eeprom *page_data, 3638 struct netlink_ext_ack *extack) 3639 { 3640 struct bnxt *bp = netdev_priv(dev); 3641 int rc; 3642 3643 rc = bnxt_get_module_status(bp, extack); 3644 if (rc) 3645 return rc; 3646 3647 if (bp->hwrm_spec_code < 0x10202) { 3648 NL_SET_ERR_MSG_MOD(extack, "Firmware version too old"); 3649 return -EINVAL; 3650 } 3651 3652 if (page_data->bank && !(bp->phy_flags & BNXT_PHY_FL_BANK_SEL)) { 3653 NL_SET_ERR_MSG_MOD(extack, "Firmware not capable for bank selection"); 3654 return -EINVAL; 3655 } 3656 3657 rc = bnxt_read_sfp_module_eeprom_info(bp, page_data->i2c_address << 1, 3658 page_data->page, page_data->bank, 3659 page_data->offset, 3660 page_data->length, 3661 page_data->data); 3662 if (rc) { 3663 NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom read failed"); 3664 return rc; 3665 } 3666 return page_data->length; 3667 } 3668 3669 static int bnxt_nway_reset(struct net_device *dev) 3670 { 3671 int rc = 0; 3672 3673 struct bnxt *bp = netdev_priv(dev); 3674 struct bnxt_link_info *link_info = &bp->link_info; 3675 3676 if (!BNXT_PHY_CFG_ABLE(bp)) 3677 return -EOPNOTSUPP; 3678 3679 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 3680 return -EINVAL; 3681 3682 if (netif_running(dev)) 3683 rc = bnxt_hwrm_set_link_setting(bp, true, false); 3684 3685 return rc; 3686 } 3687 3688 static int bnxt_set_phys_id(struct net_device *dev, 3689 enum ethtool_phys_id_state state) 3690 { 3691 struct hwrm_port_led_cfg_input *req; 3692 struct bnxt *bp = netdev_priv(dev); 3693 struct bnxt_pf_info *pf = &bp->pf; 3694 struct bnxt_led_cfg *led_cfg; 3695 u8 led_state; 3696 __le16 duration; 3697 int rc, i; 3698 3699 if (!bp->num_leds || BNXT_VF(bp)) 3700 return -EOPNOTSUPP; 3701 3702 if (state == ETHTOOL_ID_ACTIVE) { 3703 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 3704 duration = cpu_to_le16(500); 3705 } else if (state == ETHTOOL_ID_INACTIVE) { 3706 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 3707 duration = cpu_to_le16(0); 3708 } else { 3709 return -EINVAL; 3710 } 3711 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG); 3712 if (rc) 3713 return rc; 3714 3715 req->port_id = cpu_to_le16(pf->port_id); 3716 req->num_leds = bp->num_leds; 3717 led_cfg = (struct bnxt_led_cfg *)&req->led0_id; 3718 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 3719 req->enables |= BNXT_LED_DFLT_ENABLES(i); 3720 led_cfg->led_id = bp->leds[i].led_id; 3721 led_cfg->led_state = led_state; 3722 led_cfg->led_blink_on = duration; 3723 led_cfg->led_blink_off = duration; 3724 led_cfg->led_group_id = bp->leds[i].led_group_id; 3725 } 3726 return hwrm_req_send(bp, req); 3727 } 3728 3729 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 3730 { 3731 struct hwrm_selftest_irq_input *req; 3732 int rc; 3733 3734 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ); 3735 if (rc) 3736 return rc; 3737 3738 req->cmpl_ring = cpu_to_le16(cmpl_ring); 3739 return hwrm_req_send(bp, req); 3740 } 3741 3742 static int bnxt_test_irq(struct bnxt *bp) 3743 { 3744 int i; 3745 3746 for (i = 0; i < bp->cp_nr_rings; i++) { 3747 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 3748 int rc; 3749 3750 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 3751 if (rc) 3752 return rc; 3753 } 3754 return 0; 3755 } 3756 3757 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 3758 { 3759 struct hwrm_port_mac_cfg_input *req; 3760 int rc; 3761 3762 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 3763 if (rc) 3764 return rc; 3765 3766 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 3767 if (enable) 3768 req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 3769 else 3770 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 3771 return hwrm_req_send(bp, req); 3772 } 3773 3774 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 3775 { 3776 struct hwrm_port_phy_qcaps_output *resp; 3777 struct hwrm_port_phy_qcaps_input *req; 3778 int rc; 3779 3780 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS); 3781 if (rc) 3782 return rc; 3783 3784 resp = hwrm_req_hold(bp, req); 3785 rc = hwrm_req_send(bp, req); 3786 if (!rc) 3787 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 3788 3789 hwrm_req_drop(bp, req); 3790 return rc; 3791 } 3792 3793 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 3794 struct hwrm_port_phy_cfg_input *req) 3795 { 3796 struct bnxt_link_info *link_info = &bp->link_info; 3797 u16 fw_advertising; 3798 u16 fw_speed; 3799 int rc; 3800 3801 if (!link_info->autoneg || 3802 (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK)) 3803 return 0; 3804 3805 rc = bnxt_query_force_speeds(bp, &fw_advertising); 3806 if (rc) 3807 return rc; 3808 3809 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 3810 if (BNXT_LINK_IS_UP(bp)) 3811 fw_speed = bp->link_info.link_speed; 3812 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 3813 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 3814 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 3815 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 3816 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 3817 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 3818 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 3819 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 3820 3821 req->force_link_speed = cpu_to_le16(fw_speed); 3822 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 3823 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 3824 rc = hwrm_req_send(bp, req); 3825 req->flags = 0; 3826 req->force_link_speed = cpu_to_le16(0); 3827 return rc; 3828 } 3829 3830 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 3831 { 3832 struct hwrm_port_phy_cfg_input *req; 3833 int rc; 3834 3835 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 3836 if (rc) 3837 return rc; 3838 3839 /* prevent bnxt_disable_an_for_lpbk() from consuming the request */ 3840 hwrm_req_hold(bp, req); 3841 3842 if (enable) { 3843 bnxt_disable_an_for_lpbk(bp, req); 3844 if (ext) 3845 req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 3846 else 3847 req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 3848 } else { 3849 req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 3850 } 3851 req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 3852 rc = hwrm_req_send(bp, req); 3853 hwrm_req_drop(bp, req); 3854 return rc; 3855 } 3856 3857 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 3858 u32 raw_cons, int pkt_size) 3859 { 3860 struct bnxt_napi *bnapi = cpr->bnapi; 3861 struct bnxt_rx_ring_info *rxr; 3862 struct bnxt_sw_rx_bd *rx_buf; 3863 struct rx_cmp *rxcmp; 3864 u16 cp_cons, cons; 3865 u8 *data; 3866 u32 len; 3867 int i; 3868 3869 rxr = bnapi->rx_ring; 3870 cp_cons = RING_CMP(raw_cons); 3871 rxcmp = (struct rx_cmp *) 3872 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 3873 cons = rxcmp->rx_cmp_opaque; 3874 rx_buf = &rxr->rx_buf_ring[cons]; 3875 data = rx_buf->data_ptr; 3876 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 3877 if (len != pkt_size) 3878 return -EIO; 3879 i = ETH_ALEN; 3880 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 3881 return -EIO; 3882 i += ETH_ALEN; 3883 for ( ; i < pkt_size; i++) { 3884 if (data[i] != (u8)(i & 0xff)) 3885 return -EIO; 3886 } 3887 return 0; 3888 } 3889 3890 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 3891 int pkt_size) 3892 { 3893 struct tx_cmp *txcmp; 3894 int rc = -EIO; 3895 u32 raw_cons; 3896 u32 cons; 3897 int i; 3898 3899 raw_cons = cpr->cp_raw_cons; 3900 for (i = 0; i < 200; i++) { 3901 cons = RING_CMP(raw_cons); 3902 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 3903 3904 if (!TX_CMP_VALID(txcmp, raw_cons)) { 3905 udelay(5); 3906 continue; 3907 } 3908 3909 /* The valid test of the entry must be done first before 3910 * reading any further. 3911 */ 3912 dma_rmb(); 3913 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) { 3914 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 3915 raw_cons = NEXT_RAW_CMP(raw_cons); 3916 raw_cons = NEXT_RAW_CMP(raw_cons); 3917 break; 3918 } 3919 raw_cons = NEXT_RAW_CMP(raw_cons); 3920 } 3921 cpr->cp_raw_cons = raw_cons; 3922 return rc; 3923 } 3924 3925 static int bnxt_run_loopback(struct bnxt *bp) 3926 { 3927 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 3928 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 3929 struct bnxt_cp_ring_info *cpr; 3930 int pkt_size, i = 0; 3931 struct sk_buff *skb; 3932 dma_addr_t map; 3933 u8 *data; 3934 int rc; 3935 3936 cpr = &rxr->bnapi->cp_ring; 3937 if (bp->flags & BNXT_FLAG_CHIP_P5) 3938 cpr = cpr->cp_ring_arr[BNXT_RX_HDL]; 3939 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh); 3940 skb = netdev_alloc_skb(bp->dev, pkt_size); 3941 if (!skb) 3942 return -ENOMEM; 3943 data = skb_put(skb, pkt_size); 3944 ether_addr_copy(&data[i], bp->dev->dev_addr); 3945 i += ETH_ALEN; 3946 ether_addr_copy(&data[i], bp->dev->dev_addr); 3947 i += ETH_ALEN; 3948 for ( ; i < pkt_size; i++) 3949 data[i] = (u8)(i & 0xff); 3950 3951 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 3952 DMA_TO_DEVICE); 3953 if (dma_mapping_error(&bp->pdev->dev, map)) { 3954 dev_kfree_skb(skb); 3955 return -EIO; 3956 } 3957 bnxt_xmit_bd(bp, txr, map, pkt_size, NULL); 3958 3959 /* Sync BD data before updating doorbell */ 3960 wmb(); 3961 3962 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 3963 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 3964 3965 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE); 3966 dev_kfree_skb(skb); 3967 return rc; 3968 } 3969 3970 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 3971 { 3972 struct hwrm_selftest_exec_output *resp; 3973 struct hwrm_selftest_exec_input *req; 3974 int rc; 3975 3976 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC); 3977 if (rc) 3978 return rc; 3979 3980 hwrm_req_timeout(bp, req, bp->test_info->timeout); 3981 req->flags = test_mask; 3982 3983 resp = hwrm_req_hold(bp, req); 3984 rc = hwrm_req_send(bp, req); 3985 *test_results = resp->test_success; 3986 hwrm_req_drop(bp, req); 3987 return rc; 3988 } 3989 3990 #define BNXT_DRV_TESTS 4 3991 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 3992 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 3993 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 3994 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 3995 3996 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 3997 u64 *buf) 3998 { 3999 struct bnxt *bp = netdev_priv(dev); 4000 bool do_ext_lpbk = false; 4001 bool offline = false; 4002 u8 test_results = 0; 4003 u8 test_mask = 0; 4004 int rc = 0, i; 4005 4006 if (!bp->num_tests || !BNXT_PF(bp)) 4007 return; 4008 memset(buf, 0, sizeof(u64) * bp->num_tests); 4009 if (!netif_running(dev)) { 4010 etest->flags |= ETH_TEST_FL_FAILED; 4011 return; 4012 } 4013 4014 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 4015 (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK)) 4016 do_ext_lpbk = true; 4017 4018 if (etest->flags & ETH_TEST_FL_OFFLINE) { 4019 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) { 4020 etest->flags |= ETH_TEST_FL_FAILED; 4021 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n"); 4022 return; 4023 } 4024 offline = true; 4025 } 4026 4027 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 4028 u8 bit_val = 1 << i; 4029 4030 if (!(bp->test_info->offline_mask & bit_val)) 4031 test_mask |= bit_val; 4032 else if (offline) 4033 test_mask |= bit_val; 4034 } 4035 if (!offline) { 4036 bnxt_run_fw_tests(bp, test_mask, &test_results); 4037 } else { 4038 bnxt_ulp_stop(bp); 4039 bnxt_close_nic(bp, true, false); 4040 bnxt_run_fw_tests(bp, test_mask, &test_results); 4041 4042 buf[BNXT_MACLPBK_TEST_IDX] = 1; 4043 bnxt_hwrm_mac_loopback(bp, true); 4044 msleep(250); 4045 rc = bnxt_half_open_nic(bp); 4046 if (rc) { 4047 bnxt_hwrm_mac_loopback(bp, false); 4048 etest->flags |= ETH_TEST_FL_FAILED; 4049 bnxt_ulp_start(bp, rc); 4050 return; 4051 } 4052 if (bnxt_run_loopback(bp)) 4053 etest->flags |= ETH_TEST_FL_FAILED; 4054 else 4055 buf[BNXT_MACLPBK_TEST_IDX] = 0; 4056 4057 bnxt_hwrm_mac_loopback(bp, false); 4058 bnxt_hwrm_phy_loopback(bp, true, false); 4059 msleep(1000); 4060 if (bnxt_run_loopback(bp)) { 4061 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 4062 etest->flags |= ETH_TEST_FL_FAILED; 4063 } 4064 if (do_ext_lpbk) { 4065 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 4066 bnxt_hwrm_phy_loopback(bp, true, true); 4067 msleep(1000); 4068 if (bnxt_run_loopback(bp)) { 4069 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 4070 etest->flags |= ETH_TEST_FL_FAILED; 4071 } 4072 } 4073 bnxt_hwrm_phy_loopback(bp, false, false); 4074 bnxt_half_close_nic(bp); 4075 rc = bnxt_open_nic(bp, true, true); 4076 bnxt_ulp_start(bp, rc); 4077 } 4078 if (rc || bnxt_test_irq(bp)) { 4079 buf[BNXT_IRQ_TEST_IDX] = 1; 4080 etest->flags |= ETH_TEST_FL_FAILED; 4081 } 4082 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 4083 u8 bit_val = 1 << i; 4084 4085 if ((test_mask & bit_val) && !(test_results & bit_val)) { 4086 buf[i] = 1; 4087 etest->flags |= ETH_TEST_FL_FAILED; 4088 } 4089 } 4090 } 4091 4092 static int bnxt_reset(struct net_device *dev, u32 *flags) 4093 { 4094 struct bnxt *bp = netdev_priv(dev); 4095 bool reload = false; 4096 u32 req = *flags; 4097 4098 if (!req) 4099 return -EINVAL; 4100 4101 if (!BNXT_PF(bp)) { 4102 netdev_err(dev, "Reset is not supported from a VF\n"); 4103 return -EOPNOTSUPP; 4104 } 4105 4106 if (pci_vfs_assigned(bp->pdev) && 4107 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) { 4108 netdev_err(dev, 4109 "Reset not allowed when VFs are assigned to VMs\n"); 4110 return -EBUSY; 4111 } 4112 4113 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) { 4114 /* This feature is not supported in older firmware versions */ 4115 if (bp->hwrm_spec_code >= 0x10803) { 4116 if (!bnxt_firmware_reset_chip(dev)) { 4117 netdev_info(dev, "Firmware reset request successful.\n"); 4118 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) 4119 reload = true; 4120 *flags &= ~BNXT_FW_RESET_CHIP; 4121 } 4122 } else if (req == BNXT_FW_RESET_CHIP) { 4123 return -EOPNOTSUPP; /* only request, fail hard */ 4124 } 4125 } 4126 4127 if (!BNXT_CHIP_P4_PLUS(bp) && (req & BNXT_FW_RESET_AP)) { 4128 /* This feature is not supported in older firmware versions */ 4129 if (bp->hwrm_spec_code >= 0x10803) { 4130 if (!bnxt_firmware_reset_ap(dev)) { 4131 netdev_info(dev, "Reset application processor successful.\n"); 4132 reload = true; 4133 *flags &= ~BNXT_FW_RESET_AP; 4134 } 4135 } else if (req == BNXT_FW_RESET_AP) { 4136 return -EOPNOTSUPP; /* only request, fail hard */ 4137 } 4138 } 4139 4140 if (reload) 4141 netdev_info(dev, "Reload driver to complete reset\n"); 4142 4143 return 0; 4144 } 4145 4146 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump) 4147 { 4148 struct bnxt *bp = netdev_priv(dev); 4149 4150 if (dump->flag > BNXT_DUMP_CRASH) { 4151 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n"); 4152 return -EINVAL; 4153 } 4154 4155 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) { 4156 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n"); 4157 return -EOPNOTSUPP; 4158 } 4159 4160 bp->dump_flag = dump->flag; 4161 return 0; 4162 } 4163 4164 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 4165 { 4166 struct bnxt *bp = netdev_priv(dev); 4167 4168 if (bp->hwrm_spec_code < 0x10801) 4169 return -EOPNOTSUPP; 4170 4171 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 4172 bp->ver_resp.hwrm_fw_min_8b << 16 | 4173 bp->ver_resp.hwrm_fw_bld_8b << 8 | 4174 bp->ver_resp.hwrm_fw_rsvd_8b; 4175 4176 dump->flag = bp->dump_flag; 4177 dump->len = bnxt_get_coredump_length(bp, bp->dump_flag); 4178 return 0; 4179 } 4180 4181 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 4182 void *buf) 4183 { 4184 struct bnxt *bp = netdev_priv(dev); 4185 4186 if (bp->hwrm_spec_code < 0x10801) 4187 return -EOPNOTSUPP; 4188 4189 memset(buf, 0, dump->len); 4190 4191 dump->flag = bp->dump_flag; 4192 return bnxt_get_coredump(bp, dump->flag, buf, &dump->len); 4193 } 4194 4195 static int bnxt_get_ts_info(struct net_device *dev, 4196 struct ethtool_ts_info *info) 4197 { 4198 struct bnxt *bp = netdev_priv(dev); 4199 struct bnxt_ptp_cfg *ptp; 4200 4201 ptp = bp->ptp_cfg; 4202 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 4203 SOF_TIMESTAMPING_RX_SOFTWARE | 4204 SOF_TIMESTAMPING_SOFTWARE; 4205 4206 info->phc_index = -1; 4207 if (!ptp) 4208 return 0; 4209 4210 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | 4211 SOF_TIMESTAMPING_RX_HARDWARE | 4212 SOF_TIMESTAMPING_RAW_HARDWARE; 4213 if (ptp->ptp_clock) 4214 info->phc_index = ptp_clock_index(ptp->ptp_clock); 4215 4216 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 4217 4218 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 4219 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 4220 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 4221 4222 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) 4223 info->rx_filters |= (1 << HWTSTAMP_FILTER_ALL); 4224 return 0; 4225 } 4226 4227 void bnxt_ethtool_init(struct bnxt *bp) 4228 { 4229 struct hwrm_selftest_qlist_output *resp; 4230 struct hwrm_selftest_qlist_input *req; 4231 struct bnxt_test_info *test_info; 4232 struct net_device *dev = bp->dev; 4233 int i, rc; 4234 4235 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 4236 bnxt_get_pkgver(dev); 4237 4238 bp->num_tests = 0; 4239 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp)) 4240 return; 4241 4242 test_info = bp->test_info; 4243 if (!test_info) { 4244 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL); 4245 if (!test_info) 4246 return; 4247 bp->test_info = test_info; 4248 } 4249 4250 if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST)) 4251 return; 4252 4253 resp = hwrm_req_hold(bp, req); 4254 rc = hwrm_req_send_silent(bp, req); 4255 if (rc) 4256 goto ethtool_init_exit; 4257 4258 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 4259 if (bp->num_tests > BNXT_MAX_TEST) 4260 bp->num_tests = BNXT_MAX_TEST; 4261 4262 test_info->offline_mask = resp->offline_tests; 4263 test_info->timeout = le16_to_cpu(resp->test_timeout); 4264 if (!test_info->timeout) 4265 test_info->timeout = HWRM_CMD_TIMEOUT; 4266 for (i = 0; i < bp->num_tests; i++) { 4267 char *str = test_info->string[i]; 4268 char *fw_str = resp->test_name[i]; 4269 4270 if (i == BNXT_MACLPBK_TEST_IDX) { 4271 strcpy(str, "Mac loopback test (offline)"); 4272 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 4273 strcpy(str, "Phy loopback test (offline)"); 4274 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 4275 strcpy(str, "Ext loopback test (offline)"); 4276 } else if (i == BNXT_IRQ_TEST_IDX) { 4277 strcpy(str, "Interrupt_test (offline)"); 4278 } else { 4279 snprintf(str, ETH_GSTRING_LEN, "%s test (%s)", 4280 fw_str, test_info->offline_mask & (1 << i) ? 4281 "offline" : "online"); 4282 } 4283 } 4284 4285 ethtool_init_exit: 4286 hwrm_req_drop(bp, req); 4287 } 4288 4289 static void bnxt_get_eth_phy_stats(struct net_device *dev, 4290 struct ethtool_eth_phy_stats *phy_stats) 4291 { 4292 struct bnxt *bp = netdev_priv(dev); 4293 u64 *rx; 4294 4295 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 4296 return; 4297 4298 rx = bp->rx_port_stats_ext.sw_stats; 4299 phy_stats->SymbolErrorDuringCarrier = 4300 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err)); 4301 } 4302 4303 static void bnxt_get_eth_mac_stats(struct net_device *dev, 4304 struct ethtool_eth_mac_stats *mac_stats) 4305 { 4306 struct bnxt *bp = netdev_priv(dev); 4307 u64 *rx, *tx; 4308 4309 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 4310 return; 4311 4312 rx = bp->port_stats.sw_stats; 4313 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 4314 4315 mac_stats->FramesReceivedOK = 4316 BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames); 4317 mac_stats->FramesTransmittedOK = 4318 BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames); 4319 mac_stats->FrameCheckSequenceErrors = 4320 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames); 4321 mac_stats->AlignmentErrors = 4322 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames); 4323 mac_stats->OutOfRangeLengthField = 4324 BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames); 4325 } 4326 4327 static void bnxt_get_eth_ctrl_stats(struct net_device *dev, 4328 struct ethtool_eth_ctrl_stats *ctrl_stats) 4329 { 4330 struct bnxt *bp = netdev_priv(dev); 4331 u64 *rx; 4332 4333 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 4334 return; 4335 4336 rx = bp->port_stats.sw_stats; 4337 ctrl_stats->MACControlFramesReceived = 4338 BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames); 4339 } 4340 4341 static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = { 4342 { 0, 64 }, 4343 { 65, 127 }, 4344 { 128, 255 }, 4345 { 256, 511 }, 4346 { 512, 1023 }, 4347 { 1024, 1518 }, 4348 { 1519, 2047 }, 4349 { 2048, 4095 }, 4350 { 4096, 9216 }, 4351 { 9217, 16383 }, 4352 {} 4353 }; 4354 4355 static void bnxt_get_rmon_stats(struct net_device *dev, 4356 struct ethtool_rmon_stats *rmon_stats, 4357 const struct ethtool_rmon_hist_range **ranges) 4358 { 4359 struct bnxt *bp = netdev_priv(dev); 4360 u64 *rx, *tx; 4361 4362 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 4363 return; 4364 4365 rx = bp->port_stats.sw_stats; 4366 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 4367 4368 rmon_stats->jabbers = 4369 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames); 4370 rmon_stats->oversize_pkts = 4371 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames); 4372 rmon_stats->undersize_pkts = 4373 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames); 4374 4375 rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames); 4376 rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames); 4377 rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames); 4378 rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames); 4379 rmon_stats->hist[4] = 4380 BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames); 4381 rmon_stats->hist[5] = 4382 BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames); 4383 rmon_stats->hist[6] = 4384 BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames); 4385 rmon_stats->hist[7] = 4386 BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames); 4387 rmon_stats->hist[8] = 4388 BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames); 4389 rmon_stats->hist[9] = 4390 BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames); 4391 4392 rmon_stats->hist_tx[0] = 4393 BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames); 4394 rmon_stats->hist_tx[1] = 4395 BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames); 4396 rmon_stats->hist_tx[2] = 4397 BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames); 4398 rmon_stats->hist_tx[3] = 4399 BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames); 4400 rmon_stats->hist_tx[4] = 4401 BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames); 4402 rmon_stats->hist_tx[5] = 4403 BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames); 4404 rmon_stats->hist_tx[6] = 4405 BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames); 4406 rmon_stats->hist_tx[7] = 4407 BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames); 4408 rmon_stats->hist_tx[8] = 4409 BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames); 4410 rmon_stats->hist_tx[9] = 4411 BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames); 4412 4413 *ranges = bnxt_rmon_ranges; 4414 } 4415 4416 static void bnxt_get_link_ext_stats(struct net_device *dev, 4417 struct ethtool_link_ext_stats *stats) 4418 { 4419 struct bnxt *bp = netdev_priv(dev); 4420 u64 *rx; 4421 4422 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 4423 return; 4424 4425 rx = bp->rx_port_stats_ext.sw_stats; 4426 stats->link_down_events = 4427 *(rx + BNXT_RX_STATS_EXT_OFFSET(link_down_events)); 4428 } 4429 4430 void bnxt_ethtool_free(struct bnxt *bp) 4431 { 4432 kfree(bp->test_info); 4433 bp->test_info = NULL; 4434 } 4435 4436 const struct ethtool_ops bnxt_ethtool_ops = { 4437 .cap_link_lanes_supported = 1, 4438 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 4439 ETHTOOL_COALESCE_MAX_FRAMES | 4440 ETHTOOL_COALESCE_USECS_IRQ | 4441 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 4442 ETHTOOL_COALESCE_STATS_BLOCK_USECS | 4443 ETHTOOL_COALESCE_USE_ADAPTIVE_RX | 4444 ETHTOOL_COALESCE_USE_CQE, 4445 .get_link_ksettings = bnxt_get_link_ksettings, 4446 .set_link_ksettings = bnxt_set_link_ksettings, 4447 .get_fec_stats = bnxt_get_fec_stats, 4448 .get_fecparam = bnxt_get_fecparam, 4449 .set_fecparam = bnxt_set_fecparam, 4450 .get_pause_stats = bnxt_get_pause_stats, 4451 .get_pauseparam = bnxt_get_pauseparam, 4452 .set_pauseparam = bnxt_set_pauseparam, 4453 .get_drvinfo = bnxt_get_drvinfo, 4454 .get_regs_len = bnxt_get_regs_len, 4455 .get_regs = bnxt_get_regs, 4456 .get_wol = bnxt_get_wol, 4457 .set_wol = bnxt_set_wol, 4458 .get_coalesce = bnxt_get_coalesce, 4459 .set_coalesce = bnxt_set_coalesce, 4460 .get_msglevel = bnxt_get_msglevel, 4461 .set_msglevel = bnxt_set_msglevel, 4462 .get_sset_count = bnxt_get_sset_count, 4463 .get_strings = bnxt_get_strings, 4464 .get_ethtool_stats = bnxt_get_ethtool_stats, 4465 .set_ringparam = bnxt_set_ringparam, 4466 .get_ringparam = bnxt_get_ringparam, 4467 .get_channels = bnxt_get_channels, 4468 .set_channels = bnxt_set_channels, 4469 .get_rxnfc = bnxt_get_rxnfc, 4470 .set_rxnfc = bnxt_set_rxnfc, 4471 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 4472 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 4473 .get_rxfh = bnxt_get_rxfh, 4474 .set_rxfh = bnxt_set_rxfh, 4475 .flash_device = bnxt_flash_device, 4476 .get_eeprom_len = bnxt_get_eeprom_len, 4477 .get_eeprom = bnxt_get_eeprom, 4478 .set_eeprom = bnxt_set_eeprom, 4479 .get_link = bnxt_get_link, 4480 .get_link_ext_stats = bnxt_get_link_ext_stats, 4481 .get_eee = bnxt_get_eee, 4482 .set_eee = bnxt_set_eee, 4483 .get_module_info = bnxt_get_module_info, 4484 .get_module_eeprom = bnxt_get_module_eeprom, 4485 .get_module_eeprom_by_page = bnxt_get_module_eeprom_by_page, 4486 .nway_reset = bnxt_nway_reset, 4487 .set_phys_id = bnxt_set_phys_id, 4488 .self_test = bnxt_self_test, 4489 .get_ts_info = bnxt_get_ts_info, 4490 .reset = bnxt_reset, 4491 .set_dump = bnxt_set_dump, 4492 .get_dump_flag = bnxt_get_dump_flag, 4493 .get_dump_data = bnxt_get_dump_data, 4494 .get_eth_phy_stats = bnxt_get_eth_phy_stats, 4495 .get_eth_mac_stats = bnxt_get_eth_mac_stats, 4496 .get_eth_ctrl_stats = bnxt_get_eth_ctrl_stats, 4497 .get_rmon_stats = bnxt_get_rmon_stats, 4498 }; 4499