1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/bitops.h> 12 #include <linux/ctype.h> 13 #include <linux/stringify.h> 14 #include <linux/ethtool.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/linkmode.h> 17 #include <linux/interrupt.h> 18 #include <linux/pci.h> 19 #include <linux/etherdevice.h> 20 #include <linux/crc32.h> 21 #include <linux/firmware.h> 22 #include <linux/utsname.h> 23 #include <linux/time.h> 24 #include <linux/ptp_clock_kernel.h> 25 #include <linux/net_tstamp.h> 26 #include <linux/timecounter.h> 27 #include <net/netdev_queues.h> 28 #include <net/netlink.h> 29 #include <linux/bnxt/hsi.h> 30 #include "bnxt.h" 31 #include "bnxt_hwrm.h" 32 #include "bnxt_ulp.h" 33 #include "bnxt_xdp.h" 34 #include "bnxt_ptp.h" 35 #include "bnxt_ethtool.h" 36 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 37 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 38 #include "bnxt_coredump.h" 39 40 #define BNXT_NVM_ERR_MSG(dev, extack, msg) \ 41 do { \ 42 if (extack) \ 43 NL_SET_ERR_MSG_MOD(extack, msg); \ 44 netdev_err(dev, "%s\n", msg); \ 45 } while (0) 46 47 static u32 bnxt_get_msglevel(struct net_device *dev) 48 { 49 struct bnxt *bp = netdev_priv(dev); 50 51 return bp->msg_enable; 52 } 53 54 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 55 { 56 struct bnxt *bp = netdev_priv(dev); 57 58 bp->msg_enable = value; 59 } 60 61 static int bnxt_get_coalesce(struct net_device *dev, 62 struct ethtool_coalesce *coal, 63 struct kernel_ethtool_coalesce *kernel_coal, 64 struct netlink_ext_ack *extack) 65 { 66 struct bnxt *bp = netdev_priv(dev); 67 struct bnxt_coal *hw_coal; 68 u16 mult; 69 70 memset(coal, 0, sizeof(*coal)); 71 72 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 73 74 hw_coal = &bp->rx_coal; 75 mult = hw_coal->bufs_per_record; 76 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 77 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 78 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 79 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 80 if (hw_coal->flags & 81 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 82 kernel_coal->use_cqe_mode_rx = true; 83 84 hw_coal = &bp->tx_coal; 85 mult = hw_coal->bufs_per_record; 86 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 87 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 88 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 89 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 90 if (hw_coal->flags & 91 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 92 kernel_coal->use_cqe_mode_tx = true; 93 94 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 95 96 return 0; 97 } 98 99 static int bnxt_set_coalesce(struct net_device *dev, 100 struct ethtool_coalesce *coal, 101 struct kernel_ethtool_coalesce *kernel_coal, 102 struct netlink_ext_ack *extack) 103 { 104 struct bnxt *bp = netdev_priv(dev); 105 bool update_stats = false; 106 struct bnxt_coal *hw_coal; 107 int rc = 0; 108 u16 mult; 109 110 if (coal->use_adaptive_rx_coalesce) { 111 bp->flags |= BNXT_FLAG_DIM; 112 } else { 113 if (bp->flags & BNXT_FLAG_DIM) { 114 bp->flags &= ~(BNXT_FLAG_DIM); 115 goto reset_coalesce; 116 } 117 } 118 119 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) && 120 !(bp->coal_cap.cmpl_params & 121 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)) 122 return -EOPNOTSUPP; 123 124 hw_coal = &bp->rx_coal; 125 mult = hw_coal->bufs_per_record; 126 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 127 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 128 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 129 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 130 hw_coal->flags &= 131 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 132 if (kernel_coal->use_cqe_mode_rx) 133 hw_coal->flags |= 134 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 135 136 hw_coal = &bp->tx_coal; 137 mult = hw_coal->bufs_per_record; 138 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 139 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 140 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 141 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 142 hw_coal->flags &= 143 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 144 if (kernel_coal->use_cqe_mode_tx) 145 hw_coal->flags |= 146 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 147 148 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 149 u32 stats_ticks = coal->stats_block_coalesce_usecs; 150 151 /* Allow 0, which means disable. */ 152 if (stats_ticks) 153 stats_ticks = clamp_t(u32, stats_ticks, 154 BNXT_MIN_STATS_COAL_TICKS, 155 BNXT_MAX_STATS_COAL_TICKS); 156 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 157 bp->stats_coal_ticks = stats_ticks; 158 if (bp->stats_coal_ticks) 159 bp->current_interval = 160 bp->stats_coal_ticks * HZ / 1000000; 161 else 162 bp->current_interval = BNXT_TIMER_INTERVAL; 163 update_stats = true; 164 } 165 166 reset_coalesce: 167 if (test_bit(BNXT_STATE_OPEN, &bp->state)) { 168 if (update_stats) { 169 bnxt_close_nic(bp, true, false); 170 rc = bnxt_open_nic(bp, true, false); 171 } else { 172 rc = bnxt_hwrm_set_coal(bp); 173 } 174 } 175 176 return rc; 177 } 178 179 static const char * const bnxt_ring_rx_stats_str[] = { 180 "rx_ucast_packets", 181 "rx_mcast_packets", 182 "rx_bcast_packets", 183 "rx_discards", 184 "rx_errors", 185 "rx_ucast_bytes", 186 "rx_mcast_bytes", 187 "rx_bcast_bytes", 188 }; 189 190 static const char * const bnxt_ring_tx_stats_str[] = { 191 "tx_ucast_packets", 192 "tx_mcast_packets", 193 "tx_bcast_packets", 194 "tx_errors", 195 "tx_discards", 196 "tx_ucast_bytes", 197 "tx_mcast_bytes", 198 "tx_bcast_bytes", 199 }; 200 201 static const char * const bnxt_ring_tpa_stats_str[] = { 202 "tpa_packets", 203 "tpa_bytes", 204 "tpa_events", 205 "tpa_aborts", 206 }; 207 208 static const char * const bnxt_ring_tpa2_stats_str[] = { 209 "rx_tpa_eligible_pkt", 210 "rx_tpa_eligible_bytes", 211 "rx_tpa_pkt", 212 "rx_tpa_bytes", 213 "rx_tpa_errors", 214 "rx_tpa_events", 215 }; 216 217 static const char * const bnxt_rx_sw_stats_str[] = { 218 "rx_l4_csum_errors", 219 "rx_resets", 220 "rx_buf_errors", 221 }; 222 223 static const char * const bnxt_cmn_sw_stats_str[] = { 224 "missed_irqs", 225 }; 226 227 #define BNXT_RX_STATS_ENTRY(counter) \ 228 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 229 230 #define BNXT_TX_STATS_ENTRY(counter) \ 231 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 232 233 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 234 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 235 236 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 237 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 238 239 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 240 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 241 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 242 243 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 244 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 245 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 246 247 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 248 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 249 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 250 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 251 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 252 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 253 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 254 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 255 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 256 257 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 258 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 259 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 260 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 261 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 262 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 263 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 264 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 265 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 266 267 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 268 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 269 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 270 271 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 272 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 273 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 274 275 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 276 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 277 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 278 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 279 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 280 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 281 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 282 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 283 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 284 285 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 286 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 287 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 288 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 289 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 290 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 291 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 292 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 293 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 294 295 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 296 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 297 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 298 299 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 300 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 301 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 302 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 303 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 304 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 305 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 306 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 307 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 308 309 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 310 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 311 __stringify(counter##_pri##n) } 312 313 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 314 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 315 __stringify(counter##_pri##n) } 316 317 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 318 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 319 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 320 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 321 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 322 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 323 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 324 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 325 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 326 327 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 328 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 329 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 330 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 331 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 332 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 333 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 334 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 335 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 336 337 enum { 338 RX_TOTAL_DISCARDS, 339 TX_TOTAL_DISCARDS, 340 RX_NETPOLL_DISCARDS, 341 }; 342 343 static const char *const bnxt_ring_drv_stats_arr[] = { 344 "rx_total_l4_csum_errors", 345 "rx_total_resets", 346 "rx_total_buf_errors", 347 "rx_total_oom_discards", 348 "rx_total_netpoll_discards", 349 "rx_total_ring_discards", 350 "tx_total_resets", 351 "tx_total_ring_discards", 352 "total_missed_irqs", 353 }; 354 355 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str) 356 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str) 357 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str) 358 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str) 359 360 static const struct { 361 long offset; 362 char string[ETH_GSTRING_LEN]; 363 } bnxt_port_stats_arr[] = { 364 BNXT_RX_STATS_ENTRY(rx_64b_frames), 365 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 366 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 367 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 368 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 369 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 370 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 371 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 372 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 373 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 374 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 375 BNXT_RX_STATS_ENTRY(rx_total_frames), 376 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 377 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 378 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 379 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 380 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 381 BNXT_RX_STATS_ENTRY(rx_pause_frames), 382 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 383 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 384 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 385 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 386 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 387 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 388 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 389 BNXT_RX_STATS_ENTRY(rx_good_frames), 390 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 391 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 392 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 393 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 394 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 395 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 396 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 397 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 398 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 399 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 400 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 401 BNXT_RX_STATS_ENTRY(rx_bytes), 402 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 403 BNXT_RX_STATS_ENTRY(rx_runt_frames), 404 BNXT_RX_STATS_ENTRY(rx_stat_discard), 405 BNXT_RX_STATS_ENTRY(rx_stat_err), 406 407 BNXT_TX_STATS_ENTRY(tx_64b_frames), 408 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 409 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 410 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 411 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 412 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 413 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 414 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 415 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 416 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 417 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 418 BNXT_TX_STATS_ENTRY(tx_good_frames), 419 BNXT_TX_STATS_ENTRY(tx_total_frames), 420 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 421 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 422 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 423 BNXT_TX_STATS_ENTRY(tx_pause_frames), 424 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 425 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 426 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 427 BNXT_TX_STATS_ENTRY(tx_err), 428 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 429 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 430 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 431 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 432 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 433 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 434 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 435 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 436 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 437 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 438 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 439 BNXT_TX_STATS_ENTRY(tx_total_collisions), 440 BNXT_TX_STATS_ENTRY(tx_bytes), 441 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 442 BNXT_TX_STATS_ENTRY(tx_stat_discard), 443 BNXT_TX_STATS_ENTRY(tx_stat_error), 444 }; 445 446 static const struct { 447 long offset; 448 char string[ETH_GSTRING_LEN]; 449 } bnxt_port_stats_ext_arr[] = { 450 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 451 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 452 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 453 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 454 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 455 BNXT_RX_STATS_EXT_COS_ENTRIES, 456 BNXT_RX_STATS_EXT_PFC_ENTRIES, 457 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 458 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 459 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 460 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 461 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 462 BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks), 463 BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks), 464 BNXT_RX_STATS_EXT_ENTRY(rx_filter_miss), 465 }; 466 467 static const struct { 468 long offset; 469 char string[ETH_GSTRING_LEN]; 470 } bnxt_tx_port_stats_ext_arr[] = { 471 BNXT_TX_STATS_EXT_COS_ENTRIES, 472 BNXT_TX_STATS_EXT_PFC_ENTRIES, 473 }; 474 475 static const struct { 476 long base_off; 477 char string[ETH_GSTRING_LEN]; 478 } bnxt_rx_bytes_pri_arr[] = { 479 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 480 }; 481 482 static const struct { 483 long base_off; 484 char string[ETH_GSTRING_LEN]; 485 } bnxt_rx_pkts_pri_arr[] = { 486 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 487 }; 488 489 static const struct { 490 long base_off; 491 char string[ETH_GSTRING_LEN]; 492 } bnxt_tx_bytes_pri_arr[] = { 493 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 494 }; 495 496 static const struct { 497 long base_off; 498 char string[ETH_GSTRING_LEN]; 499 } bnxt_tx_pkts_pri_arr[] = { 500 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 501 }; 502 503 #define BNXT_NUM_RING_DRV_STATS ARRAY_SIZE(bnxt_ring_drv_stats_arr) 504 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 505 #define BNXT_NUM_STATS_PRI \ 506 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 507 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 508 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 509 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 510 511 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 512 { 513 if (BNXT_SUPPORTS_TPA(bp)) { 514 if (bp->max_tpa_v2) { 515 if (BNXT_CHIP_P5(bp)) 516 return BNXT_NUM_TPA_RING_STATS_P5; 517 return BNXT_NUM_TPA_RING_STATS_P7; 518 } 519 return BNXT_NUM_TPA_RING_STATS; 520 } 521 return 0; 522 } 523 524 static int bnxt_get_num_ring_stats(struct bnxt *bp) 525 { 526 int rx, tx, cmn; 527 528 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS + 529 bnxt_get_num_tpa_ring_stats(bp); 530 tx = NUM_RING_TX_HW_STATS; 531 cmn = NUM_RING_CMN_SW_STATS; 532 return rx * bp->rx_nr_rings + 533 tx * (bp->tx_nr_rings_xdp + bp->tx_nr_rings_per_tc) + 534 cmn * bp->cp_nr_rings; 535 } 536 537 static int bnxt_get_num_stats(struct bnxt *bp) 538 { 539 int num_stats = bnxt_get_num_ring_stats(bp); 540 int len; 541 542 num_stats += BNXT_NUM_RING_DRV_STATS; 543 544 if (bp->flags & BNXT_FLAG_PORT_STATS) 545 num_stats += BNXT_NUM_PORT_STATS; 546 547 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 548 len = min_t(int, bp->fw_rx_stats_ext_size, 549 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 550 num_stats += len; 551 len = min_t(int, bp->fw_tx_stats_ext_size, 552 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 553 num_stats += len; 554 if (bp->pri2cos_valid) 555 num_stats += BNXT_NUM_STATS_PRI; 556 } 557 558 return num_stats; 559 } 560 561 static int bnxt_get_sset_count(struct net_device *dev, int sset) 562 { 563 struct bnxt *bp = netdev_priv(dev); 564 565 switch (sset) { 566 case ETH_SS_STATS: 567 return bnxt_get_num_stats(bp); 568 case ETH_SS_TEST: 569 if (!bp->num_tests) 570 return -EOPNOTSUPP; 571 return bp->num_tests; 572 default: 573 return -EOPNOTSUPP; 574 } 575 } 576 577 static bool is_rx_ring(struct bnxt *bp, int ring_num) 578 { 579 return ring_num < bp->rx_nr_rings; 580 } 581 582 static bool is_tx_ring(struct bnxt *bp, int ring_num) 583 { 584 int tx_base = 0; 585 586 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 587 tx_base = bp->rx_nr_rings; 588 589 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings)) 590 return true; 591 return false; 592 } 593 594 static void bnxt_get_ethtool_stats(struct net_device *dev, 595 struct ethtool_stats *stats, u64 *buf) 596 { 597 struct bnxt_total_ring_drv_stats ring_drv_stats = {0}; 598 struct bnxt *bp = netdev_priv(dev); 599 u64 *curr, *prev; 600 u32 tpa_stats; 601 u32 i, j = 0; 602 603 if (!bp->bnapi) { 604 j += bnxt_get_num_ring_stats(bp); 605 goto skip_ring_stats; 606 } 607 608 tpa_stats = bnxt_get_num_tpa_ring_stats(bp); 609 for (i = 0; i < bp->cp_nr_rings; i++) { 610 struct bnxt_napi *bnapi = bp->bnapi[i]; 611 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 612 u64 *sw_stats = cpr->stats.sw_stats; 613 u64 *sw; 614 int k; 615 616 if (is_rx_ring(bp, i)) { 617 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++) 618 buf[j] = sw_stats[k]; 619 } 620 if (is_tx_ring(bp, i)) { 621 k = NUM_RING_RX_HW_STATS; 622 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 623 j++, k++) 624 buf[j] = sw_stats[k]; 625 } 626 if (!tpa_stats || !is_rx_ring(bp, i)) 627 goto skip_tpa_ring_stats; 628 629 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 630 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS + 631 tpa_stats; j++, k++) 632 buf[j] = sw_stats[k]; 633 634 skip_tpa_ring_stats: 635 sw = (u64 *)&cpr->sw_stats->rx; 636 if (is_rx_ring(bp, i)) { 637 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++) 638 buf[j] = sw[k]; 639 } 640 641 sw = (u64 *)&cpr->sw_stats->cmn; 642 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++) 643 buf[j] = sw[k]; 644 } 645 646 bnxt_get_ring_drv_stats(bp, &ring_drv_stats); 647 648 skip_ring_stats: 649 curr = &ring_drv_stats.rx_total_l4_csum_errors; 650 prev = &bp->ring_drv_stats_prev.rx_total_l4_csum_errors; 651 for (i = 0; i < BNXT_NUM_RING_DRV_STATS; i++, j++, curr++, prev++) 652 buf[j] = *curr + *prev; 653 654 if (bp->flags & BNXT_FLAG_PORT_STATS) { 655 u64 *port_stats = bp->port_stats.sw_stats; 656 657 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) 658 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset); 659 } 660 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 661 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats; 662 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats; 663 u32 len; 664 665 len = min_t(u32, bp->fw_rx_stats_ext_size, 666 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 667 for (i = 0; i < len; i++, j++) { 668 buf[j] = *(rx_port_stats_ext + 669 bnxt_port_stats_ext_arr[i].offset); 670 } 671 len = min_t(u32, bp->fw_tx_stats_ext_size, 672 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 673 for (i = 0; i < len; i++, j++) { 674 buf[j] = *(tx_port_stats_ext + 675 bnxt_tx_port_stats_ext_arr[i].offset); 676 } 677 if (bp->pri2cos_valid) { 678 for (i = 0; i < 8; i++, j++) { 679 long n = bnxt_rx_bytes_pri_arr[i].base_off + 680 bp->pri2cos_idx[i]; 681 682 buf[j] = *(rx_port_stats_ext + n); 683 } 684 for (i = 0; i < 8; i++, j++) { 685 long n = bnxt_rx_pkts_pri_arr[i].base_off + 686 bp->pri2cos_idx[i]; 687 688 buf[j] = *(rx_port_stats_ext + n); 689 } 690 for (i = 0; i < 8; i++, j++) { 691 u8 cos_idx = bp->pri2cos_idx[i]; 692 long n; 693 694 n = bnxt_tx_bytes_pri_arr[i].base_off + cos_idx; 695 buf[j] = *(tx_port_stats_ext + n); 696 if (bp->cos0_cos1_shared && !cos_idx) 697 buf[j] += *(tx_port_stats_ext + n + 1); 698 } 699 for (i = 0; i < 8; i++, j++) { 700 u8 cos_idx = bp->pri2cos_idx[i]; 701 long n; 702 703 n = bnxt_tx_pkts_pri_arr[i].base_off + cos_idx; 704 buf[j] = *(tx_port_stats_ext + n); 705 if (bp->cos0_cos1_shared && !cos_idx) 706 buf[j] += *(tx_port_stats_ext + n + 1); 707 } 708 } 709 } 710 } 711 712 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 713 { 714 struct bnxt *bp = netdev_priv(dev); 715 u32 i, j, num_str; 716 const char *str; 717 718 switch (stringset) { 719 case ETH_SS_STATS: 720 for (i = 0; i < bp->cp_nr_rings; i++) { 721 if (is_rx_ring(bp, i)) 722 for (j = 0; j < NUM_RING_RX_HW_STATS; j++) { 723 str = bnxt_ring_rx_stats_str[j]; 724 ethtool_sprintf(&buf, "[%d]: %s", i, 725 str); 726 } 727 if (is_tx_ring(bp, i)) 728 for (j = 0; j < NUM_RING_TX_HW_STATS; j++) { 729 str = bnxt_ring_tx_stats_str[j]; 730 ethtool_sprintf(&buf, "[%d]: %s", i, 731 str); 732 } 733 num_str = bnxt_get_num_tpa_ring_stats(bp); 734 if (!num_str || !is_rx_ring(bp, i)) 735 goto skip_tpa_stats; 736 737 if (bp->max_tpa_v2) 738 for (j = 0; j < num_str; j++) { 739 str = bnxt_ring_tpa2_stats_str[j]; 740 ethtool_sprintf(&buf, "[%d]: %s", i, 741 str); 742 } 743 else 744 for (j = 0; j < num_str; j++) { 745 str = bnxt_ring_tpa_stats_str[j]; 746 ethtool_sprintf(&buf, "[%d]: %s", i, 747 str); 748 } 749 skip_tpa_stats: 750 if (is_rx_ring(bp, i)) 751 for (j = 0; j < NUM_RING_RX_SW_STATS; j++) { 752 str = bnxt_rx_sw_stats_str[j]; 753 ethtool_sprintf(&buf, "[%d]: %s", i, 754 str); 755 } 756 for (j = 0; j < NUM_RING_CMN_SW_STATS; j++) { 757 str = bnxt_cmn_sw_stats_str[j]; 758 ethtool_sprintf(&buf, "[%d]: %s", i, str); 759 } 760 } 761 for (i = 0; i < BNXT_NUM_RING_DRV_STATS; i++) 762 ethtool_puts(&buf, bnxt_ring_drv_stats_arr[i]); 763 764 if (bp->flags & BNXT_FLAG_PORT_STATS) 765 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 766 str = bnxt_port_stats_arr[i].string; 767 ethtool_puts(&buf, str); 768 } 769 770 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 771 u32 len; 772 773 len = min_t(u32, bp->fw_rx_stats_ext_size, 774 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 775 for (i = 0; i < len; i++) { 776 str = bnxt_port_stats_ext_arr[i].string; 777 ethtool_puts(&buf, str); 778 } 779 780 len = min_t(u32, bp->fw_tx_stats_ext_size, 781 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 782 for (i = 0; i < len; i++) { 783 str = bnxt_tx_port_stats_ext_arr[i].string; 784 ethtool_puts(&buf, str); 785 } 786 787 if (bp->pri2cos_valid) { 788 for (i = 0; i < 8; i++) { 789 str = bnxt_rx_bytes_pri_arr[i].string; 790 ethtool_puts(&buf, str); 791 } 792 793 for (i = 0; i < 8; i++) { 794 str = bnxt_rx_pkts_pri_arr[i].string; 795 ethtool_puts(&buf, str); 796 } 797 798 for (i = 0; i < 8; i++) { 799 str = bnxt_tx_bytes_pri_arr[i].string; 800 ethtool_puts(&buf, str); 801 } 802 803 for (i = 0; i < 8; i++) { 804 str = bnxt_tx_pkts_pri_arr[i].string; 805 ethtool_puts(&buf, str); 806 } 807 } 808 } 809 break; 810 case ETH_SS_TEST: 811 if (bp->num_tests) 812 for (i = 0; i < bp->num_tests; i++) 813 ethtool_puts(&buf, bp->test_info->string[i]); 814 break; 815 default: 816 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 817 stringset); 818 break; 819 } 820 } 821 822 static void bnxt_get_ringparam(struct net_device *dev, 823 struct ethtool_ringparam *ering, 824 struct kernel_ethtool_ringparam *kernel_ering, 825 struct netlink_ext_ack *extack) 826 { 827 struct bnxt *bp = netdev_priv(dev); 828 829 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 830 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA; 831 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 832 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_ENABLED; 833 } else { 834 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 835 ering->rx_jumbo_max_pending = 0; 836 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_DISABLED; 837 } 838 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 839 840 ering->rx_pending = bp->rx_ring_size; 841 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 842 ering->tx_pending = bp->tx_ring_size; 843 844 kernel_ering->hds_thresh_max = BNXT_HDS_THRESHOLD_MAX; 845 } 846 847 static int bnxt_set_ringparam(struct net_device *dev, 848 struct ethtool_ringparam *ering, 849 struct kernel_ethtool_ringparam *kernel_ering, 850 struct netlink_ext_ack *extack) 851 { 852 u8 tcp_data_split = kernel_ering->tcp_data_split; 853 struct bnxt *bp = netdev_priv(dev); 854 u8 hds_config_mod; 855 856 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 857 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 858 (ering->tx_pending < BNXT_MIN_TX_DESC_CNT)) 859 return -EINVAL; 860 861 hds_config_mod = tcp_data_split != dev->cfg->hds_config; 862 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_DISABLED && hds_config_mod) 863 return -EINVAL; 864 865 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_ENABLED && 866 hds_config_mod && BNXT_RX_PAGE_MODE(bp)) { 867 NL_SET_ERR_MSG_MOD(extack, "tcp-data-split is disallowed when XDP is attached"); 868 return -EINVAL; 869 } 870 871 if (netif_running(dev)) 872 bnxt_close_nic(bp, false, false); 873 874 if (hds_config_mod) { 875 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_ENABLED) 876 bp->flags |= BNXT_FLAG_HDS; 877 else if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_UNKNOWN) 878 bp->flags &= ~BNXT_FLAG_HDS; 879 } 880 881 bp->rx_ring_size = ering->rx_pending; 882 bp->tx_ring_size = ering->tx_pending; 883 bnxt_set_ring_params(bp); 884 885 if (netif_running(dev)) 886 return bnxt_open_nic(bp, false, false); 887 888 return 0; 889 } 890 891 static void bnxt_get_channels(struct net_device *dev, 892 struct ethtool_channels *channel) 893 { 894 struct bnxt *bp = netdev_priv(dev); 895 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 896 int max_rx_rings, max_tx_rings, tcs; 897 int max_tx_sch_inputs, tx_grps; 898 899 /* Get the most up-to-date max_tx_sch_inputs. */ 900 if (netif_running(dev) && BNXT_NEW_RM(bp)) 901 bnxt_hwrm_func_resc_qcaps(bp, false); 902 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 903 904 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 905 if (max_tx_sch_inputs) 906 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 907 908 tcs = bp->num_tc; 909 tx_grps = max(tcs, 1); 910 if (bp->tx_nr_rings_xdp) 911 tx_grps++; 912 max_tx_rings /= tx_grps; 913 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 914 915 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 916 max_rx_rings = 0; 917 max_tx_rings = 0; 918 } 919 if (max_tx_sch_inputs) 920 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 921 922 if (tcs > 1) 923 max_tx_rings /= tcs; 924 925 channel->max_rx = max_rx_rings; 926 channel->max_tx = max_tx_rings; 927 channel->max_other = 0; 928 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 929 channel->combined_count = bp->rx_nr_rings; 930 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 931 channel->combined_count--; 932 } else { 933 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 934 channel->rx_count = bp->rx_nr_rings; 935 channel->tx_count = bp->tx_nr_rings_per_tc; 936 } 937 } 938 } 939 940 static int bnxt_set_channels(struct net_device *dev, 941 struct ethtool_channels *channel) 942 { 943 struct bnxt *bp = netdev_priv(dev); 944 int req_tx_rings, req_rx_rings, tcs; 945 u32 new_tbl_size = 0, old_tbl_size; 946 bool sh = false; 947 int tx_xdp = 0; 948 int rc = 0; 949 950 if (channel->other_count) 951 return -EINVAL; 952 953 if (!channel->combined_count && 954 (!channel->rx_count || !channel->tx_count)) 955 return -EINVAL; 956 957 if (channel->combined_count && 958 (channel->rx_count || channel->tx_count)) 959 return -EINVAL; 960 961 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 962 channel->tx_count)) 963 return -EINVAL; 964 965 if (channel->combined_count) 966 sh = true; 967 968 tcs = bp->num_tc; 969 970 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 971 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 972 if (bp->tx_nr_rings_xdp) { 973 if (!sh) { 974 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 975 return -EINVAL; 976 } 977 tx_xdp = req_rx_rings; 978 } 979 980 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 981 if (rc) { 982 netdev_warn(dev, "Unable to allocate the requested rings\n"); 983 return rc; 984 } 985 986 /* RSS table size only changes on P5 chips with older firmware; 987 * newer firmware always uses the largest table size. 988 */ 989 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) != 990 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings)) { 991 new_tbl_size = bnxt_get_nr_rss_ctxs(bp, req_rx_rings) * 992 BNXT_RSS_TABLE_ENTRIES_P5; 993 old_tbl_size = bnxt_get_rxfh_indir_size(dev); 994 995 if (!ethtool_rxfh_indir_can_resize(dev, bp->rss_indir_tbl, 996 old_tbl_size, 997 new_tbl_size)) { 998 netdev_warn(dev, "RSS table resize not possible\n"); 999 return -EINVAL; 1000 } 1001 1002 rc = ethtool_rxfh_ctxs_can_resize(dev, new_tbl_size); 1003 if (rc) 1004 return rc; 1005 } 1006 1007 if (netif_running(dev)) { 1008 if (BNXT_PF(bp)) { 1009 /* TODO CHIMP_FW: Send message to all VF's 1010 * before PF unload 1011 */ 1012 } 1013 bnxt_close_nic(bp, true, false); 1014 } 1015 1016 if (new_tbl_size) { 1017 ethtool_rxfh_indir_resize(dev, bp->rss_indir_tbl, 1018 old_tbl_size, new_tbl_size); 1019 ethtool_rxfh_ctxs_resize(dev, new_tbl_size); 1020 } 1021 1022 if (sh) { 1023 bp->flags |= BNXT_FLAG_SHARED_RINGS; 1024 bp->rx_nr_rings = channel->combined_count; 1025 bp->tx_nr_rings_per_tc = channel->combined_count; 1026 } else { 1027 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 1028 bp->rx_nr_rings = channel->rx_count; 1029 bp->tx_nr_rings_per_tc = channel->tx_count; 1030 } 1031 bp->tx_nr_rings_xdp = tx_xdp; 1032 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 1033 if (tcs > 1) 1034 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 1035 1036 bnxt_set_cp_rings(bp, sh); 1037 1038 /* After changing number of rx channels, update NTUPLE feature. */ 1039 netdev_update_features(dev); 1040 if (netif_running(dev)) { 1041 rc = bnxt_open_nic(bp, true, false); 1042 if ((!rc) && BNXT_PF(bp)) { 1043 /* TODO CHIMP_FW: Send message to all VF's 1044 * to renable 1045 */ 1046 } 1047 } else { 1048 rc = bnxt_reserve_rings(bp, true); 1049 } 1050 1051 return rc; 1052 } 1053 1054 static u32 bnxt_get_all_fltr_ids_rcu(struct bnxt *bp, struct hlist_head tbl[], 1055 int tbl_size, u32 *ids, u32 start, 1056 u32 id_cnt) 1057 { 1058 int i, j = start; 1059 1060 if (j >= id_cnt) 1061 return j; 1062 for (i = 0; i < tbl_size; i++) { 1063 struct hlist_head *head; 1064 struct bnxt_filter_base *fltr; 1065 1066 head = &tbl[i]; 1067 hlist_for_each_entry_rcu(fltr, head, hash) { 1068 if (!fltr->flags || 1069 test_bit(BNXT_FLTR_FW_DELETED, &fltr->state)) 1070 continue; 1071 ids[j++] = fltr->sw_id; 1072 if (j == id_cnt) 1073 return j; 1074 } 1075 } 1076 return j; 1077 } 1078 1079 static struct bnxt_filter_base *bnxt_get_one_fltr_rcu(struct bnxt *bp, 1080 struct hlist_head tbl[], 1081 int tbl_size, u32 id) 1082 { 1083 int i; 1084 1085 for (i = 0; i < tbl_size; i++) { 1086 struct hlist_head *head; 1087 struct bnxt_filter_base *fltr; 1088 1089 head = &tbl[i]; 1090 hlist_for_each_entry_rcu(fltr, head, hash) { 1091 if (fltr->flags && fltr->sw_id == id) 1092 return fltr; 1093 } 1094 } 1095 return NULL; 1096 } 1097 1098 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 1099 u32 *rule_locs) 1100 { 1101 u32 count; 1102 1103 cmd->data = bp->ntp_fltr_count; 1104 rcu_read_lock(); 1105 count = bnxt_get_all_fltr_ids_rcu(bp, bp->l2_fltr_hash_tbl, 1106 BNXT_L2_FLTR_HASH_SIZE, rule_locs, 0, 1107 cmd->rule_cnt); 1108 cmd->rule_cnt = bnxt_get_all_fltr_ids_rcu(bp, bp->ntp_fltr_hash_tbl, 1109 BNXT_NTP_FLTR_HASH_SIZE, 1110 rule_locs, count, 1111 cmd->rule_cnt); 1112 rcu_read_unlock(); 1113 1114 return 0; 1115 } 1116 1117 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1118 { 1119 struct ethtool_rx_flow_spec *fs = 1120 (struct ethtool_rx_flow_spec *)&cmd->fs; 1121 struct bnxt_filter_base *fltr_base; 1122 struct bnxt_ntuple_filter *fltr; 1123 struct bnxt_flow_masks *fmasks; 1124 struct flow_keys *fkeys; 1125 int rc = -EINVAL; 1126 1127 if (fs->location >= bp->max_fltr) 1128 return rc; 1129 1130 rcu_read_lock(); 1131 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl, 1132 BNXT_L2_FLTR_HASH_SIZE, 1133 fs->location); 1134 if (fltr_base) { 1135 struct ethhdr *h_ether = &fs->h_u.ether_spec; 1136 struct ethhdr *m_ether = &fs->m_u.ether_spec; 1137 struct bnxt_l2_filter *l2_fltr; 1138 struct bnxt_l2_key *l2_key; 1139 1140 l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base); 1141 l2_key = &l2_fltr->l2_key; 1142 fs->flow_type = ETHER_FLOW; 1143 ether_addr_copy(h_ether->h_dest, l2_key->dst_mac_addr); 1144 eth_broadcast_addr(m_ether->h_dest); 1145 if (l2_key->vlan) { 1146 struct ethtool_flow_ext *m_ext = &fs->m_ext; 1147 struct ethtool_flow_ext *h_ext = &fs->h_ext; 1148 1149 fs->flow_type |= FLOW_EXT; 1150 m_ext->vlan_tci = htons(0xfff); 1151 h_ext->vlan_tci = htons(l2_key->vlan); 1152 } 1153 if (fltr_base->flags & BNXT_ACT_RING_DST) 1154 fs->ring_cookie = fltr_base->rxq; 1155 if (fltr_base->flags & BNXT_ACT_FUNC_DST) 1156 fs->ring_cookie = (u64)(fltr_base->vf_idx + 1) << 1157 ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 1158 rcu_read_unlock(); 1159 return 0; 1160 } 1161 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl, 1162 BNXT_NTP_FLTR_HASH_SIZE, 1163 fs->location); 1164 if (!fltr_base) { 1165 rcu_read_unlock(); 1166 return rc; 1167 } 1168 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base); 1169 1170 fkeys = &fltr->fkeys; 1171 fmasks = &fltr->fmasks; 1172 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 1173 if (fkeys->basic.ip_proto == BNXT_IP_PROTO_WILDCARD) { 1174 fs->flow_type = IP_USER_FLOW; 1175 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 1176 fs->h_u.usr_ip4_spec.proto = BNXT_IP_PROTO_WILDCARD; 1177 fs->m_u.usr_ip4_spec.proto = 0; 1178 } else if (fkeys->basic.ip_proto == IPPROTO_ICMP) { 1179 fs->flow_type = IP_USER_FLOW; 1180 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 1181 fs->h_u.usr_ip4_spec.proto = IPPROTO_ICMP; 1182 fs->m_u.usr_ip4_spec.proto = BNXT_IP_PROTO_FULL_MASK; 1183 } else if (fkeys->basic.ip_proto == IPPROTO_TCP) { 1184 fs->flow_type = TCP_V4_FLOW; 1185 } else if (fkeys->basic.ip_proto == IPPROTO_UDP) { 1186 fs->flow_type = UDP_V4_FLOW; 1187 } else { 1188 goto fltr_err; 1189 } 1190 1191 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 1192 fs->m_u.tcp_ip4_spec.ip4src = fmasks->addrs.v4addrs.src; 1193 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 1194 fs->m_u.tcp_ip4_spec.ip4dst = fmasks->addrs.v4addrs.dst; 1195 if (fs->flow_type == TCP_V4_FLOW || 1196 fs->flow_type == UDP_V4_FLOW) { 1197 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 1198 fs->m_u.tcp_ip4_spec.psrc = fmasks->ports.src; 1199 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 1200 fs->m_u.tcp_ip4_spec.pdst = fmasks->ports.dst; 1201 } 1202 } else { 1203 if (fkeys->basic.ip_proto == BNXT_IP_PROTO_WILDCARD) { 1204 fs->flow_type = IPV6_USER_FLOW; 1205 fs->h_u.usr_ip6_spec.l4_proto = BNXT_IP_PROTO_WILDCARD; 1206 fs->m_u.usr_ip6_spec.l4_proto = 0; 1207 } else if (fkeys->basic.ip_proto == IPPROTO_ICMPV6) { 1208 fs->flow_type = IPV6_USER_FLOW; 1209 fs->h_u.usr_ip6_spec.l4_proto = IPPROTO_ICMPV6; 1210 fs->m_u.usr_ip6_spec.l4_proto = BNXT_IP_PROTO_FULL_MASK; 1211 } else if (fkeys->basic.ip_proto == IPPROTO_TCP) { 1212 fs->flow_type = TCP_V6_FLOW; 1213 } else if (fkeys->basic.ip_proto == IPPROTO_UDP) { 1214 fs->flow_type = UDP_V6_FLOW; 1215 } else { 1216 goto fltr_err; 1217 } 1218 1219 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 1220 fkeys->addrs.v6addrs.src; 1221 *(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6src[0] = 1222 fmasks->addrs.v6addrs.src; 1223 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 1224 fkeys->addrs.v6addrs.dst; 1225 *(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6dst[0] = 1226 fmasks->addrs.v6addrs.dst; 1227 if (fs->flow_type == TCP_V6_FLOW || 1228 fs->flow_type == UDP_V6_FLOW) { 1229 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 1230 fs->m_u.tcp_ip6_spec.psrc = fmasks->ports.src; 1231 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 1232 fs->m_u.tcp_ip6_spec.pdst = fmasks->ports.dst; 1233 } 1234 } 1235 1236 if (fltr->base.flags & BNXT_ACT_DROP) { 1237 fs->ring_cookie = RX_CLS_FLOW_DISC; 1238 } else if (fltr->base.flags & BNXT_ACT_RSS_CTX) { 1239 fs->flow_type |= FLOW_RSS; 1240 cmd->rss_context = fltr->base.fw_vnic_id; 1241 } else { 1242 fs->ring_cookie = fltr->base.rxq; 1243 } 1244 rc = 0; 1245 1246 fltr_err: 1247 rcu_read_unlock(); 1248 1249 return rc; 1250 } 1251 1252 static struct bnxt_rss_ctx *bnxt_get_rss_ctx_from_index(struct bnxt *bp, 1253 u32 index) 1254 { 1255 struct ethtool_rxfh_context *ctx; 1256 1257 ctx = xa_load(&bp->dev->ethtool->rss_ctx, index); 1258 if (!ctx) 1259 return NULL; 1260 return ethtool_rxfh_context_priv(ctx); 1261 } 1262 1263 static int bnxt_alloc_vnic_rss_table(struct bnxt *bp, 1264 struct bnxt_vnic_info *vnic) 1265 { 1266 int size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5); 1267 1268 vnic->rss_table_size = size + HW_HASH_KEY_SIZE; 1269 vnic->rss_table = dma_alloc_coherent(&bp->pdev->dev, 1270 vnic->rss_table_size, 1271 &vnic->rss_table_dma_addr, 1272 GFP_KERNEL); 1273 if (!vnic->rss_table) 1274 return -ENOMEM; 1275 1276 vnic->rss_hash_key = ((void *)vnic->rss_table) + size; 1277 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; 1278 return 0; 1279 } 1280 1281 static int bnxt_add_l2_cls_rule(struct bnxt *bp, 1282 struct ethtool_rx_flow_spec *fs) 1283 { 1284 u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1285 u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1286 struct ethhdr *h_ether = &fs->h_u.ether_spec; 1287 struct ethhdr *m_ether = &fs->m_u.ether_spec; 1288 struct bnxt_l2_filter *fltr; 1289 struct bnxt_l2_key key; 1290 u16 vnic_id; 1291 u8 flags; 1292 int rc; 1293 1294 if (BNXT_CHIP_P5_PLUS(bp)) 1295 return -EOPNOTSUPP; 1296 1297 if (!is_broadcast_ether_addr(m_ether->h_dest)) 1298 return -EINVAL; 1299 ether_addr_copy(key.dst_mac_addr, h_ether->h_dest); 1300 key.vlan = 0; 1301 if (fs->flow_type & FLOW_EXT) { 1302 struct ethtool_flow_ext *m_ext = &fs->m_ext; 1303 struct ethtool_flow_ext *h_ext = &fs->h_ext; 1304 1305 if (m_ext->vlan_tci != htons(0xfff) || !h_ext->vlan_tci) 1306 return -EINVAL; 1307 key.vlan = ntohs(h_ext->vlan_tci); 1308 } 1309 1310 if (vf) { 1311 flags = BNXT_ACT_FUNC_DST; 1312 vnic_id = 0xffff; 1313 vf--; 1314 } else { 1315 flags = BNXT_ACT_RING_DST; 1316 vnic_id = bp->vnic_info[ring + 1].fw_vnic_id; 1317 } 1318 fltr = bnxt_alloc_new_l2_filter(bp, &key, flags); 1319 if (IS_ERR(fltr)) 1320 return PTR_ERR(fltr); 1321 1322 fltr->base.fw_vnic_id = vnic_id; 1323 fltr->base.rxq = ring; 1324 fltr->base.vf_idx = vf; 1325 rc = bnxt_hwrm_l2_filter_alloc(bp, fltr); 1326 if (rc) 1327 bnxt_del_l2_filter(bp, fltr); 1328 else 1329 fs->location = fltr->base.sw_id; 1330 return rc; 1331 } 1332 1333 static bool bnxt_verify_ntuple_ip4_flow(struct ethtool_usrip4_spec *ip_spec, 1334 struct ethtool_usrip4_spec *ip_mask) 1335 { 1336 u8 mproto = ip_mask->proto; 1337 u8 sproto = ip_spec->proto; 1338 1339 if (ip_mask->l4_4_bytes || ip_mask->tos || 1340 ip_spec->ip_ver != ETH_RX_NFC_IP4 || 1341 (mproto && (mproto != BNXT_IP_PROTO_FULL_MASK || sproto != IPPROTO_ICMP))) 1342 return false; 1343 return true; 1344 } 1345 1346 static bool bnxt_verify_ntuple_ip6_flow(struct ethtool_usrip6_spec *ip_spec, 1347 struct ethtool_usrip6_spec *ip_mask) 1348 { 1349 u8 mproto = ip_mask->l4_proto; 1350 u8 sproto = ip_spec->l4_proto; 1351 1352 if (ip_mask->l4_4_bytes || ip_mask->tclass || 1353 (mproto && (mproto != BNXT_IP_PROTO_FULL_MASK || sproto != IPPROTO_ICMPV6))) 1354 return false; 1355 return true; 1356 } 1357 1358 static int bnxt_add_ntuple_cls_rule(struct bnxt *bp, 1359 struct ethtool_rxnfc *cmd) 1360 { 1361 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1362 struct bnxt_ntuple_filter *new_fltr, *fltr; 1363 u32 flow_type = fs->flow_type & 0xff; 1364 struct bnxt_l2_filter *l2_fltr; 1365 struct bnxt_flow_masks *fmasks; 1366 struct flow_keys *fkeys; 1367 u32 idx; 1368 int rc; 1369 1370 if (!bp->vnic_info) 1371 return -EAGAIN; 1372 1373 if (fs->flow_type & (FLOW_MAC_EXT | FLOW_EXT)) 1374 return -EOPNOTSUPP; 1375 1376 if (fs->ring_cookie != RX_CLS_FLOW_DISC && 1377 ethtool_get_flow_spec_ring_vf(fs->ring_cookie)) 1378 return -EOPNOTSUPP; 1379 1380 if (flow_type == IP_USER_FLOW) { 1381 if (!bnxt_verify_ntuple_ip4_flow(&fs->h_u.usr_ip4_spec, 1382 &fs->m_u.usr_ip4_spec)) 1383 return -EOPNOTSUPP; 1384 } 1385 1386 if (flow_type == IPV6_USER_FLOW) { 1387 if (!bnxt_verify_ntuple_ip6_flow(&fs->h_u.usr_ip6_spec, 1388 &fs->m_u.usr_ip6_spec)) 1389 return -EOPNOTSUPP; 1390 } 1391 1392 new_fltr = kzalloc_obj(*new_fltr); 1393 if (!new_fltr) 1394 return -ENOMEM; 1395 1396 l2_fltr = bp->vnic_info[BNXT_VNIC_DEFAULT].l2_filters[0]; 1397 atomic_inc(&l2_fltr->refcnt); 1398 new_fltr->l2_fltr = l2_fltr; 1399 fmasks = &new_fltr->fmasks; 1400 fkeys = &new_fltr->fkeys; 1401 1402 rc = -EOPNOTSUPP; 1403 switch (flow_type) { 1404 case IP_USER_FLOW: { 1405 struct ethtool_usrip4_spec *ip_spec = &fs->h_u.usr_ip4_spec; 1406 struct ethtool_usrip4_spec *ip_mask = &fs->m_u.usr_ip4_spec; 1407 1408 fkeys->basic.ip_proto = ip_mask->proto ? ip_spec->proto 1409 : BNXT_IP_PROTO_WILDCARD; 1410 fkeys->basic.n_proto = htons(ETH_P_IP); 1411 fkeys->addrs.v4addrs.src = ip_spec->ip4src; 1412 fmasks->addrs.v4addrs.src = ip_mask->ip4src; 1413 fkeys->addrs.v4addrs.dst = ip_spec->ip4dst; 1414 fmasks->addrs.v4addrs.dst = ip_mask->ip4dst; 1415 break; 1416 } 1417 case TCP_V4_FLOW: 1418 case UDP_V4_FLOW: { 1419 struct ethtool_tcpip4_spec *ip_spec = &fs->h_u.tcp_ip4_spec; 1420 struct ethtool_tcpip4_spec *ip_mask = &fs->m_u.tcp_ip4_spec; 1421 1422 fkeys->basic.ip_proto = IPPROTO_TCP; 1423 if (flow_type == UDP_V4_FLOW) 1424 fkeys->basic.ip_proto = IPPROTO_UDP; 1425 fkeys->basic.n_proto = htons(ETH_P_IP); 1426 fkeys->addrs.v4addrs.src = ip_spec->ip4src; 1427 fmasks->addrs.v4addrs.src = ip_mask->ip4src; 1428 fkeys->addrs.v4addrs.dst = ip_spec->ip4dst; 1429 fmasks->addrs.v4addrs.dst = ip_mask->ip4dst; 1430 fkeys->ports.src = ip_spec->psrc; 1431 fmasks->ports.src = ip_mask->psrc; 1432 fkeys->ports.dst = ip_spec->pdst; 1433 fmasks->ports.dst = ip_mask->pdst; 1434 break; 1435 } 1436 case IPV6_USER_FLOW: { 1437 struct ethtool_usrip6_spec *ip_spec = &fs->h_u.usr_ip6_spec; 1438 struct ethtool_usrip6_spec *ip_mask = &fs->m_u.usr_ip6_spec; 1439 1440 fkeys->basic.ip_proto = ip_mask->l4_proto ? ip_spec->l4_proto 1441 : BNXT_IP_PROTO_WILDCARD; 1442 fkeys->basic.n_proto = htons(ETH_P_IPV6); 1443 fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src; 1444 fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src; 1445 fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst; 1446 fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst; 1447 break; 1448 } 1449 case TCP_V6_FLOW: 1450 case UDP_V6_FLOW: { 1451 struct ethtool_tcpip6_spec *ip_spec = &fs->h_u.tcp_ip6_spec; 1452 struct ethtool_tcpip6_spec *ip_mask = &fs->m_u.tcp_ip6_spec; 1453 1454 fkeys->basic.ip_proto = IPPROTO_TCP; 1455 if (flow_type == UDP_V6_FLOW) 1456 fkeys->basic.ip_proto = IPPROTO_UDP; 1457 fkeys->basic.n_proto = htons(ETH_P_IPV6); 1458 1459 fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src; 1460 fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src; 1461 fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst; 1462 fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst; 1463 fkeys->ports.src = ip_spec->psrc; 1464 fmasks->ports.src = ip_mask->psrc; 1465 fkeys->ports.dst = ip_spec->pdst; 1466 fmasks->ports.dst = ip_mask->pdst; 1467 break; 1468 } 1469 default: 1470 rc = -EOPNOTSUPP; 1471 goto ntuple_err; 1472 } 1473 if (!memcmp(&BNXT_FLOW_MASK_NONE, fmasks, sizeof(*fmasks))) 1474 goto ntuple_err; 1475 1476 idx = bnxt_get_ntp_filter_idx(bp, fkeys, NULL); 1477 rcu_read_lock(); 1478 fltr = bnxt_lookup_ntp_filter_from_idx(bp, new_fltr, idx); 1479 if (fltr) { 1480 rcu_read_unlock(); 1481 rc = -EEXIST; 1482 goto ntuple_err; 1483 } 1484 rcu_read_unlock(); 1485 1486 new_fltr->base.flags = BNXT_ACT_NO_AGING; 1487 if (fs->flow_type & FLOW_RSS) { 1488 struct bnxt_rss_ctx *rss_ctx; 1489 1490 new_fltr->base.fw_vnic_id = 0; 1491 new_fltr->base.flags |= BNXT_ACT_RSS_CTX; 1492 rss_ctx = bnxt_get_rss_ctx_from_index(bp, cmd->rss_context); 1493 if (rss_ctx) { 1494 new_fltr->base.fw_vnic_id = rss_ctx->index; 1495 } else { 1496 rc = -EINVAL; 1497 goto ntuple_err; 1498 } 1499 } 1500 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1501 new_fltr->base.flags |= BNXT_ACT_DROP; 1502 else 1503 new_fltr->base.rxq = ethtool_get_flow_spec_ring(fs->ring_cookie); 1504 __set_bit(BNXT_FLTR_VALID, &new_fltr->base.state); 1505 rc = bnxt_insert_ntp_filter(bp, new_fltr, idx); 1506 if (!rc) { 1507 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, new_fltr); 1508 if (rc) { 1509 bnxt_del_ntp_filter(bp, new_fltr); 1510 return rc; 1511 } 1512 fs->location = new_fltr->base.sw_id; 1513 return 0; 1514 } 1515 1516 ntuple_err: 1517 atomic_dec(&l2_fltr->refcnt); 1518 kfree(new_fltr); 1519 return rc; 1520 } 1521 1522 static int bnxt_srxclsrlins(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1523 { 1524 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1525 u32 ring, flow_type; 1526 int rc; 1527 u8 vf; 1528 1529 if (!netif_running(bp->dev)) 1530 return -EAGAIN; 1531 if (!(bp->flags & BNXT_FLAG_RFS)) 1532 return -EPERM; 1533 if (fs->location != RX_CLS_LOC_ANY) 1534 return -EINVAL; 1535 1536 flow_type = fs->flow_type; 1537 if ((flow_type == IP_USER_FLOW || 1538 flow_type == IPV6_USER_FLOW) && 1539 !(bp->fw_cap & BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO)) 1540 return -EOPNOTSUPP; 1541 if (flow_type & FLOW_MAC_EXT) 1542 return -EINVAL; 1543 flow_type &= ~FLOW_EXT; 1544 1545 if (fs->ring_cookie == RX_CLS_FLOW_DISC && flow_type != ETHER_FLOW) 1546 return bnxt_add_ntuple_cls_rule(bp, cmd); 1547 1548 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 1549 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 1550 if (BNXT_VF(bp) && vf) 1551 return -EINVAL; 1552 if (BNXT_PF(bp) && vf > bp->pf.active_vfs) 1553 return -EINVAL; 1554 if (!vf && ring >= bp->rx_nr_rings) 1555 return -EINVAL; 1556 1557 if (flow_type == ETHER_FLOW) 1558 rc = bnxt_add_l2_cls_rule(bp, fs); 1559 else 1560 rc = bnxt_add_ntuple_cls_rule(bp, cmd); 1561 return rc; 1562 } 1563 1564 static int bnxt_srxclsrldel(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1565 { 1566 struct ethtool_rx_flow_spec *fs = &cmd->fs; 1567 struct bnxt_filter_base *fltr_base; 1568 struct bnxt_ntuple_filter *fltr; 1569 u32 id = fs->location; 1570 1571 rcu_read_lock(); 1572 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl, 1573 BNXT_L2_FLTR_HASH_SIZE, id); 1574 if (fltr_base) { 1575 struct bnxt_l2_filter *l2_fltr; 1576 1577 l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base); 1578 rcu_read_unlock(); 1579 bnxt_hwrm_l2_filter_free(bp, l2_fltr); 1580 bnxt_del_l2_filter(bp, l2_fltr); 1581 return 0; 1582 } 1583 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl, 1584 BNXT_NTP_FLTR_HASH_SIZE, id); 1585 if (!fltr_base) { 1586 rcu_read_unlock(); 1587 return -ENOENT; 1588 } 1589 1590 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base); 1591 if (!(fltr->base.flags & BNXT_ACT_NO_AGING)) { 1592 rcu_read_unlock(); 1593 return -EINVAL; 1594 } 1595 rcu_read_unlock(); 1596 bnxt_hwrm_cfa_ntuple_filter_free(bp, fltr); 1597 bnxt_del_ntp_filter(bp, fltr); 1598 return 0; 1599 } 1600 1601 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1602 { 1603 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1604 return RXH_IP_SRC | RXH_IP_DST; 1605 return 0; 1606 } 1607 1608 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1609 { 1610 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1611 return RXH_IP_SRC | RXH_IP_DST; 1612 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL) 1613 return RXH_IP_SRC | RXH_IP_DST | RXH_IP6_FL; 1614 return 0; 1615 } 1616 1617 static int bnxt_get_rxfh_fields(struct net_device *dev, 1618 struct ethtool_rxfh_fields *cmd) 1619 { 1620 struct bnxt *bp = netdev_priv(dev); 1621 1622 cmd->data = 0; 1623 switch (cmd->flow_type) { 1624 case TCP_V4_FLOW: 1625 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1626 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1627 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1628 cmd->data |= get_ethtool_ipv4_rss(bp); 1629 break; 1630 case UDP_V4_FLOW: 1631 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1632 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1633 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1634 fallthrough; 1635 case AH_ESP_V4_FLOW: 1636 if (bp->rss_hash_cfg & 1637 (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1638 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4)) 1639 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1640 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1641 fallthrough; 1642 case SCTP_V4_FLOW: 1643 case AH_V4_FLOW: 1644 case ESP_V4_FLOW: 1645 case IPV4_FLOW: 1646 cmd->data |= get_ethtool_ipv4_rss(bp); 1647 break; 1648 1649 case TCP_V6_FLOW: 1650 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1651 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1652 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1653 cmd->data |= get_ethtool_ipv6_rss(bp); 1654 break; 1655 case UDP_V6_FLOW: 1656 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1657 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1658 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1659 fallthrough; 1660 case AH_ESP_V6_FLOW: 1661 if (bp->rss_hash_cfg & 1662 (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1663 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6)) 1664 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1665 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1666 fallthrough; 1667 case SCTP_V6_FLOW: 1668 case AH_V6_FLOW: 1669 case ESP_V6_FLOW: 1670 case IPV6_FLOW: 1671 cmd->data |= get_ethtool_ipv6_rss(bp); 1672 break; 1673 } 1674 return 0; 1675 } 1676 1677 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1678 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1679 1680 static int bnxt_set_rxfh_fields(struct net_device *dev, 1681 const struct ethtool_rxfh_fields *cmd, 1682 struct netlink_ext_ack *extack) 1683 { 1684 struct bnxt *bp = netdev_priv(dev); 1685 int tuple, rc = 0; 1686 u32 rss_hash_cfg; 1687 1688 rss_hash_cfg = bp->rss_hash_cfg; 1689 1690 if (cmd->data == RXH_4TUPLE) 1691 tuple = 4; 1692 else if (cmd->data == RXH_2TUPLE || 1693 cmd->data == (RXH_2TUPLE | RXH_IP6_FL)) 1694 tuple = 2; 1695 else if (!cmd->data) 1696 tuple = 0; 1697 else 1698 return -EINVAL; 1699 1700 if (cmd->data & RXH_IP6_FL && 1701 !(bp->rss_cap & BNXT_RSS_CAP_IPV6_FLOW_LABEL_RSS_CAP)) 1702 return -EINVAL; 1703 1704 if (cmd->flow_type == TCP_V4_FLOW) { 1705 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1706 if (tuple == 4) 1707 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1708 } else if (cmd->flow_type == UDP_V4_FLOW) { 1709 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP)) 1710 return -EINVAL; 1711 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1712 if (tuple == 4) 1713 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1714 } else if (cmd->flow_type == TCP_V6_FLOW) { 1715 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1716 if (tuple == 4) 1717 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1718 } else if (cmd->flow_type == UDP_V6_FLOW) { 1719 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP)) 1720 return -EINVAL; 1721 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1722 if (tuple == 4) 1723 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1724 } else if (cmd->flow_type == AH_ESP_V4_FLOW) { 1725 if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V4_RSS_CAP) || 1726 !(bp->rss_cap & BNXT_RSS_CAP_ESP_V4_RSS_CAP))) 1727 return -EINVAL; 1728 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1729 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4); 1730 if (tuple == 4) 1731 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 | 1732 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4; 1733 } else if (cmd->flow_type == AH_ESP_V6_FLOW) { 1734 if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V6_RSS_CAP) || 1735 !(bp->rss_cap & BNXT_RSS_CAP_ESP_V6_RSS_CAP))) 1736 return -EINVAL; 1737 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1738 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6); 1739 if (tuple == 4) 1740 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 | 1741 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6; 1742 } else if (tuple == 4) { 1743 return -EINVAL; 1744 } 1745 1746 switch (cmd->flow_type) { 1747 case TCP_V4_FLOW: 1748 case UDP_V4_FLOW: 1749 case SCTP_V4_FLOW: 1750 case AH_ESP_V4_FLOW: 1751 case AH_V4_FLOW: 1752 case ESP_V4_FLOW: 1753 case IPV4_FLOW: 1754 if (tuple == 2) 1755 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1756 else if (!tuple) 1757 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1758 break; 1759 1760 case TCP_V6_FLOW: 1761 case UDP_V6_FLOW: 1762 case SCTP_V6_FLOW: 1763 case AH_ESP_V6_FLOW: 1764 case AH_V6_FLOW: 1765 case ESP_V6_FLOW: 1766 case IPV6_FLOW: 1767 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 | 1768 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL); 1769 if (!tuple) 1770 break; 1771 if (cmd->data & RXH_IP6_FL) 1772 rss_hash_cfg |= 1773 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL; 1774 else if (tuple == 2) 1775 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1776 break; 1777 } 1778 1779 if (bp->rss_hash_cfg == rss_hash_cfg) 1780 return 0; 1781 1782 if (bp->rss_cap & BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA) 1783 bp->rss_hash_delta = bp->rss_hash_cfg ^ rss_hash_cfg; 1784 bp->rss_hash_cfg = rss_hash_cfg; 1785 if (netif_running(bp->dev)) { 1786 bnxt_close_nic(bp, false, false); 1787 rc = bnxt_open_nic(bp, false, false); 1788 } 1789 return rc; 1790 } 1791 1792 static u32 bnxt_get_rx_ring_count(struct net_device *dev) 1793 { 1794 struct bnxt *bp = netdev_priv(dev); 1795 1796 return bp->rx_nr_rings; 1797 } 1798 1799 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1800 u32 *rule_locs) 1801 { 1802 struct bnxt *bp = netdev_priv(dev); 1803 int rc = 0; 1804 1805 switch (cmd->cmd) { 1806 case ETHTOOL_GRXCLSRLCNT: 1807 cmd->rule_cnt = bp->ntp_fltr_count; 1808 cmd->data = bp->max_fltr | RX_CLS_LOC_SPECIAL; 1809 break; 1810 1811 case ETHTOOL_GRXCLSRLALL: 1812 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1813 break; 1814 1815 case ETHTOOL_GRXCLSRULE: 1816 rc = bnxt_grxclsrule(bp, cmd); 1817 break; 1818 1819 default: 1820 rc = -EOPNOTSUPP; 1821 break; 1822 } 1823 1824 return rc; 1825 } 1826 1827 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1828 { 1829 struct bnxt *bp = netdev_priv(dev); 1830 int rc; 1831 1832 switch (cmd->cmd) { 1833 case ETHTOOL_SRXCLSRLINS: 1834 rc = bnxt_srxclsrlins(bp, cmd); 1835 break; 1836 1837 case ETHTOOL_SRXCLSRLDEL: 1838 rc = bnxt_srxclsrldel(bp, cmd); 1839 break; 1840 1841 default: 1842 rc = -EOPNOTSUPP; 1843 break; 1844 } 1845 return rc; 1846 } 1847 1848 u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1849 { 1850 struct bnxt *bp = netdev_priv(dev); 1851 1852 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) 1853 return bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) * 1854 BNXT_RSS_TABLE_ENTRIES_P5; 1855 return HW_HASH_INDEX_SIZE; 1856 } 1857 1858 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1859 { 1860 return HW_HASH_KEY_SIZE; 1861 } 1862 1863 static int bnxt_get_rxfh(struct net_device *dev, 1864 struct ethtool_rxfh_param *rxfh) 1865 { 1866 struct bnxt_rss_ctx *rss_ctx = NULL; 1867 struct bnxt *bp = netdev_priv(dev); 1868 u32 *indir_tbl = bp->rss_indir_tbl; 1869 struct bnxt_vnic_info *vnic; 1870 u32 i, tbl_size; 1871 1872 rxfh->hfunc = ETH_RSS_HASH_TOP; 1873 1874 if (!bp->vnic_info) 1875 return 0; 1876 1877 vnic = &bp->vnic_info[BNXT_VNIC_DEFAULT]; 1878 if (rxfh->rss_context) { 1879 struct ethtool_rxfh_context *ctx; 1880 1881 ctx = xa_load(&bp->dev->ethtool->rss_ctx, rxfh->rss_context); 1882 if (!ctx) 1883 return -EINVAL; 1884 indir_tbl = ethtool_rxfh_context_indir(ctx); 1885 rss_ctx = ethtool_rxfh_context_priv(ctx); 1886 vnic = &rss_ctx->vnic; 1887 } 1888 1889 if (rxfh->indir && indir_tbl) { 1890 tbl_size = bnxt_get_rxfh_indir_size(dev); 1891 for (i = 0; i < tbl_size; i++) 1892 rxfh->indir[i] = indir_tbl[i]; 1893 } 1894 1895 if (rxfh->key && vnic->rss_hash_key) 1896 memcpy(rxfh->key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1897 1898 return 0; 1899 } 1900 1901 static void bnxt_modify_rss(struct bnxt *bp, struct ethtool_rxfh_context *ctx, 1902 struct bnxt_rss_ctx *rss_ctx, 1903 const struct ethtool_rxfh_param *rxfh) 1904 { 1905 if (rxfh->key) { 1906 if (rss_ctx) { 1907 memcpy(rss_ctx->vnic.rss_hash_key, rxfh->key, 1908 HW_HASH_KEY_SIZE); 1909 } else { 1910 memcpy(bp->rss_hash_key, rxfh->key, HW_HASH_KEY_SIZE); 1911 bp->rss_hash_key_updated = true; 1912 } 1913 } 1914 if (rxfh->indir) { 1915 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(bp->dev); 1916 u32 *indir_tbl = bp->rss_indir_tbl; 1917 1918 if (rss_ctx) 1919 indir_tbl = ethtool_rxfh_context_indir(ctx); 1920 for (i = 0; i < tbl_size; i++) 1921 indir_tbl[i] = rxfh->indir[i]; 1922 pad = bp->rss_indir_tbl_entries - tbl_size; 1923 if (pad) 1924 memset(&indir_tbl[i], 0, pad * sizeof(*indir_tbl)); 1925 } 1926 } 1927 1928 static int bnxt_rxfh_context_check(struct bnxt *bp, 1929 const struct ethtool_rxfh_param *rxfh, 1930 struct netlink_ext_ack *extack) 1931 { 1932 if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP) { 1933 NL_SET_ERR_MSG_MOD(extack, "RSS hash function not supported"); 1934 return -EOPNOTSUPP; 1935 } 1936 1937 if (!BNXT_SUPPORTS_MULTI_RSS_CTX(bp)) { 1938 NL_SET_ERR_MSG_MOD(extack, "RSS contexts not supported"); 1939 return -EOPNOTSUPP; 1940 } 1941 1942 if (!netif_running(bp->dev)) { 1943 NL_SET_ERR_MSG_MOD(extack, "Unable to set RSS contexts when interface is down"); 1944 return -EAGAIN; 1945 } 1946 1947 return 0; 1948 } 1949 1950 static int bnxt_create_rxfh_context(struct net_device *dev, 1951 struct ethtool_rxfh_context *ctx, 1952 const struct ethtool_rxfh_param *rxfh, 1953 struct netlink_ext_ack *extack) 1954 { 1955 struct bnxt *bp = netdev_priv(dev); 1956 struct bnxt_rss_ctx *rss_ctx; 1957 struct bnxt_vnic_info *vnic; 1958 int rc; 1959 1960 rc = bnxt_rxfh_context_check(bp, rxfh, extack); 1961 if (rc) 1962 return rc; 1963 1964 if (bp->num_rss_ctx >= BNXT_MAX_ETH_RSS_CTX) { 1965 NL_SET_ERR_MSG_FMT_MOD(extack, "Out of RSS contexts, maximum %u", 1966 BNXT_MAX_ETH_RSS_CTX); 1967 return -EINVAL; 1968 } 1969 1970 if (!bnxt_rfs_capable(bp, true)) { 1971 NL_SET_ERR_MSG_MOD(extack, "Out hardware resources"); 1972 return -ENOMEM; 1973 } 1974 1975 rss_ctx = ethtool_rxfh_context_priv(ctx); 1976 1977 bp->num_rss_ctx++; 1978 1979 vnic = &rss_ctx->vnic; 1980 vnic->rss_ctx = ctx; 1981 vnic->flags |= BNXT_VNIC_RSSCTX_FLAG; 1982 vnic->vnic_id = BNXT_VNIC_ID_INVALID; 1983 rc = bnxt_alloc_vnic_rss_table(bp, vnic); 1984 if (rc) 1985 goto out; 1986 1987 /* Populate defaults in the context */ 1988 bnxt_set_dflt_rss_indir_tbl(bp, ctx); 1989 ctx->hfunc = ETH_RSS_HASH_TOP; 1990 memcpy(vnic->rss_hash_key, bp->rss_hash_key, HW_HASH_KEY_SIZE); 1991 memcpy(ethtool_rxfh_context_key(ctx), 1992 bp->rss_hash_key, HW_HASH_KEY_SIZE); 1993 1994 rc = bnxt_hwrm_vnic_alloc(bp, vnic, 0, bp->rx_nr_rings); 1995 if (rc) { 1996 NL_SET_ERR_MSG_MOD(extack, "Unable to allocate VNIC"); 1997 goto out; 1998 } 1999 2000 rc = bnxt_hwrm_vnic_set_tpa(bp, vnic, bp->flags & BNXT_FLAG_TPA); 2001 if (rc) { 2002 NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA"); 2003 goto out; 2004 } 2005 bnxt_modify_rss(bp, ctx, rss_ctx, rxfh); 2006 2007 rc = __bnxt_setup_vnic_p5(bp, vnic); 2008 if (rc) { 2009 NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA"); 2010 goto out; 2011 } 2012 2013 rss_ctx->index = rxfh->rss_context; 2014 return 0; 2015 out: 2016 bnxt_del_one_rss_ctx(bp, rss_ctx, true); 2017 return rc; 2018 } 2019 2020 static int bnxt_modify_rxfh_context(struct net_device *dev, 2021 struct ethtool_rxfh_context *ctx, 2022 const struct ethtool_rxfh_param *rxfh, 2023 struct netlink_ext_ack *extack) 2024 { 2025 struct bnxt *bp = netdev_priv(dev); 2026 struct bnxt_rss_ctx *rss_ctx; 2027 int rc; 2028 2029 rc = bnxt_rxfh_context_check(bp, rxfh, extack); 2030 if (rc) 2031 return rc; 2032 2033 rss_ctx = ethtool_rxfh_context_priv(ctx); 2034 2035 bnxt_modify_rss(bp, ctx, rss_ctx, rxfh); 2036 2037 return bnxt_hwrm_vnic_rss_cfg_p5(bp, &rss_ctx->vnic); 2038 } 2039 2040 static int bnxt_remove_rxfh_context(struct net_device *dev, 2041 struct ethtool_rxfh_context *ctx, 2042 u32 rss_context, 2043 struct netlink_ext_ack *extack) 2044 { 2045 struct bnxt *bp = netdev_priv(dev); 2046 struct bnxt_rss_ctx *rss_ctx; 2047 2048 rss_ctx = ethtool_rxfh_context_priv(ctx); 2049 2050 bnxt_del_one_rss_ctx(bp, rss_ctx, true); 2051 return 0; 2052 } 2053 2054 static int bnxt_set_rxfh(struct net_device *dev, 2055 struct ethtool_rxfh_param *rxfh, 2056 struct netlink_ext_ack *extack) 2057 { 2058 struct bnxt *bp = netdev_priv(dev); 2059 int rc = 0; 2060 2061 if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP) 2062 return -EOPNOTSUPP; 2063 2064 bnxt_modify_rss(bp, NULL, NULL, rxfh); 2065 2066 if (netif_running(bp->dev)) { 2067 bnxt_close_nic(bp, false, false); 2068 rc = bnxt_open_nic(bp, false, false); 2069 } 2070 return rc; 2071 } 2072 2073 static void bnxt_get_drvinfo(struct net_device *dev, 2074 struct ethtool_drvinfo *info) 2075 { 2076 struct bnxt *bp = netdev_priv(dev); 2077 2078 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 2079 strscpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 2080 strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 2081 info->n_stats = bnxt_get_num_stats(bp); 2082 info->testinfo_len = bp->num_tests; 2083 /* TODO CHIMP_FW: eeprom dump details */ 2084 info->eedump_len = 0; 2085 /* TODO CHIMP FW: reg dump details */ 2086 info->regdump_len = 0; 2087 } 2088 2089 static int bnxt_get_regs_len(struct net_device *dev) 2090 { 2091 struct bnxt *bp = netdev_priv(dev); 2092 2093 if (!BNXT_PF(bp)) 2094 return -EOPNOTSUPP; 2095 2096 return BNXT_PXP_REG_LEN + bp->pcie_stat_len; 2097 } 2098 2099 static void * 2100 __bnxt_hwrm_pcie_qstats(struct bnxt *bp, struct hwrm_pcie_qstats_input *req) 2101 { 2102 struct pcie_ctx_hw_stats_v2 *hw_pcie_stats; 2103 dma_addr_t hw_pcie_stats_addr; 2104 int rc; 2105 2106 hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats), 2107 &hw_pcie_stats_addr); 2108 if (!hw_pcie_stats) 2109 return NULL; 2110 2111 req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats)); 2112 req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr); 2113 rc = hwrm_req_send(bp, req); 2114 2115 return rc ? NULL : hw_pcie_stats; 2116 } 2117 2118 #define BNXT_PCIE_32B_ENTRY(start, end) \ 2119 { offsetof(struct pcie_ctx_hw_stats_v2, start),\ 2120 offsetof(struct pcie_ctx_hw_stats_v2, end) } 2121 2122 static const struct { 2123 u16 start; 2124 u16 end; 2125 } bnxt_pcie_32b_entries[] = { 2126 BNXT_PCIE_32B_ENTRY(pcie_ltssm_histogram[0], pcie_ltssm_histogram[3]), 2127 BNXT_PCIE_32B_ENTRY(pcie_tl_credit_nph_histogram[0], unused_1), 2128 BNXT_PCIE_32B_ENTRY(pcie_rd_latency_histogram[0], unused_2), 2129 }; 2130 2131 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs, 2132 void *_p) 2133 { 2134 struct hwrm_pcie_qstats_output *resp; 2135 struct hwrm_pcie_qstats_input *req; 2136 struct bnxt *bp = netdev_priv(dev); 2137 u8 *src; 2138 2139 regs->version = 0; 2140 if (!(bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_REG_ACCESS_RESTRICTED)) 2141 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p); 2142 2143 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 2144 return; 2145 2146 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS)) 2147 return; 2148 2149 resp = hwrm_req_hold(bp, req); 2150 src = __bnxt_hwrm_pcie_qstats(bp, req); 2151 if (src) { 2152 u8 *dst = (u8 *)(_p + BNXT_PXP_REG_LEN); 2153 int i, j, len; 2154 2155 len = min(bp->pcie_stat_len, le16_to_cpu(resp->pcie_stat_size)); 2156 if (len <= sizeof(struct pcie_ctx_hw_stats)) 2157 regs->version = 1; 2158 else if (len < sizeof(struct pcie_ctx_hw_stats_v2)) 2159 regs->version = 2; 2160 else 2161 regs->version = 3; 2162 2163 for (i = 0, j = 0; i < len; ) { 2164 if (i >= bnxt_pcie_32b_entries[j].start && 2165 i <= bnxt_pcie_32b_entries[j].end) { 2166 u32 *dst32 = (u32 *)(dst + i); 2167 2168 *dst32 = le32_to_cpu(*(__le32 *)(src + i)); 2169 i += 4; 2170 if (i > bnxt_pcie_32b_entries[j].end && 2171 j < ARRAY_SIZE(bnxt_pcie_32b_entries) - 1) 2172 j++; 2173 } else { 2174 u64 *dst64 = (u64 *)(dst + i); 2175 2176 *dst64 = le64_to_cpu(*(__le64 *)(src + i)); 2177 i += 8; 2178 } 2179 } 2180 } 2181 hwrm_req_drop(bp, req); 2182 } 2183 2184 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2185 { 2186 struct bnxt *bp = netdev_priv(dev); 2187 2188 wol->supported = 0; 2189 wol->wolopts = 0; 2190 memset(&wol->sopass, 0, sizeof(wol->sopass)); 2191 if (bp->flags & BNXT_FLAG_WOL_CAP) { 2192 wol->supported = WAKE_MAGIC; 2193 if (bp->wol) 2194 wol->wolopts = WAKE_MAGIC; 2195 } 2196 } 2197 2198 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2199 { 2200 struct bnxt *bp = netdev_priv(dev); 2201 2202 if (wol->wolopts & ~WAKE_MAGIC) 2203 return -EINVAL; 2204 2205 if (wol->wolopts & WAKE_MAGIC) { 2206 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 2207 return -EINVAL; 2208 if (!bp->wol) { 2209 if (bnxt_hwrm_alloc_wol_fltr(bp)) 2210 return -EBUSY; 2211 bp->wol = 1; 2212 } 2213 } else { 2214 if (bp->wol) { 2215 if (bnxt_hwrm_free_wol_fltr(bp)) 2216 return -EBUSY; 2217 bp->wol = 0; 2218 } 2219 } 2220 return 0; 2221 } 2222 2223 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 2224 void _bnxt_fw_to_linkmode(unsigned long *mode, u16 fw_speeds) 2225 { 2226 linkmode_zero(mode); 2227 2228 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 2229 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode); 2230 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 2231 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode); 2232 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 2233 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT, mode); 2234 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 2235 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode); 2236 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 2237 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode); 2238 } 2239 2240 enum bnxt_media_type { 2241 BNXT_MEDIA_UNKNOWN = 0, 2242 BNXT_MEDIA_TP, 2243 BNXT_MEDIA_CR, 2244 BNXT_MEDIA_SR, 2245 BNXT_MEDIA_LR_ER_FR, 2246 BNXT_MEDIA_KR, 2247 BNXT_MEDIA_KX, 2248 BNXT_MEDIA_X, 2249 __BNXT_MEDIA_END, 2250 }; 2251 2252 static const enum bnxt_media_type bnxt_phy_types[] = { 2253 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR] = BNXT_MEDIA_CR, 2254 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4] = BNXT_MEDIA_KR, 2255 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR] = BNXT_MEDIA_LR_ER_FR, 2256 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR] = BNXT_MEDIA_SR, 2257 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2] = BNXT_MEDIA_KR, 2258 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX] = BNXT_MEDIA_KX, 2259 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR] = BNXT_MEDIA_KR, 2260 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASET] = BNXT_MEDIA_TP, 2261 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE] = BNXT_MEDIA_TP, 2262 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L] = BNXT_MEDIA_CR, 2263 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S] = BNXT_MEDIA_CR, 2264 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N] = BNXT_MEDIA_CR, 2265 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR] = BNXT_MEDIA_SR, 2266 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4] = BNXT_MEDIA_CR, 2267 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4] = BNXT_MEDIA_SR, 2268 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2269 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2270 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10] = BNXT_MEDIA_SR, 2271 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4] = BNXT_MEDIA_CR, 2272 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4] = BNXT_MEDIA_SR, 2273 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2274 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2275 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE] = BNXT_MEDIA_SR, 2276 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET] = BNXT_MEDIA_TP, 2277 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX] = BNXT_MEDIA_X, 2278 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX] = BNXT_MEDIA_X, 2279 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4] = BNXT_MEDIA_CR, 2280 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4] = BNXT_MEDIA_SR, 2281 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2282 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2283 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR] = BNXT_MEDIA_CR, 2284 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR] = BNXT_MEDIA_SR, 2285 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR] = BNXT_MEDIA_LR_ER_FR, 2286 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER] = BNXT_MEDIA_LR_ER_FR, 2287 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2] = BNXT_MEDIA_CR, 2288 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2] = BNXT_MEDIA_SR, 2289 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2] = BNXT_MEDIA_LR_ER_FR, 2290 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2] = BNXT_MEDIA_LR_ER_FR, 2291 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR] = BNXT_MEDIA_CR, 2292 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR] = BNXT_MEDIA_SR, 2293 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR] = BNXT_MEDIA_LR_ER_FR, 2294 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER] = BNXT_MEDIA_LR_ER_FR, 2295 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2] = BNXT_MEDIA_CR, 2296 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2] = BNXT_MEDIA_SR, 2297 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2] = BNXT_MEDIA_LR_ER_FR, 2298 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2] = BNXT_MEDIA_LR_ER_FR, 2299 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8] = BNXT_MEDIA_CR, 2300 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8] = BNXT_MEDIA_SR, 2301 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8] = BNXT_MEDIA_LR_ER_FR, 2302 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8] = BNXT_MEDIA_LR_ER_FR, 2303 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4] = BNXT_MEDIA_CR, 2304 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4] = BNXT_MEDIA_SR, 2305 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 2306 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 2307 }; 2308 2309 static enum bnxt_media_type 2310 bnxt_get_media(struct bnxt_link_info *link_info) 2311 { 2312 switch (link_info->media_type) { 2313 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP: 2314 return BNXT_MEDIA_TP; 2315 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC: 2316 return BNXT_MEDIA_CR; 2317 default: 2318 if (link_info->phy_type < ARRAY_SIZE(bnxt_phy_types)) 2319 return bnxt_phy_types[link_info->phy_type]; 2320 return BNXT_MEDIA_UNKNOWN; 2321 } 2322 } 2323 2324 enum bnxt_link_speed_indices { 2325 BNXT_LINK_SPEED_UNKNOWN = 0, 2326 BNXT_LINK_SPEED_100MB_IDX, 2327 BNXT_LINK_SPEED_1GB_IDX, 2328 BNXT_LINK_SPEED_10GB_IDX, 2329 BNXT_LINK_SPEED_25GB_IDX, 2330 BNXT_LINK_SPEED_40GB_IDX, 2331 BNXT_LINK_SPEED_50GB_IDX, 2332 BNXT_LINK_SPEED_100GB_IDX, 2333 BNXT_LINK_SPEED_200GB_IDX, 2334 BNXT_LINK_SPEED_400GB_IDX, 2335 __BNXT_LINK_SPEED_END 2336 }; 2337 2338 static enum bnxt_link_speed_indices bnxt_fw_speed_idx(u16 speed) 2339 { 2340 switch (speed) { 2341 case BNXT_LINK_SPEED_100MB: return BNXT_LINK_SPEED_100MB_IDX; 2342 case BNXT_LINK_SPEED_1GB: return BNXT_LINK_SPEED_1GB_IDX; 2343 case BNXT_LINK_SPEED_10GB: return BNXT_LINK_SPEED_10GB_IDX; 2344 case BNXT_LINK_SPEED_25GB: return BNXT_LINK_SPEED_25GB_IDX; 2345 case BNXT_LINK_SPEED_40GB: return BNXT_LINK_SPEED_40GB_IDX; 2346 case BNXT_LINK_SPEED_50GB: 2347 case BNXT_LINK_SPEED_50GB_PAM4: 2348 return BNXT_LINK_SPEED_50GB_IDX; 2349 case BNXT_LINK_SPEED_100GB: 2350 case BNXT_LINK_SPEED_100GB_PAM4: 2351 case BNXT_LINK_SPEED_100GB_PAM4_112: 2352 return BNXT_LINK_SPEED_100GB_IDX; 2353 case BNXT_LINK_SPEED_200GB: 2354 case BNXT_LINK_SPEED_200GB_PAM4: 2355 case BNXT_LINK_SPEED_200GB_PAM4_112: 2356 return BNXT_LINK_SPEED_200GB_IDX; 2357 case BNXT_LINK_SPEED_400GB: 2358 case BNXT_LINK_SPEED_400GB_PAM4: 2359 case BNXT_LINK_SPEED_400GB_PAM4_112: 2360 return BNXT_LINK_SPEED_400GB_IDX; 2361 default: return BNXT_LINK_SPEED_UNKNOWN; 2362 } 2363 } 2364 2365 static const enum ethtool_link_mode_bit_indices 2366 bnxt_link_modes[__BNXT_LINK_SPEED_END][BNXT_SIG_MODE_MAX][__BNXT_MEDIA_END] = { 2367 [BNXT_LINK_SPEED_100MB_IDX] = { 2368 { 2369 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_100baseT_Full_BIT, 2370 }, 2371 }, 2372 [BNXT_LINK_SPEED_1GB_IDX] = { 2373 { 2374 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 2375 /* historically baseT, but DAC is more correctly baseX */ 2376 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 2377 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2378 [BNXT_MEDIA_X] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 2379 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2380 }, 2381 }, 2382 [BNXT_LINK_SPEED_10GB_IDX] = { 2383 { 2384 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 2385 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 2386 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 2387 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 2388 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 2389 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 2390 }, 2391 }, 2392 [BNXT_LINK_SPEED_25GB_IDX] = { 2393 { 2394 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 2395 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 2396 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 2397 }, 2398 }, 2399 [BNXT_LINK_SPEED_40GB_IDX] = { 2400 { 2401 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 2402 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 2403 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 2404 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 2405 }, 2406 }, 2407 [BNXT_LINK_SPEED_50GB_IDX] = { 2408 [BNXT_SIG_MODE_NRZ] = { 2409 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 2410 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 2411 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 2412 }, 2413 [BNXT_SIG_MODE_PAM4] = { 2414 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 2415 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 2416 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 2417 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 2418 }, 2419 }, 2420 [BNXT_LINK_SPEED_100GB_IDX] = { 2421 [BNXT_SIG_MODE_NRZ] = { 2422 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 2423 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 2424 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 2425 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 2426 }, 2427 [BNXT_SIG_MODE_PAM4] = { 2428 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 2429 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 2430 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 2431 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 2432 }, 2433 [BNXT_SIG_MODE_PAM4_112] = { 2434 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR_Full_BIT, 2435 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR_Full_BIT, 2436 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR_Full_BIT, 2437 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT, 2438 }, 2439 }, 2440 [BNXT_LINK_SPEED_200GB_IDX] = { 2441 [BNXT_SIG_MODE_PAM4] = { 2442 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT, 2443 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 2444 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 2445 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 2446 }, 2447 [BNXT_SIG_MODE_PAM4_112] = { 2448 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT, 2449 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT, 2450 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT, 2451 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT, 2452 }, 2453 }, 2454 [BNXT_LINK_SPEED_400GB_IDX] = { 2455 [BNXT_SIG_MODE_PAM4] = { 2456 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT, 2457 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT, 2458 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT, 2459 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT, 2460 }, 2461 [BNXT_SIG_MODE_PAM4_112] = { 2462 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT, 2463 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT, 2464 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT, 2465 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT, 2466 }, 2467 }, 2468 }; 2469 2470 #define BNXT_LINK_MODE_UNKNOWN -1 2471 2472 static enum ethtool_link_mode_bit_indices 2473 bnxt_get_link_mode(struct bnxt_link_info *link_info) 2474 { 2475 enum ethtool_link_mode_bit_indices link_mode; 2476 enum bnxt_link_speed_indices speed; 2477 enum bnxt_media_type media; 2478 u8 sig_mode; 2479 2480 if (link_info->phy_link_status != BNXT_LINK_LINK) 2481 return BNXT_LINK_MODE_UNKNOWN; 2482 2483 media = bnxt_get_media(link_info); 2484 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 2485 speed = bnxt_fw_speed_idx(link_info->link_speed); 2486 sig_mode = link_info->active_fec_sig_mode & 2487 PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK; 2488 } else { 2489 speed = bnxt_fw_speed_idx(link_info->req_link_speed); 2490 sig_mode = link_info->req_signal_mode; 2491 } 2492 if (sig_mode >= BNXT_SIG_MODE_MAX) 2493 return BNXT_LINK_MODE_UNKNOWN; 2494 2495 /* Note ETHTOOL_LINK_MODE_10baseT_Half_BIT == 0 is a legal Linux 2496 * link mode, but since no such devices exist, the zeroes in the 2497 * map can be conveniently used to represent unknown link modes. 2498 */ 2499 link_mode = bnxt_link_modes[speed][sig_mode][media]; 2500 if (!link_mode) 2501 return BNXT_LINK_MODE_UNKNOWN; 2502 2503 switch (link_mode) { 2504 case ETHTOOL_LINK_MODE_100baseT_Full_BIT: 2505 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2506 link_mode = ETHTOOL_LINK_MODE_100baseT_Half_BIT; 2507 break; 2508 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT: 2509 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2510 link_mode = ETHTOOL_LINK_MODE_1000baseT_Half_BIT; 2511 break; 2512 default: 2513 break; 2514 } 2515 2516 return link_mode; 2517 } 2518 2519 static void bnxt_get_ethtool_modes(struct bnxt_link_info *link_info, 2520 struct ethtool_link_ksettings *lk_ksettings) 2521 { 2522 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2523 2524 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) { 2525 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2526 lk_ksettings->link_modes.supported); 2527 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2528 lk_ksettings->link_modes.supported); 2529 } 2530 2531 if (link_info->support_auto_speeds || link_info->support_auto_speeds2 || 2532 link_info->support_pam4_auto_speeds) 2533 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2534 lk_ksettings->link_modes.supported); 2535 2536 if (~link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 2537 return; 2538 2539 if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_RX) 2540 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2541 lk_ksettings->link_modes.advertising); 2542 if (hweight8(link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) == 1) 2543 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2544 lk_ksettings->link_modes.advertising); 2545 if (link_info->lp_pause & BNXT_LINK_PAUSE_RX) 2546 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2547 lk_ksettings->link_modes.lp_advertising); 2548 if (hweight8(link_info->lp_pause & BNXT_LINK_PAUSE_BOTH) == 1) 2549 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2550 lk_ksettings->link_modes.lp_advertising); 2551 } 2552 2553 static const u16 bnxt_nrz_speed_masks[] = { 2554 [BNXT_LINK_SPEED_100MB_IDX] = BNXT_LINK_SPEED_MSK_100MB, 2555 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEED_MSK_1GB, 2556 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEED_MSK_10GB, 2557 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEED_MSK_25GB, 2558 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEED_MSK_40GB, 2559 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEED_MSK_50GB, 2560 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEED_MSK_100GB, 2561 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2562 }; 2563 2564 static const u16 bnxt_pam4_speed_masks[] = { 2565 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_50GB, 2566 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_100GB, 2567 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_200GB, 2568 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2569 }; 2570 2571 static const u16 bnxt_nrz_speeds2_masks[] = { 2572 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEEDS2_MSK_1GB, 2573 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEEDS2_MSK_10GB, 2574 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEEDS2_MSK_25GB, 2575 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEEDS2_MSK_40GB, 2576 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB, 2577 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB, 2578 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 2579 }; 2580 2581 static const u16 bnxt_pam4_speeds2_masks[] = { 2582 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB_PAM4, 2583 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4, 2584 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4, 2585 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4, 2586 }; 2587 2588 static const u16 bnxt_pam4_112_speeds2_masks[] = { 2589 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112, 2590 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112, 2591 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112, 2592 }; 2593 2594 static enum bnxt_link_speed_indices 2595 bnxt_encoding_speed_idx(u8 sig_mode, u16 phy_flags, u16 speed_msk) 2596 { 2597 const u16 *speeds; 2598 int idx, len; 2599 2600 switch (sig_mode) { 2601 case BNXT_SIG_MODE_NRZ: 2602 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2603 speeds = bnxt_nrz_speeds2_masks; 2604 len = ARRAY_SIZE(bnxt_nrz_speeds2_masks); 2605 } else { 2606 speeds = bnxt_nrz_speed_masks; 2607 len = ARRAY_SIZE(bnxt_nrz_speed_masks); 2608 } 2609 break; 2610 case BNXT_SIG_MODE_PAM4: 2611 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2612 speeds = bnxt_pam4_speeds2_masks; 2613 len = ARRAY_SIZE(bnxt_pam4_speeds2_masks); 2614 } else { 2615 speeds = bnxt_pam4_speed_masks; 2616 len = ARRAY_SIZE(bnxt_pam4_speed_masks); 2617 } 2618 break; 2619 case BNXT_SIG_MODE_PAM4_112: 2620 speeds = bnxt_pam4_112_speeds2_masks; 2621 len = ARRAY_SIZE(bnxt_pam4_112_speeds2_masks); 2622 break; 2623 default: 2624 return BNXT_LINK_SPEED_UNKNOWN; 2625 } 2626 2627 for (idx = 0; idx < len; idx++) { 2628 if (speeds[idx] == speed_msk) 2629 return idx; 2630 } 2631 2632 return BNXT_LINK_SPEED_UNKNOWN; 2633 } 2634 2635 #define BNXT_FW_SPEED_MSK_BITS 16 2636 2637 static void 2638 __bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media, 2639 u8 sig_mode, u16 phy_flags, unsigned long *et_mask) 2640 { 2641 enum ethtool_link_mode_bit_indices link_mode; 2642 enum bnxt_link_speed_indices speed; 2643 u8 bit; 2644 2645 for_each_set_bit(bit, &fw_mask, BNXT_FW_SPEED_MSK_BITS) { 2646 speed = bnxt_encoding_speed_idx(sig_mode, phy_flags, 1 << bit); 2647 if (!speed) 2648 continue; 2649 2650 link_mode = bnxt_link_modes[speed][sig_mode][media]; 2651 if (!link_mode) 2652 continue; 2653 2654 linkmode_set_bit(link_mode, et_mask); 2655 } 2656 } 2657 2658 static void 2659 bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media, 2660 u8 sig_mode, u16 phy_flags, unsigned long *et_mask) 2661 { 2662 if (media) { 2663 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags, 2664 et_mask); 2665 return; 2666 } 2667 2668 /* list speeds for all media if unknown */ 2669 for (media = 1; media < __BNXT_MEDIA_END; media++) 2670 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags, 2671 et_mask); 2672 } 2673 2674 static void 2675 bnxt_get_all_ethtool_support_speeds(struct bnxt_link_info *link_info, 2676 enum bnxt_media_type media, 2677 struct ethtool_link_ksettings *lk_ksettings) 2678 { 2679 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2680 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0; 2681 u16 phy_flags = bp->phy_flags; 2682 2683 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2684 sp_nrz = link_info->support_speeds2; 2685 sp_pam4 = link_info->support_speeds2; 2686 sp_pam4_112 = link_info->support_speeds2; 2687 } else { 2688 sp_nrz = link_info->support_speeds; 2689 sp_pam4 = link_info->support_pam4_speeds; 2690 } 2691 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags, 2692 lk_ksettings->link_modes.supported); 2693 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags, 2694 lk_ksettings->link_modes.supported); 2695 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112, 2696 phy_flags, lk_ksettings->link_modes.supported); 2697 } 2698 2699 static void 2700 bnxt_get_all_ethtool_adv_speeds(struct bnxt_link_info *link_info, 2701 enum bnxt_media_type media, 2702 struct ethtool_link_ksettings *lk_ksettings) 2703 { 2704 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2705 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0; 2706 u16 phy_flags = bp->phy_flags; 2707 2708 sp_nrz = link_info->advertising; 2709 if (phy_flags & BNXT_PHY_FL_SPEEDS2) { 2710 sp_pam4 = link_info->advertising; 2711 sp_pam4_112 = link_info->advertising; 2712 } else { 2713 sp_pam4 = link_info->advertising_pam4; 2714 } 2715 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags, 2716 lk_ksettings->link_modes.advertising); 2717 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags, 2718 lk_ksettings->link_modes.advertising); 2719 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112, 2720 phy_flags, lk_ksettings->link_modes.advertising); 2721 } 2722 2723 static void 2724 bnxt_get_all_ethtool_lp_speeds(struct bnxt_link_info *link_info, 2725 enum bnxt_media_type media, 2726 struct ethtool_link_ksettings *lk_ksettings) 2727 { 2728 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2729 u16 phy_flags = bp->phy_flags; 2730 2731 bnxt_get_ethtool_speeds(link_info->lp_auto_link_speeds, media, 2732 BNXT_SIG_MODE_NRZ, phy_flags, 2733 lk_ksettings->link_modes.lp_advertising); 2734 bnxt_get_ethtool_speeds(link_info->lp_auto_pam4_link_speeds, media, 2735 BNXT_SIG_MODE_PAM4, phy_flags, 2736 lk_ksettings->link_modes.lp_advertising); 2737 } 2738 2739 static void bnxt_update_speed(u32 *delta, bool installed_media, u16 *speeds, 2740 u16 speed_msk, const unsigned long *et_mask, 2741 enum ethtool_link_mode_bit_indices mode) 2742 { 2743 bool mode_desired = linkmode_test_bit(mode, et_mask); 2744 2745 if (!mode) 2746 return; 2747 2748 /* enabled speeds for installed media should override */ 2749 if (installed_media && mode_desired) { 2750 *speeds |= speed_msk; 2751 *delta |= speed_msk; 2752 return; 2753 } 2754 2755 /* many to one mapping, only allow one change per fw_speed bit */ 2756 if (!(*delta & speed_msk) && (mode_desired == !(*speeds & speed_msk))) { 2757 *speeds ^= speed_msk; 2758 *delta |= speed_msk; 2759 } 2760 } 2761 2762 static void bnxt_set_ethtool_speeds(struct bnxt_link_info *link_info, 2763 const unsigned long *et_mask) 2764 { 2765 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 2766 u16 const *sp_msks, *sp_pam4_msks, *sp_pam4_112_msks; 2767 enum bnxt_media_type media = bnxt_get_media(link_info); 2768 u16 *adv, *adv_pam4, *adv_pam4_112 = NULL; 2769 u32 delta_pam4_112 = 0; 2770 u32 delta_pam4 = 0; 2771 u32 delta_nrz = 0; 2772 int i, m; 2773 2774 adv = &link_info->advertising; 2775 if (bp->phy_flags & BNXT_PHY_FL_SPEEDS2) { 2776 adv_pam4 = &link_info->advertising; 2777 adv_pam4_112 = &link_info->advertising; 2778 sp_msks = bnxt_nrz_speeds2_masks; 2779 sp_pam4_msks = bnxt_pam4_speeds2_masks; 2780 sp_pam4_112_msks = bnxt_pam4_112_speeds2_masks; 2781 } else { 2782 adv_pam4 = &link_info->advertising_pam4; 2783 sp_msks = bnxt_nrz_speed_masks; 2784 sp_pam4_msks = bnxt_pam4_speed_masks; 2785 } 2786 for (i = 1; i < __BNXT_LINK_SPEED_END; i++) { 2787 /* accept any legal media from user */ 2788 for (m = 1; m < __BNXT_MEDIA_END; m++) { 2789 bnxt_update_speed(&delta_nrz, m == media, 2790 adv, sp_msks[i], et_mask, 2791 bnxt_link_modes[i][BNXT_SIG_MODE_NRZ][m]); 2792 bnxt_update_speed(&delta_pam4, m == media, 2793 adv_pam4, sp_pam4_msks[i], et_mask, 2794 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4][m]); 2795 if (!adv_pam4_112) 2796 continue; 2797 2798 bnxt_update_speed(&delta_pam4_112, m == media, 2799 adv_pam4_112, sp_pam4_112_msks[i], et_mask, 2800 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4_112][m]); 2801 } 2802 } 2803 } 2804 2805 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info, 2806 struct ethtool_link_ksettings *lk_ksettings) 2807 { 2808 u16 fec_cfg = link_info->fec_cfg; 2809 2810 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) { 2811 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 2812 lk_ksettings->link_modes.advertising); 2813 return; 2814 } 2815 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 2816 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 2817 lk_ksettings->link_modes.advertising); 2818 if (fec_cfg & BNXT_FEC_ENC_RS) 2819 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 2820 lk_ksettings->link_modes.advertising); 2821 if (fec_cfg & BNXT_FEC_ENC_LLRS) 2822 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 2823 lk_ksettings->link_modes.advertising); 2824 } 2825 2826 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info, 2827 struct ethtool_link_ksettings *lk_ksettings) 2828 { 2829 u16 fec_cfg = link_info->fec_cfg; 2830 2831 if (fec_cfg & BNXT_FEC_NONE) { 2832 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 2833 lk_ksettings->link_modes.supported); 2834 return; 2835 } 2836 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP) 2837 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 2838 lk_ksettings->link_modes.supported); 2839 if (fec_cfg & BNXT_FEC_ENC_RS_CAP) 2840 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 2841 lk_ksettings->link_modes.supported); 2842 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP) 2843 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 2844 lk_ksettings->link_modes.supported); 2845 } 2846 2847 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 2848 { 2849 switch (fw_link_speed) { 2850 case BNXT_LINK_SPEED_100MB: 2851 return SPEED_100; 2852 case BNXT_LINK_SPEED_1GB: 2853 return SPEED_1000; 2854 case BNXT_LINK_SPEED_2_5GB: 2855 return SPEED_2500; 2856 case BNXT_LINK_SPEED_10GB: 2857 return SPEED_10000; 2858 case BNXT_LINK_SPEED_20GB: 2859 return SPEED_20000; 2860 case BNXT_LINK_SPEED_25GB: 2861 return SPEED_25000; 2862 case BNXT_LINK_SPEED_40GB: 2863 return SPEED_40000; 2864 case BNXT_LINK_SPEED_50GB: 2865 case BNXT_LINK_SPEED_50GB_PAM4: 2866 return SPEED_50000; 2867 case BNXT_LINK_SPEED_100GB: 2868 case BNXT_LINK_SPEED_100GB_PAM4: 2869 case BNXT_LINK_SPEED_100GB_PAM4_112: 2870 return SPEED_100000; 2871 case BNXT_LINK_SPEED_200GB: 2872 case BNXT_LINK_SPEED_200GB_PAM4: 2873 case BNXT_LINK_SPEED_200GB_PAM4_112: 2874 return SPEED_200000; 2875 case BNXT_LINK_SPEED_400GB: 2876 case BNXT_LINK_SPEED_400GB_PAM4: 2877 case BNXT_LINK_SPEED_400GB_PAM4_112: 2878 return SPEED_400000; 2879 default: 2880 return SPEED_UNKNOWN; 2881 } 2882 } 2883 2884 static void bnxt_get_default_speeds(struct ethtool_link_ksettings *lk_ksettings, 2885 struct bnxt_link_info *link_info) 2886 { 2887 struct ethtool_link_settings *base = &lk_ksettings->base; 2888 2889 if (link_info->link_state == BNXT_LINK_STATE_UP) { 2890 base->speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 2891 base->duplex = DUPLEX_HALF; 2892 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 2893 base->duplex = DUPLEX_FULL; 2894 lk_ksettings->lanes = link_info->active_lanes; 2895 } else if (!link_info->autoneg) { 2896 base->speed = bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 2897 base->duplex = DUPLEX_HALF; 2898 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 2899 base->duplex = DUPLEX_FULL; 2900 } 2901 } 2902 2903 static int bnxt_get_link_ksettings(struct net_device *dev, 2904 struct ethtool_link_ksettings *lk_ksettings) 2905 { 2906 struct ethtool_link_settings *base = &lk_ksettings->base; 2907 enum ethtool_link_mode_bit_indices link_mode; 2908 struct bnxt *bp = netdev_priv(dev); 2909 struct bnxt_link_info *link_info; 2910 enum bnxt_media_type media; 2911 2912 ethtool_link_ksettings_zero_link_mode(lk_ksettings, lp_advertising); 2913 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 2914 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 2915 base->duplex = DUPLEX_UNKNOWN; 2916 base->speed = SPEED_UNKNOWN; 2917 link_info = &bp->link_info; 2918 2919 mutex_lock(&bp->link_lock); 2920 bnxt_get_ethtool_modes(link_info, lk_ksettings); 2921 media = bnxt_get_media(link_info); 2922 bnxt_get_all_ethtool_support_speeds(link_info, media, lk_ksettings); 2923 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings); 2924 link_mode = bnxt_get_link_mode(link_info); 2925 if (link_mode != BNXT_LINK_MODE_UNKNOWN) 2926 ethtool_params_from_link_mode(lk_ksettings, link_mode); 2927 else 2928 bnxt_get_default_speeds(lk_ksettings, link_info); 2929 2930 if (link_info->autoneg) { 2931 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings); 2932 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2933 lk_ksettings->link_modes.advertising); 2934 base->autoneg = AUTONEG_ENABLE; 2935 bnxt_get_all_ethtool_adv_speeds(link_info, media, lk_ksettings); 2936 if (link_info->phy_link_status == BNXT_LINK_LINK) 2937 bnxt_get_all_ethtool_lp_speeds(link_info, media, 2938 lk_ksettings); 2939 } else { 2940 base->autoneg = AUTONEG_DISABLE; 2941 } 2942 2943 base->port = PORT_NONE; 2944 if (media == BNXT_MEDIA_TP) { 2945 base->port = PORT_TP; 2946 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2947 lk_ksettings->link_modes.supported); 2948 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2949 lk_ksettings->link_modes.advertising); 2950 } else if (media == BNXT_MEDIA_KR) { 2951 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, 2952 lk_ksettings->link_modes.supported); 2953 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, 2954 lk_ksettings->link_modes.advertising); 2955 } else { 2956 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 2957 lk_ksettings->link_modes.supported); 2958 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 2959 lk_ksettings->link_modes.advertising); 2960 2961 if (media == BNXT_MEDIA_CR) 2962 base->port = PORT_DA; 2963 else 2964 base->port = PORT_FIBRE; 2965 } 2966 base->phy_address = link_info->phy_addr; 2967 mutex_unlock(&bp->link_lock); 2968 2969 return 0; 2970 } 2971 2972 static int 2973 bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed, u32 lanes) 2974 { 2975 struct bnxt *bp = netdev_priv(dev); 2976 struct bnxt_link_info *link_info = &bp->link_info; 2977 u16 support_pam4_spds = link_info->support_pam4_speeds; 2978 u16 support_spds2 = link_info->support_speeds2; 2979 u16 support_spds = link_info->support_speeds; 2980 u8 sig_mode = BNXT_SIG_MODE_NRZ; 2981 u32 lanes_needed = 1; 2982 u16 fw_speed = 0; 2983 2984 switch (ethtool_speed) { 2985 case SPEED_100: 2986 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 2987 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB; 2988 break; 2989 case SPEED_1000: 2990 if ((support_spds & BNXT_LINK_SPEED_MSK_1GB) || 2991 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_1GB)) 2992 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 2993 break; 2994 case SPEED_2500: 2995 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 2996 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB; 2997 break; 2998 case SPEED_10000: 2999 if ((support_spds & BNXT_LINK_SPEED_MSK_10GB) || 3000 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_10GB)) 3001 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 3002 break; 3003 case SPEED_20000: 3004 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) { 3005 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB; 3006 lanes_needed = 2; 3007 } 3008 break; 3009 case SPEED_25000: 3010 if ((support_spds & BNXT_LINK_SPEED_MSK_25GB) || 3011 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_25GB)) 3012 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 3013 break; 3014 case SPEED_40000: 3015 if ((support_spds & BNXT_LINK_SPEED_MSK_40GB) || 3016 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_40GB)) { 3017 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 3018 lanes_needed = 4; 3019 } 3020 break; 3021 case SPEED_50000: 3022 if (((support_spds & BNXT_LINK_SPEED_MSK_50GB) || 3023 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB)) && 3024 lanes != 1) { 3025 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 3026 lanes_needed = 2; 3027 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) { 3028 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB; 3029 sig_mode = BNXT_SIG_MODE_PAM4; 3030 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB_PAM4) { 3031 fw_speed = BNXT_LINK_SPEED_50GB_PAM4; 3032 sig_mode = BNXT_SIG_MODE_PAM4; 3033 } 3034 break; 3035 case SPEED_100000: 3036 if (((support_spds & BNXT_LINK_SPEED_MSK_100GB) || 3037 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB)) && 3038 lanes != 2 && lanes != 1) { 3039 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB; 3040 lanes_needed = 4; 3041 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) { 3042 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB; 3043 sig_mode = BNXT_SIG_MODE_PAM4; 3044 lanes_needed = 2; 3045 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4) && 3046 lanes != 1) { 3047 fw_speed = BNXT_LINK_SPEED_100GB_PAM4; 3048 sig_mode = BNXT_SIG_MODE_PAM4; 3049 lanes_needed = 2; 3050 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112) { 3051 fw_speed = BNXT_LINK_SPEED_100GB_PAM4_112; 3052 sig_mode = BNXT_SIG_MODE_PAM4_112; 3053 } 3054 break; 3055 case SPEED_200000: 3056 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) { 3057 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB; 3058 sig_mode = BNXT_SIG_MODE_PAM4; 3059 lanes_needed = 4; 3060 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4) && 3061 lanes != 2) { 3062 fw_speed = BNXT_LINK_SPEED_200GB_PAM4; 3063 sig_mode = BNXT_SIG_MODE_PAM4; 3064 lanes_needed = 4; 3065 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112) { 3066 fw_speed = BNXT_LINK_SPEED_200GB_PAM4_112; 3067 sig_mode = BNXT_SIG_MODE_PAM4_112; 3068 lanes_needed = 2; 3069 } 3070 break; 3071 case SPEED_400000: 3072 if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4) && 3073 lanes != 4) { 3074 fw_speed = BNXT_LINK_SPEED_400GB_PAM4; 3075 sig_mode = BNXT_SIG_MODE_PAM4; 3076 lanes_needed = 8; 3077 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112) { 3078 fw_speed = BNXT_LINK_SPEED_400GB_PAM4_112; 3079 sig_mode = BNXT_SIG_MODE_PAM4_112; 3080 lanes_needed = 4; 3081 } 3082 break; 3083 } 3084 3085 if (!fw_speed) { 3086 netdev_err(dev, "unsupported speed!\n"); 3087 return -EINVAL; 3088 } 3089 3090 if (lanes && lanes != lanes_needed) { 3091 netdev_err(dev, "unsupported number of lanes for speed\n"); 3092 return -EINVAL; 3093 } 3094 3095 if (link_info->req_link_speed == fw_speed && 3096 link_info->req_signal_mode == sig_mode && 3097 link_info->autoneg == 0) 3098 return -EALREADY; 3099 3100 link_info->req_link_speed = fw_speed; 3101 link_info->req_signal_mode = sig_mode; 3102 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 3103 link_info->autoneg = 0; 3104 link_info->advertising = 0; 3105 link_info->advertising_pam4 = 0; 3106 3107 return 0; 3108 } 3109 3110 u16 bnxt_get_fw_auto_link_speeds(const unsigned long *mode) 3111 { 3112 u16 fw_speed_mask = 0; 3113 3114 if (linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode) || 3115 linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mode)) 3116 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 3117 3118 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode) || 3119 linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, mode)) 3120 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 3121 3122 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode)) 3123 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 3124 3125 if (linkmode_test_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode)) 3126 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 3127 3128 return fw_speed_mask; 3129 } 3130 3131 static int bnxt_set_link_ksettings(struct net_device *dev, 3132 const struct ethtool_link_ksettings *lk_ksettings) 3133 { 3134 struct bnxt *bp = netdev_priv(dev); 3135 struct bnxt_link_info *link_info = &bp->link_info; 3136 const struct ethtool_link_settings *base = &lk_ksettings->base; 3137 bool set_pause = false; 3138 u32 speed, lanes = 0; 3139 int rc = 0; 3140 3141 if (!BNXT_PHY_CFG_ABLE(bp)) 3142 return -EOPNOTSUPP; 3143 3144 mutex_lock(&bp->link_lock); 3145 if (base->autoneg == AUTONEG_ENABLE) { 3146 bnxt_set_ethtool_speeds(link_info, 3147 lk_ksettings->link_modes.advertising); 3148 link_info->autoneg |= BNXT_AUTONEG_SPEED; 3149 if (!link_info->advertising && !link_info->advertising_pam4) { 3150 link_info->advertising = link_info->support_auto_speeds; 3151 link_info->advertising_pam4 = 3152 link_info->support_pam4_auto_speeds; 3153 } 3154 /* any change to autoneg will cause link change, therefore the 3155 * driver should put back the original pause setting in autoneg 3156 */ 3157 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 3158 set_pause = true; 3159 } else { 3160 u8 phy_type = link_info->phy_type; 3161 3162 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 3163 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 3164 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 3165 netdev_err(dev, "10GBase-T devices must autoneg\n"); 3166 rc = -EINVAL; 3167 goto set_setting_exit; 3168 } 3169 if (base->duplex == DUPLEX_HALF) { 3170 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 3171 rc = -EINVAL; 3172 goto set_setting_exit; 3173 } 3174 speed = base->speed; 3175 lanes = lk_ksettings->lanes; 3176 rc = bnxt_force_link_speed(dev, speed, lanes); 3177 if (rc) { 3178 if (rc == -EALREADY) 3179 rc = 0; 3180 goto set_setting_exit; 3181 } 3182 } 3183 3184 if (netif_running(dev)) 3185 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 3186 3187 set_setting_exit: 3188 mutex_unlock(&bp->link_lock); 3189 return rc; 3190 } 3191 3192 static int bnxt_get_fecparam(struct net_device *dev, 3193 struct ethtool_fecparam *fec) 3194 { 3195 struct bnxt *bp = netdev_priv(dev); 3196 struct bnxt_link_info *link_info; 3197 u8 active_fec; 3198 u16 fec_cfg; 3199 3200 link_info = &bp->link_info; 3201 fec_cfg = link_info->fec_cfg; 3202 active_fec = link_info->active_fec_sig_mode & 3203 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK; 3204 if (fec_cfg & BNXT_FEC_NONE) { 3205 fec->fec = ETHTOOL_FEC_NONE; 3206 fec->active_fec = ETHTOOL_FEC_NONE; 3207 return 0; 3208 } 3209 if (fec_cfg & BNXT_FEC_AUTONEG) 3210 fec->fec |= ETHTOOL_FEC_AUTO; 3211 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 3212 fec->fec |= ETHTOOL_FEC_BASER; 3213 if (fec_cfg & BNXT_FEC_ENC_RS) 3214 fec->fec |= ETHTOOL_FEC_RS; 3215 if (fec_cfg & BNXT_FEC_ENC_LLRS) 3216 fec->fec |= ETHTOOL_FEC_LLRS; 3217 3218 switch (active_fec) { 3219 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE: 3220 fec->active_fec |= ETHTOOL_FEC_BASER; 3221 break; 3222 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE: 3223 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE: 3224 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE: 3225 fec->active_fec |= ETHTOOL_FEC_RS; 3226 break; 3227 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE: 3228 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE: 3229 fec->active_fec |= ETHTOOL_FEC_LLRS; 3230 break; 3231 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE: 3232 fec->active_fec |= ETHTOOL_FEC_OFF; 3233 break; 3234 } 3235 return 0; 3236 } 3237 3238 static const struct ethtool_fec_hist_range bnxt_fec_ranges[] = { 3239 { 0, 0}, 3240 { 1, 1}, 3241 { 2, 2}, 3242 { 3, 3}, 3243 { 4, 4}, 3244 { 5, 5}, 3245 { 6, 6}, 3246 { 7, 7}, 3247 { 8, 8}, 3248 { 9, 9}, 3249 { 10, 10}, 3250 { 11, 11}, 3251 { 12, 12}, 3252 { 13, 13}, 3253 { 14, 14}, 3254 { 15, 15}, 3255 { 0, 0}, 3256 }; 3257 3258 static void bnxt_hwrm_port_phy_fdrstat(struct bnxt *bp, 3259 struct ethtool_fec_hist *hist) 3260 { 3261 struct ethtool_fec_hist_value *values = hist->values; 3262 struct hwrm_port_phy_fdrstat_output *resp; 3263 struct hwrm_port_phy_fdrstat_input *req; 3264 int rc, i; 3265 3266 if (!(bp->phy_flags & BNXT_PHY_FL_FDRSTATS)) 3267 return; 3268 3269 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_FDRSTAT); 3270 if (rc) 3271 return; 3272 3273 req->port_id = cpu_to_le16(bp->pf.port_id); 3274 req->ops = cpu_to_le16(PORT_PHY_FDRSTAT_REQ_OPS_COUNTER); 3275 resp = hwrm_req_hold(bp, req); 3276 rc = hwrm_req_send(bp, req); 3277 if (!rc) { 3278 hist->ranges = bnxt_fec_ranges; 3279 for (i = 0; i <= 15; i++) { 3280 __le64 sum = resp->accumulated_codewords_err_s[i]; 3281 3282 values[i].sum = le64_to_cpu(sum); 3283 } 3284 } 3285 hwrm_req_drop(bp, req); 3286 } 3287 3288 static void bnxt_get_fec_stats(struct net_device *dev, 3289 struct ethtool_fec_stats *fec_stats, 3290 struct ethtool_fec_hist *hist) 3291 { 3292 struct bnxt *bp = netdev_priv(dev); 3293 u64 *rx; 3294 3295 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 3296 return; 3297 3298 rx = bp->rx_port_stats_ext.sw_stats; 3299 fec_stats->corrected_bits.total = 3300 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits)); 3301 3302 if (bp->fw_rx_stats_ext_size <= BNXT_RX_STATS_EXT_NUM_LEGACY) 3303 return; 3304 3305 fec_stats->corrected_blocks.total = 3306 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)); 3307 fec_stats->uncorrectable_blocks.total = 3308 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_uncorrectable_blocks)); 3309 bnxt_hwrm_port_phy_fdrstat(bp, hist); 3310 } 3311 3312 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info, 3313 u32 fec) 3314 { 3315 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE; 3316 3317 if (fec & ETHTOOL_FEC_BASER) 3318 fw_fec |= BNXT_FEC_BASE_R_ON(link_info); 3319 else if (fec & ETHTOOL_FEC_RS) 3320 fw_fec |= BNXT_FEC_RS_ON(link_info); 3321 else if (fec & ETHTOOL_FEC_LLRS) 3322 fw_fec |= BNXT_FEC_LLRS_ON; 3323 return fw_fec; 3324 } 3325 3326 static int bnxt_set_fecparam(struct net_device *dev, 3327 struct ethtool_fecparam *fecparam) 3328 { 3329 struct hwrm_port_phy_cfg_input *req; 3330 struct bnxt *bp = netdev_priv(dev); 3331 struct bnxt_link_info *link_info; 3332 u32 new_cfg, fec = fecparam->fec; 3333 u16 fec_cfg; 3334 int rc; 3335 3336 link_info = &bp->link_info; 3337 fec_cfg = link_info->fec_cfg; 3338 if (fec_cfg & BNXT_FEC_NONE) 3339 return -EOPNOTSUPP; 3340 3341 if (fec & ETHTOOL_FEC_OFF) { 3342 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE | 3343 BNXT_FEC_ALL_OFF(link_info); 3344 goto apply_fec; 3345 } 3346 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) || 3347 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) || 3348 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) || 3349 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP))) 3350 return -EINVAL; 3351 3352 if (fec & ETHTOOL_FEC_AUTO) { 3353 if (!link_info->autoneg) 3354 return -EINVAL; 3355 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE; 3356 } else { 3357 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec); 3358 } 3359 3360 apply_fec: 3361 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 3362 if (rc) 3363 return rc; 3364 req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 3365 rc = hwrm_req_send(bp, req); 3366 /* update current settings */ 3367 if (!rc) { 3368 mutex_lock(&bp->link_lock); 3369 bnxt_update_link(bp, false); 3370 mutex_unlock(&bp->link_lock); 3371 } 3372 return rc; 3373 } 3374 3375 static void bnxt_get_pauseparam(struct net_device *dev, 3376 struct ethtool_pauseparam *epause) 3377 { 3378 struct bnxt *bp = netdev_priv(dev); 3379 struct bnxt_link_info *link_info = &bp->link_info; 3380 3381 if (BNXT_VF(bp)) 3382 return; 3383 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 3384 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 3385 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 3386 } 3387 3388 static void bnxt_get_pause_stats(struct net_device *dev, 3389 struct ethtool_pause_stats *epstat) 3390 { 3391 struct bnxt *bp = netdev_priv(dev); 3392 u64 *rx, *tx; 3393 3394 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 3395 return; 3396 3397 rx = bp->port_stats.sw_stats; 3398 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 3399 3400 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames); 3401 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames); 3402 } 3403 3404 static int bnxt_set_pauseparam(struct net_device *dev, 3405 struct ethtool_pauseparam *epause) 3406 { 3407 int rc = 0; 3408 struct bnxt *bp = netdev_priv(dev); 3409 struct bnxt_link_info *link_info = &bp->link_info; 3410 3411 if (!BNXT_PHY_CFG_ABLE(bp) || (bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 3412 return -EOPNOTSUPP; 3413 3414 mutex_lock(&bp->link_lock); 3415 if (epause->autoneg) { 3416 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 3417 rc = -EINVAL; 3418 goto pause_exit; 3419 } 3420 3421 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 3422 link_info->req_flow_ctrl = 0; 3423 } else { 3424 /* when transition from auto pause to force pause, 3425 * force a link change 3426 */ 3427 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 3428 link_info->force_link_chng = true; 3429 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 3430 link_info->req_flow_ctrl = 0; 3431 } 3432 if (epause->rx_pause) 3433 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 3434 3435 if (epause->tx_pause) 3436 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 3437 3438 if (netif_running(dev)) 3439 rc = bnxt_hwrm_set_pause(bp); 3440 3441 pause_exit: 3442 mutex_unlock(&bp->link_lock); 3443 return rc; 3444 } 3445 3446 static u32 bnxt_get_link(struct net_device *dev) 3447 { 3448 struct bnxt *bp = netdev_priv(dev); 3449 3450 /* TODO: handle MF, VF, driver close case */ 3451 return BNXT_LINK_IS_UP(bp); 3452 } 3453 3454 static int bnxt_get_link_ext_state(struct net_device *dev, 3455 struct ethtool_link_ext_state_info *info) 3456 { 3457 struct bnxt *bp = netdev_priv(dev); 3458 u8 reason; 3459 3460 if (BNXT_LINK_IS_UP(bp)) 3461 return -ENODATA; 3462 3463 reason = bp->link_info.link_down_reason; 3464 if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF) { 3465 info->link_ext_state = ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE; 3466 info->link_training = ETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT; 3467 return 0; 3468 } 3469 if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_CABLE_REMOVED) { 3470 info->link_ext_state = ETHTOOL_LINK_EXT_STATE_NO_CABLE; 3471 return 0; 3472 } 3473 if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_OTP_SPEED_VIOLATION) { 3474 info->link_ext_state = ETHTOOL_LINK_EXT_STATE_OTP_SPEED_VIOLATION; 3475 return 0; 3476 } 3477 if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_MODULE_FAULT) { 3478 info->link_ext_state = ETHTOOL_LINK_EXT_STATE_MODULE; 3479 return 0; 3480 } 3481 if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_BMC_REQUEST) { 3482 info->link_ext_state = ETHTOOL_LINK_EXT_STATE_BMC_REQUEST_DOWN; 3483 return 0; 3484 } 3485 return -ENODATA; 3486 } 3487 3488 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp, 3489 struct hwrm_nvm_get_dev_info_output *nvm_dev_info) 3490 { 3491 struct hwrm_nvm_get_dev_info_output *resp; 3492 struct hwrm_nvm_get_dev_info_input *req; 3493 int rc; 3494 3495 if (BNXT_VF(bp)) 3496 return -EOPNOTSUPP; 3497 3498 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO); 3499 if (rc) 3500 return rc; 3501 3502 resp = hwrm_req_hold(bp, req); 3503 rc = hwrm_req_send(bp, req); 3504 if (!rc) 3505 memcpy(nvm_dev_info, resp, sizeof(*resp)); 3506 hwrm_req_drop(bp, req); 3507 return rc; 3508 } 3509 3510 static void bnxt_print_admin_err(struct bnxt *bp) 3511 { 3512 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 3513 } 3514 3515 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 3516 u16 ext, u16 *index, u32 *item_length, 3517 u32 *data_length); 3518 3519 int bnxt_flash_nvram(struct net_device *dev, u16 dir_type, 3520 u16 dir_ordinal, u16 dir_ext, u16 dir_attr, 3521 u32 dir_item_len, const u8 *data, 3522 size_t data_len) 3523 { 3524 struct bnxt *bp = netdev_priv(dev); 3525 struct hwrm_nvm_write_input *req; 3526 int rc; 3527 3528 rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE); 3529 if (rc) 3530 return rc; 3531 3532 if (data_len && data) { 3533 dma_addr_t dma_handle; 3534 u8 *kmem; 3535 3536 kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle); 3537 if (!kmem) { 3538 hwrm_req_drop(bp, req); 3539 return -ENOMEM; 3540 } 3541 3542 req->dir_data_length = cpu_to_le32(data_len); 3543 3544 memcpy(kmem, data, data_len); 3545 req->host_src_addr = cpu_to_le64(dma_handle); 3546 } 3547 3548 hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout); 3549 req->dir_type = cpu_to_le16(dir_type); 3550 req->dir_ordinal = cpu_to_le16(dir_ordinal); 3551 req->dir_ext = cpu_to_le16(dir_ext); 3552 req->dir_attr = cpu_to_le16(dir_attr); 3553 req->dir_item_length = cpu_to_le32(dir_item_len); 3554 rc = hwrm_req_send(bp, req); 3555 3556 if (rc == -EACCES) 3557 bnxt_print_admin_err(bp); 3558 return rc; 3559 } 3560 3561 int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type, 3562 u8 self_reset, u8 flags) 3563 { 3564 struct bnxt *bp = netdev_priv(dev); 3565 struct hwrm_fw_reset_input *req; 3566 int rc; 3567 3568 if (!bnxt_hwrm_reset_permitted(bp)) { 3569 netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver"); 3570 return -EPERM; 3571 } 3572 3573 rc = hwrm_req_init(bp, req, HWRM_FW_RESET); 3574 if (rc) 3575 return rc; 3576 3577 req->embedded_proc_type = proc_type; 3578 req->selfrst_status = self_reset; 3579 req->flags = flags; 3580 3581 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) { 3582 rc = hwrm_req_send_silent(bp, req); 3583 } else { 3584 rc = hwrm_req_send(bp, req); 3585 if (rc == -EACCES) 3586 bnxt_print_admin_err(bp); 3587 } 3588 return rc; 3589 } 3590 3591 static int bnxt_firmware_reset(struct net_device *dev, 3592 enum bnxt_nvm_directory_type dir_type) 3593 { 3594 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE; 3595 u8 proc_type, flags = 0; 3596 3597 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 3598 /* (e.g. when firmware isn't already running) */ 3599 switch (dir_type) { 3600 case BNX_DIR_TYPE_CHIMP_PATCH: 3601 case BNX_DIR_TYPE_BOOTCODE: 3602 case BNX_DIR_TYPE_BOOTCODE_2: 3603 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 3604 /* Self-reset ChiMP upon next PCIe reset: */ 3605 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 3606 break; 3607 case BNX_DIR_TYPE_APE_FW: 3608 case BNX_DIR_TYPE_APE_PATCH: 3609 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 3610 /* Self-reset APE upon next PCIe reset: */ 3611 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 3612 break; 3613 case BNX_DIR_TYPE_KONG_FW: 3614 case BNX_DIR_TYPE_KONG_PATCH: 3615 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 3616 break; 3617 case BNX_DIR_TYPE_BONO_FW: 3618 case BNX_DIR_TYPE_BONO_PATCH: 3619 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 3620 break; 3621 default: 3622 return -EINVAL; 3623 } 3624 3625 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags); 3626 } 3627 3628 static int bnxt_firmware_reset_chip(struct net_device *dev) 3629 { 3630 struct bnxt *bp = netdev_priv(dev); 3631 u8 flags = 0; 3632 3633 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 3634 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 3635 3636 return bnxt_hwrm_firmware_reset(dev, 3637 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP, 3638 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP, 3639 flags); 3640 } 3641 3642 static int bnxt_firmware_reset_ap(struct net_device *dev) 3643 { 3644 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP, 3645 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE, 3646 0); 3647 } 3648 3649 static int bnxt_flash_firmware(struct net_device *dev, 3650 u16 dir_type, 3651 const u8 *fw_data, 3652 size_t fw_size) 3653 { 3654 int rc = 0; 3655 u16 code_type; 3656 u32 stored_crc; 3657 u32 calculated_crc; 3658 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 3659 3660 switch (dir_type) { 3661 case BNX_DIR_TYPE_BOOTCODE: 3662 case BNX_DIR_TYPE_BOOTCODE_2: 3663 code_type = CODE_BOOT; 3664 break; 3665 case BNX_DIR_TYPE_CHIMP_PATCH: 3666 code_type = CODE_CHIMP_PATCH; 3667 break; 3668 case BNX_DIR_TYPE_APE_FW: 3669 code_type = CODE_MCTP_PASSTHRU; 3670 break; 3671 case BNX_DIR_TYPE_APE_PATCH: 3672 code_type = CODE_APE_PATCH; 3673 break; 3674 case BNX_DIR_TYPE_KONG_FW: 3675 code_type = CODE_KONG_FW; 3676 break; 3677 case BNX_DIR_TYPE_KONG_PATCH: 3678 code_type = CODE_KONG_PATCH; 3679 break; 3680 case BNX_DIR_TYPE_BONO_FW: 3681 code_type = CODE_BONO_FW; 3682 break; 3683 case BNX_DIR_TYPE_BONO_PATCH: 3684 code_type = CODE_BONO_PATCH; 3685 break; 3686 default: 3687 netdev_err(dev, "Unsupported directory entry type: %u\n", 3688 dir_type); 3689 return -EINVAL; 3690 } 3691 if (fw_size < sizeof(struct bnxt_fw_header)) { 3692 netdev_err(dev, "Invalid firmware file size: %u\n", 3693 (unsigned int)fw_size); 3694 return -EINVAL; 3695 } 3696 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 3697 netdev_err(dev, "Invalid firmware signature: %08X\n", 3698 le32_to_cpu(header->signature)); 3699 return -EINVAL; 3700 } 3701 if (header->code_type != code_type) { 3702 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 3703 code_type, header->code_type); 3704 return -EINVAL; 3705 } 3706 if (header->device != DEVICE_CUMULUS_FAMILY) { 3707 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 3708 DEVICE_CUMULUS_FAMILY, header->device); 3709 return -EINVAL; 3710 } 3711 /* Confirm the CRC32 checksum of the file: */ 3712 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 3713 sizeof(stored_crc))); 3714 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 3715 if (calculated_crc != stored_crc) { 3716 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 3717 (unsigned long)stored_crc, 3718 (unsigned long)calculated_crc); 3719 return -EINVAL; 3720 } 3721 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3722 0, 0, 0, fw_data, fw_size); 3723 if (rc == 0) /* Firmware update successful */ 3724 rc = bnxt_firmware_reset(dev, dir_type); 3725 3726 return rc; 3727 } 3728 3729 static int bnxt_flash_microcode(struct net_device *dev, 3730 u16 dir_type, 3731 const u8 *fw_data, 3732 size_t fw_size) 3733 { 3734 struct bnxt_ucode_trailer *trailer; 3735 u32 calculated_crc; 3736 u32 stored_crc; 3737 int rc = 0; 3738 3739 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 3740 netdev_err(dev, "Invalid microcode file size: %u\n", 3741 (unsigned int)fw_size); 3742 return -EINVAL; 3743 } 3744 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 3745 sizeof(*trailer))); 3746 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 3747 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 3748 le32_to_cpu(trailer->sig)); 3749 return -EINVAL; 3750 } 3751 if (le16_to_cpu(trailer->dir_type) != dir_type) { 3752 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 3753 dir_type, le16_to_cpu(trailer->dir_type)); 3754 return -EINVAL; 3755 } 3756 if (le16_to_cpu(trailer->trailer_length) < 3757 sizeof(struct bnxt_ucode_trailer)) { 3758 netdev_err(dev, "Invalid microcode trailer length: %d\n", 3759 le16_to_cpu(trailer->trailer_length)); 3760 return -EINVAL; 3761 } 3762 3763 /* Confirm the CRC32 checksum of the file: */ 3764 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 3765 sizeof(stored_crc))); 3766 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 3767 if (calculated_crc != stored_crc) { 3768 netdev_err(dev, 3769 "CRC32 (%08lX) does not match calculated: %08lX\n", 3770 (unsigned long)stored_crc, 3771 (unsigned long)calculated_crc); 3772 return -EINVAL; 3773 } 3774 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3775 0, 0, 0, fw_data, fw_size); 3776 3777 return rc; 3778 } 3779 3780 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 3781 { 3782 switch (dir_type) { 3783 case BNX_DIR_TYPE_CHIMP_PATCH: 3784 case BNX_DIR_TYPE_BOOTCODE: 3785 case BNX_DIR_TYPE_BOOTCODE_2: 3786 case BNX_DIR_TYPE_APE_FW: 3787 case BNX_DIR_TYPE_APE_PATCH: 3788 case BNX_DIR_TYPE_KONG_FW: 3789 case BNX_DIR_TYPE_KONG_PATCH: 3790 case BNX_DIR_TYPE_BONO_FW: 3791 case BNX_DIR_TYPE_BONO_PATCH: 3792 return true; 3793 } 3794 3795 return false; 3796 } 3797 3798 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 3799 { 3800 switch (dir_type) { 3801 case BNX_DIR_TYPE_AVS: 3802 case BNX_DIR_TYPE_EXP_ROM_MBA: 3803 case BNX_DIR_TYPE_PCIE: 3804 case BNX_DIR_TYPE_TSCF_UCODE: 3805 case BNX_DIR_TYPE_EXT_PHY: 3806 case BNX_DIR_TYPE_CCM: 3807 case BNX_DIR_TYPE_ISCSI_BOOT: 3808 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 3809 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 3810 return true; 3811 } 3812 3813 return false; 3814 } 3815 3816 static bool bnxt_dir_type_is_executable(u16 dir_type) 3817 { 3818 return bnxt_dir_type_is_ape_bin_format(dir_type) || 3819 bnxt_dir_type_is_other_exec_format(dir_type); 3820 } 3821 3822 static int bnxt_flash_firmware_from_file(struct net_device *dev, 3823 u16 dir_type, 3824 const char *filename) 3825 { 3826 const struct firmware *fw; 3827 int rc; 3828 3829 rc = request_firmware(&fw, filename, &dev->dev); 3830 if (rc != 0) { 3831 netdev_err(dev, "Error %d requesting firmware file: %s\n", 3832 rc, filename); 3833 return rc; 3834 } 3835 if (bnxt_dir_type_is_ape_bin_format(dir_type)) 3836 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 3837 else if (bnxt_dir_type_is_other_exec_format(dir_type)) 3838 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 3839 else 3840 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 3841 0, 0, 0, fw->data, fw->size); 3842 release_firmware(fw); 3843 return rc; 3844 } 3845 3846 #define MSG_INTEGRITY_ERR "PKG install error : Data integrity on NVM" 3847 #define MSG_INVALID_PKG "PKG install error : Invalid package" 3848 #define MSG_AUTHENTICATION_ERR "PKG install error : Authentication error" 3849 #define MSG_INVALID_DEV "PKG install error : Invalid device" 3850 #define MSG_INTERNAL_ERR "PKG install error : Internal error" 3851 #define MSG_NO_PKG_UPDATE_AREA_ERR "PKG update area not created in nvram" 3852 #define MSG_NO_SPACE_ERR "PKG insufficient update area in nvram" 3853 #define MSG_RESIZE_UPDATE_ERR "Resize UPDATE entry error" 3854 #define MSG_ANTI_ROLLBACK_ERR "HWRM_NVM_INSTALL_UPDATE failure due to Anti-rollback detected" 3855 #define MSG_GENERIC_FAILURE_ERR "HWRM_NVM_INSTALL_UPDATE failure" 3856 3857 static int nvm_update_err_to_stderr(struct net_device *dev, u8 result, 3858 struct netlink_ext_ack *extack) 3859 { 3860 switch (result) { 3861 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER: 3862 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER: 3863 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR: 3864 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR: 3865 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND: 3866 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED: 3867 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTEGRITY_ERR); 3868 return -EINVAL; 3869 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE: 3870 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER: 3871 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE: 3872 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM: 3873 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH: 3874 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST: 3875 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER: 3876 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM: 3877 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM: 3878 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH: 3879 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE: 3880 case NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM: 3881 case NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM: 3882 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_PKG); 3883 return -ENOPKG; 3884 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR: 3885 BNXT_NVM_ERR_MSG(dev, extack, MSG_AUTHENTICATION_ERR); 3886 return -EPERM; 3887 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV: 3888 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID: 3889 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR: 3890 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID: 3891 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM: 3892 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_DEV); 3893 return -EOPNOTSUPP; 3894 default: 3895 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTERNAL_ERR); 3896 return -EIO; 3897 } 3898 } 3899 3900 #define BNXT_PKG_DMA_SIZE 0x40000 3901 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE)) 3902 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST)) 3903 3904 static int bnxt_hwrm_nvm_defrag(struct bnxt *bp) 3905 { 3906 struct hwrm_nvm_defrag_input *req; 3907 int rc; 3908 3909 rc = hwrm_req_init(bp, req, HWRM_NVM_DEFRAG); 3910 if (rc) 3911 return rc; 3912 req->flags = cpu_to_le32(NVM_DEFRAG_REQ_FLAGS_DEFRAG); 3913 hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout); 3914 3915 return hwrm_req_send(bp, req); 3916 } 3917 3918 static int bnxt_resize_update_entry(struct net_device *dev, size_t fw_size, 3919 struct netlink_ext_ack *extack) 3920 { 3921 struct bnxt *bp = netdev_priv(dev); 3922 bool retry = false; 3923 u32 item_len; 3924 int rc; 3925 3926 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 3927 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, NULL, 3928 &item_len, NULL); 3929 if (rc) { 3930 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 3931 return rc; 3932 } 3933 3934 if (fw_size > item_len) { 3935 do { 3936 rc = bnxt_flash_nvram(dev, BNX_DIR_TYPE_UPDATE, 3937 BNX_DIR_ORDINAL_FIRST, 0, 1, 3938 round_up(fw_size, 4096), NULL, 3939 0); 3940 3941 if (rc == -ENOSPC) { 3942 if (retry || bnxt_hwrm_nvm_defrag(bp)) 3943 break; 3944 retry = true; 3945 } 3946 } while (rc == -ENOSPC); 3947 3948 if (rc) { 3949 BNXT_NVM_ERR_MSG(dev, extack, MSG_RESIZE_UPDATE_ERR); 3950 return rc; 3951 } 3952 } 3953 return 0; 3954 } 3955 3956 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw, 3957 u32 install_type, struct netlink_ext_ack *extack) 3958 { 3959 struct hwrm_nvm_install_update_input *install; 3960 struct hwrm_nvm_install_update_output *resp; 3961 struct hwrm_nvm_modify_input *modify; 3962 struct bnxt *bp = netdev_priv(dev); 3963 bool defrag_attempted = false; 3964 dma_addr_t dma_handle; 3965 u8 *kmem = NULL; 3966 u32 modify_len; 3967 u32 item_len; 3968 u8 cmd_err; 3969 u16 index; 3970 int rc; 3971 3972 /* resize before flashing larger image than available space */ 3973 rc = bnxt_resize_update_entry(dev, fw->size, extack); 3974 if (rc) 3975 return rc; 3976 3977 bnxt_hwrm_fw_set_time(bp); 3978 3979 rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY); 3980 if (rc) 3981 return rc; 3982 3983 /* Try allocating a large DMA buffer first. Older fw will 3984 * cause excessive NVRAM erases when using small blocks. 3985 */ 3986 modify_len = roundup_pow_of_two(fw->size); 3987 modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE); 3988 while (1) { 3989 kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle); 3990 if (!kmem && modify_len > PAGE_SIZE) 3991 modify_len /= 2; 3992 else 3993 break; 3994 } 3995 if (!kmem) { 3996 hwrm_req_drop(bp, modify); 3997 return -ENOMEM; 3998 } 3999 4000 rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE); 4001 if (rc) { 4002 hwrm_req_drop(bp, modify); 4003 return rc; 4004 } 4005 4006 hwrm_req_timeout(bp, modify, bp->hwrm_cmd_max_timeout); 4007 hwrm_req_timeout(bp, install, bp->hwrm_cmd_max_timeout); 4008 4009 hwrm_req_hold(bp, modify); 4010 modify->host_src_addr = cpu_to_le64(dma_handle); 4011 4012 resp = hwrm_req_hold(bp, install); 4013 if ((install_type & 0xffff) == 0) 4014 install_type >>= 16; 4015 install->install_type = cpu_to_le32(install_type); 4016 4017 do { 4018 u32 copied = 0, len = modify_len; 4019 4020 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 4021 BNX_DIR_ORDINAL_FIRST, 4022 BNX_DIR_EXT_NONE, 4023 &index, &item_len, NULL); 4024 if (rc) { 4025 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 4026 break; 4027 } 4028 if (fw->size > item_len) { 4029 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_SPACE_ERR); 4030 rc = -EFBIG; 4031 break; 4032 } 4033 4034 modify->dir_idx = cpu_to_le16(index); 4035 4036 if (fw->size > modify_len) 4037 modify->flags = BNXT_NVM_MORE_FLAG; 4038 while (copied < fw->size) { 4039 u32 balance = fw->size - copied; 4040 4041 if (balance <= modify_len) { 4042 len = balance; 4043 if (copied) 4044 modify->flags |= BNXT_NVM_LAST_FLAG; 4045 } 4046 memcpy(kmem, fw->data + copied, len); 4047 modify->len = cpu_to_le32(len); 4048 modify->offset = cpu_to_le32(copied); 4049 rc = hwrm_req_send(bp, modify); 4050 if (rc) 4051 goto pkg_abort; 4052 copied += len; 4053 } 4054 4055 rc = hwrm_req_send_silent(bp, install); 4056 if (!rc) 4057 break; 4058 4059 if (defrag_attempted) { 4060 /* We have tried to defragment already in the previous 4061 * iteration. Return with the result for INSTALL_UPDATE 4062 */ 4063 break; 4064 } 4065 4066 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 4067 4068 switch (cmd_err) { 4069 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK: 4070 BNXT_NVM_ERR_MSG(dev, extack, MSG_ANTI_ROLLBACK_ERR); 4071 rc = -EALREADY; 4072 break; 4073 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR: 4074 install->flags = 4075 cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 4076 4077 rc = hwrm_req_send_silent(bp, install); 4078 if (!rc) 4079 break; 4080 4081 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 4082 4083 if (cmd_err == NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) { 4084 /* FW has cleared NVM area, driver will create 4085 * UPDATE directory and try the flash again 4086 */ 4087 defrag_attempted = true; 4088 install->flags = 0; 4089 rc = bnxt_flash_nvram(bp->dev, 4090 BNX_DIR_TYPE_UPDATE, 4091 BNX_DIR_ORDINAL_FIRST, 4092 0, 0, item_len, NULL, 0); 4093 if (!rc) 4094 break; 4095 } 4096 fallthrough; 4097 default: 4098 BNXT_NVM_ERR_MSG(dev, extack, MSG_GENERIC_FAILURE_ERR); 4099 } 4100 } while (defrag_attempted && !rc); 4101 4102 pkg_abort: 4103 hwrm_req_drop(bp, modify); 4104 hwrm_req_drop(bp, install); 4105 4106 if (resp->result) { 4107 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 4108 (s8)resp->result, (int)resp->problem_item); 4109 rc = nvm_update_err_to_stderr(dev, resp->result, extack); 4110 } 4111 if (rc == -EACCES) 4112 bnxt_print_admin_err(bp); 4113 return rc; 4114 } 4115 4116 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename, 4117 u32 install_type, struct netlink_ext_ack *extack) 4118 { 4119 const struct firmware *fw; 4120 int rc; 4121 4122 rc = request_firmware(&fw, filename, &dev->dev); 4123 if (rc != 0) { 4124 netdev_err(dev, "PKG error %d requesting file: %s\n", 4125 rc, filename); 4126 return rc; 4127 } 4128 4129 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type, extack); 4130 4131 release_firmware(fw); 4132 4133 return rc; 4134 } 4135 4136 static int bnxt_flash_device(struct net_device *dev, 4137 struct ethtool_flash *flash) 4138 { 4139 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 4140 netdev_err(dev, "flashdev not supported from a virtual function\n"); 4141 return -EINVAL; 4142 } 4143 4144 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 4145 flash->region > 0xffff) 4146 return bnxt_flash_package_from_file(dev, flash->data, 4147 flash->region, NULL); 4148 4149 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 4150 } 4151 4152 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 4153 { 4154 struct hwrm_nvm_get_dir_info_output *output; 4155 struct hwrm_nvm_get_dir_info_input *req; 4156 struct bnxt *bp = netdev_priv(dev); 4157 int rc; 4158 4159 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO); 4160 if (rc) 4161 return rc; 4162 4163 output = hwrm_req_hold(bp, req); 4164 rc = hwrm_req_send(bp, req); 4165 if (!rc) { 4166 *entries = le32_to_cpu(output->entries); 4167 *length = le32_to_cpu(output->entry_length); 4168 } 4169 hwrm_req_drop(bp, req); 4170 return rc; 4171 } 4172 4173 static int bnxt_get_eeprom_len(struct net_device *dev) 4174 { 4175 struct bnxt *bp = netdev_priv(dev); 4176 4177 if (BNXT_VF(bp)) 4178 return 0; 4179 4180 /* The -1 return value allows the entire 32-bit range of offsets to be 4181 * passed via the ethtool command-line utility. 4182 */ 4183 return -1; 4184 } 4185 4186 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 4187 { 4188 struct bnxt *bp = netdev_priv(dev); 4189 int rc; 4190 u32 dir_entries; 4191 u32 entry_length; 4192 u8 *buf; 4193 size_t buflen; 4194 dma_addr_t dma_handle; 4195 struct hwrm_nvm_get_dir_entries_input *req; 4196 4197 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 4198 if (rc != 0) 4199 return rc; 4200 4201 if (!dir_entries || !entry_length) 4202 return -EIO; 4203 4204 /* Insert 2 bytes of directory info (count and size of entries) */ 4205 if (len < 2) 4206 return -EINVAL; 4207 4208 *data++ = dir_entries; 4209 *data++ = entry_length; 4210 len -= 2; 4211 memset(data, 0xff, len); 4212 4213 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES); 4214 if (rc) 4215 return rc; 4216 4217 buflen = mul_u32_u32(dir_entries, entry_length); 4218 buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle); 4219 if (!buf) { 4220 hwrm_req_drop(bp, req); 4221 return -ENOMEM; 4222 } 4223 req->host_dest_addr = cpu_to_le64(dma_handle); 4224 4225 hwrm_req_hold(bp, req); /* hold the slice */ 4226 rc = hwrm_req_send(bp, req); 4227 if (rc == 0) 4228 memcpy(data, buf, len > buflen ? buflen : len); 4229 hwrm_req_drop(bp, req); 4230 return rc; 4231 } 4232 4233 int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 4234 u32 length, u8 *data) 4235 { 4236 struct bnxt *bp = netdev_priv(dev); 4237 int rc; 4238 u8 *buf; 4239 dma_addr_t dma_handle; 4240 struct hwrm_nvm_read_input *req; 4241 4242 if (!length) 4243 return -EINVAL; 4244 4245 rc = hwrm_req_init(bp, req, HWRM_NVM_READ); 4246 if (rc) 4247 return rc; 4248 4249 buf = hwrm_req_dma_slice(bp, req, length, &dma_handle); 4250 if (!buf) { 4251 hwrm_req_drop(bp, req); 4252 return -ENOMEM; 4253 } 4254 4255 req->host_dest_addr = cpu_to_le64(dma_handle); 4256 req->dir_idx = cpu_to_le16(index); 4257 req->offset = cpu_to_le32(offset); 4258 req->len = cpu_to_le32(length); 4259 4260 hwrm_req_hold(bp, req); /* hold the slice */ 4261 rc = hwrm_req_send(bp, req); 4262 if (rc == 0) 4263 memcpy(data, buf, length); 4264 hwrm_req_drop(bp, req); 4265 return rc; 4266 } 4267 4268 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 4269 u16 ext, u16 *index, u32 *item_length, 4270 u32 *data_length) 4271 { 4272 struct hwrm_nvm_find_dir_entry_output *output; 4273 struct hwrm_nvm_find_dir_entry_input *req; 4274 struct bnxt *bp = netdev_priv(dev); 4275 int rc; 4276 4277 rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY); 4278 if (rc) 4279 return rc; 4280 4281 req->enables = 0; 4282 req->dir_idx = 0; 4283 req->dir_type = cpu_to_le16(type); 4284 req->dir_ordinal = cpu_to_le16(ordinal); 4285 req->dir_ext = cpu_to_le16(ext); 4286 req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 4287 output = hwrm_req_hold(bp, req); 4288 rc = hwrm_req_send_silent(bp, req); 4289 if (rc == 0) { 4290 if (index) 4291 *index = le16_to_cpu(output->dir_idx); 4292 if (item_length) 4293 *item_length = le32_to_cpu(output->dir_item_length); 4294 if (data_length) 4295 *data_length = le32_to_cpu(output->dir_data_length); 4296 } 4297 hwrm_req_drop(bp, req); 4298 return rc; 4299 } 4300 4301 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 4302 { 4303 char *retval = NULL; 4304 char *p; 4305 char *value; 4306 int field = 0; 4307 4308 if (datalen < 1) 4309 return NULL; 4310 /* null-terminate the log data (removing last '\n'): */ 4311 data[datalen - 1] = 0; 4312 for (p = data; *p != 0; p++) { 4313 field = 0; 4314 retval = NULL; 4315 while (*p != 0 && *p != '\n') { 4316 value = p; 4317 while (*p != 0 && *p != '\t' && *p != '\n') 4318 p++; 4319 if (field == desired_field) 4320 retval = value; 4321 if (*p != '\t') 4322 break; 4323 *p = 0; 4324 field++; 4325 p++; 4326 } 4327 if (*p == 0) 4328 break; 4329 *p = 0; 4330 } 4331 return retval; 4332 } 4333 4334 int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size) 4335 { 4336 struct bnxt *bp = netdev_priv(dev); 4337 u16 index = 0; 4338 char *pkgver; 4339 u32 pkglen; 4340 u8 *pkgbuf; 4341 int rc; 4342 4343 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 4344 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 4345 &index, NULL, &pkglen); 4346 if (rc) 4347 return rc; 4348 4349 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 4350 if (!pkgbuf) { 4351 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 4352 pkglen); 4353 return -ENOMEM; 4354 } 4355 4356 rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf); 4357 if (rc) 4358 goto err; 4359 4360 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 4361 pkglen); 4362 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) 4363 strscpy(ver, pkgver, size); 4364 else 4365 rc = -ENOENT; 4366 4367 err: 4368 kfree(pkgbuf); 4369 4370 return rc; 4371 } 4372 4373 static void bnxt_get_pkgver(struct net_device *dev) 4374 { 4375 struct bnxt *bp = netdev_priv(dev); 4376 char buf[FW_VER_STR_LEN - 5]; 4377 int len; 4378 4379 if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) { 4380 len = strlen(bp->fw_ver_str); 4381 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len, 4382 "/pkg %s", buf); 4383 } 4384 } 4385 4386 static int bnxt_get_eeprom(struct net_device *dev, 4387 struct ethtool_eeprom *eeprom, 4388 u8 *data) 4389 { 4390 u32 index; 4391 u32 offset; 4392 4393 if (eeprom->offset == 0) /* special offset value to get directory */ 4394 return bnxt_get_nvram_directory(dev, eeprom->len, data); 4395 4396 index = eeprom->offset >> 24; 4397 offset = eeprom->offset & 0xffffff; 4398 4399 if (index == 0) { 4400 netdev_err(dev, "unsupported index value: %d\n", index); 4401 return -EINVAL; 4402 } 4403 4404 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 4405 } 4406 4407 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 4408 { 4409 struct hwrm_nvm_erase_dir_entry_input *req; 4410 struct bnxt *bp = netdev_priv(dev); 4411 int rc; 4412 4413 rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY); 4414 if (rc) 4415 return rc; 4416 4417 req->dir_idx = cpu_to_le16(index); 4418 return hwrm_req_send(bp, req); 4419 } 4420 4421 static int bnxt_set_eeprom(struct net_device *dev, 4422 struct ethtool_eeprom *eeprom, 4423 u8 *data) 4424 { 4425 struct bnxt *bp = netdev_priv(dev); 4426 u8 index, dir_op; 4427 u16 type, ext, ordinal, attr; 4428 4429 if (!BNXT_PF(bp)) { 4430 netdev_err(dev, "NVM write not supported from a virtual function\n"); 4431 return -EINVAL; 4432 } 4433 4434 type = eeprom->magic >> 16; 4435 4436 if (type == 0xffff) { /* special value for directory operations */ 4437 index = eeprom->magic & 0xff; 4438 dir_op = eeprom->magic >> 8; 4439 if (index == 0) 4440 return -EINVAL; 4441 switch (dir_op) { 4442 case 0x0e: /* erase */ 4443 if (eeprom->offset != ~eeprom->magic) 4444 return -EINVAL; 4445 return bnxt_erase_nvram_directory(dev, index - 1); 4446 default: 4447 return -EINVAL; 4448 } 4449 } 4450 4451 /* Create or re-write an NVM item: */ 4452 if (bnxt_dir_type_is_executable(type)) 4453 return -EOPNOTSUPP; 4454 ext = eeprom->magic & 0xffff; 4455 ordinal = eeprom->offset >> 16; 4456 attr = eeprom->offset & 0xffff; 4457 4458 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data, 4459 eeprom->len); 4460 } 4461 4462 static int bnxt_set_eee(struct net_device *dev, struct ethtool_keee *edata) 4463 { 4464 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 4465 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp); 4466 struct bnxt *bp = netdev_priv(dev); 4467 struct ethtool_keee *eee = &bp->eee; 4468 struct bnxt_link_info *link_info = &bp->link_info; 4469 int rc = 0; 4470 4471 if (!BNXT_PHY_CFG_ABLE(bp)) 4472 return -EOPNOTSUPP; 4473 4474 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 4475 return -EOPNOTSUPP; 4476 4477 mutex_lock(&bp->link_lock); 4478 _bnxt_fw_to_linkmode(advertising, link_info->advertising); 4479 if (!edata->eee_enabled) 4480 goto eee_ok; 4481 4482 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 4483 netdev_warn(dev, "EEE requires autoneg\n"); 4484 rc = -EINVAL; 4485 goto eee_exit; 4486 } 4487 if (edata->tx_lpi_enabled) { 4488 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 4489 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 4490 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 4491 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 4492 rc = -EINVAL; 4493 goto eee_exit; 4494 } else if (!bp->lpi_tmr_hi) { 4495 edata->tx_lpi_timer = eee->tx_lpi_timer; 4496 } 4497 } 4498 if (linkmode_empty(edata->advertised)) { 4499 linkmode_and(edata->advertised, advertising, eee->supported); 4500 } else if (linkmode_andnot(tmp, edata->advertised, advertising)) { 4501 netdev_warn(dev, "EEE advertised must be a subset of autoneg advertised speeds\n"); 4502 rc = -EINVAL; 4503 goto eee_exit; 4504 } 4505 4506 linkmode_copy(eee->advertised, edata->advertised); 4507 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 4508 eee->tx_lpi_timer = edata->tx_lpi_timer; 4509 eee_ok: 4510 eee->eee_enabled = edata->eee_enabled; 4511 4512 if (netif_running(dev)) 4513 rc = bnxt_hwrm_set_link_setting(bp, false, true); 4514 4515 eee_exit: 4516 mutex_unlock(&bp->link_lock); 4517 return rc; 4518 } 4519 4520 static int bnxt_get_eee(struct net_device *dev, struct ethtool_keee *edata) 4521 { 4522 struct bnxt *bp = netdev_priv(dev); 4523 4524 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 4525 return -EOPNOTSUPP; 4526 4527 *edata = bp->eee; 4528 if (!bp->eee.eee_enabled) { 4529 /* Preserve tx_lpi_timer so that the last value will be used 4530 * by default when it is re-enabled. 4531 */ 4532 linkmode_zero(edata->advertised); 4533 edata->tx_lpi_enabled = 0; 4534 } 4535 4536 if (!bp->eee.eee_active) 4537 linkmode_zero(edata->lp_advertised); 4538 4539 return 0; 4540 } 4541 4542 static int bnxt_hwrm_pfcwd_qcfg(struct bnxt *bp, u16 *val) 4543 { 4544 struct hwrm_queue_pfcwd_timeout_qcfg_output *resp; 4545 struct hwrm_queue_pfcwd_timeout_qcfg_input *req; 4546 int rc; 4547 4548 rc = hwrm_req_init(bp, req, HWRM_QUEUE_PFCWD_TIMEOUT_QCFG); 4549 if (rc) 4550 return rc; 4551 resp = hwrm_req_hold(bp, req); 4552 rc = hwrm_req_send(bp, req); 4553 if (!rc) 4554 *val = le16_to_cpu(resp->pfcwd_timeout_value); 4555 hwrm_req_drop(bp, req); 4556 return rc; 4557 } 4558 4559 static int bnxt_hwrm_pfcwd_cfg(struct bnxt *bp, u16 val) 4560 { 4561 struct hwrm_queue_pfcwd_timeout_cfg_input *req; 4562 int rc; 4563 4564 rc = hwrm_req_init(bp, req, HWRM_QUEUE_PFCWD_TIMEOUT_CFG); 4565 if (rc) 4566 return rc; 4567 req->pfcwd_timeout_value = cpu_to_le16(val); 4568 rc = hwrm_req_send(bp, req); 4569 return rc; 4570 } 4571 4572 static int bnxt_set_tunable(struct net_device *dev, 4573 const struct ethtool_tunable *tuna, 4574 const void *data) 4575 { 4576 struct bnxt *bp = netdev_priv(dev); 4577 u32 rx_copybreak, val; 4578 4579 switch (tuna->id) { 4580 case ETHTOOL_RX_COPYBREAK: 4581 rx_copybreak = *(u32 *)data; 4582 if (rx_copybreak > BNXT_MAX_RX_COPYBREAK) 4583 return -ERANGE; 4584 if (rx_copybreak != bp->rx_copybreak) { 4585 if (netif_running(dev)) 4586 return -EBUSY; 4587 bp->rx_copybreak = rx_copybreak; 4588 } 4589 return 0; 4590 case ETHTOOL_PFC_PREVENTION_TOUT: 4591 if (BNXT_VF(bp) || !bp->max_pfcwd_tmo_ms) 4592 return -EOPNOTSUPP; 4593 4594 val = *(u16 *)data; 4595 if (val > bp->max_pfcwd_tmo_ms && 4596 val != PFC_STORM_PREVENTION_AUTO) 4597 return -EINVAL; 4598 return bnxt_hwrm_pfcwd_cfg(bp, val); 4599 default: 4600 return -EOPNOTSUPP; 4601 } 4602 } 4603 4604 static int bnxt_get_tunable(struct net_device *dev, 4605 const struct ethtool_tunable *tuna, void *data) 4606 { 4607 struct bnxt *bp = netdev_priv(dev); 4608 4609 switch (tuna->id) { 4610 case ETHTOOL_RX_COPYBREAK: 4611 *(u32 *)data = bp->rx_copybreak; 4612 break; 4613 case ETHTOOL_PFC_PREVENTION_TOUT: 4614 if (!bp->max_pfcwd_tmo_ms) 4615 return -EOPNOTSUPP; 4616 return bnxt_hwrm_pfcwd_qcfg(bp, data); 4617 default: 4618 return -EOPNOTSUPP; 4619 } 4620 4621 return 0; 4622 } 4623 4624 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 4625 u16 page_number, u8 bank, 4626 u16 start_addr, u16 data_length, 4627 u8 *buf) 4628 { 4629 struct hwrm_port_phy_i2c_read_output *output; 4630 struct hwrm_port_phy_i2c_read_input *req; 4631 int rc, byte_offset = 0; 4632 4633 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ); 4634 if (rc) 4635 return rc; 4636 4637 output = hwrm_req_hold(bp, req); 4638 req->i2c_slave_addr = i2c_addr; 4639 req->page_number = cpu_to_le16(page_number); 4640 req->port_id = cpu_to_le16(bp->pf.port_id); 4641 do { 4642 u16 xfer_size; 4643 4644 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 4645 data_length -= xfer_size; 4646 req->page_offset = cpu_to_le16(start_addr + byte_offset); 4647 req->data_length = xfer_size; 4648 req->enables = 4649 cpu_to_le32((start_addr + byte_offset ? 4650 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 4651 0) | 4652 (bank ? 4653 PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER : 4654 0)); 4655 rc = hwrm_req_send(bp, req); 4656 if (!rc) 4657 memcpy(buf + byte_offset, output->data, xfer_size); 4658 byte_offset += xfer_size; 4659 } while (!rc && data_length > 0); 4660 hwrm_req_drop(bp, req); 4661 4662 return rc; 4663 } 4664 4665 static int bnxt_get_module_info(struct net_device *dev, 4666 struct ethtool_modinfo *modinfo) 4667 { 4668 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 4669 struct bnxt *bp = netdev_priv(dev); 4670 int rc; 4671 4672 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 4673 return -EPERM; 4674 4675 /* No point in going further if phy status indicates 4676 * module is not inserted or if it is powered down or 4677 * if it is of type 10GBase-T 4678 */ 4679 if (bp->link_info.module_status > 4680 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 4681 return -EOPNOTSUPP; 4682 4683 /* This feature is not supported in older firmware versions */ 4684 if (bp->hwrm_spec_code < 0x10202) 4685 return -EOPNOTSUPP; 4686 4687 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 0, 4688 SFF_DIAG_SUPPORT_OFFSET + 1, 4689 data); 4690 if (!rc) { 4691 u8 module_id = data[0]; 4692 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 4693 4694 switch (module_id) { 4695 case SFF_MODULE_ID_SFP: 4696 modinfo->type = ETH_MODULE_SFF_8472; 4697 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 4698 if (!diag_supported) 4699 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 4700 break; 4701 case SFF_MODULE_ID_QSFP: 4702 case SFF_MODULE_ID_QSFP_PLUS: 4703 modinfo->type = ETH_MODULE_SFF_8436; 4704 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 4705 break; 4706 case SFF_MODULE_ID_QSFP28: 4707 modinfo->type = ETH_MODULE_SFF_8636; 4708 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 4709 break; 4710 default: 4711 rc = -EOPNOTSUPP; 4712 break; 4713 } 4714 } 4715 return rc; 4716 } 4717 4718 static int bnxt_get_module_eeprom(struct net_device *dev, 4719 struct ethtool_eeprom *eeprom, 4720 u8 *data) 4721 { 4722 struct bnxt *bp = netdev_priv(dev); 4723 u16 start = eeprom->offset, length = eeprom->len; 4724 int rc = 0; 4725 4726 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 4727 return -EPERM; 4728 4729 memset(data, 0, eeprom->len); 4730 4731 /* Read A0 portion of the EEPROM */ 4732 if (start < ETH_MODULE_SFF_8436_LEN) { 4733 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 4734 length = ETH_MODULE_SFF_8436_LEN - start; 4735 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 4736 start, length, data); 4737 if (rc) 4738 return rc; 4739 start += length; 4740 data += length; 4741 length = eeprom->len - length; 4742 } 4743 4744 /* Read A2 portion of the EEPROM */ 4745 if (length) { 4746 start -= ETH_MODULE_SFF_8436_LEN; 4747 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 0, 4748 start, length, data); 4749 } 4750 return rc; 4751 } 4752 4753 static int bnxt_get_module_status(struct bnxt *bp, struct netlink_ext_ack *extack) 4754 { 4755 if (bp->link_info.module_status <= 4756 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 4757 return 0; 4758 4759 if (bp->link_info.phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 4760 bp->link_info.phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE){ 4761 NL_SET_ERR_MSG_MOD(extack, "Operation not supported as PHY type is Base-T"); 4762 return -EOPNOTSUPP; 4763 } 4764 switch (bp->link_info.module_status) { 4765 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 4766 NL_SET_ERR_MSG_MOD(extack, "Transceiver module is powering down"); 4767 break; 4768 case PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED: 4769 NL_SET_ERR_MSG_MOD(extack, "Transceiver module not inserted"); 4770 break; 4771 case PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT: 4772 NL_SET_ERR_MSG_MOD(extack, "Transceiver module disabled due to current fault"); 4773 break; 4774 default: 4775 NL_SET_ERR_MSG_MOD(extack, "Unknown error"); 4776 break; 4777 } 4778 return -EINVAL; 4779 } 4780 4781 static int 4782 bnxt_mod_eeprom_by_page_precheck(struct bnxt *bp, 4783 const struct ethtool_module_eeprom *page_data, 4784 struct netlink_ext_ack *extack) 4785 { 4786 int rc; 4787 4788 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { 4789 NL_SET_ERR_MSG_MOD(extack, 4790 "Module read/write not permitted on untrusted VF"); 4791 return -EPERM; 4792 } 4793 4794 rc = bnxt_get_module_status(bp, extack); 4795 if (rc) 4796 return rc; 4797 4798 if (bp->hwrm_spec_code < 0x10202) { 4799 NL_SET_ERR_MSG_MOD(extack, "Firmware version too old"); 4800 return -EINVAL; 4801 } 4802 4803 if (page_data->bank && !(bp->phy_flags & BNXT_PHY_FL_BANK_SEL)) { 4804 NL_SET_ERR_MSG_MOD(extack, "Firmware not capable for bank selection"); 4805 return -EINVAL; 4806 } 4807 return 0; 4808 } 4809 4810 static int bnxt_get_module_eeprom_by_page(struct net_device *dev, 4811 const struct ethtool_module_eeprom *page_data, 4812 struct netlink_ext_ack *extack) 4813 { 4814 struct bnxt *bp = netdev_priv(dev); 4815 int rc; 4816 4817 rc = bnxt_mod_eeprom_by_page_precheck(bp, page_data, extack); 4818 if (rc) 4819 return rc; 4820 4821 rc = bnxt_read_sfp_module_eeprom_info(bp, page_data->i2c_address << 1, 4822 page_data->page, page_data->bank, 4823 page_data->offset, 4824 page_data->length, 4825 page_data->data); 4826 if (rc) { 4827 NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom read failed"); 4828 return rc; 4829 } 4830 return page_data->length; 4831 } 4832 4833 static int bnxt_write_sfp_module_eeprom_info(struct bnxt *bp, 4834 const struct ethtool_module_eeprom *page) 4835 { 4836 struct hwrm_port_phy_i2c_write_input *req; 4837 int bytes_written = 0; 4838 int rc; 4839 4840 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_WRITE); 4841 if (rc) 4842 return rc; 4843 4844 hwrm_req_hold(bp, req); 4845 req->i2c_slave_addr = page->i2c_address << 1; 4846 req->page_number = cpu_to_le16(page->page); 4847 req->bank_number = page->bank; 4848 req->port_id = cpu_to_le16(bp->pf.port_id); 4849 req->enables = cpu_to_le32(PORT_PHY_I2C_WRITE_REQ_ENABLES_PAGE_OFFSET | 4850 PORT_PHY_I2C_WRITE_REQ_ENABLES_BANK_NUMBER); 4851 4852 while (bytes_written < page->length) { 4853 u16 xfer_size; 4854 4855 xfer_size = min_t(u16, page->length - bytes_written, 4856 BNXT_MAX_PHY_I2C_RESP_SIZE); 4857 req->page_offset = cpu_to_le16(page->offset + bytes_written); 4858 req->data_length = xfer_size; 4859 memcpy(req->data, page->data + bytes_written, xfer_size); 4860 rc = hwrm_req_send(bp, req); 4861 if (rc) 4862 break; 4863 bytes_written += xfer_size; 4864 } 4865 4866 hwrm_req_drop(bp, req); 4867 return rc; 4868 } 4869 4870 static int bnxt_set_module_eeprom_by_page(struct net_device *dev, 4871 const struct ethtool_module_eeprom *page_data, 4872 struct netlink_ext_ack *extack) 4873 { 4874 struct bnxt *bp = netdev_priv(dev); 4875 int rc; 4876 4877 rc = bnxt_mod_eeprom_by_page_precheck(bp, page_data, extack); 4878 if (rc) 4879 return rc; 4880 4881 rc = bnxt_write_sfp_module_eeprom_info(bp, page_data); 4882 if (rc) { 4883 NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom write failed"); 4884 return rc; 4885 } 4886 return page_data->length; 4887 } 4888 4889 static int bnxt_nway_reset(struct net_device *dev) 4890 { 4891 int rc = 0; 4892 4893 struct bnxt *bp = netdev_priv(dev); 4894 struct bnxt_link_info *link_info = &bp->link_info; 4895 4896 if (!BNXT_PHY_CFG_ABLE(bp)) 4897 return -EOPNOTSUPP; 4898 4899 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 4900 return -EINVAL; 4901 4902 if (netif_running(dev)) 4903 rc = bnxt_hwrm_set_link_setting(bp, true, false); 4904 4905 return rc; 4906 } 4907 4908 static int bnxt_set_phys_id(struct net_device *dev, 4909 enum ethtool_phys_id_state state) 4910 { 4911 struct hwrm_port_led_cfg_input *req; 4912 struct bnxt *bp = netdev_priv(dev); 4913 struct bnxt_pf_info *pf = &bp->pf; 4914 struct bnxt_led_cfg *led_cfg; 4915 u8 led_state; 4916 __le16 duration; 4917 int rc, i; 4918 4919 if (!bp->num_leds || BNXT_VF(bp)) 4920 return -EOPNOTSUPP; 4921 4922 if (state == ETHTOOL_ID_ACTIVE) { 4923 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 4924 duration = cpu_to_le16(500); 4925 } else if (state == ETHTOOL_ID_INACTIVE) { 4926 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 4927 duration = cpu_to_le16(0); 4928 } else { 4929 return -EINVAL; 4930 } 4931 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG); 4932 if (rc) 4933 return rc; 4934 4935 req->port_id = cpu_to_le16(pf->port_id); 4936 req->num_leds = bp->num_leds; 4937 led_cfg = (struct bnxt_led_cfg *)&req->led0_id; 4938 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 4939 req->enables |= BNXT_LED_DFLT_ENABLES(i); 4940 led_cfg->led_id = bp->leds[i].led_id; 4941 led_cfg->led_state = led_state; 4942 led_cfg->led_blink_on = duration; 4943 led_cfg->led_blink_off = duration; 4944 led_cfg->led_group_id = bp->leds[i].led_group_id; 4945 } 4946 return hwrm_req_send(bp, req); 4947 } 4948 4949 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 4950 { 4951 struct hwrm_selftest_irq_input *req; 4952 int rc; 4953 4954 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ); 4955 if (rc) 4956 return rc; 4957 4958 req->cmpl_ring = cpu_to_le16(cmpl_ring); 4959 return hwrm_req_send(bp, req); 4960 } 4961 4962 static int bnxt_test_irq(struct bnxt *bp) 4963 { 4964 int i; 4965 4966 for (i = 0; i < bp->cp_nr_rings; i++) { 4967 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 4968 int rc; 4969 4970 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 4971 if (rc) 4972 return rc; 4973 } 4974 return 0; 4975 } 4976 4977 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 4978 { 4979 struct hwrm_port_mac_cfg_input *req; 4980 int rc; 4981 4982 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 4983 if (rc) 4984 return rc; 4985 4986 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 4987 if (enable) 4988 req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 4989 else 4990 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 4991 return hwrm_req_send(bp, req); 4992 } 4993 4994 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 4995 { 4996 struct hwrm_port_phy_qcaps_output *resp; 4997 struct hwrm_port_phy_qcaps_input *req; 4998 int rc; 4999 5000 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS); 5001 if (rc) 5002 return rc; 5003 5004 resp = hwrm_req_hold(bp, req); 5005 rc = hwrm_req_send(bp, req); 5006 if (!rc) 5007 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 5008 5009 hwrm_req_drop(bp, req); 5010 return rc; 5011 } 5012 5013 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 5014 struct hwrm_port_phy_cfg_input *req) 5015 { 5016 struct bnxt_link_info *link_info = &bp->link_info; 5017 u16 fw_advertising; 5018 u16 fw_speed; 5019 int rc; 5020 5021 if (!link_info->autoneg || 5022 (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK)) 5023 return 0; 5024 5025 rc = bnxt_query_force_speeds(bp, &fw_advertising); 5026 if (rc) 5027 return rc; 5028 5029 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 5030 if (BNXT_LINK_IS_UP(bp)) 5031 fw_speed = bp->link_info.link_speed; 5032 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 5033 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 5034 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 5035 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 5036 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 5037 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 5038 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 5039 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 5040 5041 req->force_link_speed = cpu_to_le16(fw_speed); 5042 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 5043 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 5044 rc = hwrm_req_send(bp, req); 5045 req->flags = 0; 5046 req->force_link_speed = cpu_to_le16(0); 5047 return rc; 5048 } 5049 5050 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 5051 { 5052 struct hwrm_port_phy_cfg_input *req; 5053 int rc; 5054 5055 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 5056 if (rc) 5057 return rc; 5058 5059 /* prevent bnxt_disable_an_for_lpbk() from consuming the request */ 5060 hwrm_req_hold(bp, req); 5061 5062 if (enable) { 5063 bnxt_disable_an_for_lpbk(bp, req); 5064 if (ext) 5065 req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 5066 else 5067 req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 5068 } else { 5069 req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 5070 } 5071 req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 5072 rc = hwrm_req_send(bp, req); 5073 hwrm_req_drop(bp, req); 5074 return rc; 5075 } 5076 5077 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 5078 u32 raw_cons, int pkt_size) 5079 { 5080 struct bnxt_napi *bnapi = cpr->bnapi; 5081 struct bnxt_rx_ring_info *rxr; 5082 struct bnxt_sw_rx_bd *rx_buf; 5083 struct rx_cmp *rxcmp; 5084 u16 cp_cons, cons; 5085 u8 *data; 5086 u32 len; 5087 int i; 5088 5089 rxr = bnapi->rx_ring; 5090 cp_cons = RING_CMP(raw_cons); 5091 rxcmp = (struct rx_cmp *) 5092 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 5093 cons = rxcmp->rx_cmp_opaque; 5094 rx_buf = &rxr->rx_buf_ring[cons]; 5095 data = rx_buf->data_ptr; 5096 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 5097 if (len != pkt_size) 5098 return -EIO; 5099 i = ETH_ALEN; 5100 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 5101 return -EIO; 5102 i += ETH_ALEN; 5103 for ( ; i < pkt_size; i++) { 5104 if (data[i] != (u8)(i & 0xff)) 5105 return -EIO; 5106 } 5107 return 0; 5108 } 5109 5110 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 5111 int pkt_size) 5112 { 5113 struct tx_cmp *txcmp; 5114 int rc = -EIO; 5115 u32 raw_cons; 5116 u32 cons; 5117 int i; 5118 5119 raw_cons = cpr->cp_raw_cons; 5120 for (i = 0; i < 200; i++) { 5121 cons = RING_CMP(raw_cons); 5122 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 5123 5124 if (!TX_CMP_VALID(txcmp, raw_cons)) { 5125 udelay(5); 5126 continue; 5127 } 5128 5129 /* The valid test of the entry must be done first before 5130 * reading any further. 5131 */ 5132 dma_rmb(); 5133 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP || 5134 TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_V3_CMP) { 5135 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 5136 raw_cons = NEXT_RAW_CMP(raw_cons); 5137 raw_cons = NEXT_RAW_CMP(raw_cons); 5138 break; 5139 } 5140 raw_cons = NEXT_RAW_CMP(raw_cons); 5141 } 5142 cpr->cp_raw_cons = raw_cons; 5143 return rc; 5144 } 5145 5146 static int bnxt_run_loopback(struct bnxt *bp) 5147 { 5148 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 5149 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 5150 struct bnxt_cp_ring_info *cpr; 5151 int pkt_size, i = 0; 5152 struct sk_buff *skb; 5153 dma_addr_t map; 5154 u8 *data; 5155 int rc; 5156 5157 cpr = &rxr->bnapi->cp_ring; 5158 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) 5159 cpr = rxr->rx_cpr; 5160 pkt_size = min(bp->dev->mtu + ETH_HLEN, max(BNXT_DEFAULT_RX_COPYBREAK, 5161 bp->rx_copybreak)); 5162 skb = netdev_alloc_skb(bp->dev, pkt_size); 5163 if (!skb) 5164 return -ENOMEM; 5165 data = skb_put(skb, pkt_size); 5166 ether_addr_copy(&data[i], bp->dev->dev_addr); 5167 i += ETH_ALEN; 5168 ether_addr_copy(&data[i], bp->dev->dev_addr); 5169 i += ETH_ALEN; 5170 for ( ; i < pkt_size; i++) 5171 data[i] = (u8)(i & 0xff); 5172 5173 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 5174 DMA_TO_DEVICE); 5175 if (dma_mapping_error(&bp->pdev->dev, map)) { 5176 dev_kfree_skb(skb); 5177 return -EIO; 5178 } 5179 bnxt_xmit_bd(bp, txr, map, pkt_size, NULL); 5180 5181 /* Sync BD data before updating doorbell */ 5182 wmb(); 5183 5184 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 5185 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 5186 5187 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE); 5188 dev_kfree_skb(skb); 5189 return rc; 5190 } 5191 5192 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 5193 { 5194 struct hwrm_selftest_exec_output *resp; 5195 struct hwrm_selftest_exec_input *req; 5196 int rc; 5197 5198 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC); 5199 if (rc) 5200 return rc; 5201 5202 hwrm_req_timeout(bp, req, bp->test_info->timeout); 5203 req->flags = test_mask; 5204 5205 resp = hwrm_req_hold(bp, req); 5206 rc = hwrm_req_send(bp, req); 5207 *test_results = resp->test_success; 5208 hwrm_req_drop(bp, req); 5209 return rc; 5210 } 5211 5212 #define BNXT_DRV_TESTS 4 5213 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 5214 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 5215 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 5216 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 5217 5218 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 5219 u64 *buf) 5220 { 5221 struct bnxt *bp = netdev_priv(dev); 5222 bool do_ext_lpbk = false; 5223 bool offline = false; 5224 u8 test_results = 0; 5225 u8 test_mask = 0; 5226 int rc = 0, i; 5227 5228 if (!bp->num_tests || !BNXT_PF(bp)) 5229 return; 5230 5231 memset(buf, 0, sizeof(u64) * bp->num_tests); 5232 if (etest->flags & ETH_TEST_FL_OFFLINE && 5233 bnxt_ulp_registered(bp->edev)) { 5234 etest->flags |= ETH_TEST_FL_FAILED; 5235 netdev_warn(dev, "Offline tests cannot be run with RoCE driver loaded\n"); 5236 return; 5237 } 5238 5239 if (!netif_running(dev)) { 5240 etest->flags |= ETH_TEST_FL_FAILED; 5241 return; 5242 } 5243 5244 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 5245 (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK)) 5246 do_ext_lpbk = true; 5247 5248 if (etest->flags & ETH_TEST_FL_OFFLINE) { 5249 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) { 5250 etest->flags |= ETH_TEST_FL_FAILED; 5251 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n"); 5252 return; 5253 } 5254 offline = true; 5255 } 5256 5257 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 5258 u8 bit_val = 1 << i; 5259 5260 if (!(bp->test_info->offline_mask & bit_val)) 5261 test_mask |= bit_val; 5262 else if (offline) 5263 test_mask |= bit_val; 5264 } 5265 if (!offline) { 5266 bnxt_run_fw_tests(bp, test_mask, &test_results); 5267 } else { 5268 bnxt_close_nic(bp, true, false); 5269 bnxt_run_fw_tests(bp, test_mask, &test_results); 5270 5271 rc = bnxt_half_open_nic(bp); 5272 if (rc) { 5273 etest->flags |= ETH_TEST_FL_FAILED; 5274 return; 5275 } 5276 buf[BNXT_MACLPBK_TEST_IDX] = 1; 5277 if (bp->mac_flags & BNXT_MAC_FL_NO_MAC_LPBK) 5278 goto skip_mac_loopback; 5279 5280 bnxt_hwrm_mac_loopback(bp, true); 5281 msleep(250); 5282 if (bnxt_run_loopback(bp)) 5283 etest->flags |= ETH_TEST_FL_FAILED; 5284 else 5285 buf[BNXT_MACLPBK_TEST_IDX] = 0; 5286 5287 bnxt_hwrm_mac_loopback(bp, false); 5288 skip_mac_loopback: 5289 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 5290 if (bp->phy_flags & BNXT_PHY_FL_NO_PHY_LPBK) 5291 goto skip_phy_loopback; 5292 5293 bnxt_hwrm_phy_loopback(bp, true, false); 5294 msleep(1000); 5295 if (bnxt_run_loopback(bp)) 5296 etest->flags |= ETH_TEST_FL_FAILED; 5297 else 5298 buf[BNXT_PHYLPBK_TEST_IDX] = 0; 5299 skip_phy_loopback: 5300 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 5301 if (do_ext_lpbk) { 5302 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 5303 bnxt_hwrm_phy_loopback(bp, true, true); 5304 msleep(1000); 5305 if (bnxt_run_loopback(bp)) 5306 etest->flags |= ETH_TEST_FL_FAILED; 5307 else 5308 buf[BNXT_EXTLPBK_TEST_IDX] = 0; 5309 } 5310 bnxt_hwrm_phy_loopback(bp, false, false); 5311 bnxt_half_close_nic(bp); 5312 rc = bnxt_open_nic(bp, true, true); 5313 } 5314 if (rc || bnxt_test_irq(bp)) { 5315 buf[BNXT_IRQ_TEST_IDX] = 1; 5316 etest->flags |= ETH_TEST_FL_FAILED; 5317 } 5318 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 5319 u8 bit_val = 1 << i; 5320 5321 if ((test_mask & bit_val) && !(test_results & bit_val)) { 5322 buf[i] = 1; 5323 etest->flags |= ETH_TEST_FL_FAILED; 5324 } 5325 } 5326 } 5327 5328 static int bnxt_reset(struct net_device *dev, u32 *flags) 5329 { 5330 struct bnxt *bp = netdev_priv(dev); 5331 bool reload = false; 5332 u32 req = *flags; 5333 5334 if (!req) 5335 return -EINVAL; 5336 5337 if (!BNXT_PF(bp)) { 5338 netdev_err(dev, "Reset is not supported from a VF\n"); 5339 return -EOPNOTSUPP; 5340 } 5341 5342 if (pci_vfs_assigned(bp->pdev) && 5343 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) { 5344 netdev_err(dev, 5345 "Reset not allowed when VFs are assigned to VMs\n"); 5346 return -EBUSY; 5347 } 5348 5349 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) { 5350 /* This feature is not supported in older firmware versions */ 5351 if (bp->hwrm_spec_code >= 0x10803) { 5352 if (!bnxt_firmware_reset_chip(dev)) { 5353 netdev_info(dev, "Firmware reset request successful.\n"); 5354 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) 5355 reload = true; 5356 *flags &= ~BNXT_FW_RESET_CHIP; 5357 } 5358 } else if (req == BNXT_FW_RESET_CHIP) { 5359 return -EOPNOTSUPP; /* only request, fail hard */ 5360 } 5361 } 5362 5363 if (!BNXT_CHIP_P4_PLUS(bp) && (req & BNXT_FW_RESET_AP)) { 5364 /* This feature is not supported in older firmware versions */ 5365 if (bp->hwrm_spec_code >= 0x10803) { 5366 if (!bnxt_firmware_reset_ap(dev)) { 5367 netdev_info(dev, "Reset application processor successful.\n"); 5368 reload = true; 5369 *flags &= ~BNXT_FW_RESET_AP; 5370 } 5371 } else if (req == BNXT_FW_RESET_AP) { 5372 return -EOPNOTSUPP; /* only request, fail hard */ 5373 } 5374 } 5375 5376 if (reload) 5377 netdev_info(dev, "Reload driver to complete reset\n"); 5378 5379 return 0; 5380 } 5381 5382 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump) 5383 { 5384 struct bnxt *bp = netdev_priv(dev); 5385 5386 if (dump->flag > BNXT_DUMP_LIVE_WITH_CTX_L1_CACHE) { 5387 netdev_info(dev, 5388 "Supports only Live(0), Crash(1), Driver(2), Live with cached context(3) dumps.\n"); 5389 return -EINVAL; 5390 } 5391 5392 if (dump->flag == BNXT_DUMP_CRASH) { 5393 if (bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR && 5394 (!IS_ENABLED(CONFIG_TEE_BNXT_FW))) { 5395 netdev_info(dev, 5396 "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n"); 5397 return -EOPNOTSUPP; 5398 } else if (!(bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR)) { 5399 netdev_info(dev, "Crash dump collection from host memory is not supported on this interface.\n"); 5400 return -EOPNOTSUPP; 5401 } 5402 } 5403 5404 bp->dump_flag = dump->flag; 5405 return 0; 5406 } 5407 5408 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 5409 { 5410 struct bnxt *bp = netdev_priv(dev); 5411 5412 if (bp->hwrm_spec_code < 0x10801) 5413 return -EOPNOTSUPP; 5414 5415 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 5416 bp->ver_resp.hwrm_fw_min_8b << 16 | 5417 bp->ver_resp.hwrm_fw_bld_8b << 8 | 5418 bp->ver_resp.hwrm_fw_rsvd_8b; 5419 5420 dump->flag = bp->dump_flag; 5421 dump->len = bnxt_get_coredump_length(bp, bp->dump_flag); 5422 return 0; 5423 } 5424 5425 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 5426 void *buf) 5427 { 5428 struct bnxt *bp = netdev_priv(dev); 5429 5430 if (bp->hwrm_spec_code < 0x10801) 5431 return -EOPNOTSUPP; 5432 5433 memset(buf, 0, dump->len); 5434 5435 dump->flag = bp->dump_flag; 5436 return bnxt_get_coredump(bp, dump->flag, buf, &dump->len); 5437 } 5438 5439 static int bnxt_get_ts_info(struct net_device *dev, 5440 struct kernel_ethtool_ts_info *info) 5441 { 5442 struct bnxt *bp = netdev_priv(dev); 5443 struct bnxt_ptp_cfg *ptp; 5444 5445 ptp = bp->ptp_cfg; 5446 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE; 5447 5448 if (!ptp) 5449 return 0; 5450 5451 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | 5452 SOF_TIMESTAMPING_RX_HARDWARE | 5453 SOF_TIMESTAMPING_RAW_HARDWARE; 5454 if (ptp->ptp_clock) 5455 info->phc_index = ptp_clock_index(ptp->ptp_clock); 5456 5457 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 5458 5459 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 5460 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 5461 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 5462 5463 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) 5464 info->rx_filters |= (1 << HWTSTAMP_FILTER_ALL); 5465 return 0; 5466 } 5467 5468 static void bnxt_hwrm_pcie_qstats(struct bnxt *bp) 5469 { 5470 struct hwrm_pcie_qstats_output *resp; 5471 struct hwrm_pcie_qstats_input *req; 5472 5473 bp->pcie_stat_len = 0; 5474 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 5475 return; 5476 5477 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS)) 5478 return; 5479 5480 resp = hwrm_req_hold(bp, req); 5481 if (__bnxt_hwrm_pcie_qstats(bp, req)) 5482 bp->pcie_stat_len = min_t(u16, 5483 le16_to_cpu(resp->pcie_stat_size), 5484 sizeof(struct pcie_ctx_hw_stats_v2)); 5485 hwrm_req_drop(bp, req); 5486 } 5487 5488 void bnxt_ethtool_init(struct bnxt *bp) 5489 { 5490 struct hwrm_selftest_qlist_output *resp; 5491 struct hwrm_selftest_qlist_input *req; 5492 struct bnxt_test_info *test_info; 5493 struct net_device *dev = bp->dev; 5494 int i, rc; 5495 5496 bnxt_hwrm_pcie_qstats(bp); 5497 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 5498 bnxt_get_pkgver(dev); 5499 5500 bp->num_tests = 0; 5501 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp)) 5502 return; 5503 5504 test_info = bp->test_info; 5505 if (!test_info) { 5506 test_info = kzalloc_obj(*bp->test_info); 5507 if (!test_info) 5508 return; 5509 bp->test_info = test_info; 5510 } 5511 5512 if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST)) 5513 return; 5514 5515 resp = hwrm_req_hold(bp, req); 5516 rc = hwrm_req_send_silent(bp, req); 5517 if (rc) 5518 goto ethtool_init_exit; 5519 5520 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 5521 if (bp->num_tests > BNXT_MAX_TEST) 5522 bp->num_tests = BNXT_MAX_TEST; 5523 5524 test_info->offline_mask = resp->offline_tests; 5525 test_info->timeout = le16_to_cpu(resp->test_timeout); 5526 if (!test_info->timeout) 5527 test_info->timeout = HWRM_CMD_TIMEOUT; 5528 for (i = 0; i < bp->num_tests; i++) { 5529 char *str = test_info->string[i]; 5530 char *fw_str = resp->test_name[i]; 5531 5532 if (i == BNXT_MACLPBK_TEST_IDX) { 5533 strcpy(str, "Mac loopback test (offline)"); 5534 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 5535 strcpy(str, "Phy loopback test (offline)"); 5536 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 5537 strcpy(str, "Ext loopback test (offline)"); 5538 } else if (i == BNXT_IRQ_TEST_IDX) { 5539 strcpy(str, "Interrupt_test (offline)"); 5540 } else { 5541 snprintf(str, ETH_GSTRING_LEN, "%s test (%s)", 5542 fw_str, test_info->offline_mask & (1 << i) ? 5543 "offline" : "online"); 5544 } 5545 } 5546 5547 ethtool_init_exit: 5548 hwrm_req_drop(bp, req); 5549 } 5550 5551 static void bnxt_get_eth_phy_stats(struct net_device *dev, 5552 struct ethtool_eth_phy_stats *phy_stats) 5553 { 5554 struct bnxt *bp = netdev_priv(dev); 5555 u64 *rx; 5556 5557 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 5558 return; 5559 5560 rx = bp->rx_port_stats_ext.sw_stats; 5561 phy_stats->SymbolErrorDuringCarrier = 5562 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err)); 5563 } 5564 5565 static void bnxt_get_eth_mac_stats(struct net_device *dev, 5566 struct ethtool_eth_mac_stats *mac_stats) 5567 { 5568 struct bnxt *bp = netdev_priv(dev); 5569 u64 *rx, *tx; 5570 5571 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5572 return; 5573 5574 rx = bp->port_stats.sw_stats; 5575 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 5576 5577 mac_stats->FramesReceivedOK = 5578 BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames); 5579 mac_stats->FramesTransmittedOK = 5580 BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames); 5581 mac_stats->FrameCheckSequenceErrors = 5582 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames); 5583 mac_stats->AlignmentErrors = 5584 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames); 5585 mac_stats->OutOfRangeLengthField = 5586 BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames); 5587 } 5588 5589 static void bnxt_get_eth_ctrl_stats(struct net_device *dev, 5590 struct ethtool_eth_ctrl_stats *ctrl_stats) 5591 { 5592 struct bnxt *bp = netdev_priv(dev); 5593 u64 *rx; 5594 5595 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5596 return; 5597 5598 rx = bp->port_stats.sw_stats; 5599 ctrl_stats->MACControlFramesReceived = 5600 BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames); 5601 } 5602 5603 static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = { 5604 { 0, 64 }, 5605 { 65, 127 }, 5606 { 128, 255 }, 5607 { 256, 511 }, 5608 { 512, 1023 }, 5609 { 1024, 1518 }, 5610 { 1519, 2047 }, 5611 { 2048, 4095 }, 5612 { 4096, 9216 }, 5613 { 9217, 16383 }, 5614 {} 5615 }; 5616 5617 static void bnxt_get_rmon_stats(struct net_device *dev, 5618 struct ethtool_rmon_stats *rmon_stats, 5619 const struct ethtool_rmon_hist_range **ranges) 5620 { 5621 struct bnxt *bp = netdev_priv(dev); 5622 u64 *rx, *tx; 5623 5624 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 5625 return; 5626 5627 rx = bp->port_stats.sw_stats; 5628 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 5629 5630 rmon_stats->jabbers = 5631 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames); 5632 rmon_stats->oversize_pkts = 5633 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames); 5634 rmon_stats->undersize_pkts = 5635 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames); 5636 5637 rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames); 5638 rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames); 5639 rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames); 5640 rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames); 5641 rmon_stats->hist[4] = 5642 BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames); 5643 rmon_stats->hist[5] = 5644 BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames); 5645 rmon_stats->hist[6] = 5646 BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames); 5647 rmon_stats->hist[7] = 5648 BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames); 5649 rmon_stats->hist[8] = 5650 BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames); 5651 rmon_stats->hist[9] = 5652 BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames); 5653 5654 rmon_stats->hist_tx[0] = 5655 BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames); 5656 rmon_stats->hist_tx[1] = 5657 BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames); 5658 rmon_stats->hist_tx[2] = 5659 BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames); 5660 rmon_stats->hist_tx[3] = 5661 BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames); 5662 rmon_stats->hist_tx[4] = 5663 BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames); 5664 rmon_stats->hist_tx[5] = 5665 BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames); 5666 rmon_stats->hist_tx[6] = 5667 BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames); 5668 rmon_stats->hist_tx[7] = 5669 BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames); 5670 rmon_stats->hist_tx[8] = 5671 BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames); 5672 rmon_stats->hist_tx[9] = 5673 BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames); 5674 5675 *ranges = bnxt_rmon_ranges; 5676 } 5677 5678 static void bnxt_get_ptp_stats(struct net_device *dev, 5679 struct ethtool_ts_stats *ts_stats) 5680 { 5681 struct bnxt *bp = netdev_priv(dev); 5682 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 5683 5684 if (ptp) { 5685 ts_stats->pkts = ptp->stats.ts_pkts; 5686 ts_stats->lost = ptp->stats.ts_lost; 5687 ts_stats->err = atomic64_read(&ptp->stats.ts_err); 5688 } 5689 } 5690 5691 static void bnxt_get_link_ext_stats(struct net_device *dev, 5692 struct ethtool_link_ext_stats *stats) 5693 { 5694 struct bnxt *bp = netdev_priv(dev); 5695 u64 *rx; 5696 5697 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 5698 return; 5699 5700 rx = bp->rx_port_stats_ext.sw_stats; 5701 stats->link_down_events = 5702 *(rx + BNXT_RX_STATS_EXT_OFFSET(link_down_events)); 5703 } 5704 5705 void bnxt_ethtool_free(struct bnxt *bp) 5706 { 5707 kfree(bp->test_info); 5708 bp->test_info = NULL; 5709 } 5710 5711 const struct ethtool_ops bnxt_ethtool_ops = { 5712 .cap_link_lanes_supported = 1, 5713 .rxfh_per_ctx_key = 1, 5714 .rxfh_max_num_contexts = BNXT_MAX_ETH_RSS_CTX + 1, 5715 .rxfh_indir_space = BNXT_MAX_RSS_TABLE_ENTRIES_P5, 5716 .rxfh_priv_size = sizeof(struct bnxt_rss_ctx), 5717 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 5718 ETHTOOL_COALESCE_MAX_FRAMES | 5719 ETHTOOL_COALESCE_USECS_IRQ | 5720 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 5721 ETHTOOL_COALESCE_STATS_BLOCK_USECS | 5722 ETHTOOL_COALESCE_USE_ADAPTIVE_RX | 5723 ETHTOOL_COALESCE_USE_CQE, 5724 .supported_ring_params = ETHTOOL_RING_USE_TCP_DATA_SPLIT | 5725 ETHTOOL_RING_USE_HDS_THRS, 5726 .get_link_ksettings = bnxt_get_link_ksettings, 5727 .set_link_ksettings = bnxt_set_link_ksettings, 5728 .get_fec_stats = bnxt_get_fec_stats, 5729 .get_fecparam = bnxt_get_fecparam, 5730 .set_fecparam = bnxt_set_fecparam, 5731 .get_pause_stats = bnxt_get_pause_stats, 5732 .get_pauseparam = bnxt_get_pauseparam, 5733 .set_pauseparam = bnxt_set_pauseparam, 5734 .get_drvinfo = bnxt_get_drvinfo, 5735 .get_regs_len = bnxt_get_regs_len, 5736 .get_regs = bnxt_get_regs, 5737 .get_wol = bnxt_get_wol, 5738 .set_wol = bnxt_set_wol, 5739 .get_coalesce = bnxt_get_coalesce, 5740 .set_coalesce = bnxt_set_coalesce, 5741 .get_msglevel = bnxt_get_msglevel, 5742 .set_msglevel = bnxt_set_msglevel, 5743 .get_sset_count = bnxt_get_sset_count, 5744 .get_strings = bnxt_get_strings, 5745 .get_ethtool_stats = bnxt_get_ethtool_stats, 5746 .set_ringparam = bnxt_set_ringparam, 5747 .get_ringparam = bnxt_get_ringparam, 5748 .get_channels = bnxt_get_channels, 5749 .set_channels = bnxt_set_channels, 5750 .get_rxnfc = bnxt_get_rxnfc, 5751 .set_rxnfc = bnxt_set_rxnfc, 5752 .get_rx_ring_count = bnxt_get_rx_ring_count, 5753 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 5754 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 5755 .get_rxfh = bnxt_get_rxfh, 5756 .set_rxfh = bnxt_set_rxfh, 5757 .get_rxfh_fields = bnxt_get_rxfh_fields, 5758 .set_rxfh_fields = bnxt_set_rxfh_fields, 5759 .create_rxfh_context = bnxt_create_rxfh_context, 5760 .modify_rxfh_context = bnxt_modify_rxfh_context, 5761 .remove_rxfh_context = bnxt_remove_rxfh_context, 5762 .flash_device = bnxt_flash_device, 5763 .get_eeprom_len = bnxt_get_eeprom_len, 5764 .get_eeprom = bnxt_get_eeprom, 5765 .set_eeprom = bnxt_set_eeprom, 5766 .get_link = bnxt_get_link, 5767 .get_link_ext_state = bnxt_get_link_ext_state, 5768 .get_link_ext_stats = bnxt_get_link_ext_stats, 5769 .get_eee = bnxt_get_eee, 5770 .set_eee = bnxt_set_eee, 5771 .get_tunable = bnxt_get_tunable, 5772 .set_tunable = bnxt_set_tunable, 5773 .get_module_info = bnxt_get_module_info, 5774 .get_module_eeprom = bnxt_get_module_eeprom, 5775 .get_module_eeprom_by_page = bnxt_get_module_eeprom_by_page, 5776 .set_module_eeprom_by_page = bnxt_set_module_eeprom_by_page, 5777 .nway_reset = bnxt_nway_reset, 5778 .set_phys_id = bnxt_set_phys_id, 5779 .self_test = bnxt_self_test, 5780 .get_ts_info = bnxt_get_ts_info, 5781 .reset = bnxt_reset, 5782 .set_dump = bnxt_set_dump, 5783 .get_dump_flag = bnxt_get_dump_flag, 5784 .get_dump_data = bnxt_get_dump_data, 5785 .get_eth_phy_stats = bnxt_get_eth_phy_stats, 5786 .get_eth_mac_stats = bnxt_get_eth_mac_stats, 5787 .get_eth_ctrl_stats = bnxt_get_eth_ctrl_stats, 5788 .get_rmon_stats = bnxt_get_rmon_stats, 5789 .get_ts_stats = bnxt_get_ptp_stats, 5790 }; 5791