1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/ctype.h> 12 #include <linux/stringify.h> 13 #include <linux/ethtool.h> 14 #include <linux/ethtool_netlink.h> 15 #include <linux/linkmode.h> 16 #include <linux/interrupt.h> 17 #include <linux/pci.h> 18 #include <linux/etherdevice.h> 19 #include <linux/crc32.h> 20 #include <linux/firmware.h> 21 #include <linux/utsname.h> 22 #include <linux/time.h> 23 #include <linux/ptp_clock_kernel.h> 24 #include <linux/net_tstamp.h> 25 #include <linux/timecounter.h> 26 #include "bnxt_hsi.h" 27 #include "bnxt.h" 28 #include "bnxt_hwrm.h" 29 #include "bnxt_ulp.h" 30 #include "bnxt_xdp.h" 31 #include "bnxt_ptp.h" 32 #include "bnxt_ethtool.h" 33 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 34 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 35 #include "bnxt_coredump.h" 36 37 static u32 bnxt_get_msglevel(struct net_device *dev) 38 { 39 struct bnxt *bp = netdev_priv(dev); 40 41 return bp->msg_enable; 42 } 43 44 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 45 { 46 struct bnxt *bp = netdev_priv(dev); 47 48 bp->msg_enable = value; 49 } 50 51 static int bnxt_get_coalesce(struct net_device *dev, 52 struct ethtool_coalesce *coal, 53 struct kernel_ethtool_coalesce *kernel_coal, 54 struct netlink_ext_ack *extack) 55 { 56 struct bnxt *bp = netdev_priv(dev); 57 struct bnxt_coal *hw_coal; 58 u16 mult; 59 60 memset(coal, 0, sizeof(*coal)); 61 62 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 63 64 hw_coal = &bp->rx_coal; 65 mult = hw_coal->bufs_per_record; 66 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 67 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 68 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 69 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 70 if (hw_coal->flags & 71 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 72 kernel_coal->use_cqe_mode_rx = true; 73 74 hw_coal = &bp->tx_coal; 75 mult = hw_coal->bufs_per_record; 76 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 77 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 78 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 79 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 80 if (hw_coal->flags & 81 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 82 kernel_coal->use_cqe_mode_tx = true; 83 84 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 85 86 return 0; 87 } 88 89 static int bnxt_set_coalesce(struct net_device *dev, 90 struct ethtool_coalesce *coal, 91 struct kernel_ethtool_coalesce *kernel_coal, 92 struct netlink_ext_ack *extack) 93 { 94 struct bnxt *bp = netdev_priv(dev); 95 bool update_stats = false; 96 struct bnxt_coal *hw_coal; 97 int rc = 0; 98 u16 mult; 99 100 if (coal->use_adaptive_rx_coalesce) { 101 bp->flags |= BNXT_FLAG_DIM; 102 } else { 103 if (bp->flags & BNXT_FLAG_DIM) { 104 bp->flags &= ~(BNXT_FLAG_DIM); 105 goto reset_coalesce; 106 } 107 } 108 109 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) && 110 !(bp->coal_cap.cmpl_params & 111 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)) 112 return -EOPNOTSUPP; 113 114 hw_coal = &bp->rx_coal; 115 mult = hw_coal->bufs_per_record; 116 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 117 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 118 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 119 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 120 hw_coal->flags &= 121 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 122 if (kernel_coal->use_cqe_mode_rx) 123 hw_coal->flags |= 124 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 125 126 hw_coal = &bp->tx_coal; 127 mult = hw_coal->bufs_per_record; 128 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 129 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 130 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 131 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 132 hw_coal->flags &= 133 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 134 if (kernel_coal->use_cqe_mode_tx) 135 hw_coal->flags |= 136 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 137 138 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 139 u32 stats_ticks = coal->stats_block_coalesce_usecs; 140 141 /* Allow 0, which means disable. */ 142 if (stats_ticks) 143 stats_ticks = clamp_t(u32, stats_ticks, 144 BNXT_MIN_STATS_COAL_TICKS, 145 BNXT_MAX_STATS_COAL_TICKS); 146 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 147 bp->stats_coal_ticks = stats_ticks; 148 if (bp->stats_coal_ticks) 149 bp->current_interval = 150 bp->stats_coal_ticks * HZ / 1000000; 151 else 152 bp->current_interval = BNXT_TIMER_INTERVAL; 153 update_stats = true; 154 } 155 156 reset_coalesce: 157 if (netif_running(dev)) { 158 if (update_stats) { 159 rc = bnxt_close_nic(bp, true, false); 160 if (!rc) 161 rc = bnxt_open_nic(bp, true, false); 162 } else { 163 rc = bnxt_hwrm_set_coal(bp); 164 } 165 } 166 167 return rc; 168 } 169 170 static const char * const bnxt_ring_rx_stats_str[] = { 171 "rx_ucast_packets", 172 "rx_mcast_packets", 173 "rx_bcast_packets", 174 "rx_discards", 175 "rx_errors", 176 "rx_ucast_bytes", 177 "rx_mcast_bytes", 178 "rx_bcast_bytes", 179 }; 180 181 static const char * const bnxt_ring_tx_stats_str[] = { 182 "tx_ucast_packets", 183 "tx_mcast_packets", 184 "tx_bcast_packets", 185 "tx_errors", 186 "tx_discards", 187 "tx_ucast_bytes", 188 "tx_mcast_bytes", 189 "tx_bcast_bytes", 190 }; 191 192 static const char * const bnxt_ring_tpa_stats_str[] = { 193 "tpa_packets", 194 "tpa_bytes", 195 "tpa_events", 196 "tpa_aborts", 197 }; 198 199 static const char * const bnxt_ring_tpa2_stats_str[] = { 200 "rx_tpa_eligible_pkt", 201 "rx_tpa_eligible_bytes", 202 "rx_tpa_pkt", 203 "rx_tpa_bytes", 204 "rx_tpa_errors", 205 "rx_tpa_events", 206 }; 207 208 static const char * const bnxt_rx_sw_stats_str[] = { 209 "rx_l4_csum_errors", 210 "rx_resets", 211 "rx_buf_errors", 212 }; 213 214 static const char * const bnxt_cmn_sw_stats_str[] = { 215 "missed_irqs", 216 }; 217 218 #define BNXT_RX_STATS_ENTRY(counter) \ 219 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 220 221 #define BNXT_TX_STATS_ENTRY(counter) \ 222 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 223 224 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 225 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 226 227 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 228 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 229 230 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 231 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 232 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 233 234 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 235 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 236 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 237 238 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 239 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 240 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 241 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 242 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 243 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 244 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 245 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 246 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 247 248 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 249 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 250 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 251 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 252 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 253 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 254 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 255 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 256 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 257 258 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 259 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 260 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 261 262 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 263 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 264 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 265 266 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 267 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 268 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 269 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 270 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 271 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 272 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 273 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 274 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 275 276 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 277 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 278 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 279 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 280 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 281 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 282 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 283 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 284 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 285 286 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 287 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 288 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 289 290 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 291 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 292 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 293 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 294 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 295 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 296 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 297 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 298 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 299 300 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 301 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 302 __stringify(counter##_pri##n) } 303 304 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 305 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 306 __stringify(counter##_pri##n) } 307 308 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 309 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 310 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 311 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 312 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 313 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 314 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 315 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 316 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 317 318 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 319 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 320 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 321 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 322 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 323 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 324 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 325 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 326 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 327 328 enum { 329 RX_TOTAL_DISCARDS, 330 TX_TOTAL_DISCARDS, 331 RX_NETPOLL_DISCARDS, 332 }; 333 334 static struct { 335 u64 counter; 336 char string[ETH_GSTRING_LEN]; 337 } bnxt_sw_func_stats[] = { 338 {0, "rx_total_discard_pkts"}, 339 {0, "tx_total_discard_pkts"}, 340 {0, "rx_total_netpoll_discards"}, 341 }; 342 343 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str) 344 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str) 345 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str) 346 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str) 347 348 static const struct { 349 long offset; 350 char string[ETH_GSTRING_LEN]; 351 } bnxt_port_stats_arr[] = { 352 BNXT_RX_STATS_ENTRY(rx_64b_frames), 353 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 354 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 355 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 356 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 357 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 358 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 359 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 360 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 361 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 362 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 363 BNXT_RX_STATS_ENTRY(rx_total_frames), 364 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 365 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 366 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 367 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 368 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 369 BNXT_RX_STATS_ENTRY(rx_pause_frames), 370 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 371 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 372 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 373 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 374 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 375 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 376 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 377 BNXT_RX_STATS_ENTRY(rx_good_frames), 378 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 379 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 380 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 381 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 382 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 383 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 384 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 385 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 386 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 387 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 388 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 389 BNXT_RX_STATS_ENTRY(rx_bytes), 390 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 391 BNXT_RX_STATS_ENTRY(rx_runt_frames), 392 BNXT_RX_STATS_ENTRY(rx_stat_discard), 393 BNXT_RX_STATS_ENTRY(rx_stat_err), 394 395 BNXT_TX_STATS_ENTRY(tx_64b_frames), 396 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 397 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 398 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 399 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 400 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 401 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 402 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 403 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 404 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 405 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 406 BNXT_TX_STATS_ENTRY(tx_good_frames), 407 BNXT_TX_STATS_ENTRY(tx_total_frames), 408 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 409 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 410 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 411 BNXT_TX_STATS_ENTRY(tx_pause_frames), 412 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 413 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 414 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 415 BNXT_TX_STATS_ENTRY(tx_err), 416 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 417 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 418 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 419 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 420 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 421 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 422 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 423 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 424 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 425 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 426 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 427 BNXT_TX_STATS_ENTRY(tx_total_collisions), 428 BNXT_TX_STATS_ENTRY(tx_bytes), 429 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 430 BNXT_TX_STATS_ENTRY(tx_stat_discard), 431 BNXT_TX_STATS_ENTRY(tx_stat_error), 432 }; 433 434 static const struct { 435 long offset; 436 char string[ETH_GSTRING_LEN]; 437 } bnxt_port_stats_ext_arr[] = { 438 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 439 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 440 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 441 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 442 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 443 BNXT_RX_STATS_EXT_COS_ENTRIES, 444 BNXT_RX_STATS_EXT_PFC_ENTRIES, 445 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 446 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 447 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 448 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 449 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 450 BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks), 451 BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks), 452 }; 453 454 static const struct { 455 long offset; 456 char string[ETH_GSTRING_LEN]; 457 } bnxt_tx_port_stats_ext_arr[] = { 458 BNXT_TX_STATS_EXT_COS_ENTRIES, 459 BNXT_TX_STATS_EXT_PFC_ENTRIES, 460 }; 461 462 static const struct { 463 long base_off; 464 char string[ETH_GSTRING_LEN]; 465 } bnxt_rx_bytes_pri_arr[] = { 466 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 467 }; 468 469 static const struct { 470 long base_off; 471 char string[ETH_GSTRING_LEN]; 472 } bnxt_rx_pkts_pri_arr[] = { 473 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 474 }; 475 476 static const struct { 477 long base_off; 478 char string[ETH_GSTRING_LEN]; 479 } bnxt_tx_bytes_pri_arr[] = { 480 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 481 }; 482 483 static const struct { 484 long base_off; 485 char string[ETH_GSTRING_LEN]; 486 } bnxt_tx_pkts_pri_arr[] = { 487 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 488 }; 489 490 #define BNXT_NUM_SW_FUNC_STATS ARRAY_SIZE(bnxt_sw_func_stats) 491 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 492 #define BNXT_NUM_STATS_PRI \ 493 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 494 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 495 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 496 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 497 498 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 499 { 500 if (BNXT_SUPPORTS_TPA(bp)) { 501 if (bp->max_tpa_v2) { 502 if (BNXT_CHIP_P5_THOR(bp)) 503 return BNXT_NUM_TPA_RING_STATS_P5; 504 return BNXT_NUM_TPA_RING_STATS_P5_SR2; 505 } 506 return BNXT_NUM_TPA_RING_STATS; 507 } 508 return 0; 509 } 510 511 static int bnxt_get_num_ring_stats(struct bnxt *bp) 512 { 513 int rx, tx, cmn; 514 515 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS + 516 bnxt_get_num_tpa_ring_stats(bp); 517 tx = NUM_RING_TX_HW_STATS; 518 cmn = NUM_RING_CMN_SW_STATS; 519 return rx * bp->rx_nr_rings + tx * bp->tx_nr_rings + 520 cmn * bp->cp_nr_rings; 521 } 522 523 static int bnxt_get_num_stats(struct bnxt *bp) 524 { 525 int num_stats = bnxt_get_num_ring_stats(bp); 526 527 num_stats += BNXT_NUM_SW_FUNC_STATS; 528 529 if (bp->flags & BNXT_FLAG_PORT_STATS) 530 num_stats += BNXT_NUM_PORT_STATS; 531 532 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 533 num_stats += bp->fw_rx_stats_ext_size + 534 bp->fw_tx_stats_ext_size; 535 if (bp->pri2cos_valid) 536 num_stats += BNXT_NUM_STATS_PRI; 537 } 538 539 return num_stats; 540 } 541 542 static int bnxt_get_sset_count(struct net_device *dev, int sset) 543 { 544 struct bnxt *bp = netdev_priv(dev); 545 546 switch (sset) { 547 case ETH_SS_STATS: 548 return bnxt_get_num_stats(bp); 549 case ETH_SS_TEST: 550 if (!bp->num_tests) 551 return -EOPNOTSUPP; 552 return bp->num_tests; 553 default: 554 return -EOPNOTSUPP; 555 } 556 } 557 558 static bool is_rx_ring(struct bnxt *bp, int ring_num) 559 { 560 return ring_num < bp->rx_nr_rings; 561 } 562 563 static bool is_tx_ring(struct bnxt *bp, int ring_num) 564 { 565 int tx_base = 0; 566 567 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 568 tx_base = bp->rx_nr_rings; 569 570 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings)) 571 return true; 572 return false; 573 } 574 575 static void bnxt_get_ethtool_stats(struct net_device *dev, 576 struct ethtool_stats *stats, u64 *buf) 577 { 578 u32 i, j = 0; 579 struct bnxt *bp = netdev_priv(dev); 580 u32 tpa_stats; 581 582 if (!bp->bnapi) { 583 j += bnxt_get_num_ring_stats(bp) + BNXT_NUM_SW_FUNC_STATS; 584 goto skip_ring_stats; 585 } 586 587 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) 588 bnxt_sw_func_stats[i].counter = 0; 589 590 tpa_stats = bnxt_get_num_tpa_ring_stats(bp); 591 for (i = 0; i < bp->cp_nr_rings; i++) { 592 struct bnxt_napi *bnapi = bp->bnapi[i]; 593 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 594 u64 *sw_stats = cpr->stats.sw_stats; 595 u64 *sw; 596 int k; 597 598 if (is_rx_ring(bp, i)) { 599 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++) 600 buf[j] = sw_stats[k]; 601 } 602 if (is_tx_ring(bp, i)) { 603 k = NUM_RING_RX_HW_STATS; 604 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 605 j++, k++) 606 buf[j] = sw_stats[k]; 607 } 608 if (!tpa_stats || !is_rx_ring(bp, i)) 609 goto skip_tpa_ring_stats; 610 611 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 612 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS + 613 tpa_stats; j++, k++) 614 buf[j] = sw_stats[k]; 615 616 skip_tpa_ring_stats: 617 sw = (u64 *)&cpr->sw_stats.rx; 618 if (is_rx_ring(bp, i)) { 619 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++) 620 buf[j] = sw[k]; 621 } 622 623 sw = (u64 *)&cpr->sw_stats.cmn; 624 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++) 625 buf[j] = sw[k]; 626 627 bnxt_sw_func_stats[RX_TOTAL_DISCARDS].counter += 628 BNXT_GET_RING_STATS64(sw_stats, rx_discard_pkts); 629 bnxt_sw_func_stats[TX_TOTAL_DISCARDS].counter += 630 BNXT_GET_RING_STATS64(sw_stats, tx_discard_pkts); 631 bnxt_sw_func_stats[RX_NETPOLL_DISCARDS].counter += 632 cpr->sw_stats.rx.rx_netpoll_discards; 633 } 634 635 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++, j++) 636 buf[j] = bnxt_sw_func_stats[i].counter; 637 638 skip_ring_stats: 639 if (bp->flags & BNXT_FLAG_PORT_STATS) { 640 u64 *port_stats = bp->port_stats.sw_stats; 641 642 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) 643 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset); 644 } 645 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 646 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats; 647 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats; 648 649 for (i = 0; i < bp->fw_rx_stats_ext_size; i++, j++) { 650 buf[j] = *(rx_port_stats_ext + 651 bnxt_port_stats_ext_arr[i].offset); 652 } 653 for (i = 0; i < bp->fw_tx_stats_ext_size; i++, j++) { 654 buf[j] = *(tx_port_stats_ext + 655 bnxt_tx_port_stats_ext_arr[i].offset); 656 } 657 if (bp->pri2cos_valid) { 658 for (i = 0; i < 8; i++, j++) { 659 long n = bnxt_rx_bytes_pri_arr[i].base_off + 660 bp->pri2cos_idx[i]; 661 662 buf[j] = *(rx_port_stats_ext + n); 663 } 664 for (i = 0; i < 8; i++, j++) { 665 long n = bnxt_rx_pkts_pri_arr[i].base_off + 666 bp->pri2cos_idx[i]; 667 668 buf[j] = *(rx_port_stats_ext + n); 669 } 670 for (i = 0; i < 8; i++, j++) { 671 long n = bnxt_tx_bytes_pri_arr[i].base_off + 672 bp->pri2cos_idx[i]; 673 674 buf[j] = *(tx_port_stats_ext + n); 675 } 676 for (i = 0; i < 8; i++, j++) { 677 long n = bnxt_tx_pkts_pri_arr[i].base_off + 678 bp->pri2cos_idx[i]; 679 680 buf[j] = *(tx_port_stats_ext + n); 681 } 682 } 683 } 684 } 685 686 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 687 { 688 struct bnxt *bp = netdev_priv(dev); 689 static const char * const *str; 690 u32 i, j, num_str; 691 692 switch (stringset) { 693 case ETH_SS_STATS: 694 for (i = 0; i < bp->cp_nr_rings; i++) { 695 if (is_rx_ring(bp, i)) { 696 num_str = NUM_RING_RX_HW_STATS; 697 for (j = 0; j < num_str; j++) { 698 sprintf(buf, "[%d]: %s", i, 699 bnxt_ring_rx_stats_str[j]); 700 buf += ETH_GSTRING_LEN; 701 } 702 } 703 if (is_tx_ring(bp, i)) { 704 num_str = NUM_RING_TX_HW_STATS; 705 for (j = 0; j < num_str; j++) { 706 sprintf(buf, "[%d]: %s", i, 707 bnxt_ring_tx_stats_str[j]); 708 buf += ETH_GSTRING_LEN; 709 } 710 } 711 num_str = bnxt_get_num_tpa_ring_stats(bp); 712 if (!num_str || !is_rx_ring(bp, i)) 713 goto skip_tpa_stats; 714 715 if (bp->max_tpa_v2) 716 str = bnxt_ring_tpa2_stats_str; 717 else 718 str = bnxt_ring_tpa_stats_str; 719 720 for (j = 0; j < num_str; j++) { 721 sprintf(buf, "[%d]: %s", i, str[j]); 722 buf += ETH_GSTRING_LEN; 723 } 724 skip_tpa_stats: 725 if (is_rx_ring(bp, i)) { 726 num_str = NUM_RING_RX_SW_STATS; 727 for (j = 0; j < num_str; j++) { 728 sprintf(buf, "[%d]: %s", i, 729 bnxt_rx_sw_stats_str[j]); 730 buf += ETH_GSTRING_LEN; 731 } 732 } 733 num_str = NUM_RING_CMN_SW_STATS; 734 for (j = 0; j < num_str; j++) { 735 sprintf(buf, "[%d]: %s", i, 736 bnxt_cmn_sw_stats_str[j]); 737 buf += ETH_GSTRING_LEN; 738 } 739 } 740 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) { 741 strcpy(buf, bnxt_sw_func_stats[i].string); 742 buf += ETH_GSTRING_LEN; 743 } 744 745 if (bp->flags & BNXT_FLAG_PORT_STATS) { 746 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 747 strcpy(buf, bnxt_port_stats_arr[i].string); 748 buf += ETH_GSTRING_LEN; 749 } 750 } 751 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 752 for (i = 0; i < bp->fw_rx_stats_ext_size; i++) { 753 strcpy(buf, bnxt_port_stats_ext_arr[i].string); 754 buf += ETH_GSTRING_LEN; 755 } 756 for (i = 0; i < bp->fw_tx_stats_ext_size; i++) { 757 strcpy(buf, 758 bnxt_tx_port_stats_ext_arr[i].string); 759 buf += ETH_GSTRING_LEN; 760 } 761 if (bp->pri2cos_valid) { 762 for (i = 0; i < 8; i++) { 763 strcpy(buf, 764 bnxt_rx_bytes_pri_arr[i].string); 765 buf += ETH_GSTRING_LEN; 766 } 767 for (i = 0; i < 8; i++) { 768 strcpy(buf, 769 bnxt_rx_pkts_pri_arr[i].string); 770 buf += ETH_GSTRING_LEN; 771 } 772 for (i = 0; i < 8; i++) { 773 strcpy(buf, 774 bnxt_tx_bytes_pri_arr[i].string); 775 buf += ETH_GSTRING_LEN; 776 } 777 for (i = 0; i < 8; i++) { 778 strcpy(buf, 779 bnxt_tx_pkts_pri_arr[i].string); 780 buf += ETH_GSTRING_LEN; 781 } 782 } 783 } 784 break; 785 case ETH_SS_TEST: 786 if (bp->num_tests) 787 memcpy(buf, bp->test_info->string, 788 bp->num_tests * ETH_GSTRING_LEN); 789 break; 790 default: 791 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 792 stringset); 793 break; 794 } 795 } 796 797 static void bnxt_get_ringparam(struct net_device *dev, 798 struct ethtool_ringparam *ering, 799 struct kernel_ethtool_ringparam *kernel_ering, 800 struct netlink_ext_ack *extack) 801 { 802 struct bnxt *bp = netdev_priv(dev); 803 804 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 805 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA; 806 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 807 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_ENABLED; 808 } else { 809 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 810 ering->rx_jumbo_max_pending = 0; 811 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_DISABLED; 812 } 813 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 814 815 ering->rx_pending = bp->rx_ring_size; 816 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 817 ering->tx_pending = bp->tx_ring_size; 818 } 819 820 static int bnxt_set_ringparam(struct net_device *dev, 821 struct ethtool_ringparam *ering, 822 struct kernel_ethtool_ringparam *kernel_ering, 823 struct netlink_ext_ack *extack) 824 { 825 struct bnxt *bp = netdev_priv(dev); 826 827 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 828 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 829 (ering->tx_pending < BNXT_MIN_TX_DESC_CNT)) 830 return -EINVAL; 831 832 if (netif_running(dev)) 833 bnxt_close_nic(bp, false, false); 834 835 bp->rx_ring_size = ering->rx_pending; 836 bp->tx_ring_size = ering->tx_pending; 837 bnxt_set_ring_params(bp); 838 839 if (netif_running(dev)) 840 return bnxt_open_nic(bp, false, false); 841 842 return 0; 843 } 844 845 static void bnxt_get_channels(struct net_device *dev, 846 struct ethtool_channels *channel) 847 { 848 struct bnxt *bp = netdev_priv(dev); 849 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 850 int max_rx_rings, max_tx_rings, tcs; 851 int max_tx_sch_inputs, tx_grps; 852 853 /* Get the most up-to-date max_tx_sch_inputs. */ 854 if (netif_running(dev) && BNXT_NEW_RM(bp)) 855 bnxt_hwrm_func_resc_qcaps(bp, false); 856 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 857 858 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 859 if (max_tx_sch_inputs) 860 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 861 862 tcs = netdev_get_num_tc(dev); 863 tx_grps = max(tcs, 1); 864 if (bp->tx_nr_rings_xdp) 865 tx_grps++; 866 max_tx_rings /= tx_grps; 867 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 868 869 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 870 max_rx_rings = 0; 871 max_tx_rings = 0; 872 } 873 if (max_tx_sch_inputs) 874 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 875 876 if (tcs > 1) 877 max_tx_rings /= tcs; 878 879 channel->max_rx = max_rx_rings; 880 channel->max_tx = max_tx_rings; 881 channel->max_other = 0; 882 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 883 channel->combined_count = bp->rx_nr_rings; 884 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 885 channel->combined_count--; 886 } else { 887 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 888 channel->rx_count = bp->rx_nr_rings; 889 channel->tx_count = bp->tx_nr_rings_per_tc; 890 } 891 } 892 } 893 894 static int bnxt_set_channels(struct net_device *dev, 895 struct ethtool_channels *channel) 896 { 897 struct bnxt *bp = netdev_priv(dev); 898 int req_tx_rings, req_rx_rings, tcs; 899 bool sh = false; 900 int tx_xdp = 0; 901 int rc = 0; 902 903 if (channel->other_count) 904 return -EINVAL; 905 906 if (!channel->combined_count && 907 (!channel->rx_count || !channel->tx_count)) 908 return -EINVAL; 909 910 if (channel->combined_count && 911 (channel->rx_count || channel->tx_count)) 912 return -EINVAL; 913 914 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 915 channel->tx_count)) 916 return -EINVAL; 917 918 if (channel->combined_count) 919 sh = true; 920 921 tcs = netdev_get_num_tc(dev); 922 923 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 924 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 925 if (bp->tx_nr_rings_xdp) { 926 if (!sh) { 927 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 928 return -EINVAL; 929 } 930 tx_xdp = req_rx_rings; 931 } 932 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 933 if (rc) { 934 netdev_warn(dev, "Unable to allocate the requested rings\n"); 935 return rc; 936 } 937 938 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) != 939 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) && 940 netif_is_rxfh_configured(dev)) { 941 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n"); 942 return -EINVAL; 943 } 944 945 if (netif_running(dev)) { 946 if (BNXT_PF(bp)) { 947 /* TODO CHIMP_FW: Send message to all VF's 948 * before PF unload 949 */ 950 } 951 rc = bnxt_close_nic(bp, true, false); 952 if (rc) { 953 netdev_err(bp->dev, "Set channel failure rc :%x\n", 954 rc); 955 return rc; 956 } 957 } 958 959 if (sh) { 960 bp->flags |= BNXT_FLAG_SHARED_RINGS; 961 bp->rx_nr_rings = channel->combined_count; 962 bp->tx_nr_rings_per_tc = channel->combined_count; 963 } else { 964 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 965 bp->rx_nr_rings = channel->rx_count; 966 bp->tx_nr_rings_per_tc = channel->tx_count; 967 } 968 bp->tx_nr_rings_xdp = tx_xdp; 969 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 970 if (tcs > 1) 971 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 972 973 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 974 bp->tx_nr_rings + bp->rx_nr_rings; 975 976 /* After changing number of rx channels, update NTUPLE feature. */ 977 netdev_update_features(dev); 978 if (netif_running(dev)) { 979 rc = bnxt_open_nic(bp, true, false); 980 if ((!rc) && BNXT_PF(bp)) { 981 /* TODO CHIMP_FW: Send message to all VF's 982 * to renable 983 */ 984 } 985 } else { 986 rc = bnxt_reserve_rings(bp, true); 987 } 988 989 return rc; 990 } 991 992 #ifdef CONFIG_RFS_ACCEL 993 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 994 u32 *rule_locs) 995 { 996 int i, j = 0; 997 998 cmd->data = bp->ntp_fltr_count; 999 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 1000 struct hlist_head *head; 1001 struct bnxt_ntuple_filter *fltr; 1002 1003 head = &bp->ntp_fltr_hash_tbl[i]; 1004 rcu_read_lock(); 1005 hlist_for_each_entry_rcu(fltr, head, hash) { 1006 if (j == cmd->rule_cnt) 1007 break; 1008 rule_locs[j++] = fltr->sw_id; 1009 } 1010 rcu_read_unlock(); 1011 if (j == cmd->rule_cnt) 1012 break; 1013 } 1014 cmd->rule_cnt = j; 1015 return 0; 1016 } 1017 1018 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1019 { 1020 struct ethtool_rx_flow_spec *fs = 1021 (struct ethtool_rx_flow_spec *)&cmd->fs; 1022 struct bnxt_ntuple_filter *fltr; 1023 struct flow_keys *fkeys; 1024 int i, rc = -EINVAL; 1025 1026 if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR) 1027 return rc; 1028 1029 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 1030 struct hlist_head *head; 1031 1032 head = &bp->ntp_fltr_hash_tbl[i]; 1033 rcu_read_lock(); 1034 hlist_for_each_entry_rcu(fltr, head, hash) { 1035 if (fltr->sw_id == fs->location) 1036 goto fltr_found; 1037 } 1038 rcu_read_unlock(); 1039 } 1040 return rc; 1041 1042 fltr_found: 1043 fkeys = &fltr->fkeys; 1044 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 1045 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1046 fs->flow_type = TCP_V4_FLOW; 1047 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1048 fs->flow_type = UDP_V4_FLOW; 1049 else 1050 goto fltr_err; 1051 1052 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 1053 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0); 1054 1055 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 1056 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0); 1057 1058 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 1059 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0); 1060 1061 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 1062 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0); 1063 } else { 1064 int i; 1065 1066 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1067 fs->flow_type = TCP_V6_FLOW; 1068 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1069 fs->flow_type = UDP_V6_FLOW; 1070 else 1071 goto fltr_err; 1072 1073 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 1074 fkeys->addrs.v6addrs.src; 1075 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 1076 fkeys->addrs.v6addrs.dst; 1077 for (i = 0; i < 4; i++) { 1078 fs->m_u.tcp_ip6_spec.ip6src[i] = cpu_to_be32(~0); 1079 fs->m_u.tcp_ip6_spec.ip6dst[i] = cpu_to_be32(~0); 1080 } 1081 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 1082 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0); 1083 1084 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 1085 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0); 1086 } 1087 1088 fs->ring_cookie = fltr->rxq; 1089 rc = 0; 1090 1091 fltr_err: 1092 rcu_read_unlock(); 1093 1094 return rc; 1095 } 1096 #endif 1097 1098 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1099 { 1100 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1101 return RXH_IP_SRC | RXH_IP_DST; 1102 return 0; 1103 } 1104 1105 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1106 { 1107 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1108 return RXH_IP_SRC | RXH_IP_DST; 1109 return 0; 1110 } 1111 1112 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1113 { 1114 cmd->data = 0; 1115 switch (cmd->flow_type) { 1116 case TCP_V4_FLOW: 1117 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1118 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1119 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1120 cmd->data |= get_ethtool_ipv4_rss(bp); 1121 break; 1122 case UDP_V4_FLOW: 1123 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1124 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1125 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1126 fallthrough; 1127 case SCTP_V4_FLOW: 1128 case AH_ESP_V4_FLOW: 1129 case AH_V4_FLOW: 1130 case ESP_V4_FLOW: 1131 case IPV4_FLOW: 1132 cmd->data |= get_ethtool_ipv4_rss(bp); 1133 break; 1134 1135 case TCP_V6_FLOW: 1136 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1137 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1138 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1139 cmd->data |= get_ethtool_ipv6_rss(bp); 1140 break; 1141 case UDP_V6_FLOW: 1142 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1143 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1144 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1145 fallthrough; 1146 case SCTP_V6_FLOW: 1147 case AH_ESP_V6_FLOW: 1148 case AH_V6_FLOW: 1149 case ESP_V6_FLOW: 1150 case IPV6_FLOW: 1151 cmd->data |= get_ethtool_ipv6_rss(bp); 1152 break; 1153 } 1154 return 0; 1155 } 1156 1157 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1158 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1159 1160 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1161 { 1162 u32 rss_hash_cfg = bp->rss_hash_cfg; 1163 int tuple, rc = 0; 1164 1165 if (cmd->data == RXH_4TUPLE) 1166 tuple = 4; 1167 else if (cmd->data == RXH_2TUPLE) 1168 tuple = 2; 1169 else if (!cmd->data) 1170 tuple = 0; 1171 else 1172 return -EINVAL; 1173 1174 if (cmd->flow_type == TCP_V4_FLOW) { 1175 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1176 if (tuple == 4) 1177 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1178 } else if (cmd->flow_type == UDP_V4_FLOW) { 1179 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1180 return -EINVAL; 1181 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1182 if (tuple == 4) 1183 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1184 } else if (cmd->flow_type == TCP_V6_FLOW) { 1185 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1186 if (tuple == 4) 1187 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1188 } else if (cmd->flow_type == UDP_V6_FLOW) { 1189 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1190 return -EINVAL; 1191 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1192 if (tuple == 4) 1193 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1194 } else if (tuple == 4) { 1195 return -EINVAL; 1196 } 1197 1198 switch (cmd->flow_type) { 1199 case TCP_V4_FLOW: 1200 case UDP_V4_FLOW: 1201 case SCTP_V4_FLOW: 1202 case AH_ESP_V4_FLOW: 1203 case AH_V4_FLOW: 1204 case ESP_V4_FLOW: 1205 case IPV4_FLOW: 1206 if (tuple == 2) 1207 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1208 else if (!tuple) 1209 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1210 break; 1211 1212 case TCP_V6_FLOW: 1213 case UDP_V6_FLOW: 1214 case SCTP_V6_FLOW: 1215 case AH_ESP_V6_FLOW: 1216 case AH_V6_FLOW: 1217 case ESP_V6_FLOW: 1218 case IPV6_FLOW: 1219 if (tuple == 2) 1220 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1221 else if (!tuple) 1222 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1223 break; 1224 } 1225 1226 if (bp->rss_hash_cfg == rss_hash_cfg) 1227 return 0; 1228 1229 bp->rss_hash_cfg = rss_hash_cfg; 1230 if (netif_running(bp->dev)) { 1231 bnxt_close_nic(bp, false, false); 1232 rc = bnxt_open_nic(bp, false, false); 1233 } 1234 return rc; 1235 } 1236 1237 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1238 u32 *rule_locs) 1239 { 1240 struct bnxt *bp = netdev_priv(dev); 1241 int rc = 0; 1242 1243 switch (cmd->cmd) { 1244 #ifdef CONFIG_RFS_ACCEL 1245 case ETHTOOL_GRXRINGS: 1246 cmd->data = bp->rx_nr_rings; 1247 break; 1248 1249 case ETHTOOL_GRXCLSRLCNT: 1250 cmd->rule_cnt = bp->ntp_fltr_count; 1251 cmd->data = BNXT_NTP_FLTR_MAX_FLTR; 1252 break; 1253 1254 case ETHTOOL_GRXCLSRLALL: 1255 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1256 break; 1257 1258 case ETHTOOL_GRXCLSRULE: 1259 rc = bnxt_grxclsrule(bp, cmd); 1260 break; 1261 #endif 1262 1263 case ETHTOOL_GRXFH: 1264 rc = bnxt_grxfh(bp, cmd); 1265 break; 1266 1267 default: 1268 rc = -EOPNOTSUPP; 1269 break; 1270 } 1271 1272 return rc; 1273 } 1274 1275 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1276 { 1277 struct bnxt *bp = netdev_priv(dev); 1278 int rc; 1279 1280 switch (cmd->cmd) { 1281 case ETHTOOL_SRXFH: 1282 rc = bnxt_srxfh(bp, cmd); 1283 break; 1284 1285 default: 1286 rc = -EOPNOTSUPP; 1287 break; 1288 } 1289 return rc; 1290 } 1291 1292 u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1293 { 1294 struct bnxt *bp = netdev_priv(dev); 1295 1296 if (bp->flags & BNXT_FLAG_CHIP_P5) 1297 return ALIGN(bp->rx_nr_rings, BNXT_RSS_TABLE_ENTRIES_P5); 1298 return HW_HASH_INDEX_SIZE; 1299 } 1300 1301 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1302 { 1303 return HW_HASH_KEY_SIZE; 1304 } 1305 1306 static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 1307 u8 *hfunc) 1308 { 1309 struct bnxt *bp = netdev_priv(dev); 1310 struct bnxt_vnic_info *vnic; 1311 u32 i, tbl_size; 1312 1313 if (hfunc) 1314 *hfunc = ETH_RSS_HASH_TOP; 1315 1316 if (!bp->vnic_info) 1317 return 0; 1318 1319 vnic = &bp->vnic_info[0]; 1320 if (indir && bp->rss_indir_tbl) { 1321 tbl_size = bnxt_get_rxfh_indir_size(dev); 1322 for (i = 0; i < tbl_size; i++) 1323 indir[i] = bp->rss_indir_tbl[i]; 1324 } 1325 1326 if (key && vnic->rss_hash_key) 1327 memcpy(key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1328 1329 return 0; 1330 } 1331 1332 static int bnxt_set_rxfh(struct net_device *dev, const u32 *indir, 1333 const u8 *key, const u8 hfunc) 1334 { 1335 struct bnxt *bp = netdev_priv(dev); 1336 int rc = 0; 1337 1338 if (hfunc && hfunc != ETH_RSS_HASH_TOP) 1339 return -EOPNOTSUPP; 1340 1341 if (key) 1342 return -EOPNOTSUPP; 1343 1344 if (indir) { 1345 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(dev); 1346 1347 for (i = 0; i < tbl_size; i++) 1348 bp->rss_indir_tbl[i] = indir[i]; 1349 pad = bp->rss_indir_tbl_entries - tbl_size; 1350 if (pad) 1351 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16)); 1352 } 1353 1354 if (netif_running(bp->dev)) { 1355 bnxt_close_nic(bp, false, false); 1356 rc = bnxt_open_nic(bp, false, false); 1357 } 1358 return rc; 1359 } 1360 1361 static void bnxt_get_drvinfo(struct net_device *dev, 1362 struct ethtool_drvinfo *info) 1363 { 1364 struct bnxt *bp = netdev_priv(dev); 1365 1366 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 1367 strlcpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 1368 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1369 info->n_stats = bnxt_get_num_stats(bp); 1370 info->testinfo_len = bp->num_tests; 1371 /* TODO CHIMP_FW: eeprom dump details */ 1372 info->eedump_len = 0; 1373 /* TODO CHIMP FW: reg dump details */ 1374 info->regdump_len = 0; 1375 } 1376 1377 static int bnxt_get_regs_len(struct net_device *dev) 1378 { 1379 struct bnxt *bp = netdev_priv(dev); 1380 int reg_len; 1381 1382 if (!BNXT_PF(bp)) 1383 return -EOPNOTSUPP; 1384 1385 reg_len = BNXT_PXP_REG_LEN; 1386 1387 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED) 1388 reg_len += sizeof(struct pcie_ctx_hw_stats); 1389 1390 return reg_len; 1391 } 1392 1393 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1394 void *_p) 1395 { 1396 struct pcie_ctx_hw_stats *hw_pcie_stats; 1397 struct hwrm_pcie_qstats_input *req; 1398 struct bnxt *bp = netdev_priv(dev); 1399 dma_addr_t hw_pcie_stats_addr; 1400 int rc; 1401 1402 regs->version = 0; 1403 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p); 1404 1405 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 1406 return; 1407 1408 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS)) 1409 return; 1410 1411 hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats), 1412 &hw_pcie_stats_addr); 1413 if (!hw_pcie_stats) { 1414 hwrm_req_drop(bp, req); 1415 return; 1416 } 1417 1418 regs->version = 1; 1419 hwrm_req_hold(bp, req); /* hold on to slice */ 1420 req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats)); 1421 req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr); 1422 rc = hwrm_req_send(bp, req); 1423 if (!rc) { 1424 __le64 *src = (__le64 *)hw_pcie_stats; 1425 u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN); 1426 int i; 1427 1428 for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++) 1429 dst[i] = le64_to_cpu(src[i]); 1430 } 1431 hwrm_req_drop(bp, req); 1432 } 1433 1434 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1435 { 1436 struct bnxt *bp = netdev_priv(dev); 1437 1438 wol->supported = 0; 1439 wol->wolopts = 0; 1440 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1441 if (bp->flags & BNXT_FLAG_WOL_CAP) { 1442 wol->supported = WAKE_MAGIC; 1443 if (bp->wol) 1444 wol->wolopts = WAKE_MAGIC; 1445 } 1446 } 1447 1448 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1449 { 1450 struct bnxt *bp = netdev_priv(dev); 1451 1452 if (wol->wolopts & ~WAKE_MAGIC) 1453 return -EINVAL; 1454 1455 if (wol->wolopts & WAKE_MAGIC) { 1456 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 1457 return -EINVAL; 1458 if (!bp->wol) { 1459 if (bnxt_hwrm_alloc_wol_fltr(bp)) 1460 return -EBUSY; 1461 bp->wol = 1; 1462 } 1463 } else { 1464 if (bp->wol) { 1465 if (bnxt_hwrm_free_wol_fltr(bp)) 1466 return -EBUSY; 1467 bp->wol = 0; 1468 } 1469 } 1470 return 0; 1471 } 1472 1473 u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause) 1474 { 1475 u32 speed_mask = 0; 1476 1477 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 1478 /* set the advertised speeds */ 1479 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 1480 speed_mask |= ADVERTISED_100baseT_Full; 1481 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 1482 speed_mask |= ADVERTISED_1000baseT_Full; 1483 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 1484 speed_mask |= ADVERTISED_2500baseX_Full; 1485 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 1486 speed_mask |= ADVERTISED_10000baseT_Full; 1487 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 1488 speed_mask |= ADVERTISED_40000baseCR4_Full; 1489 1490 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH) 1491 speed_mask |= ADVERTISED_Pause; 1492 else if (fw_pause & BNXT_LINK_PAUSE_TX) 1493 speed_mask |= ADVERTISED_Asym_Pause; 1494 else if (fw_pause & BNXT_LINK_PAUSE_RX) 1495 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; 1496 1497 return speed_mask; 1498 } 1499 1500 #define BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, name)\ 1501 { \ 1502 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100MB) \ 1503 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1504 100baseT_Full); \ 1505 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_1GB) \ 1506 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1507 1000baseT_Full); \ 1508 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_10GB) \ 1509 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1510 10000baseT_Full); \ 1511 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_25GB) \ 1512 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1513 25000baseCR_Full); \ 1514 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_40GB) \ 1515 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1516 40000baseCR4_Full);\ 1517 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_50GB) \ 1518 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1519 50000baseCR2_Full);\ 1520 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100GB) \ 1521 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1522 100000baseCR4_Full);\ 1523 if ((fw_pause) & BNXT_LINK_PAUSE_RX) { \ 1524 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1525 Pause); \ 1526 if (!((fw_pause) & BNXT_LINK_PAUSE_TX)) \ 1527 ethtool_link_ksettings_add_link_mode( \ 1528 lk_ksettings, name, Asym_Pause);\ 1529 } else if ((fw_pause) & BNXT_LINK_PAUSE_TX) { \ 1530 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1531 Asym_Pause); \ 1532 } \ 1533 } 1534 1535 #define BNXT_ETHTOOL_TO_FW_SPDS(fw_speeds, lk_ksettings, name) \ 1536 { \ 1537 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1538 100baseT_Full) || \ 1539 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1540 100baseT_Half)) \ 1541 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100MB; \ 1542 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1543 1000baseT_Full) || \ 1544 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1545 1000baseT_Half)) \ 1546 (fw_speeds) |= BNXT_LINK_SPEED_MSK_1GB; \ 1547 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1548 10000baseT_Full)) \ 1549 (fw_speeds) |= BNXT_LINK_SPEED_MSK_10GB; \ 1550 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1551 25000baseCR_Full)) \ 1552 (fw_speeds) |= BNXT_LINK_SPEED_MSK_25GB; \ 1553 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1554 40000baseCR4_Full)) \ 1555 (fw_speeds) |= BNXT_LINK_SPEED_MSK_40GB; \ 1556 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1557 50000baseCR2_Full)) \ 1558 (fw_speeds) |= BNXT_LINK_SPEED_MSK_50GB; \ 1559 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1560 100000baseCR4_Full)) \ 1561 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100GB; \ 1562 } 1563 1564 #define BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, name) \ 1565 { \ 1566 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_50GB) \ 1567 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1568 50000baseCR_Full); \ 1569 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_100GB) \ 1570 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1571 100000baseCR2_Full);\ 1572 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_200GB) \ 1573 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1574 200000baseCR4_Full);\ 1575 } 1576 1577 #define BNXT_ETHTOOL_TO_FW_PAM4_SPDS(fw_speeds, lk_ksettings, name) \ 1578 { \ 1579 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1580 50000baseCR_Full)) \ 1581 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_50GB; \ 1582 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1583 100000baseCR2_Full)) \ 1584 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_100GB; \ 1585 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1586 200000baseCR4_Full)) \ 1587 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_200GB; \ 1588 } 1589 1590 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info, 1591 struct ethtool_link_ksettings *lk_ksettings) 1592 { 1593 u16 fec_cfg = link_info->fec_cfg; 1594 1595 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) { 1596 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1597 lk_ksettings->link_modes.advertising); 1598 return; 1599 } 1600 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 1601 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1602 lk_ksettings->link_modes.advertising); 1603 if (fec_cfg & BNXT_FEC_ENC_RS) 1604 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1605 lk_ksettings->link_modes.advertising); 1606 if (fec_cfg & BNXT_FEC_ENC_LLRS) 1607 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1608 lk_ksettings->link_modes.advertising); 1609 } 1610 1611 static void bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info *link_info, 1612 struct ethtool_link_ksettings *lk_ksettings) 1613 { 1614 u16 fw_speeds = link_info->advertising; 1615 u8 fw_pause = 0; 1616 1617 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1618 fw_pause = link_info->auto_pause_setting; 1619 1620 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, advertising); 1621 fw_speeds = link_info->advertising_pam4; 1622 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, advertising); 1623 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings); 1624 } 1625 1626 static void bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info *link_info, 1627 struct ethtool_link_ksettings *lk_ksettings) 1628 { 1629 u16 fw_speeds = link_info->lp_auto_link_speeds; 1630 u8 fw_pause = 0; 1631 1632 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1633 fw_pause = link_info->lp_pause; 1634 1635 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, 1636 lp_advertising); 1637 fw_speeds = link_info->lp_auto_pam4_link_speeds; 1638 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, lp_advertising); 1639 } 1640 1641 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info, 1642 struct ethtool_link_ksettings *lk_ksettings) 1643 { 1644 u16 fec_cfg = link_info->fec_cfg; 1645 1646 if (fec_cfg & BNXT_FEC_NONE) { 1647 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1648 lk_ksettings->link_modes.supported); 1649 return; 1650 } 1651 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP) 1652 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1653 lk_ksettings->link_modes.supported); 1654 if (fec_cfg & BNXT_FEC_ENC_RS_CAP) 1655 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1656 lk_ksettings->link_modes.supported); 1657 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP) 1658 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1659 lk_ksettings->link_modes.supported); 1660 } 1661 1662 static void bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info *link_info, 1663 struct ethtool_link_ksettings *lk_ksettings) 1664 { 1665 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 1666 u16 fw_speeds = link_info->support_speeds; 1667 1668 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, 0, lk_ksettings, supported); 1669 fw_speeds = link_info->support_pam4_speeds; 1670 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, supported); 1671 1672 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) { 1673 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1674 Pause); 1675 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1676 Asym_Pause); 1677 } 1678 1679 if (link_info->support_auto_speeds || 1680 link_info->support_pam4_auto_speeds) 1681 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1682 Autoneg); 1683 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings); 1684 } 1685 1686 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 1687 { 1688 switch (fw_link_speed) { 1689 case BNXT_LINK_SPEED_100MB: 1690 return SPEED_100; 1691 case BNXT_LINK_SPEED_1GB: 1692 return SPEED_1000; 1693 case BNXT_LINK_SPEED_2_5GB: 1694 return SPEED_2500; 1695 case BNXT_LINK_SPEED_10GB: 1696 return SPEED_10000; 1697 case BNXT_LINK_SPEED_20GB: 1698 return SPEED_20000; 1699 case BNXT_LINK_SPEED_25GB: 1700 return SPEED_25000; 1701 case BNXT_LINK_SPEED_40GB: 1702 return SPEED_40000; 1703 case BNXT_LINK_SPEED_50GB: 1704 return SPEED_50000; 1705 case BNXT_LINK_SPEED_100GB: 1706 return SPEED_100000; 1707 default: 1708 return SPEED_UNKNOWN; 1709 } 1710 } 1711 1712 static int bnxt_get_link_ksettings(struct net_device *dev, 1713 struct ethtool_link_ksettings *lk_ksettings) 1714 { 1715 struct bnxt *bp = netdev_priv(dev); 1716 struct bnxt_link_info *link_info = &bp->link_info; 1717 struct ethtool_link_settings *base = &lk_ksettings->base; 1718 u32 ethtool_speed; 1719 1720 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 1721 mutex_lock(&bp->link_lock); 1722 bnxt_fw_to_ethtool_support_spds(link_info, lk_ksettings); 1723 1724 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 1725 if (link_info->autoneg) { 1726 bnxt_fw_to_ethtool_advertised_spds(link_info, lk_ksettings); 1727 ethtool_link_ksettings_add_link_mode(lk_ksettings, 1728 advertising, Autoneg); 1729 base->autoneg = AUTONEG_ENABLE; 1730 base->duplex = DUPLEX_UNKNOWN; 1731 if (link_info->phy_link_status == BNXT_LINK_LINK) { 1732 bnxt_fw_to_ethtool_lp_adv(link_info, lk_ksettings); 1733 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 1734 base->duplex = DUPLEX_FULL; 1735 else 1736 base->duplex = DUPLEX_HALF; 1737 } 1738 ethtool_speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 1739 } else { 1740 base->autoneg = AUTONEG_DISABLE; 1741 ethtool_speed = 1742 bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 1743 base->duplex = DUPLEX_HALF; 1744 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 1745 base->duplex = DUPLEX_FULL; 1746 } 1747 base->speed = ethtool_speed; 1748 1749 base->port = PORT_NONE; 1750 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1751 base->port = PORT_TP; 1752 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1753 TP); 1754 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1755 TP); 1756 } else { 1757 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1758 FIBRE); 1759 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1760 FIBRE); 1761 1762 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC) 1763 base->port = PORT_DA; 1764 else if (link_info->media_type == 1765 PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE) 1766 base->port = PORT_FIBRE; 1767 } 1768 base->phy_address = link_info->phy_addr; 1769 mutex_unlock(&bp->link_lock); 1770 1771 return 0; 1772 } 1773 1774 static int bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed) 1775 { 1776 struct bnxt *bp = netdev_priv(dev); 1777 struct bnxt_link_info *link_info = &bp->link_info; 1778 u16 support_pam4_spds = link_info->support_pam4_speeds; 1779 u16 support_spds = link_info->support_speeds; 1780 u8 sig_mode = BNXT_SIG_MODE_NRZ; 1781 u16 fw_speed = 0; 1782 1783 switch (ethtool_speed) { 1784 case SPEED_100: 1785 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 1786 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB; 1787 break; 1788 case SPEED_1000: 1789 if (support_spds & BNXT_LINK_SPEED_MSK_1GB) 1790 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 1791 break; 1792 case SPEED_2500: 1793 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 1794 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB; 1795 break; 1796 case SPEED_10000: 1797 if (support_spds & BNXT_LINK_SPEED_MSK_10GB) 1798 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 1799 break; 1800 case SPEED_20000: 1801 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) 1802 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB; 1803 break; 1804 case SPEED_25000: 1805 if (support_spds & BNXT_LINK_SPEED_MSK_25GB) 1806 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 1807 break; 1808 case SPEED_40000: 1809 if (support_spds & BNXT_LINK_SPEED_MSK_40GB) 1810 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 1811 break; 1812 case SPEED_50000: 1813 if (support_spds & BNXT_LINK_SPEED_MSK_50GB) { 1814 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 1815 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) { 1816 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB; 1817 sig_mode = BNXT_SIG_MODE_PAM4; 1818 } 1819 break; 1820 case SPEED_100000: 1821 if (support_spds & BNXT_LINK_SPEED_MSK_100GB) { 1822 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB; 1823 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) { 1824 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB; 1825 sig_mode = BNXT_SIG_MODE_PAM4; 1826 } 1827 break; 1828 case SPEED_200000: 1829 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) { 1830 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB; 1831 sig_mode = BNXT_SIG_MODE_PAM4; 1832 } 1833 break; 1834 } 1835 1836 if (!fw_speed) { 1837 netdev_err(dev, "unsupported speed!\n"); 1838 return -EINVAL; 1839 } 1840 1841 if (link_info->req_link_speed == fw_speed && 1842 link_info->req_signal_mode == sig_mode && 1843 link_info->autoneg == 0) 1844 return -EALREADY; 1845 1846 link_info->req_link_speed = fw_speed; 1847 link_info->req_signal_mode = sig_mode; 1848 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 1849 link_info->autoneg = 0; 1850 link_info->advertising = 0; 1851 link_info->advertising_pam4 = 0; 1852 1853 return 0; 1854 } 1855 1856 u16 bnxt_get_fw_auto_link_speeds(u32 advertising) 1857 { 1858 u16 fw_speed_mask = 0; 1859 1860 /* only support autoneg at speed 100, 1000, and 10000 */ 1861 if (advertising & (ADVERTISED_100baseT_Full | 1862 ADVERTISED_100baseT_Half)) { 1863 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 1864 } 1865 if (advertising & (ADVERTISED_1000baseT_Full | 1866 ADVERTISED_1000baseT_Half)) { 1867 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 1868 } 1869 if (advertising & ADVERTISED_10000baseT_Full) 1870 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 1871 1872 if (advertising & ADVERTISED_40000baseCR4_Full) 1873 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 1874 1875 return fw_speed_mask; 1876 } 1877 1878 static int bnxt_set_link_ksettings(struct net_device *dev, 1879 const struct ethtool_link_ksettings *lk_ksettings) 1880 { 1881 struct bnxt *bp = netdev_priv(dev); 1882 struct bnxt_link_info *link_info = &bp->link_info; 1883 const struct ethtool_link_settings *base = &lk_ksettings->base; 1884 bool set_pause = false; 1885 u32 speed; 1886 int rc = 0; 1887 1888 if (!BNXT_PHY_CFG_ABLE(bp)) 1889 return -EOPNOTSUPP; 1890 1891 mutex_lock(&bp->link_lock); 1892 if (base->autoneg == AUTONEG_ENABLE) { 1893 link_info->advertising = 0; 1894 link_info->advertising_pam4 = 0; 1895 BNXT_ETHTOOL_TO_FW_SPDS(link_info->advertising, lk_ksettings, 1896 advertising); 1897 BNXT_ETHTOOL_TO_FW_PAM4_SPDS(link_info->advertising_pam4, 1898 lk_ksettings, advertising); 1899 link_info->autoneg |= BNXT_AUTONEG_SPEED; 1900 if (!link_info->advertising && !link_info->advertising_pam4) { 1901 link_info->advertising = link_info->support_auto_speeds; 1902 link_info->advertising_pam4 = 1903 link_info->support_pam4_auto_speeds; 1904 } 1905 /* any change to autoneg will cause link change, therefore the 1906 * driver should put back the original pause setting in autoneg 1907 */ 1908 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 1909 set_pause = true; 1910 } else { 1911 u8 phy_type = link_info->phy_type; 1912 1913 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 1914 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 1915 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1916 netdev_err(dev, "10GBase-T devices must autoneg\n"); 1917 rc = -EINVAL; 1918 goto set_setting_exit; 1919 } 1920 if (base->duplex == DUPLEX_HALF) { 1921 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 1922 rc = -EINVAL; 1923 goto set_setting_exit; 1924 } 1925 speed = base->speed; 1926 rc = bnxt_force_link_speed(dev, speed); 1927 if (rc) { 1928 if (rc == -EALREADY) 1929 rc = 0; 1930 goto set_setting_exit; 1931 } 1932 } 1933 1934 if (netif_running(dev)) 1935 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 1936 1937 set_setting_exit: 1938 mutex_unlock(&bp->link_lock); 1939 return rc; 1940 } 1941 1942 static int bnxt_get_fecparam(struct net_device *dev, 1943 struct ethtool_fecparam *fec) 1944 { 1945 struct bnxt *bp = netdev_priv(dev); 1946 struct bnxt_link_info *link_info; 1947 u8 active_fec; 1948 u16 fec_cfg; 1949 1950 link_info = &bp->link_info; 1951 fec_cfg = link_info->fec_cfg; 1952 active_fec = link_info->active_fec_sig_mode & 1953 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK; 1954 if (fec_cfg & BNXT_FEC_NONE) { 1955 fec->fec = ETHTOOL_FEC_NONE; 1956 fec->active_fec = ETHTOOL_FEC_NONE; 1957 return 0; 1958 } 1959 if (fec_cfg & BNXT_FEC_AUTONEG) 1960 fec->fec |= ETHTOOL_FEC_AUTO; 1961 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 1962 fec->fec |= ETHTOOL_FEC_BASER; 1963 if (fec_cfg & BNXT_FEC_ENC_RS) 1964 fec->fec |= ETHTOOL_FEC_RS; 1965 if (fec_cfg & BNXT_FEC_ENC_LLRS) 1966 fec->fec |= ETHTOOL_FEC_LLRS; 1967 1968 switch (active_fec) { 1969 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE: 1970 fec->active_fec |= ETHTOOL_FEC_BASER; 1971 break; 1972 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE: 1973 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE: 1974 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE: 1975 fec->active_fec |= ETHTOOL_FEC_RS; 1976 break; 1977 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE: 1978 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE: 1979 fec->active_fec |= ETHTOOL_FEC_LLRS; 1980 break; 1981 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE: 1982 fec->active_fec |= ETHTOOL_FEC_OFF; 1983 break; 1984 } 1985 return 0; 1986 } 1987 1988 static void bnxt_get_fec_stats(struct net_device *dev, 1989 struct ethtool_fec_stats *fec_stats) 1990 { 1991 struct bnxt *bp = netdev_priv(dev); 1992 u64 *rx; 1993 1994 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 1995 return; 1996 1997 rx = bp->rx_port_stats_ext.sw_stats; 1998 fec_stats->corrected_bits.total = 1999 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits)); 2000 } 2001 2002 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info, 2003 u32 fec) 2004 { 2005 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE; 2006 2007 if (fec & ETHTOOL_FEC_BASER) 2008 fw_fec |= BNXT_FEC_BASE_R_ON(link_info); 2009 else if (fec & ETHTOOL_FEC_RS) 2010 fw_fec |= BNXT_FEC_RS_ON(link_info); 2011 else if (fec & ETHTOOL_FEC_LLRS) 2012 fw_fec |= BNXT_FEC_LLRS_ON; 2013 return fw_fec; 2014 } 2015 2016 static int bnxt_set_fecparam(struct net_device *dev, 2017 struct ethtool_fecparam *fecparam) 2018 { 2019 struct hwrm_port_phy_cfg_input *req; 2020 struct bnxt *bp = netdev_priv(dev); 2021 struct bnxt_link_info *link_info; 2022 u32 new_cfg, fec = fecparam->fec; 2023 u16 fec_cfg; 2024 int rc; 2025 2026 link_info = &bp->link_info; 2027 fec_cfg = link_info->fec_cfg; 2028 if (fec_cfg & BNXT_FEC_NONE) 2029 return -EOPNOTSUPP; 2030 2031 if (fec & ETHTOOL_FEC_OFF) { 2032 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE | 2033 BNXT_FEC_ALL_OFF(link_info); 2034 goto apply_fec; 2035 } 2036 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) || 2037 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) || 2038 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) || 2039 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP))) 2040 return -EINVAL; 2041 2042 if (fec & ETHTOOL_FEC_AUTO) { 2043 if (!link_info->autoneg) 2044 return -EINVAL; 2045 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE; 2046 } else { 2047 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec); 2048 } 2049 2050 apply_fec: 2051 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 2052 if (rc) 2053 return rc; 2054 req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 2055 rc = hwrm_req_send(bp, req); 2056 /* update current settings */ 2057 if (!rc) { 2058 mutex_lock(&bp->link_lock); 2059 bnxt_update_link(bp, false); 2060 mutex_unlock(&bp->link_lock); 2061 } 2062 return rc; 2063 } 2064 2065 static void bnxt_get_pauseparam(struct net_device *dev, 2066 struct ethtool_pauseparam *epause) 2067 { 2068 struct bnxt *bp = netdev_priv(dev); 2069 struct bnxt_link_info *link_info = &bp->link_info; 2070 2071 if (BNXT_VF(bp)) 2072 return; 2073 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 2074 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 2075 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 2076 } 2077 2078 static void bnxt_get_pause_stats(struct net_device *dev, 2079 struct ethtool_pause_stats *epstat) 2080 { 2081 struct bnxt *bp = netdev_priv(dev); 2082 u64 *rx, *tx; 2083 2084 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 2085 return; 2086 2087 rx = bp->port_stats.sw_stats; 2088 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 2089 2090 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames); 2091 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames); 2092 } 2093 2094 static int bnxt_set_pauseparam(struct net_device *dev, 2095 struct ethtool_pauseparam *epause) 2096 { 2097 int rc = 0; 2098 struct bnxt *bp = netdev_priv(dev); 2099 struct bnxt_link_info *link_info = &bp->link_info; 2100 2101 if (!BNXT_PHY_CFG_ABLE(bp) || (bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 2102 return -EOPNOTSUPP; 2103 2104 mutex_lock(&bp->link_lock); 2105 if (epause->autoneg) { 2106 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 2107 rc = -EINVAL; 2108 goto pause_exit; 2109 } 2110 2111 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 2112 link_info->req_flow_ctrl = 0; 2113 } else { 2114 /* when transition from auto pause to force pause, 2115 * force a link change 2116 */ 2117 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 2118 link_info->force_link_chng = true; 2119 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 2120 link_info->req_flow_ctrl = 0; 2121 } 2122 if (epause->rx_pause) 2123 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 2124 2125 if (epause->tx_pause) 2126 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 2127 2128 if (netif_running(dev)) 2129 rc = bnxt_hwrm_set_pause(bp); 2130 2131 pause_exit: 2132 mutex_unlock(&bp->link_lock); 2133 return rc; 2134 } 2135 2136 static u32 bnxt_get_link(struct net_device *dev) 2137 { 2138 struct bnxt *bp = netdev_priv(dev); 2139 2140 /* TODO: handle MF, VF, driver close case */ 2141 return BNXT_LINK_IS_UP(bp); 2142 } 2143 2144 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp, 2145 struct hwrm_nvm_get_dev_info_output *nvm_dev_info) 2146 { 2147 struct hwrm_nvm_get_dev_info_output *resp; 2148 struct hwrm_nvm_get_dev_info_input *req; 2149 int rc; 2150 2151 if (BNXT_VF(bp)) 2152 return -EOPNOTSUPP; 2153 2154 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO); 2155 if (rc) 2156 return rc; 2157 2158 resp = hwrm_req_hold(bp, req); 2159 rc = hwrm_req_send(bp, req); 2160 if (!rc) 2161 memcpy(nvm_dev_info, resp, sizeof(*resp)); 2162 hwrm_req_drop(bp, req); 2163 return rc; 2164 } 2165 2166 static void bnxt_print_admin_err(struct bnxt *bp) 2167 { 2168 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 2169 } 2170 2171 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 2172 u16 ext, u16 *index, u32 *item_length, 2173 u32 *data_length); 2174 2175 static int bnxt_flash_nvram(struct net_device *dev, u16 dir_type, 2176 u16 dir_ordinal, u16 dir_ext, u16 dir_attr, 2177 u32 dir_item_len, const u8 *data, 2178 size_t data_len) 2179 { 2180 struct bnxt *bp = netdev_priv(dev); 2181 struct hwrm_nvm_write_input *req; 2182 int rc; 2183 2184 rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE); 2185 if (rc) 2186 return rc; 2187 2188 if (data_len && data) { 2189 dma_addr_t dma_handle; 2190 u8 *kmem; 2191 2192 kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle); 2193 if (!kmem) { 2194 hwrm_req_drop(bp, req); 2195 return -ENOMEM; 2196 } 2197 2198 req->dir_data_length = cpu_to_le32(data_len); 2199 2200 memcpy(kmem, data, data_len); 2201 req->host_src_addr = cpu_to_le64(dma_handle); 2202 } 2203 2204 hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout); 2205 req->dir_type = cpu_to_le16(dir_type); 2206 req->dir_ordinal = cpu_to_le16(dir_ordinal); 2207 req->dir_ext = cpu_to_le16(dir_ext); 2208 req->dir_attr = cpu_to_le16(dir_attr); 2209 req->dir_item_length = cpu_to_le32(dir_item_len); 2210 rc = hwrm_req_send(bp, req); 2211 2212 if (rc == -EACCES) 2213 bnxt_print_admin_err(bp); 2214 return rc; 2215 } 2216 2217 int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type, 2218 u8 self_reset, u8 flags) 2219 { 2220 struct bnxt *bp = netdev_priv(dev); 2221 struct hwrm_fw_reset_input *req; 2222 int rc; 2223 2224 if (!bnxt_hwrm_reset_permitted(bp)) { 2225 netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver"); 2226 return -EPERM; 2227 } 2228 2229 rc = hwrm_req_init(bp, req, HWRM_FW_RESET); 2230 if (rc) 2231 return rc; 2232 2233 req->embedded_proc_type = proc_type; 2234 req->selfrst_status = self_reset; 2235 req->flags = flags; 2236 2237 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) { 2238 rc = hwrm_req_send_silent(bp, req); 2239 } else { 2240 rc = hwrm_req_send(bp, req); 2241 if (rc == -EACCES) 2242 bnxt_print_admin_err(bp); 2243 } 2244 return rc; 2245 } 2246 2247 static int bnxt_firmware_reset(struct net_device *dev, 2248 enum bnxt_nvm_directory_type dir_type) 2249 { 2250 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE; 2251 u8 proc_type, flags = 0; 2252 2253 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 2254 /* (e.g. when firmware isn't already running) */ 2255 switch (dir_type) { 2256 case BNX_DIR_TYPE_CHIMP_PATCH: 2257 case BNX_DIR_TYPE_BOOTCODE: 2258 case BNX_DIR_TYPE_BOOTCODE_2: 2259 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 2260 /* Self-reset ChiMP upon next PCIe reset: */ 2261 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 2262 break; 2263 case BNX_DIR_TYPE_APE_FW: 2264 case BNX_DIR_TYPE_APE_PATCH: 2265 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 2266 /* Self-reset APE upon next PCIe reset: */ 2267 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 2268 break; 2269 case BNX_DIR_TYPE_KONG_FW: 2270 case BNX_DIR_TYPE_KONG_PATCH: 2271 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 2272 break; 2273 case BNX_DIR_TYPE_BONO_FW: 2274 case BNX_DIR_TYPE_BONO_PATCH: 2275 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 2276 break; 2277 default: 2278 return -EINVAL; 2279 } 2280 2281 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags); 2282 } 2283 2284 static int bnxt_firmware_reset_chip(struct net_device *dev) 2285 { 2286 struct bnxt *bp = netdev_priv(dev); 2287 u8 flags = 0; 2288 2289 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 2290 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 2291 2292 return bnxt_hwrm_firmware_reset(dev, 2293 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP, 2294 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP, 2295 flags); 2296 } 2297 2298 static int bnxt_firmware_reset_ap(struct net_device *dev) 2299 { 2300 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP, 2301 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE, 2302 0); 2303 } 2304 2305 static int bnxt_flash_firmware(struct net_device *dev, 2306 u16 dir_type, 2307 const u8 *fw_data, 2308 size_t fw_size) 2309 { 2310 int rc = 0; 2311 u16 code_type; 2312 u32 stored_crc; 2313 u32 calculated_crc; 2314 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 2315 2316 switch (dir_type) { 2317 case BNX_DIR_TYPE_BOOTCODE: 2318 case BNX_DIR_TYPE_BOOTCODE_2: 2319 code_type = CODE_BOOT; 2320 break; 2321 case BNX_DIR_TYPE_CHIMP_PATCH: 2322 code_type = CODE_CHIMP_PATCH; 2323 break; 2324 case BNX_DIR_TYPE_APE_FW: 2325 code_type = CODE_MCTP_PASSTHRU; 2326 break; 2327 case BNX_DIR_TYPE_APE_PATCH: 2328 code_type = CODE_APE_PATCH; 2329 break; 2330 case BNX_DIR_TYPE_KONG_FW: 2331 code_type = CODE_KONG_FW; 2332 break; 2333 case BNX_DIR_TYPE_KONG_PATCH: 2334 code_type = CODE_KONG_PATCH; 2335 break; 2336 case BNX_DIR_TYPE_BONO_FW: 2337 code_type = CODE_BONO_FW; 2338 break; 2339 case BNX_DIR_TYPE_BONO_PATCH: 2340 code_type = CODE_BONO_PATCH; 2341 break; 2342 default: 2343 netdev_err(dev, "Unsupported directory entry type: %u\n", 2344 dir_type); 2345 return -EINVAL; 2346 } 2347 if (fw_size < sizeof(struct bnxt_fw_header)) { 2348 netdev_err(dev, "Invalid firmware file size: %u\n", 2349 (unsigned int)fw_size); 2350 return -EINVAL; 2351 } 2352 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 2353 netdev_err(dev, "Invalid firmware signature: %08X\n", 2354 le32_to_cpu(header->signature)); 2355 return -EINVAL; 2356 } 2357 if (header->code_type != code_type) { 2358 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 2359 code_type, header->code_type); 2360 return -EINVAL; 2361 } 2362 if (header->device != DEVICE_CUMULUS_FAMILY) { 2363 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 2364 DEVICE_CUMULUS_FAMILY, header->device); 2365 return -EINVAL; 2366 } 2367 /* Confirm the CRC32 checksum of the file: */ 2368 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 2369 sizeof(stored_crc))); 2370 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 2371 if (calculated_crc != stored_crc) { 2372 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 2373 (unsigned long)stored_crc, 2374 (unsigned long)calculated_crc); 2375 return -EINVAL; 2376 } 2377 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2378 0, 0, 0, fw_data, fw_size); 2379 if (rc == 0) /* Firmware update successful */ 2380 rc = bnxt_firmware_reset(dev, dir_type); 2381 2382 return rc; 2383 } 2384 2385 static int bnxt_flash_microcode(struct net_device *dev, 2386 u16 dir_type, 2387 const u8 *fw_data, 2388 size_t fw_size) 2389 { 2390 struct bnxt_ucode_trailer *trailer; 2391 u32 calculated_crc; 2392 u32 stored_crc; 2393 int rc = 0; 2394 2395 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 2396 netdev_err(dev, "Invalid microcode file size: %u\n", 2397 (unsigned int)fw_size); 2398 return -EINVAL; 2399 } 2400 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 2401 sizeof(*trailer))); 2402 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 2403 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 2404 le32_to_cpu(trailer->sig)); 2405 return -EINVAL; 2406 } 2407 if (le16_to_cpu(trailer->dir_type) != dir_type) { 2408 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 2409 dir_type, le16_to_cpu(trailer->dir_type)); 2410 return -EINVAL; 2411 } 2412 if (le16_to_cpu(trailer->trailer_length) < 2413 sizeof(struct bnxt_ucode_trailer)) { 2414 netdev_err(dev, "Invalid microcode trailer length: %d\n", 2415 le16_to_cpu(trailer->trailer_length)); 2416 return -EINVAL; 2417 } 2418 2419 /* Confirm the CRC32 checksum of the file: */ 2420 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 2421 sizeof(stored_crc))); 2422 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 2423 if (calculated_crc != stored_crc) { 2424 netdev_err(dev, 2425 "CRC32 (%08lX) does not match calculated: %08lX\n", 2426 (unsigned long)stored_crc, 2427 (unsigned long)calculated_crc); 2428 return -EINVAL; 2429 } 2430 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2431 0, 0, 0, fw_data, fw_size); 2432 2433 return rc; 2434 } 2435 2436 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 2437 { 2438 switch (dir_type) { 2439 case BNX_DIR_TYPE_CHIMP_PATCH: 2440 case BNX_DIR_TYPE_BOOTCODE: 2441 case BNX_DIR_TYPE_BOOTCODE_2: 2442 case BNX_DIR_TYPE_APE_FW: 2443 case BNX_DIR_TYPE_APE_PATCH: 2444 case BNX_DIR_TYPE_KONG_FW: 2445 case BNX_DIR_TYPE_KONG_PATCH: 2446 case BNX_DIR_TYPE_BONO_FW: 2447 case BNX_DIR_TYPE_BONO_PATCH: 2448 return true; 2449 } 2450 2451 return false; 2452 } 2453 2454 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 2455 { 2456 switch (dir_type) { 2457 case BNX_DIR_TYPE_AVS: 2458 case BNX_DIR_TYPE_EXP_ROM_MBA: 2459 case BNX_DIR_TYPE_PCIE: 2460 case BNX_DIR_TYPE_TSCF_UCODE: 2461 case BNX_DIR_TYPE_EXT_PHY: 2462 case BNX_DIR_TYPE_CCM: 2463 case BNX_DIR_TYPE_ISCSI_BOOT: 2464 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 2465 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 2466 return true; 2467 } 2468 2469 return false; 2470 } 2471 2472 static bool bnxt_dir_type_is_executable(u16 dir_type) 2473 { 2474 return bnxt_dir_type_is_ape_bin_format(dir_type) || 2475 bnxt_dir_type_is_other_exec_format(dir_type); 2476 } 2477 2478 static int bnxt_flash_firmware_from_file(struct net_device *dev, 2479 u16 dir_type, 2480 const char *filename) 2481 { 2482 const struct firmware *fw; 2483 int rc; 2484 2485 rc = request_firmware(&fw, filename, &dev->dev); 2486 if (rc != 0) { 2487 netdev_err(dev, "Error %d requesting firmware file: %s\n", 2488 rc, filename); 2489 return rc; 2490 } 2491 if (bnxt_dir_type_is_ape_bin_format(dir_type)) 2492 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 2493 else if (bnxt_dir_type_is_other_exec_format(dir_type)) 2494 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 2495 else 2496 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2497 0, 0, 0, fw->data, fw->size); 2498 release_firmware(fw); 2499 return rc; 2500 } 2501 2502 #define BNXT_PKG_DMA_SIZE 0x40000 2503 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE)) 2504 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST)) 2505 2506 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw, 2507 u32 install_type) 2508 { 2509 struct hwrm_nvm_install_update_input *install; 2510 struct hwrm_nvm_install_update_output *resp; 2511 struct hwrm_nvm_modify_input *modify; 2512 struct bnxt *bp = netdev_priv(dev); 2513 bool defrag_attempted = false; 2514 dma_addr_t dma_handle; 2515 u8 *kmem = NULL; 2516 u32 modify_len; 2517 u32 item_len; 2518 u8 cmd_err; 2519 u16 index; 2520 int rc; 2521 2522 bnxt_hwrm_fw_set_time(bp); 2523 2524 rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY); 2525 if (rc) 2526 return rc; 2527 2528 /* Try allocating a large DMA buffer first. Older fw will 2529 * cause excessive NVRAM erases when using small blocks. 2530 */ 2531 modify_len = roundup_pow_of_two(fw->size); 2532 modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE); 2533 while (1) { 2534 kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle); 2535 if (!kmem && modify_len > PAGE_SIZE) 2536 modify_len /= 2; 2537 else 2538 break; 2539 } 2540 if (!kmem) { 2541 hwrm_req_drop(bp, modify); 2542 return -ENOMEM; 2543 } 2544 2545 rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE); 2546 if (rc) { 2547 hwrm_req_drop(bp, modify); 2548 return rc; 2549 } 2550 2551 hwrm_req_timeout(bp, modify, bp->hwrm_cmd_max_timeout); 2552 hwrm_req_timeout(bp, install, bp->hwrm_cmd_max_timeout); 2553 2554 hwrm_req_hold(bp, modify); 2555 modify->host_src_addr = cpu_to_le64(dma_handle); 2556 2557 resp = hwrm_req_hold(bp, install); 2558 if ((install_type & 0xffff) == 0) 2559 install_type >>= 16; 2560 install->install_type = cpu_to_le32(install_type); 2561 2562 do { 2563 u32 copied = 0, len = modify_len; 2564 2565 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 2566 BNX_DIR_ORDINAL_FIRST, 2567 BNX_DIR_EXT_NONE, 2568 &index, &item_len, NULL); 2569 if (rc) { 2570 netdev_err(dev, "PKG update area not created in nvram\n"); 2571 break; 2572 } 2573 if (fw->size > item_len) { 2574 netdev_err(dev, "PKG insufficient update area in nvram: %lu\n", 2575 (unsigned long)fw->size); 2576 rc = -EFBIG; 2577 break; 2578 } 2579 2580 modify->dir_idx = cpu_to_le16(index); 2581 2582 if (fw->size > modify_len) 2583 modify->flags = BNXT_NVM_MORE_FLAG; 2584 while (copied < fw->size) { 2585 u32 balance = fw->size - copied; 2586 2587 if (balance <= modify_len) { 2588 len = balance; 2589 if (copied) 2590 modify->flags |= BNXT_NVM_LAST_FLAG; 2591 } 2592 memcpy(kmem, fw->data + copied, len); 2593 modify->len = cpu_to_le32(len); 2594 modify->offset = cpu_to_le32(copied); 2595 rc = hwrm_req_send(bp, modify); 2596 if (rc) 2597 goto pkg_abort; 2598 copied += len; 2599 } 2600 2601 rc = hwrm_req_send_silent(bp, install); 2602 if (!rc) 2603 break; 2604 2605 if (defrag_attempted) { 2606 /* We have tried to defragment already in the previous 2607 * iteration. Return with the result for INSTALL_UPDATE 2608 */ 2609 break; 2610 } 2611 2612 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 2613 2614 switch (cmd_err) { 2615 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK: 2616 netdev_err(dev, "HWRM_NVM_INSTALL_UPDATE failure Anti-rollback detected\n"); 2617 rc = -EALREADY; 2618 break; 2619 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR: 2620 install->flags = 2621 cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 2622 2623 rc = hwrm_req_send_silent(bp, install); 2624 if (!rc) 2625 break; 2626 2627 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 2628 2629 if (cmd_err == NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) { 2630 /* FW has cleared NVM area, driver will create 2631 * UPDATE directory and try the flash again 2632 */ 2633 defrag_attempted = true; 2634 install->flags = 0; 2635 rc = bnxt_flash_nvram(bp->dev, 2636 BNX_DIR_TYPE_UPDATE, 2637 BNX_DIR_ORDINAL_FIRST, 2638 0, 0, item_len, NULL, 0); 2639 if (!rc) 2640 break; 2641 } 2642 fallthrough; 2643 default: 2644 netdev_err(dev, "HWRM_NVM_INSTALL_UPDATE failure rc :%x cmd_err :%x\n", 2645 rc, cmd_err); 2646 } 2647 } while (defrag_attempted && !rc); 2648 2649 pkg_abort: 2650 hwrm_req_drop(bp, modify); 2651 hwrm_req_drop(bp, install); 2652 2653 if (resp->result) { 2654 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 2655 (s8)resp->result, (int)resp->problem_item); 2656 rc = -ENOPKG; 2657 } 2658 if (rc == -EACCES) 2659 bnxt_print_admin_err(bp); 2660 return rc; 2661 } 2662 2663 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename, 2664 u32 install_type) 2665 { 2666 const struct firmware *fw; 2667 int rc; 2668 2669 rc = request_firmware(&fw, filename, &dev->dev); 2670 if (rc != 0) { 2671 netdev_err(dev, "PKG error %d requesting file: %s\n", 2672 rc, filename); 2673 return rc; 2674 } 2675 2676 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type); 2677 2678 release_firmware(fw); 2679 2680 return rc; 2681 } 2682 2683 static int bnxt_flash_device(struct net_device *dev, 2684 struct ethtool_flash *flash) 2685 { 2686 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 2687 netdev_err(dev, "flashdev not supported from a virtual function\n"); 2688 return -EINVAL; 2689 } 2690 2691 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 2692 flash->region > 0xffff) 2693 return bnxt_flash_package_from_file(dev, flash->data, 2694 flash->region); 2695 2696 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 2697 } 2698 2699 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 2700 { 2701 struct hwrm_nvm_get_dir_info_output *output; 2702 struct hwrm_nvm_get_dir_info_input *req; 2703 struct bnxt *bp = netdev_priv(dev); 2704 int rc; 2705 2706 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO); 2707 if (rc) 2708 return rc; 2709 2710 output = hwrm_req_hold(bp, req); 2711 rc = hwrm_req_send(bp, req); 2712 if (!rc) { 2713 *entries = le32_to_cpu(output->entries); 2714 *length = le32_to_cpu(output->entry_length); 2715 } 2716 hwrm_req_drop(bp, req); 2717 return rc; 2718 } 2719 2720 static int bnxt_get_eeprom_len(struct net_device *dev) 2721 { 2722 struct bnxt *bp = netdev_priv(dev); 2723 2724 if (BNXT_VF(bp)) 2725 return 0; 2726 2727 /* The -1 return value allows the entire 32-bit range of offsets to be 2728 * passed via the ethtool command-line utility. 2729 */ 2730 return -1; 2731 } 2732 2733 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 2734 { 2735 struct bnxt *bp = netdev_priv(dev); 2736 int rc; 2737 u32 dir_entries; 2738 u32 entry_length; 2739 u8 *buf; 2740 size_t buflen; 2741 dma_addr_t dma_handle; 2742 struct hwrm_nvm_get_dir_entries_input *req; 2743 2744 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 2745 if (rc != 0) 2746 return rc; 2747 2748 if (!dir_entries || !entry_length) 2749 return -EIO; 2750 2751 /* Insert 2 bytes of directory info (count and size of entries) */ 2752 if (len < 2) 2753 return -EINVAL; 2754 2755 *data++ = dir_entries; 2756 *data++ = entry_length; 2757 len -= 2; 2758 memset(data, 0xff, len); 2759 2760 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES); 2761 if (rc) 2762 return rc; 2763 2764 buflen = dir_entries * entry_length; 2765 buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle); 2766 if (!buf) { 2767 hwrm_req_drop(bp, req); 2768 return -ENOMEM; 2769 } 2770 req->host_dest_addr = cpu_to_le64(dma_handle); 2771 2772 hwrm_req_hold(bp, req); /* hold the slice */ 2773 rc = hwrm_req_send(bp, req); 2774 if (rc == 0) 2775 memcpy(data, buf, len > buflen ? buflen : len); 2776 hwrm_req_drop(bp, req); 2777 return rc; 2778 } 2779 2780 static int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 2781 u32 length, u8 *data) 2782 { 2783 struct bnxt *bp = netdev_priv(dev); 2784 int rc; 2785 u8 *buf; 2786 dma_addr_t dma_handle; 2787 struct hwrm_nvm_read_input *req; 2788 2789 if (!length) 2790 return -EINVAL; 2791 2792 rc = hwrm_req_init(bp, req, HWRM_NVM_READ); 2793 if (rc) 2794 return rc; 2795 2796 buf = hwrm_req_dma_slice(bp, req, length, &dma_handle); 2797 if (!buf) { 2798 hwrm_req_drop(bp, req); 2799 return -ENOMEM; 2800 } 2801 2802 req->host_dest_addr = cpu_to_le64(dma_handle); 2803 req->dir_idx = cpu_to_le16(index); 2804 req->offset = cpu_to_le32(offset); 2805 req->len = cpu_to_le32(length); 2806 2807 hwrm_req_hold(bp, req); /* hold the slice */ 2808 rc = hwrm_req_send(bp, req); 2809 if (rc == 0) 2810 memcpy(data, buf, length); 2811 hwrm_req_drop(bp, req); 2812 return rc; 2813 } 2814 2815 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 2816 u16 ext, u16 *index, u32 *item_length, 2817 u32 *data_length) 2818 { 2819 struct hwrm_nvm_find_dir_entry_output *output; 2820 struct hwrm_nvm_find_dir_entry_input *req; 2821 struct bnxt *bp = netdev_priv(dev); 2822 int rc; 2823 2824 rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY); 2825 if (rc) 2826 return rc; 2827 2828 req->enables = 0; 2829 req->dir_idx = 0; 2830 req->dir_type = cpu_to_le16(type); 2831 req->dir_ordinal = cpu_to_le16(ordinal); 2832 req->dir_ext = cpu_to_le16(ext); 2833 req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 2834 output = hwrm_req_hold(bp, req); 2835 rc = hwrm_req_send_silent(bp, req); 2836 if (rc == 0) { 2837 if (index) 2838 *index = le16_to_cpu(output->dir_idx); 2839 if (item_length) 2840 *item_length = le32_to_cpu(output->dir_item_length); 2841 if (data_length) 2842 *data_length = le32_to_cpu(output->dir_data_length); 2843 } 2844 hwrm_req_drop(bp, req); 2845 return rc; 2846 } 2847 2848 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 2849 { 2850 char *retval = NULL; 2851 char *p; 2852 char *value; 2853 int field = 0; 2854 2855 if (datalen < 1) 2856 return NULL; 2857 /* null-terminate the log data (removing last '\n'): */ 2858 data[datalen - 1] = 0; 2859 for (p = data; *p != 0; p++) { 2860 field = 0; 2861 retval = NULL; 2862 while (*p != 0 && *p != '\n') { 2863 value = p; 2864 while (*p != 0 && *p != '\t' && *p != '\n') 2865 p++; 2866 if (field == desired_field) 2867 retval = value; 2868 if (*p != '\t') 2869 break; 2870 *p = 0; 2871 field++; 2872 p++; 2873 } 2874 if (*p == 0) 2875 break; 2876 *p = 0; 2877 } 2878 return retval; 2879 } 2880 2881 int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size) 2882 { 2883 struct bnxt *bp = netdev_priv(dev); 2884 u16 index = 0; 2885 char *pkgver; 2886 u32 pkglen; 2887 u8 *pkgbuf; 2888 int rc; 2889 2890 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 2891 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 2892 &index, NULL, &pkglen); 2893 if (rc) 2894 return rc; 2895 2896 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 2897 if (!pkgbuf) { 2898 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 2899 pkglen); 2900 return -ENOMEM; 2901 } 2902 2903 rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf); 2904 if (rc) 2905 goto err; 2906 2907 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 2908 pkglen); 2909 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) 2910 strscpy(ver, pkgver, size); 2911 else 2912 rc = -ENOENT; 2913 2914 err: 2915 kfree(pkgbuf); 2916 2917 return rc; 2918 } 2919 2920 static void bnxt_get_pkgver(struct net_device *dev) 2921 { 2922 struct bnxt *bp = netdev_priv(dev); 2923 char buf[FW_VER_STR_LEN]; 2924 int len; 2925 2926 if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) { 2927 len = strlen(bp->fw_ver_str); 2928 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1, 2929 "/pkg %s", buf); 2930 } 2931 } 2932 2933 static int bnxt_get_eeprom(struct net_device *dev, 2934 struct ethtool_eeprom *eeprom, 2935 u8 *data) 2936 { 2937 u32 index; 2938 u32 offset; 2939 2940 if (eeprom->offset == 0) /* special offset value to get directory */ 2941 return bnxt_get_nvram_directory(dev, eeprom->len, data); 2942 2943 index = eeprom->offset >> 24; 2944 offset = eeprom->offset & 0xffffff; 2945 2946 if (index == 0) { 2947 netdev_err(dev, "unsupported index value: %d\n", index); 2948 return -EINVAL; 2949 } 2950 2951 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 2952 } 2953 2954 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 2955 { 2956 struct hwrm_nvm_erase_dir_entry_input *req; 2957 struct bnxt *bp = netdev_priv(dev); 2958 int rc; 2959 2960 rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY); 2961 if (rc) 2962 return rc; 2963 2964 req->dir_idx = cpu_to_le16(index); 2965 return hwrm_req_send(bp, req); 2966 } 2967 2968 static int bnxt_set_eeprom(struct net_device *dev, 2969 struct ethtool_eeprom *eeprom, 2970 u8 *data) 2971 { 2972 struct bnxt *bp = netdev_priv(dev); 2973 u8 index, dir_op; 2974 u16 type, ext, ordinal, attr; 2975 2976 if (!BNXT_PF(bp)) { 2977 netdev_err(dev, "NVM write not supported from a virtual function\n"); 2978 return -EINVAL; 2979 } 2980 2981 type = eeprom->magic >> 16; 2982 2983 if (type == 0xffff) { /* special value for directory operations */ 2984 index = eeprom->magic & 0xff; 2985 dir_op = eeprom->magic >> 8; 2986 if (index == 0) 2987 return -EINVAL; 2988 switch (dir_op) { 2989 case 0x0e: /* erase */ 2990 if (eeprom->offset != ~eeprom->magic) 2991 return -EINVAL; 2992 return bnxt_erase_nvram_directory(dev, index - 1); 2993 default: 2994 return -EINVAL; 2995 } 2996 } 2997 2998 /* Create or re-write an NVM item: */ 2999 if (bnxt_dir_type_is_executable(type)) 3000 return -EOPNOTSUPP; 3001 ext = eeprom->magic & 0xffff; 3002 ordinal = eeprom->offset >> 16; 3003 attr = eeprom->offset & 0xffff; 3004 3005 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data, 3006 eeprom->len); 3007 } 3008 3009 static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata) 3010 { 3011 struct bnxt *bp = netdev_priv(dev); 3012 struct ethtool_eee *eee = &bp->eee; 3013 struct bnxt_link_info *link_info = &bp->link_info; 3014 u32 advertising; 3015 int rc = 0; 3016 3017 if (!BNXT_PHY_CFG_ABLE(bp)) 3018 return -EOPNOTSUPP; 3019 3020 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 3021 return -EOPNOTSUPP; 3022 3023 mutex_lock(&bp->link_lock); 3024 advertising = _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 3025 if (!edata->eee_enabled) 3026 goto eee_ok; 3027 3028 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 3029 netdev_warn(dev, "EEE requires autoneg\n"); 3030 rc = -EINVAL; 3031 goto eee_exit; 3032 } 3033 if (edata->tx_lpi_enabled) { 3034 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 3035 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 3036 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 3037 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 3038 rc = -EINVAL; 3039 goto eee_exit; 3040 } else if (!bp->lpi_tmr_hi) { 3041 edata->tx_lpi_timer = eee->tx_lpi_timer; 3042 } 3043 } 3044 if (!edata->advertised) { 3045 edata->advertised = advertising & eee->supported; 3046 } else if (edata->advertised & ~advertising) { 3047 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n", 3048 edata->advertised, advertising); 3049 rc = -EINVAL; 3050 goto eee_exit; 3051 } 3052 3053 eee->advertised = edata->advertised; 3054 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 3055 eee->tx_lpi_timer = edata->tx_lpi_timer; 3056 eee_ok: 3057 eee->eee_enabled = edata->eee_enabled; 3058 3059 if (netif_running(dev)) 3060 rc = bnxt_hwrm_set_link_setting(bp, false, true); 3061 3062 eee_exit: 3063 mutex_unlock(&bp->link_lock); 3064 return rc; 3065 } 3066 3067 static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata) 3068 { 3069 struct bnxt *bp = netdev_priv(dev); 3070 3071 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 3072 return -EOPNOTSUPP; 3073 3074 *edata = bp->eee; 3075 if (!bp->eee.eee_enabled) { 3076 /* Preserve tx_lpi_timer so that the last value will be used 3077 * by default when it is re-enabled. 3078 */ 3079 edata->advertised = 0; 3080 edata->tx_lpi_enabled = 0; 3081 } 3082 3083 if (!bp->eee.eee_active) 3084 edata->lp_advertised = 0; 3085 3086 return 0; 3087 } 3088 3089 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 3090 u16 page_number, u16 start_addr, 3091 u16 data_length, u8 *buf) 3092 { 3093 struct hwrm_port_phy_i2c_read_output *output; 3094 struct hwrm_port_phy_i2c_read_input *req; 3095 int rc, byte_offset = 0; 3096 3097 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ); 3098 if (rc) 3099 return rc; 3100 3101 output = hwrm_req_hold(bp, req); 3102 req->i2c_slave_addr = i2c_addr; 3103 req->page_number = cpu_to_le16(page_number); 3104 req->port_id = cpu_to_le16(bp->pf.port_id); 3105 do { 3106 u16 xfer_size; 3107 3108 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 3109 data_length -= xfer_size; 3110 req->page_offset = cpu_to_le16(start_addr + byte_offset); 3111 req->data_length = xfer_size; 3112 req->enables = cpu_to_le32(start_addr + byte_offset ? 3113 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 0); 3114 rc = hwrm_req_send(bp, req); 3115 if (!rc) 3116 memcpy(buf + byte_offset, output->data, xfer_size); 3117 byte_offset += xfer_size; 3118 } while (!rc && data_length > 0); 3119 hwrm_req_drop(bp, req); 3120 3121 return rc; 3122 } 3123 3124 static int bnxt_get_module_info(struct net_device *dev, 3125 struct ethtool_modinfo *modinfo) 3126 { 3127 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 3128 struct bnxt *bp = netdev_priv(dev); 3129 int rc; 3130 3131 /* No point in going further if phy status indicates 3132 * module is not inserted or if it is powered down or 3133 * if it is of type 10GBase-T 3134 */ 3135 if (bp->link_info.module_status > 3136 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 3137 return -EOPNOTSUPP; 3138 3139 /* This feature is not supported in older firmware versions */ 3140 if (bp->hwrm_spec_code < 0x10202) 3141 return -EOPNOTSUPP; 3142 3143 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 3144 SFF_DIAG_SUPPORT_OFFSET + 1, 3145 data); 3146 if (!rc) { 3147 u8 module_id = data[0]; 3148 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 3149 3150 switch (module_id) { 3151 case SFF_MODULE_ID_SFP: 3152 modinfo->type = ETH_MODULE_SFF_8472; 3153 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 3154 if (!diag_supported) 3155 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 3156 break; 3157 case SFF_MODULE_ID_QSFP: 3158 case SFF_MODULE_ID_QSFP_PLUS: 3159 modinfo->type = ETH_MODULE_SFF_8436; 3160 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 3161 break; 3162 case SFF_MODULE_ID_QSFP28: 3163 modinfo->type = ETH_MODULE_SFF_8636; 3164 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 3165 break; 3166 default: 3167 rc = -EOPNOTSUPP; 3168 break; 3169 } 3170 } 3171 return rc; 3172 } 3173 3174 static int bnxt_get_module_eeprom(struct net_device *dev, 3175 struct ethtool_eeprom *eeprom, 3176 u8 *data) 3177 { 3178 struct bnxt *bp = netdev_priv(dev); 3179 u16 start = eeprom->offset, length = eeprom->len; 3180 int rc = 0; 3181 3182 memset(data, 0, eeprom->len); 3183 3184 /* Read A0 portion of the EEPROM */ 3185 if (start < ETH_MODULE_SFF_8436_LEN) { 3186 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 3187 length = ETH_MODULE_SFF_8436_LEN - start; 3188 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 3189 start, length, data); 3190 if (rc) 3191 return rc; 3192 start += length; 3193 data += length; 3194 length = eeprom->len - length; 3195 } 3196 3197 /* Read A2 portion of the EEPROM */ 3198 if (length) { 3199 start -= ETH_MODULE_SFF_8436_LEN; 3200 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 3201 start, length, data); 3202 } 3203 return rc; 3204 } 3205 3206 static int bnxt_nway_reset(struct net_device *dev) 3207 { 3208 int rc = 0; 3209 3210 struct bnxt *bp = netdev_priv(dev); 3211 struct bnxt_link_info *link_info = &bp->link_info; 3212 3213 if (!BNXT_PHY_CFG_ABLE(bp)) 3214 return -EOPNOTSUPP; 3215 3216 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 3217 return -EINVAL; 3218 3219 if (netif_running(dev)) 3220 rc = bnxt_hwrm_set_link_setting(bp, true, false); 3221 3222 return rc; 3223 } 3224 3225 static int bnxt_set_phys_id(struct net_device *dev, 3226 enum ethtool_phys_id_state state) 3227 { 3228 struct hwrm_port_led_cfg_input *req; 3229 struct bnxt *bp = netdev_priv(dev); 3230 struct bnxt_pf_info *pf = &bp->pf; 3231 struct bnxt_led_cfg *led_cfg; 3232 u8 led_state; 3233 __le16 duration; 3234 int rc, i; 3235 3236 if (!bp->num_leds || BNXT_VF(bp)) 3237 return -EOPNOTSUPP; 3238 3239 if (state == ETHTOOL_ID_ACTIVE) { 3240 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 3241 duration = cpu_to_le16(500); 3242 } else if (state == ETHTOOL_ID_INACTIVE) { 3243 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 3244 duration = cpu_to_le16(0); 3245 } else { 3246 return -EINVAL; 3247 } 3248 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG); 3249 if (rc) 3250 return rc; 3251 3252 req->port_id = cpu_to_le16(pf->port_id); 3253 req->num_leds = bp->num_leds; 3254 led_cfg = (struct bnxt_led_cfg *)&req->led0_id; 3255 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 3256 req->enables |= BNXT_LED_DFLT_ENABLES(i); 3257 led_cfg->led_id = bp->leds[i].led_id; 3258 led_cfg->led_state = led_state; 3259 led_cfg->led_blink_on = duration; 3260 led_cfg->led_blink_off = duration; 3261 led_cfg->led_group_id = bp->leds[i].led_group_id; 3262 } 3263 return hwrm_req_send(bp, req); 3264 } 3265 3266 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 3267 { 3268 struct hwrm_selftest_irq_input *req; 3269 int rc; 3270 3271 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ); 3272 if (rc) 3273 return rc; 3274 3275 req->cmpl_ring = cpu_to_le16(cmpl_ring); 3276 return hwrm_req_send(bp, req); 3277 } 3278 3279 static int bnxt_test_irq(struct bnxt *bp) 3280 { 3281 int i; 3282 3283 for (i = 0; i < bp->cp_nr_rings; i++) { 3284 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 3285 int rc; 3286 3287 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 3288 if (rc) 3289 return rc; 3290 } 3291 return 0; 3292 } 3293 3294 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 3295 { 3296 struct hwrm_port_mac_cfg_input *req; 3297 int rc; 3298 3299 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 3300 if (rc) 3301 return rc; 3302 3303 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 3304 if (enable) 3305 req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 3306 else 3307 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 3308 return hwrm_req_send(bp, req); 3309 } 3310 3311 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 3312 { 3313 struct hwrm_port_phy_qcaps_output *resp; 3314 struct hwrm_port_phy_qcaps_input *req; 3315 int rc; 3316 3317 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS); 3318 if (rc) 3319 return rc; 3320 3321 resp = hwrm_req_hold(bp, req); 3322 rc = hwrm_req_send(bp, req); 3323 if (!rc) 3324 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 3325 3326 hwrm_req_drop(bp, req); 3327 return rc; 3328 } 3329 3330 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 3331 struct hwrm_port_phy_cfg_input *req) 3332 { 3333 struct bnxt_link_info *link_info = &bp->link_info; 3334 u16 fw_advertising; 3335 u16 fw_speed; 3336 int rc; 3337 3338 if (!link_info->autoneg || 3339 (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK)) 3340 return 0; 3341 3342 rc = bnxt_query_force_speeds(bp, &fw_advertising); 3343 if (rc) 3344 return rc; 3345 3346 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 3347 if (BNXT_LINK_IS_UP(bp)) 3348 fw_speed = bp->link_info.link_speed; 3349 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 3350 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 3351 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 3352 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 3353 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 3354 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 3355 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 3356 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 3357 3358 req->force_link_speed = cpu_to_le16(fw_speed); 3359 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 3360 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 3361 rc = hwrm_req_send(bp, req); 3362 req->flags = 0; 3363 req->force_link_speed = cpu_to_le16(0); 3364 return rc; 3365 } 3366 3367 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 3368 { 3369 struct hwrm_port_phy_cfg_input *req; 3370 int rc; 3371 3372 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 3373 if (rc) 3374 return rc; 3375 3376 /* prevent bnxt_disable_an_for_lpbk() from consuming the request */ 3377 hwrm_req_hold(bp, req); 3378 3379 if (enable) { 3380 bnxt_disable_an_for_lpbk(bp, req); 3381 if (ext) 3382 req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 3383 else 3384 req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 3385 } else { 3386 req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 3387 } 3388 req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 3389 rc = hwrm_req_send(bp, req); 3390 hwrm_req_drop(bp, req); 3391 return rc; 3392 } 3393 3394 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 3395 u32 raw_cons, int pkt_size) 3396 { 3397 struct bnxt_napi *bnapi = cpr->bnapi; 3398 struct bnxt_rx_ring_info *rxr; 3399 struct bnxt_sw_rx_bd *rx_buf; 3400 struct rx_cmp *rxcmp; 3401 u16 cp_cons, cons; 3402 u8 *data; 3403 u32 len; 3404 int i; 3405 3406 rxr = bnapi->rx_ring; 3407 cp_cons = RING_CMP(raw_cons); 3408 rxcmp = (struct rx_cmp *) 3409 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 3410 cons = rxcmp->rx_cmp_opaque; 3411 rx_buf = &rxr->rx_buf_ring[cons]; 3412 data = rx_buf->data_ptr; 3413 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 3414 if (len != pkt_size) 3415 return -EIO; 3416 i = ETH_ALEN; 3417 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 3418 return -EIO; 3419 i += ETH_ALEN; 3420 for ( ; i < pkt_size; i++) { 3421 if (data[i] != (u8)(i & 0xff)) 3422 return -EIO; 3423 } 3424 return 0; 3425 } 3426 3427 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 3428 int pkt_size) 3429 { 3430 struct tx_cmp *txcmp; 3431 int rc = -EIO; 3432 u32 raw_cons; 3433 u32 cons; 3434 int i; 3435 3436 raw_cons = cpr->cp_raw_cons; 3437 for (i = 0; i < 200; i++) { 3438 cons = RING_CMP(raw_cons); 3439 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 3440 3441 if (!TX_CMP_VALID(txcmp, raw_cons)) { 3442 udelay(5); 3443 continue; 3444 } 3445 3446 /* The valid test of the entry must be done first before 3447 * reading any further. 3448 */ 3449 dma_rmb(); 3450 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) { 3451 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 3452 raw_cons = NEXT_RAW_CMP(raw_cons); 3453 raw_cons = NEXT_RAW_CMP(raw_cons); 3454 break; 3455 } 3456 raw_cons = NEXT_RAW_CMP(raw_cons); 3457 } 3458 cpr->cp_raw_cons = raw_cons; 3459 return rc; 3460 } 3461 3462 static int bnxt_run_loopback(struct bnxt *bp) 3463 { 3464 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 3465 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 3466 struct bnxt_cp_ring_info *cpr; 3467 int pkt_size, i = 0; 3468 struct sk_buff *skb; 3469 dma_addr_t map; 3470 u8 *data; 3471 int rc; 3472 3473 cpr = &rxr->bnapi->cp_ring; 3474 if (bp->flags & BNXT_FLAG_CHIP_P5) 3475 cpr = cpr->cp_ring_arr[BNXT_RX_HDL]; 3476 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh); 3477 skb = netdev_alloc_skb(bp->dev, pkt_size); 3478 if (!skb) 3479 return -ENOMEM; 3480 data = skb_put(skb, pkt_size); 3481 ether_addr_copy(&data[i], bp->dev->dev_addr); 3482 i += ETH_ALEN; 3483 ether_addr_copy(&data[i], bp->dev->dev_addr); 3484 i += ETH_ALEN; 3485 for ( ; i < pkt_size; i++) 3486 data[i] = (u8)(i & 0xff); 3487 3488 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 3489 DMA_TO_DEVICE); 3490 if (dma_mapping_error(&bp->pdev->dev, map)) { 3491 dev_kfree_skb(skb); 3492 return -EIO; 3493 } 3494 bnxt_xmit_bd(bp, txr, map, pkt_size); 3495 3496 /* Sync BD data before updating doorbell */ 3497 wmb(); 3498 3499 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 3500 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 3501 3502 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE); 3503 dev_kfree_skb(skb); 3504 return rc; 3505 } 3506 3507 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 3508 { 3509 struct hwrm_selftest_exec_output *resp; 3510 struct hwrm_selftest_exec_input *req; 3511 int rc; 3512 3513 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC); 3514 if (rc) 3515 return rc; 3516 3517 hwrm_req_timeout(bp, req, bp->test_info->timeout); 3518 req->flags = test_mask; 3519 3520 resp = hwrm_req_hold(bp, req); 3521 rc = hwrm_req_send(bp, req); 3522 *test_results = resp->test_success; 3523 hwrm_req_drop(bp, req); 3524 return rc; 3525 } 3526 3527 #define BNXT_DRV_TESTS 4 3528 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 3529 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 3530 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 3531 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 3532 3533 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 3534 u64 *buf) 3535 { 3536 struct bnxt *bp = netdev_priv(dev); 3537 bool do_ext_lpbk = false; 3538 bool offline = false; 3539 u8 test_results = 0; 3540 u8 test_mask = 0; 3541 int rc = 0, i; 3542 3543 if (!bp->num_tests || !BNXT_PF(bp)) 3544 return; 3545 memset(buf, 0, sizeof(u64) * bp->num_tests); 3546 if (!netif_running(dev)) { 3547 etest->flags |= ETH_TEST_FL_FAILED; 3548 return; 3549 } 3550 3551 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 3552 (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK)) 3553 do_ext_lpbk = true; 3554 3555 if (etest->flags & ETH_TEST_FL_OFFLINE) { 3556 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) { 3557 etest->flags |= ETH_TEST_FL_FAILED; 3558 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n"); 3559 return; 3560 } 3561 offline = true; 3562 } 3563 3564 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 3565 u8 bit_val = 1 << i; 3566 3567 if (!(bp->test_info->offline_mask & bit_val)) 3568 test_mask |= bit_val; 3569 else if (offline) 3570 test_mask |= bit_val; 3571 } 3572 if (!offline) { 3573 bnxt_run_fw_tests(bp, test_mask, &test_results); 3574 } else { 3575 bnxt_ulp_stop(bp); 3576 rc = bnxt_close_nic(bp, true, false); 3577 if (rc) { 3578 bnxt_ulp_start(bp, rc); 3579 return; 3580 } 3581 bnxt_run_fw_tests(bp, test_mask, &test_results); 3582 3583 buf[BNXT_MACLPBK_TEST_IDX] = 1; 3584 bnxt_hwrm_mac_loopback(bp, true); 3585 msleep(250); 3586 rc = bnxt_half_open_nic(bp); 3587 if (rc) { 3588 bnxt_hwrm_mac_loopback(bp, false); 3589 etest->flags |= ETH_TEST_FL_FAILED; 3590 bnxt_ulp_start(bp, rc); 3591 return; 3592 } 3593 if (bnxt_run_loopback(bp)) 3594 etest->flags |= ETH_TEST_FL_FAILED; 3595 else 3596 buf[BNXT_MACLPBK_TEST_IDX] = 0; 3597 3598 bnxt_hwrm_mac_loopback(bp, false); 3599 bnxt_hwrm_phy_loopback(bp, true, false); 3600 msleep(1000); 3601 if (bnxt_run_loopback(bp)) { 3602 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 3603 etest->flags |= ETH_TEST_FL_FAILED; 3604 } 3605 if (do_ext_lpbk) { 3606 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 3607 bnxt_hwrm_phy_loopback(bp, true, true); 3608 msleep(1000); 3609 if (bnxt_run_loopback(bp)) { 3610 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 3611 etest->flags |= ETH_TEST_FL_FAILED; 3612 } 3613 } 3614 bnxt_hwrm_phy_loopback(bp, false, false); 3615 bnxt_half_close_nic(bp); 3616 rc = bnxt_open_nic(bp, true, true); 3617 bnxt_ulp_start(bp, rc); 3618 } 3619 if (rc || bnxt_test_irq(bp)) { 3620 buf[BNXT_IRQ_TEST_IDX] = 1; 3621 etest->flags |= ETH_TEST_FL_FAILED; 3622 } 3623 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 3624 u8 bit_val = 1 << i; 3625 3626 if ((test_mask & bit_val) && !(test_results & bit_val)) { 3627 buf[i] = 1; 3628 etest->flags |= ETH_TEST_FL_FAILED; 3629 } 3630 } 3631 } 3632 3633 static int bnxt_reset(struct net_device *dev, u32 *flags) 3634 { 3635 struct bnxt *bp = netdev_priv(dev); 3636 bool reload = false; 3637 u32 req = *flags; 3638 3639 if (!req) 3640 return -EINVAL; 3641 3642 if (!BNXT_PF(bp)) { 3643 netdev_err(dev, "Reset is not supported from a VF\n"); 3644 return -EOPNOTSUPP; 3645 } 3646 3647 if (pci_vfs_assigned(bp->pdev) && 3648 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) { 3649 netdev_err(dev, 3650 "Reset not allowed when VFs are assigned to VMs\n"); 3651 return -EBUSY; 3652 } 3653 3654 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) { 3655 /* This feature is not supported in older firmware versions */ 3656 if (bp->hwrm_spec_code >= 0x10803) { 3657 if (!bnxt_firmware_reset_chip(dev)) { 3658 netdev_info(dev, "Firmware reset request successful.\n"); 3659 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) 3660 reload = true; 3661 *flags &= ~BNXT_FW_RESET_CHIP; 3662 } 3663 } else if (req == BNXT_FW_RESET_CHIP) { 3664 return -EOPNOTSUPP; /* only request, fail hard */ 3665 } 3666 } 3667 3668 if (req & BNXT_FW_RESET_AP) { 3669 /* This feature is not supported in older firmware versions */ 3670 if (bp->hwrm_spec_code >= 0x10803) { 3671 if (!bnxt_firmware_reset_ap(dev)) { 3672 netdev_info(dev, "Reset application processor successful.\n"); 3673 reload = true; 3674 *flags &= ~BNXT_FW_RESET_AP; 3675 } 3676 } else if (req == BNXT_FW_RESET_AP) { 3677 return -EOPNOTSUPP; /* only request, fail hard */ 3678 } 3679 } 3680 3681 if (reload) 3682 netdev_info(dev, "Reload driver to complete reset\n"); 3683 3684 return 0; 3685 } 3686 3687 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump) 3688 { 3689 struct bnxt *bp = netdev_priv(dev); 3690 3691 if (dump->flag > BNXT_DUMP_CRASH) { 3692 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n"); 3693 return -EINVAL; 3694 } 3695 3696 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) { 3697 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n"); 3698 return -EOPNOTSUPP; 3699 } 3700 3701 bp->dump_flag = dump->flag; 3702 return 0; 3703 } 3704 3705 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 3706 { 3707 struct bnxt *bp = netdev_priv(dev); 3708 3709 if (bp->hwrm_spec_code < 0x10801) 3710 return -EOPNOTSUPP; 3711 3712 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 3713 bp->ver_resp.hwrm_fw_min_8b << 16 | 3714 bp->ver_resp.hwrm_fw_bld_8b << 8 | 3715 bp->ver_resp.hwrm_fw_rsvd_8b; 3716 3717 dump->flag = bp->dump_flag; 3718 dump->len = bnxt_get_coredump_length(bp, bp->dump_flag); 3719 return 0; 3720 } 3721 3722 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 3723 void *buf) 3724 { 3725 struct bnxt *bp = netdev_priv(dev); 3726 3727 if (bp->hwrm_spec_code < 0x10801) 3728 return -EOPNOTSUPP; 3729 3730 memset(buf, 0, dump->len); 3731 3732 dump->flag = bp->dump_flag; 3733 return bnxt_get_coredump(bp, dump->flag, buf, &dump->len); 3734 } 3735 3736 static int bnxt_get_ts_info(struct net_device *dev, 3737 struct ethtool_ts_info *info) 3738 { 3739 struct bnxt *bp = netdev_priv(dev); 3740 struct bnxt_ptp_cfg *ptp; 3741 3742 ptp = bp->ptp_cfg; 3743 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 3744 SOF_TIMESTAMPING_RX_SOFTWARE | 3745 SOF_TIMESTAMPING_SOFTWARE; 3746 3747 info->phc_index = -1; 3748 if (!ptp) 3749 return 0; 3750 3751 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | 3752 SOF_TIMESTAMPING_RX_HARDWARE | 3753 SOF_TIMESTAMPING_RAW_HARDWARE; 3754 if (ptp->ptp_clock) 3755 info->phc_index = ptp_clock_index(ptp->ptp_clock); 3756 3757 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 3758 3759 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 3760 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 3761 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 3762 return 0; 3763 } 3764 3765 void bnxt_ethtool_init(struct bnxt *bp) 3766 { 3767 struct hwrm_selftest_qlist_output *resp; 3768 struct hwrm_selftest_qlist_input *req; 3769 struct bnxt_test_info *test_info; 3770 struct net_device *dev = bp->dev; 3771 int i, rc; 3772 3773 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 3774 bnxt_get_pkgver(dev); 3775 3776 bp->num_tests = 0; 3777 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp)) 3778 return; 3779 3780 test_info = bp->test_info; 3781 if (!test_info) { 3782 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL); 3783 if (!test_info) 3784 return; 3785 bp->test_info = test_info; 3786 } 3787 3788 if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST)) 3789 return; 3790 3791 resp = hwrm_req_hold(bp, req); 3792 rc = hwrm_req_send_silent(bp, req); 3793 if (rc) 3794 goto ethtool_init_exit; 3795 3796 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 3797 if (bp->num_tests > BNXT_MAX_TEST) 3798 bp->num_tests = BNXT_MAX_TEST; 3799 3800 test_info->offline_mask = resp->offline_tests; 3801 test_info->timeout = le16_to_cpu(resp->test_timeout); 3802 if (!test_info->timeout) 3803 test_info->timeout = HWRM_CMD_TIMEOUT; 3804 for (i = 0; i < bp->num_tests; i++) { 3805 char *str = test_info->string[i]; 3806 char *fw_str = resp->test0_name + i * 32; 3807 3808 if (i == BNXT_MACLPBK_TEST_IDX) { 3809 strcpy(str, "Mac loopback test (offline)"); 3810 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 3811 strcpy(str, "Phy loopback test (offline)"); 3812 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 3813 strcpy(str, "Ext loopback test (offline)"); 3814 } else if (i == BNXT_IRQ_TEST_IDX) { 3815 strcpy(str, "Interrupt_test (offline)"); 3816 } else { 3817 strlcpy(str, fw_str, ETH_GSTRING_LEN); 3818 strncat(str, " test", ETH_GSTRING_LEN - strlen(str)); 3819 if (test_info->offline_mask & (1 << i)) 3820 strncat(str, " (offline)", 3821 ETH_GSTRING_LEN - strlen(str)); 3822 else 3823 strncat(str, " (online)", 3824 ETH_GSTRING_LEN - strlen(str)); 3825 } 3826 } 3827 3828 ethtool_init_exit: 3829 hwrm_req_drop(bp, req); 3830 } 3831 3832 static void bnxt_get_eth_phy_stats(struct net_device *dev, 3833 struct ethtool_eth_phy_stats *phy_stats) 3834 { 3835 struct bnxt *bp = netdev_priv(dev); 3836 u64 *rx; 3837 3838 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 3839 return; 3840 3841 rx = bp->rx_port_stats_ext.sw_stats; 3842 phy_stats->SymbolErrorDuringCarrier = 3843 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err)); 3844 } 3845 3846 static void bnxt_get_eth_mac_stats(struct net_device *dev, 3847 struct ethtool_eth_mac_stats *mac_stats) 3848 { 3849 struct bnxt *bp = netdev_priv(dev); 3850 u64 *rx, *tx; 3851 3852 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 3853 return; 3854 3855 rx = bp->port_stats.sw_stats; 3856 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 3857 3858 mac_stats->FramesReceivedOK = 3859 BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames); 3860 mac_stats->FramesTransmittedOK = 3861 BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames); 3862 mac_stats->FrameCheckSequenceErrors = 3863 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames); 3864 mac_stats->AlignmentErrors = 3865 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames); 3866 mac_stats->OutOfRangeLengthField = 3867 BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames); 3868 } 3869 3870 static void bnxt_get_eth_ctrl_stats(struct net_device *dev, 3871 struct ethtool_eth_ctrl_stats *ctrl_stats) 3872 { 3873 struct bnxt *bp = netdev_priv(dev); 3874 u64 *rx; 3875 3876 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 3877 return; 3878 3879 rx = bp->port_stats.sw_stats; 3880 ctrl_stats->MACControlFramesReceived = 3881 BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames); 3882 } 3883 3884 static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = { 3885 { 0, 64 }, 3886 { 65, 127 }, 3887 { 128, 255 }, 3888 { 256, 511 }, 3889 { 512, 1023 }, 3890 { 1024, 1518 }, 3891 { 1519, 2047 }, 3892 { 2048, 4095 }, 3893 { 4096, 9216 }, 3894 { 9217, 16383 }, 3895 {} 3896 }; 3897 3898 static void bnxt_get_rmon_stats(struct net_device *dev, 3899 struct ethtool_rmon_stats *rmon_stats, 3900 const struct ethtool_rmon_hist_range **ranges) 3901 { 3902 struct bnxt *bp = netdev_priv(dev); 3903 u64 *rx, *tx; 3904 3905 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 3906 return; 3907 3908 rx = bp->port_stats.sw_stats; 3909 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 3910 3911 rmon_stats->jabbers = 3912 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames); 3913 rmon_stats->oversize_pkts = 3914 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames); 3915 rmon_stats->undersize_pkts = 3916 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames); 3917 3918 rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames); 3919 rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames); 3920 rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames); 3921 rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames); 3922 rmon_stats->hist[4] = 3923 BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames); 3924 rmon_stats->hist[5] = 3925 BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames); 3926 rmon_stats->hist[6] = 3927 BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames); 3928 rmon_stats->hist[7] = 3929 BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames); 3930 rmon_stats->hist[8] = 3931 BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames); 3932 rmon_stats->hist[9] = 3933 BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames); 3934 3935 rmon_stats->hist_tx[0] = 3936 BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames); 3937 rmon_stats->hist_tx[1] = 3938 BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames); 3939 rmon_stats->hist_tx[2] = 3940 BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames); 3941 rmon_stats->hist_tx[3] = 3942 BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames); 3943 rmon_stats->hist_tx[4] = 3944 BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames); 3945 rmon_stats->hist_tx[5] = 3946 BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames); 3947 rmon_stats->hist_tx[6] = 3948 BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames); 3949 rmon_stats->hist_tx[7] = 3950 BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames); 3951 rmon_stats->hist_tx[8] = 3952 BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames); 3953 rmon_stats->hist_tx[9] = 3954 BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames); 3955 3956 *ranges = bnxt_rmon_ranges; 3957 } 3958 3959 void bnxt_ethtool_free(struct bnxt *bp) 3960 { 3961 kfree(bp->test_info); 3962 bp->test_info = NULL; 3963 } 3964 3965 const struct ethtool_ops bnxt_ethtool_ops = { 3966 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 3967 ETHTOOL_COALESCE_MAX_FRAMES | 3968 ETHTOOL_COALESCE_USECS_IRQ | 3969 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 3970 ETHTOOL_COALESCE_STATS_BLOCK_USECS | 3971 ETHTOOL_COALESCE_USE_ADAPTIVE_RX | 3972 ETHTOOL_COALESCE_USE_CQE, 3973 .get_link_ksettings = bnxt_get_link_ksettings, 3974 .set_link_ksettings = bnxt_set_link_ksettings, 3975 .get_fec_stats = bnxt_get_fec_stats, 3976 .get_fecparam = bnxt_get_fecparam, 3977 .set_fecparam = bnxt_set_fecparam, 3978 .get_pause_stats = bnxt_get_pause_stats, 3979 .get_pauseparam = bnxt_get_pauseparam, 3980 .set_pauseparam = bnxt_set_pauseparam, 3981 .get_drvinfo = bnxt_get_drvinfo, 3982 .get_regs_len = bnxt_get_regs_len, 3983 .get_regs = bnxt_get_regs, 3984 .get_wol = bnxt_get_wol, 3985 .set_wol = bnxt_set_wol, 3986 .get_coalesce = bnxt_get_coalesce, 3987 .set_coalesce = bnxt_set_coalesce, 3988 .get_msglevel = bnxt_get_msglevel, 3989 .set_msglevel = bnxt_set_msglevel, 3990 .get_sset_count = bnxt_get_sset_count, 3991 .get_strings = bnxt_get_strings, 3992 .get_ethtool_stats = bnxt_get_ethtool_stats, 3993 .set_ringparam = bnxt_set_ringparam, 3994 .get_ringparam = bnxt_get_ringparam, 3995 .get_channels = bnxt_get_channels, 3996 .set_channels = bnxt_set_channels, 3997 .get_rxnfc = bnxt_get_rxnfc, 3998 .set_rxnfc = bnxt_set_rxnfc, 3999 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 4000 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 4001 .get_rxfh = bnxt_get_rxfh, 4002 .set_rxfh = bnxt_set_rxfh, 4003 .flash_device = bnxt_flash_device, 4004 .get_eeprom_len = bnxt_get_eeprom_len, 4005 .get_eeprom = bnxt_get_eeprom, 4006 .set_eeprom = bnxt_set_eeprom, 4007 .get_link = bnxt_get_link, 4008 .get_eee = bnxt_get_eee, 4009 .set_eee = bnxt_set_eee, 4010 .get_module_info = bnxt_get_module_info, 4011 .get_module_eeprom = bnxt_get_module_eeprom, 4012 .nway_reset = bnxt_nway_reset, 4013 .set_phys_id = bnxt_set_phys_id, 4014 .self_test = bnxt_self_test, 4015 .get_ts_info = bnxt_get_ts_info, 4016 .reset = bnxt_reset, 4017 .set_dump = bnxt_set_dump, 4018 .get_dump_flag = bnxt_get_dump_flag, 4019 .get_dump_data = bnxt_get_dump_data, 4020 .get_eth_phy_stats = bnxt_get_eth_phy_stats, 4021 .get_eth_mac_stats = bnxt_get_eth_mac_stats, 4022 .get_eth_ctrl_stats = bnxt_get_eth_ctrl_stats, 4023 .get_rmon_stats = bnxt_get_rmon_stats, 4024 }; 4025