1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/netdevice.h> 12 #include <linux/types.h> 13 #include <linux/errno.h> 14 #include <linux/rtnetlink.h> 15 #include <linux/interrupt.h> 16 #include <linux/pci.h> 17 #include <linux/etherdevice.h> 18 #include <rdma/ib_verbs.h> 19 #include "bnxt_hsi.h" 20 #include "bnxt.h" 21 #include "bnxt_dcb.h" 22 23 #ifdef CONFIG_BNXT_DCB 24 static int bnxt_queue_to_tc(struct bnxt *bp, u8 queue_id) 25 { 26 int i, j; 27 28 for (i = 0; i < bp->max_tc; i++) { 29 if (bp->q_info[i].queue_id == queue_id) { 30 for (j = 0; j < bp->max_tc; j++) { 31 if (bp->tc_to_qidx[j] == i) 32 return j; 33 } 34 } 35 } 36 return -EINVAL; 37 } 38 39 static int bnxt_hwrm_queue_pri2cos_cfg(struct bnxt *bp, struct ieee_ets *ets) 40 { 41 struct hwrm_queue_pri2cos_cfg_input req = {0}; 42 int rc = 0, i; 43 u8 *pri2cos; 44 45 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_PRI2COS_CFG, -1, -1); 46 req.flags = cpu_to_le32(QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR | 47 QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN); 48 49 pri2cos = &req.pri0_cos_queue_id; 50 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 51 u8 qidx; 52 53 req.enables |= cpu_to_le32( 54 QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID << i); 55 56 qidx = bp->tc_to_qidx[ets->prio_tc[i]]; 57 pri2cos[i] = bp->q_info[qidx].queue_id; 58 } 59 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 60 return rc; 61 } 62 63 static int bnxt_hwrm_queue_pri2cos_qcfg(struct bnxt *bp, struct ieee_ets *ets) 64 { 65 struct hwrm_queue_pri2cos_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 66 struct hwrm_queue_pri2cos_qcfg_input req = {0}; 67 int rc = 0; 68 69 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_PRI2COS_QCFG, -1, -1); 70 req.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN); 71 72 mutex_lock(&bp->hwrm_cmd_lock); 73 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 74 if (!rc) { 75 u8 *pri2cos = &resp->pri0_cos_queue_id; 76 int i; 77 78 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 79 u8 queue_id = pri2cos[i]; 80 int tc; 81 82 tc = bnxt_queue_to_tc(bp, queue_id); 83 if (tc >= 0) 84 ets->prio_tc[i] = tc; 85 } 86 } 87 mutex_unlock(&bp->hwrm_cmd_lock); 88 return rc; 89 } 90 91 static int bnxt_hwrm_queue_cos2bw_cfg(struct bnxt *bp, struct ieee_ets *ets, 92 u8 max_tc) 93 { 94 struct hwrm_queue_cos2bw_cfg_input req = {0}; 95 struct bnxt_cos2bw_cfg cos2bw; 96 int rc = 0, i; 97 void *data; 98 99 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_COS2BW_CFG, -1, -1); 100 for (i = 0; i < max_tc; i++) { 101 u8 qidx; 102 103 req.enables |= cpu_to_le32( 104 QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID << i); 105 106 memset(&cos2bw, 0, sizeof(cos2bw)); 107 qidx = bp->tc_to_qidx[i]; 108 cos2bw.queue_id = bp->q_info[qidx].queue_id; 109 if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_STRICT) { 110 cos2bw.tsa = 111 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP; 112 cos2bw.pri_lvl = i; 113 } else { 114 cos2bw.tsa = 115 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS; 116 cos2bw.bw_weight = ets->tc_tx_bw[i]; 117 /* older firmware requires min_bw to be set to the 118 * same weight value in percent. 119 */ 120 cos2bw.min_bw = 121 cpu_to_le32((ets->tc_tx_bw[i] * 100) | 122 BW_VALUE_UNIT_PERCENT1_100); 123 } 124 data = &req.unused_0 + qidx * (sizeof(cos2bw) - 4); 125 memcpy(data, &cos2bw.queue_id, sizeof(cos2bw) - 4); 126 if (qidx == 0) { 127 req.queue_id0 = cos2bw.queue_id; 128 req.unused_0 = 0; 129 } 130 } 131 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 132 return rc; 133 } 134 135 static int bnxt_hwrm_queue_cos2bw_qcfg(struct bnxt *bp, struct ieee_ets *ets) 136 { 137 struct hwrm_queue_cos2bw_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 138 struct hwrm_queue_cos2bw_qcfg_input req = {0}; 139 struct bnxt_cos2bw_cfg cos2bw; 140 void *data; 141 int rc, i; 142 143 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_COS2BW_QCFG, -1, -1); 144 145 mutex_lock(&bp->hwrm_cmd_lock); 146 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 147 if (rc) { 148 mutex_unlock(&bp->hwrm_cmd_lock); 149 return rc; 150 } 151 152 data = &resp->queue_id0 + offsetof(struct bnxt_cos2bw_cfg, queue_id); 153 for (i = 0; i < bp->max_tc; i++, data += sizeof(cos2bw) - 4) { 154 int tc; 155 156 memcpy(&cos2bw.queue_id, data, sizeof(cos2bw) - 4); 157 if (i == 0) 158 cos2bw.queue_id = resp->queue_id0; 159 160 tc = bnxt_queue_to_tc(bp, cos2bw.queue_id); 161 if (tc < 0) 162 continue; 163 164 if (cos2bw.tsa == 165 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP) { 166 ets->tc_tsa[tc] = IEEE_8021QAZ_TSA_STRICT; 167 } else { 168 ets->tc_tsa[tc] = IEEE_8021QAZ_TSA_ETS; 169 ets->tc_tx_bw[tc] = cos2bw.bw_weight; 170 } 171 } 172 mutex_unlock(&bp->hwrm_cmd_lock); 173 return 0; 174 } 175 176 static int bnxt_queue_remap(struct bnxt *bp, unsigned int lltc_mask) 177 { 178 unsigned long qmap = 0; 179 int max = bp->max_tc; 180 int i, j, rc; 181 182 /* Assign lossless TCs first */ 183 for (i = 0, j = 0; i < max; ) { 184 if (lltc_mask & (1 << i)) { 185 if (BNXT_LLQ(bp->q_info[j].queue_profile)) { 186 bp->tc_to_qidx[i] = j; 187 __set_bit(j, &qmap); 188 i++; 189 } 190 j++; 191 continue; 192 } 193 i++; 194 } 195 196 for (i = 0, j = 0; i < max; i++) { 197 if (lltc_mask & (1 << i)) 198 continue; 199 j = find_next_zero_bit(&qmap, max, j); 200 bp->tc_to_qidx[i] = j; 201 __set_bit(j, &qmap); 202 j++; 203 } 204 205 if (netif_running(bp->dev)) { 206 bnxt_close_nic(bp, false, false); 207 rc = bnxt_open_nic(bp, false, false); 208 if (rc) { 209 netdev_warn(bp->dev, "failed to open NIC, rc = %d\n", rc); 210 return rc; 211 } 212 } 213 if (bp->ieee_ets) { 214 int tc = netdev_get_num_tc(bp->dev); 215 216 if (!tc) 217 tc = 1; 218 rc = bnxt_hwrm_queue_cos2bw_cfg(bp, bp->ieee_ets, tc); 219 if (rc) { 220 netdev_warn(bp->dev, "failed to config BW, rc = %d\n", rc); 221 return rc; 222 } 223 rc = bnxt_hwrm_queue_pri2cos_cfg(bp, bp->ieee_ets); 224 if (rc) { 225 netdev_warn(bp->dev, "failed to config prio, rc = %d\n", rc); 226 return rc; 227 } 228 } 229 return 0; 230 } 231 232 static int bnxt_hwrm_queue_pfc_cfg(struct bnxt *bp, struct ieee_pfc *pfc) 233 { 234 struct hwrm_queue_pfcenable_cfg_input req = {0}; 235 struct ieee_ets *my_ets = bp->ieee_ets; 236 unsigned int tc_mask = 0, pri_mask = 0; 237 u8 i, pri, lltc_count = 0; 238 bool need_q_remap = false; 239 int rc; 240 241 if (!my_ets) 242 return -EINVAL; 243 244 for (i = 0; i < bp->max_tc; i++) { 245 for (pri = 0; pri < IEEE_8021QAZ_MAX_TCS; pri++) { 246 if ((pfc->pfc_en & (1 << pri)) && 247 (my_ets->prio_tc[pri] == i)) { 248 pri_mask |= 1 << pri; 249 tc_mask |= 1 << i; 250 } 251 } 252 if (tc_mask & (1 << i)) 253 lltc_count++; 254 } 255 if (lltc_count > bp->max_lltc) 256 return -EINVAL; 257 258 for (i = 0; i < bp->max_tc; i++) { 259 if (tc_mask & (1 << i)) { 260 u8 qidx = bp->tc_to_qidx[i]; 261 262 if (!BNXT_LLQ(bp->q_info[qidx].queue_profile)) { 263 need_q_remap = true; 264 break; 265 } 266 } 267 } 268 269 if (need_q_remap) 270 rc = bnxt_queue_remap(bp, tc_mask); 271 272 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_PFCENABLE_CFG, -1, -1); 273 req.flags = cpu_to_le32(pri_mask); 274 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 275 if (rc) 276 return rc; 277 278 return rc; 279 } 280 281 static int bnxt_hwrm_queue_pfc_qcfg(struct bnxt *bp, struct ieee_pfc *pfc) 282 { 283 struct hwrm_queue_pfcenable_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 284 struct hwrm_queue_pfcenable_qcfg_input req = {0}; 285 u8 pri_mask; 286 int rc; 287 288 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_PFCENABLE_QCFG, -1, -1); 289 290 mutex_lock(&bp->hwrm_cmd_lock); 291 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 292 if (rc) { 293 mutex_unlock(&bp->hwrm_cmd_lock); 294 return rc; 295 } 296 297 pri_mask = le32_to_cpu(resp->flags); 298 pfc->pfc_en = pri_mask; 299 mutex_unlock(&bp->hwrm_cmd_lock); 300 return 0; 301 } 302 303 static int bnxt_hwrm_set_dcbx_app(struct bnxt *bp, struct dcb_app *app, 304 bool add) 305 { 306 struct hwrm_fw_set_structured_data_input set = {0}; 307 struct hwrm_fw_get_structured_data_input get = {0}; 308 struct hwrm_struct_data_dcbx_app *fw_app; 309 struct hwrm_struct_hdr *data; 310 dma_addr_t mapping; 311 size_t data_len; 312 int rc, n, i; 313 314 if (bp->hwrm_spec_code < 0x10601) 315 return 0; 316 317 n = IEEE_8021QAZ_MAX_TCS; 318 data_len = sizeof(*data) + sizeof(*fw_app) * n; 319 data = dma_zalloc_coherent(&bp->pdev->dev, data_len, &mapping, 320 GFP_KERNEL); 321 if (!data) 322 return -ENOMEM; 323 324 bnxt_hwrm_cmd_hdr_init(bp, &get, HWRM_FW_GET_STRUCTURED_DATA, -1, -1); 325 get.dest_data_addr = cpu_to_le64(mapping); 326 get.structure_id = cpu_to_le16(STRUCT_HDR_STRUCT_ID_DCBX_APP); 327 get.subtype = cpu_to_le16(HWRM_STRUCT_DATA_SUBTYPE_HOST_OPERATIONAL); 328 get.count = 0; 329 rc = hwrm_send_message(bp, &get, sizeof(get), HWRM_CMD_TIMEOUT); 330 if (rc) 331 goto set_app_exit; 332 333 fw_app = (struct hwrm_struct_data_dcbx_app *)(data + 1); 334 335 if (data->struct_id != cpu_to_le16(STRUCT_HDR_STRUCT_ID_DCBX_APP)) { 336 rc = -ENODEV; 337 goto set_app_exit; 338 } 339 340 n = data->count; 341 for (i = 0; i < n; i++, fw_app++) { 342 if (fw_app->protocol_id == cpu_to_be16(app->protocol) && 343 fw_app->protocol_selector == app->selector && 344 fw_app->priority == app->priority) { 345 if (add) 346 goto set_app_exit; 347 else 348 break; 349 } 350 } 351 if (add) { 352 /* append */ 353 n++; 354 fw_app->protocol_id = cpu_to_be16(app->protocol); 355 fw_app->protocol_selector = app->selector; 356 fw_app->priority = app->priority; 357 fw_app->valid = 1; 358 } else { 359 size_t len = 0; 360 361 /* not found, nothing to delete */ 362 if (n == i) 363 goto set_app_exit; 364 365 len = (n - 1 - i) * sizeof(*fw_app); 366 if (len) 367 memmove(fw_app, fw_app + 1, len); 368 n--; 369 memset(fw_app + n, 0, sizeof(*fw_app)); 370 } 371 data->count = n; 372 data->len = cpu_to_le16(sizeof(*fw_app) * n); 373 data->subtype = cpu_to_le16(HWRM_STRUCT_DATA_SUBTYPE_HOST_OPERATIONAL); 374 375 bnxt_hwrm_cmd_hdr_init(bp, &set, HWRM_FW_SET_STRUCTURED_DATA, -1, -1); 376 set.src_data_addr = cpu_to_le64(mapping); 377 set.data_len = cpu_to_le16(sizeof(*data) + sizeof(*fw_app) * n); 378 set.hdr_cnt = 1; 379 rc = hwrm_send_message(bp, &set, sizeof(set), HWRM_CMD_TIMEOUT); 380 if (rc) 381 rc = -EIO; 382 383 set_app_exit: 384 dma_free_coherent(&bp->pdev->dev, data_len, data, mapping); 385 return rc; 386 } 387 388 static int bnxt_ets_validate(struct bnxt *bp, struct ieee_ets *ets, u8 *tc) 389 { 390 int total_ets_bw = 0; 391 u8 max_tc = 0; 392 int i; 393 394 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 395 if (ets->prio_tc[i] > bp->max_tc) { 396 netdev_err(bp->dev, "priority to TC mapping exceeds TC count %d\n", 397 ets->prio_tc[i]); 398 return -EINVAL; 399 } 400 if (ets->prio_tc[i] > max_tc) 401 max_tc = ets->prio_tc[i]; 402 403 if ((ets->tc_tx_bw[i] || ets->tc_tsa[i]) && i > bp->max_tc) 404 return -EINVAL; 405 406 switch (ets->tc_tsa[i]) { 407 case IEEE_8021QAZ_TSA_STRICT: 408 break; 409 case IEEE_8021QAZ_TSA_ETS: 410 total_ets_bw += ets->tc_tx_bw[i]; 411 break; 412 default: 413 return -ENOTSUPP; 414 } 415 } 416 if (total_ets_bw > 100) 417 return -EINVAL; 418 419 *tc = max_tc + 1; 420 return 0; 421 } 422 423 static int bnxt_dcbnl_ieee_getets(struct net_device *dev, struct ieee_ets *ets) 424 { 425 struct bnxt *bp = netdev_priv(dev); 426 struct ieee_ets *my_ets = bp->ieee_ets; 427 428 ets->ets_cap = bp->max_tc; 429 430 if (!my_ets) { 431 int rc; 432 433 if (bp->dcbx_cap & DCB_CAP_DCBX_HOST) 434 return 0; 435 436 my_ets = kzalloc(sizeof(*my_ets), GFP_KERNEL); 437 if (!my_ets) 438 return 0; 439 rc = bnxt_hwrm_queue_cos2bw_qcfg(bp, my_ets); 440 if (rc) 441 return 0; 442 rc = bnxt_hwrm_queue_pri2cos_qcfg(bp, my_ets); 443 if (rc) 444 return 0; 445 } 446 447 ets->cbs = my_ets->cbs; 448 memcpy(ets->tc_tx_bw, my_ets->tc_tx_bw, sizeof(ets->tc_tx_bw)); 449 memcpy(ets->tc_rx_bw, my_ets->tc_rx_bw, sizeof(ets->tc_rx_bw)); 450 memcpy(ets->tc_tsa, my_ets->tc_tsa, sizeof(ets->tc_tsa)); 451 memcpy(ets->prio_tc, my_ets->prio_tc, sizeof(ets->prio_tc)); 452 return 0; 453 } 454 455 static int bnxt_dcbnl_ieee_setets(struct net_device *dev, struct ieee_ets *ets) 456 { 457 struct bnxt *bp = netdev_priv(dev); 458 struct ieee_ets *my_ets = bp->ieee_ets; 459 u8 max_tc = 0; 460 int rc, i; 461 462 if (!(bp->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) || 463 !(bp->dcbx_cap & DCB_CAP_DCBX_HOST)) 464 return -EINVAL; 465 466 rc = bnxt_ets_validate(bp, ets, &max_tc); 467 if (!rc) { 468 if (!my_ets) { 469 my_ets = kzalloc(sizeof(*my_ets), GFP_KERNEL); 470 if (!my_ets) 471 return -ENOMEM; 472 /* initialize PRI2TC mappings to invalid value */ 473 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) 474 my_ets->prio_tc[i] = IEEE_8021QAZ_MAX_TCS; 475 bp->ieee_ets = my_ets; 476 } 477 rc = bnxt_setup_mq_tc(dev, max_tc); 478 if (rc) 479 return rc; 480 rc = bnxt_hwrm_queue_cos2bw_cfg(bp, ets, max_tc); 481 if (rc) 482 return rc; 483 rc = bnxt_hwrm_queue_pri2cos_cfg(bp, ets); 484 if (rc) 485 return rc; 486 memcpy(my_ets, ets, sizeof(*my_ets)); 487 } 488 return rc; 489 } 490 491 static int bnxt_dcbnl_ieee_getpfc(struct net_device *dev, struct ieee_pfc *pfc) 492 { 493 struct bnxt *bp = netdev_priv(dev); 494 __le64 *stats = (__le64 *)bp->hw_rx_port_stats; 495 struct ieee_pfc *my_pfc = bp->ieee_pfc; 496 long rx_off, tx_off; 497 int i, rc; 498 499 pfc->pfc_cap = bp->max_lltc; 500 501 if (!my_pfc) { 502 if (bp->dcbx_cap & DCB_CAP_DCBX_HOST) 503 return 0; 504 505 my_pfc = kzalloc(sizeof(*my_pfc), GFP_KERNEL); 506 if (!my_pfc) 507 return 0; 508 bp->ieee_pfc = my_pfc; 509 rc = bnxt_hwrm_queue_pfc_qcfg(bp, my_pfc); 510 if (rc) 511 return 0; 512 } 513 514 pfc->pfc_en = my_pfc->pfc_en; 515 pfc->mbc = my_pfc->mbc; 516 pfc->delay = my_pfc->delay; 517 518 if (!stats) 519 return 0; 520 521 rx_off = BNXT_RX_STATS_OFFSET(rx_pfc_ena_frames_pri0); 522 tx_off = BNXT_TX_STATS_OFFSET(tx_pfc_ena_frames_pri0); 523 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++, rx_off++, tx_off++) { 524 pfc->requests[i] = le64_to_cpu(*(stats + tx_off)); 525 pfc->indications[i] = le64_to_cpu(*(stats + rx_off)); 526 } 527 528 return 0; 529 } 530 531 static int bnxt_dcbnl_ieee_setpfc(struct net_device *dev, struct ieee_pfc *pfc) 532 { 533 struct bnxt *bp = netdev_priv(dev); 534 struct ieee_pfc *my_pfc = bp->ieee_pfc; 535 int rc; 536 537 if (!(bp->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) || 538 !(bp->dcbx_cap & DCB_CAP_DCBX_HOST)) 539 return -EINVAL; 540 541 if (!my_pfc) { 542 my_pfc = kzalloc(sizeof(*my_pfc), GFP_KERNEL); 543 if (!my_pfc) 544 return -ENOMEM; 545 bp->ieee_pfc = my_pfc; 546 } 547 rc = bnxt_hwrm_queue_pfc_cfg(bp, pfc); 548 if (!rc) 549 memcpy(my_pfc, pfc, sizeof(*my_pfc)); 550 551 return rc; 552 } 553 554 static int bnxt_dcbnl_ieee_setapp(struct net_device *dev, struct dcb_app *app) 555 { 556 struct bnxt *bp = netdev_priv(dev); 557 int rc = -EINVAL; 558 559 if (!(bp->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) || 560 !(bp->dcbx_cap & DCB_CAP_DCBX_HOST)) 561 return -EINVAL; 562 563 rc = dcb_ieee_setapp(dev, app); 564 if (rc) 565 return rc; 566 567 if ((app->selector == IEEE_8021QAZ_APP_SEL_ETHERTYPE && 568 app->protocol == ETH_P_IBOE) || 569 (app->selector == IEEE_8021QAZ_APP_SEL_DGRAM && 570 app->protocol == ROCE_V2_UDP_DPORT)) 571 rc = bnxt_hwrm_set_dcbx_app(bp, app, true); 572 573 return rc; 574 } 575 576 static int bnxt_dcbnl_ieee_delapp(struct net_device *dev, struct dcb_app *app) 577 { 578 struct bnxt *bp = netdev_priv(dev); 579 int rc; 580 581 if (!(bp->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) || 582 !(bp->dcbx_cap & DCB_CAP_DCBX_HOST)) 583 return -EINVAL; 584 585 rc = dcb_ieee_delapp(dev, app); 586 if (rc) 587 return rc; 588 if ((app->selector == IEEE_8021QAZ_APP_SEL_ETHERTYPE && 589 app->protocol == ETH_P_IBOE) || 590 (app->selector == IEEE_8021QAZ_APP_SEL_DGRAM && 591 app->protocol == ROCE_V2_UDP_DPORT)) 592 rc = bnxt_hwrm_set_dcbx_app(bp, app, false); 593 594 return rc; 595 } 596 597 static u8 bnxt_dcbnl_getdcbx(struct net_device *dev) 598 { 599 struct bnxt *bp = netdev_priv(dev); 600 601 return bp->dcbx_cap; 602 } 603 604 static u8 bnxt_dcbnl_setdcbx(struct net_device *dev, u8 mode) 605 { 606 struct bnxt *bp = netdev_priv(dev); 607 608 /* All firmware DCBX settings are set in NVRAM */ 609 if (bp->dcbx_cap & DCB_CAP_DCBX_LLD_MANAGED) 610 return 1; 611 612 if (mode & DCB_CAP_DCBX_HOST) { 613 if (BNXT_VF(bp) || (bp->flags & BNXT_FLAG_FW_LLDP_AGENT)) 614 return 1; 615 616 /* only support IEEE */ 617 if ((mode & DCB_CAP_DCBX_VER_CEE) || 618 !(mode & DCB_CAP_DCBX_VER_IEEE)) 619 return 1; 620 } 621 622 if (mode == bp->dcbx_cap) 623 return 0; 624 625 bp->dcbx_cap = mode; 626 return 0; 627 } 628 629 static const struct dcbnl_rtnl_ops dcbnl_ops = { 630 .ieee_getets = bnxt_dcbnl_ieee_getets, 631 .ieee_setets = bnxt_dcbnl_ieee_setets, 632 .ieee_getpfc = bnxt_dcbnl_ieee_getpfc, 633 .ieee_setpfc = bnxt_dcbnl_ieee_setpfc, 634 .ieee_setapp = bnxt_dcbnl_ieee_setapp, 635 .ieee_delapp = bnxt_dcbnl_ieee_delapp, 636 .getdcbx = bnxt_dcbnl_getdcbx, 637 .setdcbx = bnxt_dcbnl_setdcbx, 638 }; 639 640 void bnxt_dcb_init(struct bnxt *bp) 641 { 642 if (bp->hwrm_spec_code < 0x10501) 643 return; 644 645 bp->dcbx_cap = DCB_CAP_DCBX_VER_IEEE; 646 if (BNXT_PF(bp) && !(bp->flags & BNXT_FLAG_FW_LLDP_AGENT)) 647 bp->dcbx_cap |= DCB_CAP_DCBX_HOST; 648 else if (bp->flags & BNXT_FLAG_FW_DCBX_AGENT) 649 bp->dcbx_cap |= DCB_CAP_DCBX_LLD_MANAGED; 650 bp->dev->dcbnl_ops = &dcbnl_ops; 651 } 652 653 void bnxt_dcb_free(struct bnxt *bp) 654 { 655 kfree(bp->ieee_pfc); 656 kfree(bp->ieee_ets); 657 bp->ieee_pfc = NULL; 658 bp->ieee_ets = NULL; 659 } 660 661 #else 662 663 void bnxt_dcb_init(struct bnxt *bp) 664 { 665 } 666 667 void bnxt_dcb_free(struct bnxt *bp) 668 { 669 } 670 671 #endif 672