xref: /linux/drivers/net/ethernet/broadcom/bnxt/bnxt.h (revision 26fbb4c8c7c3ee9a4c3b4de555a8587b5a19154e)
1 /* Broadcom NetXtreme-C/E network driver.
2  *
3  * Copyright (c) 2014-2016 Broadcom Corporation
4  * Copyright (c) 2016-2018 Broadcom Limited
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation.
9  */
10 
11 #ifndef BNXT_H
12 #define BNXT_H
13 
14 #define DRV_MODULE_NAME		"bnxt_en"
15 
16 /* DO NOT CHANGE DRV_VER_* defines
17  * FIXME: Delete them
18  */
19 #define DRV_VER_MAJ	1
20 #define DRV_VER_MIN	10
21 #define DRV_VER_UPD	1
22 
23 #include <linux/ethtool.h>
24 #include <linux/interrupt.h>
25 #include <linux/rhashtable.h>
26 #include <linux/crash_dump.h>
27 #include <net/devlink.h>
28 #include <net/dst_metadata.h>
29 #include <net/xdp.h>
30 #include <linux/dim.h>
31 #ifdef CONFIG_TEE_BNXT_FW
32 #include <linux/firmware/broadcom/tee_bnxt_fw.h>
33 #endif
34 
35 extern struct list_head bnxt_block_cb_list;
36 
37 struct page_pool;
38 
39 struct tx_bd {
40 	__le32 tx_bd_len_flags_type;
41 	#define TX_BD_TYPE					(0x3f << 0)
42 	 #define TX_BD_TYPE_SHORT_TX_BD				 (0x00 << 0)
43 	 #define TX_BD_TYPE_LONG_TX_BD				 (0x10 << 0)
44 	#define TX_BD_FLAGS_PACKET_END				(1 << 6)
45 	#define TX_BD_FLAGS_NO_CMPL				(1 << 7)
46 	#define TX_BD_FLAGS_BD_CNT				(0x1f << 8)
47 	 #define TX_BD_FLAGS_BD_CNT_SHIFT			 8
48 	#define TX_BD_FLAGS_LHINT				(3 << 13)
49 	 #define TX_BD_FLAGS_LHINT_SHIFT			 13
50 	 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER		 (0 << 13)
51 	 #define TX_BD_FLAGS_LHINT_512_TO_1023			 (1 << 13)
52 	 #define TX_BD_FLAGS_LHINT_1024_TO_2047			 (2 << 13)
53 	 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER		 (3 << 13)
54 	#define TX_BD_FLAGS_COAL_NOW				(1 << 15)
55 	#define TX_BD_LEN					(0xffff << 16)
56 	 #define TX_BD_LEN_SHIFT				 16
57 
58 	u32 tx_bd_opaque;
59 	__le64 tx_bd_haddr;
60 } __packed;
61 
62 struct tx_bd_ext {
63 	__le32 tx_bd_hsize_lflags;
64 	#define TX_BD_FLAGS_TCP_UDP_CHKSUM			(1 << 0)
65 	#define TX_BD_FLAGS_IP_CKSUM				(1 << 1)
66 	#define TX_BD_FLAGS_NO_CRC				(1 << 2)
67 	#define TX_BD_FLAGS_STAMP				(1 << 3)
68 	#define TX_BD_FLAGS_T_IP_CHKSUM				(1 << 4)
69 	#define TX_BD_FLAGS_LSO					(1 << 5)
70 	#define TX_BD_FLAGS_IPID_FMT				(1 << 6)
71 	#define TX_BD_FLAGS_T_IPID				(1 << 7)
72 	#define TX_BD_HSIZE					(0xff << 16)
73 	 #define TX_BD_HSIZE_SHIFT				 16
74 
75 	__le32 tx_bd_mss;
76 	__le32 tx_bd_cfa_action;
77 	#define TX_BD_CFA_ACTION				(0xffff << 16)
78 	 #define TX_BD_CFA_ACTION_SHIFT				 16
79 
80 	__le32 tx_bd_cfa_meta;
81 	#define TX_BD_CFA_META_MASK                             0xfffffff
82 	#define TX_BD_CFA_META_VID_MASK                         0xfff
83 	#define TX_BD_CFA_META_PRI_MASK                         (0xf << 12)
84 	 #define TX_BD_CFA_META_PRI_SHIFT                        12
85 	#define TX_BD_CFA_META_TPID_MASK                        (3 << 16)
86 	 #define TX_BD_CFA_META_TPID_SHIFT                       16
87 	#define TX_BD_CFA_META_KEY                              (0xf << 28)
88 	 #define TX_BD_CFA_META_KEY_SHIFT			 28
89 	#define TX_BD_CFA_META_KEY_VLAN                         (1 << 28)
90 };
91 
92 struct rx_bd {
93 	__le32 rx_bd_len_flags_type;
94 	#define RX_BD_TYPE					(0x3f << 0)
95 	 #define RX_BD_TYPE_RX_PACKET_BD			 0x4
96 	 #define RX_BD_TYPE_RX_BUFFER_BD			 0x5
97 	 #define RX_BD_TYPE_RX_AGG_BD				 0x6
98 	 #define RX_BD_TYPE_16B_BD_SIZE				 (0 << 4)
99 	 #define RX_BD_TYPE_32B_BD_SIZE				 (1 << 4)
100 	 #define RX_BD_TYPE_48B_BD_SIZE				 (2 << 4)
101 	 #define RX_BD_TYPE_64B_BD_SIZE				 (3 << 4)
102 	#define RX_BD_FLAGS_SOP					(1 << 6)
103 	#define RX_BD_FLAGS_EOP					(1 << 7)
104 	#define RX_BD_FLAGS_BUFFERS				(3 << 8)
105 	 #define RX_BD_FLAGS_1_BUFFER_PACKET			 (0 << 8)
106 	 #define RX_BD_FLAGS_2_BUFFER_PACKET			 (1 << 8)
107 	 #define RX_BD_FLAGS_3_BUFFER_PACKET			 (2 << 8)
108 	 #define RX_BD_FLAGS_4_BUFFER_PACKET			 (3 << 8)
109 	#define RX_BD_LEN					(0xffff << 16)
110 	 #define RX_BD_LEN_SHIFT				 16
111 
112 	u32 rx_bd_opaque;
113 	__le64 rx_bd_haddr;
114 };
115 
116 struct tx_cmp {
117 	__le32 tx_cmp_flags_type;
118 	#define CMP_TYPE					(0x3f << 0)
119 	 #define CMP_TYPE_TX_L2_CMP				 0
120 	 #define CMP_TYPE_RX_L2_CMP				 17
121 	 #define CMP_TYPE_RX_AGG_CMP				 18
122 	 #define CMP_TYPE_RX_L2_TPA_START_CMP			 19
123 	 #define CMP_TYPE_RX_L2_TPA_END_CMP			 21
124 	 #define CMP_TYPE_RX_TPA_AGG_CMP			 22
125 	 #define CMP_TYPE_STATUS_CMP				 32
126 	 #define CMP_TYPE_REMOTE_DRIVER_REQ			 34
127 	 #define CMP_TYPE_REMOTE_DRIVER_RESP			 36
128 	 #define CMP_TYPE_ERROR_STATUS				 48
129 	 #define CMPL_BASE_TYPE_STAT_EJECT			 0x1aUL
130 	 #define CMPL_BASE_TYPE_HWRM_DONE			 0x20UL
131 	 #define CMPL_BASE_TYPE_HWRM_FWD_REQ			 0x22UL
132 	 #define CMPL_BASE_TYPE_HWRM_FWD_RESP			 0x24UL
133 	 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT		 0x2eUL
134 
135 	#define TX_CMP_FLAGS_ERROR				(1 << 6)
136 	#define TX_CMP_FLAGS_PUSH				(1 << 7)
137 
138 	u32 tx_cmp_opaque;
139 	__le32 tx_cmp_errors_v;
140 	#define TX_CMP_V					(1 << 0)
141 	#define TX_CMP_ERRORS_BUFFER_ERROR			(7 << 1)
142 	 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR		 0
143 	 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT		 2
144 	 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG	 4
145 	 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS		 5
146 	 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT			 (1 << 4)
147 	 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN			 (1 << 5)
148 	 #define TX_CMP_ERRORS_DMA_ERROR			 (1 << 6)
149 	 #define TX_CMP_ERRORS_HINT_TOO_SHORT			 (1 << 7)
150 
151 	__le32 tx_cmp_unsed_3;
152 };
153 
154 struct rx_cmp {
155 	__le32 rx_cmp_len_flags_type;
156 	#define RX_CMP_CMP_TYPE					(0x3f << 0)
157 	#define RX_CMP_FLAGS_ERROR				(1 << 6)
158 	#define RX_CMP_FLAGS_PLACEMENT				(7 << 7)
159 	#define RX_CMP_FLAGS_RSS_VALID				(1 << 10)
160 	#define RX_CMP_FLAGS_UNUSED				(1 << 11)
161 	 #define RX_CMP_FLAGS_ITYPES_SHIFT			 12
162 	 #define RX_CMP_FLAGS_ITYPE_UNKNOWN			 (0 << 12)
163 	 #define RX_CMP_FLAGS_ITYPE_IP				 (1 << 12)
164 	 #define RX_CMP_FLAGS_ITYPE_TCP				 (2 << 12)
165 	 #define RX_CMP_FLAGS_ITYPE_UDP				 (3 << 12)
166 	 #define RX_CMP_FLAGS_ITYPE_FCOE			 (4 << 12)
167 	 #define RX_CMP_FLAGS_ITYPE_ROCE			 (5 << 12)
168 	 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS			 (8 << 12)
169 	 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS			 (9 << 12)
170 	#define RX_CMP_LEN					(0xffff << 16)
171 	 #define RX_CMP_LEN_SHIFT				 16
172 
173 	u32 rx_cmp_opaque;
174 	__le32 rx_cmp_misc_v1;
175 	#define RX_CMP_V1					(1 << 0)
176 	#define RX_CMP_AGG_BUFS					(0x1f << 1)
177 	 #define RX_CMP_AGG_BUFS_SHIFT				 1
178 	#define RX_CMP_RSS_HASH_TYPE				(0x7f << 9)
179 	 #define RX_CMP_RSS_HASH_TYPE_SHIFT			 9
180 	#define RX_CMP_PAYLOAD_OFFSET				(0xff << 16)
181 	 #define RX_CMP_PAYLOAD_OFFSET_SHIFT			 16
182 
183 	__le32 rx_cmp_rss_hash;
184 };
185 
186 #define RX_CMP_HASH_VALID(rxcmp)				\
187 	((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
188 
189 #define RSS_PROFILE_ID_MASK	0x1f
190 
191 #define RX_CMP_HASH_TYPE(rxcmp)					\
192 	(((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
193 	  RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
194 
195 struct rx_cmp_ext {
196 	__le32 rx_cmp_flags2;
197 	#define RX_CMP_FLAGS2_IP_CS_CALC			0x1
198 	#define RX_CMP_FLAGS2_L4_CS_CALC			(0x1 << 1)
199 	#define RX_CMP_FLAGS2_T_IP_CS_CALC			(0x1 << 2)
200 	#define RX_CMP_FLAGS2_T_L4_CS_CALC			(0x1 << 3)
201 	#define RX_CMP_FLAGS2_META_FORMAT_VLAN			(0x1 << 4)
202 	__le32 rx_cmp_meta_data;
203 	#define RX_CMP_FLAGS2_METADATA_TCI_MASK			0xffff
204 	#define RX_CMP_FLAGS2_METADATA_VID_MASK			0xfff
205 	#define RX_CMP_FLAGS2_METADATA_TPID_MASK		0xffff0000
206 	 #define RX_CMP_FLAGS2_METADATA_TPID_SFT		 16
207 	__le32 rx_cmp_cfa_code_errors_v2;
208 	#define RX_CMP_V					(1 << 0)
209 	#define RX_CMPL_ERRORS_MASK				(0x7fff << 1)
210 	 #define RX_CMPL_ERRORS_SFT				 1
211 	#define RX_CMPL_ERRORS_BUFFER_ERROR_MASK		(0x7 << 1)
212 	 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER		 (0x0 << 1)
213 	 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT	 (0x1 << 1)
214 	 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP	 (0x2 << 1)
215 	 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT		 (0x3 << 1)
216 	#define RX_CMPL_ERRORS_IP_CS_ERROR			(0x1 << 4)
217 	#define RX_CMPL_ERRORS_L4_CS_ERROR			(0x1 << 5)
218 	#define RX_CMPL_ERRORS_T_IP_CS_ERROR			(0x1 << 6)
219 	#define RX_CMPL_ERRORS_T_L4_CS_ERROR			(0x1 << 7)
220 	#define RX_CMPL_ERRORS_CRC_ERROR			(0x1 << 8)
221 	#define RX_CMPL_ERRORS_T_PKT_ERROR_MASK			(0x7 << 9)
222 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR		 (0x0 << 9)
223 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION	 (0x1 << 9)
224 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN	 (0x2 << 9)
225 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR	 (0x3 << 9)
226 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR	 (0x4 << 9)
227 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR	 (0x5 << 9)
228 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL	 (0x6 << 9)
229 	#define RX_CMPL_ERRORS_PKT_ERROR_MASK			(0xf << 12)
230 	 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR		 (0x0 << 12)
231 	 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION	 (0x1 << 12)
232 	 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN	 (0x2 << 12)
233 	 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL		 (0x3 << 12)
234 	 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR	 (0x4 << 12)
235 	 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR	 (0x5 << 12)
236 	 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN	 (0x6 << 12)
237 	 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
238 	 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN	 (0x8 << 12)
239 
240 	#define RX_CMPL_CFA_CODE_MASK				(0xffff << 16)
241 	 #define RX_CMPL_CFA_CODE_SFT				 16
242 
243 	__le32 rx_cmp_unused3;
244 };
245 
246 #define RX_CMP_L2_ERRORS						\
247 	cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
248 
249 #define RX_CMP_L4_CS_BITS						\
250 	(cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
251 
252 #define RX_CMP_L4_CS_ERR_BITS						\
253 	(cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
254 
255 #define RX_CMP_L4_CS_OK(rxcmp1)						\
256 	    (((rxcmp1)->rx_cmp_flags2 &	RX_CMP_L4_CS_BITS) &&		\
257 	     !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
258 
259 #define RX_CMP_ENCAP(rxcmp1)						\
260 	    ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) &			\
261 	     RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
262 
263 #define RX_CMP_CFA_CODE(rxcmpl1)					\
264 	((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) &		\
265 	  RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
266 
267 struct rx_agg_cmp {
268 	__le32 rx_agg_cmp_len_flags_type;
269 	#define RX_AGG_CMP_TYPE					(0x3f << 0)
270 	#define RX_AGG_CMP_LEN					(0xffff << 16)
271 	 #define RX_AGG_CMP_LEN_SHIFT				 16
272 	u32 rx_agg_cmp_opaque;
273 	__le32 rx_agg_cmp_v;
274 	#define RX_AGG_CMP_V					(1 << 0)
275 	#define RX_AGG_CMP_AGG_ID				(0xffff << 16)
276 	 #define RX_AGG_CMP_AGG_ID_SHIFT			 16
277 	__le32 rx_agg_cmp_unused;
278 };
279 
280 #define TPA_AGG_AGG_ID(rx_agg)				\
281 	((le32_to_cpu((rx_agg)->rx_agg_cmp_v) &		\
282 	 RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT)
283 
284 struct rx_tpa_start_cmp {
285 	__le32 rx_tpa_start_cmp_len_flags_type;
286 	#define RX_TPA_START_CMP_TYPE				(0x3f << 0)
287 	#define RX_TPA_START_CMP_FLAGS				(0x3ff << 6)
288 	 #define RX_TPA_START_CMP_FLAGS_SHIFT			 6
289 	#define RX_TPA_START_CMP_FLAGS_ERROR			(0x1 << 6)
290 	#define RX_TPA_START_CMP_FLAGS_PLACEMENT		(0x7 << 7)
291 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT		 7
292 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO		 (0x1 << 7)
293 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS		 (0x2 << 7)
294 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO	 (0x5 << 7)
295 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS	 (0x6 << 7)
296 	#define RX_TPA_START_CMP_FLAGS_RSS_VALID		(0x1 << 10)
297 	#define RX_TPA_START_CMP_FLAGS_TIMESTAMP		(0x1 << 11)
298 	#define RX_TPA_START_CMP_FLAGS_ITYPES			(0xf << 12)
299 	 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT		 12
300 	 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP		 (0x2 << 12)
301 	#define RX_TPA_START_CMP_LEN				(0xffff << 16)
302 	 #define RX_TPA_START_CMP_LEN_SHIFT			 16
303 
304 	u32 rx_tpa_start_cmp_opaque;
305 	__le32 rx_tpa_start_cmp_misc_v1;
306 	#define RX_TPA_START_CMP_V1				(0x1 << 0)
307 	#define RX_TPA_START_CMP_RSS_HASH_TYPE			(0x7f << 9)
308 	 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT		 9
309 	#define RX_TPA_START_CMP_AGG_ID				(0x7f << 25)
310 	 #define RX_TPA_START_CMP_AGG_ID_SHIFT			 25
311 	#define RX_TPA_START_CMP_AGG_ID_P5			(0xffff << 16)
312 	 #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5		 16
313 
314 	__le32 rx_tpa_start_cmp_rss_hash;
315 };
316 
317 #define TPA_START_HASH_VALID(rx_tpa_start)				\
318 	((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &		\
319 	 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
320 
321 #define TPA_START_HASH_TYPE(rx_tpa_start)				\
322 	(((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\
323 	   RX_TPA_START_CMP_RSS_HASH_TYPE) >>				\
324 	  RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
325 
326 #define TPA_START_AGG_ID(rx_tpa_start)					\
327 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\
328 	 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
329 
330 #define TPA_START_AGG_ID_P5(rx_tpa_start)				\
331 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\
332 	 RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5)
333 
334 #define TPA_START_ERROR(rx_tpa_start)					\
335 	((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &		\
336 	 cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))
337 
338 struct rx_tpa_start_cmp_ext {
339 	__le32 rx_tpa_start_cmp_flags2;
340 	#define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC		(0x1 << 0)
341 	#define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC		(0x1 << 1)
342 	#define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC		(0x1 << 2)
343 	#define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC		(0x1 << 3)
344 	#define RX_TPA_START_CMP_FLAGS2_IP_TYPE			(0x1 << 8)
345 	#define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID		(0x1 << 9)
346 	#define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT		(0x3 << 10)
347 	 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT	 10
348 	#define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL		(0xffff << 16)
349 	 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT	 16
350 
351 	__le32 rx_tpa_start_cmp_metadata;
352 	__le32 rx_tpa_start_cmp_cfa_code_v2;
353 	#define RX_TPA_START_CMP_V2				(0x1 << 0)
354 	#define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK	(0x7 << 1)
355 	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT	 1
356 	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER	 (0x0 << 1)
357 	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
358 	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH	 (0x5 << 1)
359 	#define RX_TPA_START_CMP_CFA_CODE			(0xffff << 16)
360 	 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT		 16
361 	__le32 rx_tpa_start_cmp_hdr_info;
362 };
363 
364 #define TPA_START_CFA_CODE(rx_tpa_start)				\
365 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &	\
366 	 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
367 
368 #define TPA_START_IS_IPV6(rx_tpa_start)				\
369 	(!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 &		\
370 	    cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
371 
372 #define TPA_START_ERROR_CODE(rx_tpa_start)				\
373 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &	\
374 	  RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >>			\
375 	 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)
376 
377 struct rx_tpa_end_cmp {
378 	__le32 rx_tpa_end_cmp_len_flags_type;
379 	#define RX_TPA_END_CMP_TYPE				(0x3f << 0)
380 	#define RX_TPA_END_CMP_FLAGS				(0x3ff << 6)
381 	 #define RX_TPA_END_CMP_FLAGS_SHIFT			 6
382 	#define RX_TPA_END_CMP_FLAGS_PLACEMENT			(0x7 << 7)
383 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT		 7
384 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO		 (0x1 << 7)
385 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS		 (0x2 << 7)
386 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO	 (0x5 << 7)
387 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS		 (0x6 << 7)
388 	#define RX_TPA_END_CMP_FLAGS_RSS_VALID			(0x1 << 10)
389 	#define RX_TPA_END_CMP_FLAGS_ITYPES			(0xf << 12)
390 	 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT		 12
391 	 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP			 (0x2 << 12)
392 	#define RX_TPA_END_CMP_LEN				(0xffff << 16)
393 	 #define RX_TPA_END_CMP_LEN_SHIFT			 16
394 
395 	u32 rx_tpa_end_cmp_opaque;
396 	__le32 rx_tpa_end_cmp_misc_v1;
397 	#define RX_TPA_END_CMP_V1				(0x1 << 0)
398 	#define RX_TPA_END_CMP_AGG_BUFS				(0x3f << 1)
399 	 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT			 1
400 	#define RX_TPA_END_CMP_TPA_SEGS				(0xff << 8)
401 	 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT			 8
402 	#define RX_TPA_END_CMP_PAYLOAD_OFFSET			(0xff << 16)
403 	 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT		 16
404 	#define RX_TPA_END_CMP_AGG_ID				(0x7f << 25)
405 	 #define RX_TPA_END_CMP_AGG_ID_SHIFT			 25
406 	#define RX_TPA_END_CMP_AGG_ID_P5			(0xffff << 16)
407 	 #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5			 16
408 
409 	__le32 rx_tpa_end_cmp_tsdelta;
410 	#define RX_TPA_END_GRO_TS				(0x1 << 31)
411 };
412 
413 #define TPA_END_AGG_ID(rx_tpa_end)					\
414 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
415 	 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
416 
417 #define TPA_END_AGG_ID_P5(rx_tpa_end)					\
418 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
419 	 RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5)
420 
421 #define TPA_END_PAYLOAD_OFF(rx_tpa_end)					\
422 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
423 	 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT)
424 
425 #define TPA_END_AGG_BUFS(rx_tpa_end)					\
426 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
427 	 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT)
428 
429 #define TPA_END_TPA_SEGS(rx_tpa_end)					\
430 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
431 	 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
432 
433 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO				\
434 	cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO &		\
435 		    RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
436 
437 #define TPA_END_GRO(rx_tpa_end)						\
438 	((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type &			\
439 	 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
440 
441 #define TPA_END_GRO_TS(rx_tpa_end)					\
442 	(!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta &			\
443 	    cpu_to_le32(RX_TPA_END_GRO_TS)))
444 
445 struct rx_tpa_end_cmp_ext {
446 	__le32 rx_tpa_end_cmp_dup_acks;
447 	#define RX_TPA_END_CMP_TPA_DUP_ACKS			(0xf << 0)
448 	#define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5		(0xff << 16)
449 	 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5		 16
450 	#define RX_TPA_END_CMP_AGG_BUFS_P5			(0xff << 24)
451 	 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5		 24
452 
453 	__le32 rx_tpa_end_cmp_seg_len;
454 	#define RX_TPA_END_CMP_TPA_SEG_LEN			(0xffff << 0)
455 
456 	__le32 rx_tpa_end_cmp_errors_v2;
457 	#define RX_TPA_END_CMP_V2				(0x1 << 0)
458 	#define RX_TPA_END_CMP_ERRORS				(0x3 << 1)
459 	#define RX_TPA_END_CMP_ERRORS_P5			(0x7 << 1)
460 	#define RX_TPA_END_CMPL_ERRORS_SHIFT			 1
461 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER	 (0x0 << 1)
462 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP	 (0x2 << 1)
463 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT	 (0x3 << 1)
464 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR	 (0x4 << 1)
465 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH	 (0x5 << 1)
466 
467 	u32 rx_tpa_end_cmp_start_opaque;
468 };
469 
470 #define TPA_END_ERRORS(rx_tpa_end_ext)					\
471 	((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 &			\
472 	 cpu_to_le32(RX_TPA_END_CMP_ERRORS))
473 
474 #define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext)				\
475 	((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) &	\
476 	 RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >>				\
477 	RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5)
478 
479 #define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext)				\
480 	((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) &	\
481 	 RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5)
482 
483 #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1)				\
484 	(((data1) &							\
485 	  ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
486 	 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL)
487 
488 #define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1)				\
489 	!!((data1) &							\
490 	   ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)
491 
492 #define EVENT_DATA1_RECOVERY_ENABLED(data1)				\
493 	!!((data1) &							\
494 	   ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)
495 
496 struct nqe_cn {
497 	__le16	type;
498 	#define NQ_CN_TYPE_MASK           0x3fUL
499 	#define NQ_CN_TYPE_SFT            0
500 	#define NQ_CN_TYPE_CQ_NOTIFICATION  0x30UL
501 	#define NQ_CN_TYPE_LAST            NQ_CN_TYPE_CQ_NOTIFICATION
502 	__le16	reserved16;
503 	__le32	cq_handle_low;
504 	__le32	v;
505 	#define NQ_CN_V     0x1UL
506 	__le32	cq_handle_high;
507 };
508 
509 #define DB_IDX_MASK						0xffffff
510 #define DB_IDX_VALID						(0x1 << 26)
511 #define DB_IRQ_DIS						(0x1 << 27)
512 #define DB_KEY_TX						(0x0 << 28)
513 #define DB_KEY_RX						(0x1 << 28)
514 #define DB_KEY_CP						(0x2 << 28)
515 #define DB_KEY_ST						(0x3 << 28)
516 #define DB_KEY_TX_PUSH						(0x4 << 28)
517 #define DB_LONG_TX_PUSH						(0x2 << 24)
518 
519 #define BNXT_MIN_ROCE_CP_RINGS	2
520 #define BNXT_MIN_ROCE_STAT_CTXS	1
521 
522 /* 64-bit doorbell */
523 #define DBR_INDEX_MASK					0x0000000000ffffffULL
524 #define DBR_XID_MASK					0x000fffff00000000ULL
525 #define DBR_XID_SFT					32
526 #define DBR_PATH_L2					(0x1ULL << 56)
527 #define DBR_TYPE_SQ					(0x0ULL << 60)
528 #define DBR_TYPE_RQ					(0x1ULL << 60)
529 #define DBR_TYPE_SRQ					(0x2ULL << 60)
530 #define DBR_TYPE_SRQ_ARM				(0x3ULL << 60)
531 #define DBR_TYPE_CQ					(0x4ULL << 60)
532 #define DBR_TYPE_CQ_ARMSE				(0x5ULL << 60)
533 #define DBR_TYPE_CQ_ARMALL				(0x6ULL << 60)
534 #define DBR_TYPE_CQ_ARMENA				(0x7ULL << 60)
535 #define DBR_TYPE_SRQ_ARMENA				(0x8ULL << 60)
536 #define DBR_TYPE_CQ_CUTOFF_ACK				(0x9ULL << 60)
537 #define DBR_TYPE_NQ					(0xaULL << 60)
538 #define DBR_TYPE_NQ_ARM					(0xbULL << 60)
539 #define DBR_TYPE_NULL					(0xfULL << 60)
540 
541 #define DB_PF_OFFSET_P5					0x10000
542 #define DB_VF_OFFSET_P5					0x4000
543 
544 #define INVALID_HW_RING_ID	((u16)-1)
545 
546 /* The hardware supports certain page sizes.  Use the supported page sizes
547  * to allocate the rings.
548  */
549 #if (PAGE_SHIFT < 12)
550 #define BNXT_PAGE_SHIFT	12
551 #elif (PAGE_SHIFT <= 13)
552 #define BNXT_PAGE_SHIFT	PAGE_SHIFT
553 #elif (PAGE_SHIFT < 16)
554 #define BNXT_PAGE_SHIFT	13
555 #else
556 #define BNXT_PAGE_SHIFT	16
557 #endif
558 
559 #define BNXT_PAGE_SIZE	(1 << BNXT_PAGE_SHIFT)
560 
561 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
562 #if (PAGE_SHIFT > 15)
563 #define BNXT_RX_PAGE_SHIFT 15
564 #else
565 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
566 #endif
567 
568 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
569 
570 #define BNXT_MAX_MTU		9500
571 #define BNXT_MAX_PAGE_MODE_MTU	\
572 	((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN -	\
573 	 XDP_PACKET_HEADROOM)
574 
575 #define BNXT_MIN_PKT_SIZE	52
576 
577 #define BNXT_DEFAULT_RX_RING_SIZE	511
578 #define BNXT_DEFAULT_TX_RING_SIZE	511
579 
580 #define MAX_TPA		64
581 #define MAX_TPA_P5	256
582 #define MAX_TPA_P5_MASK	(MAX_TPA_P5 - 1)
583 #define MAX_TPA_SEGS_P5	0x3f
584 
585 #if (BNXT_PAGE_SHIFT == 16)
586 #define MAX_RX_PAGES	1
587 #define MAX_RX_AGG_PAGES	4
588 #define MAX_TX_PAGES	1
589 #define MAX_CP_PAGES	8
590 #else
591 #define MAX_RX_PAGES	8
592 #define MAX_RX_AGG_PAGES	32
593 #define MAX_TX_PAGES	8
594 #define MAX_CP_PAGES	64
595 #endif
596 
597 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
598 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
599 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
600 
601 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
602 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
603 
604 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
605 
606 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
607 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
608 
609 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
610 
611 #define BNXT_MAX_RX_DESC_CNT		(RX_DESC_CNT * MAX_RX_PAGES - 1)
612 #define BNXT_MAX_RX_JUM_DESC_CNT	(RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
613 #define BNXT_MAX_TX_DESC_CNT		(TX_DESC_CNT * MAX_TX_PAGES - 1)
614 
615 #define RX_RING(x)	(((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
616 #define RX_IDX(x)	((x) & (RX_DESC_CNT - 1))
617 
618 #define TX_RING(x)	(((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
619 #define TX_IDX(x)	((x) & (TX_DESC_CNT - 1))
620 
621 #define CP_RING(x)	(((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
622 #define CP_IDX(x)	((x) & (CP_DESC_CNT - 1))
623 
624 #define TX_CMP_VALID(txcmp, raw_cons)					\
625 	(!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) ==	\
626 	 !((raw_cons) & bp->cp_bit))
627 
628 #define RX_CMP_VALID(rxcmp1, raw_cons)					\
629 	(!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
630 	 !((raw_cons) & bp->cp_bit))
631 
632 #define RX_AGG_CMP_VALID(agg, raw_cons)				\
633 	(!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) ==	\
634 	 !((raw_cons) & bp->cp_bit))
635 
636 #define NQ_CMP_VALID(nqcmp, raw_cons)				\
637 	(!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
638 
639 #define TX_CMP_TYPE(txcmp)					\
640 	(le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
641 
642 #define RX_CMP_TYPE(rxcmp)					\
643 	(le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
644 
645 #define NEXT_RX(idx)		(((idx) + 1) & bp->rx_ring_mask)
646 
647 #define NEXT_RX_AGG(idx)	(((idx) + 1) & bp->rx_agg_ring_mask)
648 
649 #define NEXT_TX(idx)		(((idx) + 1) & bp->tx_ring_mask)
650 
651 #define ADV_RAW_CMP(idx, n)	((idx) + (n))
652 #define NEXT_RAW_CMP(idx)	ADV_RAW_CMP(idx, 1)
653 #define RING_CMP(idx)		((idx) & bp->cp_ring_mask)
654 #define NEXT_CMP(idx)		RING_CMP(ADV_RAW_CMP(idx, 1))
655 
656 #define BNXT_HWRM_MAX_REQ_LEN		(bp->hwrm_max_req_len)
657 #define BNXT_HWRM_SHORT_REQ_LEN		sizeof(struct hwrm_short_input)
658 #define DFLT_HWRM_CMD_TIMEOUT		500
659 #define SHORT_HWRM_CMD_TIMEOUT		20
660 #define HWRM_CMD_TIMEOUT		(bp->hwrm_cmd_timeout)
661 #define HWRM_RESET_TIMEOUT		((HWRM_CMD_TIMEOUT) * 4)
662 #define HWRM_COREDUMP_TIMEOUT		((HWRM_CMD_TIMEOUT) * 12)
663 #define BNXT_HWRM_REQ_MAX_SIZE		128
664 #define BNXT_HWRM_REQS_PER_PAGE		(BNXT_PAGE_SIZE /	\
665 					 BNXT_HWRM_REQ_MAX_SIZE)
666 #define HWRM_SHORT_MIN_TIMEOUT		3
667 #define HWRM_SHORT_MAX_TIMEOUT		10
668 #define HWRM_SHORT_TIMEOUT_COUNTER	5
669 
670 #define HWRM_MIN_TIMEOUT		25
671 #define HWRM_MAX_TIMEOUT		40
672 
673 #define HWRM_TOTAL_TIMEOUT(n)	(((n) <= HWRM_SHORT_TIMEOUT_COUNTER) ?	\
674 	((n) * HWRM_SHORT_MIN_TIMEOUT) :				\
675 	(HWRM_SHORT_TIMEOUT_COUNTER * HWRM_SHORT_MIN_TIMEOUT +		\
676 	 ((n) - HWRM_SHORT_TIMEOUT_COUNTER) * HWRM_MIN_TIMEOUT))
677 
678 #define HWRM_VALID_BIT_DELAY_USEC	150
679 
680 #define BNXT_HWRM_CHNL_CHIMP	0
681 #define BNXT_HWRM_CHNL_KONG	1
682 
683 #define BNXT_RX_EVENT		1
684 #define BNXT_AGG_EVENT		2
685 #define BNXT_TX_EVENT		4
686 #define BNXT_REDIRECT_EVENT	8
687 
688 struct bnxt_sw_tx_bd {
689 	union {
690 		struct sk_buff		*skb;
691 		struct xdp_frame	*xdpf;
692 	};
693 	DEFINE_DMA_UNMAP_ADDR(mapping);
694 	DEFINE_DMA_UNMAP_LEN(len);
695 	u8			is_gso;
696 	u8			is_push;
697 	u8			action;
698 	union {
699 		unsigned short		nr_frags;
700 		u16			rx_prod;
701 	};
702 };
703 
704 struct bnxt_sw_rx_bd {
705 	void			*data;
706 	u8			*data_ptr;
707 	dma_addr_t		mapping;
708 };
709 
710 struct bnxt_sw_rx_agg_bd {
711 	struct page		*page;
712 	unsigned int		offset;
713 	dma_addr_t		mapping;
714 };
715 
716 struct bnxt_ring_mem_info {
717 	int			nr_pages;
718 	int			page_size;
719 	u16			flags;
720 #define BNXT_RMEM_VALID_PTE_FLAG	1
721 #define BNXT_RMEM_RING_PTE_FLAG		2
722 #define BNXT_RMEM_USE_FULL_PAGE_FLAG	4
723 
724 	u16			depth;
725 	u8			init_val;
726 
727 	void			**pg_arr;
728 	dma_addr_t		*dma_arr;
729 
730 	__le64			*pg_tbl;
731 	dma_addr_t		pg_tbl_map;
732 
733 	int			vmem_size;
734 	void			**vmem;
735 };
736 
737 struct bnxt_ring_struct {
738 	struct bnxt_ring_mem_info	ring_mem;
739 
740 	u16			fw_ring_id; /* Ring id filled by Chimp FW */
741 	union {
742 		u16		grp_idx;
743 		u16		map_idx; /* Used by cmpl rings */
744 	};
745 	u32			handle;
746 	u8			queue_id;
747 };
748 
749 struct tx_push_bd {
750 	__le32			doorbell;
751 	__le32			tx_bd_len_flags_type;
752 	u32			tx_bd_opaque;
753 	struct tx_bd_ext	txbd2;
754 };
755 
756 struct tx_push_buffer {
757 	struct tx_push_bd	push_bd;
758 	u32			data[25];
759 };
760 
761 struct bnxt_db_info {
762 	void __iomem		*doorbell;
763 	union {
764 		u64		db_key64;
765 		u32		db_key32;
766 	};
767 };
768 
769 struct bnxt_tx_ring_info {
770 	struct bnxt_napi	*bnapi;
771 	u16			tx_prod;
772 	u16			tx_cons;
773 	u16			txq_index;
774 	struct bnxt_db_info	tx_db;
775 
776 	struct tx_bd		*tx_desc_ring[MAX_TX_PAGES];
777 	struct bnxt_sw_tx_bd	*tx_buf_ring;
778 
779 	dma_addr_t		tx_desc_mapping[MAX_TX_PAGES];
780 
781 	struct tx_push_buffer	*tx_push;
782 	dma_addr_t		tx_push_mapping;
783 	__le64			data_mapping;
784 
785 #define BNXT_DEV_STATE_CLOSING	0x1
786 	u32			dev_state;
787 
788 	struct bnxt_ring_struct	tx_ring_struct;
789 };
790 
791 #define BNXT_LEGACY_COAL_CMPL_PARAMS					\
792 	(RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN |		\
793 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX |		\
794 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET |		\
795 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE |			\
796 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR |		\
797 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
798 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR |		\
799 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
800 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
801 
802 #define BNXT_COAL_CMPL_ENABLES						\
803 	(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
804 	 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
805 	 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
806 	 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
807 
808 #define BNXT_COAL_CMPL_MIN_TMR_ENABLE					\
809 	RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
810 
811 #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE			\
812 	RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
813 
814 struct bnxt_coal_cap {
815 	u32			cmpl_params;
816 	u32			nq_params;
817 	u16			num_cmpl_dma_aggr_max;
818 	u16			num_cmpl_dma_aggr_during_int_max;
819 	u16			cmpl_aggr_dma_tmr_max;
820 	u16			cmpl_aggr_dma_tmr_during_int_max;
821 	u16			int_lat_tmr_min_max;
822 	u16			int_lat_tmr_max_max;
823 	u16			num_cmpl_aggr_int_max;
824 	u16			timer_units;
825 };
826 
827 struct bnxt_coal {
828 	u16			coal_ticks;
829 	u16			coal_ticks_irq;
830 	u16			coal_bufs;
831 	u16			coal_bufs_irq;
832 			/* RING_IDLE enabled when coal ticks < idle_thresh  */
833 	u16			idle_thresh;
834 	u8			bufs_per_record;
835 	u8			budget;
836 };
837 
838 struct bnxt_tpa_info {
839 	void			*data;
840 	u8			*data_ptr;
841 	dma_addr_t		mapping;
842 	u16			len;
843 	unsigned short		gso_type;
844 	u32			flags2;
845 	u32			metadata;
846 	enum pkt_hash_types	hash_type;
847 	u32			rss_hash;
848 	u32			hdr_info;
849 
850 #define BNXT_TPA_L4_SIZE(hdr_info)	\
851 	(((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
852 
853 #define BNXT_TPA_INNER_L3_OFF(hdr_info)	\
854 	(((hdr_info) >> 18) & 0x1ff)
855 
856 #define BNXT_TPA_INNER_L2_OFF(hdr_info)	\
857 	(((hdr_info) >> 9) & 0x1ff)
858 
859 #define BNXT_TPA_OUTER_L3_OFF(hdr_info)	\
860 	((hdr_info) & 0x1ff)
861 
862 	u16			cfa_code; /* cfa_code in TPA start compl */
863 	u8			agg_count;
864 	struct rx_agg_cmp	*agg_arr;
865 };
866 
867 #define BNXT_AGG_IDX_BMAP_SIZE	(MAX_TPA_P5 / BITS_PER_LONG)
868 
869 struct bnxt_tpa_idx_map {
870 	u16		agg_id_tbl[1024];
871 	unsigned long	agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];
872 };
873 
874 struct bnxt_rx_ring_info {
875 	struct bnxt_napi	*bnapi;
876 	u16			rx_prod;
877 	u16			rx_agg_prod;
878 	u16			rx_sw_agg_prod;
879 	u16			rx_next_cons;
880 	struct bnxt_db_info	rx_db;
881 	struct bnxt_db_info	rx_agg_db;
882 
883 	struct bpf_prog		*xdp_prog;
884 
885 	struct rx_bd		*rx_desc_ring[MAX_RX_PAGES];
886 	struct bnxt_sw_rx_bd	*rx_buf_ring;
887 
888 	struct rx_bd		*rx_agg_desc_ring[MAX_RX_AGG_PAGES];
889 	struct bnxt_sw_rx_agg_bd	*rx_agg_ring;
890 
891 	unsigned long		*rx_agg_bmap;
892 	u16			rx_agg_bmap_size;
893 
894 	struct page		*rx_page;
895 	unsigned int		rx_page_offset;
896 
897 	dma_addr_t		rx_desc_mapping[MAX_RX_PAGES];
898 	dma_addr_t		rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
899 
900 	struct bnxt_tpa_info	*rx_tpa;
901 	struct bnxt_tpa_idx_map *rx_tpa_idx_map;
902 
903 	struct bnxt_ring_struct	rx_ring_struct;
904 	struct bnxt_ring_struct	rx_agg_ring_struct;
905 	struct xdp_rxq_info	xdp_rxq;
906 	struct page_pool	*page_pool;
907 };
908 
909 struct bnxt_rx_sw_stats {
910 	u64			rx_l4_csum_errors;
911 	u64			rx_resets;
912 	u64			rx_buf_errors;
913 };
914 
915 struct bnxt_cmn_sw_stats {
916 	u64			missed_irqs;
917 };
918 
919 struct bnxt_sw_stats {
920 	struct bnxt_rx_sw_stats rx;
921 	struct bnxt_cmn_sw_stats cmn;
922 };
923 
924 struct bnxt_stats_mem {
925 	u64		*sw_stats;
926 	u64		*hw_masks;
927 	void		*hw_stats;
928 	dma_addr_t	hw_stats_map;
929 	int		len;
930 };
931 
932 struct bnxt_cp_ring_info {
933 	struct bnxt_napi	*bnapi;
934 	u32			cp_raw_cons;
935 	struct bnxt_db_info	cp_db;
936 
937 	u8			had_work_done:1;
938 	u8			has_more_work:1;
939 
940 	u32			last_cp_raw_cons;
941 
942 	struct bnxt_coal	rx_ring_coal;
943 	u64			rx_packets;
944 	u64			rx_bytes;
945 	u64			event_ctr;
946 
947 	struct dim		dim;
948 
949 	union {
950 		struct tx_cmp	*cp_desc_ring[MAX_CP_PAGES];
951 		struct nqe_cn	*nq_desc_ring[MAX_CP_PAGES];
952 	};
953 
954 	dma_addr_t		cp_desc_mapping[MAX_CP_PAGES];
955 
956 	struct bnxt_stats_mem	stats;
957 	u32			hw_stats_ctx_id;
958 
959 	struct bnxt_sw_stats	sw_stats;
960 
961 	struct bnxt_ring_struct	cp_ring_struct;
962 
963 	struct bnxt_cp_ring_info *cp_ring_arr[2];
964 #define BNXT_RX_HDL	0
965 #define BNXT_TX_HDL	1
966 };
967 
968 struct bnxt_napi {
969 	struct napi_struct	napi;
970 	struct bnxt		*bp;
971 
972 	int			index;
973 	struct bnxt_cp_ring_info	cp_ring;
974 	struct bnxt_rx_ring_info	*rx_ring;
975 	struct bnxt_tx_ring_info	*tx_ring;
976 
977 	void			(*tx_int)(struct bnxt *, struct bnxt_napi *,
978 					  int);
979 	int			tx_pkts;
980 	u8			events;
981 
982 	u32			flags;
983 #define BNXT_NAPI_FLAG_XDP	0x1
984 
985 	bool			in_reset;
986 };
987 
988 struct bnxt_irq {
989 	irq_handler_t	handler;
990 	unsigned int	vector;
991 	u8		requested:1;
992 	u8		have_cpumask:1;
993 	char		name[IFNAMSIZ + 2];
994 	cpumask_var_t	cpu_mask;
995 };
996 
997 #define HWRM_RING_ALLOC_TX	0x1
998 #define HWRM_RING_ALLOC_RX	0x2
999 #define HWRM_RING_ALLOC_AGG	0x4
1000 #define HWRM_RING_ALLOC_CMPL	0x8
1001 #define HWRM_RING_ALLOC_NQ	0x10
1002 
1003 #define INVALID_STATS_CTX_ID	-1
1004 
1005 struct bnxt_ring_grp_info {
1006 	u16	fw_stats_ctx;
1007 	u16	fw_grp_id;
1008 	u16	rx_fw_ring_id;
1009 	u16	agg_fw_ring_id;
1010 	u16	cp_fw_ring_id;
1011 };
1012 
1013 struct bnxt_vnic_info {
1014 	u16		fw_vnic_id; /* returned by Chimp during alloc */
1015 #define BNXT_MAX_CTX_PER_VNIC	8
1016 	u16		fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
1017 	u16		fw_l2_ctx_id;
1018 #define BNXT_MAX_UC_ADDRS	4
1019 	__le64		fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
1020 				/* index 0 always dev_addr */
1021 	u16		uc_filter_count;
1022 	u8		*uc_list;
1023 
1024 	u16		*fw_grp_ids;
1025 	dma_addr_t	rss_table_dma_addr;
1026 	__le16		*rss_table;
1027 	dma_addr_t	rss_hash_key_dma_addr;
1028 	u64		*rss_hash_key;
1029 	int		rss_table_size;
1030 #define BNXT_RSS_TABLE_ENTRIES_P5	64
1031 #define BNXT_RSS_TABLE_SIZE_P5		(BNXT_RSS_TABLE_ENTRIES_P5 * 4)
1032 #define BNXT_RSS_TABLE_MAX_TBL_P5	8
1033 #define BNXT_MAX_RSS_TABLE_SIZE_P5				\
1034 	(BNXT_RSS_TABLE_SIZE_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1035 #define BNXT_MAX_RSS_TABLE_ENTRIES_P5				\
1036 	(BNXT_RSS_TABLE_ENTRIES_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1037 
1038 	u32		rx_mask;
1039 
1040 	u8		*mc_list;
1041 	int		mc_list_size;
1042 	int		mc_list_count;
1043 	dma_addr_t	mc_list_mapping;
1044 #define BNXT_MAX_MC_ADDRS	16
1045 
1046 	u32		flags;
1047 #define BNXT_VNIC_RSS_FLAG	1
1048 #define BNXT_VNIC_RFS_FLAG	2
1049 #define BNXT_VNIC_MCAST_FLAG	4
1050 #define BNXT_VNIC_UCAST_FLAG	8
1051 #define BNXT_VNIC_RFS_NEW_RSS_FLAG	0x10
1052 };
1053 
1054 struct bnxt_hw_resc {
1055 	u16	min_rsscos_ctxs;
1056 	u16	max_rsscos_ctxs;
1057 	u16	min_cp_rings;
1058 	u16	max_cp_rings;
1059 	u16	resv_cp_rings;
1060 	u16	min_tx_rings;
1061 	u16	max_tx_rings;
1062 	u16	resv_tx_rings;
1063 	u16	max_tx_sch_inputs;
1064 	u16	min_rx_rings;
1065 	u16	max_rx_rings;
1066 	u16	resv_rx_rings;
1067 	u16	min_hw_ring_grps;
1068 	u16	max_hw_ring_grps;
1069 	u16	resv_hw_ring_grps;
1070 	u16	min_l2_ctxs;
1071 	u16	max_l2_ctxs;
1072 	u16	min_vnics;
1073 	u16	max_vnics;
1074 	u16	resv_vnics;
1075 	u16	min_stat_ctxs;
1076 	u16	max_stat_ctxs;
1077 	u16	resv_stat_ctxs;
1078 	u16	max_nqs;
1079 	u16	max_irqs;
1080 	u16	resv_irqs;
1081 };
1082 
1083 #if defined(CONFIG_BNXT_SRIOV)
1084 struct bnxt_vf_info {
1085 	u16	fw_fid;
1086 	u8	mac_addr[ETH_ALEN];	/* PF assigned MAC Address */
1087 	u8	vf_mac_addr[ETH_ALEN];	/* VF assigned MAC address, only
1088 					 * stored by PF.
1089 					 */
1090 	u16	vlan;
1091 	u16	func_qcfg_flags;
1092 	u32	flags;
1093 #define BNXT_VF_QOS		0x1
1094 #define BNXT_VF_SPOOFCHK	0x2
1095 #define BNXT_VF_LINK_FORCED	0x4
1096 #define BNXT_VF_LINK_UP		0x8
1097 #define BNXT_VF_TRUST		0x10
1098 	u32	min_tx_rate;
1099 	u32	max_tx_rate;
1100 	void	*hwrm_cmd_req_addr;
1101 	dma_addr_t	hwrm_cmd_req_dma_addr;
1102 };
1103 #endif
1104 
1105 struct bnxt_pf_info {
1106 #define BNXT_FIRST_PF_FID	1
1107 #define BNXT_FIRST_VF_FID	128
1108 	u16	fw_fid;
1109 	u16	port_id;
1110 	u8	mac_addr[ETH_ALEN];
1111 	u32	first_vf_id;
1112 	u16	active_vfs;
1113 	u16	registered_vfs;
1114 	u16	max_vfs;
1115 	u32	max_encap_records;
1116 	u32	max_decap_records;
1117 	u32	max_tx_em_flows;
1118 	u32	max_tx_wm_flows;
1119 	u32	max_rx_em_flows;
1120 	u32	max_rx_wm_flows;
1121 	unsigned long	*vf_event_bmap;
1122 	u16	hwrm_cmd_req_pages;
1123 	u8	vf_resv_strategy;
1124 #define BNXT_VF_RESV_STRATEGY_MAXIMAL	0
1125 #define BNXT_VF_RESV_STRATEGY_MINIMAL	1
1126 #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC	2
1127 	void			*hwrm_cmd_req_addr[4];
1128 	dma_addr_t		hwrm_cmd_req_dma_addr[4];
1129 	struct bnxt_vf_info	*vf;
1130 };
1131 
1132 struct bnxt_ntuple_filter {
1133 	struct hlist_node	hash;
1134 	u8			dst_mac_addr[ETH_ALEN];
1135 	u8			src_mac_addr[ETH_ALEN];
1136 	struct flow_keys	fkeys;
1137 	__le64			filter_id;
1138 	u16			sw_id;
1139 	u8			l2_fltr_idx;
1140 	u16			rxq;
1141 	u32			flow_id;
1142 	unsigned long		state;
1143 #define BNXT_FLTR_VALID		0
1144 #define BNXT_FLTR_UPDATE	1
1145 };
1146 
1147 struct bnxt_link_info {
1148 	u8			phy_type;
1149 	u8			media_type;
1150 	u8			transceiver;
1151 	u8			phy_addr;
1152 	u8			phy_link_status;
1153 #define BNXT_LINK_NO_LINK	PORT_PHY_QCFG_RESP_LINK_NO_LINK
1154 #define BNXT_LINK_SIGNAL	PORT_PHY_QCFG_RESP_LINK_SIGNAL
1155 #define BNXT_LINK_LINK		PORT_PHY_QCFG_RESP_LINK_LINK
1156 	u8			wire_speed;
1157 	u8			phy_state;
1158 #define BNXT_PHY_STATE_ENABLED		0
1159 #define BNXT_PHY_STATE_DISABLED		1
1160 
1161 	u8			link_up;
1162 	u8			duplex;
1163 #define BNXT_LINK_DUPLEX_HALF	PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1164 #define BNXT_LINK_DUPLEX_FULL	PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1165 	u8			pause;
1166 #define BNXT_LINK_PAUSE_TX	PORT_PHY_QCFG_RESP_PAUSE_TX
1167 #define BNXT_LINK_PAUSE_RX	PORT_PHY_QCFG_RESP_PAUSE_RX
1168 #define BNXT_LINK_PAUSE_BOTH	(PORT_PHY_QCFG_RESP_PAUSE_RX | \
1169 				 PORT_PHY_QCFG_RESP_PAUSE_TX)
1170 	u8			lp_pause;
1171 	u8			auto_pause_setting;
1172 	u8			force_pause_setting;
1173 	u8			duplex_setting;
1174 	u8			auto_mode;
1175 #define BNXT_AUTO_MODE(mode)	((mode) > BNXT_LINK_AUTO_NONE && \
1176 				 (mode) <= BNXT_LINK_AUTO_MSK)
1177 #define BNXT_LINK_AUTO_NONE     PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1178 #define BNXT_LINK_AUTO_ALLSPDS	PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1179 #define BNXT_LINK_AUTO_ONESPD	PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1180 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1181 #define BNXT_LINK_AUTO_MSK	PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1182 #define PHY_VER_LEN		3
1183 	u8			phy_ver[PHY_VER_LEN];
1184 	u16			link_speed;
1185 #define BNXT_LINK_SPEED_100MB	PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1186 #define BNXT_LINK_SPEED_1GB	PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1187 #define BNXT_LINK_SPEED_2GB	PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1188 #define BNXT_LINK_SPEED_2_5GB	PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1189 #define BNXT_LINK_SPEED_10GB	PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1190 #define BNXT_LINK_SPEED_20GB	PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1191 #define BNXT_LINK_SPEED_25GB	PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1192 #define BNXT_LINK_SPEED_40GB	PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1193 #define BNXT_LINK_SPEED_50GB	PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1194 #define BNXT_LINK_SPEED_100GB	PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1195 	u16			support_speeds;
1196 	u16			support_pam4_speeds;
1197 	u16			auto_link_speeds;	/* fw adv setting */
1198 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1199 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1200 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1201 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1202 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1203 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1204 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1205 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1206 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1207 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1208 	u16			auto_pam4_link_speeds;
1209 #define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G
1210 #define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G
1211 #define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G
1212 	u16			support_auto_speeds;
1213 	u16			support_pam4_auto_speeds;
1214 	u16			lp_auto_link_speeds;
1215 	u16			lp_auto_pam4_link_speeds;
1216 	u16			force_link_speed;
1217 	u16			force_pam4_link_speed;
1218 	u32			preemphasis;
1219 	u8			module_status;
1220 	u8			active_fec_sig_mode;
1221 	u16			fec_cfg;
1222 #define BNXT_FEC_NONE		PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
1223 #define BNXT_FEC_AUTONEG_CAP	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED
1224 #define BNXT_FEC_AUTONEG	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1225 #define BNXT_FEC_ENC_BASE_R_CAP	\
1226 	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED
1227 #define BNXT_FEC_ENC_BASE_R	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1228 #define BNXT_FEC_ENC_RS_CAP	\
1229 	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED
1230 #define BNXT_FEC_ENC_LLRS_CAP	\
1231 	(PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED |	\
1232 	 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED)
1233 #define BNXT_FEC_ENC_RS		\
1234 	(PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED |	\
1235 	 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED |	\
1236 	 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED)
1237 #define BNXT_FEC_ENC_LLRS	\
1238 	(PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED |	\
1239 	 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED)
1240 
1241 	/* copy of requested setting from ethtool cmd */
1242 	u8			autoneg;
1243 #define BNXT_AUTONEG_SPEED		1
1244 #define BNXT_AUTONEG_FLOW_CTRL		2
1245 	u8			req_signal_mode;
1246 #define BNXT_SIG_MODE_NRZ	PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ
1247 #define BNXT_SIG_MODE_PAM4	PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
1248 	u8			req_duplex;
1249 	u8			req_flow_ctrl;
1250 	u16			req_link_speed;
1251 	u16			advertising;	/* user adv setting */
1252 	u16			advertising_pam4;
1253 	bool			force_link_chng;
1254 
1255 	bool			phy_retry;
1256 	unsigned long		phy_retry_expires;
1257 
1258 	/* a copy of phy_qcfg output used to report link
1259 	 * info to VF
1260 	 */
1261 	struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1262 };
1263 
1264 #define BNXT_FEC_RS544_ON					\
1265 	 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE |		\
1266 	  PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE)
1267 
1268 #define BNXT_FEC_RS544_OFF					\
1269 	 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE |	\
1270 	  PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE)
1271 
1272 #define BNXT_FEC_RS272_ON					\
1273 	 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE |		\
1274 	  PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE)
1275 
1276 #define BNXT_FEC_RS272_OFF					\
1277 	 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE |	\
1278 	  PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE)
1279 
1280 #define BNXT_PAM4_SUPPORTED(link_info)				\
1281 	((link_info)->support_pam4_speeds)
1282 
1283 #define BNXT_FEC_RS_ON(link_info)				\
1284 	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE |		\
1285 	 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |		\
1286 	 (BNXT_PAM4_SUPPORTED(link_info) ?			\
1287 	  (BNXT_FEC_RS544_ON | BNXT_FEC_RS272_OFF) : 0))
1288 
1289 #define BNXT_FEC_LLRS_ON					\
1290 	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE |		\
1291 	 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |		\
1292 	 BNXT_FEC_RS272_ON | BNXT_FEC_RS544_OFF)
1293 
1294 #define BNXT_FEC_RS_OFF(link_info)				\
1295 	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE |		\
1296 	 (BNXT_PAM4_SUPPORTED(link_info) ?			\
1297 	  (BNXT_FEC_RS544_OFF | BNXT_FEC_RS272_OFF) : 0))
1298 
1299 #define BNXT_FEC_BASE_R_ON(link_info)				\
1300 	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE |		\
1301 	 BNXT_FEC_RS_OFF(link_info))
1302 
1303 #define BNXT_FEC_ALL_OFF(link_info)				\
1304 	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |		\
1305 	 BNXT_FEC_RS_OFF(link_info))
1306 
1307 #define BNXT_MAX_QUEUE	8
1308 
1309 struct bnxt_queue_info {
1310 	u8	queue_id;
1311 	u8	queue_profile;
1312 };
1313 
1314 #define BNXT_MAX_LED			4
1315 
1316 struct bnxt_led_info {
1317 	u8	led_id;
1318 	u8	led_type;
1319 	u8	led_group_id;
1320 	u8	unused;
1321 	__le16	led_state_caps;
1322 #define BNXT_LED_ALT_BLINK_CAP(x)	((x) &	\
1323 	cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1324 
1325 	__le16	led_color_caps;
1326 };
1327 
1328 #define BNXT_MAX_TEST	8
1329 
1330 struct bnxt_test_info {
1331 	u8 offline_mask;
1332 	u8 flags;
1333 #define BNXT_TEST_FL_EXT_LPBK		0x1
1334 #define BNXT_TEST_FL_AN_PHY_LPBK	0x2
1335 	u16 timeout;
1336 	char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1337 };
1338 
1339 #define CHIMP_REG_VIEW_ADDR				\
1340 	((bp->flags & BNXT_FLAG_CHIP_P5) ? 0x80000000 : 0xb1000000)
1341 
1342 #define BNXT_GRCPF_REG_CHIMP_COMM		0x0
1343 #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER	0x100
1344 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT		0x400
1345 #define BNXT_CAG_REG_LEGACY_INT_STATUS		0x4014
1346 #define BNXT_CAG_REG_BASE			0x300000
1347 
1348 #define BNXT_GRCPF_REG_KONG_COMM		0xA00
1349 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER	0xB00
1350 
1351 #define BNXT_GRC_BASE_MASK			0xfffff000
1352 #define BNXT_GRC_OFFSET_MASK			0x00000ffc
1353 
1354 struct bnxt_tc_flow_stats {
1355 	u64		packets;
1356 	u64		bytes;
1357 };
1358 
1359 #ifdef CONFIG_BNXT_FLOWER_OFFLOAD
1360 struct bnxt_flower_indr_block_cb_priv {
1361 	struct net_device *tunnel_netdev;
1362 	struct bnxt *bp;
1363 	struct list_head list;
1364 };
1365 #endif
1366 
1367 struct bnxt_tc_info {
1368 	bool				enabled;
1369 
1370 	/* hash table to store TC offloaded flows */
1371 	struct rhashtable		flow_table;
1372 	struct rhashtable_params	flow_ht_params;
1373 
1374 	/* hash table to store L2 keys of TC flows */
1375 	struct rhashtable		l2_table;
1376 	struct rhashtable_params	l2_ht_params;
1377 	/* hash table to store L2 keys for TC tunnel decap */
1378 	struct rhashtable		decap_l2_table;
1379 	struct rhashtable_params	decap_l2_ht_params;
1380 	/* hash table to store tunnel decap entries */
1381 	struct rhashtable		decap_table;
1382 	struct rhashtable_params	decap_ht_params;
1383 	/* hash table to store tunnel encap entries */
1384 	struct rhashtable		encap_table;
1385 	struct rhashtable_params	encap_ht_params;
1386 
1387 	/* lock to atomically add/del an l2 node when a flow is
1388 	 * added or deleted.
1389 	 */
1390 	struct mutex			lock;
1391 
1392 	/* Fields used for batching stats query */
1393 	struct rhashtable_iter		iter;
1394 #define BNXT_FLOW_STATS_BATCH_MAX	10
1395 	struct bnxt_tc_stats_batch {
1396 		void			  *flow_node;
1397 		struct bnxt_tc_flow_stats hw_stats;
1398 	} stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1399 
1400 	/* Stat counter mask (width) */
1401 	u64				bytes_mask;
1402 	u64				packets_mask;
1403 };
1404 
1405 struct bnxt_vf_rep_stats {
1406 	u64			packets;
1407 	u64			bytes;
1408 	u64			dropped;
1409 };
1410 
1411 struct bnxt_vf_rep {
1412 	struct bnxt			*bp;
1413 	struct net_device		*dev;
1414 	struct metadata_dst		*dst;
1415 	u16				vf_idx;
1416 	u16				tx_cfa_action;
1417 	u16				rx_cfa_code;
1418 
1419 	struct bnxt_vf_rep_stats	rx_stats;
1420 	struct bnxt_vf_rep_stats	tx_stats;
1421 };
1422 
1423 #define PTU_PTE_VALID             0x1UL
1424 #define PTU_PTE_LAST              0x2UL
1425 #define PTU_PTE_NEXT_TO_LAST      0x4UL
1426 
1427 #define MAX_CTX_PAGES	(BNXT_PAGE_SIZE / 8)
1428 #define MAX_CTX_TOTAL_PAGES	(MAX_CTX_PAGES * MAX_CTX_PAGES)
1429 
1430 struct bnxt_ctx_pg_info {
1431 	u32		entries;
1432 	u32		nr_pages;
1433 	void		*ctx_pg_arr[MAX_CTX_PAGES];
1434 	dma_addr_t	ctx_dma_arr[MAX_CTX_PAGES];
1435 	struct bnxt_ring_mem_info ring_mem;
1436 	struct bnxt_ctx_pg_info **ctx_pg_tbl;
1437 };
1438 
1439 #define BNXT_MAX_TQM_SP_RINGS		1
1440 #define BNXT_MAX_TQM_FP_RINGS		8
1441 #define BNXT_MAX_TQM_RINGS		\
1442 	(BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)
1443 
1444 struct bnxt_ctx_mem_info {
1445 	u32	qp_max_entries;
1446 	u16	qp_min_qp1_entries;
1447 	u16	qp_max_l2_entries;
1448 	u16	qp_entry_size;
1449 	u16	srq_max_l2_entries;
1450 	u32	srq_max_entries;
1451 	u16	srq_entry_size;
1452 	u16	cq_max_l2_entries;
1453 	u32	cq_max_entries;
1454 	u16	cq_entry_size;
1455 	u16	vnic_max_vnic_entries;
1456 	u16	vnic_max_ring_table_entries;
1457 	u16	vnic_entry_size;
1458 	u32	stat_max_entries;
1459 	u16	stat_entry_size;
1460 	u16	tqm_entry_size;
1461 	u32	tqm_min_entries_per_ring;
1462 	u32	tqm_max_entries_per_ring;
1463 	u32	mrav_max_entries;
1464 	u16	mrav_entry_size;
1465 	u16	tim_entry_size;
1466 	u32	tim_max_entries;
1467 	u16	mrav_num_entries_units;
1468 	u8	tqm_entries_multiple;
1469 	u8	ctx_kind_initializer;
1470 	u8	tqm_fp_rings_count;
1471 
1472 	u32	flags;
1473 	#define BNXT_CTX_FLAG_INITED	0x01
1474 
1475 	struct bnxt_ctx_pg_info qp_mem;
1476 	struct bnxt_ctx_pg_info srq_mem;
1477 	struct bnxt_ctx_pg_info cq_mem;
1478 	struct bnxt_ctx_pg_info vnic_mem;
1479 	struct bnxt_ctx_pg_info stat_mem;
1480 	struct bnxt_ctx_pg_info mrav_mem;
1481 	struct bnxt_ctx_pg_info tim_mem;
1482 	struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TQM_RINGS];
1483 };
1484 
1485 struct bnxt_fw_health {
1486 	u32 flags;
1487 	u32 polling_dsecs;
1488 	u32 master_func_wait_dsecs;
1489 	u32 normal_func_wait_dsecs;
1490 	u32 post_reset_wait_dsecs;
1491 	u32 post_reset_max_wait_dsecs;
1492 	u32 regs[4];
1493 	u32 mapped_regs[4];
1494 #define BNXT_FW_HEALTH_REG		0
1495 #define BNXT_FW_HEARTBEAT_REG		1
1496 #define BNXT_FW_RESET_CNT_REG		2
1497 #define BNXT_FW_RESET_INPROG_REG	3
1498 	u32 fw_reset_inprog_reg_mask;
1499 	u32 last_fw_heartbeat;
1500 	u32 last_fw_reset_cnt;
1501 	u8 enabled:1;
1502 	u8 master:1;
1503 	u8 fatal:1;
1504 	u8 status_reliable:1;
1505 	u8 tmr_multiplier;
1506 	u8 tmr_counter;
1507 	u8 fw_reset_seq_cnt;
1508 	u32 fw_reset_seq_regs[16];
1509 	u32 fw_reset_seq_vals[16];
1510 	u32 fw_reset_seq_delay_msec[16];
1511 	struct devlink_health_reporter	*fw_reporter;
1512 	struct devlink_health_reporter *fw_reset_reporter;
1513 	struct devlink_health_reporter *fw_fatal_reporter;
1514 };
1515 
1516 struct bnxt_fw_reporter_ctx {
1517 	unsigned long sp_event;
1518 };
1519 
1520 #define BNXT_FW_HEALTH_REG_TYPE_MASK	3
1521 #define BNXT_FW_HEALTH_REG_TYPE_CFG	0
1522 #define BNXT_FW_HEALTH_REG_TYPE_GRC	1
1523 #define BNXT_FW_HEALTH_REG_TYPE_BAR0	2
1524 #define BNXT_FW_HEALTH_REG_TYPE_BAR1	3
1525 
1526 #define BNXT_FW_HEALTH_REG_TYPE(reg)	((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)
1527 #define BNXT_FW_HEALTH_REG_OFF(reg)	((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)
1528 
1529 #define BNXT_FW_HEALTH_WIN_BASE		0x3000
1530 #define BNXT_FW_HEALTH_WIN_MAP_OFF	8
1531 
1532 #define BNXT_FW_HEALTH_WIN_OFF(reg)	(BNXT_FW_HEALTH_WIN_BASE +	\
1533 					 ((reg) & BNXT_GRC_OFFSET_MASK))
1534 
1535 #define BNXT_FW_STATUS_HEALTHY		0x8000
1536 #define BNXT_FW_STATUS_SHUTDOWN		0x100000
1537 
1538 struct bnxt {
1539 	void __iomem		*bar0;
1540 	void __iomem		*bar1;
1541 	void __iomem		*bar2;
1542 
1543 	u32			reg_base;
1544 	u16			chip_num;
1545 #define CHIP_NUM_57301		0x16c8
1546 #define CHIP_NUM_57302		0x16c9
1547 #define CHIP_NUM_57304		0x16ca
1548 #define CHIP_NUM_58700		0x16cd
1549 #define CHIP_NUM_57402		0x16d0
1550 #define CHIP_NUM_57404		0x16d1
1551 #define CHIP_NUM_57406		0x16d2
1552 #define CHIP_NUM_57407		0x16d5
1553 
1554 #define CHIP_NUM_57311		0x16ce
1555 #define CHIP_NUM_57312		0x16cf
1556 #define CHIP_NUM_57314		0x16df
1557 #define CHIP_NUM_57317		0x16e0
1558 #define CHIP_NUM_57412		0x16d6
1559 #define CHIP_NUM_57414		0x16d7
1560 #define CHIP_NUM_57416		0x16d8
1561 #define CHIP_NUM_57417		0x16d9
1562 #define CHIP_NUM_57412L		0x16da
1563 #define CHIP_NUM_57414L		0x16db
1564 
1565 #define CHIP_NUM_5745X		0xd730
1566 #define CHIP_NUM_57452		0xc452
1567 #define CHIP_NUM_57454		0xc454
1568 
1569 #define CHIP_NUM_57508		0x1750
1570 #define CHIP_NUM_57504		0x1751
1571 #define CHIP_NUM_57502		0x1752
1572 
1573 #define CHIP_NUM_58802		0xd802
1574 #define CHIP_NUM_58804		0xd804
1575 #define CHIP_NUM_58808		0xd808
1576 
1577 	u8			chip_rev;
1578 
1579 #define CHIP_NUM_58818		0xd818
1580 
1581 #define BNXT_CHIP_NUM_5730X(chip_num)		\
1582 	((chip_num) >= CHIP_NUM_57301 &&	\
1583 	 (chip_num) <= CHIP_NUM_57304)
1584 
1585 #define BNXT_CHIP_NUM_5740X(chip_num)		\
1586 	(((chip_num) >= CHIP_NUM_57402 &&	\
1587 	  (chip_num) <= CHIP_NUM_57406) ||	\
1588 	 (chip_num) == CHIP_NUM_57407)
1589 
1590 #define BNXT_CHIP_NUM_5731X(chip_num)		\
1591 	((chip_num) == CHIP_NUM_57311 ||	\
1592 	 (chip_num) == CHIP_NUM_57312 ||	\
1593 	 (chip_num) == CHIP_NUM_57314 ||	\
1594 	 (chip_num) == CHIP_NUM_57317)
1595 
1596 #define BNXT_CHIP_NUM_5741X(chip_num)		\
1597 	((chip_num) >= CHIP_NUM_57412 &&	\
1598 	 (chip_num) <= CHIP_NUM_57414L)
1599 
1600 #define BNXT_CHIP_NUM_58700(chip_num)		\
1601 	 ((chip_num) == CHIP_NUM_58700)
1602 
1603 #define BNXT_CHIP_NUM_5745X(chip_num)		\
1604 	((chip_num) == CHIP_NUM_5745X ||	\
1605 	 (chip_num) == CHIP_NUM_57452 ||	\
1606 	 (chip_num) == CHIP_NUM_57454)
1607 
1608 
1609 #define BNXT_CHIP_NUM_57X0X(chip_num)		\
1610 	(BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
1611 
1612 #define BNXT_CHIP_NUM_57X1X(chip_num)		\
1613 	(BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
1614 
1615 #define BNXT_CHIP_NUM_588XX(chip_num)		\
1616 	((chip_num) == CHIP_NUM_58802 ||	\
1617 	 (chip_num) == CHIP_NUM_58804 ||        \
1618 	 (chip_num) == CHIP_NUM_58808)
1619 
1620 #define BNXT_VPD_FLD_LEN	32
1621 	char			board_partno[BNXT_VPD_FLD_LEN];
1622 	char			board_serialno[BNXT_VPD_FLD_LEN];
1623 
1624 	struct net_device	*dev;
1625 	struct pci_dev		*pdev;
1626 
1627 	atomic_t		intr_sem;
1628 
1629 	u32			flags;
1630 	#define BNXT_FLAG_CHIP_P5	0x1
1631 	#define BNXT_FLAG_VF		0x2
1632 	#define BNXT_FLAG_LRO		0x4
1633 #ifdef CONFIG_INET
1634 	#define BNXT_FLAG_GRO		0x8
1635 #else
1636 	/* Cannot support hardware GRO if CONFIG_INET is not set */
1637 	#define BNXT_FLAG_GRO		0x0
1638 #endif
1639 	#define BNXT_FLAG_TPA		(BNXT_FLAG_LRO | BNXT_FLAG_GRO)
1640 	#define BNXT_FLAG_JUMBO		0x10
1641 	#define BNXT_FLAG_STRIP_VLAN	0x20
1642 	#define BNXT_FLAG_AGG_RINGS	(BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
1643 					 BNXT_FLAG_LRO)
1644 	#define BNXT_FLAG_USING_MSIX	0x40
1645 	#define BNXT_FLAG_MSIX_CAP	0x80
1646 	#define BNXT_FLAG_RFS		0x100
1647 	#define BNXT_FLAG_SHARED_RINGS	0x200
1648 	#define BNXT_FLAG_PORT_STATS	0x400
1649 	#define BNXT_FLAG_UDP_RSS_CAP	0x800
1650 	#define BNXT_FLAG_EEE_CAP	0x1000
1651 	#define BNXT_FLAG_NEW_RSS_CAP	0x2000
1652 	#define BNXT_FLAG_WOL_CAP	0x4000
1653 	#define BNXT_FLAG_ROCEV1_CAP	0x8000
1654 	#define BNXT_FLAG_ROCEV2_CAP	0x10000
1655 	#define BNXT_FLAG_ROCE_CAP	(BNXT_FLAG_ROCEV1_CAP |	\
1656 					 BNXT_FLAG_ROCEV2_CAP)
1657 	#define BNXT_FLAG_NO_AGG_RINGS	0x20000
1658 	#define BNXT_FLAG_RX_PAGE_MODE	0x40000
1659 	#define BNXT_FLAG_CHIP_SR2	0x80000
1660 	#define BNXT_FLAG_MULTI_HOST	0x100000
1661 	#define BNXT_FLAG_DSN_VALID	0x200000
1662 	#define BNXT_FLAG_DOUBLE_DB	0x400000
1663 	#define BNXT_FLAG_CHIP_NITRO_A0	0x1000000
1664 	#define BNXT_FLAG_DIM		0x2000000
1665 	#define BNXT_FLAG_ROCE_MIRROR_CAP	0x4000000
1666 	#define BNXT_FLAG_PORT_STATS_EXT	0x10000000
1667 
1668 	#define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA |		\
1669 					    BNXT_FLAG_RFS |		\
1670 					    BNXT_FLAG_STRIP_VLAN)
1671 
1672 #define BNXT_PF(bp)		(!((bp)->flags & BNXT_FLAG_VF))
1673 #define BNXT_VF(bp)		((bp)->flags & BNXT_FLAG_VF)
1674 #define BNXT_NPAR(bp)		((bp)->port_partition_type)
1675 #define BNXT_MH(bp)		((bp)->flags & BNXT_FLAG_MULTI_HOST)
1676 #define BNXT_SINGLE_PF(bp)	(BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
1677 #define BNXT_PHY_CFG_ABLE(bp)	((BNXT_SINGLE_PF(bp) ||			\
1678 				  ((bp)->fw_cap & BNXT_FW_CAP_SHARED_PORT_CFG)) && \
1679 				 (bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED)
1680 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1681 #define BNXT_RX_PAGE_MODE(bp)	((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1682 #define BNXT_SUPPORTS_TPA(bp)	(!BNXT_CHIP_TYPE_NITRO_A0(bp) &&	\
1683 				 (!((bp)->flags & BNXT_FLAG_CHIP_P5) ||	\
1684 				  (bp)->max_tpa_v2) && !is_kdump_kernel())
1685 
1686 #define BNXT_CHIP_SR2(bp)			\
1687 	((bp)->chip_num == CHIP_NUM_58818)
1688 
1689 #define BNXT_CHIP_P5_THOR(bp)			\
1690 	((bp)->chip_num == CHIP_NUM_57508 ||	\
1691 	 (bp)->chip_num == CHIP_NUM_57504 ||	\
1692 	 (bp)->chip_num == CHIP_NUM_57502)
1693 
1694 /* Chip class phase 5 */
1695 #define BNXT_CHIP_P5(bp)			\
1696 	(BNXT_CHIP_P5_THOR(bp) || BNXT_CHIP_SR2(bp))
1697 
1698 /* Chip class phase 4.x */
1699 #define BNXT_CHIP_P4(bp)			\
1700 	(BNXT_CHIP_NUM_57X1X((bp)->chip_num) ||	\
1701 	 BNXT_CHIP_NUM_5745X((bp)->chip_num) ||	\
1702 	 BNXT_CHIP_NUM_588XX((bp)->chip_num) ||	\
1703 	 (BNXT_CHIP_NUM_58700((bp)->chip_num) &&	\
1704 	  !BNXT_CHIP_TYPE_NITRO_A0(bp)))
1705 
1706 #define BNXT_CHIP_P4_PLUS(bp)			\
1707 	(BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))
1708 
1709 	struct bnxt_en_dev	*edev;
1710 	struct bnxt_en_dev *	(*ulp_probe)(struct net_device *);
1711 
1712 	struct bnxt_napi	**bnapi;
1713 
1714 	struct bnxt_rx_ring_info	*rx_ring;
1715 	struct bnxt_tx_ring_info	*tx_ring;
1716 	u16			*tx_ring_map;
1717 
1718 	struct sk_buff *	(*gro_func)(struct bnxt_tpa_info *, int, int,
1719 					    struct sk_buff *);
1720 
1721 	struct sk_buff *	(*rx_skb_func)(struct bnxt *,
1722 					       struct bnxt_rx_ring_info *,
1723 					       u16, void *, u8 *, dma_addr_t,
1724 					       unsigned int);
1725 
1726 	u16			max_tpa_v2;
1727 	u16			max_tpa;
1728 	u32			rx_buf_size;
1729 	u32			rx_buf_use_size;	/* useable size */
1730 	u16			rx_offset;
1731 	u16			rx_dma_offset;
1732 	enum dma_data_direction	rx_dir;
1733 	u32			rx_ring_size;
1734 	u32			rx_agg_ring_size;
1735 	u32			rx_copy_thresh;
1736 	u32			rx_ring_mask;
1737 	u32			rx_agg_ring_mask;
1738 	int			rx_nr_pages;
1739 	int			rx_agg_nr_pages;
1740 	int			rx_nr_rings;
1741 	int			rsscos_nr_ctxs;
1742 
1743 	u32			tx_ring_size;
1744 	u32			tx_ring_mask;
1745 	int			tx_nr_pages;
1746 	int			tx_nr_rings;
1747 	int			tx_nr_rings_per_tc;
1748 	int			tx_nr_rings_xdp;
1749 
1750 	int			tx_wake_thresh;
1751 	int			tx_push_thresh;
1752 	int			tx_push_size;
1753 
1754 	u32			cp_ring_size;
1755 	u32			cp_ring_mask;
1756 	u32			cp_bit;
1757 	int			cp_nr_pages;
1758 	int			cp_nr_rings;
1759 
1760 	/* grp_info indexed by completion ring index */
1761 	struct bnxt_ring_grp_info	*grp_info;
1762 	struct bnxt_vnic_info	*vnic_info;
1763 	int			nr_vnics;
1764 	u16			*rss_indir_tbl;
1765 	u16			rss_indir_tbl_entries;
1766 	u32			rss_hash_cfg;
1767 
1768 	u16			max_mtu;
1769 	u8			max_tc;
1770 	u8			max_lltc;	/* lossless TCs */
1771 	struct bnxt_queue_info	q_info[BNXT_MAX_QUEUE];
1772 	u8			tc_to_qidx[BNXT_MAX_QUEUE];
1773 	u8			q_ids[BNXT_MAX_QUEUE];
1774 	u8			max_q;
1775 
1776 	unsigned int		current_interval;
1777 #define BNXT_TIMER_INTERVAL	HZ
1778 
1779 	struct timer_list	timer;
1780 
1781 	unsigned long		state;
1782 #define BNXT_STATE_OPEN		0
1783 #define BNXT_STATE_IN_SP_TASK	1
1784 #define BNXT_STATE_READ_STATS	2
1785 #define BNXT_STATE_FW_RESET_DET 3
1786 #define BNXT_STATE_IN_FW_RESET	4
1787 #define BNXT_STATE_ABORT_ERR	5
1788 #define BNXT_STATE_FW_FATAL_COND	6
1789 #define BNXT_STATE_DRV_REGISTERED	7
1790 #define BNXT_STATE_PCI_CHANNEL_IO_FROZEN	8
1791 
1792 #define BNXT_NO_FW_ACCESS(bp)					\
1793 	(test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) ||	\
1794 	 pci_channel_offline((bp)->pdev))
1795 
1796 	struct bnxt_irq	*irq_tbl;
1797 	int			total_irqs;
1798 	u8			mac_addr[ETH_ALEN];
1799 
1800 #ifdef CONFIG_BNXT_DCB
1801 	struct ieee_pfc		*ieee_pfc;
1802 	struct ieee_ets		*ieee_ets;
1803 	u8			dcbx_cap;
1804 	u8			default_pri;
1805 	u8			max_dscp_value;
1806 #endif /* CONFIG_BNXT_DCB */
1807 
1808 	u32			msg_enable;
1809 
1810 	u32			fw_cap;
1811 	#define BNXT_FW_CAP_SHORT_CMD			0x00000001
1812 	#define BNXT_FW_CAP_LLDP_AGENT			0x00000002
1813 	#define BNXT_FW_CAP_DCBX_AGENT			0x00000004
1814 	#define BNXT_FW_CAP_NEW_RM			0x00000008
1815 	#define BNXT_FW_CAP_IF_CHANGE			0x00000010
1816 	#define BNXT_FW_CAP_KONG_MB_CHNL		0x00000080
1817 	#define BNXT_FW_CAP_OVS_64BIT_HANDLE		0x00000400
1818 	#define BNXT_FW_CAP_TRUSTED_VF			0x00000800
1819 	#define BNXT_FW_CAP_ERROR_RECOVERY		0x00002000
1820 	#define BNXT_FW_CAP_PKG_VER			0x00004000
1821 	#define BNXT_FW_CAP_CFA_ADV_FLOW		0x00008000
1822 	#define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2	0x00010000
1823 	#define BNXT_FW_CAP_PCIE_STATS_SUPPORTED	0x00020000
1824 	#define BNXT_FW_CAP_EXT_STATS_SUPPORTED		0x00040000
1825 	#define BNXT_FW_CAP_ERR_RECOVER_RELOAD		0x00100000
1826 	#define BNXT_FW_CAP_HOT_RESET			0x00200000
1827 	#define BNXT_FW_CAP_SHARED_PORT_CFG		0x00400000
1828 	#define BNXT_FW_CAP_VLAN_RX_STRIP		0x01000000
1829 	#define BNXT_FW_CAP_VLAN_TX_INSERT		0x02000000
1830 	#define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED	0x04000000
1831 	#define BNXT_FW_CAP_PORT_STATS_NO_RESET		0x10000000
1832 	#define BNXT_FW_CAP_RING_MONITOR		0x40000000
1833 
1834 #define BNXT_NEW_RM(bp)		((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
1835 	u32			hwrm_spec_code;
1836 	u16			hwrm_cmd_seq;
1837 	u16                     hwrm_cmd_kong_seq;
1838 	u16			hwrm_intr_seq_id;
1839 	void			*hwrm_short_cmd_req_addr;
1840 	dma_addr_t		hwrm_short_cmd_req_dma_addr;
1841 	void			*hwrm_cmd_resp_addr;
1842 	dma_addr_t		hwrm_cmd_resp_dma_addr;
1843 	void			*hwrm_cmd_kong_resp_addr;
1844 	dma_addr_t		hwrm_cmd_kong_resp_dma_addr;
1845 
1846 	struct rtnl_link_stats64	net_stats_prev;
1847 	struct bnxt_stats_mem	port_stats;
1848 	struct bnxt_stats_mem	rx_port_stats_ext;
1849 	struct bnxt_stats_mem	tx_port_stats_ext;
1850 	u16			fw_rx_stats_ext_size;
1851 	u16			fw_tx_stats_ext_size;
1852 	u16			hw_ring_stats_size;
1853 	u8			pri2cos_idx[8];
1854 	u8			pri2cos_valid;
1855 
1856 	u16			hwrm_max_req_len;
1857 	u16			hwrm_max_ext_req_len;
1858 	int			hwrm_cmd_timeout;
1859 	struct mutex		hwrm_cmd_lock;	/* serialize hwrm messages */
1860 	struct hwrm_ver_get_output	ver_resp;
1861 #define FW_VER_STR_LEN		32
1862 #define BC_HWRM_STR_LEN		21
1863 #define PHY_VER_STR_LEN         (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
1864 	char			fw_ver_str[FW_VER_STR_LEN];
1865 	char			hwrm_ver_supp[FW_VER_STR_LEN];
1866 	char			nvm_cfg_ver[FW_VER_STR_LEN];
1867 	u64			fw_ver_code;
1868 #define BNXT_FW_VER_CODE(maj, min, bld, rsv)			\
1869 	((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv))
1870 #define BNXT_FW_MAJ(bp)		((bp)->fw_ver_code >> 48)
1871 
1872 	u16			vxlan_fw_dst_port_id;
1873 	u16			nge_fw_dst_port_id;
1874 	u8			port_partition_type;
1875 	u8			port_count;
1876 	u16			br_mode;
1877 
1878 	struct bnxt_coal_cap	coal_cap;
1879 	struct bnxt_coal	rx_coal;
1880 	struct bnxt_coal	tx_coal;
1881 
1882 	u32			stats_coal_ticks;
1883 #define BNXT_DEF_STATS_COAL_TICKS	 1000000
1884 #define BNXT_MIN_STATS_COAL_TICKS	  250000
1885 #define BNXT_MAX_STATS_COAL_TICKS	 1000000
1886 
1887 	struct work_struct	sp_task;
1888 	unsigned long		sp_event;
1889 #define BNXT_RX_MASK_SP_EVENT		0
1890 #define BNXT_RX_NTP_FLTR_SP_EVENT	1
1891 #define BNXT_LINK_CHNG_SP_EVENT		2
1892 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT	3
1893 #define BNXT_RESET_TASK_SP_EVENT	6
1894 #define BNXT_RST_RING_SP_EVENT		7
1895 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT	8
1896 #define BNXT_PERIODIC_STATS_SP_EVENT	9
1897 #define BNXT_HWRM_PORT_MODULE_SP_EVENT	10
1898 #define BNXT_RESET_TASK_SILENT_SP_EVENT	11
1899 #define BNXT_LINK_SPEED_CHNG_SP_EVENT	14
1900 #define BNXT_FLOW_STATS_SP_EVENT	15
1901 #define BNXT_UPDATE_PHY_SP_EVENT	16
1902 #define BNXT_RING_COAL_NOW_SP_EVENT	17
1903 #define BNXT_FW_RESET_NOTIFY_SP_EVENT	18
1904 #define BNXT_FW_EXCEPTION_SP_EVENT	19
1905 #define BNXT_LINK_CFG_CHANGE_SP_EVENT	21
1906 
1907 	struct delayed_work	fw_reset_task;
1908 	int			fw_reset_state;
1909 #define BNXT_FW_RESET_STATE_POLL_VF	1
1910 #define BNXT_FW_RESET_STATE_RESET_FW	2
1911 #define BNXT_FW_RESET_STATE_ENABLE_DEV	3
1912 #define BNXT_FW_RESET_STATE_POLL_FW	4
1913 #define BNXT_FW_RESET_STATE_OPENING	5
1914 #define BNXT_FW_RESET_STATE_POLL_FW_DOWN	6
1915 
1916 	u16			fw_reset_min_dsecs;
1917 #define BNXT_DFLT_FW_RST_MIN_DSECS	20
1918 	u16			fw_reset_max_dsecs;
1919 #define BNXT_DFLT_FW_RST_MAX_DSECS	60
1920 	unsigned long		fw_reset_timestamp;
1921 
1922 	struct bnxt_fw_health	*fw_health;
1923 
1924 	struct bnxt_hw_resc	hw_resc;
1925 	struct bnxt_pf_info	pf;
1926 	struct bnxt_ctx_mem_info	*ctx;
1927 #ifdef CONFIG_BNXT_SRIOV
1928 	int			nr_vfs;
1929 	struct bnxt_vf_info	vf;
1930 	wait_queue_head_t	sriov_cfg_wait;
1931 	bool			sriov_cfg;
1932 #define BNXT_SRIOV_CFG_WAIT_TMO	msecs_to_jiffies(10000)
1933 
1934 	/* lock to protect VF-rep creation/cleanup via
1935 	 * multiple paths such as ->sriov_configure() and
1936 	 * devlink ->eswitch_mode_set()
1937 	 */
1938 	struct mutex		sriov_lock;
1939 #endif
1940 
1941 #if BITS_PER_LONG == 32
1942 	/* ensure atomic 64-bit doorbell writes on 32-bit systems. */
1943 	spinlock_t		db_lock;
1944 #endif
1945 	int			db_size;
1946 
1947 #define BNXT_NTP_FLTR_MAX_FLTR	4096
1948 #define BNXT_NTP_FLTR_HASH_SIZE	512
1949 #define BNXT_NTP_FLTR_HASH_MASK	(BNXT_NTP_FLTR_HASH_SIZE - 1)
1950 	struct hlist_head	ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
1951 	spinlock_t		ntp_fltr_lock;	/* for hash table add, del */
1952 
1953 	unsigned long		*ntp_fltr_bmap;
1954 	int			ntp_fltr_count;
1955 
1956 	/* To protect link related settings during link changes and
1957 	 * ethtool settings changes.
1958 	 */
1959 	struct mutex		link_lock;
1960 	struct bnxt_link_info	link_info;
1961 	struct ethtool_eee	eee;
1962 	u32			lpi_tmr_lo;
1963 	u32			lpi_tmr_hi;
1964 
1965 	u8			num_tests;
1966 	struct bnxt_test_info	*test_info;
1967 
1968 	u8			wol_filter_id;
1969 	u8			wol;
1970 
1971 	u8			num_leds;
1972 	struct bnxt_led_info	leds[BNXT_MAX_LED];
1973 	u16			dump_flag;
1974 #define BNXT_DUMP_LIVE		0
1975 #define BNXT_DUMP_CRASH		1
1976 
1977 	struct bpf_prog		*xdp_prog;
1978 
1979 	/* devlink interface and vf-rep structs */
1980 	struct devlink		*dl;
1981 	struct devlink_port	dl_port;
1982 	enum devlink_eswitch_mode eswitch_mode;
1983 	struct bnxt_vf_rep	**vf_reps; /* array of vf-rep ptrs */
1984 	u16			*cfa_code_map; /* cfa_code -> vf_idx map */
1985 	u8			dsn[8];
1986 	struct bnxt_tc_info	*tc_info;
1987 	struct list_head	tc_indr_block_list;
1988 	struct dentry		*debugfs_pdev;
1989 	struct device		*hwmon_dev;
1990 };
1991 
1992 #define BNXT_NUM_RX_RING_STATS			8
1993 #define BNXT_NUM_TX_RING_STATS			8
1994 #define BNXT_NUM_TPA_RING_STATS			4
1995 #define BNXT_NUM_TPA_RING_STATS_P5		5
1996 #define BNXT_NUM_TPA_RING_STATS_P5_SR2		6
1997 
1998 #define BNXT_RING_STATS_SIZE_P5					\
1999 	((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +	\
2000 	  BNXT_NUM_TPA_RING_STATS_P5) * 8)
2001 
2002 #define BNXT_RING_STATS_SIZE_P5_SR2				\
2003 	((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +	\
2004 	  BNXT_NUM_TPA_RING_STATS_P5_SR2) * 8)
2005 
2006 #define BNXT_GET_RING_STATS64(sw, counter)		\
2007 	(*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))
2008 
2009 #define BNXT_GET_RX_PORT_STATS64(sw, counter)		\
2010 	(*((sw) + offsetof(struct rx_port_stats, counter) / 8))
2011 
2012 #define BNXT_GET_TX_PORT_STATS64(sw, counter)		\
2013 	(*((sw) + offsetof(struct tx_port_stats, counter) / 8))
2014 
2015 #define BNXT_PORT_STATS_SIZE				\
2016 	(sizeof(struct rx_port_stats) + sizeof(struct tx_port_stats) + 1024)
2017 
2018 #define BNXT_TX_PORT_STATS_BYTE_OFFSET			\
2019 	(sizeof(struct rx_port_stats) + 512)
2020 
2021 #define BNXT_RX_STATS_OFFSET(counter)			\
2022 	(offsetof(struct rx_port_stats, counter) / 8)
2023 
2024 #define BNXT_TX_STATS_OFFSET(counter)			\
2025 	((offsetof(struct tx_port_stats, counter) +	\
2026 	  BNXT_TX_PORT_STATS_BYTE_OFFSET) / 8)
2027 
2028 #define BNXT_RX_STATS_EXT_OFFSET(counter)		\
2029 	(offsetof(struct rx_port_stats_ext, counter) / 8)
2030 
2031 #define BNXT_TX_STATS_EXT_OFFSET(counter)		\
2032 	(offsetof(struct tx_port_stats_ext, counter) / 8)
2033 
2034 #define BNXT_HW_FEATURE_VLAN_ALL_RX				\
2035 	(NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)
2036 #define BNXT_HW_FEATURE_VLAN_ALL_TX				\
2037 	(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX)
2038 
2039 #define I2C_DEV_ADDR_A0				0xa0
2040 #define I2C_DEV_ADDR_A2				0xa2
2041 #define SFF_DIAG_SUPPORT_OFFSET			0x5c
2042 #define SFF_MODULE_ID_SFP			0x3
2043 #define SFF_MODULE_ID_QSFP			0xc
2044 #define SFF_MODULE_ID_QSFP_PLUS			0xd
2045 #define SFF_MODULE_ID_QSFP28			0x11
2046 #define BNXT_MAX_PHY_I2C_RESP_SIZE		64
2047 
2048 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
2049 {
2050 	/* Tell compiler to fetch tx indices from memory. */
2051 	barrier();
2052 
2053 	return bp->tx_ring_size -
2054 		((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
2055 }
2056 
2057 #if BITS_PER_LONG == 32
2058 #define writeq(val64, db)			\
2059 do {						\
2060 	spin_lock(&bp->db_lock);		\
2061 	writel((val64) & 0xffffffff, db);	\
2062 	writel((val64) >> 32, (db) + 4);	\
2063 	spin_unlock(&bp->db_lock);		\
2064 } while (0)
2065 
2066 #define writeq_relaxed writeq
2067 #endif
2068 
2069 /* For TX and RX ring doorbells with no ordering guarantee*/
2070 static inline void bnxt_db_write_relaxed(struct bnxt *bp,
2071 					 struct bnxt_db_info *db, u32 idx)
2072 {
2073 	if (bp->flags & BNXT_FLAG_CHIP_P5) {
2074 		writeq_relaxed(db->db_key64 | idx, db->doorbell);
2075 	} else {
2076 		u32 db_val = db->db_key32 | idx;
2077 
2078 		writel_relaxed(db_val, db->doorbell);
2079 		if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2080 			writel_relaxed(db_val, db->doorbell);
2081 	}
2082 }
2083 
2084 /* For TX and RX ring doorbells */
2085 static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
2086 				 u32 idx)
2087 {
2088 	if (bp->flags & BNXT_FLAG_CHIP_P5) {
2089 		writeq(db->db_key64 | idx, db->doorbell);
2090 	} else {
2091 		u32 db_val = db->db_key32 | idx;
2092 
2093 		writel(db_val, db->doorbell);
2094 		if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2095 			writel(db_val, db->doorbell);
2096 	}
2097 }
2098 
2099 static inline bool bnxt_cfa_hwrm_message(u16 req_type)
2100 {
2101 	switch (req_type) {
2102 	case HWRM_CFA_ENCAP_RECORD_ALLOC:
2103 	case HWRM_CFA_ENCAP_RECORD_FREE:
2104 	case HWRM_CFA_DECAP_FILTER_ALLOC:
2105 	case HWRM_CFA_DECAP_FILTER_FREE:
2106 	case HWRM_CFA_EM_FLOW_ALLOC:
2107 	case HWRM_CFA_EM_FLOW_FREE:
2108 	case HWRM_CFA_EM_FLOW_CFG:
2109 	case HWRM_CFA_FLOW_ALLOC:
2110 	case HWRM_CFA_FLOW_FREE:
2111 	case HWRM_CFA_FLOW_INFO:
2112 	case HWRM_CFA_FLOW_FLUSH:
2113 	case HWRM_CFA_FLOW_STATS:
2114 	case HWRM_CFA_METER_PROFILE_ALLOC:
2115 	case HWRM_CFA_METER_PROFILE_FREE:
2116 	case HWRM_CFA_METER_PROFILE_CFG:
2117 	case HWRM_CFA_METER_INSTANCE_ALLOC:
2118 	case HWRM_CFA_METER_INSTANCE_FREE:
2119 		return true;
2120 	default:
2121 		return false;
2122 	}
2123 }
2124 
2125 static inline bool bnxt_kong_hwrm_message(struct bnxt *bp, struct input *req)
2126 {
2127 	return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&
2128 		bnxt_cfa_hwrm_message(le16_to_cpu(req->req_type)));
2129 }
2130 
2131 static inline bool bnxt_hwrm_kong_chnl(struct bnxt *bp, struct input *req)
2132 {
2133 	return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&
2134 		req->resp_addr == cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr));
2135 }
2136 
2137 static inline void *bnxt_get_hwrm_resp_addr(struct bnxt *bp, void *req)
2138 {
2139 	if (bnxt_hwrm_kong_chnl(bp, (struct input *)req))
2140 		return bp->hwrm_cmd_kong_resp_addr;
2141 	else
2142 		return bp->hwrm_cmd_resp_addr;
2143 }
2144 
2145 static inline u16 bnxt_get_hwrm_seq_id(struct bnxt *bp, u16 dst)
2146 {
2147 	u16 seq_id;
2148 
2149 	if (dst == BNXT_HWRM_CHNL_CHIMP)
2150 		seq_id = bp->hwrm_cmd_seq++;
2151 	else
2152 		seq_id = bp->hwrm_cmd_kong_seq++;
2153 	return seq_id;
2154 }
2155 
2156 extern const u16 bnxt_lhint_arr[];
2157 
2158 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
2159 		       u16 prod, gfp_t gfp);
2160 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
2161 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx);
2162 void bnxt_set_tpa_flags(struct bnxt *bp);
2163 void bnxt_set_ring_params(struct bnxt *);
2164 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
2165 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16);
2166 int _hwrm_send_message(struct bnxt *, void *, u32, int);
2167 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 len, int timeout);
2168 int hwrm_send_message(struct bnxt *, void *, u32, int);
2169 int hwrm_send_message_silent(struct bnxt *, void *, u32, int);
2170 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap,
2171 			    int bmap_size, bool async_only);
2172 int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings);
2173 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
2174 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
2175 int bnxt_nq_rings_in_use(struct bnxt *bp);
2176 int bnxt_hwrm_set_coal(struct bnxt *);
2177 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
2178 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
2179 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
2180 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
2181 int bnxt_get_avail_msix(struct bnxt *bp, int num);
2182 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
2183 void bnxt_tx_disable(struct bnxt *bp);
2184 void bnxt_tx_enable(struct bnxt *bp);
2185 int bnxt_update_link(struct bnxt *bp, bool chng_link_state);
2186 int bnxt_hwrm_set_pause(struct bnxt *);
2187 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
2188 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
2189 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
2190 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
2191 int bnxt_hwrm_fw_set_time(struct bnxt *);
2192 int bnxt_open_nic(struct bnxt *, bool, bool);
2193 int bnxt_half_open_nic(struct bnxt *bp);
2194 void bnxt_half_close_nic(struct bnxt *bp);
2195 int bnxt_close_nic(struct bnxt *, bool, bool);
2196 int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
2197 			 u32 *reg_buf);
2198 void bnxt_fw_exception(struct bnxt *bp);
2199 void bnxt_fw_reset(struct bnxt *bp);
2200 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
2201 		     int tx_xdp);
2202 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
2203 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
2204 int bnxt_restore_pf_fw_resources(struct bnxt *bp);
2205 int bnxt_get_port_parent_id(struct net_device *dev,
2206 			    struct netdev_phys_item_id *ppid);
2207 void bnxt_dim_work(struct work_struct *work);
2208 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);
2209 
2210 #endif
2211