1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 13 #include <linux/stringify.h> 14 #include <linux/kernel.h> 15 #include <linux/timer.h> 16 #include <linux/errno.h> 17 #include <linux/ioport.h> 18 #include <linux/slab.h> 19 #include <linux/vmalloc.h> 20 #include <linux/interrupt.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/etherdevice.h> 24 #include <linux/skbuff.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/bitops.h> 27 #include <linux/io.h> 28 #include <linux/irq.h> 29 #include <linux/delay.h> 30 #include <asm/byteorder.h> 31 #include <asm/page.h> 32 #include <linux/time.h> 33 #include <linux/mii.h> 34 #include <linux/if.h> 35 #include <linux/if_vlan.h> 36 #include <linux/if_bridge.h> 37 #include <linux/rtc.h> 38 #include <linux/bpf.h> 39 #include <net/ip.h> 40 #include <net/tcp.h> 41 #include <net/udp.h> 42 #include <net/checksum.h> 43 #include <net/ip6_checksum.h> 44 #include <net/udp_tunnel.h> 45 #include <linux/workqueue.h> 46 #include <linux/prefetch.h> 47 #include <linux/cache.h> 48 #include <linux/log2.h> 49 #include <linux/aer.h> 50 #include <linux/bitmap.h> 51 #include <linux/cpu_rmap.h> 52 #include <linux/cpumask.h> 53 #include <net/pkt_cls.h> 54 55 #include "bnxt_hsi.h" 56 #include "bnxt.h" 57 #include "bnxt_ulp.h" 58 #include "bnxt_sriov.h" 59 #include "bnxt_ethtool.h" 60 #include "bnxt_dcb.h" 61 #include "bnxt_xdp.h" 62 #include "bnxt_vfr.h" 63 #include "bnxt_tc.h" 64 #include "bnxt_devlink.h" 65 66 #define BNXT_TX_TIMEOUT (5 * HZ) 67 68 static const char version[] = 69 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n"; 70 71 MODULE_LICENSE("GPL"); 72 MODULE_DESCRIPTION("Broadcom BCM573xx network driver"); 73 MODULE_VERSION(DRV_MODULE_VERSION); 74 75 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN) 76 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD 77 #define BNXT_RX_COPY_THRESH 256 78 79 #define BNXT_TX_PUSH_THRESH 164 80 81 enum board_idx { 82 BCM57301, 83 BCM57302, 84 BCM57304, 85 BCM57417_NPAR, 86 BCM58700, 87 BCM57311, 88 BCM57312, 89 BCM57402, 90 BCM57404, 91 BCM57406, 92 BCM57402_NPAR, 93 BCM57407, 94 BCM57412, 95 BCM57414, 96 BCM57416, 97 BCM57417, 98 BCM57412_NPAR, 99 BCM57314, 100 BCM57417_SFP, 101 BCM57416_SFP, 102 BCM57404_NPAR, 103 BCM57406_NPAR, 104 BCM57407_SFP, 105 BCM57407_NPAR, 106 BCM57414_NPAR, 107 BCM57416_NPAR, 108 BCM57452, 109 BCM57454, 110 BCM58802, 111 BCM58804, 112 BCM58808, 113 NETXTREME_E_VF, 114 NETXTREME_C_VF, 115 NETXTREME_S_VF, 116 }; 117 118 /* indexed by enum above */ 119 static const struct { 120 char *name; 121 } board_info[] = { 122 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" }, 123 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" }, 124 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 125 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" }, 126 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" }, 127 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" }, 128 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" }, 129 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" }, 130 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" }, 131 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" }, 132 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" }, 133 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" }, 134 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" }, 135 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" }, 136 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" }, 137 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" }, 138 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" }, 139 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 140 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" }, 141 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" }, 142 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" }, 143 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" }, 144 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" }, 145 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" }, 146 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" }, 147 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" }, 148 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" }, 149 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 150 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" }, 151 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 152 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 153 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" }, 154 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" }, 155 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" }, 156 }; 157 158 static const struct pci_device_id bnxt_pci_tbl[] = { 159 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 }, 160 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR }, 161 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 }, 162 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 }, 163 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 }, 164 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR }, 165 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 }, 166 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 }, 167 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 }, 168 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 }, 169 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 }, 170 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 }, 171 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR }, 172 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 }, 173 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 }, 174 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 }, 175 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 }, 176 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 }, 177 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR }, 178 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 }, 179 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP }, 180 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP }, 181 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR }, 182 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR }, 183 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP }, 184 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR }, 185 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR }, 186 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR }, 187 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR }, 188 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR }, 189 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR }, 190 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 }, 191 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 }, 192 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 }, 193 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 }, 194 #ifdef CONFIG_BNXT_SRIOV 195 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF }, 196 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF }, 197 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF }, 198 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF }, 199 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF }, 200 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF }, 201 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF }, 202 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF }, 203 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF }, 204 #endif 205 { 0 } 206 }; 207 208 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl); 209 210 static const u16 bnxt_vf_req_snif[] = { 211 HWRM_FUNC_CFG, 212 HWRM_PORT_PHY_QCFG, 213 HWRM_CFA_L2_FILTER_ALLOC, 214 }; 215 216 static const u16 bnxt_async_events_arr[] = { 217 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE, 218 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD, 219 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED, 220 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE, 221 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE, 222 }; 223 224 static struct workqueue_struct *bnxt_pf_wq; 225 226 static bool bnxt_vf_pciid(enum board_idx idx) 227 { 228 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF || 229 idx == NETXTREME_S_VF); 230 } 231 232 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID) 233 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS) 234 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS) 235 236 #define BNXT_CP_DB_REARM(db, raw_cons) \ 237 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db) 238 239 #define BNXT_CP_DB(db, raw_cons) \ 240 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db) 241 242 #define BNXT_CP_DB_IRQ_DIS(db) \ 243 writel(DB_CP_IRQ_DIS_FLAGS, db) 244 245 const u16 bnxt_lhint_arr[] = { 246 TX_BD_FLAGS_LHINT_512_AND_SMALLER, 247 TX_BD_FLAGS_LHINT_512_TO_1023, 248 TX_BD_FLAGS_LHINT_1024_TO_2047, 249 TX_BD_FLAGS_LHINT_1024_TO_2047, 250 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 251 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 252 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 253 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 254 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 255 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 256 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 257 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 258 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 259 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 260 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 261 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 262 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 263 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 264 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 265 }; 266 267 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb) 268 { 269 struct metadata_dst *md_dst = skb_metadata_dst(skb); 270 271 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX) 272 return 0; 273 274 return md_dst->u.port_info.port_id; 275 } 276 277 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev) 278 { 279 struct bnxt *bp = netdev_priv(dev); 280 struct tx_bd *txbd; 281 struct tx_bd_ext *txbd1; 282 struct netdev_queue *txq; 283 int i; 284 dma_addr_t mapping; 285 unsigned int length, pad = 0; 286 u32 len, free_size, vlan_tag_flags, cfa_action, flags; 287 u16 prod, last_frag; 288 struct pci_dev *pdev = bp->pdev; 289 struct bnxt_tx_ring_info *txr; 290 struct bnxt_sw_tx_bd *tx_buf; 291 292 i = skb_get_queue_mapping(skb); 293 if (unlikely(i >= bp->tx_nr_rings)) { 294 dev_kfree_skb_any(skb); 295 return NETDEV_TX_OK; 296 } 297 298 txq = netdev_get_tx_queue(dev, i); 299 txr = &bp->tx_ring[bp->tx_ring_map[i]]; 300 prod = txr->tx_prod; 301 302 free_size = bnxt_tx_avail(bp, txr); 303 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) { 304 netif_tx_stop_queue(txq); 305 return NETDEV_TX_BUSY; 306 } 307 308 length = skb->len; 309 len = skb_headlen(skb); 310 last_frag = skb_shinfo(skb)->nr_frags; 311 312 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 313 314 txbd->tx_bd_opaque = prod; 315 316 tx_buf = &txr->tx_buf_ring[prod]; 317 tx_buf->skb = skb; 318 tx_buf->nr_frags = last_frag; 319 320 vlan_tag_flags = 0; 321 cfa_action = bnxt_xmit_get_cfa_action(skb); 322 if (skb_vlan_tag_present(skb)) { 323 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN | 324 skb_vlan_tag_get(skb); 325 /* Currently supports 8021Q, 8021AD vlan offloads 326 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated 327 */ 328 if (skb->vlan_proto == htons(ETH_P_8021Q)) 329 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT; 330 } 331 332 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) { 333 struct tx_push_buffer *tx_push_buf = txr->tx_push; 334 struct tx_push_bd *tx_push = &tx_push_buf->push_bd; 335 struct tx_bd_ext *tx_push1 = &tx_push->txbd2; 336 void *pdata = tx_push_buf->data; 337 u64 *end; 338 int j, push_len; 339 340 /* Set COAL_NOW to be ready quickly for the next push */ 341 tx_push->tx_bd_len_flags_type = 342 cpu_to_le32((length << TX_BD_LEN_SHIFT) | 343 TX_BD_TYPE_LONG_TX_BD | 344 TX_BD_FLAGS_LHINT_512_AND_SMALLER | 345 TX_BD_FLAGS_COAL_NOW | 346 TX_BD_FLAGS_PACKET_END | 347 (2 << TX_BD_FLAGS_BD_CNT_SHIFT)); 348 349 if (skb->ip_summed == CHECKSUM_PARTIAL) 350 tx_push1->tx_bd_hsize_lflags = 351 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 352 else 353 tx_push1->tx_bd_hsize_lflags = 0; 354 355 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 356 tx_push1->tx_bd_cfa_action = 357 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); 358 359 end = pdata + length; 360 end = PTR_ALIGN(end, 8) - 1; 361 *end = 0; 362 363 skb_copy_from_linear_data(skb, pdata, len); 364 pdata += len; 365 for (j = 0; j < last_frag; j++) { 366 skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; 367 void *fptr; 368 369 fptr = skb_frag_address_safe(frag); 370 if (!fptr) 371 goto normal_tx; 372 373 memcpy(pdata, fptr, skb_frag_size(frag)); 374 pdata += skb_frag_size(frag); 375 } 376 377 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type; 378 txbd->tx_bd_haddr = txr->data_mapping; 379 prod = NEXT_TX(prod); 380 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 381 memcpy(txbd, tx_push1, sizeof(*txbd)); 382 prod = NEXT_TX(prod); 383 tx_push->doorbell = 384 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod); 385 txr->tx_prod = prod; 386 387 tx_buf->is_push = 1; 388 netdev_tx_sent_queue(txq, skb->len); 389 wmb(); /* Sync is_push and byte queue before pushing data */ 390 391 push_len = (length + sizeof(*tx_push) + 7) / 8; 392 if (push_len > 16) { 393 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16); 394 __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1, 395 (push_len - 16) << 1); 396 } else { 397 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 398 push_len); 399 } 400 401 goto tx_done; 402 } 403 404 normal_tx: 405 if (length < BNXT_MIN_PKT_SIZE) { 406 pad = BNXT_MIN_PKT_SIZE - length; 407 if (skb_pad(skb, pad)) { 408 /* SKB already freed. */ 409 tx_buf->skb = NULL; 410 return NETDEV_TX_OK; 411 } 412 length = BNXT_MIN_PKT_SIZE; 413 } 414 415 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE); 416 417 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) { 418 dev_kfree_skb_any(skb); 419 tx_buf->skb = NULL; 420 return NETDEV_TX_OK; 421 } 422 423 dma_unmap_addr_set(tx_buf, mapping, mapping); 424 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD | 425 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT); 426 427 txbd->tx_bd_haddr = cpu_to_le64(mapping); 428 429 prod = NEXT_TX(prod); 430 txbd1 = (struct tx_bd_ext *) 431 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 432 433 txbd1->tx_bd_hsize_lflags = 0; 434 if (skb_is_gso(skb)) { 435 u32 hdr_len; 436 437 if (skb->encapsulation) 438 hdr_len = skb_inner_network_offset(skb) + 439 skb_inner_network_header_len(skb) + 440 inner_tcp_hdrlen(skb); 441 else 442 hdr_len = skb_transport_offset(skb) + 443 tcp_hdrlen(skb); 444 445 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO | 446 TX_BD_FLAGS_T_IPID | 447 (hdr_len << (TX_BD_HSIZE_SHIFT - 1))); 448 length = skb_shinfo(skb)->gso_size; 449 txbd1->tx_bd_mss = cpu_to_le32(length); 450 length += hdr_len; 451 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 452 txbd1->tx_bd_hsize_lflags = 453 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 454 txbd1->tx_bd_mss = 0; 455 } 456 457 length >>= 9; 458 flags |= bnxt_lhint_arr[length]; 459 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 460 461 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 462 txbd1->tx_bd_cfa_action = 463 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); 464 for (i = 0; i < last_frag; i++) { 465 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 466 467 prod = NEXT_TX(prod); 468 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 469 470 len = skb_frag_size(frag); 471 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len, 472 DMA_TO_DEVICE); 473 474 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) 475 goto tx_dma_error; 476 477 tx_buf = &txr->tx_buf_ring[prod]; 478 dma_unmap_addr_set(tx_buf, mapping, mapping); 479 480 txbd->tx_bd_haddr = cpu_to_le64(mapping); 481 482 flags = len << TX_BD_LEN_SHIFT; 483 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 484 } 485 486 flags &= ~TX_BD_LEN; 487 txbd->tx_bd_len_flags_type = 488 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags | 489 TX_BD_FLAGS_PACKET_END); 490 491 netdev_tx_sent_queue(txq, skb->len); 492 493 /* Sync BD data before updating doorbell */ 494 wmb(); 495 496 prod = NEXT_TX(prod); 497 txr->tx_prod = prod; 498 499 if (!skb->xmit_more || netif_xmit_stopped(txq)) 500 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod); 501 502 tx_done: 503 504 mmiowb(); 505 506 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) { 507 if (skb->xmit_more && !tx_buf->is_push) 508 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod); 509 510 netif_tx_stop_queue(txq); 511 512 /* netif_tx_stop_queue() must be done before checking 513 * tx index in bnxt_tx_avail() below, because in 514 * bnxt_tx_int(), we update tx index before checking for 515 * netif_tx_queue_stopped(). 516 */ 517 smp_mb(); 518 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh) 519 netif_tx_wake_queue(txq); 520 } 521 return NETDEV_TX_OK; 522 523 tx_dma_error: 524 last_frag = i; 525 526 /* start back at beginning and unmap skb */ 527 prod = txr->tx_prod; 528 tx_buf = &txr->tx_buf_ring[prod]; 529 tx_buf->skb = NULL; 530 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 531 skb_headlen(skb), PCI_DMA_TODEVICE); 532 prod = NEXT_TX(prod); 533 534 /* unmap remaining mapped pages */ 535 for (i = 0; i < last_frag; i++) { 536 prod = NEXT_TX(prod); 537 tx_buf = &txr->tx_buf_ring[prod]; 538 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 539 skb_frag_size(&skb_shinfo(skb)->frags[i]), 540 PCI_DMA_TODEVICE); 541 } 542 543 dev_kfree_skb_any(skb); 544 return NETDEV_TX_OK; 545 } 546 547 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts) 548 { 549 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 550 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index); 551 u16 cons = txr->tx_cons; 552 struct pci_dev *pdev = bp->pdev; 553 int i; 554 unsigned int tx_bytes = 0; 555 556 for (i = 0; i < nr_pkts; i++) { 557 struct bnxt_sw_tx_bd *tx_buf; 558 struct sk_buff *skb; 559 int j, last; 560 561 tx_buf = &txr->tx_buf_ring[cons]; 562 cons = NEXT_TX(cons); 563 skb = tx_buf->skb; 564 tx_buf->skb = NULL; 565 566 if (tx_buf->is_push) { 567 tx_buf->is_push = 0; 568 goto next_tx_int; 569 } 570 571 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 572 skb_headlen(skb), PCI_DMA_TODEVICE); 573 last = tx_buf->nr_frags; 574 575 for (j = 0; j < last; j++) { 576 cons = NEXT_TX(cons); 577 tx_buf = &txr->tx_buf_ring[cons]; 578 dma_unmap_page( 579 &pdev->dev, 580 dma_unmap_addr(tx_buf, mapping), 581 skb_frag_size(&skb_shinfo(skb)->frags[j]), 582 PCI_DMA_TODEVICE); 583 } 584 585 next_tx_int: 586 cons = NEXT_TX(cons); 587 588 tx_bytes += skb->len; 589 dev_kfree_skb_any(skb); 590 } 591 592 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes); 593 txr->tx_cons = cons; 594 595 /* Need to make the tx_cons update visible to bnxt_start_xmit() 596 * before checking for netif_tx_queue_stopped(). Without the 597 * memory barrier, there is a small possibility that bnxt_start_xmit() 598 * will miss it and cause the queue to be stopped forever. 599 */ 600 smp_mb(); 601 602 if (unlikely(netif_tx_queue_stopped(txq)) && 603 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) { 604 __netif_tx_lock(txq, smp_processor_id()); 605 if (netif_tx_queue_stopped(txq) && 606 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh && 607 txr->dev_state != BNXT_DEV_STATE_CLOSING) 608 netif_tx_wake_queue(txq); 609 __netif_tx_unlock(txq); 610 } 611 } 612 613 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping, 614 gfp_t gfp) 615 { 616 struct device *dev = &bp->pdev->dev; 617 struct page *page; 618 619 page = alloc_page(gfp); 620 if (!page) 621 return NULL; 622 623 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir, 624 DMA_ATTR_WEAK_ORDERING); 625 if (dma_mapping_error(dev, *mapping)) { 626 __free_page(page); 627 return NULL; 628 } 629 *mapping += bp->rx_dma_offset; 630 return page; 631 } 632 633 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping, 634 gfp_t gfp) 635 { 636 u8 *data; 637 struct pci_dev *pdev = bp->pdev; 638 639 data = kmalloc(bp->rx_buf_size, gfp); 640 if (!data) 641 return NULL; 642 643 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset, 644 bp->rx_buf_use_size, bp->rx_dir, 645 DMA_ATTR_WEAK_ORDERING); 646 647 if (dma_mapping_error(&pdev->dev, *mapping)) { 648 kfree(data); 649 data = NULL; 650 } 651 return data; 652 } 653 654 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 655 u16 prod, gfp_t gfp) 656 { 657 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 658 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod]; 659 dma_addr_t mapping; 660 661 if (BNXT_RX_PAGE_MODE(bp)) { 662 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp); 663 664 if (!page) 665 return -ENOMEM; 666 667 rx_buf->data = page; 668 rx_buf->data_ptr = page_address(page) + bp->rx_offset; 669 } else { 670 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp); 671 672 if (!data) 673 return -ENOMEM; 674 675 rx_buf->data = data; 676 rx_buf->data_ptr = data + bp->rx_offset; 677 } 678 rx_buf->mapping = mapping; 679 680 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 681 return 0; 682 } 683 684 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data) 685 { 686 u16 prod = rxr->rx_prod; 687 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 688 struct rx_bd *cons_bd, *prod_bd; 689 690 prod_rx_buf = &rxr->rx_buf_ring[prod]; 691 cons_rx_buf = &rxr->rx_buf_ring[cons]; 692 693 prod_rx_buf->data = data; 694 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr; 695 696 prod_rx_buf->mapping = cons_rx_buf->mapping; 697 698 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 699 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; 700 701 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr; 702 } 703 704 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) 705 { 706 u16 next, max = rxr->rx_agg_bmap_size; 707 708 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx); 709 if (next >= max) 710 next = find_first_zero_bit(rxr->rx_agg_bmap, max); 711 return next; 712 } 713 714 static inline int bnxt_alloc_rx_page(struct bnxt *bp, 715 struct bnxt_rx_ring_info *rxr, 716 u16 prod, gfp_t gfp) 717 { 718 struct rx_bd *rxbd = 719 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 720 struct bnxt_sw_rx_agg_bd *rx_agg_buf; 721 struct pci_dev *pdev = bp->pdev; 722 struct page *page; 723 dma_addr_t mapping; 724 u16 sw_prod = rxr->rx_sw_agg_prod; 725 unsigned int offset = 0; 726 727 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) { 728 page = rxr->rx_page; 729 if (!page) { 730 page = alloc_page(gfp); 731 if (!page) 732 return -ENOMEM; 733 rxr->rx_page = page; 734 rxr->rx_page_offset = 0; 735 } 736 offset = rxr->rx_page_offset; 737 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE; 738 if (rxr->rx_page_offset == PAGE_SIZE) 739 rxr->rx_page = NULL; 740 else 741 get_page(page); 742 } else { 743 page = alloc_page(gfp); 744 if (!page) 745 return -ENOMEM; 746 } 747 748 mapping = dma_map_page_attrs(&pdev->dev, page, offset, 749 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE, 750 DMA_ATTR_WEAK_ORDERING); 751 if (dma_mapping_error(&pdev->dev, mapping)) { 752 __free_page(page); 753 return -EIO; 754 } 755 756 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 757 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 758 759 __set_bit(sw_prod, rxr->rx_agg_bmap); 760 rx_agg_buf = &rxr->rx_agg_ring[sw_prod]; 761 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod); 762 763 rx_agg_buf->page = page; 764 rx_agg_buf->offset = offset; 765 rx_agg_buf->mapping = mapping; 766 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 767 rxbd->rx_bd_opaque = sw_prod; 768 return 0; 769 } 770 771 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons, 772 u32 agg_bufs) 773 { 774 struct bnxt *bp = bnapi->bp; 775 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 776 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 777 u16 prod = rxr->rx_agg_prod; 778 u16 sw_prod = rxr->rx_sw_agg_prod; 779 u32 i; 780 781 for (i = 0; i < agg_bufs; i++) { 782 u16 cons; 783 struct rx_agg_cmp *agg; 784 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf; 785 struct rx_bd *prod_bd; 786 struct page *page; 787 788 agg = (struct rx_agg_cmp *) 789 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 790 cons = agg->rx_agg_cmp_opaque; 791 __clear_bit(cons, rxr->rx_agg_bmap); 792 793 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 794 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 795 796 __set_bit(sw_prod, rxr->rx_agg_bmap); 797 prod_rx_buf = &rxr->rx_agg_ring[sw_prod]; 798 cons_rx_buf = &rxr->rx_agg_ring[cons]; 799 800 /* It is possible for sw_prod to be equal to cons, so 801 * set cons_rx_buf->page to NULL first. 802 */ 803 page = cons_rx_buf->page; 804 cons_rx_buf->page = NULL; 805 prod_rx_buf->page = page; 806 prod_rx_buf->offset = cons_rx_buf->offset; 807 808 prod_rx_buf->mapping = cons_rx_buf->mapping; 809 810 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 811 812 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping); 813 prod_bd->rx_bd_opaque = sw_prod; 814 815 prod = NEXT_RX_AGG(prod); 816 sw_prod = NEXT_RX_AGG(sw_prod); 817 cp_cons = NEXT_CMP(cp_cons); 818 } 819 rxr->rx_agg_prod = prod; 820 rxr->rx_sw_agg_prod = sw_prod; 821 } 822 823 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp, 824 struct bnxt_rx_ring_info *rxr, 825 u16 cons, void *data, u8 *data_ptr, 826 dma_addr_t dma_addr, 827 unsigned int offset_and_len) 828 { 829 unsigned int payload = offset_and_len >> 16; 830 unsigned int len = offset_and_len & 0xffff; 831 struct skb_frag_struct *frag; 832 struct page *page = data; 833 u16 prod = rxr->rx_prod; 834 struct sk_buff *skb; 835 int off, err; 836 837 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 838 if (unlikely(err)) { 839 bnxt_reuse_rx_data(rxr, cons, data); 840 return NULL; 841 } 842 dma_addr -= bp->rx_dma_offset; 843 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir, 844 DMA_ATTR_WEAK_ORDERING); 845 846 if (unlikely(!payload)) 847 payload = eth_get_headlen(data_ptr, len); 848 849 skb = napi_alloc_skb(&rxr->bnapi->napi, payload); 850 if (!skb) { 851 __free_page(page); 852 return NULL; 853 } 854 855 off = (void *)data_ptr - page_address(page); 856 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE); 857 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN, 858 payload + NET_IP_ALIGN); 859 860 frag = &skb_shinfo(skb)->frags[0]; 861 skb_frag_size_sub(frag, payload); 862 frag->page_offset += payload; 863 skb->data_len -= payload; 864 skb->tail += payload; 865 866 return skb; 867 } 868 869 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp, 870 struct bnxt_rx_ring_info *rxr, u16 cons, 871 void *data, u8 *data_ptr, 872 dma_addr_t dma_addr, 873 unsigned int offset_and_len) 874 { 875 u16 prod = rxr->rx_prod; 876 struct sk_buff *skb; 877 int err; 878 879 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 880 if (unlikely(err)) { 881 bnxt_reuse_rx_data(rxr, cons, data); 882 return NULL; 883 } 884 885 skb = build_skb(data, 0); 886 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, 887 bp->rx_dir, DMA_ATTR_WEAK_ORDERING); 888 if (!skb) { 889 kfree(data); 890 return NULL; 891 } 892 893 skb_reserve(skb, bp->rx_offset); 894 skb_put(skb, offset_and_len & 0xffff); 895 return skb; 896 } 897 898 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi, 899 struct sk_buff *skb, u16 cp_cons, 900 u32 agg_bufs) 901 { 902 struct pci_dev *pdev = bp->pdev; 903 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 904 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 905 u16 prod = rxr->rx_agg_prod; 906 u32 i; 907 908 for (i = 0; i < agg_bufs; i++) { 909 u16 cons, frag_len; 910 struct rx_agg_cmp *agg; 911 struct bnxt_sw_rx_agg_bd *cons_rx_buf; 912 struct page *page; 913 dma_addr_t mapping; 914 915 agg = (struct rx_agg_cmp *) 916 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 917 cons = agg->rx_agg_cmp_opaque; 918 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) & 919 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT; 920 921 cons_rx_buf = &rxr->rx_agg_ring[cons]; 922 skb_fill_page_desc(skb, i, cons_rx_buf->page, 923 cons_rx_buf->offset, frag_len); 924 __clear_bit(cons, rxr->rx_agg_bmap); 925 926 /* It is possible for bnxt_alloc_rx_page() to allocate 927 * a sw_prod index that equals the cons index, so we 928 * need to clear the cons entry now. 929 */ 930 mapping = cons_rx_buf->mapping; 931 page = cons_rx_buf->page; 932 cons_rx_buf->page = NULL; 933 934 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) { 935 struct skb_shared_info *shinfo; 936 unsigned int nr_frags; 937 938 shinfo = skb_shinfo(skb); 939 nr_frags = --shinfo->nr_frags; 940 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL); 941 942 dev_kfree_skb(skb); 943 944 cons_rx_buf->page = page; 945 946 /* Update prod since possibly some pages have been 947 * allocated already. 948 */ 949 rxr->rx_agg_prod = prod; 950 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i); 951 return NULL; 952 } 953 954 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE, 955 PCI_DMA_FROMDEVICE, 956 DMA_ATTR_WEAK_ORDERING); 957 958 skb->data_len += frag_len; 959 skb->len += frag_len; 960 skb->truesize += PAGE_SIZE; 961 962 prod = NEXT_RX_AGG(prod); 963 cp_cons = NEXT_CMP(cp_cons); 964 } 965 rxr->rx_agg_prod = prod; 966 return skb; 967 } 968 969 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 970 u8 agg_bufs, u32 *raw_cons) 971 { 972 u16 last; 973 struct rx_agg_cmp *agg; 974 975 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs); 976 last = RING_CMP(*raw_cons); 977 agg = (struct rx_agg_cmp *) 978 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)]; 979 return RX_AGG_CMP_VALID(agg, *raw_cons); 980 } 981 982 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data, 983 unsigned int len, 984 dma_addr_t mapping) 985 { 986 struct bnxt *bp = bnapi->bp; 987 struct pci_dev *pdev = bp->pdev; 988 struct sk_buff *skb; 989 990 skb = napi_alloc_skb(&bnapi->napi, len); 991 if (!skb) 992 return NULL; 993 994 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh, 995 bp->rx_dir); 996 997 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN, 998 len + NET_IP_ALIGN); 999 1000 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh, 1001 bp->rx_dir); 1002 1003 skb_put(skb, len); 1004 return skb; 1005 } 1006 1007 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi, 1008 u32 *raw_cons, void *cmp) 1009 { 1010 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1011 struct rx_cmp *rxcmp = cmp; 1012 u32 tmp_raw_cons = *raw_cons; 1013 u8 cmp_type, agg_bufs = 0; 1014 1015 cmp_type = RX_CMP_TYPE(rxcmp); 1016 1017 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 1018 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & 1019 RX_CMP_AGG_BUFS) >> 1020 RX_CMP_AGG_BUFS_SHIFT; 1021 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1022 struct rx_tpa_end_cmp *tpa_end = cmp; 1023 1024 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & 1025 RX_TPA_END_CMP_AGG_BUFS) >> 1026 RX_TPA_END_CMP_AGG_BUFS_SHIFT; 1027 } 1028 1029 if (agg_bufs) { 1030 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1031 return -EBUSY; 1032 } 1033 *raw_cons = tmp_raw_cons; 1034 return 0; 1035 } 1036 1037 static void bnxt_queue_sp_work(struct bnxt *bp) 1038 { 1039 if (BNXT_PF(bp)) 1040 queue_work(bnxt_pf_wq, &bp->sp_task); 1041 else 1042 schedule_work(&bp->sp_task); 1043 } 1044 1045 static void bnxt_cancel_sp_work(struct bnxt *bp) 1046 { 1047 if (BNXT_PF(bp)) 1048 flush_workqueue(bnxt_pf_wq); 1049 else 1050 cancel_work_sync(&bp->sp_task); 1051 } 1052 1053 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) 1054 { 1055 if (!rxr->bnapi->in_reset) { 1056 rxr->bnapi->in_reset = true; 1057 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 1058 bnxt_queue_sp_work(bp); 1059 } 1060 rxr->rx_next_cons = 0xffff; 1061 } 1062 1063 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 1064 struct rx_tpa_start_cmp *tpa_start, 1065 struct rx_tpa_start_cmp_ext *tpa_start1) 1066 { 1067 u8 agg_id = TPA_START_AGG_ID(tpa_start); 1068 u16 cons, prod; 1069 struct bnxt_tpa_info *tpa_info; 1070 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 1071 struct rx_bd *prod_bd; 1072 dma_addr_t mapping; 1073 1074 cons = tpa_start->rx_tpa_start_cmp_opaque; 1075 prod = rxr->rx_prod; 1076 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1077 prod_rx_buf = &rxr->rx_buf_ring[prod]; 1078 tpa_info = &rxr->rx_tpa[agg_id]; 1079 1080 if (unlikely(cons != rxr->rx_next_cons)) { 1081 bnxt_sched_reset(bp, rxr); 1082 return; 1083 } 1084 /* Store cfa_code in tpa_info to use in tpa_end 1085 * completion processing. 1086 */ 1087 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1); 1088 prod_rx_buf->data = tpa_info->data; 1089 prod_rx_buf->data_ptr = tpa_info->data_ptr; 1090 1091 mapping = tpa_info->mapping; 1092 prod_rx_buf->mapping = mapping; 1093 1094 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 1095 1096 prod_bd->rx_bd_haddr = cpu_to_le64(mapping); 1097 1098 tpa_info->data = cons_rx_buf->data; 1099 tpa_info->data_ptr = cons_rx_buf->data_ptr; 1100 cons_rx_buf->data = NULL; 1101 tpa_info->mapping = cons_rx_buf->mapping; 1102 1103 tpa_info->len = 1104 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >> 1105 RX_TPA_START_CMP_LEN_SHIFT; 1106 if (likely(TPA_START_HASH_VALID(tpa_start))) { 1107 u32 hash_type = TPA_START_HASH_TYPE(tpa_start); 1108 1109 tpa_info->hash_type = PKT_HASH_TYPE_L4; 1110 tpa_info->gso_type = SKB_GSO_TCPV4; 1111 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1112 if (hash_type == 3) 1113 tpa_info->gso_type = SKB_GSO_TCPV6; 1114 tpa_info->rss_hash = 1115 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash); 1116 } else { 1117 tpa_info->hash_type = PKT_HASH_TYPE_NONE; 1118 tpa_info->gso_type = 0; 1119 if (netif_msg_rx_err(bp)) 1120 netdev_warn(bp->dev, "TPA packet without valid hash\n"); 1121 } 1122 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2); 1123 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata); 1124 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info); 1125 1126 rxr->rx_prod = NEXT_RX(prod); 1127 cons = NEXT_RX(cons); 1128 rxr->rx_next_cons = NEXT_RX(cons); 1129 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1130 1131 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data); 1132 rxr->rx_prod = NEXT_RX(rxr->rx_prod); 1133 cons_rx_buf->data = NULL; 1134 } 1135 1136 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi, 1137 u16 cp_cons, u32 agg_bufs) 1138 { 1139 if (agg_bufs) 1140 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs); 1141 } 1142 1143 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info, 1144 int payload_off, int tcp_ts, 1145 struct sk_buff *skb) 1146 { 1147 #ifdef CONFIG_INET 1148 struct tcphdr *th; 1149 int len, nw_off; 1150 u16 outer_ip_off, inner_ip_off, inner_mac_off; 1151 u32 hdr_info = tpa_info->hdr_info; 1152 bool loopback = false; 1153 1154 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); 1155 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); 1156 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); 1157 1158 /* If the packet is an internal loopback packet, the offsets will 1159 * have an extra 4 bytes. 1160 */ 1161 if (inner_mac_off == 4) { 1162 loopback = true; 1163 } else if (inner_mac_off > 4) { 1164 __be16 proto = *((__be16 *)(skb->data + inner_ip_off - 1165 ETH_HLEN - 2)); 1166 1167 /* We only support inner iPv4/ipv6. If we don't see the 1168 * correct protocol ID, it must be a loopback packet where 1169 * the offsets are off by 4. 1170 */ 1171 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6)) 1172 loopback = true; 1173 } 1174 if (loopback) { 1175 /* internal loopback packet, subtract all offsets by 4 */ 1176 inner_ip_off -= 4; 1177 inner_mac_off -= 4; 1178 outer_ip_off -= 4; 1179 } 1180 1181 nw_off = inner_ip_off - ETH_HLEN; 1182 skb_set_network_header(skb, nw_off); 1183 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) { 1184 struct ipv6hdr *iph = ipv6_hdr(skb); 1185 1186 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1187 len = skb->len - skb_transport_offset(skb); 1188 th = tcp_hdr(skb); 1189 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1190 } else { 1191 struct iphdr *iph = ip_hdr(skb); 1192 1193 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1194 len = skb->len - skb_transport_offset(skb); 1195 th = tcp_hdr(skb); 1196 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1197 } 1198 1199 if (inner_mac_off) { /* tunnel */ 1200 struct udphdr *uh = NULL; 1201 __be16 proto = *((__be16 *)(skb->data + outer_ip_off - 1202 ETH_HLEN - 2)); 1203 1204 if (proto == htons(ETH_P_IP)) { 1205 struct iphdr *iph = (struct iphdr *)skb->data; 1206 1207 if (iph->protocol == IPPROTO_UDP) 1208 uh = (struct udphdr *)(iph + 1); 1209 } else { 1210 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; 1211 1212 if (iph->nexthdr == IPPROTO_UDP) 1213 uh = (struct udphdr *)(iph + 1); 1214 } 1215 if (uh) { 1216 if (uh->check) 1217 skb_shinfo(skb)->gso_type |= 1218 SKB_GSO_UDP_TUNNEL_CSUM; 1219 else 1220 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; 1221 } 1222 } 1223 #endif 1224 return skb; 1225 } 1226 1227 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr)) 1228 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr)) 1229 1230 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info, 1231 int payload_off, int tcp_ts, 1232 struct sk_buff *skb) 1233 { 1234 #ifdef CONFIG_INET 1235 struct tcphdr *th; 1236 int len, nw_off, tcp_opt_len = 0; 1237 1238 if (tcp_ts) 1239 tcp_opt_len = 12; 1240 1241 if (tpa_info->gso_type == SKB_GSO_TCPV4) { 1242 struct iphdr *iph; 1243 1244 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len - 1245 ETH_HLEN; 1246 skb_set_network_header(skb, nw_off); 1247 iph = ip_hdr(skb); 1248 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1249 len = skb->len - skb_transport_offset(skb); 1250 th = tcp_hdr(skb); 1251 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1252 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) { 1253 struct ipv6hdr *iph; 1254 1255 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len - 1256 ETH_HLEN; 1257 skb_set_network_header(skb, nw_off); 1258 iph = ipv6_hdr(skb); 1259 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1260 len = skb->len - skb_transport_offset(skb); 1261 th = tcp_hdr(skb); 1262 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1263 } else { 1264 dev_kfree_skb_any(skb); 1265 return NULL; 1266 } 1267 1268 if (nw_off) { /* tunnel */ 1269 struct udphdr *uh = NULL; 1270 1271 if (skb->protocol == htons(ETH_P_IP)) { 1272 struct iphdr *iph = (struct iphdr *)skb->data; 1273 1274 if (iph->protocol == IPPROTO_UDP) 1275 uh = (struct udphdr *)(iph + 1); 1276 } else { 1277 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; 1278 1279 if (iph->nexthdr == IPPROTO_UDP) 1280 uh = (struct udphdr *)(iph + 1); 1281 } 1282 if (uh) { 1283 if (uh->check) 1284 skb_shinfo(skb)->gso_type |= 1285 SKB_GSO_UDP_TUNNEL_CSUM; 1286 else 1287 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; 1288 } 1289 } 1290 #endif 1291 return skb; 1292 } 1293 1294 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp, 1295 struct bnxt_tpa_info *tpa_info, 1296 struct rx_tpa_end_cmp *tpa_end, 1297 struct rx_tpa_end_cmp_ext *tpa_end1, 1298 struct sk_buff *skb) 1299 { 1300 #ifdef CONFIG_INET 1301 int payload_off; 1302 u16 segs; 1303 1304 segs = TPA_END_TPA_SEGS(tpa_end); 1305 if (segs == 1) 1306 return skb; 1307 1308 NAPI_GRO_CB(skb)->count = segs; 1309 skb_shinfo(skb)->gso_size = 1310 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len); 1311 skb_shinfo(skb)->gso_type = tpa_info->gso_type; 1312 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & 1313 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> 1314 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT; 1315 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb); 1316 if (likely(skb)) 1317 tcp_gro_complete(skb); 1318 #endif 1319 return skb; 1320 } 1321 1322 /* Given the cfa_code of a received packet determine which 1323 * netdev (vf-rep or PF) the packet is destined to. 1324 */ 1325 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code) 1326 { 1327 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code); 1328 1329 /* if vf-rep dev is NULL, the must belongs to the PF */ 1330 return dev ? dev : bp->dev; 1331 } 1332 1333 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp, 1334 struct bnxt_napi *bnapi, 1335 u32 *raw_cons, 1336 struct rx_tpa_end_cmp *tpa_end, 1337 struct rx_tpa_end_cmp_ext *tpa_end1, 1338 u8 *event) 1339 { 1340 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1341 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1342 u8 agg_id = TPA_END_AGG_ID(tpa_end); 1343 u8 *data_ptr, agg_bufs; 1344 u16 cp_cons = RING_CMP(*raw_cons); 1345 unsigned int len; 1346 struct bnxt_tpa_info *tpa_info; 1347 dma_addr_t mapping; 1348 struct sk_buff *skb; 1349 void *data; 1350 1351 if (unlikely(bnapi->in_reset)) { 1352 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end); 1353 1354 if (rc < 0) 1355 return ERR_PTR(-EBUSY); 1356 return NULL; 1357 } 1358 1359 tpa_info = &rxr->rx_tpa[agg_id]; 1360 data = tpa_info->data; 1361 data_ptr = tpa_info->data_ptr; 1362 prefetch(data_ptr); 1363 len = tpa_info->len; 1364 mapping = tpa_info->mapping; 1365 1366 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & 1367 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT; 1368 1369 if (agg_bufs) { 1370 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons)) 1371 return ERR_PTR(-EBUSY); 1372 1373 *event |= BNXT_AGG_EVENT; 1374 cp_cons = NEXT_CMP(cp_cons); 1375 } 1376 1377 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) { 1378 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); 1379 if (agg_bufs > MAX_SKB_FRAGS) 1380 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n", 1381 agg_bufs, (int)MAX_SKB_FRAGS); 1382 return NULL; 1383 } 1384 1385 if (len <= bp->rx_copy_thresh) { 1386 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping); 1387 if (!skb) { 1388 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); 1389 return NULL; 1390 } 1391 } else { 1392 u8 *new_data; 1393 dma_addr_t new_mapping; 1394 1395 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC); 1396 if (!new_data) { 1397 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); 1398 return NULL; 1399 } 1400 1401 tpa_info->data = new_data; 1402 tpa_info->data_ptr = new_data + bp->rx_offset; 1403 tpa_info->mapping = new_mapping; 1404 1405 skb = build_skb(data, 0); 1406 dma_unmap_single_attrs(&bp->pdev->dev, mapping, 1407 bp->rx_buf_use_size, bp->rx_dir, 1408 DMA_ATTR_WEAK_ORDERING); 1409 1410 if (!skb) { 1411 kfree(data); 1412 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); 1413 return NULL; 1414 } 1415 skb_reserve(skb, bp->rx_offset); 1416 skb_put(skb, len); 1417 } 1418 1419 if (agg_bufs) { 1420 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs); 1421 if (!skb) { 1422 /* Page reuse already handled by bnxt_rx_pages(). */ 1423 return NULL; 1424 } 1425 } 1426 1427 skb->protocol = 1428 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code)); 1429 1430 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE) 1431 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type); 1432 1433 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) && 1434 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1435 u16 vlan_proto = tpa_info->metadata >> 1436 RX_CMP_FLAGS2_METADATA_TPID_SFT; 1437 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK; 1438 1439 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); 1440 } 1441 1442 skb_checksum_none_assert(skb); 1443 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) { 1444 skb->ip_summed = CHECKSUM_UNNECESSARY; 1445 skb->csum_level = 1446 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3; 1447 } 1448 1449 if (TPA_END_GRO(tpa_end)) 1450 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb); 1451 1452 return skb; 1453 } 1454 1455 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi, 1456 struct sk_buff *skb) 1457 { 1458 if (skb->dev != bp->dev) { 1459 /* this packet belongs to a vf-rep */ 1460 bnxt_vf_rep_rx(bp, skb); 1461 return; 1462 } 1463 skb_record_rx_queue(skb, bnapi->index); 1464 napi_gro_receive(&bnapi->napi, skb); 1465 } 1466 1467 /* returns the following: 1468 * 1 - 1 packet successfully received 1469 * 0 - successful TPA_START, packet not completed yet 1470 * -EBUSY - completion ring does not have all the agg buffers yet 1471 * -ENOMEM - packet aborted due to out of memory 1472 * -EIO - packet aborted due to hw error indicated in BD 1473 */ 1474 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons, 1475 u8 *event) 1476 { 1477 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1478 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1479 struct net_device *dev = bp->dev; 1480 struct rx_cmp *rxcmp; 1481 struct rx_cmp_ext *rxcmp1; 1482 u32 tmp_raw_cons = *raw_cons; 1483 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons); 1484 struct bnxt_sw_rx_bd *rx_buf; 1485 unsigned int len; 1486 u8 *data_ptr, agg_bufs, cmp_type; 1487 dma_addr_t dma_addr; 1488 struct sk_buff *skb; 1489 void *data; 1490 int rc = 0; 1491 u32 misc; 1492 1493 rxcmp = (struct rx_cmp *) 1494 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1495 1496 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1497 cp_cons = RING_CMP(tmp_raw_cons); 1498 rxcmp1 = (struct rx_cmp_ext *) 1499 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1500 1501 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1502 return -EBUSY; 1503 1504 cmp_type = RX_CMP_TYPE(rxcmp); 1505 1506 prod = rxr->rx_prod; 1507 1508 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) { 1509 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp, 1510 (struct rx_tpa_start_cmp_ext *)rxcmp1); 1511 1512 *event |= BNXT_RX_EVENT; 1513 goto next_rx_no_prod; 1514 1515 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1516 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons, 1517 (struct rx_tpa_end_cmp *)rxcmp, 1518 (struct rx_tpa_end_cmp_ext *)rxcmp1, event); 1519 1520 if (IS_ERR(skb)) 1521 return -EBUSY; 1522 1523 rc = -ENOMEM; 1524 if (likely(skb)) { 1525 bnxt_deliver_skb(bp, bnapi, skb); 1526 rc = 1; 1527 } 1528 *event |= BNXT_RX_EVENT; 1529 goto next_rx_no_prod; 1530 } 1531 1532 cons = rxcmp->rx_cmp_opaque; 1533 rx_buf = &rxr->rx_buf_ring[cons]; 1534 data = rx_buf->data; 1535 data_ptr = rx_buf->data_ptr; 1536 if (unlikely(cons != rxr->rx_next_cons)) { 1537 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp); 1538 1539 bnxt_sched_reset(bp, rxr); 1540 return rc1; 1541 } 1542 prefetch(data_ptr); 1543 1544 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1); 1545 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT; 1546 1547 if (agg_bufs) { 1548 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1549 return -EBUSY; 1550 1551 cp_cons = NEXT_CMP(cp_cons); 1552 *event |= BNXT_AGG_EVENT; 1553 } 1554 *event |= BNXT_RX_EVENT; 1555 1556 rx_buf->data = NULL; 1557 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) { 1558 bnxt_reuse_rx_data(rxr, cons, data); 1559 if (agg_bufs) 1560 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs); 1561 1562 rc = -EIO; 1563 goto next_rx; 1564 } 1565 1566 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 1567 dma_addr = rx_buf->mapping; 1568 1569 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) { 1570 rc = 1; 1571 goto next_rx; 1572 } 1573 1574 if (len <= bp->rx_copy_thresh) { 1575 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr); 1576 bnxt_reuse_rx_data(rxr, cons, data); 1577 if (!skb) { 1578 rc = -ENOMEM; 1579 goto next_rx; 1580 } 1581 } else { 1582 u32 payload; 1583 1584 if (rx_buf->data_ptr == data_ptr) 1585 payload = misc & RX_CMP_PAYLOAD_OFFSET; 1586 else 1587 payload = 0; 1588 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr, 1589 payload | len); 1590 if (!skb) { 1591 rc = -ENOMEM; 1592 goto next_rx; 1593 } 1594 } 1595 1596 if (agg_bufs) { 1597 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs); 1598 if (!skb) { 1599 rc = -ENOMEM; 1600 goto next_rx; 1601 } 1602 } 1603 1604 if (RX_CMP_HASH_VALID(rxcmp)) { 1605 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp); 1606 enum pkt_hash_types type = PKT_HASH_TYPE_L4; 1607 1608 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1609 if (hash_type != 1 && hash_type != 3) 1610 type = PKT_HASH_TYPE_L3; 1611 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type); 1612 } 1613 1614 cfa_code = RX_CMP_CFA_CODE(rxcmp1); 1615 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code)); 1616 1617 if ((rxcmp1->rx_cmp_flags2 & 1618 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) && 1619 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1620 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data); 1621 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK; 1622 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT; 1623 1624 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); 1625 } 1626 1627 skb_checksum_none_assert(skb); 1628 if (RX_CMP_L4_CS_OK(rxcmp1)) { 1629 if (dev->features & NETIF_F_RXCSUM) { 1630 skb->ip_summed = CHECKSUM_UNNECESSARY; 1631 skb->csum_level = RX_CMP_ENCAP(rxcmp1); 1632 } 1633 } else { 1634 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) { 1635 if (dev->features & NETIF_F_RXCSUM) 1636 cpr->rx_l4_csum_errors++; 1637 } 1638 } 1639 1640 bnxt_deliver_skb(bp, bnapi, skb); 1641 rc = 1; 1642 1643 next_rx: 1644 rxr->rx_prod = NEXT_RX(prod); 1645 rxr->rx_next_cons = NEXT_RX(cons); 1646 1647 next_rx_no_prod: 1648 *raw_cons = tmp_raw_cons; 1649 1650 return rc; 1651 } 1652 1653 /* In netpoll mode, if we are using a combined completion ring, we need to 1654 * discard the rx packets and recycle the buffers. 1655 */ 1656 static int bnxt_force_rx_discard(struct bnxt *bp, struct bnxt_napi *bnapi, 1657 u32 *raw_cons, u8 *event) 1658 { 1659 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1660 u32 tmp_raw_cons = *raw_cons; 1661 struct rx_cmp_ext *rxcmp1; 1662 struct rx_cmp *rxcmp; 1663 u16 cp_cons; 1664 u8 cmp_type; 1665 1666 cp_cons = RING_CMP(tmp_raw_cons); 1667 rxcmp = (struct rx_cmp *) 1668 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1669 1670 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1671 cp_cons = RING_CMP(tmp_raw_cons); 1672 rxcmp1 = (struct rx_cmp_ext *) 1673 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1674 1675 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1676 return -EBUSY; 1677 1678 cmp_type = RX_CMP_TYPE(rxcmp); 1679 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 1680 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 1681 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 1682 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1683 struct rx_tpa_end_cmp_ext *tpa_end1; 1684 1685 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1; 1686 tpa_end1->rx_tpa_end_cmp_errors_v2 |= 1687 cpu_to_le32(RX_TPA_END_CMP_ERRORS); 1688 } 1689 return bnxt_rx_pkt(bp, bnapi, raw_cons, event); 1690 } 1691 1692 #define BNXT_GET_EVENT_PORT(data) \ 1693 ((data) & \ 1694 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK) 1695 1696 static int bnxt_async_event_process(struct bnxt *bp, 1697 struct hwrm_async_event_cmpl *cmpl) 1698 { 1699 u16 event_id = le16_to_cpu(cmpl->event_id); 1700 1701 /* TODO CHIMP_FW: Define event id's for link change, error etc */ 1702 switch (event_id) { 1703 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: { 1704 u32 data1 = le32_to_cpu(cmpl->event_data1); 1705 struct bnxt_link_info *link_info = &bp->link_info; 1706 1707 if (BNXT_VF(bp)) 1708 goto async_event_process_exit; 1709 if (data1 & 0x20000) { 1710 u16 fw_speed = link_info->force_link_speed; 1711 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed); 1712 1713 netdev_warn(bp->dev, "Link speed %d no longer supported\n", 1714 speed); 1715 } 1716 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event); 1717 /* fall thru */ 1718 } 1719 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE: 1720 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event); 1721 break; 1722 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD: 1723 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event); 1724 break; 1725 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: { 1726 u32 data1 = le32_to_cpu(cmpl->event_data1); 1727 u16 port_id = BNXT_GET_EVENT_PORT(data1); 1728 1729 if (BNXT_VF(bp)) 1730 break; 1731 1732 if (bp->pf.port_id != port_id) 1733 break; 1734 1735 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event); 1736 break; 1737 } 1738 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE: 1739 if (BNXT_PF(bp)) 1740 goto async_event_process_exit; 1741 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event); 1742 break; 1743 default: 1744 goto async_event_process_exit; 1745 } 1746 bnxt_queue_sp_work(bp); 1747 async_event_process_exit: 1748 bnxt_ulp_async_events(bp, cmpl); 1749 return 0; 1750 } 1751 1752 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp) 1753 { 1754 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id; 1755 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp; 1756 struct hwrm_fwd_req_cmpl *fwd_req_cmpl = 1757 (struct hwrm_fwd_req_cmpl *)txcmp; 1758 1759 switch (cmpl_type) { 1760 case CMPL_BASE_TYPE_HWRM_DONE: 1761 seq_id = le16_to_cpu(h_cmpl->sequence_id); 1762 if (seq_id == bp->hwrm_intr_seq_id) 1763 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID; 1764 else 1765 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id); 1766 break; 1767 1768 case CMPL_BASE_TYPE_HWRM_FWD_REQ: 1769 vf_id = le16_to_cpu(fwd_req_cmpl->source_id); 1770 1771 if ((vf_id < bp->pf.first_vf_id) || 1772 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) { 1773 netdev_err(bp->dev, "Msg contains invalid VF id %x\n", 1774 vf_id); 1775 return -EINVAL; 1776 } 1777 1778 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap); 1779 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event); 1780 bnxt_queue_sp_work(bp); 1781 break; 1782 1783 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: 1784 bnxt_async_event_process(bp, 1785 (struct hwrm_async_event_cmpl *)txcmp); 1786 1787 default: 1788 break; 1789 } 1790 1791 return 0; 1792 } 1793 1794 static irqreturn_t bnxt_msix(int irq, void *dev_instance) 1795 { 1796 struct bnxt_napi *bnapi = dev_instance; 1797 struct bnxt *bp = bnapi->bp; 1798 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1799 u32 cons = RING_CMP(cpr->cp_raw_cons); 1800 1801 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 1802 napi_schedule(&bnapi->napi); 1803 return IRQ_HANDLED; 1804 } 1805 1806 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) 1807 { 1808 u32 raw_cons = cpr->cp_raw_cons; 1809 u16 cons = RING_CMP(raw_cons); 1810 struct tx_cmp *txcmp; 1811 1812 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 1813 1814 return TX_CMP_VALID(txcmp, raw_cons); 1815 } 1816 1817 static irqreturn_t bnxt_inta(int irq, void *dev_instance) 1818 { 1819 struct bnxt_napi *bnapi = dev_instance; 1820 struct bnxt *bp = bnapi->bp; 1821 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1822 u32 cons = RING_CMP(cpr->cp_raw_cons); 1823 u32 int_status; 1824 1825 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 1826 1827 if (!bnxt_has_work(bp, cpr)) { 1828 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS); 1829 /* return if erroneous interrupt */ 1830 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id))) 1831 return IRQ_NONE; 1832 } 1833 1834 /* disable ring IRQ */ 1835 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell); 1836 1837 /* Return here if interrupt is shared and is disabled. */ 1838 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 1839 return IRQ_HANDLED; 1840 1841 napi_schedule(&bnapi->napi); 1842 return IRQ_HANDLED; 1843 } 1844 1845 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget) 1846 { 1847 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1848 u32 raw_cons = cpr->cp_raw_cons; 1849 u32 cons; 1850 int tx_pkts = 0; 1851 int rx_pkts = 0; 1852 u8 event = 0; 1853 struct tx_cmp *txcmp; 1854 1855 while (1) { 1856 int rc; 1857 1858 cons = RING_CMP(raw_cons); 1859 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 1860 1861 if (!TX_CMP_VALID(txcmp, raw_cons)) 1862 break; 1863 1864 /* The valid test of the entry must be done first before 1865 * reading any further. 1866 */ 1867 dma_rmb(); 1868 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) { 1869 tx_pkts++; 1870 /* return full budget so NAPI will complete. */ 1871 if (unlikely(tx_pkts > bp->tx_wake_thresh)) 1872 rx_pkts = budget; 1873 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 1874 if (likely(budget)) 1875 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event); 1876 else 1877 rc = bnxt_force_rx_discard(bp, bnapi, &raw_cons, 1878 &event); 1879 if (likely(rc >= 0)) 1880 rx_pkts += rc; 1881 /* Increment rx_pkts when rc is -ENOMEM to count towards 1882 * the NAPI budget. Otherwise, we may potentially loop 1883 * here forever if we consistently cannot allocate 1884 * buffers. 1885 */ 1886 else if (rc == -ENOMEM) 1887 rx_pkts++; 1888 else if (rc == -EBUSY) /* partial completion */ 1889 break; 1890 } else if (unlikely((TX_CMP_TYPE(txcmp) == 1891 CMPL_BASE_TYPE_HWRM_DONE) || 1892 (TX_CMP_TYPE(txcmp) == 1893 CMPL_BASE_TYPE_HWRM_FWD_REQ) || 1894 (TX_CMP_TYPE(txcmp) == 1895 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) { 1896 bnxt_hwrm_handler(bp, txcmp); 1897 } 1898 raw_cons = NEXT_RAW_CMP(raw_cons); 1899 1900 if (rx_pkts == budget) 1901 break; 1902 } 1903 1904 if (event & BNXT_TX_EVENT) { 1905 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 1906 void __iomem *db = txr->tx_doorbell; 1907 u16 prod = txr->tx_prod; 1908 1909 /* Sync BD data before updating doorbell */ 1910 wmb(); 1911 1912 bnxt_db_write(bp, db, DB_KEY_TX | prod); 1913 } 1914 1915 cpr->cp_raw_cons = raw_cons; 1916 /* ACK completion ring before freeing tx ring and producing new 1917 * buffers in rx/agg rings to prevent overflowing the completion 1918 * ring. 1919 */ 1920 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); 1921 1922 if (tx_pkts) 1923 bnapi->tx_int(bp, bnapi, tx_pkts); 1924 1925 if (event & BNXT_RX_EVENT) { 1926 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1927 1928 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod); 1929 if (event & BNXT_AGG_EVENT) 1930 bnxt_db_write(bp, rxr->rx_agg_doorbell, 1931 DB_KEY_RX | rxr->rx_agg_prod); 1932 } 1933 return rx_pkts; 1934 } 1935 1936 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget) 1937 { 1938 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 1939 struct bnxt *bp = bnapi->bp; 1940 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1941 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1942 struct tx_cmp *txcmp; 1943 struct rx_cmp_ext *rxcmp1; 1944 u32 cp_cons, tmp_raw_cons; 1945 u32 raw_cons = cpr->cp_raw_cons; 1946 u32 rx_pkts = 0; 1947 u8 event = 0; 1948 1949 while (1) { 1950 int rc; 1951 1952 cp_cons = RING_CMP(raw_cons); 1953 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1954 1955 if (!TX_CMP_VALID(txcmp, raw_cons)) 1956 break; 1957 1958 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 1959 tmp_raw_cons = NEXT_RAW_CMP(raw_cons); 1960 cp_cons = RING_CMP(tmp_raw_cons); 1961 rxcmp1 = (struct rx_cmp_ext *) 1962 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1963 1964 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1965 break; 1966 1967 /* force an error to recycle the buffer */ 1968 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 1969 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 1970 1971 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event); 1972 if (likely(rc == -EIO)) 1973 rx_pkts++; 1974 else if (rc == -EBUSY) /* partial completion */ 1975 break; 1976 } else if (unlikely(TX_CMP_TYPE(txcmp) == 1977 CMPL_BASE_TYPE_HWRM_DONE)) { 1978 bnxt_hwrm_handler(bp, txcmp); 1979 } else { 1980 netdev_err(bp->dev, 1981 "Invalid completion received on special ring\n"); 1982 } 1983 raw_cons = NEXT_RAW_CMP(raw_cons); 1984 1985 if (rx_pkts == budget) 1986 break; 1987 } 1988 1989 cpr->cp_raw_cons = raw_cons; 1990 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); 1991 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod); 1992 1993 if (event & BNXT_AGG_EVENT) 1994 bnxt_db_write(bp, rxr->rx_agg_doorbell, 1995 DB_KEY_RX | rxr->rx_agg_prod); 1996 1997 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) { 1998 napi_complete_done(napi, rx_pkts); 1999 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons); 2000 } 2001 return rx_pkts; 2002 } 2003 2004 static int bnxt_poll(struct napi_struct *napi, int budget) 2005 { 2006 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2007 struct bnxt *bp = bnapi->bp; 2008 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2009 int work_done = 0; 2010 2011 while (1) { 2012 work_done += bnxt_poll_work(bp, bnapi, budget - work_done); 2013 2014 if (work_done >= budget) 2015 break; 2016 2017 if (!bnxt_has_work(bp, cpr)) { 2018 if (napi_complete_done(napi, work_done)) 2019 BNXT_CP_DB_REARM(cpr->cp_doorbell, 2020 cpr->cp_raw_cons); 2021 break; 2022 } 2023 } 2024 mmiowb(); 2025 return work_done; 2026 } 2027 2028 static void bnxt_free_tx_skbs(struct bnxt *bp) 2029 { 2030 int i, max_idx; 2031 struct pci_dev *pdev = bp->pdev; 2032 2033 if (!bp->tx_ring) 2034 return; 2035 2036 max_idx = bp->tx_nr_pages * TX_DESC_CNT; 2037 for (i = 0; i < bp->tx_nr_rings; i++) { 2038 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2039 int j; 2040 2041 for (j = 0; j < max_idx;) { 2042 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; 2043 struct sk_buff *skb = tx_buf->skb; 2044 int k, last; 2045 2046 if (!skb) { 2047 j++; 2048 continue; 2049 } 2050 2051 tx_buf->skb = NULL; 2052 2053 if (tx_buf->is_push) { 2054 dev_kfree_skb(skb); 2055 j += 2; 2056 continue; 2057 } 2058 2059 dma_unmap_single(&pdev->dev, 2060 dma_unmap_addr(tx_buf, mapping), 2061 skb_headlen(skb), 2062 PCI_DMA_TODEVICE); 2063 2064 last = tx_buf->nr_frags; 2065 j += 2; 2066 for (k = 0; k < last; k++, j++) { 2067 int ring_idx = j & bp->tx_ring_mask; 2068 skb_frag_t *frag = &skb_shinfo(skb)->frags[k]; 2069 2070 tx_buf = &txr->tx_buf_ring[ring_idx]; 2071 dma_unmap_page( 2072 &pdev->dev, 2073 dma_unmap_addr(tx_buf, mapping), 2074 skb_frag_size(frag), PCI_DMA_TODEVICE); 2075 } 2076 dev_kfree_skb(skb); 2077 } 2078 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); 2079 } 2080 } 2081 2082 static void bnxt_free_rx_skbs(struct bnxt *bp) 2083 { 2084 int i, max_idx, max_agg_idx; 2085 struct pci_dev *pdev = bp->pdev; 2086 2087 if (!bp->rx_ring) 2088 return; 2089 2090 max_idx = bp->rx_nr_pages * RX_DESC_CNT; 2091 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT; 2092 for (i = 0; i < bp->rx_nr_rings; i++) { 2093 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2094 int j; 2095 2096 if (rxr->rx_tpa) { 2097 for (j = 0; j < MAX_TPA; j++) { 2098 struct bnxt_tpa_info *tpa_info = 2099 &rxr->rx_tpa[j]; 2100 u8 *data = tpa_info->data; 2101 2102 if (!data) 2103 continue; 2104 2105 dma_unmap_single_attrs(&pdev->dev, 2106 tpa_info->mapping, 2107 bp->rx_buf_use_size, 2108 bp->rx_dir, 2109 DMA_ATTR_WEAK_ORDERING); 2110 2111 tpa_info->data = NULL; 2112 2113 kfree(data); 2114 } 2115 } 2116 2117 for (j = 0; j < max_idx; j++) { 2118 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j]; 2119 dma_addr_t mapping = rx_buf->mapping; 2120 void *data = rx_buf->data; 2121 2122 if (!data) 2123 continue; 2124 2125 rx_buf->data = NULL; 2126 2127 if (BNXT_RX_PAGE_MODE(bp)) { 2128 mapping -= bp->rx_dma_offset; 2129 dma_unmap_page_attrs(&pdev->dev, mapping, 2130 PAGE_SIZE, bp->rx_dir, 2131 DMA_ATTR_WEAK_ORDERING); 2132 __free_page(data); 2133 } else { 2134 dma_unmap_single_attrs(&pdev->dev, mapping, 2135 bp->rx_buf_use_size, 2136 bp->rx_dir, 2137 DMA_ATTR_WEAK_ORDERING); 2138 kfree(data); 2139 } 2140 } 2141 2142 for (j = 0; j < max_agg_idx; j++) { 2143 struct bnxt_sw_rx_agg_bd *rx_agg_buf = 2144 &rxr->rx_agg_ring[j]; 2145 struct page *page = rx_agg_buf->page; 2146 2147 if (!page) 2148 continue; 2149 2150 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping, 2151 BNXT_RX_PAGE_SIZE, 2152 PCI_DMA_FROMDEVICE, 2153 DMA_ATTR_WEAK_ORDERING); 2154 2155 rx_agg_buf->page = NULL; 2156 __clear_bit(j, rxr->rx_agg_bmap); 2157 2158 __free_page(page); 2159 } 2160 if (rxr->rx_page) { 2161 __free_page(rxr->rx_page); 2162 rxr->rx_page = NULL; 2163 } 2164 } 2165 } 2166 2167 static void bnxt_free_skbs(struct bnxt *bp) 2168 { 2169 bnxt_free_tx_skbs(bp); 2170 bnxt_free_rx_skbs(bp); 2171 } 2172 2173 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring) 2174 { 2175 struct pci_dev *pdev = bp->pdev; 2176 int i; 2177 2178 for (i = 0; i < ring->nr_pages; i++) { 2179 if (!ring->pg_arr[i]) 2180 continue; 2181 2182 dma_free_coherent(&pdev->dev, ring->page_size, 2183 ring->pg_arr[i], ring->dma_arr[i]); 2184 2185 ring->pg_arr[i] = NULL; 2186 } 2187 if (ring->pg_tbl) { 2188 dma_free_coherent(&pdev->dev, ring->nr_pages * 8, 2189 ring->pg_tbl, ring->pg_tbl_map); 2190 ring->pg_tbl = NULL; 2191 } 2192 if (ring->vmem_size && *ring->vmem) { 2193 vfree(*ring->vmem); 2194 *ring->vmem = NULL; 2195 } 2196 } 2197 2198 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring) 2199 { 2200 int i; 2201 struct pci_dev *pdev = bp->pdev; 2202 2203 if (ring->nr_pages > 1) { 2204 ring->pg_tbl = dma_alloc_coherent(&pdev->dev, 2205 ring->nr_pages * 8, 2206 &ring->pg_tbl_map, 2207 GFP_KERNEL); 2208 if (!ring->pg_tbl) 2209 return -ENOMEM; 2210 } 2211 2212 for (i = 0; i < ring->nr_pages; i++) { 2213 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev, 2214 ring->page_size, 2215 &ring->dma_arr[i], 2216 GFP_KERNEL); 2217 if (!ring->pg_arr[i]) 2218 return -ENOMEM; 2219 2220 if (ring->nr_pages > 1) 2221 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]); 2222 } 2223 2224 if (ring->vmem_size) { 2225 *ring->vmem = vzalloc(ring->vmem_size); 2226 if (!(*ring->vmem)) 2227 return -ENOMEM; 2228 } 2229 return 0; 2230 } 2231 2232 static void bnxt_free_rx_rings(struct bnxt *bp) 2233 { 2234 int i; 2235 2236 if (!bp->rx_ring) 2237 return; 2238 2239 for (i = 0; i < bp->rx_nr_rings; i++) { 2240 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2241 struct bnxt_ring_struct *ring; 2242 2243 if (rxr->xdp_prog) 2244 bpf_prog_put(rxr->xdp_prog); 2245 2246 kfree(rxr->rx_tpa); 2247 rxr->rx_tpa = NULL; 2248 2249 kfree(rxr->rx_agg_bmap); 2250 rxr->rx_agg_bmap = NULL; 2251 2252 ring = &rxr->rx_ring_struct; 2253 bnxt_free_ring(bp, ring); 2254 2255 ring = &rxr->rx_agg_ring_struct; 2256 bnxt_free_ring(bp, ring); 2257 } 2258 } 2259 2260 static int bnxt_alloc_rx_rings(struct bnxt *bp) 2261 { 2262 int i, rc, agg_rings = 0, tpa_rings = 0; 2263 2264 if (!bp->rx_ring) 2265 return -ENOMEM; 2266 2267 if (bp->flags & BNXT_FLAG_AGG_RINGS) 2268 agg_rings = 1; 2269 2270 if (bp->flags & BNXT_FLAG_TPA) 2271 tpa_rings = 1; 2272 2273 for (i = 0; i < bp->rx_nr_rings; i++) { 2274 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2275 struct bnxt_ring_struct *ring; 2276 2277 ring = &rxr->rx_ring_struct; 2278 2279 rc = bnxt_alloc_ring(bp, ring); 2280 if (rc) 2281 return rc; 2282 2283 if (agg_rings) { 2284 u16 mem_size; 2285 2286 ring = &rxr->rx_agg_ring_struct; 2287 rc = bnxt_alloc_ring(bp, ring); 2288 if (rc) 2289 return rc; 2290 2291 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1; 2292 mem_size = rxr->rx_agg_bmap_size / 8; 2293 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL); 2294 if (!rxr->rx_agg_bmap) 2295 return -ENOMEM; 2296 2297 if (tpa_rings) { 2298 rxr->rx_tpa = kcalloc(MAX_TPA, 2299 sizeof(struct bnxt_tpa_info), 2300 GFP_KERNEL); 2301 if (!rxr->rx_tpa) 2302 return -ENOMEM; 2303 } 2304 } 2305 } 2306 return 0; 2307 } 2308 2309 static void bnxt_free_tx_rings(struct bnxt *bp) 2310 { 2311 int i; 2312 struct pci_dev *pdev = bp->pdev; 2313 2314 if (!bp->tx_ring) 2315 return; 2316 2317 for (i = 0; i < bp->tx_nr_rings; i++) { 2318 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2319 struct bnxt_ring_struct *ring; 2320 2321 if (txr->tx_push) { 2322 dma_free_coherent(&pdev->dev, bp->tx_push_size, 2323 txr->tx_push, txr->tx_push_mapping); 2324 txr->tx_push = NULL; 2325 } 2326 2327 ring = &txr->tx_ring_struct; 2328 2329 bnxt_free_ring(bp, ring); 2330 } 2331 } 2332 2333 static int bnxt_alloc_tx_rings(struct bnxt *bp) 2334 { 2335 int i, j, rc; 2336 struct pci_dev *pdev = bp->pdev; 2337 2338 bp->tx_push_size = 0; 2339 if (bp->tx_push_thresh) { 2340 int push_size; 2341 2342 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) + 2343 bp->tx_push_thresh); 2344 2345 if (push_size > 256) { 2346 push_size = 0; 2347 bp->tx_push_thresh = 0; 2348 } 2349 2350 bp->tx_push_size = push_size; 2351 } 2352 2353 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) { 2354 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2355 struct bnxt_ring_struct *ring; 2356 2357 ring = &txr->tx_ring_struct; 2358 2359 rc = bnxt_alloc_ring(bp, ring); 2360 if (rc) 2361 return rc; 2362 2363 if (bp->tx_push_size) { 2364 dma_addr_t mapping; 2365 2366 /* One pre-allocated DMA buffer to backup 2367 * TX push operation 2368 */ 2369 txr->tx_push = dma_alloc_coherent(&pdev->dev, 2370 bp->tx_push_size, 2371 &txr->tx_push_mapping, 2372 GFP_KERNEL); 2373 2374 if (!txr->tx_push) 2375 return -ENOMEM; 2376 2377 mapping = txr->tx_push_mapping + 2378 sizeof(struct tx_push_bd); 2379 txr->data_mapping = cpu_to_le64(mapping); 2380 2381 memset(txr->tx_push, 0, sizeof(struct tx_push_bd)); 2382 } 2383 ring->queue_id = bp->q_info[j].queue_id; 2384 if (i < bp->tx_nr_rings_xdp) 2385 continue; 2386 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1)) 2387 j++; 2388 } 2389 return 0; 2390 } 2391 2392 static void bnxt_free_cp_rings(struct bnxt *bp) 2393 { 2394 int i; 2395 2396 if (!bp->bnapi) 2397 return; 2398 2399 for (i = 0; i < bp->cp_nr_rings; i++) { 2400 struct bnxt_napi *bnapi = bp->bnapi[i]; 2401 struct bnxt_cp_ring_info *cpr; 2402 struct bnxt_ring_struct *ring; 2403 2404 if (!bnapi) 2405 continue; 2406 2407 cpr = &bnapi->cp_ring; 2408 ring = &cpr->cp_ring_struct; 2409 2410 bnxt_free_ring(bp, ring); 2411 } 2412 } 2413 2414 static int bnxt_alloc_cp_rings(struct bnxt *bp) 2415 { 2416 int i, rc; 2417 2418 for (i = 0; i < bp->cp_nr_rings; i++) { 2419 struct bnxt_napi *bnapi = bp->bnapi[i]; 2420 struct bnxt_cp_ring_info *cpr; 2421 struct bnxt_ring_struct *ring; 2422 2423 if (!bnapi) 2424 continue; 2425 2426 cpr = &bnapi->cp_ring; 2427 ring = &cpr->cp_ring_struct; 2428 2429 rc = bnxt_alloc_ring(bp, ring); 2430 if (rc) 2431 return rc; 2432 } 2433 return 0; 2434 } 2435 2436 static void bnxt_init_ring_struct(struct bnxt *bp) 2437 { 2438 int i; 2439 2440 for (i = 0; i < bp->cp_nr_rings; i++) { 2441 struct bnxt_napi *bnapi = bp->bnapi[i]; 2442 struct bnxt_cp_ring_info *cpr; 2443 struct bnxt_rx_ring_info *rxr; 2444 struct bnxt_tx_ring_info *txr; 2445 struct bnxt_ring_struct *ring; 2446 2447 if (!bnapi) 2448 continue; 2449 2450 cpr = &bnapi->cp_ring; 2451 ring = &cpr->cp_ring_struct; 2452 ring->nr_pages = bp->cp_nr_pages; 2453 ring->page_size = HW_CMPD_RING_SIZE; 2454 ring->pg_arr = (void **)cpr->cp_desc_ring; 2455 ring->dma_arr = cpr->cp_desc_mapping; 2456 ring->vmem_size = 0; 2457 2458 rxr = bnapi->rx_ring; 2459 if (!rxr) 2460 goto skip_rx; 2461 2462 ring = &rxr->rx_ring_struct; 2463 ring->nr_pages = bp->rx_nr_pages; 2464 ring->page_size = HW_RXBD_RING_SIZE; 2465 ring->pg_arr = (void **)rxr->rx_desc_ring; 2466 ring->dma_arr = rxr->rx_desc_mapping; 2467 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages; 2468 ring->vmem = (void **)&rxr->rx_buf_ring; 2469 2470 ring = &rxr->rx_agg_ring_struct; 2471 ring->nr_pages = bp->rx_agg_nr_pages; 2472 ring->page_size = HW_RXBD_RING_SIZE; 2473 ring->pg_arr = (void **)rxr->rx_agg_desc_ring; 2474 ring->dma_arr = rxr->rx_agg_desc_mapping; 2475 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages; 2476 ring->vmem = (void **)&rxr->rx_agg_ring; 2477 2478 skip_rx: 2479 txr = bnapi->tx_ring; 2480 if (!txr) 2481 continue; 2482 2483 ring = &txr->tx_ring_struct; 2484 ring->nr_pages = bp->tx_nr_pages; 2485 ring->page_size = HW_RXBD_RING_SIZE; 2486 ring->pg_arr = (void **)txr->tx_desc_ring; 2487 ring->dma_arr = txr->tx_desc_mapping; 2488 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages; 2489 ring->vmem = (void **)&txr->tx_buf_ring; 2490 } 2491 } 2492 2493 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type) 2494 { 2495 int i; 2496 u32 prod; 2497 struct rx_bd **rx_buf_ring; 2498 2499 rx_buf_ring = (struct rx_bd **)ring->pg_arr; 2500 for (i = 0, prod = 0; i < ring->nr_pages; i++) { 2501 int j; 2502 struct rx_bd *rxbd; 2503 2504 rxbd = rx_buf_ring[i]; 2505 if (!rxbd) 2506 continue; 2507 2508 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) { 2509 rxbd->rx_bd_len_flags_type = cpu_to_le32(type); 2510 rxbd->rx_bd_opaque = prod; 2511 } 2512 } 2513 } 2514 2515 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr) 2516 { 2517 struct net_device *dev = bp->dev; 2518 struct bnxt_rx_ring_info *rxr; 2519 struct bnxt_ring_struct *ring; 2520 u32 prod, type; 2521 int i; 2522 2523 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) | 2524 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP; 2525 2526 if (NET_IP_ALIGN == 2) 2527 type |= RX_BD_FLAGS_SOP; 2528 2529 rxr = &bp->rx_ring[ring_nr]; 2530 ring = &rxr->rx_ring_struct; 2531 bnxt_init_rxbd_pages(ring, type); 2532 2533 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) { 2534 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1); 2535 if (IS_ERR(rxr->xdp_prog)) { 2536 int rc = PTR_ERR(rxr->xdp_prog); 2537 2538 rxr->xdp_prog = NULL; 2539 return rc; 2540 } 2541 } 2542 prod = rxr->rx_prod; 2543 for (i = 0; i < bp->rx_ring_size; i++) { 2544 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) { 2545 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n", 2546 ring_nr, i, bp->rx_ring_size); 2547 break; 2548 } 2549 prod = NEXT_RX(prod); 2550 } 2551 rxr->rx_prod = prod; 2552 ring->fw_ring_id = INVALID_HW_RING_ID; 2553 2554 ring = &rxr->rx_agg_ring_struct; 2555 ring->fw_ring_id = INVALID_HW_RING_ID; 2556 2557 if (!(bp->flags & BNXT_FLAG_AGG_RINGS)) 2558 return 0; 2559 2560 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) | 2561 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP; 2562 2563 bnxt_init_rxbd_pages(ring, type); 2564 2565 prod = rxr->rx_agg_prod; 2566 for (i = 0; i < bp->rx_agg_ring_size; i++) { 2567 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) { 2568 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n", 2569 ring_nr, i, bp->rx_ring_size); 2570 break; 2571 } 2572 prod = NEXT_RX_AGG(prod); 2573 } 2574 rxr->rx_agg_prod = prod; 2575 2576 if (bp->flags & BNXT_FLAG_TPA) { 2577 if (rxr->rx_tpa) { 2578 u8 *data; 2579 dma_addr_t mapping; 2580 2581 for (i = 0; i < MAX_TPA; i++) { 2582 data = __bnxt_alloc_rx_data(bp, &mapping, 2583 GFP_KERNEL); 2584 if (!data) 2585 return -ENOMEM; 2586 2587 rxr->rx_tpa[i].data = data; 2588 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset; 2589 rxr->rx_tpa[i].mapping = mapping; 2590 } 2591 } else { 2592 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n"); 2593 return -ENOMEM; 2594 } 2595 } 2596 2597 return 0; 2598 } 2599 2600 static void bnxt_init_cp_rings(struct bnxt *bp) 2601 { 2602 int i; 2603 2604 for (i = 0; i < bp->cp_nr_rings; i++) { 2605 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 2606 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 2607 2608 ring->fw_ring_id = INVALID_HW_RING_ID; 2609 } 2610 } 2611 2612 static int bnxt_init_rx_rings(struct bnxt *bp) 2613 { 2614 int i, rc = 0; 2615 2616 if (BNXT_RX_PAGE_MODE(bp)) { 2617 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM; 2618 bp->rx_dma_offset = XDP_PACKET_HEADROOM; 2619 } else { 2620 bp->rx_offset = BNXT_RX_OFFSET; 2621 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET; 2622 } 2623 2624 for (i = 0; i < bp->rx_nr_rings; i++) { 2625 rc = bnxt_init_one_rx_ring(bp, i); 2626 if (rc) 2627 break; 2628 } 2629 2630 return rc; 2631 } 2632 2633 static int bnxt_init_tx_rings(struct bnxt *bp) 2634 { 2635 u16 i; 2636 2637 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2, 2638 MAX_SKB_FRAGS + 1); 2639 2640 for (i = 0; i < bp->tx_nr_rings; i++) { 2641 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2642 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 2643 2644 ring->fw_ring_id = INVALID_HW_RING_ID; 2645 } 2646 2647 return 0; 2648 } 2649 2650 static void bnxt_free_ring_grps(struct bnxt *bp) 2651 { 2652 kfree(bp->grp_info); 2653 bp->grp_info = NULL; 2654 } 2655 2656 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init) 2657 { 2658 int i; 2659 2660 if (irq_re_init) { 2661 bp->grp_info = kcalloc(bp->cp_nr_rings, 2662 sizeof(struct bnxt_ring_grp_info), 2663 GFP_KERNEL); 2664 if (!bp->grp_info) 2665 return -ENOMEM; 2666 } 2667 for (i = 0; i < bp->cp_nr_rings; i++) { 2668 if (irq_re_init) 2669 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID; 2670 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 2671 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID; 2672 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID; 2673 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 2674 } 2675 return 0; 2676 } 2677 2678 static void bnxt_free_vnics(struct bnxt *bp) 2679 { 2680 kfree(bp->vnic_info); 2681 bp->vnic_info = NULL; 2682 bp->nr_vnics = 0; 2683 } 2684 2685 static int bnxt_alloc_vnics(struct bnxt *bp) 2686 { 2687 int num_vnics = 1; 2688 2689 #ifdef CONFIG_RFS_ACCEL 2690 if (bp->flags & BNXT_FLAG_RFS) 2691 num_vnics += bp->rx_nr_rings; 2692 #endif 2693 2694 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 2695 num_vnics++; 2696 2697 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info), 2698 GFP_KERNEL); 2699 if (!bp->vnic_info) 2700 return -ENOMEM; 2701 2702 bp->nr_vnics = num_vnics; 2703 return 0; 2704 } 2705 2706 static void bnxt_init_vnics(struct bnxt *bp) 2707 { 2708 int i; 2709 2710 for (i = 0; i < bp->nr_vnics; i++) { 2711 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2712 2713 vnic->fw_vnic_id = INVALID_HW_RING_ID; 2714 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID; 2715 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID; 2716 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID; 2717 2718 if (bp->vnic_info[i].rss_hash_key) { 2719 if (i == 0) 2720 prandom_bytes(vnic->rss_hash_key, 2721 HW_HASH_KEY_SIZE); 2722 else 2723 memcpy(vnic->rss_hash_key, 2724 bp->vnic_info[0].rss_hash_key, 2725 HW_HASH_KEY_SIZE); 2726 } 2727 } 2728 } 2729 2730 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg) 2731 { 2732 int pages; 2733 2734 pages = ring_size / desc_per_pg; 2735 2736 if (!pages) 2737 return 1; 2738 2739 pages++; 2740 2741 while (pages & (pages - 1)) 2742 pages++; 2743 2744 return pages; 2745 } 2746 2747 void bnxt_set_tpa_flags(struct bnxt *bp) 2748 { 2749 bp->flags &= ~BNXT_FLAG_TPA; 2750 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 2751 return; 2752 if (bp->dev->features & NETIF_F_LRO) 2753 bp->flags |= BNXT_FLAG_LRO; 2754 if (bp->dev->features & NETIF_F_GRO) 2755 bp->flags |= BNXT_FLAG_GRO; 2756 } 2757 2758 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must 2759 * be set on entry. 2760 */ 2761 void bnxt_set_ring_params(struct bnxt *bp) 2762 { 2763 u32 ring_size, rx_size, rx_space; 2764 u32 agg_factor = 0, agg_ring_size = 0; 2765 2766 /* 8 for CRC and VLAN */ 2767 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8); 2768 2769 rx_space = rx_size + NET_SKB_PAD + 2770 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 2771 2772 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH; 2773 ring_size = bp->rx_ring_size; 2774 bp->rx_agg_ring_size = 0; 2775 bp->rx_agg_nr_pages = 0; 2776 2777 if (bp->flags & BNXT_FLAG_TPA) 2778 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE); 2779 2780 bp->flags &= ~BNXT_FLAG_JUMBO; 2781 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) { 2782 u32 jumbo_factor; 2783 2784 bp->flags |= BNXT_FLAG_JUMBO; 2785 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; 2786 if (jumbo_factor > agg_factor) 2787 agg_factor = jumbo_factor; 2788 } 2789 agg_ring_size = ring_size * agg_factor; 2790 2791 if (agg_ring_size) { 2792 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size, 2793 RX_DESC_CNT); 2794 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) { 2795 u32 tmp = agg_ring_size; 2796 2797 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES; 2798 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1; 2799 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n", 2800 tmp, agg_ring_size); 2801 } 2802 bp->rx_agg_ring_size = agg_ring_size; 2803 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1; 2804 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN); 2805 rx_space = rx_size + NET_SKB_PAD + 2806 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 2807 } 2808 2809 bp->rx_buf_use_size = rx_size; 2810 bp->rx_buf_size = rx_space; 2811 2812 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT); 2813 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1; 2814 2815 ring_size = bp->tx_ring_size; 2816 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT); 2817 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1; 2818 2819 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size; 2820 bp->cp_ring_size = ring_size; 2821 2822 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT); 2823 if (bp->cp_nr_pages > MAX_CP_PAGES) { 2824 bp->cp_nr_pages = MAX_CP_PAGES; 2825 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1; 2826 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n", 2827 ring_size, bp->cp_ring_size); 2828 } 2829 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT; 2830 bp->cp_ring_mask = bp->cp_bit - 1; 2831 } 2832 2833 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode) 2834 { 2835 if (page_mode) { 2836 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU) 2837 return -EOPNOTSUPP; 2838 bp->dev->max_mtu = 2839 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU); 2840 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 2841 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE; 2842 bp->dev->hw_features &= ~NETIF_F_LRO; 2843 bp->dev->features &= ~NETIF_F_LRO; 2844 bp->rx_dir = DMA_BIDIRECTIONAL; 2845 bp->rx_skb_func = bnxt_rx_page_skb; 2846 } else { 2847 bp->dev->max_mtu = bp->max_mtu; 2848 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE; 2849 bp->rx_dir = DMA_FROM_DEVICE; 2850 bp->rx_skb_func = bnxt_rx_skb; 2851 } 2852 return 0; 2853 } 2854 2855 static void bnxt_free_vnic_attributes(struct bnxt *bp) 2856 { 2857 int i; 2858 struct bnxt_vnic_info *vnic; 2859 struct pci_dev *pdev = bp->pdev; 2860 2861 if (!bp->vnic_info) 2862 return; 2863 2864 for (i = 0; i < bp->nr_vnics; i++) { 2865 vnic = &bp->vnic_info[i]; 2866 2867 kfree(vnic->fw_grp_ids); 2868 vnic->fw_grp_ids = NULL; 2869 2870 kfree(vnic->uc_list); 2871 vnic->uc_list = NULL; 2872 2873 if (vnic->mc_list) { 2874 dma_free_coherent(&pdev->dev, vnic->mc_list_size, 2875 vnic->mc_list, vnic->mc_list_mapping); 2876 vnic->mc_list = NULL; 2877 } 2878 2879 if (vnic->rss_table) { 2880 dma_free_coherent(&pdev->dev, PAGE_SIZE, 2881 vnic->rss_table, 2882 vnic->rss_table_dma_addr); 2883 vnic->rss_table = NULL; 2884 } 2885 2886 vnic->rss_hash_key = NULL; 2887 vnic->flags = 0; 2888 } 2889 } 2890 2891 static int bnxt_alloc_vnic_attributes(struct bnxt *bp) 2892 { 2893 int i, rc = 0, size; 2894 struct bnxt_vnic_info *vnic; 2895 struct pci_dev *pdev = bp->pdev; 2896 int max_rings; 2897 2898 for (i = 0; i < bp->nr_vnics; i++) { 2899 vnic = &bp->vnic_info[i]; 2900 2901 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) { 2902 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN; 2903 2904 if (mem_size > 0) { 2905 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL); 2906 if (!vnic->uc_list) { 2907 rc = -ENOMEM; 2908 goto out; 2909 } 2910 } 2911 } 2912 2913 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) { 2914 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN; 2915 vnic->mc_list = 2916 dma_alloc_coherent(&pdev->dev, 2917 vnic->mc_list_size, 2918 &vnic->mc_list_mapping, 2919 GFP_KERNEL); 2920 if (!vnic->mc_list) { 2921 rc = -ENOMEM; 2922 goto out; 2923 } 2924 } 2925 2926 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 2927 max_rings = bp->rx_nr_rings; 2928 else 2929 max_rings = 1; 2930 2931 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL); 2932 if (!vnic->fw_grp_ids) { 2933 rc = -ENOMEM; 2934 goto out; 2935 } 2936 2937 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) && 2938 !(vnic->flags & BNXT_VNIC_RSS_FLAG)) 2939 continue; 2940 2941 /* Allocate rss table and hash key */ 2942 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 2943 &vnic->rss_table_dma_addr, 2944 GFP_KERNEL); 2945 if (!vnic->rss_table) { 2946 rc = -ENOMEM; 2947 goto out; 2948 } 2949 2950 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16)); 2951 2952 vnic->rss_hash_key = ((void *)vnic->rss_table) + size; 2953 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; 2954 } 2955 return 0; 2956 2957 out: 2958 return rc; 2959 } 2960 2961 static void bnxt_free_hwrm_resources(struct bnxt *bp) 2962 { 2963 struct pci_dev *pdev = bp->pdev; 2964 2965 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr, 2966 bp->hwrm_cmd_resp_dma_addr); 2967 2968 bp->hwrm_cmd_resp_addr = NULL; 2969 if (bp->hwrm_dbg_resp_addr) { 2970 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE, 2971 bp->hwrm_dbg_resp_addr, 2972 bp->hwrm_dbg_resp_dma_addr); 2973 2974 bp->hwrm_dbg_resp_addr = NULL; 2975 } 2976 } 2977 2978 static int bnxt_alloc_hwrm_resources(struct bnxt *bp) 2979 { 2980 struct pci_dev *pdev = bp->pdev; 2981 2982 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 2983 &bp->hwrm_cmd_resp_dma_addr, 2984 GFP_KERNEL); 2985 if (!bp->hwrm_cmd_resp_addr) 2986 return -ENOMEM; 2987 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev, 2988 HWRM_DBG_REG_BUF_SIZE, 2989 &bp->hwrm_dbg_resp_dma_addr, 2990 GFP_KERNEL); 2991 if (!bp->hwrm_dbg_resp_addr) 2992 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n"); 2993 2994 return 0; 2995 } 2996 2997 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp) 2998 { 2999 if (bp->hwrm_short_cmd_req_addr) { 3000 struct pci_dev *pdev = bp->pdev; 3001 3002 dma_free_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN, 3003 bp->hwrm_short_cmd_req_addr, 3004 bp->hwrm_short_cmd_req_dma_addr); 3005 bp->hwrm_short_cmd_req_addr = NULL; 3006 } 3007 } 3008 3009 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp) 3010 { 3011 struct pci_dev *pdev = bp->pdev; 3012 3013 bp->hwrm_short_cmd_req_addr = 3014 dma_alloc_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN, 3015 &bp->hwrm_short_cmd_req_dma_addr, 3016 GFP_KERNEL); 3017 if (!bp->hwrm_short_cmd_req_addr) 3018 return -ENOMEM; 3019 3020 return 0; 3021 } 3022 3023 static void bnxt_free_stats(struct bnxt *bp) 3024 { 3025 u32 size, i; 3026 struct pci_dev *pdev = bp->pdev; 3027 3028 if (bp->hw_rx_port_stats) { 3029 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size, 3030 bp->hw_rx_port_stats, 3031 bp->hw_rx_port_stats_map); 3032 bp->hw_rx_port_stats = NULL; 3033 bp->flags &= ~BNXT_FLAG_PORT_STATS; 3034 } 3035 3036 if (!bp->bnapi) 3037 return; 3038 3039 size = sizeof(struct ctx_hw_stats); 3040 3041 for (i = 0; i < bp->cp_nr_rings; i++) { 3042 struct bnxt_napi *bnapi = bp->bnapi[i]; 3043 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3044 3045 if (cpr->hw_stats) { 3046 dma_free_coherent(&pdev->dev, size, cpr->hw_stats, 3047 cpr->hw_stats_map); 3048 cpr->hw_stats = NULL; 3049 } 3050 } 3051 } 3052 3053 static int bnxt_alloc_stats(struct bnxt *bp) 3054 { 3055 u32 size, i; 3056 struct pci_dev *pdev = bp->pdev; 3057 3058 size = sizeof(struct ctx_hw_stats); 3059 3060 for (i = 0; i < bp->cp_nr_rings; i++) { 3061 struct bnxt_napi *bnapi = bp->bnapi[i]; 3062 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3063 3064 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size, 3065 &cpr->hw_stats_map, 3066 GFP_KERNEL); 3067 if (!cpr->hw_stats) 3068 return -ENOMEM; 3069 3070 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 3071 } 3072 3073 if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) { 3074 bp->hw_port_stats_size = sizeof(struct rx_port_stats) + 3075 sizeof(struct tx_port_stats) + 1024; 3076 3077 bp->hw_rx_port_stats = 3078 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size, 3079 &bp->hw_rx_port_stats_map, 3080 GFP_KERNEL); 3081 if (!bp->hw_rx_port_stats) 3082 return -ENOMEM; 3083 3084 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) + 3085 512; 3086 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map + 3087 sizeof(struct rx_port_stats) + 512; 3088 bp->flags |= BNXT_FLAG_PORT_STATS; 3089 } 3090 return 0; 3091 } 3092 3093 static void bnxt_clear_ring_indices(struct bnxt *bp) 3094 { 3095 int i; 3096 3097 if (!bp->bnapi) 3098 return; 3099 3100 for (i = 0; i < bp->cp_nr_rings; i++) { 3101 struct bnxt_napi *bnapi = bp->bnapi[i]; 3102 struct bnxt_cp_ring_info *cpr; 3103 struct bnxt_rx_ring_info *rxr; 3104 struct bnxt_tx_ring_info *txr; 3105 3106 if (!bnapi) 3107 continue; 3108 3109 cpr = &bnapi->cp_ring; 3110 cpr->cp_raw_cons = 0; 3111 3112 txr = bnapi->tx_ring; 3113 if (txr) { 3114 txr->tx_prod = 0; 3115 txr->tx_cons = 0; 3116 } 3117 3118 rxr = bnapi->rx_ring; 3119 if (rxr) { 3120 rxr->rx_prod = 0; 3121 rxr->rx_agg_prod = 0; 3122 rxr->rx_sw_agg_prod = 0; 3123 rxr->rx_next_cons = 0; 3124 } 3125 } 3126 } 3127 3128 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit) 3129 { 3130 #ifdef CONFIG_RFS_ACCEL 3131 int i; 3132 3133 /* Under rtnl_lock and all our NAPIs have been disabled. It's 3134 * safe to delete the hash table. 3135 */ 3136 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 3137 struct hlist_head *head; 3138 struct hlist_node *tmp; 3139 struct bnxt_ntuple_filter *fltr; 3140 3141 head = &bp->ntp_fltr_hash_tbl[i]; 3142 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 3143 hlist_del(&fltr->hash); 3144 kfree(fltr); 3145 } 3146 } 3147 if (irq_reinit) { 3148 kfree(bp->ntp_fltr_bmap); 3149 bp->ntp_fltr_bmap = NULL; 3150 } 3151 bp->ntp_fltr_count = 0; 3152 #endif 3153 } 3154 3155 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp) 3156 { 3157 #ifdef CONFIG_RFS_ACCEL 3158 int i, rc = 0; 3159 3160 if (!(bp->flags & BNXT_FLAG_RFS)) 3161 return 0; 3162 3163 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) 3164 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]); 3165 3166 bp->ntp_fltr_count = 0; 3167 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR), 3168 sizeof(long), 3169 GFP_KERNEL); 3170 3171 if (!bp->ntp_fltr_bmap) 3172 rc = -ENOMEM; 3173 3174 return rc; 3175 #else 3176 return 0; 3177 #endif 3178 } 3179 3180 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init) 3181 { 3182 bnxt_free_vnic_attributes(bp); 3183 bnxt_free_tx_rings(bp); 3184 bnxt_free_rx_rings(bp); 3185 bnxt_free_cp_rings(bp); 3186 bnxt_free_ntp_fltrs(bp, irq_re_init); 3187 if (irq_re_init) { 3188 bnxt_free_stats(bp); 3189 bnxt_free_ring_grps(bp); 3190 bnxt_free_vnics(bp); 3191 kfree(bp->tx_ring_map); 3192 bp->tx_ring_map = NULL; 3193 kfree(bp->tx_ring); 3194 bp->tx_ring = NULL; 3195 kfree(bp->rx_ring); 3196 bp->rx_ring = NULL; 3197 kfree(bp->bnapi); 3198 bp->bnapi = NULL; 3199 } else { 3200 bnxt_clear_ring_indices(bp); 3201 } 3202 } 3203 3204 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init) 3205 { 3206 int i, j, rc, size, arr_size; 3207 void *bnapi; 3208 3209 if (irq_re_init) { 3210 /* Allocate bnapi mem pointer array and mem block for 3211 * all queues 3212 */ 3213 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) * 3214 bp->cp_nr_rings); 3215 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi)); 3216 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL); 3217 if (!bnapi) 3218 return -ENOMEM; 3219 3220 bp->bnapi = bnapi; 3221 bnapi += arr_size; 3222 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) { 3223 bp->bnapi[i] = bnapi; 3224 bp->bnapi[i]->index = i; 3225 bp->bnapi[i]->bp = bp; 3226 } 3227 3228 bp->rx_ring = kcalloc(bp->rx_nr_rings, 3229 sizeof(struct bnxt_rx_ring_info), 3230 GFP_KERNEL); 3231 if (!bp->rx_ring) 3232 return -ENOMEM; 3233 3234 for (i = 0; i < bp->rx_nr_rings; i++) { 3235 bp->rx_ring[i].bnapi = bp->bnapi[i]; 3236 bp->bnapi[i]->rx_ring = &bp->rx_ring[i]; 3237 } 3238 3239 bp->tx_ring = kcalloc(bp->tx_nr_rings, 3240 sizeof(struct bnxt_tx_ring_info), 3241 GFP_KERNEL); 3242 if (!bp->tx_ring) 3243 return -ENOMEM; 3244 3245 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16), 3246 GFP_KERNEL); 3247 3248 if (!bp->tx_ring_map) 3249 return -ENOMEM; 3250 3251 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 3252 j = 0; 3253 else 3254 j = bp->rx_nr_rings; 3255 3256 for (i = 0; i < bp->tx_nr_rings; i++, j++) { 3257 bp->tx_ring[i].bnapi = bp->bnapi[j]; 3258 bp->bnapi[j]->tx_ring = &bp->tx_ring[i]; 3259 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i; 3260 if (i >= bp->tx_nr_rings_xdp) { 3261 bp->tx_ring[i].txq_index = i - 3262 bp->tx_nr_rings_xdp; 3263 bp->bnapi[j]->tx_int = bnxt_tx_int; 3264 } else { 3265 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP; 3266 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp; 3267 } 3268 } 3269 3270 rc = bnxt_alloc_stats(bp); 3271 if (rc) 3272 goto alloc_mem_err; 3273 3274 rc = bnxt_alloc_ntp_fltrs(bp); 3275 if (rc) 3276 goto alloc_mem_err; 3277 3278 rc = bnxt_alloc_vnics(bp); 3279 if (rc) 3280 goto alloc_mem_err; 3281 } 3282 3283 bnxt_init_ring_struct(bp); 3284 3285 rc = bnxt_alloc_rx_rings(bp); 3286 if (rc) 3287 goto alloc_mem_err; 3288 3289 rc = bnxt_alloc_tx_rings(bp); 3290 if (rc) 3291 goto alloc_mem_err; 3292 3293 rc = bnxt_alloc_cp_rings(bp); 3294 if (rc) 3295 goto alloc_mem_err; 3296 3297 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG | 3298 BNXT_VNIC_UCAST_FLAG; 3299 rc = bnxt_alloc_vnic_attributes(bp); 3300 if (rc) 3301 goto alloc_mem_err; 3302 return 0; 3303 3304 alloc_mem_err: 3305 bnxt_free_mem(bp, true); 3306 return rc; 3307 } 3308 3309 static void bnxt_disable_int(struct bnxt *bp) 3310 { 3311 int i; 3312 3313 if (!bp->bnapi) 3314 return; 3315 3316 for (i = 0; i < bp->cp_nr_rings; i++) { 3317 struct bnxt_napi *bnapi = bp->bnapi[i]; 3318 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3319 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 3320 3321 if (ring->fw_ring_id != INVALID_HW_RING_ID) 3322 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); 3323 } 3324 } 3325 3326 static void bnxt_disable_int_sync(struct bnxt *bp) 3327 { 3328 int i; 3329 3330 atomic_inc(&bp->intr_sem); 3331 3332 bnxt_disable_int(bp); 3333 for (i = 0; i < bp->cp_nr_rings; i++) 3334 synchronize_irq(bp->irq_tbl[i].vector); 3335 } 3336 3337 static void bnxt_enable_int(struct bnxt *bp) 3338 { 3339 int i; 3340 3341 atomic_set(&bp->intr_sem, 0); 3342 for (i = 0; i < bp->cp_nr_rings; i++) { 3343 struct bnxt_napi *bnapi = bp->bnapi[i]; 3344 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3345 3346 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons); 3347 } 3348 } 3349 3350 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type, 3351 u16 cmpl_ring, u16 target_id) 3352 { 3353 struct input *req = request; 3354 3355 req->req_type = cpu_to_le16(req_type); 3356 req->cmpl_ring = cpu_to_le16(cmpl_ring); 3357 req->target_id = cpu_to_le16(target_id); 3358 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr); 3359 } 3360 3361 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len, 3362 int timeout, bool silent) 3363 { 3364 int i, intr_process, rc, tmo_count; 3365 struct input *req = msg; 3366 u32 *data = msg; 3367 __le32 *resp_len, *valid; 3368 u16 cp_ring_id, len = 0; 3369 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr; 3370 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN; 3371 3372 req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++); 3373 memset(resp, 0, PAGE_SIZE); 3374 cp_ring_id = le16_to_cpu(req->cmpl_ring); 3375 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1; 3376 3377 if (bp->flags & BNXT_FLAG_SHORT_CMD) { 3378 void *short_cmd_req = bp->hwrm_short_cmd_req_addr; 3379 struct hwrm_short_input short_input = {0}; 3380 3381 memcpy(short_cmd_req, req, msg_len); 3382 memset(short_cmd_req + msg_len, 0, BNXT_HWRM_MAX_REQ_LEN - 3383 msg_len); 3384 3385 short_input.req_type = req->req_type; 3386 short_input.signature = 3387 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD); 3388 short_input.size = cpu_to_le16(msg_len); 3389 short_input.req_addr = 3390 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr); 3391 3392 data = (u32 *)&short_input; 3393 msg_len = sizeof(short_input); 3394 3395 /* Sync memory write before updating doorbell */ 3396 wmb(); 3397 3398 max_req_len = BNXT_HWRM_SHORT_REQ_LEN; 3399 } 3400 3401 /* Write request msg to hwrm channel */ 3402 __iowrite32_copy(bp->bar0, data, msg_len / 4); 3403 3404 for (i = msg_len; i < max_req_len; i += 4) 3405 writel(0, bp->bar0 + i); 3406 3407 /* currently supports only one outstanding message */ 3408 if (intr_process) 3409 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id); 3410 3411 /* Ring channel doorbell */ 3412 writel(1, bp->bar0 + 0x100); 3413 3414 if (!timeout) 3415 timeout = DFLT_HWRM_CMD_TIMEOUT; 3416 3417 i = 0; 3418 tmo_count = timeout * 40; 3419 if (intr_process) { 3420 /* Wait until hwrm response cmpl interrupt is processed */ 3421 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID && 3422 i++ < tmo_count) { 3423 usleep_range(25, 40); 3424 } 3425 3426 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) { 3427 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n", 3428 le16_to_cpu(req->req_type)); 3429 return -1; 3430 } 3431 } else { 3432 /* Check if response len is updated */ 3433 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET; 3434 for (i = 0; i < tmo_count; i++) { 3435 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >> 3436 HWRM_RESP_LEN_SFT; 3437 if (len) 3438 break; 3439 usleep_range(25, 40); 3440 } 3441 3442 if (i >= tmo_count) { 3443 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n", 3444 timeout, le16_to_cpu(req->req_type), 3445 le16_to_cpu(req->seq_id), len); 3446 return -1; 3447 } 3448 3449 /* Last word of resp contains valid bit */ 3450 valid = bp->hwrm_cmd_resp_addr + len - 4; 3451 for (i = 0; i < 5; i++) { 3452 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK) 3453 break; 3454 udelay(1); 3455 } 3456 3457 if (i >= 5) { 3458 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n", 3459 timeout, le16_to_cpu(req->req_type), 3460 le16_to_cpu(req->seq_id), len, *valid); 3461 return -1; 3462 } 3463 } 3464 3465 rc = le16_to_cpu(resp->error_code); 3466 if (rc && !silent) 3467 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n", 3468 le16_to_cpu(resp->req_type), 3469 le16_to_cpu(resp->seq_id), rc); 3470 return rc; 3471 } 3472 3473 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 3474 { 3475 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false); 3476 } 3477 3478 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, 3479 int timeout) 3480 { 3481 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); 3482 } 3483 3484 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 3485 { 3486 int rc; 3487 3488 mutex_lock(&bp->hwrm_cmd_lock); 3489 rc = _hwrm_send_message(bp, msg, msg_len, timeout); 3490 mutex_unlock(&bp->hwrm_cmd_lock); 3491 return rc; 3492 } 3493 3494 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, 3495 int timeout) 3496 { 3497 int rc; 3498 3499 mutex_lock(&bp->hwrm_cmd_lock); 3500 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); 3501 mutex_unlock(&bp->hwrm_cmd_lock); 3502 return rc; 3503 } 3504 3505 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap, 3506 int bmap_size) 3507 { 3508 struct hwrm_func_drv_rgtr_input req = {0}; 3509 DECLARE_BITMAP(async_events_bmap, 256); 3510 u32 *events = (u32 *)async_events_bmap; 3511 int i; 3512 3513 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); 3514 3515 req.enables = 3516 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); 3517 3518 memset(async_events_bmap, 0, sizeof(async_events_bmap)); 3519 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) 3520 __set_bit(bnxt_async_events_arr[i], async_events_bmap); 3521 3522 if (bmap && bmap_size) { 3523 for (i = 0; i < bmap_size; i++) { 3524 if (test_bit(i, bmap)) 3525 __set_bit(i, async_events_bmap); 3526 } 3527 } 3528 3529 for (i = 0; i < 8; i++) 3530 req.async_event_fwd[i] |= cpu_to_le32(events[i]); 3531 3532 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3533 } 3534 3535 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp) 3536 { 3537 struct hwrm_func_drv_rgtr_input req = {0}; 3538 3539 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); 3540 3541 req.enables = 3542 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE | 3543 FUNC_DRV_RGTR_REQ_ENABLES_VER); 3544 3545 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX); 3546 req.ver_maj = DRV_VER_MAJ; 3547 req.ver_min = DRV_VER_MIN; 3548 req.ver_upd = DRV_VER_UPD; 3549 3550 if (BNXT_PF(bp)) { 3551 u32 data[8]; 3552 int i; 3553 3554 memset(data, 0, sizeof(data)); 3555 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) { 3556 u16 cmd = bnxt_vf_req_snif[i]; 3557 unsigned int bit, idx; 3558 3559 idx = cmd / 32; 3560 bit = cmd % 32; 3561 data[idx] |= 1 << bit; 3562 } 3563 3564 for (i = 0; i < 8; i++) 3565 req.vf_req_fwd[i] = cpu_to_le32(data[i]); 3566 3567 req.enables |= 3568 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD); 3569 } 3570 3571 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3572 } 3573 3574 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp) 3575 { 3576 struct hwrm_func_drv_unrgtr_input req = {0}; 3577 3578 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1); 3579 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3580 } 3581 3582 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type) 3583 { 3584 u32 rc = 0; 3585 struct hwrm_tunnel_dst_port_free_input req = {0}; 3586 3587 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1); 3588 req.tunnel_type = tunnel_type; 3589 3590 switch (tunnel_type) { 3591 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN: 3592 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id; 3593 break; 3594 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE: 3595 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id; 3596 break; 3597 default: 3598 break; 3599 } 3600 3601 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3602 if (rc) 3603 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n", 3604 rc); 3605 return rc; 3606 } 3607 3608 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port, 3609 u8 tunnel_type) 3610 { 3611 u32 rc = 0; 3612 struct hwrm_tunnel_dst_port_alloc_input req = {0}; 3613 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr; 3614 3615 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1); 3616 3617 req.tunnel_type = tunnel_type; 3618 req.tunnel_dst_port_val = port; 3619 3620 mutex_lock(&bp->hwrm_cmd_lock); 3621 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3622 if (rc) { 3623 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n", 3624 rc); 3625 goto err_out; 3626 } 3627 3628 switch (tunnel_type) { 3629 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN: 3630 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id; 3631 break; 3632 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE: 3633 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id; 3634 break; 3635 default: 3636 break; 3637 } 3638 3639 err_out: 3640 mutex_unlock(&bp->hwrm_cmd_lock); 3641 return rc; 3642 } 3643 3644 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id) 3645 { 3646 struct hwrm_cfa_l2_set_rx_mask_input req = {0}; 3647 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3648 3649 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1); 3650 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 3651 3652 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count); 3653 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping); 3654 req.mask = cpu_to_le32(vnic->rx_mask); 3655 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3656 } 3657 3658 #ifdef CONFIG_RFS_ACCEL 3659 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp, 3660 struct bnxt_ntuple_filter *fltr) 3661 { 3662 struct hwrm_cfa_ntuple_filter_free_input req = {0}; 3663 3664 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1); 3665 req.ntuple_filter_id = fltr->filter_id; 3666 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3667 } 3668 3669 #define BNXT_NTP_FLTR_FLAGS \ 3670 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \ 3671 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \ 3672 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \ 3673 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \ 3674 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \ 3675 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \ 3676 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \ 3677 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \ 3678 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \ 3679 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \ 3680 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \ 3681 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \ 3682 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \ 3683 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID) 3684 3685 #define BNXT_NTP_TUNNEL_FLTR_FLAG \ 3686 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 3687 3688 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp, 3689 struct bnxt_ntuple_filter *fltr) 3690 { 3691 int rc = 0; 3692 struct hwrm_cfa_ntuple_filter_alloc_input req = {0}; 3693 struct hwrm_cfa_ntuple_filter_alloc_output *resp = 3694 bp->hwrm_cmd_resp_addr; 3695 struct flow_keys *keys = &fltr->fkeys; 3696 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1]; 3697 3698 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1); 3699 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx]; 3700 3701 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS); 3702 3703 req.ethertype = htons(ETH_P_IP); 3704 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN); 3705 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4; 3706 req.ip_protocol = keys->basic.ip_proto; 3707 3708 if (keys->basic.n_proto == htons(ETH_P_IPV6)) { 3709 int i; 3710 3711 req.ethertype = htons(ETH_P_IPV6); 3712 req.ip_addr_type = 3713 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6; 3714 *(struct in6_addr *)&req.src_ipaddr[0] = 3715 keys->addrs.v6addrs.src; 3716 *(struct in6_addr *)&req.dst_ipaddr[0] = 3717 keys->addrs.v6addrs.dst; 3718 for (i = 0; i < 4; i++) { 3719 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 3720 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 3721 } 3722 } else { 3723 req.src_ipaddr[0] = keys->addrs.v4addrs.src; 3724 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 3725 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst; 3726 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 3727 } 3728 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) { 3729 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG); 3730 req.tunnel_type = 3731 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL; 3732 } 3733 3734 req.src_port = keys->ports.src; 3735 req.src_port_mask = cpu_to_be16(0xffff); 3736 req.dst_port = keys->ports.dst; 3737 req.dst_port_mask = cpu_to_be16(0xffff); 3738 3739 req.dst_id = cpu_to_le16(vnic->fw_vnic_id); 3740 mutex_lock(&bp->hwrm_cmd_lock); 3741 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3742 if (!rc) 3743 fltr->filter_id = resp->ntuple_filter_id; 3744 mutex_unlock(&bp->hwrm_cmd_lock); 3745 return rc; 3746 } 3747 #endif 3748 3749 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx, 3750 u8 *mac_addr) 3751 { 3752 u32 rc = 0; 3753 struct hwrm_cfa_l2_filter_alloc_input req = {0}; 3754 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; 3755 3756 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1); 3757 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX); 3758 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) 3759 req.flags |= 3760 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST); 3761 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id); 3762 req.enables = 3763 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR | 3764 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID | 3765 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK); 3766 memcpy(req.l2_addr, mac_addr, ETH_ALEN); 3767 req.l2_addr_mask[0] = 0xff; 3768 req.l2_addr_mask[1] = 0xff; 3769 req.l2_addr_mask[2] = 0xff; 3770 req.l2_addr_mask[3] = 0xff; 3771 req.l2_addr_mask[4] = 0xff; 3772 req.l2_addr_mask[5] = 0xff; 3773 3774 mutex_lock(&bp->hwrm_cmd_lock); 3775 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3776 if (!rc) 3777 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] = 3778 resp->l2_filter_id; 3779 mutex_unlock(&bp->hwrm_cmd_lock); 3780 return rc; 3781 } 3782 3783 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp) 3784 { 3785 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */ 3786 int rc = 0; 3787 3788 /* Any associated ntuple filters will also be cleared by firmware. */ 3789 mutex_lock(&bp->hwrm_cmd_lock); 3790 for (i = 0; i < num_of_vnics; i++) { 3791 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3792 3793 for (j = 0; j < vnic->uc_filter_count; j++) { 3794 struct hwrm_cfa_l2_filter_free_input req = {0}; 3795 3796 bnxt_hwrm_cmd_hdr_init(bp, &req, 3797 HWRM_CFA_L2_FILTER_FREE, -1, -1); 3798 3799 req.l2_filter_id = vnic->fw_l2_filter_id[j]; 3800 3801 rc = _hwrm_send_message(bp, &req, sizeof(req), 3802 HWRM_CMD_TIMEOUT); 3803 } 3804 vnic->uc_filter_count = 0; 3805 } 3806 mutex_unlock(&bp->hwrm_cmd_lock); 3807 3808 return rc; 3809 } 3810 3811 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags) 3812 { 3813 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3814 struct hwrm_vnic_tpa_cfg_input req = {0}; 3815 3816 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1); 3817 3818 if (tpa_flags) { 3819 u16 mss = bp->dev->mtu - 40; 3820 u32 nsegs, n, segs = 0, flags; 3821 3822 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA | 3823 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA | 3824 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE | 3825 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN | 3826 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ; 3827 if (tpa_flags & BNXT_FLAG_GRO) 3828 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO; 3829 3830 req.flags = cpu_to_le32(flags); 3831 3832 req.enables = 3833 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS | 3834 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS | 3835 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN); 3836 3837 /* Number of segs are log2 units, and first packet is not 3838 * included as part of this units. 3839 */ 3840 if (mss <= BNXT_RX_PAGE_SIZE) { 3841 n = BNXT_RX_PAGE_SIZE / mss; 3842 nsegs = (MAX_SKB_FRAGS - 1) * n; 3843 } else { 3844 n = mss / BNXT_RX_PAGE_SIZE; 3845 if (mss & (BNXT_RX_PAGE_SIZE - 1)) 3846 n++; 3847 nsegs = (MAX_SKB_FRAGS - n) / n; 3848 } 3849 3850 segs = ilog2(nsegs); 3851 req.max_agg_segs = cpu_to_le16(segs); 3852 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX); 3853 3854 req.min_agg_len = cpu_to_le32(512); 3855 } 3856 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 3857 3858 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3859 } 3860 3861 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss) 3862 { 3863 u32 i, j, max_rings; 3864 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3865 struct hwrm_vnic_rss_cfg_input req = {0}; 3866 3867 if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID) 3868 return 0; 3869 3870 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); 3871 if (set_rss) { 3872 req.hash_type = cpu_to_le32(bp->rss_hash_cfg); 3873 if (vnic->flags & BNXT_VNIC_RSS_FLAG) { 3874 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 3875 max_rings = bp->rx_nr_rings - 1; 3876 else 3877 max_rings = bp->rx_nr_rings; 3878 } else { 3879 max_rings = 1; 3880 } 3881 3882 /* Fill the RSS indirection table with ring group ids */ 3883 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) { 3884 if (j == max_rings) 3885 j = 0; 3886 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]); 3887 } 3888 3889 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); 3890 req.hash_key_tbl_addr = 3891 cpu_to_le64(vnic->rss_hash_key_dma_addr); 3892 } 3893 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 3894 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3895 } 3896 3897 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id) 3898 { 3899 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3900 struct hwrm_vnic_plcmodes_cfg_input req = {0}; 3901 3902 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1); 3903 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT | 3904 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 | 3905 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6); 3906 req.enables = 3907 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID | 3908 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID); 3909 /* thresholds not implemented in firmware yet */ 3910 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh); 3911 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh); 3912 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 3913 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3914 } 3915 3916 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id, 3917 u16 ctx_idx) 3918 { 3919 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0}; 3920 3921 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1); 3922 req.rss_cos_lb_ctx_id = 3923 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]); 3924 3925 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3926 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID; 3927 } 3928 3929 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp) 3930 { 3931 int i, j; 3932 3933 for (i = 0; i < bp->nr_vnics; i++) { 3934 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3935 3936 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) { 3937 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID) 3938 bnxt_hwrm_vnic_ctx_free_one(bp, i, j); 3939 } 3940 } 3941 bp->rsscos_nr_ctxs = 0; 3942 } 3943 3944 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx) 3945 { 3946 int rc; 3947 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0}; 3948 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp = 3949 bp->hwrm_cmd_resp_addr; 3950 3951 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1, 3952 -1); 3953 3954 mutex_lock(&bp->hwrm_cmd_lock); 3955 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3956 if (!rc) 3957 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = 3958 le16_to_cpu(resp->rss_cos_lb_ctx_id); 3959 mutex_unlock(&bp->hwrm_cmd_lock); 3960 3961 return rc; 3962 } 3963 3964 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id) 3965 { 3966 unsigned int ring = 0, grp_idx; 3967 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3968 struct hwrm_vnic_cfg_input req = {0}; 3969 u16 def_vlan = 0; 3970 3971 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1); 3972 3973 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP); 3974 /* Only RSS support for now TBD: COS & LB */ 3975 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) { 3976 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 3977 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 3978 VNIC_CFG_REQ_ENABLES_MRU); 3979 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) { 3980 req.rss_rule = 3981 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]); 3982 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 3983 VNIC_CFG_REQ_ENABLES_MRU); 3984 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE); 3985 } else { 3986 req.rss_rule = cpu_to_le16(0xffff); 3987 } 3988 3989 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && 3990 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) { 3991 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]); 3992 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE); 3993 } else { 3994 req.cos_rule = cpu_to_le16(0xffff); 3995 } 3996 3997 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 3998 ring = 0; 3999 else if (vnic->flags & BNXT_VNIC_RFS_FLAG) 4000 ring = vnic_id - 1; 4001 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp)) 4002 ring = bp->rx_nr_rings - 1; 4003 4004 grp_idx = bp->rx_ring[ring].bnapi->index; 4005 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 4006 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id); 4007 4008 req.lb_rule = cpu_to_le16(0xffff); 4009 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + 4010 VLAN_HLEN); 4011 4012 #ifdef CONFIG_BNXT_SRIOV 4013 if (BNXT_VF(bp)) 4014 def_vlan = bp->vf.vlan; 4015 #endif 4016 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan) 4017 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE); 4018 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP)) 4019 req.flags |= 4020 cpu_to_le32(VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE); 4021 4022 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4023 } 4024 4025 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id) 4026 { 4027 u32 rc = 0; 4028 4029 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) { 4030 struct hwrm_vnic_free_input req = {0}; 4031 4032 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1); 4033 req.vnic_id = 4034 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id); 4035 4036 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4037 if (rc) 4038 return rc; 4039 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID; 4040 } 4041 return rc; 4042 } 4043 4044 static void bnxt_hwrm_vnic_free(struct bnxt *bp) 4045 { 4046 u16 i; 4047 4048 for (i = 0; i < bp->nr_vnics; i++) 4049 bnxt_hwrm_vnic_free_one(bp, i); 4050 } 4051 4052 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, 4053 unsigned int start_rx_ring_idx, 4054 unsigned int nr_rings) 4055 { 4056 int rc = 0; 4057 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings; 4058 struct hwrm_vnic_alloc_input req = {0}; 4059 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4060 4061 /* map ring groups to this vnic */ 4062 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) { 4063 grp_idx = bp->rx_ring[i].bnapi->index; 4064 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) { 4065 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n", 4066 j, nr_rings); 4067 break; 4068 } 4069 bp->vnic_info[vnic_id].fw_grp_ids[j] = 4070 bp->grp_info[grp_idx].fw_grp_id; 4071 } 4072 4073 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID; 4074 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID; 4075 if (vnic_id == 0) 4076 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT); 4077 4078 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1); 4079 4080 mutex_lock(&bp->hwrm_cmd_lock); 4081 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4082 if (!rc) 4083 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id); 4084 mutex_unlock(&bp->hwrm_cmd_lock); 4085 return rc; 4086 } 4087 4088 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp) 4089 { 4090 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 4091 struct hwrm_vnic_qcaps_input req = {0}; 4092 int rc; 4093 4094 if (bp->hwrm_spec_code < 0x10600) 4095 return 0; 4096 4097 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1); 4098 mutex_lock(&bp->hwrm_cmd_lock); 4099 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4100 if (!rc) { 4101 if (resp->flags & 4102 cpu_to_le32(VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP)) 4103 bp->flags |= BNXT_FLAG_NEW_RSS_CAP; 4104 } 4105 mutex_unlock(&bp->hwrm_cmd_lock); 4106 return rc; 4107 } 4108 4109 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp) 4110 { 4111 u16 i; 4112 u32 rc = 0; 4113 4114 mutex_lock(&bp->hwrm_cmd_lock); 4115 for (i = 0; i < bp->rx_nr_rings; i++) { 4116 struct hwrm_ring_grp_alloc_input req = {0}; 4117 struct hwrm_ring_grp_alloc_output *resp = 4118 bp->hwrm_cmd_resp_addr; 4119 unsigned int grp_idx = bp->rx_ring[i].bnapi->index; 4120 4121 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1); 4122 4123 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id); 4124 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id); 4125 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id); 4126 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx); 4127 4128 rc = _hwrm_send_message(bp, &req, sizeof(req), 4129 HWRM_CMD_TIMEOUT); 4130 if (rc) 4131 break; 4132 4133 bp->grp_info[grp_idx].fw_grp_id = 4134 le32_to_cpu(resp->ring_group_id); 4135 } 4136 mutex_unlock(&bp->hwrm_cmd_lock); 4137 return rc; 4138 } 4139 4140 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp) 4141 { 4142 u16 i; 4143 u32 rc = 0; 4144 struct hwrm_ring_grp_free_input req = {0}; 4145 4146 if (!bp->grp_info) 4147 return 0; 4148 4149 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1); 4150 4151 mutex_lock(&bp->hwrm_cmd_lock); 4152 for (i = 0; i < bp->cp_nr_rings; i++) { 4153 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) 4154 continue; 4155 req.ring_group_id = 4156 cpu_to_le32(bp->grp_info[i].fw_grp_id); 4157 4158 rc = _hwrm_send_message(bp, &req, sizeof(req), 4159 HWRM_CMD_TIMEOUT); 4160 if (rc) 4161 break; 4162 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 4163 } 4164 mutex_unlock(&bp->hwrm_cmd_lock); 4165 return rc; 4166 } 4167 4168 static int hwrm_ring_alloc_send_msg(struct bnxt *bp, 4169 struct bnxt_ring_struct *ring, 4170 u32 ring_type, u32 map_index, 4171 u32 stats_ctx_id) 4172 { 4173 int rc = 0, err = 0; 4174 struct hwrm_ring_alloc_input req = {0}; 4175 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4176 u16 ring_id; 4177 4178 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1); 4179 4180 req.enables = 0; 4181 if (ring->nr_pages > 1) { 4182 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map); 4183 /* Page size is in log2 units */ 4184 req.page_size = BNXT_PAGE_SHIFT; 4185 req.page_tbl_depth = 1; 4186 } else { 4187 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]); 4188 } 4189 req.fbo = 0; 4190 /* Association of ring index with doorbell index and MSIX number */ 4191 req.logical_id = cpu_to_le16(map_index); 4192 4193 switch (ring_type) { 4194 case HWRM_RING_ALLOC_TX: 4195 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX; 4196 /* Association of transmit ring with completion ring */ 4197 req.cmpl_ring_id = 4198 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id); 4199 req.length = cpu_to_le32(bp->tx_ring_mask + 1); 4200 req.stat_ctx_id = cpu_to_le32(stats_ctx_id); 4201 req.queue_id = cpu_to_le16(ring->queue_id); 4202 break; 4203 case HWRM_RING_ALLOC_RX: 4204 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 4205 req.length = cpu_to_le32(bp->rx_ring_mask + 1); 4206 break; 4207 case HWRM_RING_ALLOC_AGG: 4208 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 4209 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1); 4210 break; 4211 case HWRM_RING_ALLOC_CMPL: 4212 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL; 4213 req.length = cpu_to_le32(bp->cp_ring_mask + 1); 4214 if (bp->flags & BNXT_FLAG_USING_MSIX) 4215 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; 4216 break; 4217 default: 4218 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n", 4219 ring_type); 4220 return -1; 4221 } 4222 4223 mutex_lock(&bp->hwrm_cmd_lock); 4224 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4225 err = le16_to_cpu(resp->error_code); 4226 ring_id = le16_to_cpu(resp->ring_id); 4227 mutex_unlock(&bp->hwrm_cmd_lock); 4228 4229 if (rc || err) { 4230 switch (ring_type) { 4231 case RING_FREE_REQ_RING_TYPE_L2_CMPL: 4232 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n", 4233 rc, err); 4234 return -1; 4235 4236 case RING_FREE_REQ_RING_TYPE_RX: 4237 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n", 4238 rc, err); 4239 return -1; 4240 4241 case RING_FREE_REQ_RING_TYPE_TX: 4242 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n", 4243 rc, err); 4244 return -1; 4245 4246 default: 4247 netdev_err(bp->dev, "Invalid ring\n"); 4248 return -1; 4249 } 4250 } 4251 ring->fw_ring_id = ring_id; 4252 return rc; 4253 } 4254 4255 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx) 4256 { 4257 int rc; 4258 4259 if (BNXT_PF(bp)) { 4260 struct hwrm_func_cfg_input req = {0}; 4261 4262 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 4263 req.fid = cpu_to_le16(0xffff); 4264 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 4265 req.async_event_cr = cpu_to_le16(idx); 4266 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4267 } else { 4268 struct hwrm_func_vf_cfg_input req = {0}; 4269 4270 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1); 4271 req.enables = 4272 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 4273 req.async_event_cr = cpu_to_le16(idx); 4274 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4275 } 4276 return rc; 4277 } 4278 4279 static int bnxt_hwrm_ring_alloc(struct bnxt *bp) 4280 { 4281 int i, rc = 0; 4282 4283 for (i = 0; i < bp->cp_nr_rings; i++) { 4284 struct bnxt_napi *bnapi = bp->bnapi[i]; 4285 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4286 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 4287 4288 cpr->cp_doorbell = bp->bar1 + i * 0x80; 4289 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i, 4290 INVALID_STATS_CTX_ID); 4291 if (rc) 4292 goto err_out; 4293 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); 4294 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id; 4295 4296 if (!i) { 4297 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id); 4298 if (rc) 4299 netdev_warn(bp->dev, "Failed to set async event completion ring.\n"); 4300 } 4301 } 4302 4303 for (i = 0; i < bp->tx_nr_rings; i++) { 4304 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 4305 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 4306 u32 map_idx = txr->bnapi->index; 4307 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx; 4308 4309 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX, 4310 map_idx, fw_stats_ctx); 4311 if (rc) 4312 goto err_out; 4313 txr->tx_doorbell = bp->bar1 + map_idx * 0x80; 4314 } 4315 4316 for (i = 0; i < bp->rx_nr_rings; i++) { 4317 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 4318 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 4319 u32 map_idx = rxr->bnapi->index; 4320 4321 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX, 4322 map_idx, INVALID_STATS_CTX_ID); 4323 if (rc) 4324 goto err_out; 4325 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80; 4326 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell); 4327 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id; 4328 } 4329 4330 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 4331 for (i = 0; i < bp->rx_nr_rings; i++) { 4332 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 4333 struct bnxt_ring_struct *ring = 4334 &rxr->rx_agg_ring_struct; 4335 u32 grp_idx = rxr->bnapi->index; 4336 u32 map_idx = grp_idx + bp->rx_nr_rings; 4337 4338 rc = hwrm_ring_alloc_send_msg(bp, ring, 4339 HWRM_RING_ALLOC_AGG, 4340 map_idx, 4341 INVALID_STATS_CTX_ID); 4342 if (rc) 4343 goto err_out; 4344 4345 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80; 4346 writel(DB_KEY_RX | rxr->rx_agg_prod, 4347 rxr->rx_agg_doorbell); 4348 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id; 4349 } 4350 } 4351 err_out: 4352 return rc; 4353 } 4354 4355 static int hwrm_ring_free_send_msg(struct bnxt *bp, 4356 struct bnxt_ring_struct *ring, 4357 u32 ring_type, int cmpl_ring_id) 4358 { 4359 int rc; 4360 struct hwrm_ring_free_input req = {0}; 4361 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr; 4362 u16 error_code; 4363 4364 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1); 4365 req.ring_type = ring_type; 4366 req.ring_id = cpu_to_le16(ring->fw_ring_id); 4367 4368 mutex_lock(&bp->hwrm_cmd_lock); 4369 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4370 error_code = le16_to_cpu(resp->error_code); 4371 mutex_unlock(&bp->hwrm_cmd_lock); 4372 4373 if (rc || error_code) { 4374 switch (ring_type) { 4375 case RING_FREE_REQ_RING_TYPE_L2_CMPL: 4376 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n", 4377 rc); 4378 return rc; 4379 case RING_FREE_REQ_RING_TYPE_RX: 4380 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n", 4381 rc); 4382 return rc; 4383 case RING_FREE_REQ_RING_TYPE_TX: 4384 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n", 4385 rc); 4386 return rc; 4387 default: 4388 netdev_err(bp->dev, "Invalid ring\n"); 4389 return -1; 4390 } 4391 } 4392 return 0; 4393 } 4394 4395 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path) 4396 { 4397 int i; 4398 4399 if (!bp->bnapi) 4400 return; 4401 4402 for (i = 0; i < bp->tx_nr_rings; i++) { 4403 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 4404 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 4405 u32 grp_idx = txr->bnapi->index; 4406 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id; 4407 4408 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 4409 hwrm_ring_free_send_msg(bp, ring, 4410 RING_FREE_REQ_RING_TYPE_TX, 4411 close_path ? cmpl_ring_id : 4412 INVALID_HW_RING_ID); 4413 ring->fw_ring_id = INVALID_HW_RING_ID; 4414 } 4415 } 4416 4417 for (i = 0; i < bp->rx_nr_rings; i++) { 4418 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 4419 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 4420 u32 grp_idx = rxr->bnapi->index; 4421 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id; 4422 4423 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 4424 hwrm_ring_free_send_msg(bp, ring, 4425 RING_FREE_REQ_RING_TYPE_RX, 4426 close_path ? cmpl_ring_id : 4427 INVALID_HW_RING_ID); 4428 ring->fw_ring_id = INVALID_HW_RING_ID; 4429 bp->grp_info[grp_idx].rx_fw_ring_id = 4430 INVALID_HW_RING_ID; 4431 } 4432 } 4433 4434 for (i = 0; i < bp->rx_nr_rings; i++) { 4435 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 4436 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct; 4437 u32 grp_idx = rxr->bnapi->index; 4438 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id; 4439 4440 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 4441 hwrm_ring_free_send_msg(bp, ring, 4442 RING_FREE_REQ_RING_TYPE_RX, 4443 close_path ? cmpl_ring_id : 4444 INVALID_HW_RING_ID); 4445 ring->fw_ring_id = INVALID_HW_RING_ID; 4446 bp->grp_info[grp_idx].agg_fw_ring_id = 4447 INVALID_HW_RING_ID; 4448 } 4449 } 4450 4451 /* The completion rings are about to be freed. After that the 4452 * IRQ doorbell will not work anymore. So we need to disable 4453 * IRQ here. 4454 */ 4455 bnxt_disable_int_sync(bp); 4456 4457 for (i = 0; i < bp->cp_nr_rings; i++) { 4458 struct bnxt_napi *bnapi = bp->bnapi[i]; 4459 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4460 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 4461 4462 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 4463 hwrm_ring_free_send_msg(bp, ring, 4464 RING_FREE_REQ_RING_TYPE_L2_CMPL, 4465 INVALID_HW_RING_ID); 4466 ring->fw_ring_id = INVALID_HW_RING_ID; 4467 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 4468 } 4469 } 4470 } 4471 4472 /* Caller must hold bp->hwrm_cmd_lock */ 4473 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings) 4474 { 4475 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 4476 struct hwrm_func_qcfg_input req = {0}; 4477 int rc; 4478 4479 if (bp->hwrm_spec_code < 0x10601) 4480 return 0; 4481 4482 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 4483 req.fid = cpu_to_le16(fid); 4484 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4485 if (!rc) 4486 *tx_rings = le16_to_cpu(resp->alloc_tx_rings); 4487 4488 return rc; 4489 } 4490 4491 static int bnxt_hwrm_reserve_tx_rings(struct bnxt *bp, int *tx_rings) 4492 { 4493 struct hwrm_func_cfg_input req = {0}; 4494 int rc; 4495 4496 if (bp->hwrm_spec_code < 0x10601) 4497 return 0; 4498 4499 if (BNXT_VF(bp)) 4500 return 0; 4501 4502 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 4503 req.fid = cpu_to_le16(0xffff); 4504 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS); 4505 req.num_tx_rings = cpu_to_le16(*tx_rings); 4506 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4507 if (rc) 4508 return rc; 4509 4510 mutex_lock(&bp->hwrm_cmd_lock); 4511 rc = __bnxt_hwrm_get_tx_rings(bp, 0xffff, tx_rings); 4512 mutex_unlock(&bp->hwrm_cmd_lock); 4513 if (!rc) 4514 bp->tx_reserved_rings = *tx_rings; 4515 return rc; 4516 } 4517 4518 static int bnxt_hwrm_check_tx_rings(struct bnxt *bp, int tx_rings) 4519 { 4520 struct hwrm_func_cfg_input req = {0}; 4521 int rc; 4522 4523 if (bp->hwrm_spec_code < 0x10801) 4524 return 0; 4525 4526 if (BNXT_VF(bp)) 4527 return 0; 4528 4529 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 4530 req.fid = cpu_to_le16(0xffff); 4531 req.flags = cpu_to_le32(FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST); 4532 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS); 4533 req.num_tx_rings = cpu_to_le16(tx_rings); 4534 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4535 if (rc) 4536 return -ENOMEM; 4537 return 0; 4538 } 4539 4540 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal, 4541 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req) 4542 { 4543 u16 val, tmr, max, flags; 4544 4545 max = hw_coal->bufs_per_record * 128; 4546 if (hw_coal->budget) 4547 max = hw_coal->bufs_per_record * hw_coal->budget; 4548 4549 val = clamp_t(u16, hw_coal->coal_bufs, 1, max); 4550 req->num_cmpl_aggr_int = cpu_to_le16(val); 4551 req->num_cmpl_dma_aggr = cpu_to_le16(val); 4552 4553 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, max); 4554 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val); 4555 4556 tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks); 4557 tmr = max_t(u16, tmr, 1); 4558 req->int_lat_tmr_max = cpu_to_le16(tmr); 4559 4560 /* min timer set to 1/2 of interrupt timer */ 4561 val = tmr / 2; 4562 req->int_lat_tmr_min = cpu_to_le16(val); 4563 4564 /* buf timer set to 1/4 of interrupt timer */ 4565 val = max_t(u16, tmr / 4, 1); 4566 req->cmpl_aggr_dma_tmr = cpu_to_le16(val); 4567 4568 tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks_irq); 4569 tmr = max_t(u16, tmr, 1); 4570 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr); 4571 4572 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 4573 if (hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh) 4574 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE; 4575 req->flags = cpu_to_le16(flags); 4576 } 4577 4578 int bnxt_hwrm_set_coal(struct bnxt *bp) 4579 { 4580 int i, rc = 0; 4581 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}, 4582 req_tx = {0}, *req; 4583 4584 bnxt_hwrm_cmd_hdr_init(bp, &req_rx, 4585 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 4586 bnxt_hwrm_cmd_hdr_init(bp, &req_tx, 4587 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 4588 4589 bnxt_hwrm_set_coal_params(&bp->rx_coal, &req_rx); 4590 bnxt_hwrm_set_coal_params(&bp->tx_coal, &req_tx); 4591 4592 mutex_lock(&bp->hwrm_cmd_lock); 4593 for (i = 0; i < bp->cp_nr_rings; i++) { 4594 struct bnxt_napi *bnapi = bp->bnapi[i]; 4595 4596 req = &req_rx; 4597 if (!bnapi->rx_ring) 4598 req = &req_tx; 4599 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id); 4600 4601 rc = _hwrm_send_message(bp, req, sizeof(*req), 4602 HWRM_CMD_TIMEOUT); 4603 if (rc) 4604 break; 4605 } 4606 mutex_unlock(&bp->hwrm_cmd_lock); 4607 return rc; 4608 } 4609 4610 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp) 4611 { 4612 int rc = 0, i; 4613 struct hwrm_stat_ctx_free_input req = {0}; 4614 4615 if (!bp->bnapi) 4616 return 0; 4617 4618 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 4619 return 0; 4620 4621 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1); 4622 4623 mutex_lock(&bp->hwrm_cmd_lock); 4624 for (i = 0; i < bp->cp_nr_rings; i++) { 4625 struct bnxt_napi *bnapi = bp->bnapi[i]; 4626 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4627 4628 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) { 4629 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id); 4630 4631 rc = _hwrm_send_message(bp, &req, sizeof(req), 4632 HWRM_CMD_TIMEOUT); 4633 if (rc) 4634 break; 4635 4636 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 4637 } 4638 } 4639 mutex_unlock(&bp->hwrm_cmd_lock); 4640 return rc; 4641 } 4642 4643 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp) 4644 { 4645 int rc = 0, i; 4646 struct hwrm_stat_ctx_alloc_input req = {0}; 4647 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4648 4649 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 4650 return 0; 4651 4652 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1); 4653 4654 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000); 4655 4656 mutex_lock(&bp->hwrm_cmd_lock); 4657 for (i = 0; i < bp->cp_nr_rings; i++) { 4658 struct bnxt_napi *bnapi = bp->bnapi[i]; 4659 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4660 4661 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map); 4662 4663 rc = _hwrm_send_message(bp, &req, sizeof(req), 4664 HWRM_CMD_TIMEOUT); 4665 if (rc) 4666 break; 4667 4668 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id); 4669 4670 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id; 4671 } 4672 mutex_unlock(&bp->hwrm_cmd_lock); 4673 return rc; 4674 } 4675 4676 static int bnxt_hwrm_func_qcfg(struct bnxt *bp) 4677 { 4678 struct hwrm_func_qcfg_input req = {0}; 4679 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 4680 u16 flags; 4681 int rc; 4682 4683 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 4684 req.fid = cpu_to_le16(0xffff); 4685 mutex_lock(&bp->hwrm_cmd_lock); 4686 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4687 if (rc) 4688 goto func_qcfg_exit; 4689 4690 #ifdef CONFIG_BNXT_SRIOV 4691 if (BNXT_VF(bp)) { 4692 struct bnxt_vf_info *vf = &bp->vf; 4693 4694 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK; 4695 } 4696 #endif 4697 flags = le16_to_cpu(resp->flags); 4698 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED | 4699 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) { 4700 bp->flags |= BNXT_FLAG_FW_LLDP_AGENT; 4701 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED) 4702 bp->flags |= BNXT_FLAG_FW_DCBX_AGENT; 4703 } 4704 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST)) 4705 bp->flags |= BNXT_FLAG_MULTI_HOST; 4706 4707 switch (resp->port_partition_type) { 4708 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0: 4709 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5: 4710 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0: 4711 bp->port_partition_type = resp->port_partition_type; 4712 break; 4713 } 4714 if (bp->hwrm_spec_code < 0x10707 || 4715 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB) 4716 bp->br_mode = BRIDGE_MODE_VEB; 4717 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA) 4718 bp->br_mode = BRIDGE_MODE_VEPA; 4719 else 4720 bp->br_mode = BRIDGE_MODE_UNDEF; 4721 4722 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured); 4723 if (!bp->max_mtu) 4724 bp->max_mtu = BNXT_MAX_MTU; 4725 4726 func_qcfg_exit: 4727 mutex_unlock(&bp->hwrm_cmd_lock); 4728 return rc; 4729 } 4730 4731 static int bnxt_hwrm_func_qcaps(struct bnxt *bp) 4732 { 4733 int rc = 0; 4734 struct hwrm_func_qcaps_input req = {0}; 4735 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 4736 4737 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1); 4738 req.fid = cpu_to_le16(0xffff); 4739 4740 mutex_lock(&bp->hwrm_cmd_lock); 4741 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4742 if (rc) 4743 goto hwrm_func_qcaps_exit; 4744 4745 if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)) 4746 bp->flags |= BNXT_FLAG_ROCEV1_CAP; 4747 if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)) 4748 bp->flags |= BNXT_FLAG_ROCEV2_CAP; 4749 4750 bp->tx_push_thresh = 0; 4751 if (resp->flags & 4752 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)) 4753 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH; 4754 4755 if (BNXT_PF(bp)) { 4756 struct bnxt_pf_info *pf = &bp->pf; 4757 4758 pf->fw_fid = le16_to_cpu(resp->fid); 4759 pf->port_id = le16_to_cpu(resp->port_id); 4760 bp->dev->dev_port = pf->port_id; 4761 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN); 4762 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 4763 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 4764 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 4765 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 4766 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); 4767 if (!pf->max_hw_ring_grps) 4768 pf->max_hw_ring_grps = pf->max_tx_rings; 4769 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 4770 pf->max_vnics = le16_to_cpu(resp->max_vnics); 4771 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 4772 pf->first_vf_id = le16_to_cpu(resp->first_vf_id); 4773 pf->max_vfs = le16_to_cpu(resp->max_vfs); 4774 pf->max_encap_records = le32_to_cpu(resp->max_encap_records); 4775 pf->max_decap_records = le32_to_cpu(resp->max_decap_records); 4776 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows); 4777 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows); 4778 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows); 4779 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows); 4780 if (resp->flags & 4781 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)) 4782 bp->flags |= BNXT_FLAG_WOL_CAP; 4783 } else { 4784 #ifdef CONFIG_BNXT_SRIOV 4785 struct bnxt_vf_info *vf = &bp->vf; 4786 4787 vf->fw_fid = le16_to_cpu(resp->fid); 4788 4789 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 4790 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 4791 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 4792 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 4793 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); 4794 if (!vf->max_hw_ring_grps) 4795 vf->max_hw_ring_grps = vf->max_tx_rings; 4796 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 4797 vf->max_vnics = le16_to_cpu(resp->max_vnics); 4798 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 4799 4800 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN); 4801 #endif 4802 } 4803 4804 hwrm_func_qcaps_exit: 4805 mutex_unlock(&bp->hwrm_cmd_lock); 4806 return rc; 4807 } 4808 4809 static int bnxt_hwrm_func_reset(struct bnxt *bp) 4810 { 4811 struct hwrm_func_reset_input req = {0}; 4812 4813 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1); 4814 req.enables = 0; 4815 4816 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT); 4817 } 4818 4819 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp) 4820 { 4821 int rc = 0; 4822 struct hwrm_queue_qportcfg_input req = {0}; 4823 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr; 4824 u8 i, *qptr; 4825 4826 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1); 4827 4828 mutex_lock(&bp->hwrm_cmd_lock); 4829 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4830 if (rc) 4831 goto qportcfg_exit; 4832 4833 if (!resp->max_configurable_queues) { 4834 rc = -EINVAL; 4835 goto qportcfg_exit; 4836 } 4837 bp->max_tc = resp->max_configurable_queues; 4838 bp->max_lltc = resp->max_configurable_lossless_queues; 4839 if (bp->max_tc > BNXT_MAX_QUEUE) 4840 bp->max_tc = BNXT_MAX_QUEUE; 4841 4842 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG) 4843 bp->max_tc = 1; 4844 4845 if (bp->max_lltc > bp->max_tc) 4846 bp->max_lltc = bp->max_tc; 4847 4848 qptr = &resp->queue_id0; 4849 for (i = 0; i < bp->max_tc; i++) { 4850 bp->q_info[i].queue_id = *qptr++; 4851 bp->q_info[i].queue_profile = *qptr++; 4852 } 4853 4854 qportcfg_exit: 4855 mutex_unlock(&bp->hwrm_cmd_lock); 4856 return rc; 4857 } 4858 4859 static int bnxt_hwrm_ver_get(struct bnxt *bp) 4860 { 4861 int rc; 4862 struct hwrm_ver_get_input req = {0}; 4863 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr; 4864 u32 dev_caps_cfg; 4865 4866 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN; 4867 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1); 4868 req.hwrm_intf_maj = HWRM_VERSION_MAJOR; 4869 req.hwrm_intf_min = HWRM_VERSION_MINOR; 4870 req.hwrm_intf_upd = HWRM_VERSION_UPDATE; 4871 mutex_lock(&bp->hwrm_cmd_lock); 4872 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4873 if (rc) 4874 goto hwrm_ver_get_exit; 4875 4876 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output)); 4877 4878 bp->hwrm_spec_code = resp->hwrm_intf_maj << 16 | 4879 resp->hwrm_intf_min << 8 | resp->hwrm_intf_upd; 4880 if (resp->hwrm_intf_maj < 1) { 4881 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n", 4882 resp->hwrm_intf_maj, resp->hwrm_intf_min, 4883 resp->hwrm_intf_upd); 4884 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n"); 4885 } 4886 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d", 4887 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld, 4888 resp->hwrm_fw_rsvd); 4889 4890 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout); 4891 if (!bp->hwrm_cmd_timeout) 4892 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; 4893 4894 if (resp->hwrm_intf_maj >= 1) 4895 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len); 4896 4897 bp->chip_num = le16_to_cpu(resp->chip_num); 4898 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev && 4899 !resp->chip_metal) 4900 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0; 4901 4902 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg); 4903 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) && 4904 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) 4905 bp->flags |= BNXT_FLAG_SHORT_CMD; 4906 4907 hwrm_ver_get_exit: 4908 mutex_unlock(&bp->hwrm_cmd_lock); 4909 return rc; 4910 } 4911 4912 int bnxt_hwrm_fw_set_time(struct bnxt *bp) 4913 { 4914 #if IS_ENABLED(CONFIG_RTC_LIB) 4915 struct hwrm_fw_set_time_input req = {0}; 4916 struct rtc_time tm; 4917 struct timeval tv; 4918 4919 if (bp->hwrm_spec_code < 0x10400) 4920 return -EOPNOTSUPP; 4921 4922 do_gettimeofday(&tv); 4923 rtc_time_to_tm(tv.tv_sec, &tm); 4924 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1); 4925 req.year = cpu_to_le16(1900 + tm.tm_year); 4926 req.month = 1 + tm.tm_mon; 4927 req.day = tm.tm_mday; 4928 req.hour = tm.tm_hour; 4929 req.minute = tm.tm_min; 4930 req.second = tm.tm_sec; 4931 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4932 #else 4933 return -EOPNOTSUPP; 4934 #endif 4935 } 4936 4937 static int bnxt_hwrm_port_qstats(struct bnxt *bp) 4938 { 4939 int rc; 4940 struct bnxt_pf_info *pf = &bp->pf; 4941 struct hwrm_port_qstats_input req = {0}; 4942 4943 if (!(bp->flags & BNXT_FLAG_PORT_STATS)) 4944 return 0; 4945 4946 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1); 4947 req.port_id = cpu_to_le16(pf->port_id); 4948 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map); 4949 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map); 4950 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4951 return rc; 4952 } 4953 4954 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp) 4955 { 4956 if (bp->vxlan_port_cnt) { 4957 bnxt_hwrm_tunnel_dst_port_free( 4958 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 4959 } 4960 bp->vxlan_port_cnt = 0; 4961 if (bp->nge_port_cnt) { 4962 bnxt_hwrm_tunnel_dst_port_free( 4963 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 4964 } 4965 bp->nge_port_cnt = 0; 4966 } 4967 4968 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa) 4969 { 4970 int rc, i; 4971 u32 tpa_flags = 0; 4972 4973 if (set_tpa) 4974 tpa_flags = bp->flags & BNXT_FLAG_TPA; 4975 for (i = 0; i < bp->nr_vnics; i++) { 4976 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags); 4977 if (rc) { 4978 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n", 4979 i, rc); 4980 return rc; 4981 } 4982 } 4983 return 0; 4984 } 4985 4986 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp) 4987 { 4988 int i; 4989 4990 for (i = 0; i < bp->nr_vnics; i++) 4991 bnxt_hwrm_vnic_set_rss(bp, i, false); 4992 } 4993 4994 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path, 4995 bool irq_re_init) 4996 { 4997 if (bp->vnic_info) { 4998 bnxt_hwrm_clear_vnic_filter(bp); 4999 /* clear all RSS setting before free vnic ctx */ 5000 bnxt_hwrm_clear_vnic_rss(bp); 5001 bnxt_hwrm_vnic_ctx_free(bp); 5002 /* before free the vnic, undo the vnic tpa settings */ 5003 if (bp->flags & BNXT_FLAG_TPA) 5004 bnxt_set_tpa(bp, false); 5005 bnxt_hwrm_vnic_free(bp); 5006 } 5007 bnxt_hwrm_ring_free(bp, close_path); 5008 bnxt_hwrm_ring_grp_free(bp); 5009 if (irq_re_init) { 5010 bnxt_hwrm_stat_ctx_free(bp); 5011 bnxt_hwrm_free_tunnel_ports(bp); 5012 } 5013 } 5014 5015 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode) 5016 { 5017 struct hwrm_func_cfg_input req = {0}; 5018 int rc; 5019 5020 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 5021 req.fid = cpu_to_le16(0xffff); 5022 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE); 5023 if (br_mode == BRIDGE_MODE_VEB) 5024 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB; 5025 else if (br_mode == BRIDGE_MODE_VEPA) 5026 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA; 5027 else 5028 return -EINVAL; 5029 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5030 if (rc) 5031 rc = -EIO; 5032 return rc; 5033 } 5034 5035 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) 5036 { 5037 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 5038 int rc; 5039 5040 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) 5041 goto skip_rss_ctx; 5042 5043 /* allocate context for vnic */ 5044 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0); 5045 if (rc) { 5046 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 5047 vnic_id, rc); 5048 goto vnic_setup_err; 5049 } 5050 bp->rsscos_nr_ctxs++; 5051 5052 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 5053 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1); 5054 if (rc) { 5055 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n", 5056 vnic_id, rc); 5057 goto vnic_setup_err; 5058 } 5059 bp->rsscos_nr_ctxs++; 5060 } 5061 5062 skip_rss_ctx: 5063 /* configure default vnic, ring grp */ 5064 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); 5065 if (rc) { 5066 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", 5067 vnic_id, rc); 5068 goto vnic_setup_err; 5069 } 5070 5071 /* Enable RSS hashing on vnic */ 5072 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true); 5073 if (rc) { 5074 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n", 5075 vnic_id, rc); 5076 goto vnic_setup_err; 5077 } 5078 5079 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 5080 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); 5081 if (rc) { 5082 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", 5083 vnic_id, rc); 5084 } 5085 } 5086 5087 vnic_setup_err: 5088 return rc; 5089 } 5090 5091 static int bnxt_alloc_rfs_vnics(struct bnxt *bp) 5092 { 5093 #ifdef CONFIG_RFS_ACCEL 5094 int i, rc = 0; 5095 5096 for (i = 0; i < bp->rx_nr_rings; i++) { 5097 struct bnxt_vnic_info *vnic; 5098 u16 vnic_id = i + 1; 5099 u16 ring_id = i; 5100 5101 if (vnic_id >= bp->nr_vnics) 5102 break; 5103 5104 vnic = &bp->vnic_info[vnic_id]; 5105 vnic->flags |= BNXT_VNIC_RFS_FLAG; 5106 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 5107 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG; 5108 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1); 5109 if (rc) { 5110 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 5111 vnic_id, rc); 5112 break; 5113 } 5114 rc = bnxt_setup_vnic(bp, vnic_id); 5115 if (rc) 5116 break; 5117 } 5118 return rc; 5119 #else 5120 return 0; 5121 #endif 5122 } 5123 5124 /* Allow PF and VF with default VLAN to be in promiscuous mode */ 5125 static bool bnxt_promisc_ok(struct bnxt *bp) 5126 { 5127 #ifdef CONFIG_BNXT_SRIOV 5128 if (BNXT_VF(bp) && !bp->vf.vlan) 5129 return false; 5130 #endif 5131 return true; 5132 } 5133 5134 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp) 5135 { 5136 unsigned int rc = 0; 5137 5138 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1); 5139 if (rc) { 5140 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 5141 rc); 5142 return rc; 5143 } 5144 5145 rc = bnxt_hwrm_vnic_cfg(bp, 1); 5146 if (rc) { 5147 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 5148 rc); 5149 return rc; 5150 } 5151 return rc; 5152 } 5153 5154 static int bnxt_cfg_rx_mode(struct bnxt *); 5155 static bool bnxt_mc_list_updated(struct bnxt *, u32 *); 5156 5157 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init) 5158 { 5159 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 5160 int rc = 0; 5161 unsigned int rx_nr_rings = bp->rx_nr_rings; 5162 5163 if (irq_re_init) { 5164 rc = bnxt_hwrm_stat_ctx_alloc(bp); 5165 if (rc) { 5166 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n", 5167 rc); 5168 goto err_out; 5169 } 5170 if (bp->tx_reserved_rings != bp->tx_nr_rings) { 5171 int tx = bp->tx_nr_rings; 5172 5173 if (bnxt_hwrm_reserve_tx_rings(bp, &tx) || 5174 tx < bp->tx_nr_rings) { 5175 rc = -ENOMEM; 5176 goto err_out; 5177 } 5178 } 5179 } 5180 5181 rc = bnxt_hwrm_ring_alloc(bp); 5182 if (rc) { 5183 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc); 5184 goto err_out; 5185 } 5186 5187 rc = bnxt_hwrm_ring_grp_alloc(bp); 5188 if (rc) { 5189 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc); 5190 goto err_out; 5191 } 5192 5193 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 5194 rx_nr_rings--; 5195 5196 /* default vnic 0 */ 5197 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings); 5198 if (rc) { 5199 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc); 5200 goto err_out; 5201 } 5202 5203 rc = bnxt_setup_vnic(bp, 0); 5204 if (rc) 5205 goto err_out; 5206 5207 if (bp->flags & BNXT_FLAG_RFS) { 5208 rc = bnxt_alloc_rfs_vnics(bp); 5209 if (rc) 5210 goto err_out; 5211 } 5212 5213 if (bp->flags & BNXT_FLAG_TPA) { 5214 rc = bnxt_set_tpa(bp, true); 5215 if (rc) 5216 goto err_out; 5217 } 5218 5219 if (BNXT_VF(bp)) 5220 bnxt_update_vf_mac(bp); 5221 5222 /* Filter for default vnic 0 */ 5223 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr); 5224 if (rc) { 5225 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc); 5226 goto err_out; 5227 } 5228 vnic->uc_filter_count = 1; 5229 5230 vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 5231 5232 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) 5233 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 5234 5235 if (bp->dev->flags & IFF_ALLMULTI) { 5236 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 5237 vnic->mc_list_count = 0; 5238 } else { 5239 u32 mask = 0; 5240 5241 bnxt_mc_list_updated(bp, &mask); 5242 vnic->rx_mask |= mask; 5243 } 5244 5245 rc = bnxt_cfg_rx_mode(bp); 5246 if (rc) 5247 goto err_out; 5248 5249 rc = bnxt_hwrm_set_coal(bp); 5250 if (rc) 5251 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n", 5252 rc); 5253 5254 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 5255 rc = bnxt_setup_nitroa0_vnic(bp); 5256 if (rc) 5257 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n", 5258 rc); 5259 } 5260 5261 if (BNXT_VF(bp)) { 5262 bnxt_hwrm_func_qcfg(bp); 5263 netdev_update_features(bp->dev); 5264 } 5265 5266 return 0; 5267 5268 err_out: 5269 bnxt_hwrm_resource_free(bp, 0, true); 5270 5271 return rc; 5272 } 5273 5274 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init) 5275 { 5276 bnxt_hwrm_resource_free(bp, 1, irq_re_init); 5277 return 0; 5278 } 5279 5280 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init) 5281 { 5282 bnxt_init_cp_rings(bp); 5283 bnxt_init_rx_rings(bp); 5284 bnxt_init_tx_rings(bp); 5285 bnxt_init_ring_grps(bp, irq_re_init); 5286 bnxt_init_vnics(bp); 5287 5288 return bnxt_init_chip(bp, irq_re_init); 5289 } 5290 5291 static int bnxt_set_real_num_queues(struct bnxt *bp) 5292 { 5293 int rc; 5294 struct net_device *dev = bp->dev; 5295 5296 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings - 5297 bp->tx_nr_rings_xdp); 5298 if (rc) 5299 return rc; 5300 5301 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings); 5302 if (rc) 5303 return rc; 5304 5305 #ifdef CONFIG_RFS_ACCEL 5306 if (bp->flags & BNXT_FLAG_RFS) 5307 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings); 5308 #endif 5309 5310 return rc; 5311 } 5312 5313 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 5314 bool shared) 5315 { 5316 int _rx = *rx, _tx = *tx; 5317 5318 if (shared) { 5319 *rx = min_t(int, _rx, max); 5320 *tx = min_t(int, _tx, max); 5321 } else { 5322 if (max < 2) 5323 return -ENOMEM; 5324 5325 while (_rx + _tx > max) { 5326 if (_rx > _tx && _rx > 1) 5327 _rx--; 5328 else if (_tx > 1) 5329 _tx--; 5330 } 5331 *rx = _rx; 5332 *tx = _tx; 5333 } 5334 return 0; 5335 } 5336 5337 static void bnxt_setup_msix(struct bnxt *bp) 5338 { 5339 const int len = sizeof(bp->irq_tbl[0].name); 5340 struct net_device *dev = bp->dev; 5341 int tcs, i; 5342 5343 tcs = netdev_get_num_tc(dev); 5344 if (tcs > 1) { 5345 int i, off, count; 5346 5347 for (i = 0; i < tcs; i++) { 5348 count = bp->tx_nr_rings_per_tc; 5349 off = i * count; 5350 netdev_set_tc_queue(dev, i, count, off); 5351 } 5352 } 5353 5354 for (i = 0; i < bp->cp_nr_rings; i++) { 5355 char *attr; 5356 5357 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 5358 attr = "TxRx"; 5359 else if (i < bp->rx_nr_rings) 5360 attr = "rx"; 5361 else 5362 attr = "tx"; 5363 5364 snprintf(bp->irq_tbl[i].name, len, "%s-%s-%d", dev->name, attr, 5365 i); 5366 bp->irq_tbl[i].handler = bnxt_msix; 5367 } 5368 } 5369 5370 static void bnxt_setup_inta(struct bnxt *bp) 5371 { 5372 const int len = sizeof(bp->irq_tbl[0].name); 5373 5374 if (netdev_get_num_tc(bp->dev)) 5375 netdev_reset_tc(bp->dev); 5376 5377 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx", 5378 0); 5379 bp->irq_tbl[0].handler = bnxt_inta; 5380 } 5381 5382 static int bnxt_setup_int_mode(struct bnxt *bp) 5383 { 5384 int rc; 5385 5386 if (bp->flags & BNXT_FLAG_USING_MSIX) 5387 bnxt_setup_msix(bp); 5388 else 5389 bnxt_setup_inta(bp); 5390 5391 rc = bnxt_set_real_num_queues(bp); 5392 return rc; 5393 } 5394 5395 #ifdef CONFIG_RFS_ACCEL 5396 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp) 5397 { 5398 #if defined(CONFIG_BNXT_SRIOV) 5399 if (BNXT_VF(bp)) 5400 return bp->vf.max_rsscos_ctxs; 5401 #endif 5402 return bp->pf.max_rsscos_ctxs; 5403 } 5404 5405 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp) 5406 { 5407 #if defined(CONFIG_BNXT_SRIOV) 5408 if (BNXT_VF(bp)) 5409 return bp->vf.max_vnics; 5410 #endif 5411 return bp->pf.max_vnics; 5412 } 5413 #endif 5414 5415 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp) 5416 { 5417 #if defined(CONFIG_BNXT_SRIOV) 5418 if (BNXT_VF(bp)) 5419 return bp->vf.max_stat_ctxs; 5420 #endif 5421 return bp->pf.max_stat_ctxs; 5422 } 5423 5424 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max) 5425 { 5426 #if defined(CONFIG_BNXT_SRIOV) 5427 if (BNXT_VF(bp)) 5428 bp->vf.max_stat_ctxs = max; 5429 else 5430 #endif 5431 bp->pf.max_stat_ctxs = max; 5432 } 5433 5434 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp) 5435 { 5436 #if defined(CONFIG_BNXT_SRIOV) 5437 if (BNXT_VF(bp)) 5438 return bp->vf.max_cp_rings; 5439 #endif 5440 return bp->pf.max_cp_rings; 5441 } 5442 5443 void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max) 5444 { 5445 #if defined(CONFIG_BNXT_SRIOV) 5446 if (BNXT_VF(bp)) 5447 bp->vf.max_cp_rings = max; 5448 else 5449 #endif 5450 bp->pf.max_cp_rings = max; 5451 } 5452 5453 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp) 5454 { 5455 #if defined(CONFIG_BNXT_SRIOV) 5456 if (BNXT_VF(bp)) 5457 return min_t(unsigned int, bp->vf.max_irqs, 5458 bp->vf.max_cp_rings); 5459 #endif 5460 return min_t(unsigned int, bp->pf.max_irqs, bp->pf.max_cp_rings); 5461 } 5462 5463 void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs) 5464 { 5465 #if defined(CONFIG_BNXT_SRIOV) 5466 if (BNXT_VF(bp)) 5467 bp->vf.max_irqs = max_irqs; 5468 else 5469 #endif 5470 bp->pf.max_irqs = max_irqs; 5471 } 5472 5473 static int bnxt_init_msix(struct bnxt *bp) 5474 { 5475 int i, total_vecs, rc = 0, min = 1; 5476 struct msix_entry *msix_ent; 5477 5478 total_vecs = bnxt_get_max_func_irqs(bp); 5479 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL); 5480 if (!msix_ent) 5481 return -ENOMEM; 5482 5483 for (i = 0; i < total_vecs; i++) { 5484 msix_ent[i].entry = i; 5485 msix_ent[i].vector = 0; 5486 } 5487 5488 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 5489 min = 2; 5490 5491 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs); 5492 if (total_vecs < 0) { 5493 rc = -ENODEV; 5494 goto msix_setup_exit; 5495 } 5496 5497 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL); 5498 if (bp->irq_tbl) { 5499 for (i = 0; i < total_vecs; i++) 5500 bp->irq_tbl[i].vector = msix_ent[i].vector; 5501 5502 bp->total_irqs = total_vecs; 5503 /* Trim rings based upon num of vectors allocated */ 5504 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings, 5505 total_vecs, min == 1); 5506 if (rc) 5507 goto msix_setup_exit; 5508 5509 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 5510 bp->cp_nr_rings = (min == 1) ? 5511 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 5512 bp->tx_nr_rings + bp->rx_nr_rings; 5513 5514 } else { 5515 rc = -ENOMEM; 5516 goto msix_setup_exit; 5517 } 5518 bp->flags |= BNXT_FLAG_USING_MSIX; 5519 kfree(msix_ent); 5520 return 0; 5521 5522 msix_setup_exit: 5523 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc); 5524 kfree(bp->irq_tbl); 5525 bp->irq_tbl = NULL; 5526 pci_disable_msix(bp->pdev); 5527 kfree(msix_ent); 5528 return rc; 5529 } 5530 5531 static int bnxt_init_inta(struct bnxt *bp) 5532 { 5533 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL); 5534 if (!bp->irq_tbl) 5535 return -ENOMEM; 5536 5537 bp->total_irqs = 1; 5538 bp->rx_nr_rings = 1; 5539 bp->tx_nr_rings = 1; 5540 bp->cp_nr_rings = 1; 5541 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 5542 bp->flags |= BNXT_FLAG_SHARED_RINGS; 5543 bp->irq_tbl[0].vector = bp->pdev->irq; 5544 return 0; 5545 } 5546 5547 static int bnxt_init_int_mode(struct bnxt *bp) 5548 { 5549 int rc = 0; 5550 5551 if (bp->flags & BNXT_FLAG_MSIX_CAP) 5552 rc = bnxt_init_msix(bp); 5553 5554 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) { 5555 /* fallback to INTA */ 5556 rc = bnxt_init_inta(bp); 5557 } 5558 return rc; 5559 } 5560 5561 static void bnxt_clear_int_mode(struct bnxt *bp) 5562 { 5563 if (bp->flags & BNXT_FLAG_USING_MSIX) 5564 pci_disable_msix(bp->pdev); 5565 5566 kfree(bp->irq_tbl); 5567 bp->irq_tbl = NULL; 5568 bp->flags &= ~BNXT_FLAG_USING_MSIX; 5569 } 5570 5571 static void bnxt_free_irq(struct bnxt *bp) 5572 { 5573 struct bnxt_irq *irq; 5574 int i; 5575 5576 #ifdef CONFIG_RFS_ACCEL 5577 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap); 5578 bp->dev->rx_cpu_rmap = NULL; 5579 #endif 5580 if (!bp->irq_tbl) 5581 return; 5582 5583 for (i = 0; i < bp->cp_nr_rings; i++) { 5584 irq = &bp->irq_tbl[i]; 5585 if (irq->requested) { 5586 if (irq->have_cpumask) { 5587 irq_set_affinity_hint(irq->vector, NULL); 5588 free_cpumask_var(irq->cpu_mask); 5589 irq->have_cpumask = 0; 5590 } 5591 free_irq(irq->vector, bp->bnapi[i]); 5592 } 5593 5594 irq->requested = 0; 5595 } 5596 } 5597 5598 static int bnxt_request_irq(struct bnxt *bp) 5599 { 5600 int i, j, rc = 0; 5601 unsigned long flags = 0; 5602 #ifdef CONFIG_RFS_ACCEL 5603 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap; 5604 #endif 5605 5606 if (!(bp->flags & BNXT_FLAG_USING_MSIX)) 5607 flags = IRQF_SHARED; 5608 5609 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) { 5610 struct bnxt_irq *irq = &bp->irq_tbl[i]; 5611 #ifdef CONFIG_RFS_ACCEL 5612 if (rmap && bp->bnapi[i]->rx_ring) { 5613 rc = irq_cpu_rmap_add(rmap, irq->vector); 5614 if (rc) 5615 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n", 5616 j); 5617 j++; 5618 } 5619 #endif 5620 rc = request_irq(irq->vector, irq->handler, flags, irq->name, 5621 bp->bnapi[i]); 5622 if (rc) 5623 break; 5624 5625 irq->requested = 1; 5626 5627 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) { 5628 int numa_node = dev_to_node(&bp->pdev->dev); 5629 5630 irq->have_cpumask = 1; 5631 cpumask_set_cpu(cpumask_local_spread(i, numa_node), 5632 irq->cpu_mask); 5633 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask); 5634 if (rc) { 5635 netdev_warn(bp->dev, 5636 "Set affinity failed, IRQ = %d\n", 5637 irq->vector); 5638 break; 5639 } 5640 } 5641 } 5642 return rc; 5643 } 5644 5645 static void bnxt_del_napi(struct bnxt *bp) 5646 { 5647 int i; 5648 5649 if (!bp->bnapi) 5650 return; 5651 5652 for (i = 0; i < bp->cp_nr_rings; i++) { 5653 struct bnxt_napi *bnapi = bp->bnapi[i]; 5654 5655 napi_hash_del(&bnapi->napi); 5656 netif_napi_del(&bnapi->napi); 5657 } 5658 /* We called napi_hash_del() before netif_napi_del(), we need 5659 * to respect an RCU grace period before freeing napi structures. 5660 */ 5661 synchronize_net(); 5662 } 5663 5664 static void bnxt_init_napi(struct bnxt *bp) 5665 { 5666 int i; 5667 unsigned int cp_nr_rings = bp->cp_nr_rings; 5668 struct bnxt_napi *bnapi; 5669 5670 if (bp->flags & BNXT_FLAG_USING_MSIX) { 5671 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 5672 cp_nr_rings--; 5673 for (i = 0; i < cp_nr_rings; i++) { 5674 bnapi = bp->bnapi[i]; 5675 netif_napi_add(bp->dev, &bnapi->napi, 5676 bnxt_poll, 64); 5677 } 5678 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 5679 bnapi = bp->bnapi[cp_nr_rings]; 5680 netif_napi_add(bp->dev, &bnapi->napi, 5681 bnxt_poll_nitroa0, 64); 5682 } 5683 } else { 5684 bnapi = bp->bnapi[0]; 5685 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64); 5686 } 5687 } 5688 5689 static void bnxt_disable_napi(struct bnxt *bp) 5690 { 5691 int i; 5692 5693 if (!bp->bnapi) 5694 return; 5695 5696 for (i = 0; i < bp->cp_nr_rings; i++) 5697 napi_disable(&bp->bnapi[i]->napi); 5698 } 5699 5700 static void bnxt_enable_napi(struct bnxt *bp) 5701 { 5702 int i; 5703 5704 for (i = 0; i < bp->cp_nr_rings; i++) { 5705 bp->bnapi[i]->in_reset = false; 5706 napi_enable(&bp->bnapi[i]->napi); 5707 } 5708 } 5709 5710 void bnxt_tx_disable(struct bnxt *bp) 5711 { 5712 int i; 5713 struct bnxt_tx_ring_info *txr; 5714 5715 if (bp->tx_ring) { 5716 for (i = 0; i < bp->tx_nr_rings; i++) { 5717 txr = &bp->tx_ring[i]; 5718 txr->dev_state = BNXT_DEV_STATE_CLOSING; 5719 } 5720 } 5721 /* Stop all TX queues */ 5722 netif_tx_disable(bp->dev); 5723 netif_carrier_off(bp->dev); 5724 } 5725 5726 void bnxt_tx_enable(struct bnxt *bp) 5727 { 5728 int i; 5729 struct bnxt_tx_ring_info *txr; 5730 5731 for (i = 0; i < bp->tx_nr_rings; i++) { 5732 txr = &bp->tx_ring[i]; 5733 txr->dev_state = 0; 5734 } 5735 netif_tx_wake_all_queues(bp->dev); 5736 if (bp->link_info.link_up) 5737 netif_carrier_on(bp->dev); 5738 } 5739 5740 static void bnxt_report_link(struct bnxt *bp) 5741 { 5742 if (bp->link_info.link_up) { 5743 const char *duplex; 5744 const char *flow_ctrl; 5745 u32 speed; 5746 u16 fec; 5747 5748 netif_carrier_on(bp->dev); 5749 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL) 5750 duplex = "full"; 5751 else 5752 duplex = "half"; 5753 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH) 5754 flow_ctrl = "ON - receive & transmit"; 5755 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX) 5756 flow_ctrl = "ON - transmit"; 5757 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX) 5758 flow_ctrl = "ON - receive"; 5759 else 5760 flow_ctrl = "none"; 5761 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed); 5762 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n", 5763 speed, duplex, flow_ctrl); 5764 if (bp->flags & BNXT_FLAG_EEE_CAP) 5765 netdev_info(bp->dev, "EEE is %s\n", 5766 bp->eee.eee_active ? "active" : 5767 "not active"); 5768 fec = bp->link_info.fec_cfg; 5769 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED)) 5770 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n", 5771 (fec & BNXT_FEC_AUTONEG) ? "on" : "off", 5772 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" : 5773 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None"); 5774 } else { 5775 netif_carrier_off(bp->dev); 5776 netdev_err(bp->dev, "NIC Link is Down\n"); 5777 } 5778 } 5779 5780 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp) 5781 { 5782 int rc = 0; 5783 struct hwrm_port_phy_qcaps_input req = {0}; 5784 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 5785 struct bnxt_link_info *link_info = &bp->link_info; 5786 5787 if (bp->hwrm_spec_code < 0x10201) 5788 return 0; 5789 5790 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1); 5791 5792 mutex_lock(&bp->hwrm_cmd_lock); 5793 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5794 if (rc) 5795 goto hwrm_phy_qcaps_exit; 5796 5797 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) { 5798 struct ethtool_eee *eee = &bp->eee; 5799 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode); 5800 5801 bp->flags |= BNXT_FLAG_EEE_CAP; 5802 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 5803 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) & 5804 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK; 5805 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) & 5806 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK; 5807 } 5808 if (resp->supported_speeds_auto_mode) 5809 link_info->support_auto_speeds = 5810 le16_to_cpu(resp->supported_speeds_auto_mode); 5811 5812 bp->port_count = resp->port_cnt; 5813 5814 hwrm_phy_qcaps_exit: 5815 mutex_unlock(&bp->hwrm_cmd_lock); 5816 return rc; 5817 } 5818 5819 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state) 5820 { 5821 int rc = 0; 5822 struct bnxt_link_info *link_info = &bp->link_info; 5823 struct hwrm_port_phy_qcfg_input req = {0}; 5824 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 5825 u8 link_up = link_info->link_up; 5826 u16 diff; 5827 5828 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1); 5829 5830 mutex_lock(&bp->hwrm_cmd_lock); 5831 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5832 if (rc) { 5833 mutex_unlock(&bp->hwrm_cmd_lock); 5834 return rc; 5835 } 5836 5837 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp)); 5838 link_info->phy_link_status = resp->link; 5839 link_info->duplex = resp->duplex_cfg; 5840 if (bp->hwrm_spec_code >= 0x10800) 5841 link_info->duplex = resp->duplex_state; 5842 link_info->pause = resp->pause; 5843 link_info->auto_mode = resp->auto_mode; 5844 link_info->auto_pause_setting = resp->auto_pause; 5845 link_info->lp_pause = resp->link_partner_adv_pause; 5846 link_info->force_pause_setting = resp->force_pause; 5847 link_info->duplex_setting = resp->duplex_cfg; 5848 if (link_info->phy_link_status == BNXT_LINK_LINK) 5849 link_info->link_speed = le16_to_cpu(resp->link_speed); 5850 else 5851 link_info->link_speed = 0; 5852 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed); 5853 link_info->support_speeds = le16_to_cpu(resp->support_speeds); 5854 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask); 5855 link_info->lp_auto_link_speeds = 5856 le16_to_cpu(resp->link_partner_adv_speeds); 5857 link_info->preemphasis = le32_to_cpu(resp->preemphasis); 5858 link_info->phy_ver[0] = resp->phy_maj; 5859 link_info->phy_ver[1] = resp->phy_min; 5860 link_info->phy_ver[2] = resp->phy_bld; 5861 link_info->media_type = resp->media_type; 5862 link_info->phy_type = resp->phy_type; 5863 link_info->transceiver = resp->xcvr_pkg_type; 5864 link_info->phy_addr = resp->eee_config_phy_addr & 5865 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK; 5866 link_info->module_status = resp->module_status; 5867 5868 if (bp->flags & BNXT_FLAG_EEE_CAP) { 5869 struct ethtool_eee *eee = &bp->eee; 5870 u16 fw_speeds; 5871 5872 eee->eee_active = 0; 5873 if (resp->eee_config_phy_addr & 5874 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) { 5875 eee->eee_active = 1; 5876 fw_speeds = le16_to_cpu( 5877 resp->link_partner_adv_eee_link_speed_mask); 5878 eee->lp_advertised = 5879 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 5880 } 5881 5882 /* Pull initial EEE config */ 5883 if (!chng_link_state) { 5884 if (resp->eee_config_phy_addr & 5885 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED) 5886 eee->eee_enabled = 1; 5887 5888 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask); 5889 eee->advertised = 5890 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 5891 5892 if (resp->eee_config_phy_addr & 5893 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) { 5894 __le32 tmr; 5895 5896 eee->tx_lpi_enabled = 1; 5897 tmr = resp->xcvr_identifier_type_tx_lpi_timer; 5898 eee->tx_lpi_timer = le32_to_cpu(tmr) & 5899 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK; 5900 } 5901 } 5902 } 5903 5904 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED; 5905 if (bp->hwrm_spec_code >= 0x10504) 5906 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg); 5907 5908 /* TODO: need to add more logic to report VF link */ 5909 if (chng_link_state) { 5910 if (link_info->phy_link_status == BNXT_LINK_LINK) 5911 link_info->link_up = 1; 5912 else 5913 link_info->link_up = 0; 5914 if (link_up != link_info->link_up) 5915 bnxt_report_link(bp); 5916 } else { 5917 /* alwasy link down if not require to update link state */ 5918 link_info->link_up = 0; 5919 } 5920 mutex_unlock(&bp->hwrm_cmd_lock); 5921 5922 diff = link_info->support_auto_speeds ^ link_info->advertising; 5923 if ((link_info->support_auto_speeds | diff) != 5924 link_info->support_auto_speeds) { 5925 /* An advertised speed is no longer supported, so we need to 5926 * update the advertisement settings. Caller holds RTNL 5927 * so we can modify link settings. 5928 */ 5929 link_info->advertising = link_info->support_auto_speeds; 5930 if (link_info->autoneg & BNXT_AUTONEG_SPEED) 5931 bnxt_hwrm_set_link_setting(bp, true, false); 5932 } 5933 return 0; 5934 } 5935 5936 static void bnxt_get_port_module_status(struct bnxt *bp) 5937 { 5938 struct bnxt_link_info *link_info = &bp->link_info; 5939 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp; 5940 u8 module_status; 5941 5942 if (bnxt_update_link(bp, true)) 5943 return; 5944 5945 module_status = link_info->module_status; 5946 switch (module_status) { 5947 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX: 5948 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 5949 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG: 5950 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n", 5951 bp->pf.port_id); 5952 if (bp->hwrm_spec_code >= 0x10201) { 5953 netdev_warn(bp->dev, "Module part number %s\n", 5954 resp->phy_vendor_partnumber); 5955 } 5956 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX) 5957 netdev_warn(bp->dev, "TX is disabled\n"); 5958 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN) 5959 netdev_warn(bp->dev, "SFP+ module is shutdown\n"); 5960 } 5961 } 5962 5963 static void 5964 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req) 5965 { 5966 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) { 5967 if (bp->hwrm_spec_code >= 0x10201) 5968 req->auto_pause = 5969 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 5970 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 5971 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX; 5972 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 5973 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX; 5974 req->enables |= 5975 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 5976 } else { 5977 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 5978 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX; 5979 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 5980 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX; 5981 req->enables |= 5982 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE); 5983 if (bp->hwrm_spec_code >= 0x10201) { 5984 req->auto_pause = req->force_pause; 5985 req->enables |= cpu_to_le32( 5986 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 5987 } 5988 } 5989 } 5990 5991 static void bnxt_hwrm_set_link_common(struct bnxt *bp, 5992 struct hwrm_port_phy_cfg_input *req) 5993 { 5994 u8 autoneg = bp->link_info.autoneg; 5995 u16 fw_link_speed = bp->link_info.req_link_speed; 5996 u16 advertising = bp->link_info.advertising; 5997 5998 if (autoneg & BNXT_AUTONEG_SPEED) { 5999 req->auto_mode |= 6000 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK; 6001 6002 req->enables |= cpu_to_le32( 6003 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK); 6004 req->auto_link_speed_mask = cpu_to_le16(advertising); 6005 6006 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE); 6007 req->flags |= 6008 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG); 6009 } else { 6010 req->force_link_speed = cpu_to_le16(fw_link_speed); 6011 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE); 6012 } 6013 6014 /* tell chimp that the setting takes effect immediately */ 6015 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 6016 } 6017 6018 int bnxt_hwrm_set_pause(struct bnxt *bp) 6019 { 6020 struct hwrm_port_phy_cfg_input req = {0}; 6021 int rc; 6022 6023 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 6024 bnxt_hwrm_set_pause_common(bp, &req); 6025 6026 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) || 6027 bp->link_info.force_link_chng) 6028 bnxt_hwrm_set_link_common(bp, &req); 6029 6030 mutex_lock(&bp->hwrm_cmd_lock); 6031 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6032 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) { 6033 /* since changing of pause setting doesn't trigger any link 6034 * change event, the driver needs to update the current pause 6035 * result upon successfully return of the phy_cfg command 6036 */ 6037 bp->link_info.pause = 6038 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl; 6039 bp->link_info.auto_pause_setting = 0; 6040 if (!bp->link_info.force_link_chng) 6041 bnxt_report_link(bp); 6042 } 6043 bp->link_info.force_link_chng = false; 6044 mutex_unlock(&bp->hwrm_cmd_lock); 6045 return rc; 6046 } 6047 6048 static void bnxt_hwrm_set_eee(struct bnxt *bp, 6049 struct hwrm_port_phy_cfg_input *req) 6050 { 6051 struct ethtool_eee *eee = &bp->eee; 6052 6053 if (eee->eee_enabled) { 6054 u16 eee_speeds; 6055 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE; 6056 6057 if (eee->tx_lpi_enabled) 6058 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE; 6059 else 6060 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE; 6061 6062 req->flags |= cpu_to_le32(flags); 6063 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised); 6064 req->eee_link_speed_mask = cpu_to_le16(eee_speeds); 6065 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer); 6066 } else { 6067 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE); 6068 } 6069 } 6070 6071 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee) 6072 { 6073 struct hwrm_port_phy_cfg_input req = {0}; 6074 6075 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 6076 if (set_pause) 6077 bnxt_hwrm_set_pause_common(bp, &req); 6078 6079 bnxt_hwrm_set_link_common(bp, &req); 6080 6081 if (set_eee) 6082 bnxt_hwrm_set_eee(bp, &req); 6083 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6084 } 6085 6086 static int bnxt_hwrm_shutdown_link(struct bnxt *bp) 6087 { 6088 struct hwrm_port_phy_cfg_input req = {0}; 6089 6090 if (!BNXT_SINGLE_PF(bp)) 6091 return 0; 6092 6093 if (pci_num_vf(bp->pdev)) 6094 return 0; 6095 6096 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 6097 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN); 6098 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6099 } 6100 6101 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp) 6102 { 6103 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 6104 struct hwrm_port_led_qcaps_input req = {0}; 6105 struct bnxt_pf_info *pf = &bp->pf; 6106 int rc; 6107 6108 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601) 6109 return 0; 6110 6111 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1); 6112 req.port_id = cpu_to_le16(pf->port_id); 6113 mutex_lock(&bp->hwrm_cmd_lock); 6114 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6115 if (rc) { 6116 mutex_unlock(&bp->hwrm_cmd_lock); 6117 return rc; 6118 } 6119 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) { 6120 int i; 6121 6122 bp->num_leds = resp->num_leds; 6123 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) * 6124 bp->num_leds); 6125 for (i = 0; i < bp->num_leds; i++) { 6126 struct bnxt_led_info *led = &bp->leds[i]; 6127 __le16 caps = led->led_state_caps; 6128 6129 if (!led->led_group_id || 6130 !BNXT_LED_ALT_BLINK_CAP(caps)) { 6131 bp->num_leds = 0; 6132 break; 6133 } 6134 } 6135 } 6136 mutex_unlock(&bp->hwrm_cmd_lock); 6137 return 0; 6138 } 6139 6140 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp) 6141 { 6142 struct hwrm_wol_filter_alloc_input req = {0}; 6143 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; 6144 int rc; 6145 6146 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1); 6147 req.port_id = cpu_to_le16(bp->pf.port_id); 6148 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT; 6149 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS); 6150 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN); 6151 mutex_lock(&bp->hwrm_cmd_lock); 6152 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6153 if (!rc) 6154 bp->wol_filter_id = resp->wol_filter_id; 6155 mutex_unlock(&bp->hwrm_cmd_lock); 6156 return rc; 6157 } 6158 6159 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp) 6160 { 6161 struct hwrm_wol_filter_free_input req = {0}; 6162 int rc; 6163 6164 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1); 6165 req.port_id = cpu_to_le16(bp->pf.port_id); 6166 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID); 6167 req.wol_filter_id = bp->wol_filter_id; 6168 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6169 return rc; 6170 } 6171 6172 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle) 6173 { 6174 struct hwrm_wol_filter_qcfg_input req = {0}; 6175 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 6176 u16 next_handle = 0; 6177 int rc; 6178 6179 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1); 6180 req.port_id = cpu_to_le16(bp->pf.port_id); 6181 req.handle = cpu_to_le16(handle); 6182 mutex_lock(&bp->hwrm_cmd_lock); 6183 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6184 if (!rc) { 6185 next_handle = le16_to_cpu(resp->next_handle); 6186 if (next_handle != 0) { 6187 if (resp->wol_type == 6188 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) { 6189 bp->wol = 1; 6190 bp->wol_filter_id = resp->wol_filter_id; 6191 } 6192 } 6193 } 6194 mutex_unlock(&bp->hwrm_cmd_lock); 6195 return next_handle; 6196 } 6197 6198 static void bnxt_get_wol_settings(struct bnxt *bp) 6199 { 6200 u16 handle = 0; 6201 6202 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP)) 6203 return; 6204 6205 do { 6206 handle = bnxt_hwrm_get_wol_fltrs(bp, handle); 6207 } while (handle && handle != 0xffff); 6208 } 6209 6210 static bool bnxt_eee_config_ok(struct bnxt *bp) 6211 { 6212 struct ethtool_eee *eee = &bp->eee; 6213 struct bnxt_link_info *link_info = &bp->link_info; 6214 6215 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 6216 return true; 6217 6218 if (eee->eee_enabled) { 6219 u32 advertising = 6220 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 6221 6222 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 6223 eee->eee_enabled = 0; 6224 return false; 6225 } 6226 if (eee->advertised & ~advertising) { 6227 eee->advertised = advertising & eee->supported; 6228 return false; 6229 } 6230 } 6231 return true; 6232 } 6233 6234 static int bnxt_update_phy_setting(struct bnxt *bp) 6235 { 6236 int rc; 6237 bool update_link = false; 6238 bool update_pause = false; 6239 bool update_eee = false; 6240 struct bnxt_link_info *link_info = &bp->link_info; 6241 6242 rc = bnxt_update_link(bp, true); 6243 if (rc) { 6244 netdev_err(bp->dev, "failed to update link (rc: %x)\n", 6245 rc); 6246 return rc; 6247 } 6248 if (!BNXT_SINGLE_PF(bp)) 6249 return 0; 6250 6251 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 6252 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) != 6253 link_info->req_flow_ctrl) 6254 update_pause = true; 6255 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 6256 link_info->force_pause_setting != link_info->req_flow_ctrl) 6257 update_pause = true; 6258 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 6259 if (BNXT_AUTO_MODE(link_info->auto_mode)) 6260 update_link = true; 6261 if (link_info->req_link_speed != link_info->force_link_speed) 6262 update_link = true; 6263 if (link_info->req_duplex != link_info->duplex_setting) 6264 update_link = true; 6265 } else { 6266 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE) 6267 update_link = true; 6268 if (link_info->advertising != link_info->auto_link_speeds) 6269 update_link = true; 6270 } 6271 6272 /* The last close may have shutdown the link, so need to call 6273 * PHY_CFG to bring it back up. 6274 */ 6275 if (!netif_carrier_ok(bp->dev)) 6276 update_link = true; 6277 6278 if (!bnxt_eee_config_ok(bp)) 6279 update_eee = true; 6280 6281 if (update_link) 6282 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee); 6283 else if (update_pause) 6284 rc = bnxt_hwrm_set_pause(bp); 6285 if (rc) { 6286 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n", 6287 rc); 6288 return rc; 6289 } 6290 6291 return rc; 6292 } 6293 6294 /* Common routine to pre-map certain register block to different GRC window. 6295 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows 6296 * in PF and 3 windows in VF that can be customized to map in different 6297 * register blocks. 6298 */ 6299 static void bnxt_preset_reg_win(struct bnxt *bp) 6300 { 6301 if (BNXT_PF(bp)) { 6302 /* CAG registers map to GRC window #4 */ 6303 writel(BNXT_CAG_REG_BASE, 6304 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12); 6305 } 6306 } 6307 6308 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 6309 { 6310 int rc = 0; 6311 6312 bnxt_preset_reg_win(bp); 6313 netif_carrier_off(bp->dev); 6314 if (irq_re_init) { 6315 rc = bnxt_setup_int_mode(bp); 6316 if (rc) { 6317 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n", 6318 rc); 6319 return rc; 6320 } 6321 } 6322 if ((bp->flags & BNXT_FLAG_RFS) && 6323 !(bp->flags & BNXT_FLAG_USING_MSIX)) { 6324 /* disable RFS if falling back to INTA */ 6325 bp->dev->hw_features &= ~NETIF_F_NTUPLE; 6326 bp->flags &= ~BNXT_FLAG_RFS; 6327 } 6328 6329 rc = bnxt_alloc_mem(bp, irq_re_init); 6330 if (rc) { 6331 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 6332 goto open_err_free_mem; 6333 } 6334 6335 if (irq_re_init) { 6336 bnxt_init_napi(bp); 6337 rc = bnxt_request_irq(bp); 6338 if (rc) { 6339 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc); 6340 goto open_err; 6341 } 6342 } 6343 6344 bnxt_enable_napi(bp); 6345 6346 rc = bnxt_init_nic(bp, irq_re_init); 6347 if (rc) { 6348 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 6349 goto open_err; 6350 } 6351 6352 if (link_re_init) { 6353 mutex_lock(&bp->link_lock); 6354 rc = bnxt_update_phy_setting(bp); 6355 mutex_unlock(&bp->link_lock); 6356 if (rc) 6357 netdev_warn(bp->dev, "failed to update phy settings\n"); 6358 } 6359 6360 if (irq_re_init) 6361 udp_tunnel_get_rx_info(bp->dev); 6362 6363 set_bit(BNXT_STATE_OPEN, &bp->state); 6364 bnxt_enable_int(bp); 6365 /* Enable TX queues */ 6366 bnxt_tx_enable(bp); 6367 mod_timer(&bp->timer, jiffies + bp->current_interval); 6368 /* Poll link status and check for SFP+ module status */ 6369 bnxt_get_port_module_status(bp); 6370 6371 /* VF-reps may need to be re-opened after the PF is re-opened */ 6372 if (BNXT_PF(bp)) 6373 bnxt_vf_reps_open(bp); 6374 return 0; 6375 6376 open_err: 6377 bnxt_disable_napi(bp); 6378 bnxt_del_napi(bp); 6379 6380 open_err_free_mem: 6381 bnxt_free_skbs(bp); 6382 bnxt_free_irq(bp); 6383 bnxt_free_mem(bp, true); 6384 return rc; 6385 } 6386 6387 /* rtnl_lock held */ 6388 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 6389 { 6390 int rc = 0; 6391 6392 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init); 6393 if (rc) { 6394 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc); 6395 dev_close(bp->dev); 6396 } 6397 return rc; 6398 } 6399 6400 /* rtnl_lock held, open the NIC half way by allocating all resources, but 6401 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline 6402 * self tests. 6403 */ 6404 int bnxt_half_open_nic(struct bnxt *bp) 6405 { 6406 int rc = 0; 6407 6408 rc = bnxt_alloc_mem(bp, false); 6409 if (rc) { 6410 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 6411 goto half_open_err; 6412 } 6413 rc = bnxt_init_nic(bp, false); 6414 if (rc) { 6415 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 6416 goto half_open_err; 6417 } 6418 return 0; 6419 6420 half_open_err: 6421 bnxt_free_skbs(bp); 6422 bnxt_free_mem(bp, false); 6423 dev_close(bp->dev); 6424 return rc; 6425 } 6426 6427 /* rtnl_lock held, this call can only be made after a previous successful 6428 * call to bnxt_half_open_nic(). 6429 */ 6430 void bnxt_half_close_nic(struct bnxt *bp) 6431 { 6432 bnxt_hwrm_resource_free(bp, false, false); 6433 bnxt_free_skbs(bp); 6434 bnxt_free_mem(bp, false); 6435 } 6436 6437 static int bnxt_open(struct net_device *dev) 6438 { 6439 struct bnxt *bp = netdev_priv(dev); 6440 6441 return __bnxt_open_nic(bp, true, true); 6442 } 6443 6444 static bool bnxt_drv_busy(struct bnxt *bp) 6445 { 6446 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) || 6447 test_bit(BNXT_STATE_READ_STATS, &bp->state)); 6448 } 6449 6450 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 6451 { 6452 int rc = 0; 6453 6454 #ifdef CONFIG_BNXT_SRIOV 6455 if (bp->sriov_cfg) { 6456 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait, 6457 !bp->sriov_cfg, 6458 BNXT_SRIOV_CFG_WAIT_TMO); 6459 if (rc) 6460 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n"); 6461 } 6462 6463 /* Close the VF-reps before closing PF */ 6464 if (BNXT_PF(bp)) 6465 bnxt_vf_reps_close(bp); 6466 #endif 6467 /* Change device state to avoid TX queue wake up's */ 6468 bnxt_tx_disable(bp); 6469 6470 clear_bit(BNXT_STATE_OPEN, &bp->state); 6471 smp_mb__after_atomic(); 6472 while (bnxt_drv_busy(bp)) 6473 msleep(20); 6474 6475 /* Flush rings and and disable interrupts */ 6476 bnxt_shutdown_nic(bp, irq_re_init); 6477 6478 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */ 6479 6480 bnxt_disable_napi(bp); 6481 del_timer_sync(&bp->timer); 6482 bnxt_free_skbs(bp); 6483 6484 if (irq_re_init) { 6485 bnxt_free_irq(bp); 6486 bnxt_del_napi(bp); 6487 } 6488 bnxt_free_mem(bp, irq_re_init); 6489 return rc; 6490 } 6491 6492 static int bnxt_close(struct net_device *dev) 6493 { 6494 struct bnxt *bp = netdev_priv(dev); 6495 6496 bnxt_close_nic(bp, true, true); 6497 bnxt_hwrm_shutdown_link(bp); 6498 return 0; 6499 } 6500 6501 /* rtnl_lock held */ 6502 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 6503 { 6504 switch (cmd) { 6505 case SIOCGMIIPHY: 6506 /* fallthru */ 6507 case SIOCGMIIREG: { 6508 if (!netif_running(dev)) 6509 return -EAGAIN; 6510 6511 return 0; 6512 } 6513 6514 case SIOCSMIIREG: 6515 if (!netif_running(dev)) 6516 return -EAGAIN; 6517 6518 return 0; 6519 6520 default: 6521 /* do nothing */ 6522 break; 6523 } 6524 return -EOPNOTSUPP; 6525 } 6526 6527 static void 6528 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 6529 { 6530 u32 i; 6531 struct bnxt *bp = netdev_priv(dev); 6532 6533 set_bit(BNXT_STATE_READ_STATS, &bp->state); 6534 /* Make sure bnxt_close_nic() sees that we are reading stats before 6535 * we check the BNXT_STATE_OPEN flag. 6536 */ 6537 smp_mb__after_atomic(); 6538 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 6539 clear_bit(BNXT_STATE_READ_STATS, &bp->state); 6540 return; 6541 } 6542 6543 /* TODO check if we need to synchronize with bnxt_close path */ 6544 for (i = 0; i < bp->cp_nr_rings; i++) { 6545 struct bnxt_napi *bnapi = bp->bnapi[i]; 6546 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6547 struct ctx_hw_stats *hw_stats = cpr->hw_stats; 6548 6549 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts); 6550 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts); 6551 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts); 6552 6553 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts); 6554 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts); 6555 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts); 6556 6557 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes); 6558 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes); 6559 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes); 6560 6561 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes); 6562 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes); 6563 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes); 6564 6565 stats->rx_missed_errors += 6566 le64_to_cpu(hw_stats->rx_discard_pkts); 6567 6568 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts); 6569 6570 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts); 6571 } 6572 6573 if (bp->flags & BNXT_FLAG_PORT_STATS) { 6574 struct rx_port_stats *rx = bp->hw_rx_port_stats; 6575 struct tx_port_stats *tx = bp->hw_tx_port_stats; 6576 6577 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames); 6578 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames); 6579 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) + 6580 le64_to_cpu(rx->rx_ovrsz_frames) + 6581 le64_to_cpu(rx->rx_runt_frames); 6582 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) + 6583 le64_to_cpu(rx->rx_jbr_frames); 6584 stats->collisions = le64_to_cpu(tx->tx_total_collisions); 6585 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns); 6586 stats->tx_errors = le64_to_cpu(tx->tx_err); 6587 } 6588 clear_bit(BNXT_STATE_READ_STATS, &bp->state); 6589 } 6590 6591 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask) 6592 { 6593 struct net_device *dev = bp->dev; 6594 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 6595 struct netdev_hw_addr *ha; 6596 u8 *haddr; 6597 int mc_count = 0; 6598 bool update = false; 6599 int off = 0; 6600 6601 netdev_for_each_mc_addr(ha, dev) { 6602 if (mc_count >= BNXT_MAX_MC_ADDRS) { 6603 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 6604 vnic->mc_list_count = 0; 6605 return false; 6606 } 6607 haddr = ha->addr; 6608 if (!ether_addr_equal(haddr, vnic->mc_list + off)) { 6609 memcpy(vnic->mc_list + off, haddr, ETH_ALEN); 6610 update = true; 6611 } 6612 off += ETH_ALEN; 6613 mc_count++; 6614 } 6615 if (mc_count) 6616 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST; 6617 6618 if (mc_count != vnic->mc_list_count) { 6619 vnic->mc_list_count = mc_count; 6620 update = true; 6621 } 6622 return update; 6623 } 6624 6625 static bool bnxt_uc_list_updated(struct bnxt *bp) 6626 { 6627 struct net_device *dev = bp->dev; 6628 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 6629 struct netdev_hw_addr *ha; 6630 int off = 0; 6631 6632 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1)) 6633 return true; 6634 6635 netdev_for_each_uc_addr(ha, dev) { 6636 if (!ether_addr_equal(ha->addr, vnic->uc_list + off)) 6637 return true; 6638 6639 off += ETH_ALEN; 6640 } 6641 return false; 6642 } 6643 6644 static void bnxt_set_rx_mode(struct net_device *dev) 6645 { 6646 struct bnxt *bp = netdev_priv(dev); 6647 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 6648 u32 mask = vnic->rx_mask; 6649 bool mc_update = false; 6650 bool uc_update; 6651 6652 if (!netif_running(dev)) 6653 return; 6654 6655 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS | 6656 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST | 6657 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST); 6658 6659 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) 6660 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 6661 6662 uc_update = bnxt_uc_list_updated(bp); 6663 6664 if (dev->flags & IFF_ALLMULTI) { 6665 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 6666 vnic->mc_list_count = 0; 6667 } else { 6668 mc_update = bnxt_mc_list_updated(bp, &mask); 6669 } 6670 6671 if (mask != vnic->rx_mask || uc_update || mc_update) { 6672 vnic->rx_mask = mask; 6673 6674 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event); 6675 bnxt_queue_sp_work(bp); 6676 } 6677 } 6678 6679 static int bnxt_cfg_rx_mode(struct bnxt *bp) 6680 { 6681 struct net_device *dev = bp->dev; 6682 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 6683 struct netdev_hw_addr *ha; 6684 int i, off = 0, rc; 6685 bool uc_update; 6686 6687 netif_addr_lock_bh(dev); 6688 uc_update = bnxt_uc_list_updated(bp); 6689 netif_addr_unlock_bh(dev); 6690 6691 if (!uc_update) 6692 goto skip_uc; 6693 6694 mutex_lock(&bp->hwrm_cmd_lock); 6695 for (i = 1; i < vnic->uc_filter_count; i++) { 6696 struct hwrm_cfa_l2_filter_free_input req = {0}; 6697 6698 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1, 6699 -1); 6700 6701 req.l2_filter_id = vnic->fw_l2_filter_id[i]; 6702 6703 rc = _hwrm_send_message(bp, &req, sizeof(req), 6704 HWRM_CMD_TIMEOUT); 6705 } 6706 mutex_unlock(&bp->hwrm_cmd_lock); 6707 6708 vnic->uc_filter_count = 1; 6709 6710 netif_addr_lock_bh(dev); 6711 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) { 6712 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 6713 } else { 6714 netdev_for_each_uc_addr(ha, dev) { 6715 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN); 6716 off += ETH_ALEN; 6717 vnic->uc_filter_count++; 6718 } 6719 } 6720 netif_addr_unlock_bh(dev); 6721 6722 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) { 6723 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off); 6724 if (rc) { 6725 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", 6726 rc); 6727 vnic->uc_filter_count = i; 6728 return rc; 6729 } 6730 } 6731 6732 skip_uc: 6733 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); 6734 if (rc) 6735 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n", 6736 rc); 6737 6738 return rc; 6739 } 6740 6741 /* If the chip and firmware supports RFS */ 6742 static bool bnxt_rfs_supported(struct bnxt *bp) 6743 { 6744 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) 6745 return true; 6746 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 6747 return true; 6748 return false; 6749 } 6750 6751 /* If runtime conditions support RFS */ 6752 static bool bnxt_rfs_capable(struct bnxt *bp) 6753 { 6754 #ifdef CONFIG_RFS_ACCEL 6755 int vnics, max_vnics, max_rss_ctxs; 6756 6757 if (!(bp->flags & BNXT_FLAG_MSIX_CAP)) 6758 return false; 6759 6760 vnics = 1 + bp->rx_nr_rings; 6761 max_vnics = bnxt_get_max_func_vnics(bp); 6762 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp); 6763 6764 /* RSS contexts not a limiting factor */ 6765 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 6766 max_rss_ctxs = max_vnics; 6767 if (vnics > max_vnics || vnics > max_rss_ctxs) { 6768 netdev_warn(bp->dev, 6769 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n", 6770 min(max_rss_ctxs - 1, max_vnics - 1)); 6771 return false; 6772 } 6773 6774 return true; 6775 #else 6776 return false; 6777 #endif 6778 } 6779 6780 static netdev_features_t bnxt_fix_features(struct net_device *dev, 6781 netdev_features_t features) 6782 { 6783 struct bnxt *bp = netdev_priv(dev); 6784 6785 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp)) 6786 features &= ~NETIF_F_NTUPLE; 6787 6788 /* Both CTAG and STAG VLAN accelaration on the RX side have to be 6789 * turned on or off together. 6790 */ 6791 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) != 6792 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) { 6793 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX) 6794 features &= ~(NETIF_F_HW_VLAN_CTAG_RX | 6795 NETIF_F_HW_VLAN_STAG_RX); 6796 else 6797 features |= NETIF_F_HW_VLAN_CTAG_RX | 6798 NETIF_F_HW_VLAN_STAG_RX; 6799 } 6800 #ifdef CONFIG_BNXT_SRIOV 6801 if (BNXT_VF(bp)) { 6802 if (bp->vf.vlan) { 6803 features &= ~(NETIF_F_HW_VLAN_CTAG_RX | 6804 NETIF_F_HW_VLAN_STAG_RX); 6805 } 6806 } 6807 #endif 6808 return features; 6809 } 6810 6811 static int bnxt_set_features(struct net_device *dev, netdev_features_t features) 6812 { 6813 struct bnxt *bp = netdev_priv(dev); 6814 u32 flags = bp->flags; 6815 u32 changes; 6816 int rc = 0; 6817 bool re_init = false; 6818 bool update_tpa = false; 6819 6820 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS; 6821 if ((features & NETIF_F_GRO) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) 6822 flags |= BNXT_FLAG_GRO; 6823 if (features & NETIF_F_LRO) 6824 flags |= BNXT_FLAG_LRO; 6825 6826 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 6827 flags &= ~BNXT_FLAG_TPA; 6828 6829 if (features & NETIF_F_HW_VLAN_CTAG_RX) 6830 flags |= BNXT_FLAG_STRIP_VLAN; 6831 6832 if (features & NETIF_F_NTUPLE) 6833 flags |= BNXT_FLAG_RFS; 6834 6835 changes = flags ^ bp->flags; 6836 if (changes & BNXT_FLAG_TPA) { 6837 update_tpa = true; 6838 if ((bp->flags & BNXT_FLAG_TPA) == 0 || 6839 (flags & BNXT_FLAG_TPA) == 0) 6840 re_init = true; 6841 } 6842 6843 if (changes & ~BNXT_FLAG_TPA) 6844 re_init = true; 6845 6846 if (flags != bp->flags) { 6847 u32 old_flags = bp->flags; 6848 6849 bp->flags = flags; 6850 6851 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 6852 if (update_tpa) 6853 bnxt_set_ring_params(bp); 6854 return rc; 6855 } 6856 6857 if (re_init) { 6858 bnxt_close_nic(bp, false, false); 6859 if (update_tpa) 6860 bnxt_set_ring_params(bp); 6861 6862 return bnxt_open_nic(bp, false, false); 6863 } 6864 if (update_tpa) { 6865 rc = bnxt_set_tpa(bp, 6866 (flags & BNXT_FLAG_TPA) ? 6867 true : false); 6868 if (rc) 6869 bp->flags = old_flags; 6870 } 6871 } 6872 return rc; 6873 } 6874 6875 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi) 6876 { 6877 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 6878 int i = bnapi->index; 6879 6880 if (!txr) 6881 return; 6882 6883 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n", 6884 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod, 6885 txr->tx_cons); 6886 } 6887 6888 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi) 6889 { 6890 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 6891 int i = bnapi->index; 6892 6893 if (!rxr) 6894 return; 6895 6896 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n", 6897 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod, 6898 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod, 6899 rxr->rx_sw_agg_prod); 6900 } 6901 6902 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi) 6903 { 6904 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6905 int i = bnapi->index; 6906 6907 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n", 6908 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons); 6909 } 6910 6911 static void bnxt_dbg_dump_states(struct bnxt *bp) 6912 { 6913 int i; 6914 struct bnxt_napi *bnapi; 6915 6916 for (i = 0; i < bp->cp_nr_rings; i++) { 6917 bnapi = bp->bnapi[i]; 6918 if (netif_msg_drv(bp)) { 6919 bnxt_dump_tx_sw_state(bnapi); 6920 bnxt_dump_rx_sw_state(bnapi); 6921 bnxt_dump_cp_sw_state(bnapi); 6922 } 6923 } 6924 } 6925 6926 static void bnxt_reset_task(struct bnxt *bp, bool silent) 6927 { 6928 if (!silent) 6929 bnxt_dbg_dump_states(bp); 6930 if (netif_running(bp->dev)) { 6931 int rc; 6932 6933 if (!silent) 6934 bnxt_ulp_stop(bp); 6935 bnxt_close_nic(bp, false, false); 6936 rc = bnxt_open_nic(bp, false, false); 6937 if (!silent && !rc) 6938 bnxt_ulp_start(bp); 6939 } 6940 } 6941 6942 static void bnxt_tx_timeout(struct net_device *dev) 6943 { 6944 struct bnxt *bp = netdev_priv(dev); 6945 6946 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n"); 6947 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 6948 bnxt_queue_sp_work(bp); 6949 } 6950 6951 #ifdef CONFIG_NET_POLL_CONTROLLER 6952 static void bnxt_poll_controller(struct net_device *dev) 6953 { 6954 struct bnxt *bp = netdev_priv(dev); 6955 int i; 6956 6957 /* Only process tx rings/combined rings in netpoll mode. */ 6958 for (i = 0; i < bp->tx_nr_rings; i++) { 6959 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 6960 6961 napi_schedule(&txr->bnapi->napi); 6962 } 6963 } 6964 #endif 6965 6966 static void bnxt_timer(unsigned long data) 6967 { 6968 struct bnxt *bp = (struct bnxt *)data; 6969 struct net_device *dev = bp->dev; 6970 6971 if (!netif_running(dev)) 6972 return; 6973 6974 if (atomic_read(&bp->intr_sem) != 0) 6975 goto bnxt_restart_timer; 6976 6977 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) && 6978 bp->stats_coal_ticks) { 6979 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event); 6980 bnxt_queue_sp_work(bp); 6981 } 6982 6983 if (bnxt_tc_flower_enabled(bp)) { 6984 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event); 6985 bnxt_queue_sp_work(bp); 6986 } 6987 bnxt_restart_timer: 6988 mod_timer(&bp->timer, jiffies + bp->current_interval); 6989 } 6990 6991 static void bnxt_rtnl_lock_sp(struct bnxt *bp) 6992 { 6993 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK 6994 * set. If the device is being closed, bnxt_close() may be holding 6995 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we 6996 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl(). 6997 */ 6998 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 6999 rtnl_lock(); 7000 } 7001 7002 static void bnxt_rtnl_unlock_sp(struct bnxt *bp) 7003 { 7004 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 7005 rtnl_unlock(); 7006 } 7007 7008 /* Only called from bnxt_sp_task() */ 7009 static void bnxt_reset(struct bnxt *bp, bool silent) 7010 { 7011 bnxt_rtnl_lock_sp(bp); 7012 if (test_bit(BNXT_STATE_OPEN, &bp->state)) 7013 bnxt_reset_task(bp, silent); 7014 bnxt_rtnl_unlock_sp(bp); 7015 } 7016 7017 static void bnxt_cfg_ntp_filters(struct bnxt *); 7018 7019 static void bnxt_sp_task(struct work_struct *work) 7020 { 7021 struct bnxt *bp = container_of(work, struct bnxt, sp_task); 7022 7023 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 7024 smp_mb__after_atomic(); 7025 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 7026 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 7027 return; 7028 } 7029 7030 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event)) 7031 bnxt_cfg_rx_mode(bp); 7032 7033 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event)) 7034 bnxt_cfg_ntp_filters(bp); 7035 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event)) 7036 bnxt_hwrm_exec_fwd_req(bp); 7037 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) { 7038 bnxt_hwrm_tunnel_dst_port_alloc( 7039 bp, bp->vxlan_port, 7040 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 7041 } 7042 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) { 7043 bnxt_hwrm_tunnel_dst_port_free( 7044 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 7045 } 7046 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) { 7047 bnxt_hwrm_tunnel_dst_port_alloc( 7048 bp, bp->nge_port, 7049 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 7050 } 7051 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) { 7052 bnxt_hwrm_tunnel_dst_port_free( 7053 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 7054 } 7055 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) 7056 bnxt_hwrm_port_qstats(bp); 7057 7058 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) { 7059 int rc; 7060 7061 mutex_lock(&bp->link_lock); 7062 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, 7063 &bp->sp_event)) 7064 bnxt_hwrm_phy_qcaps(bp); 7065 7066 rc = bnxt_update_link(bp, true); 7067 mutex_unlock(&bp->link_lock); 7068 if (rc) 7069 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n", 7070 rc); 7071 } 7072 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) { 7073 mutex_lock(&bp->link_lock); 7074 bnxt_get_port_module_status(bp); 7075 mutex_unlock(&bp->link_lock); 7076 } 7077 7078 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event)) 7079 bnxt_tc_flow_stats_work(bp); 7080 7081 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They 7082 * must be the last functions to be called before exiting. 7083 */ 7084 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) 7085 bnxt_reset(bp, false); 7086 7087 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event)) 7088 bnxt_reset(bp, true); 7089 7090 smp_mb__before_atomic(); 7091 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 7092 } 7093 7094 /* Under rtnl_lock */ 7095 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs, 7096 int tx_xdp) 7097 { 7098 int max_rx, max_tx, tx_sets = 1; 7099 int tx_rings_needed; 7100 int rc; 7101 7102 if (tcs) 7103 tx_sets = tcs; 7104 7105 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh); 7106 if (rc) 7107 return rc; 7108 7109 if (max_rx < rx) 7110 return -ENOMEM; 7111 7112 tx_rings_needed = tx * tx_sets + tx_xdp; 7113 if (max_tx < tx_rings_needed) 7114 return -ENOMEM; 7115 7116 return bnxt_hwrm_check_tx_rings(bp, tx_rings_needed); 7117 } 7118 7119 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev) 7120 { 7121 if (bp->bar2) { 7122 pci_iounmap(pdev, bp->bar2); 7123 bp->bar2 = NULL; 7124 } 7125 7126 if (bp->bar1) { 7127 pci_iounmap(pdev, bp->bar1); 7128 bp->bar1 = NULL; 7129 } 7130 7131 if (bp->bar0) { 7132 pci_iounmap(pdev, bp->bar0); 7133 bp->bar0 = NULL; 7134 } 7135 } 7136 7137 static void bnxt_cleanup_pci(struct bnxt *bp) 7138 { 7139 bnxt_unmap_bars(bp, bp->pdev); 7140 pci_release_regions(bp->pdev); 7141 pci_disable_device(bp->pdev); 7142 } 7143 7144 static void bnxt_init_dflt_coal(struct bnxt *bp) 7145 { 7146 struct bnxt_coal *coal; 7147 7148 /* Tick values in micro seconds. 7149 * 1 coal_buf x bufs_per_record = 1 completion record. 7150 */ 7151 coal = &bp->rx_coal; 7152 coal->coal_ticks = 14; 7153 coal->coal_bufs = 30; 7154 coal->coal_ticks_irq = 1; 7155 coal->coal_bufs_irq = 2; 7156 coal->idle_thresh = 25; 7157 coal->bufs_per_record = 2; 7158 coal->budget = 64; /* NAPI budget */ 7159 7160 coal = &bp->tx_coal; 7161 coal->coal_ticks = 28; 7162 coal->coal_bufs = 30; 7163 coal->coal_ticks_irq = 2; 7164 coal->coal_bufs_irq = 2; 7165 coal->bufs_per_record = 1; 7166 7167 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS; 7168 } 7169 7170 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev) 7171 { 7172 int rc; 7173 struct bnxt *bp = netdev_priv(dev); 7174 7175 SET_NETDEV_DEV(dev, &pdev->dev); 7176 7177 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 7178 rc = pci_enable_device(pdev); 7179 if (rc) { 7180 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 7181 goto init_err; 7182 } 7183 7184 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 7185 dev_err(&pdev->dev, 7186 "Cannot find PCI device base address, aborting\n"); 7187 rc = -ENODEV; 7188 goto init_err_disable; 7189 } 7190 7191 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 7192 if (rc) { 7193 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); 7194 goto init_err_disable; 7195 } 7196 7197 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 && 7198 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) { 7199 dev_err(&pdev->dev, "System does not support DMA, aborting\n"); 7200 goto init_err_disable; 7201 } 7202 7203 pci_set_master(pdev); 7204 7205 bp->dev = dev; 7206 bp->pdev = pdev; 7207 7208 bp->bar0 = pci_ioremap_bar(pdev, 0); 7209 if (!bp->bar0) { 7210 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); 7211 rc = -ENOMEM; 7212 goto init_err_release; 7213 } 7214 7215 bp->bar1 = pci_ioremap_bar(pdev, 2); 7216 if (!bp->bar1) { 7217 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n"); 7218 rc = -ENOMEM; 7219 goto init_err_release; 7220 } 7221 7222 bp->bar2 = pci_ioremap_bar(pdev, 4); 7223 if (!bp->bar2) { 7224 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n"); 7225 rc = -ENOMEM; 7226 goto init_err_release; 7227 } 7228 7229 pci_enable_pcie_error_reporting(pdev); 7230 7231 INIT_WORK(&bp->sp_task, bnxt_sp_task); 7232 7233 spin_lock_init(&bp->ntp_fltr_lock); 7234 7235 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE; 7236 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE; 7237 7238 bnxt_init_dflt_coal(bp); 7239 7240 setup_timer(&bp->timer, bnxt_timer, (unsigned long)bp); 7241 bp->current_interval = BNXT_TIMER_INTERVAL; 7242 7243 clear_bit(BNXT_STATE_OPEN, &bp->state); 7244 return 0; 7245 7246 init_err_release: 7247 bnxt_unmap_bars(bp, pdev); 7248 pci_release_regions(pdev); 7249 7250 init_err_disable: 7251 pci_disable_device(pdev); 7252 7253 init_err: 7254 return rc; 7255 } 7256 7257 /* rtnl_lock held */ 7258 static int bnxt_change_mac_addr(struct net_device *dev, void *p) 7259 { 7260 struct sockaddr *addr = p; 7261 struct bnxt *bp = netdev_priv(dev); 7262 int rc = 0; 7263 7264 if (!is_valid_ether_addr(addr->sa_data)) 7265 return -EADDRNOTAVAIL; 7266 7267 if (ether_addr_equal(addr->sa_data, dev->dev_addr)) 7268 return 0; 7269 7270 rc = bnxt_approve_mac(bp, addr->sa_data); 7271 if (rc) 7272 return rc; 7273 7274 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 7275 if (netif_running(dev)) { 7276 bnxt_close_nic(bp, false, false); 7277 rc = bnxt_open_nic(bp, false, false); 7278 } 7279 7280 return rc; 7281 } 7282 7283 /* rtnl_lock held */ 7284 static int bnxt_change_mtu(struct net_device *dev, int new_mtu) 7285 { 7286 struct bnxt *bp = netdev_priv(dev); 7287 7288 if (netif_running(dev)) 7289 bnxt_close_nic(bp, false, false); 7290 7291 dev->mtu = new_mtu; 7292 bnxt_set_ring_params(bp); 7293 7294 if (netif_running(dev)) 7295 return bnxt_open_nic(bp, false, false); 7296 7297 return 0; 7298 } 7299 7300 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc) 7301 { 7302 struct bnxt *bp = netdev_priv(dev); 7303 bool sh = false; 7304 int rc; 7305 7306 if (tc > bp->max_tc) { 7307 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n", 7308 tc, bp->max_tc); 7309 return -EINVAL; 7310 } 7311 7312 if (netdev_get_num_tc(dev) == tc) 7313 return 0; 7314 7315 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 7316 sh = true; 7317 7318 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings, 7319 sh, tc, bp->tx_nr_rings_xdp); 7320 if (rc) 7321 return rc; 7322 7323 /* Needs to close the device and do hw resource re-allocations */ 7324 if (netif_running(bp->dev)) 7325 bnxt_close_nic(bp, true, false); 7326 7327 if (tc) { 7328 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc; 7329 netdev_set_num_tc(dev, tc); 7330 } else { 7331 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 7332 netdev_reset_tc(dev); 7333 } 7334 bp->tx_nr_rings += bp->tx_nr_rings_xdp; 7335 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 7336 bp->tx_nr_rings + bp->rx_nr_rings; 7337 bp->num_stat_ctxs = bp->cp_nr_rings; 7338 7339 if (netif_running(bp->dev)) 7340 return bnxt_open_nic(bp, true, false); 7341 7342 return 0; 7343 } 7344 7345 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 7346 void *cb_priv) 7347 { 7348 struct bnxt *bp = cb_priv; 7349 7350 if (!bnxt_tc_flower_enabled(bp)) 7351 return -EOPNOTSUPP; 7352 7353 switch (type) { 7354 case TC_SETUP_CLSFLOWER: 7355 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data); 7356 default: 7357 return -EOPNOTSUPP; 7358 } 7359 } 7360 7361 static int bnxt_setup_tc_block(struct net_device *dev, 7362 struct tc_block_offload *f) 7363 { 7364 struct bnxt *bp = netdev_priv(dev); 7365 7366 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 7367 return -EOPNOTSUPP; 7368 7369 switch (f->command) { 7370 case TC_BLOCK_BIND: 7371 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb, 7372 bp, bp); 7373 case TC_BLOCK_UNBIND: 7374 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp); 7375 return 0; 7376 default: 7377 return -EOPNOTSUPP; 7378 } 7379 } 7380 7381 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type, 7382 void *type_data) 7383 { 7384 switch (type) { 7385 case TC_SETUP_BLOCK: 7386 return bnxt_setup_tc_block(dev, type_data); 7387 case TC_SETUP_MQPRIO: { 7388 struct tc_mqprio_qopt *mqprio = type_data; 7389 7390 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 7391 7392 return bnxt_setup_mq_tc(dev, mqprio->num_tc); 7393 } 7394 default: 7395 return -EOPNOTSUPP; 7396 } 7397 } 7398 7399 #ifdef CONFIG_RFS_ACCEL 7400 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1, 7401 struct bnxt_ntuple_filter *f2) 7402 { 7403 struct flow_keys *keys1 = &f1->fkeys; 7404 struct flow_keys *keys2 = &f2->fkeys; 7405 7406 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src && 7407 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst && 7408 keys1->ports.ports == keys2->ports.ports && 7409 keys1->basic.ip_proto == keys2->basic.ip_proto && 7410 keys1->basic.n_proto == keys2->basic.n_proto && 7411 keys1->control.flags == keys2->control.flags && 7412 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) && 7413 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr)) 7414 return true; 7415 7416 return false; 7417 } 7418 7419 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 7420 u16 rxq_index, u32 flow_id) 7421 { 7422 struct bnxt *bp = netdev_priv(dev); 7423 struct bnxt_ntuple_filter *fltr, *new_fltr; 7424 struct flow_keys *fkeys; 7425 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb); 7426 int rc = 0, idx, bit_id, l2_idx = 0; 7427 struct hlist_head *head; 7428 7429 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) { 7430 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 7431 int off = 0, j; 7432 7433 netif_addr_lock_bh(dev); 7434 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) { 7435 if (ether_addr_equal(eth->h_dest, 7436 vnic->uc_list + off)) { 7437 l2_idx = j + 1; 7438 break; 7439 } 7440 } 7441 netif_addr_unlock_bh(dev); 7442 if (!l2_idx) 7443 return -EINVAL; 7444 } 7445 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC); 7446 if (!new_fltr) 7447 return -ENOMEM; 7448 7449 fkeys = &new_fltr->fkeys; 7450 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) { 7451 rc = -EPROTONOSUPPORT; 7452 goto err_free; 7453 } 7454 7455 if ((fkeys->basic.n_proto != htons(ETH_P_IP) && 7456 fkeys->basic.n_proto != htons(ETH_P_IPV6)) || 7457 ((fkeys->basic.ip_proto != IPPROTO_TCP) && 7458 (fkeys->basic.ip_proto != IPPROTO_UDP))) { 7459 rc = -EPROTONOSUPPORT; 7460 goto err_free; 7461 } 7462 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) && 7463 bp->hwrm_spec_code < 0x10601) { 7464 rc = -EPROTONOSUPPORT; 7465 goto err_free; 7466 } 7467 if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) && 7468 bp->hwrm_spec_code < 0x10601) { 7469 rc = -EPROTONOSUPPORT; 7470 goto err_free; 7471 } 7472 7473 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN); 7474 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN); 7475 7476 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK; 7477 head = &bp->ntp_fltr_hash_tbl[idx]; 7478 rcu_read_lock(); 7479 hlist_for_each_entry_rcu(fltr, head, hash) { 7480 if (bnxt_fltr_match(fltr, new_fltr)) { 7481 rcu_read_unlock(); 7482 rc = 0; 7483 goto err_free; 7484 } 7485 } 7486 rcu_read_unlock(); 7487 7488 spin_lock_bh(&bp->ntp_fltr_lock); 7489 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap, 7490 BNXT_NTP_FLTR_MAX_FLTR, 0); 7491 if (bit_id < 0) { 7492 spin_unlock_bh(&bp->ntp_fltr_lock); 7493 rc = -ENOMEM; 7494 goto err_free; 7495 } 7496 7497 new_fltr->sw_id = (u16)bit_id; 7498 new_fltr->flow_id = flow_id; 7499 new_fltr->l2_fltr_idx = l2_idx; 7500 new_fltr->rxq = rxq_index; 7501 hlist_add_head_rcu(&new_fltr->hash, head); 7502 bp->ntp_fltr_count++; 7503 spin_unlock_bh(&bp->ntp_fltr_lock); 7504 7505 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); 7506 bnxt_queue_sp_work(bp); 7507 7508 return new_fltr->sw_id; 7509 7510 err_free: 7511 kfree(new_fltr); 7512 return rc; 7513 } 7514 7515 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 7516 { 7517 int i; 7518 7519 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 7520 struct hlist_head *head; 7521 struct hlist_node *tmp; 7522 struct bnxt_ntuple_filter *fltr; 7523 int rc; 7524 7525 head = &bp->ntp_fltr_hash_tbl[i]; 7526 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 7527 bool del = false; 7528 7529 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) { 7530 if (rps_may_expire_flow(bp->dev, fltr->rxq, 7531 fltr->flow_id, 7532 fltr->sw_id)) { 7533 bnxt_hwrm_cfa_ntuple_filter_free(bp, 7534 fltr); 7535 del = true; 7536 } 7537 } else { 7538 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, 7539 fltr); 7540 if (rc) 7541 del = true; 7542 else 7543 set_bit(BNXT_FLTR_VALID, &fltr->state); 7544 } 7545 7546 if (del) { 7547 spin_lock_bh(&bp->ntp_fltr_lock); 7548 hlist_del_rcu(&fltr->hash); 7549 bp->ntp_fltr_count--; 7550 spin_unlock_bh(&bp->ntp_fltr_lock); 7551 synchronize_rcu(); 7552 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap); 7553 kfree(fltr); 7554 } 7555 } 7556 } 7557 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event)) 7558 netdev_info(bp->dev, "Receive PF driver unload event!"); 7559 } 7560 7561 #else 7562 7563 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 7564 { 7565 } 7566 7567 #endif /* CONFIG_RFS_ACCEL */ 7568 7569 static void bnxt_udp_tunnel_add(struct net_device *dev, 7570 struct udp_tunnel_info *ti) 7571 { 7572 struct bnxt *bp = netdev_priv(dev); 7573 7574 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) 7575 return; 7576 7577 if (!netif_running(dev)) 7578 return; 7579 7580 switch (ti->type) { 7581 case UDP_TUNNEL_TYPE_VXLAN: 7582 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port) 7583 return; 7584 7585 bp->vxlan_port_cnt++; 7586 if (bp->vxlan_port_cnt == 1) { 7587 bp->vxlan_port = ti->port; 7588 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event); 7589 bnxt_queue_sp_work(bp); 7590 } 7591 break; 7592 case UDP_TUNNEL_TYPE_GENEVE: 7593 if (bp->nge_port_cnt && bp->nge_port != ti->port) 7594 return; 7595 7596 bp->nge_port_cnt++; 7597 if (bp->nge_port_cnt == 1) { 7598 bp->nge_port = ti->port; 7599 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event); 7600 } 7601 break; 7602 default: 7603 return; 7604 } 7605 7606 bnxt_queue_sp_work(bp); 7607 } 7608 7609 static void bnxt_udp_tunnel_del(struct net_device *dev, 7610 struct udp_tunnel_info *ti) 7611 { 7612 struct bnxt *bp = netdev_priv(dev); 7613 7614 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) 7615 return; 7616 7617 if (!netif_running(dev)) 7618 return; 7619 7620 switch (ti->type) { 7621 case UDP_TUNNEL_TYPE_VXLAN: 7622 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port) 7623 return; 7624 bp->vxlan_port_cnt--; 7625 7626 if (bp->vxlan_port_cnt != 0) 7627 return; 7628 7629 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event); 7630 break; 7631 case UDP_TUNNEL_TYPE_GENEVE: 7632 if (!bp->nge_port_cnt || bp->nge_port != ti->port) 7633 return; 7634 bp->nge_port_cnt--; 7635 7636 if (bp->nge_port_cnt != 0) 7637 return; 7638 7639 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event); 7640 break; 7641 default: 7642 return; 7643 } 7644 7645 bnxt_queue_sp_work(bp); 7646 } 7647 7648 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 7649 struct net_device *dev, u32 filter_mask, 7650 int nlflags) 7651 { 7652 struct bnxt *bp = netdev_priv(dev); 7653 7654 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0, 7655 nlflags, filter_mask, NULL); 7656 } 7657 7658 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, 7659 u16 flags) 7660 { 7661 struct bnxt *bp = netdev_priv(dev); 7662 struct nlattr *attr, *br_spec; 7663 int rem, rc = 0; 7664 7665 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp)) 7666 return -EOPNOTSUPP; 7667 7668 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 7669 if (!br_spec) 7670 return -EINVAL; 7671 7672 nla_for_each_nested(attr, br_spec, rem) { 7673 u16 mode; 7674 7675 if (nla_type(attr) != IFLA_BRIDGE_MODE) 7676 continue; 7677 7678 if (nla_len(attr) < sizeof(mode)) 7679 return -EINVAL; 7680 7681 mode = nla_get_u16(attr); 7682 if (mode == bp->br_mode) 7683 break; 7684 7685 rc = bnxt_hwrm_set_br_mode(bp, mode); 7686 if (!rc) 7687 bp->br_mode = mode; 7688 break; 7689 } 7690 return rc; 7691 } 7692 7693 static int bnxt_get_phys_port_name(struct net_device *dev, char *buf, 7694 size_t len) 7695 { 7696 struct bnxt *bp = netdev_priv(dev); 7697 int rc; 7698 7699 /* The PF and it's VF-reps only support the switchdev framework */ 7700 if (!BNXT_PF(bp)) 7701 return -EOPNOTSUPP; 7702 7703 rc = snprintf(buf, len, "p%d", bp->pf.port_id); 7704 7705 if (rc >= len) 7706 return -EOPNOTSUPP; 7707 return 0; 7708 } 7709 7710 int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr) 7711 { 7712 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV) 7713 return -EOPNOTSUPP; 7714 7715 /* The PF and it's VF-reps only support the switchdev framework */ 7716 if (!BNXT_PF(bp)) 7717 return -EOPNOTSUPP; 7718 7719 switch (attr->id) { 7720 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID: 7721 /* In SRIOV each PF-pool (PF + child VFs) serves as a 7722 * switching domain, the PF's perm mac-addr can be used 7723 * as the unique parent-id 7724 */ 7725 attr->u.ppid.id_len = ETH_ALEN; 7726 ether_addr_copy(attr->u.ppid.id, bp->pf.mac_addr); 7727 break; 7728 default: 7729 return -EOPNOTSUPP; 7730 } 7731 return 0; 7732 } 7733 7734 static int bnxt_swdev_port_attr_get(struct net_device *dev, 7735 struct switchdev_attr *attr) 7736 { 7737 return bnxt_port_attr_get(netdev_priv(dev), attr); 7738 } 7739 7740 static const struct switchdev_ops bnxt_switchdev_ops = { 7741 .switchdev_port_attr_get = bnxt_swdev_port_attr_get 7742 }; 7743 7744 static const struct net_device_ops bnxt_netdev_ops = { 7745 .ndo_open = bnxt_open, 7746 .ndo_start_xmit = bnxt_start_xmit, 7747 .ndo_stop = bnxt_close, 7748 .ndo_get_stats64 = bnxt_get_stats64, 7749 .ndo_set_rx_mode = bnxt_set_rx_mode, 7750 .ndo_do_ioctl = bnxt_ioctl, 7751 .ndo_validate_addr = eth_validate_addr, 7752 .ndo_set_mac_address = bnxt_change_mac_addr, 7753 .ndo_change_mtu = bnxt_change_mtu, 7754 .ndo_fix_features = bnxt_fix_features, 7755 .ndo_set_features = bnxt_set_features, 7756 .ndo_tx_timeout = bnxt_tx_timeout, 7757 #ifdef CONFIG_BNXT_SRIOV 7758 .ndo_get_vf_config = bnxt_get_vf_config, 7759 .ndo_set_vf_mac = bnxt_set_vf_mac, 7760 .ndo_set_vf_vlan = bnxt_set_vf_vlan, 7761 .ndo_set_vf_rate = bnxt_set_vf_bw, 7762 .ndo_set_vf_link_state = bnxt_set_vf_link_state, 7763 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk, 7764 #endif 7765 #ifdef CONFIG_NET_POLL_CONTROLLER 7766 .ndo_poll_controller = bnxt_poll_controller, 7767 #endif 7768 .ndo_setup_tc = bnxt_setup_tc, 7769 #ifdef CONFIG_RFS_ACCEL 7770 .ndo_rx_flow_steer = bnxt_rx_flow_steer, 7771 #endif 7772 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add, 7773 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del, 7774 .ndo_xdp = bnxt_xdp, 7775 .ndo_bridge_getlink = bnxt_bridge_getlink, 7776 .ndo_bridge_setlink = bnxt_bridge_setlink, 7777 .ndo_get_phys_port_name = bnxt_get_phys_port_name 7778 }; 7779 7780 static void bnxt_remove_one(struct pci_dev *pdev) 7781 { 7782 struct net_device *dev = pci_get_drvdata(pdev); 7783 struct bnxt *bp = netdev_priv(dev); 7784 7785 if (BNXT_PF(bp)) { 7786 bnxt_sriov_disable(bp); 7787 bnxt_dl_unregister(bp); 7788 } 7789 7790 pci_disable_pcie_error_reporting(pdev); 7791 unregister_netdev(dev); 7792 bnxt_shutdown_tc(bp); 7793 bnxt_cancel_sp_work(bp); 7794 bp->sp_event = 0; 7795 7796 bnxt_clear_int_mode(bp); 7797 bnxt_hwrm_func_drv_unrgtr(bp); 7798 bnxt_free_hwrm_resources(bp); 7799 bnxt_free_hwrm_short_cmd_req(bp); 7800 bnxt_ethtool_free(bp); 7801 bnxt_dcb_free(bp); 7802 kfree(bp->edev); 7803 bp->edev = NULL; 7804 if (bp->xdp_prog) 7805 bpf_prog_put(bp->xdp_prog); 7806 bnxt_cleanup_pci(bp); 7807 free_netdev(dev); 7808 } 7809 7810 static int bnxt_probe_phy(struct bnxt *bp) 7811 { 7812 int rc = 0; 7813 struct bnxt_link_info *link_info = &bp->link_info; 7814 7815 rc = bnxt_hwrm_phy_qcaps(bp); 7816 if (rc) { 7817 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n", 7818 rc); 7819 return rc; 7820 } 7821 mutex_init(&bp->link_lock); 7822 7823 rc = bnxt_update_link(bp, false); 7824 if (rc) { 7825 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n", 7826 rc); 7827 return rc; 7828 } 7829 7830 /* Older firmware does not have supported_auto_speeds, so assume 7831 * that all supported speeds can be autonegotiated. 7832 */ 7833 if (link_info->auto_link_speeds && !link_info->support_auto_speeds) 7834 link_info->support_auto_speeds = link_info->support_speeds; 7835 7836 /*initialize the ethool setting copy with NVM settings */ 7837 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 7838 link_info->autoneg = BNXT_AUTONEG_SPEED; 7839 if (bp->hwrm_spec_code >= 0x10201) { 7840 if (link_info->auto_pause_setting & 7841 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE) 7842 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 7843 } else { 7844 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 7845 } 7846 link_info->advertising = link_info->auto_link_speeds; 7847 } else { 7848 link_info->req_link_speed = link_info->force_link_speed; 7849 link_info->req_duplex = link_info->duplex_setting; 7850 } 7851 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 7852 link_info->req_flow_ctrl = 7853 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH; 7854 else 7855 link_info->req_flow_ctrl = link_info->force_pause_setting; 7856 return rc; 7857 } 7858 7859 static int bnxt_get_max_irq(struct pci_dev *pdev) 7860 { 7861 u16 ctrl; 7862 7863 if (!pdev->msix_cap) 7864 return 1; 7865 7866 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 7867 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; 7868 } 7869 7870 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, 7871 int *max_cp) 7872 { 7873 int max_ring_grps = 0; 7874 7875 #ifdef CONFIG_BNXT_SRIOV 7876 if (!BNXT_PF(bp)) { 7877 *max_tx = bp->vf.max_tx_rings; 7878 *max_rx = bp->vf.max_rx_rings; 7879 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings); 7880 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs); 7881 max_ring_grps = bp->vf.max_hw_ring_grps; 7882 } else 7883 #endif 7884 { 7885 *max_tx = bp->pf.max_tx_rings; 7886 *max_rx = bp->pf.max_rx_rings; 7887 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings); 7888 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs); 7889 max_ring_grps = bp->pf.max_hw_ring_grps; 7890 } 7891 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) { 7892 *max_cp -= 1; 7893 *max_rx -= 2; 7894 } 7895 if (bp->flags & BNXT_FLAG_AGG_RINGS) 7896 *max_rx >>= 1; 7897 *max_rx = min_t(int, *max_rx, max_ring_grps); 7898 } 7899 7900 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared) 7901 { 7902 int rx, tx, cp; 7903 7904 _bnxt_get_max_rings(bp, &rx, &tx, &cp); 7905 if (!rx || !tx || !cp) 7906 return -ENOMEM; 7907 7908 *max_rx = rx; 7909 *max_tx = tx; 7910 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared); 7911 } 7912 7913 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx, 7914 bool shared) 7915 { 7916 int rc; 7917 7918 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 7919 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) { 7920 /* Not enough rings, try disabling agg rings. */ 7921 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 7922 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 7923 if (rc) 7924 return rc; 7925 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 7926 bp->dev->hw_features &= ~NETIF_F_LRO; 7927 bp->dev->features &= ~NETIF_F_LRO; 7928 bnxt_set_ring_params(bp); 7929 } 7930 7931 if (bp->flags & BNXT_FLAG_ROCE_CAP) { 7932 int max_cp, max_stat, max_irq; 7933 7934 /* Reserve minimum resources for RoCE */ 7935 max_cp = bnxt_get_max_func_cp_rings(bp); 7936 max_stat = bnxt_get_max_func_stat_ctxs(bp); 7937 max_irq = bnxt_get_max_func_irqs(bp); 7938 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS || 7939 max_irq <= BNXT_MIN_ROCE_CP_RINGS || 7940 max_stat <= BNXT_MIN_ROCE_STAT_CTXS) 7941 return 0; 7942 7943 max_cp -= BNXT_MIN_ROCE_CP_RINGS; 7944 max_irq -= BNXT_MIN_ROCE_CP_RINGS; 7945 max_stat -= BNXT_MIN_ROCE_STAT_CTXS; 7946 max_cp = min_t(int, max_cp, max_irq); 7947 max_cp = min_t(int, max_cp, max_stat); 7948 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared); 7949 if (rc) 7950 rc = 0; 7951 } 7952 return rc; 7953 } 7954 7955 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh) 7956 { 7957 int dflt_rings, max_rx_rings, max_tx_rings, rc; 7958 7959 if (sh) 7960 bp->flags |= BNXT_FLAG_SHARED_RINGS; 7961 dflt_rings = netif_get_num_default_rss_queues(); 7962 /* Reduce default rings to reduce memory usage on multi-port cards */ 7963 if (bp->port_count > 1) 7964 dflt_rings = min_t(int, dflt_rings, 4); 7965 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh); 7966 if (rc) 7967 return rc; 7968 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings); 7969 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings); 7970 7971 rc = bnxt_hwrm_reserve_tx_rings(bp, &bp->tx_nr_rings_per_tc); 7972 if (rc) 7973 netdev_warn(bp->dev, "Unable to reserve tx rings\n"); 7974 7975 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 7976 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 7977 bp->tx_nr_rings + bp->rx_nr_rings; 7978 bp->num_stat_ctxs = bp->cp_nr_rings; 7979 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 7980 bp->rx_nr_rings++; 7981 bp->cp_nr_rings++; 7982 } 7983 return rc; 7984 } 7985 7986 void bnxt_restore_pf_fw_resources(struct bnxt *bp) 7987 { 7988 ASSERT_RTNL(); 7989 bnxt_hwrm_func_qcaps(bp); 7990 bnxt_subtract_ulp_resources(bp, BNXT_ROCE_ULP); 7991 } 7992 7993 static int bnxt_init_mac_addr(struct bnxt *bp) 7994 { 7995 int rc = 0; 7996 7997 if (BNXT_PF(bp)) { 7998 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN); 7999 } else { 8000 #ifdef CONFIG_BNXT_SRIOV 8001 struct bnxt_vf_info *vf = &bp->vf; 8002 8003 if (is_valid_ether_addr(vf->mac_addr)) { 8004 /* overwrite netdev dev_adr with admin VF MAC */ 8005 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN); 8006 } else { 8007 eth_hw_addr_random(bp->dev); 8008 rc = bnxt_approve_mac(bp, bp->dev->dev_addr); 8009 } 8010 #endif 8011 } 8012 return rc; 8013 } 8014 8015 static void bnxt_parse_log_pcie_link(struct bnxt *bp) 8016 { 8017 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN; 8018 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN; 8019 8020 if (pcie_get_minimum_link(pci_physfn(bp->pdev), &speed, &width) || 8021 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) 8022 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n"); 8023 else 8024 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n", 8025 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : 8026 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : 8027 speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : 8028 "Unknown", width); 8029 } 8030 8031 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 8032 { 8033 static int version_printed; 8034 struct net_device *dev; 8035 struct bnxt *bp; 8036 int rc, max_irqs; 8037 8038 if (pci_is_bridge(pdev)) 8039 return -ENODEV; 8040 8041 if (version_printed++ == 0) 8042 pr_info("%s", version); 8043 8044 max_irqs = bnxt_get_max_irq(pdev); 8045 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs); 8046 if (!dev) 8047 return -ENOMEM; 8048 8049 bp = netdev_priv(dev); 8050 8051 if (bnxt_vf_pciid(ent->driver_data)) 8052 bp->flags |= BNXT_FLAG_VF; 8053 8054 if (pdev->msix_cap) 8055 bp->flags |= BNXT_FLAG_MSIX_CAP; 8056 8057 rc = bnxt_init_board(pdev, dev); 8058 if (rc < 0) 8059 goto init_err_free; 8060 8061 dev->netdev_ops = &bnxt_netdev_ops; 8062 dev->watchdog_timeo = BNXT_TX_TIMEOUT; 8063 dev->ethtool_ops = &bnxt_ethtool_ops; 8064 SWITCHDEV_SET_OPS(dev, &bnxt_switchdev_ops); 8065 pci_set_drvdata(pdev, dev); 8066 8067 rc = bnxt_alloc_hwrm_resources(bp); 8068 if (rc) 8069 goto init_err_pci_clean; 8070 8071 mutex_init(&bp->hwrm_cmd_lock); 8072 rc = bnxt_hwrm_ver_get(bp); 8073 if (rc) 8074 goto init_err_pci_clean; 8075 8076 if (bp->flags & BNXT_FLAG_SHORT_CMD) { 8077 rc = bnxt_alloc_hwrm_short_cmd_req(bp); 8078 if (rc) 8079 goto init_err_pci_clean; 8080 } 8081 8082 rc = bnxt_hwrm_func_reset(bp); 8083 if (rc) 8084 goto init_err_pci_clean; 8085 8086 bnxt_hwrm_fw_set_time(bp); 8087 8088 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 8089 NETIF_F_TSO | NETIF_F_TSO6 | 8090 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 8091 NETIF_F_GSO_IPXIP4 | 8092 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 8093 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH | 8094 NETIF_F_RXCSUM | NETIF_F_GRO; 8095 8096 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) 8097 dev->hw_features |= NETIF_F_LRO; 8098 8099 dev->hw_enc_features = 8100 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 8101 NETIF_F_TSO | NETIF_F_TSO6 | 8102 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 8103 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 8104 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL; 8105 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM | 8106 NETIF_F_GSO_GRE_CSUM; 8107 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA; 8108 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 8109 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX; 8110 dev->features |= dev->hw_features | NETIF_F_HIGHDMA; 8111 dev->priv_flags |= IFF_UNICAST_FLT; 8112 8113 #ifdef CONFIG_BNXT_SRIOV 8114 init_waitqueue_head(&bp->sriov_cfg_wait); 8115 mutex_init(&bp->sriov_lock); 8116 #endif 8117 bp->gro_func = bnxt_gro_func_5730x; 8118 if (BNXT_CHIP_P4_PLUS(bp)) 8119 bp->gro_func = bnxt_gro_func_5731x; 8120 else 8121 bp->flags |= BNXT_FLAG_DOUBLE_DB; 8122 8123 rc = bnxt_hwrm_func_drv_rgtr(bp); 8124 if (rc) 8125 goto init_err_pci_clean; 8126 8127 rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0); 8128 if (rc) 8129 goto init_err_pci_clean; 8130 8131 bp->ulp_probe = bnxt_ulp_probe; 8132 8133 /* Get the MAX capabilities for this function */ 8134 rc = bnxt_hwrm_func_qcaps(bp); 8135 if (rc) { 8136 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n", 8137 rc); 8138 rc = -1; 8139 goto init_err_pci_clean; 8140 } 8141 rc = bnxt_init_mac_addr(bp); 8142 if (rc) { 8143 dev_err(&pdev->dev, "Unable to initialize mac address.\n"); 8144 rc = -EADDRNOTAVAIL; 8145 goto init_err_pci_clean; 8146 } 8147 rc = bnxt_hwrm_queue_qportcfg(bp); 8148 if (rc) { 8149 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n", 8150 rc); 8151 rc = -1; 8152 goto init_err_pci_clean; 8153 } 8154 8155 bnxt_hwrm_func_qcfg(bp); 8156 bnxt_hwrm_port_led_qcaps(bp); 8157 bnxt_ethtool_init(bp); 8158 bnxt_dcb_init(bp); 8159 8160 /* MTU range: 60 - FW defined max */ 8161 dev->min_mtu = ETH_ZLEN; 8162 dev->max_mtu = bp->max_mtu; 8163 8164 rc = bnxt_probe_phy(bp); 8165 if (rc) 8166 goto init_err_pci_clean; 8167 8168 bnxt_set_rx_skb_mode(bp, false); 8169 bnxt_set_tpa_flags(bp); 8170 bnxt_set_ring_params(bp); 8171 bnxt_set_max_func_irqs(bp, max_irqs); 8172 rc = bnxt_set_dflt_rings(bp, true); 8173 if (rc) { 8174 netdev_err(bp->dev, "Not enough rings available.\n"); 8175 rc = -ENOMEM; 8176 goto init_err_pci_clean; 8177 } 8178 8179 /* Default RSS hash cfg. */ 8180 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 | 8181 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 | 8182 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 | 8183 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 8184 if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) { 8185 bp->flags |= BNXT_FLAG_UDP_RSS_CAP; 8186 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 | 8187 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 8188 } 8189 8190 bnxt_hwrm_vnic_qcaps(bp); 8191 if (bnxt_rfs_supported(bp)) { 8192 dev->hw_features |= NETIF_F_NTUPLE; 8193 if (bnxt_rfs_capable(bp)) { 8194 bp->flags |= BNXT_FLAG_RFS; 8195 dev->features |= NETIF_F_NTUPLE; 8196 } 8197 } 8198 8199 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX) 8200 bp->flags |= BNXT_FLAG_STRIP_VLAN; 8201 8202 rc = bnxt_init_int_mode(bp); 8203 if (rc) 8204 goto init_err_pci_clean; 8205 8206 bnxt_get_wol_settings(bp); 8207 if (bp->flags & BNXT_FLAG_WOL_CAP) 8208 device_set_wakeup_enable(&pdev->dev, bp->wol); 8209 else 8210 device_set_wakeup_capable(&pdev->dev, false); 8211 8212 if (BNXT_PF(bp)) { 8213 if (!bnxt_pf_wq) { 8214 bnxt_pf_wq = 8215 create_singlethread_workqueue("bnxt_pf_wq"); 8216 if (!bnxt_pf_wq) { 8217 dev_err(&pdev->dev, "Unable to create workqueue.\n"); 8218 goto init_err_pci_clean; 8219 } 8220 } 8221 bnxt_init_tc(bp); 8222 } 8223 8224 rc = register_netdev(dev); 8225 if (rc) 8226 goto init_err_cleanup_tc; 8227 8228 if (BNXT_PF(bp)) 8229 bnxt_dl_register(bp); 8230 8231 netdev_info(dev, "%s found at mem %lx, node addr %pM\n", 8232 board_info[ent->driver_data].name, 8233 (long)pci_resource_start(pdev, 0), dev->dev_addr); 8234 8235 bnxt_parse_log_pcie_link(bp); 8236 8237 return 0; 8238 8239 init_err_cleanup_tc: 8240 bnxt_shutdown_tc(bp); 8241 bnxt_clear_int_mode(bp); 8242 8243 init_err_pci_clean: 8244 bnxt_cleanup_pci(bp); 8245 8246 init_err_free: 8247 free_netdev(dev); 8248 return rc; 8249 } 8250 8251 static void bnxt_shutdown(struct pci_dev *pdev) 8252 { 8253 struct net_device *dev = pci_get_drvdata(pdev); 8254 struct bnxt *bp; 8255 8256 if (!dev) 8257 return; 8258 8259 rtnl_lock(); 8260 bp = netdev_priv(dev); 8261 if (!bp) 8262 goto shutdown_exit; 8263 8264 if (netif_running(dev)) 8265 dev_close(dev); 8266 8267 if (system_state == SYSTEM_POWER_OFF) { 8268 bnxt_ulp_shutdown(bp); 8269 bnxt_clear_int_mode(bp); 8270 pci_wake_from_d3(pdev, bp->wol); 8271 pci_set_power_state(pdev, PCI_D3hot); 8272 } 8273 8274 shutdown_exit: 8275 rtnl_unlock(); 8276 } 8277 8278 #ifdef CONFIG_PM_SLEEP 8279 static int bnxt_suspend(struct device *device) 8280 { 8281 struct pci_dev *pdev = to_pci_dev(device); 8282 struct net_device *dev = pci_get_drvdata(pdev); 8283 struct bnxt *bp = netdev_priv(dev); 8284 int rc = 0; 8285 8286 rtnl_lock(); 8287 if (netif_running(dev)) { 8288 netif_device_detach(dev); 8289 rc = bnxt_close(dev); 8290 } 8291 bnxt_hwrm_func_drv_unrgtr(bp); 8292 rtnl_unlock(); 8293 return rc; 8294 } 8295 8296 static int bnxt_resume(struct device *device) 8297 { 8298 struct pci_dev *pdev = to_pci_dev(device); 8299 struct net_device *dev = pci_get_drvdata(pdev); 8300 struct bnxt *bp = netdev_priv(dev); 8301 int rc = 0; 8302 8303 rtnl_lock(); 8304 if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) { 8305 rc = -ENODEV; 8306 goto resume_exit; 8307 } 8308 rc = bnxt_hwrm_func_reset(bp); 8309 if (rc) { 8310 rc = -EBUSY; 8311 goto resume_exit; 8312 } 8313 bnxt_get_wol_settings(bp); 8314 if (netif_running(dev)) { 8315 rc = bnxt_open(dev); 8316 if (!rc) 8317 netif_device_attach(dev); 8318 } 8319 8320 resume_exit: 8321 rtnl_unlock(); 8322 return rc; 8323 } 8324 8325 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume); 8326 #define BNXT_PM_OPS (&bnxt_pm_ops) 8327 8328 #else 8329 8330 #define BNXT_PM_OPS NULL 8331 8332 #endif /* CONFIG_PM_SLEEP */ 8333 8334 /** 8335 * bnxt_io_error_detected - called when PCI error is detected 8336 * @pdev: Pointer to PCI device 8337 * @state: The current pci connection state 8338 * 8339 * This function is called after a PCI bus error affecting 8340 * this device has been detected. 8341 */ 8342 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev, 8343 pci_channel_state_t state) 8344 { 8345 struct net_device *netdev = pci_get_drvdata(pdev); 8346 struct bnxt *bp = netdev_priv(netdev); 8347 8348 netdev_info(netdev, "PCI I/O error detected\n"); 8349 8350 rtnl_lock(); 8351 netif_device_detach(netdev); 8352 8353 bnxt_ulp_stop(bp); 8354 8355 if (state == pci_channel_io_perm_failure) { 8356 rtnl_unlock(); 8357 return PCI_ERS_RESULT_DISCONNECT; 8358 } 8359 8360 if (netif_running(netdev)) 8361 bnxt_close(netdev); 8362 8363 pci_disable_device(pdev); 8364 rtnl_unlock(); 8365 8366 /* Request a slot slot reset. */ 8367 return PCI_ERS_RESULT_NEED_RESET; 8368 } 8369 8370 /** 8371 * bnxt_io_slot_reset - called after the pci bus has been reset. 8372 * @pdev: Pointer to PCI device 8373 * 8374 * Restart the card from scratch, as if from a cold-boot. 8375 * At this point, the card has exprienced a hard reset, 8376 * followed by fixups by BIOS, and has its config space 8377 * set up identically to what it was at cold boot. 8378 */ 8379 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev) 8380 { 8381 struct net_device *netdev = pci_get_drvdata(pdev); 8382 struct bnxt *bp = netdev_priv(netdev); 8383 int err = 0; 8384 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT; 8385 8386 netdev_info(bp->dev, "PCI Slot Reset\n"); 8387 8388 rtnl_lock(); 8389 8390 if (pci_enable_device(pdev)) { 8391 dev_err(&pdev->dev, 8392 "Cannot re-enable PCI device after reset.\n"); 8393 } else { 8394 pci_set_master(pdev); 8395 8396 err = bnxt_hwrm_func_reset(bp); 8397 if (!err && netif_running(netdev)) 8398 err = bnxt_open(netdev); 8399 8400 if (!err) { 8401 result = PCI_ERS_RESULT_RECOVERED; 8402 bnxt_ulp_start(bp); 8403 } 8404 } 8405 8406 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev)) 8407 dev_close(netdev); 8408 8409 rtnl_unlock(); 8410 8411 err = pci_cleanup_aer_uncorrect_error_status(pdev); 8412 if (err) { 8413 dev_err(&pdev->dev, 8414 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 8415 err); /* non-fatal, continue */ 8416 } 8417 8418 return PCI_ERS_RESULT_RECOVERED; 8419 } 8420 8421 /** 8422 * bnxt_io_resume - called when traffic can start flowing again. 8423 * @pdev: Pointer to PCI device 8424 * 8425 * This callback is called when the error recovery driver tells 8426 * us that its OK to resume normal operation. 8427 */ 8428 static void bnxt_io_resume(struct pci_dev *pdev) 8429 { 8430 struct net_device *netdev = pci_get_drvdata(pdev); 8431 8432 rtnl_lock(); 8433 8434 netif_device_attach(netdev); 8435 8436 rtnl_unlock(); 8437 } 8438 8439 static const struct pci_error_handlers bnxt_err_handler = { 8440 .error_detected = bnxt_io_error_detected, 8441 .slot_reset = bnxt_io_slot_reset, 8442 .resume = bnxt_io_resume 8443 }; 8444 8445 static struct pci_driver bnxt_pci_driver = { 8446 .name = DRV_MODULE_NAME, 8447 .id_table = bnxt_pci_tbl, 8448 .probe = bnxt_init_one, 8449 .remove = bnxt_remove_one, 8450 .shutdown = bnxt_shutdown, 8451 .driver.pm = BNXT_PM_OPS, 8452 .err_handler = &bnxt_err_handler, 8453 #if defined(CONFIG_BNXT_SRIOV) 8454 .sriov_configure = bnxt_sriov_configure, 8455 #endif 8456 }; 8457 8458 static int __init bnxt_init(void) 8459 { 8460 return pci_register_driver(&bnxt_pci_driver); 8461 } 8462 8463 static void __exit bnxt_exit(void) 8464 { 8465 pci_unregister_driver(&bnxt_pci_driver); 8466 if (bnxt_pf_wq) 8467 destroy_workqueue(bnxt_pf_wq); 8468 } 8469 8470 module_init(bnxt_init); 8471 module_exit(bnxt_exit); 8472