1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2019 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 13 #include <linux/stringify.h> 14 #include <linux/kernel.h> 15 #include <linux/timer.h> 16 #include <linux/errno.h> 17 #include <linux/ioport.h> 18 #include <linux/slab.h> 19 #include <linux/vmalloc.h> 20 #include <linux/interrupt.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/etherdevice.h> 24 #include <linux/skbuff.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/bitops.h> 27 #include <linux/io.h> 28 #include <linux/irq.h> 29 #include <linux/delay.h> 30 #include <asm/byteorder.h> 31 #include <asm/page.h> 32 #include <linux/time.h> 33 #include <linux/mii.h> 34 #include <linux/mdio.h> 35 #include <linux/if.h> 36 #include <linux/if_vlan.h> 37 #include <linux/if_bridge.h> 38 #include <linux/rtc.h> 39 #include <linux/bpf.h> 40 #include <net/ip.h> 41 #include <net/tcp.h> 42 #include <net/udp.h> 43 #include <net/checksum.h> 44 #include <net/ip6_checksum.h> 45 #include <net/udp_tunnel.h> 46 #include <linux/workqueue.h> 47 #include <linux/prefetch.h> 48 #include <linux/cache.h> 49 #include <linux/log2.h> 50 #include <linux/aer.h> 51 #include <linux/bitmap.h> 52 #include <linux/cpu_rmap.h> 53 #include <linux/cpumask.h> 54 #include <net/pkt_cls.h> 55 #include <linux/hwmon.h> 56 #include <linux/hwmon-sysfs.h> 57 #include <net/page_pool.h> 58 59 #include "bnxt_hsi.h" 60 #include "bnxt.h" 61 #include "bnxt_ulp.h" 62 #include "bnxt_sriov.h" 63 #include "bnxt_ethtool.h" 64 #include "bnxt_dcb.h" 65 #include "bnxt_xdp.h" 66 #include "bnxt_vfr.h" 67 #include "bnxt_tc.h" 68 #include "bnxt_devlink.h" 69 #include "bnxt_debugfs.h" 70 71 #define BNXT_TX_TIMEOUT (5 * HZ) 72 73 MODULE_LICENSE("GPL"); 74 MODULE_DESCRIPTION("Broadcom BCM573xx network driver"); 75 76 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN) 77 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD 78 #define BNXT_RX_COPY_THRESH 256 79 80 #define BNXT_TX_PUSH_THRESH 164 81 82 enum board_idx { 83 BCM57301, 84 BCM57302, 85 BCM57304, 86 BCM57417_NPAR, 87 BCM58700, 88 BCM57311, 89 BCM57312, 90 BCM57402, 91 BCM57404, 92 BCM57406, 93 BCM57402_NPAR, 94 BCM57407, 95 BCM57412, 96 BCM57414, 97 BCM57416, 98 BCM57417, 99 BCM57412_NPAR, 100 BCM57314, 101 BCM57417_SFP, 102 BCM57416_SFP, 103 BCM57404_NPAR, 104 BCM57406_NPAR, 105 BCM57407_SFP, 106 BCM57407_NPAR, 107 BCM57414_NPAR, 108 BCM57416_NPAR, 109 BCM57452, 110 BCM57454, 111 BCM5745x_NPAR, 112 BCM57508, 113 BCM57504, 114 BCM57502, 115 BCM57508_NPAR, 116 BCM57504_NPAR, 117 BCM57502_NPAR, 118 BCM58802, 119 BCM58804, 120 BCM58808, 121 NETXTREME_E_VF, 122 NETXTREME_C_VF, 123 NETXTREME_S_VF, 124 NETXTREME_E_P5_VF, 125 }; 126 127 /* indexed by enum above */ 128 static const struct { 129 char *name; 130 } board_info[] = { 131 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" }, 132 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" }, 133 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 134 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" }, 135 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" }, 136 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" }, 137 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" }, 138 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" }, 139 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" }, 140 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" }, 141 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" }, 142 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" }, 143 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" }, 144 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" }, 145 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" }, 146 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" }, 147 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" }, 148 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 149 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" }, 150 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" }, 151 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" }, 152 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" }, 153 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" }, 154 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" }, 155 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" }, 156 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" }, 157 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" }, 158 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 159 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" }, 160 [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, 161 [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, 162 [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" }, 163 [BCM57508_NPAR] = { "Broadcom BCM57508 NetXtreme-E Ethernet Partition" }, 164 [BCM57504_NPAR] = { "Broadcom BCM57504 NetXtreme-E Ethernet Partition" }, 165 [BCM57502_NPAR] = { "Broadcom BCM57502 NetXtreme-E Ethernet Partition" }, 166 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" }, 167 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 168 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 169 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" }, 170 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" }, 171 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" }, 172 [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" }, 173 }; 174 175 static const struct pci_device_id bnxt_pci_tbl[] = { 176 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR }, 177 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR }, 178 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 }, 179 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR }, 180 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 }, 181 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 }, 182 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 }, 183 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR }, 184 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 }, 185 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 }, 186 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 }, 187 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 }, 188 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 }, 189 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 }, 190 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR }, 191 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 }, 192 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 }, 193 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 }, 194 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 }, 195 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 }, 196 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR }, 197 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 }, 198 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP }, 199 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP }, 200 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR }, 201 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR }, 202 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP }, 203 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR }, 204 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR }, 205 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR }, 206 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR }, 207 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR }, 208 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR }, 209 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 }, 210 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 }, 211 { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 }, 212 { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 }, 213 { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 }, 214 { PCI_VDEVICE(BROADCOM, 0x1800), .driver_data = BCM57508_NPAR }, 215 { PCI_VDEVICE(BROADCOM, 0x1801), .driver_data = BCM57504_NPAR }, 216 { PCI_VDEVICE(BROADCOM, 0x1802), .driver_data = BCM57502_NPAR }, 217 { PCI_VDEVICE(BROADCOM, 0x1803), .driver_data = BCM57508_NPAR }, 218 { PCI_VDEVICE(BROADCOM, 0x1804), .driver_data = BCM57504_NPAR }, 219 { PCI_VDEVICE(BROADCOM, 0x1805), .driver_data = BCM57502_NPAR }, 220 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 }, 221 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 }, 222 #ifdef CONFIG_BNXT_SRIOV 223 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF }, 224 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF }, 225 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF }, 226 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF }, 227 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF }, 228 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF }, 229 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF }, 230 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF }, 231 { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF }, 232 { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF }, 233 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF }, 234 #endif 235 { 0 } 236 }; 237 238 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl); 239 240 static const u16 bnxt_vf_req_snif[] = { 241 HWRM_FUNC_CFG, 242 HWRM_FUNC_VF_CFG, 243 HWRM_PORT_PHY_QCFG, 244 HWRM_CFA_L2_FILTER_ALLOC, 245 }; 246 247 static const u16 bnxt_async_events_arr[] = { 248 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE, 249 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE, 250 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD, 251 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED, 252 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE, 253 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE, 254 ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE, 255 ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY, 256 ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY, 257 }; 258 259 static struct workqueue_struct *bnxt_pf_wq; 260 261 static bool bnxt_vf_pciid(enum board_idx idx) 262 { 263 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF || 264 idx == NETXTREME_S_VF || idx == NETXTREME_E_P5_VF); 265 } 266 267 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID) 268 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS) 269 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS) 270 271 #define BNXT_CP_DB_IRQ_DIS(db) \ 272 writel(DB_CP_IRQ_DIS_FLAGS, db) 273 274 #define BNXT_DB_CQ(db, idx) \ 275 writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell) 276 277 #define BNXT_DB_NQ_P5(db, idx) \ 278 writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell) 279 280 #define BNXT_DB_CQ_ARM(db, idx) \ 281 writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell) 282 283 #define BNXT_DB_NQ_ARM_P5(db, idx) \ 284 writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell) 285 286 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 287 { 288 if (bp->flags & BNXT_FLAG_CHIP_P5) 289 BNXT_DB_NQ_P5(db, idx); 290 else 291 BNXT_DB_CQ(db, idx); 292 } 293 294 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 295 { 296 if (bp->flags & BNXT_FLAG_CHIP_P5) 297 BNXT_DB_NQ_ARM_P5(db, idx); 298 else 299 BNXT_DB_CQ_ARM(db, idx); 300 } 301 302 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 303 { 304 if (bp->flags & BNXT_FLAG_CHIP_P5) 305 writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx), 306 db->doorbell); 307 else 308 BNXT_DB_CQ(db, idx); 309 } 310 311 const u16 bnxt_lhint_arr[] = { 312 TX_BD_FLAGS_LHINT_512_AND_SMALLER, 313 TX_BD_FLAGS_LHINT_512_TO_1023, 314 TX_BD_FLAGS_LHINT_1024_TO_2047, 315 TX_BD_FLAGS_LHINT_1024_TO_2047, 316 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 317 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 318 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 319 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 320 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 321 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 322 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 323 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 324 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 325 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 326 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 327 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 328 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 329 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 330 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 331 }; 332 333 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb) 334 { 335 struct metadata_dst *md_dst = skb_metadata_dst(skb); 336 337 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX) 338 return 0; 339 340 return md_dst->u.port_info.port_id; 341 } 342 343 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev) 344 { 345 struct bnxt *bp = netdev_priv(dev); 346 struct tx_bd *txbd; 347 struct tx_bd_ext *txbd1; 348 struct netdev_queue *txq; 349 int i; 350 dma_addr_t mapping; 351 unsigned int length, pad = 0; 352 u32 len, free_size, vlan_tag_flags, cfa_action, flags; 353 u16 prod, last_frag; 354 struct pci_dev *pdev = bp->pdev; 355 struct bnxt_tx_ring_info *txr; 356 struct bnxt_sw_tx_bd *tx_buf; 357 358 i = skb_get_queue_mapping(skb); 359 if (unlikely(i >= bp->tx_nr_rings)) { 360 dev_kfree_skb_any(skb); 361 return NETDEV_TX_OK; 362 } 363 364 txq = netdev_get_tx_queue(dev, i); 365 txr = &bp->tx_ring[bp->tx_ring_map[i]]; 366 prod = txr->tx_prod; 367 368 free_size = bnxt_tx_avail(bp, txr); 369 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) { 370 netif_tx_stop_queue(txq); 371 return NETDEV_TX_BUSY; 372 } 373 374 length = skb->len; 375 len = skb_headlen(skb); 376 last_frag = skb_shinfo(skb)->nr_frags; 377 378 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 379 380 txbd->tx_bd_opaque = prod; 381 382 tx_buf = &txr->tx_buf_ring[prod]; 383 tx_buf->skb = skb; 384 tx_buf->nr_frags = last_frag; 385 386 vlan_tag_flags = 0; 387 cfa_action = bnxt_xmit_get_cfa_action(skb); 388 if (skb_vlan_tag_present(skb)) { 389 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN | 390 skb_vlan_tag_get(skb); 391 /* Currently supports 8021Q, 8021AD vlan offloads 392 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated 393 */ 394 if (skb->vlan_proto == htons(ETH_P_8021Q)) 395 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT; 396 } 397 398 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) { 399 struct tx_push_buffer *tx_push_buf = txr->tx_push; 400 struct tx_push_bd *tx_push = &tx_push_buf->push_bd; 401 struct tx_bd_ext *tx_push1 = &tx_push->txbd2; 402 void __iomem *db = txr->tx_db.doorbell; 403 void *pdata = tx_push_buf->data; 404 u64 *end; 405 int j, push_len; 406 407 /* Set COAL_NOW to be ready quickly for the next push */ 408 tx_push->tx_bd_len_flags_type = 409 cpu_to_le32((length << TX_BD_LEN_SHIFT) | 410 TX_BD_TYPE_LONG_TX_BD | 411 TX_BD_FLAGS_LHINT_512_AND_SMALLER | 412 TX_BD_FLAGS_COAL_NOW | 413 TX_BD_FLAGS_PACKET_END | 414 (2 << TX_BD_FLAGS_BD_CNT_SHIFT)); 415 416 if (skb->ip_summed == CHECKSUM_PARTIAL) 417 tx_push1->tx_bd_hsize_lflags = 418 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 419 else 420 tx_push1->tx_bd_hsize_lflags = 0; 421 422 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 423 tx_push1->tx_bd_cfa_action = 424 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); 425 426 end = pdata + length; 427 end = PTR_ALIGN(end, 8) - 1; 428 *end = 0; 429 430 skb_copy_from_linear_data(skb, pdata, len); 431 pdata += len; 432 for (j = 0; j < last_frag; j++) { 433 skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; 434 void *fptr; 435 436 fptr = skb_frag_address_safe(frag); 437 if (!fptr) 438 goto normal_tx; 439 440 memcpy(pdata, fptr, skb_frag_size(frag)); 441 pdata += skb_frag_size(frag); 442 } 443 444 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type; 445 txbd->tx_bd_haddr = txr->data_mapping; 446 prod = NEXT_TX(prod); 447 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 448 memcpy(txbd, tx_push1, sizeof(*txbd)); 449 prod = NEXT_TX(prod); 450 tx_push->doorbell = 451 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod); 452 txr->tx_prod = prod; 453 454 tx_buf->is_push = 1; 455 netdev_tx_sent_queue(txq, skb->len); 456 wmb(); /* Sync is_push and byte queue before pushing data */ 457 458 push_len = (length + sizeof(*tx_push) + 7) / 8; 459 if (push_len > 16) { 460 __iowrite64_copy(db, tx_push_buf, 16); 461 __iowrite32_copy(db + 4, tx_push_buf + 1, 462 (push_len - 16) << 1); 463 } else { 464 __iowrite64_copy(db, tx_push_buf, push_len); 465 } 466 467 goto tx_done; 468 } 469 470 normal_tx: 471 if (length < BNXT_MIN_PKT_SIZE) { 472 pad = BNXT_MIN_PKT_SIZE - length; 473 if (skb_pad(skb, pad)) { 474 /* SKB already freed. */ 475 tx_buf->skb = NULL; 476 return NETDEV_TX_OK; 477 } 478 length = BNXT_MIN_PKT_SIZE; 479 } 480 481 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE); 482 483 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) { 484 dev_kfree_skb_any(skb); 485 tx_buf->skb = NULL; 486 return NETDEV_TX_OK; 487 } 488 489 dma_unmap_addr_set(tx_buf, mapping, mapping); 490 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD | 491 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT); 492 493 txbd->tx_bd_haddr = cpu_to_le64(mapping); 494 495 prod = NEXT_TX(prod); 496 txbd1 = (struct tx_bd_ext *) 497 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 498 499 txbd1->tx_bd_hsize_lflags = 0; 500 if (skb_is_gso(skb)) { 501 u32 hdr_len; 502 503 if (skb->encapsulation) 504 hdr_len = skb_inner_network_offset(skb) + 505 skb_inner_network_header_len(skb) + 506 inner_tcp_hdrlen(skb); 507 else 508 hdr_len = skb_transport_offset(skb) + 509 tcp_hdrlen(skb); 510 511 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO | 512 TX_BD_FLAGS_T_IPID | 513 (hdr_len << (TX_BD_HSIZE_SHIFT - 1))); 514 length = skb_shinfo(skb)->gso_size; 515 txbd1->tx_bd_mss = cpu_to_le32(length); 516 length += hdr_len; 517 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 518 txbd1->tx_bd_hsize_lflags = 519 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 520 txbd1->tx_bd_mss = 0; 521 } 522 523 length >>= 9; 524 if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) { 525 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n", 526 skb->len); 527 i = 0; 528 goto tx_dma_error; 529 } 530 flags |= bnxt_lhint_arr[length]; 531 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 532 533 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 534 txbd1->tx_bd_cfa_action = 535 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); 536 for (i = 0; i < last_frag; i++) { 537 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 538 539 prod = NEXT_TX(prod); 540 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 541 542 len = skb_frag_size(frag); 543 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len, 544 DMA_TO_DEVICE); 545 546 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) 547 goto tx_dma_error; 548 549 tx_buf = &txr->tx_buf_ring[prod]; 550 dma_unmap_addr_set(tx_buf, mapping, mapping); 551 552 txbd->tx_bd_haddr = cpu_to_le64(mapping); 553 554 flags = len << TX_BD_LEN_SHIFT; 555 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 556 } 557 558 flags &= ~TX_BD_LEN; 559 txbd->tx_bd_len_flags_type = 560 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags | 561 TX_BD_FLAGS_PACKET_END); 562 563 netdev_tx_sent_queue(txq, skb->len); 564 565 /* Sync BD data before updating doorbell */ 566 wmb(); 567 568 prod = NEXT_TX(prod); 569 txr->tx_prod = prod; 570 571 if (!netdev_xmit_more() || netif_xmit_stopped(txq)) 572 bnxt_db_write(bp, &txr->tx_db, prod); 573 574 tx_done: 575 576 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) { 577 if (netdev_xmit_more() && !tx_buf->is_push) 578 bnxt_db_write(bp, &txr->tx_db, prod); 579 580 netif_tx_stop_queue(txq); 581 582 /* netif_tx_stop_queue() must be done before checking 583 * tx index in bnxt_tx_avail() below, because in 584 * bnxt_tx_int(), we update tx index before checking for 585 * netif_tx_queue_stopped(). 586 */ 587 smp_mb(); 588 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh) 589 netif_tx_wake_queue(txq); 590 } 591 return NETDEV_TX_OK; 592 593 tx_dma_error: 594 last_frag = i; 595 596 /* start back at beginning and unmap skb */ 597 prod = txr->tx_prod; 598 tx_buf = &txr->tx_buf_ring[prod]; 599 tx_buf->skb = NULL; 600 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 601 skb_headlen(skb), PCI_DMA_TODEVICE); 602 prod = NEXT_TX(prod); 603 604 /* unmap remaining mapped pages */ 605 for (i = 0; i < last_frag; i++) { 606 prod = NEXT_TX(prod); 607 tx_buf = &txr->tx_buf_ring[prod]; 608 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 609 skb_frag_size(&skb_shinfo(skb)->frags[i]), 610 PCI_DMA_TODEVICE); 611 } 612 613 dev_kfree_skb_any(skb); 614 return NETDEV_TX_OK; 615 } 616 617 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts) 618 { 619 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 620 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index); 621 u16 cons = txr->tx_cons; 622 struct pci_dev *pdev = bp->pdev; 623 int i; 624 unsigned int tx_bytes = 0; 625 626 for (i = 0; i < nr_pkts; i++) { 627 struct bnxt_sw_tx_bd *tx_buf; 628 struct sk_buff *skb; 629 int j, last; 630 631 tx_buf = &txr->tx_buf_ring[cons]; 632 cons = NEXT_TX(cons); 633 skb = tx_buf->skb; 634 tx_buf->skb = NULL; 635 636 if (tx_buf->is_push) { 637 tx_buf->is_push = 0; 638 goto next_tx_int; 639 } 640 641 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 642 skb_headlen(skb), PCI_DMA_TODEVICE); 643 last = tx_buf->nr_frags; 644 645 for (j = 0; j < last; j++) { 646 cons = NEXT_TX(cons); 647 tx_buf = &txr->tx_buf_ring[cons]; 648 dma_unmap_page( 649 &pdev->dev, 650 dma_unmap_addr(tx_buf, mapping), 651 skb_frag_size(&skb_shinfo(skb)->frags[j]), 652 PCI_DMA_TODEVICE); 653 } 654 655 next_tx_int: 656 cons = NEXT_TX(cons); 657 658 tx_bytes += skb->len; 659 dev_kfree_skb_any(skb); 660 } 661 662 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes); 663 txr->tx_cons = cons; 664 665 /* Need to make the tx_cons update visible to bnxt_start_xmit() 666 * before checking for netif_tx_queue_stopped(). Without the 667 * memory barrier, there is a small possibility that bnxt_start_xmit() 668 * will miss it and cause the queue to be stopped forever. 669 */ 670 smp_mb(); 671 672 if (unlikely(netif_tx_queue_stopped(txq)) && 673 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) { 674 __netif_tx_lock(txq, smp_processor_id()); 675 if (netif_tx_queue_stopped(txq) && 676 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh && 677 txr->dev_state != BNXT_DEV_STATE_CLOSING) 678 netif_tx_wake_queue(txq); 679 __netif_tx_unlock(txq); 680 } 681 } 682 683 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping, 684 struct bnxt_rx_ring_info *rxr, 685 gfp_t gfp) 686 { 687 struct device *dev = &bp->pdev->dev; 688 struct page *page; 689 690 page = page_pool_dev_alloc_pages(rxr->page_pool); 691 if (!page) 692 return NULL; 693 694 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir, 695 DMA_ATTR_WEAK_ORDERING); 696 if (dma_mapping_error(dev, *mapping)) { 697 page_pool_recycle_direct(rxr->page_pool, page); 698 return NULL; 699 } 700 *mapping += bp->rx_dma_offset; 701 return page; 702 } 703 704 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping, 705 gfp_t gfp) 706 { 707 u8 *data; 708 struct pci_dev *pdev = bp->pdev; 709 710 data = kmalloc(bp->rx_buf_size, gfp); 711 if (!data) 712 return NULL; 713 714 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset, 715 bp->rx_buf_use_size, bp->rx_dir, 716 DMA_ATTR_WEAK_ORDERING); 717 718 if (dma_mapping_error(&pdev->dev, *mapping)) { 719 kfree(data); 720 data = NULL; 721 } 722 return data; 723 } 724 725 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 726 u16 prod, gfp_t gfp) 727 { 728 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 729 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod]; 730 dma_addr_t mapping; 731 732 if (BNXT_RX_PAGE_MODE(bp)) { 733 struct page *page = 734 __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp); 735 736 if (!page) 737 return -ENOMEM; 738 739 rx_buf->data = page; 740 rx_buf->data_ptr = page_address(page) + bp->rx_offset; 741 } else { 742 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp); 743 744 if (!data) 745 return -ENOMEM; 746 747 rx_buf->data = data; 748 rx_buf->data_ptr = data + bp->rx_offset; 749 } 750 rx_buf->mapping = mapping; 751 752 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 753 return 0; 754 } 755 756 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data) 757 { 758 u16 prod = rxr->rx_prod; 759 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 760 struct rx_bd *cons_bd, *prod_bd; 761 762 prod_rx_buf = &rxr->rx_buf_ring[prod]; 763 cons_rx_buf = &rxr->rx_buf_ring[cons]; 764 765 prod_rx_buf->data = data; 766 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr; 767 768 prod_rx_buf->mapping = cons_rx_buf->mapping; 769 770 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 771 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; 772 773 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr; 774 } 775 776 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) 777 { 778 u16 next, max = rxr->rx_agg_bmap_size; 779 780 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx); 781 if (next >= max) 782 next = find_first_zero_bit(rxr->rx_agg_bmap, max); 783 return next; 784 } 785 786 static inline int bnxt_alloc_rx_page(struct bnxt *bp, 787 struct bnxt_rx_ring_info *rxr, 788 u16 prod, gfp_t gfp) 789 { 790 struct rx_bd *rxbd = 791 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 792 struct bnxt_sw_rx_agg_bd *rx_agg_buf; 793 struct pci_dev *pdev = bp->pdev; 794 struct page *page; 795 dma_addr_t mapping; 796 u16 sw_prod = rxr->rx_sw_agg_prod; 797 unsigned int offset = 0; 798 799 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) { 800 page = rxr->rx_page; 801 if (!page) { 802 page = alloc_page(gfp); 803 if (!page) 804 return -ENOMEM; 805 rxr->rx_page = page; 806 rxr->rx_page_offset = 0; 807 } 808 offset = rxr->rx_page_offset; 809 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE; 810 if (rxr->rx_page_offset == PAGE_SIZE) 811 rxr->rx_page = NULL; 812 else 813 get_page(page); 814 } else { 815 page = alloc_page(gfp); 816 if (!page) 817 return -ENOMEM; 818 } 819 820 mapping = dma_map_page_attrs(&pdev->dev, page, offset, 821 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE, 822 DMA_ATTR_WEAK_ORDERING); 823 if (dma_mapping_error(&pdev->dev, mapping)) { 824 __free_page(page); 825 return -EIO; 826 } 827 828 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 829 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 830 831 __set_bit(sw_prod, rxr->rx_agg_bmap); 832 rx_agg_buf = &rxr->rx_agg_ring[sw_prod]; 833 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod); 834 835 rx_agg_buf->page = page; 836 rx_agg_buf->offset = offset; 837 rx_agg_buf->mapping = mapping; 838 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 839 rxbd->rx_bd_opaque = sw_prod; 840 return 0; 841 } 842 843 static struct rx_agg_cmp *bnxt_get_agg(struct bnxt *bp, 844 struct bnxt_cp_ring_info *cpr, 845 u16 cp_cons, u16 curr) 846 { 847 struct rx_agg_cmp *agg; 848 849 cp_cons = RING_CMP(ADV_RAW_CMP(cp_cons, curr)); 850 agg = (struct rx_agg_cmp *) 851 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 852 return agg; 853 } 854 855 static struct rx_agg_cmp *bnxt_get_tpa_agg_p5(struct bnxt *bp, 856 struct bnxt_rx_ring_info *rxr, 857 u16 agg_id, u16 curr) 858 { 859 struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[agg_id]; 860 861 return &tpa_info->agg_arr[curr]; 862 } 863 864 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 idx, 865 u16 start, u32 agg_bufs, bool tpa) 866 { 867 struct bnxt_napi *bnapi = cpr->bnapi; 868 struct bnxt *bp = bnapi->bp; 869 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 870 u16 prod = rxr->rx_agg_prod; 871 u16 sw_prod = rxr->rx_sw_agg_prod; 872 bool p5_tpa = false; 873 u32 i; 874 875 if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa) 876 p5_tpa = true; 877 878 for (i = 0; i < agg_bufs; i++) { 879 u16 cons; 880 struct rx_agg_cmp *agg; 881 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf; 882 struct rx_bd *prod_bd; 883 struct page *page; 884 885 if (p5_tpa) 886 agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, start + i); 887 else 888 agg = bnxt_get_agg(bp, cpr, idx, start + i); 889 cons = agg->rx_agg_cmp_opaque; 890 __clear_bit(cons, rxr->rx_agg_bmap); 891 892 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 893 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 894 895 __set_bit(sw_prod, rxr->rx_agg_bmap); 896 prod_rx_buf = &rxr->rx_agg_ring[sw_prod]; 897 cons_rx_buf = &rxr->rx_agg_ring[cons]; 898 899 /* It is possible for sw_prod to be equal to cons, so 900 * set cons_rx_buf->page to NULL first. 901 */ 902 page = cons_rx_buf->page; 903 cons_rx_buf->page = NULL; 904 prod_rx_buf->page = page; 905 prod_rx_buf->offset = cons_rx_buf->offset; 906 907 prod_rx_buf->mapping = cons_rx_buf->mapping; 908 909 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 910 911 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping); 912 prod_bd->rx_bd_opaque = sw_prod; 913 914 prod = NEXT_RX_AGG(prod); 915 sw_prod = NEXT_RX_AGG(sw_prod); 916 } 917 rxr->rx_agg_prod = prod; 918 rxr->rx_sw_agg_prod = sw_prod; 919 } 920 921 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp, 922 struct bnxt_rx_ring_info *rxr, 923 u16 cons, void *data, u8 *data_ptr, 924 dma_addr_t dma_addr, 925 unsigned int offset_and_len) 926 { 927 unsigned int payload = offset_and_len >> 16; 928 unsigned int len = offset_and_len & 0xffff; 929 skb_frag_t *frag; 930 struct page *page = data; 931 u16 prod = rxr->rx_prod; 932 struct sk_buff *skb; 933 int off, err; 934 935 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 936 if (unlikely(err)) { 937 bnxt_reuse_rx_data(rxr, cons, data); 938 return NULL; 939 } 940 dma_addr -= bp->rx_dma_offset; 941 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir, 942 DMA_ATTR_WEAK_ORDERING); 943 page_pool_release_page(rxr->page_pool, page); 944 945 if (unlikely(!payload)) 946 payload = eth_get_headlen(bp->dev, data_ptr, len); 947 948 skb = napi_alloc_skb(&rxr->bnapi->napi, payload); 949 if (!skb) { 950 __free_page(page); 951 return NULL; 952 } 953 954 off = (void *)data_ptr - page_address(page); 955 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE); 956 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN, 957 payload + NET_IP_ALIGN); 958 959 frag = &skb_shinfo(skb)->frags[0]; 960 skb_frag_size_sub(frag, payload); 961 skb_frag_off_add(frag, payload); 962 skb->data_len -= payload; 963 skb->tail += payload; 964 965 return skb; 966 } 967 968 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp, 969 struct bnxt_rx_ring_info *rxr, u16 cons, 970 void *data, u8 *data_ptr, 971 dma_addr_t dma_addr, 972 unsigned int offset_and_len) 973 { 974 u16 prod = rxr->rx_prod; 975 struct sk_buff *skb; 976 int err; 977 978 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 979 if (unlikely(err)) { 980 bnxt_reuse_rx_data(rxr, cons, data); 981 return NULL; 982 } 983 984 skb = build_skb(data, 0); 985 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, 986 bp->rx_dir, DMA_ATTR_WEAK_ORDERING); 987 if (!skb) { 988 kfree(data); 989 return NULL; 990 } 991 992 skb_reserve(skb, bp->rx_offset); 993 skb_put(skb, offset_and_len & 0xffff); 994 return skb; 995 } 996 997 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, 998 struct bnxt_cp_ring_info *cpr, 999 struct sk_buff *skb, u16 idx, 1000 u32 agg_bufs, bool tpa) 1001 { 1002 struct bnxt_napi *bnapi = cpr->bnapi; 1003 struct pci_dev *pdev = bp->pdev; 1004 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1005 u16 prod = rxr->rx_agg_prod; 1006 bool p5_tpa = false; 1007 u32 i; 1008 1009 if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa) 1010 p5_tpa = true; 1011 1012 for (i = 0; i < agg_bufs; i++) { 1013 u16 cons, frag_len; 1014 struct rx_agg_cmp *agg; 1015 struct bnxt_sw_rx_agg_bd *cons_rx_buf; 1016 struct page *page; 1017 dma_addr_t mapping; 1018 1019 if (p5_tpa) 1020 agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, i); 1021 else 1022 agg = bnxt_get_agg(bp, cpr, idx, i); 1023 cons = agg->rx_agg_cmp_opaque; 1024 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) & 1025 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT; 1026 1027 cons_rx_buf = &rxr->rx_agg_ring[cons]; 1028 skb_fill_page_desc(skb, i, cons_rx_buf->page, 1029 cons_rx_buf->offset, frag_len); 1030 __clear_bit(cons, rxr->rx_agg_bmap); 1031 1032 /* It is possible for bnxt_alloc_rx_page() to allocate 1033 * a sw_prod index that equals the cons index, so we 1034 * need to clear the cons entry now. 1035 */ 1036 mapping = cons_rx_buf->mapping; 1037 page = cons_rx_buf->page; 1038 cons_rx_buf->page = NULL; 1039 1040 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) { 1041 struct skb_shared_info *shinfo; 1042 unsigned int nr_frags; 1043 1044 shinfo = skb_shinfo(skb); 1045 nr_frags = --shinfo->nr_frags; 1046 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL); 1047 1048 dev_kfree_skb(skb); 1049 1050 cons_rx_buf->page = page; 1051 1052 /* Update prod since possibly some pages have been 1053 * allocated already. 1054 */ 1055 rxr->rx_agg_prod = prod; 1056 bnxt_reuse_rx_agg_bufs(cpr, idx, i, agg_bufs - i, tpa); 1057 return NULL; 1058 } 1059 1060 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE, 1061 PCI_DMA_FROMDEVICE, 1062 DMA_ATTR_WEAK_ORDERING); 1063 1064 skb->data_len += frag_len; 1065 skb->len += frag_len; 1066 skb->truesize += PAGE_SIZE; 1067 1068 prod = NEXT_RX_AGG(prod); 1069 } 1070 rxr->rx_agg_prod = prod; 1071 return skb; 1072 } 1073 1074 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1075 u8 agg_bufs, u32 *raw_cons) 1076 { 1077 u16 last; 1078 struct rx_agg_cmp *agg; 1079 1080 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs); 1081 last = RING_CMP(*raw_cons); 1082 agg = (struct rx_agg_cmp *) 1083 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)]; 1084 return RX_AGG_CMP_VALID(agg, *raw_cons); 1085 } 1086 1087 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data, 1088 unsigned int len, 1089 dma_addr_t mapping) 1090 { 1091 struct bnxt *bp = bnapi->bp; 1092 struct pci_dev *pdev = bp->pdev; 1093 struct sk_buff *skb; 1094 1095 skb = napi_alloc_skb(&bnapi->napi, len); 1096 if (!skb) 1097 return NULL; 1098 1099 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh, 1100 bp->rx_dir); 1101 1102 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN, 1103 len + NET_IP_ALIGN); 1104 1105 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh, 1106 bp->rx_dir); 1107 1108 skb_put(skb, len); 1109 return skb; 1110 } 1111 1112 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1113 u32 *raw_cons, void *cmp) 1114 { 1115 struct rx_cmp *rxcmp = cmp; 1116 u32 tmp_raw_cons = *raw_cons; 1117 u8 cmp_type, agg_bufs = 0; 1118 1119 cmp_type = RX_CMP_TYPE(rxcmp); 1120 1121 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 1122 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & 1123 RX_CMP_AGG_BUFS) >> 1124 RX_CMP_AGG_BUFS_SHIFT; 1125 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1126 struct rx_tpa_end_cmp *tpa_end = cmp; 1127 1128 if (bp->flags & BNXT_FLAG_CHIP_P5) 1129 return 0; 1130 1131 agg_bufs = TPA_END_AGG_BUFS(tpa_end); 1132 } 1133 1134 if (agg_bufs) { 1135 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1136 return -EBUSY; 1137 } 1138 *raw_cons = tmp_raw_cons; 1139 return 0; 1140 } 1141 1142 static void bnxt_queue_fw_reset_work(struct bnxt *bp, unsigned long delay) 1143 { 1144 if (BNXT_PF(bp)) 1145 queue_delayed_work(bnxt_pf_wq, &bp->fw_reset_task, delay); 1146 else 1147 schedule_delayed_work(&bp->fw_reset_task, delay); 1148 } 1149 1150 static void bnxt_queue_sp_work(struct bnxt *bp) 1151 { 1152 if (BNXT_PF(bp)) 1153 queue_work(bnxt_pf_wq, &bp->sp_task); 1154 else 1155 schedule_work(&bp->sp_task); 1156 } 1157 1158 static void bnxt_cancel_sp_work(struct bnxt *bp) 1159 { 1160 if (BNXT_PF(bp)) 1161 flush_workqueue(bnxt_pf_wq); 1162 else 1163 cancel_work_sync(&bp->sp_task); 1164 } 1165 1166 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) 1167 { 1168 if (!rxr->bnapi->in_reset) { 1169 rxr->bnapi->in_reset = true; 1170 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 1171 bnxt_queue_sp_work(bp); 1172 } 1173 rxr->rx_next_cons = 0xffff; 1174 } 1175 1176 static u16 bnxt_alloc_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id) 1177 { 1178 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; 1179 u16 idx = agg_id & MAX_TPA_P5_MASK; 1180 1181 if (test_bit(idx, map->agg_idx_bmap)) 1182 idx = find_first_zero_bit(map->agg_idx_bmap, 1183 BNXT_AGG_IDX_BMAP_SIZE); 1184 __set_bit(idx, map->agg_idx_bmap); 1185 map->agg_id_tbl[agg_id] = idx; 1186 return idx; 1187 } 1188 1189 static void bnxt_free_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) 1190 { 1191 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; 1192 1193 __clear_bit(idx, map->agg_idx_bmap); 1194 } 1195 1196 static u16 bnxt_lookup_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id) 1197 { 1198 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map; 1199 1200 return map->agg_id_tbl[agg_id]; 1201 } 1202 1203 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 1204 struct rx_tpa_start_cmp *tpa_start, 1205 struct rx_tpa_start_cmp_ext *tpa_start1) 1206 { 1207 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 1208 struct bnxt_tpa_info *tpa_info; 1209 u16 cons, prod, agg_id; 1210 struct rx_bd *prod_bd; 1211 dma_addr_t mapping; 1212 1213 if (bp->flags & BNXT_FLAG_CHIP_P5) { 1214 agg_id = TPA_START_AGG_ID_P5(tpa_start); 1215 agg_id = bnxt_alloc_agg_idx(rxr, agg_id); 1216 } else { 1217 agg_id = TPA_START_AGG_ID(tpa_start); 1218 } 1219 cons = tpa_start->rx_tpa_start_cmp_opaque; 1220 prod = rxr->rx_prod; 1221 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1222 prod_rx_buf = &rxr->rx_buf_ring[prod]; 1223 tpa_info = &rxr->rx_tpa[agg_id]; 1224 1225 if (unlikely(cons != rxr->rx_next_cons || 1226 TPA_START_ERROR(tpa_start))) { 1227 netdev_warn(bp->dev, "TPA cons %x, expected cons %x, error code %x\n", 1228 cons, rxr->rx_next_cons, 1229 TPA_START_ERROR_CODE(tpa_start1)); 1230 bnxt_sched_reset(bp, rxr); 1231 return; 1232 } 1233 /* Store cfa_code in tpa_info to use in tpa_end 1234 * completion processing. 1235 */ 1236 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1); 1237 prod_rx_buf->data = tpa_info->data; 1238 prod_rx_buf->data_ptr = tpa_info->data_ptr; 1239 1240 mapping = tpa_info->mapping; 1241 prod_rx_buf->mapping = mapping; 1242 1243 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 1244 1245 prod_bd->rx_bd_haddr = cpu_to_le64(mapping); 1246 1247 tpa_info->data = cons_rx_buf->data; 1248 tpa_info->data_ptr = cons_rx_buf->data_ptr; 1249 cons_rx_buf->data = NULL; 1250 tpa_info->mapping = cons_rx_buf->mapping; 1251 1252 tpa_info->len = 1253 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >> 1254 RX_TPA_START_CMP_LEN_SHIFT; 1255 if (likely(TPA_START_HASH_VALID(tpa_start))) { 1256 u32 hash_type = TPA_START_HASH_TYPE(tpa_start); 1257 1258 tpa_info->hash_type = PKT_HASH_TYPE_L4; 1259 tpa_info->gso_type = SKB_GSO_TCPV4; 1260 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1261 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1)) 1262 tpa_info->gso_type = SKB_GSO_TCPV6; 1263 tpa_info->rss_hash = 1264 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash); 1265 } else { 1266 tpa_info->hash_type = PKT_HASH_TYPE_NONE; 1267 tpa_info->gso_type = 0; 1268 if (netif_msg_rx_err(bp)) 1269 netdev_warn(bp->dev, "TPA packet without valid hash\n"); 1270 } 1271 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2); 1272 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata); 1273 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info); 1274 tpa_info->agg_count = 0; 1275 1276 rxr->rx_prod = NEXT_RX(prod); 1277 cons = NEXT_RX(cons); 1278 rxr->rx_next_cons = NEXT_RX(cons); 1279 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1280 1281 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data); 1282 rxr->rx_prod = NEXT_RX(rxr->rx_prod); 1283 cons_rx_buf->data = NULL; 1284 } 1285 1286 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 idx, u32 agg_bufs) 1287 { 1288 if (agg_bufs) 1289 bnxt_reuse_rx_agg_bufs(cpr, idx, 0, agg_bufs, true); 1290 } 1291 1292 #ifdef CONFIG_INET 1293 static void bnxt_gro_tunnel(struct sk_buff *skb, __be16 ip_proto) 1294 { 1295 struct udphdr *uh = NULL; 1296 1297 if (ip_proto == htons(ETH_P_IP)) { 1298 struct iphdr *iph = (struct iphdr *)skb->data; 1299 1300 if (iph->protocol == IPPROTO_UDP) 1301 uh = (struct udphdr *)(iph + 1); 1302 } else { 1303 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; 1304 1305 if (iph->nexthdr == IPPROTO_UDP) 1306 uh = (struct udphdr *)(iph + 1); 1307 } 1308 if (uh) { 1309 if (uh->check) 1310 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL_CSUM; 1311 else 1312 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; 1313 } 1314 } 1315 #endif 1316 1317 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info, 1318 int payload_off, int tcp_ts, 1319 struct sk_buff *skb) 1320 { 1321 #ifdef CONFIG_INET 1322 struct tcphdr *th; 1323 int len, nw_off; 1324 u16 outer_ip_off, inner_ip_off, inner_mac_off; 1325 u32 hdr_info = tpa_info->hdr_info; 1326 bool loopback = false; 1327 1328 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); 1329 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); 1330 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); 1331 1332 /* If the packet is an internal loopback packet, the offsets will 1333 * have an extra 4 bytes. 1334 */ 1335 if (inner_mac_off == 4) { 1336 loopback = true; 1337 } else if (inner_mac_off > 4) { 1338 __be16 proto = *((__be16 *)(skb->data + inner_ip_off - 1339 ETH_HLEN - 2)); 1340 1341 /* We only support inner iPv4/ipv6. If we don't see the 1342 * correct protocol ID, it must be a loopback packet where 1343 * the offsets are off by 4. 1344 */ 1345 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6)) 1346 loopback = true; 1347 } 1348 if (loopback) { 1349 /* internal loopback packet, subtract all offsets by 4 */ 1350 inner_ip_off -= 4; 1351 inner_mac_off -= 4; 1352 outer_ip_off -= 4; 1353 } 1354 1355 nw_off = inner_ip_off - ETH_HLEN; 1356 skb_set_network_header(skb, nw_off); 1357 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) { 1358 struct ipv6hdr *iph = ipv6_hdr(skb); 1359 1360 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1361 len = skb->len - skb_transport_offset(skb); 1362 th = tcp_hdr(skb); 1363 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1364 } else { 1365 struct iphdr *iph = ip_hdr(skb); 1366 1367 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1368 len = skb->len - skb_transport_offset(skb); 1369 th = tcp_hdr(skb); 1370 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1371 } 1372 1373 if (inner_mac_off) { /* tunnel */ 1374 __be16 proto = *((__be16 *)(skb->data + outer_ip_off - 1375 ETH_HLEN - 2)); 1376 1377 bnxt_gro_tunnel(skb, proto); 1378 } 1379 #endif 1380 return skb; 1381 } 1382 1383 static struct sk_buff *bnxt_gro_func_5750x(struct bnxt_tpa_info *tpa_info, 1384 int payload_off, int tcp_ts, 1385 struct sk_buff *skb) 1386 { 1387 #ifdef CONFIG_INET 1388 u16 outer_ip_off, inner_ip_off, inner_mac_off; 1389 u32 hdr_info = tpa_info->hdr_info; 1390 int iphdr_len, nw_off; 1391 1392 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); 1393 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); 1394 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); 1395 1396 nw_off = inner_ip_off - ETH_HLEN; 1397 skb_set_network_header(skb, nw_off); 1398 iphdr_len = (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) ? 1399 sizeof(struct ipv6hdr) : sizeof(struct iphdr); 1400 skb_set_transport_header(skb, nw_off + iphdr_len); 1401 1402 if (inner_mac_off) { /* tunnel */ 1403 __be16 proto = *((__be16 *)(skb->data + outer_ip_off - 1404 ETH_HLEN - 2)); 1405 1406 bnxt_gro_tunnel(skb, proto); 1407 } 1408 #endif 1409 return skb; 1410 } 1411 1412 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr)) 1413 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr)) 1414 1415 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info, 1416 int payload_off, int tcp_ts, 1417 struct sk_buff *skb) 1418 { 1419 #ifdef CONFIG_INET 1420 struct tcphdr *th; 1421 int len, nw_off, tcp_opt_len = 0; 1422 1423 if (tcp_ts) 1424 tcp_opt_len = 12; 1425 1426 if (tpa_info->gso_type == SKB_GSO_TCPV4) { 1427 struct iphdr *iph; 1428 1429 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len - 1430 ETH_HLEN; 1431 skb_set_network_header(skb, nw_off); 1432 iph = ip_hdr(skb); 1433 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1434 len = skb->len - skb_transport_offset(skb); 1435 th = tcp_hdr(skb); 1436 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1437 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) { 1438 struct ipv6hdr *iph; 1439 1440 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len - 1441 ETH_HLEN; 1442 skb_set_network_header(skb, nw_off); 1443 iph = ipv6_hdr(skb); 1444 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1445 len = skb->len - skb_transport_offset(skb); 1446 th = tcp_hdr(skb); 1447 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1448 } else { 1449 dev_kfree_skb_any(skb); 1450 return NULL; 1451 } 1452 1453 if (nw_off) /* tunnel */ 1454 bnxt_gro_tunnel(skb, skb->protocol); 1455 #endif 1456 return skb; 1457 } 1458 1459 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp, 1460 struct bnxt_tpa_info *tpa_info, 1461 struct rx_tpa_end_cmp *tpa_end, 1462 struct rx_tpa_end_cmp_ext *tpa_end1, 1463 struct sk_buff *skb) 1464 { 1465 #ifdef CONFIG_INET 1466 int payload_off; 1467 u16 segs; 1468 1469 segs = TPA_END_TPA_SEGS(tpa_end); 1470 if (segs == 1) 1471 return skb; 1472 1473 NAPI_GRO_CB(skb)->count = segs; 1474 skb_shinfo(skb)->gso_size = 1475 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len); 1476 skb_shinfo(skb)->gso_type = tpa_info->gso_type; 1477 if (bp->flags & BNXT_FLAG_CHIP_P5) 1478 payload_off = TPA_END_PAYLOAD_OFF_P5(tpa_end1); 1479 else 1480 payload_off = TPA_END_PAYLOAD_OFF(tpa_end); 1481 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb); 1482 if (likely(skb)) 1483 tcp_gro_complete(skb); 1484 #endif 1485 return skb; 1486 } 1487 1488 /* Given the cfa_code of a received packet determine which 1489 * netdev (vf-rep or PF) the packet is destined to. 1490 */ 1491 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code) 1492 { 1493 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code); 1494 1495 /* if vf-rep dev is NULL, the must belongs to the PF */ 1496 return dev ? dev : bp->dev; 1497 } 1498 1499 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp, 1500 struct bnxt_cp_ring_info *cpr, 1501 u32 *raw_cons, 1502 struct rx_tpa_end_cmp *tpa_end, 1503 struct rx_tpa_end_cmp_ext *tpa_end1, 1504 u8 *event) 1505 { 1506 struct bnxt_napi *bnapi = cpr->bnapi; 1507 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1508 u8 *data_ptr, agg_bufs; 1509 unsigned int len; 1510 struct bnxt_tpa_info *tpa_info; 1511 dma_addr_t mapping; 1512 struct sk_buff *skb; 1513 u16 idx = 0, agg_id; 1514 void *data; 1515 bool gro; 1516 1517 if (unlikely(bnapi->in_reset)) { 1518 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end); 1519 1520 if (rc < 0) 1521 return ERR_PTR(-EBUSY); 1522 return NULL; 1523 } 1524 1525 if (bp->flags & BNXT_FLAG_CHIP_P5) { 1526 agg_id = TPA_END_AGG_ID_P5(tpa_end); 1527 agg_id = bnxt_lookup_agg_idx(rxr, agg_id); 1528 agg_bufs = TPA_END_AGG_BUFS_P5(tpa_end1); 1529 tpa_info = &rxr->rx_tpa[agg_id]; 1530 if (unlikely(agg_bufs != tpa_info->agg_count)) { 1531 netdev_warn(bp->dev, "TPA end agg_buf %d != expected agg_bufs %d\n", 1532 agg_bufs, tpa_info->agg_count); 1533 agg_bufs = tpa_info->agg_count; 1534 } 1535 tpa_info->agg_count = 0; 1536 *event |= BNXT_AGG_EVENT; 1537 bnxt_free_agg_idx(rxr, agg_id); 1538 idx = agg_id; 1539 gro = !!(bp->flags & BNXT_FLAG_GRO); 1540 } else { 1541 agg_id = TPA_END_AGG_ID(tpa_end); 1542 agg_bufs = TPA_END_AGG_BUFS(tpa_end); 1543 tpa_info = &rxr->rx_tpa[agg_id]; 1544 idx = RING_CMP(*raw_cons); 1545 if (agg_bufs) { 1546 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons)) 1547 return ERR_PTR(-EBUSY); 1548 1549 *event |= BNXT_AGG_EVENT; 1550 idx = NEXT_CMP(idx); 1551 } 1552 gro = !!TPA_END_GRO(tpa_end); 1553 } 1554 data = tpa_info->data; 1555 data_ptr = tpa_info->data_ptr; 1556 prefetch(data_ptr); 1557 len = tpa_info->len; 1558 mapping = tpa_info->mapping; 1559 1560 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) { 1561 bnxt_abort_tpa(cpr, idx, agg_bufs); 1562 if (agg_bufs > MAX_SKB_FRAGS) 1563 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n", 1564 agg_bufs, (int)MAX_SKB_FRAGS); 1565 return NULL; 1566 } 1567 1568 if (len <= bp->rx_copy_thresh) { 1569 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping); 1570 if (!skb) { 1571 bnxt_abort_tpa(cpr, idx, agg_bufs); 1572 return NULL; 1573 } 1574 } else { 1575 u8 *new_data; 1576 dma_addr_t new_mapping; 1577 1578 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC); 1579 if (!new_data) { 1580 bnxt_abort_tpa(cpr, idx, agg_bufs); 1581 return NULL; 1582 } 1583 1584 tpa_info->data = new_data; 1585 tpa_info->data_ptr = new_data + bp->rx_offset; 1586 tpa_info->mapping = new_mapping; 1587 1588 skb = build_skb(data, 0); 1589 dma_unmap_single_attrs(&bp->pdev->dev, mapping, 1590 bp->rx_buf_use_size, bp->rx_dir, 1591 DMA_ATTR_WEAK_ORDERING); 1592 1593 if (!skb) { 1594 kfree(data); 1595 bnxt_abort_tpa(cpr, idx, agg_bufs); 1596 return NULL; 1597 } 1598 skb_reserve(skb, bp->rx_offset); 1599 skb_put(skb, len); 1600 } 1601 1602 if (agg_bufs) { 1603 skb = bnxt_rx_pages(bp, cpr, skb, idx, agg_bufs, true); 1604 if (!skb) { 1605 /* Page reuse already handled by bnxt_rx_pages(). */ 1606 return NULL; 1607 } 1608 } 1609 1610 skb->protocol = 1611 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code)); 1612 1613 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE) 1614 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type); 1615 1616 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) && 1617 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1618 u16 vlan_proto = tpa_info->metadata >> 1619 RX_CMP_FLAGS2_METADATA_TPID_SFT; 1620 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK; 1621 1622 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); 1623 } 1624 1625 skb_checksum_none_assert(skb); 1626 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) { 1627 skb->ip_summed = CHECKSUM_UNNECESSARY; 1628 skb->csum_level = 1629 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3; 1630 } 1631 1632 if (gro) 1633 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb); 1634 1635 return skb; 1636 } 1637 1638 static void bnxt_tpa_agg(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 1639 struct rx_agg_cmp *rx_agg) 1640 { 1641 u16 agg_id = TPA_AGG_AGG_ID(rx_agg); 1642 struct bnxt_tpa_info *tpa_info; 1643 1644 agg_id = bnxt_lookup_agg_idx(rxr, agg_id); 1645 tpa_info = &rxr->rx_tpa[agg_id]; 1646 BUG_ON(tpa_info->agg_count >= MAX_SKB_FRAGS); 1647 tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg; 1648 } 1649 1650 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi, 1651 struct sk_buff *skb) 1652 { 1653 if (skb->dev != bp->dev) { 1654 /* this packet belongs to a vf-rep */ 1655 bnxt_vf_rep_rx(bp, skb); 1656 return; 1657 } 1658 skb_record_rx_queue(skb, bnapi->index); 1659 napi_gro_receive(&bnapi->napi, skb); 1660 } 1661 1662 /* returns the following: 1663 * 1 - 1 packet successfully received 1664 * 0 - successful TPA_START, packet not completed yet 1665 * -EBUSY - completion ring does not have all the agg buffers yet 1666 * -ENOMEM - packet aborted due to out of memory 1667 * -EIO - packet aborted due to hw error indicated in BD 1668 */ 1669 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1670 u32 *raw_cons, u8 *event) 1671 { 1672 struct bnxt_napi *bnapi = cpr->bnapi; 1673 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1674 struct net_device *dev = bp->dev; 1675 struct rx_cmp *rxcmp; 1676 struct rx_cmp_ext *rxcmp1; 1677 u32 tmp_raw_cons = *raw_cons; 1678 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons); 1679 struct bnxt_sw_rx_bd *rx_buf; 1680 unsigned int len; 1681 u8 *data_ptr, agg_bufs, cmp_type; 1682 dma_addr_t dma_addr; 1683 struct sk_buff *skb; 1684 void *data; 1685 int rc = 0; 1686 u32 misc; 1687 1688 rxcmp = (struct rx_cmp *) 1689 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1690 1691 cmp_type = RX_CMP_TYPE(rxcmp); 1692 1693 if (cmp_type == CMP_TYPE_RX_TPA_AGG_CMP) { 1694 bnxt_tpa_agg(bp, rxr, (struct rx_agg_cmp *)rxcmp); 1695 goto next_rx_no_prod_no_len; 1696 } 1697 1698 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1699 cp_cons = RING_CMP(tmp_raw_cons); 1700 rxcmp1 = (struct rx_cmp_ext *) 1701 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1702 1703 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1704 return -EBUSY; 1705 1706 prod = rxr->rx_prod; 1707 1708 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) { 1709 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp, 1710 (struct rx_tpa_start_cmp_ext *)rxcmp1); 1711 1712 *event |= BNXT_RX_EVENT; 1713 goto next_rx_no_prod_no_len; 1714 1715 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1716 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons, 1717 (struct rx_tpa_end_cmp *)rxcmp, 1718 (struct rx_tpa_end_cmp_ext *)rxcmp1, event); 1719 1720 if (IS_ERR(skb)) 1721 return -EBUSY; 1722 1723 rc = -ENOMEM; 1724 if (likely(skb)) { 1725 bnxt_deliver_skb(bp, bnapi, skb); 1726 rc = 1; 1727 } 1728 *event |= BNXT_RX_EVENT; 1729 goto next_rx_no_prod_no_len; 1730 } 1731 1732 cons = rxcmp->rx_cmp_opaque; 1733 if (unlikely(cons != rxr->rx_next_cons)) { 1734 int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp); 1735 1736 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n", 1737 cons, rxr->rx_next_cons); 1738 bnxt_sched_reset(bp, rxr); 1739 return rc1; 1740 } 1741 rx_buf = &rxr->rx_buf_ring[cons]; 1742 data = rx_buf->data; 1743 data_ptr = rx_buf->data_ptr; 1744 prefetch(data_ptr); 1745 1746 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1); 1747 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT; 1748 1749 if (agg_bufs) { 1750 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1751 return -EBUSY; 1752 1753 cp_cons = NEXT_CMP(cp_cons); 1754 *event |= BNXT_AGG_EVENT; 1755 } 1756 *event |= BNXT_RX_EVENT; 1757 1758 rx_buf->data = NULL; 1759 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) { 1760 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2); 1761 1762 bnxt_reuse_rx_data(rxr, cons, data); 1763 if (agg_bufs) 1764 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, agg_bufs, 1765 false); 1766 1767 rc = -EIO; 1768 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) { 1769 bnapi->cp_ring.sw_stats.rx.rx_buf_errors++; 1770 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) { 1771 netdev_warn(bp->dev, "RX buffer error %x\n", 1772 rx_err); 1773 bnxt_sched_reset(bp, rxr); 1774 } 1775 } 1776 goto next_rx_no_len; 1777 } 1778 1779 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 1780 dma_addr = rx_buf->mapping; 1781 1782 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) { 1783 rc = 1; 1784 goto next_rx; 1785 } 1786 1787 if (len <= bp->rx_copy_thresh) { 1788 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr); 1789 bnxt_reuse_rx_data(rxr, cons, data); 1790 if (!skb) { 1791 if (agg_bufs) 1792 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, 1793 agg_bufs, false); 1794 rc = -ENOMEM; 1795 goto next_rx; 1796 } 1797 } else { 1798 u32 payload; 1799 1800 if (rx_buf->data_ptr == data_ptr) 1801 payload = misc & RX_CMP_PAYLOAD_OFFSET; 1802 else 1803 payload = 0; 1804 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr, 1805 payload | len); 1806 if (!skb) { 1807 rc = -ENOMEM; 1808 goto next_rx; 1809 } 1810 } 1811 1812 if (agg_bufs) { 1813 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs, false); 1814 if (!skb) { 1815 rc = -ENOMEM; 1816 goto next_rx; 1817 } 1818 } 1819 1820 if (RX_CMP_HASH_VALID(rxcmp)) { 1821 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp); 1822 enum pkt_hash_types type = PKT_HASH_TYPE_L4; 1823 1824 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1825 if (hash_type != 1 && hash_type != 3) 1826 type = PKT_HASH_TYPE_L3; 1827 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type); 1828 } 1829 1830 cfa_code = RX_CMP_CFA_CODE(rxcmp1); 1831 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code)); 1832 1833 if ((rxcmp1->rx_cmp_flags2 & 1834 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) && 1835 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1836 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data); 1837 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK; 1838 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT; 1839 1840 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); 1841 } 1842 1843 skb_checksum_none_assert(skb); 1844 if (RX_CMP_L4_CS_OK(rxcmp1)) { 1845 if (dev->features & NETIF_F_RXCSUM) { 1846 skb->ip_summed = CHECKSUM_UNNECESSARY; 1847 skb->csum_level = RX_CMP_ENCAP(rxcmp1); 1848 } 1849 } else { 1850 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) { 1851 if (dev->features & NETIF_F_RXCSUM) 1852 bnapi->cp_ring.sw_stats.rx.rx_l4_csum_errors++; 1853 } 1854 } 1855 1856 bnxt_deliver_skb(bp, bnapi, skb); 1857 rc = 1; 1858 1859 next_rx: 1860 cpr->rx_packets += 1; 1861 cpr->rx_bytes += len; 1862 1863 next_rx_no_len: 1864 rxr->rx_prod = NEXT_RX(prod); 1865 rxr->rx_next_cons = NEXT_RX(cons); 1866 1867 next_rx_no_prod_no_len: 1868 *raw_cons = tmp_raw_cons; 1869 1870 return rc; 1871 } 1872 1873 /* In netpoll mode, if we are using a combined completion ring, we need to 1874 * discard the rx packets and recycle the buffers. 1875 */ 1876 static int bnxt_force_rx_discard(struct bnxt *bp, 1877 struct bnxt_cp_ring_info *cpr, 1878 u32 *raw_cons, u8 *event) 1879 { 1880 u32 tmp_raw_cons = *raw_cons; 1881 struct rx_cmp_ext *rxcmp1; 1882 struct rx_cmp *rxcmp; 1883 u16 cp_cons; 1884 u8 cmp_type; 1885 1886 cp_cons = RING_CMP(tmp_raw_cons); 1887 rxcmp = (struct rx_cmp *) 1888 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1889 1890 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1891 cp_cons = RING_CMP(tmp_raw_cons); 1892 rxcmp1 = (struct rx_cmp_ext *) 1893 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1894 1895 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1896 return -EBUSY; 1897 1898 cmp_type = RX_CMP_TYPE(rxcmp); 1899 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 1900 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 1901 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 1902 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1903 struct rx_tpa_end_cmp_ext *tpa_end1; 1904 1905 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1; 1906 tpa_end1->rx_tpa_end_cmp_errors_v2 |= 1907 cpu_to_le32(RX_TPA_END_CMP_ERRORS); 1908 } 1909 return bnxt_rx_pkt(bp, cpr, raw_cons, event); 1910 } 1911 1912 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx) 1913 { 1914 struct bnxt_fw_health *fw_health = bp->fw_health; 1915 u32 reg = fw_health->regs[reg_idx]; 1916 u32 reg_type, reg_off, val = 0; 1917 1918 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); 1919 reg_off = BNXT_FW_HEALTH_REG_OFF(reg); 1920 switch (reg_type) { 1921 case BNXT_FW_HEALTH_REG_TYPE_CFG: 1922 pci_read_config_dword(bp->pdev, reg_off, &val); 1923 break; 1924 case BNXT_FW_HEALTH_REG_TYPE_GRC: 1925 reg_off = fw_health->mapped_regs[reg_idx]; 1926 /* fall through */ 1927 case BNXT_FW_HEALTH_REG_TYPE_BAR0: 1928 val = readl(bp->bar0 + reg_off); 1929 break; 1930 case BNXT_FW_HEALTH_REG_TYPE_BAR1: 1931 val = readl(bp->bar1 + reg_off); 1932 break; 1933 } 1934 if (reg_idx == BNXT_FW_RESET_INPROG_REG) 1935 val &= fw_health->fw_reset_inprog_reg_mask; 1936 return val; 1937 } 1938 1939 #define BNXT_GET_EVENT_PORT(data) \ 1940 ((data) & \ 1941 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK) 1942 1943 static int bnxt_async_event_process(struct bnxt *bp, 1944 struct hwrm_async_event_cmpl *cmpl) 1945 { 1946 u16 event_id = le16_to_cpu(cmpl->event_id); 1947 1948 /* TODO CHIMP_FW: Define event id's for link change, error etc */ 1949 switch (event_id) { 1950 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: { 1951 u32 data1 = le32_to_cpu(cmpl->event_data1); 1952 struct bnxt_link_info *link_info = &bp->link_info; 1953 1954 if (BNXT_VF(bp)) 1955 goto async_event_process_exit; 1956 1957 /* print unsupported speed warning in forced speed mode only */ 1958 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) && 1959 (data1 & 0x20000)) { 1960 u16 fw_speed = link_info->force_link_speed; 1961 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed); 1962 1963 if (speed != SPEED_UNKNOWN) 1964 netdev_warn(bp->dev, "Link speed %d no longer supported\n", 1965 speed); 1966 } 1967 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event); 1968 } 1969 /* fall through */ 1970 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE: 1971 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE: 1972 set_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, &bp->sp_event); 1973 /* fall through */ 1974 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE: 1975 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event); 1976 break; 1977 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD: 1978 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event); 1979 break; 1980 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: { 1981 u32 data1 = le32_to_cpu(cmpl->event_data1); 1982 u16 port_id = BNXT_GET_EVENT_PORT(data1); 1983 1984 if (BNXT_VF(bp)) 1985 break; 1986 1987 if (bp->pf.port_id != port_id) 1988 break; 1989 1990 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event); 1991 break; 1992 } 1993 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE: 1994 if (BNXT_PF(bp)) 1995 goto async_event_process_exit; 1996 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event); 1997 break; 1998 case ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY: { 1999 u32 data1 = le32_to_cpu(cmpl->event_data1); 2000 2001 if (!bp->fw_health) 2002 goto async_event_process_exit; 2003 2004 bp->fw_reset_timestamp = jiffies; 2005 bp->fw_reset_min_dsecs = cmpl->timestamp_lo; 2006 if (!bp->fw_reset_min_dsecs) 2007 bp->fw_reset_min_dsecs = BNXT_DFLT_FW_RST_MIN_DSECS; 2008 bp->fw_reset_max_dsecs = le16_to_cpu(cmpl->timestamp_hi); 2009 if (!bp->fw_reset_max_dsecs) 2010 bp->fw_reset_max_dsecs = BNXT_DFLT_FW_RST_MAX_DSECS; 2011 if (EVENT_DATA1_RESET_NOTIFY_FATAL(data1)) { 2012 netdev_warn(bp->dev, "Firmware fatal reset event received\n"); 2013 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); 2014 } else { 2015 netdev_warn(bp->dev, "Firmware non-fatal reset event received, max wait time %d msec\n", 2016 bp->fw_reset_max_dsecs * 100); 2017 } 2018 set_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event); 2019 break; 2020 } 2021 case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY: { 2022 struct bnxt_fw_health *fw_health = bp->fw_health; 2023 u32 data1 = le32_to_cpu(cmpl->event_data1); 2024 2025 if (!fw_health) 2026 goto async_event_process_exit; 2027 2028 fw_health->enabled = EVENT_DATA1_RECOVERY_ENABLED(data1); 2029 fw_health->master = EVENT_DATA1_RECOVERY_MASTER_FUNC(data1); 2030 if (!fw_health->enabled) 2031 break; 2032 2033 if (netif_msg_drv(bp)) 2034 netdev_info(bp->dev, "Error recovery info: error recovery[%d], master[%d], reset count[0x%x], health status: 0x%x\n", 2035 fw_health->enabled, fw_health->master, 2036 bnxt_fw_health_readl(bp, 2037 BNXT_FW_RESET_CNT_REG), 2038 bnxt_fw_health_readl(bp, 2039 BNXT_FW_HEALTH_REG)); 2040 fw_health->tmr_multiplier = 2041 DIV_ROUND_UP(fw_health->polling_dsecs * HZ, 2042 bp->current_interval * 10); 2043 fw_health->tmr_counter = fw_health->tmr_multiplier; 2044 fw_health->last_fw_heartbeat = 2045 bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); 2046 fw_health->last_fw_reset_cnt = 2047 bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 2048 goto async_event_process_exit; 2049 } 2050 default: 2051 goto async_event_process_exit; 2052 } 2053 bnxt_queue_sp_work(bp); 2054 async_event_process_exit: 2055 bnxt_ulp_async_events(bp, cmpl); 2056 return 0; 2057 } 2058 2059 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp) 2060 { 2061 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id; 2062 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp; 2063 struct hwrm_fwd_req_cmpl *fwd_req_cmpl = 2064 (struct hwrm_fwd_req_cmpl *)txcmp; 2065 2066 switch (cmpl_type) { 2067 case CMPL_BASE_TYPE_HWRM_DONE: 2068 seq_id = le16_to_cpu(h_cmpl->sequence_id); 2069 if (seq_id == bp->hwrm_intr_seq_id) 2070 bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id; 2071 else 2072 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id); 2073 break; 2074 2075 case CMPL_BASE_TYPE_HWRM_FWD_REQ: 2076 vf_id = le16_to_cpu(fwd_req_cmpl->source_id); 2077 2078 if ((vf_id < bp->pf.first_vf_id) || 2079 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) { 2080 netdev_err(bp->dev, "Msg contains invalid VF id %x\n", 2081 vf_id); 2082 return -EINVAL; 2083 } 2084 2085 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap); 2086 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event); 2087 bnxt_queue_sp_work(bp); 2088 break; 2089 2090 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: 2091 bnxt_async_event_process(bp, 2092 (struct hwrm_async_event_cmpl *)txcmp); 2093 2094 default: 2095 break; 2096 } 2097 2098 return 0; 2099 } 2100 2101 static irqreturn_t bnxt_msix(int irq, void *dev_instance) 2102 { 2103 struct bnxt_napi *bnapi = dev_instance; 2104 struct bnxt *bp = bnapi->bp; 2105 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2106 u32 cons = RING_CMP(cpr->cp_raw_cons); 2107 2108 cpr->event_ctr++; 2109 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 2110 napi_schedule(&bnapi->napi); 2111 return IRQ_HANDLED; 2112 } 2113 2114 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) 2115 { 2116 u32 raw_cons = cpr->cp_raw_cons; 2117 u16 cons = RING_CMP(raw_cons); 2118 struct tx_cmp *txcmp; 2119 2120 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2121 2122 return TX_CMP_VALID(txcmp, raw_cons); 2123 } 2124 2125 static irqreturn_t bnxt_inta(int irq, void *dev_instance) 2126 { 2127 struct bnxt_napi *bnapi = dev_instance; 2128 struct bnxt *bp = bnapi->bp; 2129 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2130 u32 cons = RING_CMP(cpr->cp_raw_cons); 2131 u32 int_status; 2132 2133 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 2134 2135 if (!bnxt_has_work(bp, cpr)) { 2136 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS); 2137 /* return if erroneous interrupt */ 2138 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id))) 2139 return IRQ_NONE; 2140 } 2141 2142 /* disable ring IRQ */ 2143 BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell); 2144 2145 /* Return here if interrupt is shared and is disabled. */ 2146 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 2147 return IRQ_HANDLED; 2148 2149 napi_schedule(&bnapi->napi); 2150 return IRQ_HANDLED; 2151 } 2152 2153 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2154 int budget) 2155 { 2156 struct bnxt_napi *bnapi = cpr->bnapi; 2157 u32 raw_cons = cpr->cp_raw_cons; 2158 u32 cons; 2159 int tx_pkts = 0; 2160 int rx_pkts = 0; 2161 u8 event = 0; 2162 struct tx_cmp *txcmp; 2163 2164 cpr->has_more_work = 0; 2165 cpr->had_work_done = 1; 2166 while (1) { 2167 int rc; 2168 2169 cons = RING_CMP(raw_cons); 2170 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2171 2172 if (!TX_CMP_VALID(txcmp, raw_cons)) 2173 break; 2174 2175 /* The valid test of the entry must be done first before 2176 * reading any further. 2177 */ 2178 dma_rmb(); 2179 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) { 2180 tx_pkts++; 2181 /* return full budget so NAPI will complete. */ 2182 if (unlikely(tx_pkts > bp->tx_wake_thresh)) { 2183 rx_pkts = budget; 2184 raw_cons = NEXT_RAW_CMP(raw_cons); 2185 if (budget) 2186 cpr->has_more_work = 1; 2187 break; 2188 } 2189 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 2190 if (likely(budget)) 2191 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); 2192 else 2193 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons, 2194 &event); 2195 if (likely(rc >= 0)) 2196 rx_pkts += rc; 2197 /* Increment rx_pkts when rc is -ENOMEM to count towards 2198 * the NAPI budget. Otherwise, we may potentially loop 2199 * here forever if we consistently cannot allocate 2200 * buffers. 2201 */ 2202 else if (rc == -ENOMEM && budget) 2203 rx_pkts++; 2204 else if (rc == -EBUSY) /* partial completion */ 2205 break; 2206 } else if (unlikely((TX_CMP_TYPE(txcmp) == 2207 CMPL_BASE_TYPE_HWRM_DONE) || 2208 (TX_CMP_TYPE(txcmp) == 2209 CMPL_BASE_TYPE_HWRM_FWD_REQ) || 2210 (TX_CMP_TYPE(txcmp) == 2211 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) { 2212 bnxt_hwrm_handler(bp, txcmp); 2213 } 2214 raw_cons = NEXT_RAW_CMP(raw_cons); 2215 2216 if (rx_pkts && rx_pkts == budget) { 2217 cpr->has_more_work = 1; 2218 break; 2219 } 2220 } 2221 2222 if (event & BNXT_REDIRECT_EVENT) 2223 xdp_do_flush_map(); 2224 2225 if (event & BNXT_TX_EVENT) { 2226 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 2227 u16 prod = txr->tx_prod; 2228 2229 /* Sync BD data before updating doorbell */ 2230 wmb(); 2231 2232 bnxt_db_write_relaxed(bp, &txr->tx_db, prod); 2233 } 2234 2235 cpr->cp_raw_cons = raw_cons; 2236 bnapi->tx_pkts += tx_pkts; 2237 bnapi->events |= event; 2238 return rx_pkts; 2239 } 2240 2241 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi) 2242 { 2243 if (bnapi->tx_pkts) { 2244 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts); 2245 bnapi->tx_pkts = 0; 2246 } 2247 2248 if (bnapi->events & BNXT_RX_EVENT) { 2249 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 2250 2251 if (bnapi->events & BNXT_AGG_EVENT) 2252 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 2253 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 2254 } 2255 bnapi->events = 0; 2256 } 2257 2258 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2259 int budget) 2260 { 2261 struct bnxt_napi *bnapi = cpr->bnapi; 2262 int rx_pkts; 2263 2264 rx_pkts = __bnxt_poll_work(bp, cpr, budget); 2265 2266 /* ACK completion ring before freeing tx ring and producing new 2267 * buffers in rx/agg rings to prevent overflowing the completion 2268 * ring. 2269 */ 2270 bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons); 2271 2272 __bnxt_poll_work_done(bp, bnapi); 2273 return rx_pkts; 2274 } 2275 2276 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget) 2277 { 2278 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2279 struct bnxt *bp = bnapi->bp; 2280 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2281 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 2282 struct tx_cmp *txcmp; 2283 struct rx_cmp_ext *rxcmp1; 2284 u32 cp_cons, tmp_raw_cons; 2285 u32 raw_cons = cpr->cp_raw_cons; 2286 u32 rx_pkts = 0; 2287 u8 event = 0; 2288 2289 while (1) { 2290 int rc; 2291 2292 cp_cons = RING_CMP(raw_cons); 2293 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2294 2295 if (!TX_CMP_VALID(txcmp, raw_cons)) 2296 break; 2297 2298 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 2299 tmp_raw_cons = NEXT_RAW_CMP(raw_cons); 2300 cp_cons = RING_CMP(tmp_raw_cons); 2301 rxcmp1 = (struct rx_cmp_ext *) 2302 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2303 2304 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 2305 break; 2306 2307 /* force an error to recycle the buffer */ 2308 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 2309 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 2310 2311 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); 2312 if (likely(rc == -EIO) && budget) 2313 rx_pkts++; 2314 else if (rc == -EBUSY) /* partial completion */ 2315 break; 2316 } else if (unlikely(TX_CMP_TYPE(txcmp) == 2317 CMPL_BASE_TYPE_HWRM_DONE)) { 2318 bnxt_hwrm_handler(bp, txcmp); 2319 } else { 2320 netdev_err(bp->dev, 2321 "Invalid completion received on special ring\n"); 2322 } 2323 raw_cons = NEXT_RAW_CMP(raw_cons); 2324 2325 if (rx_pkts == budget) 2326 break; 2327 } 2328 2329 cpr->cp_raw_cons = raw_cons; 2330 BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons); 2331 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 2332 2333 if (event & BNXT_AGG_EVENT) 2334 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 2335 2336 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) { 2337 napi_complete_done(napi, rx_pkts); 2338 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2339 } 2340 return rx_pkts; 2341 } 2342 2343 static int bnxt_poll(struct napi_struct *napi, int budget) 2344 { 2345 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2346 struct bnxt *bp = bnapi->bp; 2347 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2348 int work_done = 0; 2349 2350 while (1) { 2351 work_done += bnxt_poll_work(bp, cpr, budget - work_done); 2352 2353 if (work_done >= budget) { 2354 if (!budget) 2355 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2356 break; 2357 } 2358 2359 if (!bnxt_has_work(bp, cpr)) { 2360 if (napi_complete_done(napi, work_done)) 2361 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2362 break; 2363 } 2364 } 2365 if (bp->flags & BNXT_FLAG_DIM) { 2366 struct dim_sample dim_sample = {}; 2367 2368 dim_update_sample(cpr->event_ctr, 2369 cpr->rx_packets, 2370 cpr->rx_bytes, 2371 &dim_sample); 2372 net_dim(&cpr->dim, dim_sample); 2373 } 2374 return work_done; 2375 } 2376 2377 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget) 2378 { 2379 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2380 int i, work_done = 0; 2381 2382 for (i = 0; i < 2; i++) { 2383 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; 2384 2385 if (cpr2) { 2386 work_done += __bnxt_poll_work(bp, cpr2, 2387 budget - work_done); 2388 cpr->has_more_work |= cpr2->has_more_work; 2389 } 2390 } 2391 return work_done; 2392 } 2393 2394 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi, 2395 u64 dbr_type) 2396 { 2397 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2398 int i; 2399 2400 for (i = 0; i < 2; i++) { 2401 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; 2402 struct bnxt_db_info *db; 2403 2404 if (cpr2 && cpr2->had_work_done) { 2405 db = &cpr2->cp_db; 2406 writeq(db->db_key64 | dbr_type | 2407 RING_CMP(cpr2->cp_raw_cons), db->doorbell); 2408 cpr2->had_work_done = 0; 2409 } 2410 } 2411 __bnxt_poll_work_done(bp, bnapi); 2412 } 2413 2414 static int bnxt_poll_p5(struct napi_struct *napi, int budget) 2415 { 2416 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2417 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2418 u32 raw_cons = cpr->cp_raw_cons; 2419 struct bnxt *bp = bnapi->bp; 2420 struct nqe_cn *nqcmp; 2421 int work_done = 0; 2422 u32 cons; 2423 2424 if (cpr->has_more_work) { 2425 cpr->has_more_work = 0; 2426 work_done = __bnxt_poll_cqs(bp, bnapi, budget); 2427 } 2428 while (1) { 2429 cons = RING_CMP(raw_cons); 2430 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2431 2432 if (!NQ_CMP_VALID(nqcmp, raw_cons)) { 2433 if (cpr->has_more_work) 2434 break; 2435 2436 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL); 2437 cpr->cp_raw_cons = raw_cons; 2438 if (napi_complete_done(napi, work_done)) 2439 BNXT_DB_NQ_ARM_P5(&cpr->cp_db, 2440 cpr->cp_raw_cons); 2441 return work_done; 2442 } 2443 2444 /* The valid test of the entry must be done first before 2445 * reading any further. 2446 */ 2447 dma_rmb(); 2448 2449 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) { 2450 u32 idx = le32_to_cpu(nqcmp->cq_handle_low); 2451 struct bnxt_cp_ring_info *cpr2; 2452 2453 cpr2 = cpr->cp_ring_arr[idx]; 2454 work_done += __bnxt_poll_work(bp, cpr2, 2455 budget - work_done); 2456 cpr->has_more_work |= cpr2->has_more_work; 2457 } else { 2458 bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp); 2459 } 2460 raw_cons = NEXT_RAW_CMP(raw_cons); 2461 } 2462 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ); 2463 if (raw_cons != cpr->cp_raw_cons) { 2464 cpr->cp_raw_cons = raw_cons; 2465 BNXT_DB_NQ_P5(&cpr->cp_db, raw_cons); 2466 } 2467 return work_done; 2468 } 2469 2470 static void bnxt_free_tx_skbs(struct bnxt *bp) 2471 { 2472 int i, max_idx; 2473 struct pci_dev *pdev = bp->pdev; 2474 2475 if (!bp->tx_ring) 2476 return; 2477 2478 max_idx = bp->tx_nr_pages * TX_DESC_CNT; 2479 for (i = 0; i < bp->tx_nr_rings; i++) { 2480 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2481 int j; 2482 2483 for (j = 0; j < max_idx;) { 2484 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; 2485 struct sk_buff *skb; 2486 int k, last; 2487 2488 if (i < bp->tx_nr_rings_xdp && 2489 tx_buf->action == XDP_REDIRECT) { 2490 dma_unmap_single(&pdev->dev, 2491 dma_unmap_addr(tx_buf, mapping), 2492 dma_unmap_len(tx_buf, len), 2493 PCI_DMA_TODEVICE); 2494 xdp_return_frame(tx_buf->xdpf); 2495 tx_buf->action = 0; 2496 tx_buf->xdpf = NULL; 2497 j++; 2498 continue; 2499 } 2500 2501 skb = tx_buf->skb; 2502 if (!skb) { 2503 j++; 2504 continue; 2505 } 2506 2507 tx_buf->skb = NULL; 2508 2509 if (tx_buf->is_push) { 2510 dev_kfree_skb(skb); 2511 j += 2; 2512 continue; 2513 } 2514 2515 dma_unmap_single(&pdev->dev, 2516 dma_unmap_addr(tx_buf, mapping), 2517 skb_headlen(skb), 2518 PCI_DMA_TODEVICE); 2519 2520 last = tx_buf->nr_frags; 2521 j += 2; 2522 for (k = 0; k < last; k++, j++) { 2523 int ring_idx = j & bp->tx_ring_mask; 2524 skb_frag_t *frag = &skb_shinfo(skb)->frags[k]; 2525 2526 tx_buf = &txr->tx_buf_ring[ring_idx]; 2527 dma_unmap_page( 2528 &pdev->dev, 2529 dma_unmap_addr(tx_buf, mapping), 2530 skb_frag_size(frag), PCI_DMA_TODEVICE); 2531 } 2532 dev_kfree_skb(skb); 2533 } 2534 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); 2535 } 2536 } 2537 2538 static void bnxt_free_rx_skbs(struct bnxt *bp) 2539 { 2540 int i, max_idx, max_agg_idx; 2541 struct pci_dev *pdev = bp->pdev; 2542 2543 if (!bp->rx_ring) 2544 return; 2545 2546 max_idx = bp->rx_nr_pages * RX_DESC_CNT; 2547 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT; 2548 for (i = 0; i < bp->rx_nr_rings; i++) { 2549 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2550 struct bnxt_tpa_idx_map *map; 2551 int j; 2552 2553 if (rxr->rx_tpa) { 2554 for (j = 0; j < bp->max_tpa; j++) { 2555 struct bnxt_tpa_info *tpa_info = 2556 &rxr->rx_tpa[j]; 2557 u8 *data = tpa_info->data; 2558 2559 if (!data) 2560 continue; 2561 2562 dma_unmap_single_attrs(&pdev->dev, 2563 tpa_info->mapping, 2564 bp->rx_buf_use_size, 2565 bp->rx_dir, 2566 DMA_ATTR_WEAK_ORDERING); 2567 2568 tpa_info->data = NULL; 2569 2570 kfree(data); 2571 } 2572 } 2573 2574 for (j = 0; j < max_idx; j++) { 2575 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j]; 2576 dma_addr_t mapping = rx_buf->mapping; 2577 void *data = rx_buf->data; 2578 2579 if (!data) 2580 continue; 2581 2582 rx_buf->data = NULL; 2583 2584 if (BNXT_RX_PAGE_MODE(bp)) { 2585 mapping -= bp->rx_dma_offset; 2586 dma_unmap_page_attrs(&pdev->dev, mapping, 2587 PAGE_SIZE, bp->rx_dir, 2588 DMA_ATTR_WEAK_ORDERING); 2589 page_pool_recycle_direct(rxr->page_pool, data); 2590 } else { 2591 dma_unmap_single_attrs(&pdev->dev, mapping, 2592 bp->rx_buf_use_size, 2593 bp->rx_dir, 2594 DMA_ATTR_WEAK_ORDERING); 2595 kfree(data); 2596 } 2597 } 2598 2599 for (j = 0; j < max_agg_idx; j++) { 2600 struct bnxt_sw_rx_agg_bd *rx_agg_buf = 2601 &rxr->rx_agg_ring[j]; 2602 struct page *page = rx_agg_buf->page; 2603 2604 if (!page) 2605 continue; 2606 2607 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping, 2608 BNXT_RX_PAGE_SIZE, 2609 PCI_DMA_FROMDEVICE, 2610 DMA_ATTR_WEAK_ORDERING); 2611 2612 rx_agg_buf->page = NULL; 2613 __clear_bit(j, rxr->rx_agg_bmap); 2614 2615 __free_page(page); 2616 } 2617 if (rxr->rx_page) { 2618 __free_page(rxr->rx_page); 2619 rxr->rx_page = NULL; 2620 } 2621 map = rxr->rx_tpa_idx_map; 2622 if (map) 2623 memset(map->agg_idx_bmap, 0, sizeof(map->agg_idx_bmap)); 2624 } 2625 } 2626 2627 static void bnxt_free_skbs(struct bnxt *bp) 2628 { 2629 bnxt_free_tx_skbs(bp); 2630 bnxt_free_rx_skbs(bp); 2631 } 2632 2633 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) 2634 { 2635 struct pci_dev *pdev = bp->pdev; 2636 int i; 2637 2638 for (i = 0; i < rmem->nr_pages; i++) { 2639 if (!rmem->pg_arr[i]) 2640 continue; 2641 2642 dma_free_coherent(&pdev->dev, rmem->page_size, 2643 rmem->pg_arr[i], rmem->dma_arr[i]); 2644 2645 rmem->pg_arr[i] = NULL; 2646 } 2647 if (rmem->pg_tbl) { 2648 size_t pg_tbl_size = rmem->nr_pages * 8; 2649 2650 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) 2651 pg_tbl_size = rmem->page_size; 2652 dma_free_coherent(&pdev->dev, pg_tbl_size, 2653 rmem->pg_tbl, rmem->pg_tbl_map); 2654 rmem->pg_tbl = NULL; 2655 } 2656 if (rmem->vmem_size && *rmem->vmem) { 2657 vfree(*rmem->vmem); 2658 *rmem->vmem = NULL; 2659 } 2660 } 2661 2662 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) 2663 { 2664 struct pci_dev *pdev = bp->pdev; 2665 u64 valid_bit = 0; 2666 int i; 2667 2668 if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG)) 2669 valid_bit = PTU_PTE_VALID; 2670 if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) { 2671 size_t pg_tbl_size = rmem->nr_pages * 8; 2672 2673 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) 2674 pg_tbl_size = rmem->page_size; 2675 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size, 2676 &rmem->pg_tbl_map, 2677 GFP_KERNEL); 2678 if (!rmem->pg_tbl) 2679 return -ENOMEM; 2680 } 2681 2682 for (i = 0; i < rmem->nr_pages; i++) { 2683 u64 extra_bits = valid_bit; 2684 2685 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev, 2686 rmem->page_size, 2687 &rmem->dma_arr[i], 2688 GFP_KERNEL); 2689 if (!rmem->pg_arr[i]) 2690 return -ENOMEM; 2691 2692 if (rmem->init_val) 2693 memset(rmem->pg_arr[i], rmem->init_val, 2694 rmem->page_size); 2695 if (rmem->nr_pages > 1 || rmem->depth > 0) { 2696 if (i == rmem->nr_pages - 2 && 2697 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 2698 extra_bits |= PTU_PTE_NEXT_TO_LAST; 2699 else if (i == rmem->nr_pages - 1 && 2700 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 2701 extra_bits |= PTU_PTE_LAST; 2702 rmem->pg_tbl[i] = 2703 cpu_to_le64(rmem->dma_arr[i] | extra_bits); 2704 } 2705 } 2706 2707 if (rmem->vmem_size) { 2708 *rmem->vmem = vzalloc(rmem->vmem_size); 2709 if (!(*rmem->vmem)) 2710 return -ENOMEM; 2711 } 2712 return 0; 2713 } 2714 2715 static void bnxt_free_tpa_info(struct bnxt *bp) 2716 { 2717 int i; 2718 2719 for (i = 0; i < bp->rx_nr_rings; i++) { 2720 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2721 2722 kfree(rxr->rx_tpa_idx_map); 2723 rxr->rx_tpa_idx_map = NULL; 2724 if (rxr->rx_tpa) { 2725 kfree(rxr->rx_tpa[0].agg_arr); 2726 rxr->rx_tpa[0].agg_arr = NULL; 2727 } 2728 kfree(rxr->rx_tpa); 2729 rxr->rx_tpa = NULL; 2730 } 2731 } 2732 2733 static int bnxt_alloc_tpa_info(struct bnxt *bp) 2734 { 2735 int i, j, total_aggs = 0; 2736 2737 bp->max_tpa = MAX_TPA; 2738 if (bp->flags & BNXT_FLAG_CHIP_P5) { 2739 if (!bp->max_tpa_v2) 2740 return 0; 2741 bp->max_tpa = max_t(u16, bp->max_tpa_v2, MAX_TPA_P5); 2742 total_aggs = bp->max_tpa * MAX_SKB_FRAGS; 2743 } 2744 2745 for (i = 0; i < bp->rx_nr_rings; i++) { 2746 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2747 struct rx_agg_cmp *agg; 2748 2749 rxr->rx_tpa = kcalloc(bp->max_tpa, sizeof(struct bnxt_tpa_info), 2750 GFP_KERNEL); 2751 if (!rxr->rx_tpa) 2752 return -ENOMEM; 2753 2754 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 2755 continue; 2756 agg = kcalloc(total_aggs, sizeof(*agg), GFP_KERNEL); 2757 rxr->rx_tpa[0].agg_arr = agg; 2758 if (!agg) 2759 return -ENOMEM; 2760 for (j = 1; j < bp->max_tpa; j++) 2761 rxr->rx_tpa[j].agg_arr = agg + j * MAX_SKB_FRAGS; 2762 rxr->rx_tpa_idx_map = kzalloc(sizeof(*rxr->rx_tpa_idx_map), 2763 GFP_KERNEL); 2764 if (!rxr->rx_tpa_idx_map) 2765 return -ENOMEM; 2766 } 2767 return 0; 2768 } 2769 2770 static void bnxt_free_rx_rings(struct bnxt *bp) 2771 { 2772 int i; 2773 2774 if (!bp->rx_ring) 2775 return; 2776 2777 bnxt_free_tpa_info(bp); 2778 for (i = 0; i < bp->rx_nr_rings; i++) { 2779 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2780 struct bnxt_ring_struct *ring; 2781 2782 if (rxr->xdp_prog) 2783 bpf_prog_put(rxr->xdp_prog); 2784 2785 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq)) 2786 xdp_rxq_info_unreg(&rxr->xdp_rxq); 2787 2788 page_pool_destroy(rxr->page_pool); 2789 rxr->page_pool = NULL; 2790 2791 kfree(rxr->rx_agg_bmap); 2792 rxr->rx_agg_bmap = NULL; 2793 2794 ring = &rxr->rx_ring_struct; 2795 bnxt_free_ring(bp, &ring->ring_mem); 2796 2797 ring = &rxr->rx_agg_ring_struct; 2798 bnxt_free_ring(bp, &ring->ring_mem); 2799 } 2800 } 2801 2802 static int bnxt_alloc_rx_page_pool(struct bnxt *bp, 2803 struct bnxt_rx_ring_info *rxr) 2804 { 2805 struct page_pool_params pp = { 0 }; 2806 2807 pp.pool_size = bp->rx_ring_size; 2808 pp.nid = dev_to_node(&bp->pdev->dev); 2809 pp.dev = &bp->pdev->dev; 2810 pp.dma_dir = DMA_BIDIRECTIONAL; 2811 2812 rxr->page_pool = page_pool_create(&pp); 2813 if (IS_ERR(rxr->page_pool)) { 2814 int err = PTR_ERR(rxr->page_pool); 2815 2816 rxr->page_pool = NULL; 2817 return err; 2818 } 2819 return 0; 2820 } 2821 2822 static int bnxt_alloc_rx_rings(struct bnxt *bp) 2823 { 2824 int i, rc = 0, agg_rings = 0; 2825 2826 if (!bp->rx_ring) 2827 return -ENOMEM; 2828 2829 if (bp->flags & BNXT_FLAG_AGG_RINGS) 2830 agg_rings = 1; 2831 2832 for (i = 0; i < bp->rx_nr_rings; i++) { 2833 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2834 struct bnxt_ring_struct *ring; 2835 2836 ring = &rxr->rx_ring_struct; 2837 2838 rc = bnxt_alloc_rx_page_pool(bp, rxr); 2839 if (rc) 2840 return rc; 2841 2842 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i); 2843 if (rc < 0) 2844 return rc; 2845 2846 rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq, 2847 MEM_TYPE_PAGE_POOL, 2848 rxr->page_pool); 2849 if (rc) { 2850 xdp_rxq_info_unreg(&rxr->xdp_rxq); 2851 return rc; 2852 } 2853 2854 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 2855 if (rc) 2856 return rc; 2857 2858 ring->grp_idx = i; 2859 if (agg_rings) { 2860 u16 mem_size; 2861 2862 ring = &rxr->rx_agg_ring_struct; 2863 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 2864 if (rc) 2865 return rc; 2866 2867 ring->grp_idx = i; 2868 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1; 2869 mem_size = rxr->rx_agg_bmap_size / 8; 2870 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL); 2871 if (!rxr->rx_agg_bmap) 2872 return -ENOMEM; 2873 } 2874 } 2875 if (bp->flags & BNXT_FLAG_TPA) 2876 rc = bnxt_alloc_tpa_info(bp); 2877 return rc; 2878 } 2879 2880 static void bnxt_free_tx_rings(struct bnxt *bp) 2881 { 2882 int i; 2883 struct pci_dev *pdev = bp->pdev; 2884 2885 if (!bp->tx_ring) 2886 return; 2887 2888 for (i = 0; i < bp->tx_nr_rings; i++) { 2889 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2890 struct bnxt_ring_struct *ring; 2891 2892 if (txr->tx_push) { 2893 dma_free_coherent(&pdev->dev, bp->tx_push_size, 2894 txr->tx_push, txr->tx_push_mapping); 2895 txr->tx_push = NULL; 2896 } 2897 2898 ring = &txr->tx_ring_struct; 2899 2900 bnxt_free_ring(bp, &ring->ring_mem); 2901 } 2902 } 2903 2904 static int bnxt_alloc_tx_rings(struct bnxt *bp) 2905 { 2906 int i, j, rc; 2907 struct pci_dev *pdev = bp->pdev; 2908 2909 bp->tx_push_size = 0; 2910 if (bp->tx_push_thresh) { 2911 int push_size; 2912 2913 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) + 2914 bp->tx_push_thresh); 2915 2916 if (push_size > 256) { 2917 push_size = 0; 2918 bp->tx_push_thresh = 0; 2919 } 2920 2921 bp->tx_push_size = push_size; 2922 } 2923 2924 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) { 2925 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2926 struct bnxt_ring_struct *ring; 2927 u8 qidx; 2928 2929 ring = &txr->tx_ring_struct; 2930 2931 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 2932 if (rc) 2933 return rc; 2934 2935 ring->grp_idx = txr->bnapi->index; 2936 if (bp->tx_push_size) { 2937 dma_addr_t mapping; 2938 2939 /* One pre-allocated DMA buffer to backup 2940 * TX push operation 2941 */ 2942 txr->tx_push = dma_alloc_coherent(&pdev->dev, 2943 bp->tx_push_size, 2944 &txr->tx_push_mapping, 2945 GFP_KERNEL); 2946 2947 if (!txr->tx_push) 2948 return -ENOMEM; 2949 2950 mapping = txr->tx_push_mapping + 2951 sizeof(struct tx_push_bd); 2952 txr->data_mapping = cpu_to_le64(mapping); 2953 } 2954 qidx = bp->tc_to_qidx[j]; 2955 ring->queue_id = bp->q_info[qidx].queue_id; 2956 if (i < bp->tx_nr_rings_xdp) 2957 continue; 2958 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1)) 2959 j++; 2960 } 2961 return 0; 2962 } 2963 2964 static void bnxt_free_cp_rings(struct bnxt *bp) 2965 { 2966 int i; 2967 2968 if (!bp->bnapi) 2969 return; 2970 2971 for (i = 0; i < bp->cp_nr_rings; i++) { 2972 struct bnxt_napi *bnapi = bp->bnapi[i]; 2973 struct bnxt_cp_ring_info *cpr; 2974 struct bnxt_ring_struct *ring; 2975 int j; 2976 2977 if (!bnapi) 2978 continue; 2979 2980 cpr = &bnapi->cp_ring; 2981 ring = &cpr->cp_ring_struct; 2982 2983 bnxt_free_ring(bp, &ring->ring_mem); 2984 2985 for (j = 0; j < 2; j++) { 2986 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 2987 2988 if (cpr2) { 2989 ring = &cpr2->cp_ring_struct; 2990 bnxt_free_ring(bp, &ring->ring_mem); 2991 kfree(cpr2); 2992 cpr->cp_ring_arr[j] = NULL; 2993 } 2994 } 2995 } 2996 } 2997 2998 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp) 2999 { 3000 struct bnxt_ring_mem_info *rmem; 3001 struct bnxt_ring_struct *ring; 3002 struct bnxt_cp_ring_info *cpr; 3003 int rc; 3004 3005 cpr = kzalloc(sizeof(*cpr), GFP_KERNEL); 3006 if (!cpr) 3007 return NULL; 3008 3009 ring = &cpr->cp_ring_struct; 3010 rmem = &ring->ring_mem; 3011 rmem->nr_pages = bp->cp_nr_pages; 3012 rmem->page_size = HW_CMPD_RING_SIZE; 3013 rmem->pg_arr = (void **)cpr->cp_desc_ring; 3014 rmem->dma_arr = cpr->cp_desc_mapping; 3015 rmem->flags = BNXT_RMEM_RING_PTE_FLAG; 3016 rc = bnxt_alloc_ring(bp, rmem); 3017 if (rc) { 3018 bnxt_free_ring(bp, rmem); 3019 kfree(cpr); 3020 cpr = NULL; 3021 } 3022 return cpr; 3023 } 3024 3025 static int bnxt_alloc_cp_rings(struct bnxt *bp) 3026 { 3027 bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS); 3028 int i, rc, ulp_base_vec, ulp_msix; 3029 3030 ulp_msix = bnxt_get_ulp_msix_num(bp); 3031 ulp_base_vec = bnxt_get_ulp_msix_base(bp); 3032 for (i = 0; i < bp->cp_nr_rings; i++) { 3033 struct bnxt_napi *bnapi = bp->bnapi[i]; 3034 struct bnxt_cp_ring_info *cpr; 3035 struct bnxt_ring_struct *ring; 3036 3037 if (!bnapi) 3038 continue; 3039 3040 cpr = &bnapi->cp_ring; 3041 cpr->bnapi = bnapi; 3042 ring = &cpr->cp_ring_struct; 3043 3044 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 3045 if (rc) 3046 return rc; 3047 3048 if (ulp_msix && i >= ulp_base_vec) 3049 ring->map_idx = i + ulp_msix; 3050 else 3051 ring->map_idx = i; 3052 3053 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 3054 continue; 3055 3056 if (i < bp->rx_nr_rings) { 3057 struct bnxt_cp_ring_info *cpr2 = 3058 bnxt_alloc_cp_sub_ring(bp); 3059 3060 cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2; 3061 if (!cpr2) 3062 return -ENOMEM; 3063 cpr2->bnapi = bnapi; 3064 } 3065 if ((sh && i < bp->tx_nr_rings) || 3066 (!sh && i >= bp->rx_nr_rings)) { 3067 struct bnxt_cp_ring_info *cpr2 = 3068 bnxt_alloc_cp_sub_ring(bp); 3069 3070 cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2; 3071 if (!cpr2) 3072 return -ENOMEM; 3073 cpr2->bnapi = bnapi; 3074 } 3075 } 3076 return 0; 3077 } 3078 3079 static void bnxt_init_ring_struct(struct bnxt *bp) 3080 { 3081 int i; 3082 3083 for (i = 0; i < bp->cp_nr_rings; i++) { 3084 struct bnxt_napi *bnapi = bp->bnapi[i]; 3085 struct bnxt_ring_mem_info *rmem; 3086 struct bnxt_cp_ring_info *cpr; 3087 struct bnxt_rx_ring_info *rxr; 3088 struct bnxt_tx_ring_info *txr; 3089 struct bnxt_ring_struct *ring; 3090 3091 if (!bnapi) 3092 continue; 3093 3094 cpr = &bnapi->cp_ring; 3095 ring = &cpr->cp_ring_struct; 3096 rmem = &ring->ring_mem; 3097 rmem->nr_pages = bp->cp_nr_pages; 3098 rmem->page_size = HW_CMPD_RING_SIZE; 3099 rmem->pg_arr = (void **)cpr->cp_desc_ring; 3100 rmem->dma_arr = cpr->cp_desc_mapping; 3101 rmem->vmem_size = 0; 3102 3103 rxr = bnapi->rx_ring; 3104 if (!rxr) 3105 goto skip_rx; 3106 3107 ring = &rxr->rx_ring_struct; 3108 rmem = &ring->ring_mem; 3109 rmem->nr_pages = bp->rx_nr_pages; 3110 rmem->page_size = HW_RXBD_RING_SIZE; 3111 rmem->pg_arr = (void **)rxr->rx_desc_ring; 3112 rmem->dma_arr = rxr->rx_desc_mapping; 3113 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages; 3114 rmem->vmem = (void **)&rxr->rx_buf_ring; 3115 3116 ring = &rxr->rx_agg_ring_struct; 3117 rmem = &ring->ring_mem; 3118 rmem->nr_pages = bp->rx_agg_nr_pages; 3119 rmem->page_size = HW_RXBD_RING_SIZE; 3120 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring; 3121 rmem->dma_arr = rxr->rx_agg_desc_mapping; 3122 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages; 3123 rmem->vmem = (void **)&rxr->rx_agg_ring; 3124 3125 skip_rx: 3126 txr = bnapi->tx_ring; 3127 if (!txr) 3128 continue; 3129 3130 ring = &txr->tx_ring_struct; 3131 rmem = &ring->ring_mem; 3132 rmem->nr_pages = bp->tx_nr_pages; 3133 rmem->page_size = HW_RXBD_RING_SIZE; 3134 rmem->pg_arr = (void **)txr->tx_desc_ring; 3135 rmem->dma_arr = txr->tx_desc_mapping; 3136 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages; 3137 rmem->vmem = (void **)&txr->tx_buf_ring; 3138 } 3139 } 3140 3141 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type) 3142 { 3143 int i; 3144 u32 prod; 3145 struct rx_bd **rx_buf_ring; 3146 3147 rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr; 3148 for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) { 3149 int j; 3150 struct rx_bd *rxbd; 3151 3152 rxbd = rx_buf_ring[i]; 3153 if (!rxbd) 3154 continue; 3155 3156 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) { 3157 rxbd->rx_bd_len_flags_type = cpu_to_le32(type); 3158 rxbd->rx_bd_opaque = prod; 3159 } 3160 } 3161 } 3162 3163 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr) 3164 { 3165 struct net_device *dev = bp->dev; 3166 struct bnxt_rx_ring_info *rxr; 3167 struct bnxt_ring_struct *ring; 3168 u32 prod, type; 3169 int i; 3170 3171 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) | 3172 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP; 3173 3174 if (NET_IP_ALIGN == 2) 3175 type |= RX_BD_FLAGS_SOP; 3176 3177 rxr = &bp->rx_ring[ring_nr]; 3178 ring = &rxr->rx_ring_struct; 3179 bnxt_init_rxbd_pages(ring, type); 3180 3181 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) { 3182 bpf_prog_add(bp->xdp_prog, 1); 3183 rxr->xdp_prog = bp->xdp_prog; 3184 } 3185 prod = rxr->rx_prod; 3186 for (i = 0; i < bp->rx_ring_size; i++) { 3187 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) { 3188 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n", 3189 ring_nr, i, bp->rx_ring_size); 3190 break; 3191 } 3192 prod = NEXT_RX(prod); 3193 } 3194 rxr->rx_prod = prod; 3195 ring->fw_ring_id = INVALID_HW_RING_ID; 3196 3197 ring = &rxr->rx_agg_ring_struct; 3198 ring->fw_ring_id = INVALID_HW_RING_ID; 3199 3200 if (!(bp->flags & BNXT_FLAG_AGG_RINGS)) 3201 return 0; 3202 3203 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) | 3204 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP; 3205 3206 bnxt_init_rxbd_pages(ring, type); 3207 3208 prod = rxr->rx_agg_prod; 3209 for (i = 0; i < bp->rx_agg_ring_size; i++) { 3210 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) { 3211 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n", 3212 ring_nr, i, bp->rx_ring_size); 3213 break; 3214 } 3215 prod = NEXT_RX_AGG(prod); 3216 } 3217 rxr->rx_agg_prod = prod; 3218 3219 if (bp->flags & BNXT_FLAG_TPA) { 3220 if (rxr->rx_tpa) { 3221 u8 *data; 3222 dma_addr_t mapping; 3223 3224 for (i = 0; i < bp->max_tpa; i++) { 3225 data = __bnxt_alloc_rx_data(bp, &mapping, 3226 GFP_KERNEL); 3227 if (!data) 3228 return -ENOMEM; 3229 3230 rxr->rx_tpa[i].data = data; 3231 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset; 3232 rxr->rx_tpa[i].mapping = mapping; 3233 } 3234 } else { 3235 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n"); 3236 return -ENOMEM; 3237 } 3238 } 3239 3240 return 0; 3241 } 3242 3243 static void bnxt_init_cp_rings(struct bnxt *bp) 3244 { 3245 int i, j; 3246 3247 for (i = 0; i < bp->cp_nr_rings; i++) { 3248 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 3249 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 3250 3251 ring->fw_ring_id = INVALID_HW_RING_ID; 3252 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; 3253 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; 3254 for (j = 0; j < 2; j++) { 3255 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 3256 3257 if (!cpr2) 3258 continue; 3259 3260 ring = &cpr2->cp_ring_struct; 3261 ring->fw_ring_id = INVALID_HW_RING_ID; 3262 cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; 3263 cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; 3264 } 3265 } 3266 } 3267 3268 static int bnxt_init_rx_rings(struct bnxt *bp) 3269 { 3270 int i, rc = 0; 3271 3272 if (BNXT_RX_PAGE_MODE(bp)) { 3273 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM; 3274 bp->rx_dma_offset = XDP_PACKET_HEADROOM; 3275 } else { 3276 bp->rx_offset = BNXT_RX_OFFSET; 3277 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET; 3278 } 3279 3280 for (i = 0; i < bp->rx_nr_rings; i++) { 3281 rc = bnxt_init_one_rx_ring(bp, i); 3282 if (rc) 3283 break; 3284 } 3285 3286 return rc; 3287 } 3288 3289 static int bnxt_init_tx_rings(struct bnxt *bp) 3290 { 3291 u16 i; 3292 3293 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2, 3294 MAX_SKB_FRAGS + 1); 3295 3296 for (i = 0; i < bp->tx_nr_rings; i++) { 3297 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 3298 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 3299 3300 ring->fw_ring_id = INVALID_HW_RING_ID; 3301 } 3302 3303 return 0; 3304 } 3305 3306 static void bnxt_free_ring_grps(struct bnxt *bp) 3307 { 3308 kfree(bp->grp_info); 3309 bp->grp_info = NULL; 3310 } 3311 3312 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init) 3313 { 3314 int i; 3315 3316 if (irq_re_init) { 3317 bp->grp_info = kcalloc(bp->cp_nr_rings, 3318 sizeof(struct bnxt_ring_grp_info), 3319 GFP_KERNEL); 3320 if (!bp->grp_info) 3321 return -ENOMEM; 3322 } 3323 for (i = 0; i < bp->cp_nr_rings; i++) { 3324 if (irq_re_init) 3325 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID; 3326 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 3327 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID; 3328 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID; 3329 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 3330 } 3331 return 0; 3332 } 3333 3334 static void bnxt_free_vnics(struct bnxt *bp) 3335 { 3336 kfree(bp->vnic_info); 3337 bp->vnic_info = NULL; 3338 bp->nr_vnics = 0; 3339 } 3340 3341 static int bnxt_alloc_vnics(struct bnxt *bp) 3342 { 3343 int num_vnics = 1; 3344 3345 #ifdef CONFIG_RFS_ACCEL 3346 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS) 3347 num_vnics += bp->rx_nr_rings; 3348 #endif 3349 3350 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 3351 num_vnics++; 3352 3353 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info), 3354 GFP_KERNEL); 3355 if (!bp->vnic_info) 3356 return -ENOMEM; 3357 3358 bp->nr_vnics = num_vnics; 3359 return 0; 3360 } 3361 3362 static void bnxt_init_vnics(struct bnxt *bp) 3363 { 3364 int i; 3365 3366 for (i = 0; i < bp->nr_vnics; i++) { 3367 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3368 int j; 3369 3370 vnic->fw_vnic_id = INVALID_HW_RING_ID; 3371 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) 3372 vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID; 3373 3374 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID; 3375 3376 if (bp->vnic_info[i].rss_hash_key) { 3377 if (i == 0) 3378 prandom_bytes(vnic->rss_hash_key, 3379 HW_HASH_KEY_SIZE); 3380 else 3381 memcpy(vnic->rss_hash_key, 3382 bp->vnic_info[0].rss_hash_key, 3383 HW_HASH_KEY_SIZE); 3384 } 3385 } 3386 } 3387 3388 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg) 3389 { 3390 int pages; 3391 3392 pages = ring_size / desc_per_pg; 3393 3394 if (!pages) 3395 return 1; 3396 3397 pages++; 3398 3399 while (pages & (pages - 1)) 3400 pages++; 3401 3402 return pages; 3403 } 3404 3405 void bnxt_set_tpa_flags(struct bnxt *bp) 3406 { 3407 bp->flags &= ~BNXT_FLAG_TPA; 3408 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 3409 return; 3410 if (bp->dev->features & NETIF_F_LRO) 3411 bp->flags |= BNXT_FLAG_LRO; 3412 else if (bp->dev->features & NETIF_F_GRO_HW) 3413 bp->flags |= BNXT_FLAG_GRO; 3414 } 3415 3416 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must 3417 * be set on entry. 3418 */ 3419 void bnxt_set_ring_params(struct bnxt *bp) 3420 { 3421 u32 ring_size, rx_size, rx_space; 3422 u32 agg_factor = 0, agg_ring_size = 0; 3423 3424 /* 8 for CRC and VLAN */ 3425 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8); 3426 3427 rx_space = rx_size + NET_SKB_PAD + 3428 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 3429 3430 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH; 3431 ring_size = bp->rx_ring_size; 3432 bp->rx_agg_ring_size = 0; 3433 bp->rx_agg_nr_pages = 0; 3434 3435 if (bp->flags & BNXT_FLAG_TPA) 3436 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE); 3437 3438 bp->flags &= ~BNXT_FLAG_JUMBO; 3439 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) { 3440 u32 jumbo_factor; 3441 3442 bp->flags |= BNXT_FLAG_JUMBO; 3443 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; 3444 if (jumbo_factor > agg_factor) 3445 agg_factor = jumbo_factor; 3446 } 3447 agg_ring_size = ring_size * agg_factor; 3448 3449 if (agg_ring_size) { 3450 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size, 3451 RX_DESC_CNT); 3452 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) { 3453 u32 tmp = agg_ring_size; 3454 3455 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES; 3456 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1; 3457 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n", 3458 tmp, agg_ring_size); 3459 } 3460 bp->rx_agg_ring_size = agg_ring_size; 3461 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1; 3462 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN); 3463 rx_space = rx_size + NET_SKB_PAD + 3464 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 3465 } 3466 3467 bp->rx_buf_use_size = rx_size; 3468 bp->rx_buf_size = rx_space; 3469 3470 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT); 3471 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1; 3472 3473 ring_size = bp->tx_ring_size; 3474 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT); 3475 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1; 3476 3477 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size; 3478 bp->cp_ring_size = ring_size; 3479 3480 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT); 3481 if (bp->cp_nr_pages > MAX_CP_PAGES) { 3482 bp->cp_nr_pages = MAX_CP_PAGES; 3483 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1; 3484 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n", 3485 ring_size, bp->cp_ring_size); 3486 } 3487 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT; 3488 bp->cp_ring_mask = bp->cp_bit - 1; 3489 } 3490 3491 /* Changing allocation mode of RX rings. 3492 * TODO: Update when extending xdp_rxq_info to support allocation modes. 3493 */ 3494 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode) 3495 { 3496 if (page_mode) { 3497 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU) 3498 return -EOPNOTSUPP; 3499 bp->dev->max_mtu = 3500 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU); 3501 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 3502 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE; 3503 bp->rx_dir = DMA_BIDIRECTIONAL; 3504 bp->rx_skb_func = bnxt_rx_page_skb; 3505 /* Disable LRO or GRO_HW */ 3506 netdev_update_features(bp->dev); 3507 } else { 3508 bp->dev->max_mtu = bp->max_mtu; 3509 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE; 3510 bp->rx_dir = DMA_FROM_DEVICE; 3511 bp->rx_skb_func = bnxt_rx_skb; 3512 } 3513 return 0; 3514 } 3515 3516 static void bnxt_free_vnic_attributes(struct bnxt *bp) 3517 { 3518 int i; 3519 struct bnxt_vnic_info *vnic; 3520 struct pci_dev *pdev = bp->pdev; 3521 3522 if (!bp->vnic_info) 3523 return; 3524 3525 for (i = 0; i < bp->nr_vnics; i++) { 3526 vnic = &bp->vnic_info[i]; 3527 3528 kfree(vnic->fw_grp_ids); 3529 vnic->fw_grp_ids = NULL; 3530 3531 kfree(vnic->uc_list); 3532 vnic->uc_list = NULL; 3533 3534 if (vnic->mc_list) { 3535 dma_free_coherent(&pdev->dev, vnic->mc_list_size, 3536 vnic->mc_list, vnic->mc_list_mapping); 3537 vnic->mc_list = NULL; 3538 } 3539 3540 if (vnic->rss_table) { 3541 dma_free_coherent(&pdev->dev, PAGE_SIZE, 3542 vnic->rss_table, 3543 vnic->rss_table_dma_addr); 3544 vnic->rss_table = NULL; 3545 } 3546 3547 vnic->rss_hash_key = NULL; 3548 vnic->flags = 0; 3549 } 3550 } 3551 3552 static int bnxt_alloc_vnic_attributes(struct bnxt *bp) 3553 { 3554 int i, rc = 0, size; 3555 struct bnxt_vnic_info *vnic; 3556 struct pci_dev *pdev = bp->pdev; 3557 int max_rings; 3558 3559 for (i = 0; i < bp->nr_vnics; i++) { 3560 vnic = &bp->vnic_info[i]; 3561 3562 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) { 3563 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN; 3564 3565 if (mem_size > 0) { 3566 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL); 3567 if (!vnic->uc_list) { 3568 rc = -ENOMEM; 3569 goto out; 3570 } 3571 } 3572 } 3573 3574 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) { 3575 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN; 3576 vnic->mc_list = 3577 dma_alloc_coherent(&pdev->dev, 3578 vnic->mc_list_size, 3579 &vnic->mc_list_mapping, 3580 GFP_KERNEL); 3581 if (!vnic->mc_list) { 3582 rc = -ENOMEM; 3583 goto out; 3584 } 3585 } 3586 3587 if (bp->flags & BNXT_FLAG_CHIP_P5) 3588 goto vnic_skip_grps; 3589 3590 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 3591 max_rings = bp->rx_nr_rings; 3592 else 3593 max_rings = 1; 3594 3595 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL); 3596 if (!vnic->fw_grp_ids) { 3597 rc = -ENOMEM; 3598 goto out; 3599 } 3600 vnic_skip_grps: 3601 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) && 3602 !(vnic->flags & BNXT_VNIC_RSS_FLAG)) 3603 continue; 3604 3605 /* Allocate rss table and hash key */ 3606 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 3607 &vnic->rss_table_dma_addr, 3608 GFP_KERNEL); 3609 if (!vnic->rss_table) { 3610 rc = -ENOMEM; 3611 goto out; 3612 } 3613 3614 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16)); 3615 3616 vnic->rss_hash_key = ((void *)vnic->rss_table) + size; 3617 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; 3618 } 3619 return 0; 3620 3621 out: 3622 return rc; 3623 } 3624 3625 static void bnxt_free_hwrm_resources(struct bnxt *bp) 3626 { 3627 struct pci_dev *pdev = bp->pdev; 3628 3629 if (bp->hwrm_cmd_resp_addr) { 3630 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr, 3631 bp->hwrm_cmd_resp_dma_addr); 3632 bp->hwrm_cmd_resp_addr = NULL; 3633 } 3634 3635 if (bp->hwrm_cmd_kong_resp_addr) { 3636 dma_free_coherent(&pdev->dev, PAGE_SIZE, 3637 bp->hwrm_cmd_kong_resp_addr, 3638 bp->hwrm_cmd_kong_resp_dma_addr); 3639 bp->hwrm_cmd_kong_resp_addr = NULL; 3640 } 3641 } 3642 3643 static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp) 3644 { 3645 struct pci_dev *pdev = bp->pdev; 3646 3647 if (bp->hwrm_cmd_kong_resp_addr) 3648 return 0; 3649 3650 bp->hwrm_cmd_kong_resp_addr = 3651 dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 3652 &bp->hwrm_cmd_kong_resp_dma_addr, 3653 GFP_KERNEL); 3654 if (!bp->hwrm_cmd_kong_resp_addr) 3655 return -ENOMEM; 3656 3657 return 0; 3658 } 3659 3660 static int bnxt_alloc_hwrm_resources(struct bnxt *bp) 3661 { 3662 struct pci_dev *pdev = bp->pdev; 3663 3664 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 3665 &bp->hwrm_cmd_resp_dma_addr, 3666 GFP_KERNEL); 3667 if (!bp->hwrm_cmd_resp_addr) 3668 return -ENOMEM; 3669 3670 return 0; 3671 } 3672 3673 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp) 3674 { 3675 if (bp->hwrm_short_cmd_req_addr) { 3676 struct pci_dev *pdev = bp->pdev; 3677 3678 dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len, 3679 bp->hwrm_short_cmd_req_addr, 3680 bp->hwrm_short_cmd_req_dma_addr); 3681 bp->hwrm_short_cmd_req_addr = NULL; 3682 } 3683 } 3684 3685 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp) 3686 { 3687 struct pci_dev *pdev = bp->pdev; 3688 3689 if (bp->hwrm_short_cmd_req_addr) 3690 return 0; 3691 3692 bp->hwrm_short_cmd_req_addr = 3693 dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len, 3694 &bp->hwrm_short_cmd_req_dma_addr, 3695 GFP_KERNEL); 3696 if (!bp->hwrm_short_cmd_req_addr) 3697 return -ENOMEM; 3698 3699 return 0; 3700 } 3701 3702 static void bnxt_free_port_stats(struct bnxt *bp) 3703 { 3704 struct pci_dev *pdev = bp->pdev; 3705 3706 bp->flags &= ~BNXT_FLAG_PORT_STATS; 3707 bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT; 3708 3709 if (bp->hw_rx_port_stats) { 3710 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size, 3711 bp->hw_rx_port_stats, 3712 bp->hw_rx_port_stats_map); 3713 bp->hw_rx_port_stats = NULL; 3714 } 3715 3716 if (bp->hw_tx_port_stats_ext) { 3717 dma_free_coherent(&pdev->dev, sizeof(struct tx_port_stats_ext), 3718 bp->hw_tx_port_stats_ext, 3719 bp->hw_tx_port_stats_ext_map); 3720 bp->hw_tx_port_stats_ext = NULL; 3721 } 3722 3723 if (bp->hw_rx_port_stats_ext) { 3724 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext), 3725 bp->hw_rx_port_stats_ext, 3726 bp->hw_rx_port_stats_ext_map); 3727 bp->hw_rx_port_stats_ext = NULL; 3728 } 3729 3730 if (bp->hw_pcie_stats) { 3731 dma_free_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats), 3732 bp->hw_pcie_stats, bp->hw_pcie_stats_map); 3733 bp->hw_pcie_stats = NULL; 3734 } 3735 } 3736 3737 static void bnxt_free_ring_stats(struct bnxt *bp) 3738 { 3739 struct pci_dev *pdev = bp->pdev; 3740 int size, i; 3741 3742 if (!bp->bnapi) 3743 return; 3744 3745 size = bp->hw_ring_stats_size; 3746 3747 for (i = 0; i < bp->cp_nr_rings; i++) { 3748 struct bnxt_napi *bnapi = bp->bnapi[i]; 3749 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3750 3751 if (cpr->hw_stats) { 3752 dma_free_coherent(&pdev->dev, size, cpr->hw_stats, 3753 cpr->hw_stats_map); 3754 cpr->hw_stats = NULL; 3755 } 3756 } 3757 } 3758 3759 static int bnxt_alloc_stats(struct bnxt *bp) 3760 { 3761 u32 size, i; 3762 struct pci_dev *pdev = bp->pdev; 3763 3764 size = bp->hw_ring_stats_size; 3765 3766 for (i = 0; i < bp->cp_nr_rings; i++) { 3767 struct bnxt_napi *bnapi = bp->bnapi[i]; 3768 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3769 3770 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size, 3771 &cpr->hw_stats_map, 3772 GFP_KERNEL); 3773 if (!cpr->hw_stats) 3774 return -ENOMEM; 3775 3776 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 3777 } 3778 3779 if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700) 3780 return 0; 3781 3782 if (bp->hw_rx_port_stats) 3783 goto alloc_ext_stats; 3784 3785 bp->hw_port_stats_size = sizeof(struct rx_port_stats) + 3786 sizeof(struct tx_port_stats) + 1024; 3787 3788 bp->hw_rx_port_stats = 3789 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size, 3790 &bp->hw_rx_port_stats_map, 3791 GFP_KERNEL); 3792 if (!bp->hw_rx_port_stats) 3793 return -ENOMEM; 3794 3795 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) + 512; 3796 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map + 3797 sizeof(struct rx_port_stats) + 512; 3798 bp->flags |= BNXT_FLAG_PORT_STATS; 3799 3800 alloc_ext_stats: 3801 /* Display extended statistics only if FW supports it */ 3802 if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900) 3803 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) 3804 return 0; 3805 3806 if (bp->hw_rx_port_stats_ext) 3807 goto alloc_tx_ext_stats; 3808 3809 bp->hw_rx_port_stats_ext = 3810 dma_alloc_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext), 3811 &bp->hw_rx_port_stats_ext_map, GFP_KERNEL); 3812 if (!bp->hw_rx_port_stats_ext) 3813 return 0; 3814 3815 alloc_tx_ext_stats: 3816 if (bp->hw_tx_port_stats_ext) 3817 goto alloc_pcie_stats; 3818 3819 if (bp->hwrm_spec_code >= 0x10902 || 3820 (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) { 3821 bp->hw_tx_port_stats_ext = 3822 dma_alloc_coherent(&pdev->dev, 3823 sizeof(struct tx_port_stats_ext), 3824 &bp->hw_tx_port_stats_ext_map, 3825 GFP_KERNEL); 3826 } 3827 bp->flags |= BNXT_FLAG_PORT_STATS_EXT; 3828 3829 alloc_pcie_stats: 3830 if (bp->hw_pcie_stats || 3831 !(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 3832 return 0; 3833 3834 bp->hw_pcie_stats = 3835 dma_alloc_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats), 3836 &bp->hw_pcie_stats_map, GFP_KERNEL); 3837 if (!bp->hw_pcie_stats) 3838 return 0; 3839 3840 bp->flags |= BNXT_FLAG_PCIE_STATS; 3841 return 0; 3842 } 3843 3844 static void bnxt_clear_ring_indices(struct bnxt *bp) 3845 { 3846 int i; 3847 3848 if (!bp->bnapi) 3849 return; 3850 3851 for (i = 0; i < bp->cp_nr_rings; i++) { 3852 struct bnxt_napi *bnapi = bp->bnapi[i]; 3853 struct bnxt_cp_ring_info *cpr; 3854 struct bnxt_rx_ring_info *rxr; 3855 struct bnxt_tx_ring_info *txr; 3856 3857 if (!bnapi) 3858 continue; 3859 3860 cpr = &bnapi->cp_ring; 3861 cpr->cp_raw_cons = 0; 3862 3863 txr = bnapi->tx_ring; 3864 if (txr) { 3865 txr->tx_prod = 0; 3866 txr->tx_cons = 0; 3867 } 3868 3869 rxr = bnapi->rx_ring; 3870 if (rxr) { 3871 rxr->rx_prod = 0; 3872 rxr->rx_agg_prod = 0; 3873 rxr->rx_sw_agg_prod = 0; 3874 rxr->rx_next_cons = 0; 3875 } 3876 } 3877 } 3878 3879 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit) 3880 { 3881 #ifdef CONFIG_RFS_ACCEL 3882 int i; 3883 3884 /* Under rtnl_lock and all our NAPIs have been disabled. It's 3885 * safe to delete the hash table. 3886 */ 3887 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 3888 struct hlist_head *head; 3889 struct hlist_node *tmp; 3890 struct bnxt_ntuple_filter *fltr; 3891 3892 head = &bp->ntp_fltr_hash_tbl[i]; 3893 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 3894 hlist_del(&fltr->hash); 3895 kfree(fltr); 3896 } 3897 } 3898 if (irq_reinit) { 3899 kfree(bp->ntp_fltr_bmap); 3900 bp->ntp_fltr_bmap = NULL; 3901 } 3902 bp->ntp_fltr_count = 0; 3903 #endif 3904 } 3905 3906 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp) 3907 { 3908 #ifdef CONFIG_RFS_ACCEL 3909 int i, rc = 0; 3910 3911 if (!(bp->flags & BNXT_FLAG_RFS)) 3912 return 0; 3913 3914 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) 3915 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]); 3916 3917 bp->ntp_fltr_count = 0; 3918 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR), 3919 sizeof(long), 3920 GFP_KERNEL); 3921 3922 if (!bp->ntp_fltr_bmap) 3923 rc = -ENOMEM; 3924 3925 return rc; 3926 #else 3927 return 0; 3928 #endif 3929 } 3930 3931 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init) 3932 { 3933 bnxt_free_vnic_attributes(bp); 3934 bnxt_free_tx_rings(bp); 3935 bnxt_free_rx_rings(bp); 3936 bnxt_free_cp_rings(bp); 3937 bnxt_free_ntp_fltrs(bp, irq_re_init); 3938 if (irq_re_init) { 3939 bnxt_free_ring_stats(bp); 3940 bnxt_free_ring_grps(bp); 3941 bnxt_free_vnics(bp); 3942 kfree(bp->tx_ring_map); 3943 bp->tx_ring_map = NULL; 3944 kfree(bp->tx_ring); 3945 bp->tx_ring = NULL; 3946 kfree(bp->rx_ring); 3947 bp->rx_ring = NULL; 3948 kfree(bp->bnapi); 3949 bp->bnapi = NULL; 3950 } else { 3951 bnxt_clear_ring_indices(bp); 3952 } 3953 } 3954 3955 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init) 3956 { 3957 int i, j, rc, size, arr_size; 3958 void *bnapi; 3959 3960 if (irq_re_init) { 3961 /* Allocate bnapi mem pointer array and mem block for 3962 * all queues 3963 */ 3964 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) * 3965 bp->cp_nr_rings); 3966 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi)); 3967 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL); 3968 if (!bnapi) 3969 return -ENOMEM; 3970 3971 bp->bnapi = bnapi; 3972 bnapi += arr_size; 3973 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) { 3974 bp->bnapi[i] = bnapi; 3975 bp->bnapi[i]->index = i; 3976 bp->bnapi[i]->bp = bp; 3977 if (bp->flags & BNXT_FLAG_CHIP_P5) { 3978 struct bnxt_cp_ring_info *cpr = 3979 &bp->bnapi[i]->cp_ring; 3980 3981 cpr->cp_ring_struct.ring_mem.flags = 3982 BNXT_RMEM_RING_PTE_FLAG; 3983 } 3984 } 3985 3986 bp->rx_ring = kcalloc(bp->rx_nr_rings, 3987 sizeof(struct bnxt_rx_ring_info), 3988 GFP_KERNEL); 3989 if (!bp->rx_ring) 3990 return -ENOMEM; 3991 3992 for (i = 0; i < bp->rx_nr_rings; i++) { 3993 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 3994 3995 if (bp->flags & BNXT_FLAG_CHIP_P5) { 3996 rxr->rx_ring_struct.ring_mem.flags = 3997 BNXT_RMEM_RING_PTE_FLAG; 3998 rxr->rx_agg_ring_struct.ring_mem.flags = 3999 BNXT_RMEM_RING_PTE_FLAG; 4000 } 4001 rxr->bnapi = bp->bnapi[i]; 4002 bp->bnapi[i]->rx_ring = &bp->rx_ring[i]; 4003 } 4004 4005 bp->tx_ring = kcalloc(bp->tx_nr_rings, 4006 sizeof(struct bnxt_tx_ring_info), 4007 GFP_KERNEL); 4008 if (!bp->tx_ring) 4009 return -ENOMEM; 4010 4011 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16), 4012 GFP_KERNEL); 4013 4014 if (!bp->tx_ring_map) 4015 return -ENOMEM; 4016 4017 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 4018 j = 0; 4019 else 4020 j = bp->rx_nr_rings; 4021 4022 for (i = 0; i < bp->tx_nr_rings; i++, j++) { 4023 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 4024 4025 if (bp->flags & BNXT_FLAG_CHIP_P5) 4026 txr->tx_ring_struct.ring_mem.flags = 4027 BNXT_RMEM_RING_PTE_FLAG; 4028 txr->bnapi = bp->bnapi[j]; 4029 bp->bnapi[j]->tx_ring = txr; 4030 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i; 4031 if (i >= bp->tx_nr_rings_xdp) { 4032 txr->txq_index = i - bp->tx_nr_rings_xdp; 4033 bp->bnapi[j]->tx_int = bnxt_tx_int; 4034 } else { 4035 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP; 4036 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp; 4037 } 4038 } 4039 4040 rc = bnxt_alloc_stats(bp); 4041 if (rc) 4042 goto alloc_mem_err; 4043 4044 rc = bnxt_alloc_ntp_fltrs(bp); 4045 if (rc) 4046 goto alloc_mem_err; 4047 4048 rc = bnxt_alloc_vnics(bp); 4049 if (rc) 4050 goto alloc_mem_err; 4051 } 4052 4053 bnxt_init_ring_struct(bp); 4054 4055 rc = bnxt_alloc_rx_rings(bp); 4056 if (rc) 4057 goto alloc_mem_err; 4058 4059 rc = bnxt_alloc_tx_rings(bp); 4060 if (rc) 4061 goto alloc_mem_err; 4062 4063 rc = bnxt_alloc_cp_rings(bp); 4064 if (rc) 4065 goto alloc_mem_err; 4066 4067 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG | 4068 BNXT_VNIC_UCAST_FLAG; 4069 rc = bnxt_alloc_vnic_attributes(bp); 4070 if (rc) 4071 goto alloc_mem_err; 4072 return 0; 4073 4074 alloc_mem_err: 4075 bnxt_free_mem(bp, true); 4076 return rc; 4077 } 4078 4079 static void bnxt_disable_int(struct bnxt *bp) 4080 { 4081 int i; 4082 4083 if (!bp->bnapi) 4084 return; 4085 4086 for (i = 0; i < bp->cp_nr_rings; i++) { 4087 struct bnxt_napi *bnapi = bp->bnapi[i]; 4088 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4089 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 4090 4091 if (ring->fw_ring_id != INVALID_HW_RING_ID) 4092 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); 4093 } 4094 } 4095 4096 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n) 4097 { 4098 struct bnxt_napi *bnapi = bp->bnapi[n]; 4099 struct bnxt_cp_ring_info *cpr; 4100 4101 cpr = &bnapi->cp_ring; 4102 return cpr->cp_ring_struct.map_idx; 4103 } 4104 4105 static void bnxt_disable_int_sync(struct bnxt *bp) 4106 { 4107 int i; 4108 4109 atomic_inc(&bp->intr_sem); 4110 4111 bnxt_disable_int(bp); 4112 for (i = 0; i < bp->cp_nr_rings; i++) { 4113 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 4114 4115 synchronize_irq(bp->irq_tbl[map_idx].vector); 4116 } 4117 } 4118 4119 static void bnxt_enable_int(struct bnxt *bp) 4120 { 4121 int i; 4122 4123 atomic_set(&bp->intr_sem, 0); 4124 for (i = 0; i < bp->cp_nr_rings; i++) { 4125 struct bnxt_napi *bnapi = bp->bnapi[i]; 4126 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4127 4128 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons); 4129 } 4130 } 4131 4132 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type, 4133 u16 cmpl_ring, u16 target_id) 4134 { 4135 struct input *req = request; 4136 4137 req->req_type = cpu_to_le16(req_type); 4138 req->cmpl_ring = cpu_to_le16(cmpl_ring); 4139 req->target_id = cpu_to_le16(target_id); 4140 if (bnxt_kong_hwrm_message(bp, req)) 4141 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr); 4142 else 4143 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr); 4144 } 4145 4146 static int bnxt_hwrm_to_stderr(u32 hwrm_err) 4147 { 4148 switch (hwrm_err) { 4149 case HWRM_ERR_CODE_SUCCESS: 4150 return 0; 4151 case HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED: 4152 return -EACCES; 4153 case HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR: 4154 return -ENOSPC; 4155 case HWRM_ERR_CODE_INVALID_PARAMS: 4156 case HWRM_ERR_CODE_INVALID_FLAGS: 4157 case HWRM_ERR_CODE_INVALID_ENABLES: 4158 case HWRM_ERR_CODE_UNSUPPORTED_TLV: 4159 case HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR: 4160 return -EINVAL; 4161 case HWRM_ERR_CODE_NO_BUFFER: 4162 return -ENOMEM; 4163 case HWRM_ERR_CODE_HOT_RESET_PROGRESS: 4164 case HWRM_ERR_CODE_BUSY: 4165 return -EAGAIN; 4166 case HWRM_ERR_CODE_CMD_NOT_SUPPORTED: 4167 return -EOPNOTSUPP; 4168 default: 4169 return -EIO; 4170 } 4171 } 4172 4173 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len, 4174 int timeout, bool silent) 4175 { 4176 int i, intr_process, rc, tmo_count; 4177 struct input *req = msg; 4178 u32 *data = msg; 4179 __le32 *resp_len; 4180 u8 *valid; 4181 u16 cp_ring_id, len = 0; 4182 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr; 4183 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN; 4184 struct hwrm_short_input short_input = {0}; 4185 u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER; 4186 u8 *resp_addr = (u8 *)bp->hwrm_cmd_resp_addr; 4187 u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM; 4188 u16 dst = BNXT_HWRM_CHNL_CHIMP; 4189 4190 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 4191 return -EBUSY; 4192 4193 if (msg_len > BNXT_HWRM_MAX_REQ_LEN) { 4194 if (msg_len > bp->hwrm_max_ext_req_len || 4195 !bp->hwrm_short_cmd_req_addr) 4196 return -EINVAL; 4197 } 4198 4199 if (bnxt_hwrm_kong_chnl(bp, req)) { 4200 dst = BNXT_HWRM_CHNL_KONG; 4201 bar_offset = BNXT_GRCPF_REG_KONG_COMM; 4202 doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER; 4203 resp = bp->hwrm_cmd_kong_resp_addr; 4204 resp_addr = (u8 *)bp->hwrm_cmd_kong_resp_addr; 4205 } 4206 4207 memset(resp, 0, PAGE_SIZE); 4208 cp_ring_id = le16_to_cpu(req->cmpl_ring); 4209 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1; 4210 4211 req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst)); 4212 /* currently supports only one outstanding message */ 4213 if (intr_process) 4214 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id); 4215 4216 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) || 4217 msg_len > BNXT_HWRM_MAX_REQ_LEN) { 4218 void *short_cmd_req = bp->hwrm_short_cmd_req_addr; 4219 u16 max_msg_len; 4220 4221 /* Set boundary for maximum extended request length for short 4222 * cmd format. If passed up from device use the max supported 4223 * internal req length. 4224 */ 4225 max_msg_len = bp->hwrm_max_ext_req_len; 4226 4227 memcpy(short_cmd_req, req, msg_len); 4228 if (msg_len < max_msg_len) 4229 memset(short_cmd_req + msg_len, 0, 4230 max_msg_len - msg_len); 4231 4232 short_input.req_type = req->req_type; 4233 short_input.signature = 4234 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD); 4235 short_input.size = cpu_to_le16(msg_len); 4236 short_input.req_addr = 4237 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr); 4238 4239 data = (u32 *)&short_input; 4240 msg_len = sizeof(short_input); 4241 4242 /* Sync memory write before updating doorbell */ 4243 wmb(); 4244 4245 max_req_len = BNXT_HWRM_SHORT_REQ_LEN; 4246 } 4247 4248 /* Write request msg to hwrm channel */ 4249 __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4); 4250 4251 for (i = msg_len; i < max_req_len; i += 4) 4252 writel(0, bp->bar0 + bar_offset + i); 4253 4254 /* Ring channel doorbell */ 4255 writel(1, bp->bar0 + doorbell_offset); 4256 4257 if (!pci_is_enabled(bp->pdev)) 4258 return 0; 4259 4260 if (!timeout) 4261 timeout = DFLT_HWRM_CMD_TIMEOUT; 4262 /* convert timeout to usec */ 4263 timeout *= 1000; 4264 4265 i = 0; 4266 /* Short timeout for the first few iterations: 4267 * number of loops = number of loops for short timeout + 4268 * number of loops for standard timeout. 4269 */ 4270 tmo_count = HWRM_SHORT_TIMEOUT_COUNTER; 4271 timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER; 4272 tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT); 4273 resp_len = (__le32 *)(resp_addr + HWRM_RESP_LEN_OFFSET); 4274 4275 if (intr_process) { 4276 u16 seq_id = bp->hwrm_intr_seq_id; 4277 4278 /* Wait until hwrm response cmpl interrupt is processed */ 4279 while (bp->hwrm_intr_seq_id != (u16)~seq_id && 4280 i++ < tmo_count) { 4281 /* Abort the wait for completion if the FW health 4282 * check has failed. 4283 */ 4284 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 4285 return -EBUSY; 4286 /* on first few passes, just barely sleep */ 4287 if (i < HWRM_SHORT_TIMEOUT_COUNTER) 4288 usleep_range(HWRM_SHORT_MIN_TIMEOUT, 4289 HWRM_SHORT_MAX_TIMEOUT); 4290 else 4291 usleep_range(HWRM_MIN_TIMEOUT, 4292 HWRM_MAX_TIMEOUT); 4293 } 4294 4295 if (bp->hwrm_intr_seq_id != (u16)~seq_id) { 4296 if (!silent) 4297 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n", 4298 le16_to_cpu(req->req_type)); 4299 return -EBUSY; 4300 } 4301 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >> 4302 HWRM_RESP_LEN_SFT; 4303 valid = resp_addr + len - 1; 4304 } else { 4305 int j; 4306 4307 /* Check if response len is updated */ 4308 for (i = 0; i < tmo_count; i++) { 4309 /* Abort the wait for completion if the FW health 4310 * check has failed. 4311 */ 4312 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 4313 return -EBUSY; 4314 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >> 4315 HWRM_RESP_LEN_SFT; 4316 if (len) 4317 break; 4318 /* on first few passes, just barely sleep */ 4319 if (i < HWRM_SHORT_TIMEOUT_COUNTER) 4320 usleep_range(HWRM_SHORT_MIN_TIMEOUT, 4321 HWRM_SHORT_MAX_TIMEOUT); 4322 else 4323 usleep_range(HWRM_MIN_TIMEOUT, 4324 HWRM_MAX_TIMEOUT); 4325 } 4326 4327 if (i >= tmo_count) { 4328 if (!silent) 4329 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n", 4330 HWRM_TOTAL_TIMEOUT(i), 4331 le16_to_cpu(req->req_type), 4332 le16_to_cpu(req->seq_id), len); 4333 return -EBUSY; 4334 } 4335 4336 /* Last byte of resp contains valid bit */ 4337 valid = resp_addr + len - 1; 4338 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) { 4339 /* make sure we read from updated DMA memory */ 4340 dma_rmb(); 4341 if (*valid) 4342 break; 4343 usleep_range(1, 5); 4344 } 4345 4346 if (j >= HWRM_VALID_BIT_DELAY_USEC) { 4347 if (!silent) 4348 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n", 4349 HWRM_TOTAL_TIMEOUT(i), 4350 le16_to_cpu(req->req_type), 4351 le16_to_cpu(req->seq_id), len, 4352 *valid); 4353 return -EBUSY; 4354 } 4355 } 4356 4357 /* Zero valid bit for compatibility. Valid bit in an older spec 4358 * may become a new field in a newer spec. We must make sure that 4359 * a new field not implemented by old spec will read zero. 4360 */ 4361 *valid = 0; 4362 rc = le16_to_cpu(resp->error_code); 4363 if (rc && !silent) 4364 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n", 4365 le16_to_cpu(resp->req_type), 4366 le16_to_cpu(resp->seq_id), rc); 4367 return bnxt_hwrm_to_stderr(rc); 4368 } 4369 4370 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 4371 { 4372 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false); 4373 } 4374 4375 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, 4376 int timeout) 4377 { 4378 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); 4379 } 4380 4381 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 4382 { 4383 int rc; 4384 4385 mutex_lock(&bp->hwrm_cmd_lock); 4386 rc = _hwrm_send_message(bp, msg, msg_len, timeout); 4387 mutex_unlock(&bp->hwrm_cmd_lock); 4388 return rc; 4389 } 4390 4391 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, 4392 int timeout) 4393 { 4394 int rc; 4395 4396 mutex_lock(&bp->hwrm_cmd_lock); 4397 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); 4398 mutex_unlock(&bp->hwrm_cmd_lock); 4399 return rc; 4400 } 4401 4402 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap, int bmap_size, 4403 bool async_only) 4404 { 4405 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr; 4406 struct hwrm_func_drv_rgtr_input req = {0}; 4407 DECLARE_BITMAP(async_events_bmap, 256); 4408 u32 *events = (u32 *)async_events_bmap; 4409 u32 flags; 4410 int rc, i; 4411 4412 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); 4413 4414 req.enables = 4415 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE | 4416 FUNC_DRV_RGTR_REQ_ENABLES_VER | 4417 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); 4418 4419 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX); 4420 flags = FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE; 4421 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 4422 flags |= FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT; 4423 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) 4424 flags |= FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT | 4425 FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT; 4426 req.flags = cpu_to_le32(flags); 4427 req.ver_maj_8b = DRV_VER_MAJ; 4428 req.ver_min_8b = DRV_VER_MIN; 4429 req.ver_upd_8b = DRV_VER_UPD; 4430 req.ver_maj = cpu_to_le16(DRV_VER_MAJ); 4431 req.ver_min = cpu_to_le16(DRV_VER_MIN); 4432 req.ver_upd = cpu_to_le16(DRV_VER_UPD); 4433 4434 if (BNXT_PF(bp)) { 4435 u32 data[8]; 4436 int i; 4437 4438 memset(data, 0, sizeof(data)); 4439 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) { 4440 u16 cmd = bnxt_vf_req_snif[i]; 4441 unsigned int bit, idx; 4442 4443 idx = cmd / 32; 4444 bit = cmd % 32; 4445 data[idx] |= 1 << bit; 4446 } 4447 4448 for (i = 0; i < 8; i++) 4449 req.vf_req_fwd[i] = cpu_to_le32(data[i]); 4450 4451 req.enables |= 4452 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD); 4453 } 4454 4455 if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE) 4456 req.flags |= cpu_to_le32( 4457 FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE); 4458 4459 memset(async_events_bmap, 0, sizeof(async_events_bmap)); 4460 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) { 4461 u16 event_id = bnxt_async_events_arr[i]; 4462 4463 if (event_id == ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY && 4464 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 4465 continue; 4466 __set_bit(bnxt_async_events_arr[i], async_events_bmap); 4467 } 4468 if (bmap && bmap_size) { 4469 for (i = 0; i < bmap_size; i++) { 4470 if (test_bit(i, bmap)) 4471 __set_bit(i, async_events_bmap); 4472 } 4473 } 4474 for (i = 0; i < 8; i++) 4475 req.async_event_fwd[i] |= cpu_to_le32(events[i]); 4476 4477 if (async_only) 4478 req.enables = 4479 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); 4480 4481 mutex_lock(&bp->hwrm_cmd_lock); 4482 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4483 if (!rc) { 4484 set_bit(BNXT_STATE_DRV_REGISTERED, &bp->state); 4485 if (resp->flags & 4486 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED)) 4487 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE; 4488 } 4489 mutex_unlock(&bp->hwrm_cmd_lock); 4490 return rc; 4491 } 4492 4493 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp) 4494 { 4495 struct hwrm_func_drv_unrgtr_input req = {0}; 4496 4497 if (!test_and_clear_bit(BNXT_STATE_DRV_REGISTERED, &bp->state)) 4498 return 0; 4499 4500 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1); 4501 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4502 } 4503 4504 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type) 4505 { 4506 u32 rc = 0; 4507 struct hwrm_tunnel_dst_port_free_input req = {0}; 4508 4509 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1); 4510 req.tunnel_type = tunnel_type; 4511 4512 switch (tunnel_type) { 4513 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN: 4514 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id; 4515 break; 4516 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE: 4517 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id; 4518 break; 4519 default: 4520 break; 4521 } 4522 4523 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4524 if (rc) 4525 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n", 4526 rc); 4527 return rc; 4528 } 4529 4530 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port, 4531 u8 tunnel_type) 4532 { 4533 u32 rc = 0; 4534 struct hwrm_tunnel_dst_port_alloc_input req = {0}; 4535 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4536 4537 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1); 4538 4539 req.tunnel_type = tunnel_type; 4540 req.tunnel_dst_port_val = port; 4541 4542 mutex_lock(&bp->hwrm_cmd_lock); 4543 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4544 if (rc) { 4545 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n", 4546 rc); 4547 goto err_out; 4548 } 4549 4550 switch (tunnel_type) { 4551 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN: 4552 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id; 4553 break; 4554 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE: 4555 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id; 4556 break; 4557 default: 4558 break; 4559 } 4560 4561 err_out: 4562 mutex_unlock(&bp->hwrm_cmd_lock); 4563 return rc; 4564 } 4565 4566 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id) 4567 { 4568 struct hwrm_cfa_l2_set_rx_mask_input req = {0}; 4569 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4570 4571 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1); 4572 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 4573 4574 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count); 4575 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping); 4576 req.mask = cpu_to_le32(vnic->rx_mask); 4577 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4578 } 4579 4580 #ifdef CONFIG_RFS_ACCEL 4581 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp, 4582 struct bnxt_ntuple_filter *fltr) 4583 { 4584 struct hwrm_cfa_ntuple_filter_free_input req = {0}; 4585 4586 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1); 4587 req.ntuple_filter_id = fltr->filter_id; 4588 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4589 } 4590 4591 #define BNXT_NTP_FLTR_FLAGS \ 4592 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \ 4593 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \ 4594 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \ 4595 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \ 4596 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \ 4597 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \ 4598 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \ 4599 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \ 4600 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \ 4601 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \ 4602 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \ 4603 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \ 4604 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \ 4605 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID) 4606 4607 #define BNXT_NTP_TUNNEL_FLTR_FLAG \ 4608 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 4609 4610 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp, 4611 struct bnxt_ntuple_filter *fltr) 4612 { 4613 struct hwrm_cfa_ntuple_filter_alloc_input req = {0}; 4614 struct hwrm_cfa_ntuple_filter_alloc_output *resp; 4615 struct flow_keys *keys = &fltr->fkeys; 4616 struct bnxt_vnic_info *vnic; 4617 u32 flags = 0; 4618 int rc = 0; 4619 4620 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1); 4621 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx]; 4622 4623 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) { 4624 flags = CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX; 4625 req.dst_id = cpu_to_le16(fltr->rxq); 4626 } else { 4627 vnic = &bp->vnic_info[fltr->rxq + 1]; 4628 req.dst_id = cpu_to_le16(vnic->fw_vnic_id); 4629 } 4630 req.flags = cpu_to_le32(flags); 4631 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS); 4632 4633 req.ethertype = htons(ETH_P_IP); 4634 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN); 4635 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4; 4636 req.ip_protocol = keys->basic.ip_proto; 4637 4638 if (keys->basic.n_proto == htons(ETH_P_IPV6)) { 4639 int i; 4640 4641 req.ethertype = htons(ETH_P_IPV6); 4642 req.ip_addr_type = 4643 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6; 4644 *(struct in6_addr *)&req.src_ipaddr[0] = 4645 keys->addrs.v6addrs.src; 4646 *(struct in6_addr *)&req.dst_ipaddr[0] = 4647 keys->addrs.v6addrs.dst; 4648 for (i = 0; i < 4; i++) { 4649 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 4650 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 4651 } 4652 } else { 4653 req.src_ipaddr[0] = keys->addrs.v4addrs.src; 4654 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 4655 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst; 4656 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 4657 } 4658 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) { 4659 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG); 4660 req.tunnel_type = 4661 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL; 4662 } 4663 4664 req.src_port = keys->ports.src; 4665 req.src_port_mask = cpu_to_be16(0xffff); 4666 req.dst_port = keys->ports.dst; 4667 req.dst_port_mask = cpu_to_be16(0xffff); 4668 4669 mutex_lock(&bp->hwrm_cmd_lock); 4670 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4671 if (!rc) { 4672 resp = bnxt_get_hwrm_resp_addr(bp, &req); 4673 fltr->filter_id = resp->ntuple_filter_id; 4674 } 4675 mutex_unlock(&bp->hwrm_cmd_lock); 4676 return rc; 4677 } 4678 #endif 4679 4680 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx, 4681 u8 *mac_addr) 4682 { 4683 u32 rc = 0; 4684 struct hwrm_cfa_l2_filter_alloc_input req = {0}; 4685 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4686 4687 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1); 4688 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX); 4689 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) 4690 req.flags |= 4691 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST); 4692 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id); 4693 req.enables = 4694 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR | 4695 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID | 4696 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK); 4697 memcpy(req.l2_addr, mac_addr, ETH_ALEN); 4698 req.l2_addr_mask[0] = 0xff; 4699 req.l2_addr_mask[1] = 0xff; 4700 req.l2_addr_mask[2] = 0xff; 4701 req.l2_addr_mask[3] = 0xff; 4702 req.l2_addr_mask[4] = 0xff; 4703 req.l2_addr_mask[5] = 0xff; 4704 4705 mutex_lock(&bp->hwrm_cmd_lock); 4706 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4707 if (!rc) 4708 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] = 4709 resp->l2_filter_id; 4710 mutex_unlock(&bp->hwrm_cmd_lock); 4711 return rc; 4712 } 4713 4714 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp) 4715 { 4716 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */ 4717 int rc = 0; 4718 4719 /* Any associated ntuple filters will also be cleared by firmware. */ 4720 mutex_lock(&bp->hwrm_cmd_lock); 4721 for (i = 0; i < num_of_vnics; i++) { 4722 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 4723 4724 for (j = 0; j < vnic->uc_filter_count; j++) { 4725 struct hwrm_cfa_l2_filter_free_input req = {0}; 4726 4727 bnxt_hwrm_cmd_hdr_init(bp, &req, 4728 HWRM_CFA_L2_FILTER_FREE, -1, -1); 4729 4730 req.l2_filter_id = vnic->fw_l2_filter_id[j]; 4731 4732 rc = _hwrm_send_message(bp, &req, sizeof(req), 4733 HWRM_CMD_TIMEOUT); 4734 } 4735 vnic->uc_filter_count = 0; 4736 } 4737 mutex_unlock(&bp->hwrm_cmd_lock); 4738 4739 return rc; 4740 } 4741 4742 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags) 4743 { 4744 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4745 u16 max_aggs = VNIC_TPA_CFG_REQ_MAX_AGGS_MAX; 4746 struct hwrm_vnic_tpa_cfg_input req = {0}; 4747 4748 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) 4749 return 0; 4750 4751 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1); 4752 4753 if (tpa_flags) { 4754 u16 mss = bp->dev->mtu - 40; 4755 u32 nsegs, n, segs = 0, flags; 4756 4757 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA | 4758 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA | 4759 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE | 4760 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN | 4761 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ; 4762 if (tpa_flags & BNXT_FLAG_GRO) 4763 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO; 4764 4765 req.flags = cpu_to_le32(flags); 4766 4767 req.enables = 4768 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS | 4769 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS | 4770 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN); 4771 4772 /* Number of segs are log2 units, and first packet is not 4773 * included as part of this units. 4774 */ 4775 if (mss <= BNXT_RX_PAGE_SIZE) { 4776 n = BNXT_RX_PAGE_SIZE / mss; 4777 nsegs = (MAX_SKB_FRAGS - 1) * n; 4778 } else { 4779 n = mss / BNXT_RX_PAGE_SIZE; 4780 if (mss & (BNXT_RX_PAGE_SIZE - 1)) 4781 n++; 4782 nsegs = (MAX_SKB_FRAGS - n) / n; 4783 } 4784 4785 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4786 segs = MAX_TPA_SEGS_P5; 4787 max_aggs = bp->max_tpa; 4788 } else { 4789 segs = ilog2(nsegs); 4790 } 4791 req.max_agg_segs = cpu_to_le16(segs); 4792 req.max_aggs = cpu_to_le16(max_aggs); 4793 4794 req.min_agg_len = cpu_to_le32(512); 4795 } 4796 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 4797 4798 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4799 } 4800 4801 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring) 4802 { 4803 struct bnxt_ring_grp_info *grp_info; 4804 4805 grp_info = &bp->grp_info[ring->grp_idx]; 4806 return grp_info->cp_fw_ring_id; 4807 } 4808 4809 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) 4810 { 4811 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4812 struct bnxt_napi *bnapi = rxr->bnapi; 4813 struct bnxt_cp_ring_info *cpr; 4814 4815 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL]; 4816 return cpr->cp_ring_struct.fw_ring_id; 4817 } else { 4818 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct); 4819 } 4820 } 4821 4822 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr) 4823 { 4824 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4825 struct bnxt_napi *bnapi = txr->bnapi; 4826 struct bnxt_cp_ring_info *cpr; 4827 4828 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL]; 4829 return cpr->cp_ring_struct.fw_ring_id; 4830 } else { 4831 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct); 4832 } 4833 } 4834 4835 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss) 4836 { 4837 u32 i, j, max_rings; 4838 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4839 struct hwrm_vnic_rss_cfg_input req = {0}; 4840 4841 if ((bp->flags & BNXT_FLAG_CHIP_P5) || 4842 vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID) 4843 return 0; 4844 4845 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); 4846 if (set_rss) { 4847 req.hash_type = cpu_to_le32(bp->rss_hash_cfg); 4848 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; 4849 if (vnic->flags & BNXT_VNIC_RSS_FLAG) { 4850 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 4851 max_rings = bp->rx_nr_rings - 1; 4852 else 4853 max_rings = bp->rx_nr_rings; 4854 } else { 4855 max_rings = 1; 4856 } 4857 4858 /* Fill the RSS indirection table with ring group ids */ 4859 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) { 4860 if (j == max_rings) 4861 j = 0; 4862 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]); 4863 } 4864 4865 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); 4866 req.hash_key_tbl_addr = 4867 cpu_to_le64(vnic->rss_hash_key_dma_addr); 4868 } 4869 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 4870 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4871 } 4872 4873 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss) 4874 { 4875 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4876 u32 i, j, k, nr_ctxs, max_rings = bp->rx_nr_rings; 4877 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 4878 struct hwrm_vnic_rss_cfg_input req = {0}; 4879 4880 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); 4881 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 4882 if (!set_rss) { 4883 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4884 return 0; 4885 } 4886 req.hash_type = cpu_to_le32(bp->rss_hash_cfg); 4887 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; 4888 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); 4889 req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr); 4890 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64); 4891 for (i = 0, k = 0; i < nr_ctxs; i++) { 4892 __le16 *ring_tbl = vnic->rss_table; 4893 int rc; 4894 4895 req.ring_table_pair_index = i; 4896 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]); 4897 for (j = 0; j < 64; j++) { 4898 u16 ring_id; 4899 4900 ring_id = rxr->rx_ring_struct.fw_ring_id; 4901 *ring_tbl++ = cpu_to_le16(ring_id); 4902 ring_id = bnxt_cp_ring_for_rx(bp, rxr); 4903 *ring_tbl++ = cpu_to_le16(ring_id); 4904 rxr++; 4905 k++; 4906 if (k == max_rings) { 4907 k = 0; 4908 rxr = &bp->rx_ring[0]; 4909 } 4910 } 4911 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4912 if (rc) 4913 return rc; 4914 } 4915 return 0; 4916 } 4917 4918 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id) 4919 { 4920 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4921 struct hwrm_vnic_plcmodes_cfg_input req = {0}; 4922 4923 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1); 4924 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT | 4925 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 | 4926 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6); 4927 req.enables = 4928 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID | 4929 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID); 4930 /* thresholds not implemented in firmware yet */ 4931 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh); 4932 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh); 4933 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 4934 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4935 } 4936 4937 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id, 4938 u16 ctx_idx) 4939 { 4940 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0}; 4941 4942 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1); 4943 req.rss_cos_lb_ctx_id = 4944 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]); 4945 4946 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4947 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID; 4948 } 4949 4950 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp) 4951 { 4952 int i, j; 4953 4954 for (i = 0; i < bp->nr_vnics; i++) { 4955 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 4956 4957 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) { 4958 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID) 4959 bnxt_hwrm_vnic_ctx_free_one(bp, i, j); 4960 } 4961 } 4962 bp->rsscos_nr_ctxs = 0; 4963 } 4964 4965 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx) 4966 { 4967 int rc; 4968 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0}; 4969 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp = 4970 bp->hwrm_cmd_resp_addr; 4971 4972 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1, 4973 -1); 4974 4975 mutex_lock(&bp->hwrm_cmd_lock); 4976 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4977 if (!rc) 4978 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = 4979 le16_to_cpu(resp->rss_cos_lb_ctx_id); 4980 mutex_unlock(&bp->hwrm_cmd_lock); 4981 4982 return rc; 4983 } 4984 4985 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp) 4986 { 4987 if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP) 4988 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE; 4989 return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE; 4990 } 4991 4992 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id) 4993 { 4994 unsigned int ring = 0, grp_idx; 4995 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4996 struct hwrm_vnic_cfg_input req = {0}; 4997 u16 def_vlan = 0; 4998 4999 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1); 5000 5001 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5002 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 5003 5004 req.default_rx_ring_id = 5005 cpu_to_le16(rxr->rx_ring_struct.fw_ring_id); 5006 req.default_cmpl_ring_id = 5007 cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr)); 5008 req.enables = 5009 cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID | 5010 VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID); 5011 goto vnic_mru; 5012 } 5013 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP); 5014 /* Only RSS support for now TBD: COS & LB */ 5015 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) { 5016 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 5017 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 5018 VNIC_CFG_REQ_ENABLES_MRU); 5019 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) { 5020 req.rss_rule = 5021 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]); 5022 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 5023 VNIC_CFG_REQ_ENABLES_MRU); 5024 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE); 5025 } else { 5026 req.rss_rule = cpu_to_le16(0xffff); 5027 } 5028 5029 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && 5030 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) { 5031 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]); 5032 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE); 5033 } else { 5034 req.cos_rule = cpu_to_le16(0xffff); 5035 } 5036 5037 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 5038 ring = 0; 5039 else if (vnic->flags & BNXT_VNIC_RFS_FLAG) 5040 ring = vnic_id - 1; 5041 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp)) 5042 ring = bp->rx_nr_rings - 1; 5043 5044 grp_idx = bp->rx_ring[ring].bnapi->index; 5045 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id); 5046 req.lb_rule = cpu_to_le16(0xffff); 5047 vnic_mru: 5048 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + VLAN_HLEN); 5049 5050 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 5051 #ifdef CONFIG_BNXT_SRIOV 5052 if (BNXT_VF(bp)) 5053 def_vlan = bp->vf.vlan; 5054 #endif 5055 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan) 5056 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE); 5057 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP)) 5058 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp)); 5059 5060 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5061 } 5062 5063 static void bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id) 5064 { 5065 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) { 5066 struct hwrm_vnic_free_input req = {0}; 5067 5068 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1); 5069 req.vnic_id = 5070 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id); 5071 5072 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5073 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID; 5074 } 5075 } 5076 5077 static void bnxt_hwrm_vnic_free(struct bnxt *bp) 5078 { 5079 u16 i; 5080 5081 for (i = 0; i < bp->nr_vnics; i++) 5082 bnxt_hwrm_vnic_free_one(bp, i); 5083 } 5084 5085 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, 5086 unsigned int start_rx_ring_idx, 5087 unsigned int nr_rings) 5088 { 5089 int rc = 0; 5090 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings; 5091 struct hwrm_vnic_alloc_input req = {0}; 5092 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr; 5093 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 5094 5095 if (bp->flags & BNXT_FLAG_CHIP_P5) 5096 goto vnic_no_ring_grps; 5097 5098 /* map ring groups to this vnic */ 5099 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) { 5100 grp_idx = bp->rx_ring[i].bnapi->index; 5101 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) { 5102 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n", 5103 j, nr_rings); 5104 break; 5105 } 5106 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id; 5107 } 5108 5109 vnic_no_ring_grps: 5110 for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++) 5111 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID; 5112 if (vnic_id == 0) 5113 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT); 5114 5115 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1); 5116 5117 mutex_lock(&bp->hwrm_cmd_lock); 5118 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5119 if (!rc) 5120 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id); 5121 mutex_unlock(&bp->hwrm_cmd_lock); 5122 return rc; 5123 } 5124 5125 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp) 5126 { 5127 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 5128 struct hwrm_vnic_qcaps_input req = {0}; 5129 int rc; 5130 5131 bp->hw_ring_stats_size = sizeof(struct ctx_hw_stats); 5132 bp->flags &= ~(BNXT_FLAG_NEW_RSS_CAP | BNXT_FLAG_ROCE_MIRROR_CAP); 5133 if (bp->hwrm_spec_code < 0x10600) 5134 return 0; 5135 5136 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1); 5137 mutex_lock(&bp->hwrm_cmd_lock); 5138 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5139 if (!rc) { 5140 u32 flags = le32_to_cpu(resp->flags); 5141 5142 if (!(bp->flags & BNXT_FLAG_CHIP_P5) && 5143 (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP)) 5144 bp->flags |= BNXT_FLAG_NEW_RSS_CAP; 5145 if (flags & 5146 VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP) 5147 bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP; 5148 bp->max_tpa_v2 = le16_to_cpu(resp->max_aggs_supported); 5149 if (bp->max_tpa_v2) 5150 bp->hw_ring_stats_size = 5151 sizeof(struct ctx_hw_stats_ext); 5152 } 5153 mutex_unlock(&bp->hwrm_cmd_lock); 5154 return rc; 5155 } 5156 5157 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp) 5158 { 5159 u16 i; 5160 u32 rc = 0; 5161 5162 if (bp->flags & BNXT_FLAG_CHIP_P5) 5163 return 0; 5164 5165 mutex_lock(&bp->hwrm_cmd_lock); 5166 for (i = 0; i < bp->rx_nr_rings; i++) { 5167 struct hwrm_ring_grp_alloc_input req = {0}; 5168 struct hwrm_ring_grp_alloc_output *resp = 5169 bp->hwrm_cmd_resp_addr; 5170 unsigned int grp_idx = bp->rx_ring[i].bnapi->index; 5171 5172 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1); 5173 5174 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id); 5175 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id); 5176 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id); 5177 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx); 5178 5179 rc = _hwrm_send_message(bp, &req, sizeof(req), 5180 HWRM_CMD_TIMEOUT); 5181 if (rc) 5182 break; 5183 5184 bp->grp_info[grp_idx].fw_grp_id = 5185 le32_to_cpu(resp->ring_group_id); 5186 } 5187 mutex_unlock(&bp->hwrm_cmd_lock); 5188 return rc; 5189 } 5190 5191 static void bnxt_hwrm_ring_grp_free(struct bnxt *bp) 5192 { 5193 u16 i; 5194 struct hwrm_ring_grp_free_input req = {0}; 5195 5196 if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5)) 5197 return; 5198 5199 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1); 5200 5201 mutex_lock(&bp->hwrm_cmd_lock); 5202 for (i = 0; i < bp->cp_nr_rings; i++) { 5203 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) 5204 continue; 5205 req.ring_group_id = 5206 cpu_to_le32(bp->grp_info[i].fw_grp_id); 5207 5208 _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5209 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 5210 } 5211 mutex_unlock(&bp->hwrm_cmd_lock); 5212 } 5213 5214 static int hwrm_ring_alloc_send_msg(struct bnxt *bp, 5215 struct bnxt_ring_struct *ring, 5216 u32 ring_type, u32 map_index) 5217 { 5218 int rc = 0, err = 0; 5219 struct hwrm_ring_alloc_input req = {0}; 5220 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr; 5221 struct bnxt_ring_mem_info *rmem = &ring->ring_mem; 5222 struct bnxt_ring_grp_info *grp_info; 5223 u16 ring_id; 5224 5225 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1); 5226 5227 req.enables = 0; 5228 if (rmem->nr_pages > 1) { 5229 req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map); 5230 /* Page size is in log2 units */ 5231 req.page_size = BNXT_PAGE_SHIFT; 5232 req.page_tbl_depth = 1; 5233 } else { 5234 req.page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]); 5235 } 5236 req.fbo = 0; 5237 /* Association of ring index with doorbell index and MSIX number */ 5238 req.logical_id = cpu_to_le16(map_index); 5239 5240 switch (ring_type) { 5241 case HWRM_RING_ALLOC_TX: { 5242 struct bnxt_tx_ring_info *txr; 5243 5244 txr = container_of(ring, struct bnxt_tx_ring_info, 5245 tx_ring_struct); 5246 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX; 5247 /* Association of transmit ring with completion ring */ 5248 grp_info = &bp->grp_info[ring->grp_idx]; 5249 req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr)); 5250 req.length = cpu_to_le32(bp->tx_ring_mask + 1); 5251 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 5252 req.queue_id = cpu_to_le16(ring->queue_id); 5253 break; 5254 } 5255 case HWRM_RING_ALLOC_RX: 5256 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 5257 req.length = cpu_to_le32(bp->rx_ring_mask + 1); 5258 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5259 u16 flags = 0; 5260 5261 /* Association of rx ring with stats context */ 5262 grp_info = &bp->grp_info[ring->grp_idx]; 5263 req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size); 5264 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 5265 req.enables |= cpu_to_le32( 5266 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); 5267 if (NET_IP_ALIGN == 2) 5268 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD; 5269 req.flags = cpu_to_le16(flags); 5270 } 5271 break; 5272 case HWRM_RING_ALLOC_AGG: 5273 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5274 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG; 5275 /* Association of agg ring with rx ring */ 5276 grp_info = &bp->grp_info[ring->grp_idx]; 5277 req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id); 5278 req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE); 5279 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 5280 req.enables |= cpu_to_le32( 5281 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID | 5282 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); 5283 } else { 5284 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 5285 } 5286 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1); 5287 break; 5288 case HWRM_RING_ALLOC_CMPL: 5289 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL; 5290 req.length = cpu_to_le32(bp->cp_ring_mask + 1); 5291 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5292 /* Association of cp ring with nq */ 5293 grp_info = &bp->grp_info[map_index]; 5294 req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id); 5295 req.cq_handle = cpu_to_le64(ring->handle); 5296 req.enables |= cpu_to_le32( 5297 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID); 5298 } else if (bp->flags & BNXT_FLAG_USING_MSIX) { 5299 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; 5300 } 5301 break; 5302 case HWRM_RING_ALLOC_NQ: 5303 req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ; 5304 req.length = cpu_to_le32(bp->cp_ring_mask + 1); 5305 if (bp->flags & BNXT_FLAG_USING_MSIX) 5306 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; 5307 break; 5308 default: 5309 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n", 5310 ring_type); 5311 return -1; 5312 } 5313 5314 mutex_lock(&bp->hwrm_cmd_lock); 5315 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5316 err = le16_to_cpu(resp->error_code); 5317 ring_id = le16_to_cpu(resp->ring_id); 5318 mutex_unlock(&bp->hwrm_cmd_lock); 5319 5320 if (rc || err) { 5321 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n", 5322 ring_type, rc, err); 5323 return -EIO; 5324 } 5325 ring->fw_ring_id = ring_id; 5326 return rc; 5327 } 5328 5329 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx) 5330 { 5331 int rc; 5332 5333 if (BNXT_PF(bp)) { 5334 struct hwrm_func_cfg_input req = {0}; 5335 5336 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 5337 req.fid = cpu_to_le16(0xffff); 5338 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 5339 req.async_event_cr = cpu_to_le16(idx); 5340 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5341 } else { 5342 struct hwrm_func_vf_cfg_input req = {0}; 5343 5344 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1); 5345 req.enables = 5346 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 5347 req.async_event_cr = cpu_to_le16(idx); 5348 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5349 } 5350 return rc; 5351 } 5352 5353 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type, 5354 u32 map_idx, u32 xid) 5355 { 5356 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5357 if (BNXT_PF(bp)) 5358 db->doorbell = bp->bar1 + DB_PF_OFFSET_P5; 5359 else 5360 db->doorbell = bp->bar1 + DB_VF_OFFSET_P5; 5361 switch (ring_type) { 5362 case HWRM_RING_ALLOC_TX: 5363 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ; 5364 break; 5365 case HWRM_RING_ALLOC_RX: 5366 case HWRM_RING_ALLOC_AGG: 5367 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ; 5368 break; 5369 case HWRM_RING_ALLOC_CMPL: 5370 db->db_key64 = DBR_PATH_L2; 5371 break; 5372 case HWRM_RING_ALLOC_NQ: 5373 db->db_key64 = DBR_PATH_L2; 5374 break; 5375 } 5376 db->db_key64 |= (u64)xid << DBR_XID_SFT; 5377 } else { 5378 db->doorbell = bp->bar1 + map_idx * 0x80; 5379 switch (ring_type) { 5380 case HWRM_RING_ALLOC_TX: 5381 db->db_key32 = DB_KEY_TX; 5382 break; 5383 case HWRM_RING_ALLOC_RX: 5384 case HWRM_RING_ALLOC_AGG: 5385 db->db_key32 = DB_KEY_RX; 5386 break; 5387 case HWRM_RING_ALLOC_CMPL: 5388 db->db_key32 = DB_KEY_CP; 5389 break; 5390 } 5391 } 5392 } 5393 5394 static int bnxt_hwrm_ring_alloc(struct bnxt *bp) 5395 { 5396 bool agg_rings = !!(bp->flags & BNXT_FLAG_AGG_RINGS); 5397 int i, rc = 0; 5398 u32 type; 5399 5400 if (bp->flags & BNXT_FLAG_CHIP_P5) 5401 type = HWRM_RING_ALLOC_NQ; 5402 else 5403 type = HWRM_RING_ALLOC_CMPL; 5404 for (i = 0; i < bp->cp_nr_rings; i++) { 5405 struct bnxt_napi *bnapi = bp->bnapi[i]; 5406 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5407 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 5408 u32 map_idx = ring->map_idx; 5409 unsigned int vector; 5410 5411 vector = bp->irq_tbl[map_idx].vector; 5412 disable_irq_nosync(vector); 5413 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5414 if (rc) { 5415 enable_irq(vector); 5416 goto err_out; 5417 } 5418 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id); 5419 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); 5420 enable_irq(vector); 5421 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id; 5422 5423 if (!i) { 5424 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id); 5425 if (rc) 5426 netdev_warn(bp->dev, "Failed to set async event completion ring.\n"); 5427 } 5428 } 5429 5430 type = HWRM_RING_ALLOC_TX; 5431 for (i = 0; i < bp->tx_nr_rings; i++) { 5432 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 5433 struct bnxt_ring_struct *ring; 5434 u32 map_idx; 5435 5436 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5437 struct bnxt_napi *bnapi = txr->bnapi; 5438 struct bnxt_cp_ring_info *cpr, *cpr2; 5439 u32 type2 = HWRM_RING_ALLOC_CMPL; 5440 5441 cpr = &bnapi->cp_ring; 5442 cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL]; 5443 ring = &cpr2->cp_ring_struct; 5444 ring->handle = BNXT_TX_HDL; 5445 map_idx = bnapi->index; 5446 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); 5447 if (rc) 5448 goto err_out; 5449 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, 5450 ring->fw_ring_id); 5451 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); 5452 } 5453 ring = &txr->tx_ring_struct; 5454 map_idx = i; 5455 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5456 if (rc) 5457 goto err_out; 5458 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id); 5459 } 5460 5461 type = HWRM_RING_ALLOC_RX; 5462 for (i = 0; i < bp->rx_nr_rings; i++) { 5463 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5464 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 5465 struct bnxt_napi *bnapi = rxr->bnapi; 5466 u32 map_idx = bnapi->index; 5467 5468 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5469 if (rc) 5470 goto err_out; 5471 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id); 5472 /* If we have agg rings, post agg buffers first. */ 5473 if (!agg_rings) 5474 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 5475 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id; 5476 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5477 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5478 u32 type2 = HWRM_RING_ALLOC_CMPL; 5479 struct bnxt_cp_ring_info *cpr2; 5480 5481 cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL]; 5482 ring = &cpr2->cp_ring_struct; 5483 ring->handle = BNXT_RX_HDL; 5484 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); 5485 if (rc) 5486 goto err_out; 5487 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, 5488 ring->fw_ring_id); 5489 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); 5490 } 5491 } 5492 5493 if (agg_rings) { 5494 type = HWRM_RING_ALLOC_AGG; 5495 for (i = 0; i < bp->rx_nr_rings; i++) { 5496 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5497 struct bnxt_ring_struct *ring = 5498 &rxr->rx_agg_ring_struct; 5499 u32 grp_idx = ring->grp_idx; 5500 u32 map_idx = grp_idx + bp->rx_nr_rings; 5501 5502 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5503 if (rc) 5504 goto err_out; 5505 5506 bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx, 5507 ring->fw_ring_id); 5508 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 5509 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 5510 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id; 5511 } 5512 } 5513 err_out: 5514 return rc; 5515 } 5516 5517 static int hwrm_ring_free_send_msg(struct bnxt *bp, 5518 struct bnxt_ring_struct *ring, 5519 u32 ring_type, int cmpl_ring_id) 5520 { 5521 int rc; 5522 struct hwrm_ring_free_input req = {0}; 5523 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr; 5524 u16 error_code; 5525 5526 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 5527 return 0; 5528 5529 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1); 5530 req.ring_type = ring_type; 5531 req.ring_id = cpu_to_le16(ring->fw_ring_id); 5532 5533 mutex_lock(&bp->hwrm_cmd_lock); 5534 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5535 error_code = le16_to_cpu(resp->error_code); 5536 mutex_unlock(&bp->hwrm_cmd_lock); 5537 5538 if (rc || error_code) { 5539 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n", 5540 ring_type, rc, error_code); 5541 return -EIO; 5542 } 5543 return 0; 5544 } 5545 5546 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path) 5547 { 5548 u32 type; 5549 int i; 5550 5551 if (!bp->bnapi) 5552 return; 5553 5554 for (i = 0; i < bp->tx_nr_rings; i++) { 5555 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 5556 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 5557 5558 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5559 u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr); 5560 5561 hwrm_ring_free_send_msg(bp, ring, 5562 RING_FREE_REQ_RING_TYPE_TX, 5563 close_path ? cmpl_ring_id : 5564 INVALID_HW_RING_ID); 5565 ring->fw_ring_id = INVALID_HW_RING_ID; 5566 } 5567 } 5568 5569 for (i = 0; i < bp->rx_nr_rings; i++) { 5570 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5571 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 5572 u32 grp_idx = rxr->bnapi->index; 5573 5574 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5575 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); 5576 5577 hwrm_ring_free_send_msg(bp, ring, 5578 RING_FREE_REQ_RING_TYPE_RX, 5579 close_path ? cmpl_ring_id : 5580 INVALID_HW_RING_ID); 5581 ring->fw_ring_id = INVALID_HW_RING_ID; 5582 bp->grp_info[grp_idx].rx_fw_ring_id = 5583 INVALID_HW_RING_ID; 5584 } 5585 } 5586 5587 if (bp->flags & BNXT_FLAG_CHIP_P5) 5588 type = RING_FREE_REQ_RING_TYPE_RX_AGG; 5589 else 5590 type = RING_FREE_REQ_RING_TYPE_RX; 5591 for (i = 0; i < bp->rx_nr_rings; i++) { 5592 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5593 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct; 5594 u32 grp_idx = rxr->bnapi->index; 5595 5596 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5597 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); 5598 5599 hwrm_ring_free_send_msg(bp, ring, type, 5600 close_path ? cmpl_ring_id : 5601 INVALID_HW_RING_ID); 5602 ring->fw_ring_id = INVALID_HW_RING_ID; 5603 bp->grp_info[grp_idx].agg_fw_ring_id = 5604 INVALID_HW_RING_ID; 5605 } 5606 } 5607 5608 /* The completion rings are about to be freed. After that the 5609 * IRQ doorbell will not work anymore. So we need to disable 5610 * IRQ here. 5611 */ 5612 bnxt_disable_int_sync(bp); 5613 5614 if (bp->flags & BNXT_FLAG_CHIP_P5) 5615 type = RING_FREE_REQ_RING_TYPE_NQ; 5616 else 5617 type = RING_FREE_REQ_RING_TYPE_L2_CMPL; 5618 for (i = 0; i < bp->cp_nr_rings; i++) { 5619 struct bnxt_napi *bnapi = bp->bnapi[i]; 5620 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5621 struct bnxt_ring_struct *ring; 5622 int j; 5623 5624 for (j = 0; j < 2; j++) { 5625 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 5626 5627 if (cpr2) { 5628 ring = &cpr2->cp_ring_struct; 5629 if (ring->fw_ring_id == INVALID_HW_RING_ID) 5630 continue; 5631 hwrm_ring_free_send_msg(bp, ring, 5632 RING_FREE_REQ_RING_TYPE_L2_CMPL, 5633 INVALID_HW_RING_ID); 5634 ring->fw_ring_id = INVALID_HW_RING_ID; 5635 } 5636 } 5637 ring = &cpr->cp_ring_struct; 5638 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5639 hwrm_ring_free_send_msg(bp, ring, type, 5640 INVALID_HW_RING_ID); 5641 ring->fw_ring_id = INVALID_HW_RING_ID; 5642 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 5643 } 5644 } 5645 } 5646 5647 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 5648 bool shared); 5649 5650 static int bnxt_hwrm_get_rings(struct bnxt *bp) 5651 { 5652 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 5653 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5654 struct hwrm_func_qcfg_input req = {0}; 5655 int rc; 5656 5657 if (bp->hwrm_spec_code < 0x10601) 5658 return 0; 5659 5660 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 5661 req.fid = cpu_to_le16(0xffff); 5662 mutex_lock(&bp->hwrm_cmd_lock); 5663 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5664 if (rc) { 5665 mutex_unlock(&bp->hwrm_cmd_lock); 5666 return rc; 5667 } 5668 5669 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings); 5670 if (BNXT_NEW_RM(bp)) { 5671 u16 cp, stats; 5672 5673 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings); 5674 hw_resc->resv_hw_ring_grps = 5675 le32_to_cpu(resp->alloc_hw_ring_grps); 5676 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics); 5677 cp = le16_to_cpu(resp->alloc_cmpl_rings); 5678 stats = le16_to_cpu(resp->alloc_stat_ctx); 5679 hw_resc->resv_irqs = cp; 5680 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5681 int rx = hw_resc->resv_rx_rings; 5682 int tx = hw_resc->resv_tx_rings; 5683 5684 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5685 rx >>= 1; 5686 if (cp < (rx + tx)) { 5687 bnxt_trim_rings(bp, &rx, &tx, cp, false); 5688 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5689 rx <<= 1; 5690 hw_resc->resv_rx_rings = rx; 5691 hw_resc->resv_tx_rings = tx; 5692 } 5693 hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix); 5694 hw_resc->resv_hw_ring_grps = rx; 5695 } 5696 hw_resc->resv_cp_rings = cp; 5697 hw_resc->resv_stat_ctxs = stats; 5698 } 5699 mutex_unlock(&bp->hwrm_cmd_lock); 5700 return 0; 5701 } 5702 5703 /* Caller must hold bp->hwrm_cmd_lock */ 5704 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings) 5705 { 5706 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 5707 struct hwrm_func_qcfg_input req = {0}; 5708 int rc; 5709 5710 if (bp->hwrm_spec_code < 0x10601) 5711 return 0; 5712 5713 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 5714 req.fid = cpu_to_le16(fid); 5715 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5716 if (!rc) 5717 *tx_rings = le16_to_cpu(resp->alloc_tx_rings); 5718 5719 return rc; 5720 } 5721 5722 static bool bnxt_rfs_supported(struct bnxt *bp); 5723 5724 static void 5725 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req, 5726 int tx_rings, int rx_rings, int ring_grps, 5727 int cp_rings, int stats, int vnics) 5728 { 5729 u32 enables = 0; 5730 5731 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1); 5732 req->fid = cpu_to_le16(0xffff); 5733 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; 5734 req->num_tx_rings = cpu_to_le16(tx_rings); 5735 if (BNXT_NEW_RM(bp)) { 5736 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0; 5737 enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; 5738 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5739 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0; 5740 enables |= tx_rings + ring_grps ? 5741 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5742 enables |= rx_rings ? 5743 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 5744 } else { 5745 enables |= cp_rings ? 5746 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5747 enables |= ring_grps ? 5748 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS | 5749 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 5750 } 5751 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0; 5752 5753 req->num_rx_rings = cpu_to_le16(rx_rings); 5754 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5755 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); 5756 req->num_msix = cpu_to_le16(cp_rings); 5757 req->num_rsscos_ctxs = 5758 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); 5759 } else { 5760 req->num_cmpl_rings = cpu_to_le16(cp_rings); 5761 req->num_hw_ring_grps = cpu_to_le16(ring_grps); 5762 req->num_rsscos_ctxs = cpu_to_le16(1); 5763 if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) && 5764 bnxt_rfs_supported(bp)) 5765 req->num_rsscos_ctxs = 5766 cpu_to_le16(ring_grps + 1); 5767 } 5768 req->num_stat_ctxs = cpu_to_le16(stats); 5769 req->num_vnics = cpu_to_le16(vnics); 5770 } 5771 req->enables = cpu_to_le32(enables); 5772 } 5773 5774 static void 5775 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, 5776 struct hwrm_func_vf_cfg_input *req, int tx_rings, 5777 int rx_rings, int ring_grps, int cp_rings, 5778 int stats, int vnics) 5779 { 5780 u32 enables = 0; 5781 5782 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1); 5783 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; 5784 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS | 5785 FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 5786 enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; 5787 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5788 enables |= tx_rings + ring_grps ? 5789 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5790 } else { 5791 enables |= cp_rings ? 5792 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5793 enables |= ring_grps ? 5794 FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0; 5795 } 5796 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0; 5797 enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS; 5798 5799 req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX); 5800 req->num_tx_rings = cpu_to_le16(tx_rings); 5801 req->num_rx_rings = cpu_to_le16(rx_rings); 5802 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5803 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); 5804 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); 5805 } else { 5806 req->num_cmpl_rings = cpu_to_le16(cp_rings); 5807 req->num_hw_ring_grps = cpu_to_le16(ring_grps); 5808 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX); 5809 } 5810 req->num_stat_ctxs = cpu_to_le16(stats); 5811 req->num_vnics = cpu_to_le16(vnics); 5812 5813 req->enables = cpu_to_le32(enables); 5814 } 5815 5816 static int 5817 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 5818 int ring_grps, int cp_rings, int stats, int vnics) 5819 { 5820 struct hwrm_func_cfg_input req = {0}; 5821 int rc; 5822 5823 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 5824 cp_rings, stats, vnics); 5825 if (!req.enables) 5826 return 0; 5827 5828 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5829 if (rc) 5830 return rc; 5831 5832 if (bp->hwrm_spec_code < 0x10601) 5833 bp->hw_resc.resv_tx_rings = tx_rings; 5834 5835 return bnxt_hwrm_get_rings(bp); 5836 } 5837 5838 static int 5839 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 5840 int ring_grps, int cp_rings, int stats, int vnics) 5841 { 5842 struct hwrm_func_vf_cfg_input req = {0}; 5843 int rc; 5844 5845 if (!BNXT_NEW_RM(bp)) { 5846 bp->hw_resc.resv_tx_rings = tx_rings; 5847 return 0; 5848 } 5849 5850 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 5851 cp_rings, stats, vnics); 5852 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5853 if (rc) 5854 return rc; 5855 5856 return bnxt_hwrm_get_rings(bp); 5857 } 5858 5859 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp, 5860 int cp, int stat, int vnic) 5861 { 5862 if (BNXT_PF(bp)) 5863 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat, 5864 vnic); 5865 else 5866 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat, 5867 vnic); 5868 } 5869 5870 int bnxt_nq_rings_in_use(struct bnxt *bp) 5871 { 5872 int cp = bp->cp_nr_rings; 5873 int ulp_msix, ulp_base; 5874 5875 ulp_msix = bnxt_get_ulp_msix_num(bp); 5876 if (ulp_msix) { 5877 ulp_base = bnxt_get_ulp_msix_base(bp); 5878 cp += ulp_msix; 5879 if ((ulp_base + ulp_msix) > cp) 5880 cp = ulp_base + ulp_msix; 5881 } 5882 return cp; 5883 } 5884 5885 static int bnxt_cp_rings_in_use(struct bnxt *bp) 5886 { 5887 int cp; 5888 5889 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 5890 return bnxt_nq_rings_in_use(bp); 5891 5892 cp = bp->tx_nr_rings + bp->rx_nr_rings; 5893 return cp; 5894 } 5895 5896 static int bnxt_get_func_stat_ctxs(struct bnxt *bp) 5897 { 5898 int ulp_stat = bnxt_get_ulp_stat_ctxs(bp); 5899 int cp = bp->cp_nr_rings; 5900 5901 if (!ulp_stat) 5902 return cp; 5903 5904 if (bnxt_nq_rings_in_use(bp) > cp + bnxt_get_ulp_msix_num(bp)) 5905 return bnxt_get_ulp_msix_base(bp) + ulp_stat; 5906 5907 return cp + ulp_stat; 5908 } 5909 5910 static bool bnxt_need_reserve_rings(struct bnxt *bp) 5911 { 5912 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5913 int cp = bnxt_cp_rings_in_use(bp); 5914 int nq = bnxt_nq_rings_in_use(bp); 5915 int rx = bp->rx_nr_rings, stat; 5916 int vnic = 1, grp = rx; 5917 5918 if (bp->hwrm_spec_code < 0x10601) 5919 return false; 5920 5921 if (hw_resc->resv_tx_rings != bp->tx_nr_rings) 5922 return true; 5923 5924 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) 5925 vnic = rx + 1; 5926 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5927 rx <<= 1; 5928 stat = bnxt_get_func_stat_ctxs(bp); 5929 if (BNXT_NEW_RM(bp) && 5930 (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp || 5931 hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat || 5932 (hw_resc->resv_hw_ring_grps != grp && 5933 !(bp->flags & BNXT_FLAG_CHIP_P5)))) 5934 return true; 5935 if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) && 5936 hw_resc->resv_irqs != nq) 5937 return true; 5938 return false; 5939 } 5940 5941 static int __bnxt_reserve_rings(struct bnxt *bp) 5942 { 5943 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5944 int cp = bnxt_nq_rings_in_use(bp); 5945 int tx = bp->tx_nr_rings; 5946 int rx = bp->rx_nr_rings; 5947 int grp, rx_rings, rc; 5948 int vnic = 1, stat; 5949 bool sh = false; 5950 5951 if (!bnxt_need_reserve_rings(bp)) 5952 return 0; 5953 5954 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 5955 sh = true; 5956 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) 5957 vnic = rx + 1; 5958 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5959 rx <<= 1; 5960 grp = bp->rx_nr_rings; 5961 stat = bnxt_get_func_stat_ctxs(bp); 5962 5963 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic); 5964 if (rc) 5965 return rc; 5966 5967 tx = hw_resc->resv_tx_rings; 5968 if (BNXT_NEW_RM(bp)) { 5969 rx = hw_resc->resv_rx_rings; 5970 cp = hw_resc->resv_irqs; 5971 grp = hw_resc->resv_hw_ring_grps; 5972 vnic = hw_resc->resv_vnics; 5973 stat = hw_resc->resv_stat_ctxs; 5974 } 5975 5976 rx_rings = rx; 5977 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 5978 if (rx >= 2) { 5979 rx_rings = rx >> 1; 5980 } else { 5981 if (netif_running(bp->dev)) 5982 return -ENOMEM; 5983 5984 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 5985 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 5986 bp->dev->hw_features &= ~NETIF_F_LRO; 5987 bp->dev->features &= ~NETIF_F_LRO; 5988 bnxt_set_ring_params(bp); 5989 } 5990 } 5991 rx_rings = min_t(int, rx_rings, grp); 5992 cp = min_t(int, cp, bp->cp_nr_rings); 5993 if (stat > bnxt_get_ulp_stat_ctxs(bp)) 5994 stat -= bnxt_get_ulp_stat_ctxs(bp); 5995 cp = min_t(int, cp, stat); 5996 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh); 5997 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5998 rx = rx_rings << 1; 5999 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings; 6000 bp->tx_nr_rings = tx; 6001 bp->rx_nr_rings = rx_rings; 6002 bp->cp_nr_rings = cp; 6003 6004 if (!tx || !rx || !cp || !grp || !vnic || !stat) 6005 return -ENOMEM; 6006 6007 return rc; 6008 } 6009 6010 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6011 int ring_grps, int cp_rings, int stats, 6012 int vnics) 6013 { 6014 struct hwrm_func_vf_cfg_input req = {0}; 6015 u32 flags; 6016 6017 if (!BNXT_NEW_RM(bp)) 6018 return 0; 6019 6020 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 6021 cp_rings, stats, vnics); 6022 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST | 6023 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST | 6024 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | 6025 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | 6026 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST | 6027 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST; 6028 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 6029 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; 6030 6031 req.flags = cpu_to_le32(flags); 6032 return hwrm_send_message_silent(bp, &req, sizeof(req), 6033 HWRM_CMD_TIMEOUT); 6034 } 6035 6036 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6037 int ring_grps, int cp_rings, int stats, 6038 int vnics) 6039 { 6040 struct hwrm_func_cfg_input req = {0}; 6041 u32 flags; 6042 6043 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 6044 cp_rings, stats, vnics); 6045 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST; 6046 if (BNXT_NEW_RM(bp)) { 6047 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST | 6048 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | 6049 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | 6050 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST; 6051 if (bp->flags & BNXT_FLAG_CHIP_P5) 6052 flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST | 6053 FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST; 6054 else 6055 flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; 6056 } 6057 6058 req.flags = cpu_to_le32(flags); 6059 return hwrm_send_message_silent(bp, &req, sizeof(req), 6060 HWRM_CMD_TIMEOUT); 6061 } 6062 6063 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings, 6064 int ring_grps, int cp_rings, int stats, 6065 int vnics) 6066 { 6067 if (bp->hwrm_spec_code < 0x10801) 6068 return 0; 6069 6070 if (BNXT_PF(bp)) 6071 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings, 6072 ring_grps, cp_rings, stats, 6073 vnics); 6074 6075 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps, 6076 cp_rings, stats, vnics); 6077 } 6078 6079 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp) 6080 { 6081 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 6082 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6083 struct hwrm_ring_aggint_qcaps_input req = {0}; 6084 int rc; 6085 6086 coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS; 6087 coal_cap->num_cmpl_dma_aggr_max = 63; 6088 coal_cap->num_cmpl_dma_aggr_during_int_max = 63; 6089 coal_cap->cmpl_aggr_dma_tmr_max = 65535; 6090 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535; 6091 coal_cap->int_lat_tmr_min_max = 65535; 6092 coal_cap->int_lat_tmr_max_max = 65535; 6093 coal_cap->num_cmpl_aggr_int_max = 65535; 6094 coal_cap->timer_units = 80; 6095 6096 if (bp->hwrm_spec_code < 0x10902) 6097 return; 6098 6099 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1); 6100 mutex_lock(&bp->hwrm_cmd_lock); 6101 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6102 if (!rc) { 6103 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params); 6104 coal_cap->nq_params = le32_to_cpu(resp->nq_params); 6105 coal_cap->num_cmpl_dma_aggr_max = 6106 le16_to_cpu(resp->num_cmpl_dma_aggr_max); 6107 coal_cap->num_cmpl_dma_aggr_during_int_max = 6108 le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max); 6109 coal_cap->cmpl_aggr_dma_tmr_max = 6110 le16_to_cpu(resp->cmpl_aggr_dma_tmr_max); 6111 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 6112 le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max); 6113 coal_cap->int_lat_tmr_min_max = 6114 le16_to_cpu(resp->int_lat_tmr_min_max); 6115 coal_cap->int_lat_tmr_max_max = 6116 le16_to_cpu(resp->int_lat_tmr_max_max); 6117 coal_cap->num_cmpl_aggr_int_max = 6118 le16_to_cpu(resp->num_cmpl_aggr_int_max); 6119 coal_cap->timer_units = le16_to_cpu(resp->timer_units); 6120 } 6121 mutex_unlock(&bp->hwrm_cmd_lock); 6122 } 6123 6124 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec) 6125 { 6126 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6127 6128 return usec * 1000 / coal_cap->timer_units; 6129 } 6130 6131 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, 6132 struct bnxt_coal *hw_coal, 6133 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req) 6134 { 6135 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6136 u32 cmpl_params = coal_cap->cmpl_params; 6137 u16 val, tmr, max, flags = 0; 6138 6139 max = hw_coal->bufs_per_record * 128; 6140 if (hw_coal->budget) 6141 max = hw_coal->bufs_per_record * hw_coal->budget; 6142 max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max); 6143 6144 val = clamp_t(u16, hw_coal->coal_bufs, 1, max); 6145 req->num_cmpl_aggr_int = cpu_to_le16(val); 6146 6147 val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max); 6148 req->num_cmpl_dma_aggr = cpu_to_le16(val); 6149 6150 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, 6151 coal_cap->num_cmpl_dma_aggr_during_int_max); 6152 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val); 6153 6154 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks); 6155 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max); 6156 req->int_lat_tmr_max = cpu_to_le16(tmr); 6157 6158 /* min timer set to 1/2 of interrupt timer */ 6159 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) { 6160 val = tmr / 2; 6161 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max); 6162 req->int_lat_tmr_min = cpu_to_le16(val); 6163 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); 6164 } 6165 6166 /* buf timer set to 1/4 of interrupt timer */ 6167 val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max); 6168 req->cmpl_aggr_dma_tmr = cpu_to_le16(val); 6169 6170 if (cmpl_params & 6171 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) { 6172 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq); 6173 val = clamp_t(u16, tmr, 1, 6174 coal_cap->cmpl_aggr_dma_tmr_during_int_max); 6175 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(val); 6176 req->enables |= 6177 cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE); 6178 } 6179 6180 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET) 6181 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 6182 if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) && 6183 hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh) 6184 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE; 6185 req->flags = cpu_to_le16(flags); 6186 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES); 6187 } 6188 6189 /* Caller holds bp->hwrm_cmd_lock */ 6190 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi, 6191 struct bnxt_coal *hw_coal) 6192 { 6193 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0}; 6194 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6195 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 6196 u32 nq_params = coal_cap->nq_params; 6197 u16 tmr; 6198 6199 if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN)) 6200 return 0; 6201 6202 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, 6203 -1, -1); 6204 req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id); 6205 req.flags = 6206 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ); 6207 6208 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2; 6209 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max); 6210 req.int_lat_tmr_min = cpu_to_le16(tmr); 6211 req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); 6212 return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6213 } 6214 6215 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi) 6216 { 6217 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}; 6218 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6219 struct bnxt_coal coal; 6220 6221 /* Tick values in micro seconds. 6222 * 1 coal_buf x bufs_per_record = 1 completion record. 6223 */ 6224 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal)); 6225 6226 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks; 6227 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs; 6228 6229 if (!bnapi->rx_ring) 6230 return -ENODEV; 6231 6232 bnxt_hwrm_cmd_hdr_init(bp, &req_rx, 6233 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 6234 6235 bnxt_hwrm_set_coal_params(bp, &coal, &req_rx); 6236 6237 req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring)); 6238 6239 return hwrm_send_message(bp, &req_rx, sizeof(req_rx), 6240 HWRM_CMD_TIMEOUT); 6241 } 6242 6243 int bnxt_hwrm_set_coal(struct bnxt *bp) 6244 { 6245 int i, rc = 0; 6246 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}, 6247 req_tx = {0}, *req; 6248 6249 bnxt_hwrm_cmd_hdr_init(bp, &req_rx, 6250 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 6251 bnxt_hwrm_cmd_hdr_init(bp, &req_tx, 6252 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 6253 6254 bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx); 6255 bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx); 6256 6257 mutex_lock(&bp->hwrm_cmd_lock); 6258 for (i = 0; i < bp->cp_nr_rings; i++) { 6259 struct bnxt_napi *bnapi = bp->bnapi[i]; 6260 struct bnxt_coal *hw_coal; 6261 u16 ring_id; 6262 6263 req = &req_rx; 6264 if (!bnapi->rx_ring) { 6265 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); 6266 req = &req_tx; 6267 } else { 6268 ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring); 6269 } 6270 req->ring_id = cpu_to_le16(ring_id); 6271 6272 rc = _hwrm_send_message(bp, req, sizeof(*req), 6273 HWRM_CMD_TIMEOUT); 6274 if (rc) 6275 break; 6276 6277 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 6278 continue; 6279 6280 if (bnapi->rx_ring && bnapi->tx_ring) { 6281 req = &req_tx; 6282 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); 6283 req->ring_id = cpu_to_le16(ring_id); 6284 rc = _hwrm_send_message(bp, req, sizeof(*req), 6285 HWRM_CMD_TIMEOUT); 6286 if (rc) 6287 break; 6288 } 6289 if (bnapi->rx_ring) 6290 hw_coal = &bp->rx_coal; 6291 else 6292 hw_coal = &bp->tx_coal; 6293 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal); 6294 } 6295 mutex_unlock(&bp->hwrm_cmd_lock); 6296 return rc; 6297 } 6298 6299 static void bnxt_hwrm_stat_ctx_free(struct bnxt *bp) 6300 { 6301 struct hwrm_stat_ctx_free_input req = {0}; 6302 int i; 6303 6304 if (!bp->bnapi) 6305 return; 6306 6307 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 6308 return; 6309 6310 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1); 6311 6312 mutex_lock(&bp->hwrm_cmd_lock); 6313 for (i = 0; i < bp->cp_nr_rings; i++) { 6314 struct bnxt_napi *bnapi = bp->bnapi[i]; 6315 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6316 6317 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) { 6318 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id); 6319 6320 _hwrm_send_message(bp, &req, sizeof(req), 6321 HWRM_CMD_TIMEOUT); 6322 6323 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 6324 } 6325 } 6326 mutex_unlock(&bp->hwrm_cmd_lock); 6327 } 6328 6329 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp) 6330 { 6331 int rc = 0, i; 6332 struct hwrm_stat_ctx_alloc_input req = {0}; 6333 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr; 6334 6335 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 6336 return 0; 6337 6338 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1); 6339 6340 req.stats_dma_length = cpu_to_le16(bp->hw_ring_stats_size); 6341 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000); 6342 6343 mutex_lock(&bp->hwrm_cmd_lock); 6344 for (i = 0; i < bp->cp_nr_rings; i++) { 6345 struct bnxt_napi *bnapi = bp->bnapi[i]; 6346 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6347 6348 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map); 6349 6350 rc = _hwrm_send_message(bp, &req, sizeof(req), 6351 HWRM_CMD_TIMEOUT); 6352 if (rc) 6353 break; 6354 6355 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id); 6356 6357 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id; 6358 } 6359 mutex_unlock(&bp->hwrm_cmd_lock); 6360 return rc; 6361 } 6362 6363 static int bnxt_hwrm_func_qcfg(struct bnxt *bp) 6364 { 6365 struct hwrm_func_qcfg_input req = {0}; 6366 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 6367 u32 min_db_offset = 0; 6368 u16 flags; 6369 int rc; 6370 6371 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 6372 req.fid = cpu_to_le16(0xffff); 6373 mutex_lock(&bp->hwrm_cmd_lock); 6374 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6375 if (rc) 6376 goto func_qcfg_exit; 6377 6378 #ifdef CONFIG_BNXT_SRIOV 6379 if (BNXT_VF(bp)) { 6380 struct bnxt_vf_info *vf = &bp->vf; 6381 6382 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK; 6383 } else { 6384 bp->pf.registered_vfs = le16_to_cpu(resp->registered_vfs); 6385 } 6386 #endif 6387 flags = le16_to_cpu(resp->flags); 6388 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED | 6389 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) { 6390 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT; 6391 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED) 6392 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT; 6393 } 6394 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST)) 6395 bp->flags |= BNXT_FLAG_MULTI_HOST; 6396 6397 switch (resp->port_partition_type) { 6398 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0: 6399 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5: 6400 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0: 6401 bp->port_partition_type = resp->port_partition_type; 6402 break; 6403 } 6404 if (bp->hwrm_spec_code < 0x10707 || 6405 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB) 6406 bp->br_mode = BRIDGE_MODE_VEB; 6407 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA) 6408 bp->br_mode = BRIDGE_MODE_VEPA; 6409 else 6410 bp->br_mode = BRIDGE_MODE_UNDEF; 6411 6412 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured); 6413 if (!bp->max_mtu) 6414 bp->max_mtu = BNXT_MAX_MTU; 6415 6416 if (bp->db_size) 6417 goto func_qcfg_exit; 6418 6419 if (bp->flags & BNXT_FLAG_CHIP_P5) { 6420 if (BNXT_PF(bp)) 6421 min_db_offset = DB_PF_OFFSET_P5; 6422 else 6423 min_db_offset = DB_VF_OFFSET_P5; 6424 } 6425 bp->db_size = PAGE_ALIGN(le16_to_cpu(resp->l2_doorbell_bar_size_kb) * 6426 1024); 6427 if (!bp->db_size || bp->db_size > pci_resource_len(bp->pdev, 2) || 6428 bp->db_size <= min_db_offset) 6429 bp->db_size = pci_resource_len(bp->pdev, 2); 6430 6431 func_qcfg_exit: 6432 mutex_unlock(&bp->hwrm_cmd_lock); 6433 return rc; 6434 } 6435 6436 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp) 6437 { 6438 struct hwrm_func_backing_store_qcaps_input req = {0}; 6439 struct hwrm_func_backing_store_qcaps_output *resp = 6440 bp->hwrm_cmd_resp_addr; 6441 int rc; 6442 6443 if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx) 6444 return 0; 6445 6446 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1); 6447 mutex_lock(&bp->hwrm_cmd_lock); 6448 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6449 if (!rc) { 6450 struct bnxt_ctx_pg_info *ctx_pg; 6451 struct bnxt_ctx_mem_info *ctx; 6452 int i, tqm_rings; 6453 6454 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 6455 if (!ctx) { 6456 rc = -ENOMEM; 6457 goto ctx_err; 6458 } 6459 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries); 6460 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries); 6461 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries); 6462 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size); 6463 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries); 6464 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries); 6465 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size); 6466 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries); 6467 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries); 6468 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size); 6469 ctx->vnic_max_vnic_entries = 6470 le16_to_cpu(resp->vnic_max_vnic_entries); 6471 ctx->vnic_max_ring_table_entries = 6472 le16_to_cpu(resp->vnic_max_ring_table_entries); 6473 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size); 6474 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries); 6475 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size); 6476 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size); 6477 ctx->tqm_min_entries_per_ring = 6478 le32_to_cpu(resp->tqm_min_entries_per_ring); 6479 ctx->tqm_max_entries_per_ring = 6480 le32_to_cpu(resp->tqm_max_entries_per_ring); 6481 ctx->tqm_entries_multiple = resp->tqm_entries_multiple; 6482 if (!ctx->tqm_entries_multiple) 6483 ctx->tqm_entries_multiple = 1; 6484 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries); 6485 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size); 6486 ctx->mrav_num_entries_units = 6487 le16_to_cpu(resp->mrav_num_entries_units); 6488 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size); 6489 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries); 6490 ctx->ctx_kind_initializer = resp->ctx_kind_initializer; 6491 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count; 6492 if (!ctx->tqm_fp_rings_count) 6493 ctx->tqm_fp_rings_count = bp->max_q; 6494 6495 tqm_rings = ctx->tqm_fp_rings_count + 1; 6496 ctx_pg = kcalloc(tqm_rings, sizeof(*ctx_pg), GFP_KERNEL); 6497 if (!ctx_pg) { 6498 kfree(ctx); 6499 rc = -ENOMEM; 6500 goto ctx_err; 6501 } 6502 for (i = 0; i < tqm_rings; i++, ctx_pg++) 6503 ctx->tqm_mem[i] = ctx_pg; 6504 bp->ctx = ctx; 6505 } else { 6506 rc = 0; 6507 } 6508 ctx_err: 6509 mutex_unlock(&bp->hwrm_cmd_lock); 6510 return rc; 6511 } 6512 6513 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr, 6514 __le64 *pg_dir) 6515 { 6516 u8 pg_size = 0; 6517 6518 if (BNXT_PAGE_SHIFT == 13) 6519 pg_size = 1 << 4; 6520 else if (BNXT_PAGE_SIZE == 16) 6521 pg_size = 2 << 4; 6522 6523 *pg_attr = pg_size; 6524 if (rmem->depth >= 1) { 6525 if (rmem->depth == 2) 6526 *pg_attr |= 2; 6527 else 6528 *pg_attr |= 1; 6529 *pg_dir = cpu_to_le64(rmem->pg_tbl_map); 6530 } else { 6531 *pg_dir = cpu_to_le64(rmem->dma_arr[0]); 6532 } 6533 } 6534 6535 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \ 6536 (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \ 6537 FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \ 6538 FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \ 6539 FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \ 6540 FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) 6541 6542 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables) 6543 { 6544 struct hwrm_func_backing_store_cfg_input req = {0}; 6545 struct bnxt_ctx_mem_info *ctx = bp->ctx; 6546 struct bnxt_ctx_pg_info *ctx_pg; 6547 __le32 *num_entries; 6548 __le64 *pg_dir; 6549 u32 flags = 0; 6550 u8 *pg_attr; 6551 u32 ena; 6552 int i; 6553 6554 if (!ctx) 6555 return 0; 6556 6557 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1); 6558 req.enables = cpu_to_le32(enables); 6559 6560 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) { 6561 ctx_pg = &ctx->qp_mem; 6562 req.qp_num_entries = cpu_to_le32(ctx_pg->entries); 6563 req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries); 6564 req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries); 6565 req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size); 6566 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6567 &req.qpc_pg_size_qpc_lvl, 6568 &req.qpc_page_dir); 6569 } 6570 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) { 6571 ctx_pg = &ctx->srq_mem; 6572 req.srq_num_entries = cpu_to_le32(ctx_pg->entries); 6573 req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries); 6574 req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size); 6575 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6576 &req.srq_pg_size_srq_lvl, 6577 &req.srq_page_dir); 6578 } 6579 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) { 6580 ctx_pg = &ctx->cq_mem; 6581 req.cq_num_entries = cpu_to_le32(ctx_pg->entries); 6582 req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries); 6583 req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size); 6584 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl, 6585 &req.cq_page_dir); 6586 } 6587 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) { 6588 ctx_pg = &ctx->vnic_mem; 6589 req.vnic_num_vnic_entries = 6590 cpu_to_le16(ctx->vnic_max_vnic_entries); 6591 req.vnic_num_ring_table_entries = 6592 cpu_to_le16(ctx->vnic_max_ring_table_entries); 6593 req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size); 6594 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6595 &req.vnic_pg_size_vnic_lvl, 6596 &req.vnic_page_dir); 6597 } 6598 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) { 6599 ctx_pg = &ctx->stat_mem; 6600 req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries); 6601 req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size); 6602 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6603 &req.stat_pg_size_stat_lvl, 6604 &req.stat_page_dir); 6605 } 6606 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) { 6607 ctx_pg = &ctx->mrav_mem; 6608 req.mrav_num_entries = cpu_to_le32(ctx_pg->entries); 6609 if (ctx->mrav_num_entries_units) 6610 flags |= 6611 FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT; 6612 req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size); 6613 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6614 &req.mrav_pg_size_mrav_lvl, 6615 &req.mrav_page_dir); 6616 } 6617 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) { 6618 ctx_pg = &ctx->tim_mem; 6619 req.tim_num_entries = cpu_to_le32(ctx_pg->entries); 6620 req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size); 6621 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6622 &req.tim_pg_size_tim_lvl, 6623 &req.tim_page_dir); 6624 } 6625 for (i = 0, num_entries = &req.tqm_sp_num_entries, 6626 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl, 6627 pg_dir = &req.tqm_sp_page_dir, 6628 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP; 6629 i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) { 6630 if (!(enables & ena)) 6631 continue; 6632 6633 req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size); 6634 ctx_pg = ctx->tqm_mem[i]; 6635 *num_entries = cpu_to_le32(ctx_pg->entries); 6636 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir); 6637 } 6638 req.flags = cpu_to_le32(flags); 6639 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6640 } 6641 6642 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, 6643 struct bnxt_ctx_pg_info *ctx_pg) 6644 { 6645 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 6646 6647 rmem->page_size = BNXT_PAGE_SIZE; 6648 rmem->pg_arr = ctx_pg->ctx_pg_arr; 6649 rmem->dma_arr = ctx_pg->ctx_dma_arr; 6650 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 6651 if (rmem->depth >= 1) 6652 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG; 6653 return bnxt_alloc_ring(bp, rmem); 6654 } 6655 6656 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp, 6657 struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size, 6658 u8 depth, bool use_init_val) 6659 { 6660 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 6661 int rc; 6662 6663 if (!mem_size) 6664 return -EINVAL; 6665 6666 ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); 6667 if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) { 6668 ctx_pg->nr_pages = 0; 6669 return -EINVAL; 6670 } 6671 if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) { 6672 int nr_tbls, i; 6673 6674 rmem->depth = 2; 6675 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg), 6676 GFP_KERNEL); 6677 if (!ctx_pg->ctx_pg_tbl) 6678 return -ENOMEM; 6679 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES); 6680 rmem->nr_pages = nr_tbls; 6681 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); 6682 if (rc) 6683 return rc; 6684 for (i = 0; i < nr_tbls; i++) { 6685 struct bnxt_ctx_pg_info *pg_tbl; 6686 6687 pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL); 6688 if (!pg_tbl) 6689 return -ENOMEM; 6690 ctx_pg->ctx_pg_tbl[i] = pg_tbl; 6691 rmem = &pg_tbl->ring_mem; 6692 rmem->pg_tbl = ctx_pg->ctx_pg_arr[i]; 6693 rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i]; 6694 rmem->depth = 1; 6695 rmem->nr_pages = MAX_CTX_PAGES; 6696 if (use_init_val) 6697 rmem->init_val = bp->ctx->ctx_kind_initializer; 6698 if (i == (nr_tbls - 1)) { 6699 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES; 6700 6701 if (rem) 6702 rmem->nr_pages = rem; 6703 } 6704 rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl); 6705 if (rc) 6706 break; 6707 } 6708 } else { 6709 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); 6710 if (rmem->nr_pages > 1 || depth) 6711 rmem->depth = 1; 6712 if (use_init_val) 6713 rmem->init_val = bp->ctx->ctx_kind_initializer; 6714 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); 6715 } 6716 return rc; 6717 } 6718 6719 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp, 6720 struct bnxt_ctx_pg_info *ctx_pg) 6721 { 6722 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 6723 6724 if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES || 6725 ctx_pg->ctx_pg_tbl) { 6726 int i, nr_tbls = rmem->nr_pages; 6727 6728 for (i = 0; i < nr_tbls; i++) { 6729 struct bnxt_ctx_pg_info *pg_tbl; 6730 struct bnxt_ring_mem_info *rmem2; 6731 6732 pg_tbl = ctx_pg->ctx_pg_tbl[i]; 6733 if (!pg_tbl) 6734 continue; 6735 rmem2 = &pg_tbl->ring_mem; 6736 bnxt_free_ring(bp, rmem2); 6737 ctx_pg->ctx_pg_arr[i] = NULL; 6738 kfree(pg_tbl); 6739 ctx_pg->ctx_pg_tbl[i] = NULL; 6740 } 6741 kfree(ctx_pg->ctx_pg_tbl); 6742 ctx_pg->ctx_pg_tbl = NULL; 6743 } 6744 bnxt_free_ring(bp, rmem); 6745 ctx_pg->nr_pages = 0; 6746 } 6747 6748 static void bnxt_free_ctx_mem(struct bnxt *bp) 6749 { 6750 struct bnxt_ctx_mem_info *ctx = bp->ctx; 6751 int i; 6752 6753 if (!ctx) 6754 return; 6755 6756 if (ctx->tqm_mem[0]) { 6757 for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++) 6758 bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]); 6759 kfree(ctx->tqm_mem[0]); 6760 ctx->tqm_mem[0] = NULL; 6761 } 6762 6763 bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem); 6764 bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem); 6765 bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem); 6766 bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem); 6767 bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem); 6768 bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem); 6769 bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem); 6770 ctx->flags &= ~BNXT_CTX_FLAG_INITED; 6771 } 6772 6773 static int bnxt_alloc_ctx_mem(struct bnxt *bp) 6774 { 6775 struct bnxt_ctx_pg_info *ctx_pg; 6776 struct bnxt_ctx_mem_info *ctx; 6777 u32 mem_size, ena, entries; 6778 u32 entries_sp, min; 6779 u32 num_mr, num_ah; 6780 u32 extra_srqs = 0; 6781 u32 extra_qps = 0; 6782 u8 pg_lvl = 1; 6783 int i, rc; 6784 6785 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 6786 if (rc) { 6787 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n", 6788 rc); 6789 return rc; 6790 } 6791 ctx = bp->ctx; 6792 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 6793 return 0; 6794 6795 if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) { 6796 pg_lvl = 2; 6797 extra_qps = 65536; 6798 extra_srqs = 8192; 6799 } 6800 6801 ctx_pg = &ctx->qp_mem; 6802 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries + 6803 extra_qps; 6804 mem_size = ctx->qp_entry_size * ctx_pg->entries; 6805 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true); 6806 if (rc) 6807 return rc; 6808 6809 ctx_pg = &ctx->srq_mem; 6810 ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs; 6811 mem_size = ctx->srq_entry_size * ctx_pg->entries; 6812 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true); 6813 if (rc) 6814 return rc; 6815 6816 ctx_pg = &ctx->cq_mem; 6817 ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2; 6818 mem_size = ctx->cq_entry_size * ctx_pg->entries; 6819 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true); 6820 if (rc) 6821 return rc; 6822 6823 ctx_pg = &ctx->vnic_mem; 6824 ctx_pg->entries = ctx->vnic_max_vnic_entries + 6825 ctx->vnic_max_ring_table_entries; 6826 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 6827 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, true); 6828 if (rc) 6829 return rc; 6830 6831 ctx_pg = &ctx->stat_mem; 6832 ctx_pg->entries = ctx->stat_max_entries; 6833 mem_size = ctx->stat_entry_size * ctx_pg->entries; 6834 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, true); 6835 if (rc) 6836 return rc; 6837 6838 ena = 0; 6839 if (!(bp->flags & BNXT_FLAG_ROCE_CAP)) 6840 goto skip_rdma; 6841 6842 ctx_pg = &ctx->mrav_mem; 6843 /* 128K extra is needed to accommodate static AH context 6844 * allocation by f/w. 6845 */ 6846 num_mr = 1024 * 256; 6847 num_ah = 1024 * 128; 6848 ctx_pg->entries = num_mr + num_ah; 6849 mem_size = ctx->mrav_entry_size * ctx_pg->entries; 6850 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2, true); 6851 if (rc) 6852 return rc; 6853 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV; 6854 if (ctx->mrav_num_entries_units) 6855 ctx_pg->entries = 6856 ((num_mr / ctx->mrav_num_entries_units) << 16) | 6857 (num_ah / ctx->mrav_num_entries_units); 6858 6859 ctx_pg = &ctx->tim_mem; 6860 ctx_pg->entries = ctx->qp_mem.entries; 6861 mem_size = ctx->tim_entry_size * ctx_pg->entries; 6862 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, false); 6863 if (rc) 6864 return rc; 6865 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM; 6866 6867 skip_rdma: 6868 min = ctx->tqm_min_entries_per_ring; 6869 entries_sp = ctx->vnic_max_vnic_entries + ctx->qp_max_l2_entries + 6870 2 * (extra_qps + ctx->qp_min_qp1_entries) + min; 6871 entries_sp = roundup(entries_sp, ctx->tqm_entries_multiple); 6872 entries = ctx->qp_max_l2_entries + extra_qps + ctx->qp_min_qp1_entries; 6873 entries = roundup(entries, ctx->tqm_entries_multiple); 6874 entries = clamp_t(u32, entries, min, ctx->tqm_max_entries_per_ring); 6875 for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++) { 6876 ctx_pg = ctx->tqm_mem[i]; 6877 ctx_pg->entries = i ? entries : entries_sp; 6878 mem_size = ctx->tqm_entry_size * ctx_pg->entries; 6879 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, false); 6880 if (rc) 6881 return rc; 6882 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i; 6883 } 6884 ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES; 6885 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 6886 if (rc) { 6887 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n", 6888 rc); 6889 return rc; 6890 } 6891 ctx->flags |= BNXT_CTX_FLAG_INITED; 6892 return 0; 6893 } 6894 6895 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all) 6896 { 6897 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 6898 struct hwrm_func_resource_qcaps_input req = {0}; 6899 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 6900 int rc; 6901 6902 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1); 6903 req.fid = cpu_to_le16(0xffff); 6904 6905 mutex_lock(&bp->hwrm_cmd_lock); 6906 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), 6907 HWRM_CMD_TIMEOUT); 6908 if (rc) 6909 goto hwrm_func_resc_qcaps_exit; 6910 6911 hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs); 6912 if (!all) 6913 goto hwrm_func_resc_qcaps_exit; 6914 6915 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx); 6916 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 6917 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings); 6918 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 6919 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings); 6920 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 6921 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings); 6922 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 6923 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps); 6924 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps); 6925 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs); 6926 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 6927 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics); 6928 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); 6929 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx); 6930 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 6931 6932 if (bp->flags & BNXT_FLAG_CHIP_P5) { 6933 u16 max_msix = le16_to_cpu(resp->max_msix); 6934 6935 hw_resc->max_nqs = max_msix; 6936 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings; 6937 } 6938 6939 if (BNXT_PF(bp)) { 6940 struct bnxt_pf_info *pf = &bp->pf; 6941 6942 pf->vf_resv_strategy = 6943 le16_to_cpu(resp->vf_reservation_strategy); 6944 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC) 6945 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL; 6946 } 6947 hwrm_func_resc_qcaps_exit: 6948 mutex_unlock(&bp->hwrm_cmd_lock); 6949 return rc; 6950 } 6951 6952 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) 6953 { 6954 int rc = 0; 6955 struct hwrm_func_qcaps_input req = {0}; 6956 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 6957 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 6958 u32 flags; 6959 6960 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1); 6961 req.fid = cpu_to_le16(0xffff); 6962 6963 mutex_lock(&bp->hwrm_cmd_lock); 6964 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6965 if (rc) 6966 goto hwrm_func_qcaps_exit; 6967 6968 flags = le32_to_cpu(resp->flags); 6969 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED) 6970 bp->flags |= BNXT_FLAG_ROCEV1_CAP; 6971 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED) 6972 bp->flags |= BNXT_FLAG_ROCEV2_CAP; 6973 if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED) 6974 bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED; 6975 if (flags & FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE) 6976 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET; 6977 if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED) 6978 bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED; 6979 if (flags & FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE) 6980 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY; 6981 if (flags & FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD) 6982 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD; 6983 6984 bp->tx_push_thresh = 0; 6985 if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) 6986 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH; 6987 6988 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 6989 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 6990 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 6991 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 6992 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); 6993 if (!hw_resc->max_hw_ring_grps) 6994 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings; 6995 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 6996 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); 6997 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 6998 6999 if (BNXT_PF(bp)) { 7000 struct bnxt_pf_info *pf = &bp->pf; 7001 7002 pf->fw_fid = le16_to_cpu(resp->fid); 7003 pf->port_id = le16_to_cpu(resp->port_id); 7004 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN); 7005 pf->first_vf_id = le16_to_cpu(resp->first_vf_id); 7006 pf->max_vfs = le16_to_cpu(resp->max_vfs); 7007 pf->max_encap_records = le32_to_cpu(resp->max_encap_records); 7008 pf->max_decap_records = le32_to_cpu(resp->max_decap_records); 7009 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows); 7010 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows); 7011 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows); 7012 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows); 7013 bp->flags &= ~BNXT_FLAG_WOL_CAP; 7014 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED) 7015 bp->flags |= BNXT_FLAG_WOL_CAP; 7016 } else { 7017 #ifdef CONFIG_BNXT_SRIOV 7018 struct bnxt_vf_info *vf = &bp->vf; 7019 7020 vf->fw_fid = le16_to_cpu(resp->fid); 7021 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN); 7022 #endif 7023 } 7024 7025 hwrm_func_qcaps_exit: 7026 mutex_unlock(&bp->hwrm_cmd_lock); 7027 return rc; 7028 } 7029 7030 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp); 7031 7032 static int bnxt_hwrm_func_qcaps(struct bnxt *bp) 7033 { 7034 int rc; 7035 7036 rc = __bnxt_hwrm_func_qcaps(bp); 7037 if (rc) 7038 return rc; 7039 rc = bnxt_hwrm_queue_qportcfg(bp); 7040 if (rc) { 7041 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc); 7042 return rc; 7043 } 7044 if (bp->hwrm_spec_code >= 0x10803) { 7045 rc = bnxt_alloc_ctx_mem(bp); 7046 if (rc) 7047 return rc; 7048 rc = bnxt_hwrm_func_resc_qcaps(bp, true); 7049 if (!rc) 7050 bp->fw_cap |= BNXT_FW_CAP_NEW_RM; 7051 } 7052 return 0; 7053 } 7054 7055 static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp) 7056 { 7057 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0}; 7058 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp; 7059 int rc = 0; 7060 u32 flags; 7061 7062 if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW)) 7063 return 0; 7064 7065 resp = bp->hwrm_cmd_resp_addr; 7066 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, -1, -1); 7067 7068 mutex_lock(&bp->hwrm_cmd_lock); 7069 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7070 if (rc) 7071 goto hwrm_cfa_adv_qcaps_exit; 7072 7073 flags = le32_to_cpu(resp->flags); 7074 if (flags & 7075 CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED) 7076 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2; 7077 7078 hwrm_cfa_adv_qcaps_exit: 7079 mutex_unlock(&bp->hwrm_cmd_lock); 7080 return rc; 7081 } 7082 7083 static int bnxt_map_fw_health_regs(struct bnxt *bp) 7084 { 7085 struct bnxt_fw_health *fw_health = bp->fw_health; 7086 u32 reg_base = 0xffffffff; 7087 int i; 7088 7089 /* Only pre-map the monitoring GRC registers using window 3 */ 7090 for (i = 0; i < 4; i++) { 7091 u32 reg = fw_health->regs[i]; 7092 7093 if (BNXT_FW_HEALTH_REG_TYPE(reg) != BNXT_FW_HEALTH_REG_TYPE_GRC) 7094 continue; 7095 if (reg_base == 0xffffffff) 7096 reg_base = reg & BNXT_GRC_BASE_MASK; 7097 if ((reg & BNXT_GRC_BASE_MASK) != reg_base) 7098 return -ERANGE; 7099 fw_health->mapped_regs[i] = BNXT_FW_HEALTH_WIN_BASE + 7100 (reg & BNXT_GRC_OFFSET_MASK); 7101 } 7102 if (reg_base == 0xffffffff) 7103 return 0; 7104 7105 writel(reg_base, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 7106 BNXT_FW_HEALTH_WIN_MAP_OFF); 7107 return 0; 7108 } 7109 7110 static int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp) 7111 { 7112 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 7113 struct bnxt_fw_health *fw_health = bp->fw_health; 7114 struct hwrm_error_recovery_qcfg_input req = {0}; 7115 int rc, i; 7116 7117 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 7118 return 0; 7119 7120 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_ERROR_RECOVERY_QCFG, -1, -1); 7121 mutex_lock(&bp->hwrm_cmd_lock); 7122 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7123 if (rc) 7124 goto err_recovery_out; 7125 fw_health->flags = le32_to_cpu(resp->flags); 7126 if ((fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) && 7127 !(bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL)) { 7128 rc = -EINVAL; 7129 goto err_recovery_out; 7130 } 7131 fw_health->polling_dsecs = le32_to_cpu(resp->driver_polling_freq); 7132 fw_health->master_func_wait_dsecs = 7133 le32_to_cpu(resp->master_func_wait_period); 7134 fw_health->normal_func_wait_dsecs = 7135 le32_to_cpu(resp->normal_func_wait_period); 7136 fw_health->post_reset_wait_dsecs = 7137 le32_to_cpu(resp->master_func_wait_period_after_reset); 7138 fw_health->post_reset_max_wait_dsecs = 7139 le32_to_cpu(resp->max_bailout_time_after_reset); 7140 fw_health->regs[BNXT_FW_HEALTH_REG] = 7141 le32_to_cpu(resp->fw_health_status_reg); 7142 fw_health->regs[BNXT_FW_HEARTBEAT_REG] = 7143 le32_to_cpu(resp->fw_heartbeat_reg); 7144 fw_health->regs[BNXT_FW_RESET_CNT_REG] = 7145 le32_to_cpu(resp->fw_reset_cnt_reg); 7146 fw_health->regs[BNXT_FW_RESET_INPROG_REG] = 7147 le32_to_cpu(resp->reset_inprogress_reg); 7148 fw_health->fw_reset_inprog_reg_mask = 7149 le32_to_cpu(resp->reset_inprogress_reg_mask); 7150 fw_health->fw_reset_seq_cnt = resp->reg_array_cnt; 7151 if (fw_health->fw_reset_seq_cnt >= 16) { 7152 rc = -EINVAL; 7153 goto err_recovery_out; 7154 } 7155 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) { 7156 fw_health->fw_reset_seq_regs[i] = 7157 le32_to_cpu(resp->reset_reg[i]); 7158 fw_health->fw_reset_seq_vals[i] = 7159 le32_to_cpu(resp->reset_reg_val[i]); 7160 fw_health->fw_reset_seq_delay_msec[i] = 7161 resp->delay_after_reset[i]; 7162 } 7163 err_recovery_out: 7164 mutex_unlock(&bp->hwrm_cmd_lock); 7165 if (!rc) 7166 rc = bnxt_map_fw_health_regs(bp); 7167 if (rc) 7168 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 7169 return rc; 7170 } 7171 7172 static int bnxt_hwrm_func_reset(struct bnxt *bp) 7173 { 7174 struct hwrm_func_reset_input req = {0}; 7175 7176 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1); 7177 req.enables = 0; 7178 7179 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT); 7180 } 7181 7182 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp) 7183 { 7184 int rc = 0; 7185 struct hwrm_queue_qportcfg_input req = {0}; 7186 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr; 7187 u8 i, j, *qptr; 7188 bool no_rdma; 7189 7190 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1); 7191 7192 mutex_lock(&bp->hwrm_cmd_lock); 7193 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7194 if (rc) 7195 goto qportcfg_exit; 7196 7197 if (!resp->max_configurable_queues) { 7198 rc = -EINVAL; 7199 goto qportcfg_exit; 7200 } 7201 bp->max_tc = resp->max_configurable_queues; 7202 bp->max_lltc = resp->max_configurable_lossless_queues; 7203 if (bp->max_tc > BNXT_MAX_QUEUE) 7204 bp->max_tc = BNXT_MAX_QUEUE; 7205 7206 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP); 7207 qptr = &resp->queue_id0; 7208 for (i = 0, j = 0; i < bp->max_tc; i++) { 7209 bp->q_info[j].queue_id = *qptr; 7210 bp->q_ids[i] = *qptr++; 7211 bp->q_info[j].queue_profile = *qptr++; 7212 bp->tc_to_qidx[j] = j; 7213 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) || 7214 (no_rdma && BNXT_PF(bp))) 7215 j++; 7216 } 7217 bp->max_q = bp->max_tc; 7218 bp->max_tc = max_t(u8, j, 1); 7219 7220 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG) 7221 bp->max_tc = 1; 7222 7223 if (bp->max_lltc > bp->max_tc) 7224 bp->max_lltc = bp->max_tc; 7225 7226 qportcfg_exit: 7227 mutex_unlock(&bp->hwrm_cmd_lock); 7228 return rc; 7229 } 7230 7231 static int __bnxt_hwrm_ver_get(struct bnxt *bp, bool silent) 7232 { 7233 struct hwrm_ver_get_input req = {0}; 7234 int rc; 7235 7236 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1); 7237 req.hwrm_intf_maj = HWRM_VERSION_MAJOR; 7238 req.hwrm_intf_min = HWRM_VERSION_MINOR; 7239 req.hwrm_intf_upd = HWRM_VERSION_UPDATE; 7240 7241 rc = bnxt_hwrm_do_send_msg(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT, 7242 silent); 7243 return rc; 7244 } 7245 7246 static int bnxt_hwrm_ver_get(struct bnxt *bp) 7247 { 7248 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr; 7249 u32 dev_caps_cfg, hwrm_ver; 7250 int rc; 7251 7252 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN; 7253 mutex_lock(&bp->hwrm_cmd_lock); 7254 rc = __bnxt_hwrm_ver_get(bp, false); 7255 if (rc) 7256 goto hwrm_ver_get_exit; 7257 7258 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output)); 7259 7260 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 | 7261 resp->hwrm_intf_min_8b << 8 | 7262 resp->hwrm_intf_upd_8b; 7263 if (resp->hwrm_intf_maj_8b < 1) { 7264 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n", 7265 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, 7266 resp->hwrm_intf_upd_8b); 7267 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n"); 7268 } 7269 7270 hwrm_ver = HWRM_VERSION_MAJOR << 16 | HWRM_VERSION_MINOR << 8 | 7271 HWRM_VERSION_UPDATE; 7272 7273 if (bp->hwrm_spec_code > hwrm_ver) 7274 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d", 7275 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, 7276 HWRM_VERSION_UPDATE); 7277 else 7278 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d", 7279 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, 7280 resp->hwrm_intf_upd_8b); 7281 7282 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d", 7283 resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b, 7284 resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b); 7285 7286 if (strlen(resp->active_pkg_name)) { 7287 int fw_ver_len = strlen(bp->fw_ver_str); 7288 7289 snprintf(bp->fw_ver_str + fw_ver_len, 7290 FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s", 7291 resp->active_pkg_name); 7292 bp->fw_cap |= BNXT_FW_CAP_PKG_VER; 7293 } 7294 7295 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout); 7296 if (!bp->hwrm_cmd_timeout) 7297 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; 7298 7299 if (resp->hwrm_intf_maj_8b >= 1) { 7300 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len); 7301 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len); 7302 } 7303 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN) 7304 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN; 7305 7306 bp->chip_num = le16_to_cpu(resp->chip_num); 7307 bp->chip_rev = resp->chip_rev; 7308 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev && 7309 !resp->chip_metal) 7310 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0; 7311 7312 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg); 7313 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) && 7314 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) 7315 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD; 7316 7317 if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) 7318 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL; 7319 7320 if (dev_caps_cfg & 7321 VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED) 7322 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE; 7323 7324 if (dev_caps_cfg & 7325 VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED) 7326 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF; 7327 7328 if (dev_caps_cfg & 7329 VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) 7330 bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW; 7331 7332 hwrm_ver_get_exit: 7333 mutex_unlock(&bp->hwrm_cmd_lock); 7334 return rc; 7335 } 7336 7337 int bnxt_hwrm_fw_set_time(struct bnxt *bp) 7338 { 7339 struct hwrm_fw_set_time_input req = {0}; 7340 struct tm tm; 7341 time64_t now = ktime_get_real_seconds(); 7342 7343 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) || 7344 bp->hwrm_spec_code < 0x10400) 7345 return -EOPNOTSUPP; 7346 7347 time64_to_tm(now, 0, &tm); 7348 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1); 7349 req.year = cpu_to_le16(1900 + tm.tm_year); 7350 req.month = 1 + tm.tm_mon; 7351 req.day = tm.tm_mday; 7352 req.hour = tm.tm_hour; 7353 req.minute = tm.tm_min; 7354 req.second = tm.tm_sec; 7355 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7356 } 7357 7358 static int bnxt_hwrm_port_qstats(struct bnxt *bp) 7359 { 7360 struct bnxt_pf_info *pf = &bp->pf; 7361 struct hwrm_port_qstats_input req = {0}; 7362 7363 if (!(bp->flags & BNXT_FLAG_PORT_STATS)) 7364 return 0; 7365 7366 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1); 7367 req.port_id = cpu_to_le16(pf->port_id); 7368 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map); 7369 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map); 7370 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7371 } 7372 7373 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp) 7374 { 7375 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr; 7376 struct hwrm_queue_pri2cos_qcfg_input req2 = {0}; 7377 struct hwrm_port_qstats_ext_input req = {0}; 7378 struct bnxt_pf_info *pf = &bp->pf; 7379 u32 tx_stat_size; 7380 int rc; 7381 7382 if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 7383 return 0; 7384 7385 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1); 7386 req.port_id = cpu_to_le16(pf->port_id); 7387 req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext)); 7388 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map); 7389 tx_stat_size = bp->hw_tx_port_stats_ext ? 7390 sizeof(*bp->hw_tx_port_stats_ext) : 0; 7391 req.tx_stat_size = cpu_to_le16(tx_stat_size); 7392 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_ext_map); 7393 mutex_lock(&bp->hwrm_cmd_lock); 7394 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7395 if (!rc) { 7396 bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8; 7397 bp->fw_tx_stats_ext_size = tx_stat_size ? 7398 le16_to_cpu(resp->tx_stat_size) / 8 : 0; 7399 } else { 7400 bp->fw_rx_stats_ext_size = 0; 7401 bp->fw_tx_stats_ext_size = 0; 7402 } 7403 if (bp->fw_tx_stats_ext_size <= 7404 offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) { 7405 mutex_unlock(&bp->hwrm_cmd_lock); 7406 bp->pri2cos_valid = 0; 7407 return rc; 7408 } 7409 7410 bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1); 7411 req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN); 7412 7413 rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT); 7414 if (!rc) { 7415 struct hwrm_queue_pri2cos_qcfg_output *resp2; 7416 u8 *pri2cos; 7417 int i, j; 7418 7419 resp2 = bp->hwrm_cmd_resp_addr; 7420 pri2cos = &resp2->pri0_cos_queue_id; 7421 for (i = 0; i < 8; i++) { 7422 u8 queue_id = pri2cos[i]; 7423 u8 queue_idx; 7424 7425 /* Per port queue IDs start from 0, 10, 20, etc */ 7426 queue_idx = queue_id % 10; 7427 if (queue_idx > BNXT_MAX_QUEUE) { 7428 bp->pri2cos_valid = false; 7429 goto qstats_done; 7430 } 7431 for (j = 0; j < bp->max_q; j++) { 7432 if (bp->q_ids[j] == queue_id) 7433 bp->pri2cos_idx[i] = queue_idx; 7434 } 7435 } 7436 bp->pri2cos_valid = 1; 7437 } 7438 qstats_done: 7439 mutex_unlock(&bp->hwrm_cmd_lock); 7440 return rc; 7441 } 7442 7443 static int bnxt_hwrm_pcie_qstats(struct bnxt *bp) 7444 { 7445 struct hwrm_pcie_qstats_input req = {0}; 7446 7447 if (!(bp->flags & BNXT_FLAG_PCIE_STATS)) 7448 return 0; 7449 7450 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PCIE_QSTATS, -1, -1); 7451 req.pcie_stat_size = cpu_to_le16(sizeof(struct pcie_ctx_hw_stats)); 7452 req.pcie_stat_host_addr = cpu_to_le64(bp->hw_pcie_stats_map); 7453 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7454 } 7455 7456 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp) 7457 { 7458 if (bp->vxlan_port_cnt) { 7459 bnxt_hwrm_tunnel_dst_port_free( 7460 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 7461 } 7462 bp->vxlan_port_cnt = 0; 7463 if (bp->nge_port_cnt) { 7464 bnxt_hwrm_tunnel_dst_port_free( 7465 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 7466 } 7467 bp->nge_port_cnt = 0; 7468 } 7469 7470 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa) 7471 { 7472 int rc, i; 7473 u32 tpa_flags = 0; 7474 7475 if (set_tpa) 7476 tpa_flags = bp->flags & BNXT_FLAG_TPA; 7477 else if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 7478 return 0; 7479 for (i = 0; i < bp->nr_vnics; i++) { 7480 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags); 7481 if (rc) { 7482 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n", 7483 i, rc); 7484 return rc; 7485 } 7486 } 7487 return 0; 7488 } 7489 7490 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp) 7491 { 7492 int i; 7493 7494 for (i = 0; i < bp->nr_vnics; i++) 7495 bnxt_hwrm_vnic_set_rss(bp, i, false); 7496 } 7497 7498 static void bnxt_clear_vnic(struct bnxt *bp) 7499 { 7500 if (!bp->vnic_info) 7501 return; 7502 7503 bnxt_hwrm_clear_vnic_filter(bp); 7504 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) { 7505 /* clear all RSS setting before free vnic ctx */ 7506 bnxt_hwrm_clear_vnic_rss(bp); 7507 bnxt_hwrm_vnic_ctx_free(bp); 7508 } 7509 /* before free the vnic, undo the vnic tpa settings */ 7510 if (bp->flags & BNXT_FLAG_TPA) 7511 bnxt_set_tpa(bp, false); 7512 bnxt_hwrm_vnic_free(bp); 7513 if (bp->flags & BNXT_FLAG_CHIP_P5) 7514 bnxt_hwrm_vnic_ctx_free(bp); 7515 } 7516 7517 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path, 7518 bool irq_re_init) 7519 { 7520 bnxt_clear_vnic(bp); 7521 bnxt_hwrm_ring_free(bp, close_path); 7522 bnxt_hwrm_ring_grp_free(bp); 7523 if (irq_re_init) { 7524 bnxt_hwrm_stat_ctx_free(bp); 7525 bnxt_hwrm_free_tunnel_ports(bp); 7526 } 7527 } 7528 7529 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode) 7530 { 7531 struct hwrm_func_cfg_input req = {0}; 7532 7533 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 7534 req.fid = cpu_to_le16(0xffff); 7535 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE); 7536 if (br_mode == BRIDGE_MODE_VEB) 7537 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB; 7538 else if (br_mode == BRIDGE_MODE_VEPA) 7539 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA; 7540 else 7541 return -EINVAL; 7542 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7543 } 7544 7545 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size) 7546 { 7547 struct hwrm_func_cfg_input req = {0}; 7548 7549 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803) 7550 return 0; 7551 7552 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 7553 req.fid = cpu_to_le16(0xffff); 7554 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE); 7555 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64; 7556 if (size == 128) 7557 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128; 7558 7559 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7560 } 7561 7562 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) 7563 { 7564 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 7565 int rc; 7566 7567 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) 7568 goto skip_rss_ctx; 7569 7570 /* allocate context for vnic */ 7571 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0); 7572 if (rc) { 7573 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 7574 vnic_id, rc); 7575 goto vnic_setup_err; 7576 } 7577 bp->rsscos_nr_ctxs++; 7578 7579 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 7580 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1); 7581 if (rc) { 7582 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n", 7583 vnic_id, rc); 7584 goto vnic_setup_err; 7585 } 7586 bp->rsscos_nr_ctxs++; 7587 } 7588 7589 skip_rss_ctx: 7590 /* configure default vnic, ring grp */ 7591 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); 7592 if (rc) { 7593 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", 7594 vnic_id, rc); 7595 goto vnic_setup_err; 7596 } 7597 7598 /* Enable RSS hashing on vnic */ 7599 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true); 7600 if (rc) { 7601 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n", 7602 vnic_id, rc); 7603 goto vnic_setup_err; 7604 } 7605 7606 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 7607 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); 7608 if (rc) { 7609 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", 7610 vnic_id, rc); 7611 } 7612 } 7613 7614 vnic_setup_err: 7615 return rc; 7616 } 7617 7618 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id) 7619 { 7620 int rc, i, nr_ctxs; 7621 7622 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64); 7623 for (i = 0; i < nr_ctxs; i++) { 7624 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i); 7625 if (rc) { 7626 netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n", 7627 vnic_id, i, rc); 7628 break; 7629 } 7630 bp->rsscos_nr_ctxs++; 7631 } 7632 if (i < nr_ctxs) 7633 return -ENOMEM; 7634 7635 rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true); 7636 if (rc) { 7637 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n", 7638 vnic_id, rc); 7639 return rc; 7640 } 7641 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); 7642 if (rc) { 7643 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", 7644 vnic_id, rc); 7645 return rc; 7646 } 7647 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 7648 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); 7649 if (rc) { 7650 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", 7651 vnic_id, rc); 7652 } 7653 } 7654 return rc; 7655 } 7656 7657 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) 7658 { 7659 if (bp->flags & BNXT_FLAG_CHIP_P5) 7660 return __bnxt_setup_vnic_p5(bp, vnic_id); 7661 else 7662 return __bnxt_setup_vnic(bp, vnic_id); 7663 } 7664 7665 static int bnxt_alloc_rfs_vnics(struct bnxt *bp) 7666 { 7667 #ifdef CONFIG_RFS_ACCEL 7668 int i, rc = 0; 7669 7670 if (bp->flags & BNXT_FLAG_CHIP_P5) 7671 return 0; 7672 7673 for (i = 0; i < bp->rx_nr_rings; i++) { 7674 struct bnxt_vnic_info *vnic; 7675 u16 vnic_id = i + 1; 7676 u16 ring_id = i; 7677 7678 if (vnic_id >= bp->nr_vnics) 7679 break; 7680 7681 vnic = &bp->vnic_info[vnic_id]; 7682 vnic->flags |= BNXT_VNIC_RFS_FLAG; 7683 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 7684 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG; 7685 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1); 7686 if (rc) { 7687 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 7688 vnic_id, rc); 7689 break; 7690 } 7691 rc = bnxt_setup_vnic(bp, vnic_id); 7692 if (rc) 7693 break; 7694 } 7695 return rc; 7696 #else 7697 return 0; 7698 #endif 7699 } 7700 7701 /* Allow PF and VF with default VLAN to be in promiscuous mode */ 7702 static bool bnxt_promisc_ok(struct bnxt *bp) 7703 { 7704 #ifdef CONFIG_BNXT_SRIOV 7705 if (BNXT_VF(bp) && !bp->vf.vlan) 7706 return false; 7707 #endif 7708 return true; 7709 } 7710 7711 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp) 7712 { 7713 unsigned int rc = 0; 7714 7715 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1); 7716 if (rc) { 7717 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 7718 rc); 7719 return rc; 7720 } 7721 7722 rc = bnxt_hwrm_vnic_cfg(bp, 1); 7723 if (rc) { 7724 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 7725 rc); 7726 return rc; 7727 } 7728 return rc; 7729 } 7730 7731 static int bnxt_cfg_rx_mode(struct bnxt *); 7732 static bool bnxt_mc_list_updated(struct bnxt *, u32 *); 7733 7734 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init) 7735 { 7736 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 7737 int rc = 0; 7738 unsigned int rx_nr_rings = bp->rx_nr_rings; 7739 7740 if (irq_re_init) { 7741 rc = bnxt_hwrm_stat_ctx_alloc(bp); 7742 if (rc) { 7743 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n", 7744 rc); 7745 goto err_out; 7746 } 7747 } 7748 7749 rc = bnxt_hwrm_ring_alloc(bp); 7750 if (rc) { 7751 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc); 7752 goto err_out; 7753 } 7754 7755 rc = bnxt_hwrm_ring_grp_alloc(bp); 7756 if (rc) { 7757 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc); 7758 goto err_out; 7759 } 7760 7761 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 7762 rx_nr_rings--; 7763 7764 /* default vnic 0 */ 7765 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings); 7766 if (rc) { 7767 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc); 7768 goto err_out; 7769 } 7770 7771 rc = bnxt_setup_vnic(bp, 0); 7772 if (rc) 7773 goto err_out; 7774 7775 if (bp->flags & BNXT_FLAG_RFS) { 7776 rc = bnxt_alloc_rfs_vnics(bp); 7777 if (rc) 7778 goto err_out; 7779 } 7780 7781 if (bp->flags & BNXT_FLAG_TPA) { 7782 rc = bnxt_set_tpa(bp, true); 7783 if (rc) 7784 goto err_out; 7785 } 7786 7787 if (BNXT_VF(bp)) 7788 bnxt_update_vf_mac(bp); 7789 7790 /* Filter for default vnic 0 */ 7791 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr); 7792 if (rc) { 7793 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc); 7794 goto err_out; 7795 } 7796 vnic->uc_filter_count = 1; 7797 7798 vnic->rx_mask = 0; 7799 if (bp->dev->flags & IFF_BROADCAST) 7800 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 7801 7802 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) 7803 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 7804 7805 if (bp->dev->flags & IFF_ALLMULTI) { 7806 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 7807 vnic->mc_list_count = 0; 7808 } else { 7809 u32 mask = 0; 7810 7811 bnxt_mc_list_updated(bp, &mask); 7812 vnic->rx_mask |= mask; 7813 } 7814 7815 rc = bnxt_cfg_rx_mode(bp); 7816 if (rc) 7817 goto err_out; 7818 7819 rc = bnxt_hwrm_set_coal(bp); 7820 if (rc) 7821 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n", 7822 rc); 7823 7824 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 7825 rc = bnxt_setup_nitroa0_vnic(bp); 7826 if (rc) 7827 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n", 7828 rc); 7829 } 7830 7831 if (BNXT_VF(bp)) { 7832 bnxt_hwrm_func_qcfg(bp); 7833 netdev_update_features(bp->dev); 7834 } 7835 7836 return 0; 7837 7838 err_out: 7839 bnxt_hwrm_resource_free(bp, 0, true); 7840 7841 return rc; 7842 } 7843 7844 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init) 7845 { 7846 bnxt_hwrm_resource_free(bp, 1, irq_re_init); 7847 return 0; 7848 } 7849 7850 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init) 7851 { 7852 bnxt_init_cp_rings(bp); 7853 bnxt_init_rx_rings(bp); 7854 bnxt_init_tx_rings(bp); 7855 bnxt_init_ring_grps(bp, irq_re_init); 7856 bnxt_init_vnics(bp); 7857 7858 return bnxt_init_chip(bp, irq_re_init); 7859 } 7860 7861 static int bnxt_set_real_num_queues(struct bnxt *bp) 7862 { 7863 int rc; 7864 struct net_device *dev = bp->dev; 7865 7866 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings - 7867 bp->tx_nr_rings_xdp); 7868 if (rc) 7869 return rc; 7870 7871 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings); 7872 if (rc) 7873 return rc; 7874 7875 #ifdef CONFIG_RFS_ACCEL 7876 if (bp->flags & BNXT_FLAG_RFS) 7877 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings); 7878 #endif 7879 7880 return rc; 7881 } 7882 7883 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 7884 bool shared) 7885 { 7886 int _rx = *rx, _tx = *tx; 7887 7888 if (shared) { 7889 *rx = min_t(int, _rx, max); 7890 *tx = min_t(int, _tx, max); 7891 } else { 7892 if (max < 2) 7893 return -ENOMEM; 7894 7895 while (_rx + _tx > max) { 7896 if (_rx > _tx && _rx > 1) 7897 _rx--; 7898 else if (_tx > 1) 7899 _tx--; 7900 } 7901 *rx = _rx; 7902 *tx = _tx; 7903 } 7904 return 0; 7905 } 7906 7907 static void bnxt_setup_msix(struct bnxt *bp) 7908 { 7909 const int len = sizeof(bp->irq_tbl[0].name); 7910 struct net_device *dev = bp->dev; 7911 int tcs, i; 7912 7913 tcs = netdev_get_num_tc(dev); 7914 if (tcs) { 7915 int i, off, count; 7916 7917 for (i = 0; i < tcs; i++) { 7918 count = bp->tx_nr_rings_per_tc; 7919 off = i * count; 7920 netdev_set_tc_queue(dev, i, count, off); 7921 } 7922 } 7923 7924 for (i = 0; i < bp->cp_nr_rings; i++) { 7925 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 7926 char *attr; 7927 7928 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 7929 attr = "TxRx"; 7930 else if (i < bp->rx_nr_rings) 7931 attr = "rx"; 7932 else 7933 attr = "tx"; 7934 7935 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name, 7936 attr, i); 7937 bp->irq_tbl[map_idx].handler = bnxt_msix; 7938 } 7939 } 7940 7941 static void bnxt_setup_inta(struct bnxt *bp) 7942 { 7943 const int len = sizeof(bp->irq_tbl[0].name); 7944 7945 if (netdev_get_num_tc(bp->dev)) 7946 netdev_reset_tc(bp->dev); 7947 7948 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx", 7949 0); 7950 bp->irq_tbl[0].handler = bnxt_inta; 7951 } 7952 7953 static int bnxt_setup_int_mode(struct bnxt *bp) 7954 { 7955 int rc; 7956 7957 if (bp->flags & BNXT_FLAG_USING_MSIX) 7958 bnxt_setup_msix(bp); 7959 else 7960 bnxt_setup_inta(bp); 7961 7962 rc = bnxt_set_real_num_queues(bp); 7963 return rc; 7964 } 7965 7966 #ifdef CONFIG_RFS_ACCEL 7967 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp) 7968 { 7969 return bp->hw_resc.max_rsscos_ctxs; 7970 } 7971 7972 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp) 7973 { 7974 return bp->hw_resc.max_vnics; 7975 } 7976 #endif 7977 7978 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp) 7979 { 7980 return bp->hw_resc.max_stat_ctxs; 7981 } 7982 7983 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp) 7984 { 7985 return bp->hw_resc.max_cp_rings; 7986 } 7987 7988 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp) 7989 { 7990 unsigned int cp = bp->hw_resc.max_cp_rings; 7991 7992 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 7993 cp -= bnxt_get_ulp_msix_num(bp); 7994 7995 return cp; 7996 } 7997 7998 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp) 7999 { 8000 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 8001 8002 if (bp->flags & BNXT_FLAG_CHIP_P5) 8003 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs); 8004 8005 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings); 8006 } 8007 8008 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs) 8009 { 8010 bp->hw_resc.max_irqs = max_irqs; 8011 } 8012 8013 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp) 8014 { 8015 unsigned int cp; 8016 8017 cp = bnxt_get_max_func_cp_rings_for_en(bp); 8018 if (bp->flags & BNXT_FLAG_CHIP_P5) 8019 return cp - bp->rx_nr_rings - bp->tx_nr_rings; 8020 else 8021 return cp - bp->cp_nr_rings; 8022 } 8023 8024 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp) 8025 { 8026 return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp); 8027 } 8028 8029 int bnxt_get_avail_msix(struct bnxt *bp, int num) 8030 { 8031 int max_cp = bnxt_get_max_func_cp_rings(bp); 8032 int max_irq = bnxt_get_max_func_irqs(bp); 8033 int total_req = bp->cp_nr_rings + num; 8034 int max_idx, avail_msix; 8035 8036 max_idx = bp->total_irqs; 8037 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 8038 max_idx = min_t(int, bp->total_irqs, max_cp); 8039 avail_msix = max_idx - bp->cp_nr_rings; 8040 if (!BNXT_NEW_RM(bp) || avail_msix >= num) 8041 return avail_msix; 8042 8043 if (max_irq < total_req) { 8044 num = max_irq - bp->cp_nr_rings; 8045 if (num <= 0) 8046 return 0; 8047 } 8048 return num; 8049 } 8050 8051 static int bnxt_get_num_msix(struct bnxt *bp) 8052 { 8053 if (!BNXT_NEW_RM(bp)) 8054 return bnxt_get_max_func_irqs(bp); 8055 8056 return bnxt_nq_rings_in_use(bp); 8057 } 8058 8059 static int bnxt_init_msix(struct bnxt *bp) 8060 { 8061 int i, total_vecs, max, rc = 0, min = 1, ulp_msix; 8062 struct msix_entry *msix_ent; 8063 8064 total_vecs = bnxt_get_num_msix(bp); 8065 max = bnxt_get_max_func_irqs(bp); 8066 if (total_vecs > max) 8067 total_vecs = max; 8068 8069 if (!total_vecs) 8070 return 0; 8071 8072 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL); 8073 if (!msix_ent) 8074 return -ENOMEM; 8075 8076 for (i = 0; i < total_vecs; i++) { 8077 msix_ent[i].entry = i; 8078 msix_ent[i].vector = 0; 8079 } 8080 8081 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 8082 min = 2; 8083 8084 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs); 8085 ulp_msix = bnxt_get_ulp_msix_num(bp); 8086 if (total_vecs < 0 || total_vecs < ulp_msix) { 8087 rc = -ENODEV; 8088 goto msix_setup_exit; 8089 } 8090 8091 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL); 8092 if (bp->irq_tbl) { 8093 for (i = 0; i < total_vecs; i++) 8094 bp->irq_tbl[i].vector = msix_ent[i].vector; 8095 8096 bp->total_irqs = total_vecs; 8097 /* Trim rings based upon num of vectors allocated */ 8098 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings, 8099 total_vecs - ulp_msix, min == 1); 8100 if (rc) 8101 goto msix_setup_exit; 8102 8103 bp->cp_nr_rings = (min == 1) ? 8104 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 8105 bp->tx_nr_rings + bp->rx_nr_rings; 8106 8107 } else { 8108 rc = -ENOMEM; 8109 goto msix_setup_exit; 8110 } 8111 bp->flags |= BNXT_FLAG_USING_MSIX; 8112 kfree(msix_ent); 8113 return 0; 8114 8115 msix_setup_exit: 8116 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc); 8117 kfree(bp->irq_tbl); 8118 bp->irq_tbl = NULL; 8119 pci_disable_msix(bp->pdev); 8120 kfree(msix_ent); 8121 return rc; 8122 } 8123 8124 static int bnxt_init_inta(struct bnxt *bp) 8125 { 8126 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL); 8127 if (!bp->irq_tbl) 8128 return -ENOMEM; 8129 8130 bp->total_irqs = 1; 8131 bp->rx_nr_rings = 1; 8132 bp->tx_nr_rings = 1; 8133 bp->cp_nr_rings = 1; 8134 bp->flags |= BNXT_FLAG_SHARED_RINGS; 8135 bp->irq_tbl[0].vector = bp->pdev->irq; 8136 return 0; 8137 } 8138 8139 static int bnxt_init_int_mode(struct bnxt *bp) 8140 { 8141 int rc = 0; 8142 8143 if (bp->flags & BNXT_FLAG_MSIX_CAP) 8144 rc = bnxt_init_msix(bp); 8145 8146 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) { 8147 /* fallback to INTA */ 8148 rc = bnxt_init_inta(bp); 8149 } 8150 return rc; 8151 } 8152 8153 static void bnxt_clear_int_mode(struct bnxt *bp) 8154 { 8155 if (bp->flags & BNXT_FLAG_USING_MSIX) 8156 pci_disable_msix(bp->pdev); 8157 8158 kfree(bp->irq_tbl); 8159 bp->irq_tbl = NULL; 8160 bp->flags &= ~BNXT_FLAG_USING_MSIX; 8161 } 8162 8163 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init) 8164 { 8165 int tcs = netdev_get_num_tc(bp->dev); 8166 bool irq_cleared = false; 8167 int rc; 8168 8169 if (!bnxt_need_reserve_rings(bp)) 8170 return 0; 8171 8172 if (irq_re_init && BNXT_NEW_RM(bp) && 8173 bnxt_get_num_msix(bp) != bp->total_irqs) { 8174 bnxt_ulp_irq_stop(bp); 8175 bnxt_clear_int_mode(bp); 8176 irq_cleared = true; 8177 } 8178 rc = __bnxt_reserve_rings(bp); 8179 if (irq_cleared) { 8180 if (!rc) 8181 rc = bnxt_init_int_mode(bp); 8182 bnxt_ulp_irq_restart(bp, rc); 8183 } 8184 if (rc) { 8185 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc); 8186 return rc; 8187 } 8188 if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) { 8189 netdev_err(bp->dev, "tx ring reservation failure\n"); 8190 netdev_reset_tc(bp->dev); 8191 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 8192 return -ENOMEM; 8193 } 8194 return 0; 8195 } 8196 8197 static void bnxt_free_irq(struct bnxt *bp) 8198 { 8199 struct bnxt_irq *irq; 8200 int i; 8201 8202 #ifdef CONFIG_RFS_ACCEL 8203 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap); 8204 bp->dev->rx_cpu_rmap = NULL; 8205 #endif 8206 if (!bp->irq_tbl || !bp->bnapi) 8207 return; 8208 8209 for (i = 0; i < bp->cp_nr_rings; i++) { 8210 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 8211 8212 irq = &bp->irq_tbl[map_idx]; 8213 if (irq->requested) { 8214 if (irq->have_cpumask) { 8215 irq_set_affinity_hint(irq->vector, NULL); 8216 free_cpumask_var(irq->cpu_mask); 8217 irq->have_cpumask = 0; 8218 } 8219 free_irq(irq->vector, bp->bnapi[i]); 8220 } 8221 8222 irq->requested = 0; 8223 } 8224 } 8225 8226 static int bnxt_request_irq(struct bnxt *bp) 8227 { 8228 int i, j, rc = 0; 8229 unsigned long flags = 0; 8230 #ifdef CONFIG_RFS_ACCEL 8231 struct cpu_rmap *rmap; 8232 #endif 8233 8234 rc = bnxt_setup_int_mode(bp); 8235 if (rc) { 8236 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n", 8237 rc); 8238 return rc; 8239 } 8240 #ifdef CONFIG_RFS_ACCEL 8241 rmap = bp->dev->rx_cpu_rmap; 8242 #endif 8243 if (!(bp->flags & BNXT_FLAG_USING_MSIX)) 8244 flags = IRQF_SHARED; 8245 8246 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) { 8247 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 8248 struct bnxt_irq *irq = &bp->irq_tbl[map_idx]; 8249 8250 #ifdef CONFIG_RFS_ACCEL 8251 if (rmap && bp->bnapi[i]->rx_ring) { 8252 rc = irq_cpu_rmap_add(rmap, irq->vector); 8253 if (rc) 8254 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n", 8255 j); 8256 j++; 8257 } 8258 #endif 8259 rc = request_irq(irq->vector, irq->handler, flags, irq->name, 8260 bp->bnapi[i]); 8261 if (rc) 8262 break; 8263 8264 irq->requested = 1; 8265 8266 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) { 8267 int numa_node = dev_to_node(&bp->pdev->dev); 8268 8269 irq->have_cpumask = 1; 8270 cpumask_set_cpu(cpumask_local_spread(i, numa_node), 8271 irq->cpu_mask); 8272 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask); 8273 if (rc) { 8274 netdev_warn(bp->dev, 8275 "Set affinity failed, IRQ = %d\n", 8276 irq->vector); 8277 break; 8278 } 8279 } 8280 } 8281 return rc; 8282 } 8283 8284 static void bnxt_del_napi(struct bnxt *bp) 8285 { 8286 int i; 8287 8288 if (!bp->bnapi) 8289 return; 8290 8291 for (i = 0; i < bp->cp_nr_rings; i++) { 8292 struct bnxt_napi *bnapi = bp->bnapi[i]; 8293 8294 napi_hash_del(&bnapi->napi); 8295 netif_napi_del(&bnapi->napi); 8296 } 8297 /* We called napi_hash_del() before netif_napi_del(), we need 8298 * to respect an RCU grace period before freeing napi structures. 8299 */ 8300 synchronize_net(); 8301 } 8302 8303 static void bnxt_init_napi(struct bnxt *bp) 8304 { 8305 int i; 8306 unsigned int cp_nr_rings = bp->cp_nr_rings; 8307 struct bnxt_napi *bnapi; 8308 8309 if (bp->flags & BNXT_FLAG_USING_MSIX) { 8310 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll; 8311 8312 if (bp->flags & BNXT_FLAG_CHIP_P5) 8313 poll_fn = bnxt_poll_p5; 8314 else if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 8315 cp_nr_rings--; 8316 for (i = 0; i < cp_nr_rings; i++) { 8317 bnapi = bp->bnapi[i]; 8318 netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64); 8319 } 8320 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 8321 bnapi = bp->bnapi[cp_nr_rings]; 8322 netif_napi_add(bp->dev, &bnapi->napi, 8323 bnxt_poll_nitroa0, 64); 8324 } 8325 } else { 8326 bnapi = bp->bnapi[0]; 8327 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64); 8328 } 8329 } 8330 8331 static void bnxt_disable_napi(struct bnxt *bp) 8332 { 8333 int i; 8334 8335 if (!bp->bnapi) 8336 return; 8337 8338 for (i = 0; i < bp->cp_nr_rings; i++) { 8339 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 8340 8341 if (bp->bnapi[i]->rx_ring) 8342 cancel_work_sync(&cpr->dim.work); 8343 8344 napi_disable(&bp->bnapi[i]->napi); 8345 } 8346 } 8347 8348 static void bnxt_enable_napi(struct bnxt *bp) 8349 { 8350 int i; 8351 8352 for (i = 0; i < bp->cp_nr_rings; i++) { 8353 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 8354 bp->bnapi[i]->in_reset = false; 8355 8356 if (bp->bnapi[i]->rx_ring) { 8357 INIT_WORK(&cpr->dim.work, bnxt_dim_work); 8358 cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 8359 } 8360 napi_enable(&bp->bnapi[i]->napi); 8361 } 8362 } 8363 8364 void bnxt_tx_disable(struct bnxt *bp) 8365 { 8366 int i; 8367 struct bnxt_tx_ring_info *txr; 8368 8369 if (bp->tx_ring) { 8370 for (i = 0; i < bp->tx_nr_rings; i++) { 8371 txr = &bp->tx_ring[i]; 8372 txr->dev_state = BNXT_DEV_STATE_CLOSING; 8373 } 8374 } 8375 /* Stop all TX queues */ 8376 netif_tx_disable(bp->dev); 8377 netif_carrier_off(bp->dev); 8378 } 8379 8380 void bnxt_tx_enable(struct bnxt *bp) 8381 { 8382 int i; 8383 struct bnxt_tx_ring_info *txr; 8384 8385 for (i = 0; i < bp->tx_nr_rings; i++) { 8386 txr = &bp->tx_ring[i]; 8387 txr->dev_state = 0; 8388 } 8389 netif_tx_wake_all_queues(bp->dev); 8390 if (bp->link_info.link_up) 8391 netif_carrier_on(bp->dev); 8392 } 8393 8394 static void bnxt_report_link(struct bnxt *bp) 8395 { 8396 if (bp->link_info.link_up) { 8397 const char *duplex; 8398 const char *flow_ctrl; 8399 u32 speed; 8400 u16 fec; 8401 8402 netif_carrier_on(bp->dev); 8403 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL) 8404 duplex = "full"; 8405 else 8406 duplex = "half"; 8407 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH) 8408 flow_ctrl = "ON - receive & transmit"; 8409 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX) 8410 flow_ctrl = "ON - transmit"; 8411 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX) 8412 flow_ctrl = "ON - receive"; 8413 else 8414 flow_ctrl = "none"; 8415 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed); 8416 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n", 8417 speed, duplex, flow_ctrl); 8418 if (bp->flags & BNXT_FLAG_EEE_CAP) 8419 netdev_info(bp->dev, "EEE is %s\n", 8420 bp->eee.eee_active ? "active" : 8421 "not active"); 8422 fec = bp->link_info.fec_cfg; 8423 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED)) 8424 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n", 8425 (fec & BNXT_FEC_AUTONEG) ? "on" : "off", 8426 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" : 8427 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None"); 8428 } else { 8429 netif_carrier_off(bp->dev); 8430 netdev_err(bp->dev, "NIC Link is Down\n"); 8431 } 8432 } 8433 8434 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp) 8435 { 8436 int rc = 0; 8437 struct hwrm_port_phy_qcaps_input req = {0}; 8438 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 8439 struct bnxt_link_info *link_info = &bp->link_info; 8440 8441 bp->flags &= ~BNXT_FLAG_EEE_CAP; 8442 if (bp->test_info) 8443 bp->test_info->flags &= ~(BNXT_TEST_FL_EXT_LPBK | 8444 BNXT_TEST_FL_AN_PHY_LPBK); 8445 if (bp->hwrm_spec_code < 0x10201) 8446 return 0; 8447 8448 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1); 8449 8450 mutex_lock(&bp->hwrm_cmd_lock); 8451 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8452 if (rc) 8453 goto hwrm_phy_qcaps_exit; 8454 8455 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) { 8456 struct ethtool_eee *eee = &bp->eee; 8457 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode); 8458 8459 bp->flags |= BNXT_FLAG_EEE_CAP; 8460 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 8461 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) & 8462 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK; 8463 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) & 8464 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK; 8465 } 8466 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) { 8467 if (bp->test_info) 8468 bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK; 8469 } 8470 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED) { 8471 if (bp->test_info) 8472 bp->test_info->flags |= BNXT_TEST_FL_AN_PHY_LPBK; 8473 } 8474 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED) { 8475 if (BNXT_PF(bp)) 8476 bp->fw_cap |= BNXT_FW_CAP_SHARED_PORT_CFG; 8477 } 8478 if (resp->supported_speeds_auto_mode) 8479 link_info->support_auto_speeds = 8480 le16_to_cpu(resp->supported_speeds_auto_mode); 8481 8482 bp->port_count = resp->port_cnt; 8483 8484 hwrm_phy_qcaps_exit: 8485 mutex_unlock(&bp->hwrm_cmd_lock); 8486 return rc; 8487 } 8488 8489 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state) 8490 { 8491 int rc = 0; 8492 struct bnxt_link_info *link_info = &bp->link_info; 8493 struct hwrm_port_phy_qcfg_input req = {0}; 8494 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 8495 u8 link_up = link_info->link_up; 8496 u16 diff; 8497 8498 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1); 8499 8500 mutex_lock(&bp->hwrm_cmd_lock); 8501 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8502 if (rc) { 8503 mutex_unlock(&bp->hwrm_cmd_lock); 8504 return rc; 8505 } 8506 8507 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp)); 8508 link_info->phy_link_status = resp->link; 8509 link_info->duplex = resp->duplex_cfg; 8510 if (bp->hwrm_spec_code >= 0x10800) 8511 link_info->duplex = resp->duplex_state; 8512 link_info->pause = resp->pause; 8513 link_info->auto_mode = resp->auto_mode; 8514 link_info->auto_pause_setting = resp->auto_pause; 8515 link_info->lp_pause = resp->link_partner_adv_pause; 8516 link_info->force_pause_setting = resp->force_pause; 8517 link_info->duplex_setting = resp->duplex_cfg; 8518 if (link_info->phy_link_status == BNXT_LINK_LINK) 8519 link_info->link_speed = le16_to_cpu(resp->link_speed); 8520 else 8521 link_info->link_speed = 0; 8522 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed); 8523 link_info->support_speeds = le16_to_cpu(resp->support_speeds); 8524 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask); 8525 link_info->lp_auto_link_speeds = 8526 le16_to_cpu(resp->link_partner_adv_speeds); 8527 link_info->preemphasis = le32_to_cpu(resp->preemphasis); 8528 link_info->phy_ver[0] = resp->phy_maj; 8529 link_info->phy_ver[1] = resp->phy_min; 8530 link_info->phy_ver[2] = resp->phy_bld; 8531 link_info->media_type = resp->media_type; 8532 link_info->phy_type = resp->phy_type; 8533 link_info->transceiver = resp->xcvr_pkg_type; 8534 link_info->phy_addr = resp->eee_config_phy_addr & 8535 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK; 8536 link_info->module_status = resp->module_status; 8537 8538 if (bp->flags & BNXT_FLAG_EEE_CAP) { 8539 struct ethtool_eee *eee = &bp->eee; 8540 u16 fw_speeds; 8541 8542 eee->eee_active = 0; 8543 if (resp->eee_config_phy_addr & 8544 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) { 8545 eee->eee_active = 1; 8546 fw_speeds = le16_to_cpu( 8547 resp->link_partner_adv_eee_link_speed_mask); 8548 eee->lp_advertised = 8549 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 8550 } 8551 8552 /* Pull initial EEE config */ 8553 if (!chng_link_state) { 8554 if (resp->eee_config_phy_addr & 8555 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED) 8556 eee->eee_enabled = 1; 8557 8558 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask); 8559 eee->advertised = 8560 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 8561 8562 if (resp->eee_config_phy_addr & 8563 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) { 8564 __le32 tmr; 8565 8566 eee->tx_lpi_enabled = 1; 8567 tmr = resp->xcvr_identifier_type_tx_lpi_timer; 8568 eee->tx_lpi_timer = le32_to_cpu(tmr) & 8569 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK; 8570 } 8571 } 8572 } 8573 8574 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED; 8575 if (bp->hwrm_spec_code >= 0x10504) 8576 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg); 8577 8578 /* TODO: need to add more logic to report VF link */ 8579 if (chng_link_state) { 8580 if (link_info->phy_link_status == BNXT_LINK_LINK) 8581 link_info->link_up = 1; 8582 else 8583 link_info->link_up = 0; 8584 if (link_up != link_info->link_up) 8585 bnxt_report_link(bp); 8586 } else { 8587 /* alwasy link down if not require to update link state */ 8588 link_info->link_up = 0; 8589 } 8590 mutex_unlock(&bp->hwrm_cmd_lock); 8591 8592 if (!BNXT_PHY_CFG_ABLE(bp)) 8593 return 0; 8594 8595 diff = link_info->support_auto_speeds ^ link_info->advertising; 8596 if ((link_info->support_auto_speeds | diff) != 8597 link_info->support_auto_speeds) { 8598 /* An advertised speed is no longer supported, so we need to 8599 * update the advertisement settings. Caller holds RTNL 8600 * so we can modify link settings. 8601 */ 8602 link_info->advertising = link_info->support_auto_speeds; 8603 if (link_info->autoneg & BNXT_AUTONEG_SPEED) 8604 bnxt_hwrm_set_link_setting(bp, true, false); 8605 } 8606 return 0; 8607 } 8608 8609 static void bnxt_get_port_module_status(struct bnxt *bp) 8610 { 8611 struct bnxt_link_info *link_info = &bp->link_info; 8612 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp; 8613 u8 module_status; 8614 8615 if (bnxt_update_link(bp, true)) 8616 return; 8617 8618 module_status = link_info->module_status; 8619 switch (module_status) { 8620 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX: 8621 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 8622 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG: 8623 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n", 8624 bp->pf.port_id); 8625 if (bp->hwrm_spec_code >= 0x10201) { 8626 netdev_warn(bp->dev, "Module part number %s\n", 8627 resp->phy_vendor_partnumber); 8628 } 8629 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX) 8630 netdev_warn(bp->dev, "TX is disabled\n"); 8631 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN) 8632 netdev_warn(bp->dev, "SFP+ module is shutdown\n"); 8633 } 8634 } 8635 8636 static void 8637 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req) 8638 { 8639 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) { 8640 if (bp->hwrm_spec_code >= 0x10201) 8641 req->auto_pause = 8642 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 8643 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 8644 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX; 8645 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 8646 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX; 8647 req->enables |= 8648 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 8649 } else { 8650 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 8651 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX; 8652 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 8653 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX; 8654 req->enables |= 8655 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE); 8656 if (bp->hwrm_spec_code >= 0x10201) { 8657 req->auto_pause = req->force_pause; 8658 req->enables |= cpu_to_le32( 8659 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 8660 } 8661 } 8662 } 8663 8664 static void bnxt_hwrm_set_link_common(struct bnxt *bp, 8665 struct hwrm_port_phy_cfg_input *req) 8666 { 8667 u8 autoneg = bp->link_info.autoneg; 8668 u16 fw_link_speed = bp->link_info.req_link_speed; 8669 u16 advertising = bp->link_info.advertising; 8670 8671 if (autoneg & BNXT_AUTONEG_SPEED) { 8672 req->auto_mode |= 8673 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK; 8674 8675 req->enables |= cpu_to_le32( 8676 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK); 8677 req->auto_link_speed_mask = cpu_to_le16(advertising); 8678 8679 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE); 8680 req->flags |= 8681 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG); 8682 } else { 8683 req->force_link_speed = cpu_to_le16(fw_link_speed); 8684 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE); 8685 } 8686 8687 /* tell chimp that the setting takes effect immediately */ 8688 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 8689 } 8690 8691 int bnxt_hwrm_set_pause(struct bnxt *bp) 8692 { 8693 struct hwrm_port_phy_cfg_input req = {0}; 8694 int rc; 8695 8696 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 8697 bnxt_hwrm_set_pause_common(bp, &req); 8698 8699 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) || 8700 bp->link_info.force_link_chng) 8701 bnxt_hwrm_set_link_common(bp, &req); 8702 8703 mutex_lock(&bp->hwrm_cmd_lock); 8704 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8705 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) { 8706 /* since changing of pause setting doesn't trigger any link 8707 * change event, the driver needs to update the current pause 8708 * result upon successfully return of the phy_cfg command 8709 */ 8710 bp->link_info.pause = 8711 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl; 8712 bp->link_info.auto_pause_setting = 0; 8713 if (!bp->link_info.force_link_chng) 8714 bnxt_report_link(bp); 8715 } 8716 bp->link_info.force_link_chng = false; 8717 mutex_unlock(&bp->hwrm_cmd_lock); 8718 return rc; 8719 } 8720 8721 static void bnxt_hwrm_set_eee(struct bnxt *bp, 8722 struct hwrm_port_phy_cfg_input *req) 8723 { 8724 struct ethtool_eee *eee = &bp->eee; 8725 8726 if (eee->eee_enabled) { 8727 u16 eee_speeds; 8728 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE; 8729 8730 if (eee->tx_lpi_enabled) 8731 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE; 8732 else 8733 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE; 8734 8735 req->flags |= cpu_to_le32(flags); 8736 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised); 8737 req->eee_link_speed_mask = cpu_to_le16(eee_speeds); 8738 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer); 8739 } else { 8740 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE); 8741 } 8742 } 8743 8744 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee) 8745 { 8746 struct hwrm_port_phy_cfg_input req = {0}; 8747 8748 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 8749 if (set_pause) 8750 bnxt_hwrm_set_pause_common(bp, &req); 8751 8752 bnxt_hwrm_set_link_common(bp, &req); 8753 8754 if (set_eee) 8755 bnxt_hwrm_set_eee(bp, &req); 8756 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8757 } 8758 8759 static int bnxt_hwrm_shutdown_link(struct bnxt *bp) 8760 { 8761 struct hwrm_port_phy_cfg_input req = {0}; 8762 8763 if (!BNXT_SINGLE_PF(bp)) 8764 return 0; 8765 8766 if (pci_num_vf(bp->pdev)) 8767 return 0; 8768 8769 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 8770 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN); 8771 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8772 } 8773 8774 static int bnxt_fw_init_one(struct bnxt *bp); 8775 8776 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up) 8777 { 8778 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr; 8779 struct hwrm_func_drv_if_change_input req = {0}; 8780 bool resc_reinit = false, fw_reset = false; 8781 u32 flags = 0; 8782 int rc; 8783 8784 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE)) 8785 return 0; 8786 8787 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1); 8788 if (up) 8789 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP); 8790 mutex_lock(&bp->hwrm_cmd_lock); 8791 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8792 if (!rc) 8793 flags = le32_to_cpu(resp->flags); 8794 mutex_unlock(&bp->hwrm_cmd_lock); 8795 if (rc) 8796 return rc; 8797 8798 if (!up) 8799 return 0; 8800 8801 if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE) 8802 resc_reinit = true; 8803 if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE) 8804 fw_reset = true; 8805 8806 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state) && !fw_reset) { 8807 netdev_err(bp->dev, "RESET_DONE not set during FW reset.\n"); 8808 return -ENODEV; 8809 } 8810 if (resc_reinit || fw_reset) { 8811 if (fw_reset) { 8812 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 8813 bnxt_ulp_stop(bp); 8814 bnxt_free_ctx_mem(bp); 8815 kfree(bp->ctx); 8816 bp->ctx = NULL; 8817 bnxt_dcb_free(bp); 8818 rc = bnxt_fw_init_one(bp); 8819 if (rc) { 8820 set_bit(BNXT_STATE_ABORT_ERR, &bp->state); 8821 return rc; 8822 } 8823 bnxt_clear_int_mode(bp); 8824 rc = bnxt_init_int_mode(bp); 8825 if (rc) { 8826 netdev_err(bp->dev, "init int mode failed\n"); 8827 return rc; 8828 } 8829 set_bit(BNXT_STATE_FW_RESET_DET, &bp->state); 8830 } 8831 if (BNXT_NEW_RM(bp)) { 8832 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 8833 8834 rc = bnxt_hwrm_func_resc_qcaps(bp, true); 8835 hw_resc->resv_cp_rings = 0; 8836 hw_resc->resv_stat_ctxs = 0; 8837 hw_resc->resv_irqs = 0; 8838 hw_resc->resv_tx_rings = 0; 8839 hw_resc->resv_rx_rings = 0; 8840 hw_resc->resv_hw_ring_grps = 0; 8841 hw_resc->resv_vnics = 0; 8842 if (!fw_reset) { 8843 bp->tx_nr_rings = 0; 8844 bp->rx_nr_rings = 0; 8845 } 8846 } 8847 } 8848 return 0; 8849 } 8850 8851 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp) 8852 { 8853 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 8854 struct hwrm_port_led_qcaps_input req = {0}; 8855 struct bnxt_pf_info *pf = &bp->pf; 8856 int rc; 8857 8858 bp->num_leds = 0; 8859 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601) 8860 return 0; 8861 8862 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1); 8863 req.port_id = cpu_to_le16(pf->port_id); 8864 mutex_lock(&bp->hwrm_cmd_lock); 8865 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8866 if (rc) { 8867 mutex_unlock(&bp->hwrm_cmd_lock); 8868 return rc; 8869 } 8870 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) { 8871 int i; 8872 8873 bp->num_leds = resp->num_leds; 8874 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) * 8875 bp->num_leds); 8876 for (i = 0; i < bp->num_leds; i++) { 8877 struct bnxt_led_info *led = &bp->leds[i]; 8878 __le16 caps = led->led_state_caps; 8879 8880 if (!led->led_group_id || 8881 !BNXT_LED_ALT_BLINK_CAP(caps)) { 8882 bp->num_leds = 0; 8883 break; 8884 } 8885 } 8886 } 8887 mutex_unlock(&bp->hwrm_cmd_lock); 8888 return 0; 8889 } 8890 8891 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp) 8892 { 8893 struct hwrm_wol_filter_alloc_input req = {0}; 8894 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; 8895 int rc; 8896 8897 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1); 8898 req.port_id = cpu_to_le16(bp->pf.port_id); 8899 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT; 8900 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS); 8901 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN); 8902 mutex_lock(&bp->hwrm_cmd_lock); 8903 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8904 if (!rc) 8905 bp->wol_filter_id = resp->wol_filter_id; 8906 mutex_unlock(&bp->hwrm_cmd_lock); 8907 return rc; 8908 } 8909 8910 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp) 8911 { 8912 struct hwrm_wol_filter_free_input req = {0}; 8913 8914 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1); 8915 req.port_id = cpu_to_le16(bp->pf.port_id); 8916 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID); 8917 req.wol_filter_id = bp->wol_filter_id; 8918 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8919 } 8920 8921 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle) 8922 { 8923 struct hwrm_wol_filter_qcfg_input req = {0}; 8924 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 8925 u16 next_handle = 0; 8926 int rc; 8927 8928 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1); 8929 req.port_id = cpu_to_le16(bp->pf.port_id); 8930 req.handle = cpu_to_le16(handle); 8931 mutex_lock(&bp->hwrm_cmd_lock); 8932 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8933 if (!rc) { 8934 next_handle = le16_to_cpu(resp->next_handle); 8935 if (next_handle != 0) { 8936 if (resp->wol_type == 8937 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) { 8938 bp->wol = 1; 8939 bp->wol_filter_id = resp->wol_filter_id; 8940 } 8941 } 8942 } 8943 mutex_unlock(&bp->hwrm_cmd_lock); 8944 return next_handle; 8945 } 8946 8947 static void bnxt_get_wol_settings(struct bnxt *bp) 8948 { 8949 u16 handle = 0; 8950 8951 bp->wol = 0; 8952 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP)) 8953 return; 8954 8955 do { 8956 handle = bnxt_hwrm_get_wol_fltrs(bp, handle); 8957 } while (handle && handle != 0xffff); 8958 } 8959 8960 #ifdef CONFIG_BNXT_HWMON 8961 static ssize_t bnxt_show_temp(struct device *dev, 8962 struct device_attribute *devattr, char *buf) 8963 { 8964 struct hwrm_temp_monitor_query_input req = {0}; 8965 struct hwrm_temp_monitor_query_output *resp; 8966 struct bnxt *bp = dev_get_drvdata(dev); 8967 u32 temp = 0; 8968 8969 resp = bp->hwrm_cmd_resp_addr; 8970 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1); 8971 mutex_lock(&bp->hwrm_cmd_lock); 8972 if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT)) 8973 temp = resp->temp * 1000; /* display millidegree */ 8974 mutex_unlock(&bp->hwrm_cmd_lock); 8975 8976 return sprintf(buf, "%u\n", temp); 8977 } 8978 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0); 8979 8980 static struct attribute *bnxt_attrs[] = { 8981 &sensor_dev_attr_temp1_input.dev_attr.attr, 8982 NULL 8983 }; 8984 ATTRIBUTE_GROUPS(bnxt); 8985 8986 static void bnxt_hwmon_close(struct bnxt *bp) 8987 { 8988 if (bp->hwmon_dev) { 8989 hwmon_device_unregister(bp->hwmon_dev); 8990 bp->hwmon_dev = NULL; 8991 } 8992 } 8993 8994 static void bnxt_hwmon_open(struct bnxt *bp) 8995 { 8996 struct pci_dev *pdev = bp->pdev; 8997 8998 if (bp->hwmon_dev) 8999 return; 9000 9001 bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, 9002 DRV_MODULE_NAME, bp, 9003 bnxt_groups); 9004 if (IS_ERR(bp->hwmon_dev)) { 9005 bp->hwmon_dev = NULL; 9006 dev_warn(&pdev->dev, "Cannot register hwmon device\n"); 9007 } 9008 } 9009 #else 9010 static void bnxt_hwmon_close(struct bnxt *bp) 9011 { 9012 } 9013 9014 static void bnxt_hwmon_open(struct bnxt *bp) 9015 { 9016 } 9017 #endif 9018 9019 static bool bnxt_eee_config_ok(struct bnxt *bp) 9020 { 9021 struct ethtool_eee *eee = &bp->eee; 9022 struct bnxt_link_info *link_info = &bp->link_info; 9023 9024 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 9025 return true; 9026 9027 if (eee->eee_enabled) { 9028 u32 advertising = 9029 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 9030 9031 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 9032 eee->eee_enabled = 0; 9033 return false; 9034 } 9035 if (eee->advertised & ~advertising) { 9036 eee->advertised = advertising & eee->supported; 9037 return false; 9038 } 9039 } 9040 return true; 9041 } 9042 9043 static int bnxt_update_phy_setting(struct bnxt *bp) 9044 { 9045 int rc; 9046 bool update_link = false; 9047 bool update_pause = false; 9048 bool update_eee = false; 9049 struct bnxt_link_info *link_info = &bp->link_info; 9050 9051 rc = bnxt_update_link(bp, true); 9052 if (rc) { 9053 netdev_err(bp->dev, "failed to update link (rc: %x)\n", 9054 rc); 9055 return rc; 9056 } 9057 if (!BNXT_SINGLE_PF(bp)) 9058 return 0; 9059 9060 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 9061 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) != 9062 link_info->req_flow_ctrl) 9063 update_pause = true; 9064 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 9065 link_info->force_pause_setting != link_info->req_flow_ctrl) 9066 update_pause = true; 9067 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 9068 if (BNXT_AUTO_MODE(link_info->auto_mode)) 9069 update_link = true; 9070 if (link_info->req_link_speed != link_info->force_link_speed) 9071 update_link = true; 9072 if (link_info->req_duplex != link_info->duplex_setting) 9073 update_link = true; 9074 } else { 9075 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE) 9076 update_link = true; 9077 if (link_info->advertising != link_info->auto_link_speeds) 9078 update_link = true; 9079 } 9080 9081 /* The last close may have shutdown the link, so need to call 9082 * PHY_CFG to bring it back up. 9083 */ 9084 if (!bp->link_info.link_up) 9085 update_link = true; 9086 9087 if (!bnxt_eee_config_ok(bp)) 9088 update_eee = true; 9089 9090 if (update_link) 9091 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee); 9092 else if (update_pause) 9093 rc = bnxt_hwrm_set_pause(bp); 9094 if (rc) { 9095 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n", 9096 rc); 9097 return rc; 9098 } 9099 9100 return rc; 9101 } 9102 9103 /* Common routine to pre-map certain register block to different GRC window. 9104 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows 9105 * in PF and 3 windows in VF that can be customized to map in different 9106 * register blocks. 9107 */ 9108 static void bnxt_preset_reg_win(struct bnxt *bp) 9109 { 9110 if (BNXT_PF(bp)) { 9111 /* CAG registers map to GRC window #4 */ 9112 writel(BNXT_CAG_REG_BASE, 9113 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12); 9114 } 9115 } 9116 9117 static int bnxt_init_dflt_ring_mode(struct bnxt *bp); 9118 9119 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 9120 { 9121 int rc = 0; 9122 9123 bnxt_preset_reg_win(bp); 9124 netif_carrier_off(bp->dev); 9125 if (irq_re_init) { 9126 /* Reserve rings now if none were reserved at driver probe. */ 9127 rc = bnxt_init_dflt_ring_mode(bp); 9128 if (rc) { 9129 netdev_err(bp->dev, "Failed to reserve default rings at open\n"); 9130 return rc; 9131 } 9132 } 9133 rc = bnxt_reserve_rings(bp, irq_re_init); 9134 if (rc) 9135 return rc; 9136 if ((bp->flags & BNXT_FLAG_RFS) && 9137 !(bp->flags & BNXT_FLAG_USING_MSIX)) { 9138 /* disable RFS if falling back to INTA */ 9139 bp->dev->hw_features &= ~NETIF_F_NTUPLE; 9140 bp->flags &= ~BNXT_FLAG_RFS; 9141 } 9142 9143 rc = bnxt_alloc_mem(bp, irq_re_init); 9144 if (rc) { 9145 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 9146 goto open_err_free_mem; 9147 } 9148 9149 if (irq_re_init) { 9150 bnxt_init_napi(bp); 9151 rc = bnxt_request_irq(bp); 9152 if (rc) { 9153 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc); 9154 goto open_err_irq; 9155 } 9156 } 9157 9158 bnxt_enable_napi(bp); 9159 bnxt_debug_dev_init(bp); 9160 9161 rc = bnxt_init_nic(bp, irq_re_init); 9162 if (rc) { 9163 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 9164 goto open_err; 9165 } 9166 9167 if (link_re_init) { 9168 mutex_lock(&bp->link_lock); 9169 rc = bnxt_update_phy_setting(bp); 9170 mutex_unlock(&bp->link_lock); 9171 if (rc) { 9172 netdev_warn(bp->dev, "failed to update phy settings\n"); 9173 if (BNXT_SINGLE_PF(bp)) { 9174 bp->link_info.phy_retry = true; 9175 bp->link_info.phy_retry_expires = 9176 jiffies + 5 * HZ; 9177 } 9178 } 9179 } 9180 9181 if (irq_re_init) 9182 udp_tunnel_get_rx_info(bp->dev); 9183 9184 set_bit(BNXT_STATE_OPEN, &bp->state); 9185 bnxt_enable_int(bp); 9186 /* Enable TX queues */ 9187 bnxt_tx_enable(bp); 9188 mod_timer(&bp->timer, jiffies + bp->current_interval); 9189 /* Poll link status and check for SFP+ module status */ 9190 bnxt_get_port_module_status(bp); 9191 9192 /* VF-reps may need to be re-opened after the PF is re-opened */ 9193 if (BNXT_PF(bp)) 9194 bnxt_vf_reps_open(bp); 9195 return 0; 9196 9197 open_err: 9198 bnxt_debug_dev_exit(bp); 9199 bnxt_disable_napi(bp); 9200 9201 open_err_irq: 9202 bnxt_del_napi(bp); 9203 9204 open_err_free_mem: 9205 bnxt_free_skbs(bp); 9206 bnxt_free_irq(bp); 9207 bnxt_free_mem(bp, true); 9208 return rc; 9209 } 9210 9211 /* rtnl_lock held */ 9212 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 9213 { 9214 int rc = 0; 9215 9216 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init); 9217 if (rc) { 9218 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc); 9219 dev_close(bp->dev); 9220 } 9221 return rc; 9222 } 9223 9224 /* rtnl_lock held, open the NIC half way by allocating all resources, but 9225 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline 9226 * self tests. 9227 */ 9228 int bnxt_half_open_nic(struct bnxt *bp) 9229 { 9230 int rc = 0; 9231 9232 rc = bnxt_alloc_mem(bp, false); 9233 if (rc) { 9234 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 9235 goto half_open_err; 9236 } 9237 rc = bnxt_init_nic(bp, false); 9238 if (rc) { 9239 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 9240 goto half_open_err; 9241 } 9242 return 0; 9243 9244 half_open_err: 9245 bnxt_free_skbs(bp); 9246 bnxt_free_mem(bp, false); 9247 dev_close(bp->dev); 9248 return rc; 9249 } 9250 9251 /* rtnl_lock held, this call can only be made after a previous successful 9252 * call to bnxt_half_open_nic(). 9253 */ 9254 void bnxt_half_close_nic(struct bnxt *bp) 9255 { 9256 bnxt_hwrm_resource_free(bp, false, false); 9257 bnxt_free_skbs(bp); 9258 bnxt_free_mem(bp, false); 9259 } 9260 9261 static void bnxt_reenable_sriov(struct bnxt *bp) 9262 { 9263 if (BNXT_PF(bp)) { 9264 struct bnxt_pf_info *pf = &bp->pf; 9265 int n = pf->active_vfs; 9266 9267 if (n) 9268 bnxt_cfg_hw_sriov(bp, &n, true); 9269 } 9270 } 9271 9272 static int bnxt_open(struct net_device *dev) 9273 { 9274 struct bnxt *bp = netdev_priv(dev); 9275 int rc; 9276 9277 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) { 9278 netdev_err(bp->dev, "A previous firmware reset did not complete, aborting\n"); 9279 return -ENODEV; 9280 } 9281 9282 rc = bnxt_hwrm_if_change(bp, true); 9283 if (rc) 9284 return rc; 9285 rc = __bnxt_open_nic(bp, true, true); 9286 if (rc) { 9287 bnxt_hwrm_if_change(bp, false); 9288 } else { 9289 if (test_and_clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) { 9290 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 9291 bnxt_ulp_start(bp, 0); 9292 bnxt_reenable_sriov(bp); 9293 } 9294 } 9295 bnxt_hwmon_open(bp); 9296 } 9297 9298 return rc; 9299 } 9300 9301 static bool bnxt_drv_busy(struct bnxt *bp) 9302 { 9303 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) || 9304 test_bit(BNXT_STATE_READ_STATS, &bp->state)); 9305 } 9306 9307 static void bnxt_get_ring_stats(struct bnxt *bp, 9308 struct rtnl_link_stats64 *stats); 9309 9310 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init, 9311 bool link_re_init) 9312 { 9313 /* Close the VF-reps before closing PF */ 9314 if (BNXT_PF(bp)) 9315 bnxt_vf_reps_close(bp); 9316 9317 /* Change device state to avoid TX queue wake up's */ 9318 bnxt_tx_disable(bp); 9319 9320 clear_bit(BNXT_STATE_OPEN, &bp->state); 9321 smp_mb__after_atomic(); 9322 while (bnxt_drv_busy(bp)) 9323 msleep(20); 9324 9325 /* Flush rings and and disable interrupts */ 9326 bnxt_shutdown_nic(bp, irq_re_init); 9327 9328 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */ 9329 9330 bnxt_debug_dev_exit(bp); 9331 bnxt_disable_napi(bp); 9332 del_timer_sync(&bp->timer); 9333 bnxt_free_skbs(bp); 9334 9335 /* Save ring stats before shutdown */ 9336 if (bp->bnapi) 9337 bnxt_get_ring_stats(bp, &bp->net_stats_prev); 9338 if (irq_re_init) { 9339 bnxt_free_irq(bp); 9340 bnxt_del_napi(bp); 9341 } 9342 bnxt_free_mem(bp, irq_re_init); 9343 } 9344 9345 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 9346 { 9347 int rc = 0; 9348 9349 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 9350 /* If we get here, it means firmware reset is in progress 9351 * while we are trying to close. We can safely proceed with 9352 * the close because we are holding rtnl_lock(). Some firmware 9353 * messages may fail as we proceed to close. We set the 9354 * ABORT_ERR flag here so that the FW reset thread will later 9355 * abort when it gets the rtnl_lock() and sees the flag. 9356 */ 9357 netdev_warn(bp->dev, "FW reset in progress during close, FW reset will be aborted\n"); 9358 set_bit(BNXT_STATE_ABORT_ERR, &bp->state); 9359 } 9360 9361 #ifdef CONFIG_BNXT_SRIOV 9362 if (bp->sriov_cfg) { 9363 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait, 9364 !bp->sriov_cfg, 9365 BNXT_SRIOV_CFG_WAIT_TMO); 9366 if (rc) 9367 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n"); 9368 } 9369 #endif 9370 __bnxt_close_nic(bp, irq_re_init, link_re_init); 9371 return rc; 9372 } 9373 9374 static int bnxt_close(struct net_device *dev) 9375 { 9376 struct bnxt *bp = netdev_priv(dev); 9377 9378 bnxt_hwmon_close(bp); 9379 bnxt_close_nic(bp, true, true); 9380 bnxt_hwrm_shutdown_link(bp); 9381 bnxt_hwrm_if_change(bp, false); 9382 return 0; 9383 } 9384 9385 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg, 9386 u16 *val) 9387 { 9388 struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr; 9389 struct hwrm_port_phy_mdio_read_input req = {0}; 9390 int rc; 9391 9392 if (bp->hwrm_spec_code < 0x10a00) 9393 return -EOPNOTSUPP; 9394 9395 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1); 9396 req.port_id = cpu_to_le16(bp->pf.port_id); 9397 req.phy_addr = phy_addr; 9398 req.reg_addr = cpu_to_le16(reg & 0x1f); 9399 if (mdio_phy_id_is_c45(phy_addr)) { 9400 req.cl45_mdio = 1; 9401 req.phy_addr = mdio_phy_id_prtad(phy_addr); 9402 req.dev_addr = mdio_phy_id_devad(phy_addr); 9403 req.reg_addr = cpu_to_le16(reg); 9404 } 9405 9406 mutex_lock(&bp->hwrm_cmd_lock); 9407 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 9408 if (!rc) 9409 *val = le16_to_cpu(resp->reg_data); 9410 mutex_unlock(&bp->hwrm_cmd_lock); 9411 return rc; 9412 } 9413 9414 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg, 9415 u16 val) 9416 { 9417 struct hwrm_port_phy_mdio_write_input req = {0}; 9418 9419 if (bp->hwrm_spec_code < 0x10a00) 9420 return -EOPNOTSUPP; 9421 9422 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1); 9423 req.port_id = cpu_to_le16(bp->pf.port_id); 9424 req.phy_addr = phy_addr; 9425 req.reg_addr = cpu_to_le16(reg & 0x1f); 9426 if (mdio_phy_id_is_c45(phy_addr)) { 9427 req.cl45_mdio = 1; 9428 req.phy_addr = mdio_phy_id_prtad(phy_addr); 9429 req.dev_addr = mdio_phy_id_devad(phy_addr); 9430 req.reg_addr = cpu_to_le16(reg); 9431 } 9432 req.reg_data = cpu_to_le16(val); 9433 9434 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 9435 } 9436 9437 /* rtnl_lock held */ 9438 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 9439 { 9440 struct mii_ioctl_data *mdio = if_mii(ifr); 9441 struct bnxt *bp = netdev_priv(dev); 9442 int rc; 9443 9444 switch (cmd) { 9445 case SIOCGMIIPHY: 9446 mdio->phy_id = bp->link_info.phy_addr; 9447 9448 /* fallthru */ 9449 case SIOCGMIIREG: { 9450 u16 mii_regval = 0; 9451 9452 if (!netif_running(dev)) 9453 return -EAGAIN; 9454 9455 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num, 9456 &mii_regval); 9457 mdio->val_out = mii_regval; 9458 return rc; 9459 } 9460 9461 case SIOCSMIIREG: 9462 if (!netif_running(dev)) 9463 return -EAGAIN; 9464 9465 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num, 9466 mdio->val_in); 9467 9468 default: 9469 /* do nothing */ 9470 break; 9471 } 9472 return -EOPNOTSUPP; 9473 } 9474 9475 static void bnxt_get_ring_stats(struct bnxt *bp, 9476 struct rtnl_link_stats64 *stats) 9477 { 9478 int i; 9479 9480 9481 for (i = 0; i < bp->cp_nr_rings; i++) { 9482 struct bnxt_napi *bnapi = bp->bnapi[i]; 9483 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 9484 struct ctx_hw_stats *hw_stats = cpr->hw_stats; 9485 9486 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts); 9487 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts); 9488 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts); 9489 9490 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts); 9491 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts); 9492 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts); 9493 9494 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes); 9495 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes); 9496 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes); 9497 9498 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes); 9499 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes); 9500 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes); 9501 9502 stats->rx_missed_errors += 9503 le64_to_cpu(hw_stats->rx_discard_pkts); 9504 9505 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts); 9506 9507 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts); 9508 } 9509 } 9510 9511 static void bnxt_add_prev_stats(struct bnxt *bp, 9512 struct rtnl_link_stats64 *stats) 9513 { 9514 struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev; 9515 9516 stats->rx_packets += prev_stats->rx_packets; 9517 stats->tx_packets += prev_stats->tx_packets; 9518 stats->rx_bytes += prev_stats->rx_bytes; 9519 stats->tx_bytes += prev_stats->tx_bytes; 9520 stats->rx_missed_errors += prev_stats->rx_missed_errors; 9521 stats->multicast += prev_stats->multicast; 9522 stats->tx_dropped += prev_stats->tx_dropped; 9523 } 9524 9525 static void 9526 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 9527 { 9528 struct bnxt *bp = netdev_priv(dev); 9529 9530 set_bit(BNXT_STATE_READ_STATS, &bp->state); 9531 /* Make sure bnxt_close_nic() sees that we are reading stats before 9532 * we check the BNXT_STATE_OPEN flag. 9533 */ 9534 smp_mb__after_atomic(); 9535 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 9536 clear_bit(BNXT_STATE_READ_STATS, &bp->state); 9537 *stats = bp->net_stats_prev; 9538 return; 9539 } 9540 9541 bnxt_get_ring_stats(bp, stats); 9542 bnxt_add_prev_stats(bp, stats); 9543 9544 if (bp->flags & BNXT_FLAG_PORT_STATS) { 9545 struct rx_port_stats *rx = bp->hw_rx_port_stats; 9546 struct tx_port_stats *tx = bp->hw_tx_port_stats; 9547 9548 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames); 9549 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames); 9550 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) + 9551 le64_to_cpu(rx->rx_ovrsz_frames) + 9552 le64_to_cpu(rx->rx_runt_frames); 9553 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) + 9554 le64_to_cpu(rx->rx_jbr_frames); 9555 stats->collisions = le64_to_cpu(tx->tx_total_collisions); 9556 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns); 9557 stats->tx_errors = le64_to_cpu(tx->tx_err); 9558 } 9559 clear_bit(BNXT_STATE_READ_STATS, &bp->state); 9560 } 9561 9562 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask) 9563 { 9564 struct net_device *dev = bp->dev; 9565 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 9566 struct netdev_hw_addr *ha; 9567 u8 *haddr; 9568 int mc_count = 0; 9569 bool update = false; 9570 int off = 0; 9571 9572 netdev_for_each_mc_addr(ha, dev) { 9573 if (mc_count >= BNXT_MAX_MC_ADDRS) { 9574 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 9575 vnic->mc_list_count = 0; 9576 return false; 9577 } 9578 haddr = ha->addr; 9579 if (!ether_addr_equal(haddr, vnic->mc_list + off)) { 9580 memcpy(vnic->mc_list + off, haddr, ETH_ALEN); 9581 update = true; 9582 } 9583 off += ETH_ALEN; 9584 mc_count++; 9585 } 9586 if (mc_count) 9587 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST; 9588 9589 if (mc_count != vnic->mc_list_count) { 9590 vnic->mc_list_count = mc_count; 9591 update = true; 9592 } 9593 return update; 9594 } 9595 9596 static bool bnxt_uc_list_updated(struct bnxt *bp) 9597 { 9598 struct net_device *dev = bp->dev; 9599 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 9600 struct netdev_hw_addr *ha; 9601 int off = 0; 9602 9603 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1)) 9604 return true; 9605 9606 netdev_for_each_uc_addr(ha, dev) { 9607 if (!ether_addr_equal(ha->addr, vnic->uc_list + off)) 9608 return true; 9609 9610 off += ETH_ALEN; 9611 } 9612 return false; 9613 } 9614 9615 static void bnxt_set_rx_mode(struct net_device *dev) 9616 { 9617 struct bnxt *bp = netdev_priv(dev); 9618 struct bnxt_vnic_info *vnic; 9619 bool mc_update = false; 9620 bool uc_update; 9621 u32 mask; 9622 9623 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) 9624 return; 9625 9626 vnic = &bp->vnic_info[0]; 9627 mask = vnic->rx_mask; 9628 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS | 9629 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST | 9630 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST | 9631 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST); 9632 9633 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) 9634 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 9635 9636 uc_update = bnxt_uc_list_updated(bp); 9637 9638 if (dev->flags & IFF_BROADCAST) 9639 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 9640 if (dev->flags & IFF_ALLMULTI) { 9641 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 9642 vnic->mc_list_count = 0; 9643 } else { 9644 mc_update = bnxt_mc_list_updated(bp, &mask); 9645 } 9646 9647 if (mask != vnic->rx_mask || uc_update || mc_update) { 9648 vnic->rx_mask = mask; 9649 9650 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event); 9651 bnxt_queue_sp_work(bp); 9652 } 9653 } 9654 9655 static int bnxt_cfg_rx_mode(struct bnxt *bp) 9656 { 9657 struct net_device *dev = bp->dev; 9658 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 9659 struct netdev_hw_addr *ha; 9660 int i, off = 0, rc; 9661 bool uc_update; 9662 9663 netif_addr_lock_bh(dev); 9664 uc_update = bnxt_uc_list_updated(bp); 9665 netif_addr_unlock_bh(dev); 9666 9667 if (!uc_update) 9668 goto skip_uc; 9669 9670 mutex_lock(&bp->hwrm_cmd_lock); 9671 for (i = 1; i < vnic->uc_filter_count; i++) { 9672 struct hwrm_cfa_l2_filter_free_input req = {0}; 9673 9674 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1, 9675 -1); 9676 9677 req.l2_filter_id = vnic->fw_l2_filter_id[i]; 9678 9679 rc = _hwrm_send_message(bp, &req, sizeof(req), 9680 HWRM_CMD_TIMEOUT); 9681 } 9682 mutex_unlock(&bp->hwrm_cmd_lock); 9683 9684 vnic->uc_filter_count = 1; 9685 9686 netif_addr_lock_bh(dev); 9687 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) { 9688 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 9689 } else { 9690 netdev_for_each_uc_addr(ha, dev) { 9691 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN); 9692 off += ETH_ALEN; 9693 vnic->uc_filter_count++; 9694 } 9695 } 9696 netif_addr_unlock_bh(dev); 9697 9698 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) { 9699 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off); 9700 if (rc) { 9701 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", 9702 rc); 9703 vnic->uc_filter_count = i; 9704 return rc; 9705 } 9706 } 9707 9708 skip_uc: 9709 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); 9710 if (rc && vnic->mc_list_count) { 9711 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n", 9712 rc); 9713 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 9714 vnic->mc_list_count = 0; 9715 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); 9716 } 9717 if (rc) 9718 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n", 9719 rc); 9720 9721 return rc; 9722 } 9723 9724 static bool bnxt_can_reserve_rings(struct bnxt *bp) 9725 { 9726 #ifdef CONFIG_BNXT_SRIOV 9727 if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) { 9728 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 9729 9730 /* No minimum rings were provisioned by the PF. Don't 9731 * reserve rings by default when device is down. 9732 */ 9733 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings) 9734 return true; 9735 9736 if (!netif_running(bp->dev)) 9737 return false; 9738 } 9739 #endif 9740 return true; 9741 } 9742 9743 /* If the chip and firmware supports RFS */ 9744 static bool bnxt_rfs_supported(struct bnxt *bp) 9745 { 9746 if (bp->flags & BNXT_FLAG_CHIP_P5) { 9747 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) 9748 return true; 9749 return false; 9750 } 9751 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) 9752 return true; 9753 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 9754 return true; 9755 return false; 9756 } 9757 9758 /* If runtime conditions support RFS */ 9759 static bool bnxt_rfs_capable(struct bnxt *bp) 9760 { 9761 #ifdef CONFIG_RFS_ACCEL 9762 int vnics, max_vnics, max_rss_ctxs; 9763 9764 if (bp->flags & BNXT_FLAG_CHIP_P5) 9765 return bnxt_rfs_supported(bp); 9766 if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp)) 9767 return false; 9768 9769 vnics = 1 + bp->rx_nr_rings; 9770 max_vnics = bnxt_get_max_func_vnics(bp); 9771 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp); 9772 9773 /* RSS contexts not a limiting factor */ 9774 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 9775 max_rss_ctxs = max_vnics; 9776 if (vnics > max_vnics || vnics > max_rss_ctxs) { 9777 if (bp->rx_nr_rings > 1) 9778 netdev_warn(bp->dev, 9779 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n", 9780 min(max_rss_ctxs - 1, max_vnics - 1)); 9781 return false; 9782 } 9783 9784 if (!BNXT_NEW_RM(bp)) 9785 return true; 9786 9787 if (vnics == bp->hw_resc.resv_vnics) 9788 return true; 9789 9790 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics); 9791 if (vnics <= bp->hw_resc.resv_vnics) 9792 return true; 9793 9794 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n"); 9795 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1); 9796 return false; 9797 #else 9798 return false; 9799 #endif 9800 } 9801 9802 static netdev_features_t bnxt_fix_features(struct net_device *dev, 9803 netdev_features_t features) 9804 { 9805 struct bnxt *bp = netdev_priv(dev); 9806 netdev_features_t vlan_features; 9807 9808 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp)) 9809 features &= ~NETIF_F_NTUPLE; 9810 9811 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 9812 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 9813 9814 if (!(features & NETIF_F_GRO)) 9815 features &= ~NETIF_F_GRO_HW; 9816 9817 if (features & NETIF_F_GRO_HW) 9818 features &= ~NETIF_F_LRO; 9819 9820 /* Both CTAG and STAG VLAN accelaration on the RX side have to be 9821 * turned on or off together. 9822 */ 9823 vlan_features = features & (NETIF_F_HW_VLAN_CTAG_RX | 9824 NETIF_F_HW_VLAN_STAG_RX); 9825 if (vlan_features != (NETIF_F_HW_VLAN_CTAG_RX | 9826 NETIF_F_HW_VLAN_STAG_RX)) { 9827 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX) 9828 features &= ~(NETIF_F_HW_VLAN_CTAG_RX | 9829 NETIF_F_HW_VLAN_STAG_RX); 9830 else if (vlan_features) 9831 features |= NETIF_F_HW_VLAN_CTAG_RX | 9832 NETIF_F_HW_VLAN_STAG_RX; 9833 } 9834 #ifdef CONFIG_BNXT_SRIOV 9835 if (BNXT_VF(bp)) { 9836 if (bp->vf.vlan) { 9837 features &= ~(NETIF_F_HW_VLAN_CTAG_RX | 9838 NETIF_F_HW_VLAN_STAG_RX); 9839 } 9840 } 9841 #endif 9842 return features; 9843 } 9844 9845 static int bnxt_set_features(struct net_device *dev, netdev_features_t features) 9846 { 9847 struct bnxt *bp = netdev_priv(dev); 9848 u32 flags = bp->flags; 9849 u32 changes; 9850 int rc = 0; 9851 bool re_init = false; 9852 bool update_tpa = false; 9853 9854 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS; 9855 if (features & NETIF_F_GRO_HW) 9856 flags |= BNXT_FLAG_GRO; 9857 else if (features & NETIF_F_LRO) 9858 flags |= BNXT_FLAG_LRO; 9859 9860 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 9861 flags &= ~BNXT_FLAG_TPA; 9862 9863 if (features & NETIF_F_HW_VLAN_CTAG_RX) 9864 flags |= BNXT_FLAG_STRIP_VLAN; 9865 9866 if (features & NETIF_F_NTUPLE) 9867 flags |= BNXT_FLAG_RFS; 9868 9869 changes = flags ^ bp->flags; 9870 if (changes & BNXT_FLAG_TPA) { 9871 update_tpa = true; 9872 if ((bp->flags & BNXT_FLAG_TPA) == 0 || 9873 (flags & BNXT_FLAG_TPA) == 0 || 9874 (bp->flags & BNXT_FLAG_CHIP_P5)) 9875 re_init = true; 9876 } 9877 9878 if (changes & ~BNXT_FLAG_TPA) 9879 re_init = true; 9880 9881 if (flags != bp->flags) { 9882 u32 old_flags = bp->flags; 9883 9884 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 9885 bp->flags = flags; 9886 if (update_tpa) 9887 bnxt_set_ring_params(bp); 9888 return rc; 9889 } 9890 9891 if (re_init) { 9892 bnxt_close_nic(bp, false, false); 9893 bp->flags = flags; 9894 if (update_tpa) 9895 bnxt_set_ring_params(bp); 9896 9897 return bnxt_open_nic(bp, false, false); 9898 } 9899 if (update_tpa) { 9900 bp->flags = flags; 9901 rc = bnxt_set_tpa(bp, 9902 (flags & BNXT_FLAG_TPA) ? 9903 true : false); 9904 if (rc) 9905 bp->flags = old_flags; 9906 } 9907 } 9908 return rc; 9909 } 9910 9911 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type, 9912 u32 ring_id, u32 *prod, u32 *cons) 9913 { 9914 struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr; 9915 struct hwrm_dbg_ring_info_get_input req = {0}; 9916 int rc; 9917 9918 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1); 9919 req.ring_type = ring_type; 9920 req.fw_ring_id = cpu_to_le32(ring_id); 9921 mutex_lock(&bp->hwrm_cmd_lock); 9922 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 9923 if (!rc) { 9924 *prod = le32_to_cpu(resp->producer_index); 9925 *cons = le32_to_cpu(resp->consumer_index); 9926 } 9927 mutex_unlock(&bp->hwrm_cmd_lock); 9928 return rc; 9929 } 9930 9931 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi) 9932 { 9933 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 9934 int i = bnapi->index; 9935 9936 if (!txr) 9937 return; 9938 9939 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n", 9940 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod, 9941 txr->tx_cons); 9942 } 9943 9944 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi) 9945 { 9946 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 9947 int i = bnapi->index; 9948 9949 if (!rxr) 9950 return; 9951 9952 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n", 9953 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod, 9954 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod, 9955 rxr->rx_sw_agg_prod); 9956 } 9957 9958 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi) 9959 { 9960 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 9961 int i = bnapi->index; 9962 9963 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n", 9964 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons); 9965 } 9966 9967 static void bnxt_dbg_dump_states(struct bnxt *bp) 9968 { 9969 int i; 9970 struct bnxt_napi *bnapi; 9971 9972 for (i = 0; i < bp->cp_nr_rings; i++) { 9973 bnapi = bp->bnapi[i]; 9974 if (netif_msg_drv(bp)) { 9975 bnxt_dump_tx_sw_state(bnapi); 9976 bnxt_dump_rx_sw_state(bnapi); 9977 bnxt_dump_cp_sw_state(bnapi); 9978 } 9979 } 9980 } 9981 9982 static void bnxt_reset_task(struct bnxt *bp, bool silent) 9983 { 9984 if (!silent) 9985 bnxt_dbg_dump_states(bp); 9986 if (netif_running(bp->dev)) { 9987 int rc; 9988 9989 if (silent) { 9990 bnxt_close_nic(bp, false, false); 9991 bnxt_open_nic(bp, false, false); 9992 } else { 9993 bnxt_ulp_stop(bp); 9994 bnxt_close_nic(bp, true, false); 9995 rc = bnxt_open_nic(bp, true, false); 9996 bnxt_ulp_start(bp, rc); 9997 } 9998 } 9999 } 10000 10001 static void bnxt_tx_timeout(struct net_device *dev, unsigned int txqueue) 10002 { 10003 struct bnxt *bp = netdev_priv(dev); 10004 10005 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n"); 10006 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 10007 bnxt_queue_sp_work(bp); 10008 } 10009 10010 static void bnxt_fw_health_check(struct bnxt *bp) 10011 { 10012 struct bnxt_fw_health *fw_health = bp->fw_health; 10013 u32 val; 10014 10015 if (!fw_health->enabled || test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 10016 return; 10017 10018 if (fw_health->tmr_counter) { 10019 fw_health->tmr_counter--; 10020 return; 10021 } 10022 10023 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); 10024 if (val == fw_health->last_fw_heartbeat) 10025 goto fw_reset; 10026 10027 fw_health->last_fw_heartbeat = val; 10028 10029 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 10030 if (val != fw_health->last_fw_reset_cnt) 10031 goto fw_reset; 10032 10033 fw_health->tmr_counter = fw_health->tmr_multiplier; 10034 return; 10035 10036 fw_reset: 10037 set_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event); 10038 bnxt_queue_sp_work(bp); 10039 } 10040 10041 static void bnxt_timer(struct timer_list *t) 10042 { 10043 struct bnxt *bp = from_timer(bp, t, timer); 10044 struct net_device *dev = bp->dev; 10045 10046 if (!netif_running(dev)) 10047 return; 10048 10049 if (atomic_read(&bp->intr_sem) != 0) 10050 goto bnxt_restart_timer; 10051 10052 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) 10053 bnxt_fw_health_check(bp); 10054 10055 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) && 10056 bp->stats_coal_ticks) { 10057 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event); 10058 bnxt_queue_sp_work(bp); 10059 } 10060 10061 if (bnxt_tc_flower_enabled(bp)) { 10062 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event); 10063 bnxt_queue_sp_work(bp); 10064 } 10065 10066 #ifdef CONFIG_RFS_ACCEL 10067 if ((bp->flags & BNXT_FLAG_RFS) && bp->ntp_fltr_count) { 10068 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); 10069 bnxt_queue_sp_work(bp); 10070 } 10071 #endif /*CONFIG_RFS_ACCEL*/ 10072 10073 if (bp->link_info.phy_retry) { 10074 if (time_after(jiffies, bp->link_info.phy_retry_expires)) { 10075 bp->link_info.phy_retry = false; 10076 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n"); 10077 } else { 10078 set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event); 10079 bnxt_queue_sp_work(bp); 10080 } 10081 } 10082 10083 if ((bp->flags & BNXT_FLAG_CHIP_P5) && !bp->chip_rev && 10084 netif_carrier_ok(dev)) { 10085 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event); 10086 bnxt_queue_sp_work(bp); 10087 } 10088 bnxt_restart_timer: 10089 mod_timer(&bp->timer, jiffies + bp->current_interval); 10090 } 10091 10092 static void bnxt_rtnl_lock_sp(struct bnxt *bp) 10093 { 10094 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK 10095 * set. If the device is being closed, bnxt_close() may be holding 10096 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we 10097 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl(). 10098 */ 10099 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10100 rtnl_lock(); 10101 } 10102 10103 static void bnxt_rtnl_unlock_sp(struct bnxt *bp) 10104 { 10105 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10106 rtnl_unlock(); 10107 } 10108 10109 /* Only called from bnxt_sp_task() */ 10110 static void bnxt_reset(struct bnxt *bp, bool silent) 10111 { 10112 bnxt_rtnl_lock_sp(bp); 10113 if (test_bit(BNXT_STATE_OPEN, &bp->state)) 10114 bnxt_reset_task(bp, silent); 10115 bnxt_rtnl_unlock_sp(bp); 10116 } 10117 10118 static void bnxt_fw_reset_close(struct bnxt *bp) 10119 { 10120 bnxt_ulp_stop(bp); 10121 /* When firmware is fatal state, disable PCI device to prevent 10122 * any potential bad DMAs before freeing kernel memory. 10123 */ 10124 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 10125 pci_disable_device(bp->pdev); 10126 __bnxt_close_nic(bp, true, false); 10127 bnxt_clear_int_mode(bp); 10128 bnxt_hwrm_func_drv_unrgtr(bp); 10129 if (pci_is_enabled(bp->pdev)) 10130 pci_disable_device(bp->pdev); 10131 bnxt_free_ctx_mem(bp); 10132 kfree(bp->ctx); 10133 bp->ctx = NULL; 10134 } 10135 10136 static bool is_bnxt_fw_ok(struct bnxt *bp) 10137 { 10138 struct bnxt_fw_health *fw_health = bp->fw_health; 10139 bool no_heartbeat = false, has_reset = false; 10140 u32 val; 10141 10142 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); 10143 if (val == fw_health->last_fw_heartbeat) 10144 no_heartbeat = true; 10145 10146 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 10147 if (val != fw_health->last_fw_reset_cnt) 10148 has_reset = true; 10149 10150 if (!no_heartbeat && has_reset) 10151 return true; 10152 10153 return false; 10154 } 10155 10156 /* rtnl_lock is acquired before calling this function */ 10157 static void bnxt_force_fw_reset(struct bnxt *bp) 10158 { 10159 struct bnxt_fw_health *fw_health = bp->fw_health; 10160 u32 wait_dsecs; 10161 10162 if (!test_bit(BNXT_STATE_OPEN, &bp->state) || 10163 test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 10164 return; 10165 10166 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10167 bnxt_fw_reset_close(bp); 10168 wait_dsecs = fw_health->master_func_wait_dsecs; 10169 if (fw_health->master) { 10170 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) 10171 wait_dsecs = 0; 10172 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; 10173 } else { 10174 bp->fw_reset_timestamp = jiffies + wait_dsecs * HZ / 10; 10175 wait_dsecs = fw_health->normal_func_wait_dsecs; 10176 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10177 } 10178 10179 bp->fw_reset_min_dsecs = fw_health->post_reset_wait_dsecs; 10180 bp->fw_reset_max_dsecs = fw_health->post_reset_max_wait_dsecs; 10181 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); 10182 } 10183 10184 void bnxt_fw_exception(struct bnxt *bp) 10185 { 10186 netdev_warn(bp->dev, "Detected firmware fatal condition, initiating reset\n"); 10187 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); 10188 bnxt_rtnl_lock_sp(bp); 10189 bnxt_force_fw_reset(bp); 10190 bnxt_rtnl_unlock_sp(bp); 10191 } 10192 10193 /* Returns the number of registered VFs, or 1 if VF configuration is pending, or 10194 * < 0 on error. 10195 */ 10196 static int bnxt_get_registered_vfs(struct bnxt *bp) 10197 { 10198 #ifdef CONFIG_BNXT_SRIOV 10199 int rc; 10200 10201 if (!BNXT_PF(bp)) 10202 return 0; 10203 10204 rc = bnxt_hwrm_func_qcfg(bp); 10205 if (rc) { 10206 netdev_err(bp->dev, "func_qcfg cmd failed, rc = %d\n", rc); 10207 return rc; 10208 } 10209 if (bp->pf.registered_vfs) 10210 return bp->pf.registered_vfs; 10211 if (bp->sriov_cfg) 10212 return 1; 10213 #endif 10214 return 0; 10215 } 10216 10217 void bnxt_fw_reset(struct bnxt *bp) 10218 { 10219 bnxt_rtnl_lock_sp(bp); 10220 if (test_bit(BNXT_STATE_OPEN, &bp->state) && 10221 !test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 10222 int n = 0, tmo; 10223 10224 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10225 if (bp->pf.active_vfs && 10226 !test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 10227 n = bnxt_get_registered_vfs(bp); 10228 if (n < 0) { 10229 netdev_err(bp->dev, "Firmware reset aborted, rc = %d\n", 10230 n); 10231 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10232 dev_close(bp->dev); 10233 goto fw_reset_exit; 10234 } else if (n > 0) { 10235 u16 vf_tmo_dsecs = n * 10; 10236 10237 if (bp->fw_reset_max_dsecs < vf_tmo_dsecs) 10238 bp->fw_reset_max_dsecs = vf_tmo_dsecs; 10239 bp->fw_reset_state = 10240 BNXT_FW_RESET_STATE_POLL_VF; 10241 bnxt_queue_fw_reset_work(bp, HZ / 10); 10242 goto fw_reset_exit; 10243 } 10244 bnxt_fw_reset_close(bp); 10245 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { 10246 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN; 10247 tmo = HZ / 10; 10248 } else { 10249 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10250 tmo = bp->fw_reset_min_dsecs * HZ / 10; 10251 } 10252 bnxt_queue_fw_reset_work(bp, tmo); 10253 } 10254 fw_reset_exit: 10255 bnxt_rtnl_unlock_sp(bp); 10256 } 10257 10258 static void bnxt_chk_missed_irq(struct bnxt *bp) 10259 { 10260 int i; 10261 10262 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 10263 return; 10264 10265 for (i = 0; i < bp->cp_nr_rings; i++) { 10266 struct bnxt_napi *bnapi = bp->bnapi[i]; 10267 struct bnxt_cp_ring_info *cpr; 10268 u32 fw_ring_id; 10269 int j; 10270 10271 if (!bnapi) 10272 continue; 10273 10274 cpr = &bnapi->cp_ring; 10275 for (j = 0; j < 2; j++) { 10276 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 10277 u32 val[2]; 10278 10279 if (!cpr2 || cpr2->has_more_work || 10280 !bnxt_has_work(bp, cpr2)) 10281 continue; 10282 10283 if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) { 10284 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons; 10285 continue; 10286 } 10287 fw_ring_id = cpr2->cp_ring_struct.fw_ring_id; 10288 bnxt_dbg_hwrm_ring_info_get(bp, 10289 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL, 10290 fw_ring_id, &val[0], &val[1]); 10291 cpr->sw_stats.cmn.missed_irqs++; 10292 } 10293 } 10294 } 10295 10296 static void bnxt_cfg_ntp_filters(struct bnxt *); 10297 10298 static void bnxt_init_ethtool_link_settings(struct bnxt *bp) 10299 { 10300 struct bnxt_link_info *link_info = &bp->link_info; 10301 10302 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 10303 link_info->autoneg = BNXT_AUTONEG_SPEED; 10304 if (bp->hwrm_spec_code >= 0x10201) { 10305 if (link_info->auto_pause_setting & 10306 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE) 10307 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 10308 } else { 10309 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 10310 } 10311 link_info->advertising = link_info->auto_link_speeds; 10312 } else { 10313 link_info->req_link_speed = link_info->force_link_speed; 10314 link_info->req_duplex = link_info->duplex_setting; 10315 } 10316 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 10317 link_info->req_flow_ctrl = 10318 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH; 10319 else 10320 link_info->req_flow_ctrl = link_info->force_pause_setting; 10321 } 10322 10323 static void bnxt_sp_task(struct work_struct *work) 10324 { 10325 struct bnxt *bp = container_of(work, struct bnxt, sp_task); 10326 10327 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10328 smp_mb__after_atomic(); 10329 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 10330 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10331 return; 10332 } 10333 10334 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event)) 10335 bnxt_cfg_rx_mode(bp); 10336 10337 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event)) 10338 bnxt_cfg_ntp_filters(bp); 10339 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event)) 10340 bnxt_hwrm_exec_fwd_req(bp); 10341 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) { 10342 bnxt_hwrm_tunnel_dst_port_alloc( 10343 bp, bp->vxlan_port, 10344 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 10345 } 10346 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) { 10347 bnxt_hwrm_tunnel_dst_port_free( 10348 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 10349 } 10350 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) { 10351 bnxt_hwrm_tunnel_dst_port_alloc( 10352 bp, bp->nge_port, 10353 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 10354 } 10355 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) { 10356 bnxt_hwrm_tunnel_dst_port_free( 10357 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 10358 } 10359 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) { 10360 bnxt_hwrm_port_qstats(bp); 10361 bnxt_hwrm_port_qstats_ext(bp); 10362 bnxt_hwrm_pcie_qstats(bp); 10363 } 10364 10365 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) { 10366 int rc; 10367 10368 mutex_lock(&bp->link_lock); 10369 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, 10370 &bp->sp_event)) 10371 bnxt_hwrm_phy_qcaps(bp); 10372 10373 if (test_and_clear_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, 10374 &bp->sp_event)) 10375 bnxt_init_ethtool_link_settings(bp); 10376 10377 rc = bnxt_update_link(bp, true); 10378 mutex_unlock(&bp->link_lock); 10379 if (rc) 10380 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n", 10381 rc); 10382 } 10383 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) { 10384 int rc; 10385 10386 mutex_lock(&bp->link_lock); 10387 rc = bnxt_update_phy_setting(bp); 10388 mutex_unlock(&bp->link_lock); 10389 if (rc) { 10390 netdev_warn(bp->dev, "update phy settings retry failed\n"); 10391 } else { 10392 bp->link_info.phy_retry = false; 10393 netdev_info(bp->dev, "update phy settings retry succeeded\n"); 10394 } 10395 } 10396 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) { 10397 mutex_lock(&bp->link_lock); 10398 bnxt_get_port_module_status(bp); 10399 mutex_unlock(&bp->link_lock); 10400 } 10401 10402 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event)) 10403 bnxt_tc_flow_stats_work(bp); 10404 10405 if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event)) 10406 bnxt_chk_missed_irq(bp); 10407 10408 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They 10409 * must be the last functions to be called before exiting. 10410 */ 10411 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) 10412 bnxt_reset(bp, false); 10413 10414 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event)) 10415 bnxt_reset(bp, true); 10416 10417 if (test_and_clear_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event)) 10418 bnxt_devlink_health_report(bp, BNXT_FW_RESET_NOTIFY_SP_EVENT); 10419 10420 if (test_and_clear_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event)) { 10421 if (!is_bnxt_fw_ok(bp)) 10422 bnxt_devlink_health_report(bp, 10423 BNXT_FW_EXCEPTION_SP_EVENT); 10424 } 10425 10426 smp_mb__before_atomic(); 10427 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 10428 } 10429 10430 /* Under rtnl_lock */ 10431 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs, 10432 int tx_xdp) 10433 { 10434 int max_rx, max_tx, tx_sets = 1; 10435 int tx_rings_needed, stats; 10436 int rx_rings = rx; 10437 int cp, vnics, rc; 10438 10439 if (tcs) 10440 tx_sets = tcs; 10441 10442 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh); 10443 if (rc) 10444 return rc; 10445 10446 if (max_rx < rx) 10447 return -ENOMEM; 10448 10449 tx_rings_needed = tx * tx_sets + tx_xdp; 10450 if (max_tx < tx_rings_needed) 10451 return -ENOMEM; 10452 10453 vnics = 1; 10454 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS) 10455 vnics += rx_rings; 10456 10457 if (bp->flags & BNXT_FLAG_AGG_RINGS) 10458 rx_rings <<= 1; 10459 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx; 10460 stats = cp; 10461 if (BNXT_NEW_RM(bp)) { 10462 cp += bnxt_get_ulp_msix_num(bp); 10463 stats += bnxt_get_ulp_stat_ctxs(bp); 10464 } 10465 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp, 10466 stats, vnics); 10467 } 10468 10469 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev) 10470 { 10471 if (bp->bar2) { 10472 pci_iounmap(pdev, bp->bar2); 10473 bp->bar2 = NULL; 10474 } 10475 10476 if (bp->bar1) { 10477 pci_iounmap(pdev, bp->bar1); 10478 bp->bar1 = NULL; 10479 } 10480 10481 if (bp->bar0) { 10482 pci_iounmap(pdev, bp->bar0); 10483 bp->bar0 = NULL; 10484 } 10485 } 10486 10487 static void bnxt_cleanup_pci(struct bnxt *bp) 10488 { 10489 bnxt_unmap_bars(bp, bp->pdev); 10490 pci_release_regions(bp->pdev); 10491 if (pci_is_enabled(bp->pdev)) 10492 pci_disable_device(bp->pdev); 10493 } 10494 10495 static void bnxt_init_dflt_coal(struct bnxt *bp) 10496 { 10497 struct bnxt_coal *coal; 10498 10499 /* Tick values in micro seconds. 10500 * 1 coal_buf x bufs_per_record = 1 completion record. 10501 */ 10502 coal = &bp->rx_coal; 10503 coal->coal_ticks = 10; 10504 coal->coal_bufs = 30; 10505 coal->coal_ticks_irq = 1; 10506 coal->coal_bufs_irq = 2; 10507 coal->idle_thresh = 50; 10508 coal->bufs_per_record = 2; 10509 coal->budget = 64; /* NAPI budget */ 10510 10511 coal = &bp->tx_coal; 10512 coal->coal_ticks = 28; 10513 coal->coal_bufs = 30; 10514 coal->coal_ticks_irq = 2; 10515 coal->coal_bufs_irq = 2; 10516 coal->bufs_per_record = 1; 10517 10518 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS; 10519 } 10520 10521 static void bnxt_alloc_fw_health(struct bnxt *bp) 10522 { 10523 if (bp->fw_health) 10524 return; 10525 10526 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET) && 10527 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 10528 return; 10529 10530 bp->fw_health = kzalloc(sizeof(*bp->fw_health), GFP_KERNEL); 10531 if (!bp->fw_health) { 10532 netdev_warn(bp->dev, "Failed to allocate fw_health\n"); 10533 bp->fw_cap &= ~BNXT_FW_CAP_HOT_RESET; 10534 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 10535 } 10536 } 10537 10538 static int bnxt_fw_init_one_p1(struct bnxt *bp) 10539 { 10540 int rc; 10541 10542 bp->fw_cap = 0; 10543 rc = bnxt_hwrm_ver_get(bp); 10544 if (rc) 10545 return rc; 10546 10547 if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) { 10548 rc = bnxt_alloc_kong_hwrm_resources(bp); 10549 if (rc) 10550 bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL; 10551 } 10552 10553 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) || 10554 bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) { 10555 rc = bnxt_alloc_hwrm_short_cmd_req(bp); 10556 if (rc) 10557 return rc; 10558 } 10559 rc = bnxt_hwrm_func_reset(bp); 10560 if (rc) 10561 return -ENODEV; 10562 10563 bnxt_hwrm_fw_set_time(bp); 10564 return 0; 10565 } 10566 10567 static int bnxt_fw_init_one_p2(struct bnxt *bp) 10568 { 10569 int rc; 10570 10571 /* Get the MAX capabilities for this function */ 10572 rc = bnxt_hwrm_func_qcaps(bp); 10573 if (rc) { 10574 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n", 10575 rc); 10576 return -ENODEV; 10577 } 10578 10579 rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp); 10580 if (rc) 10581 netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n", 10582 rc); 10583 10584 bnxt_alloc_fw_health(bp); 10585 rc = bnxt_hwrm_error_recovery_qcfg(bp); 10586 if (rc) 10587 netdev_warn(bp->dev, "hwrm query error recovery failure rc: %d\n", 10588 rc); 10589 10590 rc = bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false); 10591 if (rc) 10592 return -ENODEV; 10593 10594 bnxt_hwrm_func_qcfg(bp); 10595 bnxt_hwrm_vnic_qcaps(bp); 10596 bnxt_hwrm_port_led_qcaps(bp); 10597 bnxt_ethtool_init(bp); 10598 bnxt_dcb_init(bp); 10599 return 0; 10600 } 10601 10602 static void bnxt_set_dflt_rss_hash_type(struct bnxt *bp) 10603 { 10604 bp->flags &= ~BNXT_FLAG_UDP_RSS_CAP; 10605 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 | 10606 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 | 10607 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 | 10608 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 10609 if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) { 10610 bp->flags |= BNXT_FLAG_UDP_RSS_CAP; 10611 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 | 10612 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 10613 } 10614 } 10615 10616 static void bnxt_set_dflt_rfs(struct bnxt *bp) 10617 { 10618 struct net_device *dev = bp->dev; 10619 10620 dev->hw_features &= ~NETIF_F_NTUPLE; 10621 dev->features &= ~NETIF_F_NTUPLE; 10622 bp->flags &= ~BNXT_FLAG_RFS; 10623 if (bnxt_rfs_supported(bp)) { 10624 dev->hw_features |= NETIF_F_NTUPLE; 10625 if (bnxt_rfs_capable(bp)) { 10626 bp->flags |= BNXT_FLAG_RFS; 10627 dev->features |= NETIF_F_NTUPLE; 10628 } 10629 } 10630 } 10631 10632 static void bnxt_fw_init_one_p3(struct bnxt *bp) 10633 { 10634 struct pci_dev *pdev = bp->pdev; 10635 10636 bnxt_set_dflt_rss_hash_type(bp); 10637 bnxt_set_dflt_rfs(bp); 10638 10639 bnxt_get_wol_settings(bp); 10640 if (bp->flags & BNXT_FLAG_WOL_CAP) 10641 device_set_wakeup_enable(&pdev->dev, bp->wol); 10642 else 10643 device_set_wakeup_capable(&pdev->dev, false); 10644 10645 bnxt_hwrm_set_cache_line_size(bp, cache_line_size()); 10646 bnxt_hwrm_coal_params_qcaps(bp); 10647 } 10648 10649 static int bnxt_fw_init_one(struct bnxt *bp) 10650 { 10651 int rc; 10652 10653 rc = bnxt_fw_init_one_p1(bp); 10654 if (rc) { 10655 netdev_err(bp->dev, "Firmware init phase 1 failed\n"); 10656 return rc; 10657 } 10658 rc = bnxt_fw_init_one_p2(bp); 10659 if (rc) { 10660 netdev_err(bp->dev, "Firmware init phase 2 failed\n"); 10661 return rc; 10662 } 10663 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, false); 10664 if (rc) 10665 return rc; 10666 10667 /* In case fw capabilities have changed, destroy the unneeded 10668 * reporters and create newly capable ones. 10669 */ 10670 bnxt_dl_fw_reporters_destroy(bp, false); 10671 bnxt_dl_fw_reporters_create(bp); 10672 bnxt_fw_init_one_p3(bp); 10673 return 0; 10674 } 10675 10676 static void bnxt_fw_reset_writel(struct bnxt *bp, int reg_idx) 10677 { 10678 struct bnxt_fw_health *fw_health = bp->fw_health; 10679 u32 reg = fw_health->fw_reset_seq_regs[reg_idx]; 10680 u32 val = fw_health->fw_reset_seq_vals[reg_idx]; 10681 u32 reg_type, reg_off, delay_msecs; 10682 10683 delay_msecs = fw_health->fw_reset_seq_delay_msec[reg_idx]; 10684 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); 10685 reg_off = BNXT_FW_HEALTH_REG_OFF(reg); 10686 switch (reg_type) { 10687 case BNXT_FW_HEALTH_REG_TYPE_CFG: 10688 pci_write_config_dword(bp->pdev, reg_off, val); 10689 break; 10690 case BNXT_FW_HEALTH_REG_TYPE_GRC: 10691 writel(reg_off & BNXT_GRC_BASE_MASK, 10692 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 10693 reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000; 10694 /* fall through */ 10695 case BNXT_FW_HEALTH_REG_TYPE_BAR0: 10696 writel(val, bp->bar0 + reg_off); 10697 break; 10698 case BNXT_FW_HEALTH_REG_TYPE_BAR1: 10699 writel(val, bp->bar1 + reg_off); 10700 break; 10701 } 10702 if (delay_msecs) { 10703 pci_read_config_dword(bp->pdev, 0, &val); 10704 msleep(delay_msecs); 10705 } 10706 } 10707 10708 static void bnxt_reset_all(struct bnxt *bp) 10709 { 10710 struct bnxt_fw_health *fw_health = bp->fw_health; 10711 int i, rc; 10712 10713 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { 10714 #ifdef CONFIG_TEE_BNXT_FW 10715 rc = tee_bnxt_fw_load(); 10716 if (rc) 10717 netdev_err(bp->dev, "Unable to reset FW rc=%d\n", rc); 10718 bp->fw_reset_timestamp = jiffies; 10719 #endif 10720 return; 10721 } 10722 10723 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST) { 10724 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) 10725 bnxt_fw_reset_writel(bp, i); 10726 } else if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) { 10727 struct hwrm_fw_reset_input req = {0}; 10728 10729 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1); 10730 req.resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr); 10731 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP; 10732 req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP; 10733 req.flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 10734 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 10735 if (rc) 10736 netdev_warn(bp->dev, "Unable to reset FW rc=%d\n", rc); 10737 } 10738 bp->fw_reset_timestamp = jiffies; 10739 } 10740 10741 static void bnxt_fw_reset_task(struct work_struct *work) 10742 { 10743 struct bnxt *bp = container_of(work, struct bnxt, fw_reset_task.work); 10744 int rc; 10745 10746 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 10747 netdev_err(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n"); 10748 return; 10749 } 10750 10751 switch (bp->fw_reset_state) { 10752 case BNXT_FW_RESET_STATE_POLL_VF: { 10753 int n = bnxt_get_registered_vfs(bp); 10754 int tmo; 10755 10756 if (n < 0) { 10757 netdev_err(bp->dev, "Firmware reset aborted, subsequent func_qcfg cmd failed, rc = %d, %d msecs since reset timestamp\n", 10758 n, jiffies_to_msecs(jiffies - 10759 bp->fw_reset_timestamp)); 10760 goto fw_reset_abort; 10761 } else if (n > 0) { 10762 if (time_after(jiffies, bp->fw_reset_timestamp + 10763 (bp->fw_reset_max_dsecs * HZ / 10))) { 10764 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10765 bp->fw_reset_state = 0; 10766 netdev_err(bp->dev, "Firmware reset aborted, bnxt_get_registered_vfs() returns %d\n", 10767 n); 10768 return; 10769 } 10770 bnxt_queue_fw_reset_work(bp, HZ / 10); 10771 return; 10772 } 10773 bp->fw_reset_timestamp = jiffies; 10774 rtnl_lock(); 10775 bnxt_fw_reset_close(bp); 10776 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { 10777 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN; 10778 tmo = HZ / 10; 10779 } else { 10780 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10781 tmo = bp->fw_reset_min_dsecs * HZ / 10; 10782 } 10783 rtnl_unlock(); 10784 bnxt_queue_fw_reset_work(bp, tmo); 10785 return; 10786 } 10787 case BNXT_FW_RESET_STATE_POLL_FW_DOWN: { 10788 u32 val; 10789 10790 val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); 10791 if (!(val & BNXT_FW_STATUS_SHUTDOWN) && 10792 !time_after(jiffies, bp->fw_reset_timestamp + 10793 (bp->fw_reset_max_dsecs * HZ / 10))) { 10794 bnxt_queue_fw_reset_work(bp, HZ / 5); 10795 return; 10796 } 10797 10798 if (!bp->fw_health->master) { 10799 u32 wait_dsecs = bp->fw_health->normal_func_wait_dsecs; 10800 10801 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10802 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); 10803 return; 10804 } 10805 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; 10806 } 10807 /* fall through */ 10808 case BNXT_FW_RESET_STATE_RESET_FW: 10809 bnxt_reset_all(bp); 10810 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 10811 bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10); 10812 return; 10813 case BNXT_FW_RESET_STATE_ENABLE_DEV: 10814 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) { 10815 u32 val; 10816 10817 val = bnxt_fw_health_readl(bp, 10818 BNXT_FW_RESET_INPROG_REG); 10819 if (val) 10820 netdev_warn(bp->dev, "FW reset inprog %x after min wait time.\n", 10821 val); 10822 } 10823 clear_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); 10824 if (pci_enable_device(bp->pdev)) { 10825 netdev_err(bp->dev, "Cannot re-enable PCI device\n"); 10826 goto fw_reset_abort; 10827 } 10828 pci_set_master(bp->pdev); 10829 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW; 10830 /* fall through */ 10831 case BNXT_FW_RESET_STATE_POLL_FW: 10832 bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT; 10833 rc = __bnxt_hwrm_ver_get(bp, true); 10834 if (rc) { 10835 if (time_after(jiffies, bp->fw_reset_timestamp + 10836 (bp->fw_reset_max_dsecs * HZ / 10))) { 10837 netdev_err(bp->dev, "Firmware reset aborted\n"); 10838 goto fw_reset_abort; 10839 } 10840 bnxt_queue_fw_reset_work(bp, HZ / 5); 10841 return; 10842 } 10843 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; 10844 bp->fw_reset_state = BNXT_FW_RESET_STATE_OPENING; 10845 /* fall through */ 10846 case BNXT_FW_RESET_STATE_OPENING: 10847 while (!rtnl_trylock()) { 10848 bnxt_queue_fw_reset_work(bp, HZ / 10); 10849 return; 10850 } 10851 rc = bnxt_open(bp->dev); 10852 if (rc) { 10853 netdev_err(bp->dev, "bnxt_open_nic() failed\n"); 10854 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10855 dev_close(bp->dev); 10856 } 10857 10858 bp->fw_reset_state = 0; 10859 /* Make sure fw_reset_state is 0 before clearing the flag */ 10860 smp_mb__before_atomic(); 10861 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10862 bnxt_ulp_start(bp, rc); 10863 if (!rc) 10864 bnxt_reenable_sriov(bp); 10865 bnxt_dl_health_recovery_done(bp); 10866 bnxt_dl_health_status_update(bp, true); 10867 rtnl_unlock(); 10868 break; 10869 } 10870 return; 10871 10872 fw_reset_abort: 10873 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 10874 if (bp->fw_reset_state != BNXT_FW_RESET_STATE_POLL_VF) 10875 bnxt_dl_health_status_update(bp, false); 10876 bp->fw_reset_state = 0; 10877 rtnl_lock(); 10878 dev_close(bp->dev); 10879 rtnl_unlock(); 10880 } 10881 10882 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev) 10883 { 10884 int rc; 10885 struct bnxt *bp = netdev_priv(dev); 10886 10887 SET_NETDEV_DEV(dev, &pdev->dev); 10888 10889 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 10890 rc = pci_enable_device(pdev); 10891 if (rc) { 10892 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 10893 goto init_err; 10894 } 10895 10896 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 10897 dev_err(&pdev->dev, 10898 "Cannot find PCI device base address, aborting\n"); 10899 rc = -ENODEV; 10900 goto init_err_disable; 10901 } 10902 10903 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 10904 if (rc) { 10905 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); 10906 goto init_err_disable; 10907 } 10908 10909 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 && 10910 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) { 10911 dev_err(&pdev->dev, "System does not support DMA, aborting\n"); 10912 goto init_err_disable; 10913 } 10914 10915 pci_set_master(pdev); 10916 10917 bp->dev = dev; 10918 bp->pdev = pdev; 10919 10920 /* Doorbell BAR bp->bar1 is mapped after bnxt_fw_init_one_p2() 10921 * determines the BAR size. 10922 */ 10923 bp->bar0 = pci_ioremap_bar(pdev, 0); 10924 if (!bp->bar0) { 10925 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); 10926 rc = -ENOMEM; 10927 goto init_err_release; 10928 } 10929 10930 bp->bar2 = pci_ioremap_bar(pdev, 4); 10931 if (!bp->bar2) { 10932 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n"); 10933 rc = -ENOMEM; 10934 goto init_err_release; 10935 } 10936 10937 pci_enable_pcie_error_reporting(pdev); 10938 10939 INIT_WORK(&bp->sp_task, bnxt_sp_task); 10940 INIT_DELAYED_WORK(&bp->fw_reset_task, bnxt_fw_reset_task); 10941 10942 spin_lock_init(&bp->ntp_fltr_lock); 10943 #if BITS_PER_LONG == 32 10944 spin_lock_init(&bp->db_lock); 10945 #endif 10946 10947 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE; 10948 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE; 10949 10950 bnxt_init_dflt_coal(bp); 10951 10952 timer_setup(&bp->timer, bnxt_timer, 0); 10953 bp->current_interval = BNXT_TIMER_INTERVAL; 10954 10955 clear_bit(BNXT_STATE_OPEN, &bp->state); 10956 return 0; 10957 10958 init_err_release: 10959 bnxt_unmap_bars(bp, pdev); 10960 pci_release_regions(pdev); 10961 10962 init_err_disable: 10963 pci_disable_device(pdev); 10964 10965 init_err: 10966 return rc; 10967 } 10968 10969 /* rtnl_lock held */ 10970 static int bnxt_change_mac_addr(struct net_device *dev, void *p) 10971 { 10972 struct sockaddr *addr = p; 10973 struct bnxt *bp = netdev_priv(dev); 10974 int rc = 0; 10975 10976 if (!is_valid_ether_addr(addr->sa_data)) 10977 return -EADDRNOTAVAIL; 10978 10979 if (ether_addr_equal(addr->sa_data, dev->dev_addr)) 10980 return 0; 10981 10982 rc = bnxt_approve_mac(bp, addr->sa_data, true); 10983 if (rc) 10984 return rc; 10985 10986 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 10987 if (netif_running(dev)) { 10988 bnxt_close_nic(bp, false, false); 10989 rc = bnxt_open_nic(bp, false, false); 10990 } 10991 10992 return rc; 10993 } 10994 10995 /* rtnl_lock held */ 10996 static int bnxt_change_mtu(struct net_device *dev, int new_mtu) 10997 { 10998 struct bnxt *bp = netdev_priv(dev); 10999 11000 if (netif_running(dev)) 11001 bnxt_close_nic(bp, true, false); 11002 11003 dev->mtu = new_mtu; 11004 bnxt_set_ring_params(bp); 11005 11006 if (netif_running(dev)) 11007 return bnxt_open_nic(bp, true, false); 11008 11009 return 0; 11010 } 11011 11012 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc) 11013 { 11014 struct bnxt *bp = netdev_priv(dev); 11015 bool sh = false; 11016 int rc; 11017 11018 if (tc > bp->max_tc) { 11019 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n", 11020 tc, bp->max_tc); 11021 return -EINVAL; 11022 } 11023 11024 if (netdev_get_num_tc(dev) == tc) 11025 return 0; 11026 11027 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 11028 sh = true; 11029 11030 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings, 11031 sh, tc, bp->tx_nr_rings_xdp); 11032 if (rc) 11033 return rc; 11034 11035 /* Needs to close the device and do hw resource re-allocations */ 11036 if (netif_running(bp->dev)) 11037 bnxt_close_nic(bp, true, false); 11038 11039 if (tc) { 11040 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc; 11041 netdev_set_num_tc(dev, tc); 11042 } else { 11043 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 11044 netdev_reset_tc(dev); 11045 } 11046 bp->tx_nr_rings += bp->tx_nr_rings_xdp; 11047 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 11048 bp->tx_nr_rings + bp->rx_nr_rings; 11049 11050 if (netif_running(bp->dev)) 11051 return bnxt_open_nic(bp, true, false); 11052 11053 return 0; 11054 } 11055 11056 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 11057 void *cb_priv) 11058 { 11059 struct bnxt *bp = cb_priv; 11060 11061 if (!bnxt_tc_flower_enabled(bp) || 11062 !tc_cls_can_offload_and_chain0(bp->dev, type_data)) 11063 return -EOPNOTSUPP; 11064 11065 switch (type) { 11066 case TC_SETUP_CLSFLOWER: 11067 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data); 11068 default: 11069 return -EOPNOTSUPP; 11070 } 11071 } 11072 11073 LIST_HEAD(bnxt_block_cb_list); 11074 11075 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type, 11076 void *type_data) 11077 { 11078 struct bnxt *bp = netdev_priv(dev); 11079 11080 switch (type) { 11081 case TC_SETUP_BLOCK: 11082 return flow_block_cb_setup_simple(type_data, 11083 &bnxt_block_cb_list, 11084 bnxt_setup_tc_block_cb, 11085 bp, bp, true); 11086 case TC_SETUP_QDISC_MQPRIO: { 11087 struct tc_mqprio_qopt *mqprio = type_data; 11088 11089 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 11090 11091 return bnxt_setup_mq_tc(dev, mqprio->num_tc); 11092 } 11093 default: 11094 return -EOPNOTSUPP; 11095 } 11096 } 11097 11098 #ifdef CONFIG_RFS_ACCEL 11099 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1, 11100 struct bnxt_ntuple_filter *f2) 11101 { 11102 struct flow_keys *keys1 = &f1->fkeys; 11103 struct flow_keys *keys2 = &f2->fkeys; 11104 11105 if (keys1->basic.n_proto != keys2->basic.n_proto || 11106 keys1->basic.ip_proto != keys2->basic.ip_proto) 11107 return false; 11108 11109 if (keys1->basic.n_proto == htons(ETH_P_IP)) { 11110 if (keys1->addrs.v4addrs.src != keys2->addrs.v4addrs.src || 11111 keys1->addrs.v4addrs.dst != keys2->addrs.v4addrs.dst) 11112 return false; 11113 } else { 11114 if (memcmp(&keys1->addrs.v6addrs.src, &keys2->addrs.v6addrs.src, 11115 sizeof(keys1->addrs.v6addrs.src)) || 11116 memcmp(&keys1->addrs.v6addrs.dst, &keys2->addrs.v6addrs.dst, 11117 sizeof(keys1->addrs.v6addrs.dst))) 11118 return false; 11119 } 11120 11121 if (keys1->ports.ports == keys2->ports.ports && 11122 keys1->control.flags == keys2->control.flags && 11123 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) && 11124 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr)) 11125 return true; 11126 11127 return false; 11128 } 11129 11130 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 11131 u16 rxq_index, u32 flow_id) 11132 { 11133 struct bnxt *bp = netdev_priv(dev); 11134 struct bnxt_ntuple_filter *fltr, *new_fltr; 11135 struct flow_keys *fkeys; 11136 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb); 11137 int rc = 0, idx, bit_id, l2_idx = 0; 11138 struct hlist_head *head; 11139 u32 flags; 11140 11141 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) { 11142 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 11143 int off = 0, j; 11144 11145 netif_addr_lock_bh(dev); 11146 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) { 11147 if (ether_addr_equal(eth->h_dest, 11148 vnic->uc_list + off)) { 11149 l2_idx = j + 1; 11150 break; 11151 } 11152 } 11153 netif_addr_unlock_bh(dev); 11154 if (!l2_idx) 11155 return -EINVAL; 11156 } 11157 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC); 11158 if (!new_fltr) 11159 return -ENOMEM; 11160 11161 fkeys = &new_fltr->fkeys; 11162 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) { 11163 rc = -EPROTONOSUPPORT; 11164 goto err_free; 11165 } 11166 11167 if ((fkeys->basic.n_proto != htons(ETH_P_IP) && 11168 fkeys->basic.n_proto != htons(ETH_P_IPV6)) || 11169 ((fkeys->basic.ip_proto != IPPROTO_TCP) && 11170 (fkeys->basic.ip_proto != IPPROTO_UDP))) { 11171 rc = -EPROTONOSUPPORT; 11172 goto err_free; 11173 } 11174 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) && 11175 bp->hwrm_spec_code < 0x10601) { 11176 rc = -EPROTONOSUPPORT; 11177 goto err_free; 11178 } 11179 flags = fkeys->control.flags; 11180 if (((flags & FLOW_DIS_ENCAPSULATION) && 11181 bp->hwrm_spec_code < 0x10601) || (flags & FLOW_DIS_IS_FRAGMENT)) { 11182 rc = -EPROTONOSUPPORT; 11183 goto err_free; 11184 } 11185 11186 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN); 11187 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN); 11188 11189 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK; 11190 head = &bp->ntp_fltr_hash_tbl[idx]; 11191 rcu_read_lock(); 11192 hlist_for_each_entry_rcu(fltr, head, hash) { 11193 if (bnxt_fltr_match(fltr, new_fltr)) { 11194 rcu_read_unlock(); 11195 rc = 0; 11196 goto err_free; 11197 } 11198 } 11199 rcu_read_unlock(); 11200 11201 spin_lock_bh(&bp->ntp_fltr_lock); 11202 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap, 11203 BNXT_NTP_FLTR_MAX_FLTR, 0); 11204 if (bit_id < 0) { 11205 spin_unlock_bh(&bp->ntp_fltr_lock); 11206 rc = -ENOMEM; 11207 goto err_free; 11208 } 11209 11210 new_fltr->sw_id = (u16)bit_id; 11211 new_fltr->flow_id = flow_id; 11212 new_fltr->l2_fltr_idx = l2_idx; 11213 new_fltr->rxq = rxq_index; 11214 hlist_add_head_rcu(&new_fltr->hash, head); 11215 bp->ntp_fltr_count++; 11216 spin_unlock_bh(&bp->ntp_fltr_lock); 11217 11218 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); 11219 bnxt_queue_sp_work(bp); 11220 11221 return new_fltr->sw_id; 11222 11223 err_free: 11224 kfree(new_fltr); 11225 return rc; 11226 } 11227 11228 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 11229 { 11230 int i; 11231 11232 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 11233 struct hlist_head *head; 11234 struct hlist_node *tmp; 11235 struct bnxt_ntuple_filter *fltr; 11236 int rc; 11237 11238 head = &bp->ntp_fltr_hash_tbl[i]; 11239 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 11240 bool del = false; 11241 11242 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) { 11243 if (rps_may_expire_flow(bp->dev, fltr->rxq, 11244 fltr->flow_id, 11245 fltr->sw_id)) { 11246 bnxt_hwrm_cfa_ntuple_filter_free(bp, 11247 fltr); 11248 del = true; 11249 } 11250 } else { 11251 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, 11252 fltr); 11253 if (rc) 11254 del = true; 11255 else 11256 set_bit(BNXT_FLTR_VALID, &fltr->state); 11257 } 11258 11259 if (del) { 11260 spin_lock_bh(&bp->ntp_fltr_lock); 11261 hlist_del_rcu(&fltr->hash); 11262 bp->ntp_fltr_count--; 11263 spin_unlock_bh(&bp->ntp_fltr_lock); 11264 synchronize_rcu(); 11265 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap); 11266 kfree(fltr); 11267 } 11268 } 11269 } 11270 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event)) 11271 netdev_info(bp->dev, "Receive PF driver unload event!\n"); 11272 } 11273 11274 #else 11275 11276 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 11277 { 11278 } 11279 11280 #endif /* CONFIG_RFS_ACCEL */ 11281 11282 static void bnxt_udp_tunnel_add(struct net_device *dev, 11283 struct udp_tunnel_info *ti) 11284 { 11285 struct bnxt *bp = netdev_priv(dev); 11286 11287 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) 11288 return; 11289 11290 if (!netif_running(dev)) 11291 return; 11292 11293 switch (ti->type) { 11294 case UDP_TUNNEL_TYPE_VXLAN: 11295 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port) 11296 return; 11297 11298 bp->vxlan_port_cnt++; 11299 if (bp->vxlan_port_cnt == 1) { 11300 bp->vxlan_port = ti->port; 11301 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event); 11302 bnxt_queue_sp_work(bp); 11303 } 11304 break; 11305 case UDP_TUNNEL_TYPE_GENEVE: 11306 if (bp->nge_port_cnt && bp->nge_port != ti->port) 11307 return; 11308 11309 bp->nge_port_cnt++; 11310 if (bp->nge_port_cnt == 1) { 11311 bp->nge_port = ti->port; 11312 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event); 11313 } 11314 break; 11315 default: 11316 return; 11317 } 11318 11319 bnxt_queue_sp_work(bp); 11320 } 11321 11322 static void bnxt_udp_tunnel_del(struct net_device *dev, 11323 struct udp_tunnel_info *ti) 11324 { 11325 struct bnxt *bp = netdev_priv(dev); 11326 11327 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) 11328 return; 11329 11330 if (!netif_running(dev)) 11331 return; 11332 11333 switch (ti->type) { 11334 case UDP_TUNNEL_TYPE_VXLAN: 11335 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port) 11336 return; 11337 bp->vxlan_port_cnt--; 11338 11339 if (bp->vxlan_port_cnt != 0) 11340 return; 11341 11342 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event); 11343 break; 11344 case UDP_TUNNEL_TYPE_GENEVE: 11345 if (!bp->nge_port_cnt || bp->nge_port != ti->port) 11346 return; 11347 bp->nge_port_cnt--; 11348 11349 if (bp->nge_port_cnt != 0) 11350 return; 11351 11352 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event); 11353 break; 11354 default: 11355 return; 11356 } 11357 11358 bnxt_queue_sp_work(bp); 11359 } 11360 11361 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 11362 struct net_device *dev, u32 filter_mask, 11363 int nlflags) 11364 { 11365 struct bnxt *bp = netdev_priv(dev); 11366 11367 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0, 11368 nlflags, filter_mask, NULL); 11369 } 11370 11371 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, 11372 u16 flags, struct netlink_ext_ack *extack) 11373 { 11374 struct bnxt *bp = netdev_priv(dev); 11375 struct nlattr *attr, *br_spec; 11376 int rem, rc = 0; 11377 11378 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp)) 11379 return -EOPNOTSUPP; 11380 11381 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 11382 if (!br_spec) 11383 return -EINVAL; 11384 11385 nla_for_each_nested(attr, br_spec, rem) { 11386 u16 mode; 11387 11388 if (nla_type(attr) != IFLA_BRIDGE_MODE) 11389 continue; 11390 11391 if (nla_len(attr) < sizeof(mode)) 11392 return -EINVAL; 11393 11394 mode = nla_get_u16(attr); 11395 if (mode == bp->br_mode) 11396 break; 11397 11398 rc = bnxt_hwrm_set_br_mode(bp, mode); 11399 if (!rc) 11400 bp->br_mode = mode; 11401 break; 11402 } 11403 return rc; 11404 } 11405 11406 int bnxt_get_port_parent_id(struct net_device *dev, 11407 struct netdev_phys_item_id *ppid) 11408 { 11409 struct bnxt *bp = netdev_priv(dev); 11410 11411 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV) 11412 return -EOPNOTSUPP; 11413 11414 /* The PF and it's VF-reps only support the switchdev framework */ 11415 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_DSN_VALID)) 11416 return -EOPNOTSUPP; 11417 11418 ppid->id_len = sizeof(bp->dsn); 11419 memcpy(ppid->id, bp->dsn, ppid->id_len); 11420 11421 return 0; 11422 } 11423 11424 static struct devlink_port *bnxt_get_devlink_port(struct net_device *dev) 11425 { 11426 struct bnxt *bp = netdev_priv(dev); 11427 11428 return &bp->dl_port; 11429 } 11430 11431 static const struct net_device_ops bnxt_netdev_ops = { 11432 .ndo_open = bnxt_open, 11433 .ndo_start_xmit = bnxt_start_xmit, 11434 .ndo_stop = bnxt_close, 11435 .ndo_get_stats64 = bnxt_get_stats64, 11436 .ndo_set_rx_mode = bnxt_set_rx_mode, 11437 .ndo_do_ioctl = bnxt_ioctl, 11438 .ndo_validate_addr = eth_validate_addr, 11439 .ndo_set_mac_address = bnxt_change_mac_addr, 11440 .ndo_change_mtu = bnxt_change_mtu, 11441 .ndo_fix_features = bnxt_fix_features, 11442 .ndo_set_features = bnxt_set_features, 11443 .ndo_tx_timeout = bnxt_tx_timeout, 11444 #ifdef CONFIG_BNXT_SRIOV 11445 .ndo_get_vf_config = bnxt_get_vf_config, 11446 .ndo_set_vf_mac = bnxt_set_vf_mac, 11447 .ndo_set_vf_vlan = bnxt_set_vf_vlan, 11448 .ndo_set_vf_rate = bnxt_set_vf_bw, 11449 .ndo_set_vf_link_state = bnxt_set_vf_link_state, 11450 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk, 11451 .ndo_set_vf_trust = bnxt_set_vf_trust, 11452 #endif 11453 .ndo_setup_tc = bnxt_setup_tc, 11454 #ifdef CONFIG_RFS_ACCEL 11455 .ndo_rx_flow_steer = bnxt_rx_flow_steer, 11456 #endif 11457 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add, 11458 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del, 11459 .ndo_bpf = bnxt_xdp, 11460 .ndo_xdp_xmit = bnxt_xdp_xmit, 11461 .ndo_bridge_getlink = bnxt_bridge_getlink, 11462 .ndo_bridge_setlink = bnxt_bridge_setlink, 11463 .ndo_get_devlink_port = bnxt_get_devlink_port, 11464 }; 11465 11466 static void bnxt_remove_one(struct pci_dev *pdev) 11467 { 11468 struct net_device *dev = pci_get_drvdata(pdev); 11469 struct bnxt *bp = netdev_priv(dev); 11470 11471 if (BNXT_PF(bp)) 11472 bnxt_sriov_disable(bp); 11473 11474 bnxt_dl_fw_reporters_destroy(bp, true); 11475 if (BNXT_PF(bp)) 11476 devlink_port_type_clear(&bp->dl_port); 11477 pci_disable_pcie_error_reporting(pdev); 11478 unregister_netdev(dev); 11479 bnxt_dl_unregister(bp); 11480 bnxt_shutdown_tc(bp); 11481 bnxt_cancel_sp_work(bp); 11482 bp->sp_event = 0; 11483 11484 bnxt_clear_int_mode(bp); 11485 bnxt_hwrm_func_drv_unrgtr(bp); 11486 bnxt_free_hwrm_resources(bp); 11487 bnxt_free_hwrm_short_cmd_req(bp); 11488 bnxt_ethtool_free(bp); 11489 bnxt_dcb_free(bp); 11490 kfree(bp->edev); 11491 bp->edev = NULL; 11492 kfree(bp->fw_health); 11493 bp->fw_health = NULL; 11494 bnxt_cleanup_pci(bp); 11495 bnxt_free_ctx_mem(bp); 11496 kfree(bp->ctx); 11497 bp->ctx = NULL; 11498 bnxt_free_port_stats(bp); 11499 free_netdev(dev); 11500 } 11501 11502 static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt) 11503 { 11504 int rc = 0; 11505 struct bnxt_link_info *link_info = &bp->link_info; 11506 11507 rc = bnxt_hwrm_phy_qcaps(bp); 11508 if (rc) { 11509 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n", 11510 rc); 11511 return rc; 11512 } 11513 if (!fw_dflt) 11514 return 0; 11515 11516 rc = bnxt_update_link(bp, false); 11517 if (rc) { 11518 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n", 11519 rc); 11520 return rc; 11521 } 11522 11523 /* Older firmware does not have supported_auto_speeds, so assume 11524 * that all supported speeds can be autonegotiated. 11525 */ 11526 if (link_info->auto_link_speeds && !link_info->support_auto_speeds) 11527 link_info->support_auto_speeds = link_info->support_speeds; 11528 11529 bnxt_init_ethtool_link_settings(bp); 11530 return 0; 11531 } 11532 11533 static int bnxt_get_max_irq(struct pci_dev *pdev) 11534 { 11535 u16 ctrl; 11536 11537 if (!pdev->msix_cap) 11538 return 1; 11539 11540 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 11541 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; 11542 } 11543 11544 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, 11545 int *max_cp) 11546 { 11547 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 11548 int max_ring_grps = 0, max_irq; 11549 11550 *max_tx = hw_resc->max_tx_rings; 11551 *max_rx = hw_resc->max_rx_rings; 11552 *max_cp = bnxt_get_max_func_cp_rings_for_en(bp); 11553 max_irq = min_t(int, bnxt_get_max_func_irqs(bp) - 11554 bnxt_get_ulp_msix_num(bp), 11555 hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp)); 11556 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 11557 *max_cp = min_t(int, *max_cp, max_irq); 11558 max_ring_grps = hw_resc->max_hw_ring_grps; 11559 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) { 11560 *max_cp -= 1; 11561 *max_rx -= 2; 11562 } 11563 if (bp->flags & BNXT_FLAG_AGG_RINGS) 11564 *max_rx >>= 1; 11565 if (bp->flags & BNXT_FLAG_CHIP_P5) { 11566 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false); 11567 /* On P5 chips, max_cp output param should be available NQs */ 11568 *max_cp = max_irq; 11569 } 11570 *max_rx = min_t(int, *max_rx, max_ring_grps); 11571 } 11572 11573 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared) 11574 { 11575 int rx, tx, cp; 11576 11577 _bnxt_get_max_rings(bp, &rx, &tx, &cp); 11578 *max_rx = rx; 11579 *max_tx = tx; 11580 if (!rx || !tx || !cp) 11581 return -ENOMEM; 11582 11583 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared); 11584 } 11585 11586 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx, 11587 bool shared) 11588 { 11589 int rc; 11590 11591 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 11592 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) { 11593 /* Not enough rings, try disabling agg rings. */ 11594 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 11595 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 11596 if (rc) { 11597 /* set BNXT_FLAG_AGG_RINGS back for consistency */ 11598 bp->flags |= BNXT_FLAG_AGG_RINGS; 11599 return rc; 11600 } 11601 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 11602 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 11603 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 11604 bnxt_set_ring_params(bp); 11605 } 11606 11607 if (bp->flags & BNXT_FLAG_ROCE_CAP) { 11608 int max_cp, max_stat, max_irq; 11609 11610 /* Reserve minimum resources for RoCE */ 11611 max_cp = bnxt_get_max_func_cp_rings(bp); 11612 max_stat = bnxt_get_max_func_stat_ctxs(bp); 11613 max_irq = bnxt_get_max_func_irqs(bp); 11614 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS || 11615 max_irq <= BNXT_MIN_ROCE_CP_RINGS || 11616 max_stat <= BNXT_MIN_ROCE_STAT_CTXS) 11617 return 0; 11618 11619 max_cp -= BNXT_MIN_ROCE_CP_RINGS; 11620 max_irq -= BNXT_MIN_ROCE_CP_RINGS; 11621 max_stat -= BNXT_MIN_ROCE_STAT_CTXS; 11622 max_cp = min_t(int, max_cp, max_irq); 11623 max_cp = min_t(int, max_cp, max_stat); 11624 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared); 11625 if (rc) 11626 rc = 0; 11627 } 11628 return rc; 11629 } 11630 11631 /* In initial default shared ring setting, each shared ring must have a 11632 * RX/TX ring pair. 11633 */ 11634 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp) 11635 { 11636 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings); 11637 bp->rx_nr_rings = bp->cp_nr_rings; 11638 bp->tx_nr_rings_per_tc = bp->cp_nr_rings; 11639 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 11640 } 11641 11642 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh) 11643 { 11644 int dflt_rings, max_rx_rings, max_tx_rings, rc; 11645 11646 if (!bnxt_can_reserve_rings(bp)) 11647 return 0; 11648 11649 if (sh) 11650 bp->flags |= BNXT_FLAG_SHARED_RINGS; 11651 dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues(); 11652 /* Reduce default rings on multi-port cards so that total default 11653 * rings do not exceed CPU count. 11654 */ 11655 if (bp->port_count > 1) { 11656 int max_rings = 11657 max_t(int, num_online_cpus() / bp->port_count, 1); 11658 11659 dflt_rings = min_t(int, dflt_rings, max_rings); 11660 } 11661 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh); 11662 if (rc) 11663 return rc; 11664 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings); 11665 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings); 11666 if (sh) 11667 bnxt_trim_dflt_sh_rings(bp); 11668 else 11669 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings; 11670 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 11671 11672 rc = __bnxt_reserve_rings(bp); 11673 if (rc) 11674 netdev_warn(bp->dev, "Unable to reserve tx rings\n"); 11675 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 11676 if (sh) 11677 bnxt_trim_dflt_sh_rings(bp); 11678 11679 /* Rings may have been trimmed, re-reserve the trimmed rings. */ 11680 if (bnxt_need_reserve_rings(bp)) { 11681 rc = __bnxt_reserve_rings(bp); 11682 if (rc) 11683 netdev_warn(bp->dev, "2nd rings reservation failed.\n"); 11684 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 11685 } 11686 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 11687 bp->rx_nr_rings++; 11688 bp->cp_nr_rings++; 11689 } 11690 if (rc) { 11691 bp->tx_nr_rings = 0; 11692 bp->rx_nr_rings = 0; 11693 } 11694 return rc; 11695 } 11696 11697 static int bnxt_init_dflt_ring_mode(struct bnxt *bp) 11698 { 11699 int rc; 11700 11701 if (bp->tx_nr_rings) 11702 return 0; 11703 11704 bnxt_ulp_irq_stop(bp); 11705 bnxt_clear_int_mode(bp); 11706 rc = bnxt_set_dflt_rings(bp, true); 11707 if (rc) { 11708 netdev_err(bp->dev, "Not enough rings available.\n"); 11709 goto init_dflt_ring_err; 11710 } 11711 rc = bnxt_init_int_mode(bp); 11712 if (rc) 11713 goto init_dflt_ring_err; 11714 11715 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 11716 if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) { 11717 bp->flags |= BNXT_FLAG_RFS; 11718 bp->dev->features |= NETIF_F_NTUPLE; 11719 } 11720 init_dflt_ring_err: 11721 bnxt_ulp_irq_restart(bp, rc); 11722 return rc; 11723 } 11724 11725 int bnxt_restore_pf_fw_resources(struct bnxt *bp) 11726 { 11727 int rc; 11728 11729 ASSERT_RTNL(); 11730 bnxt_hwrm_func_qcaps(bp); 11731 11732 if (netif_running(bp->dev)) 11733 __bnxt_close_nic(bp, true, false); 11734 11735 bnxt_ulp_irq_stop(bp); 11736 bnxt_clear_int_mode(bp); 11737 rc = bnxt_init_int_mode(bp); 11738 bnxt_ulp_irq_restart(bp, rc); 11739 11740 if (netif_running(bp->dev)) { 11741 if (rc) 11742 dev_close(bp->dev); 11743 else 11744 rc = bnxt_open_nic(bp, true, false); 11745 } 11746 11747 return rc; 11748 } 11749 11750 static int bnxt_init_mac_addr(struct bnxt *bp) 11751 { 11752 int rc = 0; 11753 11754 if (BNXT_PF(bp)) { 11755 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN); 11756 } else { 11757 #ifdef CONFIG_BNXT_SRIOV 11758 struct bnxt_vf_info *vf = &bp->vf; 11759 bool strict_approval = true; 11760 11761 if (is_valid_ether_addr(vf->mac_addr)) { 11762 /* overwrite netdev dev_addr with admin VF MAC */ 11763 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN); 11764 /* Older PF driver or firmware may not approve this 11765 * correctly. 11766 */ 11767 strict_approval = false; 11768 } else { 11769 eth_hw_addr_random(bp->dev); 11770 } 11771 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval); 11772 #endif 11773 } 11774 return rc; 11775 } 11776 11777 #define BNXT_VPD_LEN 512 11778 static void bnxt_vpd_read_info(struct bnxt *bp) 11779 { 11780 struct pci_dev *pdev = bp->pdev; 11781 int i, len, pos, ro_size; 11782 ssize_t vpd_size; 11783 u8 *vpd_data; 11784 11785 vpd_data = kmalloc(BNXT_VPD_LEN, GFP_KERNEL); 11786 if (!vpd_data) 11787 return; 11788 11789 vpd_size = pci_read_vpd(pdev, 0, BNXT_VPD_LEN, vpd_data); 11790 if (vpd_size <= 0) { 11791 netdev_err(bp->dev, "Unable to read VPD\n"); 11792 goto exit; 11793 } 11794 11795 i = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA); 11796 if (i < 0) { 11797 netdev_err(bp->dev, "VPD READ-Only not found\n"); 11798 goto exit; 11799 } 11800 11801 ro_size = pci_vpd_lrdt_size(&vpd_data[i]); 11802 i += PCI_VPD_LRDT_TAG_SIZE; 11803 if (i + ro_size > vpd_size) 11804 goto exit; 11805 11806 pos = pci_vpd_find_info_keyword(vpd_data, i, ro_size, 11807 PCI_VPD_RO_KEYWORD_PARTNO); 11808 if (pos < 0) 11809 goto read_sn; 11810 11811 len = pci_vpd_info_field_size(&vpd_data[pos]); 11812 pos += PCI_VPD_INFO_FLD_HDR_SIZE; 11813 if (len + pos > vpd_size) 11814 goto read_sn; 11815 11816 strlcpy(bp->board_partno, &vpd_data[pos], min(len, BNXT_VPD_FLD_LEN)); 11817 11818 read_sn: 11819 pos = pci_vpd_find_info_keyword(vpd_data, i, ro_size, 11820 PCI_VPD_RO_KEYWORD_SERIALNO); 11821 if (pos < 0) 11822 goto exit; 11823 11824 len = pci_vpd_info_field_size(&vpd_data[pos]); 11825 pos += PCI_VPD_INFO_FLD_HDR_SIZE; 11826 if (len + pos > vpd_size) 11827 goto exit; 11828 11829 strlcpy(bp->board_serialno, &vpd_data[pos], min(len, BNXT_VPD_FLD_LEN)); 11830 exit: 11831 kfree(vpd_data); 11832 } 11833 11834 static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[]) 11835 { 11836 struct pci_dev *pdev = bp->pdev; 11837 u64 qword; 11838 11839 qword = pci_get_dsn(pdev); 11840 if (!qword) { 11841 netdev_info(bp->dev, "Unable to read adapter's DSN\n"); 11842 return -EOPNOTSUPP; 11843 } 11844 11845 put_unaligned_le64(qword, dsn); 11846 11847 bp->flags |= BNXT_FLAG_DSN_VALID; 11848 return 0; 11849 } 11850 11851 static int bnxt_map_db_bar(struct bnxt *bp) 11852 { 11853 if (!bp->db_size) 11854 return -ENODEV; 11855 bp->bar1 = pci_iomap(bp->pdev, 2, bp->db_size); 11856 if (!bp->bar1) 11857 return -ENOMEM; 11858 return 0; 11859 } 11860 11861 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 11862 { 11863 struct net_device *dev; 11864 struct bnxt *bp; 11865 int rc, max_irqs; 11866 11867 if (pci_is_bridge(pdev)) 11868 return -ENODEV; 11869 11870 /* Clear any pending DMA transactions from crash kernel 11871 * while loading driver in capture kernel. 11872 */ 11873 if (is_kdump_kernel()) { 11874 pci_clear_master(pdev); 11875 pcie_flr(pdev); 11876 } 11877 11878 max_irqs = bnxt_get_max_irq(pdev); 11879 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs); 11880 if (!dev) 11881 return -ENOMEM; 11882 11883 bp = netdev_priv(dev); 11884 bnxt_set_max_func_irqs(bp, max_irqs); 11885 11886 if (bnxt_vf_pciid(ent->driver_data)) 11887 bp->flags |= BNXT_FLAG_VF; 11888 11889 if (pdev->msix_cap) 11890 bp->flags |= BNXT_FLAG_MSIX_CAP; 11891 11892 rc = bnxt_init_board(pdev, dev); 11893 if (rc < 0) 11894 goto init_err_free; 11895 11896 dev->netdev_ops = &bnxt_netdev_ops; 11897 dev->watchdog_timeo = BNXT_TX_TIMEOUT; 11898 dev->ethtool_ops = &bnxt_ethtool_ops; 11899 pci_set_drvdata(pdev, dev); 11900 11901 bnxt_vpd_read_info(bp); 11902 11903 rc = bnxt_alloc_hwrm_resources(bp); 11904 if (rc) 11905 goto init_err_pci_clean; 11906 11907 mutex_init(&bp->hwrm_cmd_lock); 11908 mutex_init(&bp->link_lock); 11909 11910 rc = bnxt_fw_init_one_p1(bp); 11911 if (rc) 11912 goto init_err_pci_clean; 11913 11914 if (BNXT_CHIP_P5(bp)) 11915 bp->flags |= BNXT_FLAG_CHIP_P5; 11916 11917 rc = bnxt_fw_init_one_p2(bp); 11918 if (rc) 11919 goto init_err_pci_clean; 11920 11921 rc = bnxt_map_db_bar(bp); 11922 if (rc) { 11923 dev_err(&pdev->dev, "Cannot map doorbell BAR rc = %d, aborting\n", 11924 rc); 11925 goto init_err_pci_clean; 11926 } 11927 11928 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 11929 NETIF_F_TSO | NETIF_F_TSO6 | 11930 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 11931 NETIF_F_GSO_IPXIP4 | 11932 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 11933 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH | 11934 NETIF_F_RXCSUM | NETIF_F_GRO; 11935 11936 if (BNXT_SUPPORTS_TPA(bp)) 11937 dev->hw_features |= NETIF_F_LRO; 11938 11939 dev->hw_enc_features = 11940 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 11941 NETIF_F_TSO | NETIF_F_TSO6 | 11942 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 11943 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 11944 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL; 11945 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM | 11946 NETIF_F_GSO_GRE_CSUM; 11947 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA; 11948 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 11949 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX; 11950 if (BNXT_SUPPORTS_TPA(bp)) 11951 dev->hw_features |= NETIF_F_GRO_HW; 11952 dev->features |= dev->hw_features | NETIF_F_HIGHDMA; 11953 if (dev->features & NETIF_F_GRO_HW) 11954 dev->features &= ~NETIF_F_LRO; 11955 dev->priv_flags |= IFF_UNICAST_FLT; 11956 11957 #ifdef CONFIG_BNXT_SRIOV 11958 init_waitqueue_head(&bp->sriov_cfg_wait); 11959 mutex_init(&bp->sriov_lock); 11960 #endif 11961 if (BNXT_SUPPORTS_TPA(bp)) { 11962 bp->gro_func = bnxt_gro_func_5730x; 11963 if (BNXT_CHIP_P4(bp)) 11964 bp->gro_func = bnxt_gro_func_5731x; 11965 else if (BNXT_CHIP_P5(bp)) 11966 bp->gro_func = bnxt_gro_func_5750x; 11967 } 11968 if (!BNXT_CHIP_P4_PLUS(bp)) 11969 bp->flags |= BNXT_FLAG_DOUBLE_DB; 11970 11971 bp->ulp_probe = bnxt_ulp_probe; 11972 11973 rc = bnxt_init_mac_addr(bp); 11974 if (rc) { 11975 dev_err(&pdev->dev, "Unable to initialize mac address.\n"); 11976 rc = -EADDRNOTAVAIL; 11977 goto init_err_pci_clean; 11978 } 11979 11980 if (BNXT_PF(bp)) { 11981 /* Read the adapter's DSN to use as the eswitch switch_id */ 11982 rc = bnxt_pcie_dsn_get(bp, bp->dsn); 11983 } 11984 11985 /* MTU range: 60 - FW defined max */ 11986 dev->min_mtu = ETH_ZLEN; 11987 dev->max_mtu = bp->max_mtu; 11988 11989 rc = bnxt_probe_phy(bp, true); 11990 if (rc) 11991 goto init_err_pci_clean; 11992 11993 bnxt_set_rx_skb_mode(bp, false); 11994 bnxt_set_tpa_flags(bp); 11995 bnxt_set_ring_params(bp); 11996 rc = bnxt_set_dflt_rings(bp, true); 11997 if (rc) { 11998 netdev_err(bp->dev, "Not enough rings available.\n"); 11999 rc = -ENOMEM; 12000 goto init_err_pci_clean; 12001 } 12002 12003 bnxt_fw_init_one_p3(bp); 12004 12005 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX) 12006 bp->flags |= BNXT_FLAG_STRIP_VLAN; 12007 12008 rc = bnxt_init_int_mode(bp); 12009 if (rc) 12010 goto init_err_pci_clean; 12011 12012 /* No TC has been set yet and rings may have been trimmed due to 12013 * limited MSIX, so we re-initialize the TX rings per TC. 12014 */ 12015 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 12016 12017 if (BNXT_PF(bp)) { 12018 if (!bnxt_pf_wq) { 12019 bnxt_pf_wq = 12020 create_singlethread_workqueue("bnxt_pf_wq"); 12021 if (!bnxt_pf_wq) { 12022 dev_err(&pdev->dev, "Unable to create workqueue.\n"); 12023 goto init_err_pci_clean; 12024 } 12025 } 12026 bnxt_init_tc(bp); 12027 } 12028 12029 bnxt_dl_register(bp); 12030 12031 rc = register_netdev(dev); 12032 if (rc) 12033 goto init_err_cleanup; 12034 12035 if (BNXT_PF(bp)) 12036 devlink_port_type_eth_set(&bp->dl_port, bp->dev); 12037 bnxt_dl_fw_reporters_create(bp); 12038 12039 netdev_info(dev, "%s found at mem %lx, node addr %pM\n", 12040 board_info[ent->driver_data].name, 12041 (long)pci_resource_start(pdev, 0), dev->dev_addr); 12042 pcie_print_link_status(pdev); 12043 12044 return 0; 12045 12046 init_err_cleanup: 12047 bnxt_dl_unregister(bp); 12048 bnxt_shutdown_tc(bp); 12049 bnxt_clear_int_mode(bp); 12050 12051 init_err_pci_clean: 12052 bnxt_hwrm_func_drv_unrgtr(bp); 12053 bnxt_free_hwrm_short_cmd_req(bp); 12054 bnxt_free_hwrm_resources(bp); 12055 kfree(bp->fw_health); 12056 bp->fw_health = NULL; 12057 bnxt_cleanup_pci(bp); 12058 bnxt_free_ctx_mem(bp); 12059 kfree(bp->ctx); 12060 bp->ctx = NULL; 12061 12062 init_err_free: 12063 free_netdev(dev); 12064 return rc; 12065 } 12066 12067 static void bnxt_shutdown(struct pci_dev *pdev) 12068 { 12069 struct net_device *dev = pci_get_drvdata(pdev); 12070 struct bnxt *bp; 12071 12072 if (!dev) 12073 return; 12074 12075 rtnl_lock(); 12076 bp = netdev_priv(dev); 12077 if (!bp) 12078 goto shutdown_exit; 12079 12080 if (netif_running(dev)) 12081 dev_close(dev); 12082 12083 bnxt_ulp_shutdown(bp); 12084 bnxt_clear_int_mode(bp); 12085 pci_disable_device(pdev); 12086 12087 if (system_state == SYSTEM_POWER_OFF) { 12088 pci_wake_from_d3(pdev, bp->wol); 12089 pci_set_power_state(pdev, PCI_D3hot); 12090 } 12091 12092 shutdown_exit: 12093 rtnl_unlock(); 12094 } 12095 12096 #ifdef CONFIG_PM_SLEEP 12097 static int bnxt_suspend(struct device *device) 12098 { 12099 struct net_device *dev = dev_get_drvdata(device); 12100 struct bnxt *bp = netdev_priv(dev); 12101 int rc = 0; 12102 12103 rtnl_lock(); 12104 bnxt_ulp_stop(bp); 12105 if (netif_running(dev)) { 12106 netif_device_detach(dev); 12107 rc = bnxt_close(dev); 12108 } 12109 bnxt_hwrm_func_drv_unrgtr(bp); 12110 pci_disable_device(bp->pdev); 12111 bnxt_free_ctx_mem(bp); 12112 kfree(bp->ctx); 12113 bp->ctx = NULL; 12114 rtnl_unlock(); 12115 return rc; 12116 } 12117 12118 static int bnxt_resume(struct device *device) 12119 { 12120 struct net_device *dev = dev_get_drvdata(device); 12121 struct bnxt *bp = netdev_priv(dev); 12122 int rc = 0; 12123 12124 rtnl_lock(); 12125 rc = pci_enable_device(bp->pdev); 12126 if (rc) { 12127 netdev_err(dev, "Cannot re-enable PCI device during resume, err = %d\n", 12128 rc); 12129 goto resume_exit; 12130 } 12131 pci_set_master(bp->pdev); 12132 if (bnxt_hwrm_ver_get(bp)) { 12133 rc = -ENODEV; 12134 goto resume_exit; 12135 } 12136 rc = bnxt_hwrm_func_reset(bp); 12137 if (rc) { 12138 rc = -EBUSY; 12139 goto resume_exit; 12140 } 12141 12142 if (bnxt_hwrm_queue_qportcfg(bp)) { 12143 rc = -ENODEV; 12144 goto resume_exit; 12145 } 12146 12147 if (bp->hwrm_spec_code >= 0x10803) { 12148 if (bnxt_alloc_ctx_mem(bp)) { 12149 rc = -ENODEV; 12150 goto resume_exit; 12151 } 12152 } 12153 if (BNXT_NEW_RM(bp)) 12154 bnxt_hwrm_func_resc_qcaps(bp, false); 12155 12156 if (bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false)) { 12157 rc = -ENODEV; 12158 goto resume_exit; 12159 } 12160 12161 bnxt_get_wol_settings(bp); 12162 if (netif_running(dev)) { 12163 rc = bnxt_open(dev); 12164 if (!rc) 12165 netif_device_attach(dev); 12166 } 12167 12168 resume_exit: 12169 bnxt_ulp_start(bp, rc); 12170 rtnl_unlock(); 12171 return rc; 12172 } 12173 12174 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume); 12175 #define BNXT_PM_OPS (&bnxt_pm_ops) 12176 12177 #else 12178 12179 #define BNXT_PM_OPS NULL 12180 12181 #endif /* CONFIG_PM_SLEEP */ 12182 12183 /** 12184 * bnxt_io_error_detected - called when PCI error is detected 12185 * @pdev: Pointer to PCI device 12186 * @state: The current pci connection state 12187 * 12188 * This function is called after a PCI bus error affecting 12189 * this device has been detected. 12190 */ 12191 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev, 12192 pci_channel_state_t state) 12193 { 12194 struct net_device *netdev = pci_get_drvdata(pdev); 12195 struct bnxt *bp = netdev_priv(netdev); 12196 12197 netdev_info(netdev, "PCI I/O error detected\n"); 12198 12199 rtnl_lock(); 12200 netif_device_detach(netdev); 12201 12202 bnxt_ulp_stop(bp); 12203 12204 if (state == pci_channel_io_perm_failure) { 12205 rtnl_unlock(); 12206 return PCI_ERS_RESULT_DISCONNECT; 12207 } 12208 12209 if (netif_running(netdev)) 12210 bnxt_close(netdev); 12211 12212 pci_disable_device(pdev); 12213 rtnl_unlock(); 12214 12215 /* Request a slot slot reset. */ 12216 return PCI_ERS_RESULT_NEED_RESET; 12217 } 12218 12219 /** 12220 * bnxt_io_slot_reset - called after the pci bus has been reset. 12221 * @pdev: Pointer to PCI device 12222 * 12223 * Restart the card from scratch, as if from a cold-boot. 12224 * At this point, the card has exprienced a hard reset, 12225 * followed by fixups by BIOS, and has its config space 12226 * set up identically to what it was at cold boot. 12227 */ 12228 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev) 12229 { 12230 struct net_device *netdev = pci_get_drvdata(pdev); 12231 struct bnxt *bp = netdev_priv(netdev); 12232 int err = 0; 12233 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT; 12234 12235 netdev_info(bp->dev, "PCI Slot Reset\n"); 12236 12237 rtnl_lock(); 12238 12239 if (pci_enable_device(pdev)) { 12240 dev_err(&pdev->dev, 12241 "Cannot re-enable PCI device after reset.\n"); 12242 } else { 12243 pci_set_master(pdev); 12244 12245 err = bnxt_hwrm_func_reset(bp); 12246 if (!err && netif_running(netdev)) 12247 err = bnxt_open(netdev); 12248 12249 if (!err) 12250 result = PCI_ERS_RESULT_RECOVERED; 12251 bnxt_ulp_start(bp, err); 12252 } 12253 12254 if (result != PCI_ERS_RESULT_RECOVERED) { 12255 if (netif_running(netdev)) 12256 dev_close(netdev); 12257 pci_disable_device(pdev); 12258 } 12259 12260 rtnl_unlock(); 12261 12262 return result; 12263 } 12264 12265 /** 12266 * bnxt_io_resume - called when traffic can start flowing again. 12267 * @pdev: Pointer to PCI device 12268 * 12269 * This callback is called when the error recovery driver tells 12270 * us that its OK to resume normal operation. 12271 */ 12272 static void bnxt_io_resume(struct pci_dev *pdev) 12273 { 12274 struct net_device *netdev = pci_get_drvdata(pdev); 12275 12276 rtnl_lock(); 12277 12278 netif_device_attach(netdev); 12279 12280 rtnl_unlock(); 12281 } 12282 12283 static const struct pci_error_handlers bnxt_err_handler = { 12284 .error_detected = bnxt_io_error_detected, 12285 .slot_reset = bnxt_io_slot_reset, 12286 .resume = bnxt_io_resume 12287 }; 12288 12289 static struct pci_driver bnxt_pci_driver = { 12290 .name = DRV_MODULE_NAME, 12291 .id_table = bnxt_pci_tbl, 12292 .probe = bnxt_init_one, 12293 .remove = bnxt_remove_one, 12294 .shutdown = bnxt_shutdown, 12295 .driver.pm = BNXT_PM_OPS, 12296 .err_handler = &bnxt_err_handler, 12297 #if defined(CONFIG_BNXT_SRIOV) 12298 .sriov_configure = bnxt_sriov_configure, 12299 #endif 12300 }; 12301 12302 static int __init bnxt_init(void) 12303 { 12304 bnxt_debug_init(); 12305 return pci_register_driver(&bnxt_pci_driver); 12306 } 12307 12308 static void __exit bnxt_exit(void) 12309 { 12310 pci_unregister_driver(&bnxt_pci_driver); 12311 if (bnxt_pf_wq) 12312 destroy_workqueue(bnxt_pf_wq); 12313 bnxt_debug_exit(); 12314 } 12315 12316 module_init(bnxt_init); 12317 module_exit(bnxt_exit); 12318