1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 13 #include <linux/stringify.h> 14 #include <linux/kernel.h> 15 #include <linux/timer.h> 16 #include <linux/errno.h> 17 #include <linux/ioport.h> 18 #include <linux/slab.h> 19 #include <linux/vmalloc.h> 20 #include <linux/interrupt.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/etherdevice.h> 24 #include <linux/skbuff.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/bitops.h> 27 #include <linux/io.h> 28 #include <linux/irq.h> 29 #include <linux/delay.h> 30 #include <asm/byteorder.h> 31 #include <asm/page.h> 32 #include <linux/time.h> 33 #include <linux/mii.h> 34 #include <linux/if.h> 35 #include <linux/if_vlan.h> 36 #include <linux/rtc.h> 37 #include <linux/bpf.h> 38 #include <net/ip.h> 39 #include <net/tcp.h> 40 #include <net/udp.h> 41 #include <net/checksum.h> 42 #include <net/ip6_checksum.h> 43 #include <net/udp_tunnel.h> 44 #include <linux/workqueue.h> 45 #include <linux/prefetch.h> 46 #include <linux/cache.h> 47 #include <linux/log2.h> 48 #include <linux/aer.h> 49 #include <linux/bitmap.h> 50 #include <linux/cpu_rmap.h> 51 52 #include "bnxt_hsi.h" 53 #include "bnxt.h" 54 #include "bnxt_ulp.h" 55 #include "bnxt_sriov.h" 56 #include "bnxt_ethtool.h" 57 #include "bnxt_dcb.h" 58 #include "bnxt_xdp.h" 59 60 #define BNXT_TX_TIMEOUT (5 * HZ) 61 62 static const char version[] = 63 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n"; 64 65 MODULE_LICENSE("GPL"); 66 MODULE_DESCRIPTION("Broadcom BCM573xx network driver"); 67 MODULE_VERSION(DRV_MODULE_VERSION); 68 69 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN) 70 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD 71 #define BNXT_RX_COPY_THRESH 256 72 73 #define BNXT_TX_PUSH_THRESH 164 74 75 enum board_idx { 76 BCM57301, 77 BCM57302, 78 BCM57304, 79 BCM57417_NPAR, 80 BCM58700, 81 BCM57311, 82 BCM57312, 83 BCM57402, 84 BCM57404, 85 BCM57406, 86 BCM57402_NPAR, 87 BCM57407, 88 BCM57412, 89 BCM57414, 90 BCM57416, 91 BCM57417, 92 BCM57412_NPAR, 93 BCM57314, 94 BCM57417_SFP, 95 BCM57416_SFP, 96 BCM57404_NPAR, 97 BCM57406_NPAR, 98 BCM57407_SFP, 99 BCM57407_NPAR, 100 BCM57414_NPAR, 101 BCM57416_NPAR, 102 BCM57452, 103 BCM57454, 104 NETXTREME_E_VF, 105 NETXTREME_C_VF, 106 }; 107 108 /* indexed by enum above */ 109 static const struct { 110 char *name; 111 } board_info[] = { 112 { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" }, 113 { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" }, 114 { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 115 { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" }, 116 { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" }, 117 { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" }, 118 { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" }, 119 { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" }, 120 { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" }, 121 { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" }, 122 { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" }, 123 { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" }, 124 { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" }, 125 { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" }, 126 { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" }, 127 { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" }, 128 { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" }, 129 { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 130 { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" }, 131 { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" }, 132 { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" }, 133 { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" }, 134 { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" }, 135 { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" }, 136 { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" }, 137 { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" }, 138 { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" }, 139 { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 140 { "Broadcom NetXtreme-E Ethernet Virtual Function" }, 141 { "Broadcom NetXtreme-C Ethernet Virtual Function" }, 142 }; 143 144 static const struct pci_device_id bnxt_pci_tbl[] = { 145 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR }, 146 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 }, 147 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 }, 148 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 }, 149 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR }, 150 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 }, 151 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 }, 152 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 }, 153 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 }, 154 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 }, 155 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 }, 156 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR }, 157 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 }, 158 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 }, 159 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 }, 160 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 }, 161 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 }, 162 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR }, 163 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 }, 164 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP }, 165 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP }, 166 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR }, 167 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR }, 168 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP }, 169 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR }, 170 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR }, 171 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR }, 172 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR }, 173 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR }, 174 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR }, 175 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 }, 176 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 }, 177 #ifdef CONFIG_BNXT_SRIOV 178 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF }, 179 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF }, 180 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF }, 181 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF }, 182 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF }, 183 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF }, 184 #endif 185 { 0 } 186 }; 187 188 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl); 189 190 static const u16 bnxt_vf_req_snif[] = { 191 HWRM_FUNC_CFG, 192 HWRM_PORT_PHY_QCFG, 193 HWRM_CFA_L2_FILTER_ALLOC, 194 }; 195 196 static const u16 bnxt_async_events_arr[] = { 197 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE, 198 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD, 199 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED, 200 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE, 201 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE, 202 }; 203 204 static bool bnxt_vf_pciid(enum board_idx idx) 205 { 206 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF); 207 } 208 209 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID) 210 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS) 211 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS) 212 213 #define BNXT_CP_DB_REARM(db, raw_cons) \ 214 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db) 215 216 #define BNXT_CP_DB(db, raw_cons) \ 217 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db) 218 219 #define BNXT_CP_DB_IRQ_DIS(db) \ 220 writel(DB_CP_IRQ_DIS_FLAGS, db) 221 222 const u16 bnxt_lhint_arr[] = { 223 TX_BD_FLAGS_LHINT_512_AND_SMALLER, 224 TX_BD_FLAGS_LHINT_512_TO_1023, 225 TX_BD_FLAGS_LHINT_1024_TO_2047, 226 TX_BD_FLAGS_LHINT_1024_TO_2047, 227 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 228 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 229 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 230 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 231 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 232 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 233 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 234 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 235 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 236 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 237 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 238 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 239 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 240 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 241 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 242 }; 243 244 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev) 245 { 246 struct bnxt *bp = netdev_priv(dev); 247 struct tx_bd *txbd; 248 struct tx_bd_ext *txbd1; 249 struct netdev_queue *txq; 250 int i; 251 dma_addr_t mapping; 252 unsigned int length, pad = 0; 253 u32 len, free_size, vlan_tag_flags, cfa_action, flags; 254 u16 prod, last_frag; 255 struct pci_dev *pdev = bp->pdev; 256 struct bnxt_tx_ring_info *txr; 257 struct bnxt_sw_tx_bd *tx_buf; 258 259 i = skb_get_queue_mapping(skb); 260 if (unlikely(i >= bp->tx_nr_rings)) { 261 dev_kfree_skb_any(skb); 262 return NETDEV_TX_OK; 263 } 264 265 txq = netdev_get_tx_queue(dev, i); 266 txr = &bp->tx_ring[bp->tx_ring_map[i]]; 267 prod = txr->tx_prod; 268 269 free_size = bnxt_tx_avail(bp, txr); 270 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) { 271 netif_tx_stop_queue(txq); 272 return NETDEV_TX_BUSY; 273 } 274 275 length = skb->len; 276 len = skb_headlen(skb); 277 last_frag = skb_shinfo(skb)->nr_frags; 278 279 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 280 281 txbd->tx_bd_opaque = prod; 282 283 tx_buf = &txr->tx_buf_ring[prod]; 284 tx_buf->skb = skb; 285 tx_buf->nr_frags = last_frag; 286 287 vlan_tag_flags = 0; 288 cfa_action = 0; 289 if (skb_vlan_tag_present(skb)) { 290 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN | 291 skb_vlan_tag_get(skb); 292 /* Currently supports 8021Q, 8021AD vlan offloads 293 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated 294 */ 295 if (skb->vlan_proto == htons(ETH_P_8021Q)) 296 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT; 297 } 298 299 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) { 300 struct tx_push_buffer *tx_push_buf = txr->tx_push; 301 struct tx_push_bd *tx_push = &tx_push_buf->push_bd; 302 struct tx_bd_ext *tx_push1 = &tx_push->txbd2; 303 void *pdata = tx_push_buf->data; 304 u64 *end; 305 int j, push_len; 306 307 /* Set COAL_NOW to be ready quickly for the next push */ 308 tx_push->tx_bd_len_flags_type = 309 cpu_to_le32((length << TX_BD_LEN_SHIFT) | 310 TX_BD_TYPE_LONG_TX_BD | 311 TX_BD_FLAGS_LHINT_512_AND_SMALLER | 312 TX_BD_FLAGS_COAL_NOW | 313 TX_BD_FLAGS_PACKET_END | 314 (2 << TX_BD_FLAGS_BD_CNT_SHIFT)); 315 316 if (skb->ip_summed == CHECKSUM_PARTIAL) 317 tx_push1->tx_bd_hsize_lflags = 318 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 319 else 320 tx_push1->tx_bd_hsize_lflags = 0; 321 322 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 323 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action); 324 325 end = pdata + length; 326 end = PTR_ALIGN(end, 8) - 1; 327 *end = 0; 328 329 skb_copy_from_linear_data(skb, pdata, len); 330 pdata += len; 331 for (j = 0; j < last_frag; j++) { 332 skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; 333 void *fptr; 334 335 fptr = skb_frag_address_safe(frag); 336 if (!fptr) 337 goto normal_tx; 338 339 memcpy(pdata, fptr, skb_frag_size(frag)); 340 pdata += skb_frag_size(frag); 341 } 342 343 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type; 344 txbd->tx_bd_haddr = txr->data_mapping; 345 prod = NEXT_TX(prod); 346 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 347 memcpy(txbd, tx_push1, sizeof(*txbd)); 348 prod = NEXT_TX(prod); 349 tx_push->doorbell = 350 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod); 351 txr->tx_prod = prod; 352 353 tx_buf->is_push = 1; 354 netdev_tx_sent_queue(txq, skb->len); 355 wmb(); /* Sync is_push and byte queue before pushing data */ 356 357 push_len = (length + sizeof(*tx_push) + 7) / 8; 358 if (push_len > 16) { 359 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16); 360 __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1, 361 (push_len - 16) << 1); 362 } else { 363 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 364 push_len); 365 } 366 367 goto tx_done; 368 } 369 370 normal_tx: 371 if (length < BNXT_MIN_PKT_SIZE) { 372 pad = BNXT_MIN_PKT_SIZE - length; 373 if (skb_pad(skb, pad)) { 374 /* SKB already freed. */ 375 tx_buf->skb = NULL; 376 return NETDEV_TX_OK; 377 } 378 length = BNXT_MIN_PKT_SIZE; 379 } 380 381 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE); 382 383 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) { 384 dev_kfree_skb_any(skb); 385 tx_buf->skb = NULL; 386 return NETDEV_TX_OK; 387 } 388 389 dma_unmap_addr_set(tx_buf, mapping, mapping); 390 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD | 391 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT); 392 393 txbd->tx_bd_haddr = cpu_to_le64(mapping); 394 395 prod = NEXT_TX(prod); 396 txbd1 = (struct tx_bd_ext *) 397 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 398 399 txbd1->tx_bd_hsize_lflags = 0; 400 if (skb_is_gso(skb)) { 401 u32 hdr_len; 402 403 if (skb->encapsulation) 404 hdr_len = skb_inner_network_offset(skb) + 405 skb_inner_network_header_len(skb) + 406 inner_tcp_hdrlen(skb); 407 else 408 hdr_len = skb_transport_offset(skb) + 409 tcp_hdrlen(skb); 410 411 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO | 412 TX_BD_FLAGS_T_IPID | 413 (hdr_len << (TX_BD_HSIZE_SHIFT - 1))); 414 length = skb_shinfo(skb)->gso_size; 415 txbd1->tx_bd_mss = cpu_to_le32(length); 416 length += hdr_len; 417 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 418 txbd1->tx_bd_hsize_lflags = 419 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 420 txbd1->tx_bd_mss = 0; 421 } 422 423 length >>= 9; 424 flags |= bnxt_lhint_arr[length]; 425 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 426 427 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 428 txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action); 429 for (i = 0; i < last_frag; i++) { 430 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 431 432 prod = NEXT_TX(prod); 433 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 434 435 len = skb_frag_size(frag); 436 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len, 437 DMA_TO_DEVICE); 438 439 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) 440 goto tx_dma_error; 441 442 tx_buf = &txr->tx_buf_ring[prod]; 443 dma_unmap_addr_set(tx_buf, mapping, mapping); 444 445 txbd->tx_bd_haddr = cpu_to_le64(mapping); 446 447 flags = len << TX_BD_LEN_SHIFT; 448 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 449 } 450 451 flags &= ~TX_BD_LEN; 452 txbd->tx_bd_len_flags_type = 453 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags | 454 TX_BD_FLAGS_PACKET_END); 455 456 netdev_tx_sent_queue(txq, skb->len); 457 458 /* Sync BD data before updating doorbell */ 459 wmb(); 460 461 prod = NEXT_TX(prod); 462 txr->tx_prod = prod; 463 464 writel(DB_KEY_TX | prod, txr->tx_doorbell); 465 writel(DB_KEY_TX | prod, txr->tx_doorbell); 466 467 tx_done: 468 469 mmiowb(); 470 471 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) { 472 netif_tx_stop_queue(txq); 473 474 /* netif_tx_stop_queue() must be done before checking 475 * tx index in bnxt_tx_avail() below, because in 476 * bnxt_tx_int(), we update tx index before checking for 477 * netif_tx_queue_stopped(). 478 */ 479 smp_mb(); 480 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh) 481 netif_tx_wake_queue(txq); 482 } 483 return NETDEV_TX_OK; 484 485 tx_dma_error: 486 last_frag = i; 487 488 /* start back at beginning and unmap skb */ 489 prod = txr->tx_prod; 490 tx_buf = &txr->tx_buf_ring[prod]; 491 tx_buf->skb = NULL; 492 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 493 skb_headlen(skb), PCI_DMA_TODEVICE); 494 prod = NEXT_TX(prod); 495 496 /* unmap remaining mapped pages */ 497 for (i = 0; i < last_frag; i++) { 498 prod = NEXT_TX(prod); 499 tx_buf = &txr->tx_buf_ring[prod]; 500 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 501 skb_frag_size(&skb_shinfo(skb)->frags[i]), 502 PCI_DMA_TODEVICE); 503 } 504 505 dev_kfree_skb_any(skb); 506 return NETDEV_TX_OK; 507 } 508 509 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts) 510 { 511 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 512 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index); 513 u16 cons = txr->tx_cons; 514 struct pci_dev *pdev = bp->pdev; 515 int i; 516 unsigned int tx_bytes = 0; 517 518 for (i = 0; i < nr_pkts; i++) { 519 struct bnxt_sw_tx_bd *tx_buf; 520 struct sk_buff *skb; 521 int j, last; 522 523 tx_buf = &txr->tx_buf_ring[cons]; 524 cons = NEXT_TX(cons); 525 skb = tx_buf->skb; 526 tx_buf->skb = NULL; 527 528 if (tx_buf->is_push) { 529 tx_buf->is_push = 0; 530 goto next_tx_int; 531 } 532 533 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 534 skb_headlen(skb), PCI_DMA_TODEVICE); 535 last = tx_buf->nr_frags; 536 537 for (j = 0; j < last; j++) { 538 cons = NEXT_TX(cons); 539 tx_buf = &txr->tx_buf_ring[cons]; 540 dma_unmap_page( 541 &pdev->dev, 542 dma_unmap_addr(tx_buf, mapping), 543 skb_frag_size(&skb_shinfo(skb)->frags[j]), 544 PCI_DMA_TODEVICE); 545 } 546 547 next_tx_int: 548 cons = NEXT_TX(cons); 549 550 tx_bytes += skb->len; 551 dev_kfree_skb_any(skb); 552 } 553 554 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes); 555 txr->tx_cons = cons; 556 557 /* Need to make the tx_cons update visible to bnxt_start_xmit() 558 * before checking for netif_tx_queue_stopped(). Without the 559 * memory barrier, there is a small possibility that bnxt_start_xmit() 560 * will miss it and cause the queue to be stopped forever. 561 */ 562 smp_mb(); 563 564 if (unlikely(netif_tx_queue_stopped(txq)) && 565 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) { 566 __netif_tx_lock(txq, smp_processor_id()); 567 if (netif_tx_queue_stopped(txq) && 568 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh && 569 txr->dev_state != BNXT_DEV_STATE_CLOSING) 570 netif_tx_wake_queue(txq); 571 __netif_tx_unlock(txq); 572 } 573 } 574 575 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping, 576 gfp_t gfp) 577 { 578 struct device *dev = &bp->pdev->dev; 579 struct page *page; 580 581 page = alloc_page(gfp); 582 if (!page) 583 return NULL; 584 585 *mapping = dma_map_page(dev, page, 0, PAGE_SIZE, bp->rx_dir); 586 if (dma_mapping_error(dev, *mapping)) { 587 __free_page(page); 588 return NULL; 589 } 590 *mapping += bp->rx_dma_offset; 591 return page; 592 } 593 594 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping, 595 gfp_t gfp) 596 { 597 u8 *data; 598 struct pci_dev *pdev = bp->pdev; 599 600 data = kmalloc(bp->rx_buf_size, gfp); 601 if (!data) 602 return NULL; 603 604 *mapping = dma_map_single(&pdev->dev, data + bp->rx_dma_offset, 605 bp->rx_buf_use_size, bp->rx_dir); 606 607 if (dma_mapping_error(&pdev->dev, *mapping)) { 608 kfree(data); 609 data = NULL; 610 } 611 return data; 612 } 613 614 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 615 u16 prod, gfp_t gfp) 616 { 617 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 618 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod]; 619 dma_addr_t mapping; 620 621 if (BNXT_RX_PAGE_MODE(bp)) { 622 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp); 623 624 if (!page) 625 return -ENOMEM; 626 627 rx_buf->data = page; 628 rx_buf->data_ptr = page_address(page) + bp->rx_offset; 629 } else { 630 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp); 631 632 if (!data) 633 return -ENOMEM; 634 635 rx_buf->data = data; 636 rx_buf->data_ptr = data + bp->rx_offset; 637 } 638 rx_buf->mapping = mapping; 639 640 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 641 return 0; 642 } 643 644 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data) 645 { 646 u16 prod = rxr->rx_prod; 647 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 648 struct rx_bd *cons_bd, *prod_bd; 649 650 prod_rx_buf = &rxr->rx_buf_ring[prod]; 651 cons_rx_buf = &rxr->rx_buf_ring[cons]; 652 653 prod_rx_buf->data = data; 654 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr; 655 656 prod_rx_buf->mapping = cons_rx_buf->mapping; 657 658 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 659 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; 660 661 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr; 662 } 663 664 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) 665 { 666 u16 next, max = rxr->rx_agg_bmap_size; 667 668 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx); 669 if (next >= max) 670 next = find_first_zero_bit(rxr->rx_agg_bmap, max); 671 return next; 672 } 673 674 static inline int bnxt_alloc_rx_page(struct bnxt *bp, 675 struct bnxt_rx_ring_info *rxr, 676 u16 prod, gfp_t gfp) 677 { 678 struct rx_bd *rxbd = 679 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 680 struct bnxt_sw_rx_agg_bd *rx_agg_buf; 681 struct pci_dev *pdev = bp->pdev; 682 struct page *page; 683 dma_addr_t mapping; 684 u16 sw_prod = rxr->rx_sw_agg_prod; 685 unsigned int offset = 0; 686 687 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) { 688 page = rxr->rx_page; 689 if (!page) { 690 page = alloc_page(gfp); 691 if (!page) 692 return -ENOMEM; 693 rxr->rx_page = page; 694 rxr->rx_page_offset = 0; 695 } 696 offset = rxr->rx_page_offset; 697 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE; 698 if (rxr->rx_page_offset == PAGE_SIZE) 699 rxr->rx_page = NULL; 700 else 701 get_page(page); 702 } else { 703 page = alloc_page(gfp); 704 if (!page) 705 return -ENOMEM; 706 } 707 708 mapping = dma_map_page(&pdev->dev, page, offset, BNXT_RX_PAGE_SIZE, 709 PCI_DMA_FROMDEVICE); 710 if (dma_mapping_error(&pdev->dev, mapping)) { 711 __free_page(page); 712 return -EIO; 713 } 714 715 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 716 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 717 718 __set_bit(sw_prod, rxr->rx_agg_bmap); 719 rx_agg_buf = &rxr->rx_agg_ring[sw_prod]; 720 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod); 721 722 rx_agg_buf->page = page; 723 rx_agg_buf->offset = offset; 724 rx_agg_buf->mapping = mapping; 725 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 726 rxbd->rx_bd_opaque = sw_prod; 727 return 0; 728 } 729 730 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons, 731 u32 agg_bufs) 732 { 733 struct bnxt *bp = bnapi->bp; 734 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 735 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 736 u16 prod = rxr->rx_agg_prod; 737 u16 sw_prod = rxr->rx_sw_agg_prod; 738 u32 i; 739 740 for (i = 0; i < agg_bufs; i++) { 741 u16 cons; 742 struct rx_agg_cmp *agg; 743 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf; 744 struct rx_bd *prod_bd; 745 struct page *page; 746 747 agg = (struct rx_agg_cmp *) 748 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 749 cons = agg->rx_agg_cmp_opaque; 750 __clear_bit(cons, rxr->rx_agg_bmap); 751 752 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 753 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 754 755 __set_bit(sw_prod, rxr->rx_agg_bmap); 756 prod_rx_buf = &rxr->rx_agg_ring[sw_prod]; 757 cons_rx_buf = &rxr->rx_agg_ring[cons]; 758 759 /* It is possible for sw_prod to be equal to cons, so 760 * set cons_rx_buf->page to NULL first. 761 */ 762 page = cons_rx_buf->page; 763 cons_rx_buf->page = NULL; 764 prod_rx_buf->page = page; 765 prod_rx_buf->offset = cons_rx_buf->offset; 766 767 prod_rx_buf->mapping = cons_rx_buf->mapping; 768 769 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 770 771 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping); 772 prod_bd->rx_bd_opaque = sw_prod; 773 774 prod = NEXT_RX_AGG(prod); 775 sw_prod = NEXT_RX_AGG(sw_prod); 776 cp_cons = NEXT_CMP(cp_cons); 777 } 778 rxr->rx_agg_prod = prod; 779 rxr->rx_sw_agg_prod = sw_prod; 780 } 781 782 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp, 783 struct bnxt_rx_ring_info *rxr, 784 u16 cons, void *data, u8 *data_ptr, 785 dma_addr_t dma_addr, 786 unsigned int offset_and_len) 787 { 788 unsigned int payload = offset_and_len >> 16; 789 unsigned int len = offset_and_len & 0xffff; 790 struct skb_frag_struct *frag; 791 struct page *page = data; 792 u16 prod = rxr->rx_prod; 793 struct sk_buff *skb; 794 int off, err; 795 796 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 797 if (unlikely(err)) { 798 bnxt_reuse_rx_data(rxr, cons, data); 799 return NULL; 800 } 801 dma_addr -= bp->rx_dma_offset; 802 dma_unmap_page(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir); 803 804 if (unlikely(!payload)) 805 payload = eth_get_headlen(data_ptr, len); 806 807 skb = napi_alloc_skb(&rxr->bnapi->napi, payload); 808 if (!skb) { 809 __free_page(page); 810 return NULL; 811 } 812 813 off = (void *)data_ptr - page_address(page); 814 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE); 815 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN, 816 payload + NET_IP_ALIGN); 817 818 frag = &skb_shinfo(skb)->frags[0]; 819 skb_frag_size_sub(frag, payload); 820 frag->page_offset += payload; 821 skb->data_len -= payload; 822 skb->tail += payload; 823 824 return skb; 825 } 826 827 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp, 828 struct bnxt_rx_ring_info *rxr, u16 cons, 829 void *data, u8 *data_ptr, 830 dma_addr_t dma_addr, 831 unsigned int offset_and_len) 832 { 833 u16 prod = rxr->rx_prod; 834 struct sk_buff *skb; 835 int err; 836 837 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 838 if (unlikely(err)) { 839 bnxt_reuse_rx_data(rxr, cons, data); 840 return NULL; 841 } 842 843 skb = build_skb(data, 0); 844 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, 845 bp->rx_dir); 846 if (!skb) { 847 kfree(data); 848 return NULL; 849 } 850 851 skb_reserve(skb, bp->rx_offset); 852 skb_put(skb, offset_and_len & 0xffff); 853 return skb; 854 } 855 856 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi, 857 struct sk_buff *skb, u16 cp_cons, 858 u32 agg_bufs) 859 { 860 struct pci_dev *pdev = bp->pdev; 861 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 862 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 863 u16 prod = rxr->rx_agg_prod; 864 u32 i; 865 866 for (i = 0; i < agg_bufs; i++) { 867 u16 cons, frag_len; 868 struct rx_agg_cmp *agg; 869 struct bnxt_sw_rx_agg_bd *cons_rx_buf; 870 struct page *page; 871 dma_addr_t mapping; 872 873 agg = (struct rx_agg_cmp *) 874 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 875 cons = agg->rx_agg_cmp_opaque; 876 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) & 877 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT; 878 879 cons_rx_buf = &rxr->rx_agg_ring[cons]; 880 skb_fill_page_desc(skb, i, cons_rx_buf->page, 881 cons_rx_buf->offset, frag_len); 882 __clear_bit(cons, rxr->rx_agg_bmap); 883 884 /* It is possible for bnxt_alloc_rx_page() to allocate 885 * a sw_prod index that equals the cons index, so we 886 * need to clear the cons entry now. 887 */ 888 mapping = cons_rx_buf->mapping; 889 page = cons_rx_buf->page; 890 cons_rx_buf->page = NULL; 891 892 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) { 893 struct skb_shared_info *shinfo; 894 unsigned int nr_frags; 895 896 shinfo = skb_shinfo(skb); 897 nr_frags = --shinfo->nr_frags; 898 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL); 899 900 dev_kfree_skb(skb); 901 902 cons_rx_buf->page = page; 903 904 /* Update prod since possibly some pages have been 905 * allocated already. 906 */ 907 rxr->rx_agg_prod = prod; 908 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i); 909 return NULL; 910 } 911 912 dma_unmap_page(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE, 913 PCI_DMA_FROMDEVICE); 914 915 skb->data_len += frag_len; 916 skb->len += frag_len; 917 skb->truesize += PAGE_SIZE; 918 919 prod = NEXT_RX_AGG(prod); 920 cp_cons = NEXT_CMP(cp_cons); 921 } 922 rxr->rx_agg_prod = prod; 923 return skb; 924 } 925 926 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 927 u8 agg_bufs, u32 *raw_cons) 928 { 929 u16 last; 930 struct rx_agg_cmp *agg; 931 932 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs); 933 last = RING_CMP(*raw_cons); 934 agg = (struct rx_agg_cmp *) 935 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)]; 936 return RX_AGG_CMP_VALID(agg, *raw_cons); 937 } 938 939 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data, 940 unsigned int len, 941 dma_addr_t mapping) 942 { 943 struct bnxt *bp = bnapi->bp; 944 struct pci_dev *pdev = bp->pdev; 945 struct sk_buff *skb; 946 947 skb = napi_alloc_skb(&bnapi->napi, len); 948 if (!skb) 949 return NULL; 950 951 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh, 952 bp->rx_dir); 953 954 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN, 955 len + NET_IP_ALIGN); 956 957 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh, 958 bp->rx_dir); 959 960 skb_put(skb, len); 961 return skb; 962 } 963 964 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi, 965 u32 *raw_cons, void *cmp) 966 { 967 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 968 struct rx_cmp *rxcmp = cmp; 969 u32 tmp_raw_cons = *raw_cons; 970 u8 cmp_type, agg_bufs = 0; 971 972 cmp_type = RX_CMP_TYPE(rxcmp); 973 974 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 975 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & 976 RX_CMP_AGG_BUFS) >> 977 RX_CMP_AGG_BUFS_SHIFT; 978 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 979 struct rx_tpa_end_cmp *tpa_end = cmp; 980 981 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & 982 RX_TPA_END_CMP_AGG_BUFS) >> 983 RX_TPA_END_CMP_AGG_BUFS_SHIFT; 984 } 985 986 if (agg_bufs) { 987 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 988 return -EBUSY; 989 } 990 *raw_cons = tmp_raw_cons; 991 return 0; 992 } 993 994 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) 995 { 996 if (!rxr->bnapi->in_reset) { 997 rxr->bnapi->in_reset = true; 998 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 999 schedule_work(&bp->sp_task); 1000 } 1001 rxr->rx_next_cons = 0xffff; 1002 } 1003 1004 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 1005 struct rx_tpa_start_cmp *tpa_start, 1006 struct rx_tpa_start_cmp_ext *tpa_start1) 1007 { 1008 u8 agg_id = TPA_START_AGG_ID(tpa_start); 1009 u16 cons, prod; 1010 struct bnxt_tpa_info *tpa_info; 1011 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 1012 struct rx_bd *prod_bd; 1013 dma_addr_t mapping; 1014 1015 cons = tpa_start->rx_tpa_start_cmp_opaque; 1016 prod = rxr->rx_prod; 1017 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1018 prod_rx_buf = &rxr->rx_buf_ring[prod]; 1019 tpa_info = &rxr->rx_tpa[agg_id]; 1020 1021 if (unlikely(cons != rxr->rx_next_cons)) { 1022 bnxt_sched_reset(bp, rxr); 1023 return; 1024 } 1025 1026 prod_rx_buf->data = tpa_info->data; 1027 prod_rx_buf->data_ptr = tpa_info->data_ptr; 1028 1029 mapping = tpa_info->mapping; 1030 prod_rx_buf->mapping = mapping; 1031 1032 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 1033 1034 prod_bd->rx_bd_haddr = cpu_to_le64(mapping); 1035 1036 tpa_info->data = cons_rx_buf->data; 1037 tpa_info->data_ptr = cons_rx_buf->data_ptr; 1038 cons_rx_buf->data = NULL; 1039 tpa_info->mapping = cons_rx_buf->mapping; 1040 1041 tpa_info->len = 1042 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >> 1043 RX_TPA_START_CMP_LEN_SHIFT; 1044 if (likely(TPA_START_HASH_VALID(tpa_start))) { 1045 u32 hash_type = TPA_START_HASH_TYPE(tpa_start); 1046 1047 tpa_info->hash_type = PKT_HASH_TYPE_L4; 1048 tpa_info->gso_type = SKB_GSO_TCPV4; 1049 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1050 if (hash_type == 3) 1051 tpa_info->gso_type = SKB_GSO_TCPV6; 1052 tpa_info->rss_hash = 1053 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash); 1054 } else { 1055 tpa_info->hash_type = PKT_HASH_TYPE_NONE; 1056 tpa_info->gso_type = 0; 1057 if (netif_msg_rx_err(bp)) 1058 netdev_warn(bp->dev, "TPA packet without valid hash\n"); 1059 } 1060 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2); 1061 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata); 1062 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info); 1063 1064 rxr->rx_prod = NEXT_RX(prod); 1065 cons = NEXT_RX(cons); 1066 rxr->rx_next_cons = NEXT_RX(cons); 1067 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1068 1069 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data); 1070 rxr->rx_prod = NEXT_RX(rxr->rx_prod); 1071 cons_rx_buf->data = NULL; 1072 } 1073 1074 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi, 1075 u16 cp_cons, u32 agg_bufs) 1076 { 1077 if (agg_bufs) 1078 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs); 1079 } 1080 1081 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info, 1082 int payload_off, int tcp_ts, 1083 struct sk_buff *skb) 1084 { 1085 #ifdef CONFIG_INET 1086 struct tcphdr *th; 1087 int len, nw_off; 1088 u16 outer_ip_off, inner_ip_off, inner_mac_off; 1089 u32 hdr_info = tpa_info->hdr_info; 1090 bool loopback = false; 1091 1092 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); 1093 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); 1094 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); 1095 1096 /* If the packet is an internal loopback packet, the offsets will 1097 * have an extra 4 bytes. 1098 */ 1099 if (inner_mac_off == 4) { 1100 loopback = true; 1101 } else if (inner_mac_off > 4) { 1102 __be16 proto = *((__be16 *)(skb->data + inner_ip_off - 1103 ETH_HLEN - 2)); 1104 1105 /* We only support inner iPv4/ipv6. If we don't see the 1106 * correct protocol ID, it must be a loopback packet where 1107 * the offsets are off by 4. 1108 */ 1109 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6)) 1110 loopback = true; 1111 } 1112 if (loopback) { 1113 /* internal loopback packet, subtract all offsets by 4 */ 1114 inner_ip_off -= 4; 1115 inner_mac_off -= 4; 1116 outer_ip_off -= 4; 1117 } 1118 1119 nw_off = inner_ip_off - ETH_HLEN; 1120 skb_set_network_header(skb, nw_off); 1121 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) { 1122 struct ipv6hdr *iph = ipv6_hdr(skb); 1123 1124 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1125 len = skb->len - skb_transport_offset(skb); 1126 th = tcp_hdr(skb); 1127 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1128 } else { 1129 struct iphdr *iph = ip_hdr(skb); 1130 1131 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1132 len = skb->len - skb_transport_offset(skb); 1133 th = tcp_hdr(skb); 1134 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1135 } 1136 1137 if (inner_mac_off) { /* tunnel */ 1138 struct udphdr *uh = NULL; 1139 __be16 proto = *((__be16 *)(skb->data + outer_ip_off - 1140 ETH_HLEN - 2)); 1141 1142 if (proto == htons(ETH_P_IP)) { 1143 struct iphdr *iph = (struct iphdr *)skb->data; 1144 1145 if (iph->protocol == IPPROTO_UDP) 1146 uh = (struct udphdr *)(iph + 1); 1147 } else { 1148 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; 1149 1150 if (iph->nexthdr == IPPROTO_UDP) 1151 uh = (struct udphdr *)(iph + 1); 1152 } 1153 if (uh) { 1154 if (uh->check) 1155 skb_shinfo(skb)->gso_type |= 1156 SKB_GSO_UDP_TUNNEL_CSUM; 1157 else 1158 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; 1159 } 1160 } 1161 #endif 1162 return skb; 1163 } 1164 1165 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr)) 1166 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr)) 1167 1168 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info, 1169 int payload_off, int tcp_ts, 1170 struct sk_buff *skb) 1171 { 1172 #ifdef CONFIG_INET 1173 struct tcphdr *th; 1174 int len, nw_off, tcp_opt_len = 0; 1175 1176 if (tcp_ts) 1177 tcp_opt_len = 12; 1178 1179 if (tpa_info->gso_type == SKB_GSO_TCPV4) { 1180 struct iphdr *iph; 1181 1182 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len - 1183 ETH_HLEN; 1184 skb_set_network_header(skb, nw_off); 1185 iph = ip_hdr(skb); 1186 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1187 len = skb->len - skb_transport_offset(skb); 1188 th = tcp_hdr(skb); 1189 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1190 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) { 1191 struct ipv6hdr *iph; 1192 1193 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len - 1194 ETH_HLEN; 1195 skb_set_network_header(skb, nw_off); 1196 iph = ipv6_hdr(skb); 1197 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1198 len = skb->len - skb_transport_offset(skb); 1199 th = tcp_hdr(skb); 1200 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1201 } else { 1202 dev_kfree_skb_any(skb); 1203 return NULL; 1204 } 1205 1206 if (nw_off) { /* tunnel */ 1207 struct udphdr *uh = NULL; 1208 1209 if (skb->protocol == htons(ETH_P_IP)) { 1210 struct iphdr *iph = (struct iphdr *)skb->data; 1211 1212 if (iph->protocol == IPPROTO_UDP) 1213 uh = (struct udphdr *)(iph + 1); 1214 } else { 1215 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; 1216 1217 if (iph->nexthdr == IPPROTO_UDP) 1218 uh = (struct udphdr *)(iph + 1); 1219 } 1220 if (uh) { 1221 if (uh->check) 1222 skb_shinfo(skb)->gso_type |= 1223 SKB_GSO_UDP_TUNNEL_CSUM; 1224 else 1225 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; 1226 } 1227 } 1228 #endif 1229 return skb; 1230 } 1231 1232 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp, 1233 struct bnxt_tpa_info *tpa_info, 1234 struct rx_tpa_end_cmp *tpa_end, 1235 struct rx_tpa_end_cmp_ext *tpa_end1, 1236 struct sk_buff *skb) 1237 { 1238 #ifdef CONFIG_INET 1239 int payload_off; 1240 u16 segs; 1241 1242 segs = TPA_END_TPA_SEGS(tpa_end); 1243 if (segs == 1) 1244 return skb; 1245 1246 NAPI_GRO_CB(skb)->count = segs; 1247 skb_shinfo(skb)->gso_size = 1248 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len); 1249 skb_shinfo(skb)->gso_type = tpa_info->gso_type; 1250 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & 1251 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> 1252 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT; 1253 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb); 1254 if (likely(skb)) 1255 tcp_gro_complete(skb); 1256 #endif 1257 return skb; 1258 } 1259 1260 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp, 1261 struct bnxt_napi *bnapi, 1262 u32 *raw_cons, 1263 struct rx_tpa_end_cmp *tpa_end, 1264 struct rx_tpa_end_cmp_ext *tpa_end1, 1265 u8 *event) 1266 { 1267 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1268 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1269 u8 agg_id = TPA_END_AGG_ID(tpa_end); 1270 u8 *data_ptr, agg_bufs; 1271 u16 cp_cons = RING_CMP(*raw_cons); 1272 unsigned int len; 1273 struct bnxt_tpa_info *tpa_info; 1274 dma_addr_t mapping; 1275 struct sk_buff *skb; 1276 void *data; 1277 1278 if (unlikely(bnapi->in_reset)) { 1279 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end); 1280 1281 if (rc < 0) 1282 return ERR_PTR(-EBUSY); 1283 return NULL; 1284 } 1285 1286 tpa_info = &rxr->rx_tpa[agg_id]; 1287 data = tpa_info->data; 1288 data_ptr = tpa_info->data_ptr; 1289 prefetch(data_ptr); 1290 len = tpa_info->len; 1291 mapping = tpa_info->mapping; 1292 1293 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & 1294 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT; 1295 1296 if (agg_bufs) { 1297 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons)) 1298 return ERR_PTR(-EBUSY); 1299 1300 *event |= BNXT_AGG_EVENT; 1301 cp_cons = NEXT_CMP(cp_cons); 1302 } 1303 1304 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) { 1305 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); 1306 if (agg_bufs > MAX_SKB_FRAGS) 1307 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n", 1308 agg_bufs, (int)MAX_SKB_FRAGS); 1309 return NULL; 1310 } 1311 1312 if (len <= bp->rx_copy_thresh) { 1313 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping); 1314 if (!skb) { 1315 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); 1316 return NULL; 1317 } 1318 } else { 1319 u8 *new_data; 1320 dma_addr_t new_mapping; 1321 1322 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC); 1323 if (!new_data) { 1324 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); 1325 return NULL; 1326 } 1327 1328 tpa_info->data = new_data; 1329 tpa_info->data_ptr = new_data + bp->rx_offset; 1330 tpa_info->mapping = new_mapping; 1331 1332 skb = build_skb(data, 0); 1333 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size, 1334 bp->rx_dir); 1335 1336 if (!skb) { 1337 kfree(data); 1338 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); 1339 return NULL; 1340 } 1341 skb_reserve(skb, bp->rx_offset); 1342 skb_put(skb, len); 1343 } 1344 1345 if (agg_bufs) { 1346 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs); 1347 if (!skb) { 1348 /* Page reuse already handled by bnxt_rx_pages(). */ 1349 return NULL; 1350 } 1351 } 1352 skb->protocol = eth_type_trans(skb, bp->dev); 1353 1354 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE) 1355 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type); 1356 1357 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) && 1358 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1359 u16 vlan_proto = tpa_info->metadata >> 1360 RX_CMP_FLAGS2_METADATA_TPID_SFT; 1361 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK; 1362 1363 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); 1364 } 1365 1366 skb_checksum_none_assert(skb); 1367 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) { 1368 skb->ip_summed = CHECKSUM_UNNECESSARY; 1369 skb->csum_level = 1370 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3; 1371 } 1372 1373 if (TPA_END_GRO(tpa_end)) 1374 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb); 1375 1376 return skb; 1377 } 1378 1379 /* returns the following: 1380 * 1 - 1 packet successfully received 1381 * 0 - successful TPA_START, packet not completed yet 1382 * -EBUSY - completion ring does not have all the agg buffers yet 1383 * -ENOMEM - packet aborted due to out of memory 1384 * -EIO - packet aborted due to hw error indicated in BD 1385 */ 1386 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons, 1387 u8 *event) 1388 { 1389 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1390 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1391 struct net_device *dev = bp->dev; 1392 struct rx_cmp *rxcmp; 1393 struct rx_cmp_ext *rxcmp1; 1394 u32 tmp_raw_cons = *raw_cons; 1395 u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons); 1396 struct bnxt_sw_rx_bd *rx_buf; 1397 unsigned int len; 1398 u8 *data_ptr, agg_bufs, cmp_type; 1399 dma_addr_t dma_addr; 1400 struct sk_buff *skb; 1401 void *data; 1402 int rc = 0; 1403 u32 misc; 1404 1405 rxcmp = (struct rx_cmp *) 1406 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1407 1408 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1409 cp_cons = RING_CMP(tmp_raw_cons); 1410 rxcmp1 = (struct rx_cmp_ext *) 1411 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1412 1413 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1414 return -EBUSY; 1415 1416 cmp_type = RX_CMP_TYPE(rxcmp); 1417 1418 prod = rxr->rx_prod; 1419 1420 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) { 1421 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp, 1422 (struct rx_tpa_start_cmp_ext *)rxcmp1); 1423 1424 *event |= BNXT_RX_EVENT; 1425 goto next_rx_no_prod; 1426 1427 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1428 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons, 1429 (struct rx_tpa_end_cmp *)rxcmp, 1430 (struct rx_tpa_end_cmp_ext *)rxcmp1, event); 1431 1432 if (unlikely(IS_ERR(skb))) 1433 return -EBUSY; 1434 1435 rc = -ENOMEM; 1436 if (likely(skb)) { 1437 skb_record_rx_queue(skb, bnapi->index); 1438 napi_gro_receive(&bnapi->napi, skb); 1439 rc = 1; 1440 } 1441 *event |= BNXT_RX_EVENT; 1442 goto next_rx_no_prod; 1443 } 1444 1445 cons = rxcmp->rx_cmp_opaque; 1446 rx_buf = &rxr->rx_buf_ring[cons]; 1447 data = rx_buf->data; 1448 data_ptr = rx_buf->data_ptr; 1449 if (unlikely(cons != rxr->rx_next_cons)) { 1450 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp); 1451 1452 bnxt_sched_reset(bp, rxr); 1453 return rc1; 1454 } 1455 prefetch(data_ptr); 1456 1457 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1); 1458 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT; 1459 1460 if (agg_bufs) { 1461 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1462 return -EBUSY; 1463 1464 cp_cons = NEXT_CMP(cp_cons); 1465 *event |= BNXT_AGG_EVENT; 1466 } 1467 *event |= BNXT_RX_EVENT; 1468 1469 rx_buf->data = NULL; 1470 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) { 1471 bnxt_reuse_rx_data(rxr, cons, data); 1472 if (agg_bufs) 1473 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs); 1474 1475 rc = -EIO; 1476 goto next_rx; 1477 } 1478 1479 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 1480 dma_addr = rx_buf->mapping; 1481 1482 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) { 1483 rc = 1; 1484 goto next_rx; 1485 } 1486 1487 if (len <= bp->rx_copy_thresh) { 1488 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr); 1489 bnxt_reuse_rx_data(rxr, cons, data); 1490 if (!skb) { 1491 rc = -ENOMEM; 1492 goto next_rx; 1493 } 1494 } else { 1495 u32 payload; 1496 1497 if (rx_buf->data_ptr == data_ptr) 1498 payload = misc & RX_CMP_PAYLOAD_OFFSET; 1499 else 1500 payload = 0; 1501 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr, 1502 payload | len); 1503 if (!skb) { 1504 rc = -ENOMEM; 1505 goto next_rx; 1506 } 1507 } 1508 1509 if (agg_bufs) { 1510 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs); 1511 if (!skb) { 1512 rc = -ENOMEM; 1513 goto next_rx; 1514 } 1515 } 1516 1517 if (RX_CMP_HASH_VALID(rxcmp)) { 1518 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp); 1519 enum pkt_hash_types type = PKT_HASH_TYPE_L4; 1520 1521 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1522 if (hash_type != 1 && hash_type != 3) 1523 type = PKT_HASH_TYPE_L3; 1524 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type); 1525 } 1526 1527 skb->protocol = eth_type_trans(skb, dev); 1528 1529 if ((rxcmp1->rx_cmp_flags2 & 1530 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) && 1531 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1532 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data); 1533 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK; 1534 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT; 1535 1536 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); 1537 } 1538 1539 skb_checksum_none_assert(skb); 1540 if (RX_CMP_L4_CS_OK(rxcmp1)) { 1541 if (dev->features & NETIF_F_RXCSUM) { 1542 skb->ip_summed = CHECKSUM_UNNECESSARY; 1543 skb->csum_level = RX_CMP_ENCAP(rxcmp1); 1544 } 1545 } else { 1546 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) { 1547 if (dev->features & NETIF_F_RXCSUM) 1548 cpr->rx_l4_csum_errors++; 1549 } 1550 } 1551 1552 skb_record_rx_queue(skb, bnapi->index); 1553 napi_gro_receive(&bnapi->napi, skb); 1554 rc = 1; 1555 1556 next_rx: 1557 rxr->rx_prod = NEXT_RX(prod); 1558 rxr->rx_next_cons = NEXT_RX(cons); 1559 1560 next_rx_no_prod: 1561 *raw_cons = tmp_raw_cons; 1562 1563 return rc; 1564 } 1565 1566 /* In netpoll mode, if we are using a combined completion ring, we need to 1567 * discard the rx packets and recycle the buffers. 1568 */ 1569 static int bnxt_force_rx_discard(struct bnxt *bp, struct bnxt_napi *bnapi, 1570 u32 *raw_cons, u8 *event) 1571 { 1572 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1573 u32 tmp_raw_cons = *raw_cons; 1574 struct rx_cmp_ext *rxcmp1; 1575 struct rx_cmp *rxcmp; 1576 u16 cp_cons; 1577 u8 cmp_type; 1578 1579 cp_cons = RING_CMP(tmp_raw_cons); 1580 rxcmp = (struct rx_cmp *) 1581 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1582 1583 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1584 cp_cons = RING_CMP(tmp_raw_cons); 1585 rxcmp1 = (struct rx_cmp_ext *) 1586 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1587 1588 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1589 return -EBUSY; 1590 1591 cmp_type = RX_CMP_TYPE(rxcmp); 1592 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 1593 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 1594 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 1595 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1596 struct rx_tpa_end_cmp_ext *tpa_end1; 1597 1598 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1; 1599 tpa_end1->rx_tpa_end_cmp_errors_v2 |= 1600 cpu_to_le32(RX_TPA_END_CMP_ERRORS); 1601 } 1602 return bnxt_rx_pkt(bp, bnapi, raw_cons, event); 1603 } 1604 1605 #define BNXT_GET_EVENT_PORT(data) \ 1606 ((data) & \ 1607 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK) 1608 1609 static int bnxt_async_event_process(struct bnxt *bp, 1610 struct hwrm_async_event_cmpl *cmpl) 1611 { 1612 u16 event_id = le16_to_cpu(cmpl->event_id); 1613 1614 /* TODO CHIMP_FW: Define event id's for link change, error etc */ 1615 switch (event_id) { 1616 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: { 1617 u32 data1 = le32_to_cpu(cmpl->event_data1); 1618 struct bnxt_link_info *link_info = &bp->link_info; 1619 1620 if (BNXT_VF(bp)) 1621 goto async_event_process_exit; 1622 if (data1 & 0x20000) { 1623 u16 fw_speed = link_info->force_link_speed; 1624 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed); 1625 1626 netdev_warn(bp->dev, "Link speed %d no longer supported\n", 1627 speed); 1628 } 1629 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event); 1630 /* fall thru */ 1631 } 1632 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE: 1633 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event); 1634 break; 1635 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD: 1636 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event); 1637 break; 1638 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: { 1639 u32 data1 = le32_to_cpu(cmpl->event_data1); 1640 u16 port_id = BNXT_GET_EVENT_PORT(data1); 1641 1642 if (BNXT_VF(bp)) 1643 break; 1644 1645 if (bp->pf.port_id != port_id) 1646 break; 1647 1648 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event); 1649 break; 1650 } 1651 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE: 1652 if (BNXT_PF(bp)) 1653 goto async_event_process_exit; 1654 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event); 1655 break; 1656 default: 1657 goto async_event_process_exit; 1658 } 1659 schedule_work(&bp->sp_task); 1660 async_event_process_exit: 1661 bnxt_ulp_async_events(bp, cmpl); 1662 return 0; 1663 } 1664 1665 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp) 1666 { 1667 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id; 1668 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp; 1669 struct hwrm_fwd_req_cmpl *fwd_req_cmpl = 1670 (struct hwrm_fwd_req_cmpl *)txcmp; 1671 1672 switch (cmpl_type) { 1673 case CMPL_BASE_TYPE_HWRM_DONE: 1674 seq_id = le16_to_cpu(h_cmpl->sequence_id); 1675 if (seq_id == bp->hwrm_intr_seq_id) 1676 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID; 1677 else 1678 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id); 1679 break; 1680 1681 case CMPL_BASE_TYPE_HWRM_FWD_REQ: 1682 vf_id = le16_to_cpu(fwd_req_cmpl->source_id); 1683 1684 if ((vf_id < bp->pf.first_vf_id) || 1685 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) { 1686 netdev_err(bp->dev, "Msg contains invalid VF id %x\n", 1687 vf_id); 1688 return -EINVAL; 1689 } 1690 1691 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap); 1692 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event); 1693 schedule_work(&bp->sp_task); 1694 break; 1695 1696 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: 1697 bnxt_async_event_process(bp, 1698 (struct hwrm_async_event_cmpl *)txcmp); 1699 1700 default: 1701 break; 1702 } 1703 1704 return 0; 1705 } 1706 1707 static irqreturn_t bnxt_msix(int irq, void *dev_instance) 1708 { 1709 struct bnxt_napi *bnapi = dev_instance; 1710 struct bnxt *bp = bnapi->bp; 1711 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1712 u32 cons = RING_CMP(cpr->cp_raw_cons); 1713 1714 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 1715 napi_schedule(&bnapi->napi); 1716 return IRQ_HANDLED; 1717 } 1718 1719 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) 1720 { 1721 u32 raw_cons = cpr->cp_raw_cons; 1722 u16 cons = RING_CMP(raw_cons); 1723 struct tx_cmp *txcmp; 1724 1725 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 1726 1727 return TX_CMP_VALID(txcmp, raw_cons); 1728 } 1729 1730 static irqreturn_t bnxt_inta(int irq, void *dev_instance) 1731 { 1732 struct bnxt_napi *bnapi = dev_instance; 1733 struct bnxt *bp = bnapi->bp; 1734 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1735 u32 cons = RING_CMP(cpr->cp_raw_cons); 1736 u32 int_status; 1737 1738 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 1739 1740 if (!bnxt_has_work(bp, cpr)) { 1741 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS); 1742 /* return if erroneous interrupt */ 1743 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id))) 1744 return IRQ_NONE; 1745 } 1746 1747 /* disable ring IRQ */ 1748 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell); 1749 1750 /* Return here if interrupt is shared and is disabled. */ 1751 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 1752 return IRQ_HANDLED; 1753 1754 napi_schedule(&bnapi->napi); 1755 return IRQ_HANDLED; 1756 } 1757 1758 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget) 1759 { 1760 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1761 u32 raw_cons = cpr->cp_raw_cons; 1762 u32 cons; 1763 int tx_pkts = 0; 1764 int rx_pkts = 0; 1765 u8 event = 0; 1766 struct tx_cmp *txcmp; 1767 1768 while (1) { 1769 int rc; 1770 1771 cons = RING_CMP(raw_cons); 1772 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 1773 1774 if (!TX_CMP_VALID(txcmp, raw_cons)) 1775 break; 1776 1777 /* The valid test of the entry must be done first before 1778 * reading any further. 1779 */ 1780 dma_rmb(); 1781 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) { 1782 tx_pkts++; 1783 /* return full budget so NAPI will complete. */ 1784 if (unlikely(tx_pkts > bp->tx_wake_thresh)) 1785 rx_pkts = budget; 1786 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 1787 if (likely(budget)) 1788 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event); 1789 else 1790 rc = bnxt_force_rx_discard(bp, bnapi, &raw_cons, 1791 &event); 1792 if (likely(rc >= 0)) 1793 rx_pkts += rc; 1794 else if (rc == -EBUSY) /* partial completion */ 1795 break; 1796 } else if (unlikely((TX_CMP_TYPE(txcmp) == 1797 CMPL_BASE_TYPE_HWRM_DONE) || 1798 (TX_CMP_TYPE(txcmp) == 1799 CMPL_BASE_TYPE_HWRM_FWD_REQ) || 1800 (TX_CMP_TYPE(txcmp) == 1801 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) { 1802 bnxt_hwrm_handler(bp, txcmp); 1803 } 1804 raw_cons = NEXT_RAW_CMP(raw_cons); 1805 1806 if (rx_pkts == budget) 1807 break; 1808 } 1809 1810 if (event & BNXT_TX_EVENT) { 1811 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 1812 void __iomem *db = txr->tx_doorbell; 1813 u16 prod = txr->tx_prod; 1814 1815 /* Sync BD data before updating doorbell */ 1816 wmb(); 1817 1818 writel(DB_KEY_TX | prod, db); 1819 writel(DB_KEY_TX | prod, db); 1820 } 1821 1822 cpr->cp_raw_cons = raw_cons; 1823 /* ACK completion ring before freeing tx ring and producing new 1824 * buffers in rx/agg rings to prevent overflowing the completion 1825 * ring. 1826 */ 1827 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); 1828 1829 if (tx_pkts) 1830 bnapi->tx_int(bp, bnapi, tx_pkts); 1831 1832 if (event & BNXT_RX_EVENT) { 1833 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1834 1835 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell); 1836 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell); 1837 if (event & BNXT_AGG_EVENT) { 1838 writel(DB_KEY_RX | rxr->rx_agg_prod, 1839 rxr->rx_agg_doorbell); 1840 writel(DB_KEY_RX | rxr->rx_agg_prod, 1841 rxr->rx_agg_doorbell); 1842 } 1843 } 1844 return rx_pkts; 1845 } 1846 1847 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget) 1848 { 1849 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 1850 struct bnxt *bp = bnapi->bp; 1851 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1852 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1853 struct tx_cmp *txcmp; 1854 struct rx_cmp_ext *rxcmp1; 1855 u32 cp_cons, tmp_raw_cons; 1856 u32 raw_cons = cpr->cp_raw_cons; 1857 u32 rx_pkts = 0; 1858 u8 event = 0; 1859 1860 while (1) { 1861 int rc; 1862 1863 cp_cons = RING_CMP(raw_cons); 1864 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1865 1866 if (!TX_CMP_VALID(txcmp, raw_cons)) 1867 break; 1868 1869 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 1870 tmp_raw_cons = NEXT_RAW_CMP(raw_cons); 1871 cp_cons = RING_CMP(tmp_raw_cons); 1872 rxcmp1 = (struct rx_cmp_ext *) 1873 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1874 1875 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1876 break; 1877 1878 /* force an error to recycle the buffer */ 1879 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 1880 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 1881 1882 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event); 1883 if (likely(rc == -EIO)) 1884 rx_pkts++; 1885 else if (rc == -EBUSY) /* partial completion */ 1886 break; 1887 } else if (unlikely(TX_CMP_TYPE(txcmp) == 1888 CMPL_BASE_TYPE_HWRM_DONE)) { 1889 bnxt_hwrm_handler(bp, txcmp); 1890 } else { 1891 netdev_err(bp->dev, 1892 "Invalid completion received on special ring\n"); 1893 } 1894 raw_cons = NEXT_RAW_CMP(raw_cons); 1895 1896 if (rx_pkts == budget) 1897 break; 1898 } 1899 1900 cpr->cp_raw_cons = raw_cons; 1901 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); 1902 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell); 1903 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell); 1904 1905 if (event & BNXT_AGG_EVENT) { 1906 writel(DB_KEY_RX | rxr->rx_agg_prod, rxr->rx_agg_doorbell); 1907 writel(DB_KEY_RX | rxr->rx_agg_prod, rxr->rx_agg_doorbell); 1908 } 1909 1910 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) { 1911 napi_complete_done(napi, rx_pkts); 1912 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons); 1913 } 1914 return rx_pkts; 1915 } 1916 1917 static int bnxt_poll(struct napi_struct *napi, int budget) 1918 { 1919 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 1920 struct bnxt *bp = bnapi->bp; 1921 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1922 int work_done = 0; 1923 1924 while (1) { 1925 work_done += bnxt_poll_work(bp, bnapi, budget - work_done); 1926 1927 if (work_done >= budget) 1928 break; 1929 1930 if (!bnxt_has_work(bp, cpr)) { 1931 if (napi_complete_done(napi, work_done)) 1932 BNXT_CP_DB_REARM(cpr->cp_doorbell, 1933 cpr->cp_raw_cons); 1934 break; 1935 } 1936 } 1937 mmiowb(); 1938 return work_done; 1939 } 1940 1941 static void bnxt_free_tx_skbs(struct bnxt *bp) 1942 { 1943 int i, max_idx; 1944 struct pci_dev *pdev = bp->pdev; 1945 1946 if (!bp->tx_ring) 1947 return; 1948 1949 max_idx = bp->tx_nr_pages * TX_DESC_CNT; 1950 for (i = 0; i < bp->tx_nr_rings; i++) { 1951 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 1952 int j; 1953 1954 for (j = 0; j < max_idx;) { 1955 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; 1956 struct sk_buff *skb = tx_buf->skb; 1957 int k, last; 1958 1959 if (!skb) { 1960 j++; 1961 continue; 1962 } 1963 1964 tx_buf->skb = NULL; 1965 1966 if (tx_buf->is_push) { 1967 dev_kfree_skb(skb); 1968 j += 2; 1969 continue; 1970 } 1971 1972 dma_unmap_single(&pdev->dev, 1973 dma_unmap_addr(tx_buf, mapping), 1974 skb_headlen(skb), 1975 PCI_DMA_TODEVICE); 1976 1977 last = tx_buf->nr_frags; 1978 j += 2; 1979 for (k = 0; k < last; k++, j++) { 1980 int ring_idx = j & bp->tx_ring_mask; 1981 skb_frag_t *frag = &skb_shinfo(skb)->frags[k]; 1982 1983 tx_buf = &txr->tx_buf_ring[ring_idx]; 1984 dma_unmap_page( 1985 &pdev->dev, 1986 dma_unmap_addr(tx_buf, mapping), 1987 skb_frag_size(frag), PCI_DMA_TODEVICE); 1988 } 1989 dev_kfree_skb(skb); 1990 } 1991 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); 1992 } 1993 } 1994 1995 static void bnxt_free_rx_skbs(struct bnxt *bp) 1996 { 1997 int i, max_idx, max_agg_idx; 1998 struct pci_dev *pdev = bp->pdev; 1999 2000 if (!bp->rx_ring) 2001 return; 2002 2003 max_idx = bp->rx_nr_pages * RX_DESC_CNT; 2004 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT; 2005 for (i = 0; i < bp->rx_nr_rings; i++) { 2006 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2007 int j; 2008 2009 if (rxr->rx_tpa) { 2010 for (j = 0; j < MAX_TPA; j++) { 2011 struct bnxt_tpa_info *tpa_info = 2012 &rxr->rx_tpa[j]; 2013 u8 *data = tpa_info->data; 2014 2015 if (!data) 2016 continue; 2017 2018 dma_unmap_single(&pdev->dev, tpa_info->mapping, 2019 bp->rx_buf_use_size, 2020 bp->rx_dir); 2021 2022 tpa_info->data = NULL; 2023 2024 kfree(data); 2025 } 2026 } 2027 2028 for (j = 0; j < max_idx; j++) { 2029 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j]; 2030 dma_addr_t mapping = rx_buf->mapping; 2031 void *data = rx_buf->data; 2032 2033 if (!data) 2034 continue; 2035 2036 rx_buf->data = NULL; 2037 2038 if (BNXT_RX_PAGE_MODE(bp)) { 2039 mapping -= bp->rx_dma_offset; 2040 dma_unmap_page(&pdev->dev, mapping, 2041 PAGE_SIZE, bp->rx_dir); 2042 __free_page(data); 2043 } else { 2044 dma_unmap_single(&pdev->dev, mapping, 2045 bp->rx_buf_use_size, 2046 bp->rx_dir); 2047 kfree(data); 2048 } 2049 } 2050 2051 for (j = 0; j < max_agg_idx; j++) { 2052 struct bnxt_sw_rx_agg_bd *rx_agg_buf = 2053 &rxr->rx_agg_ring[j]; 2054 struct page *page = rx_agg_buf->page; 2055 2056 if (!page) 2057 continue; 2058 2059 dma_unmap_page(&pdev->dev, rx_agg_buf->mapping, 2060 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE); 2061 2062 rx_agg_buf->page = NULL; 2063 __clear_bit(j, rxr->rx_agg_bmap); 2064 2065 __free_page(page); 2066 } 2067 if (rxr->rx_page) { 2068 __free_page(rxr->rx_page); 2069 rxr->rx_page = NULL; 2070 } 2071 } 2072 } 2073 2074 static void bnxt_free_skbs(struct bnxt *bp) 2075 { 2076 bnxt_free_tx_skbs(bp); 2077 bnxt_free_rx_skbs(bp); 2078 } 2079 2080 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring) 2081 { 2082 struct pci_dev *pdev = bp->pdev; 2083 int i; 2084 2085 for (i = 0; i < ring->nr_pages; i++) { 2086 if (!ring->pg_arr[i]) 2087 continue; 2088 2089 dma_free_coherent(&pdev->dev, ring->page_size, 2090 ring->pg_arr[i], ring->dma_arr[i]); 2091 2092 ring->pg_arr[i] = NULL; 2093 } 2094 if (ring->pg_tbl) { 2095 dma_free_coherent(&pdev->dev, ring->nr_pages * 8, 2096 ring->pg_tbl, ring->pg_tbl_map); 2097 ring->pg_tbl = NULL; 2098 } 2099 if (ring->vmem_size && *ring->vmem) { 2100 vfree(*ring->vmem); 2101 *ring->vmem = NULL; 2102 } 2103 } 2104 2105 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring) 2106 { 2107 int i; 2108 struct pci_dev *pdev = bp->pdev; 2109 2110 if (ring->nr_pages > 1) { 2111 ring->pg_tbl = dma_alloc_coherent(&pdev->dev, 2112 ring->nr_pages * 8, 2113 &ring->pg_tbl_map, 2114 GFP_KERNEL); 2115 if (!ring->pg_tbl) 2116 return -ENOMEM; 2117 } 2118 2119 for (i = 0; i < ring->nr_pages; i++) { 2120 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev, 2121 ring->page_size, 2122 &ring->dma_arr[i], 2123 GFP_KERNEL); 2124 if (!ring->pg_arr[i]) 2125 return -ENOMEM; 2126 2127 if (ring->nr_pages > 1) 2128 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]); 2129 } 2130 2131 if (ring->vmem_size) { 2132 *ring->vmem = vzalloc(ring->vmem_size); 2133 if (!(*ring->vmem)) 2134 return -ENOMEM; 2135 } 2136 return 0; 2137 } 2138 2139 static void bnxt_free_rx_rings(struct bnxt *bp) 2140 { 2141 int i; 2142 2143 if (!bp->rx_ring) 2144 return; 2145 2146 for (i = 0; i < bp->rx_nr_rings; i++) { 2147 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2148 struct bnxt_ring_struct *ring; 2149 2150 if (rxr->xdp_prog) 2151 bpf_prog_put(rxr->xdp_prog); 2152 2153 kfree(rxr->rx_tpa); 2154 rxr->rx_tpa = NULL; 2155 2156 kfree(rxr->rx_agg_bmap); 2157 rxr->rx_agg_bmap = NULL; 2158 2159 ring = &rxr->rx_ring_struct; 2160 bnxt_free_ring(bp, ring); 2161 2162 ring = &rxr->rx_agg_ring_struct; 2163 bnxt_free_ring(bp, ring); 2164 } 2165 } 2166 2167 static int bnxt_alloc_rx_rings(struct bnxt *bp) 2168 { 2169 int i, rc, agg_rings = 0, tpa_rings = 0; 2170 2171 if (!bp->rx_ring) 2172 return -ENOMEM; 2173 2174 if (bp->flags & BNXT_FLAG_AGG_RINGS) 2175 agg_rings = 1; 2176 2177 if (bp->flags & BNXT_FLAG_TPA) 2178 tpa_rings = 1; 2179 2180 for (i = 0; i < bp->rx_nr_rings; i++) { 2181 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2182 struct bnxt_ring_struct *ring; 2183 2184 ring = &rxr->rx_ring_struct; 2185 2186 rc = bnxt_alloc_ring(bp, ring); 2187 if (rc) 2188 return rc; 2189 2190 if (agg_rings) { 2191 u16 mem_size; 2192 2193 ring = &rxr->rx_agg_ring_struct; 2194 rc = bnxt_alloc_ring(bp, ring); 2195 if (rc) 2196 return rc; 2197 2198 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1; 2199 mem_size = rxr->rx_agg_bmap_size / 8; 2200 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL); 2201 if (!rxr->rx_agg_bmap) 2202 return -ENOMEM; 2203 2204 if (tpa_rings) { 2205 rxr->rx_tpa = kcalloc(MAX_TPA, 2206 sizeof(struct bnxt_tpa_info), 2207 GFP_KERNEL); 2208 if (!rxr->rx_tpa) 2209 return -ENOMEM; 2210 } 2211 } 2212 } 2213 return 0; 2214 } 2215 2216 static void bnxt_free_tx_rings(struct bnxt *bp) 2217 { 2218 int i; 2219 struct pci_dev *pdev = bp->pdev; 2220 2221 if (!bp->tx_ring) 2222 return; 2223 2224 for (i = 0; i < bp->tx_nr_rings; i++) { 2225 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2226 struct bnxt_ring_struct *ring; 2227 2228 if (txr->tx_push) { 2229 dma_free_coherent(&pdev->dev, bp->tx_push_size, 2230 txr->tx_push, txr->tx_push_mapping); 2231 txr->tx_push = NULL; 2232 } 2233 2234 ring = &txr->tx_ring_struct; 2235 2236 bnxt_free_ring(bp, ring); 2237 } 2238 } 2239 2240 static int bnxt_alloc_tx_rings(struct bnxt *bp) 2241 { 2242 int i, j, rc; 2243 struct pci_dev *pdev = bp->pdev; 2244 2245 bp->tx_push_size = 0; 2246 if (bp->tx_push_thresh) { 2247 int push_size; 2248 2249 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) + 2250 bp->tx_push_thresh); 2251 2252 if (push_size > 256) { 2253 push_size = 0; 2254 bp->tx_push_thresh = 0; 2255 } 2256 2257 bp->tx_push_size = push_size; 2258 } 2259 2260 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) { 2261 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2262 struct bnxt_ring_struct *ring; 2263 2264 ring = &txr->tx_ring_struct; 2265 2266 rc = bnxt_alloc_ring(bp, ring); 2267 if (rc) 2268 return rc; 2269 2270 if (bp->tx_push_size) { 2271 dma_addr_t mapping; 2272 2273 /* One pre-allocated DMA buffer to backup 2274 * TX push operation 2275 */ 2276 txr->tx_push = dma_alloc_coherent(&pdev->dev, 2277 bp->tx_push_size, 2278 &txr->tx_push_mapping, 2279 GFP_KERNEL); 2280 2281 if (!txr->tx_push) 2282 return -ENOMEM; 2283 2284 mapping = txr->tx_push_mapping + 2285 sizeof(struct tx_push_bd); 2286 txr->data_mapping = cpu_to_le64(mapping); 2287 2288 memset(txr->tx_push, 0, sizeof(struct tx_push_bd)); 2289 } 2290 ring->queue_id = bp->q_info[j].queue_id; 2291 if (i < bp->tx_nr_rings_xdp) 2292 continue; 2293 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1)) 2294 j++; 2295 } 2296 return 0; 2297 } 2298 2299 static void bnxt_free_cp_rings(struct bnxt *bp) 2300 { 2301 int i; 2302 2303 if (!bp->bnapi) 2304 return; 2305 2306 for (i = 0; i < bp->cp_nr_rings; i++) { 2307 struct bnxt_napi *bnapi = bp->bnapi[i]; 2308 struct bnxt_cp_ring_info *cpr; 2309 struct bnxt_ring_struct *ring; 2310 2311 if (!bnapi) 2312 continue; 2313 2314 cpr = &bnapi->cp_ring; 2315 ring = &cpr->cp_ring_struct; 2316 2317 bnxt_free_ring(bp, ring); 2318 } 2319 } 2320 2321 static int bnxt_alloc_cp_rings(struct bnxt *bp) 2322 { 2323 int i, rc; 2324 2325 for (i = 0; i < bp->cp_nr_rings; i++) { 2326 struct bnxt_napi *bnapi = bp->bnapi[i]; 2327 struct bnxt_cp_ring_info *cpr; 2328 struct bnxt_ring_struct *ring; 2329 2330 if (!bnapi) 2331 continue; 2332 2333 cpr = &bnapi->cp_ring; 2334 ring = &cpr->cp_ring_struct; 2335 2336 rc = bnxt_alloc_ring(bp, ring); 2337 if (rc) 2338 return rc; 2339 } 2340 return 0; 2341 } 2342 2343 static void bnxt_init_ring_struct(struct bnxt *bp) 2344 { 2345 int i; 2346 2347 for (i = 0; i < bp->cp_nr_rings; i++) { 2348 struct bnxt_napi *bnapi = bp->bnapi[i]; 2349 struct bnxt_cp_ring_info *cpr; 2350 struct bnxt_rx_ring_info *rxr; 2351 struct bnxt_tx_ring_info *txr; 2352 struct bnxt_ring_struct *ring; 2353 2354 if (!bnapi) 2355 continue; 2356 2357 cpr = &bnapi->cp_ring; 2358 ring = &cpr->cp_ring_struct; 2359 ring->nr_pages = bp->cp_nr_pages; 2360 ring->page_size = HW_CMPD_RING_SIZE; 2361 ring->pg_arr = (void **)cpr->cp_desc_ring; 2362 ring->dma_arr = cpr->cp_desc_mapping; 2363 ring->vmem_size = 0; 2364 2365 rxr = bnapi->rx_ring; 2366 if (!rxr) 2367 goto skip_rx; 2368 2369 ring = &rxr->rx_ring_struct; 2370 ring->nr_pages = bp->rx_nr_pages; 2371 ring->page_size = HW_RXBD_RING_SIZE; 2372 ring->pg_arr = (void **)rxr->rx_desc_ring; 2373 ring->dma_arr = rxr->rx_desc_mapping; 2374 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages; 2375 ring->vmem = (void **)&rxr->rx_buf_ring; 2376 2377 ring = &rxr->rx_agg_ring_struct; 2378 ring->nr_pages = bp->rx_agg_nr_pages; 2379 ring->page_size = HW_RXBD_RING_SIZE; 2380 ring->pg_arr = (void **)rxr->rx_agg_desc_ring; 2381 ring->dma_arr = rxr->rx_agg_desc_mapping; 2382 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages; 2383 ring->vmem = (void **)&rxr->rx_agg_ring; 2384 2385 skip_rx: 2386 txr = bnapi->tx_ring; 2387 if (!txr) 2388 continue; 2389 2390 ring = &txr->tx_ring_struct; 2391 ring->nr_pages = bp->tx_nr_pages; 2392 ring->page_size = HW_RXBD_RING_SIZE; 2393 ring->pg_arr = (void **)txr->tx_desc_ring; 2394 ring->dma_arr = txr->tx_desc_mapping; 2395 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages; 2396 ring->vmem = (void **)&txr->tx_buf_ring; 2397 } 2398 } 2399 2400 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type) 2401 { 2402 int i; 2403 u32 prod; 2404 struct rx_bd **rx_buf_ring; 2405 2406 rx_buf_ring = (struct rx_bd **)ring->pg_arr; 2407 for (i = 0, prod = 0; i < ring->nr_pages; i++) { 2408 int j; 2409 struct rx_bd *rxbd; 2410 2411 rxbd = rx_buf_ring[i]; 2412 if (!rxbd) 2413 continue; 2414 2415 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) { 2416 rxbd->rx_bd_len_flags_type = cpu_to_le32(type); 2417 rxbd->rx_bd_opaque = prod; 2418 } 2419 } 2420 } 2421 2422 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr) 2423 { 2424 struct net_device *dev = bp->dev; 2425 struct bnxt_rx_ring_info *rxr; 2426 struct bnxt_ring_struct *ring; 2427 u32 prod, type; 2428 int i; 2429 2430 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) | 2431 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP; 2432 2433 if (NET_IP_ALIGN == 2) 2434 type |= RX_BD_FLAGS_SOP; 2435 2436 rxr = &bp->rx_ring[ring_nr]; 2437 ring = &rxr->rx_ring_struct; 2438 bnxt_init_rxbd_pages(ring, type); 2439 2440 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) { 2441 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1); 2442 if (IS_ERR(rxr->xdp_prog)) { 2443 int rc = PTR_ERR(rxr->xdp_prog); 2444 2445 rxr->xdp_prog = NULL; 2446 return rc; 2447 } 2448 } 2449 prod = rxr->rx_prod; 2450 for (i = 0; i < bp->rx_ring_size; i++) { 2451 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) { 2452 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n", 2453 ring_nr, i, bp->rx_ring_size); 2454 break; 2455 } 2456 prod = NEXT_RX(prod); 2457 } 2458 rxr->rx_prod = prod; 2459 ring->fw_ring_id = INVALID_HW_RING_ID; 2460 2461 ring = &rxr->rx_agg_ring_struct; 2462 ring->fw_ring_id = INVALID_HW_RING_ID; 2463 2464 if (!(bp->flags & BNXT_FLAG_AGG_RINGS)) 2465 return 0; 2466 2467 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) | 2468 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP; 2469 2470 bnxt_init_rxbd_pages(ring, type); 2471 2472 prod = rxr->rx_agg_prod; 2473 for (i = 0; i < bp->rx_agg_ring_size; i++) { 2474 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) { 2475 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n", 2476 ring_nr, i, bp->rx_ring_size); 2477 break; 2478 } 2479 prod = NEXT_RX_AGG(prod); 2480 } 2481 rxr->rx_agg_prod = prod; 2482 2483 if (bp->flags & BNXT_FLAG_TPA) { 2484 if (rxr->rx_tpa) { 2485 u8 *data; 2486 dma_addr_t mapping; 2487 2488 for (i = 0; i < MAX_TPA; i++) { 2489 data = __bnxt_alloc_rx_data(bp, &mapping, 2490 GFP_KERNEL); 2491 if (!data) 2492 return -ENOMEM; 2493 2494 rxr->rx_tpa[i].data = data; 2495 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset; 2496 rxr->rx_tpa[i].mapping = mapping; 2497 } 2498 } else { 2499 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n"); 2500 return -ENOMEM; 2501 } 2502 } 2503 2504 return 0; 2505 } 2506 2507 static void bnxt_init_cp_rings(struct bnxt *bp) 2508 { 2509 int i; 2510 2511 for (i = 0; i < bp->cp_nr_rings; i++) { 2512 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 2513 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 2514 2515 ring->fw_ring_id = INVALID_HW_RING_ID; 2516 } 2517 } 2518 2519 static int bnxt_init_rx_rings(struct bnxt *bp) 2520 { 2521 int i, rc = 0; 2522 2523 if (BNXT_RX_PAGE_MODE(bp)) { 2524 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM; 2525 bp->rx_dma_offset = XDP_PACKET_HEADROOM; 2526 } else { 2527 bp->rx_offset = BNXT_RX_OFFSET; 2528 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET; 2529 } 2530 2531 for (i = 0; i < bp->rx_nr_rings; i++) { 2532 rc = bnxt_init_one_rx_ring(bp, i); 2533 if (rc) 2534 break; 2535 } 2536 2537 return rc; 2538 } 2539 2540 static int bnxt_init_tx_rings(struct bnxt *bp) 2541 { 2542 u16 i; 2543 2544 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2, 2545 MAX_SKB_FRAGS + 1); 2546 2547 for (i = 0; i < bp->tx_nr_rings; i++) { 2548 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2549 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 2550 2551 ring->fw_ring_id = INVALID_HW_RING_ID; 2552 } 2553 2554 return 0; 2555 } 2556 2557 static void bnxt_free_ring_grps(struct bnxt *bp) 2558 { 2559 kfree(bp->grp_info); 2560 bp->grp_info = NULL; 2561 } 2562 2563 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init) 2564 { 2565 int i; 2566 2567 if (irq_re_init) { 2568 bp->grp_info = kcalloc(bp->cp_nr_rings, 2569 sizeof(struct bnxt_ring_grp_info), 2570 GFP_KERNEL); 2571 if (!bp->grp_info) 2572 return -ENOMEM; 2573 } 2574 for (i = 0; i < bp->cp_nr_rings; i++) { 2575 if (irq_re_init) 2576 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID; 2577 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 2578 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID; 2579 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID; 2580 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 2581 } 2582 return 0; 2583 } 2584 2585 static void bnxt_free_vnics(struct bnxt *bp) 2586 { 2587 kfree(bp->vnic_info); 2588 bp->vnic_info = NULL; 2589 bp->nr_vnics = 0; 2590 } 2591 2592 static int bnxt_alloc_vnics(struct bnxt *bp) 2593 { 2594 int num_vnics = 1; 2595 2596 #ifdef CONFIG_RFS_ACCEL 2597 if (bp->flags & BNXT_FLAG_RFS) 2598 num_vnics += bp->rx_nr_rings; 2599 #endif 2600 2601 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 2602 num_vnics++; 2603 2604 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info), 2605 GFP_KERNEL); 2606 if (!bp->vnic_info) 2607 return -ENOMEM; 2608 2609 bp->nr_vnics = num_vnics; 2610 return 0; 2611 } 2612 2613 static void bnxt_init_vnics(struct bnxt *bp) 2614 { 2615 int i; 2616 2617 for (i = 0; i < bp->nr_vnics; i++) { 2618 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2619 2620 vnic->fw_vnic_id = INVALID_HW_RING_ID; 2621 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID; 2622 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID; 2623 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID; 2624 2625 if (bp->vnic_info[i].rss_hash_key) { 2626 if (i == 0) 2627 prandom_bytes(vnic->rss_hash_key, 2628 HW_HASH_KEY_SIZE); 2629 else 2630 memcpy(vnic->rss_hash_key, 2631 bp->vnic_info[0].rss_hash_key, 2632 HW_HASH_KEY_SIZE); 2633 } 2634 } 2635 } 2636 2637 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg) 2638 { 2639 int pages; 2640 2641 pages = ring_size / desc_per_pg; 2642 2643 if (!pages) 2644 return 1; 2645 2646 pages++; 2647 2648 while (pages & (pages - 1)) 2649 pages++; 2650 2651 return pages; 2652 } 2653 2654 void bnxt_set_tpa_flags(struct bnxt *bp) 2655 { 2656 bp->flags &= ~BNXT_FLAG_TPA; 2657 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 2658 return; 2659 if (bp->dev->features & NETIF_F_LRO) 2660 bp->flags |= BNXT_FLAG_LRO; 2661 if (bp->dev->features & NETIF_F_GRO) 2662 bp->flags |= BNXT_FLAG_GRO; 2663 } 2664 2665 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must 2666 * be set on entry. 2667 */ 2668 void bnxt_set_ring_params(struct bnxt *bp) 2669 { 2670 u32 ring_size, rx_size, rx_space; 2671 u32 agg_factor = 0, agg_ring_size = 0; 2672 2673 /* 8 for CRC and VLAN */ 2674 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8); 2675 2676 rx_space = rx_size + NET_SKB_PAD + 2677 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 2678 2679 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH; 2680 ring_size = bp->rx_ring_size; 2681 bp->rx_agg_ring_size = 0; 2682 bp->rx_agg_nr_pages = 0; 2683 2684 if (bp->flags & BNXT_FLAG_TPA) 2685 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE); 2686 2687 bp->flags &= ~BNXT_FLAG_JUMBO; 2688 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) { 2689 u32 jumbo_factor; 2690 2691 bp->flags |= BNXT_FLAG_JUMBO; 2692 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; 2693 if (jumbo_factor > agg_factor) 2694 agg_factor = jumbo_factor; 2695 } 2696 agg_ring_size = ring_size * agg_factor; 2697 2698 if (agg_ring_size) { 2699 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size, 2700 RX_DESC_CNT); 2701 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) { 2702 u32 tmp = agg_ring_size; 2703 2704 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES; 2705 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1; 2706 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n", 2707 tmp, agg_ring_size); 2708 } 2709 bp->rx_agg_ring_size = agg_ring_size; 2710 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1; 2711 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN); 2712 rx_space = rx_size + NET_SKB_PAD + 2713 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 2714 } 2715 2716 bp->rx_buf_use_size = rx_size; 2717 bp->rx_buf_size = rx_space; 2718 2719 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT); 2720 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1; 2721 2722 ring_size = bp->tx_ring_size; 2723 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT); 2724 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1; 2725 2726 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size; 2727 bp->cp_ring_size = ring_size; 2728 2729 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT); 2730 if (bp->cp_nr_pages > MAX_CP_PAGES) { 2731 bp->cp_nr_pages = MAX_CP_PAGES; 2732 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1; 2733 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n", 2734 ring_size, bp->cp_ring_size); 2735 } 2736 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT; 2737 bp->cp_ring_mask = bp->cp_bit - 1; 2738 } 2739 2740 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode) 2741 { 2742 if (page_mode) { 2743 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU) 2744 return -EOPNOTSUPP; 2745 bp->dev->max_mtu = BNXT_MAX_PAGE_MODE_MTU; 2746 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 2747 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE; 2748 bp->dev->hw_features &= ~NETIF_F_LRO; 2749 bp->dev->features &= ~NETIF_F_LRO; 2750 bp->rx_dir = DMA_BIDIRECTIONAL; 2751 bp->rx_skb_func = bnxt_rx_page_skb; 2752 } else { 2753 bp->dev->max_mtu = BNXT_MAX_MTU; 2754 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE; 2755 bp->rx_dir = DMA_FROM_DEVICE; 2756 bp->rx_skb_func = bnxt_rx_skb; 2757 } 2758 return 0; 2759 } 2760 2761 static void bnxt_free_vnic_attributes(struct bnxt *bp) 2762 { 2763 int i; 2764 struct bnxt_vnic_info *vnic; 2765 struct pci_dev *pdev = bp->pdev; 2766 2767 if (!bp->vnic_info) 2768 return; 2769 2770 for (i = 0; i < bp->nr_vnics; i++) { 2771 vnic = &bp->vnic_info[i]; 2772 2773 kfree(vnic->fw_grp_ids); 2774 vnic->fw_grp_ids = NULL; 2775 2776 kfree(vnic->uc_list); 2777 vnic->uc_list = NULL; 2778 2779 if (vnic->mc_list) { 2780 dma_free_coherent(&pdev->dev, vnic->mc_list_size, 2781 vnic->mc_list, vnic->mc_list_mapping); 2782 vnic->mc_list = NULL; 2783 } 2784 2785 if (vnic->rss_table) { 2786 dma_free_coherent(&pdev->dev, PAGE_SIZE, 2787 vnic->rss_table, 2788 vnic->rss_table_dma_addr); 2789 vnic->rss_table = NULL; 2790 } 2791 2792 vnic->rss_hash_key = NULL; 2793 vnic->flags = 0; 2794 } 2795 } 2796 2797 static int bnxt_alloc_vnic_attributes(struct bnxt *bp) 2798 { 2799 int i, rc = 0, size; 2800 struct bnxt_vnic_info *vnic; 2801 struct pci_dev *pdev = bp->pdev; 2802 int max_rings; 2803 2804 for (i = 0; i < bp->nr_vnics; i++) { 2805 vnic = &bp->vnic_info[i]; 2806 2807 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) { 2808 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN; 2809 2810 if (mem_size > 0) { 2811 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL); 2812 if (!vnic->uc_list) { 2813 rc = -ENOMEM; 2814 goto out; 2815 } 2816 } 2817 } 2818 2819 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) { 2820 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN; 2821 vnic->mc_list = 2822 dma_alloc_coherent(&pdev->dev, 2823 vnic->mc_list_size, 2824 &vnic->mc_list_mapping, 2825 GFP_KERNEL); 2826 if (!vnic->mc_list) { 2827 rc = -ENOMEM; 2828 goto out; 2829 } 2830 } 2831 2832 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 2833 max_rings = bp->rx_nr_rings; 2834 else 2835 max_rings = 1; 2836 2837 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL); 2838 if (!vnic->fw_grp_ids) { 2839 rc = -ENOMEM; 2840 goto out; 2841 } 2842 2843 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) && 2844 !(vnic->flags & BNXT_VNIC_RSS_FLAG)) 2845 continue; 2846 2847 /* Allocate rss table and hash key */ 2848 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 2849 &vnic->rss_table_dma_addr, 2850 GFP_KERNEL); 2851 if (!vnic->rss_table) { 2852 rc = -ENOMEM; 2853 goto out; 2854 } 2855 2856 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16)); 2857 2858 vnic->rss_hash_key = ((void *)vnic->rss_table) + size; 2859 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; 2860 } 2861 return 0; 2862 2863 out: 2864 return rc; 2865 } 2866 2867 static void bnxt_free_hwrm_resources(struct bnxt *bp) 2868 { 2869 struct pci_dev *pdev = bp->pdev; 2870 2871 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr, 2872 bp->hwrm_cmd_resp_dma_addr); 2873 2874 bp->hwrm_cmd_resp_addr = NULL; 2875 if (bp->hwrm_dbg_resp_addr) { 2876 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE, 2877 bp->hwrm_dbg_resp_addr, 2878 bp->hwrm_dbg_resp_dma_addr); 2879 2880 bp->hwrm_dbg_resp_addr = NULL; 2881 } 2882 } 2883 2884 static int bnxt_alloc_hwrm_resources(struct bnxt *bp) 2885 { 2886 struct pci_dev *pdev = bp->pdev; 2887 2888 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 2889 &bp->hwrm_cmd_resp_dma_addr, 2890 GFP_KERNEL); 2891 if (!bp->hwrm_cmd_resp_addr) 2892 return -ENOMEM; 2893 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev, 2894 HWRM_DBG_REG_BUF_SIZE, 2895 &bp->hwrm_dbg_resp_dma_addr, 2896 GFP_KERNEL); 2897 if (!bp->hwrm_dbg_resp_addr) 2898 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n"); 2899 2900 return 0; 2901 } 2902 2903 static void bnxt_free_stats(struct bnxt *bp) 2904 { 2905 u32 size, i; 2906 struct pci_dev *pdev = bp->pdev; 2907 2908 if (bp->hw_rx_port_stats) { 2909 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size, 2910 bp->hw_rx_port_stats, 2911 bp->hw_rx_port_stats_map); 2912 bp->hw_rx_port_stats = NULL; 2913 bp->flags &= ~BNXT_FLAG_PORT_STATS; 2914 } 2915 2916 if (!bp->bnapi) 2917 return; 2918 2919 size = sizeof(struct ctx_hw_stats); 2920 2921 for (i = 0; i < bp->cp_nr_rings; i++) { 2922 struct bnxt_napi *bnapi = bp->bnapi[i]; 2923 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2924 2925 if (cpr->hw_stats) { 2926 dma_free_coherent(&pdev->dev, size, cpr->hw_stats, 2927 cpr->hw_stats_map); 2928 cpr->hw_stats = NULL; 2929 } 2930 } 2931 } 2932 2933 static int bnxt_alloc_stats(struct bnxt *bp) 2934 { 2935 u32 size, i; 2936 struct pci_dev *pdev = bp->pdev; 2937 2938 size = sizeof(struct ctx_hw_stats); 2939 2940 for (i = 0; i < bp->cp_nr_rings; i++) { 2941 struct bnxt_napi *bnapi = bp->bnapi[i]; 2942 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2943 2944 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size, 2945 &cpr->hw_stats_map, 2946 GFP_KERNEL); 2947 if (!cpr->hw_stats) 2948 return -ENOMEM; 2949 2950 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 2951 } 2952 2953 if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) { 2954 bp->hw_port_stats_size = sizeof(struct rx_port_stats) + 2955 sizeof(struct tx_port_stats) + 1024; 2956 2957 bp->hw_rx_port_stats = 2958 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size, 2959 &bp->hw_rx_port_stats_map, 2960 GFP_KERNEL); 2961 if (!bp->hw_rx_port_stats) 2962 return -ENOMEM; 2963 2964 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) + 2965 512; 2966 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map + 2967 sizeof(struct rx_port_stats) + 512; 2968 bp->flags |= BNXT_FLAG_PORT_STATS; 2969 } 2970 return 0; 2971 } 2972 2973 static void bnxt_clear_ring_indices(struct bnxt *bp) 2974 { 2975 int i; 2976 2977 if (!bp->bnapi) 2978 return; 2979 2980 for (i = 0; i < bp->cp_nr_rings; i++) { 2981 struct bnxt_napi *bnapi = bp->bnapi[i]; 2982 struct bnxt_cp_ring_info *cpr; 2983 struct bnxt_rx_ring_info *rxr; 2984 struct bnxt_tx_ring_info *txr; 2985 2986 if (!bnapi) 2987 continue; 2988 2989 cpr = &bnapi->cp_ring; 2990 cpr->cp_raw_cons = 0; 2991 2992 txr = bnapi->tx_ring; 2993 if (txr) { 2994 txr->tx_prod = 0; 2995 txr->tx_cons = 0; 2996 } 2997 2998 rxr = bnapi->rx_ring; 2999 if (rxr) { 3000 rxr->rx_prod = 0; 3001 rxr->rx_agg_prod = 0; 3002 rxr->rx_sw_agg_prod = 0; 3003 rxr->rx_next_cons = 0; 3004 } 3005 } 3006 } 3007 3008 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit) 3009 { 3010 #ifdef CONFIG_RFS_ACCEL 3011 int i; 3012 3013 /* Under rtnl_lock and all our NAPIs have been disabled. It's 3014 * safe to delete the hash table. 3015 */ 3016 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 3017 struct hlist_head *head; 3018 struct hlist_node *tmp; 3019 struct bnxt_ntuple_filter *fltr; 3020 3021 head = &bp->ntp_fltr_hash_tbl[i]; 3022 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 3023 hlist_del(&fltr->hash); 3024 kfree(fltr); 3025 } 3026 } 3027 if (irq_reinit) { 3028 kfree(bp->ntp_fltr_bmap); 3029 bp->ntp_fltr_bmap = NULL; 3030 } 3031 bp->ntp_fltr_count = 0; 3032 #endif 3033 } 3034 3035 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp) 3036 { 3037 #ifdef CONFIG_RFS_ACCEL 3038 int i, rc = 0; 3039 3040 if (!(bp->flags & BNXT_FLAG_RFS)) 3041 return 0; 3042 3043 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) 3044 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]); 3045 3046 bp->ntp_fltr_count = 0; 3047 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR), 3048 sizeof(long), 3049 GFP_KERNEL); 3050 3051 if (!bp->ntp_fltr_bmap) 3052 rc = -ENOMEM; 3053 3054 return rc; 3055 #else 3056 return 0; 3057 #endif 3058 } 3059 3060 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init) 3061 { 3062 bnxt_free_vnic_attributes(bp); 3063 bnxt_free_tx_rings(bp); 3064 bnxt_free_rx_rings(bp); 3065 bnxt_free_cp_rings(bp); 3066 bnxt_free_ntp_fltrs(bp, irq_re_init); 3067 if (irq_re_init) { 3068 bnxt_free_stats(bp); 3069 bnxt_free_ring_grps(bp); 3070 bnxt_free_vnics(bp); 3071 kfree(bp->tx_ring_map); 3072 bp->tx_ring_map = NULL; 3073 kfree(bp->tx_ring); 3074 bp->tx_ring = NULL; 3075 kfree(bp->rx_ring); 3076 bp->rx_ring = NULL; 3077 kfree(bp->bnapi); 3078 bp->bnapi = NULL; 3079 } else { 3080 bnxt_clear_ring_indices(bp); 3081 } 3082 } 3083 3084 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init) 3085 { 3086 int i, j, rc, size, arr_size; 3087 void *bnapi; 3088 3089 if (irq_re_init) { 3090 /* Allocate bnapi mem pointer array and mem block for 3091 * all queues 3092 */ 3093 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) * 3094 bp->cp_nr_rings); 3095 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi)); 3096 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL); 3097 if (!bnapi) 3098 return -ENOMEM; 3099 3100 bp->bnapi = bnapi; 3101 bnapi += arr_size; 3102 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) { 3103 bp->bnapi[i] = bnapi; 3104 bp->bnapi[i]->index = i; 3105 bp->bnapi[i]->bp = bp; 3106 } 3107 3108 bp->rx_ring = kcalloc(bp->rx_nr_rings, 3109 sizeof(struct bnxt_rx_ring_info), 3110 GFP_KERNEL); 3111 if (!bp->rx_ring) 3112 return -ENOMEM; 3113 3114 for (i = 0; i < bp->rx_nr_rings; i++) { 3115 bp->rx_ring[i].bnapi = bp->bnapi[i]; 3116 bp->bnapi[i]->rx_ring = &bp->rx_ring[i]; 3117 } 3118 3119 bp->tx_ring = kcalloc(bp->tx_nr_rings, 3120 sizeof(struct bnxt_tx_ring_info), 3121 GFP_KERNEL); 3122 if (!bp->tx_ring) 3123 return -ENOMEM; 3124 3125 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16), 3126 GFP_KERNEL); 3127 3128 if (!bp->tx_ring_map) 3129 return -ENOMEM; 3130 3131 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 3132 j = 0; 3133 else 3134 j = bp->rx_nr_rings; 3135 3136 for (i = 0; i < bp->tx_nr_rings; i++, j++) { 3137 bp->tx_ring[i].bnapi = bp->bnapi[j]; 3138 bp->bnapi[j]->tx_ring = &bp->tx_ring[i]; 3139 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i; 3140 if (i >= bp->tx_nr_rings_xdp) { 3141 bp->tx_ring[i].txq_index = i - 3142 bp->tx_nr_rings_xdp; 3143 bp->bnapi[j]->tx_int = bnxt_tx_int; 3144 } else { 3145 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP; 3146 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp; 3147 } 3148 } 3149 3150 rc = bnxt_alloc_stats(bp); 3151 if (rc) 3152 goto alloc_mem_err; 3153 3154 rc = bnxt_alloc_ntp_fltrs(bp); 3155 if (rc) 3156 goto alloc_mem_err; 3157 3158 rc = bnxt_alloc_vnics(bp); 3159 if (rc) 3160 goto alloc_mem_err; 3161 } 3162 3163 bnxt_init_ring_struct(bp); 3164 3165 rc = bnxt_alloc_rx_rings(bp); 3166 if (rc) 3167 goto alloc_mem_err; 3168 3169 rc = bnxt_alloc_tx_rings(bp); 3170 if (rc) 3171 goto alloc_mem_err; 3172 3173 rc = bnxt_alloc_cp_rings(bp); 3174 if (rc) 3175 goto alloc_mem_err; 3176 3177 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG | 3178 BNXT_VNIC_UCAST_FLAG; 3179 rc = bnxt_alloc_vnic_attributes(bp); 3180 if (rc) 3181 goto alloc_mem_err; 3182 return 0; 3183 3184 alloc_mem_err: 3185 bnxt_free_mem(bp, true); 3186 return rc; 3187 } 3188 3189 static void bnxt_disable_int(struct bnxt *bp) 3190 { 3191 int i; 3192 3193 if (!bp->bnapi) 3194 return; 3195 3196 for (i = 0; i < bp->cp_nr_rings; i++) { 3197 struct bnxt_napi *bnapi = bp->bnapi[i]; 3198 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3199 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 3200 3201 if (ring->fw_ring_id != INVALID_HW_RING_ID) 3202 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); 3203 } 3204 } 3205 3206 static void bnxt_disable_int_sync(struct bnxt *bp) 3207 { 3208 int i; 3209 3210 atomic_inc(&bp->intr_sem); 3211 3212 bnxt_disable_int(bp); 3213 for (i = 0; i < bp->cp_nr_rings; i++) 3214 synchronize_irq(bp->irq_tbl[i].vector); 3215 } 3216 3217 static void bnxt_enable_int(struct bnxt *bp) 3218 { 3219 int i; 3220 3221 atomic_set(&bp->intr_sem, 0); 3222 for (i = 0; i < bp->cp_nr_rings; i++) { 3223 struct bnxt_napi *bnapi = bp->bnapi[i]; 3224 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3225 3226 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons); 3227 } 3228 } 3229 3230 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type, 3231 u16 cmpl_ring, u16 target_id) 3232 { 3233 struct input *req = request; 3234 3235 req->req_type = cpu_to_le16(req_type); 3236 req->cmpl_ring = cpu_to_le16(cmpl_ring); 3237 req->target_id = cpu_to_le16(target_id); 3238 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr); 3239 } 3240 3241 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len, 3242 int timeout, bool silent) 3243 { 3244 int i, intr_process, rc, tmo_count; 3245 struct input *req = msg; 3246 u32 *data = msg; 3247 __le32 *resp_len, *valid; 3248 u16 cp_ring_id, len = 0; 3249 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr; 3250 3251 req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++); 3252 memset(resp, 0, PAGE_SIZE); 3253 cp_ring_id = le16_to_cpu(req->cmpl_ring); 3254 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1; 3255 3256 /* Write request msg to hwrm channel */ 3257 __iowrite32_copy(bp->bar0, data, msg_len / 4); 3258 3259 for (i = msg_len; i < BNXT_HWRM_MAX_REQ_LEN; i += 4) 3260 writel(0, bp->bar0 + i); 3261 3262 /* currently supports only one outstanding message */ 3263 if (intr_process) 3264 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id); 3265 3266 /* Ring channel doorbell */ 3267 writel(1, bp->bar0 + 0x100); 3268 3269 if (!timeout) 3270 timeout = DFLT_HWRM_CMD_TIMEOUT; 3271 3272 i = 0; 3273 tmo_count = timeout * 40; 3274 if (intr_process) { 3275 /* Wait until hwrm response cmpl interrupt is processed */ 3276 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID && 3277 i++ < tmo_count) { 3278 usleep_range(25, 40); 3279 } 3280 3281 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) { 3282 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n", 3283 le16_to_cpu(req->req_type)); 3284 return -1; 3285 } 3286 } else { 3287 /* Check if response len is updated */ 3288 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET; 3289 for (i = 0; i < tmo_count; i++) { 3290 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >> 3291 HWRM_RESP_LEN_SFT; 3292 if (len) 3293 break; 3294 usleep_range(25, 40); 3295 } 3296 3297 if (i >= tmo_count) { 3298 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n", 3299 timeout, le16_to_cpu(req->req_type), 3300 le16_to_cpu(req->seq_id), len); 3301 return -1; 3302 } 3303 3304 /* Last word of resp contains valid bit */ 3305 valid = bp->hwrm_cmd_resp_addr + len - 4; 3306 for (i = 0; i < 5; i++) { 3307 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK) 3308 break; 3309 udelay(1); 3310 } 3311 3312 if (i >= 5) { 3313 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n", 3314 timeout, le16_to_cpu(req->req_type), 3315 le16_to_cpu(req->seq_id), len, *valid); 3316 return -1; 3317 } 3318 } 3319 3320 rc = le16_to_cpu(resp->error_code); 3321 if (rc && !silent) 3322 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n", 3323 le16_to_cpu(resp->req_type), 3324 le16_to_cpu(resp->seq_id), rc); 3325 return rc; 3326 } 3327 3328 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 3329 { 3330 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false); 3331 } 3332 3333 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 3334 { 3335 int rc; 3336 3337 mutex_lock(&bp->hwrm_cmd_lock); 3338 rc = _hwrm_send_message(bp, msg, msg_len, timeout); 3339 mutex_unlock(&bp->hwrm_cmd_lock); 3340 return rc; 3341 } 3342 3343 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, 3344 int timeout) 3345 { 3346 int rc; 3347 3348 mutex_lock(&bp->hwrm_cmd_lock); 3349 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); 3350 mutex_unlock(&bp->hwrm_cmd_lock); 3351 return rc; 3352 } 3353 3354 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap, 3355 int bmap_size) 3356 { 3357 struct hwrm_func_drv_rgtr_input req = {0}; 3358 DECLARE_BITMAP(async_events_bmap, 256); 3359 u32 *events = (u32 *)async_events_bmap; 3360 int i; 3361 3362 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); 3363 3364 req.enables = 3365 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); 3366 3367 memset(async_events_bmap, 0, sizeof(async_events_bmap)); 3368 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) 3369 __set_bit(bnxt_async_events_arr[i], async_events_bmap); 3370 3371 if (bmap && bmap_size) { 3372 for (i = 0; i < bmap_size; i++) { 3373 if (test_bit(i, bmap)) 3374 __set_bit(i, async_events_bmap); 3375 } 3376 } 3377 3378 for (i = 0; i < 8; i++) 3379 req.async_event_fwd[i] |= cpu_to_le32(events[i]); 3380 3381 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3382 } 3383 3384 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp) 3385 { 3386 struct hwrm_func_drv_rgtr_input req = {0}; 3387 3388 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); 3389 3390 req.enables = 3391 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE | 3392 FUNC_DRV_RGTR_REQ_ENABLES_VER); 3393 3394 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX); 3395 req.ver_maj = DRV_VER_MAJ; 3396 req.ver_min = DRV_VER_MIN; 3397 req.ver_upd = DRV_VER_UPD; 3398 3399 if (BNXT_PF(bp)) { 3400 DECLARE_BITMAP(vf_req_snif_bmap, 256); 3401 u32 *data = (u32 *)vf_req_snif_bmap; 3402 int i; 3403 3404 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap)); 3405 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) 3406 __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap); 3407 3408 for (i = 0; i < 8; i++) 3409 req.vf_req_fwd[i] = cpu_to_le32(data[i]); 3410 3411 req.enables |= 3412 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD); 3413 } 3414 3415 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3416 } 3417 3418 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp) 3419 { 3420 struct hwrm_func_drv_unrgtr_input req = {0}; 3421 3422 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1); 3423 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3424 } 3425 3426 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type) 3427 { 3428 u32 rc = 0; 3429 struct hwrm_tunnel_dst_port_free_input req = {0}; 3430 3431 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1); 3432 req.tunnel_type = tunnel_type; 3433 3434 switch (tunnel_type) { 3435 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN: 3436 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id; 3437 break; 3438 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE: 3439 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id; 3440 break; 3441 default: 3442 break; 3443 } 3444 3445 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3446 if (rc) 3447 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n", 3448 rc); 3449 return rc; 3450 } 3451 3452 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port, 3453 u8 tunnel_type) 3454 { 3455 u32 rc = 0; 3456 struct hwrm_tunnel_dst_port_alloc_input req = {0}; 3457 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr; 3458 3459 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1); 3460 3461 req.tunnel_type = tunnel_type; 3462 req.tunnel_dst_port_val = port; 3463 3464 mutex_lock(&bp->hwrm_cmd_lock); 3465 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3466 if (rc) { 3467 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n", 3468 rc); 3469 goto err_out; 3470 } 3471 3472 switch (tunnel_type) { 3473 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN: 3474 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id; 3475 break; 3476 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE: 3477 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id; 3478 break; 3479 default: 3480 break; 3481 } 3482 3483 err_out: 3484 mutex_unlock(&bp->hwrm_cmd_lock); 3485 return rc; 3486 } 3487 3488 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id) 3489 { 3490 struct hwrm_cfa_l2_set_rx_mask_input req = {0}; 3491 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3492 3493 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1); 3494 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 3495 3496 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count); 3497 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping); 3498 req.mask = cpu_to_le32(vnic->rx_mask); 3499 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3500 } 3501 3502 #ifdef CONFIG_RFS_ACCEL 3503 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp, 3504 struct bnxt_ntuple_filter *fltr) 3505 { 3506 struct hwrm_cfa_ntuple_filter_free_input req = {0}; 3507 3508 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1); 3509 req.ntuple_filter_id = fltr->filter_id; 3510 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3511 } 3512 3513 #define BNXT_NTP_FLTR_FLAGS \ 3514 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \ 3515 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \ 3516 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \ 3517 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \ 3518 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \ 3519 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \ 3520 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \ 3521 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \ 3522 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \ 3523 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \ 3524 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \ 3525 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \ 3526 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \ 3527 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID) 3528 3529 #define BNXT_NTP_TUNNEL_FLTR_FLAG \ 3530 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 3531 3532 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp, 3533 struct bnxt_ntuple_filter *fltr) 3534 { 3535 int rc = 0; 3536 struct hwrm_cfa_ntuple_filter_alloc_input req = {0}; 3537 struct hwrm_cfa_ntuple_filter_alloc_output *resp = 3538 bp->hwrm_cmd_resp_addr; 3539 struct flow_keys *keys = &fltr->fkeys; 3540 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1]; 3541 3542 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1); 3543 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx]; 3544 3545 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS); 3546 3547 req.ethertype = htons(ETH_P_IP); 3548 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN); 3549 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4; 3550 req.ip_protocol = keys->basic.ip_proto; 3551 3552 if (keys->basic.n_proto == htons(ETH_P_IPV6)) { 3553 int i; 3554 3555 req.ethertype = htons(ETH_P_IPV6); 3556 req.ip_addr_type = 3557 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6; 3558 *(struct in6_addr *)&req.src_ipaddr[0] = 3559 keys->addrs.v6addrs.src; 3560 *(struct in6_addr *)&req.dst_ipaddr[0] = 3561 keys->addrs.v6addrs.dst; 3562 for (i = 0; i < 4; i++) { 3563 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 3564 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 3565 } 3566 } else { 3567 req.src_ipaddr[0] = keys->addrs.v4addrs.src; 3568 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 3569 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst; 3570 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 3571 } 3572 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) { 3573 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG); 3574 req.tunnel_type = 3575 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL; 3576 } 3577 3578 req.src_port = keys->ports.src; 3579 req.src_port_mask = cpu_to_be16(0xffff); 3580 req.dst_port = keys->ports.dst; 3581 req.dst_port_mask = cpu_to_be16(0xffff); 3582 3583 req.dst_id = cpu_to_le16(vnic->fw_vnic_id); 3584 mutex_lock(&bp->hwrm_cmd_lock); 3585 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3586 if (!rc) 3587 fltr->filter_id = resp->ntuple_filter_id; 3588 mutex_unlock(&bp->hwrm_cmd_lock); 3589 return rc; 3590 } 3591 #endif 3592 3593 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx, 3594 u8 *mac_addr) 3595 { 3596 u32 rc = 0; 3597 struct hwrm_cfa_l2_filter_alloc_input req = {0}; 3598 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; 3599 3600 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1); 3601 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX); 3602 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) 3603 req.flags |= 3604 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST); 3605 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id); 3606 req.enables = 3607 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR | 3608 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID | 3609 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK); 3610 memcpy(req.l2_addr, mac_addr, ETH_ALEN); 3611 req.l2_addr_mask[0] = 0xff; 3612 req.l2_addr_mask[1] = 0xff; 3613 req.l2_addr_mask[2] = 0xff; 3614 req.l2_addr_mask[3] = 0xff; 3615 req.l2_addr_mask[4] = 0xff; 3616 req.l2_addr_mask[5] = 0xff; 3617 3618 mutex_lock(&bp->hwrm_cmd_lock); 3619 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3620 if (!rc) 3621 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] = 3622 resp->l2_filter_id; 3623 mutex_unlock(&bp->hwrm_cmd_lock); 3624 return rc; 3625 } 3626 3627 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp) 3628 { 3629 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */ 3630 int rc = 0; 3631 3632 /* Any associated ntuple filters will also be cleared by firmware. */ 3633 mutex_lock(&bp->hwrm_cmd_lock); 3634 for (i = 0; i < num_of_vnics; i++) { 3635 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3636 3637 for (j = 0; j < vnic->uc_filter_count; j++) { 3638 struct hwrm_cfa_l2_filter_free_input req = {0}; 3639 3640 bnxt_hwrm_cmd_hdr_init(bp, &req, 3641 HWRM_CFA_L2_FILTER_FREE, -1, -1); 3642 3643 req.l2_filter_id = vnic->fw_l2_filter_id[j]; 3644 3645 rc = _hwrm_send_message(bp, &req, sizeof(req), 3646 HWRM_CMD_TIMEOUT); 3647 } 3648 vnic->uc_filter_count = 0; 3649 } 3650 mutex_unlock(&bp->hwrm_cmd_lock); 3651 3652 return rc; 3653 } 3654 3655 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags) 3656 { 3657 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3658 struct hwrm_vnic_tpa_cfg_input req = {0}; 3659 3660 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1); 3661 3662 if (tpa_flags) { 3663 u16 mss = bp->dev->mtu - 40; 3664 u32 nsegs, n, segs = 0, flags; 3665 3666 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA | 3667 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA | 3668 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE | 3669 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN | 3670 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ; 3671 if (tpa_flags & BNXT_FLAG_GRO) 3672 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO; 3673 3674 req.flags = cpu_to_le32(flags); 3675 3676 req.enables = 3677 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS | 3678 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS | 3679 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN); 3680 3681 /* Number of segs are log2 units, and first packet is not 3682 * included as part of this units. 3683 */ 3684 if (mss <= BNXT_RX_PAGE_SIZE) { 3685 n = BNXT_RX_PAGE_SIZE / mss; 3686 nsegs = (MAX_SKB_FRAGS - 1) * n; 3687 } else { 3688 n = mss / BNXT_RX_PAGE_SIZE; 3689 if (mss & (BNXT_RX_PAGE_SIZE - 1)) 3690 n++; 3691 nsegs = (MAX_SKB_FRAGS - n) / n; 3692 } 3693 3694 segs = ilog2(nsegs); 3695 req.max_agg_segs = cpu_to_le16(segs); 3696 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX); 3697 3698 req.min_agg_len = cpu_to_le32(512); 3699 } 3700 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 3701 3702 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3703 } 3704 3705 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss) 3706 { 3707 u32 i, j, max_rings; 3708 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3709 struct hwrm_vnic_rss_cfg_input req = {0}; 3710 3711 if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID) 3712 return 0; 3713 3714 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); 3715 if (set_rss) { 3716 req.hash_type = cpu_to_le32(bp->rss_hash_cfg); 3717 if (vnic->flags & BNXT_VNIC_RSS_FLAG) { 3718 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 3719 max_rings = bp->rx_nr_rings - 1; 3720 else 3721 max_rings = bp->rx_nr_rings; 3722 } else { 3723 max_rings = 1; 3724 } 3725 3726 /* Fill the RSS indirection table with ring group ids */ 3727 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) { 3728 if (j == max_rings) 3729 j = 0; 3730 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]); 3731 } 3732 3733 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); 3734 req.hash_key_tbl_addr = 3735 cpu_to_le64(vnic->rss_hash_key_dma_addr); 3736 } 3737 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 3738 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3739 } 3740 3741 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id) 3742 { 3743 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3744 struct hwrm_vnic_plcmodes_cfg_input req = {0}; 3745 3746 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1); 3747 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT | 3748 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 | 3749 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6); 3750 req.enables = 3751 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID | 3752 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID); 3753 /* thresholds not implemented in firmware yet */ 3754 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh); 3755 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh); 3756 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 3757 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3758 } 3759 3760 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id, 3761 u16 ctx_idx) 3762 { 3763 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0}; 3764 3765 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1); 3766 req.rss_cos_lb_ctx_id = 3767 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]); 3768 3769 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3770 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID; 3771 } 3772 3773 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp) 3774 { 3775 int i, j; 3776 3777 for (i = 0; i < bp->nr_vnics; i++) { 3778 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3779 3780 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) { 3781 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID) 3782 bnxt_hwrm_vnic_ctx_free_one(bp, i, j); 3783 } 3784 } 3785 bp->rsscos_nr_ctxs = 0; 3786 } 3787 3788 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx) 3789 { 3790 int rc; 3791 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0}; 3792 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp = 3793 bp->hwrm_cmd_resp_addr; 3794 3795 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1, 3796 -1); 3797 3798 mutex_lock(&bp->hwrm_cmd_lock); 3799 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3800 if (!rc) 3801 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = 3802 le16_to_cpu(resp->rss_cos_lb_ctx_id); 3803 mutex_unlock(&bp->hwrm_cmd_lock); 3804 3805 return rc; 3806 } 3807 3808 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id) 3809 { 3810 unsigned int ring = 0, grp_idx; 3811 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 3812 struct hwrm_vnic_cfg_input req = {0}; 3813 u16 def_vlan = 0; 3814 3815 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1); 3816 3817 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP); 3818 /* Only RSS support for now TBD: COS & LB */ 3819 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) { 3820 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 3821 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 3822 VNIC_CFG_REQ_ENABLES_MRU); 3823 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) { 3824 req.rss_rule = 3825 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]); 3826 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 3827 VNIC_CFG_REQ_ENABLES_MRU); 3828 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE); 3829 } else { 3830 req.rss_rule = cpu_to_le16(0xffff); 3831 } 3832 3833 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && 3834 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) { 3835 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]); 3836 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE); 3837 } else { 3838 req.cos_rule = cpu_to_le16(0xffff); 3839 } 3840 3841 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 3842 ring = 0; 3843 else if (vnic->flags & BNXT_VNIC_RFS_FLAG) 3844 ring = vnic_id - 1; 3845 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp)) 3846 ring = bp->rx_nr_rings - 1; 3847 3848 grp_idx = bp->rx_ring[ring].bnapi->index; 3849 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 3850 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id); 3851 3852 req.lb_rule = cpu_to_le16(0xffff); 3853 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + 3854 VLAN_HLEN); 3855 3856 #ifdef CONFIG_BNXT_SRIOV 3857 if (BNXT_VF(bp)) 3858 def_vlan = bp->vf.vlan; 3859 #endif 3860 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan) 3861 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE); 3862 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP)) 3863 req.flags |= 3864 cpu_to_le32(VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE); 3865 3866 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3867 } 3868 3869 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id) 3870 { 3871 u32 rc = 0; 3872 3873 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) { 3874 struct hwrm_vnic_free_input req = {0}; 3875 3876 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1); 3877 req.vnic_id = 3878 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id); 3879 3880 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3881 if (rc) 3882 return rc; 3883 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID; 3884 } 3885 return rc; 3886 } 3887 3888 static void bnxt_hwrm_vnic_free(struct bnxt *bp) 3889 { 3890 u16 i; 3891 3892 for (i = 0; i < bp->nr_vnics; i++) 3893 bnxt_hwrm_vnic_free_one(bp, i); 3894 } 3895 3896 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, 3897 unsigned int start_rx_ring_idx, 3898 unsigned int nr_rings) 3899 { 3900 int rc = 0; 3901 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings; 3902 struct hwrm_vnic_alloc_input req = {0}; 3903 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr; 3904 3905 /* map ring groups to this vnic */ 3906 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) { 3907 grp_idx = bp->rx_ring[i].bnapi->index; 3908 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) { 3909 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n", 3910 j, nr_rings); 3911 break; 3912 } 3913 bp->vnic_info[vnic_id].fw_grp_ids[j] = 3914 bp->grp_info[grp_idx].fw_grp_id; 3915 } 3916 3917 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID; 3918 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID; 3919 if (vnic_id == 0) 3920 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT); 3921 3922 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1); 3923 3924 mutex_lock(&bp->hwrm_cmd_lock); 3925 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3926 if (!rc) 3927 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id); 3928 mutex_unlock(&bp->hwrm_cmd_lock); 3929 return rc; 3930 } 3931 3932 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp) 3933 { 3934 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 3935 struct hwrm_vnic_qcaps_input req = {0}; 3936 int rc; 3937 3938 if (bp->hwrm_spec_code < 0x10600) 3939 return 0; 3940 3941 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1); 3942 mutex_lock(&bp->hwrm_cmd_lock); 3943 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3944 if (!rc) { 3945 if (resp->flags & 3946 cpu_to_le32(VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP)) 3947 bp->flags |= BNXT_FLAG_NEW_RSS_CAP; 3948 } 3949 mutex_unlock(&bp->hwrm_cmd_lock); 3950 return rc; 3951 } 3952 3953 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp) 3954 { 3955 u16 i; 3956 u32 rc = 0; 3957 3958 mutex_lock(&bp->hwrm_cmd_lock); 3959 for (i = 0; i < bp->rx_nr_rings; i++) { 3960 struct hwrm_ring_grp_alloc_input req = {0}; 3961 struct hwrm_ring_grp_alloc_output *resp = 3962 bp->hwrm_cmd_resp_addr; 3963 unsigned int grp_idx = bp->rx_ring[i].bnapi->index; 3964 3965 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1); 3966 3967 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id); 3968 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id); 3969 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id); 3970 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx); 3971 3972 rc = _hwrm_send_message(bp, &req, sizeof(req), 3973 HWRM_CMD_TIMEOUT); 3974 if (rc) 3975 break; 3976 3977 bp->grp_info[grp_idx].fw_grp_id = 3978 le32_to_cpu(resp->ring_group_id); 3979 } 3980 mutex_unlock(&bp->hwrm_cmd_lock); 3981 return rc; 3982 } 3983 3984 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp) 3985 { 3986 u16 i; 3987 u32 rc = 0; 3988 struct hwrm_ring_grp_free_input req = {0}; 3989 3990 if (!bp->grp_info) 3991 return 0; 3992 3993 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1); 3994 3995 mutex_lock(&bp->hwrm_cmd_lock); 3996 for (i = 0; i < bp->cp_nr_rings; i++) { 3997 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) 3998 continue; 3999 req.ring_group_id = 4000 cpu_to_le32(bp->grp_info[i].fw_grp_id); 4001 4002 rc = _hwrm_send_message(bp, &req, sizeof(req), 4003 HWRM_CMD_TIMEOUT); 4004 if (rc) 4005 break; 4006 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 4007 } 4008 mutex_unlock(&bp->hwrm_cmd_lock); 4009 return rc; 4010 } 4011 4012 static int hwrm_ring_alloc_send_msg(struct bnxt *bp, 4013 struct bnxt_ring_struct *ring, 4014 u32 ring_type, u32 map_index, 4015 u32 stats_ctx_id) 4016 { 4017 int rc = 0, err = 0; 4018 struct hwrm_ring_alloc_input req = {0}; 4019 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4020 u16 ring_id; 4021 4022 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1); 4023 4024 req.enables = 0; 4025 if (ring->nr_pages > 1) { 4026 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map); 4027 /* Page size is in log2 units */ 4028 req.page_size = BNXT_PAGE_SHIFT; 4029 req.page_tbl_depth = 1; 4030 } else { 4031 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]); 4032 } 4033 req.fbo = 0; 4034 /* Association of ring index with doorbell index and MSIX number */ 4035 req.logical_id = cpu_to_le16(map_index); 4036 4037 switch (ring_type) { 4038 case HWRM_RING_ALLOC_TX: 4039 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX; 4040 /* Association of transmit ring with completion ring */ 4041 req.cmpl_ring_id = 4042 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id); 4043 req.length = cpu_to_le32(bp->tx_ring_mask + 1); 4044 req.stat_ctx_id = cpu_to_le32(stats_ctx_id); 4045 req.queue_id = cpu_to_le16(ring->queue_id); 4046 break; 4047 case HWRM_RING_ALLOC_RX: 4048 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 4049 req.length = cpu_to_le32(bp->rx_ring_mask + 1); 4050 break; 4051 case HWRM_RING_ALLOC_AGG: 4052 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 4053 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1); 4054 break; 4055 case HWRM_RING_ALLOC_CMPL: 4056 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL; 4057 req.length = cpu_to_le32(bp->cp_ring_mask + 1); 4058 if (bp->flags & BNXT_FLAG_USING_MSIX) 4059 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; 4060 break; 4061 default: 4062 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n", 4063 ring_type); 4064 return -1; 4065 } 4066 4067 mutex_lock(&bp->hwrm_cmd_lock); 4068 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4069 err = le16_to_cpu(resp->error_code); 4070 ring_id = le16_to_cpu(resp->ring_id); 4071 mutex_unlock(&bp->hwrm_cmd_lock); 4072 4073 if (rc || err) { 4074 switch (ring_type) { 4075 case RING_FREE_REQ_RING_TYPE_L2_CMPL: 4076 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n", 4077 rc, err); 4078 return -1; 4079 4080 case RING_FREE_REQ_RING_TYPE_RX: 4081 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n", 4082 rc, err); 4083 return -1; 4084 4085 case RING_FREE_REQ_RING_TYPE_TX: 4086 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n", 4087 rc, err); 4088 return -1; 4089 4090 default: 4091 netdev_err(bp->dev, "Invalid ring\n"); 4092 return -1; 4093 } 4094 } 4095 ring->fw_ring_id = ring_id; 4096 return rc; 4097 } 4098 4099 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx) 4100 { 4101 int rc; 4102 4103 if (BNXT_PF(bp)) { 4104 struct hwrm_func_cfg_input req = {0}; 4105 4106 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 4107 req.fid = cpu_to_le16(0xffff); 4108 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 4109 req.async_event_cr = cpu_to_le16(idx); 4110 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4111 } else { 4112 struct hwrm_func_vf_cfg_input req = {0}; 4113 4114 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1); 4115 req.enables = 4116 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 4117 req.async_event_cr = cpu_to_le16(idx); 4118 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4119 } 4120 return rc; 4121 } 4122 4123 static int bnxt_hwrm_ring_alloc(struct bnxt *bp) 4124 { 4125 int i, rc = 0; 4126 4127 for (i = 0; i < bp->cp_nr_rings; i++) { 4128 struct bnxt_napi *bnapi = bp->bnapi[i]; 4129 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4130 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 4131 4132 cpr->cp_doorbell = bp->bar1 + i * 0x80; 4133 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i, 4134 INVALID_STATS_CTX_ID); 4135 if (rc) 4136 goto err_out; 4137 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); 4138 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id; 4139 4140 if (!i) { 4141 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id); 4142 if (rc) 4143 netdev_warn(bp->dev, "Failed to set async event completion ring.\n"); 4144 } 4145 } 4146 4147 for (i = 0; i < bp->tx_nr_rings; i++) { 4148 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 4149 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 4150 u32 map_idx = txr->bnapi->index; 4151 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx; 4152 4153 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX, 4154 map_idx, fw_stats_ctx); 4155 if (rc) 4156 goto err_out; 4157 txr->tx_doorbell = bp->bar1 + map_idx * 0x80; 4158 } 4159 4160 for (i = 0; i < bp->rx_nr_rings; i++) { 4161 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 4162 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 4163 u32 map_idx = rxr->bnapi->index; 4164 4165 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX, 4166 map_idx, INVALID_STATS_CTX_ID); 4167 if (rc) 4168 goto err_out; 4169 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80; 4170 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell); 4171 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id; 4172 } 4173 4174 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 4175 for (i = 0; i < bp->rx_nr_rings; i++) { 4176 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 4177 struct bnxt_ring_struct *ring = 4178 &rxr->rx_agg_ring_struct; 4179 u32 grp_idx = rxr->bnapi->index; 4180 u32 map_idx = grp_idx + bp->rx_nr_rings; 4181 4182 rc = hwrm_ring_alloc_send_msg(bp, ring, 4183 HWRM_RING_ALLOC_AGG, 4184 map_idx, 4185 INVALID_STATS_CTX_ID); 4186 if (rc) 4187 goto err_out; 4188 4189 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80; 4190 writel(DB_KEY_RX | rxr->rx_agg_prod, 4191 rxr->rx_agg_doorbell); 4192 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id; 4193 } 4194 } 4195 err_out: 4196 return rc; 4197 } 4198 4199 static int hwrm_ring_free_send_msg(struct bnxt *bp, 4200 struct bnxt_ring_struct *ring, 4201 u32 ring_type, int cmpl_ring_id) 4202 { 4203 int rc; 4204 struct hwrm_ring_free_input req = {0}; 4205 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr; 4206 u16 error_code; 4207 4208 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1); 4209 req.ring_type = ring_type; 4210 req.ring_id = cpu_to_le16(ring->fw_ring_id); 4211 4212 mutex_lock(&bp->hwrm_cmd_lock); 4213 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4214 error_code = le16_to_cpu(resp->error_code); 4215 mutex_unlock(&bp->hwrm_cmd_lock); 4216 4217 if (rc || error_code) { 4218 switch (ring_type) { 4219 case RING_FREE_REQ_RING_TYPE_L2_CMPL: 4220 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n", 4221 rc); 4222 return rc; 4223 case RING_FREE_REQ_RING_TYPE_RX: 4224 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n", 4225 rc); 4226 return rc; 4227 case RING_FREE_REQ_RING_TYPE_TX: 4228 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n", 4229 rc); 4230 return rc; 4231 default: 4232 netdev_err(bp->dev, "Invalid ring\n"); 4233 return -1; 4234 } 4235 } 4236 return 0; 4237 } 4238 4239 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path) 4240 { 4241 int i; 4242 4243 if (!bp->bnapi) 4244 return; 4245 4246 for (i = 0; i < bp->tx_nr_rings; i++) { 4247 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 4248 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 4249 u32 grp_idx = txr->bnapi->index; 4250 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id; 4251 4252 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 4253 hwrm_ring_free_send_msg(bp, ring, 4254 RING_FREE_REQ_RING_TYPE_TX, 4255 close_path ? cmpl_ring_id : 4256 INVALID_HW_RING_ID); 4257 ring->fw_ring_id = INVALID_HW_RING_ID; 4258 } 4259 } 4260 4261 for (i = 0; i < bp->rx_nr_rings; i++) { 4262 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 4263 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 4264 u32 grp_idx = rxr->bnapi->index; 4265 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id; 4266 4267 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 4268 hwrm_ring_free_send_msg(bp, ring, 4269 RING_FREE_REQ_RING_TYPE_RX, 4270 close_path ? cmpl_ring_id : 4271 INVALID_HW_RING_ID); 4272 ring->fw_ring_id = INVALID_HW_RING_ID; 4273 bp->grp_info[grp_idx].rx_fw_ring_id = 4274 INVALID_HW_RING_ID; 4275 } 4276 } 4277 4278 for (i = 0; i < bp->rx_nr_rings; i++) { 4279 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 4280 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct; 4281 u32 grp_idx = rxr->bnapi->index; 4282 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id; 4283 4284 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 4285 hwrm_ring_free_send_msg(bp, ring, 4286 RING_FREE_REQ_RING_TYPE_RX, 4287 close_path ? cmpl_ring_id : 4288 INVALID_HW_RING_ID); 4289 ring->fw_ring_id = INVALID_HW_RING_ID; 4290 bp->grp_info[grp_idx].agg_fw_ring_id = 4291 INVALID_HW_RING_ID; 4292 } 4293 } 4294 4295 /* The completion rings are about to be freed. After that the 4296 * IRQ doorbell will not work anymore. So we need to disable 4297 * IRQ here. 4298 */ 4299 bnxt_disable_int_sync(bp); 4300 4301 for (i = 0; i < bp->cp_nr_rings; i++) { 4302 struct bnxt_napi *bnapi = bp->bnapi[i]; 4303 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4304 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 4305 4306 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 4307 hwrm_ring_free_send_msg(bp, ring, 4308 RING_FREE_REQ_RING_TYPE_L2_CMPL, 4309 INVALID_HW_RING_ID); 4310 ring->fw_ring_id = INVALID_HW_RING_ID; 4311 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 4312 } 4313 } 4314 } 4315 4316 /* Caller must hold bp->hwrm_cmd_lock */ 4317 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings) 4318 { 4319 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 4320 struct hwrm_func_qcfg_input req = {0}; 4321 int rc; 4322 4323 if (bp->hwrm_spec_code < 0x10601) 4324 return 0; 4325 4326 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 4327 req.fid = cpu_to_le16(fid); 4328 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4329 if (!rc) 4330 *tx_rings = le16_to_cpu(resp->alloc_tx_rings); 4331 4332 return rc; 4333 } 4334 4335 static int bnxt_hwrm_reserve_tx_rings(struct bnxt *bp, int *tx_rings) 4336 { 4337 struct hwrm_func_cfg_input req = {0}; 4338 int rc; 4339 4340 if (bp->hwrm_spec_code < 0x10601) 4341 return 0; 4342 4343 if (BNXT_VF(bp)) 4344 return 0; 4345 4346 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 4347 req.fid = cpu_to_le16(0xffff); 4348 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS); 4349 req.num_tx_rings = cpu_to_le16(*tx_rings); 4350 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4351 if (rc) 4352 return rc; 4353 4354 mutex_lock(&bp->hwrm_cmd_lock); 4355 rc = __bnxt_hwrm_get_tx_rings(bp, 0xffff, tx_rings); 4356 mutex_unlock(&bp->hwrm_cmd_lock); 4357 return rc; 4358 } 4359 4360 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, u32 max_bufs, 4361 u32 buf_tmrs, u16 flags, 4362 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req) 4363 { 4364 req->flags = cpu_to_le16(flags); 4365 req->num_cmpl_dma_aggr = cpu_to_le16((u16)max_bufs); 4366 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(max_bufs >> 16); 4367 req->cmpl_aggr_dma_tmr = cpu_to_le16((u16)buf_tmrs); 4368 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmrs >> 16); 4369 /* Minimum time between 2 interrupts set to buf_tmr x 2 */ 4370 req->int_lat_tmr_min = cpu_to_le16((u16)buf_tmrs * 2); 4371 req->int_lat_tmr_max = cpu_to_le16((u16)buf_tmrs * 4); 4372 req->num_cmpl_aggr_int = cpu_to_le16((u16)max_bufs * 4); 4373 } 4374 4375 int bnxt_hwrm_set_coal(struct bnxt *bp) 4376 { 4377 int i, rc = 0; 4378 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}, 4379 req_tx = {0}, *req; 4380 u16 max_buf, max_buf_irq; 4381 u16 buf_tmr, buf_tmr_irq; 4382 u32 flags; 4383 4384 bnxt_hwrm_cmd_hdr_init(bp, &req_rx, 4385 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 4386 bnxt_hwrm_cmd_hdr_init(bp, &req_tx, 4387 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 4388 4389 /* Each rx completion (2 records) should be DMAed immediately. 4390 * DMA 1/4 of the completion buffers at a time. 4391 */ 4392 max_buf = min_t(u16, bp->rx_coal_bufs / 4, 2); 4393 /* max_buf must not be zero */ 4394 max_buf = clamp_t(u16, max_buf, 1, 63); 4395 max_buf_irq = clamp_t(u16, bp->rx_coal_bufs_irq, 1, 63); 4396 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks); 4397 /* buf timer set to 1/4 of interrupt timer */ 4398 buf_tmr = max_t(u16, buf_tmr / 4, 1); 4399 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks_irq); 4400 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1); 4401 4402 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 4403 4404 /* RING_IDLE generates more IRQs for lower latency. Enable it only 4405 * if coal_ticks is less than 25 us. 4406 */ 4407 if (bp->rx_coal_ticks < 25) 4408 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE; 4409 4410 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf, 4411 buf_tmr_irq << 16 | buf_tmr, flags, &req_rx); 4412 4413 /* max_buf must not be zero */ 4414 max_buf = clamp_t(u16, bp->tx_coal_bufs, 1, 63); 4415 max_buf_irq = clamp_t(u16, bp->tx_coal_bufs_irq, 1, 63); 4416 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks); 4417 /* buf timer set to 1/4 of interrupt timer */ 4418 buf_tmr = max_t(u16, buf_tmr / 4, 1); 4419 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks_irq); 4420 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1); 4421 4422 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 4423 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf, 4424 buf_tmr_irq << 16 | buf_tmr, flags, &req_tx); 4425 4426 mutex_lock(&bp->hwrm_cmd_lock); 4427 for (i = 0; i < bp->cp_nr_rings; i++) { 4428 struct bnxt_napi *bnapi = bp->bnapi[i]; 4429 4430 req = &req_rx; 4431 if (!bnapi->rx_ring) 4432 req = &req_tx; 4433 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id); 4434 4435 rc = _hwrm_send_message(bp, req, sizeof(*req), 4436 HWRM_CMD_TIMEOUT); 4437 if (rc) 4438 break; 4439 } 4440 mutex_unlock(&bp->hwrm_cmd_lock); 4441 return rc; 4442 } 4443 4444 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp) 4445 { 4446 int rc = 0, i; 4447 struct hwrm_stat_ctx_free_input req = {0}; 4448 4449 if (!bp->bnapi) 4450 return 0; 4451 4452 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 4453 return 0; 4454 4455 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1); 4456 4457 mutex_lock(&bp->hwrm_cmd_lock); 4458 for (i = 0; i < bp->cp_nr_rings; i++) { 4459 struct bnxt_napi *bnapi = bp->bnapi[i]; 4460 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4461 4462 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) { 4463 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id); 4464 4465 rc = _hwrm_send_message(bp, &req, sizeof(req), 4466 HWRM_CMD_TIMEOUT); 4467 if (rc) 4468 break; 4469 4470 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 4471 } 4472 } 4473 mutex_unlock(&bp->hwrm_cmd_lock); 4474 return rc; 4475 } 4476 4477 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp) 4478 { 4479 int rc = 0, i; 4480 struct hwrm_stat_ctx_alloc_input req = {0}; 4481 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4482 4483 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 4484 return 0; 4485 4486 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1); 4487 4488 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000); 4489 4490 mutex_lock(&bp->hwrm_cmd_lock); 4491 for (i = 0; i < bp->cp_nr_rings; i++) { 4492 struct bnxt_napi *bnapi = bp->bnapi[i]; 4493 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 4494 4495 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map); 4496 4497 rc = _hwrm_send_message(bp, &req, sizeof(req), 4498 HWRM_CMD_TIMEOUT); 4499 if (rc) 4500 break; 4501 4502 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id); 4503 4504 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id; 4505 } 4506 mutex_unlock(&bp->hwrm_cmd_lock); 4507 return rc; 4508 } 4509 4510 static int bnxt_hwrm_func_qcfg(struct bnxt *bp) 4511 { 4512 struct hwrm_func_qcfg_input req = {0}; 4513 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 4514 int rc; 4515 4516 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 4517 req.fid = cpu_to_le16(0xffff); 4518 mutex_lock(&bp->hwrm_cmd_lock); 4519 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4520 if (rc) 4521 goto func_qcfg_exit; 4522 4523 #ifdef CONFIG_BNXT_SRIOV 4524 if (BNXT_VF(bp)) { 4525 struct bnxt_vf_info *vf = &bp->vf; 4526 4527 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK; 4528 } 4529 #endif 4530 if (BNXT_PF(bp)) { 4531 u16 flags = le16_to_cpu(resp->flags); 4532 4533 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED | 4534 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) 4535 bp->flags |= BNXT_FLAG_FW_LLDP_AGENT; 4536 if (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST) 4537 bp->flags |= BNXT_FLAG_MULTI_HOST; 4538 } 4539 4540 switch (resp->port_partition_type) { 4541 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0: 4542 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5: 4543 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0: 4544 bp->port_partition_type = resp->port_partition_type; 4545 break; 4546 } 4547 4548 func_qcfg_exit: 4549 mutex_unlock(&bp->hwrm_cmd_lock); 4550 return rc; 4551 } 4552 4553 static int bnxt_hwrm_func_qcaps(struct bnxt *bp) 4554 { 4555 int rc = 0; 4556 struct hwrm_func_qcaps_input req = {0}; 4557 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 4558 4559 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1); 4560 req.fid = cpu_to_le16(0xffff); 4561 4562 mutex_lock(&bp->hwrm_cmd_lock); 4563 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4564 if (rc) 4565 goto hwrm_func_qcaps_exit; 4566 4567 if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)) 4568 bp->flags |= BNXT_FLAG_ROCEV1_CAP; 4569 if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)) 4570 bp->flags |= BNXT_FLAG_ROCEV2_CAP; 4571 4572 bp->tx_push_thresh = 0; 4573 if (resp->flags & 4574 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)) 4575 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH; 4576 4577 if (BNXT_PF(bp)) { 4578 struct bnxt_pf_info *pf = &bp->pf; 4579 4580 pf->fw_fid = le16_to_cpu(resp->fid); 4581 pf->port_id = le16_to_cpu(resp->port_id); 4582 bp->dev->dev_port = pf->port_id; 4583 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN); 4584 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN); 4585 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 4586 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 4587 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 4588 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 4589 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); 4590 if (!pf->max_hw_ring_grps) 4591 pf->max_hw_ring_grps = pf->max_tx_rings; 4592 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 4593 pf->max_vnics = le16_to_cpu(resp->max_vnics); 4594 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 4595 pf->first_vf_id = le16_to_cpu(resp->first_vf_id); 4596 pf->max_vfs = le16_to_cpu(resp->max_vfs); 4597 pf->max_encap_records = le32_to_cpu(resp->max_encap_records); 4598 pf->max_decap_records = le32_to_cpu(resp->max_decap_records); 4599 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows); 4600 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows); 4601 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows); 4602 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows); 4603 if (resp->flags & 4604 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)) 4605 bp->flags |= BNXT_FLAG_WOL_CAP; 4606 } else { 4607 #ifdef CONFIG_BNXT_SRIOV 4608 struct bnxt_vf_info *vf = &bp->vf; 4609 4610 vf->fw_fid = le16_to_cpu(resp->fid); 4611 4612 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 4613 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 4614 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 4615 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 4616 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); 4617 if (!vf->max_hw_ring_grps) 4618 vf->max_hw_ring_grps = vf->max_tx_rings; 4619 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 4620 vf->max_vnics = le16_to_cpu(resp->max_vnics); 4621 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 4622 4623 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN); 4624 mutex_unlock(&bp->hwrm_cmd_lock); 4625 4626 if (is_valid_ether_addr(vf->mac_addr)) { 4627 /* overwrite netdev dev_adr with admin VF MAC */ 4628 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN); 4629 } else { 4630 eth_hw_addr_random(bp->dev); 4631 rc = bnxt_approve_mac(bp, bp->dev->dev_addr); 4632 } 4633 return rc; 4634 #endif 4635 } 4636 4637 hwrm_func_qcaps_exit: 4638 mutex_unlock(&bp->hwrm_cmd_lock); 4639 return rc; 4640 } 4641 4642 static int bnxt_hwrm_func_reset(struct bnxt *bp) 4643 { 4644 struct hwrm_func_reset_input req = {0}; 4645 4646 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1); 4647 req.enables = 0; 4648 4649 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT); 4650 } 4651 4652 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp) 4653 { 4654 int rc = 0; 4655 struct hwrm_queue_qportcfg_input req = {0}; 4656 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr; 4657 u8 i, *qptr; 4658 4659 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1); 4660 4661 mutex_lock(&bp->hwrm_cmd_lock); 4662 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4663 if (rc) 4664 goto qportcfg_exit; 4665 4666 if (!resp->max_configurable_queues) { 4667 rc = -EINVAL; 4668 goto qportcfg_exit; 4669 } 4670 bp->max_tc = resp->max_configurable_queues; 4671 bp->max_lltc = resp->max_configurable_lossless_queues; 4672 if (bp->max_tc > BNXT_MAX_QUEUE) 4673 bp->max_tc = BNXT_MAX_QUEUE; 4674 4675 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG) 4676 bp->max_tc = 1; 4677 4678 if (bp->max_lltc > bp->max_tc) 4679 bp->max_lltc = bp->max_tc; 4680 4681 qptr = &resp->queue_id0; 4682 for (i = 0; i < bp->max_tc; i++) { 4683 bp->q_info[i].queue_id = *qptr++; 4684 bp->q_info[i].queue_profile = *qptr++; 4685 } 4686 4687 qportcfg_exit: 4688 mutex_unlock(&bp->hwrm_cmd_lock); 4689 return rc; 4690 } 4691 4692 static int bnxt_hwrm_ver_get(struct bnxt *bp) 4693 { 4694 int rc; 4695 struct hwrm_ver_get_input req = {0}; 4696 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr; 4697 4698 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN; 4699 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1); 4700 req.hwrm_intf_maj = HWRM_VERSION_MAJOR; 4701 req.hwrm_intf_min = HWRM_VERSION_MINOR; 4702 req.hwrm_intf_upd = HWRM_VERSION_UPDATE; 4703 mutex_lock(&bp->hwrm_cmd_lock); 4704 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4705 if (rc) 4706 goto hwrm_ver_get_exit; 4707 4708 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output)); 4709 4710 bp->hwrm_spec_code = resp->hwrm_intf_maj << 16 | 4711 resp->hwrm_intf_min << 8 | resp->hwrm_intf_upd; 4712 if (resp->hwrm_intf_maj < 1) { 4713 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n", 4714 resp->hwrm_intf_maj, resp->hwrm_intf_min, 4715 resp->hwrm_intf_upd); 4716 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n"); 4717 } 4718 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d/%d.%d.%d", 4719 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld, 4720 resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd); 4721 4722 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout); 4723 if (!bp->hwrm_cmd_timeout) 4724 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; 4725 4726 if (resp->hwrm_intf_maj >= 1) 4727 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len); 4728 4729 bp->chip_num = le16_to_cpu(resp->chip_num); 4730 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev && 4731 !resp->chip_metal) 4732 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0; 4733 4734 hwrm_ver_get_exit: 4735 mutex_unlock(&bp->hwrm_cmd_lock); 4736 return rc; 4737 } 4738 4739 int bnxt_hwrm_fw_set_time(struct bnxt *bp) 4740 { 4741 #if IS_ENABLED(CONFIG_RTC_LIB) 4742 struct hwrm_fw_set_time_input req = {0}; 4743 struct rtc_time tm; 4744 struct timeval tv; 4745 4746 if (bp->hwrm_spec_code < 0x10400) 4747 return -EOPNOTSUPP; 4748 4749 do_gettimeofday(&tv); 4750 rtc_time_to_tm(tv.tv_sec, &tm); 4751 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1); 4752 req.year = cpu_to_le16(1900 + tm.tm_year); 4753 req.month = 1 + tm.tm_mon; 4754 req.day = tm.tm_mday; 4755 req.hour = tm.tm_hour; 4756 req.minute = tm.tm_min; 4757 req.second = tm.tm_sec; 4758 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4759 #else 4760 return -EOPNOTSUPP; 4761 #endif 4762 } 4763 4764 static int bnxt_hwrm_port_qstats(struct bnxt *bp) 4765 { 4766 int rc; 4767 struct bnxt_pf_info *pf = &bp->pf; 4768 struct hwrm_port_qstats_input req = {0}; 4769 4770 if (!(bp->flags & BNXT_FLAG_PORT_STATS)) 4771 return 0; 4772 4773 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1); 4774 req.port_id = cpu_to_le16(pf->port_id); 4775 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map); 4776 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map); 4777 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4778 return rc; 4779 } 4780 4781 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp) 4782 { 4783 if (bp->vxlan_port_cnt) { 4784 bnxt_hwrm_tunnel_dst_port_free( 4785 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 4786 } 4787 bp->vxlan_port_cnt = 0; 4788 if (bp->nge_port_cnt) { 4789 bnxt_hwrm_tunnel_dst_port_free( 4790 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 4791 } 4792 bp->nge_port_cnt = 0; 4793 } 4794 4795 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa) 4796 { 4797 int rc, i; 4798 u32 tpa_flags = 0; 4799 4800 if (set_tpa) 4801 tpa_flags = bp->flags & BNXT_FLAG_TPA; 4802 for (i = 0; i < bp->nr_vnics; i++) { 4803 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags); 4804 if (rc) { 4805 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n", 4806 i, rc); 4807 return rc; 4808 } 4809 } 4810 return 0; 4811 } 4812 4813 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp) 4814 { 4815 int i; 4816 4817 for (i = 0; i < bp->nr_vnics; i++) 4818 bnxt_hwrm_vnic_set_rss(bp, i, false); 4819 } 4820 4821 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path, 4822 bool irq_re_init) 4823 { 4824 if (bp->vnic_info) { 4825 bnxt_hwrm_clear_vnic_filter(bp); 4826 /* clear all RSS setting before free vnic ctx */ 4827 bnxt_hwrm_clear_vnic_rss(bp); 4828 bnxt_hwrm_vnic_ctx_free(bp); 4829 /* before free the vnic, undo the vnic tpa settings */ 4830 if (bp->flags & BNXT_FLAG_TPA) 4831 bnxt_set_tpa(bp, false); 4832 bnxt_hwrm_vnic_free(bp); 4833 } 4834 bnxt_hwrm_ring_free(bp, close_path); 4835 bnxt_hwrm_ring_grp_free(bp); 4836 if (irq_re_init) { 4837 bnxt_hwrm_stat_ctx_free(bp); 4838 bnxt_hwrm_free_tunnel_ports(bp); 4839 } 4840 } 4841 4842 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) 4843 { 4844 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4845 int rc; 4846 4847 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) 4848 goto skip_rss_ctx; 4849 4850 /* allocate context for vnic */ 4851 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0); 4852 if (rc) { 4853 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 4854 vnic_id, rc); 4855 goto vnic_setup_err; 4856 } 4857 bp->rsscos_nr_ctxs++; 4858 4859 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 4860 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1); 4861 if (rc) { 4862 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n", 4863 vnic_id, rc); 4864 goto vnic_setup_err; 4865 } 4866 bp->rsscos_nr_ctxs++; 4867 } 4868 4869 skip_rss_ctx: 4870 /* configure default vnic, ring grp */ 4871 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); 4872 if (rc) { 4873 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", 4874 vnic_id, rc); 4875 goto vnic_setup_err; 4876 } 4877 4878 /* Enable RSS hashing on vnic */ 4879 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true); 4880 if (rc) { 4881 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n", 4882 vnic_id, rc); 4883 goto vnic_setup_err; 4884 } 4885 4886 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 4887 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); 4888 if (rc) { 4889 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", 4890 vnic_id, rc); 4891 } 4892 } 4893 4894 vnic_setup_err: 4895 return rc; 4896 } 4897 4898 static int bnxt_alloc_rfs_vnics(struct bnxt *bp) 4899 { 4900 #ifdef CONFIG_RFS_ACCEL 4901 int i, rc = 0; 4902 4903 for (i = 0; i < bp->rx_nr_rings; i++) { 4904 struct bnxt_vnic_info *vnic; 4905 u16 vnic_id = i + 1; 4906 u16 ring_id = i; 4907 4908 if (vnic_id >= bp->nr_vnics) 4909 break; 4910 4911 vnic = &bp->vnic_info[vnic_id]; 4912 vnic->flags |= BNXT_VNIC_RFS_FLAG; 4913 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 4914 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG; 4915 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1); 4916 if (rc) { 4917 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 4918 vnic_id, rc); 4919 break; 4920 } 4921 rc = bnxt_setup_vnic(bp, vnic_id); 4922 if (rc) 4923 break; 4924 } 4925 return rc; 4926 #else 4927 return 0; 4928 #endif 4929 } 4930 4931 /* Allow PF and VF with default VLAN to be in promiscuous mode */ 4932 static bool bnxt_promisc_ok(struct bnxt *bp) 4933 { 4934 #ifdef CONFIG_BNXT_SRIOV 4935 if (BNXT_VF(bp) && !bp->vf.vlan) 4936 return false; 4937 #endif 4938 return true; 4939 } 4940 4941 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp) 4942 { 4943 unsigned int rc = 0; 4944 4945 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1); 4946 if (rc) { 4947 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 4948 rc); 4949 return rc; 4950 } 4951 4952 rc = bnxt_hwrm_vnic_cfg(bp, 1); 4953 if (rc) { 4954 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 4955 rc); 4956 return rc; 4957 } 4958 return rc; 4959 } 4960 4961 static int bnxt_cfg_rx_mode(struct bnxt *); 4962 static bool bnxt_mc_list_updated(struct bnxt *, u32 *); 4963 4964 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init) 4965 { 4966 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 4967 int rc = 0; 4968 unsigned int rx_nr_rings = bp->rx_nr_rings; 4969 4970 if (irq_re_init) { 4971 rc = bnxt_hwrm_stat_ctx_alloc(bp); 4972 if (rc) { 4973 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n", 4974 rc); 4975 goto err_out; 4976 } 4977 } 4978 4979 rc = bnxt_hwrm_ring_alloc(bp); 4980 if (rc) { 4981 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc); 4982 goto err_out; 4983 } 4984 4985 rc = bnxt_hwrm_ring_grp_alloc(bp); 4986 if (rc) { 4987 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc); 4988 goto err_out; 4989 } 4990 4991 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 4992 rx_nr_rings--; 4993 4994 /* default vnic 0 */ 4995 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings); 4996 if (rc) { 4997 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc); 4998 goto err_out; 4999 } 5000 5001 rc = bnxt_setup_vnic(bp, 0); 5002 if (rc) 5003 goto err_out; 5004 5005 if (bp->flags & BNXT_FLAG_RFS) { 5006 rc = bnxt_alloc_rfs_vnics(bp); 5007 if (rc) 5008 goto err_out; 5009 } 5010 5011 if (bp->flags & BNXT_FLAG_TPA) { 5012 rc = bnxt_set_tpa(bp, true); 5013 if (rc) 5014 goto err_out; 5015 } 5016 5017 if (BNXT_VF(bp)) 5018 bnxt_update_vf_mac(bp); 5019 5020 /* Filter for default vnic 0 */ 5021 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr); 5022 if (rc) { 5023 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc); 5024 goto err_out; 5025 } 5026 vnic->uc_filter_count = 1; 5027 5028 vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 5029 5030 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) 5031 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 5032 5033 if (bp->dev->flags & IFF_ALLMULTI) { 5034 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 5035 vnic->mc_list_count = 0; 5036 } else { 5037 u32 mask = 0; 5038 5039 bnxt_mc_list_updated(bp, &mask); 5040 vnic->rx_mask |= mask; 5041 } 5042 5043 rc = bnxt_cfg_rx_mode(bp); 5044 if (rc) 5045 goto err_out; 5046 5047 rc = bnxt_hwrm_set_coal(bp); 5048 if (rc) 5049 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n", 5050 rc); 5051 5052 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 5053 rc = bnxt_setup_nitroa0_vnic(bp); 5054 if (rc) 5055 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n", 5056 rc); 5057 } 5058 5059 if (BNXT_VF(bp)) { 5060 bnxt_hwrm_func_qcfg(bp); 5061 netdev_update_features(bp->dev); 5062 } 5063 5064 return 0; 5065 5066 err_out: 5067 bnxt_hwrm_resource_free(bp, 0, true); 5068 5069 return rc; 5070 } 5071 5072 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init) 5073 { 5074 bnxt_hwrm_resource_free(bp, 1, irq_re_init); 5075 return 0; 5076 } 5077 5078 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init) 5079 { 5080 bnxt_init_cp_rings(bp); 5081 bnxt_init_rx_rings(bp); 5082 bnxt_init_tx_rings(bp); 5083 bnxt_init_ring_grps(bp, irq_re_init); 5084 bnxt_init_vnics(bp); 5085 5086 return bnxt_init_chip(bp, irq_re_init); 5087 } 5088 5089 static int bnxt_set_real_num_queues(struct bnxt *bp) 5090 { 5091 int rc; 5092 struct net_device *dev = bp->dev; 5093 5094 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings - 5095 bp->tx_nr_rings_xdp); 5096 if (rc) 5097 return rc; 5098 5099 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings); 5100 if (rc) 5101 return rc; 5102 5103 #ifdef CONFIG_RFS_ACCEL 5104 if (bp->flags & BNXT_FLAG_RFS) 5105 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings); 5106 #endif 5107 5108 return rc; 5109 } 5110 5111 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 5112 bool shared) 5113 { 5114 int _rx = *rx, _tx = *tx; 5115 5116 if (shared) { 5117 *rx = min_t(int, _rx, max); 5118 *tx = min_t(int, _tx, max); 5119 } else { 5120 if (max < 2) 5121 return -ENOMEM; 5122 5123 while (_rx + _tx > max) { 5124 if (_rx > _tx && _rx > 1) 5125 _rx--; 5126 else if (_tx > 1) 5127 _tx--; 5128 } 5129 *rx = _rx; 5130 *tx = _tx; 5131 } 5132 return 0; 5133 } 5134 5135 static void bnxt_setup_msix(struct bnxt *bp) 5136 { 5137 const int len = sizeof(bp->irq_tbl[0].name); 5138 struct net_device *dev = bp->dev; 5139 int tcs, i; 5140 5141 tcs = netdev_get_num_tc(dev); 5142 if (tcs > 1) { 5143 int i, off, count; 5144 5145 for (i = 0; i < tcs; i++) { 5146 count = bp->tx_nr_rings_per_tc; 5147 off = i * count; 5148 netdev_set_tc_queue(dev, i, count, off); 5149 } 5150 } 5151 5152 for (i = 0; i < bp->cp_nr_rings; i++) { 5153 char *attr; 5154 5155 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 5156 attr = "TxRx"; 5157 else if (i < bp->rx_nr_rings) 5158 attr = "rx"; 5159 else 5160 attr = "tx"; 5161 5162 snprintf(bp->irq_tbl[i].name, len, "%s-%s-%d", dev->name, attr, 5163 i); 5164 bp->irq_tbl[i].handler = bnxt_msix; 5165 } 5166 } 5167 5168 static void bnxt_setup_inta(struct bnxt *bp) 5169 { 5170 const int len = sizeof(bp->irq_tbl[0].name); 5171 5172 if (netdev_get_num_tc(bp->dev)) 5173 netdev_reset_tc(bp->dev); 5174 5175 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx", 5176 0); 5177 bp->irq_tbl[0].handler = bnxt_inta; 5178 } 5179 5180 static int bnxt_setup_int_mode(struct bnxt *bp) 5181 { 5182 int rc; 5183 5184 if (bp->flags & BNXT_FLAG_USING_MSIX) 5185 bnxt_setup_msix(bp); 5186 else 5187 bnxt_setup_inta(bp); 5188 5189 rc = bnxt_set_real_num_queues(bp); 5190 return rc; 5191 } 5192 5193 #ifdef CONFIG_RFS_ACCEL 5194 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp) 5195 { 5196 #if defined(CONFIG_BNXT_SRIOV) 5197 if (BNXT_VF(bp)) 5198 return bp->vf.max_rsscos_ctxs; 5199 #endif 5200 return bp->pf.max_rsscos_ctxs; 5201 } 5202 5203 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp) 5204 { 5205 #if defined(CONFIG_BNXT_SRIOV) 5206 if (BNXT_VF(bp)) 5207 return bp->vf.max_vnics; 5208 #endif 5209 return bp->pf.max_vnics; 5210 } 5211 #endif 5212 5213 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp) 5214 { 5215 #if defined(CONFIG_BNXT_SRIOV) 5216 if (BNXT_VF(bp)) 5217 return bp->vf.max_stat_ctxs; 5218 #endif 5219 return bp->pf.max_stat_ctxs; 5220 } 5221 5222 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max) 5223 { 5224 #if defined(CONFIG_BNXT_SRIOV) 5225 if (BNXT_VF(bp)) 5226 bp->vf.max_stat_ctxs = max; 5227 else 5228 #endif 5229 bp->pf.max_stat_ctxs = max; 5230 } 5231 5232 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp) 5233 { 5234 #if defined(CONFIG_BNXT_SRIOV) 5235 if (BNXT_VF(bp)) 5236 return bp->vf.max_cp_rings; 5237 #endif 5238 return bp->pf.max_cp_rings; 5239 } 5240 5241 void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max) 5242 { 5243 #if defined(CONFIG_BNXT_SRIOV) 5244 if (BNXT_VF(bp)) 5245 bp->vf.max_cp_rings = max; 5246 else 5247 #endif 5248 bp->pf.max_cp_rings = max; 5249 } 5250 5251 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp) 5252 { 5253 #if defined(CONFIG_BNXT_SRIOV) 5254 if (BNXT_VF(bp)) 5255 return min_t(unsigned int, bp->vf.max_irqs, 5256 bp->vf.max_cp_rings); 5257 #endif 5258 return min_t(unsigned int, bp->pf.max_irqs, bp->pf.max_cp_rings); 5259 } 5260 5261 void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs) 5262 { 5263 #if defined(CONFIG_BNXT_SRIOV) 5264 if (BNXT_VF(bp)) 5265 bp->vf.max_irqs = max_irqs; 5266 else 5267 #endif 5268 bp->pf.max_irqs = max_irqs; 5269 } 5270 5271 static int bnxt_init_msix(struct bnxt *bp) 5272 { 5273 int i, total_vecs, rc = 0, min = 1; 5274 struct msix_entry *msix_ent; 5275 5276 total_vecs = bnxt_get_max_func_irqs(bp); 5277 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL); 5278 if (!msix_ent) 5279 return -ENOMEM; 5280 5281 for (i = 0; i < total_vecs; i++) { 5282 msix_ent[i].entry = i; 5283 msix_ent[i].vector = 0; 5284 } 5285 5286 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 5287 min = 2; 5288 5289 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs); 5290 if (total_vecs < 0) { 5291 rc = -ENODEV; 5292 goto msix_setup_exit; 5293 } 5294 5295 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL); 5296 if (bp->irq_tbl) { 5297 for (i = 0; i < total_vecs; i++) 5298 bp->irq_tbl[i].vector = msix_ent[i].vector; 5299 5300 bp->total_irqs = total_vecs; 5301 /* Trim rings based upon num of vectors allocated */ 5302 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings, 5303 total_vecs, min == 1); 5304 if (rc) 5305 goto msix_setup_exit; 5306 5307 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 5308 bp->cp_nr_rings = (min == 1) ? 5309 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 5310 bp->tx_nr_rings + bp->rx_nr_rings; 5311 5312 } else { 5313 rc = -ENOMEM; 5314 goto msix_setup_exit; 5315 } 5316 bp->flags |= BNXT_FLAG_USING_MSIX; 5317 kfree(msix_ent); 5318 return 0; 5319 5320 msix_setup_exit: 5321 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc); 5322 kfree(bp->irq_tbl); 5323 bp->irq_tbl = NULL; 5324 pci_disable_msix(bp->pdev); 5325 kfree(msix_ent); 5326 return rc; 5327 } 5328 5329 static int bnxt_init_inta(struct bnxt *bp) 5330 { 5331 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL); 5332 if (!bp->irq_tbl) 5333 return -ENOMEM; 5334 5335 bp->total_irqs = 1; 5336 bp->rx_nr_rings = 1; 5337 bp->tx_nr_rings = 1; 5338 bp->cp_nr_rings = 1; 5339 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 5340 bp->flags |= BNXT_FLAG_SHARED_RINGS; 5341 bp->irq_tbl[0].vector = bp->pdev->irq; 5342 return 0; 5343 } 5344 5345 static int bnxt_init_int_mode(struct bnxt *bp) 5346 { 5347 int rc = 0; 5348 5349 if (bp->flags & BNXT_FLAG_MSIX_CAP) 5350 rc = bnxt_init_msix(bp); 5351 5352 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) { 5353 /* fallback to INTA */ 5354 rc = bnxt_init_inta(bp); 5355 } 5356 return rc; 5357 } 5358 5359 static void bnxt_clear_int_mode(struct bnxt *bp) 5360 { 5361 if (bp->flags & BNXT_FLAG_USING_MSIX) 5362 pci_disable_msix(bp->pdev); 5363 5364 kfree(bp->irq_tbl); 5365 bp->irq_tbl = NULL; 5366 bp->flags &= ~BNXT_FLAG_USING_MSIX; 5367 } 5368 5369 static void bnxt_free_irq(struct bnxt *bp) 5370 { 5371 struct bnxt_irq *irq; 5372 int i; 5373 5374 #ifdef CONFIG_RFS_ACCEL 5375 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap); 5376 bp->dev->rx_cpu_rmap = NULL; 5377 #endif 5378 if (!bp->irq_tbl) 5379 return; 5380 5381 for (i = 0; i < bp->cp_nr_rings; i++) { 5382 irq = &bp->irq_tbl[i]; 5383 if (irq->requested) 5384 free_irq(irq->vector, bp->bnapi[i]); 5385 irq->requested = 0; 5386 } 5387 } 5388 5389 static int bnxt_request_irq(struct bnxt *bp) 5390 { 5391 int i, j, rc = 0; 5392 unsigned long flags = 0; 5393 #ifdef CONFIG_RFS_ACCEL 5394 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap; 5395 #endif 5396 5397 if (!(bp->flags & BNXT_FLAG_USING_MSIX)) 5398 flags = IRQF_SHARED; 5399 5400 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) { 5401 struct bnxt_irq *irq = &bp->irq_tbl[i]; 5402 #ifdef CONFIG_RFS_ACCEL 5403 if (rmap && bp->bnapi[i]->rx_ring) { 5404 rc = irq_cpu_rmap_add(rmap, irq->vector); 5405 if (rc) 5406 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n", 5407 j); 5408 j++; 5409 } 5410 #endif 5411 rc = request_irq(irq->vector, irq->handler, flags, irq->name, 5412 bp->bnapi[i]); 5413 if (rc) 5414 break; 5415 5416 irq->requested = 1; 5417 } 5418 return rc; 5419 } 5420 5421 static void bnxt_del_napi(struct bnxt *bp) 5422 { 5423 int i; 5424 5425 if (!bp->bnapi) 5426 return; 5427 5428 for (i = 0; i < bp->cp_nr_rings; i++) { 5429 struct bnxt_napi *bnapi = bp->bnapi[i]; 5430 5431 napi_hash_del(&bnapi->napi); 5432 netif_napi_del(&bnapi->napi); 5433 } 5434 /* We called napi_hash_del() before netif_napi_del(), we need 5435 * to respect an RCU grace period before freeing napi structures. 5436 */ 5437 synchronize_net(); 5438 } 5439 5440 static void bnxt_init_napi(struct bnxt *bp) 5441 { 5442 int i; 5443 unsigned int cp_nr_rings = bp->cp_nr_rings; 5444 struct bnxt_napi *bnapi; 5445 5446 if (bp->flags & BNXT_FLAG_USING_MSIX) { 5447 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 5448 cp_nr_rings--; 5449 for (i = 0; i < cp_nr_rings; i++) { 5450 bnapi = bp->bnapi[i]; 5451 netif_napi_add(bp->dev, &bnapi->napi, 5452 bnxt_poll, 64); 5453 } 5454 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 5455 bnapi = bp->bnapi[cp_nr_rings]; 5456 netif_napi_add(bp->dev, &bnapi->napi, 5457 bnxt_poll_nitroa0, 64); 5458 } 5459 } else { 5460 bnapi = bp->bnapi[0]; 5461 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64); 5462 } 5463 } 5464 5465 static void bnxt_disable_napi(struct bnxt *bp) 5466 { 5467 int i; 5468 5469 if (!bp->bnapi) 5470 return; 5471 5472 for (i = 0; i < bp->cp_nr_rings; i++) 5473 napi_disable(&bp->bnapi[i]->napi); 5474 } 5475 5476 static void bnxt_enable_napi(struct bnxt *bp) 5477 { 5478 int i; 5479 5480 for (i = 0; i < bp->cp_nr_rings; i++) { 5481 bp->bnapi[i]->in_reset = false; 5482 napi_enable(&bp->bnapi[i]->napi); 5483 } 5484 } 5485 5486 void bnxt_tx_disable(struct bnxt *bp) 5487 { 5488 int i; 5489 struct bnxt_tx_ring_info *txr; 5490 struct netdev_queue *txq; 5491 5492 if (bp->tx_ring) { 5493 for (i = 0; i < bp->tx_nr_rings; i++) { 5494 txr = &bp->tx_ring[i]; 5495 txq = netdev_get_tx_queue(bp->dev, i); 5496 txr->dev_state = BNXT_DEV_STATE_CLOSING; 5497 } 5498 } 5499 /* Stop all TX queues */ 5500 netif_tx_disable(bp->dev); 5501 netif_carrier_off(bp->dev); 5502 } 5503 5504 void bnxt_tx_enable(struct bnxt *bp) 5505 { 5506 int i; 5507 struct bnxt_tx_ring_info *txr; 5508 struct netdev_queue *txq; 5509 5510 for (i = 0; i < bp->tx_nr_rings; i++) { 5511 txr = &bp->tx_ring[i]; 5512 txq = netdev_get_tx_queue(bp->dev, i); 5513 txr->dev_state = 0; 5514 } 5515 netif_tx_wake_all_queues(bp->dev); 5516 if (bp->link_info.link_up) 5517 netif_carrier_on(bp->dev); 5518 } 5519 5520 static void bnxt_report_link(struct bnxt *bp) 5521 { 5522 if (bp->link_info.link_up) { 5523 const char *duplex; 5524 const char *flow_ctrl; 5525 u32 speed; 5526 u16 fec; 5527 5528 netif_carrier_on(bp->dev); 5529 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL) 5530 duplex = "full"; 5531 else 5532 duplex = "half"; 5533 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH) 5534 flow_ctrl = "ON - receive & transmit"; 5535 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX) 5536 flow_ctrl = "ON - transmit"; 5537 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX) 5538 flow_ctrl = "ON - receive"; 5539 else 5540 flow_ctrl = "none"; 5541 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed); 5542 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n", 5543 speed, duplex, flow_ctrl); 5544 if (bp->flags & BNXT_FLAG_EEE_CAP) 5545 netdev_info(bp->dev, "EEE is %s\n", 5546 bp->eee.eee_active ? "active" : 5547 "not active"); 5548 fec = bp->link_info.fec_cfg; 5549 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED)) 5550 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n", 5551 (fec & BNXT_FEC_AUTONEG) ? "on" : "off", 5552 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" : 5553 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None"); 5554 } else { 5555 netif_carrier_off(bp->dev); 5556 netdev_err(bp->dev, "NIC Link is Down\n"); 5557 } 5558 } 5559 5560 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp) 5561 { 5562 int rc = 0; 5563 struct hwrm_port_phy_qcaps_input req = {0}; 5564 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 5565 struct bnxt_link_info *link_info = &bp->link_info; 5566 5567 if (bp->hwrm_spec_code < 0x10201) 5568 return 0; 5569 5570 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1); 5571 5572 mutex_lock(&bp->hwrm_cmd_lock); 5573 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5574 if (rc) 5575 goto hwrm_phy_qcaps_exit; 5576 5577 if (resp->eee_supported & PORT_PHY_QCAPS_RESP_EEE_SUPPORTED) { 5578 struct ethtool_eee *eee = &bp->eee; 5579 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode); 5580 5581 bp->flags |= BNXT_FLAG_EEE_CAP; 5582 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 5583 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) & 5584 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK; 5585 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) & 5586 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK; 5587 } 5588 if (resp->supported_speeds_auto_mode) 5589 link_info->support_auto_speeds = 5590 le16_to_cpu(resp->supported_speeds_auto_mode); 5591 5592 hwrm_phy_qcaps_exit: 5593 mutex_unlock(&bp->hwrm_cmd_lock); 5594 return rc; 5595 } 5596 5597 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state) 5598 { 5599 int rc = 0; 5600 struct bnxt_link_info *link_info = &bp->link_info; 5601 struct hwrm_port_phy_qcfg_input req = {0}; 5602 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 5603 u8 link_up = link_info->link_up; 5604 u16 diff; 5605 5606 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1); 5607 5608 mutex_lock(&bp->hwrm_cmd_lock); 5609 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5610 if (rc) { 5611 mutex_unlock(&bp->hwrm_cmd_lock); 5612 return rc; 5613 } 5614 5615 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp)); 5616 link_info->phy_link_status = resp->link; 5617 link_info->duplex = resp->duplex; 5618 link_info->pause = resp->pause; 5619 link_info->auto_mode = resp->auto_mode; 5620 link_info->auto_pause_setting = resp->auto_pause; 5621 link_info->lp_pause = resp->link_partner_adv_pause; 5622 link_info->force_pause_setting = resp->force_pause; 5623 link_info->duplex_setting = resp->duplex; 5624 if (link_info->phy_link_status == BNXT_LINK_LINK) 5625 link_info->link_speed = le16_to_cpu(resp->link_speed); 5626 else 5627 link_info->link_speed = 0; 5628 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed); 5629 link_info->support_speeds = le16_to_cpu(resp->support_speeds); 5630 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask); 5631 link_info->lp_auto_link_speeds = 5632 le16_to_cpu(resp->link_partner_adv_speeds); 5633 link_info->preemphasis = le32_to_cpu(resp->preemphasis); 5634 link_info->phy_ver[0] = resp->phy_maj; 5635 link_info->phy_ver[1] = resp->phy_min; 5636 link_info->phy_ver[2] = resp->phy_bld; 5637 link_info->media_type = resp->media_type; 5638 link_info->phy_type = resp->phy_type; 5639 link_info->transceiver = resp->xcvr_pkg_type; 5640 link_info->phy_addr = resp->eee_config_phy_addr & 5641 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK; 5642 link_info->module_status = resp->module_status; 5643 5644 if (bp->flags & BNXT_FLAG_EEE_CAP) { 5645 struct ethtool_eee *eee = &bp->eee; 5646 u16 fw_speeds; 5647 5648 eee->eee_active = 0; 5649 if (resp->eee_config_phy_addr & 5650 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) { 5651 eee->eee_active = 1; 5652 fw_speeds = le16_to_cpu( 5653 resp->link_partner_adv_eee_link_speed_mask); 5654 eee->lp_advertised = 5655 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 5656 } 5657 5658 /* Pull initial EEE config */ 5659 if (!chng_link_state) { 5660 if (resp->eee_config_phy_addr & 5661 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED) 5662 eee->eee_enabled = 1; 5663 5664 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask); 5665 eee->advertised = 5666 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 5667 5668 if (resp->eee_config_phy_addr & 5669 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) { 5670 __le32 tmr; 5671 5672 eee->tx_lpi_enabled = 1; 5673 tmr = resp->xcvr_identifier_type_tx_lpi_timer; 5674 eee->tx_lpi_timer = le32_to_cpu(tmr) & 5675 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK; 5676 } 5677 } 5678 } 5679 5680 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED; 5681 if (bp->hwrm_spec_code >= 0x10504) 5682 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg); 5683 5684 /* TODO: need to add more logic to report VF link */ 5685 if (chng_link_state) { 5686 if (link_info->phy_link_status == BNXT_LINK_LINK) 5687 link_info->link_up = 1; 5688 else 5689 link_info->link_up = 0; 5690 if (link_up != link_info->link_up) 5691 bnxt_report_link(bp); 5692 } else { 5693 /* alwasy link down if not require to update link state */ 5694 link_info->link_up = 0; 5695 } 5696 mutex_unlock(&bp->hwrm_cmd_lock); 5697 5698 diff = link_info->support_auto_speeds ^ link_info->advertising; 5699 if ((link_info->support_auto_speeds | diff) != 5700 link_info->support_auto_speeds) { 5701 /* An advertised speed is no longer supported, so we need to 5702 * update the advertisement settings. Caller holds RTNL 5703 * so we can modify link settings. 5704 */ 5705 link_info->advertising = link_info->support_auto_speeds; 5706 if (link_info->autoneg & BNXT_AUTONEG_SPEED) 5707 bnxt_hwrm_set_link_setting(bp, true, false); 5708 } 5709 return 0; 5710 } 5711 5712 static void bnxt_get_port_module_status(struct bnxt *bp) 5713 { 5714 struct bnxt_link_info *link_info = &bp->link_info; 5715 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp; 5716 u8 module_status; 5717 5718 if (bnxt_update_link(bp, true)) 5719 return; 5720 5721 module_status = link_info->module_status; 5722 switch (module_status) { 5723 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX: 5724 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 5725 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG: 5726 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n", 5727 bp->pf.port_id); 5728 if (bp->hwrm_spec_code >= 0x10201) { 5729 netdev_warn(bp->dev, "Module part number %s\n", 5730 resp->phy_vendor_partnumber); 5731 } 5732 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX) 5733 netdev_warn(bp->dev, "TX is disabled\n"); 5734 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN) 5735 netdev_warn(bp->dev, "SFP+ module is shutdown\n"); 5736 } 5737 } 5738 5739 static void 5740 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req) 5741 { 5742 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) { 5743 if (bp->hwrm_spec_code >= 0x10201) 5744 req->auto_pause = 5745 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 5746 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 5747 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX; 5748 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 5749 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX; 5750 req->enables |= 5751 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 5752 } else { 5753 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 5754 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX; 5755 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 5756 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX; 5757 req->enables |= 5758 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE); 5759 if (bp->hwrm_spec_code >= 0x10201) { 5760 req->auto_pause = req->force_pause; 5761 req->enables |= cpu_to_le32( 5762 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 5763 } 5764 } 5765 } 5766 5767 static void bnxt_hwrm_set_link_common(struct bnxt *bp, 5768 struct hwrm_port_phy_cfg_input *req) 5769 { 5770 u8 autoneg = bp->link_info.autoneg; 5771 u16 fw_link_speed = bp->link_info.req_link_speed; 5772 u16 advertising = bp->link_info.advertising; 5773 5774 if (autoneg & BNXT_AUTONEG_SPEED) { 5775 req->auto_mode |= 5776 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK; 5777 5778 req->enables |= cpu_to_le32( 5779 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK); 5780 req->auto_link_speed_mask = cpu_to_le16(advertising); 5781 5782 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE); 5783 req->flags |= 5784 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG); 5785 } else { 5786 req->force_link_speed = cpu_to_le16(fw_link_speed); 5787 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE); 5788 } 5789 5790 /* tell chimp that the setting takes effect immediately */ 5791 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 5792 } 5793 5794 int bnxt_hwrm_set_pause(struct bnxt *bp) 5795 { 5796 struct hwrm_port_phy_cfg_input req = {0}; 5797 int rc; 5798 5799 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 5800 bnxt_hwrm_set_pause_common(bp, &req); 5801 5802 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) || 5803 bp->link_info.force_link_chng) 5804 bnxt_hwrm_set_link_common(bp, &req); 5805 5806 mutex_lock(&bp->hwrm_cmd_lock); 5807 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5808 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) { 5809 /* since changing of pause setting doesn't trigger any link 5810 * change event, the driver needs to update the current pause 5811 * result upon successfully return of the phy_cfg command 5812 */ 5813 bp->link_info.pause = 5814 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl; 5815 bp->link_info.auto_pause_setting = 0; 5816 if (!bp->link_info.force_link_chng) 5817 bnxt_report_link(bp); 5818 } 5819 bp->link_info.force_link_chng = false; 5820 mutex_unlock(&bp->hwrm_cmd_lock); 5821 return rc; 5822 } 5823 5824 static void bnxt_hwrm_set_eee(struct bnxt *bp, 5825 struct hwrm_port_phy_cfg_input *req) 5826 { 5827 struct ethtool_eee *eee = &bp->eee; 5828 5829 if (eee->eee_enabled) { 5830 u16 eee_speeds; 5831 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE; 5832 5833 if (eee->tx_lpi_enabled) 5834 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE; 5835 else 5836 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE; 5837 5838 req->flags |= cpu_to_le32(flags); 5839 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised); 5840 req->eee_link_speed_mask = cpu_to_le16(eee_speeds); 5841 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer); 5842 } else { 5843 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE); 5844 } 5845 } 5846 5847 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee) 5848 { 5849 struct hwrm_port_phy_cfg_input req = {0}; 5850 5851 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 5852 if (set_pause) 5853 bnxt_hwrm_set_pause_common(bp, &req); 5854 5855 bnxt_hwrm_set_link_common(bp, &req); 5856 5857 if (set_eee) 5858 bnxt_hwrm_set_eee(bp, &req); 5859 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5860 } 5861 5862 static int bnxt_hwrm_shutdown_link(struct bnxt *bp) 5863 { 5864 struct hwrm_port_phy_cfg_input req = {0}; 5865 5866 if (!BNXT_SINGLE_PF(bp)) 5867 return 0; 5868 5869 if (pci_num_vf(bp->pdev)) 5870 return 0; 5871 5872 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 5873 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN); 5874 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5875 } 5876 5877 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp) 5878 { 5879 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 5880 struct hwrm_port_led_qcaps_input req = {0}; 5881 struct bnxt_pf_info *pf = &bp->pf; 5882 int rc; 5883 5884 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601) 5885 return 0; 5886 5887 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1); 5888 req.port_id = cpu_to_le16(pf->port_id); 5889 mutex_lock(&bp->hwrm_cmd_lock); 5890 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5891 if (rc) { 5892 mutex_unlock(&bp->hwrm_cmd_lock); 5893 return rc; 5894 } 5895 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) { 5896 int i; 5897 5898 bp->num_leds = resp->num_leds; 5899 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) * 5900 bp->num_leds); 5901 for (i = 0; i < bp->num_leds; i++) { 5902 struct bnxt_led_info *led = &bp->leds[i]; 5903 __le16 caps = led->led_state_caps; 5904 5905 if (!led->led_group_id || 5906 !BNXT_LED_ALT_BLINK_CAP(caps)) { 5907 bp->num_leds = 0; 5908 break; 5909 } 5910 } 5911 } 5912 mutex_unlock(&bp->hwrm_cmd_lock); 5913 return 0; 5914 } 5915 5916 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp) 5917 { 5918 struct hwrm_wol_filter_alloc_input req = {0}; 5919 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; 5920 int rc; 5921 5922 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1); 5923 req.port_id = cpu_to_le16(bp->pf.port_id); 5924 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT; 5925 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS); 5926 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN); 5927 mutex_lock(&bp->hwrm_cmd_lock); 5928 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5929 if (!rc) 5930 bp->wol_filter_id = resp->wol_filter_id; 5931 mutex_unlock(&bp->hwrm_cmd_lock); 5932 return rc; 5933 } 5934 5935 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp) 5936 { 5937 struct hwrm_wol_filter_free_input req = {0}; 5938 int rc; 5939 5940 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1); 5941 req.port_id = cpu_to_le16(bp->pf.port_id); 5942 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID); 5943 req.wol_filter_id = bp->wol_filter_id; 5944 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5945 return rc; 5946 } 5947 5948 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle) 5949 { 5950 struct hwrm_wol_filter_qcfg_input req = {0}; 5951 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 5952 u16 next_handle = 0; 5953 int rc; 5954 5955 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1); 5956 req.port_id = cpu_to_le16(bp->pf.port_id); 5957 req.handle = cpu_to_le16(handle); 5958 mutex_lock(&bp->hwrm_cmd_lock); 5959 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5960 if (!rc) { 5961 next_handle = le16_to_cpu(resp->next_handle); 5962 if (next_handle != 0) { 5963 if (resp->wol_type == 5964 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) { 5965 bp->wol = 1; 5966 bp->wol_filter_id = resp->wol_filter_id; 5967 } 5968 } 5969 } 5970 mutex_unlock(&bp->hwrm_cmd_lock); 5971 return next_handle; 5972 } 5973 5974 static void bnxt_get_wol_settings(struct bnxt *bp) 5975 { 5976 u16 handle = 0; 5977 5978 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP)) 5979 return; 5980 5981 do { 5982 handle = bnxt_hwrm_get_wol_fltrs(bp, handle); 5983 } while (handle && handle != 0xffff); 5984 } 5985 5986 static bool bnxt_eee_config_ok(struct bnxt *bp) 5987 { 5988 struct ethtool_eee *eee = &bp->eee; 5989 struct bnxt_link_info *link_info = &bp->link_info; 5990 5991 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 5992 return true; 5993 5994 if (eee->eee_enabled) { 5995 u32 advertising = 5996 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 5997 5998 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 5999 eee->eee_enabled = 0; 6000 return false; 6001 } 6002 if (eee->advertised & ~advertising) { 6003 eee->advertised = advertising & eee->supported; 6004 return false; 6005 } 6006 } 6007 return true; 6008 } 6009 6010 static int bnxt_update_phy_setting(struct bnxt *bp) 6011 { 6012 int rc; 6013 bool update_link = false; 6014 bool update_pause = false; 6015 bool update_eee = false; 6016 struct bnxt_link_info *link_info = &bp->link_info; 6017 6018 rc = bnxt_update_link(bp, true); 6019 if (rc) { 6020 netdev_err(bp->dev, "failed to update link (rc: %x)\n", 6021 rc); 6022 return rc; 6023 } 6024 if (!BNXT_SINGLE_PF(bp)) 6025 return 0; 6026 6027 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 6028 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) != 6029 link_info->req_flow_ctrl) 6030 update_pause = true; 6031 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 6032 link_info->force_pause_setting != link_info->req_flow_ctrl) 6033 update_pause = true; 6034 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 6035 if (BNXT_AUTO_MODE(link_info->auto_mode)) 6036 update_link = true; 6037 if (link_info->req_link_speed != link_info->force_link_speed) 6038 update_link = true; 6039 if (link_info->req_duplex != link_info->duplex_setting) 6040 update_link = true; 6041 } else { 6042 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE) 6043 update_link = true; 6044 if (link_info->advertising != link_info->auto_link_speeds) 6045 update_link = true; 6046 } 6047 6048 /* The last close may have shutdown the link, so need to call 6049 * PHY_CFG to bring it back up. 6050 */ 6051 if (!netif_carrier_ok(bp->dev)) 6052 update_link = true; 6053 6054 if (!bnxt_eee_config_ok(bp)) 6055 update_eee = true; 6056 6057 if (update_link) 6058 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee); 6059 else if (update_pause) 6060 rc = bnxt_hwrm_set_pause(bp); 6061 if (rc) { 6062 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n", 6063 rc); 6064 return rc; 6065 } 6066 6067 return rc; 6068 } 6069 6070 /* Common routine to pre-map certain register block to different GRC window. 6071 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows 6072 * in PF and 3 windows in VF that can be customized to map in different 6073 * register blocks. 6074 */ 6075 static void bnxt_preset_reg_win(struct bnxt *bp) 6076 { 6077 if (BNXT_PF(bp)) { 6078 /* CAG registers map to GRC window #4 */ 6079 writel(BNXT_CAG_REG_BASE, 6080 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12); 6081 } 6082 } 6083 6084 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 6085 { 6086 int rc = 0; 6087 6088 bnxt_preset_reg_win(bp); 6089 netif_carrier_off(bp->dev); 6090 if (irq_re_init) { 6091 rc = bnxt_setup_int_mode(bp); 6092 if (rc) { 6093 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n", 6094 rc); 6095 return rc; 6096 } 6097 } 6098 if ((bp->flags & BNXT_FLAG_RFS) && 6099 !(bp->flags & BNXT_FLAG_USING_MSIX)) { 6100 /* disable RFS if falling back to INTA */ 6101 bp->dev->hw_features &= ~NETIF_F_NTUPLE; 6102 bp->flags &= ~BNXT_FLAG_RFS; 6103 } 6104 6105 rc = bnxt_alloc_mem(bp, irq_re_init); 6106 if (rc) { 6107 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 6108 goto open_err_free_mem; 6109 } 6110 6111 if (irq_re_init) { 6112 bnxt_init_napi(bp); 6113 rc = bnxt_request_irq(bp); 6114 if (rc) { 6115 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc); 6116 goto open_err; 6117 } 6118 } 6119 6120 bnxt_enable_napi(bp); 6121 6122 rc = bnxt_init_nic(bp, irq_re_init); 6123 if (rc) { 6124 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 6125 goto open_err; 6126 } 6127 6128 if (link_re_init) { 6129 rc = bnxt_update_phy_setting(bp); 6130 if (rc) 6131 netdev_warn(bp->dev, "failed to update phy settings\n"); 6132 } 6133 6134 if (irq_re_init) 6135 udp_tunnel_get_rx_info(bp->dev); 6136 6137 set_bit(BNXT_STATE_OPEN, &bp->state); 6138 bnxt_enable_int(bp); 6139 /* Enable TX queues */ 6140 bnxt_tx_enable(bp); 6141 mod_timer(&bp->timer, jiffies + bp->current_interval); 6142 /* Poll link status and check for SFP+ module status */ 6143 bnxt_get_port_module_status(bp); 6144 6145 return 0; 6146 6147 open_err: 6148 bnxt_disable_napi(bp); 6149 bnxt_del_napi(bp); 6150 6151 open_err_free_mem: 6152 bnxt_free_skbs(bp); 6153 bnxt_free_irq(bp); 6154 bnxt_free_mem(bp, true); 6155 return rc; 6156 } 6157 6158 /* rtnl_lock held */ 6159 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 6160 { 6161 int rc = 0; 6162 6163 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init); 6164 if (rc) { 6165 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc); 6166 dev_close(bp->dev); 6167 } 6168 return rc; 6169 } 6170 6171 /* rtnl_lock held, open the NIC half way by allocating all resources, but 6172 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline 6173 * self tests. 6174 */ 6175 int bnxt_half_open_nic(struct bnxt *bp) 6176 { 6177 int rc = 0; 6178 6179 rc = bnxt_alloc_mem(bp, false); 6180 if (rc) { 6181 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 6182 goto half_open_err; 6183 } 6184 rc = bnxt_init_nic(bp, false); 6185 if (rc) { 6186 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 6187 goto half_open_err; 6188 } 6189 return 0; 6190 6191 half_open_err: 6192 bnxt_free_skbs(bp); 6193 bnxt_free_mem(bp, false); 6194 dev_close(bp->dev); 6195 return rc; 6196 } 6197 6198 /* rtnl_lock held, this call can only be made after a previous successful 6199 * call to bnxt_half_open_nic(). 6200 */ 6201 void bnxt_half_close_nic(struct bnxt *bp) 6202 { 6203 bnxt_hwrm_resource_free(bp, false, false); 6204 bnxt_free_skbs(bp); 6205 bnxt_free_mem(bp, false); 6206 } 6207 6208 static int bnxt_open(struct net_device *dev) 6209 { 6210 struct bnxt *bp = netdev_priv(dev); 6211 6212 return __bnxt_open_nic(bp, true, true); 6213 } 6214 6215 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 6216 { 6217 int rc = 0; 6218 6219 #ifdef CONFIG_BNXT_SRIOV 6220 if (bp->sriov_cfg) { 6221 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait, 6222 !bp->sriov_cfg, 6223 BNXT_SRIOV_CFG_WAIT_TMO); 6224 if (rc) 6225 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n"); 6226 } 6227 #endif 6228 /* Change device state to avoid TX queue wake up's */ 6229 bnxt_tx_disable(bp); 6230 6231 clear_bit(BNXT_STATE_OPEN, &bp->state); 6232 smp_mb__after_atomic(); 6233 while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state)) 6234 msleep(20); 6235 6236 /* Flush rings and and disable interrupts */ 6237 bnxt_shutdown_nic(bp, irq_re_init); 6238 6239 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */ 6240 6241 bnxt_disable_napi(bp); 6242 del_timer_sync(&bp->timer); 6243 bnxt_free_skbs(bp); 6244 6245 if (irq_re_init) { 6246 bnxt_free_irq(bp); 6247 bnxt_del_napi(bp); 6248 } 6249 bnxt_free_mem(bp, irq_re_init); 6250 return rc; 6251 } 6252 6253 static int bnxt_close(struct net_device *dev) 6254 { 6255 struct bnxt *bp = netdev_priv(dev); 6256 6257 bnxt_close_nic(bp, true, true); 6258 bnxt_hwrm_shutdown_link(bp); 6259 return 0; 6260 } 6261 6262 /* rtnl_lock held */ 6263 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 6264 { 6265 switch (cmd) { 6266 case SIOCGMIIPHY: 6267 /* fallthru */ 6268 case SIOCGMIIREG: { 6269 if (!netif_running(dev)) 6270 return -EAGAIN; 6271 6272 return 0; 6273 } 6274 6275 case SIOCSMIIREG: 6276 if (!netif_running(dev)) 6277 return -EAGAIN; 6278 6279 return 0; 6280 6281 default: 6282 /* do nothing */ 6283 break; 6284 } 6285 return -EOPNOTSUPP; 6286 } 6287 6288 static void 6289 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 6290 { 6291 u32 i; 6292 struct bnxt *bp = netdev_priv(dev); 6293 6294 if (!bp->bnapi) 6295 return; 6296 6297 /* TODO check if we need to synchronize with bnxt_close path */ 6298 for (i = 0; i < bp->cp_nr_rings; i++) { 6299 struct bnxt_napi *bnapi = bp->bnapi[i]; 6300 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6301 struct ctx_hw_stats *hw_stats = cpr->hw_stats; 6302 6303 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts); 6304 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts); 6305 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts); 6306 6307 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts); 6308 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts); 6309 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts); 6310 6311 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes); 6312 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes); 6313 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes); 6314 6315 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes); 6316 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes); 6317 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes); 6318 6319 stats->rx_missed_errors += 6320 le64_to_cpu(hw_stats->rx_discard_pkts); 6321 6322 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts); 6323 6324 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts); 6325 } 6326 6327 if (bp->flags & BNXT_FLAG_PORT_STATS) { 6328 struct rx_port_stats *rx = bp->hw_rx_port_stats; 6329 struct tx_port_stats *tx = bp->hw_tx_port_stats; 6330 6331 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames); 6332 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames); 6333 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) + 6334 le64_to_cpu(rx->rx_ovrsz_frames) + 6335 le64_to_cpu(rx->rx_runt_frames); 6336 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) + 6337 le64_to_cpu(rx->rx_jbr_frames); 6338 stats->collisions = le64_to_cpu(tx->tx_total_collisions); 6339 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns); 6340 stats->tx_errors = le64_to_cpu(tx->tx_err); 6341 } 6342 } 6343 6344 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask) 6345 { 6346 struct net_device *dev = bp->dev; 6347 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 6348 struct netdev_hw_addr *ha; 6349 u8 *haddr; 6350 int mc_count = 0; 6351 bool update = false; 6352 int off = 0; 6353 6354 netdev_for_each_mc_addr(ha, dev) { 6355 if (mc_count >= BNXT_MAX_MC_ADDRS) { 6356 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 6357 vnic->mc_list_count = 0; 6358 return false; 6359 } 6360 haddr = ha->addr; 6361 if (!ether_addr_equal(haddr, vnic->mc_list + off)) { 6362 memcpy(vnic->mc_list + off, haddr, ETH_ALEN); 6363 update = true; 6364 } 6365 off += ETH_ALEN; 6366 mc_count++; 6367 } 6368 if (mc_count) 6369 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST; 6370 6371 if (mc_count != vnic->mc_list_count) { 6372 vnic->mc_list_count = mc_count; 6373 update = true; 6374 } 6375 return update; 6376 } 6377 6378 static bool bnxt_uc_list_updated(struct bnxt *bp) 6379 { 6380 struct net_device *dev = bp->dev; 6381 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 6382 struct netdev_hw_addr *ha; 6383 int off = 0; 6384 6385 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1)) 6386 return true; 6387 6388 netdev_for_each_uc_addr(ha, dev) { 6389 if (!ether_addr_equal(ha->addr, vnic->uc_list + off)) 6390 return true; 6391 6392 off += ETH_ALEN; 6393 } 6394 return false; 6395 } 6396 6397 static void bnxt_set_rx_mode(struct net_device *dev) 6398 { 6399 struct bnxt *bp = netdev_priv(dev); 6400 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 6401 u32 mask = vnic->rx_mask; 6402 bool mc_update = false; 6403 bool uc_update; 6404 6405 if (!netif_running(dev)) 6406 return; 6407 6408 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS | 6409 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST | 6410 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST); 6411 6412 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) 6413 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 6414 6415 uc_update = bnxt_uc_list_updated(bp); 6416 6417 if (dev->flags & IFF_ALLMULTI) { 6418 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 6419 vnic->mc_list_count = 0; 6420 } else { 6421 mc_update = bnxt_mc_list_updated(bp, &mask); 6422 } 6423 6424 if (mask != vnic->rx_mask || uc_update || mc_update) { 6425 vnic->rx_mask = mask; 6426 6427 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event); 6428 schedule_work(&bp->sp_task); 6429 } 6430 } 6431 6432 static int bnxt_cfg_rx_mode(struct bnxt *bp) 6433 { 6434 struct net_device *dev = bp->dev; 6435 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 6436 struct netdev_hw_addr *ha; 6437 int i, off = 0, rc; 6438 bool uc_update; 6439 6440 netif_addr_lock_bh(dev); 6441 uc_update = bnxt_uc_list_updated(bp); 6442 netif_addr_unlock_bh(dev); 6443 6444 if (!uc_update) 6445 goto skip_uc; 6446 6447 mutex_lock(&bp->hwrm_cmd_lock); 6448 for (i = 1; i < vnic->uc_filter_count; i++) { 6449 struct hwrm_cfa_l2_filter_free_input req = {0}; 6450 6451 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1, 6452 -1); 6453 6454 req.l2_filter_id = vnic->fw_l2_filter_id[i]; 6455 6456 rc = _hwrm_send_message(bp, &req, sizeof(req), 6457 HWRM_CMD_TIMEOUT); 6458 } 6459 mutex_unlock(&bp->hwrm_cmd_lock); 6460 6461 vnic->uc_filter_count = 1; 6462 6463 netif_addr_lock_bh(dev); 6464 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) { 6465 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 6466 } else { 6467 netdev_for_each_uc_addr(ha, dev) { 6468 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN); 6469 off += ETH_ALEN; 6470 vnic->uc_filter_count++; 6471 } 6472 } 6473 netif_addr_unlock_bh(dev); 6474 6475 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) { 6476 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off); 6477 if (rc) { 6478 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", 6479 rc); 6480 vnic->uc_filter_count = i; 6481 return rc; 6482 } 6483 } 6484 6485 skip_uc: 6486 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); 6487 if (rc) 6488 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n", 6489 rc); 6490 6491 return rc; 6492 } 6493 6494 /* If the chip and firmware supports RFS */ 6495 static bool bnxt_rfs_supported(struct bnxt *bp) 6496 { 6497 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) 6498 return true; 6499 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 6500 return true; 6501 return false; 6502 } 6503 6504 /* If runtime conditions support RFS */ 6505 static bool bnxt_rfs_capable(struct bnxt *bp) 6506 { 6507 #ifdef CONFIG_RFS_ACCEL 6508 int vnics, max_vnics, max_rss_ctxs; 6509 6510 if (!(bp->flags & BNXT_FLAG_MSIX_CAP)) 6511 return false; 6512 6513 vnics = 1 + bp->rx_nr_rings; 6514 max_vnics = bnxt_get_max_func_vnics(bp); 6515 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp); 6516 6517 /* RSS contexts not a limiting factor */ 6518 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 6519 max_rss_ctxs = max_vnics; 6520 if (vnics > max_vnics || vnics > max_rss_ctxs) { 6521 netdev_warn(bp->dev, 6522 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n", 6523 min(max_rss_ctxs - 1, max_vnics - 1)); 6524 return false; 6525 } 6526 6527 return true; 6528 #else 6529 return false; 6530 #endif 6531 } 6532 6533 static netdev_features_t bnxt_fix_features(struct net_device *dev, 6534 netdev_features_t features) 6535 { 6536 struct bnxt *bp = netdev_priv(dev); 6537 6538 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp)) 6539 features &= ~NETIF_F_NTUPLE; 6540 6541 /* Both CTAG and STAG VLAN accelaration on the RX side have to be 6542 * turned on or off together. 6543 */ 6544 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) != 6545 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) { 6546 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX) 6547 features &= ~(NETIF_F_HW_VLAN_CTAG_RX | 6548 NETIF_F_HW_VLAN_STAG_RX); 6549 else 6550 features |= NETIF_F_HW_VLAN_CTAG_RX | 6551 NETIF_F_HW_VLAN_STAG_RX; 6552 } 6553 #ifdef CONFIG_BNXT_SRIOV 6554 if (BNXT_VF(bp)) { 6555 if (bp->vf.vlan) { 6556 features &= ~(NETIF_F_HW_VLAN_CTAG_RX | 6557 NETIF_F_HW_VLAN_STAG_RX); 6558 } 6559 } 6560 #endif 6561 return features; 6562 } 6563 6564 static int bnxt_set_features(struct net_device *dev, netdev_features_t features) 6565 { 6566 struct bnxt *bp = netdev_priv(dev); 6567 u32 flags = bp->flags; 6568 u32 changes; 6569 int rc = 0; 6570 bool re_init = false; 6571 bool update_tpa = false; 6572 6573 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS; 6574 if ((features & NETIF_F_GRO) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) 6575 flags |= BNXT_FLAG_GRO; 6576 if (features & NETIF_F_LRO) 6577 flags |= BNXT_FLAG_LRO; 6578 6579 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 6580 flags &= ~BNXT_FLAG_TPA; 6581 6582 if (features & NETIF_F_HW_VLAN_CTAG_RX) 6583 flags |= BNXT_FLAG_STRIP_VLAN; 6584 6585 if (features & NETIF_F_NTUPLE) 6586 flags |= BNXT_FLAG_RFS; 6587 6588 changes = flags ^ bp->flags; 6589 if (changes & BNXT_FLAG_TPA) { 6590 update_tpa = true; 6591 if ((bp->flags & BNXT_FLAG_TPA) == 0 || 6592 (flags & BNXT_FLAG_TPA) == 0) 6593 re_init = true; 6594 } 6595 6596 if (changes & ~BNXT_FLAG_TPA) 6597 re_init = true; 6598 6599 if (flags != bp->flags) { 6600 u32 old_flags = bp->flags; 6601 6602 bp->flags = flags; 6603 6604 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 6605 if (update_tpa) 6606 bnxt_set_ring_params(bp); 6607 return rc; 6608 } 6609 6610 if (re_init) { 6611 bnxt_close_nic(bp, false, false); 6612 if (update_tpa) 6613 bnxt_set_ring_params(bp); 6614 6615 return bnxt_open_nic(bp, false, false); 6616 } 6617 if (update_tpa) { 6618 rc = bnxt_set_tpa(bp, 6619 (flags & BNXT_FLAG_TPA) ? 6620 true : false); 6621 if (rc) 6622 bp->flags = old_flags; 6623 } 6624 } 6625 return rc; 6626 } 6627 6628 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi) 6629 { 6630 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 6631 int i = bnapi->index; 6632 6633 if (!txr) 6634 return; 6635 6636 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n", 6637 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod, 6638 txr->tx_cons); 6639 } 6640 6641 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi) 6642 { 6643 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 6644 int i = bnapi->index; 6645 6646 if (!rxr) 6647 return; 6648 6649 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n", 6650 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod, 6651 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod, 6652 rxr->rx_sw_agg_prod); 6653 } 6654 6655 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi) 6656 { 6657 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6658 int i = bnapi->index; 6659 6660 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n", 6661 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons); 6662 } 6663 6664 static void bnxt_dbg_dump_states(struct bnxt *bp) 6665 { 6666 int i; 6667 struct bnxt_napi *bnapi; 6668 6669 for (i = 0; i < bp->cp_nr_rings; i++) { 6670 bnapi = bp->bnapi[i]; 6671 if (netif_msg_drv(bp)) { 6672 bnxt_dump_tx_sw_state(bnapi); 6673 bnxt_dump_rx_sw_state(bnapi); 6674 bnxt_dump_cp_sw_state(bnapi); 6675 } 6676 } 6677 } 6678 6679 static void bnxt_reset_task(struct bnxt *bp, bool silent) 6680 { 6681 if (!silent) 6682 bnxt_dbg_dump_states(bp); 6683 if (netif_running(bp->dev)) { 6684 int rc; 6685 6686 if (!silent) 6687 bnxt_ulp_stop(bp); 6688 bnxt_close_nic(bp, false, false); 6689 rc = bnxt_open_nic(bp, false, false); 6690 if (!silent && !rc) 6691 bnxt_ulp_start(bp); 6692 } 6693 } 6694 6695 static void bnxt_tx_timeout(struct net_device *dev) 6696 { 6697 struct bnxt *bp = netdev_priv(dev); 6698 6699 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n"); 6700 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 6701 schedule_work(&bp->sp_task); 6702 } 6703 6704 #ifdef CONFIG_NET_POLL_CONTROLLER 6705 static void bnxt_poll_controller(struct net_device *dev) 6706 { 6707 struct bnxt *bp = netdev_priv(dev); 6708 int i; 6709 6710 /* Only process tx rings/combined rings in netpoll mode. */ 6711 for (i = 0; i < bp->tx_nr_rings; i++) { 6712 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 6713 6714 napi_schedule(&txr->bnapi->napi); 6715 } 6716 } 6717 #endif 6718 6719 static void bnxt_timer(unsigned long data) 6720 { 6721 struct bnxt *bp = (struct bnxt *)data; 6722 struct net_device *dev = bp->dev; 6723 6724 if (!netif_running(dev)) 6725 return; 6726 6727 if (atomic_read(&bp->intr_sem) != 0) 6728 goto bnxt_restart_timer; 6729 6730 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS)) { 6731 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event); 6732 schedule_work(&bp->sp_task); 6733 } 6734 bnxt_restart_timer: 6735 mod_timer(&bp->timer, jiffies + bp->current_interval); 6736 } 6737 6738 static void bnxt_rtnl_lock_sp(struct bnxt *bp) 6739 { 6740 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK 6741 * set. If the device is being closed, bnxt_close() may be holding 6742 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we 6743 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl(). 6744 */ 6745 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 6746 rtnl_lock(); 6747 } 6748 6749 static void bnxt_rtnl_unlock_sp(struct bnxt *bp) 6750 { 6751 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 6752 rtnl_unlock(); 6753 } 6754 6755 /* Only called from bnxt_sp_task() */ 6756 static void bnxt_reset(struct bnxt *bp, bool silent) 6757 { 6758 bnxt_rtnl_lock_sp(bp); 6759 if (test_bit(BNXT_STATE_OPEN, &bp->state)) 6760 bnxt_reset_task(bp, silent); 6761 bnxt_rtnl_unlock_sp(bp); 6762 } 6763 6764 static void bnxt_cfg_ntp_filters(struct bnxt *); 6765 6766 static void bnxt_sp_task(struct work_struct *work) 6767 { 6768 struct bnxt *bp = container_of(work, struct bnxt, sp_task); 6769 6770 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 6771 smp_mb__after_atomic(); 6772 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 6773 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 6774 return; 6775 } 6776 6777 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event)) 6778 bnxt_cfg_rx_mode(bp); 6779 6780 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event)) 6781 bnxt_cfg_ntp_filters(bp); 6782 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event)) 6783 bnxt_hwrm_exec_fwd_req(bp); 6784 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) { 6785 bnxt_hwrm_tunnel_dst_port_alloc( 6786 bp, bp->vxlan_port, 6787 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 6788 } 6789 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) { 6790 bnxt_hwrm_tunnel_dst_port_free( 6791 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 6792 } 6793 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) { 6794 bnxt_hwrm_tunnel_dst_port_alloc( 6795 bp, bp->nge_port, 6796 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 6797 } 6798 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) { 6799 bnxt_hwrm_tunnel_dst_port_free( 6800 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 6801 } 6802 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) 6803 bnxt_hwrm_port_qstats(bp); 6804 6805 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They 6806 * must be the last functions to be called before exiting. 6807 */ 6808 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) { 6809 int rc = 0; 6810 6811 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, 6812 &bp->sp_event)) 6813 bnxt_hwrm_phy_qcaps(bp); 6814 6815 bnxt_rtnl_lock_sp(bp); 6816 if (test_bit(BNXT_STATE_OPEN, &bp->state)) 6817 rc = bnxt_update_link(bp, true); 6818 bnxt_rtnl_unlock_sp(bp); 6819 if (rc) 6820 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n", 6821 rc); 6822 } 6823 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) { 6824 bnxt_rtnl_lock_sp(bp); 6825 if (test_bit(BNXT_STATE_OPEN, &bp->state)) 6826 bnxt_get_port_module_status(bp); 6827 bnxt_rtnl_unlock_sp(bp); 6828 } 6829 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) 6830 bnxt_reset(bp, false); 6831 6832 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event)) 6833 bnxt_reset(bp, true); 6834 6835 smp_mb__before_atomic(); 6836 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 6837 } 6838 6839 /* Under rtnl_lock */ 6840 int bnxt_reserve_rings(struct bnxt *bp, int tx, int rx, int tcs, int tx_xdp) 6841 { 6842 int max_rx, max_tx, tx_sets = 1; 6843 int tx_rings_needed; 6844 bool sh = true; 6845 int rc; 6846 6847 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 6848 sh = false; 6849 6850 if (tcs) 6851 tx_sets = tcs; 6852 6853 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh); 6854 if (rc) 6855 return rc; 6856 6857 if (max_rx < rx) 6858 return -ENOMEM; 6859 6860 tx_rings_needed = tx * tx_sets + tx_xdp; 6861 if (max_tx < tx_rings_needed) 6862 return -ENOMEM; 6863 6864 if (bnxt_hwrm_reserve_tx_rings(bp, &tx_rings_needed) || 6865 tx_rings_needed < (tx * tx_sets + tx_xdp)) 6866 return -ENOMEM; 6867 return 0; 6868 } 6869 6870 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev) 6871 { 6872 if (bp->bar2) { 6873 pci_iounmap(pdev, bp->bar2); 6874 bp->bar2 = NULL; 6875 } 6876 6877 if (bp->bar1) { 6878 pci_iounmap(pdev, bp->bar1); 6879 bp->bar1 = NULL; 6880 } 6881 6882 if (bp->bar0) { 6883 pci_iounmap(pdev, bp->bar0); 6884 bp->bar0 = NULL; 6885 } 6886 } 6887 6888 static void bnxt_cleanup_pci(struct bnxt *bp) 6889 { 6890 bnxt_unmap_bars(bp, bp->pdev); 6891 pci_release_regions(bp->pdev); 6892 pci_disable_device(bp->pdev); 6893 } 6894 6895 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev) 6896 { 6897 int rc; 6898 struct bnxt *bp = netdev_priv(dev); 6899 6900 SET_NETDEV_DEV(dev, &pdev->dev); 6901 6902 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 6903 rc = pci_enable_device(pdev); 6904 if (rc) { 6905 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 6906 goto init_err; 6907 } 6908 6909 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 6910 dev_err(&pdev->dev, 6911 "Cannot find PCI device base address, aborting\n"); 6912 rc = -ENODEV; 6913 goto init_err_disable; 6914 } 6915 6916 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 6917 if (rc) { 6918 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); 6919 goto init_err_disable; 6920 } 6921 6922 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 && 6923 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) { 6924 dev_err(&pdev->dev, "System does not support DMA, aborting\n"); 6925 goto init_err_disable; 6926 } 6927 6928 pci_set_master(pdev); 6929 6930 bp->dev = dev; 6931 bp->pdev = pdev; 6932 6933 bp->bar0 = pci_ioremap_bar(pdev, 0); 6934 if (!bp->bar0) { 6935 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); 6936 rc = -ENOMEM; 6937 goto init_err_release; 6938 } 6939 6940 bp->bar1 = pci_ioremap_bar(pdev, 2); 6941 if (!bp->bar1) { 6942 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n"); 6943 rc = -ENOMEM; 6944 goto init_err_release; 6945 } 6946 6947 bp->bar2 = pci_ioremap_bar(pdev, 4); 6948 if (!bp->bar2) { 6949 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n"); 6950 rc = -ENOMEM; 6951 goto init_err_release; 6952 } 6953 6954 pci_enable_pcie_error_reporting(pdev); 6955 6956 INIT_WORK(&bp->sp_task, bnxt_sp_task); 6957 6958 spin_lock_init(&bp->ntp_fltr_lock); 6959 6960 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE; 6961 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE; 6962 6963 /* tick values in micro seconds */ 6964 bp->rx_coal_ticks = 12; 6965 bp->rx_coal_bufs = 30; 6966 bp->rx_coal_ticks_irq = 1; 6967 bp->rx_coal_bufs_irq = 2; 6968 6969 bp->tx_coal_ticks = 25; 6970 bp->tx_coal_bufs = 30; 6971 bp->tx_coal_ticks_irq = 2; 6972 bp->tx_coal_bufs_irq = 2; 6973 6974 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS; 6975 6976 init_timer(&bp->timer); 6977 bp->timer.data = (unsigned long)bp; 6978 bp->timer.function = bnxt_timer; 6979 bp->current_interval = BNXT_TIMER_INTERVAL; 6980 6981 clear_bit(BNXT_STATE_OPEN, &bp->state); 6982 return 0; 6983 6984 init_err_release: 6985 bnxt_unmap_bars(bp, pdev); 6986 pci_release_regions(pdev); 6987 6988 init_err_disable: 6989 pci_disable_device(pdev); 6990 6991 init_err: 6992 return rc; 6993 } 6994 6995 /* rtnl_lock held */ 6996 static int bnxt_change_mac_addr(struct net_device *dev, void *p) 6997 { 6998 struct sockaddr *addr = p; 6999 struct bnxt *bp = netdev_priv(dev); 7000 int rc = 0; 7001 7002 if (!is_valid_ether_addr(addr->sa_data)) 7003 return -EADDRNOTAVAIL; 7004 7005 rc = bnxt_approve_mac(bp, addr->sa_data); 7006 if (rc) 7007 return rc; 7008 7009 if (ether_addr_equal(addr->sa_data, dev->dev_addr)) 7010 return 0; 7011 7012 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 7013 if (netif_running(dev)) { 7014 bnxt_close_nic(bp, false, false); 7015 rc = bnxt_open_nic(bp, false, false); 7016 } 7017 7018 return rc; 7019 } 7020 7021 /* rtnl_lock held */ 7022 static int bnxt_change_mtu(struct net_device *dev, int new_mtu) 7023 { 7024 struct bnxt *bp = netdev_priv(dev); 7025 7026 if (netif_running(dev)) 7027 bnxt_close_nic(bp, false, false); 7028 7029 dev->mtu = new_mtu; 7030 bnxt_set_ring_params(bp); 7031 7032 if (netif_running(dev)) 7033 return bnxt_open_nic(bp, false, false); 7034 7035 return 0; 7036 } 7037 7038 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc) 7039 { 7040 struct bnxt *bp = netdev_priv(dev); 7041 bool sh = false; 7042 int rc; 7043 7044 if (tc > bp->max_tc) { 7045 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n", 7046 tc, bp->max_tc); 7047 return -EINVAL; 7048 } 7049 7050 if (netdev_get_num_tc(dev) == tc) 7051 return 0; 7052 7053 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 7054 sh = true; 7055 7056 rc = bnxt_reserve_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings, 7057 tc, bp->tx_nr_rings_xdp); 7058 if (rc) 7059 return rc; 7060 7061 /* Needs to close the device and do hw resource re-allocations */ 7062 if (netif_running(bp->dev)) 7063 bnxt_close_nic(bp, true, false); 7064 7065 if (tc) { 7066 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc; 7067 netdev_set_num_tc(dev, tc); 7068 } else { 7069 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 7070 netdev_reset_tc(dev); 7071 } 7072 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 7073 bp->tx_nr_rings + bp->rx_nr_rings; 7074 bp->num_stat_ctxs = bp->cp_nr_rings; 7075 7076 if (netif_running(bp->dev)) 7077 return bnxt_open_nic(bp, true, false); 7078 7079 return 0; 7080 } 7081 7082 static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto, 7083 struct tc_to_netdev *ntc) 7084 { 7085 if (ntc->type != TC_SETUP_MQPRIO) 7086 return -EINVAL; 7087 7088 ntc->mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 7089 7090 return bnxt_setup_mq_tc(dev, ntc->mqprio->num_tc); 7091 } 7092 7093 #ifdef CONFIG_RFS_ACCEL 7094 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1, 7095 struct bnxt_ntuple_filter *f2) 7096 { 7097 struct flow_keys *keys1 = &f1->fkeys; 7098 struct flow_keys *keys2 = &f2->fkeys; 7099 7100 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src && 7101 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst && 7102 keys1->ports.ports == keys2->ports.ports && 7103 keys1->basic.ip_proto == keys2->basic.ip_proto && 7104 keys1->basic.n_proto == keys2->basic.n_proto && 7105 keys1->control.flags == keys2->control.flags && 7106 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) && 7107 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr)) 7108 return true; 7109 7110 return false; 7111 } 7112 7113 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 7114 u16 rxq_index, u32 flow_id) 7115 { 7116 struct bnxt *bp = netdev_priv(dev); 7117 struct bnxt_ntuple_filter *fltr, *new_fltr; 7118 struct flow_keys *fkeys; 7119 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb); 7120 int rc = 0, idx, bit_id, l2_idx = 0; 7121 struct hlist_head *head; 7122 7123 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) { 7124 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 7125 int off = 0, j; 7126 7127 netif_addr_lock_bh(dev); 7128 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) { 7129 if (ether_addr_equal(eth->h_dest, 7130 vnic->uc_list + off)) { 7131 l2_idx = j + 1; 7132 break; 7133 } 7134 } 7135 netif_addr_unlock_bh(dev); 7136 if (!l2_idx) 7137 return -EINVAL; 7138 } 7139 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC); 7140 if (!new_fltr) 7141 return -ENOMEM; 7142 7143 fkeys = &new_fltr->fkeys; 7144 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) { 7145 rc = -EPROTONOSUPPORT; 7146 goto err_free; 7147 } 7148 7149 if ((fkeys->basic.n_proto != htons(ETH_P_IP) && 7150 fkeys->basic.n_proto != htons(ETH_P_IPV6)) || 7151 ((fkeys->basic.ip_proto != IPPROTO_TCP) && 7152 (fkeys->basic.ip_proto != IPPROTO_UDP))) { 7153 rc = -EPROTONOSUPPORT; 7154 goto err_free; 7155 } 7156 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) && 7157 bp->hwrm_spec_code < 0x10601) { 7158 rc = -EPROTONOSUPPORT; 7159 goto err_free; 7160 } 7161 if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) && 7162 bp->hwrm_spec_code < 0x10601) { 7163 rc = -EPROTONOSUPPORT; 7164 goto err_free; 7165 } 7166 7167 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN); 7168 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN); 7169 7170 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK; 7171 head = &bp->ntp_fltr_hash_tbl[idx]; 7172 rcu_read_lock(); 7173 hlist_for_each_entry_rcu(fltr, head, hash) { 7174 if (bnxt_fltr_match(fltr, new_fltr)) { 7175 rcu_read_unlock(); 7176 rc = 0; 7177 goto err_free; 7178 } 7179 } 7180 rcu_read_unlock(); 7181 7182 spin_lock_bh(&bp->ntp_fltr_lock); 7183 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap, 7184 BNXT_NTP_FLTR_MAX_FLTR, 0); 7185 if (bit_id < 0) { 7186 spin_unlock_bh(&bp->ntp_fltr_lock); 7187 rc = -ENOMEM; 7188 goto err_free; 7189 } 7190 7191 new_fltr->sw_id = (u16)bit_id; 7192 new_fltr->flow_id = flow_id; 7193 new_fltr->l2_fltr_idx = l2_idx; 7194 new_fltr->rxq = rxq_index; 7195 hlist_add_head_rcu(&new_fltr->hash, head); 7196 bp->ntp_fltr_count++; 7197 spin_unlock_bh(&bp->ntp_fltr_lock); 7198 7199 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); 7200 schedule_work(&bp->sp_task); 7201 7202 return new_fltr->sw_id; 7203 7204 err_free: 7205 kfree(new_fltr); 7206 return rc; 7207 } 7208 7209 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 7210 { 7211 int i; 7212 7213 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 7214 struct hlist_head *head; 7215 struct hlist_node *tmp; 7216 struct bnxt_ntuple_filter *fltr; 7217 int rc; 7218 7219 head = &bp->ntp_fltr_hash_tbl[i]; 7220 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 7221 bool del = false; 7222 7223 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) { 7224 if (rps_may_expire_flow(bp->dev, fltr->rxq, 7225 fltr->flow_id, 7226 fltr->sw_id)) { 7227 bnxt_hwrm_cfa_ntuple_filter_free(bp, 7228 fltr); 7229 del = true; 7230 } 7231 } else { 7232 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, 7233 fltr); 7234 if (rc) 7235 del = true; 7236 else 7237 set_bit(BNXT_FLTR_VALID, &fltr->state); 7238 } 7239 7240 if (del) { 7241 spin_lock_bh(&bp->ntp_fltr_lock); 7242 hlist_del_rcu(&fltr->hash); 7243 bp->ntp_fltr_count--; 7244 spin_unlock_bh(&bp->ntp_fltr_lock); 7245 synchronize_rcu(); 7246 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap); 7247 kfree(fltr); 7248 } 7249 } 7250 } 7251 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event)) 7252 netdev_info(bp->dev, "Receive PF driver unload event!"); 7253 } 7254 7255 #else 7256 7257 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 7258 { 7259 } 7260 7261 #endif /* CONFIG_RFS_ACCEL */ 7262 7263 static void bnxt_udp_tunnel_add(struct net_device *dev, 7264 struct udp_tunnel_info *ti) 7265 { 7266 struct bnxt *bp = netdev_priv(dev); 7267 7268 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) 7269 return; 7270 7271 if (!netif_running(dev)) 7272 return; 7273 7274 switch (ti->type) { 7275 case UDP_TUNNEL_TYPE_VXLAN: 7276 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port) 7277 return; 7278 7279 bp->vxlan_port_cnt++; 7280 if (bp->vxlan_port_cnt == 1) { 7281 bp->vxlan_port = ti->port; 7282 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event); 7283 schedule_work(&bp->sp_task); 7284 } 7285 break; 7286 case UDP_TUNNEL_TYPE_GENEVE: 7287 if (bp->nge_port_cnt && bp->nge_port != ti->port) 7288 return; 7289 7290 bp->nge_port_cnt++; 7291 if (bp->nge_port_cnt == 1) { 7292 bp->nge_port = ti->port; 7293 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event); 7294 } 7295 break; 7296 default: 7297 return; 7298 } 7299 7300 schedule_work(&bp->sp_task); 7301 } 7302 7303 static void bnxt_udp_tunnel_del(struct net_device *dev, 7304 struct udp_tunnel_info *ti) 7305 { 7306 struct bnxt *bp = netdev_priv(dev); 7307 7308 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) 7309 return; 7310 7311 if (!netif_running(dev)) 7312 return; 7313 7314 switch (ti->type) { 7315 case UDP_TUNNEL_TYPE_VXLAN: 7316 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port) 7317 return; 7318 bp->vxlan_port_cnt--; 7319 7320 if (bp->vxlan_port_cnt != 0) 7321 return; 7322 7323 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event); 7324 break; 7325 case UDP_TUNNEL_TYPE_GENEVE: 7326 if (!bp->nge_port_cnt || bp->nge_port != ti->port) 7327 return; 7328 bp->nge_port_cnt--; 7329 7330 if (bp->nge_port_cnt != 0) 7331 return; 7332 7333 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event); 7334 break; 7335 default: 7336 return; 7337 } 7338 7339 schedule_work(&bp->sp_task); 7340 } 7341 7342 static const struct net_device_ops bnxt_netdev_ops = { 7343 .ndo_open = bnxt_open, 7344 .ndo_start_xmit = bnxt_start_xmit, 7345 .ndo_stop = bnxt_close, 7346 .ndo_get_stats64 = bnxt_get_stats64, 7347 .ndo_set_rx_mode = bnxt_set_rx_mode, 7348 .ndo_do_ioctl = bnxt_ioctl, 7349 .ndo_validate_addr = eth_validate_addr, 7350 .ndo_set_mac_address = bnxt_change_mac_addr, 7351 .ndo_change_mtu = bnxt_change_mtu, 7352 .ndo_fix_features = bnxt_fix_features, 7353 .ndo_set_features = bnxt_set_features, 7354 .ndo_tx_timeout = bnxt_tx_timeout, 7355 #ifdef CONFIG_BNXT_SRIOV 7356 .ndo_get_vf_config = bnxt_get_vf_config, 7357 .ndo_set_vf_mac = bnxt_set_vf_mac, 7358 .ndo_set_vf_vlan = bnxt_set_vf_vlan, 7359 .ndo_set_vf_rate = bnxt_set_vf_bw, 7360 .ndo_set_vf_link_state = bnxt_set_vf_link_state, 7361 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk, 7362 #endif 7363 #ifdef CONFIG_NET_POLL_CONTROLLER 7364 .ndo_poll_controller = bnxt_poll_controller, 7365 #endif 7366 .ndo_setup_tc = bnxt_setup_tc, 7367 #ifdef CONFIG_RFS_ACCEL 7368 .ndo_rx_flow_steer = bnxt_rx_flow_steer, 7369 #endif 7370 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add, 7371 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del, 7372 .ndo_xdp = bnxt_xdp, 7373 }; 7374 7375 static void bnxt_remove_one(struct pci_dev *pdev) 7376 { 7377 struct net_device *dev = pci_get_drvdata(pdev); 7378 struct bnxt *bp = netdev_priv(dev); 7379 7380 if (BNXT_PF(bp)) 7381 bnxt_sriov_disable(bp); 7382 7383 pci_disable_pcie_error_reporting(pdev); 7384 unregister_netdev(dev); 7385 cancel_work_sync(&bp->sp_task); 7386 bp->sp_event = 0; 7387 7388 bnxt_clear_int_mode(bp); 7389 bnxt_hwrm_func_drv_unrgtr(bp); 7390 bnxt_free_hwrm_resources(bp); 7391 bnxt_ethtool_free(bp); 7392 bnxt_dcb_free(bp); 7393 kfree(bp->edev); 7394 bp->edev = NULL; 7395 if (bp->xdp_prog) 7396 bpf_prog_put(bp->xdp_prog); 7397 bnxt_cleanup_pci(bp); 7398 free_netdev(dev); 7399 } 7400 7401 static int bnxt_probe_phy(struct bnxt *bp) 7402 { 7403 int rc = 0; 7404 struct bnxt_link_info *link_info = &bp->link_info; 7405 7406 rc = bnxt_hwrm_phy_qcaps(bp); 7407 if (rc) { 7408 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n", 7409 rc); 7410 return rc; 7411 } 7412 7413 rc = bnxt_update_link(bp, false); 7414 if (rc) { 7415 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n", 7416 rc); 7417 return rc; 7418 } 7419 7420 /* Older firmware does not have supported_auto_speeds, so assume 7421 * that all supported speeds can be autonegotiated. 7422 */ 7423 if (link_info->auto_link_speeds && !link_info->support_auto_speeds) 7424 link_info->support_auto_speeds = link_info->support_speeds; 7425 7426 /*initialize the ethool setting copy with NVM settings */ 7427 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 7428 link_info->autoneg = BNXT_AUTONEG_SPEED; 7429 if (bp->hwrm_spec_code >= 0x10201) { 7430 if (link_info->auto_pause_setting & 7431 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE) 7432 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 7433 } else { 7434 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 7435 } 7436 link_info->advertising = link_info->auto_link_speeds; 7437 } else { 7438 link_info->req_link_speed = link_info->force_link_speed; 7439 link_info->req_duplex = link_info->duplex_setting; 7440 } 7441 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 7442 link_info->req_flow_ctrl = 7443 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH; 7444 else 7445 link_info->req_flow_ctrl = link_info->force_pause_setting; 7446 return rc; 7447 } 7448 7449 static int bnxt_get_max_irq(struct pci_dev *pdev) 7450 { 7451 u16 ctrl; 7452 7453 if (!pdev->msix_cap) 7454 return 1; 7455 7456 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 7457 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; 7458 } 7459 7460 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, 7461 int *max_cp) 7462 { 7463 int max_ring_grps = 0; 7464 7465 #ifdef CONFIG_BNXT_SRIOV 7466 if (!BNXT_PF(bp)) { 7467 *max_tx = bp->vf.max_tx_rings; 7468 *max_rx = bp->vf.max_rx_rings; 7469 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings); 7470 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs); 7471 max_ring_grps = bp->vf.max_hw_ring_grps; 7472 } else 7473 #endif 7474 { 7475 *max_tx = bp->pf.max_tx_rings; 7476 *max_rx = bp->pf.max_rx_rings; 7477 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings); 7478 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs); 7479 max_ring_grps = bp->pf.max_hw_ring_grps; 7480 } 7481 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) { 7482 *max_cp -= 1; 7483 *max_rx -= 2; 7484 } 7485 if (bp->flags & BNXT_FLAG_AGG_RINGS) 7486 *max_rx >>= 1; 7487 *max_rx = min_t(int, *max_rx, max_ring_grps); 7488 } 7489 7490 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared) 7491 { 7492 int rx, tx, cp; 7493 7494 _bnxt_get_max_rings(bp, &rx, &tx, &cp); 7495 if (!rx || !tx || !cp) 7496 return -ENOMEM; 7497 7498 *max_rx = rx; 7499 *max_tx = tx; 7500 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared); 7501 } 7502 7503 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx, 7504 bool shared) 7505 { 7506 int rc; 7507 7508 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 7509 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) { 7510 /* Not enough rings, try disabling agg rings. */ 7511 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 7512 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 7513 if (rc) 7514 return rc; 7515 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 7516 bp->dev->hw_features &= ~NETIF_F_LRO; 7517 bp->dev->features &= ~NETIF_F_LRO; 7518 bnxt_set_ring_params(bp); 7519 } 7520 7521 if (bp->flags & BNXT_FLAG_ROCE_CAP) { 7522 int max_cp, max_stat, max_irq; 7523 7524 /* Reserve minimum resources for RoCE */ 7525 max_cp = bnxt_get_max_func_cp_rings(bp); 7526 max_stat = bnxt_get_max_func_stat_ctxs(bp); 7527 max_irq = bnxt_get_max_func_irqs(bp); 7528 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS || 7529 max_irq <= BNXT_MIN_ROCE_CP_RINGS || 7530 max_stat <= BNXT_MIN_ROCE_STAT_CTXS) 7531 return 0; 7532 7533 max_cp -= BNXT_MIN_ROCE_CP_RINGS; 7534 max_irq -= BNXT_MIN_ROCE_CP_RINGS; 7535 max_stat -= BNXT_MIN_ROCE_STAT_CTXS; 7536 max_cp = min_t(int, max_cp, max_irq); 7537 max_cp = min_t(int, max_cp, max_stat); 7538 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared); 7539 if (rc) 7540 rc = 0; 7541 } 7542 return rc; 7543 } 7544 7545 static int bnxt_set_dflt_rings(struct bnxt *bp) 7546 { 7547 int dflt_rings, max_rx_rings, max_tx_rings, rc; 7548 bool sh = true; 7549 7550 if (sh) 7551 bp->flags |= BNXT_FLAG_SHARED_RINGS; 7552 dflt_rings = netif_get_num_default_rss_queues(); 7553 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh); 7554 if (rc) 7555 return rc; 7556 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings); 7557 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings); 7558 7559 rc = bnxt_hwrm_reserve_tx_rings(bp, &bp->tx_nr_rings_per_tc); 7560 if (rc) 7561 netdev_warn(bp->dev, "Unable to reserve tx rings\n"); 7562 7563 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 7564 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 7565 bp->tx_nr_rings + bp->rx_nr_rings; 7566 bp->num_stat_ctxs = bp->cp_nr_rings; 7567 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 7568 bp->rx_nr_rings++; 7569 bp->cp_nr_rings++; 7570 } 7571 return rc; 7572 } 7573 7574 void bnxt_restore_pf_fw_resources(struct bnxt *bp) 7575 { 7576 ASSERT_RTNL(); 7577 bnxt_hwrm_func_qcaps(bp); 7578 bnxt_subtract_ulp_resources(bp, BNXT_ROCE_ULP); 7579 } 7580 7581 static void bnxt_parse_log_pcie_link(struct bnxt *bp) 7582 { 7583 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN; 7584 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN; 7585 7586 if (pcie_get_minimum_link(bp->pdev, &speed, &width) || 7587 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) 7588 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n"); 7589 else 7590 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n", 7591 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : 7592 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : 7593 speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : 7594 "Unknown", width); 7595 } 7596 7597 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 7598 { 7599 static int version_printed; 7600 struct net_device *dev; 7601 struct bnxt *bp; 7602 int rc, max_irqs; 7603 7604 if (pci_is_bridge(pdev)) 7605 return -ENODEV; 7606 7607 if (version_printed++ == 0) 7608 pr_info("%s", version); 7609 7610 max_irqs = bnxt_get_max_irq(pdev); 7611 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs); 7612 if (!dev) 7613 return -ENOMEM; 7614 7615 bp = netdev_priv(dev); 7616 7617 if (bnxt_vf_pciid(ent->driver_data)) 7618 bp->flags |= BNXT_FLAG_VF; 7619 7620 if (pdev->msix_cap) 7621 bp->flags |= BNXT_FLAG_MSIX_CAP; 7622 7623 rc = bnxt_init_board(pdev, dev); 7624 if (rc < 0) 7625 goto init_err_free; 7626 7627 dev->netdev_ops = &bnxt_netdev_ops; 7628 dev->watchdog_timeo = BNXT_TX_TIMEOUT; 7629 dev->ethtool_ops = &bnxt_ethtool_ops; 7630 pci_set_drvdata(pdev, dev); 7631 7632 rc = bnxt_alloc_hwrm_resources(bp); 7633 if (rc) 7634 goto init_err_pci_clean; 7635 7636 mutex_init(&bp->hwrm_cmd_lock); 7637 rc = bnxt_hwrm_ver_get(bp); 7638 if (rc) 7639 goto init_err_pci_clean; 7640 7641 rc = bnxt_hwrm_func_reset(bp); 7642 if (rc) 7643 goto init_err_pci_clean; 7644 7645 bnxt_hwrm_fw_set_time(bp); 7646 7647 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 7648 NETIF_F_TSO | NETIF_F_TSO6 | 7649 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 7650 NETIF_F_GSO_IPXIP4 | 7651 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 7652 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH | 7653 NETIF_F_RXCSUM | NETIF_F_GRO; 7654 7655 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) 7656 dev->hw_features |= NETIF_F_LRO; 7657 7658 dev->hw_enc_features = 7659 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 7660 NETIF_F_TSO | NETIF_F_TSO6 | 7661 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 7662 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 7663 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL; 7664 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM | 7665 NETIF_F_GSO_GRE_CSUM; 7666 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA; 7667 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 7668 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX; 7669 dev->features |= dev->hw_features | NETIF_F_HIGHDMA; 7670 dev->priv_flags |= IFF_UNICAST_FLT; 7671 7672 /* MTU range: 60 - 9500 */ 7673 dev->min_mtu = ETH_ZLEN; 7674 dev->max_mtu = BNXT_MAX_MTU; 7675 7676 #ifdef CONFIG_BNXT_SRIOV 7677 init_waitqueue_head(&bp->sriov_cfg_wait); 7678 #endif 7679 bp->gro_func = bnxt_gro_func_5730x; 7680 if (BNXT_CHIP_NUM_57X1X(bp->chip_num)) 7681 bp->gro_func = bnxt_gro_func_5731x; 7682 7683 rc = bnxt_hwrm_func_drv_rgtr(bp); 7684 if (rc) 7685 goto init_err_pci_clean; 7686 7687 rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0); 7688 if (rc) 7689 goto init_err_pci_clean; 7690 7691 bp->ulp_probe = bnxt_ulp_probe; 7692 7693 /* Get the MAX capabilities for this function */ 7694 rc = bnxt_hwrm_func_qcaps(bp); 7695 if (rc) { 7696 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n", 7697 rc); 7698 rc = -1; 7699 goto init_err_pci_clean; 7700 } 7701 7702 rc = bnxt_hwrm_queue_qportcfg(bp); 7703 if (rc) { 7704 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n", 7705 rc); 7706 rc = -1; 7707 goto init_err_pci_clean; 7708 } 7709 7710 bnxt_hwrm_func_qcfg(bp); 7711 bnxt_hwrm_port_led_qcaps(bp); 7712 bnxt_ethtool_init(bp); 7713 bnxt_dcb_init(bp); 7714 7715 bnxt_set_rx_skb_mode(bp, false); 7716 bnxt_set_tpa_flags(bp); 7717 bnxt_set_ring_params(bp); 7718 bnxt_set_max_func_irqs(bp, max_irqs); 7719 rc = bnxt_set_dflt_rings(bp); 7720 if (rc) { 7721 netdev_err(bp->dev, "Not enough rings available.\n"); 7722 rc = -ENOMEM; 7723 goto init_err_pci_clean; 7724 } 7725 7726 /* Default RSS hash cfg. */ 7727 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 | 7728 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 | 7729 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 | 7730 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 7731 if (!BNXT_CHIP_NUM_57X0X(bp->chip_num) && 7732 !BNXT_CHIP_TYPE_NITRO_A0(bp) && 7733 bp->hwrm_spec_code >= 0x10501) { 7734 bp->flags |= BNXT_FLAG_UDP_RSS_CAP; 7735 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 | 7736 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 7737 } 7738 7739 bnxt_hwrm_vnic_qcaps(bp); 7740 if (bnxt_rfs_supported(bp)) { 7741 dev->hw_features |= NETIF_F_NTUPLE; 7742 if (bnxt_rfs_capable(bp)) { 7743 bp->flags |= BNXT_FLAG_RFS; 7744 dev->features |= NETIF_F_NTUPLE; 7745 } 7746 } 7747 7748 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX) 7749 bp->flags |= BNXT_FLAG_STRIP_VLAN; 7750 7751 rc = bnxt_probe_phy(bp); 7752 if (rc) 7753 goto init_err_pci_clean; 7754 7755 rc = bnxt_init_int_mode(bp); 7756 if (rc) 7757 goto init_err_pci_clean; 7758 7759 bnxt_get_wol_settings(bp); 7760 if (bp->flags & BNXT_FLAG_WOL_CAP) 7761 device_set_wakeup_enable(&pdev->dev, bp->wol); 7762 else 7763 device_set_wakeup_capable(&pdev->dev, false); 7764 7765 rc = register_netdev(dev); 7766 if (rc) 7767 goto init_err_clr_int; 7768 7769 netdev_info(dev, "%s found at mem %lx, node addr %pM\n", 7770 board_info[ent->driver_data].name, 7771 (long)pci_resource_start(pdev, 0), dev->dev_addr); 7772 7773 bnxt_parse_log_pcie_link(bp); 7774 7775 return 0; 7776 7777 init_err_clr_int: 7778 bnxt_clear_int_mode(bp); 7779 7780 init_err_pci_clean: 7781 bnxt_cleanup_pci(bp); 7782 7783 init_err_free: 7784 free_netdev(dev); 7785 return rc; 7786 } 7787 7788 static void bnxt_shutdown(struct pci_dev *pdev) 7789 { 7790 struct net_device *dev = pci_get_drvdata(pdev); 7791 struct bnxt *bp; 7792 7793 if (!dev) 7794 return; 7795 7796 rtnl_lock(); 7797 bp = netdev_priv(dev); 7798 if (!bp) 7799 goto shutdown_exit; 7800 7801 if (netif_running(dev)) 7802 dev_close(dev); 7803 7804 if (system_state == SYSTEM_POWER_OFF) { 7805 bnxt_clear_int_mode(bp); 7806 pci_wake_from_d3(pdev, bp->wol); 7807 pci_set_power_state(pdev, PCI_D3hot); 7808 } 7809 7810 shutdown_exit: 7811 rtnl_unlock(); 7812 } 7813 7814 #ifdef CONFIG_PM_SLEEP 7815 static int bnxt_suspend(struct device *device) 7816 { 7817 struct pci_dev *pdev = to_pci_dev(device); 7818 struct net_device *dev = pci_get_drvdata(pdev); 7819 struct bnxt *bp = netdev_priv(dev); 7820 int rc = 0; 7821 7822 rtnl_lock(); 7823 if (netif_running(dev)) { 7824 netif_device_detach(dev); 7825 rc = bnxt_close(dev); 7826 } 7827 bnxt_hwrm_func_drv_unrgtr(bp); 7828 rtnl_unlock(); 7829 return rc; 7830 } 7831 7832 static int bnxt_resume(struct device *device) 7833 { 7834 struct pci_dev *pdev = to_pci_dev(device); 7835 struct net_device *dev = pci_get_drvdata(pdev); 7836 struct bnxt *bp = netdev_priv(dev); 7837 int rc = 0; 7838 7839 rtnl_lock(); 7840 if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) { 7841 rc = -ENODEV; 7842 goto resume_exit; 7843 } 7844 rc = bnxt_hwrm_func_reset(bp); 7845 if (rc) { 7846 rc = -EBUSY; 7847 goto resume_exit; 7848 } 7849 bnxt_get_wol_settings(bp); 7850 if (netif_running(dev)) { 7851 rc = bnxt_open(dev); 7852 if (!rc) 7853 netif_device_attach(dev); 7854 } 7855 7856 resume_exit: 7857 rtnl_unlock(); 7858 return rc; 7859 } 7860 7861 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume); 7862 #define BNXT_PM_OPS (&bnxt_pm_ops) 7863 7864 #else 7865 7866 #define BNXT_PM_OPS NULL 7867 7868 #endif /* CONFIG_PM_SLEEP */ 7869 7870 /** 7871 * bnxt_io_error_detected - called when PCI error is detected 7872 * @pdev: Pointer to PCI device 7873 * @state: The current pci connection state 7874 * 7875 * This function is called after a PCI bus error affecting 7876 * this device has been detected. 7877 */ 7878 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev, 7879 pci_channel_state_t state) 7880 { 7881 struct net_device *netdev = pci_get_drvdata(pdev); 7882 struct bnxt *bp = netdev_priv(netdev); 7883 7884 netdev_info(netdev, "PCI I/O error detected\n"); 7885 7886 rtnl_lock(); 7887 netif_device_detach(netdev); 7888 7889 bnxt_ulp_stop(bp); 7890 7891 if (state == pci_channel_io_perm_failure) { 7892 rtnl_unlock(); 7893 return PCI_ERS_RESULT_DISCONNECT; 7894 } 7895 7896 if (netif_running(netdev)) 7897 bnxt_close(netdev); 7898 7899 pci_disable_device(pdev); 7900 rtnl_unlock(); 7901 7902 /* Request a slot slot reset. */ 7903 return PCI_ERS_RESULT_NEED_RESET; 7904 } 7905 7906 /** 7907 * bnxt_io_slot_reset - called after the pci bus has been reset. 7908 * @pdev: Pointer to PCI device 7909 * 7910 * Restart the card from scratch, as if from a cold-boot. 7911 * At this point, the card has exprienced a hard reset, 7912 * followed by fixups by BIOS, and has its config space 7913 * set up identically to what it was at cold boot. 7914 */ 7915 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev) 7916 { 7917 struct net_device *netdev = pci_get_drvdata(pdev); 7918 struct bnxt *bp = netdev_priv(netdev); 7919 int err = 0; 7920 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT; 7921 7922 netdev_info(bp->dev, "PCI Slot Reset\n"); 7923 7924 rtnl_lock(); 7925 7926 if (pci_enable_device(pdev)) { 7927 dev_err(&pdev->dev, 7928 "Cannot re-enable PCI device after reset.\n"); 7929 } else { 7930 pci_set_master(pdev); 7931 7932 err = bnxt_hwrm_func_reset(bp); 7933 if (!err && netif_running(netdev)) 7934 err = bnxt_open(netdev); 7935 7936 if (!err) { 7937 result = PCI_ERS_RESULT_RECOVERED; 7938 bnxt_ulp_start(bp); 7939 } 7940 } 7941 7942 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev)) 7943 dev_close(netdev); 7944 7945 rtnl_unlock(); 7946 7947 err = pci_cleanup_aer_uncorrect_error_status(pdev); 7948 if (err) { 7949 dev_err(&pdev->dev, 7950 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 7951 err); /* non-fatal, continue */ 7952 } 7953 7954 return PCI_ERS_RESULT_RECOVERED; 7955 } 7956 7957 /** 7958 * bnxt_io_resume - called when traffic can start flowing again. 7959 * @pdev: Pointer to PCI device 7960 * 7961 * This callback is called when the error recovery driver tells 7962 * us that its OK to resume normal operation. 7963 */ 7964 static void bnxt_io_resume(struct pci_dev *pdev) 7965 { 7966 struct net_device *netdev = pci_get_drvdata(pdev); 7967 7968 rtnl_lock(); 7969 7970 netif_device_attach(netdev); 7971 7972 rtnl_unlock(); 7973 } 7974 7975 static const struct pci_error_handlers bnxt_err_handler = { 7976 .error_detected = bnxt_io_error_detected, 7977 .slot_reset = bnxt_io_slot_reset, 7978 .resume = bnxt_io_resume 7979 }; 7980 7981 static struct pci_driver bnxt_pci_driver = { 7982 .name = DRV_MODULE_NAME, 7983 .id_table = bnxt_pci_tbl, 7984 .probe = bnxt_init_one, 7985 .remove = bnxt_remove_one, 7986 .shutdown = bnxt_shutdown, 7987 .driver.pm = BNXT_PM_OPS, 7988 .err_handler = &bnxt_err_handler, 7989 #if defined(CONFIG_BNXT_SRIOV) 7990 .sriov_configure = bnxt_sriov_configure, 7991 #endif 7992 }; 7993 7994 module_pci_driver(bnxt_pci_driver); 7995