1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2019 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 13 #include <linux/stringify.h> 14 #include <linux/kernel.h> 15 #include <linux/timer.h> 16 #include <linux/errno.h> 17 #include <linux/ioport.h> 18 #include <linux/slab.h> 19 #include <linux/vmalloc.h> 20 #include <linux/interrupt.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/etherdevice.h> 24 #include <linux/skbuff.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/bitops.h> 27 #include <linux/io.h> 28 #include <linux/irq.h> 29 #include <linux/delay.h> 30 #include <asm/byteorder.h> 31 #include <asm/page.h> 32 #include <linux/time.h> 33 #include <linux/mii.h> 34 #include <linux/mdio.h> 35 #include <linux/if.h> 36 #include <linux/if_vlan.h> 37 #include <linux/if_bridge.h> 38 #include <linux/rtc.h> 39 #include <linux/bpf.h> 40 #include <net/ip.h> 41 #include <net/tcp.h> 42 #include <net/udp.h> 43 #include <net/checksum.h> 44 #include <net/ip6_checksum.h> 45 #include <net/udp_tunnel.h> 46 #include <linux/workqueue.h> 47 #include <linux/prefetch.h> 48 #include <linux/cache.h> 49 #include <linux/log2.h> 50 #include <linux/aer.h> 51 #include <linux/bitmap.h> 52 #include <linux/cpu_rmap.h> 53 #include <linux/cpumask.h> 54 #include <net/pkt_cls.h> 55 #include <linux/hwmon.h> 56 #include <linux/hwmon-sysfs.h> 57 #include <net/page_pool.h> 58 59 #include "bnxt_hsi.h" 60 #include "bnxt.h" 61 #include "bnxt_ulp.h" 62 #include "bnxt_sriov.h" 63 #include "bnxt_ethtool.h" 64 #include "bnxt_dcb.h" 65 #include "bnxt_xdp.h" 66 #include "bnxt_vfr.h" 67 #include "bnxt_tc.h" 68 #include "bnxt_devlink.h" 69 #include "bnxt_debugfs.h" 70 71 #define BNXT_TX_TIMEOUT (5 * HZ) 72 73 static const char version[] = 74 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n"; 75 76 MODULE_LICENSE("GPL"); 77 MODULE_DESCRIPTION("Broadcom BCM573xx network driver"); 78 MODULE_VERSION(DRV_MODULE_VERSION); 79 80 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN) 81 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD 82 #define BNXT_RX_COPY_THRESH 256 83 84 #define BNXT_TX_PUSH_THRESH 164 85 86 enum board_idx { 87 BCM57301, 88 BCM57302, 89 BCM57304, 90 BCM57417_NPAR, 91 BCM58700, 92 BCM57311, 93 BCM57312, 94 BCM57402, 95 BCM57404, 96 BCM57406, 97 BCM57402_NPAR, 98 BCM57407, 99 BCM57412, 100 BCM57414, 101 BCM57416, 102 BCM57417, 103 BCM57412_NPAR, 104 BCM57314, 105 BCM57417_SFP, 106 BCM57416_SFP, 107 BCM57404_NPAR, 108 BCM57406_NPAR, 109 BCM57407_SFP, 110 BCM57407_NPAR, 111 BCM57414_NPAR, 112 BCM57416_NPAR, 113 BCM57452, 114 BCM57454, 115 BCM5745x_NPAR, 116 BCM57508, 117 BCM57504, 118 BCM57502, 119 BCM58802, 120 BCM58804, 121 BCM58808, 122 NETXTREME_E_VF, 123 NETXTREME_C_VF, 124 NETXTREME_S_VF, 125 NETXTREME_E_P5_VF, 126 }; 127 128 /* indexed by enum above */ 129 static const struct { 130 char *name; 131 } board_info[] = { 132 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" }, 133 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" }, 134 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 135 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" }, 136 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" }, 137 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" }, 138 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" }, 139 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" }, 140 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" }, 141 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" }, 142 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" }, 143 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" }, 144 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" }, 145 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" }, 146 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" }, 147 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" }, 148 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" }, 149 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" }, 150 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" }, 151 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" }, 152 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" }, 153 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" }, 154 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" }, 155 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" }, 156 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" }, 157 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" }, 158 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" }, 159 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 160 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" }, 161 [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, 162 [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" }, 163 [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" }, 164 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" }, 165 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 166 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" }, 167 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" }, 168 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" }, 169 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" }, 170 [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" }, 171 }; 172 173 static const struct pci_device_id bnxt_pci_tbl[] = { 174 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR }, 175 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR }, 176 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 }, 177 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR }, 178 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 }, 179 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 }, 180 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 }, 181 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR }, 182 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 }, 183 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 }, 184 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 }, 185 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 }, 186 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 }, 187 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 }, 188 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR }, 189 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 }, 190 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 }, 191 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 }, 192 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 }, 193 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 }, 194 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR }, 195 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 }, 196 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP }, 197 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP }, 198 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR }, 199 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR }, 200 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP }, 201 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR }, 202 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR }, 203 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR }, 204 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR }, 205 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR }, 206 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR }, 207 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 }, 208 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 }, 209 { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 }, 210 { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 }, 211 { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 }, 212 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 }, 213 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 }, 214 #ifdef CONFIG_BNXT_SRIOV 215 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF }, 216 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF }, 217 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF }, 218 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF }, 219 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF }, 220 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF }, 221 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF }, 222 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF }, 223 { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF }, 224 { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF }, 225 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF }, 226 #endif 227 { 0 } 228 }; 229 230 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl); 231 232 static const u16 bnxt_vf_req_snif[] = { 233 HWRM_FUNC_CFG, 234 HWRM_FUNC_VF_CFG, 235 HWRM_PORT_PHY_QCFG, 236 HWRM_CFA_L2_FILTER_ALLOC, 237 }; 238 239 static const u16 bnxt_async_events_arr[] = { 240 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE, 241 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD, 242 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED, 243 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE, 244 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE, 245 }; 246 247 static struct workqueue_struct *bnxt_pf_wq; 248 249 static bool bnxt_vf_pciid(enum board_idx idx) 250 { 251 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF || 252 idx == NETXTREME_S_VF || idx == NETXTREME_E_P5_VF); 253 } 254 255 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID) 256 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS) 257 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS) 258 259 #define BNXT_CP_DB_IRQ_DIS(db) \ 260 writel(DB_CP_IRQ_DIS_FLAGS, db) 261 262 #define BNXT_DB_CQ(db, idx) \ 263 writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell) 264 265 #define BNXT_DB_NQ_P5(db, idx) \ 266 writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell) 267 268 #define BNXT_DB_CQ_ARM(db, idx) \ 269 writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell) 270 271 #define BNXT_DB_NQ_ARM_P5(db, idx) \ 272 writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell) 273 274 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 275 { 276 if (bp->flags & BNXT_FLAG_CHIP_P5) 277 BNXT_DB_NQ_P5(db, idx); 278 else 279 BNXT_DB_CQ(db, idx); 280 } 281 282 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 283 { 284 if (bp->flags & BNXT_FLAG_CHIP_P5) 285 BNXT_DB_NQ_ARM_P5(db, idx); 286 else 287 BNXT_DB_CQ_ARM(db, idx); 288 } 289 290 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) 291 { 292 if (bp->flags & BNXT_FLAG_CHIP_P5) 293 writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx), 294 db->doorbell); 295 else 296 BNXT_DB_CQ(db, idx); 297 } 298 299 const u16 bnxt_lhint_arr[] = { 300 TX_BD_FLAGS_LHINT_512_AND_SMALLER, 301 TX_BD_FLAGS_LHINT_512_TO_1023, 302 TX_BD_FLAGS_LHINT_1024_TO_2047, 303 TX_BD_FLAGS_LHINT_1024_TO_2047, 304 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 305 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 306 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 307 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 308 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 309 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 310 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 311 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 312 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 313 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 314 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 315 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 316 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 317 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 318 TX_BD_FLAGS_LHINT_2048_AND_LARGER, 319 }; 320 321 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb) 322 { 323 struct metadata_dst *md_dst = skb_metadata_dst(skb); 324 325 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX) 326 return 0; 327 328 return md_dst->u.port_info.port_id; 329 } 330 331 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev) 332 { 333 struct bnxt *bp = netdev_priv(dev); 334 struct tx_bd *txbd; 335 struct tx_bd_ext *txbd1; 336 struct netdev_queue *txq; 337 int i; 338 dma_addr_t mapping; 339 unsigned int length, pad = 0; 340 u32 len, free_size, vlan_tag_flags, cfa_action, flags; 341 u16 prod, last_frag; 342 struct pci_dev *pdev = bp->pdev; 343 struct bnxt_tx_ring_info *txr; 344 struct bnxt_sw_tx_bd *tx_buf; 345 346 i = skb_get_queue_mapping(skb); 347 if (unlikely(i >= bp->tx_nr_rings)) { 348 dev_kfree_skb_any(skb); 349 return NETDEV_TX_OK; 350 } 351 352 txq = netdev_get_tx_queue(dev, i); 353 txr = &bp->tx_ring[bp->tx_ring_map[i]]; 354 prod = txr->tx_prod; 355 356 free_size = bnxt_tx_avail(bp, txr); 357 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) { 358 netif_tx_stop_queue(txq); 359 return NETDEV_TX_BUSY; 360 } 361 362 length = skb->len; 363 len = skb_headlen(skb); 364 last_frag = skb_shinfo(skb)->nr_frags; 365 366 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 367 368 txbd->tx_bd_opaque = prod; 369 370 tx_buf = &txr->tx_buf_ring[prod]; 371 tx_buf->skb = skb; 372 tx_buf->nr_frags = last_frag; 373 374 vlan_tag_flags = 0; 375 cfa_action = bnxt_xmit_get_cfa_action(skb); 376 if (skb_vlan_tag_present(skb)) { 377 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN | 378 skb_vlan_tag_get(skb); 379 /* Currently supports 8021Q, 8021AD vlan offloads 380 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated 381 */ 382 if (skb->vlan_proto == htons(ETH_P_8021Q)) 383 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT; 384 } 385 386 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) { 387 struct tx_push_buffer *tx_push_buf = txr->tx_push; 388 struct tx_push_bd *tx_push = &tx_push_buf->push_bd; 389 struct tx_bd_ext *tx_push1 = &tx_push->txbd2; 390 void __iomem *db = txr->tx_db.doorbell; 391 void *pdata = tx_push_buf->data; 392 u64 *end; 393 int j, push_len; 394 395 /* Set COAL_NOW to be ready quickly for the next push */ 396 tx_push->tx_bd_len_flags_type = 397 cpu_to_le32((length << TX_BD_LEN_SHIFT) | 398 TX_BD_TYPE_LONG_TX_BD | 399 TX_BD_FLAGS_LHINT_512_AND_SMALLER | 400 TX_BD_FLAGS_COAL_NOW | 401 TX_BD_FLAGS_PACKET_END | 402 (2 << TX_BD_FLAGS_BD_CNT_SHIFT)); 403 404 if (skb->ip_summed == CHECKSUM_PARTIAL) 405 tx_push1->tx_bd_hsize_lflags = 406 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 407 else 408 tx_push1->tx_bd_hsize_lflags = 0; 409 410 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 411 tx_push1->tx_bd_cfa_action = 412 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); 413 414 end = pdata + length; 415 end = PTR_ALIGN(end, 8) - 1; 416 *end = 0; 417 418 skb_copy_from_linear_data(skb, pdata, len); 419 pdata += len; 420 for (j = 0; j < last_frag; j++) { 421 skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; 422 void *fptr; 423 424 fptr = skb_frag_address_safe(frag); 425 if (!fptr) 426 goto normal_tx; 427 428 memcpy(pdata, fptr, skb_frag_size(frag)); 429 pdata += skb_frag_size(frag); 430 } 431 432 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type; 433 txbd->tx_bd_haddr = txr->data_mapping; 434 prod = NEXT_TX(prod); 435 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 436 memcpy(txbd, tx_push1, sizeof(*txbd)); 437 prod = NEXT_TX(prod); 438 tx_push->doorbell = 439 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod); 440 txr->tx_prod = prod; 441 442 tx_buf->is_push = 1; 443 netdev_tx_sent_queue(txq, skb->len); 444 wmb(); /* Sync is_push and byte queue before pushing data */ 445 446 push_len = (length + sizeof(*tx_push) + 7) / 8; 447 if (push_len > 16) { 448 __iowrite64_copy(db, tx_push_buf, 16); 449 __iowrite32_copy(db + 4, tx_push_buf + 1, 450 (push_len - 16) << 1); 451 } else { 452 __iowrite64_copy(db, tx_push_buf, push_len); 453 } 454 455 goto tx_done; 456 } 457 458 normal_tx: 459 if (length < BNXT_MIN_PKT_SIZE) { 460 pad = BNXT_MIN_PKT_SIZE - length; 461 if (skb_pad(skb, pad)) { 462 /* SKB already freed. */ 463 tx_buf->skb = NULL; 464 return NETDEV_TX_OK; 465 } 466 length = BNXT_MIN_PKT_SIZE; 467 } 468 469 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE); 470 471 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) { 472 dev_kfree_skb_any(skb); 473 tx_buf->skb = NULL; 474 return NETDEV_TX_OK; 475 } 476 477 dma_unmap_addr_set(tx_buf, mapping, mapping); 478 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD | 479 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT); 480 481 txbd->tx_bd_haddr = cpu_to_le64(mapping); 482 483 prod = NEXT_TX(prod); 484 txbd1 = (struct tx_bd_ext *) 485 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 486 487 txbd1->tx_bd_hsize_lflags = 0; 488 if (skb_is_gso(skb)) { 489 u32 hdr_len; 490 491 if (skb->encapsulation) 492 hdr_len = skb_inner_network_offset(skb) + 493 skb_inner_network_header_len(skb) + 494 inner_tcp_hdrlen(skb); 495 else 496 hdr_len = skb_transport_offset(skb) + 497 tcp_hdrlen(skb); 498 499 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO | 500 TX_BD_FLAGS_T_IPID | 501 (hdr_len << (TX_BD_HSIZE_SHIFT - 1))); 502 length = skb_shinfo(skb)->gso_size; 503 txbd1->tx_bd_mss = cpu_to_le32(length); 504 length += hdr_len; 505 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 506 txbd1->tx_bd_hsize_lflags = 507 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); 508 txbd1->tx_bd_mss = 0; 509 } 510 511 length >>= 9; 512 if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) { 513 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n", 514 skb->len); 515 i = 0; 516 goto tx_dma_error; 517 } 518 flags |= bnxt_lhint_arr[length]; 519 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 520 521 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); 522 txbd1->tx_bd_cfa_action = 523 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT); 524 for (i = 0; i < last_frag; i++) { 525 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 526 527 prod = NEXT_TX(prod); 528 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; 529 530 len = skb_frag_size(frag); 531 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len, 532 DMA_TO_DEVICE); 533 534 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) 535 goto tx_dma_error; 536 537 tx_buf = &txr->tx_buf_ring[prod]; 538 dma_unmap_addr_set(tx_buf, mapping, mapping); 539 540 txbd->tx_bd_haddr = cpu_to_le64(mapping); 541 542 flags = len << TX_BD_LEN_SHIFT; 543 txbd->tx_bd_len_flags_type = cpu_to_le32(flags); 544 } 545 546 flags &= ~TX_BD_LEN; 547 txbd->tx_bd_len_flags_type = 548 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags | 549 TX_BD_FLAGS_PACKET_END); 550 551 netdev_tx_sent_queue(txq, skb->len); 552 553 /* Sync BD data before updating doorbell */ 554 wmb(); 555 556 prod = NEXT_TX(prod); 557 txr->tx_prod = prod; 558 559 if (!netdev_xmit_more() || netif_xmit_stopped(txq)) 560 bnxt_db_write(bp, &txr->tx_db, prod); 561 562 tx_done: 563 564 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) { 565 if (netdev_xmit_more() && !tx_buf->is_push) 566 bnxt_db_write(bp, &txr->tx_db, prod); 567 568 netif_tx_stop_queue(txq); 569 570 /* netif_tx_stop_queue() must be done before checking 571 * tx index in bnxt_tx_avail() below, because in 572 * bnxt_tx_int(), we update tx index before checking for 573 * netif_tx_queue_stopped(). 574 */ 575 smp_mb(); 576 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh) 577 netif_tx_wake_queue(txq); 578 } 579 return NETDEV_TX_OK; 580 581 tx_dma_error: 582 last_frag = i; 583 584 /* start back at beginning and unmap skb */ 585 prod = txr->tx_prod; 586 tx_buf = &txr->tx_buf_ring[prod]; 587 tx_buf->skb = NULL; 588 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 589 skb_headlen(skb), PCI_DMA_TODEVICE); 590 prod = NEXT_TX(prod); 591 592 /* unmap remaining mapped pages */ 593 for (i = 0; i < last_frag; i++) { 594 prod = NEXT_TX(prod); 595 tx_buf = &txr->tx_buf_ring[prod]; 596 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 597 skb_frag_size(&skb_shinfo(skb)->frags[i]), 598 PCI_DMA_TODEVICE); 599 } 600 601 dev_kfree_skb_any(skb); 602 return NETDEV_TX_OK; 603 } 604 605 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts) 606 { 607 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 608 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index); 609 u16 cons = txr->tx_cons; 610 struct pci_dev *pdev = bp->pdev; 611 int i; 612 unsigned int tx_bytes = 0; 613 614 for (i = 0; i < nr_pkts; i++) { 615 struct bnxt_sw_tx_bd *tx_buf; 616 struct sk_buff *skb; 617 int j, last; 618 619 tx_buf = &txr->tx_buf_ring[cons]; 620 cons = NEXT_TX(cons); 621 skb = tx_buf->skb; 622 tx_buf->skb = NULL; 623 624 if (tx_buf->is_push) { 625 tx_buf->is_push = 0; 626 goto next_tx_int; 627 } 628 629 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), 630 skb_headlen(skb), PCI_DMA_TODEVICE); 631 last = tx_buf->nr_frags; 632 633 for (j = 0; j < last; j++) { 634 cons = NEXT_TX(cons); 635 tx_buf = &txr->tx_buf_ring[cons]; 636 dma_unmap_page( 637 &pdev->dev, 638 dma_unmap_addr(tx_buf, mapping), 639 skb_frag_size(&skb_shinfo(skb)->frags[j]), 640 PCI_DMA_TODEVICE); 641 } 642 643 next_tx_int: 644 cons = NEXT_TX(cons); 645 646 tx_bytes += skb->len; 647 dev_kfree_skb_any(skb); 648 } 649 650 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes); 651 txr->tx_cons = cons; 652 653 /* Need to make the tx_cons update visible to bnxt_start_xmit() 654 * before checking for netif_tx_queue_stopped(). Without the 655 * memory barrier, there is a small possibility that bnxt_start_xmit() 656 * will miss it and cause the queue to be stopped forever. 657 */ 658 smp_mb(); 659 660 if (unlikely(netif_tx_queue_stopped(txq)) && 661 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) { 662 __netif_tx_lock(txq, smp_processor_id()); 663 if (netif_tx_queue_stopped(txq) && 664 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh && 665 txr->dev_state != BNXT_DEV_STATE_CLOSING) 666 netif_tx_wake_queue(txq); 667 __netif_tx_unlock(txq); 668 } 669 } 670 671 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping, 672 struct bnxt_rx_ring_info *rxr, 673 gfp_t gfp) 674 { 675 struct device *dev = &bp->pdev->dev; 676 struct page *page; 677 678 page = page_pool_dev_alloc_pages(rxr->page_pool); 679 if (!page) 680 return NULL; 681 682 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir, 683 DMA_ATTR_WEAK_ORDERING); 684 if (dma_mapping_error(dev, *mapping)) { 685 page_pool_recycle_direct(rxr->page_pool, page); 686 return NULL; 687 } 688 *mapping += bp->rx_dma_offset; 689 return page; 690 } 691 692 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping, 693 gfp_t gfp) 694 { 695 u8 *data; 696 struct pci_dev *pdev = bp->pdev; 697 698 data = kmalloc(bp->rx_buf_size, gfp); 699 if (!data) 700 return NULL; 701 702 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset, 703 bp->rx_buf_use_size, bp->rx_dir, 704 DMA_ATTR_WEAK_ORDERING); 705 706 if (dma_mapping_error(&pdev->dev, *mapping)) { 707 kfree(data); 708 data = NULL; 709 } 710 return data; 711 } 712 713 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 714 u16 prod, gfp_t gfp) 715 { 716 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 717 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod]; 718 dma_addr_t mapping; 719 720 if (BNXT_RX_PAGE_MODE(bp)) { 721 struct page *page = 722 __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp); 723 724 if (!page) 725 return -ENOMEM; 726 727 rx_buf->data = page; 728 rx_buf->data_ptr = page_address(page) + bp->rx_offset; 729 } else { 730 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp); 731 732 if (!data) 733 return -ENOMEM; 734 735 rx_buf->data = data; 736 rx_buf->data_ptr = data + bp->rx_offset; 737 } 738 rx_buf->mapping = mapping; 739 740 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 741 return 0; 742 } 743 744 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data) 745 { 746 u16 prod = rxr->rx_prod; 747 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 748 struct rx_bd *cons_bd, *prod_bd; 749 750 prod_rx_buf = &rxr->rx_buf_ring[prod]; 751 cons_rx_buf = &rxr->rx_buf_ring[cons]; 752 753 prod_rx_buf->data = data; 754 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr; 755 756 prod_rx_buf->mapping = cons_rx_buf->mapping; 757 758 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 759 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; 760 761 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr; 762 } 763 764 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) 765 { 766 u16 next, max = rxr->rx_agg_bmap_size; 767 768 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx); 769 if (next >= max) 770 next = find_first_zero_bit(rxr->rx_agg_bmap, max); 771 return next; 772 } 773 774 static inline int bnxt_alloc_rx_page(struct bnxt *bp, 775 struct bnxt_rx_ring_info *rxr, 776 u16 prod, gfp_t gfp) 777 { 778 struct rx_bd *rxbd = 779 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 780 struct bnxt_sw_rx_agg_bd *rx_agg_buf; 781 struct pci_dev *pdev = bp->pdev; 782 struct page *page; 783 dma_addr_t mapping; 784 u16 sw_prod = rxr->rx_sw_agg_prod; 785 unsigned int offset = 0; 786 787 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) { 788 page = rxr->rx_page; 789 if (!page) { 790 page = alloc_page(gfp); 791 if (!page) 792 return -ENOMEM; 793 rxr->rx_page = page; 794 rxr->rx_page_offset = 0; 795 } 796 offset = rxr->rx_page_offset; 797 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE; 798 if (rxr->rx_page_offset == PAGE_SIZE) 799 rxr->rx_page = NULL; 800 else 801 get_page(page); 802 } else { 803 page = alloc_page(gfp); 804 if (!page) 805 return -ENOMEM; 806 } 807 808 mapping = dma_map_page_attrs(&pdev->dev, page, offset, 809 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE, 810 DMA_ATTR_WEAK_ORDERING); 811 if (dma_mapping_error(&pdev->dev, mapping)) { 812 __free_page(page); 813 return -EIO; 814 } 815 816 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 817 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 818 819 __set_bit(sw_prod, rxr->rx_agg_bmap); 820 rx_agg_buf = &rxr->rx_agg_ring[sw_prod]; 821 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod); 822 823 rx_agg_buf->page = page; 824 rx_agg_buf->offset = offset; 825 rx_agg_buf->mapping = mapping; 826 rxbd->rx_bd_haddr = cpu_to_le64(mapping); 827 rxbd->rx_bd_opaque = sw_prod; 828 return 0; 829 } 830 831 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 cp_cons, 832 u32 agg_bufs) 833 { 834 struct bnxt_napi *bnapi = cpr->bnapi; 835 struct bnxt *bp = bnapi->bp; 836 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 837 u16 prod = rxr->rx_agg_prod; 838 u16 sw_prod = rxr->rx_sw_agg_prod; 839 u32 i; 840 841 for (i = 0; i < agg_bufs; i++) { 842 u16 cons; 843 struct rx_agg_cmp *agg; 844 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf; 845 struct rx_bd *prod_bd; 846 struct page *page; 847 848 agg = (struct rx_agg_cmp *) 849 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 850 cons = agg->rx_agg_cmp_opaque; 851 __clear_bit(cons, rxr->rx_agg_bmap); 852 853 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) 854 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); 855 856 __set_bit(sw_prod, rxr->rx_agg_bmap); 857 prod_rx_buf = &rxr->rx_agg_ring[sw_prod]; 858 cons_rx_buf = &rxr->rx_agg_ring[cons]; 859 860 /* It is possible for sw_prod to be equal to cons, so 861 * set cons_rx_buf->page to NULL first. 862 */ 863 page = cons_rx_buf->page; 864 cons_rx_buf->page = NULL; 865 prod_rx_buf->page = page; 866 prod_rx_buf->offset = cons_rx_buf->offset; 867 868 prod_rx_buf->mapping = cons_rx_buf->mapping; 869 870 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 871 872 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping); 873 prod_bd->rx_bd_opaque = sw_prod; 874 875 prod = NEXT_RX_AGG(prod); 876 sw_prod = NEXT_RX_AGG(sw_prod); 877 cp_cons = NEXT_CMP(cp_cons); 878 } 879 rxr->rx_agg_prod = prod; 880 rxr->rx_sw_agg_prod = sw_prod; 881 } 882 883 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp, 884 struct bnxt_rx_ring_info *rxr, 885 u16 cons, void *data, u8 *data_ptr, 886 dma_addr_t dma_addr, 887 unsigned int offset_and_len) 888 { 889 unsigned int payload = offset_and_len >> 16; 890 unsigned int len = offset_and_len & 0xffff; 891 struct skb_frag_struct *frag; 892 struct page *page = data; 893 u16 prod = rxr->rx_prod; 894 struct sk_buff *skb; 895 int off, err; 896 897 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 898 if (unlikely(err)) { 899 bnxt_reuse_rx_data(rxr, cons, data); 900 return NULL; 901 } 902 dma_addr -= bp->rx_dma_offset; 903 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir, 904 DMA_ATTR_WEAK_ORDERING); 905 906 if (unlikely(!payload)) 907 payload = eth_get_headlen(bp->dev, data_ptr, len); 908 909 skb = napi_alloc_skb(&rxr->bnapi->napi, payload); 910 if (!skb) { 911 __free_page(page); 912 return NULL; 913 } 914 915 off = (void *)data_ptr - page_address(page); 916 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE); 917 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN, 918 payload + NET_IP_ALIGN); 919 920 frag = &skb_shinfo(skb)->frags[0]; 921 skb_frag_size_sub(frag, payload); 922 frag->page_offset += payload; 923 skb->data_len -= payload; 924 skb->tail += payload; 925 926 return skb; 927 } 928 929 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp, 930 struct bnxt_rx_ring_info *rxr, u16 cons, 931 void *data, u8 *data_ptr, 932 dma_addr_t dma_addr, 933 unsigned int offset_and_len) 934 { 935 u16 prod = rxr->rx_prod; 936 struct sk_buff *skb; 937 int err; 938 939 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 940 if (unlikely(err)) { 941 bnxt_reuse_rx_data(rxr, cons, data); 942 return NULL; 943 } 944 945 skb = build_skb(data, 0); 946 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, 947 bp->rx_dir, DMA_ATTR_WEAK_ORDERING); 948 if (!skb) { 949 kfree(data); 950 return NULL; 951 } 952 953 skb_reserve(skb, bp->rx_offset); 954 skb_put(skb, offset_and_len & 0xffff); 955 return skb; 956 } 957 958 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, 959 struct bnxt_cp_ring_info *cpr, 960 struct sk_buff *skb, u16 cp_cons, 961 u32 agg_bufs) 962 { 963 struct bnxt_napi *bnapi = cpr->bnapi; 964 struct pci_dev *pdev = bp->pdev; 965 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 966 u16 prod = rxr->rx_agg_prod; 967 u32 i; 968 969 for (i = 0; i < agg_bufs; i++) { 970 u16 cons, frag_len; 971 struct rx_agg_cmp *agg; 972 struct bnxt_sw_rx_agg_bd *cons_rx_buf; 973 struct page *page; 974 dma_addr_t mapping; 975 976 agg = (struct rx_agg_cmp *) 977 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 978 cons = agg->rx_agg_cmp_opaque; 979 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) & 980 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT; 981 982 cons_rx_buf = &rxr->rx_agg_ring[cons]; 983 skb_fill_page_desc(skb, i, cons_rx_buf->page, 984 cons_rx_buf->offset, frag_len); 985 __clear_bit(cons, rxr->rx_agg_bmap); 986 987 /* It is possible for bnxt_alloc_rx_page() to allocate 988 * a sw_prod index that equals the cons index, so we 989 * need to clear the cons entry now. 990 */ 991 mapping = cons_rx_buf->mapping; 992 page = cons_rx_buf->page; 993 cons_rx_buf->page = NULL; 994 995 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) { 996 struct skb_shared_info *shinfo; 997 unsigned int nr_frags; 998 999 shinfo = skb_shinfo(skb); 1000 nr_frags = --shinfo->nr_frags; 1001 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL); 1002 1003 dev_kfree_skb(skb); 1004 1005 cons_rx_buf->page = page; 1006 1007 /* Update prod since possibly some pages have been 1008 * allocated already. 1009 */ 1010 rxr->rx_agg_prod = prod; 1011 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs - i); 1012 return NULL; 1013 } 1014 1015 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE, 1016 PCI_DMA_FROMDEVICE, 1017 DMA_ATTR_WEAK_ORDERING); 1018 1019 skb->data_len += frag_len; 1020 skb->len += frag_len; 1021 skb->truesize += PAGE_SIZE; 1022 1023 prod = NEXT_RX_AGG(prod); 1024 cp_cons = NEXT_CMP(cp_cons); 1025 } 1026 rxr->rx_agg_prod = prod; 1027 return skb; 1028 } 1029 1030 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1031 u8 agg_bufs, u32 *raw_cons) 1032 { 1033 u16 last; 1034 struct rx_agg_cmp *agg; 1035 1036 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs); 1037 last = RING_CMP(*raw_cons); 1038 agg = (struct rx_agg_cmp *) 1039 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)]; 1040 return RX_AGG_CMP_VALID(agg, *raw_cons); 1041 } 1042 1043 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data, 1044 unsigned int len, 1045 dma_addr_t mapping) 1046 { 1047 struct bnxt *bp = bnapi->bp; 1048 struct pci_dev *pdev = bp->pdev; 1049 struct sk_buff *skb; 1050 1051 skb = napi_alloc_skb(&bnapi->napi, len); 1052 if (!skb) 1053 return NULL; 1054 1055 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh, 1056 bp->rx_dir); 1057 1058 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN, 1059 len + NET_IP_ALIGN); 1060 1061 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh, 1062 bp->rx_dir); 1063 1064 skb_put(skb, len); 1065 return skb; 1066 } 1067 1068 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1069 u32 *raw_cons, void *cmp) 1070 { 1071 struct rx_cmp *rxcmp = cmp; 1072 u32 tmp_raw_cons = *raw_cons; 1073 u8 cmp_type, agg_bufs = 0; 1074 1075 cmp_type = RX_CMP_TYPE(rxcmp); 1076 1077 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 1078 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & 1079 RX_CMP_AGG_BUFS) >> 1080 RX_CMP_AGG_BUFS_SHIFT; 1081 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1082 struct rx_tpa_end_cmp *tpa_end = cmp; 1083 1084 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & 1085 RX_TPA_END_CMP_AGG_BUFS) >> 1086 RX_TPA_END_CMP_AGG_BUFS_SHIFT; 1087 } 1088 1089 if (agg_bufs) { 1090 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1091 return -EBUSY; 1092 } 1093 *raw_cons = tmp_raw_cons; 1094 return 0; 1095 } 1096 1097 static void bnxt_queue_sp_work(struct bnxt *bp) 1098 { 1099 if (BNXT_PF(bp)) 1100 queue_work(bnxt_pf_wq, &bp->sp_task); 1101 else 1102 schedule_work(&bp->sp_task); 1103 } 1104 1105 static void bnxt_cancel_sp_work(struct bnxt *bp) 1106 { 1107 if (BNXT_PF(bp)) 1108 flush_workqueue(bnxt_pf_wq); 1109 else 1110 cancel_work_sync(&bp->sp_task); 1111 } 1112 1113 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) 1114 { 1115 if (!rxr->bnapi->in_reset) { 1116 rxr->bnapi->in_reset = true; 1117 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 1118 bnxt_queue_sp_work(bp); 1119 } 1120 rxr->rx_next_cons = 0xffff; 1121 } 1122 1123 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 1124 struct rx_tpa_start_cmp *tpa_start, 1125 struct rx_tpa_start_cmp_ext *tpa_start1) 1126 { 1127 u8 agg_id = TPA_START_AGG_ID(tpa_start); 1128 u16 cons, prod; 1129 struct bnxt_tpa_info *tpa_info; 1130 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; 1131 struct rx_bd *prod_bd; 1132 dma_addr_t mapping; 1133 1134 cons = tpa_start->rx_tpa_start_cmp_opaque; 1135 prod = rxr->rx_prod; 1136 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1137 prod_rx_buf = &rxr->rx_buf_ring[prod]; 1138 tpa_info = &rxr->rx_tpa[agg_id]; 1139 1140 if (unlikely(cons != rxr->rx_next_cons)) { 1141 netdev_warn(bp->dev, "TPA cons %x != expected cons %x\n", 1142 cons, rxr->rx_next_cons); 1143 bnxt_sched_reset(bp, rxr); 1144 return; 1145 } 1146 /* Store cfa_code in tpa_info to use in tpa_end 1147 * completion processing. 1148 */ 1149 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1); 1150 prod_rx_buf->data = tpa_info->data; 1151 prod_rx_buf->data_ptr = tpa_info->data_ptr; 1152 1153 mapping = tpa_info->mapping; 1154 prod_rx_buf->mapping = mapping; 1155 1156 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; 1157 1158 prod_bd->rx_bd_haddr = cpu_to_le64(mapping); 1159 1160 tpa_info->data = cons_rx_buf->data; 1161 tpa_info->data_ptr = cons_rx_buf->data_ptr; 1162 cons_rx_buf->data = NULL; 1163 tpa_info->mapping = cons_rx_buf->mapping; 1164 1165 tpa_info->len = 1166 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >> 1167 RX_TPA_START_CMP_LEN_SHIFT; 1168 if (likely(TPA_START_HASH_VALID(tpa_start))) { 1169 u32 hash_type = TPA_START_HASH_TYPE(tpa_start); 1170 1171 tpa_info->hash_type = PKT_HASH_TYPE_L4; 1172 tpa_info->gso_type = SKB_GSO_TCPV4; 1173 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1174 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1)) 1175 tpa_info->gso_type = SKB_GSO_TCPV6; 1176 tpa_info->rss_hash = 1177 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash); 1178 } else { 1179 tpa_info->hash_type = PKT_HASH_TYPE_NONE; 1180 tpa_info->gso_type = 0; 1181 if (netif_msg_rx_err(bp)) 1182 netdev_warn(bp->dev, "TPA packet without valid hash\n"); 1183 } 1184 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2); 1185 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata); 1186 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info); 1187 1188 rxr->rx_prod = NEXT_RX(prod); 1189 cons = NEXT_RX(cons); 1190 rxr->rx_next_cons = NEXT_RX(cons); 1191 cons_rx_buf = &rxr->rx_buf_ring[cons]; 1192 1193 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data); 1194 rxr->rx_prod = NEXT_RX(rxr->rx_prod); 1195 cons_rx_buf->data = NULL; 1196 } 1197 1198 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 cp_cons, 1199 u32 agg_bufs) 1200 { 1201 if (agg_bufs) 1202 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs); 1203 } 1204 1205 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info, 1206 int payload_off, int tcp_ts, 1207 struct sk_buff *skb) 1208 { 1209 #ifdef CONFIG_INET 1210 struct tcphdr *th; 1211 int len, nw_off; 1212 u16 outer_ip_off, inner_ip_off, inner_mac_off; 1213 u32 hdr_info = tpa_info->hdr_info; 1214 bool loopback = false; 1215 1216 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info); 1217 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info); 1218 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info); 1219 1220 /* If the packet is an internal loopback packet, the offsets will 1221 * have an extra 4 bytes. 1222 */ 1223 if (inner_mac_off == 4) { 1224 loopback = true; 1225 } else if (inner_mac_off > 4) { 1226 __be16 proto = *((__be16 *)(skb->data + inner_ip_off - 1227 ETH_HLEN - 2)); 1228 1229 /* We only support inner iPv4/ipv6. If we don't see the 1230 * correct protocol ID, it must be a loopback packet where 1231 * the offsets are off by 4. 1232 */ 1233 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6)) 1234 loopback = true; 1235 } 1236 if (loopback) { 1237 /* internal loopback packet, subtract all offsets by 4 */ 1238 inner_ip_off -= 4; 1239 inner_mac_off -= 4; 1240 outer_ip_off -= 4; 1241 } 1242 1243 nw_off = inner_ip_off - ETH_HLEN; 1244 skb_set_network_header(skb, nw_off); 1245 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) { 1246 struct ipv6hdr *iph = ipv6_hdr(skb); 1247 1248 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1249 len = skb->len - skb_transport_offset(skb); 1250 th = tcp_hdr(skb); 1251 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1252 } else { 1253 struct iphdr *iph = ip_hdr(skb); 1254 1255 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1256 len = skb->len - skb_transport_offset(skb); 1257 th = tcp_hdr(skb); 1258 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1259 } 1260 1261 if (inner_mac_off) { /* tunnel */ 1262 struct udphdr *uh = NULL; 1263 __be16 proto = *((__be16 *)(skb->data + outer_ip_off - 1264 ETH_HLEN - 2)); 1265 1266 if (proto == htons(ETH_P_IP)) { 1267 struct iphdr *iph = (struct iphdr *)skb->data; 1268 1269 if (iph->protocol == IPPROTO_UDP) 1270 uh = (struct udphdr *)(iph + 1); 1271 } else { 1272 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; 1273 1274 if (iph->nexthdr == IPPROTO_UDP) 1275 uh = (struct udphdr *)(iph + 1); 1276 } 1277 if (uh) { 1278 if (uh->check) 1279 skb_shinfo(skb)->gso_type |= 1280 SKB_GSO_UDP_TUNNEL_CSUM; 1281 else 1282 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; 1283 } 1284 } 1285 #endif 1286 return skb; 1287 } 1288 1289 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr)) 1290 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr)) 1291 1292 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info, 1293 int payload_off, int tcp_ts, 1294 struct sk_buff *skb) 1295 { 1296 #ifdef CONFIG_INET 1297 struct tcphdr *th; 1298 int len, nw_off, tcp_opt_len = 0; 1299 1300 if (tcp_ts) 1301 tcp_opt_len = 12; 1302 1303 if (tpa_info->gso_type == SKB_GSO_TCPV4) { 1304 struct iphdr *iph; 1305 1306 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len - 1307 ETH_HLEN; 1308 skb_set_network_header(skb, nw_off); 1309 iph = ip_hdr(skb); 1310 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); 1311 len = skb->len - skb_transport_offset(skb); 1312 th = tcp_hdr(skb); 1313 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); 1314 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) { 1315 struct ipv6hdr *iph; 1316 1317 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len - 1318 ETH_HLEN; 1319 skb_set_network_header(skb, nw_off); 1320 iph = ipv6_hdr(skb); 1321 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); 1322 len = skb->len - skb_transport_offset(skb); 1323 th = tcp_hdr(skb); 1324 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); 1325 } else { 1326 dev_kfree_skb_any(skb); 1327 return NULL; 1328 } 1329 1330 if (nw_off) { /* tunnel */ 1331 struct udphdr *uh = NULL; 1332 1333 if (skb->protocol == htons(ETH_P_IP)) { 1334 struct iphdr *iph = (struct iphdr *)skb->data; 1335 1336 if (iph->protocol == IPPROTO_UDP) 1337 uh = (struct udphdr *)(iph + 1); 1338 } else { 1339 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; 1340 1341 if (iph->nexthdr == IPPROTO_UDP) 1342 uh = (struct udphdr *)(iph + 1); 1343 } 1344 if (uh) { 1345 if (uh->check) 1346 skb_shinfo(skb)->gso_type |= 1347 SKB_GSO_UDP_TUNNEL_CSUM; 1348 else 1349 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; 1350 } 1351 } 1352 #endif 1353 return skb; 1354 } 1355 1356 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp, 1357 struct bnxt_tpa_info *tpa_info, 1358 struct rx_tpa_end_cmp *tpa_end, 1359 struct rx_tpa_end_cmp_ext *tpa_end1, 1360 struct sk_buff *skb) 1361 { 1362 #ifdef CONFIG_INET 1363 int payload_off; 1364 u16 segs; 1365 1366 segs = TPA_END_TPA_SEGS(tpa_end); 1367 if (segs == 1) 1368 return skb; 1369 1370 NAPI_GRO_CB(skb)->count = segs; 1371 skb_shinfo(skb)->gso_size = 1372 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len); 1373 skb_shinfo(skb)->gso_type = tpa_info->gso_type; 1374 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & 1375 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> 1376 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT; 1377 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb); 1378 if (likely(skb)) 1379 tcp_gro_complete(skb); 1380 #endif 1381 return skb; 1382 } 1383 1384 /* Given the cfa_code of a received packet determine which 1385 * netdev (vf-rep or PF) the packet is destined to. 1386 */ 1387 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code) 1388 { 1389 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code); 1390 1391 /* if vf-rep dev is NULL, the must belongs to the PF */ 1392 return dev ? dev : bp->dev; 1393 } 1394 1395 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp, 1396 struct bnxt_cp_ring_info *cpr, 1397 u32 *raw_cons, 1398 struct rx_tpa_end_cmp *tpa_end, 1399 struct rx_tpa_end_cmp_ext *tpa_end1, 1400 u8 *event) 1401 { 1402 struct bnxt_napi *bnapi = cpr->bnapi; 1403 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1404 u8 agg_id = TPA_END_AGG_ID(tpa_end); 1405 u8 *data_ptr, agg_bufs; 1406 u16 cp_cons = RING_CMP(*raw_cons); 1407 unsigned int len; 1408 struct bnxt_tpa_info *tpa_info; 1409 dma_addr_t mapping; 1410 struct sk_buff *skb; 1411 void *data; 1412 1413 if (unlikely(bnapi->in_reset)) { 1414 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end); 1415 1416 if (rc < 0) 1417 return ERR_PTR(-EBUSY); 1418 return NULL; 1419 } 1420 1421 tpa_info = &rxr->rx_tpa[agg_id]; 1422 data = tpa_info->data; 1423 data_ptr = tpa_info->data_ptr; 1424 prefetch(data_ptr); 1425 len = tpa_info->len; 1426 mapping = tpa_info->mapping; 1427 1428 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & 1429 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT; 1430 1431 if (agg_bufs) { 1432 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons)) 1433 return ERR_PTR(-EBUSY); 1434 1435 *event |= BNXT_AGG_EVENT; 1436 cp_cons = NEXT_CMP(cp_cons); 1437 } 1438 1439 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) { 1440 bnxt_abort_tpa(cpr, cp_cons, agg_bufs); 1441 if (agg_bufs > MAX_SKB_FRAGS) 1442 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n", 1443 agg_bufs, (int)MAX_SKB_FRAGS); 1444 return NULL; 1445 } 1446 1447 if (len <= bp->rx_copy_thresh) { 1448 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping); 1449 if (!skb) { 1450 bnxt_abort_tpa(cpr, cp_cons, agg_bufs); 1451 return NULL; 1452 } 1453 } else { 1454 u8 *new_data; 1455 dma_addr_t new_mapping; 1456 1457 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC); 1458 if (!new_data) { 1459 bnxt_abort_tpa(cpr, cp_cons, agg_bufs); 1460 return NULL; 1461 } 1462 1463 tpa_info->data = new_data; 1464 tpa_info->data_ptr = new_data + bp->rx_offset; 1465 tpa_info->mapping = new_mapping; 1466 1467 skb = build_skb(data, 0); 1468 dma_unmap_single_attrs(&bp->pdev->dev, mapping, 1469 bp->rx_buf_use_size, bp->rx_dir, 1470 DMA_ATTR_WEAK_ORDERING); 1471 1472 if (!skb) { 1473 kfree(data); 1474 bnxt_abort_tpa(cpr, cp_cons, agg_bufs); 1475 return NULL; 1476 } 1477 skb_reserve(skb, bp->rx_offset); 1478 skb_put(skb, len); 1479 } 1480 1481 if (agg_bufs) { 1482 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs); 1483 if (!skb) { 1484 /* Page reuse already handled by bnxt_rx_pages(). */ 1485 return NULL; 1486 } 1487 } 1488 1489 skb->protocol = 1490 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code)); 1491 1492 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE) 1493 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type); 1494 1495 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) && 1496 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1497 u16 vlan_proto = tpa_info->metadata >> 1498 RX_CMP_FLAGS2_METADATA_TPID_SFT; 1499 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK; 1500 1501 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); 1502 } 1503 1504 skb_checksum_none_assert(skb); 1505 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) { 1506 skb->ip_summed = CHECKSUM_UNNECESSARY; 1507 skb->csum_level = 1508 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3; 1509 } 1510 1511 if (TPA_END_GRO(tpa_end)) 1512 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb); 1513 1514 return skb; 1515 } 1516 1517 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi, 1518 struct sk_buff *skb) 1519 { 1520 if (skb->dev != bp->dev) { 1521 /* this packet belongs to a vf-rep */ 1522 bnxt_vf_rep_rx(bp, skb); 1523 return; 1524 } 1525 skb_record_rx_queue(skb, bnapi->index); 1526 napi_gro_receive(&bnapi->napi, skb); 1527 } 1528 1529 /* returns the following: 1530 * 1 - 1 packet successfully received 1531 * 0 - successful TPA_START, packet not completed yet 1532 * -EBUSY - completion ring does not have all the agg buffers yet 1533 * -ENOMEM - packet aborted due to out of memory 1534 * -EIO - packet aborted due to hw error indicated in BD 1535 */ 1536 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1537 u32 *raw_cons, u8 *event) 1538 { 1539 struct bnxt_napi *bnapi = cpr->bnapi; 1540 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 1541 struct net_device *dev = bp->dev; 1542 struct rx_cmp *rxcmp; 1543 struct rx_cmp_ext *rxcmp1; 1544 u32 tmp_raw_cons = *raw_cons; 1545 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons); 1546 struct bnxt_sw_rx_bd *rx_buf; 1547 unsigned int len; 1548 u8 *data_ptr, agg_bufs, cmp_type; 1549 dma_addr_t dma_addr; 1550 struct sk_buff *skb; 1551 void *data; 1552 int rc = 0; 1553 u32 misc; 1554 1555 rxcmp = (struct rx_cmp *) 1556 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1557 1558 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1559 cp_cons = RING_CMP(tmp_raw_cons); 1560 rxcmp1 = (struct rx_cmp_ext *) 1561 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1562 1563 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1564 return -EBUSY; 1565 1566 cmp_type = RX_CMP_TYPE(rxcmp); 1567 1568 prod = rxr->rx_prod; 1569 1570 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) { 1571 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp, 1572 (struct rx_tpa_start_cmp_ext *)rxcmp1); 1573 1574 *event |= BNXT_RX_EVENT; 1575 goto next_rx_no_prod_no_len; 1576 1577 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1578 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons, 1579 (struct rx_tpa_end_cmp *)rxcmp, 1580 (struct rx_tpa_end_cmp_ext *)rxcmp1, event); 1581 1582 if (IS_ERR(skb)) 1583 return -EBUSY; 1584 1585 rc = -ENOMEM; 1586 if (likely(skb)) { 1587 bnxt_deliver_skb(bp, bnapi, skb); 1588 rc = 1; 1589 } 1590 *event |= BNXT_RX_EVENT; 1591 goto next_rx_no_prod_no_len; 1592 } 1593 1594 cons = rxcmp->rx_cmp_opaque; 1595 if (unlikely(cons != rxr->rx_next_cons)) { 1596 int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp); 1597 1598 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n", 1599 cons, rxr->rx_next_cons); 1600 bnxt_sched_reset(bp, rxr); 1601 return rc1; 1602 } 1603 rx_buf = &rxr->rx_buf_ring[cons]; 1604 data = rx_buf->data; 1605 data_ptr = rx_buf->data_ptr; 1606 prefetch(data_ptr); 1607 1608 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1); 1609 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT; 1610 1611 if (agg_bufs) { 1612 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) 1613 return -EBUSY; 1614 1615 cp_cons = NEXT_CMP(cp_cons); 1616 *event |= BNXT_AGG_EVENT; 1617 } 1618 *event |= BNXT_RX_EVENT; 1619 1620 rx_buf->data = NULL; 1621 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) { 1622 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2); 1623 1624 bnxt_reuse_rx_data(rxr, cons, data); 1625 if (agg_bufs) 1626 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs); 1627 1628 rc = -EIO; 1629 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) { 1630 netdev_warn(bp->dev, "RX buffer error %x\n", rx_err); 1631 bnxt_sched_reset(bp, rxr); 1632 } 1633 goto next_rx_no_len; 1634 } 1635 1636 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 1637 dma_addr = rx_buf->mapping; 1638 1639 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) { 1640 rc = 1; 1641 goto next_rx; 1642 } 1643 1644 if (len <= bp->rx_copy_thresh) { 1645 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr); 1646 bnxt_reuse_rx_data(rxr, cons, data); 1647 if (!skb) { 1648 if (agg_bufs) 1649 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs); 1650 rc = -ENOMEM; 1651 goto next_rx; 1652 } 1653 } else { 1654 u32 payload; 1655 1656 if (rx_buf->data_ptr == data_ptr) 1657 payload = misc & RX_CMP_PAYLOAD_OFFSET; 1658 else 1659 payload = 0; 1660 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr, 1661 payload | len); 1662 if (!skb) { 1663 rc = -ENOMEM; 1664 goto next_rx; 1665 } 1666 } 1667 1668 if (agg_bufs) { 1669 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs); 1670 if (!skb) { 1671 rc = -ENOMEM; 1672 goto next_rx; 1673 } 1674 } 1675 1676 if (RX_CMP_HASH_VALID(rxcmp)) { 1677 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp); 1678 enum pkt_hash_types type = PKT_HASH_TYPE_L4; 1679 1680 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1681 if (hash_type != 1 && hash_type != 3) 1682 type = PKT_HASH_TYPE_L3; 1683 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type); 1684 } 1685 1686 cfa_code = RX_CMP_CFA_CODE(rxcmp1); 1687 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code)); 1688 1689 if ((rxcmp1->rx_cmp_flags2 & 1690 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) && 1691 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1692 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data); 1693 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK; 1694 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT; 1695 1696 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag); 1697 } 1698 1699 skb_checksum_none_assert(skb); 1700 if (RX_CMP_L4_CS_OK(rxcmp1)) { 1701 if (dev->features & NETIF_F_RXCSUM) { 1702 skb->ip_summed = CHECKSUM_UNNECESSARY; 1703 skb->csum_level = RX_CMP_ENCAP(rxcmp1); 1704 } 1705 } else { 1706 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) { 1707 if (dev->features & NETIF_F_RXCSUM) 1708 bnapi->cp_ring.rx_l4_csum_errors++; 1709 } 1710 } 1711 1712 bnxt_deliver_skb(bp, bnapi, skb); 1713 rc = 1; 1714 1715 next_rx: 1716 cpr->rx_packets += 1; 1717 cpr->rx_bytes += len; 1718 1719 next_rx_no_len: 1720 rxr->rx_prod = NEXT_RX(prod); 1721 rxr->rx_next_cons = NEXT_RX(cons); 1722 1723 next_rx_no_prod_no_len: 1724 *raw_cons = tmp_raw_cons; 1725 1726 return rc; 1727 } 1728 1729 /* In netpoll mode, if we are using a combined completion ring, we need to 1730 * discard the rx packets and recycle the buffers. 1731 */ 1732 static int bnxt_force_rx_discard(struct bnxt *bp, 1733 struct bnxt_cp_ring_info *cpr, 1734 u32 *raw_cons, u8 *event) 1735 { 1736 u32 tmp_raw_cons = *raw_cons; 1737 struct rx_cmp_ext *rxcmp1; 1738 struct rx_cmp *rxcmp; 1739 u16 cp_cons; 1740 u8 cmp_type; 1741 1742 cp_cons = RING_CMP(tmp_raw_cons); 1743 rxcmp = (struct rx_cmp *) 1744 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1745 1746 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 1747 cp_cons = RING_CMP(tmp_raw_cons); 1748 rxcmp1 = (struct rx_cmp_ext *) 1749 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 1750 1751 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 1752 return -EBUSY; 1753 1754 cmp_type = RX_CMP_TYPE(rxcmp); 1755 if (cmp_type == CMP_TYPE_RX_L2_CMP) { 1756 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 1757 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 1758 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { 1759 struct rx_tpa_end_cmp_ext *tpa_end1; 1760 1761 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1; 1762 tpa_end1->rx_tpa_end_cmp_errors_v2 |= 1763 cpu_to_le32(RX_TPA_END_CMP_ERRORS); 1764 } 1765 return bnxt_rx_pkt(bp, cpr, raw_cons, event); 1766 } 1767 1768 #define BNXT_GET_EVENT_PORT(data) \ 1769 ((data) & \ 1770 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK) 1771 1772 static int bnxt_async_event_process(struct bnxt *bp, 1773 struct hwrm_async_event_cmpl *cmpl) 1774 { 1775 u16 event_id = le16_to_cpu(cmpl->event_id); 1776 1777 /* TODO CHIMP_FW: Define event id's for link change, error etc */ 1778 switch (event_id) { 1779 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: { 1780 u32 data1 = le32_to_cpu(cmpl->event_data1); 1781 struct bnxt_link_info *link_info = &bp->link_info; 1782 1783 if (BNXT_VF(bp)) 1784 goto async_event_process_exit; 1785 1786 /* print unsupported speed warning in forced speed mode only */ 1787 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) && 1788 (data1 & 0x20000)) { 1789 u16 fw_speed = link_info->force_link_speed; 1790 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed); 1791 1792 if (speed != SPEED_UNKNOWN) 1793 netdev_warn(bp->dev, "Link speed %d no longer supported\n", 1794 speed); 1795 } 1796 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event); 1797 } 1798 /* fall through */ 1799 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE: 1800 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event); 1801 break; 1802 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD: 1803 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event); 1804 break; 1805 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: { 1806 u32 data1 = le32_to_cpu(cmpl->event_data1); 1807 u16 port_id = BNXT_GET_EVENT_PORT(data1); 1808 1809 if (BNXT_VF(bp)) 1810 break; 1811 1812 if (bp->pf.port_id != port_id) 1813 break; 1814 1815 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event); 1816 break; 1817 } 1818 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE: 1819 if (BNXT_PF(bp)) 1820 goto async_event_process_exit; 1821 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event); 1822 break; 1823 default: 1824 goto async_event_process_exit; 1825 } 1826 bnxt_queue_sp_work(bp); 1827 async_event_process_exit: 1828 bnxt_ulp_async_events(bp, cmpl); 1829 return 0; 1830 } 1831 1832 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp) 1833 { 1834 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id; 1835 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp; 1836 struct hwrm_fwd_req_cmpl *fwd_req_cmpl = 1837 (struct hwrm_fwd_req_cmpl *)txcmp; 1838 1839 switch (cmpl_type) { 1840 case CMPL_BASE_TYPE_HWRM_DONE: 1841 seq_id = le16_to_cpu(h_cmpl->sequence_id); 1842 if (seq_id == bp->hwrm_intr_seq_id) 1843 bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id; 1844 else 1845 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id); 1846 break; 1847 1848 case CMPL_BASE_TYPE_HWRM_FWD_REQ: 1849 vf_id = le16_to_cpu(fwd_req_cmpl->source_id); 1850 1851 if ((vf_id < bp->pf.first_vf_id) || 1852 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) { 1853 netdev_err(bp->dev, "Msg contains invalid VF id %x\n", 1854 vf_id); 1855 return -EINVAL; 1856 } 1857 1858 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap); 1859 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event); 1860 bnxt_queue_sp_work(bp); 1861 break; 1862 1863 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: 1864 bnxt_async_event_process(bp, 1865 (struct hwrm_async_event_cmpl *)txcmp); 1866 1867 default: 1868 break; 1869 } 1870 1871 return 0; 1872 } 1873 1874 static irqreturn_t bnxt_msix(int irq, void *dev_instance) 1875 { 1876 struct bnxt_napi *bnapi = dev_instance; 1877 struct bnxt *bp = bnapi->bp; 1878 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1879 u32 cons = RING_CMP(cpr->cp_raw_cons); 1880 1881 cpr->event_ctr++; 1882 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 1883 napi_schedule(&bnapi->napi); 1884 return IRQ_HANDLED; 1885 } 1886 1887 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) 1888 { 1889 u32 raw_cons = cpr->cp_raw_cons; 1890 u16 cons = RING_CMP(raw_cons); 1891 struct tx_cmp *txcmp; 1892 1893 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 1894 1895 return TX_CMP_VALID(txcmp, raw_cons); 1896 } 1897 1898 static irqreturn_t bnxt_inta(int irq, void *dev_instance) 1899 { 1900 struct bnxt_napi *bnapi = dev_instance; 1901 struct bnxt *bp = bnapi->bp; 1902 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 1903 u32 cons = RING_CMP(cpr->cp_raw_cons); 1904 u32 int_status; 1905 1906 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); 1907 1908 if (!bnxt_has_work(bp, cpr)) { 1909 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS); 1910 /* return if erroneous interrupt */ 1911 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id))) 1912 return IRQ_NONE; 1913 } 1914 1915 /* disable ring IRQ */ 1916 BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell); 1917 1918 /* Return here if interrupt is shared and is disabled. */ 1919 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 1920 return IRQ_HANDLED; 1921 1922 napi_schedule(&bnapi->napi); 1923 return IRQ_HANDLED; 1924 } 1925 1926 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 1927 int budget) 1928 { 1929 struct bnxt_napi *bnapi = cpr->bnapi; 1930 u32 raw_cons = cpr->cp_raw_cons; 1931 u32 cons; 1932 int tx_pkts = 0; 1933 int rx_pkts = 0; 1934 u8 event = 0; 1935 struct tx_cmp *txcmp; 1936 1937 cpr->has_more_work = 0; 1938 while (1) { 1939 int rc; 1940 1941 cons = RING_CMP(raw_cons); 1942 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 1943 1944 if (!TX_CMP_VALID(txcmp, raw_cons)) 1945 break; 1946 1947 /* The valid test of the entry must be done first before 1948 * reading any further. 1949 */ 1950 dma_rmb(); 1951 cpr->had_work_done = 1; 1952 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) { 1953 tx_pkts++; 1954 /* return full budget so NAPI will complete. */ 1955 if (unlikely(tx_pkts > bp->tx_wake_thresh)) { 1956 rx_pkts = budget; 1957 raw_cons = NEXT_RAW_CMP(raw_cons); 1958 if (budget) 1959 cpr->has_more_work = 1; 1960 break; 1961 } 1962 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 1963 if (likely(budget)) 1964 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); 1965 else 1966 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons, 1967 &event); 1968 if (likely(rc >= 0)) 1969 rx_pkts += rc; 1970 /* Increment rx_pkts when rc is -ENOMEM to count towards 1971 * the NAPI budget. Otherwise, we may potentially loop 1972 * here forever if we consistently cannot allocate 1973 * buffers. 1974 */ 1975 else if (rc == -ENOMEM && budget) 1976 rx_pkts++; 1977 else if (rc == -EBUSY) /* partial completion */ 1978 break; 1979 } else if (unlikely((TX_CMP_TYPE(txcmp) == 1980 CMPL_BASE_TYPE_HWRM_DONE) || 1981 (TX_CMP_TYPE(txcmp) == 1982 CMPL_BASE_TYPE_HWRM_FWD_REQ) || 1983 (TX_CMP_TYPE(txcmp) == 1984 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) { 1985 bnxt_hwrm_handler(bp, txcmp); 1986 } 1987 raw_cons = NEXT_RAW_CMP(raw_cons); 1988 1989 if (rx_pkts && rx_pkts == budget) { 1990 cpr->has_more_work = 1; 1991 break; 1992 } 1993 } 1994 1995 if (event & BNXT_REDIRECT_EVENT) 1996 xdp_do_flush_map(); 1997 1998 if (event & BNXT_TX_EVENT) { 1999 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 2000 u16 prod = txr->tx_prod; 2001 2002 /* Sync BD data before updating doorbell */ 2003 wmb(); 2004 2005 bnxt_db_write_relaxed(bp, &txr->tx_db, prod); 2006 } 2007 2008 cpr->cp_raw_cons = raw_cons; 2009 bnapi->tx_pkts += tx_pkts; 2010 bnapi->events |= event; 2011 return rx_pkts; 2012 } 2013 2014 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi) 2015 { 2016 if (bnapi->tx_pkts) { 2017 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts); 2018 bnapi->tx_pkts = 0; 2019 } 2020 2021 if (bnapi->events & BNXT_RX_EVENT) { 2022 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 2023 2024 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 2025 if (bnapi->events & BNXT_AGG_EVENT) 2026 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 2027 } 2028 bnapi->events = 0; 2029 } 2030 2031 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2032 int budget) 2033 { 2034 struct bnxt_napi *bnapi = cpr->bnapi; 2035 int rx_pkts; 2036 2037 rx_pkts = __bnxt_poll_work(bp, cpr, budget); 2038 2039 /* ACK completion ring before freeing tx ring and producing new 2040 * buffers in rx/agg rings to prevent overflowing the completion 2041 * ring. 2042 */ 2043 bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons); 2044 2045 __bnxt_poll_work_done(bp, bnapi); 2046 return rx_pkts; 2047 } 2048 2049 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget) 2050 { 2051 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2052 struct bnxt *bp = bnapi->bp; 2053 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2054 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 2055 struct tx_cmp *txcmp; 2056 struct rx_cmp_ext *rxcmp1; 2057 u32 cp_cons, tmp_raw_cons; 2058 u32 raw_cons = cpr->cp_raw_cons; 2059 u32 rx_pkts = 0; 2060 u8 event = 0; 2061 2062 while (1) { 2063 int rc; 2064 2065 cp_cons = RING_CMP(raw_cons); 2066 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2067 2068 if (!TX_CMP_VALID(txcmp, raw_cons)) 2069 break; 2070 2071 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { 2072 tmp_raw_cons = NEXT_RAW_CMP(raw_cons); 2073 cp_cons = RING_CMP(tmp_raw_cons); 2074 rxcmp1 = (struct rx_cmp_ext *) 2075 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2076 2077 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) 2078 break; 2079 2080 /* force an error to recycle the buffer */ 2081 rxcmp1->rx_cmp_cfa_code_errors_v2 |= 2082 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR); 2083 2084 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event); 2085 if (likely(rc == -EIO) && budget) 2086 rx_pkts++; 2087 else if (rc == -EBUSY) /* partial completion */ 2088 break; 2089 } else if (unlikely(TX_CMP_TYPE(txcmp) == 2090 CMPL_BASE_TYPE_HWRM_DONE)) { 2091 bnxt_hwrm_handler(bp, txcmp); 2092 } else { 2093 netdev_err(bp->dev, 2094 "Invalid completion received on special ring\n"); 2095 } 2096 raw_cons = NEXT_RAW_CMP(raw_cons); 2097 2098 if (rx_pkts == budget) 2099 break; 2100 } 2101 2102 cpr->cp_raw_cons = raw_cons; 2103 BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons); 2104 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 2105 2106 if (event & BNXT_AGG_EVENT) 2107 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 2108 2109 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) { 2110 napi_complete_done(napi, rx_pkts); 2111 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2112 } 2113 return rx_pkts; 2114 } 2115 2116 static int bnxt_poll(struct napi_struct *napi, int budget) 2117 { 2118 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2119 struct bnxt *bp = bnapi->bp; 2120 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2121 int work_done = 0; 2122 2123 while (1) { 2124 work_done += bnxt_poll_work(bp, cpr, budget - work_done); 2125 2126 if (work_done >= budget) { 2127 if (!budget) 2128 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2129 break; 2130 } 2131 2132 if (!bnxt_has_work(bp, cpr)) { 2133 if (napi_complete_done(napi, work_done)) 2134 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons); 2135 break; 2136 } 2137 } 2138 if (bp->flags & BNXT_FLAG_DIM) { 2139 struct dim_sample dim_sample; 2140 2141 dim_update_sample(cpr->event_ctr, 2142 cpr->rx_packets, 2143 cpr->rx_bytes, 2144 &dim_sample); 2145 net_dim(&cpr->dim, dim_sample); 2146 } 2147 return work_done; 2148 } 2149 2150 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget) 2151 { 2152 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2153 int i, work_done = 0; 2154 2155 for (i = 0; i < 2; i++) { 2156 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; 2157 2158 if (cpr2) { 2159 work_done += __bnxt_poll_work(bp, cpr2, 2160 budget - work_done); 2161 cpr->has_more_work |= cpr2->has_more_work; 2162 } 2163 } 2164 return work_done; 2165 } 2166 2167 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi, 2168 u64 dbr_type, bool all) 2169 { 2170 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2171 int i; 2172 2173 for (i = 0; i < 2; i++) { 2174 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i]; 2175 struct bnxt_db_info *db; 2176 2177 if (cpr2 && (all || cpr2->had_work_done)) { 2178 db = &cpr2->cp_db; 2179 writeq(db->db_key64 | dbr_type | 2180 RING_CMP(cpr2->cp_raw_cons), db->doorbell); 2181 cpr2->had_work_done = 0; 2182 } 2183 } 2184 __bnxt_poll_work_done(bp, bnapi); 2185 } 2186 2187 static int bnxt_poll_p5(struct napi_struct *napi, int budget) 2188 { 2189 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); 2190 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2191 u32 raw_cons = cpr->cp_raw_cons; 2192 struct bnxt *bp = bnapi->bp; 2193 struct nqe_cn *nqcmp; 2194 int work_done = 0; 2195 u32 cons; 2196 2197 if (cpr->has_more_work) { 2198 cpr->has_more_work = 0; 2199 work_done = __bnxt_poll_cqs(bp, bnapi, budget); 2200 if (cpr->has_more_work) { 2201 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, false); 2202 return work_done; 2203 } 2204 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL, true); 2205 if (napi_complete_done(napi, work_done)) 2206 BNXT_DB_NQ_ARM_P5(&cpr->cp_db, cpr->cp_raw_cons); 2207 return work_done; 2208 } 2209 while (1) { 2210 cons = RING_CMP(raw_cons); 2211 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2212 2213 if (!NQ_CMP_VALID(nqcmp, raw_cons)) { 2214 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL, 2215 false); 2216 cpr->cp_raw_cons = raw_cons; 2217 if (napi_complete_done(napi, work_done)) 2218 BNXT_DB_NQ_ARM_P5(&cpr->cp_db, 2219 cpr->cp_raw_cons); 2220 return work_done; 2221 } 2222 2223 /* The valid test of the entry must be done first before 2224 * reading any further. 2225 */ 2226 dma_rmb(); 2227 2228 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) { 2229 u32 idx = le32_to_cpu(nqcmp->cq_handle_low); 2230 struct bnxt_cp_ring_info *cpr2; 2231 2232 cpr2 = cpr->cp_ring_arr[idx]; 2233 work_done += __bnxt_poll_work(bp, cpr2, 2234 budget - work_done); 2235 cpr->has_more_work = cpr2->has_more_work; 2236 } else { 2237 bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp); 2238 } 2239 raw_cons = NEXT_RAW_CMP(raw_cons); 2240 if (cpr->has_more_work) 2241 break; 2242 } 2243 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, true); 2244 cpr->cp_raw_cons = raw_cons; 2245 return work_done; 2246 } 2247 2248 static void bnxt_free_tx_skbs(struct bnxt *bp) 2249 { 2250 int i, max_idx; 2251 struct pci_dev *pdev = bp->pdev; 2252 2253 if (!bp->tx_ring) 2254 return; 2255 2256 max_idx = bp->tx_nr_pages * TX_DESC_CNT; 2257 for (i = 0; i < bp->tx_nr_rings; i++) { 2258 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2259 int j; 2260 2261 for (j = 0; j < max_idx;) { 2262 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; 2263 struct sk_buff *skb; 2264 int k, last; 2265 2266 if (i < bp->tx_nr_rings_xdp && 2267 tx_buf->action == XDP_REDIRECT) { 2268 dma_unmap_single(&pdev->dev, 2269 dma_unmap_addr(tx_buf, mapping), 2270 dma_unmap_len(tx_buf, len), 2271 PCI_DMA_TODEVICE); 2272 xdp_return_frame(tx_buf->xdpf); 2273 tx_buf->action = 0; 2274 tx_buf->xdpf = NULL; 2275 j++; 2276 continue; 2277 } 2278 2279 skb = tx_buf->skb; 2280 if (!skb) { 2281 j++; 2282 continue; 2283 } 2284 2285 tx_buf->skb = NULL; 2286 2287 if (tx_buf->is_push) { 2288 dev_kfree_skb(skb); 2289 j += 2; 2290 continue; 2291 } 2292 2293 dma_unmap_single(&pdev->dev, 2294 dma_unmap_addr(tx_buf, mapping), 2295 skb_headlen(skb), 2296 PCI_DMA_TODEVICE); 2297 2298 last = tx_buf->nr_frags; 2299 j += 2; 2300 for (k = 0; k < last; k++, j++) { 2301 int ring_idx = j & bp->tx_ring_mask; 2302 skb_frag_t *frag = &skb_shinfo(skb)->frags[k]; 2303 2304 tx_buf = &txr->tx_buf_ring[ring_idx]; 2305 dma_unmap_page( 2306 &pdev->dev, 2307 dma_unmap_addr(tx_buf, mapping), 2308 skb_frag_size(frag), PCI_DMA_TODEVICE); 2309 } 2310 dev_kfree_skb(skb); 2311 } 2312 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); 2313 } 2314 } 2315 2316 static void bnxt_free_rx_skbs(struct bnxt *bp) 2317 { 2318 int i, max_idx, max_agg_idx; 2319 struct pci_dev *pdev = bp->pdev; 2320 2321 if (!bp->rx_ring) 2322 return; 2323 2324 max_idx = bp->rx_nr_pages * RX_DESC_CNT; 2325 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT; 2326 for (i = 0; i < bp->rx_nr_rings; i++) { 2327 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2328 int j; 2329 2330 if (rxr->rx_tpa) { 2331 for (j = 0; j < MAX_TPA; j++) { 2332 struct bnxt_tpa_info *tpa_info = 2333 &rxr->rx_tpa[j]; 2334 u8 *data = tpa_info->data; 2335 2336 if (!data) 2337 continue; 2338 2339 dma_unmap_single_attrs(&pdev->dev, 2340 tpa_info->mapping, 2341 bp->rx_buf_use_size, 2342 bp->rx_dir, 2343 DMA_ATTR_WEAK_ORDERING); 2344 2345 tpa_info->data = NULL; 2346 2347 kfree(data); 2348 } 2349 } 2350 2351 for (j = 0; j < max_idx; j++) { 2352 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j]; 2353 dma_addr_t mapping = rx_buf->mapping; 2354 void *data = rx_buf->data; 2355 2356 if (!data) 2357 continue; 2358 2359 rx_buf->data = NULL; 2360 2361 if (BNXT_RX_PAGE_MODE(bp)) { 2362 mapping -= bp->rx_dma_offset; 2363 dma_unmap_page_attrs(&pdev->dev, mapping, 2364 PAGE_SIZE, bp->rx_dir, 2365 DMA_ATTR_WEAK_ORDERING); 2366 page_pool_recycle_direct(rxr->page_pool, data); 2367 } else { 2368 dma_unmap_single_attrs(&pdev->dev, mapping, 2369 bp->rx_buf_use_size, 2370 bp->rx_dir, 2371 DMA_ATTR_WEAK_ORDERING); 2372 kfree(data); 2373 } 2374 } 2375 2376 for (j = 0; j < max_agg_idx; j++) { 2377 struct bnxt_sw_rx_agg_bd *rx_agg_buf = 2378 &rxr->rx_agg_ring[j]; 2379 struct page *page = rx_agg_buf->page; 2380 2381 if (!page) 2382 continue; 2383 2384 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping, 2385 BNXT_RX_PAGE_SIZE, 2386 PCI_DMA_FROMDEVICE, 2387 DMA_ATTR_WEAK_ORDERING); 2388 2389 rx_agg_buf->page = NULL; 2390 __clear_bit(j, rxr->rx_agg_bmap); 2391 2392 __free_page(page); 2393 } 2394 if (rxr->rx_page) { 2395 __free_page(rxr->rx_page); 2396 rxr->rx_page = NULL; 2397 } 2398 } 2399 } 2400 2401 static void bnxt_free_skbs(struct bnxt *bp) 2402 { 2403 bnxt_free_tx_skbs(bp); 2404 bnxt_free_rx_skbs(bp); 2405 } 2406 2407 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) 2408 { 2409 struct pci_dev *pdev = bp->pdev; 2410 int i; 2411 2412 for (i = 0; i < rmem->nr_pages; i++) { 2413 if (!rmem->pg_arr[i]) 2414 continue; 2415 2416 dma_free_coherent(&pdev->dev, rmem->page_size, 2417 rmem->pg_arr[i], rmem->dma_arr[i]); 2418 2419 rmem->pg_arr[i] = NULL; 2420 } 2421 if (rmem->pg_tbl) { 2422 size_t pg_tbl_size = rmem->nr_pages * 8; 2423 2424 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) 2425 pg_tbl_size = rmem->page_size; 2426 dma_free_coherent(&pdev->dev, pg_tbl_size, 2427 rmem->pg_tbl, rmem->pg_tbl_map); 2428 rmem->pg_tbl = NULL; 2429 } 2430 if (rmem->vmem_size && *rmem->vmem) { 2431 vfree(*rmem->vmem); 2432 *rmem->vmem = NULL; 2433 } 2434 } 2435 2436 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem) 2437 { 2438 struct pci_dev *pdev = bp->pdev; 2439 u64 valid_bit = 0; 2440 int i; 2441 2442 if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG)) 2443 valid_bit = PTU_PTE_VALID; 2444 if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) { 2445 size_t pg_tbl_size = rmem->nr_pages * 8; 2446 2447 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) 2448 pg_tbl_size = rmem->page_size; 2449 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size, 2450 &rmem->pg_tbl_map, 2451 GFP_KERNEL); 2452 if (!rmem->pg_tbl) 2453 return -ENOMEM; 2454 } 2455 2456 for (i = 0; i < rmem->nr_pages; i++) { 2457 u64 extra_bits = valid_bit; 2458 2459 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev, 2460 rmem->page_size, 2461 &rmem->dma_arr[i], 2462 GFP_KERNEL); 2463 if (!rmem->pg_arr[i]) 2464 return -ENOMEM; 2465 2466 if (rmem->nr_pages > 1 || rmem->depth > 0) { 2467 if (i == rmem->nr_pages - 2 && 2468 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 2469 extra_bits |= PTU_PTE_NEXT_TO_LAST; 2470 else if (i == rmem->nr_pages - 1 && 2471 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 2472 extra_bits |= PTU_PTE_LAST; 2473 rmem->pg_tbl[i] = 2474 cpu_to_le64(rmem->dma_arr[i] | extra_bits); 2475 } 2476 } 2477 2478 if (rmem->vmem_size) { 2479 *rmem->vmem = vzalloc(rmem->vmem_size); 2480 if (!(*rmem->vmem)) 2481 return -ENOMEM; 2482 } 2483 return 0; 2484 } 2485 2486 static void bnxt_free_rx_rings(struct bnxt *bp) 2487 { 2488 int i; 2489 2490 if (!bp->rx_ring) 2491 return; 2492 2493 for (i = 0; i < bp->rx_nr_rings; i++) { 2494 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2495 struct bnxt_ring_struct *ring; 2496 2497 if (rxr->xdp_prog) 2498 bpf_prog_put(rxr->xdp_prog); 2499 2500 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq)) 2501 xdp_rxq_info_unreg(&rxr->xdp_rxq); 2502 2503 rxr->page_pool = NULL; 2504 2505 kfree(rxr->rx_tpa); 2506 rxr->rx_tpa = NULL; 2507 2508 kfree(rxr->rx_agg_bmap); 2509 rxr->rx_agg_bmap = NULL; 2510 2511 ring = &rxr->rx_ring_struct; 2512 bnxt_free_ring(bp, &ring->ring_mem); 2513 2514 ring = &rxr->rx_agg_ring_struct; 2515 bnxt_free_ring(bp, &ring->ring_mem); 2516 } 2517 } 2518 2519 static int bnxt_alloc_rx_page_pool(struct bnxt *bp, 2520 struct bnxt_rx_ring_info *rxr) 2521 { 2522 struct page_pool_params pp = { 0 }; 2523 2524 pp.pool_size = bp->rx_ring_size; 2525 pp.nid = dev_to_node(&bp->pdev->dev); 2526 pp.dev = &bp->pdev->dev; 2527 pp.dma_dir = DMA_BIDIRECTIONAL; 2528 2529 rxr->page_pool = page_pool_create(&pp); 2530 if (IS_ERR(rxr->page_pool)) { 2531 int err = PTR_ERR(rxr->page_pool); 2532 2533 rxr->page_pool = NULL; 2534 return err; 2535 } 2536 return 0; 2537 } 2538 2539 static int bnxt_alloc_rx_rings(struct bnxt *bp) 2540 { 2541 int i, rc, agg_rings = 0, tpa_rings = 0; 2542 2543 if (!bp->rx_ring) 2544 return -ENOMEM; 2545 2546 if (bp->flags & BNXT_FLAG_AGG_RINGS) 2547 agg_rings = 1; 2548 2549 if (bp->flags & BNXT_FLAG_TPA) 2550 tpa_rings = 1; 2551 2552 for (i = 0; i < bp->rx_nr_rings; i++) { 2553 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 2554 struct bnxt_ring_struct *ring; 2555 2556 ring = &rxr->rx_ring_struct; 2557 2558 rc = bnxt_alloc_rx_page_pool(bp, rxr); 2559 if (rc) 2560 return rc; 2561 2562 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i); 2563 if (rc < 0) { 2564 page_pool_free(rxr->page_pool); 2565 rxr->page_pool = NULL; 2566 return rc; 2567 } 2568 2569 rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq, 2570 MEM_TYPE_PAGE_POOL, 2571 rxr->page_pool); 2572 if (rc) { 2573 xdp_rxq_info_unreg(&rxr->xdp_rxq); 2574 page_pool_free(rxr->page_pool); 2575 rxr->page_pool = NULL; 2576 return rc; 2577 } 2578 2579 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 2580 if (rc) 2581 return rc; 2582 2583 ring->grp_idx = i; 2584 if (agg_rings) { 2585 u16 mem_size; 2586 2587 ring = &rxr->rx_agg_ring_struct; 2588 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 2589 if (rc) 2590 return rc; 2591 2592 ring->grp_idx = i; 2593 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1; 2594 mem_size = rxr->rx_agg_bmap_size / 8; 2595 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL); 2596 if (!rxr->rx_agg_bmap) 2597 return -ENOMEM; 2598 2599 if (tpa_rings) { 2600 rxr->rx_tpa = kcalloc(MAX_TPA, 2601 sizeof(struct bnxt_tpa_info), 2602 GFP_KERNEL); 2603 if (!rxr->rx_tpa) 2604 return -ENOMEM; 2605 } 2606 } 2607 } 2608 return 0; 2609 } 2610 2611 static void bnxt_free_tx_rings(struct bnxt *bp) 2612 { 2613 int i; 2614 struct pci_dev *pdev = bp->pdev; 2615 2616 if (!bp->tx_ring) 2617 return; 2618 2619 for (i = 0; i < bp->tx_nr_rings; i++) { 2620 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2621 struct bnxt_ring_struct *ring; 2622 2623 if (txr->tx_push) { 2624 dma_free_coherent(&pdev->dev, bp->tx_push_size, 2625 txr->tx_push, txr->tx_push_mapping); 2626 txr->tx_push = NULL; 2627 } 2628 2629 ring = &txr->tx_ring_struct; 2630 2631 bnxt_free_ring(bp, &ring->ring_mem); 2632 } 2633 } 2634 2635 static int bnxt_alloc_tx_rings(struct bnxt *bp) 2636 { 2637 int i, j, rc; 2638 struct pci_dev *pdev = bp->pdev; 2639 2640 bp->tx_push_size = 0; 2641 if (bp->tx_push_thresh) { 2642 int push_size; 2643 2644 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) + 2645 bp->tx_push_thresh); 2646 2647 if (push_size > 256) { 2648 push_size = 0; 2649 bp->tx_push_thresh = 0; 2650 } 2651 2652 bp->tx_push_size = push_size; 2653 } 2654 2655 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) { 2656 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 2657 struct bnxt_ring_struct *ring; 2658 u8 qidx; 2659 2660 ring = &txr->tx_ring_struct; 2661 2662 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 2663 if (rc) 2664 return rc; 2665 2666 ring->grp_idx = txr->bnapi->index; 2667 if (bp->tx_push_size) { 2668 dma_addr_t mapping; 2669 2670 /* One pre-allocated DMA buffer to backup 2671 * TX push operation 2672 */ 2673 txr->tx_push = dma_alloc_coherent(&pdev->dev, 2674 bp->tx_push_size, 2675 &txr->tx_push_mapping, 2676 GFP_KERNEL); 2677 2678 if (!txr->tx_push) 2679 return -ENOMEM; 2680 2681 mapping = txr->tx_push_mapping + 2682 sizeof(struct tx_push_bd); 2683 txr->data_mapping = cpu_to_le64(mapping); 2684 2685 memset(txr->tx_push, 0, sizeof(struct tx_push_bd)); 2686 } 2687 qidx = bp->tc_to_qidx[j]; 2688 ring->queue_id = bp->q_info[qidx].queue_id; 2689 if (i < bp->tx_nr_rings_xdp) 2690 continue; 2691 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1)) 2692 j++; 2693 } 2694 return 0; 2695 } 2696 2697 static void bnxt_free_cp_rings(struct bnxt *bp) 2698 { 2699 int i; 2700 2701 if (!bp->bnapi) 2702 return; 2703 2704 for (i = 0; i < bp->cp_nr_rings; i++) { 2705 struct bnxt_napi *bnapi = bp->bnapi[i]; 2706 struct bnxt_cp_ring_info *cpr; 2707 struct bnxt_ring_struct *ring; 2708 int j; 2709 2710 if (!bnapi) 2711 continue; 2712 2713 cpr = &bnapi->cp_ring; 2714 ring = &cpr->cp_ring_struct; 2715 2716 bnxt_free_ring(bp, &ring->ring_mem); 2717 2718 for (j = 0; j < 2; j++) { 2719 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 2720 2721 if (cpr2) { 2722 ring = &cpr2->cp_ring_struct; 2723 bnxt_free_ring(bp, &ring->ring_mem); 2724 kfree(cpr2); 2725 cpr->cp_ring_arr[j] = NULL; 2726 } 2727 } 2728 } 2729 } 2730 2731 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp) 2732 { 2733 struct bnxt_ring_mem_info *rmem; 2734 struct bnxt_ring_struct *ring; 2735 struct bnxt_cp_ring_info *cpr; 2736 int rc; 2737 2738 cpr = kzalloc(sizeof(*cpr), GFP_KERNEL); 2739 if (!cpr) 2740 return NULL; 2741 2742 ring = &cpr->cp_ring_struct; 2743 rmem = &ring->ring_mem; 2744 rmem->nr_pages = bp->cp_nr_pages; 2745 rmem->page_size = HW_CMPD_RING_SIZE; 2746 rmem->pg_arr = (void **)cpr->cp_desc_ring; 2747 rmem->dma_arr = cpr->cp_desc_mapping; 2748 rmem->flags = BNXT_RMEM_RING_PTE_FLAG; 2749 rc = bnxt_alloc_ring(bp, rmem); 2750 if (rc) { 2751 bnxt_free_ring(bp, rmem); 2752 kfree(cpr); 2753 cpr = NULL; 2754 } 2755 return cpr; 2756 } 2757 2758 static int bnxt_alloc_cp_rings(struct bnxt *bp) 2759 { 2760 bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS); 2761 int i, rc, ulp_base_vec, ulp_msix; 2762 2763 ulp_msix = bnxt_get_ulp_msix_num(bp); 2764 ulp_base_vec = bnxt_get_ulp_msix_base(bp); 2765 for (i = 0; i < bp->cp_nr_rings; i++) { 2766 struct bnxt_napi *bnapi = bp->bnapi[i]; 2767 struct bnxt_cp_ring_info *cpr; 2768 struct bnxt_ring_struct *ring; 2769 2770 if (!bnapi) 2771 continue; 2772 2773 cpr = &bnapi->cp_ring; 2774 cpr->bnapi = bnapi; 2775 ring = &cpr->cp_ring_struct; 2776 2777 rc = bnxt_alloc_ring(bp, &ring->ring_mem); 2778 if (rc) 2779 return rc; 2780 2781 if (ulp_msix && i >= ulp_base_vec) 2782 ring->map_idx = i + ulp_msix; 2783 else 2784 ring->map_idx = i; 2785 2786 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 2787 continue; 2788 2789 if (i < bp->rx_nr_rings) { 2790 struct bnxt_cp_ring_info *cpr2 = 2791 bnxt_alloc_cp_sub_ring(bp); 2792 2793 cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2; 2794 if (!cpr2) 2795 return -ENOMEM; 2796 cpr2->bnapi = bnapi; 2797 } 2798 if ((sh && i < bp->tx_nr_rings) || 2799 (!sh && i >= bp->rx_nr_rings)) { 2800 struct bnxt_cp_ring_info *cpr2 = 2801 bnxt_alloc_cp_sub_ring(bp); 2802 2803 cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2; 2804 if (!cpr2) 2805 return -ENOMEM; 2806 cpr2->bnapi = bnapi; 2807 } 2808 } 2809 return 0; 2810 } 2811 2812 static void bnxt_init_ring_struct(struct bnxt *bp) 2813 { 2814 int i; 2815 2816 for (i = 0; i < bp->cp_nr_rings; i++) { 2817 struct bnxt_napi *bnapi = bp->bnapi[i]; 2818 struct bnxt_ring_mem_info *rmem; 2819 struct bnxt_cp_ring_info *cpr; 2820 struct bnxt_rx_ring_info *rxr; 2821 struct bnxt_tx_ring_info *txr; 2822 struct bnxt_ring_struct *ring; 2823 2824 if (!bnapi) 2825 continue; 2826 2827 cpr = &bnapi->cp_ring; 2828 ring = &cpr->cp_ring_struct; 2829 rmem = &ring->ring_mem; 2830 rmem->nr_pages = bp->cp_nr_pages; 2831 rmem->page_size = HW_CMPD_RING_SIZE; 2832 rmem->pg_arr = (void **)cpr->cp_desc_ring; 2833 rmem->dma_arr = cpr->cp_desc_mapping; 2834 rmem->vmem_size = 0; 2835 2836 rxr = bnapi->rx_ring; 2837 if (!rxr) 2838 goto skip_rx; 2839 2840 ring = &rxr->rx_ring_struct; 2841 rmem = &ring->ring_mem; 2842 rmem->nr_pages = bp->rx_nr_pages; 2843 rmem->page_size = HW_RXBD_RING_SIZE; 2844 rmem->pg_arr = (void **)rxr->rx_desc_ring; 2845 rmem->dma_arr = rxr->rx_desc_mapping; 2846 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages; 2847 rmem->vmem = (void **)&rxr->rx_buf_ring; 2848 2849 ring = &rxr->rx_agg_ring_struct; 2850 rmem = &ring->ring_mem; 2851 rmem->nr_pages = bp->rx_agg_nr_pages; 2852 rmem->page_size = HW_RXBD_RING_SIZE; 2853 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring; 2854 rmem->dma_arr = rxr->rx_agg_desc_mapping; 2855 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages; 2856 rmem->vmem = (void **)&rxr->rx_agg_ring; 2857 2858 skip_rx: 2859 txr = bnapi->tx_ring; 2860 if (!txr) 2861 continue; 2862 2863 ring = &txr->tx_ring_struct; 2864 rmem = &ring->ring_mem; 2865 rmem->nr_pages = bp->tx_nr_pages; 2866 rmem->page_size = HW_RXBD_RING_SIZE; 2867 rmem->pg_arr = (void **)txr->tx_desc_ring; 2868 rmem->dma_arr = txr->tx_desc_mapping; 2869 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages; 2870 rmem->vmem = (void **)&txr->tx_buf_ring; 2871 } 2872 } 2873 2874 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type) 2875 { 2876 int i; 2877 u32 prod; 2878 struct rx_bd **rx_buf_ring; 2879 2880 rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr; 2881 for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) { 2882 int j; 2883 struct rx_bd *rxbd; 2884 2885 rxbd = rx_buf_ring[i]; 2886 if (!rxbd) 2887 continue; 2888 2889 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) { 2890 rxbd->rx_bd_len_flags_type = cpu_to_le32(type); 2891 rxbd->rx_bd_opaque = prod; 2892 } 2893 } 2894 } 2895 2896 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr) 2897 { 2898 struct net_device *dev = bp->dev; 2899 struct bnxt_rx_ring_info *rxr; 2900 struct bnxt_ring_struct *ring; 2901 u32 prod, type; 2902 int i; 2903 2904 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) | 2905 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP; 2906 2907 if (NET_IP_ALIGN == 2) 2908 type |= RX_BD_FLAGS_SOP; 2909 2910 rxr = &bp->rx_ring[ring_nr]; 2911 ring = &rxr->rx_ring_struct; 2912 bnxt_init_rxbd_pages(ring, type); 2913 2914 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) { 2915 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1); 2916 if (IS_ERR(rxr->xdp_prog)) { 2917 int rc = PTR_ERR(rxr->xdp_prog); 2918 2919 rxr->xdp_prog = NULL; 2920 return rc; 2921 } 2922 } 2923 prod = rxr->rx_prod; 2924 for (i = 0; i < bp->rx_ring_size; i++) { 2925 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) { 2926 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n", 2927 ring_nr, i, bp->rx_ring_size); 2928 break; 2929 } 2930 prod = NEXT_RX(prod); 2931 } 2932 rxr->rx_prod = prod; 2933 ring->fw_ring_id = INVALID_HW_RING_ID; 2934 2935 ring = &rxr->rx_agg_ring_struct; 2936 ring->fw_ring_id = INVALID_HW_RING_ID; 2937 2938 if (!(bp->flags & BNXT_FLAG_AGG_RINGS)) 2939 return 0; 2940 2941 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) | 2942 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP; 2943 2944 bnxt_init_rxbd_pages(ring, type); 2945 2946 prod = rxr->rx_agg_prod; 2947 for (i = 0; i < bp->rx_agg_ring_size; i++) { 2948 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) { 2949 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n", 2950 ring_nr, i, bp->rx_ring_size); 2951 break; 2952 } 2953 prod = NEXT_RX_AGG(prod); 2954 } 2955 rxr->rx_agg_prod = prod; 2956 2957 if (bp->flags & BNXT_FLAG_TPA) { 2958 if (rxr->rx_tpa) { 2959 u8 *data; 2960 dma_addr_t mapping; 2961 2962 for (i = 0; i < MAX_TPA; i++) { 2963 data = __bnxt_alloc_rx_data(bp, &mapping, 2964 GFP_KERNEL); 2965 if (!data) 2966 return -ENOMEM; 2967 2968 rxr->rx_tpa[i].data = data; 2969 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset; 2970 rxr->rx_tpa[i].mapping = mapping; 2971 } 2972 } else { 2973 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n"); 2974 return -ENOMEM; 2975 } 2976 } 2977 2978 return 0; 2979 } 2980 2981 static void bnxt_init_cp_rings(struct bnxt *bp) 2982 { 2983 int i, j; 2984 2985 for (i = 0; i < bp->cp_nr_rings; i++) { 2986 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 2987 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 2988 2989 ring->fw_ring_id = INVALID_HW_RING_ID; 2990 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; 2991 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; 2992 for (j = 0; j < 2; j++) { 2993 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 2994 2995 if (!cpr2) 2996 continue; 2997 2998 ring = &cpr2->cp_ring_struct; 2999 ring->fw_ring_id = INVALID_HW_RING_ID; 3000 cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks; 3001 cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs; 3002 } 3003 } 3004 } 3005 3006 static int bnxt_init_rx_rings(struct bnxt *bp) 3007 { 3008 int i, rc = 0; 3009 3010 if (BNXT_RX_PAGE_MODE(bp)) { 3011 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM; 3012 bp->rx_dma_offset = XDP_PACKET_HEADROOM; 3013 } else { 3014 bp->rx_offset = BNXT_RX_OFFSET; 3015 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET; 3016 } 3017 3018 for (i = 0; i < bp->rx_nr_rings; i++) { 3019 rc = bnxt_init_one_rx_ring(bp, i); 3020 if (rc) 3021 break; 3022 } 3023 3024 return rc; 3025 } 3026 3027 static int bnxt_init_tx_rings(struct bnxt *bp) 3028 { 3029 u16 i; 3030 3031 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2, 3032 MAX_SKB_FRAGS + 1); 3033 3034 for (i = 0; i < bp->tx_nr_rings; i++) { 3035 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 3036 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 3037 3038 ring->fw_ring_id = INVALID_HW_RING_ID; 3039 } 3040 3041 return 0; 3042 } 3043 3044 static void bnxt_free_ring_grps(struct bnxt *bp) 3045 { 3046 kfree(bp->grp_info); 3047 bp->grp_info = NULL; 3048 } 3049 3050 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init) 3051 { 3052 int i; 3053 3054 if (irq_re_init) { 3055 bp->grp_info = kcalloc(bp->cp_nr_rings, 3056 sizeof(struct bnxt_ring_grp_info), 3057 GFP_KERNEL); 3058 if (!bp->grp_info) 3059 return -ENOMEM; 3060 } 3061 for (i = 0; i < bp->cp_nr_rings; i++) { 3062 if (irq_re_init) 3063 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID; 3064 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 3065 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID; 3066 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID; 3067 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 3068 } 3069 return 0; 3070 } 3071 3072 static void bnxt_free_vnics(struct bnxt *bp) 3073 { 3074 kfree(bp->vnic_info); 3075 bp->vnic_info = NULL; 3076 bp->nr_vnics = 0; 3077 } 3078 3079 static int bnxt_alloc_vnics(struct bnxt *bp) 3080 { 3081 int num_vnics = 1; 3082 3083 #ifdef CONFIG_RFS_ACCEL 3084 if (bp->flags & BNXT_FLAG_RFS) 3085 num_vnics += bp->rx_nr_rings; 3086 #endif 3087 3088 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 3089 num_vnics++; 3090 3091 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info), 3092 GFP_KERNEL); 3093 if (!bp->vnic_info) 3094 return -ENOMEM; 3095 3096 bp->nr_vnics = num_vnics; 3097 return 0; 3098 } 3099 3100 static void bnxt_init_vnics(struct bnxt *bp) 3101 { 3102 int i; 3103 3104 for (i = 0; i < bp->nr_vnics; i++) { 3105 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3106 int j; 3107 3108 vnic->fw_vnic_id = INVALID_HW_RING_ID; 3109 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) 3110 vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID; 3111 3112 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID; 3113 3114 if (bp->vnic_info[i].rss_hash_key) { 3115 if (i == 0) 3116 prandom_bytes(vnic->rss_hash_key, 3117 HW_HASH_KEY_SIZE); 3118 else 3119 memcpy(vnic->rss_hash_key, 3120 bp->vnic_info[0].rss_hash_key, 3121 HW_HASH_KEY_SIZE); 3122 } 3123 } 3124 } 3125 3126 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg) 3127 { 3128 int pages; 3129 3130 pages = ring_size / desc_per_pg; 3131 3132 if (!pages) 3133 return 1; 3134 3135 pages++; 3136 3137 while (pages & (pages - 1)) 3138 pages++; 3139 3140 return pages; 3141 } 3142 3143 void bnxt_set_tpa_flags(struct bnxt *bp) 3144 { 3145 bp->flags &= ~BNXT_FLAG_TPA; 3146 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 3147 return; 3148 if (bp->dev->features & NETIF_F_LRO) 3149 bp->flags |= BNXT_FLAG_LRO; 3150 else if (bp->dev->features & NETIF_F_GRO_HW) 3151 bp->flags |= BNXT_FLAG_GRO; 3152 } 3153 3154 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must 3155 * be set on entry. 3156 */ 3157 void bnxt_set_ring_params(struct bnxt *bp) 3158 { 3159 u32 ring_size, rx_size, rx_space; 3160 u32 agg_factor = 0, agg_ring_size = 0; 3161 3162 /* 8 for CRC and VLAN */ 3163 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8); 3164 3165 rx_space = rx_size + NET_SKB_PAD + 3166 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 3167 3168 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH; 3169 ring_size = bp->rx_ring_size; 3170 bp->rx_agg_ring_size = 0; 3171 bp->rx_agg_nr_pages = 0; 3172 3173 if (bp->flags & BNXT_FLAG_TPA) 3174 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE); 3175 3176 bp->flags &= ~BNXT_FLAG_JUMBO; 3177 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) { 3178 u32 jumbo_factor; 3179 3180 bp->flags |= BNXT_FLAG_JUMBO; 3181 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; 3182 if (jumbo_factor > agg_factor) 3183 agg_factor = jumbo_factor; 3184 } 3185 agg_ring_size = ring_size * agg_factor; 3186 3187 if (agg_ring_size) { 3188 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size, 3189 RX_DESC_CNT); 3190 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) { 3191 u32 tmp = agg_ring_size; 3192 3193 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES; 3194 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1; 3195 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n", 3196 tmp, agg_ring_size); 3197 } 3198 bp->rx_agg_ring_size = agg_ring_size; 3199 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1; 3200 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN); 3201 rx_space = rx_size + NET_SKB_PAD + 3202 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 3203 } 3204 3205 bp->rx_buf_use_size = rx_size; 3206 bp->rx_buf_size = rx_space; 3207 3208 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT); 3209 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1; 3210 3211 ring_size = bp->tx_ring_size; 3212 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT); 3213 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1; 3214 3215 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size; 3216 bp->cp_ring_size = ring_size; 3217 3218 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT); 3219 if (bp->cp_nr_pages > MAX_CP_PAGES) { 3220 bp->cp_nr_pages = MAX_CP_PAGES; 3221 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1; 3222 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n", 3223 ring_size, bp->cp_ring_size); 3224 } 3225 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT; 3226 bp->cp_ring_mask = bp->cp_bit - 1; 3227 } 3228 3229 /* Changing allocation mode of RX rings. 3230 * TODO: Update when extending xdp_rxq_info to support allocation modes. 3231 */ 3232 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode) 3233 { 3234 if (page_mode) { 3235 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU) 3236 return -EOPNOTSUPP; 3237 bp->dev->max_mtu = 3238 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU); 3239 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 3240 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE; 3241 bp->rx_dir = DMA_BIDIRECTIONAL; 3242 bp->rx_skb_func = bnxt_rx_page_skb; 3243 /* Disable LRO or GRO_HW */ 3244 netdev_update_features(bp->dev); 3245 } else { 3246 bp->dev->max_mtu = bp->max_mtu; 3247 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE; 3248 bp->rx_dir = DMA_FROM_DEVICE; 3249 bp->rx_skb_func = bnxt_rx_skb; 3250 } 3251 return 0; 3252 } 3253 3254 static void bnxt_free_vnic_attributes(struct bnxt *bp) 3255 { 3256 int i; 3257 struct bnxt_vnic_info *vnic; 3258 struct pci_dev *pdev = bp->pdev; 3259 3260 if (!bp->vnic_info) 3261 return; 3262 3263 for (i = 0; i < bp->nr_vnics; i++) { 3264 vnic = &bp->vnic_info[i]; 3265 3266 kfree(vnic->fw_grp_ids); 3267 vnic->fw_grp_ids = NULL; 3268 3269 kfree(vnic->uc_list); 3270 vnic->uc_list = NULL; 3271 3272 if (vnic->mc_list) { 3273 dma_free_coherent(&pdev->dev, vnic->mc_list_size, 3274 vnic->mc_list, vnic->mc_list_mapping); 3275 vnic->mc_list = NULL; 3276 } 3277 3278 if (vnic->rss_table) { 3279 dma_free_coherent(&pdev->dev, PAGE_SIZE, 3280 vnic->rss_table, 3281 vnic->rss_table_dma_addr); 3282 vnic->rss_table = NULL; 3283 } 3284 3285 vnic->rss_hash_key = NULL; 3286 vnic->flags = 0; 3287 } 3288 } 3289 3290 static int bnxt_alloc_vnic_attributes(struct bnxt *bp) 3291 { 3292 int i, rc = 0, size; 3293 struct bnxt_vnic_info *vnic; 3294 struct pci_dev *pdev = bp->pdev; 3295 int max_rings; 3296 3297 for (i = 0; i < bp->nr_vnics; i++) { 3298 vnic = &bp->vnic_info[i]; 3299 3300 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) { 3301 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN; 3302 3303 if (mem_size > 0) { 3304 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL); 3305 if (!vnic->uc_list) { 3306 rc = -ENOMEM; 3307 goto out; 3308 } 3309 } 3310 } 3311 3312 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) { 3313 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN; 3314 vnic->mc_list = 3315 dma_alloc_coherent(&pdev->dev, 3316 vnic->mc_list_size, 3317 &vnic->mc_list_mapping, 3318 GFP_KERNEL); 3319 if (!vnic->mc_list) { 3320 rc = -ENOMEM; 3321 goto out; 3322 } 3323 } 3324 3325 if (bp->flags & BNXT_FLAG_CHIP_P5) 3326 goto vnic_skip_grps; 3327 3328 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 3329 max_rings = bp->rx_nr_rings; 3330 else 3331 max_rings = 1; 3332 3333 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL); 3334 if (!vnic->fw_grp_ids) { 3335 rc = -ENOMEM; 3336 goto out; 3337 } 3338 vnic_skip_grps: 3339 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) && 3340 !(vnic->flags & BNXT_VNIC_RSS_FLAG)) 3341 continue; 3342 3343 /* Allocate rss table and hash key */ 3344 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 3345 &vnic->rss_table_dma_addr, 3346 GFP_KERNEL); 3347 if (!vnic->rss_table) { 3348 rc = -ENOMEM; 3349 goto out; 3350 } 3351 3352 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16)); 3353 3354 vnic->rss_hash_key = ((void *)vnic->rss_table) + size; 3355 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; 3356 } 3357 return 0; 3358 3359 out: 3360 return rc; 3361 } 3362 3363 static void bnxt_free_hwrm_resources(struct bnxt *bp) 3364 { 3365 struct pci_dev *pdev = bp->pdev; 3366 3367 if (bp->hwrm_cmd_resp_addr) { 3368 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr, 3369 bp->hwrm_cmd_resp_dma_addr); 3370 bp->hwrm_cmd_resp_addr = NULL; 3371 } 3372 3373 if (bp->hwrm_cmd_kong_resp_addr) { 3374 dma_free_coherent(&pdev->dev, PAGE_SIZE, 3375 bp->hwrm_cmd_kong_resp_addr, 3376 bp->hwrm_cmd_kong_resp_dma_addr); 3377 bp->hwrm_cmd_kong_resp_addr = NULL; 3378 } 3379 } 3380 3381 static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp) 3382 { 3383 struct pci_dev *pdev = bp->pdev; 3384 3385 bp->hwrm_cmd_kong_resp_addr = 3386 dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 3387 &bp->hwrm_cmd_kong_resp_dma_addr, 3388 GFP_KERNEL); 3389 if (!bp->hwrm_cmd_kong_resp_addr) 3390 return -ENOMEM; 3391 3392 return 0; 3393 } 3394 3395 static int bnxt_alloc_hwrm_resources(struct bnxt *bp) 3396 { 3397 struct pci_dev *pdev = bp->pdev; 3398 3399 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 3400 &bp->hwrm_cmd_resp_dma_addr, 3401 GFP_KERNEL); 3402 if (!bp->hwrm_cmd_resp_addr) 3403 return -ENOMEM; 3404 3405 return 0; 3406 } 3407 3408 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp) 3409 { 3410 if (bp->hwrm_short_cmd_req_addr) { 3411 struct pci_dev *pdev = bp->pdev; 3412 3413 dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len, 3414 bp->hwrm_short_cmd_req_addr, 3415 bp->hwrm_short_cmd_req_dma_addr); 3416 bp->hwrm_short_cmd_req_addr = NULL; 3417 } 3418 } 3419 3420 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp) 3421 { 3422 struct pci_dev *pdev = bp->pdev; 3423 3424 bp->hwrm_short_cmd_req_addr = 3425 dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len, 3426 &bp->hwrm_short_cmd_req_dma_addr, 3427 GFP_KERNEL); 3428 if (!bp->hwrm_short_cmd_req_addr) 3429 return -ENOMEM; 3430 3431 return 0; 3432 } 3433 3434 static void bnxt_free_port_stats(struct bnxt *bp) 3435 { 3436 struct pci_dev *pdev = bp->pdev; 3437 3438 bp->flags &= ~BNXT_FLAG_PORT_STATS; 3439 bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT; 3440 3441 if (bp->hw_rx_port_stats) { 3442 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size, 3443 bp->hw_rx_port_stats, 3444 bp->hw_rx_port_stats_map); 3445 bp->hw_rx_port_stats = NULL; 3446 } 3447 3448 if (bp->hw_tx_port_stats_ext) { 3449 dma_free_coherent(&pdev->dev, sizeof(struct tx_port_stats_ext), 3450 bp->hw_tx_port_stats_ext, 3451 bp->hw_tx_port_stats_ext_map); 3452 bp->hw_tx_port_stats_ext = NULL; 3453 } 3454 3455 if (bp->hw_rx_port_stats_ext) { 3456 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext), 3457 bp->hw_rx_port_stats_ext, 3458 bp->hw_rx_port_stats_ext_map); 3459 bp->hw_rx_port_stats_ext = NULL; 3460 } 3461 3462 if (bp->hw_pcie_stats) { 3463 dma_free_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats), 3464 bp->hw_pcie_stats, bp->hw_pcie_stats_map); 3465 bp->hw_pcie_stats = NULL; 3466 } 3467 } 3468 3469 static void bnxt_free_ring_stats(struct bnxt *bp) 3470 { 3471 struct pci_dev *pdev = bp->pdev; 3472 int size, i; 3473 3474 if (!bp->bnapi) 3475 return; 3476 3477 size = sizeof(struct ctx_hw_stats); 3478 3479 for (i = 0; i < bp->cp_nr_rings; i++) { 3480 struct bnxt_napi *bnapi = bp->bnapi[i]; 3481 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3482 3483 if (cpr->hw_stats) { 3484 dma_free_coherent(&pdev->dev, size, cpr->hw_stats, 3485 cpr->hw_stats_map); 3486 cpr->hw_stats = NULL; 3487 } 3488 } 3489 } 3490 3491 static int bnxt_alloc_stats(struct bnxt *bp) 3492 { 3493 u32 size, i; 3494 struct pci_dev *pdev = bp->pdev; 3495 3496 size = sizeof(struct ctx_hw_stats); 3497 3498 for (i = 0; i < bp->cp_nr_rings; i++) { 3499 struct bnxt_napi *bnapi = bp->bnapi[i]; 3500 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3501 3502 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size, 3503 &cpr->hw_stats_map, 3504 GFP_KERNEL); 3505 if (!cpr->hw_stats) 3506 return -ENOMEM; 3507 3508 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 3509 } 3510 3511 if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700) 3512 return 0; 3513 3514 if (bp->hw_rx_port_stats) 3515 goto alloc_ext_stats; 3516 3517 bp->hw_port_stats_size = sizeof(struct rx_port_stats) + 3518 sizeof(struct tx_port_stats) + 1024; 3519 3520 bp->hw_rx_port_stats = 3521 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size, 3522 &bp->hw_rx_port_stats_map, 3523 GFP_KERNEL); 3524 if (!bp->hw_rx_port_stats) 3525 return -ENOMEM; 3526 3527 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) + 512; 3528 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map + 3529 sizeof(struct rx_port_stats) + 512; 3530 bp->flags |= BNXT_FLAG_PORT_STATS; 3531 3532 alloc_ext_stats: 3533 /* Display extended statistics only if FW supports it */ 3534 if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900) 3535 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) 3536 return 0; 3537 3538 if (bp->hw_rx_port_stats_ext) 3539 goto alloc_tx_ext_stats; 3540 3541 bp->hw_rx_port_stats_ext = 3542 dma_alloc_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext), 3543 &bp->hw_rx_port_stats_ext_map, GFP_KERNEL); 3544 if (!bp->hw_rx_port_stats_ext) 3545 return 0; 3546 3547 alloc_tx_ext_stats: 3548 if (bp->hw_tx_port_stats_ext) 3549 goto alloc_pcie_stats; 3550 3551 if (bp->hwrm_spec_code >= 0x10902 || 3552 (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) { 3553 bp->hw_tx_port_stats_ext = 3554 dma_alloc_coherent(&pdev->dev, 3555 sizeof(struct tx_port_stats_ext), 3556 &bp->hw_tx_port_stats_ext_map, 3557 GFP_KERNEL); 3558 } 3559 bp->flags |= BNXT_FLAG_PORT_STATS_EXT; 3560 3561 alloc_pcie_stats: 3562 if (bp->hw_pcie_stats || 3563 !(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 3564 return 0; 3565 3566 bp->hw_pcie_stats = 3567 dma_alloc_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats), 3568 &bp->hw_pcie_stats_map, GFP_KERNEL); 3569 if (!bp->hw_pcie_stats) 3570 return 0; 3571 3572 bp->flags |= BNXT_FLAG_PCIE_STATS; 3573 return 0; 3574 } 3575 3576 static void bnxt_clear_ring_indices(struct bnxt *bp) 3577 { 3578 int i; 3579 3580 if (!bp->bnapi) 3581 return; 3582 3583 for (i = 0; i < bp->cp_nr_rings; i++) { 3584 struct bnxt_napi *bnapi = bp->bnapi[i]; 3585 struct bnxt_cp_ring_info *cpr; 3586 struct bnxt_rx_ring_info *rxr; 3587 struct bnxt_tx_ring_info *txr; 3588 3589 if (!bnapi) 3590 continue; 3591 3592 cpr = &bnapi->cp_ring; 3593 cpr->cp_raw_cons = 0; 3594 3595 txr = bnapi->tx_ring; 3596 if (txr) { 3597 txr->tx_prod = 0; 3598 txr->tx_cons = 0; 3599 } 3600 3601 rxr = bnapi->rx_ring; 3602 if (rxr) { 3603 rxr->rx_prod = 0; 3604 rxr->rx_agg_prod = 0; 3605 rxr->rx_sw_agg_prod = 0; 3606 rxr->rx_next_cons = 0; 3607 } 3608 } 3609 } 3610 3611 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit) 3612 { 3613 #ifdef CONFIG_RFS_ACCEL 3614 int i; 3615 3616 /* Under rtnl_lock and all our NAPIs have been disabled. It's 3617 * safe to delete the hash table. 3618 */ 3619 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 3620 struct hlist_head *head; 3621 struct hlist_node *tmp; 3622 struct bnxt_ntuple_filter *fltr; 3623 3624 head = &bp->ntp_fltr_hash_tbl[i]; 3625 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 3626 hlist_del(&fltr->hash); 3627 kfree(fltr); 3628 } 3629 } 3630 if (irq_reinit) { 3631 kfree(bp->ntp_fltr_bmap); 3632 bp->ntp_fltr_bmap = NULL; 3633 } 3634 bp->ntp_fltr_count = 0; 3635 #endif 3636 } 3637 3638 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp) 3639 { 3640 #ifdef CONFIG_RFS_ACCEL 3641 int i, rc = 0; 3642 3643 if (!(bp->flags & BNXT_FLAG_RFS)) 3644 return 0; 3645 3646 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) 3647 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]); 3648 3649 bp->ntp_fltr_count = 0; 3650 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR), 3651 sizeof(long), 3652 GFP_KERNEL); 3653 3654 if (!bp->ntp_fltr_bmap) 3655 rc = -ENOMEM; 3656 3657 return rc; 3658 #else 3659 return 0; 3660 #endif 3661 } 3662 3663 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init) 3664 { 3665 bnxt_free_vnic_attributes(bp); 3666 bnxt_free_tx_rings(bp); 3667 bnxt_free_rx_rings(bp); 3668 bnxt_free_cp_rings(bp); 3669 bnxt_free_ntp_fltrs(bp, irq_re_init); 3670 if (irq_re_init) { 3671 bnxt_free_ring_stats(bp); 3672 bnxt_free_ring_grps(bp); 3673 bnxt_free_vnics(bp); 3674 kfree(bp->tx_ring_map); 3675 bp->tx_ring_map = NULL; 3676 kfree(bp->tx_ring); 3677 bp->tx_ring = NULL; 3678 kfree(bp->rx_ring); 3679 bp->rx_ring = NULL; 3680 kfree(bp->bnapi); 3681 bp->bnapi = NULL; 3682 } else { 3683 bnxt_clear_ring_indices(bp); 3684 } 3685 } 3686 3687 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init) 3688 { 3689 int i, j, rc, size, arr_size; 3690 void *bnapi; 3691 3692 if (irq_re_init) { 3693 /* Allocate bnapi mem pointer array and mem block for 3694 * all queues 3695 */ 3696 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) * 3697 bp->cp_nr_rings); 3698 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi)); 3699 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL); 3700 if (!bnapi) 3701 return -ENOMEM; 3702 3703 bp->bnapi = bnapi; 3704 bnapi += arr_size; 3705 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) { 3706 bp->bnapi[i] = bnapi; 3707 bp->bnapi[i]->index = i; 3708 bp->bnapi[i]->bp = bp; 3709 if (bp->flags & BNXT_FLAG_CHIP_P5) { 3710 struct bnxt_cp_ring_info *cpr = 3711 &bp->bnapi[i]->cp_ring; 3712 3713 cpr->cp_ring_struct.ring_mem.flags = 3714 BNXT_RMEM_RING_PTE_FLAG; 3715 } 3716 } 3717 3718 bp->rx_ring = kcalloc(bp->rx_nr_rings, 3719 sizeof(struct bnxt_rx_ring_info), 3720 GFP_KERNEL); 3721 if (!bp->rx_ring) 3722 return -ENOMEM; 3723 3724 for (i = 0; i < bp->rx_nr_rings; i++) { 3725 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 3726 3727 if (bp->flags & BNXT_FLAG_CHIP_P5) { 3728 rxr->rx_ring_struct.ring_mem.flags = 3729 BNXT_RMEM_RING_PTE_FLAG; 3730 rxr->rx_agg_ring_struct.ring_mem.flags = 3731 BNXT_RMEM_RING_PTE_FLAG; 3732 } 3733 rxr->bnapi = bp->bnapi[i]; 3734 bp->bnapi[i]->rx_ring = &bp->rx_ring[i]; 3735 } 3736 3737 bp->tx_ring = kcalloc(bp->tx_nr_rings, 3738 sizeof(struct bnxt_tx_ring_info), 3739 GFP_KERNEL); 3740 if (!bp->tx_ring) 3741 return -ENOMEM; 3742 3743 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16), 3744 GFP_KERNEL); 3745 3746 if (!bp->tx_ring_map) 3747 return -ENOMEM; 3748 3749 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 3750 j = 0; 3751 else 3752 j = bp->rx_nr_rings; 3753 3754 for (i = 0; i < bp->tx_nr_rings; i++, j++) { 3755 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 3756 3757 if (bp->flags & BNXT_FLAG_CHIP_P5) 3758 txr->tx_ring_struct.ring_mem.flags = 3759 BNXT_RMEM_RING_PTE_FLAG; 3760 txr->bnapi = bp->bnapi[j]; 3761 bp->bnapi[j]->tx_ring = txr; 3762 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i; 3763 if (i >= bp->tx_nr_rings_xdp) { 3764 txr->txq_index = i - bp->tx_nr_rings_xdp; 3765 bp->bnapi[j]->tx_int = bnxt_tx_int; 3766 } else { 3767 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP; 3768 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp; 3769 } 3770 } 3771 3772 rc = bnxt_alloc_stats(bp); 3773 if (rc) 3774 goto alloc_mem_err; 3775 3776 rc = bnxt_alloc_ntp_fltrs(bp); 3777 if (rc) 3778 goto alloc_mem_err; 3779 3780 rc = bnxt_alloc_vnics(bp); 3781 if (rc) 3782 goto alloc_mem_err; 3783 } 3784 3785 bnxt_init_ring_struct(bp); 3786 3787 rc = bnxt_alloc_rx_rings(bp); 3788 if (rc) 3789 goto alloc_mem_err; 3790 3791 rc = bnxt_alloc_tx_rings(bp); 3792 if (rc) 3793 goto alloc_mem_err; 3794 3795 rc = bnxt_alloc_cp_rings(bp); 3796 if (rc) 3797 goto alloc_mem_err; 3798 3799 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG | 3800 BNXT_VNIC_UCAST_FLAG; 3801 rc = bnxt_alloc_vnic_attributes(bp); 3802 if (rc) 3803 goto alloc_mem_err; 3804 return 0; 3805 3806 alloc_mem_err: 3807 bnxt_free_mem(bp, true); 3808 return rc; 3809 } 3810 3811 static void bnxt_disable_int(struct bnxt *bp) 3812 { 3813 int i; 3814 3815 if (!bp->bnapi) 3816 return; 3817 3818 for (i = 0; i < bp->cp_nr_rings; i++) { 3819 struct bnxt_napi *bnapi = bp->bnapi[i]; 3820 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3821 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 3822 3823 if (ring->fw_ring_id != INVALID_HW_RING_ID) 3824 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); 3825 } 3826 } 3827 3828 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n) 3829 { 3830 struct bnxt_napi *bnapi = bp->bnapi[n]; 3831 struct bnxt_cp_ring_info *cpr; 3832 3833 cpr = &bnapi->cp_ring; 3834 return cpr->cp_ring_struct.map_idx; 3835 } 3836 3837 static void bnxt_disable_int_sync(struct bnxt *bp) 3838 { 3839 int i; 3840 3841 atomic_inc(&bp->intr_sem); 3842 3843 bnxt_disable_int(bp); 3844 for (i = 0; i < bp->cp_nr_rings; i++) { 3845 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 3846 3847 synchronize_irq(bp->irq_tbl[map_idx].vector); 3848 } 3849 } 3850 3851 static void bnxt_enable_int(struct bnxt *bp) 3852 { 3853 int i; 3854 3855 atomic_set(&bp->intr_sem, 0); 3856 for (i = 0; i < bp->cp_nr_rings; i++) { 3857 struct bnxt_napi *bnapi = bp->bnapi[i]; 3858 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 3859 3860 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons); 3861 } 3862 } 3863 3864 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type, 3865 u16 cmpl_ring, u16 target_id) 3866 { 3867 struct input *req = request; 3868 3869 req->req_type = cpu_to_le16(req_type); 3870 req->cmpl_ring = cpu_to_le16(cmpl_ring); 3871 req->target_id = cpu_to_le16(target_id); 3872 if (bnxt_kong_hwrm_message(bp, req)) 3873 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr); 3874 else 3875 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr); 3876 } 3877 3878 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len, 3879 int timeout, bool silent) 3880 { 3881 int i, intr_process, rc, tmo_count; 3882 struct input *req = msg; 3883 u32 *data = msg; 3884 __le32 *resp_len; 3885 u8 *valid; 3886 u16 cp_ring_id, len = 0; 3887 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr; 3888 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN; 3889 struct hwrm_short_input short_input = {0}; 3890 u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER; 3891 u8 *resp_addr = (u8 *)bp->hwrm_cmd_resp_addr; 3892 u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM; 3893 u16 dst = BNXT_HWRM_CHNL_CHIMP; 3894 3895 if (msg_len > BNXT_HWRM_MAX_REQ_LEN) { 3896 if (msg_len > bp->hwrm_max_ext_req_len || 3897 !bp->hwrm_short_cmd_req_addr) 3898 return -EINVAL; 3899 } 3900 3901 if (bnxt_hwrm_kong_chnl(bp, req)) { 3902 dst = BNXT_HWRM_CHNL_KONG; 3903 bar_offset = BNXT_GRCPF_REG_KONG_COMM; 3904 doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER; 3905 resp = bp->hwrm_cmd_kong_resp_addr; 3906 resp_addr = (u8 *)bp->hwrm_cmd_kong_resp_addr; 3907 } 3908 3909 memset(resp, 0, PAGE_SIZE); 3910 cp_ring_id = le16_to_cpu(req->cmpl_ring); 3911 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1; 3912 3913 req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst)); 3914 /* currently supports only one outstanding message */ 3915 if (intr_process) 3916 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id); 3917 3918 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) || 3919 msg_len > BNXT_HWRM_MAX_REQ_LEN) { 3920 void *short_cmd_req = bp->hwrm_short_cmd_req_addr; 3921 u16 max_msg_len; 3922 3923 /* Set boundary for maximum extended request length for short 3924 * cmd format. If passed up from device use the max supported 3925 * internal req length. 3926 */ 3927 max_msg_len = bp->hwrm_max_ext_req_len; 3928 3929 memcpy(short_cmd_req, req, msg_len); 3930 if (msg_len < max_msg_len) 3931 memset(short_cmd_req + msg_len, 0, 3932 max_msg_len - msg_len); 3933 3934 short_input.req_type = req->req_type; 3935 short_input.signature = 3936 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD); 3937 short_input.size = cpu_to_le16(msg_len); 3938 short_input.req_addr = 3939 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr); 3940 3941 data = (u32 *)&short_input; 3942 msg_len = sizeof(short_input); 3943 3944 /* Sync memory write before updating doorbell */ 3945 wmb(); 3946 3947 max_req_len = BNXT_HWRM_SHORT_REQ_LEN; 3948 } 3949 3950 /* Write request msg to hwrm channel */ 3951 __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4); 3952 3953 for (i = msg_len; i < max_req_len; i += 4) 3954 writel(0, bp->bar0 + bar_offset + i); 3955 3956 /* Ring channel doorbell */ 3957 writel(1, bp->bar0 + doorbell_offset); 3958 3959 if (!timeout) 3960 timeout = DFLT_HWRM_CMD_TIMEOUT; 3961 /* convert timeout to usec */ 3962 timeout *= 1000; 3963 3964 i = 0; 3965 /* Short timeout for the first few iterations: 3966 * number of loops = number of loops for short timeout + 3967 * number of loops for standard timeout. 3968 */ 3969 tmo_count = HWRM_SHORT_TIMEOUT_COUNTER; 3970 timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER; 3971 tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT); 3972 resp_len = (__le32 *)(resp_addr + HWRM_RESP_LEN_OFFSET); 3973 3974 if (intr_process) { 3975 u16 seq_id = bp->hwrm_intr_seq_id; 3976 3977 /* Wait until hwrm response cmpl interrupt is processed */ 3978 while (bp->hwrm_intr_seq_id != (u16)~seq_id && 3979 i++ < tmo_count) { 3980 /* on first few passes, just barely sleep */ 3981 if (i < HWRM_SHORT_TIMEOUT_COUNTER) 3982 usleep_range(HWRM_SHORT_MIN_TIMEOUT, 3983 HWRM_SHORT_MAX_TIMEOUT); 3984 else 3985 usleep_range(HWRM_MIN_TIMEOUT, 3986 HWRM_MAX_TIMEOUT); 3987 } 3988 3989 if (bp->hwrm_intr_seq_id != (u16)~seq_id) { 3990 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n", 3991 le16_to_cpu(req->req_type)); 3992 return -1; 3993 } 3994 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >> 3995 HWRM_RESP_LEN_SFT; 3996 valid = resp_addr + len - 1; 3997 } else { 3998 int j; 3999 4000 /* Check if response len is updated */ 4001 for (i = 0; i < tmo_count; i++) { 4002 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >> 4003 HWRM_RESP_LEN_SFT; 4004 if (len) 4005 break; 4006 /* on first few passes, just barely sleep */ 4007 if (i < HWRM_SHORT_TIMEOUT_COUNTER) 4008 usleep_range(HWRM_SHORT_MIN_TIMEOUT, 4009 HWRM_SHORT_MAX_TIMEOUT); 4010 else 4011 usleep_range(HWRM_MIN_TIMEOUT, 4012 HWRM_MAX_TIMEOUT); 4013 } 4014 4015 if (i >= tmo_count) { 4016 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n", 4017 HWRM_TOTAL_TIMEOUT(i), 4018 le16_to_cpu(req->req_type), 4019 le16_to_cpu(req->seq_id), len); 4020 return -1; 4021 } 4022 4023 /* Last byte of resp contains valid bit */ 4024 valid = resp_addr + len - 1; 4025 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) { 4026 /* make sure we read from updated DMA memory */ 4027 dma_rmb(); 4028 if (*valid) 4029 break; 4030 usleep_range(1, 5); 4031 } 4032 4033 if (j >= HWRM_VALID_BIT_DELAY_USEC) { 4034 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n", 4035 HWRM_TOTAL_TIMEOUT(i), 4036 le16_to_cpu(req->req_type), 4037 le16_to_cpu(req->seq_id), len, *valid); 4038 return -1; 4039 } 4040 } 4041 4042 /* Zero valid bit for compatibility. Valid bit in an older spec 4043 * may become a new field in a newer spec. We must make sure that 4044 * a new field not implemented by old spec will read zero. 4045 */ 4046 *valid = 0; 4047 rc = le16_to_cpu(resp->error_code); 4048 if (rc && !silent) 4049 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n", 4050 le16_to_cpu(resp->req_type), 4051 le16_to_cpu(resp->seq_id), rc); 4052 return rc; 4053 } 4054 4055 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 4056 { 4057 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false); 4058 } 4059 4060 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, 4061 int timeout) 4062 { 4063 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); 4064 } 4065 4066 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) 4067 { 4068 int rc; 4069 4070 mutex_lock(&bp->hwrm_cmd_lock); 4071 rc = _hwrm_send_message(bp, msg, msg_len, timeout); 4072 mutex_unlock(&bp->hwrm_cmd_lock); 4073 return rc; 4074 } 4075 4076 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len, 4077 int timeout) 4078 { 4079 int rc; 4080 4081 mutex_lock(&bp->hwrm_cmd_lock); 4082 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true); 4083 mutex_unlock(&bp->hwrm_cmd_lock); 4084 return rc; 4085 } 4086 4087 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap, 4088 int bmap_size) 4089 { 4090 struct hwrm_func_drv_rgtr_input req = {0}; 4091 DECLARE_BITMAP(async_events_bmap, 256); 4092 u32 *events = (u32 *)async_events_bmap; 4093 int i; 4094 4095 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); 4096 4097 req.enables = 4098 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); 4099 4100 memset(async_events_bmap, 0, sizeof(async_events_bmap)); 4101 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) 4102 __set_bit(bnxt_async_events_arr[i], async_events_bmap); 4103 4104 if (bmap && bmap_size) { 4105 for (i = 0; i < bmap_size; i++) { 4106 if (test_bit(i, bmap)) 4107 __set_bit(i, async_events_bmap); 4108 } 4109 } 4110 4111 for (i = 0; i < 8; i++) 4112 req.async_event_fwd[i] |= cpu_to_le32(events[i]); 4113 4114 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4115 } 4116 4117 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp) 4118 { 4119 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr; 4120 struct hwrm_func_drv_rgtr_input req = {0}; 4121 int rc; 4122 4123 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); 4124 4125 req.enables = 4126 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE | 4127 FUNC_DRV_RGTR_REQ_ENABLES_VER); 4128 4129 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX); 4130 req.flags = cpu_to_le32(FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE); 4131 req.ver_maj_8b = DRV_VER_MAJ; 4132 req.ver_min_8b = DRV_VER_MIN; 4133 req.ver_upd_8b = DRV_VER_UPD; 4134 req.ver_maj = cpu_to_le16(DRV_VER_MAJ); 4135 req.ver_min = cpu_to_le16(DRV_VER_MIN); 4136 req.ver_upd = cpu_to_le16(DRV_VER_UPD); 4137 4138 if (BNXT_PF(bp)) { 4139 u32 data[8]; 4140 int i; 4141 4142 memset(data, 0, sizeof(data)); 4143 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) { 4144 u16 cmd = bnxt_vf_req_snif[i]; 4145 unsigned int bit, idx; 4146 4147 idx = cmd / 32; 4148 bit = cmd % 32; 4149 data[idx] |= 1 << bit; 4150 } 4151 4152 for (i = 0; i < 8; i++) 4153 req.vf_req_fwd[i] = cpu_to_le32(data[i]); 4154 4155 req.enables |= 4156 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD); 4157 } 4158 4159 if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE) 4160 req.flags |= cpu_to_le32( 4161 FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE); 4162 4163 mutex_lock(&bp->hwrm_cmd_lock); 4164 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4165 if (rc) 4166 rc = -EIO; 4167 else if (resp->flags & 4168 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED)) 4169 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE; 4170 mutex_unlock(&bp->hwrm_cmd_lock); 4171 return rc; 4172 } 4173 4174 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp) 4175 { 4176 struct hwrm_func_drv_unrgtr_input req = {0}; 4177 4178 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1); 4179 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4180 } 4181 4182 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type) 4183 { 4184 u32 rc = 0; 4185 struct hwrm_tunnel_dst_port_free_input req = {0}; 4186 4187 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1); 4188 req.tunnel_type = tunnel_type; 4189 4190 switch (tunnel_type) { 4191 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN: 4192 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id; 4193 break; 4194 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE: 4195 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id; 4196 break; 4197 default: 4198 break; 4199 } 4200 4201 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4202 if (rc) 4203 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n", 4204 rc); 4205 return rc; 4206 } 4207 4208 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port, 4209 u8 tunnel_type) 4210 { 4211 u32 rc = 0; 4212 struct hwrm_tunnel_dst_port_alloc_input req = {0}; 4213 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4214 4215 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1); 4216 4217 req.tunnel_type = tunnel_type; 4218 req.tunnel_dst_port_val = port; 4219 4220 mutex_lock(&bp->hwrm_cmd_lock); 4221 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4222 if (rc) { 4223 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n", 4224 rc); 4225 goto err_out; 4226 } 4227 4228 switch (tunnel_type) { 4229 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN: 4230 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id; 4231 break; 4232 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE: 4233 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id; 4234 break; 4235 default: 4236 break; 4237 } 4238 4239 err_out: 4240 mutex_unlock(&bp->hwrm_cmd_lock); 4241 return rc; 4242 } 4243 4244 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id) 4245 { 4246 struct hwrm_cfa_l2_set_rx_mask_input req = {0}; 4247 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4248 4249 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1); 4250 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 4251 4252 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count); 4253 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping); 4254 req.mask = cpu_to_le32(vnic->rx_mask); 4255 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4256 } 4257 4258 #ifdef CONFIG_RFS_ACCEL 4259 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp, 4260 struct bnxt_ntuple_filter *fltr) 4261 { 4262 struct hwrm_cfa_ntuple_filter_free_input req = {0}; 4263 4264 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1); 4265 req.ntuple_filter_id = fltr->filter_id; 4266 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4267 } 4268 4269 #define BNXT_NTP_FLTR_FLAGS \ 4270 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \ 4271 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \ 4272 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \ 4273 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \ 4274 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \ 4275 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \ 4276 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \ 4277 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \ 4278 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \ 4279 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \ 4280 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \ 4281 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \ 4282 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \ 4283 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID) 4284 4285 #define BNXT_NTP_TUNNEL_FLTR_FLAG \ 4286 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 4287 4288 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp, 4289 struct bnxt_ntuple_filter *fltr) 4290 { 4291 struct hwrm_cfa_ntuple_filter_alloc_input req = {0}; 4292 struct hwrm_cfa_ntuple_filter_alloc_output *resp; 4293 struct flow_keys *keys = &fltr->fkeys; 4294 struct bnxt_vnic_info *vnic; 4295 u32 dst_ena = 0; 4296 int rc = 0; 4297 4298 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1); 4299 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx]; 4300 4301 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX) { 4302 dst_ena = CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX; 4303 req.rfs_ring_tbl_idx = cpu_to_le16(fltr->rxq); 4304 vnic = &bp->vnic_info[0]; 4305 } else { 4306 vnic = &bp->vnic_info[fltr->rxq + 1]; 4307 } 4308 req.dst_id = cpu_to_le16(vnic->fw_vnic_id); 4309 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS | dst_ena); 4310 4311 req.ethertype = htons(ETH_P_IP); 4312 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN); 4313 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4; 4314 req.ip_protocol = keys->basic.ip_proto; 4315 4316 if (keys->basic.n_proto == htons(ETH_P_IPV6)) { 4317 int i; 4318 4319 req.ethertype = htons(ETH_P_IPV6); 4320 req.ip_addr_type = 4321 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6; 4322 *(struct in6_addr *)&req.src_ipaddr[0] = 4323 keys->addrs.v6addrs.src; 4324 *(struct in6_addr *)&req.dst_ipaddr[0] = 4325 keys->addrs.v6addrs.dst; 4326 for (i = 0; i < 4; i++) { 4327 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 4328 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff); 4329 } 4330 } else { 4331 req.src_ipaddr[0] = keys->addrs.v4addrs.src; 4332 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 4333 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst; 4334 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff); 4335 } 4336 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) { 4337 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG); 4338 req.tunnel_type = 4339 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL; 4340 } 4341 4342 req.src_port = keys->ports.src; 4343 req.src_port_mask = cpu_to_be16(0xffff); 4344 req.dst_port = keys->ports.dst; 4345 req.dst_port_mask = cpu_to_be16(0xffff); 4346 4347 mutex_lock(&bp->hwrm_cmd_lock); 4348 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4349 if (!rc) { 4350 resp = bnxt_get_hwrm_resp_addr(bp, &req); 4351 fltr->filter_id = resp->ntuple_filter_id; 4352 } 4353 mutex_unlock(&bp->hwrm_cmd_lock); 4354 return rc; 4355 } 4356 #endif 4357 4358 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx, 4359 u8 *mac_addr) 4360 { 4361 u32 rc = 0; 4362 struct hwrm_cfa_l2_filter_alloc_input req = {0}; 4363 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4364 4365 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1); 4366 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX); 4367 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) 4368 req.flags |= 4369 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST); 4370 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id); 4371 req.enables = 4372 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR | 4373 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID | 4374 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK); 4375 memcpy(req.l2_addr, mac_addr, ETH_ALEN); 4376 req.l2_addr_mask[0] = 0xff; 4377 req.l2_addr_mask[1] = 0xff; 4378 req.l2_addr_mask[2] = 0xff; 4379 req.l2_addr_mask[3] = 0xff; 4380 req.l2_addr_mask[4] = 0xff; 4381 req.l2_addr_mask[5] = 0xff; 4382 4383 mutex_lock(&bp->hwrm_cmd_lock); 4384 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4385 if (!rc) 4386 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] = 4387 resp->l2_filter_id; 4388 mutex_unlock(&bp->hwrm_cmd_lock); 4389 return rc; 4390 } 4391 4392 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp) 4393 { 4394 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */ 4395 int rc = 0; 4396 4397 /* Any associated ntuple filters will also be cleared by firmware. */ 4398 mutex_lock(&bp->hwrm_cmd_lock); 4399 for (i = 0; i < num_of_vnics; i++) { 4400 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 4401 4402 for (j = 0; j < vnic->uc_filter_count; j++) { 4403 struct hwrm_cfa_l2_filter_free_input req = {0}; 4404 4405 bnxt_hwrm_cmd_hdr_init(bp, &req, 4406 HWRM_CFA_L2_FILTER_FREE, -1, -1); 4407 4408 req.l2_filter_id = vnic->fw_l2_filter_id[j]; 4409 4410 rc = _hwrm_send_message(bp, &req, sizeof(req), 4411 HWRM_CMD_TIMEOUT); 4412 } 4413 vnic->uc_filter_count = 0; 4414 } 4415 mutex_unlock(&bp->hwrm_cmd_lock); 4416 4417 return rc; 4418 } 4419 4420 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags) 4421 { 4422 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4423 struct hwrm_vnic_tpa_cfg_input req = {0}; 4424 4425 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) 4426 return 0; 4427 4428 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1); 4429 4430 if (tpa_flags) { 4431 u16 mss = bp->dev->mtu - 40; 4432 u32 nsegs, n, segs = 0, flags; 4433 4434 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA | 4435 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA | 4436 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE | 4437 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN | 4438 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ; 4439 if (tpa_flags & BNXT_FLAG_GRO) 4440 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO; 4441 4442 req.flags = cpu_to_le32(flags); 4443 4444 req.enables = 4445 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS | 4446 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS | 4447 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN); 4448 4449 /* Number of segs are log2 units, and first packet is not 4450 * included as part of this units. 4451 */ 4452 if (mss <= BNXT_RX_PAGE_SIZE) { 4453 n = BNXT_RX_PAGE_SIZE / mss; 4454 nsegs = (MAX_SKB_FRAGS - 1) * n; 4455 } else { 4456 n = mss / BNXT_RX_PAGE_SIZE; 4457 if (mss & (BNXT_RX_PAGE_SIZE - 1)) 4458 n++; 4459 nsegs = (MAX_SKB_FRAGS - n) / n; 4460 } 4461 4462 segs = ilog2(nsegs); 4463 req.max_agg_segs = cpu_to_le16(segs); 4464 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX); 4465 4466 req.min_agg_len = cpu_to_le32(512); 4467 } 4468 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 4469 4470 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4471 } 4472 4473 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring) 4474 { 4475 struct bnxt_ring_grp_info *grp_info; 4476 4477 grp_info = &bp->grp_info[ring->grp_idx]; 4478 return grp_info->cp_fw_ring_id; 4479 } 4480 4481 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr) 4482 { 4483 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4484 struct bnxt_napi *bnapi = rxr->bnapi; 4485 struct bnxt_cp_ring_info *cpr; 4486 4487 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL]; 4488 return cpr->cp_ring_struct.fw_ring_id; 4489 } else { 4490 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct); 4491 } 4492 } 4493 4494 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr) 4495 { 4496 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4497 struct bnxt_napi *bnapi = txr->bnapi; 4498 struct bnxt_cp_ring_info *cpr; 4499 4500 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL]; 4501 return cpr->cp_ring_struct.fw_ring_id; 4502 } else { 4503 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct); 4504 } 4505 } 4506 4507 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss) 4508 { 4509 u32 i, j, max_rings; 4510 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4511 struct hwrm_vnic_rss_cfg_input req = {0}; 4512 4513 if ((bp->flags & BNXT_FLAG_CHIP_P5) || 4514 vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID) 4515 return 0; 4516 4517 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); 4518 if (set_rss) { 4519 req.hash_type = cpu_to_le32(bp->rss_hash_cfg); 4520 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; 4521 if (vnic->flags & BNXT_VNIC_RSS_FLAG) { 4522 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 4523 max_rings = bp->rx_nr_rings - 1; 4524 else 4525 max_rings = bp->rx_nr_rings; 4526 } else { 4527 max_rings = 1; 4528 } 4529 4530 /* Fill the RSS indirection table with ring group ids */ 4531 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) { 4532 if (j == max_rings) 4533 j = 0; 4534 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]); 4535 } 4536 4537 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); 4538 req.hash_key_tbl_addr = 4539 cpu_to_le64(vnic->rss_hash_key_dma_addr); 4540 } 4541 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 4542 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4543 } 4544 4545 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss) 4546 { 4547 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4548 u32 i, j, k, nr_ctxs, max_rings = bp->rx_nr_rings; 4549 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 4550 struct hwrm_vnic_rss_cfg_input req = {0}; 4551 4552 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); 4553 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 4554 if (!set_rss) { 4555 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4556 return 0; 4557 } 4558 req.hash_type = cpu_to_le32(bp->rss_hash_cfg); 4559 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT; 4560 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); 4561 req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr); 4562 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64); 4563 for (i = 0, k = 0; i < nr_ctxs; i++) { 4564 __le16 *ring_tbl = vnic->rss_table; 4565 int rc; 4566 4567 req.ring_table_pair_index = i; 4568 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]); 4569 for (j = 0; j < 64; j++) { 4570 u16 ring_id; 4571 4572 ring_id = rxr->rx_ring_struct.fw_ring_id; 4573 *ring_tbl++ = cpu_to_le16(ring_id); 4574 ring_id = bnxt_cp_ring_for_rx(bp, rxr); 4575 *ring_tbl++ = cpu_to_le16(ring_id); 4576 rxr++; 4577 k++; 4578 if (k == max_rings) { 4579 k = 0; 4580 rxr = &bp->rx_ring[0]; 4581 } 4582 } 4583 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4584 if (rc) 4585 return -EIO; 4586 } 4587 return 0; 4588 } 4589 4590 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id) 4591 { 4592 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4593 struct hwrm_vnic_plcmodes_cfg_input req = {0}; 4594 4595 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1); 4596 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT | 4597 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 | 4598 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6); 4599 req.enables = 4600 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID | 4601 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID); 4602 /* thresholds not implemented in firmware yet */ 4603 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh); 4604 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh); 4605 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); 4606 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4607 } 4608 4609 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id, 4610 u16 ctx_idx) 4611 { 4612 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0}; 4613 4614 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1); 4615 req.rss_cos_lb_ctx_id = 4616 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]); 4617 4618 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4619 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID; 4620 } 4621 4622 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp) 4623 { 4624 int i, j; 4625 4626 for (i = 0; i < bp->nr_vnics; i++) { 4627 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 4628 4629 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) { 4630 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID) 4631 bnxt_hwrm_vnic_ctx_free_one(bp, i, j); 4632 } 4633 } 4634 bp->rsscos_nr_ctxs = 0; 4635 } 4636 4637 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx) 4638 { 4639 int rc; 4640 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0}; 4641 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp = 4642 bp->hwrm_cmd_resp_addr; 4643 4644 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1, 4645 -1); 4646 4647 mutex_lock(&bp->hwrm_cmd_lock); 4648 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4649 if (!rc) 4650 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = 4651 le16_to_cpu(resp->rss_cos_lb_ctx_id); 4652 mutex_unlock(&bp->hwrm_cmd_lock); 4653 4654 return rc; 4655 } 4656 4657 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp) 4658 { 4659 if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP) 4660 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE; 4661 return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE; 4662 } 4663 4664 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id) 4665 { 4666 unsigned int ring = 0, grp_idx; 4667 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4668 struct hwrm_vnic_cfg_input req = {0}; 4669 u16 def_vlan = 0; 4670 4671 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1); 4672 4673 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4674 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 4675 4676 req.default_rx_ring_id = 4677 cpu_to_le16(rxr->rx_ring_struct.fw_ring_id); 4678 req.default_cmpl_ring_id = 4679 cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr)); 4680 req.enables = 4681 cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID | 4682 VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID); 4683 goto vnic_mru; 4684 } 4685 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP); 4686 /* Only RSS support for now TBD: COS & LB */ 4687 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) { 4688 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]); 4689 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 4690 VNIC_CFG_REQ_ENABLES_MRU); 4691 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) { 4692 req.rss_rule = 4693 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]); 4694 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE | 4695 VNIC_CFG_REQ_ENABLES_MRU); 4696 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE); 4697 } else { 4698 req.rss_rule = cpu_to_le16(0xffff); 4699 } 4700 4701 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && 4702 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) { 4703 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]); 4704 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE); 4705 } else { 4706 req.cos_rule = cpu_to_le16(0xffff); 4707 } 4708 4709 if (vnic->flags & BNXT_VNIC_RSS_FLAG) 4710 ring = 0; 4711 else if (vnic->flags & BNXT_VNIC_RFS_FLAG) 4712 ring = vnic_id - 1; 4713 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp)) 4714 ring = bp->rx_nr_rings - 1; 4715 4716 grp_idx = bp->rx_ring[ring].bnapi->index; 4717 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id); 4718 req.lb_rule = cpu_to_le16(0xffff); 4719 vnic_mru: 4720 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + 4721 VLAN_HLEN); 4722 4723 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); 4724 #ifdef CONFIG_BNXT_SRIOV 4725 if (BNXT_VF(bp)) 4726 def_vlan = bp->vf.vlan; 4727 #endif 4728 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan) 4729 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE); 4730 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP)) 4731 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp)); 4732 4733 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4734 } 4735 4736 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id) 4737 { 4738 u32 rc = 0; 4739 4740 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) { 4741 struct hwrm_vnic_free_input req = {0}; 4742 4743 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1); 4744 req.vnic_id = 4745 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id); 4746 4747 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4748 if (rc) 4749 return rc; 4750 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID; 4751 } 4752 return rc; 4753 } 4754 4755 static void bnxt_hwrm_vnic_free(struct bnxt *bp) 4756 { 4757 u16 i; 4758 4759 for (i = 0; i < bp->nr_vnics; i++) 4760 bnxt_hwrm_vnic_free_one(bp, i); 4761 } 4762 4763 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, 4764 unsigned int start_rx_ring_idx, 4765 unsigned int nr_rings) 4766 { 4767 int rc = 0; 4768 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings; 4769 struct hwrm_vnic_alloc_input req = {0}; 4770 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4771 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 4772 4773 if (bp->flags & BNXT_FLAG_CHIP_P5) 4774 goto vnic_no_ring_grps; 4775 4776 /* map ring groups to this vnic */ 4777 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) { 4778 grp_idx = bp->rx_ring[i].bnapi->index; 4779 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) { 4780 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n", 4781 j, nr_rings); 4782 break; 4783 } 4784 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id; 4785 } 4786 4787 vnic_no_ring_grps: 4788 for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++) 4789 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID; 4790 if (vnic_id == 0) 4791 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT); 4792 4793 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1); 4794 4795 mutex_lock(&bp->hwrm_cmd_lock); 4796 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4797 if (!rc) 4798 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id); 4799 mutex_unlock(&bp->hwrm_cmd_lock); 4800 return rc; 4801 } 4802 4803 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp) 4804 { 4805 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 4806 struct hwrm_vnic_qcaps_input req = {0}; 4807 int rc; 4808 4809 if (bp->hwrm_spec_code < 0x10600) 4810 return 0; 4811 4812 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1); 4813 mutex_lock(&bp->hwrm_cmd_lock); 4814 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4815 if (!rc) { 4816 u32 flags = le32_to_cpu(resp->flags); 4817 4818 if (!(bp->flags & BNXT_FLAG_CHIP_P5) && 4819 (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP)) 4820 bp->flags |= BNXT_FLAG_NEW_RSS_CAP; 4821 if (flags & 4822 VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP) 4823 bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP; 4824 } 4825 mutex_unlock(&bp->hwrm_cmd_lock); 4826 return rc; 4827 } 4828 4829 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp) 4830 { 4831 u16 i; 4832 u32 rc = 0; 4833 4834 if (bp->flags & BNXT_FLAG_CHIP_P5) 4835 return 0; 4836 4837 mutex_lock(&bp->hwrm_cmd_lock); 4838 for (i = 0; i < bp->rx_nr_rings; i++) { 4839 struct hwrm_ring_grp_alloc_input req = {0}; 4840 struct hwrm_ring_grp_alloc_output *resp = 4841 bp->hwrm_cmd_resp_addr; 4842 unsigned int grp_idx = bp->rx_ring[i].bnapi->index; 4843 4844 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1); 4845 4846 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id); 4847 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id); 4848 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id); 4849 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx); 4850 4851 rc = _hwrm_send_message(bp, &req, sizeof(req), 4852 HWRM_CMD_TIMEOUT); 4853 if (rc) 4854 break; 4855 4856 bp->grp_info[grp_idx].fw_grp_id = 4857 le32_to_cpu(resp->ring_group_id); 4858 } 4859 mutex_unlock(&bp->hwrm_cmd_lock); 4860 return rc; 4861 } 4862 4863 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp) 4864 { 4865 u16 i; 4866 u32 rc = 0; 4867 struct hwrm_ring_grp_free_input req = {0}; 4868 4869 if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5)) 4870 return 0; 4871 4872 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1); 4873 4874 mutex_lock(&bp->hwrm_cmd_lock); 4875 for (i = 0; i < bp->cp_nr_rings; i++) { 4876 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) 4877 continue; 4878 req.ring_group_id = 4879 cpu_to_le32(bp->grp_info[i].fw_grp_id); 4880 4881 rc = _hwrm_send_message(bp, &req, sizeof(req), 4882 HWRM_CMD_TIMEOUT); 4883 if (rc) 4884 break; 4885 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; 4886 } 4887 mutex_unlock(&bp->hwrm_cmd_lock); 4888 return rc; 4889 } 4890 4891 static int hwrm_ring_alloc_send_msg(struct bnxt *bp, 4892 struct bnxt_ring_struct *ring, 4893 u32 ring_type, u32 map_index) 4894 { 4895 int rc = 0, err = 0; 4896 struct hwrm_ring_alloc_input req = {0}; 4897 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr; 4898 struct bnxt_ring_mem_info *rmem = &ring->ring_mem; 4899 struct bnxt_ring_grp_info *grp_info; 4900 u16 ring_id; 4901 4902 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1); 4903 4904 req.enables = 0; 4905 if (rmem->nr_pages > 1) { 4906 req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map); 4907 /* Page size is in log2 units */ 4908 req.page_size = BNXT_PAGE_SHIFT; 4909 req.page_tbl_depth = 1; 4910 } else { 4911 req.page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]); 4912 } 4913 req.fbo = 0; 4914 /* Association of ring index with doorbell index and MSIX number */ 4915 req.logical_id = cpu_to_le16(map_index); 4916 4917 switch (ring_type) { 4918 case HWRM_RING_ALLOC_TX: { 4919 struct bnxt_tx_ring_info *txr; 4920 4921 txr = container_of(ring, struct bnxt_tx_ring_info, 4922 tx_ring_struct); 4923 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX; 4924 /* Association of transmit ring with completion ring */ 4925 grp_info = &bp->grp_info[ring->grp_idx]; 4926 req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr)); 4927 req.length = cpu_to_le32(bp->tx_ring_mask + 1); 4928 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 4929 req.queue_id = cpu_to_le16(ring->queue_id); 4930 break; 4931 } 4932 case HWRM_RING_ALLOC_RX: 4933 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 4934 req.length = cpu_to_le32(bp->rx_ring_mask + 1); 4935 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4936 u16 flags = 0; 4937 4938 /* Association of rx ring with stats context */ 4939 grp_info = &bp->grp_info[ring->grp_idx]; 4940 req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size); 4941 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 4942 req.enables |= cpu_to_le32( 4943 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); 4944 if (NET_IP_ALIGN == 2) 4945 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD; 4946 req.flags = cpu_to_le16(flags); 4947 } 4948 break; 4949 case HWRM_RING_ALLOC_AGG: 4950 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4951 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG; 4952 /* Association of agg ring with rx ring */ 4953 grp_info = &bp->grp_info[ring->grp_idx]; 4954 req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id); 4955 req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE); 4956 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); 4957 req.enables |= cpu_to_le32( 4958 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID | 4959 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); 4960 } else { 4961 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; 4962 } 4963 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1); 4964 break; 4965 case HWRM_RING_ALLOC_CMPL: 4966 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL; 4967 req.length = cpu_to_le32(bp->cp_ring_mask + 1); 4968 if (bp->flags & BNXT_FLAG_CHIP_P5) { 4969 /* Association of cp ring with nq */ 4970 grp_info = &bp->grp_info[map_index]; 4971 req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id); 4972 req.cq_handle = cpu_to_le64(ring->handle); 4973 req.enables |= cpu_to_le32( 4974 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID); 4975 } else if (bp->flags & BNXT_FLAG_USING_MSIX) { 4976 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; 4977 } 4978 break; 4979 case HWRM_RING_ALLOC_NQ: 4980 req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ; 4981 req.length = cpu_to_le32(bp->cp_ring_mask + 1); 4982 if (bp->flags & BNXT_FLAG_USING_MSIX) 4983 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; 4984 break; 4985 default: 4986 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n", 4987 ring_type); 4988 return -1; 4989 } 4990 4991 mutex_lock(&bp->hwrm_cmd_lock); 4992 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 4993 err = le16_to_cpu(resp->error_code); 4994 ring_id = le16_to_cpu(resp->ring_id); 4995 mutex_unlock(&bp->hwrm_cmd_lock); 4996 4997 if (rc || err) { 4998 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n", 4999 ring_type, rc, err); 5000 return -EIO; 5001 } 5002 ring->fw_ring_id = ring_id; 5003 return rc; 5004 } 5005 5006 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx) 5007 { 5008 int rc; 5009 5010 if (BNXT_PF(bp)) { 5011 struct hwrm_func_cfg_input req = {0}; 5012 5013 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 5014 req.fid = cpu_to_le16(0xffff); 5015 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 5016 req.async_event_cr = cpu_to_le16(idx); 5017 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5018 } else { 5019 struct hwrm_func_vf_cfg_input req = {0}; 5020 5021 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1); 5022 req.enables = 5023 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR); 5024 req.async_event_cr = cpu_to_le16(idx); 5025 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5026 } 5027 return rc; 5028 } 5029 5030 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type, 5031 u32 map_idx, u32 xid) 5032 { 5033 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5034 if (BNXT_PF(bp)) 5035 db->doorbell = bp->bar1 + 0x10000; 5036 else 5037 db->doorbell = bp->bar1 + 0x4000; 5038 switch (ring_type) { 5039 case HWRM_RING_ALLOC_TX: 5040 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ; 5041 break; 5042 case HWRM_RING_ALLOC_RX: 5043 case HWRM_RING_ALLOC_AGG: 5044 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ; 5045 break; 5046 case HWRM_RING_ALLOC_CMPL: 5047 db->db_key64 = DBR_PATH_L2; 5048 break; 5049 case HWRM_RING_ALLOC_NQ: 5050 db->db_key64 = DBR_PATH_L2; 5051 break; 5052 } 5053 db->db_key64 |= (u64)xid << DBR_XID_SFT; 5054 } else { 5055 db->doorbell = bp->bar1 + map_idx * 0x80; 5056 switch (ring_type) { 5057 case HWRM_RING_ALLOC_TX: 5058 db->db_key32 = DB_KEY_TX; 5059 break; 5060 case HWRM_RING_ALLOC_RX: 5061 case HWRM_RING_ALLOC_AGG: 5062 db->db_key32 = DB_KEY_RX; 5063 break; 5064 case HWRM_RING_ALLOC_CMPL: 5065 db->db_key32 = DB_KEY_CP; 5066 break; 5067 } 5068 } 5069 } 5070 5071 static int bnxt_hwrm_ring_alloc(struct bnxt *bp) 5072 { 5073 int i, rc = 0; 5074 u32 type; 5075 5076 if (bp->flags & BNXT_FLAG_CHIP_P5) 5077 type = HWRM_RING_ALLOC_NQ; 5078 else 5079 type = HWRM_RING_ALLOC_CMPL; 5080 for (i = 0; i < bp->cp_nr_rings; i++) { 5081 struct bnxt_napi *bnapi = bp->bnapi[i]; 5082 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5083 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; 5084 u32 map_idx = ring->map_idx; 5085 unsigned int vector; 5086 5087 vector = bp->irq_tbl[map_idx].vector; 5088 disable_irq_nosync(vector); 5089 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5090 if (rc) { 5091 enable_irq(vector); 5092 goto err_out; 5093 } 5094 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id); 5095 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons); 5096 enable_irq(vector); 5097 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id; 5098 5099 if (!i) { 5100 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id); 5101 if (rc) 5102 netdev_warn(bp->dev, "Failed to set async event completion ring.\n"); 5103 } 5104 } 5105 5106 type = HWRM_RING_ALLOC_TX; 5107 for (i = 0; i < bp->tx_nr_rings; i++) { 5108 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 5109 struct bnxt_ring_struct *ring; 5110 u32 map_idx; 5111 5112 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5113 struct bnxt_napi *bnapi = txr->bnapi; 5114 struct bnxt_cp_ring_info *cpr, *cpr2; 5115 u32 type2 = HWRM_RING_ALLOC_CMPL; 5116 5117 cpr = &bnapi->cp_ring; 5118 cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL]; 5119 ring = &cpr2->cp_ring_struct; 5120 ring->handle = BNXT_TX_HDL; 5121 map_idx = bnapi->index; 5122 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); 5123 if (rc) 5124 goto err_out; 5125 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, 5126 ring->fw_ring_id); 5127 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); 5128 } 5129 ring = &txr->tx_ring_struct; 5130 map_idx = i; 5131 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5132 if (rc) 5133 goto err_out; 5134 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id); 5135 } 5136 5137 type = HWRM_RING_ALLOC_RX; 5138 for (i = 0; i < bp->rx_nr_rings; i++) { 5139 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5140 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 5141 struct bnxt_napi *bnapi = rxr->bnapi; 5142 u32 map_idx = bnapi->index; 5143 5144 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5145 if (rc) 5146 goto err_out; 5147 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id); 5148 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod); 5149 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id; 5150 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5151 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5152 u32 type2 = HWRM_RING_ALLOC_CMPL; 5153 struct bnxt_cp_ring_info *cpr2; 5154 5155 cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL]; 5156 ring = &cpr2->cp_ring_struct; 5157 ring->handle = BNXT_RX_HDL; 5158 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); 5159 if (rc) 5160 goto err_out; 5161 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx, 5162 ring->fw_ring_id); 5163 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons); 5164 } 5165 } 5166 5167 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 5168 type = HWRM_RING_ALLOC_AGG; 5169 for (i = 0; i < bp->rx_nr_rings; i++) { 5170 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5171 struct bnxt_ring_struct *ring = 5172 &rxr->rx_agg_ring_struct; 5173 u32 grp_idx = ring->grp_idx; 5174 u32 map_idx = grp_idx + bp->rx_nr_rings; 5175 5176 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx); 5177 if (rc) 5178 goto err_out; 5179 5180 bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx, 5181 ring->fw_ring_id); 5182 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 5183 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id; 5184 } 5185 } 5186 err_out: 5187 return rc; 5188 } 5189 5190 static int hwrm_ring_free_send_msg(struct bnxt *bp, 5191 struct bnxt_ring_struct *ring, 5192 u32 ring_type, int cmpl_ring_id) 5193 { 5194 int rc; 5195 struct hwrm_ring_free_input req = {0}; 5196 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr; 5197 u16 error_code; 5198 5199 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1); 5200 req.ring_type = ring_type; 5201 req.ring_id = cpu_to_le16(ring->fw_ring_id); 5202 5203 mutex_lock(&bp->hwrm_cmd_lock); 5204 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5205 error_code = le16_to_cpu(resp->error_code); 5206 mutex_unlock(&bp->hwrm_cmd_lock); 5207 5208 if (rc || error_code) { 5209 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n", 5210 ring_type, rc, error_code); 5211 return -EIO; 5212 } 5213 return 0; 5214 } 5215 5216 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path) 5217 { 5218 u32 type; 5219 int i; 5220 5221 if (!bp->bnapi) 5222 return; 5223 5224 for (i = 0; i < bp->tx_nr_rings; i++) { 5225 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; 5226 struct bnxt_ring_struct *ring = &txr->tx_ring_struct; 5227 5228 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5229 u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr); 5230 5231 hwrm_ring_free_send_msg(bp, ring, 5232 RING_FREE_REQ_RING_TYPE_TX, 5233 close_path ? cmpl_ring_id : 5234 INVALID_HW_RING_ID); 5235 ring->fw_ring_id = INVALID_HW_RING_ID; 5236 } 5237 } 5238 5239 for (i = 0; i < bp->rx_nr_rings; i++) { 5240 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5241 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; 5242 u32 grp_idx = rxr->bnapi->index; 5243 5244 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5245 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); 5246 5247 hwrm_ring_free_send_msg(bp, ring, 5248 RING_FREE_REQ_RING_TYPE_RX, 5249 close_path ? cmpl_ring_id : 5250 INVALID_HW_RING_ID); 5251 ring->fw_ring_id = INVALID_HW_RING_ID; 5252 bp->grp_info[grp_idx].rx_fw_ring_id = 5253 INVALID_HW_RING_ID; 5254 } 5255 } 5256 5257 if (bp->flags & BNXT_FLAG_CHIP_P5) 5258 type = RING_FREE_REQ_RING_TYPE_RX_AGG; 5259 else 5260 type = RING_FREE_REQ_RING_TYPE_RX; 5261 for (i = 0; i < bp->rx_nr_rings; i++) { 5262 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 5263 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct; 5264 u32 grp_idx = rxr->bnapi->index; 5265 5266 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5267 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr); 5268 5269 hwrm_ring_free_send_msg(bp, ring, type, 5270 close_path ? cmpl_ring_id : 5271 INVALID_HW_RING_ID); 5272 ring->fw_ring_id = INVALID_HW_RING_ID; 5273 bp->grp_info[grp_idx].agg_fw_ring_id = 5274 INVALID_HW_RING_ID; 5275 } 5276 } 5277 5278 /* The completion rings are about to be freed. After that the 5279 * IRQ doorbell will not work anymore. So we need to disable 5280 * IRQ here. 5281 */ 5282 bnxt_disable_int_sync(bp); 5283 5284 if (bp->flags & BNXT_FLAG_CHIP_P5) 5285 type = RING_FREE_REQ_RING_TYPE_NQ; 5286 else 5287 type = RING_FREE_REQ_RING_TYPE_L2_CMPL; 5288 for (i = 0; i < bp->cp_nr_rings; i++) { 5289 struct bnxt_napi *bnapi = bp->bnapi[i]; 5290 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5291 struct bnxt_ring_struct *ring; 5292 int j; 5293 5294 for (j = 0; j < 2; j++) { 5295 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 5296 5297 if (cpr2) { 5298 ring = &cpr2->cp_ring_struct; 5299 if (ring->fw_ring_id == INVALID_HW_RING_ID) 5300 continue; 5301 hwrm_ring_free_send_msg(bp, ring, 5302 RING_FREE_REQ_RING_TYPE_L2_CMPL, 5303 INVALID_HW_RING_ID); 5304 ring->fw_ring_id = INVALID_HW_RING_ID; 5305 } 5306 } 5307 ring = &cpr->cp_ring_struct; 5308 if (ring->fw_ring_id != INVALID_HW_RING_ID) { 5309 hwrm_ring_free_send_msg(bp, ring, type, 5310 INVALID_HW_RING_ID); 5311 ring->fw_ring_id = INVALID_HW_RING_ID; 5312 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; 5313 } 5314 } 5315 } 5316 5317 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 5318 bool shared); 5319 5320 static int bnxt_hwrm_get_rings(struct bnxt *bp) 5321 { 5322 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 5323 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5324 struct hwrm_func_qcfg_input req = {0}; 5325 int rc; 5326 5327 if (bp->hwrm_spec_code < 0x10601) 5328 return 0; 5329 5330 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 5331 req.fid = cpu_to_le16(0xffff); 5332 mutex_lock(&bp->hwrm_cmd_lock); 5333 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5334 if (rc) { 5335 mutex_unlock(&bp->hwrm_cmd_lock); 5336 return -EIO; 5337 } 5338 5339 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings); 5340 if (BNXT_NEW_RM(bp)) { 5341 u16 cp, stats; 5342 5343 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings); 5344 hw_resc->resv_hw_ring_grps = 5345 le32_to_cpu(resp->alloc_hw_ring_grps); 5346 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics); 5347 cp = le16_to_cpu(resp->alloc_cmpl_rings); 5348 stats = le16_to_cpu(resp->alloc_stat_ctx); 5349 hw_resc->resv_irqs = cp; 5350 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5351 int rx = hw_resc->resv_rx_rings; 5352 int tx = hw_resc->resv_tx_rings; 5353 5354 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5355 rx >>= 1; 5356 if (cp < (rx + tx)) { 5357 bnxt_trim_rings(bp, &rx, &tx, cp, false); 5358 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5359 rx <<= 1; 5360 hw_resc->resv_rx_rings = rx; 5361 hw_resc->resv_tx_rings = tx; 5362 } 5363 hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix); 5364 hw_resc->resv_hw_ring_grps = rx; 5365 } 5366 hw_resc->resv_cp_rings = cp; 5367 hw_resc->resv_stat_ctxs = stats; 5368 } 5369 mutex_unlock(&bp->hwrm_cmd_lock); 5370 return 0; 5371 } 5372 5373 /* Caller must hold bp->hwrm_cmd_lock */ 5374 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings) 5375 { 5376 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 5377 struct hwrm_func_qcfg_input req = {0}; 5378 int rc; 5379 5380 if (bp->hwrm_spec_code < 0x10601) 5381 return 0; 5382 5383 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 5384 req.fid = cpu_to_le16(fid); 5385 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5386 if (!rc) 5387 *tx_rings = le16_to_cpu(resp->alloc_tx_rings); 5388 5389 return rc; 5390 } 5391 5392 static bool bnxt_rfs_supported(struct bnxt *bp); 5393 5394 static void 5395 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req, 5396 int tx_rings, int rx_rings, int ring_grps, 5397 int cp_rings, int stats, int vnics) 5398 { 5399 u32 enables = 0; 5400 5401 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1); 5402 req->fid = cpu_to_le16(0xffff); 5403 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; 5404 req->num_tx_rings = cpu_to_le16(tx_rings); 5405 if (BNXT_NEW_RM(bp)) { 5406 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0; 5407 enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; 5408 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5409 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0; 5410 enables |= tx_rings + ring_grps ? 5411 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5412 enables |= rx_rings ? 5413 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 5414 } else { 5415 enables |= cp_rings ? 5416 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5417 enables |= ring_grps ? 5418 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS | 5419 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 5420 } 5421 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0; 5422 5423 req->num_rx_rings = cpu_to_le16(rx_rings); 5424 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5425 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); 5426 req->num_msix = cpu_to_le16(cp_rings); 5427 req->num_rsscos_ctxs = 5428 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); 5429 } else { 5430 req->num_cmpl_rings = cpu_to_le16(cp_rings); 5431 req->num_hw_ring_grps = cpu_to_le16(ring_grps); 5432 req->num_rsscos_ctxs = cpu_to_le16(1); 5433 if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) && 5434 bnxt_rfs_supported(bp)) 5435 req->num_rsscos_ctxs = 5436 cpu_to_le16(ring_grps + 1); 5437 } 5438 req->num_stat_ctxs = cpu_to_le16(stats); 5439 req->num_vnics = cpu_to_le16(vnics); 5440 } 5441 req->enables = cpu_to_le32(enables); 5442 } 5443 5444 static void 5445 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, 5446 struct hwrm_func_vf_cfg_input *req, int tx_rings, 5447 int rx_rings, int ring_grps, int cp_rings, 5448 int stats, int vnics) 5449 { 5450 u32 enables = 0; 5451 5452 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1); 5453 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; 5454 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS | 5455 FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0; 5456 enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; 5457 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5458 enables |= tx_rings + ring_grps ? 5459 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5460 } else { 5461 enables |= cp_rings ? 5462 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0; 5463 enables |= ring_grps ? 5464 FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0; 5465 } 5466 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0; 5467 enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS; 5468 5469 req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX); 5470 req->num_tx_rings = cpu_to_le16(tx_rings); 5471 req->num_rx_rings = cpu_to_le16(rx_rings); 5472 if (bp->flags & BNXT_FLAG_CHIP_P5) { 5473 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps); 5474 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64)); 5475 } else { 5476 req->num_cmpl_rings = cpu_to_le16(cp_rings); 5477 req->num_hw_ring_grps = cpu_to_le16(ring_grps); 5478 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX); 5479 } 5480 req->num_stat_ctxs = cpu_to_le16(stats); 5481 req->num_vnics = cpu_to_le16(vnics); 5482 5483 req->enables = cpu_to_le32(enables); 5484 } 5485 5486 static int 5487 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 5488 int ring_grps, int cp_rings, int stats, int vnics) 5489 { 5490 struct hwrm_func_cfg_input req = {0}; 5491 int rc; 5492 5493 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 5494 cp_rings, stats, vnics); 5495 if (!req.enables) 5496 return 0; 5497 5498 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5499 if (rc) 5500 return -ENOMEM; 5501 5502 if (bp->hwrm_spec_code < 0x10601) 5503 bp->hw_resc.resv_tx_rings = tx_rings; 5504 5505 rc = bnxt_hwrm_get_rings(bp); 5506 return rc; 5507 } 5508 5509 static int 5510 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 5511 int ring_grps, int cp_rings, int stats, int vnics) 5512 { 5513 struct hwrm_func_vf_cfg_input req = {0}; 5514 int rc; 5515 5516 if (!BNXT_NEW_RM(bp)) { 5517 bp->hw_resc.resv_tx_rings = tx_rings; 5518 return 0; 5519 } 5520 5521 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 5522 cp_rings, stats, vnics); 5523 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5524 if (rc) 5525 return -ENOMEM; 5526 5527 rc = bnxt_hwrm_get_rings(bp); 5528 return rc; 5529 } 5530 5531 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp, 5532 int cp, int stat, int vnic) 5533 { 5534 if (BNXT_PF(bp)) 5535 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat, 5536 vnic); 5537 else 5538 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat, 5539 vnic); 5540 } 5541 5542 int bnxt_nq_rings_in_use(struct bnxt *bp) 5543 { 5544 int cp = bp->cp_nr_rings; 5545 int ulp_msix, ulp_base; 5546 5547 ulp_msix = bnxt_get_ulp_msix_num(bp); 5548 if (ulp_msix) { 5549 ulp_base = bnxt_get_ulp_msix_base(bp); 5550 cp += ulp_msix; 5551 if ((ulp_base + ulp_msix) > cp) 5552 cp = ulp_base + ulp_msix; 5553 } 5554 return cp; 5555 } 5556 5557 static int bnxt_cp_rings_in_use(struct bnxt *bp) 5558 { 5559 int cp; 5560 5561 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 5562 return bnxt_nq_rings_in_use(bp); 5563 5564 cp = bp->tx_nr_rings + bp->rx_nr_rings; 5565 return cp; 5566 } 5567 5568 static int bnxt_get_func_stat_ctxs(struct bnxt *bp) 5569 { 5570 return bp->cp_nr_rings + bnxt_get_ulp_stat_ctxs(bp); 5571 } 5572 5573 static bool bnxt_need_reserve_rings(struct bnxt *bp) 5574 { 5575 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5576 int cp = bnxt_cp_rings_in_use(bp); 5577 int nq = bnxt_nq_rings_in_use(bp); 5578 int rx = bp->rx_nr_rings, stat; 5579 int vnic = 1, grp = rx; 5580 5581 if (bp->hwrm_spec_code < 0x10601) 5582 return false; 5583 5584 if (hw_resc->resv_tx_rings != bp->tx_nr_rings) 5585 return true; 5586 5587 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) 5588 vnic = rx + 1; 5589 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5590 rx <<= 1; 5591 stat = bnxt_get_func_stat_ctxs(bp); 5592 if (BNXT_NEW_RM(bp) && 5593 (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp || 5594 hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat || 5595 (hw_resc->resv_hw_ring_grps != grp && 5596 !(bp->flags & BNXT_FLAG_CHIP_P5)))) 5597 return true; 5598 if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) && 5599 hw_resc->resv_irqs != nq) 5600 return true; 5601 return false; 5602 } 5603 5604 static int __bnxt_reserve_rings(struct bnxt *bp) 5605 { 5606 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 5607 int cp = bnxt_nq_rings_in_use(bp); 5608 int tx = bp->tx_nr_rings; 5609 int rx = bp->rx_nr_rings; 5610 int grp, rx_rings, rc; 5611 int vnic = 1, stat; 5612 bool sh = false; 5613 5614 if (!bnxt_need_reserve_rings(bp)) 5615 return 0; 5616 5617 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 5618 sh = true; 5619 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5)) 5620 vnic = rx + 1; 5621 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5622 rx <<= 1; 5623 grp = bp->rx_nr_rings; 5624 stat = bnxt_get_func_stat_ctxs(bp); 5625 5626 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic); 5627 if (rc) 5628 return rc; 5629 5630 tx = hw_resc->resv_tx_rings; 5631 if (BNXT_NEW_RM(bp)) { 5632 rx = hw_resc->resv_rx_rings; 5633 cp = hw_resc->resv_irqs; 5634 grp = hw_resc->resv_hw_ring_grps; 5635 vnic = hw_resc->resv_vnics; 5636 stat = hw_resc->resv_stat_ctxs; 5637 } 5638 5639 rx_rings = rx; 5640 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 5641 if (rx >= 2) { 5642 rx_rings = rx >> 1; 5643 } else { 5644 if (netif_running(bp->dev)) 5645 return -ENOMEM; 5646 5647 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 5648 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 5649 bp->dev->hw_features &= ~NETIF_F_LRO; 5650 bp->dev->features &= ~NETIF_F_LRO; 5651 bnxt_set_ring_params(bp); 5652 } 5653 } 5654 rx_rings = min_t(int, rx_rings, grp); 5655 cp = min_t(int, cp, bp->cp_nr_rings); 5656 if (stat > bnxt_get_ulp_stat_ctxs(bp)) 5657 stat -= bnxt_get_ulp_stat_ctxs(bp); 5658 cp = min_t(int, cp, stat); 5659 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh); 5660 if (bp->flags & BNXT_FLAG_AGG_RINGS) 5661 rx = rx_rings << 1; 5662 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings; 5663 bp->tx_nr_rings = tx; 5664 bp->rx_nr_rings = rx_rings; 5665 bp->cp_nr_rings = cp; 5666 5667 if (!tx || !rx || !cp || !grp || !vnic || !stat) 5668 return -ENOMEM; 5669 5670 return rc; 5671 } 5672 5673 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 5674 int ring_grps, int cp_rings, int stats, 5675 int vnics) 5676 { 5677 struct hwrm_func_vf_cfg_input req = {0}; 5678 u32 flags; 5679 int rc; 5680 5681 if (!BNXT_NEW_RM(bp)) 5682 return 0; 5683 5684 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 5685 cp_rings, stats, vnics); 5686 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST | 5687 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST | 5688 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | 5689 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | 5690 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST | 5691 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST; 5692 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 5693 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; 5694 5695 req.flags = cpu_to_le32(flags); 5696 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5697 if (rc) 5698 return -ENOMEM; 5699 return 0; 5700 } 5701 5702 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings, 5703 int ring_grps, int cp_rings, int stats, 5704 int vnics) 5705 { 5706 struct hwrm_func_cfg_input req = {0}; 5707 u32 flags; 5708 int rc; 5709 5710 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 5711 cp_rings, stats, vnics); 5712 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST; 5713 if (BNXT_NEW_RM(bp)) { 5714 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST | 5715 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | 5716 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST | 5717 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST; 5718 if (bp->flags & BNXT_FLAG_CHIP_P5) 5719 flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST | 5720 FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST; 5721 else 5722 flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST; 5723 } 5724 5725 req.flags = cpu_to_le32(flags); 5726 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5727 if (rc) 5728 return -ENOMEM; 5729 return 0; 5730 } 5731 5732 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings, 5733 int ring_grps, int cp_rings, int stats, 5734 int vnics) 5735 { 5736 if (bp->hwrm_spec_code < 0x10801) 5737 return 0; 5738 5739 if (BNXT_PF(bp)) 5740 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings, 5741 ring_grps, cp_rings, stats, 5742 vnics); 5743 5744 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps, 5745 cp_rings, stats, vnics); 5746 } 5747 5748 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp) 5749 { 5750 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 5751 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 5752 struct hwrm_ring_aggint_qcaps_input req = {0}; 5753 int rc; 5754 5755 coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS; 5756 coal_cap->num_cmpl_dma_aggr_max = 63; 5757 coal_cap->num_cmpl_dma_aggr_during_int_max = 63; 5758 coal_cap->cmpl_aggr_dma_tmr_max = 65535; 5759 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535; 5760 coal_cap->int_lat_tmr_min_max = 65535; 5761 coal_cap->int_lat_tmr_max_max = 65535; 5762 coal_cap->num_cmpl_aggr_int_max = 65535; 5763 coal_cap->timer_units = 80; 5764 5765 if (bp->hwrm_spec_code < 0x10902) 5766 return; 5767 5768 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1); 5769 mutex_lock(&bp->hwrm_cmd_lock); 5770 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5771 if (!rc) { 5772 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params); 5773 coal_cap->nq_params = le32_to_cpu(resp->nq_params); 5774 coal_cap->num_cmpl_dma_aggr_max = 5775 le16_to_cpu(resp->num_cmpl_dma_aggr_max); 5776 coal_cap->num_cmpl_dma_aggr_during_int_max = 5777 le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max); 5778 coal_cap->cmpl_aggr_dma_tmr_max = 5779 le16_to_cpu(resp->cmpl_aggr_dma_tmr_max); 5780 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 5781 le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max); 5782 coal_cap->int_lat_tmr_min_max = 5783 le16_to_cpu(resp->int_lat_tmr_min_max); 5784 coal_cap->int_lat_tmr_max_max = 5785 le16_to_cpu(resp->int_lat_tmr_max_max); 5786 coal_cap->num_cmpl_aggr_int_max = 5787 le16_to_cpu(resp->num_cmpl_aggr_int_max); 5788 coal_cap->timer_units = le16_to_cpu(resp->timer_units); 5789 } 5790 mutex_unlock(&bp->hwrm_cmd_lock); 5791 } 5792 5793 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec) 5794 { 5795 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 5796 5797 return usec * 1000 / coal_cap->timer_units; 5798 } 5799 5800 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, 5801 struct bnxt_coal *hw_coal, 5802 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req) 5803 { 5804 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 5805 u32 cmpl_params = coal_cap->cmpl_params; 5806 u16 val, tmr, max, flags = 0; 5807 5808 max = hw_coal->bufs_per_record * 128; 5809 if (hw_coal->budget) 5810 max = hw_coal->bufs_per_record * hw_coal->budget; 5811 max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max); 5812 5813 val = clamp_t(u16, hw_coal->coal_bufs, 1, max); 5814 req->num_cmpl_aggr_int = cpu_to_le16(val); 5815 5816 val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max); 5817 req->num_cmpl_dma_aggr = cpu_to_le16(val); 5818 5819 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, 5820 coal_cap->num_cmpl_dma_aggr_during_int_max); 5821 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val); 5822 5823 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks); 5824 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max); 5825 req->int_lat_tmr_max = cpu_to_le16(tmr); 5826 5827 /* min timer set to 1/2 of interrupt timer */ 5828 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) { 5829 val = tmr / 2; 5830 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max); 5831 req->int_lat_tmr_min = cpu_to_le16(val); 5832 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); 5833 } 5834 5835 /* buf timer set to 1/4 of interrupt timer */ 5836 val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max); 5837 req->cmpl_aggr_dma_tmr = cpu_to_le16(val); 5838 5839 if (cmpl_params & 5840 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) { 5841 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq); 5842 val = clamp_t(u16, tmr, 1, 5843 coal_cap->cmpl_aggr_dma_tmr_during_int_max); 5844 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr); 5845 req->enables |= 5846 cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE); 5847 } 5848 5849 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET) 5850 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 5851 if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) && 5852 hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh) 5853 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE; 5854 req->flags = cpu_to_le16(flags); 5855 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES); 5856 } 5857 5858 /* Caller holds bp->hwrm_cmd_lock */ 5859 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi, 5860 struct bnxt_coal *hw_coal) 5861 { 5862 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0}; 5863 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5864 struct bnxt_coal_cap *coal_cap = &bp->coal_cap; 5865 u32 nq_params = coal_cap->nq_params; 5866 u16 tmr; 5867 5868 if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN)) 5869 return 0; 5870 5871 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, 5872 -1, -1); 5873 req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id); 5874 req.flags = 5875 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ); 5876 5877 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2; 5878 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max); 5879 req.int_lat_tmr_min = cpu_to_le16(tmr); 5880 req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE); 5881 return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5882 } 5883 5884 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi) 5885 { 5886 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}; 5887 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5888 struct bnxt_coal coal; 5889 5890 /* Tick values in micro seconds. 5891 * 1 coal_buf x bufs_per_record = 1 completion record. 5892 */ 5893 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal)); 5894 5895 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks; 5896 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs; 5897 5898 if (!bnapi->rx_ring) 5899 return -ENODEV; 5900 5901 bnxt_hwrm_cmd_hdr_init(bp, &req_rx, 5902 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 5903 5904 bnxt_hwrm_set_coal_params(bp, &coal, &req_rx); 5905 5906 req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring)); 5907 5908 return hwrm_send_message(bp, &req_rx, sizeof(req_rx), 5909 HWRM_CMD_TIMEOUT); 5910 } 5911 5912 int bnxt_hwrm_set_coal(struct bnxt *bp) 5913 { 5914 int i, rc = 0; 5915 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0}, 5916 req_tx = {0}, *req; 5917 5918 bnxt_hwrm_cmd_hdr_init(bp, &req_rx, 5919 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 5920 bnxt_hwrm_cmd_hdr_init(bp, &req_tx, 5921 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1); 5922 5923 bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx); 5924 bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx); 5925 5926 mutex_lock(&bp->hwrm_cmd_lock); 5927 for (i = 0; i < bp->cp_nr_rings; i++) { 5928 struct bnxt_napi *bnapi = bp->bnapi[i]; 5929 struct bnxt_coal *hw_coal; 5930 u16 ring_id; 5931 5932 req = &req_rx; 5933 if (!bnapi->rx_ring) { 5934 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); 5935 req = &req_tx; 5936 } else { 5937 ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring); 5938 } 5939 req->ring_id = cpu_to_le16(ring_id); 5940 5941 rc = _hwrm_send_message(bp, req, sizeof(*req), 5942 HWRM_CMD_TIMEOUT); 5943 if (rc) 5944 break; 5945 5946 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 5947 continue; 5948 5949 if (bnapi->rx_ring && bnapi->tx_ring) { 5950 req = &req_tx; 5951 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring); 5952 req->ring_id = cpu_to_le16(ring_id); 5953 rc = _hwrm_send_message(bp, req, sizeof(*req), 5954 HWRM_CMD_TIMEOUT); 5955 if (rc) 5956 break; 5957 } 5958 if (bnapi->rx_ring) 5959 hw_coal = &bp->rx_coal; 5960 else 5961 hw_coal = &bp->tx_coal; 5962 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal); 5963 } 5964 mutex_unlock(&bp->hwrm_cmd_lock); 5965 return rc; 5966 } 5967 5968 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp) 5969 { 5970 int rc = 0, i; 5971 struct hwrm_stat_ctx_free_input req = {0}; 5972 5973 if (!bp->bnapi) 5974 return 0; 5975 5976 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 5977 return 0; 5978 5979 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1); 5980 5981 mutex_lock(&bp->hwrm_cmd_lock); 5982 for (i = 0; i < bp->cp_nr_rings; i++) { 5983 struct bnxt_napi *bnapi = bp->bnapi[i]; 5984 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 5985 5986 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) { 5987 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id); 5988 5989 rc = _hwrm_send_message(bp, &req, sizeof(req), 5990 HWRM_CMD_TIMEOUT); 5991 if (rc) 5992 break; 5993 5994 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; 5995 } 5996 } 5997 mutex_unlock(&bp->hwrm_cmd_lock); 5998 return rc; 5999 } 6000 6001 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp) 6002 { 6003 int rc = 0, i; 6004 struct hwrm_stat_ctx_alloc_input req = {0}; 6005 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr; 6006 6007 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 6008 return 0; 6009 6010 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1); 6011 6012 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000); 6013 6014 mutex_lock(&bp->hwrm_cmd_lock); 6015 for (i = 0; i < bp->cp_nr_rings; i++) { 6016 struct bnxt_napi *bnapi = bp->bnapi[i]; 6017 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 6018 6019 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map); 6020 6021 rc = _hwrm_send_message(bp, &req, sizeof(req), 6022 HWRM_CMD_TIMEOUT); 6023 if (rc) 6024 break; 6025 6026 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id); 6027 6028 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id; 6029 } 6030 mutex_unlock(&bp->hwrm_cmd_lock); 6031 return rc; 6032 } 6033 6034 static int bnxt_hwrm_func_qcfg(struct bnxt *bp) 6035 { 6036 struct hwrm_func_qcfg_input req = {0}; 6037 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 6038 u16 flags; 6039 int rc; 6040 6041 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1); 6042 req.fid = cpu_to_le16(0xffff); 6043 mutex_lock(&bp->hwrm_cmd_lock); 6044 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6045 if (rc) 6046 goto func_qcfg_exit; 6047 6048 #ifdef CONFIG_BNXT_SRIOV 6049 if (BNXT_VF(bp)) { 6050 struct bnxt_vf_info *vf = &bp->vf; 6051 6052 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK; 6053 } 6054 #endif 6055 flags = le16_to_cpu(resp->flags); 6056 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED | 6057 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) { 6058 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT; 6059 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED) 6060 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT; 6061 } 6062 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST)) 6063 bp->flags |= BNXT_FLAG_MULTI_HOST; 6064 6065 switch (resp->port_partition_type) { 6066 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0: 6067 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5: 6068 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0: 6069 bp->port_partition_type = resp->port_partition_type; 6070 break; 6071 } 6072 if (bp->hwrm_spec_code < 0x10707 || 6073 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB) 6074 bp->br_mode = BRIDGE_MODE_VEB; 6075 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA) 6076 bp->br_mode = BRIDGE_MODE_VEPA; 6077 else 6078 bp->br_mode = BRIDGE_MODE_UNDEF; 6079 6080 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured); 6081 if (!bp->max_mtu) 6082 bp->max_mtu = BNXT_MAX_MTU; 6083 6084 func_qcfg_exit: 6085 mutex_unlock(&bp->hwrm_cmd_lock); 6086 return rc; 6087 } 6088 6089 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp) 6090 { 6091 struct hwrm_func_backing_store_qcaps_input req = {0}; 6092 struct hwrm_func_backing_store_qcaps_output *resp = 6093 bp->hwrm_cmd_resp_addr; 6094 int rc; 6095 6096 if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx) 6097 return 0; 6098 6099 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1); 6100 mutex_lock(&bp->hwrm_cmd_lock); 6101 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6102 if (!rc) { 6103 struct bnxt_ctx_pg_info *ctx_pg; 6104 struct bnxt_ctx_mem_info *ctx; 6105 int i; 6106 6107 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 6108 if (!ctx) { 6109 rc = -ENOMEM; 6110 goto ctx_err; 6111 } 6112 ctx_pg = kzalloc(sizeof(*ctx_pg) * (bp->max_q + 1), GFP_KERNEL); 6113 if (!ctx_pg) { 6114 kfree(ctx); 6115 rc = -ENOMEM; 6116 goto ctx_err; 6117 } 6118 for (i = 0; i < bp->max_q + 1; i++, ctx_pg++) 6119 ctx->tqm_mem[i] = ctx_pg; 6120 6121 bp->ctx = ctx; 6122 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries); 6123 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries); 6124 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries); 6125 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size); 6126 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries); 6127 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries); 6128 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size); 6129 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries); 6130 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries); 6131 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size); 6132 ctx->vnic_max_vnic_entries = 6133 le16_to_cpu(resp->vnic_max_vnic_entries); 6134 ctx->vnic_max_ring_table_entries = 6135 le16_to_cpu(resp->vnic_max_ring_table_entries); 6136 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size); 6137 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries); 6138 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size); 6139 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size); 6140 ctx->tqm_min_entries_per_ring = 6141 le32_to_cpu(resp->tqm_min_entries_per_ring); 6142 ctx->tqm_max_entries_per_ring = 6143 le32_to_cpu(resp->tqm_max_entries_per_ring); 6144 ctx->tqm_entries_multiple = resp->tqm_entries_multiple; 6145 if (!ctx->tqm_entries_multiple) 6146 ctx->tqm_entries_multiple = 1; 6147 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries); 6148 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size); 6149 ctx->mrav_num_entries_units = 6150 le16_to_cpu(resp->mrav_num_entries_units); 6151 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size); 6152 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries); 6153 } else { 6154 rc = 0; 6155 } 6156 ctx_err: 6157 mutex_unlock(&bp->hwrm_cmd_lock); 6158 return rc; 6159 } 6160 6161 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr, 6162 __le64 *pg_dir) 6163 { 6164 u8 pg_size = 0; 6165 6166 if (BNXT_PAGE_SHIFT == 13) 6167 pg_size = 1 << 4; 6168 else if (BNXT_PAGE_SIZE == 16) 6169 pg_size = 2 << 4; 6170 6171 *pg_attr = pg_size; 6172 if (rmem->depth >= 1) { 6173 if (rmem->depth == 2) 6174 *pg_attr |= 2; 6175 else 6176 *pg_attr |= 1; 6177 *pg_dir = cpu_to_le64(rmem->pg_tbl_map); 6178 } else { 6179 *pg_dir = cpu_to_le64(rmem->dma_arr[0]); 6180 } 6181 } 6182 6183 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \ 6184 (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \ 6185 FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \ 6186 FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \ 6187 FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \ 6188 FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) 6189 6190 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables) 6191 { 6192 struct hwrm_func_backing_store_cfg_input req = {0}; 6193 struct bnxt_ctx_mem_info *ctx = bp->ctx; 6194 struct bnxt_ctx_pg_info *ctx_pg; 6195 __le32 *num_entries; 6196 __le64 *pg_dir; 6197 u32 flags = 0; 6198 u8 *pg_attr; 6199 int i, rc; 6200 u32 ena; 6201 6202 if (!ctx) 6203 return 0; 6204 6205 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1); 6206 req.enables = cpu_to_le32(enables); 6207 6208 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) { 6209 ctx_pg = &ctx->qp_mem; 6210 req.qp_num_entries = cpu_to_le32(ctx_pg->entries); 6211 req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries); 6212 req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries); 6213 req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size); 6214 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6215 &req.qpc_pg_size_qpc_lvl, 6216 &req.qpc_page_dir); 6217 } 6218 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) { 6219 ctx_pg = &ctx->srq_mem; 6220 req.srq_num_entries = cpu_to_le32(ctx_pg->entries); 6221 req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries); 6222 req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size); 6223 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6224 &req.srq_pg_size_srq_lvl, 6225 &req.srq_page_dir); 6226 } 6227 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) { 6228 ctx_pg = &ctx->cq_mem; 6229 req.cq_num_entries = cpu_to_le32(ctx_pg->entries); 6230 req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries); 6231 req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size); 6232 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl, 6233 &req.cq_page_dir); 6234 } 6235 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) { 6236 ctx_pg = &ctx->vnic_mem; 6237 req.vnic_num_vnic_entries = 6238 cpu_to_le16(ctx->vnic_max_vnic_entries); 6239 req.vnic_num_ring_table_entries = 6240 cpu_to_le16(ctx->vnic_max_ring_table_entries); 6241 req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size); 6242 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6243 &req.vnic_pg_size_vnic_lvl, 6244 &req.vnic_page_dir); 6245 } 6246 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) { 6247 ctx_pg = &ctx->stat_mem; 6248 req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries); 6249 req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size); 6250 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6251 &req.stat_pg_size_stat_lvl, 6252 &req.stat_page_dir); 6253 } 6254 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) { 6255 ctx_pg = &ctx->mrav_mem; 6256 req.mrav_num_entries = cpu_to_le32(ctx_pg->entries); 6257 if (ctx->mrav_num_entries_units) 6258 flags |= 6259 FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT; 6260 req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size); 6261 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6262 &req.mrav_pg_size_mrav_lvl, 6263 &req.mrav_page_dir); 6264 } 6265 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) { 6266 ctx_pg = &ctx->tim_mem; 6267 req.tim_num_entries = cpu_to_le32(ctx_pg->entries); 6268 req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size); 6269 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, 6270 &req.tim_pg_size_tim_lvl, 6271 &req.tim_page_dir); 6272 } 6273 for (i = 0, num_entries = &req.tqm_sp_num_entries, 6274 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl, 6275 pg_dir = &req.tqm_sp_page_dir, 6276 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP; 6277 i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) { 6278 if (!(enables & ena)) 6279 continue; 6280 6281 req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size); 6282 ctx_pg = ctx->tqm_mem[i]; 6283 *num_entries = cpu_to_le32(ctx_pg->entries); 6284 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir); 6285 } 6286 req.flags = cpu_to_le32(flags); 6287 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6288 if (rc) 6289 rc = -EIO; 6290 return rc; 6291 } 6292 6293 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, 6294 struct bnxt_ctx_pg_info *ctx_pg) 6295 { 6296 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 6297 6298 rmem->page_size = BNXT_PAGE_SIZE; 6299 rmem->pg_arr = ctx_pg->ctx_pg_arr; 6300 rmem->dma_arr = ctx_pg->ctx_dma_arr; 6301 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 6302 if (rmem->depth >= 1) 6303 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG; 6304 return bnxt_alloc_ring(bp, rmem); 6305 } 6306 6307 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp, 6308 struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size, 6309 u8 depth) 6310 { 6311 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 6312 int rc; 6313 6314 if (!mem_size) 6315 return 0; 6316 6317 ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); 6318 if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) { 6319 ctx_pg->nr_pages = 0; 6320 return -EINVAL; 6321 } 6322 if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) { 6323 int nr_tbls, i; 6324 6325 rmem->depth = 2; 6326 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg), 6327 GFP_KERNEL); 6328 if (!ctx_pg->ctx_pg_tbl) 6329 return -ENOMEM; 6330 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES); 6331 rmem->nr_pages = nr_tbls; 6332 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); 6333 if (rc) 6334 return rc; 6335 for (i = 0; i < nr_tbls; i++) { 6336 struct bnxt_ctx_pg_info *pg_tbl; 6337 6338 pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL); 6339 if (!pg_tbl) 6340 return -ENOMEM; 6341 ctx_pg->ctx_pg_tbl[i] = pg_tbl; 6342 rmem = &pg_tbl->ring_mem; 6343 rmem->pg_tbl = ctx_pg->ctx_pg_arr[i]; 6344 rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i]; 6345 rmem->depth = 1; 6346 rmem->nr_pages = MAX_CTX_PAGES; 6347 if (i == (nr_tbls - 1)) { 6348 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES; 6349 6350 if (rem) 6351 rmem->nr_pages = rem; 6352 } 6353 rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl); 6354 if (rc) 6355 break; 6356 } 6357 } else { 6358 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); 6359 if (rmem->nr_pages > 1 || depth) 6360 rmem->depth = 1; 6361 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg); 6362 } 6363 return rc; 6364 } 6365 6366 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp, 6367 struct bnxt_ctx_pg_info *ctx_pg) 6368 { 6369 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 6370 6371 if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES || 6372 ctx_pg->ctx_pg_tbl) { 6373 int i, nr_tbls = rmem->nr_pages; 6374 6375 for (i = 0; i < nr_tbls; i++) { 6376 struct bnxt_ctx_pg_info *pg_tbl; 6377 struct bnxt_ring_mem_info *rmem2; 6378 6379 pg_tbl = ctx_pg->ctx_pg_tbl[i]; 6380 if (!pg_tbl) 6381 continue; 6382 rmem2 = &pg_tbl->ring_mem; 6383 bnxt_free_ring(bp, rmem2); 6384 ctx_pg->ctx_pg_arr[i] = NULL; 6385 kfree(pg_tbl); 6386 ctx_pg->ctx_pg_tbl[i] = NULL; 6387 } 6388 kfree(ctx_pg->ctx_pg_tbl); 6389 ctx_pg->ctx_pg_tbl = NULL; 6390 } 6391 bnxt_free_ring(bp, rmem); 6392 ctx_pg->nr_pages = 0; 6393 } 6394 6395 static void bnxt_free_ctx_mem(struct bnxt *bp) 6396 { 6397 struct bnxt_ctx_mem_info *ctx = bp->ctx; 6398 int i; 6399 6400 if (!ctx) 6401 return; 6402 6403 if (ctx->tqm_mem[0]) { 6404 for (i = 0; i < bp->max_q + 1; i++) 6405 bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]); 6406 kfree(ctx->tqm_mem[0]); 6407 ctx->tqm_mem[0] = NULL; 6408 } 6409 6410 bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem); 6411 bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem); 6412 bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem); 6413 bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem); 6414 bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem); 6415 bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem); 6416 bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem); 6417 ctx->flags &= ~BNXT_CTX_FLAG_INITED; 6418 } 6419 6420 static int bnxt_alloc_ctx_mem(struct bnxt *bp) 6421 { 6422 struct bnxt_ctx_pg_info *ctx_pg; 6423 struct bnxt_ctx_mem_info *ctx; 6424 u32 mem_size, ena, entries; 6425 u32 num_mr, num_ah; 6426 u32 extra_srqs = 0; 6427 u32 extra_qps = 0; 6428 u8 pg_lvl = 1; 6429 int i, rc; 6430 6431 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 6432 if (rc) { 6433 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n", 6434 rc); 6435 return rc; 6436 } 6437 ctx = bp->ctx; 6438 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 6439 return 0; 6440 6441 if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) { 6442 pg_lvl = 2; 6443 extra_qps = 65536; 6444 extra_srqs = 8192; 6445 } 6446 6447 ctx_pg = &ctx->qp_mem; 6448 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries + 6449 extra_qps; 6450 mem_size = ctx->qp_entry_size * ctx_pg->entries; 6451 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl); 6452 if (rc) 6453 return rc; 6454 6455 ctx_pg = &ctx->srq_mem; 6456 ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs; 6457 mem_size = ctx->srq_entry_size * ctx_pg->entries; 6458 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl); 6459 if (rc) 6460 return rc; 6461 6462 ctx_pg = &ctx->cq_mem; 6463 ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2; 6464 mem_size = ctx->cq_entry_size * ctx_pg->entries; 6465 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl); 6466 if (rc) 6467 return rc; 6468 6469 ctx_pg = &ctx->vnic_mem; 6470 ctx_pg->entries = ctx->vnic_max_vnic_entries + 6471 ctx->vnic_max_ring_table_entries; 6472 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 6473 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1); 6474 if (rc) 6475 return rc; 6476 6477 ctx_pg = &ctx->stat_mem; 6478 ctx_pg->entries = ctx->stat_max_entries; 6479 mem_size = ctx->stat_entry_size * ctx_pg->entries; 6480 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1); 6481 if (rc) 6482 return rc; 6483 6484 ena = 0; 6485 if (!(bp->flags & BNXT_FLAG_ROCE_CAP)) 6486 goto skip_rdma; 6487 6488 ctx_pg = &ctx->mrav_mem; 6489 /* 128K extra is needed to accommodate static AH context 6490 * allocation by f/w. 6491 */ 6492 num_mr = 1024 * 256; 6493 num_ah = 1024 * 128; 6494 ctx_pg->entries = num_mr + num_ah; 6495 mem_size = ctx->mrav_entry_size * ctx_pg->entries; 6496 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2); 6497 if (rc) 6498 return rc; 6499 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV; 6500 if (ctx->mrav_num_entries_units) 6501 ctx_pg->entries = 6502 ((num_mr / ctx->mrav_num_entries_units) << 16) | 6503 (num_ah / ctx->mrav_num_entries_units); 6504 6505 ctx_pg = &ctx->tim_mem; 6506 ctx_pg->entries = ctx->qp_mem.entries; 6507 mem_size = ctx->tim_entry_size * ctx_pg->entries; 6508 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1); 6509 if (rc) 6510 return rc; 6511 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM; 6512 6513 skip_rdma: 6514 entries = ctx->qp_max_l2_entries + extra_qps; 6515 entries = roundup(entries, ctx->tqm_entries_multiple); 6516 entries = clamp_t(u32, entries, ctx->tqm_min_entries_per_ring, 6517 ctx->tqm_max_entries_per_ring); 6518 for (i = 0; i < bp->max_q + 1; i++) { 6519 ctx_pg = ctx->tqm_mem[i]; 6520 ctx_pg->entries = entries; 6521 mem_size = ctx->tqm_entry_size * entries; 6522 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1); 6523 if (rc) 6524 return rc; 6525 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i; 6526 } 6527 ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES; 6528 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 6529 if (rc) 6530 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n", 6531 rc); 6532 else 6533 ctx->flags |= BNXT_CTX_FLAG_INITED; 6534 6535 return 0; 6536 } 6537 6538 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all) 6539 { 6540 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 6541 struct hwrm_func_resource_qcaps_input req = {0}; 6542 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 6543 int rc; 6544 6545 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1); 6546 req.fid = cpu_to_le16(0xffff); 6547 6548 mutex_lock(&bp->hwrm_cmd_lock); 6549 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), 6550 HWRM_CMD_TIMEOUT); 6551 if (rc) { 6552 rc = -EIO; 6553 goto hwrm_func_resc_qcaps_exit; 6554 } 6555 6556 hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs); 6557 if (!all) 6558 goto hwrm_func_resc_qcaps_exit; 6559 6560 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx); 6561 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 6562 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings); 6563 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 6564 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings); 6565 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 6566 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings); 6567 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 6568 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps); 6569 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps); 6570 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs); 6571 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 6572 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics); 6573 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); 6574 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx); 6575 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 6576 6577 if (bp->flags & BNXT_FLAG_CHIP_P5) { 6578 u16 max_msix = le16_to_cpu(resp->max_msix); 6579 6580 hw_resc->max_nqs = max_msix; 6581 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings; 6582 } 6583 6584 if (BNXT_PF(bp)) { 6585 struct bnxt_pf_info *pf = &bp->pf; 6586 6587 pf->vf_resv_strategy = 6588 le16_to_cpu(resp->vf_reservation_strategy); 6589 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC) 6590 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL; 6591 } 6592 hwrm_func_resc_qcaps_exit: 6593 mutex_unlock(&bp->hwrm_cmd_lock); 6594 return rc; 6595 } 6596 6597 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) 6598 { 6599 int rc = 0; 6600 struct hwrm_func_qcaps_input req = {0}; 6601 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 6602 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 6603 u32 flags; 6604 6605 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1); 6606 req.fid = cpu_to_le16(0xffff); 6607 6608 mutex_lock(&bp->hwrm_cmd_lock); 6609 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6610 if (rc) 6611 goto hwrm_func_qcaps_exit; 6612 6613 flags = le32_to_cpu(resp->flags); 6614 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED) 6615 bp->flags |= BNXT_FLAG_ROCEV1_CAP; 6616 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED) 6617 bp->flags |= BNXT_FLAG_ROCEV2_CAP; 6618 if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED) 6619 bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED; 6620 if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED) 6621 bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED; 6622 6623 bp->tx_push_thresh = 0; 6624 if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) 6625 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH; 6626 6627 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); 6628 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); 6629 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings); 6630 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings); 6631 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); 6632 if (!hw_resc->max_hw_ring_grps) 6633 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings; 6634 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); 6635 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics); 6636 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 6637 6638 if (BNXT_PF(bp)) { 6639 struct bnxt_pf_info *pf = &bp->pf; 6640 6641 pf->fw_fid = le16_to_cpu(resp->fid); 6642 pf->port_id = le16_to_cpu(resp->port_id); 6643 bp->dev->dev_port = pf->port_id; 6644 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN); 6645 pf->first_vf_id = le16_to_cpu(resp->first_vf_id); 6646 pf->max_vfs = le16_to_cpu(resp->max_vfs); 6647 pf->max_encap_records = le32_to_cpu(resp->max_encap_records); 6648 pf->max_decap_records = le32_to_cpu(resp->max_decap_records); 6649 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows); 6650 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows); 6651 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows); 6652 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows); 6653 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED) 6654 bp->flags |= BNXT_FLAG_WOL_CAP; 6655 } else { 6656 #ifdef CONFIG_BNXT_SRIOV 6657 struct bnxt_vf_info *vf = &bp->vf; 6658 6659 vf->fw_fid = le16_to_cpu(resp->fid); 6660 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN); 6661 #endif 6662 } 6663 6664 hwrm_func_qcaps_exit: 6665 mutex_unlock(&bp->hwrm_cmd_lock); 6666 return rc; 6667 } 6668 6669 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp); 6670 6671 static int bnxt_hwrm_func_qcaps(struct bnxt *bp) 6672 { 6673 int rc; 6674 6675 rc = __bnxt_hwrm_func_qcaps(bp); 6676 if (rc) 6677 return rc; 6678 rc = bnxt_hwrm_queue_qportcfg(bp); 6679 if (rc) { 6680 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc); 6681 return rc; 6682 } 6683 if (bp->hwrm_spec_code >= 0x10803) { 6684 rc = bnxt_alloc_ctx_mem(bp); 6685 if (rc) 6686 return rc; 6687 rc = bnxt_hwrm_func_resc_qcaps(bp, true); 6688 if (!rc) 6689 bp->fw_cap |= BNXT_FW_CAP_NEW_RM; 6690 } 6691 return 0; 6692 } 6693 6694 static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp) 6695 { 6696 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0}; 6697 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp; 6698 int rc = 0; 6699 u32 flags; 6700 6701 if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW)) 6702 return 0; 6703 6704 resp = bp->hwrm_cmd_resp_addr; 6705 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, -1, -1); 6706 6707 mutex_lock(&bp->hwrm_cmd_lock); 6708 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6709 if (rc) 6710 goto hwrm_cfa_adv_qcaps_exit; 6711 6712 flags = le32_to_cpu(resp->flags); 6713 if (flags & 6714 CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED) 6715 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX; 6716 6717 hwrm_cfa_adv_qcaps_exit: 6718 mutex_unlock(&bp->hwrm_cmd_lock); 6719 return rc; 6720 } 6721 6722 static int bnxt_hwrm_func_reset(struct bnxt *bp) 6723 { 6724 struct hwrm_func_reset_input req = {0}; 6725 6726 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1); 6727 req.enables = 0; 6728 6729 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT); 6730 } 6731 6732 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp) 6733 { 6734 int rc = 0; 6735 struct hwrm_queue_qportcfg_input req = {0}; 6736 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr; 6737 u8 i, j, *qptr; 6738 bool no_rdma; 6739 6740 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1); 6741 6742 mutex_lock(&bp->hwrm_cmd_lock); 6743 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6744 if (rc) 6745 goto qportcfg_exit; 6746 6747 if (!resp->max_configurable_queues) { 6748 rc = -EINVAL; 6749 goto qportcfg_exit; 6750 } 6751 bp->max_tc = resp->max_configurable_queues; 6752 bp->max_lltc = resp->max_configurable_lossless_queues; 6753 if (bp->max_tc > BNXT_MAX_QUEUE) 6754 bp->max_tc = BNXT_MAX_QUEUE; 6755 6756 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP); 6757 qptr = &resp->queue_id0; 6758 for (i = 0, j = 0; i < bp->max_tc; i++) { 6759 bp->q_info[j].queue_id = *qptr; 6760 bp->q_ids[i] = *qptr++; 6761 bp->q_info[j].queue_profile = *qptr++; 6762 bp->tc_to_qidx[j] = j; 6763 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) || 6764 (no_rdma && BNXT_PF(bp))) 6765 j++; 6766 } 6767 bp->max_q = bp->max_tc; 6768 bp->max_tc = max_t(u8, j, 1); 6769 6770 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG) 6771 bp->max_tc = 1; 6772 6773 if (bp->max_lltc > bp->max_tc) 6774 bp->max_lltc = bp->max_tc; 6775 6776 qportcfg_exit: 6777 mutex_unlock(&bp->hwrm_cmd_lock); 6778 return rc; 6779 } 6780 6781 static int bnxt_hwrm_ver_get(struct bnxt *bp) 6782 { 6783 int rc; 6784 struct hwrm_ver_get_input req = {0}; 6785 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr; 6786 u32 dev_caps_cfg; 6787 6788 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN; 6789 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1); 6790 req.hwrm_intf_maj = HWRM_VERSION_MAJOR; 6791 req.hwrm_intf_min = HWRM_VERSION_MINOR; 6792 req.hwrm_intf_upd = HWRM_VERSION_UPDATE; 6793 mutex_lock(&bp->hwrm_cmd_lock); 6794 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6795 if (rc) 6796 goto hwrm_ver_get_exit; 6797 6798 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output)); 6799 6800 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 | 6801 resp->hwrm_intf_min_8b << 8 | 6802 resp->hwrm_intf_upd_8b; 6803 if (resp->hwrm_intf_maj_8b < 1) { 6804 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n", 6805 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b, 6806 resp->hwrm_intf_upd_8b); 6807 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n"); 6808 } 6809 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d", 6810 resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b, 6811 resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b); 6812 6813 if (strlen(resp->active_pkg_name)) { 6814 int fw_ver_len = strlen(bp->fw_ver_str); 6815 6816 snprintf(bp->fw_ver_str + fw_ver_len, 6817 FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s", 6818 resp->active_pkg_name); 6819 bp->fw_cap |= BNXT_FW_CAP_PKG_VER; 6820 } 6821 6822 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout); 6823 if (!bp->hwrm_cmd_timeout) 6824 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; 6825 6826 if (resp->hwrm_intf_maj_8b >= 1) { 6827 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len); 6828 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len); 6829 } 6830 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN) 6831 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN; 6832 6833 bp->chip_num = le16_to_cpu(resp->chip_num); 6834 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev && 6835 !resp->chip_metal) 6836 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0; 6837 6838 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg); 6839 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) && 6840 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) 6841 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD; 6842 6843 if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) 6844 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL; 6845 6846 if (dev_caps_cfg & 6847 VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED) 6848 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE; 6849 6850 if (dev_caps_cfg & 6851 VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED) 6852 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF; 6853 6854 if (dev_caps_cfg & 6855 VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) 6856 bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW; 6857 6858 hwrm_ver_get_exit: 6859 mutex_unlock(&bp->hwrm_cmd_lock); 6860 return rc; 6861 } 6862 6863 int bnxt_hwrm_fw_set_time(struct bnxt *bp) 6864 { 6865 struct hwrm_fw_set_time_input req = {0}; 6866 struct tm tm; 6867 time64_t now = ktime_get_real_seconds(); 6868 6869 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) || 6870 bp->hwrm_spec_code < 0x10400) 6871 return -EOPNOTSUPP; 6872 6873 time64_to_tm(now, 0, &tm); 6874 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1); 6875 req.year = cpu_to_le16(1900 + tm.tm_year); 6876 req.month = 1 + tm.tm_mon; 6877 req.day = tm.tm_mday; 6878 req.hour = tm.tm_hour; 6879 req.minute = tm.tm_min; 6880 req.second = tm.tm_sec; 6881 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6882 } 6883 6884 static int bnxt_hwrm_port_qstats(struct bnxt *bp) 6885 { 6886 int rc; 6887 struct bnxt_pf_info *pf = &bp->pf; 6888 struct hwrm_port_qstats_input req = {0}; 6889 6890 if (!(bp->flags & BNXT_FLAG_PORT_STATS)) 6891 return 0; 6892 6893 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1); 6894 req.port_id = cpu_to_le16(pf->port_id); 6895 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map); 6896 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map); 6897 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6898 return rc; 6899 } 6900 6901 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp) 6902 { 6903 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr; 6904 struct hwrm_queue_pri2cos_qcfg_input req2 = {0}; 6905 struct hwrm_port_qstats_ext_input req = {0}; 6906 struct bnxt_pf_info *pf = &bp->pf; 6907 u32 tx_stat_size; 6908 int rc; 6909 6910 if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 6911 return 0; 6912 6913 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1); 6914 req.port_id = cpu_to_le16(pf->port_id); 6915 req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext)); 6916 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map); 6917 tx_stat_size = bp->hw_tx_port_stats_ext ? 6918 sizeof(*bp->hw_tx_port_stats_ext) : 0; 6919 req.tx_stat_size = cpu_to_le16(tx_stat_size); 6920 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_ext_map); 6921 mutex_lock(&bp->hwrm_cmd_lock); 6922 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6923 if (!rc) { 6924 bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8; 6925 bp->fw_tx_stats_ext_size = tx_stat_size ? 6926 le16_to_cpu(resp->tx_stat_size) / 8 : 0; 6927 } else { 6928 bp->fw_rx_stats_ext_size = 0; 6929 bp->fw_tx_stats_ext_size = 0; 6930 } 6931 if (bp->fw_tx_stats_ext_size <= 6932 offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) { 6933 mutex_unlock(&bp->hwrm_cmd_lock); 6934 bp->pri2cos_valid = 0; 6935 return rc; 6936 } 6937 6938 bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1); 6939 req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN); 6940 6941 rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT); 6942 if (!rc) { 6943 struct hwrm_queue_pri2cos_qcfg_output *resp2; 6944 u8 *pri2cos; 6945 int i, j; 6946 6947 resp2 = bp->hwrm_cmd_resp_addr; 6948 pri2cos = &resp2->pri0_cos_queue_id; 6949 for (i = 0; i < 8; i++) { 6950 u8 queue_id = pri2cos[i]; 6951 6952 for (j = 0; j < bp->max_q; j++) { 6953 if (bp->q_ids[j] == queue_id) 6954 bp->pri2cos[i] = j; 6955 } 6956 } 6957 bp->pri2cos_valid = 1; 6958 } 6959 mutex_unlock(&bp->hwrm_cmd_lock); 6960 return rc; 6961 } 6962 6963 static int bnxt_hwrm_pcie_qstats(struct bnxt *bp) 6964 { 6965 struct hwrm_pcie_qstats_input req = {0}; 6966 6967 if (!(bp->flags & BNXT_FLAG_PCIE_STATS)) 6968 return 0; 6969 6970 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PCIE_QSTATS, -1, -1); 6971 req.pcie_stat_size = cpu_to_le16(sizeof(struct pcie_ctx_hw_stats)); 6972 req.pcie_stat_host_addr = cpu_to_le64(bp->hw_pcie_stats_map); 6973 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6974 } 6975 6976 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp) 6977 { 6978 if (bp->vxlan_port_cnt) { 6979 bnxt_hwrm_tunnel_dst_port_free( 6980 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 6981 } 6982 bp->vxlan_port_cnt = 0; 6983 if (bp->nge_port_cnt) { 6984 bnxt_hwrm_tunnel_dst_port_free( 6985 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 6986 } 6987 bp->nge_port_cnt = 0; 6988 } 6989 6990 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa) 6991 { 6992 int rc, i; 6993 u32 tpa_flags = 0; 6994 6995 if (set_tpa) 6996 tpa_flags = bp->flags & BNXT_FLAG_TPA; 6997 for (i = 0; i < bp->nr_vnics; i++) { 6998 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags); 6999 if (rc) { 7000 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n", 7001 i, rc); 7002 return rc; 7003 } 7004 } 7005 return 0; 7006 } 7007 7008 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp) 7009 { 7010 int i; 7011 7012 for (i = 0; i < bp->nr_vnics; i++) 7013 bnxt_hwrm_vnic_set_rss(bp, i, false); 7014 } 7015 7016 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path, 7017 bool irq_re_init) 7018 { 7019 if (bp->vnic_info) { 7020 bnxt_hwrm_clear_vnic_filter(bp); 7021 /* clear all RSS setting before free vnic ctx */ 7022 bnxt_hwrm_clear_vnic_rss(bp); 7023 bnxt_hwrm_vnic_ctx_free(bp); 7024 /* before free the vnic, undo the vnic tpa settings */ 7025 if (bp->flags & BNXT_FLAG_TPA) 7026 bnxt_set_tpa(bp, false); 7027 bnxt_hwrm_vnic_free(bp); 7028 } 7029 bnxt_hwrm_ring_free(bp, close_path); 7030 bnxt_hwrm_ring_grp_free(bp); 7031 if (irq_re_init) { 7032 bnxt_hwrm_stat_ctx_free(bp); 7033 bnxt_hwrm_free_tunnel_ports(bp); 7034 } 7035 } 7036 7037 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode) 7038 { 7039 struct hwrm_func_cfg_input req = {0}; 7040 int rc; 7041 7042 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 7043 req.fid = cpu_to_le16(0xffff); 7044 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE); 7045 if (br_mode == BRIDGE_MODE_VEB) 7046 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB; 7047 else if (br_mode == BRIDGE_MODE_VEPA) 7048 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA; 7049 else 7050 return -EINVAL; 7051 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7052 if (rc) 7053 rc = -EIO; 7054 return rc; 7055 } 7056 7057 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size) 7058 { 7059 struct hwrm_func_cfg_input req = {0}; 7060 int rc; 7061 7062 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803) 7063 return 0; 7064 7065 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1); 7066 req.fid = cpu_to_le16(0xffff); 7067 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE); 7068 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64; 7069 if (size == 128) 7070 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128; 7071 7072 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7073 if (rc) 7074 rc = -EIO; 7075 return rc; 7076 } 7077 7078 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) 7079 { 7080 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 7081 int rc; 7082 7083 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) 7084 goto skip_rss_ctx; 7085 7086 /* allocate context for vnic */ 7087 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0); 7088 if (rc) { 7089 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 7090 vnic_id, rc); 7091 goto vnic_setup_err; 7092 } 7093 bp->rsscos_nr_ctxs++; 7094 7095 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 7096 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1); 7097 if (rc) { 7098 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n", 7099 vnic_id, rc); 7100 goto vnic_setup_err; 7101 } 7102 bp->rsscos_nr_ctxs++; 7103 } 7104 7105 skip_rss_ctx: 7106 /* configure default vnic, ring grp */ 7107 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); 7108 if (rc) { 7109 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", 7110 vnic_id, rc); 7111 goto vnic_setup_err; 7112 } 7113 7114 /* Enable RSS hashing on vnic */ 7115 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true); 7116 if (rc) { 7117 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n", 7118 vnic_id, rc); 7119 goto vnic_setup_err; 7120 } 7121 7122 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 7123 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); 7124 if (rc) { 7125 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", 7126 vnic_id, rc); 7127 } 7128 } 7129 7130 vnic_setup_err: 7131 return rc; 7132 } 7133 7134 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id) 7135 { 7136 int rc, i, nr_ctxs; 7137 7138 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64); 7139 for (i = 0; i < nr_ctxs; i++) { 7140 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i); 7141 if (rc) { 7142 netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n", 7143 vnic_id, i, rc); 7144 break; 7145 } 7146 bp->rsscos_nr_ctxs++; 7147 } 7148 if (i < nr_ctxs) 7149 return -ENOMEM; 7150 7151 rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true); 7152 if (rc) { 7153 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n", 7154 vnic_id, rc); 7155 return rc; 7156 } 7157 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); 7158 if (rc) { 7159 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", 7160 vnic_id, rc); 7161 return rc; 7162 } 7163 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 7164 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); 7165 if (rc) { 7166 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", 7167 vnic_id, rc); 7168 } 7169 } 7170 return rc; 7171 } 7172 7173 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) 7174 { 7175 if (bp->flags & BNXT_FLAG_CHIP_P5) 7176 return __bnxt_setup_vnic_p5(bp, vnic_id); 7177 else 7178 return __bnxt_setup_vnic(bp, vnic_id); 7179 } 7180 7181 static int bnxt_alloc_rfs_vnics(struct bnxt *bp) 7182 { 7183 #ifdef CONFIG_RFS_ACCEL 7184 int i, rc = 0; 7185 7186 for (i = 0; i < bp->rx_nr_rings; i++) { 7187 struct bnxt_vnic_info *vnic; 7188 u16 vnic_id = i + 1; 7189 u16 ring_id = i; 7190 7191 if (vnic_id >= bp->nr_vnics) 7192 break; 7193 7194 vnic = &bp->vnic_info[vnic_id]; 7195 vnic->flags |= BNXT_VNIC_RFS_FLAG; 7196 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 7197 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG; 7198 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1); 7199 if (rc) { 7200 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", 7201 vnic_id, rc); 7202 break; 7203 } 7204 rc = bnxt_setup_vnic(bp, vnic_id); 7205 if (rc) 7206 break; 7207 } 7208 return rc; 7209 #else 7210 return 0; 7211 #endif 7212 } 7213 7214 /* Allow PF and VF with default VLAN to be in promiscuous mode */ 7215 static bool bnxt_promisc_ok(struct bnxt *bp) 7216 { 7217 #ifdef CONFIG_BNXT_SRIOV 7218 if (BNXT_VF(bp) && !bp->vf.vlan) 7219 return false; 7220 #endif 7221 return true; 7222 } 7223 7224 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp) 7225 { 7226 unsigned int rc = 0; 7227 7228 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1); 7229 if (rc) { 7230 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 7231 rc); 7232 return rc; 7233 } 7234 7235 rc = bnxt_hwrm_vnic_cfg(bp, 1); 7236 if (rc) { 7237 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n", 7238 rc); 7239 return rc; 7240 } 7241 return rc; 7242 } 7243 7244 static int bnxt_cfg_rx_mode(struct bnxt *); 7245 static bool bnxt_mc_list_updated(struct bnxt *, u32 *); 7246 7247 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init) 7248 { 7249 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 7250 int rc = 0; 7251 unsigned int rx_nr_rings = bp->rx_nr_rings; 7252 7253 if (irq_re_init) { 7254 rc = bnxt_hwrm_stat_ctx_alloc(bp); 7255 if (rc) { 7256 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n", 7257 rc); 7258 goto err_out; 7259 } 7260 } 7261 7262 rc = bnxt_hwrm_ring_alloc(bp); 7263 if (rc) { 7264 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc); 7265 goto err_out; 7266 } 7267 7268 rc = bnxt_hwrm_ring_grp_alloc(bp); 7269 if (rc) { 7270 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc); 7271 goto err_out; 7272 } 7273 7274 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 7275 rx_nr_rings--; 7276 7277 /* default vnic 0 */ 7278 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings); 7279 if (rc) { 7280 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc); 7281 goto err_out; 7282 } 7283 7284 rc = bnxt_setup_vnic(bp, 0); 7285 if (rc) 7286 goto err_out; 7287 7288 if (bp->flags & BNXT_FLAG_RFS) { 7289 rc = bnxt_alloc_rfs_vnics(bp); 7290 if (rc) 7291 goto err_out; 7292 } 7293 7294 if (bp->flags & BNXT_FLAG_TPA) { 7295 rc = bnxt_set_tpa(bp, true); 7296 if (rc) 7297 goto err_out; 7298 } 7299 7300 if (BNXT_VF(bp)) 7301 bnxt_update_vf_mac(bp); 7302 7303 /* Filter for default vnic 0 */ 7304 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr); 7305 if (rc) { 7306 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc); 7307 goto err_out; 7308 } 7309 vnic->uc_filter_count = 1; 7310 7311 vnic->rx_mask = 0; 7312 if (bp->dev->flags & IFF_BROADCAST) 7313 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 7314 7315 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) 7316 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 7317 7318 if (bp->dev->flags & IFF_ALLMULTI) { 7319 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 7320 vnic->mc_list_count = 0; 7321 } else { 7322 u32 mask = 0; 7323 7324 bnxt_mc_list_updated(bp, &mask); 7325 vnic->rx_mask |= mask; 7326 } 7327 7328 rc = bnxt_cfg_rx_mode(bp); 7329 if (rc) 7330 goto err_out; 7331 7332 rc = bnxt_hwrm_set_coal(bp); 7333 if (rc) 7334 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n", 7335 rc); 7336 7337 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 7338 rc = bnxt_setup_nitroa0_vnic(bp); 7339 if (rc) 7340 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n", 7341 rc); 7342 } 7343 7344 if (BNXT_VF(bp)) { 7345 bnxt_hwrm_func_qcfg(bp); 7346 netdev_update_features(bp->dev); 7347 } 7348 7349 return 0; 7350 7351 err_out: 7352 bnxt_hwrm_resource_free(bp, 0, true); 7353 7354 return rc; 7355 } 7356 7357 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init) 7358 { 7359 bnxt_hwrm_resource_free(bp, 1, irq_re_init); 7360 return 0; 7361 } 7362 7363 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init) 7364 { 7365 bnxt_init_cp_rings(bp); 7366 bnxt_init_rx_rings(bp); 7367 bnxt_init_tx_rings(bp); 7368 bnxt_init_ring_grps(bp, irq_re_init); 7369 bnxt_init_vnics(bp); 7370 7371 return bnxt_init_chip(bp, irq_re_init); 7372 } 7373 7374 static int bnxt_set_real_num_queues(struct bnxt *bp) 7375 { 7376 int rc; 7377 struct net_device *dev = bp->dev; 7378 7379 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings - 7380 bp->tx_nr_rings_xdp); 7381 if (rc) 7382 return rc; 7383 7384 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings); 7385 if (rc) 7386 return rc; 7387 7388 #ifdef CONFIG_RFS_ACCEL 7389 if (bp->flags & BNXT_FLAG_RFS) 7390 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings); 7391 #endif 7392 7393 return rc; 7394 } 7395 7396 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, 7397 bool shared) 7398 { 7399 int _rx = *rx, _tx = *tx; 7400 7401 if (shared) { 7402 *rx = min_t(int, _rx, max); 7403 *tx = min_t(int, _tx, max); 7404 } else { 7405 if (max < 2) 7406 return -ENOMEM; 7407 7408 while (_rx + _tx > max) { 7409 if (_rx > _tx && _rx > 1) 7410 _rx--; 7411 else if (_tx > 1) 7412 _tx--; 7413 } 7414 *rx = _rx; 7415 *tx = _tx; 7416 } 7417 return 0; 7418 } 7419 7420 static void bnxt_setup_msix(struct bnxt *bp) 7421 { 7422 const int len = sizeof(bp->irq_tbl[0].name); 7423 struct net_device *dev = bp->dev; 7424 int tcs, i; 7425 7426 tcs = netdev_get_num_tc(dev); 7427 if (tcs > 1) { 7428 int i, off, count; 7429 7430 for (i = 0; i < tcs; i++) { 7431 count = bp->tx_nr_rings_per_tc; 7432 off = i * count; 7433 netdev_set_tc_queue(dev, i, count, off); 7434 } 7435 } 7436 7437 for (i = 0; i < bp->cp_nr_rings; i++) { 7438 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 7439 char *attr; 7440 7441 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 7442 attr = "TxRx"; 7443 else if (i < bp->rx_nr_rings) 7444 attr = "rx"; 7445 else 7446 attr = "tx"; 7447 7448 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name, 7449 attr, i); 7450 bp->irq_tbl[map_idx].handler = bnxt_msix; 7451 } 7452 } 7453 7454 static void bnxt_setup_inta(struct bnxt *bp) 7455 { 7456 const int len = sizeof(bp->irq_tbl[0].name); 7457 7458 if (netdev_get_num_tc(bp->dev)) 7459 netdev_reset_tc(bp->dev); 7460 7461 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx", 7462 0); 7463 bp->irq_tbl[0].handler = bnxt_inta; 7464 } 7465 7466 static int bnxt_setup_int_mode(struct bnxt *bp) 7467 { 7468 int rc; 7469 7470 if (bp->flags & BNXT_FLAG_USING_MSIX) 7471 bnxt_setup_msix(bp); 7472 else 7473 bnxt_setup_inta(bp); 7474 7475 rc = bnxt_set_real_num_queues(bp); 7476 return rc; 7477 } 7478 7479 #ifdef CONFIG_RFS_ACCEL 7480 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp) 7481 { 7482 return bp->hw_resc.max_rsscos_ctxs; 7483 } 7484 7485 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp) 7486 { 7487 return bp->hw_resc.max_vnics; 7488 } 7489 #endif 7490 7491 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp) 7492 { 7493 return bp->hw_resc.max_stat_ctxs; 7494 } 7495 7496 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp) 7497 { 7498 return bp->hw_resc.max_cp_rings; 7499 } 7500 7501 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp) 7502 { 7503 unsigned int cp = bp->hw_resc.max_cp_rings; 7504 7505 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 7506 cp -= bnxt_get_ulp_msix_num(bp); 7507 7508 return cp; 7509 } 7510 7511 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp) 7512 { 7513 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 7514 7515 if (bp->flags & BNXT_FLAG_CHIP_P5) 7516 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs); 7517 7518 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings); 7519 } 7520 7521 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs) 7522 { 7523 bp->hw_resc.max_irqs = max_irqs; 7524 } 7525 7526 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp) 7527 { 7528 unsigned int cp; 7529 7530 cp = bnxt_get_max_func_cp_rings_for_en(bp); 7531 if (bp->flags & BNXT_FLAG_CHIP_P5) 7532 return cp - bp->rx_nr_rings - bp->tx_nr_rings; 7533 else 7534 return cp - bp->cp_nr_rings; 7535 } 7536 7537 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp) 7538 { 7539 unsigned int stat; 7540 7541 stat = bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_ulp_stat_ctxs(bp); 7542 stat -= bp->cp_nr_rings; 7543 return stat; 7544 } 7545 7546 int bnxt_get_avail_msix(struct bnxt *bp, int num) 7547 { 7548 int max_cp = bnxt_get_max_func_cp_rings(bp); 7549 int max_irq = bnxt_get_max_func_irqs(bp); 7550 int total_req = bp->cp_nr_rings + num; 7551 int max_idx, avail_msix; 7552 7553 max_idx = bp->total_irqs; 7554 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 7555 max_idx = min_t(int, bp->total_irqs, max_cp); 7556 avail_msix = max_idx - bp->cp_nr_rings; 7557 if (!BNXT_NEW_RM(bp) || avail_msix >= num) 7558 return avail_msix; 7559 7560 if (max_irq < total_req) { 7561 num = max_irq - bp->cp_nr_rings; 7562 if (num <= 0) 7563 return 0; 7564 } 7565 return num; 7566 } 7567 7568 static int bnxt_get_num_msix(struct bnxt *bp) 7569 { 7570 if (!BNXT_NEW_RM(bp)) 7571 return bnxt_get_max_func_irqs(bp); 7572 7573 return bnxt_nq_rings_in_use(bp); 7574 } 7575 7576 static int bnxt_init_msix(struct bnxt *bp) 7577 { 7578 int i, total_vecs, max, rc = 0, min = 1, ulp_msix; 7579 struct msix_entry *msix_ent; 7580 7581 total_vecs = bnxt_get_num_msix(bp); 7582 max = bnxt_get_max_func_irqs(bp); 7583 if (total_vecs > max) 7584 total_vecs = max; 7585 7586 if (!total_vecs) 7587 return 0; 7588 7589 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL); 7590 if (!msix_ent) 7591 return -ENOMEM; 7592 7593 for (i = 0; i < total_vecs; i++) { 7594 msix_ent[i].entry = i; 7595 msix_ent[i].vector = 0; 7596 } 7597 7598 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 7599 min = 2; 7600 7601 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs); 7602 ulp_msix = bnxt_get_ulp_msix_num(bp); 7603 if (total_vecs < 0 || total_vecs < ulp_msix) { 7604 rc = -ENODEV; 7605 goto msix_setup_exit; 7606 } 7607 7608 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL); 7609 if (bp->irq_tbl) { 7610 for (i = 0; i < total_vecs; i++) 7611 bp->irq_tbl[i].vector = msix_ent[i].vector; 7612 7613 bp->total_irqs = total_vecs; 7614 /* Trim rings based upon num of vectors allocated */ 7615 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings, 7616 total_vecs - ulp_msix, min == 1); 7617 if (rc) 7618 goto msix_setup_exit; 7619 7620 bp->cp_nr_rings = (min == 1) ? 7621 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 7622 bp->tx_nr_rings + bp->rx_nr_rings; 7623 7624 } else { 7625 rc = -ENOMEM; 7626 goto msix_setup_exit; 7627 } 7628 bp->flags |= BNXT_FLAG_USING_MSIX; 7629 kfree(msix_ent); 7630 return 0; 7631 7632 msix_setup_exit: 7633 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc); 7634 kfree(bp->irq_tbl); 7635 bp->irq_tbl = NULL; 7636 pci_disable_msix(bp->pdev); 7637 kfree(msix_ent); 7638 return rc; 7639 } 7640 7641 static int bnxt_init_inta(struct bnxt *bp) 7642 { 7643 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL); 7644 if (!bp->irq_tbl) 7645 return -ENOMEM; 7646 7647 bp->total_irqs = 1; 7648 bp->rx_nr_rings = 1; 7649 bp->tx_nr_rings = 1; 7650 bp->cp_nr_rings = 1; 7651 bp->flags |= BNXT_FLAG_SHARED_RINGS; 7652 bp->irq_tbl[0].vector = bp->pdev->irq; 7653 return 0; 7654 } 7655 7656 static int bnxt_init_int_mode(struct bnxt *bp) 7657 { 7658 int rc = 0; 7659 7660 if (bp->flags & BNXT_FLAG_MSIX_CAP) 7661 rc = bnxt_init_msix(bp); 7662 7663 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) { 7664 /* fallback to INTA */ 7665 rc = bnxt_init_inta(bp); 7666 } 7667 return rc; 7668 } 7669 7670 static void bnxt_clear_int_mode(struct bnxt *bp) 7671 { 7672 if (bp->flags & BNXT_FLAG_USING_MSIX) 7673 pci_disable_msix(bp->pdev); 7674 7675 kfree(bp->irq_tbl); 7676 bp->irq_tbl = NULL; 7677 bp->flags &= ~BNXT_FLAG_USING_MSIX; 7678 } 7679 7680 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init) 7681 { 7682 int tcs = netdev_get_num_tc(bp->dev); 7683 bool irq_cleared = false; 7684 int rc; 7685 7686 if (!bnxt_need_reserve_rings(bp)) 7687 return 0; 7688 7689 if (irq_re_init && BNXT_NEW_RM(bp) && 7690 bnxt_get_num_msix(bp) != bp->total_irqs) { 7691 bnxt_ulp_irq_stop(bp); 7692 bnxt_clear_int_mode(bp); 7693 irq_cleared = true; 7694 } 7695 rc = __bnxt_reserve_rings(bp); 7696 if (irq_cleared) { 7697 if (!rc) 7698 rc = bnxt_init_int_mode(bp); 7699 bnxt_ulp_irq_restart(bp, rc); 7700 } 7701 if (rc) { 7702 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc); 7703 return rc; 7704 } 7705 if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) { 7706 netdev_err(bp->dev, "tx ring reservation failure\n"); 7707 netdev_reset_tc(bp->dev); 7708 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 7709 return -ENOMEM; 7710 } 7711 return 0; 7712 } 7713 7714 static void bnxt_free_irq(struct bnxt *bp) 7715 { 7716 struct bnxt_irq *irq; 7717 int i; 7718 7719 #ifdef CONFIG_RFS_ACCEL 7720 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap); 7721 bp->dev->rx_cpu_rmap = NULL; 7722 #endif 7723 if (!bp->irq_tbl || !bp->bnapi) 7724 return; 7725 7726 for (i = 0; i < bp->cp_nr_rings; i++) { 7727 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 7728 7729 irq = &bp->irq_tbl[map_idx]; 7730 if (irq->requested) { 7731 if (irq->have_cpumask) { 7732 irq_set_affinity_hint(irq->vector, NULL); 7733 free_cpumask_var(irq->cpu_mask); 7734 irq->have_cpumask = 0; 7735 } 7736 free_irq(irq->vector, bp->bnapi[i]); 7737 } 7738 7739 irq->requested = 0; 7740 } 7741 } 7742 7743 static int bnxt_request_irq(struct bnxt *bp) 7744 { 7745 int i, j, rc = 0; 7746 unsigned long flags = 0; 7747 #ifdef CONFIG_RFS_ACCEL 7748 struct cpu_rmap *rmap; 7749 #endif 7750 7751 rc = bnxt_setup_int_mode(bp); 7752 if (rc) { 7753 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n", 7754 rc); 7755 return rc; 7756 } 7757 #ifdef CONFIG_RFS_ACCEL 7758 rmap = bp->dev->rx_cpu_rmap; 7759 #endif 7760 if (!(bp->flags & BNXT_FLAG_USING_MSIX)) 7761 flags = IRQF_SHARED; 7762 7763 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) { 7764 int map_idx = bnxt_cp_num_to_irq_num(bp, i); 7765 struct bnxt_irq *irq = &bp->irq_tbl[map_idx]; 7766 7767 #ifdef CONFIG_RFS_ACCEL 7768 if (rmap && bp->bnapi[i]->rx_ring) { 7769 rc = irq_cpu_rmap_add(rmap, irq->vector); 7770 if (rc) 7771 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n", 7772 j); 7773 j++; 7774 } 7775 #endif 7776 rc = request_irq(irq->vector, irq->handler, flags, irq->name, 7777 bp->bnapi[i]); 7778 if (rc) 7779 break; 7780 7781 irq->requested = 1; 7782 7783 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) { 7784 int numa_node = dev_to_node(&bp->pdev->dev); 7785 7786 irq->have_cpumask = 1; 7787 cpumask_set_cpu(cpumask_local_spread(i, numa_node), 7788 irq->cpu_mask); 7789 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask); 7790 if (rc) { 7791 netdev_warn(bp->dev, 7792 "Set affinity failed, IRQ = %d\n", 7793 irq->vector); 7794 break; 7795 } 7796 } 7797 } 7798 return rc; 7799 } 7800 7801 static void bnxt_del_napi(struct bnxt *bp) 7802 { 7803 int i; 7804 7805 if (!bp->bnapi) 7806 return; 7807 7808 for (i = 0; i < bp->cp_nr_rings; i++) { 7809 struct bnxt_napi *bnapi = bp->bnapi[i]; 7810 7811 napi_hash_del(&bnapi->napi); 7812 netif_napi_del(&bnapi->napi); 7813 } 7814 /* We called napi_hash_del() before netif_napi_del(), we need 7815 * to respect an RCU grace period before freeing napi structures. 7816 */ 7817 synchronize_net(); 7818 } 7819 7820 static void bnxt_init_napi(struct bnxt *bp) 7821 { 7822 int i; 7823 unsigned int cp_nr_rings = bp->cp_nr_rings; 7824 struct bnxt_napi *bnapi; 7825 7826 if (bp->flags & BNXT_FLAG_USING_MSIX) { 7827 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll; 7828 7829 if (bp->flags & BNXT_FLAG_CHIP_P5) 7830 poll_fn = bnxt_poll_p5; 7831 else if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 7832 cp_nr_rings--; 7833 for (i = 0; i < cp_nr_rings; i++) { 7834 bnapi = bp->bnapi[i]; 7835 netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64); 7836 } 7837 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 7838 bnapi = bp->bnapi[cp_nr_rings]; 7839 netif_napi_add(bp->dev, &bnapi->napi, 7840 bnxt_poll_nitroa0, 64); 7841 } 7842 } else { 7843 bnapi = bp->bnapi[0]; 7844 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64); 7845 } 7846 } 7847 7848 static void bnxt_disable_napi(struct bnxt *bp) 7849 { 7850 int i; 7851 7852 if (!bp->bnapi) 7853 return; 7854 7855 for (i = 0; i < bp->cp_nr_rings; i++) { 7856 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 7857 7858 if (bp->bnapi[i]->rx_ring) 7859 cancel_work_sync(&cpr->dim.work); 7860 7861 napi_disable(&bp->bnapi[i]->napi); 7862 } 7863 } 7864 7865 static void bnxt_enable_napi(struct bnxt *bp) 7866 { 7867 int i; 7868 7869 for (i = 0; i < bp->cp_nr_rings; i++) { 7870 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring; 7871 bp->bnapi[i]->in_reset = false; 7872 7873 if (bp->bnapi[i]->rx_ring) { 7874 INIT_WORK(&cpr->dim.work, bnxt_dim_work); 7875 cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 7876 } 7877 napi_enable(&bp->bnapi[i]->napi); 7878 } 7879 } 7880 7881 void bnxt_tx_disable(struct bnxt *bp) 7882 { 7883 int i; 7884 struct bnxt_tx_ring_info *txr; 7885 7886 if (bp->tx_ring) { 7887 for (i = 0; i < bp->tx_nr_rings; i++) { 7888 txr = &bp->tx_ring[i]; 7889 txr->dev_state = BNXT_DEV_STATE_CLOSING; 7890 } 7891 } 7892 /* Stop all TX queues */ 7893 netif_tx_disable(bp->dev); 7894 netif_carrier_off(bp->dev); 7895 } 7896 7897 void bnxt_tx_enable(struct bnxt *bp) 7898 { 7899 int i; 7900 struct bnxt_tx_ring_info *txr; 7901 7902 for (i = 0; i < bp->tx_nr_rings; i++) { 7903 txr = &bp->tx_ring[i]; 7904 txr->dev_state = 0; 7905 } 7906 netif_tx_wake_all_queues(bp->dev); 7907 if (bp->link_info.link_up) 7908 netif_carrier_on(bp->dev); 7909 } 7910 7911 static void bnxt_report_link(struct bnxt *bp) 7912 { 7913 if (bp->link_info.link_up) { 7914 const char *duplex; 7915 const char *flow_ctrl; 7916 u32 speed; 7917 u16 fec; 7918 7919 netif_carrier_on(bp->dev); 7920 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL) 7921 duplex = "full"; 7922 else 7923 duplex = "half"; 7924 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH) 7925 flow_ctrl = "ON - receive & transmit"; 7926 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX) 7927 flow_ctrl = "ON - transmit"; 7928 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX) 7929 flow_ctrl = "ON - receive"; 7930 else 7931 flow_ctrl = "none"; 7932 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed); 7933 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n", 7934 speed, duplex, flow_ctrl); 7935 if (bp->flags & BNXT_FLAG_EEE_CAP) 7936 netdev_info(bp->dev, "EEE is %s\n", 7937 bp->eee.eee_active ? "active" : 7938 "not active"); 7939 fec = bp->link_info.fec_cfg; 7940 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED)) 7941 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n", 7942 (fec & BNXT_FEC_AUTONEG) ? "on" : "off", 7943 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" : 7944 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None"); 7945 } else { 7946 netif_carrier_off(bp->dev); 7947 netdev_err(bp->dev, "NIC Link is Down\n"); 7948 } 7949 } 7950 7951 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp) 7952 { 7953 int rc = 0; 7954 struct hwrm_port_phy_qcaps_input req = {0}; 7955 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 7956 struct bnxt_link_info *link_info = &bp->link_info; 7957 7958 if (bp->hwrm_spec_code < 0x10201) 7959 return 0; 7960 7961 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1); 7962 7963 mutex_lock(&bp->hwrm_cmd_lock); 7964 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 7965 if (rc) 7966 goto hwrm_phy_qcaps_exit; 7967 7968 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) { 7969 struct ethtool_eee *eee = &bp->eee; 7970 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode); 7971 7972 bp->flags |= BNXT_FLAG_EEE_CAP; 7973 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 7974 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) & 7975 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK; 7976 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) & 7977 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK; 7978 } 7979 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) { 7980 if (bp->test_info) 7981 bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK; 7982 } 7983 if (resp->supported_speeds_auto_mode) 7984 link_info->support_auto_speeds = 7985 le16_to_cpu(resp->supported_speeds_auto_mode); 7986 7987 bp->port_count = resp->port_cnt; 7988 7989 hwrm_phy_qcaps_exit: 7990 mutex_unlock(&bp->hwrm_cmd_lock); 7991 return rc; 7992 } 7993 7994 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state) 7995 { 7996 int rc = 0; 7997 struct bnxt_link_info *link_info = &bp->link_info; 7998 struct hwrm_port_phy_qcfg_input req = {0}; 7999 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 8000 u8 link_up = link_info->link_up; 8001 u16 diff; 8002 8003 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1); 8004 8005 mutex_lock(&bp->hwrm_cmd_lock); 8006 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8007 if (rc) { 8008 mutex_unlock(&bp->hwrm_cmd_lock); 8009 return rc; 8010 } 8011 8012 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp)); 8013 link_info->phy_link_status = resp->link; 8014 link_info->duplex = resp->duplex_cfg; 8015 if (bp->hwrm_spec_code >= 0x10800) 8016 link_info->duplex = resp->duplex_state; 8017 link_info->pause = resp->pause; 8018 link_info->auto_mode = resp->auto_mode; 8019 link_info->auto_pause_setting = resp->auto_pause; 8020 link_info->lp_pause = resp->link_partner_adv_pause; 8021 link_info->force_pause_setting = resp->force_pause; 8022 link_info->duplex_setting = resp->duplex_cfg; 8023 if (link_info->phy_link_status == BNXT_LINK_LINK) 8024 link_info->link_speed = le16_to_cpu(resp->link_speed); 8025 else 8026 link_info->link_speed = 0; 8027 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed); 8028 link_info->support_speeds = le16_to_cpu(resp->support_speeds); 8029 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask); 8030 link_info->lp_auto_link_speeds = 8031 le16_to_cpu(resp->link_partner_adv_speeds); 8032 link_info->preemphasis = le32_to_cpu(resp->preemphasis); 8033 link_info->phy_ver[0] = resp->phy_maj; 8034 link_info->phy_ver[1] = resp->phy_min; 8035 link_info->phy_ver[2] = resp->phy_bld; 8036 link_info->media_type = resp->media_type; 8037 link_info->phy_type = resp->phy_type; 8038 link_info->transceiver = resp->xcvr_pkg_type; 8039 link_info->phy_addr = resp->eee_config_phy_addr & 8040 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK; 8041 link_info->module_status = resp->module_status; 8042 8043 if (bp->flags & BNXT_FLAG_EEE_CAP) { 8044 struct ethtool_eee *eee = &bp->eee; 8045 u16 fw_speeds; 8046 8047 eee->eee_active = 0; 8048 if (resp->eee_config_phy_addr & 8049 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) { 8050 eee->eee_active = 1; 8051 fw_speeds = le16_to_cpu( 8052 resp->link_partner_adv_eee_link_speed_mask); 8053 eee->lp_advertised = 8054 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 8055 } 8056 8057 /* Pull initial EEE config */ 8058 if (!chng_link_state) { 8059 if (resp->eee_config_phy_addr & 8060 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED) 8061 eee->eee_enabled = 1; 8062 8063 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask); 8064 eee->advertised = 8065 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0); 8066 8067 if (resp->eee_config_phy_addr & 8068 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) { 8069 __le32 tmr; 8070 8071 eee->tx_lpi_enabled = 1; 8072 tmr = resp->xcvr_identifier_type_tx_lpi_timer; 8073 eee->tx_lpi_timer = le32_to_cpu(tmr) & 8074 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK; 8075 } 8076 } 8077 } 8078 8079 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED; 8080 if (bp->hwrm_spec_code >= 0x10504) 8081 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg); 8082 8083 /* TODO: need to add more logic to report VF link */ 8084 if (chng_link_state) { 8085 if (link_info->phy_link_status == BNXT_LINK_LINK) 8086 link_info->link_up = 1; 8087 else 8088 link_info->link_up = 0; 8089 if (link_up != link_info->link_up) 8090 bnxt_report_link(bp); 8091 } else { 8092 /* alwasy link down if not require to update link state */ 8093 link_info->link_up = 0; 8094 } 8095 mutex_unlock(&bp->hwrm_cmd_lock); 8096 8097 if (!BNXT_SINGLE_PF(bp)) 8098 return 0; 8099 8100 diff = link_info->support_auto_speeds ^ link_info->advertising; 8101 if ((link_info->support_auto_speeds | diff) != 8102 link_info->support_auto_speeds) { 8103 /* An advertised speed is no longer supported, so we need to 8104 * update the advertisement settings. Caller holds RTNL 8105 * so we can modify link settings. 8106 */ 8107 link_info->advertising = link_info->support_auto_speeds; 8108 if (link_info->autoneg & BNXT_AUTONEG_SPEED) 8109 bnxt_hwrm_set_link_setting(bp, true, false); 8110 } 8111 return 0; 8112 } 8113 8114 static void bnxt_get_port_module_status(struct bnxt *bp) 8115 { 8116 struct bnxt_link_info *link_info = &bp->link_info; 8117 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp; 8118 u8 module_status; 8119 8120 if (bnxt_update_link(bp, true)) 8121 return; 8122 8123 module_status = link_info->module_status; 8124 switch (module_status) { 8125 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX: 8126 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 8127 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG: 8128 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n", 8129 bp->pf.port_id); 8130 if (bp->hwrm_spec_code >= 0x10201) { 8131 netdev_warn(bp->dev, "Module part number %s\n", 8132 resp->phy_vendor_partnumber); 8133 } 8134 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX) 8135 netdev_warn(bp->dev, "TX is disabled\n"); 8136 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN) 8137 netdev_warn(bp->dev, "SFP+ module is shutdown\n"); 8138 } 8139 } 8140 8141 static void 8142 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req) 8143 { 8144 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) { 8145 if (bp->hwrm_spec_code >= 0x10201) 8146 req->auto_pause = 8147 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 8148 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 8149 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX; 8150 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 8151 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX; 8152 req->enables |= 8153 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 8154 } else { 8155 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) 8156 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX; 8157 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) 8158 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX; 8159 req->enables |= 8160 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE); 8161 if (bp->hwrm_spec_code >= 0x10201) { 8162 req->auto_pause = req->force_pause; 8163 req->enables |= cpu_to_le32( 8164 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); 8165 } 8166 } 8167 } 8168 8169 static void bnxt_hwrm_set_link_common(struct bnxt *bp, 8170 struct hwrm_port_phy_cfg_input *req) 8171 { 8172 u8 autoneg = bp->link_info.autoneg; 8173 u16 fw_link_speed = bp->link_info.req_link_speed; 8174 u16 advertising = bp->link_info.advertising; 8175 8176 if (autoneg & BNXT_AUTONEG_SPEED) { 8177 req->auto_mode |= 8178 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK; 8179 8180 req->enables |= cpu_to_le32( 8181 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK); 8182 req->auto_link_speed_mask = cpu_to_le16(advertising); 8183 8184 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE); 8185 req->flags |= 8186 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG); 8187 } else { 8188 req->force_link_speed = cpu_to_le16(fw_link_speed); 8189 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE); 8190 } 8191 8192 /* tell chimp that the setting takes effect immediately */ 8193 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 8194 } 8195 8196 int bnxt_hwrm_set_pause(struct bnxt *bp) 8197 { 8198 struct hwrm_port_phy_cfg_input req = {0}; 8199 int rc; 8200 8201 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 8202 bnxt_hwrm_set_pause_common(bp, &req); 8203 8204 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) || 8205 bp->link_info.force_link_chng) 8206 bnxt_hwrm_set_link_common(bp, &req); 8207 8208 mutex_lock(&bp->hwrm_cmd_lock); 8209 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8210 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) { 8211 /* since changing of pause setting doesn't trigger any link 8212 * change event, the driver needs to update the current pause 8213 * result upon successfully return of the phy_cfg command 8214 */ 8215 bp->link_info.pause = 8216 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl; 8217 bp->link_info.auto_pause_setting = 0; 8218 if (!bp->link_info.force_link_chng) 8219 bnxt_report_link(bp); 8220 } 8221 bp->link_info.force_link_chng = false; 8222 mutex_unlock(&bp->hwrm_cmd_lock); 8223 return rc; 8224 } 8225 8226 static void bnxt_hwrm_set_eee(struct bnxt *bp, 8227 struct hwrm_port_phy_cfg_input *req) 8228 { 8229 struct ethtool_eee *eee = &bp->eee; 8230 8231 if (eee->eee_enabled) { 8232 u16 eee_speeds; 8233 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE; 8234 8235 if (eee->tx_lpi_enabled) 8236 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE; 8237 else 8238 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE; 8239 8240 req->flags |= cpu_to_le32(flags); 8241 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised); 8242 req->eee_link_speed_mask = cpu_to_le16(eee_speeds); 8243 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer); 8244 } else { 8245 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE); 8246 } 8247 } 8248 8249 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee) 8250 { 8251 struct hwrm_port_phy_cfg_input req = {0}; 8252 8253 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 8254 if (set_pause) 8255 bnxt_hwrm_set_pause_common(bp, &req); 8256 8257 bnxt_hwrm_set_link_common(bp, &req); 8258 8259 if (set_eee) 8260 bnxt_hwrm_set_eee(bp, &req); 8261 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8262 } 8263 8264 static int bnxt_hwrm_shutdown_link(struct bnxt *bp) 8265 { 8266 struct hwrm_port_phy_cfg_input req = {0}; 8267 8268 if (!BNXT_SINGLE_PF(bp)) 8269 return 0; 8270 8271 if (pci_num_vf(bp->pdev)) 8272 return 0; 8273 8274 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 8275 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN); 8276 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8277 } 8278 8279 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up) 8280 { 8281 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr; 8282 struct hwrm_func_drv_if_change_input req = {0}; 8283 bool resc_reinit = false; 8284 int rc; 8285 8286 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE)) 8287 return 0; 8288 8289 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1); 8290 if (up) 8291 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP); 8292 mutex_lock(&bp->hwrm_cmd_lock); 8293 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8294 if (!rc && (resp->flags & 8295 cpu_to_le32(FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE))) 8296 resc_reinit = true; 8297 mutex_unlock(&bp->hwrm_cmd_lock); 8298 8299 if (up && resc_reinit && BNXT_NEW_RM(bp)) { 8300 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 8301 8302 rc = bnxt_hwrm_func_resc_qcaps(bp, true); 8303 hw_resc->resv_cp_rings = 0; 8304 hw_resc->resv_stat_ctxs = 0; 8305 hw_resc->resv_irqs = 0; 8306 hw_resc->resv_tx_rings = 0; 8307 hw_resc->resv_rx_rings = 0; 8308 hw_resc->resv_hw_ring_grps = 0; 8309 hw_resc->resv_vnics = 0; 8310 bp->tx_nr_rings = 0; 8311 bp->rx_nr_rings = 0; 8312 } 8313 return rc; 8314 } 8315 8316 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp) 8317 { 8318 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 8319 struct hwrm_port_led_qcaps_input req = {0}; 8320 struct bnxt_pf_info *pf = &bp->pf; 8321 int rc; 8322 8323 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601) 8324 return 0; 8325 8326 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1); 8327 req.port_id = cpu_to_le16(pf->port_id); 8328 mutex_lock(&bp->hwrm_cmd_lock); 8329 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8330 if (rc) { 8331 mutex_unlock(&bp->hwrm_cmd_lock); 8332 return rc; 8333 } 8334 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) { 8335 int i; 8336 8337 bp->num_leds = resp->num_leds; 8338 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) * 8339 bp->num_leds); 8340 for (i = 0; i < bp->num_leds; i++) { 8341 struct bnxt_led_info *led = &bp->leds[i]; 8342 __le16 caps = led->led_state_caps; 8343 8344 if (!led->led_group_id || 8345 !BNXT_LED_ALT_BLINK_CAP(caps)) { 8346 bp->num_leds = 0; 8347 break; 8348 } 8349 } 8350 } 8351 mutex_unlock(&bp->hwrm_cmd_lock); 8352 return 0; 8353 } 8354 8355 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp) 8356 { 8357 struct hwrm_wol_filter_alloc_input req = {0}; 8358 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; 8359 int rc; 8360 8361 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1); 8362 req.port_id = cpu_to_le16(bp->pf.port_id); 8363 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT; 8364 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS); 8365 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN); 8366 mutex_lock(&bp->hwrm_cmd_lock); 8367 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8368 if (!rc) 8369 bp->wol_filter_id = resp->wol_filter_id; 8370 mutex_unlock(&bp->hwrm_cmd_lock); 8371 return rc; 8372 } 8373 8374 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp) 8375 { 8376 struct hwrm_wol_filter_free_input req = {0}; 8377 int rc; 8378 8379 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1); 8380 req.port_id = cpu_to_le16(bp->pf.port_id); 8381 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID); 8382 req.wol_filter_id = bp->wol_filter_id; 8383 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8384 return rc; 8385 } 8386 8387 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle) 8388 { 8389 struct hwrm_wol_filter_qcfg_input req = {0}; 8390 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr; 8391 u16 next_handle = 0; 8392 int rc; 8393 8394 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1); 8395 req.port_id = cpu_to_le16(bp->pf.port_id); 8396 req.handle = cpu_to_le16(handle); 8397 mutex_lock(&bp->hwrm_cmd_lock); 8398 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8399 if (!rc) { 8400 next_handle = le16_to_cpu(resp->next_handle); 8401 if (next_handle != 0) { 8402 if (resp->wol_type == 8403 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) { 8404 bp->wol = 1; 8405 bp->wol_filter_id = resp->wol_filter_id; 8406 } 8407 } 8408 } 8409 mutex_unlock(&bp->hwrm_cmd_lock); 8410 return next_handle; 8411 } 8412 8413 static void bnxt_get_wol_settings(struct bnxt *bp) 8414 { 8415 u16 handle = 0; 8416 8417 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP)) 8418 return; 8419 8420 do { 8421 handle = bnxt_hwrm_get_wol_fltrs(bp, handle); 8422 } while (handle && handle != 0xffff); 8423 } 8424 8425 #ifdef CONFIG_BNXT_HWMON 8426 static ssize_t bnxt_show_temp(struct device *dev, 8427 struct device_attribute *devattr, char *buf) 8428 { 8429 struct hwrm_temp_monitor_query_input req = {0}; 8430 struct hwrm_temp_monitor_query_output *resp; 8431 struct bnxt *bp = dev_get_drvdata(dev); 8432 u32 temp = 0; 8433 8434 resp = bp->hwrm_cmd_resp_addr; 8435 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1); 8436 mutex_lock(&bp->hwrm_cmd_lock); 8437 if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT)) 8438 temp = resp->temp * 1000; /* display millidegree */ 8439 mutex_unlock(&bp->hwrm_cmd_lock); 8440 8441 return sprintf(buf, "%u\n", temp); 8442 } 8443 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0); 8444 8445 static struct attribute *bnxt_attrs[] = { 8446 &sensor_dev_attr_temp1_input.dev_attr.attr, 8447 NULL 8448 }; 8449 ATTRIBUTE_GROUPS(bnxt); 8450 8451 static void bnxt_hwmon_close(struct bnxt *bp) 8452 { 8453 if (bp->hwmon_dev) { 8454 hwmon_device_unregister(bp->hwmon_dev); 8455 bp->hwmon_dev = NULL; 8456 } 8457 } 8458 8459 static void bnxt_hwmon_open(struct bnxt *bp) 8460 { 8461 struct pci_dev *pdev = bp->pdev; 8462 8463 bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, 8464 DRV_MODULE_NAME, bp, 8465 bnxt_groups); 8466 if (IS_ERR(bp->hwmon_dev)) { 8467 bp->hwmon_dev = NULL; 8468 dev_warn(&pdev->dev, "Cannot register hwmon device\n"); 8469 } 8470 } 8471 #else 8472 static void bnxt_hwmon_close(struct bnxt *bp) 8473 { 8474 } 8475 8476 static void bnxt_hwmon_open(struct bnxt *bp) 8477 { 8478 } 8479 #endif 8480 8481 static bool bnxt_eee_config_ok(struct bnxt *bp) 8482 { 8483 struct ethtool_eee *eee = &bp->eee; 8484 struct bnxt_link_info *link_info = &bp->link_info; 8485 8486 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 8487 return true; 8488 8489 if (eee->eee_enabled) { 8490 u32 advertising = 8491 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 8492 8493 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 8494 eee->eee_enabled = 0; 8495 return false; 8496 } 8497 if (eee->advertised & ~advertising) { 8498 eee->advertised = advertising & eee->supported; 8499 return false; 8500 } 8501 } 8502 return true; 8503 } 8504 8505 static int bnxt_update_phy_setting(struct bnxt *bp) 8506 { 8507 int rc; 8508 bool update_link = false; 8509 bool update_pause = false; 8510 bool update_eee = false; 8511 struct bnxt_link_info *link_info = &bp->link_info; 8512 8513 rc = bnxt_update_link(bp, true); 8514 if (rc) { 8515 netdev_err(bp->dev, "failed to update link (rc: %x)\n", 8516 rc); 8517 return rc; 8518 } 8519 if (!BNXT_SINGLE_PF(bp)) 8520 return 0; 8521 8522 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 8523 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) != 8524 link_info->req_flow_ctrl) 8525 update_pause = true; 8526 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && 8527 link_info->force_pause_setting != link_info->req_flow_ctrl) 8528 update_pause = true; 8529 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 8530 if (BNXT_AUTO_MODE(link_info->auto_mode)) 8531 update_link = true; 8532 if (link_info->req_link_speed != link_info->force_link_speed) 8533 update_link = true; 8534 if (link_info->req_duplex != link_info->duplex_setting) 8535 update_link = true; 8536 } else { 8537 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE) 8538 update_link = true; 8539 if (link_info->advertising != link_info->auto_link_speeds) 8540 update_link = true; 8541 } 8542 8543 /* The last close may have shutdown the link, so need to call 8544 * PHY_CFG to bring it back up. 8545 */ 8546 if (!netif_carrier_ok(bp->dev)) 8547 update_link = true; 8548 8549 if (!bnxt_eee_config_ok(bp)) 8550 update_eee = true; 8551 8552 if (update_link) 8553 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee); 8554 else if (update_pause) 8555 rc = bnxt_hwrm_set_pause(bp); 8556 if (rc) { 8557 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n", 8558 rc); 8559 return rc; 8560 } 8561 8562 return rc; 8563 } 8564 8565 /* Common routine to pre-map certain register block to different GRC window. 8566 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows 8567 * in PF and 3 windows in VF that can be customized to map in different 8568 * register blocks. 8569 */ 8570 static void bnxt_preset_reg_win(struct bnxt *bp) 8571 { 8572 if (BNXT_PF(bp)) { 8573 /* CAG registers map to GRC window #4 */ 8574 writel(BNXT_CAG_REG_BASE, 8575 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12); 8576 } 8577 } 8578 8579 static int bnxt_init_dflt_ring_mode(struct bnxt *bp); 8580 8581 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 8582 { 8583 int rc = 0; 8584 8585 bnxt_preset_reg_win(bp); 8586 netif_carrier_off(bp->dev); 8587 if (irq_re_init) { 8588 /* Reserve rings now if none were reserved at driver probe. */ 8589 rc = bnxt_init_dflt_ring_mode(bp); 8590 if (rc) { 8591 netdev_err(bp->dev, "Failed to reserve default rings at open\n"); 8592 return rc; 8593 } 8594 } 8595 rc = bnxt_reserve_rings(bp, irq_re_init); 8596 if (rc) 8597 return rc; 8598 if ((bp->flags & BNXT_FLAG_RFS) && 8599 !(bp->flags & BNXT_FLAG_USING_MSIX)) { 8600 /* disable RFS if falling back to INTA */ 8601 bp->dev->hw_features &= ~NETIF_F_NTUPLE; 8602 bp->flags &= ~BNXT_FLAG_RFS; 8603 } 8604 8605 rc = bnxt_alloc_mem(bp, irq_re_init); 8606 if (rc) { 8607 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 8608 goto open_err_free_mem; 8609 } 8610 8611 if (irq_re_init) { 8612 bnxt_init_napi(bp); 8613 rc = bnxt_request_irq(bp); 8614 if (rc) { 8615 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc); 8616 goto open_err_irq; 8617 } 8618 } 8619 8620 bnxt_enable_napi(bp); 8621 bnxt_debug_dev_init(bp); 8622 8623 rc = bnxt_init_nic(bp, irq_re_init); 8624 if (rc) { 8625 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 8626 goto open_err; 8627 } 8628 8629 if (link_re_init) { 8630 mutex_lock(&bp->link_lock); 8631 rc = bnxt_update_phy_setting(bp); 8632 mutex_unlock(&bp->link_lock); 8633 if (rc) { 8634 netdev_warn(bp->dev, "failed to update phy settings\n"); 8635 if (BNXT_SINGLE_PF(bp)) { 8636 bp->link_info.phy_retry = true; 8637 bp->link_info.phy_retry_expires = 8638 jiffies + 5 * HZ; 8639 } 8640 } 8641 } 8642 8643 if (irq_re_init) 8644 udp_tunnel_get_rx_info(bp->dev); 8645 8646 set_bit(BNXT_STATE_OPEN, &bp->state); 8647 bnxt_enable_int(bp); 8648 /* Enable TX queues */ 8649 bnxt_tx_enable(bp); 8650 mod_timer(&bp->timer, jiffies + bp->current_interval); 8651 /* Poll link status and check for SFP+ module status */ 8652 bnxt_get_port_module_status(bp); 8653 8654 /* VF-reps may need to be re-opened after the PF is re-opened */ 8655 if (BNXT_PF(bp)) 8656 bnxt_vf_reps_open(bp); 8657 return 0; 8658 8659 open_err: 8660 bnxt_debug_dev_exit(bp); 8661 bnxt_disable_napi(bp); 8662 8663 open_err_irq: 8664 bnxt_del_napi(bp); 8665 8666 open_err_free_mem: 8667 bnxt_free_skbs(bp); 8668 bnxt_free_irq(bp); 8669 bnxt_free_mem(bp, true); 8670 return rc; 8671 } 8672 8673 /* rtnl_lock held */ 8674 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 8675 { 8676 int rc = 0; 8677 8678 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init); 8679 if (rc) { 8680 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc); 8681 dev_close(bp->dev); 8682 } 8683 return rc; 8684 } 8685 8686 /* rtnl_lock held, open the NIC half way by allocating all resources, but 8687 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline 8688 * self tests. 8689 */ 8690 int bnxt_half_open_nic(struct bnxt *bp) 8691 { 8692 int rc = 0; 8693 8694 rc = bnxt_alloc_mem(bp, false); 8695 if (rc) { 8696 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); 8697 goto half_open_err; 8698 } 8699 rc = bnxt_init_nic(bp, false); 8700 if (rc) { 8701 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); 8702 goto half_open_err; 8703 } 8704 return 0; 8705 8706 half_open_err: 8707 bnxt_free_skbs(bp); 8708 bnxt_free_mem(bp, false); 8709 dev_close(bp->dev); 8710 return rc; 8711 } 8712 8713 /* rtnl_lock held, this call can only be made after a previous successful 8714 * call to bnxt_half_open_nic(). 8715 */ 8716 void bnxt_half_close_nic(struct bnxt *bp) 8717 { 8718 bnxt_hwrm_resource_free(bp, false, false); 8719 bnxt_free_skbs(bp); 8720 bnxt_free_mem(bp, false); 8721 } 8722 8723 static int bnxt_open(struct net_device *dev) 8724 { 8725 struct bnxt *bp = netdev_priv(dev); 8726 int rc; 8727 8728 bnxt_hwrm_if_change(bp, true); 8729 rc = __bnxt_open_nic(bp, true, true); 8730 if (rc) 8731 bnxt_hwrm_if_change(bp, false); 8732 8733 bnxt_hwmon_open(bp); 8734 8735 return rc; 8736 } 8737 8738 static bool bnxt_drv_busy(struct bnxt *bp) 8739 { 8740 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) || 8741 test_bit(BNXT_STATE_READ_STATS, &bp->state)); 8742 } 8743 8744 static void bnxt_get_ring_stats(struct bnxt *bp, 8745 struct rtnl_link_stats64 *stats); 8746 8747 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init, 8748 bool link_re_init) 8749 { 8750 /* Close the VF-reps before closing PF */ 8751 if (BNXT_PF(bp)) 8752 bnxt_vf_reps_close(bp); 8753 8754 /* Change device state to avoid TX queue wake up's */ 8755 bnxt_tx_disable(bp); 8756 8757 clear_bit(BNXT_STATE_OPEN, &bp->state); 8758 smp_mb__after_atomic(); 8759 while (bnxt_drv_busy(bp)) 8760 msleep(20); 8761 8762 /* Flush rings and and disable interrupts */ 8763 bnxt_shutdown_nic(bp, irq_re_init); 8764 8765 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */ 8766 8767 bnxt_debug_dev_exit(bp); 8768 bnxt_disable_napi(bp); 8769 del_timer_sync(&bp->timer); 8770 bnxt_free_skbs(bp); 8771 8772 /* Save ring stats before shutdown */ 8773 if (bp->bnapi) 8774 bnxt_get_ring_stats(bp, &bp->net_stats_prev); 8775 if (irq_re_init) { 8776 bnxt_free_irq(bp); 8777 bnxt_del_napi(bp); 8778 } 8779 bnxt_free_mem(bp, irq_re_init); 8780 } 8781 8782 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 8783 { 8784 int rc = 0; 8785 8786 #ifdef CONFIG_BNXT_SRIOV 8787 if (bp->sriov_cfg) { 8788 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait, 8789 !bp->sriov_cfg, 8790 BNXT_SRIOV_CFG_WAIT_TMO); 8791 if (rc) 8792 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n"); 8793 } 8794 #endif 8795 __bnxt_close_nic(bp, irq_re_init, link_re_init); 8796 return rc; 8797 } 8798 8799 static int bnxt_close(struct net_device *dev) 8800 { 8801 struct bnxt *bp = netdev_priv(dev); 8802 8803 bnxt_hwmon_close(bp); 8804 bnxt_close_nic(bp, true, true); 8805 bnxt_hwrm_shutdown_link(bp); 8806 bnxt_hwrm_if_change(bp, false); 8807 return 0; 8808 } 8809 8810 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg, 8811 u16 *val) 8812 { 8813 struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr; 8814 struct hwrm_port_phy_mdio_read_input req = {0}; 8815 int rc; 8816 8817 if (bp->hwrm_spec_code < 0x10a00) 8818 return -EOPNOTSUPP; 8819 8820 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1); 8821 req.port_id = cpu_to_le16(bp->pf.port_id); 8822 req.phy_addr = phy_addr; 8823 req.reg_addr = cpu_to_le16(reg & 0x1f); 8824 if (mdio_phy_id_is_c45(phy_addr)) { 8825 req.cl45_mdio = 1; 8826 req.phy_addr = mdio_phy_id_prtad(phy_addr); 8827 req.dev_addr = mdio_phy_id_devad(phy_addr); 8828 req.reg_addr = cpu_to_le16(reg); 8829 } 8830 8831 mutex_lock(&bp->hwrm_cmd_lock); 8832 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8833 if (!rc) 8834 *val = le16_to_cpu(resp->reg_data); 8835 mutex_unlock(&bp->hwrm_cmd_lock); 8836 return rc; 8837 } 8838 8839 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg, 8840 u16 val) 8841 { 8842 struct hwrm_port_phy_mdio_write_input req = {0}; 8843 8844 if (bp->hwrm_spec_code < 0x10a00) 8845 return -EOPNOTSUPP; 8846 8847 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1); 8848 req.port_id = cpu_to_le16(bp->pf.port_id); 8849 req.phy_addr = phy_addr; 8850 req.reg_addr = cpu_to_le16(reg & 0x1f); 8851 if (mdio_phy_id_is_c45(phy_addr)) { 8852 req.cl45_mdio = 1; 8853 req.phy_addr = mdio_phy_id_prtad(phy_addr); 8854 req.dev_addr = mdio_phy_id_devad(phy_addr); 8855 req.reg_addr = cpu_to_le16(reg); 8856 } 8857 req.reg_data = cpu_to_le16(val); 8858 8859 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 8860 } 8861 8862 /* rtnl_lock held */ 8863 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 8864 { 8865 struct mii_ioctl_data *mdio = if_mii(ifr); 8866 struct bnxt *bp = netdev_priv(dev); 8867 int rc; 8868 8869 switch (cmd) { 8870 case SIOCGMIIPHY: 8871 mdio->phy_id = bp->link_info.phy_addr; 8872 8873 /* fallthru */ 8874 case SIOCGMIIREG: { 8875 u16 mii_regval = 0; 8876 8877 if (!netif_running(dev)) 8878 return -EAGAIN; 8879 8880 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num, 8881 &mii_regval); 8882 mdio->val_out = mii_regval; 8883 return rc; 8884 } 8885 8886 case SIOCSMIIREG: 8887 if (!netif_running(dev)) 8888 return -EAGAIN; 8889 8890 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num, 8891 mdio->val_in); 8892 8893 default: 8894 /* do nothing */ 8895 break; 8896 } 8897 return -EOPNOTSUPP; 8898 } 8899 8900 static void bnxt_get_ring_stats(struct bnxt *bp, 8901 struct rtnl_link_stats64 *stats) 8902 { 8903 int i; 8904 8905 8906 for (i = 0; i < bp->cp_nr_rings; i++) { 8907 struct bnxt_napi *bnapi = bp->bnapi[i]; 8908 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 8909 struct ctx_hw_stats *hw_stats = cpr->hw_stats; 8910 8911 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts); 8912 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts); 8913 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts); 8914 8915 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts); 8916 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts); 8917 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts); 8918 8919 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes); 8920 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes); 8921 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes); 8922 8923 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes); 8924 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes); 8925 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes); 8926 8927 stats->rx_missed_errors += 8928 le64_to_cpu(hw_stats->rx_discard_pkts); 8929 8930 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts); 8931 8932 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts); 8933 } 8934 } 8935 8936 static void bnxt_add_prev_stats(struct bnxt *bp, 8937 struct rtnl_link_stats64 *stats) 8938 { 8939 struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev; 8940 8941 stats->rx_packets += prev_stats->rx_packets; 8942 stats->tx_packets += prev_stats->tx_packets; 8943 stats->rx_bytes += prev_stats->rx_bytes; 8944 stats->tx_bytes += prev_stats->tx_bytes; 8945 stats->rx_missed_errors += prev_stats->rx_missed_errors; 8946 stats->multicast += prev_stats->multicast; 8947 stats->tx_dropped += prev_stats->tx_dropped; 8948 } 8949 8950 static void 8951 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 8952 { 8953 struct bnxt *bp = netdev_priv(dev); 8954 8955 set_bit(BNXT_STATE_READ_STATS, &bp->state); 8956 /* Make sure bnxt_close_nic() sees that we are reading stats before 8957 * we check the BNXT_STATE_OPEN flag. 8958 */ 8959 smp_mb__after_atomic(); 8960 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 8961 clear_bit(BNXT_STATE_READ_STATS, &bp->state); 8962 *stats = bp->net_stats_prev; 8963 return; 8964 } 8965 8966 bnxt_get_ring_stats(bp, stats); 8967 bnxt_add_prev_stats(bp, stats); 8968 8969 if (bp->flags & BNXT_FLAG_PORT_STATS) { 8970 struct rx_port_stats *rx = bp->hw_rx_port_stats; 8971 struct tx_port_stats *tx = bp->hw_tx_port_stats; 8972 8973 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames); 8974 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames); 8975 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) + 8976 le64_to_cpu(rx->rx_ovrsz_frames) + 8977 le64_to_cpu(rx->rx_runt_frames); 8978 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) + 8979 le64_to_cpu(rx->rx_jbr_frames); 8980 stats->collisions = le64_to_cpu(tx->tx_total_collisions); 8981 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns); 8982 stats->tx_errors = le64_to_cpu(tx->tx_err); 8983 } 8984 clear_bit(BNXT_STATE_READ_STATS, &bp->state); 8985 } 8986 8987 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask) 8988 { 8989 struct net_device *dev = bp->dev; 8990 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 8991 struct netdev_hw_addr *ha; 8992 u8 *haddr; 8993 int mc_count = 0; 8994 bool update = false; 8995 int off = 0; 8996 8997 netdev_for_each_mc_addr(ha, dev) { 8998 if (mc_count >= BNXT_MAX_MC_ADDRS) { 8999 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 9000 vnic->mc_list_count = 0; 9001 return false; 9002 } 9003 haddr = ha->addr; 9004 if (!ether_addr_equal(haddr, vnic->mc_list + off)) { 9005 memcpy(vnic->mc_list + off, haddr, ETH_ALEN); 9006 update = true; 9007 } 9008 off += ETH_ALEN; 9009 mc_count++; 9010 } 9011 if (mc_count) 9012 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST; 9013 9014 if (mc_count != vnic->mc_list_count) { 9015 vnic->mc_list_count = mc_count; 9016 update = true; 9017 } 9018 return update; 9019 } 9020 9021 static bool bnxt_uc_list_updated(struct bnxt *bp) 9022 { 9023 struct net_device *dev = bp->dev; 9024 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 9025 struct netdev_hw_addr *ha; 9026 int off = 0; 9027 9028 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1)) 9029 return true; 9030 9031 netdev_for_each_uc_addr(ha, dev) { 9032 if (!ether_addr_equal(ha->addr, vnic->uc_list + off)) 9033 return true; 9034 9035 off += ETH_ALEN; 9036 } 9037 return false; 9038 } 9039 9040 static void bnxt_set_rx_mode(struct net_device *dev) 9041 { 9042 struct bnxt *bp = netdev_priv(dev); 9043 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 9044 u32 mask = vnic->rx_mask; 9045 bool mc_update = false; 9046 bool uc_update; 9047 9048 if (!netif_running(dev)) 9049 return; 9050 9051 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS | 9052 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST | 9053 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST | 9054 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST); 9055 9056 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp)) 9057 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 9058 9059 uc_update = bnxt_uc_list_updated(bp); 9060 9061 if (dev->flags & IFF_BROADCAST) 9062 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; 9063 if (dev->flags & IFF_ALLMULTI) { 9064 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 9065 vnic->mc_list_count = 0; 9066 } else { 9067 mc_update = bnxt_mc_list_updated(bp, &mask); 9068 } 9069 9070 if (mask != vnic->rx_mask || uc_update || mc_update) { 9071 vnic->rx_mask = mask; 9072 9073 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event); 9074 bnxt_queue_sp_work(bp); 9075 } 9076 } 9077 9078 static int bnxt_cfg_rx_mode(struct bnxt *bp) 9079 { 9080 struct net_device *dev = bp->dev; 9081 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 9082 struct netdev_hw_addr *ha; 9083 int i, off = 0, rc; 9084 bool uc_update; 9085 9086 netif_addr_lock_bh(dev); 9087 uc_update = bnxt_uc_list_updated(bp); 9088 netif_addr_unlock_bh(dev); 9089 9090 if (!uc_update) 9091 goto skip_uc; 9092 9093 mutex_lock(&bp->hwrm_cmd_lock); 9094 for (i = 1; i < vnic->uc_filter_count; i++) { 9095 struct hwrm_cfa_l2_filter_free_input req = {0}; 9096 9097 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1, 9098 -1); 9099 9100 req.l2_filter_id = vnic->fw_l2_filter_id[i]; 9101 9102 rc = _hwrm_send_message(bp, &req, sizeof(req), 9103 HWRM_CMD_TIMEOUT); 9104 } 9105 mutex_unlock(&bp->hwrm_cmd_lock); 9106 9107 vnic->uc_filter_count = 1; 9108 9109 netif_addr_lock_bh(dev); 9110 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) { 9111 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; 9112 } else { 9113 netdev_for_each_uc_addr(ha, dev) { 9114 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN); 9115 off += ETH_ALEN; 9116 vnic->uc_filter_count++; 9117 } 9118 } 9119 netif_addr_unlock_bh(dev); 9120 9121 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) { 9122 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off); 9123 if (rc) { 9124 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", 9125 rc); 9126 vnic->uc_filter_count = i; 9127 return rc; 9128 } 9129 } 9130 9131 skip_uc: 9132 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); 9133 if (rc && vnic->mc_list_count) { 9134 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n", 9135 rc); 9136 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; 9137 vnic->mc_list_count = 0; 9138 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); 9139 } 9140 if (rc) 9141 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n", 9142 rc); 9143 9144 return rc; 9145 } 9146 9147 static bool bnxt_can_reserve_rings(struct bnxt *bp) 9148 { 9149 #ifdef CONFIG_BNXT_SRIOV 9150 if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) { 9151 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 9152 9153 /* No minimum rings were provisioned by the PF. Don't 9154 * reserve rings by default when device is down. 9155 */ 9156 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings) 9157 return true; 9158 9159 if (!netif_running(bp->dev)) 9160 return false; 9161 } 9162 #endif 9163 return true; 9164 } 9165 9166 /* If the chip and firmware supports RFS */ 9167 static bool bnxt_rfs_supported(struct bnxt *bp) 9168 { 9169 if (bp->flags & BNXT_FLAG_CHIP_P5) { 9170 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX) 9171 return true; 9172 return false; 9173 } 9174 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) 9175 return true; 9176 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 9177 return true; 9178 return false; 9179 } 9180 9181 /* If runtime conditions support RFS */ 9182 static bool bnxt_rfs_capable(struct bnxt *bp) 9183 { 9184 #ifdef CONFIG_RFS_ACCEL 9185 int vnics, max_vnics, max_rss_ctxs; 9186 9187 if (bp->flags & BNXT_FLAG_CHIP_P5) 9188 return bnxt_rfs_supported(bp); 9189 if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp)) 9190 return false; 9191 9192 vnics = 1 + bp->rx_nr_rings; 9193 max_vnics = bnxt_get_max_func_vnics(bp); 9194 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp); 9195 9196 /* RSS contexts not a limiting factor */ 9197 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP) 9198 max_rss_ctxs = max_vnics; 9199 if (vnics > max_vnics || vnics > max_rss_ctxs) { 9200 if (bp->rx_nr_rings > 1) 9201 netdev_warn(bp->dev, 9202 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n", 9203 min(max_rss_ctxs - 1, max_vnics - 1)); 9204 return false; 9205 } 9206 9207 if (!BNXT_NEW_RM(bp)) 9208 return true; 9209 9210 if (vnics == bp->hw_resc.resv_vnics) 9211 return true; 9212 9213 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics); 9214 if (vnics <= bp->hw_resc.resv_vnics) 9215 return true; 9216 9217 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n"); 9218 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1); 9219 return false; 9220 #else 9221 return false; 9222 #endif 9223 } 9224 9225 static netdev_features_t bnxt_fix_features(struct net_device *dev, 9226 netdev_features_t features) 9227 { 9228 struct bnxt *bp = netdev_priv(dev); 9229 9230 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp)) 9231 features &= ~NETIF_F_NTUPLE; 9232 9233 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 9234 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 9235 9236 if (!(features & NETIF_F_GRO)) 9237 features &= ~NETIF_F_GRO_HW; 9238 9239 if (features & NETIF_F_GRO_HW) 9240 features &= ~NETIF_F_LRO; 9241 9242 /* Both CTAG and STAG VLAN accelaration on the RX side have to be 9243 * turned on or off together. 9244 */ 9245 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) != 9246 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) { 9247 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX) 9248 features &= ~(NETIF_F_HW_VLAN_CTAG_RX | 9249 NETIF_F_HW_VLAN_STAG_RX); 9250 else 9251 features |= NETIF_F_HW_VLAN_CTAG_RX | 9252 NETIF_F_HW_VLAN_STAG_RX; 9253 } 9254 #ifdef CONFIG_BNXT_SRIOV 9255 if (BNXT_VF(bp)) { 9256 if (bp->vf.vlan) { 9257 features &= ~(NETIF_F_HW_VLAN_CTAG_RX | 9258 NETIF_F_HW_VLAN_STAG_RX); 9259 } 9260 } 9261 #endif 9262 return features; 9263 } 9264 9265 static int bnxt_set_features(struct net_device *dev, netdev_features_t features) 9266 { 9267 struct bnxt *bp = netdev_priv(dev); 9268 u32 flags = bp->flags; 9269 u32 changes; 9270 int rc = 0; 9271 bool re_init = false; 9272 bool update_tpa = false; 9273 9274 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS; 9275 if (features & NETIF_F_GRO_HW) 9276 flags |= BNXT_FLAG_GRO; 9277 else if (features & NETIF_F_LRO) 9278 flags |= BNXT_FLAG_LRO; 9279 9280 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 9281 flags &= ~BNXT_FLAG_TPA; 9282 9283 if (features & NETIF_F_HW_VLAN_CTAG_RX) 9284 flags |= BNXT_FLAG_STRIP_VLAN; 9285 9286 if (features & NETIF_F_NTUPLE) 9287 flags |= BNXT_FLAG_RFS; 9288 9289 changes = flags ^ bp->flags; 9290 if (changes & BNXT_FLAG_TPA) { 9291 update_tpa = true; 9292 if ((bp->flags & BNXT_FLAG_TPA) == 0 || 9293 (flags & BNXT_FLAG_TPA) == 0) 9294 re_init = true; 9295 } 9296 9297 if (changes & ~BNXT_FLAG_TPA) 9298 re_init = true; 9299 9300 if (flags != bp->flags) { 9301 u32 old_flags = bp->flags; 9302 9303 bp->flags = flags; 9304 9305 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 9306 if (update_tpa) 9307 bnxt_set_ring_params(bp); 9308 return rc; 9309 } 9310 9311 if (re_init) { 9312 bnxt_close_nic(bp, false, false); 9313 if (update_tpa) 9314 bnxt_set_ring_params(bp); 9315 9316 return bnxt_open_nic(bp, false, false); 9317 } 9318 if (update_tpa) { 9319 rc = bnxt_set_tpa(bp, 9320 (flags & BNXT_FLAG_TPA) ? 9321 true : false); 9322 if (rc) 9323 bp->flags = old_flags; 9324 } 9325 } 9326 return rc; 9327 } 9328 9329 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type, 9330 u32 ring_id, u32 *prod, u32 *cons) 9331 { 9332 struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr; 9333 struct hwrm_dbg_ring_info_get_input req = {0}; 9334 int rc; 9335 9336 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1); 9337 req.ring_type = ring_type; 9338 req.fw_ring_id = cpu_to_le32(ring_id); 9339 mutex_lock(&bp->hwrm_cmd_lock); 9340 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 9341 if (!rc) { 9342 *prod = le32_to_cpu(resp->producer_index); 9343 *cons = le32_to_cpu(resp->consumer_index); 9344 } 9345 mutex_unlock(&bp->hwrm_cmd_lock); 9346 return rc; 9347 } 9348 9349 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi) 9350 { 9351 struct bnxt_tx_ring_info *txr = bnapi->tx_ring; 9352 int i = bnapi->index; 9353 9354 if (!txr) 9355 return; 9356 9357 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n", 9358 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod, 9359 txr->tx_cons); 9360 } 9361 9362 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi) 9363 { 9364 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; 9365 int i = bnapi->index; 9366 9367 if (!rxr) 9368 return; 9369 9370 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n", 9371 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod, 9372 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod, 9373 rxr->rx_sw_agg_prod); 9374 } 9375 9376 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi) 9377 { 9378 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 9379 int i = bnapi->index; 9380 9381 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n", 9382 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons); 9383 } 9384 9385 static void bnxt_dbg_dump_states(struct bnxt *bp) 9386 { 9387 int i; 9388 struct bnxt_napi *bnapi; 9389 9390 for (i = 0; i < bp->cp_nr_rings; i++) { 9391 bnapi = bp->bnapi[i]; 9392 if (netif_msg_drv(bp)) { 9393 bnxt_dump_tx_sw_state(bnapi); 9394 bnxt_dump_rx_sw_state(bnapi); 9395 bnxt_dump_cp_sw_state(bnapi); 9396 } 9397 } 9398 } 9399 9400 static void bnxt_reset_task(struct bnxt *bp, bool silent) 9401 { 9402 if (!silent) 9403 bnxt_dbg_dump_states(bp); 9404 if (netif_running(bp->dev)) { 9405 int rc; 9406 9407 if (!silent) 9408 bnxt_ulp_stop(bp); 9409 bnxt_close_nic(bp, false, false); 9410 rc = bnxt_open_nic(bp, false, false); 9411 if (!silent && !rc) 9412 bnxt_ulp_start(bp); 9413 } 9414 } 9415 9416 static void bnxt_tx_timeout(struct net_device *dev) 9417 { 9418 struct bnxt *bp = netdev_priv(dev); 9419 9420 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n"); 9421 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); 9422 bnxt_queue_sp_work(bp); 9423 } 9424 9425 static void bnxt_timer(struct timer_list *t) 9426 { 9427 struct bnxt *bp = from_timer(bp, t, timer); 9428 struct net_device *dev = bp->dev; 9429 9430 if (!netif_running(dev)) 9431 return; 9432 9433 if (atomic_read(&bp->intr_sem) != 0) 9434 goto bnxt_restart_timer; 9435 9436 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) && 9437 bp->stats_coal_ticks) { 9438 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event); 9439 bnxt_queue_sp_work(bp); 9440 } 9441 9442 if (bnxt_tc_flower_enabled(bp)) { 9443 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event); 9444 bnxt_queue_sp_work(bp); 9445 } 9446 9447 if (bp->link_info.phy_retry) { 9448 if (time_after(jiffies, bp->link_info.phy_retry_expires)) { 9449 bp->link_info.phy_retry = 0; 9450 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n"); 9451 } else { 9452 set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event); 9453 bnxt_queue_sp_work(bp); 9454 } 9455 } 9456 9457 if ((bp->flags & BNXT_FLAG_CHIP_P5) && netif_carrier_ok(dev)) { 9458 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event); 9459 bnxt_queue_sp_work(bp); 9460 } 9461 bnxt_restart_timer: 9462 mod_timer(&bp->timer, jiffies + bp->current_interval); 9463 } 9464 9465 static void bnxt_rtnl_lock_sp(struct bnxt *bp) 9466 { 9467 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK 9468 * set. If the device is being closed, bnxt_close() may be holding 9469 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we 9470 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl(). 9471 */ 9472 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 9473 rtnl_lock(); 9474 } 9475 9476 static void bnxt_rtnl_unlock_sp(struct bnxt *bp) 9477 { 9478 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 9479 rtnl_unlock(); 9480 } 9481 9482 /* Only called from bnxt_sp_task() */ 9483 static void bnxt_reset(struct bnxt *bp, bool silent) 9484 { 9485 bnxt_rtnl_lock_sp(bp); 9486 if (test_bit(BNXT_STATE_OPEN, &bp->state)) 9487 bnxt_reset_task(bp, silent); 9488 bnxt_rtnl_unlock_sp(bp); 9489 } 9490 9491 static void bnxt_chk_missed_irq(struct bnxt *bp) 9492 { 9493 int i; 9494 9495 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 9496 return; 9497 9498 for (i = 0; i < bp->cp_nr_rings; i++) { 9499 struct bnxt_napi *bnapi = bp->bnapi[i]; 9500 struct bnxt_cp_ring_info *cpr; 9501 u32 fw_ring_id; 9502 int j; 9503 9504 if (!bnapi) 9505 continue; 9506 9507 cpr = &bnapi->cp_ring; 9508 for (j = 0; j < 2; j++) { 9509 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j]; 9510 u32 val[2]; 9511 9512 if (!cpr2 || cpr2->has_more_work || 9513 !bnxt_has_work(bp, cpr2)) 9514 continue; 9515 9516 if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) { 9517 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons; 9518 continue; 9519 } 9520 fw_ring_id = cpr2->cp_ring_struct.fw_ring_id; 9521 bnxt_dbg_hwrm_ring_info_get(bp, 9522 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL, 9523 fw_ring_id, &val[0], &val[1]); 9524 cpr->missed_irqs++; 9525 } 9526 } 9527 } 9528 9529 static void bnxt_cfg_ntp_filters(struct bnxt *); 9530 9531 static void bnxt_sp_task(struct work_struct *work) 9532 { 9533 struct bnxt *bp = container_of(work, struct bnxt, sp_task); 9534 9535 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 9536 smp_mb__after_atomic(); 9537 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 9538 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 9539 return; 9540 } 9541 9542 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event)) 9543 bnxt_cfg_rx_mode(bp); 9544 9545 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event)) 9546 bnxt_cfg_ntp_filters(bp); 9547 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event)) 9548 bnxt_hwrm_exec_fwd_req(bp); 9549 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) { 9550 bnxt_hwrm_tunnel_dst_port_alloc( 9551 bp, bp->vxlan_port, 9552 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 9553 } 9554 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) { 9555 bnxt_hwrm_tunnel_dst_port_free( 9556 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); 9557 } 9558 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) { 9559 bnxt_hwrm_tunnel_dst_port_alloc( 9560 bp, bp->nge_port, 9561 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 9562 } 9563 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) { 9564 bnxt_hwrm_tunnel_dst_port_free( 9565 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); 9566 } 9567 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) { 9568 bnxt_hwrm_port_qstats(bp); 9569 bnxt_hwrm_port_qstats_ext(bp); 9570 bnxt_hwrm_pcie_qstats(bp); 9571 } 9572 9573 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) { 9574 int rc; 9575 9576 mutex_lock(&bp->link_lock); 9577 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, 9578 &bp->sp_event)) 9579 bnxt_hwrm_phy_qcaps(bp); 9580 9581 rc = bnxt_update_link(bp, true); 9582 mutex_unlock(&bp->link_lock); 9583 if (rc) 9584 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n", 9585 rc); 9586 } 9587 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) { 9588 int rc; 9589 9590 mutex_lock(&bp->link_lock); 9591 rc = bnxt_update_phy_setting(bp); 9592 mutex_unlock(&bp->link_lock); 9593 if (rc) { 9594 netdev_warn(bp->dev, "update phy settings retry failed\n"); 9595 } else { 9596 bp->link_info.phy_retry = false; 9597 netdev_info(bp->dev, "update phy settings retry succeeded\n"); 9598 } 9599 } 9600 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) { 9601 mutex_lock(&bp->link_lock); 9602 bnxt_get_port_module_status(bp); 9603 mutex_unlock(&bp->link_lock); 9604 } 9605 9606 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event)) 9607 bnxt_tc_flow_stats_work(bp); 9608 9609 if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event)) 9610 bnxt_chk_missed_irq(bp); 9611 9612 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They 9613 * must be the last functions to be called before exiting. 9614 */ 9615 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) 9616 bnxt_reset(bp, false); 9617 9618 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event)) 9619 bnxt_reset(bp, true); 9620 9621 smp_mb__before_atomic(); 9622 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 9623 } 9624 9625 /* Under rtnl_lock */ 9626 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs, 9627 int tx_xdp) 9628 { 9629 int max_rx, max_tx, tx_sets = 1; 9630 int tx_rings_needed, stats; 9631 int rx_rings = rx; 9632 int cp, vnics, rc; 9633 9634 if (tcs) 9635 tx_sets = tcs; 9636 9637 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh); 9638 if (rc) 9639 return rc; 9640 9641 if (max_rx < rx) 9642 return -ENOMEM; 9643 9644 tx_rings_needed = tx * tx_sets + tx_xdp; 9645 if (max_tx < tx_rings_needed) 9646 return -ENOMEM; 9647 9648 vnics = 1; 9649 if (bp->flags & BNXT_FLAG_RFS) 9650 vnics += rx_rings; 9651 9652 if (bp->flags & BNXT_FLAG_AGG_RINGS) 9653 rx_rings <<= 1; 9654 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx; 9655 stats = cp; 9656 if (BNXT_NEW_RM(bp)) { 9657 cp += bnxt_get_ulp_msix_num(bp); 9658 stats += bnxt_get_ulp_stat_ctxs(bp); 9659 } 9660 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp, 9661 stats, vnics); 9662 } 9663 9664 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev) 9665 { 9666 if (bp->bar2) { 9667 pci_iounmap(pdev, bp->bar2); 9668 bp->bar2 = NULL; 9669 } 9670 9671 if (bp->bar1) { 9672 pci_iounmap(pdev, bp->bar1); 9673 bp->bar1 = NULL; 9674 } 9675 9676 if (bp->bar0) { 9677 pci_iounmap(pdev, bp->bar0); 9678 bp->bar0 = NULL; 9679 } 9680 } 9681 9682 static void bnxt_cleanup_pci(struct bnxt *bp) 9683 { 9684 bnxt_unmap_bars(bp, bp->pdev); 9685 pci_release_regions(bp->pdev); 9686 pci_disable_device(bp->pdev); 9687 } 9688 9689 static void bnxt_init_dflt_coal(struct bnxt *bp) 9690 { 9691 struct bnxt_coal *coal; 9692 9693 /* Tick values in micro seconds. 9694 * 1 coal_buf x bufs_per_record = 1 completion record. 9695 */ 9696 coal = &bp->rx_coal; 9697 coal->coal_ticks = 10; 9698 coal->coal_bufs = 30; 9699 coal->coal_ticks_irq = 1; 9700 coal->coal_bufs_irq = 2; 9701 coal->idle_thresh = 50; 9702 coal->bufs_per_record = 2; 9703 coal->budget = 64; /* NAPI budget */ 9704 9705 coal = &bp->tx_coal; 9706 coal->coal_ticks = 28; 9707 coal->coal_bufs = 30; 9708 coal->coal_ticks_irq = 2; 9709 coal->coal_bufs_irq = 2; 9710 coal->bufs_per_record = 1; 9711 9712 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS; 9713 } 9714 9715 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev) 9716 { 9717 int rc; 9718 struct bnxt *bp = netdev_priv(dev); 9719 9720 SET_NETDEV_DEV(dev, &pdev->dev); 9721 9722 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 9723 rc = pci_enable_device(pdev); 9724 if (rc) { 9725 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 9726 goto init_err; 9727 } 9728 9729 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 9730 dev_err(&pdev->dev, 9731 "Cannot find PCI device base address, aborting\n"); 9732 rc = -ENODEV; 9733 goto init_err_disable; 9734 } 9735 9736 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 9737 if (rc) { 9738 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); 9739 goto init_err_disable; 9740 } 9741 9742 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 && 9743 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) { 9744 dev_err(&pdev->dev, "System does not support DMA, aborting\n"); 9745 goto init_err_disable; 9746 } 9747 9748 pci_set_master(pdev); 9749 9750 bp->dev = dev; 9751 bp->pdev = pdev; 9752 9753 bp->bar0 = pci_ioremap_bar(pdev, 0); 9754 if (!bp->bar0) { 9755 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); 9756 rc = -ENOMEM; 9757 goto init_err_release; 9758 } 9759 9760 bp->bar1 = pci_ioremap_bar(pdev, 2); 9761 if (!bp->bar1) { 9762 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n"); 9763 rc = -ENOMEM; 9764 goto init_err_release; 9765 } 9766 9767 bp->bar2 = pci_ioremap_bar(pdev, 4); 9768 if (!bp->bar2) { 9769 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n"); 9770 rc = -ENOMEM; 9771 goto init_err_release; 9772 } 9773 9774 pci_enable_pcie_error_reporting(pdev); 9775 9776 INIT_WORK(&bp->sp_task, bnxt_sp_task); 9777 9778 spin_lock_init(&bp->ntp_fltr_lock); 9779 #if BITS_PER_LONG == 32 9780 spin_lock_init(&bp->db_lock); 9781 #endif 9782 9783 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE; 9784 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE; 9785 9786 bnxt_init_dflt_coal(bp); 9787 9788 timer_setup(&bp->timer, bnxt_timer, 0); 9789 bp->current_interval = BNXT_TIMER_INTERVAL; 9790 9791 clear_bit(BNXT_STATE_OPEN, &bp->state); 9792 return 0; 9793 9794 init_err_release: 9795 bnxt_unmap_bars(bp, pdev); 9796 pci_release_regions(pdev); 9797 9798 init_err_disable: 9799 pci_disable_device(pdev); 9800 9801 init_err: 9802 return rc; 9803 } 9804 9805 /* rtnl_lock held */ 9806 static int bnxt_change_mac_addr(struct net_device *dev, void *p) 9807 { 9808 struct sockaddr *addr = p; 9809 struct bnxt *bp = netdev_priv(dev); 9810 int rc = 0; 9811 9812 if (!is_valid_ether_addr(addr->sa_data)) 9813 return -EADDRNOTAVAIL; 9814 9815 if (ether_addr_equal(addr->sa_data, dev->dev_addr)) 9816 return 0; 9817 9818 rc = bnxt_approve_mac(bp, addr->sa_data, true); 9819 if (rc) 9820 return rc; 9821 9822 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 9823 if (netif_running(dev)) { 9824 bnxt_close_nic(bp, false, false); 9825 rc = bnxt_open_nic(bp, false, false); 9826 } 9827 9828 return rc; 9829 } 9830 9831 /* rtnl_lock held */ 9832 static int bnxt_change_mtu(struct net_device *dev, int new_mtu) 9833 { 9834 struct bnxt *bp = netdev_priv(dev); 9835 9836 if (netif_running(dev)) 9837 bnxt_close_nic(bp, false, false); 9838 9839 dev->mtu = new_mtu; 9840 bnxt_set_ring_params(bp); 9841 9842 if (netif_running(dev)) 9843 return bnxt_open_nic(bp, false, false); 9844 9845 return 0; 9846 } 9847 9848 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc) 9849 { 9850 struct bnxt *bp = netdev_priv(dev); 9851 bool sh = false; 9852 int rc; 9853 9854 if (tc > bp->max_tc) { 9855 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n", 9856 tc, bp->max_tc); 9857 return -EINVAL; 9858 } 9859 9860 if (netdev_get_num_tc(dev) == tc) 9861 return 0; 9862 9863 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 9864 sh = true; 9865 9866 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings, 9867 sh, tc, bp->tx_nr_rings_xdp); 9868 if (rc) 9869 return rc; 9870 9871 /* Needs to close the device and do hw resource re-allocations */ 9872 if (netif_running(bp->dev)) 9873 bnxt_close_nic(bp, true, false); 9874 9875 if (tc) { 9876 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc; 9877 netdev_set_num_tc(dev, tc); 9878 } else { 9879 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 9880 netdev_reset_tc(dev); 9881 } 9882 bp->tx_nr_rings += bp->tx_nr_rings_xdp; 9883 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 9884 bp->tx_nr_rings + bp->rx_nr_rings; 9885 9886 if (netif_running(bp->dev)) 9887 return bnxt_open_nic(bp, true, false); 9888 9889 return 0; 9890 } 9891 9892 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 9893 void *cb_priv) 9894 { 9895 struct bnxt *bp = cb_priv; 9896 9897 if (!bnxt_tc_flower_enabled(bp) || 9898 !tc_cls_can_offload_and_chain0(bp->dev, type_data)) 9899 return -EOPNOTSUPP; 9900 9901 switch (type) { 9902 case TC_SETUP_CLSFLOWER: 9903 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data); 9904 default: 9905 return -EOPNOTSUPP; 9906 } 9907 } 9908 9909 static int bnxt_setup_tc_block(struct net_device *dev, 9910 struct tc_block_offload *f) 9911 { 9912 struct bnxt *bp = netdev_priv(dev); 9913 9914 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 9915 return -EOPNOTSUPP; 9916 9917 switch (f->command) { 9918 case TC_BLOCK_BIND: 9919 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb, 9920 bp, bp, f->extack); 9921 case TC_BLOCK_UNBIND: 9922 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp); 9923 return 0; 9924 default: 9925 return -EOPNOTSUPP; 9926 } 9927 } 9928 9929 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type, 9930 void *type_data) 9931 { 9932 switch (type) { 9933 case TC_SETUP_BLOCK: 9934 return bnxt_setup_tc_block(dev, type_data); 9935 case TC_SETUP_QDISC_MQPRIO: { 9936 struct tc_mqprio_qopt *mqprio = type_data; 9937 9938 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 9939 9940 return bnxt_setup_mq_tc(dev, mqprio->num_tc); 9941 } 9942 default: 9943 return -EOPNOTSUPP; 9944 } 9945 } 9946 9947 #ifdef CONFIG_RFS_ACCEL 9948 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1, 9949 struct bnxt_ntuple_filter *f2) 9950 { 9951 struct flow_keys *keys1 = &f1->fkeys; 9952 struct flow_keys *keys2 = &f2->fkeys; 9953 9954 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src && 9955 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst && 9956 keys1->ports.ports == keys2->ports.ports && 9957 keys1->basic.ip_proto == keys2->basic.ip_proto && 9958 keys1->basic.n_proto == keys2->basic.n_proto && 9959 keys1->control.flags == keys2->control.flags && 9960 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) && 9961 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr)) 9962 return true; 9963 9964 return false; 9965 } 9966 9967 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 9968 u16 rxq_index, u32 flow_id) 9969 { 9970 struct bnxt *bp = netdev_priv(dev); 9971 struct bnxt_ntuple_filter *fltr, *new_fltr; 9972 struct flow_keys *fkeys; 9973 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb); 9974 int rc = 0, idx, bit_id, l2_idx = 0; 9975 struct hlist_head *head; 9976 9977 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) { 9978 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 9979 int off = 0, j; 9980 9981 netif_addr_lock_bh(dev); 9982 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) { 9983 if (ether_addr_equal(eth->h_dest, 9984 vnic->uc_list + off)) { 9985 l2_idx = j + 1; 9986 break; 9987 } 9988 } 9989 netif_addr_unlock_bh(dev); 9990 if (!l2_idx) 9991 return -EINVAL; 9992 } 9993 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC); 9994 if (!new_fltr) 9995 return -ENOMEM; 9996 9997 fkeys = &new_fltr->fkeys; 9998 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) { 9999 rc = -EPROTONOSUPPORT; 10000 goto err_free; 10001 } 10002 10003 if ((fkeys->basic.n_proto != htons(ETH_P_IP) && 10004 fkeys->basic.n_proto != htons(ETH_P_IPV6)) || 10005 ((fkeys->basic.ip_proto != IPPROTO_TCP) && 10006 (fkeys->basic.ip_proto != IPPROTO_UDP))) { 10007 rc = -EPROTONOSUPPORT; 10008 goto err_free; 10009 } 10010 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) && 10011 bp->hwrm_spec_code < 0x10601) { 10012 rc = -EPROTONOSUPPORT; 10013 goto err_free; 10014 } 10015 if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) && 10016 bp->hwrm_spec_code < 0x10601) { 10017 rc = -EPROTONOSUPPORT; 10018 goto err_free; 10019 } 10020 10021 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN); 10022 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN); 10023 10024 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK; 10025 head = &bp->ntp_fltr_hash_tbl[idx]; 10026 rcu_read_lock(); 10027 hlist_for_each_entry_rcu(fltr, head, hash) { 10028 if (bnxt_fltr_match(fltr, new_fltr)) { 10029 rcu_read_unlock(); 10030 rc = 0; 10031 goto err_free; 10032 } 10033 } 10034 rcu_read_unlock(); 10035 10036 spin_lock_bh(&bp->ntp_fltr_lock); 10037 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap, 10038 BNXT_NTP_FLTR_MAX_FLTR, 0); 10039 if (bit_id < 0) { 10040 spin_unlock_bh(&bp->ntp_fltr_lock); 10041 rc = -ENOMEM; 10042 goto err_free; 10043 } 10044 10045 new_fltr->sw_id = (u16)bit_id; 10046 new_fltr->flow_id = flow_id; 10047 new_fltr->l2_fltr_idx = l2_idx; 10048 new_fltr->rxq = rxq_index; 10049 hlist_add_head_rcu(&new_fltr->hash, head); 10050 bp->ntp_fltr_count++; 10051 spin_unlock_bh(&bp->ntp_fltr_lock); 10052 10053 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); 10054 bnxt_queue_sp_work(bp); 10055 10056 return new_fltr->sw_id; 10057 10058 err_free: 10059 kfree(new_fltr); 10060 return rc; 10061 } 10062 10063 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 10064 { 10065 int i; 10066 10067 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 10068 struct hlist_head *head; 10069 struct hlist_node *tmp; 10070 struct bnxt_ntuple_filter *fltr; 10071 int rc; 10072 10073 head = &bp->ntp_fltr_hash_tbl[i]; 10074 hlist_for_each_entry_safe(fltr, tmp, head, hash) { 10075 bool del = false; 10076 10077 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) { 10078 if (rps_may_expire_flow(bp->dev, fltr->rxq, 10079 fltr->flow_id, 10080 fltr->sw_id)) { 10081 bnxt_hwrm_cfa_ntuple_filter_free(bp, 10082 fltr); 10083 del = true; 10084 } 10085 } else { 10086 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, 10087 fltr); 10088 if (rc) 10089 del = true; 10090 else 10091 set_bit(BNXT_FLTR_VALID, &fltr->state); 10092 } 10093 10094 if (del) { 10095 spin_lock_bh(&bp->ntp_fltr_lock); 10096 hlist_del_rcu(&fltr->hash); 10097 bp->ntp_fltr_count--; 10098 spin_unlock_bh(&bp->ntp_fltr_lock); 10099 synchronize_rcu(); 10100 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap); 10101 kfree(fltr); 10102 } 10103 } 10104 } 10105 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event)) 10106 netdev_info(bp->dev, "Receive PF driver unload event!"); 10107 } 10108 10109 #else 10110 10111 static void bnxt_cfg_ntp_filters(struct bnxt *bp) 10112 { 10113 } 10114 10115 #endif /* CONFIG_RFS_ACCEL */ 10116 10117 static void bnxt_udp_tunnel_add(struct net_device *dev, 10118 struct udp_tunnel_info *ti) 10119 { 10120 struct bnxt *bp = netdev_priv(dev); 10121 10122 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) 10123 return; 10124 10125 if (!netif_running(dev)) 10126 return; 10127 10128 switch (ti->type) { 10129 case UDP_TUNNEL_TYPE_VXLAN: 10130 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port) 10131 return; 10132 10133 bp->vxlan_port_cnt++; 10134 if (bp->vxlan_port_cnt == 1) { 10135 bp->vxlan_port = ti->port; 10136 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event); 10137 bnxt_queue_sp_work(bp); 10138 } 10139 break; 10140 case UDP_TUNNEL_TYPE_GENEVE: 10141 if (bp->nge_port_cnt && bp->nge_port != ti->port) 10142 return; 10143 10144 bp->nge_port_cnt++; 10145 if (bp->nge_port_cnt == 1) { 10146 bp->nge_port = ti->port; 10147 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event); 10148 } 10149 break; 10150 default: 10151 return; 10152 } 10153 10154 bnxt_queue_sp_work(bp); 10155 } 10156 10157 static void bnxt_udp_tunnel_del(struct net_device *dev, 10158 struct udp_tunnel_info *ti) 10159 { 10160 struct bnxt *bp = netdev_priv(dev); 10161 10162 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET) 10163 return; 10164 10165 if (!netif_running(dev)) 10166 return; 10167 10168 switch (ti->type) { 10169 case UDP_TUNNEL_TYPE_VXLAN: 10170 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port) 10171 return; 10172 bp->vxlan_port_cnt--; 10173 10174 if (bp->vxlan_port_cnt != 0) 10175 return; 10176 10177 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event); 10178 break; 10179 case UDP_TUNNEL_TYPE_GENEVE: 10180 if (!bp->nge_port_cnt || bp->nge_port != ti->port) 10181 return; 10182 bp->nge_port_cnt--; 10183 10184 if (bp->nge_port_cnt != 0) 10185 return; 10186 10187 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event); 10188 break; 10189 default: 10190 return; 10191 } 10192 10193 bnxt_queue_sp_work(bp); 10194 } 10195 10196 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 10197 struct net_device *dev, u32 filter_mask, 10198 int nlflags) 10199 { 10200 struct bnxt *bp = netdev_priv(dev); 10201 10202 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0, 10203 nlflags, filter_mask, NULL); 10204 } 10205 10206 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, 10207 u16 flags, struct netlink_ext_ack *extack) 10208 { 10209 struct bnxt *bp = netdev_priv(dev); 10210 struct nlattr *attr, *br_spec; 10211 int rem, rc = 0; 10212 10213 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp)) 10214 return -EOPNOTSUPP; 10215 10216 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 10217 if (!br_spec) 10218 return -EINVAL; 10219 10220 nla_for_each_nested(attr, br_spec, rem) { 10221 u16 mode; 10222 10223 if (nla_type(attr) != IFLA_BRIDGE_MODE) 10224 continue; 10225 10226 if (nla_len(attr) < sizeof(mode)) 10227 return -EINVAL; 10228 10229 mode = nla_get_u16(attr); 10230 if (mode == bp->br_mode) 10231 break; 10232 10233 rc = bnxt_hwrm_set_br_mode(bp, mode); 10234 if (!rc) 10235 bp->br_mode = mode; 10236 break; 10237 } 10238 return rc; 10239 } 10240 10241 int bnxt_get_port_parent_id(struct net_device *dev, 10242 struct netdev_phys_item_id *ppid) 10243 { 10244 struct bnxt *bp = netdev_priv(dev); 10245 10246 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV) 10247 return -EOPNOTSUPP; 10248 10249 /* The PF and it's VF-reps only support the switchdev framework */ 10250 if (!BNXT_PF(bp)) 10251 return -EOPNOTSUPP; 10252 10253 ppid->id_len = sizeof(bp->switch_id); 10254 memcpy(ppid->id, bp->switch_id, ppid->id_len); 10255 10256 return 0; 10257 } 10258 10259 static struct devlink_port *bnxt_get_devlink_port(struct net_device *dev) 10260 { 10261 struct bnxt *bp = netdev_priv(dev); 10262 10263 return &bp->dl_port; 10264 } 10265 10266 static const struct net_device_ops bnxt_netdev_ops = { 10267 .ndo_open = bnxt_open, 10268 .ndo_start_xmit = bnxt_start_xmit, 10269 .ndo_stop = bnxt_close, 10270 .ndo_get_stats64 = bnxt_get_stats64, 10271 .ndo_set_rx_mode = bnxt_set_rx_mode, 10272 .ndo_do_ioctl = bnxt_ioctl, 10273 .ndo_validate_addr = eth_validate_addr, 10274 .ndo_set_mac_address = bnxt_change_mac_addr, 10275 .ndo_change_mtu = bnxt_change_mtu, 10276 .ndo_fix_features = bnxt_fix_features, 10277 .ndo_set_features = bnxt_set_features, 10278 .ndo_tx_timeout = bnxt_tx_timeout, 10279 #ifdef CONFIG_BNXT_SRIOV 10280 .ndo_get_vf_config = bnxt_get_vf_config, 10281 .ndo_set_vf_mac = bnxt_set_vf_mac, 10282 .ndo_set_vf_vlan = bnxt_set_vf_vlan, 10283 .ndo_set_vf_rate = bnxt_set_vf_bw, 10284 .ndo_set_vf_link_state = bnxt_set_vf_link_state, 10285 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk, 10286 .ndo_set_vf_trust = bnxt_set_vf_trust, 10287 #endif 10288 .ndo_setup_tc = bnxt_setup_tc, 10289 #ifdef CONFIG_RFS_ACCEL 10290 .ndo_rx_flow_steer = bnxt_rx_flow_steer, 10291 #endif 10292 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add, 10293 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del, 10294 .ndo_bpf = bnxt_xdp, 10295 .ndo_xdp_xmit = bnxt_xdp_xmit, 10296 .ndo_bridge_getlink = bnxt_bridge_getlink, 10297 .ndo_bridge_setlink = bnxt_bridge_setlink, 10298 .ndo_get_devlink_port = bnxt_get_devlink_port, 10299 }; 10300 10301 static void bnxt_remove_one(struct pci_dev *pdev) 10302 { 10303 struct net_device *dev = pci_get_drvdata(pdev); 10304 struct bnxt *bp = netdev_priv(dev); 10305 10306 if (BNXT_PF(bp)) { 10307 bnxt_sriov_disable(bp); 10308 bnxt_dl_unregister(bp); 10309 } 10310 10311 pci_disable_pcie_error_reporting(pdev); 10312 unregister_netdev(dev); 10313 bnxt_shutdown_tc(bp); 10314 bnxt_cancel_sp_work(bp); 10315 bp->sp_event = 0; 10316 10317 bnxt_clear_int_mode(bp); 10318 bnxt_hwrm_func_drv_unrgtr(bp); 10319 bnxt_free_hwrm_resources(bp); 10320 bnxt_free_hwrm_short_cmd_req(bp); 10321 bnxt_ethtool_free(bp); 10322 bnxt_dcb_free(bp); 10323 kfree(bp->edev); 10324 bp->edev = NULL; 10325 bnxt_free_ctx_mem(bp); 10326 kfree(bp->ctx); 10327 bp->ctx = NULL; 10328 bnxt_cleanup_pci(bp); 10329 bnxt_free_port_stats(bp); 10330 free_netdev(dev); 10331 } 10332 10333 static int bnxt_probe_phy(struct bnxt *bp) 10334 { 10335 int rc = 0; 10336 struct bnxt_link_info *link_info = &bp->link_info; 10337 10338 rc = bnxt_hwrm_phy_qcaps(bp); 10339 if (rc) { 10340 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n", 10341 rc); 10342 return rc; 10343 } 10344 mutex_init(&bp->link_lock); 10345 10346 rc = bnxt_update_link(bp, false); 10347 if (rc) { 10348 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n", 10349 rc); 10350 return rc; 10351 } 10352 10353 /* Older firmware does not have supported_auto_speeds, so assume 10354 * that all supported speeds can be autonegotiated. 10355 */ 10356 if (link_info->auto_link_speeds && !link_info->support_auto_speeds) 10357 link_info->support_auto_speeds = link_info->support_speeds; 10358 10359 /*initialize the ethool setting copy with NVM settings */ 10360 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 10361 link_info->autoneg = BNXT_AUTONEG_SPEED; 10362 if (bp->hwrm_spec_code >= 0x10201) { 10363 if (link_info->auto_pause_setting & 10364 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE) 10365 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 10366 } else { 10367 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 10368 } 10369 link_info->advertising = link_info->auto_link_speeds; 10370 } else { 10371 link_info->req_link_speed = link_info->force_link_speed; 10372 link_info->req_duplex = link_info->duplex_setting; 10373 } 10374 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 10375 link_info->req_flow_ctrl = 10376 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH; 10377 else 10378 link_info->req_flow_ctrl = link_info->force_pause_setting; 10379 return rc; 10380 } 10381 10382 static int bnxt_get_max_irq(struct pci_dev *pdev) 10383 { 10384 u16 ctrl; 10385 10386 if (!pdev->msix_cap) 10387 return 1; 10388 10389 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 10390 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; 10391 } 10392 10393 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, 10394 int *max_cp) 10395 { 10396 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 10397 int max_ring_grps = 0, max_irq; 10398 10399 *max_tx = hw_resc->max_tx_rings; 10400 *max_rx = hw_resc->max_rx_rings; 10401 *max_cp = bnxt_get_max_func_cp_rings_for_en(bp); 10402 max_irq = min_t(int, bnxt_get_max_func_irqs(bp) - 10403 bnxt_get_ulp_msix_num(bp), 10404 hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp)); 10405 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) 10406 *max_cp = min_t(int, *max_cp, max_irq); 10407 max_ring_grps = hw_resc->max_hw_ring_grps; 10408 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) { 10409 *max_cp -= 1; 10410 *max_rx -= 2; 10411 } 10412 if (bp->flags & BNXT_FLAG_AGG_RINGS) 10413 *max_rx >>= 1; 10414 if (bp->flags & BNXT_FLAG_CHIP_P5) { 10415 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false); 10416 /* On P5 chips, max_cp output param should be available NQs */ 10417 *max_cp = max_irq; 10418 } 10419 *max_rx = min_t(int, *max_rx, max_ring_grps); 10420 } 10421 10422 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared) 10423 { 10424 int rx, tx, cp; 10425 10426 _bnxt_get_max_rings(bp, &rx, &tx, &cp); 10427 *max_rx = rx; 10428 *max_tx = tx; 10429 if (!rx || !tx || !cp) 10430 return -ENOMEM; 10431 10432 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared); 10433 } 10434 10435 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx, 10436 bool shared) 10437 { 10438 int rc; 10439 10440 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 10441 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) { 10442 /* Not enough rings, try disabling agg rings. */ 10443 bp->flags &= ~BNXT_FLAG_AGG_RINGS; 10444 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared); 10445 if (rc) { 10446 /* set BNXT_FLAG_AGG_RINGS back for consistency */ 10447 bp->flags |= BNXT_FLAG_AGG_RINGS; 10448 return rc; 10449 } 10450 bp->flags |= BNXT_FLAG_NO_AGG_RINGS; 10451 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 10452 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 10453 bnxt_set_ring_params(bp); 10454 } 10455 10456 if (bp->flags & BNXT_FLAG_ROCE_CAP) { 10457 int max_cp, max_stat, max_irq; 10458 10459 /* Reserve minimum resources for RoCE */ 10460 max_cp = bnxt_get_max_func_cp_rings(bp); 10461 max_stat = bnxt_get_max_func_stat_ctxs(bp); 10462 max_irq = bnxt_get_max_func_irqs(bp); 10463 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS || 10464 max_irq <= BNXT_MIN_ROCE_CP_RINGS || 10465 max_stat <= BNXT_MIN_ROCE_STAT_CTXS) 10466 return 0; 10467 10468 max_cp -= BNXT_MIN_ROCE_CP_RINGS; 10469 max_irq -= BNXT_MIN_ROCE_CP_RINGS; 10470 max_stat -= BNXT_MIN_ROCE_STAT_CTXS; 10471 max_cp = min_t(int, max_cp, max_irq); 10472 max_cp = min_t(int, max_cp, max_stat); 10473 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared); 10474 if (rc) 10475 rc = 0; 10476 } 10477 return rc; 10478 } 10479 10480 /* In initial default shared ring setting, each shared ring must have a 10481 * RX/TX ring pair. 10482 */ 10483 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp) 10484 { 10485 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings); 10486 bp->rx_nr_rings = bp->cp_nr_rings; 10487 bp->tx_nr_rings_per_tc = bp->cp_nr_rings; 10488 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 10489 } 10490 10491 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh) 10492 { 10493 int dflt_rings, max_rx_rings, max_tx_rings, rc; 10494 10495 if (!bnxt_can_reserve_rings(bp)) 10496 return 0; 10497 10498 if (sh) 10499 bp->flags |= BNXT_FLAG_SHARED_RINGS; 10500 dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues(); 10501 /* Reduce default rings on multi-port cards so that total default 10502 * rings do not exceed CPU count. 10503 */ 10504 if (bp->port_count > 1) { 10505 int max_rings = 10506 max_t(int, num_online_cpus() / bp->port_count, 1); 10507 10508 dflt_rings = min_t(int, dflt_rings, max_rings); 10509 } 10510 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh); 10511 if (rc) 10512 return rc; 10513 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings); 10514 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings); 10515 if (sh) 10516 bnxt_trim_dflt_sh_rings(bp); 10517 else 10518 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings; 10519 bp->tx_nr_rings = bp->tx_nr_rings_per_tc; 10520 10521 rc = __bnxt_reserve_rings(bp); 10522 if (rc) 10523 netdev_warn(bp->dev, "Unable to reserve tx rings\n"); 10524 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 10525 if (sh) 10526 bnxt_trim_dflt_sh_rings(bp); 10527 10528 /* Rings may have been trimmed, re-reserve the trimmed rings. */ 10529 if (bnxt_need_reserve_rings(bp)) { 10530 rc = __bnxt_reserve_rings(bp); 10531 if (rc) 10532 netdev_warn(bp->dev, "2nd rings reservation failed.\n"); 10533 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 10534 } 10535 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) { 10536 bp->rx_nr_rings++; 10537 bp->cp_nr_rings++; 10538 } 10539 return rc; 10540 } 10541 10542 static int bnxt_init_dflt_ring_mode(struct bnxt *bp) 10543 { 10544 int rc; 10545 10546 if (bp->tx_nr_rings) 10547 return 0; 10548 10549 bnxt_ulp_irq_stop(bp); 10550 bnxt_clear_int_mode(bp); 10551 rc = bnxt_set_dflt_rings(bp, true); 10552 if (rc) { 10553 netdev_err(bp->dev, "Not enough rings available.\n"); 10554 goto init_dflt_ring_err; 10555 } 10556 rc = bnxt_init_int_mode(bp); 10557 if (rc) 10558 goto init_dflt_ring_err; 10559 10560 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 10561 if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) { 10562 bp->flags |= BNXT_FLAG_RFS; 10563 bp->dev->features |= NETIF_F_NTUPLE; 10564 } 10565 init_dflt_ring_err: 10566 bnxt_ulp_irq_restart(bp, rc); 10567 return rc; 10568 } 10569 10570 int bnxt_restore_pf_fw_resources(struct bnxt *bp) 10571 { 10572 int rc; 10573 10574 ASSERT_RTNL(); 10575 bnxt_hwrm_func_qcaps(bp); 10576 10577 if (netif_running(bp->dev)) 10578 __bnxt_close_nic(bp, true, false); 10579 10580 bnxt_ulp_irq_stop(bp); 10581 bnxt_clear_int_mode(bp); 10582 rc = bnxt_init_int_mode(bp); 10583 bnxt_ulp_irq_restart(bp, rc); 10584 10585 if (netif_running(bp->dev)) { 10586 if (rc) 10587 dev_close(bp->dev); 10588 else 10589 rc = bnxt_open_nic(bp, true, false); 10590 } 10591 10592 return rc; 10593 } 10594 10595 static int bnxt_init_mac_addr(struct bnxt *bp) 10596 { 10597 int rc = 0; 10598 10599 if (BNXT_PF(bp)) { 10600 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN); 10601 } else { 10602 #ifdef CONFIG_BNXT_SRIOV 10603 struct bnxt_vf_info *vf = &bp->vf; 10604 bool strict_approval = true; 10605 10606 if (is_valid_ether_addr(vf->mac_addr)) { 10607 /* overwrite netdev dev_addr with admin VF MAC */ 10608 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN); 10609 /* Older PF driver or firmware may not approve this 10610 * correctly. 10611 */ 10612 strict_approval = false; 10613 } else { 10614 eth_hw_addr_random(bp->dev); 10615 } 10616 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval); 10617 #endif 10618 } 10619 return rc; 10620 } 10621 10622 static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[]) 10623 { 10624 struct pci_dev *pdev = bp->pdev; 10625 int pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DSN); 10626 u32 dw; 10627 10628 if (!pos) { 10629 netdev_info(bp->dev, "Unable do read adapter's DSN"); 10630 return -EOPNOTSUPP; 10631 } 10632 10633 /* DSN (two dw) is at an offset of 4 from the cap pos */ 10634 pos += 4; 10635 pci_read_config_dword(pdev, pos, &dw); 10636 put_unaligned_le32(dw, &dsn[0]); 10637 pci_read_config_dword(pdev, pos + 4, &dw); 10638 put_unaligned_le32(dw, &dsn[4]); 10639 return 0; 10640 } 10641 10642 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 10643 { 10644 static int version_printed; 10645 struct net_device *dev; 10646 struct bnxt *bp; 10647 int rc, max_irqs; 10648 10649 if (pci_is_bridge(pdev)) 10650 return -ENODEV; 10651 10652 if (version_printed++ == 0) 10653 pr_info("%s", version); 10654 10655 max_irqs = bnxt_get_max_irq(pdev); 10656 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs); 10657 if (!dev) 10658 return -ENOMEM; 10659 10660 bp = netdev_priv(dev); 10661 bnxt_set_max_func_irqs(bp, max_irqs); 10662 10663 if (bnxt_vf_pciid(ent->driver_data)) 10664 bp->flags |= BNXT_FLAG_VF; 10665 10666 if (pdev->msix_cap) 10667 bp->flags |= BNXT_FLAG_MSIX_CAP; 10668 10669 rc = bnxt_init_board(pdev, dev); 10670 if (rc < 0) 10671 goto init_err_free; 10672 10673 dev->netdev_ops = &bnxt_netdev_ops; 10674 dev->watchdog_timeo = BNXT_TX_TIMEOUT; 10675 dev->ethtool_ops = &bnxt_ethtool_ops; 10676 pci_set_drvdata(pdev, dev); 10677 10678 rc = bnxt_alloc_hwrm_resources(bp); 10679 if (rc) 10680 goto init_err_pci_clean; 10681 10682 mutex_init(&bp->hwrm_cmd_lock); 10683 rc = bnxt_hwrm_ver_get(bp); 10684 if (rc) 10685 goto init_err_pci_clean; 10686 10687 if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) { 10688 rc = bnxt_alloc_kong_hwrm_resources(bp); 10689 if (rc) 10690 bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL; 10691 } 10692 10693 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) || 10694 bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) { 10695 rc = bnxt_alloc_hwrm_short_cmd_req(bp); 10696 if (rc) 10697 goto init_err_pci_clean; 10698 } 10699 10700 if (BNXT_CHIP_P5(bp)) 10701 bp->flags |= BNXT_FLAG_CHIP_P5; 10702 10703 rc = bnxt_hwrm_func_reset(bp); 10704 if (rc) 10705 goto init_err_pci_clean; 10706 10707 bnxt_hwrm_fw_set_time(bp); 10708 10709 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 10710 NETIF_F_TSO | NETIF_F_TSO6 | 10711 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 10712 NETIF_F_GSO_IPXIP4 | 10713 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 10714 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH | 10715 NETIF_F_RXCSUM | NETIF_F_GRO; 10716 10717 if (BNXT_SUPPORTS_TPA(bp)) 10718 dev->hw_features |= NETIF_F_LRO; 10719 10720 dev->hw_enc_features = 10721 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 10722 NETIF_F_TSO | NETIF_F_TSO6 | 10723 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 10724 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM | 10725 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL; 10726 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM | 10727 NETIF_F_GSO_GRE_CSUM; 10728 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA; 10729 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 10730 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX; 10731 if (BNXT_SUPPORTS_TPA(bp)) 10732 dev->hw_features |= NETIF_F_GRO_HW; 10733 dev->features |= dev->hw_features | NETIF_F_HIGHDMA; 10734 if (dev->features & NETIF_F_GRO_HW) 10735 dev->features &= ~NETIF_F_LRO; 10736 dev->priv_flags |= IFF_UNICAST_FLT; 10737 10738 #ifdef CONFIG_BNXT_SRIOV 10739 init_waitqueue_head(&bp->sriov_cfg_wait); 10740 mutex_init(&bp->sriov_lock); 10741 #endif 10742 if (BNXT_SUPPORTS_TPA(bp)) { 10743 bp->gro_func = bnxt_gro_func_5730x; 10744 if (BNXT_CHIP_P4(bp)) 10745 bp->gro_func = bnxt_gro_func_5731x; 10746 } 10747 if (!BNXT_CHIP_P4_PLUS(bp)) 10748 bp->flags |= BNXT_FLAG_DOUBLE_DB; 10749 10750 rc = bnxt_hwrm_func_drv_rgtr(bp); 10751 if (rc) 10752 goto init_err_pci_clean; 10753 10754 rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0); 10755 if (rc) 10756 goto init_err_pci_clean; 10757 10758 bp->ulp_probe = bnxt_ulp_probe; 10759 10760 rc = bnxt_hwrm_queue_qportcfg(bp); 10761 if (rc) { 10762 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n", 10763 rc); 10764 rc = -1; 10765 goto init_err_pci_clean; 10766 } 10767 /* Get the MAX capabilities for this function */ 10768 rc = bnxt_hwrm_func_qcaps(bp); 10769 if (rc) { 10770 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n", 10771 rc); 10772 rc = -1; 10773 goto init_err_pci_clean; 10774 } 10775 10776 rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp); 10777 if (rc) 10778 netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n", 10779 rc); 10780 10781 rc = bnxt_init_mac_addr(bp); 10782 if (rc) { 10783 dev_err(&pdev->dev, "Unable to initialize mac address.\n"); 10784 rc = -EADDRNOTAVAIL; 10785 goto init_err_pci_clean; 10786 } 10787 10788 if (BNXT_PF(bp)) { 10789 /* Read the adapter's DSN to use as the eswitch switch_id */ 10790 rc = bnxt_pcie_dsn_get(bp, bp->switch_id); 10791 if (rc) 10792 goto init_err_pci_clean; 10793 } 10794 bnxt_hwrm_func_qcfg(bp); 10795 bnxt_hwrm_vnic_qcaps(bp); 10796 bnxt_hwrm_port_led_qcaps(bp); 10797 bnxt_ethtool_init(bp); 10798 bnxt_dcb_init(bp); 10799 10800 /* MTU range: 60 - FW defined max */ 10801 dev->min_mtu = ETH_ZLEN; 10802 dev->max_mtu = bp->max_mtu; 10803 10804 rc = bnxt_probe_phy(bp); 10805 if (rc) 10806 goto init_err_pci_clean; 10807 10808 bnxt_set_rx_skb_mode(bp, false); 10809 bnxt_set_tpa_flags(bp); 10810 bnxt_set_ring_params(bp); 10811 rc = bnxt_set_dflt_rings(bp, true); 10812 if (rc) { 10813 netdev_err(bp->dev, "Not enough rings available.\n"); 10814 rc = -ENOMEM; 10815 goto init_err_pci_clean; 10816 } 10817 10818 /* Default RSS hash cfg. */ 10819 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 | 10820 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 | 10821 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 | 10822 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 10823 if (BNXT_CHIP_P4(bp) && bp->hwrm_spec_code >= 0x10501) { 10824 bp->flags |= BNXT_FLAG_UDP_RSS_CAP; 10825 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 | 10826 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 10827 } 10828 10829 if (bnxt_rfs_supported(bp)) { 10830 dev->hw_features |= NETIF_F_NTUPLE; 10831 if (bnxt_rfs_capable(bp)) { 10832 bp->flags |= BNXT_FLAG_RFS; 10833 dev->features |= NETIF_F_NTUPLE; 10834 } 10835 } 10836 10837 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX) 10838 bp->flags |= BNXT_FLAG_STRIP_VLAN; 10839 10840 rc = bnxt_init_int_mode(bp); 10841 if (rc) 10842 goto init_err_pci_clean; 10843 10844 /* No TC has been set yet and rings may have been trimmed due to 10845 * limited MSIX, so we re-initialize the TX rings per TC. 10846 */ 10847 bp->tx_nr_rings_per_tc = bp->tx_nr_rings; 10848 10849 bnxt_get_wol_settings(bp); 10850 if (bp->flags & BNXT_FLAG_WOL_CAP) 10851 device_set_wakeup_enable(&pdev->dev, bp->wol); 10852 else 10853 device_set_wakeup_capable(&pdev->dev, false); 10854 10855 bnxt_hwrm_set_cache_line_size(bp, cache_line_size()); 10856 10857 bnxt_hwrm_coal_params_qcaps(bp); 10858 10859 if (BNXT_PF(bp)) { 10860 if (!bnxt_pf_wq) { 10861 bnxt_pf_wq = 10862 create_singlethread_workqueue("bnxt_pf_wq"); 10863 if (!bnxt_pf_wq) { 10864 dev_err(&pdev->dev, "Unable to create workqueue.\n"); 10865 goto init_err_pci_clean; 10866 } 10867 } 10868 bnxt_init_tc(bp); 10869 } 10870 10871 rc = register_netdev(dev); 10872 if (rc) 10873 goto init_err_cleanup_tc; 10874 10875 if (BNXT_PF(bp)) 10876 bnxt_dl_register(bp); 10877 10878 netdev_info(dev, "%s found at mem %lx, node addr %pM\n", 10879 board_info[ent->driver_data].name, 10880 (long)pci_resource_start(pdev, 0), dev->dev_addr); 10881 pcie_print_link_status(pdev); 10882 10883 return 0; 10884 10885 init_err_cleanup_tc: 10886 bnxt_shutdown_tc(bp); 10887 bnxt_clear_int_mode(bp); 10888 10889 init_err_pci_clean: 10890 bnxt_free_hwrm_short_cmd_req(bp); 10891 bnxt_free_hwrm_resources(bp); 10892 bnxt_free_ctx_mem(bp); 10893 kfree(bp->ctx); 10894 bp->ctx = NULL; 10895 bnxt_cleanup_pci(bp); 10896 10897 init_err_free: 10898 free_netdev(dev); 10899 return rc; 10900 } 10901 10902 static void bnxt_shutdown(struct pci_dev *pdev) 10903 { 10904 struct net_device *dev = pci_get_drvdata(pdev); 10905 struct bnxt *bp; 10906 10907 if (!dev) 10908 return; 10909 10910 rtnl_lock(); 10911 bp = netdev_priv(dev); 10912 if (!bp) 10913 goto shutdown_exit; 10914 10915 if (netif_running(dev)) 10916 dev_close(dev); 10917 10918 bnxt_ulp_shutdown(bp); 10919 10920 if (system_state == SYSTEM_POWER_OFF) { 10921 bnxt_clear_int_mode(bp); 10922 pci_wake_from_d3(pdev, bp->wol); 10923 pci_set_power_state(pdev, PCI_D3hot); 10924 } 10925 10926 shutdown_exit: 10927 rtnl_unlock(); 10928 } 10929 10930 #ifdef CONFIG_PM_SLEEP 10931 static int bnxt_suspend(struct device *device) 10932 { 10933 struct pci_dev *pdev = to_pci_dev(device); 10934 struct net_device *dev = pci_get_drvdata(pdev); 10935 struct bnxt *bp = netdev_priv(dev); 10936 int rc = 0; 10937 10938 rtnl_lock(); 10939 if (netif_running(dev)) { 10940 netif_device_detach(dev); 10941 rc = bnxt_close(dev); 10942 } 10943 bnxt_hwrm_func_drv_unrgtr(bp); 10944 rtnl_unlock(); 10945 return rc; 10946 } 10947 10948 static int bnxt_resume(struct device *device) 10949 { 10950 struct pci_dev *pdev = to_pci_dev(device); 10951 struct net_device *dev = pci_get_drvdata(pdev); 10952 struct bnxt *bp = netdev_priv(dev); 10953 int rc = 0; 10954 10955 rtnl_lock(); 10956 if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) { 10957 rc = -ENODEV; 10958 goto resume_exit; 10959 } 10960 rc = bnxt_hwrm_func_reset(bp); 10961 if (rc) { 10962 rc = -EBUSY; 10963 goto resume_exit; 10964 } 10965 bnxt_get_wol_settings(bp); 10966 if (netif_running(dev)) { 10967 rc = bnxt_open(dev); 10968 if (!rc) 10969 netif_device_attach(dev); 10970 } 10971 10972 resume_exit: 10973 rtnl_unlock(); 10974 return rc; 10975 } 10976 10977 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume); 10978 #define BNXT_PM_OPS (&bnxt_pm_ops) 10979 10980 #else 10981 10982 #define BNXT_PM_OPS NULL 10983 10984 #endif /* CONFIG_PM_SLEEP */ 10985 10986 /** 10987 * bnxt_io_error_detected - called when PCI error is detected 10988 * @pdev: Pointer to PCI device 10989 * @state: The current pci connection state 10990 * 10991 * This function is called after a PCI bus error affecting 10992 * this device has been detected. 10993 */ 10994 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev, 10995 pci_channel_state_t state) 10996 { 10997 struct net_device *netdev = pci_get_drvdata(pdev); 10998 struct bnxt *bp = netdev_priv(netdev); 10999 11000 netdev_info(netdev, "PCI I/O error detected\n"); 11001 11002 rtnl_lock(); 11003 netif_device_detach(netdev); 11004 11005 bnxt_ulp_stop(bp); 11006 11007 if (state == pci_channel_io_perm_failure) { 11008 rtnl_unlock(); 11009 return PCI_ERS_RESULT_DISCONNECT; 11010 } 11011 11012 if (netif_running(netdev)) 11013 bnxt_close(netdev); 11014 11015 pci_disable_device(pdev); 11016 rtnl_unlock(); 11017 11018 /* Request a slot slot reset. */ 11019 return PCI_ERS_RESULT_NEED_RESET; 11020 } 11021 11022 /** 11023 * bnxt_io_slot_reset - called after the pci bus has been reset. 11024 * @pdev: Pointer to PCI device 11025 * 11026 * Restart the card from scratch, as if from a cold-boot. 11027 * At this point, the card has exprienced a hard reset, 11028 * followed by fixups by BIOS, and has its config space 11029 * set up identically to what it was at cold boot. 11030 */ 11031 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev) 11032 { 11033 struct net_device *netdev = pci_get_drvdata(pdev); 11034 struct bnxt *bp = netdev_priv(netdev); 11035 int err = 0; 11036 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT; 11037 11038 netdev_info(bp->dev, "PCI Slot Reset\n"); 11039 11040 rtnl_lock(); 11041 11042 if (pci_enable_device(pdev)) { 11043 dev_err(&pdev->dev, 11044 "Cannot re-enable PCI device after reset.\n"); 11045 } else { 11046 pci_set_master(pdev); 11047 11048 err = bnxt_hwrm_func_reset(bp); 11049 if (!err && netif_running(netdev)) 11050 err = bnxt_open(netdev); 11051 11052 if (!err) { 11053 result = PCI_ERS_RESULT_RECOVERED; 11054 bnxt_ulp_start(bp); 11055 } 11056 } 11057 11058 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev)) 11059 dev_close(netdev); 11060 11061 rtnl_unlock(); 11062 11063 return PCI_ERS_RESULT_RECOVERED; 11064 } 11065 11066 /** 11067 * bnxt_io_resume - called when traffic can start flowing again. 11068 * @pdev: Pointer to PCI device 11069 * 11070 * This callback is called when the error recovery driver tells 11071 * us that its OK to resume normal operation. 11072 */ 11073 static void bnxt_io_resume(struct pci_dev *pdev) 11074 { 11075 struct net_device *netdev = pci_get_drvdata(pdev); 11076 11077 rtnl_lock(); 11078 11079 netif_device_attach(netdev); 11080 11081 rtnl_unlock(); 11082 } 11083 11084 static const struct pci_error_handlers bnxt_err_handler = { 11085 .error_detected = bnxt_io_error_detected, 11086 .slot_reset = bnxt_io_slot_reset, 11087 .resume = bnxt_io_resume 11088 }; 11089 11090 static struct pci_driver bnxt_pci_driver = { 11091 .name = DRV_MODULE_NAME, 11092 .id_table = bnxt_pci_tbl, 11093 .probe = bnxt_init_one, 11094 .remove = bnxt_remove_one, 11095 .shutdown = bnxt_shutdown, 11096 .driver.pm = BNXT_PM_OPS, 11097 .err_handler = &bnxt_err_handler, 11098 #if defined(CONFIG_BNXT_SRIOV) 11099 .sriov_configure = bnxt_sriov_configure, 11100 #endif 11101 }; 11102 11103 static int __init bnxt_init(void) 11104 { 11105 bnxt_debug_init(); 11106 return pci_register_driver(&bnxt_pci_driver); 11107 } 11108 11109 static void __exit bnxt_exit(void) 11110 { 11111 pci_unregister_driver(&bnxt_pci_driver); 11112 if (bnxt_pf_wq) 11113 destroy_workqueue(bnxt_pf_wq); 11114 bnxt_debug_exit(); 11115 } 11116 11117 module_init(bnxt_init); 11118 module_exit(bnxt_exit); 11119