1 /* bnx2x_sriov.c: QLogic Everest network driver. 2 * 3 * Copyright 2009-2013 Broadcom Corporation 4 * Copyright 2014 QLogic Corporation 5 * All rights reserved 6 * 7 * Unless you and QLogic execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2, available 10 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 11 * 12 * Notwithstanding the above, under no circumstances may you combine this 13 * software in any way with any other QLogic software provided under a 14 * license other than the GPL, without QLogic's express prior written 15 * consent. 16 * 17 * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 18 * Written by: Shmulik Ravid 19 * Ariel Elior <ariel.elior@qlogic.com> 20 * 21 */ 22 #include "bnx2x.h" 23 #include "bnx2x_init.h" 24 #include "bnx2x_cmn.h" 25 #include "bnx2x_sp.h" 26 #include <linux/crc32.h> 27 #include <linux/if_vlan.h> 28 29 static int bnx2x_vf_op_prep(struct bnx2x *bp, int vfidx, 30 struct bnx2x_virtf **vf, 31 struct pf_vf_bulletin_content **bulletin, 32 bool test_queue); 33 34 /* General service functions */ 35 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, 36 u16 pf_id) 37 { 38 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), 39 pf_id); 40 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), 41 pf_id); 42 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), 43 pf_id); 44 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), 45 pf_id); 46 } 47 48 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, 49 u8 enable) 50 { 51 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), 52 enable); 53 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), 54 enable); 55 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), 56 enable); 57 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), 58 enable); 59 } 60 61 int bnx2x_vf_idx_by_abs_fid(struct bnx2x *bp, u16 abs_vfid) 62 { 63 int idx; 64 65 for_each_vf(bp, idx) 66 if (bnx2x_vf(bp, idx, abs_vfid) == abs_vfid) 67 break; 68 return idx; 69 } 70 71 static 72 struct bnx2x_virtf *bnx2x_vf_by_abs_fid(struct bnx2x *bp, u16 abs_vfid) 73 { 74 u16 idx = (u16)bnx2x_vf_idx_by_abs_fid(bp, abs_vfid); 75 return (idx < BNX2X_NR_VIRTFN(bp)) ? BP_VF(bp, idx) : NULL; 76 } 77 78 static void bnx2x_vf_igu_ack_sb(struct bnx2x *bp, struct bnx2x_virtf *vf, 79 u8 igu_sb_id, u8 segment, u16 index, u8 op, 80 u8 update) 81 { 82 /* acking a VF sb through the PF - use the GRC */ 83 u32 ctl; 84 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; 85 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; 86 u32 func_encode = vf->abs_vfid; 87 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + igu_sb_id; 88 struct igu_regular cmd_data = {0}; 89 90 cmd_data.sb_id_and_flags = 91 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 92 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 93 (update << IGU_REGULAR_BUPDATE_SHIFT) | 94 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 95 96 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | 97 func_encode << IGU_CTRL_REG_FID_SHIFT | 98 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; 99 100 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 101 cmd_data.sb_id_and_flags, igu_addr_data); 102 REG_WR(bp, igu_addr_data, cmd_data.sb_id_and_flags); 103 mmiowb(); 104 barrier(); 105 106 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 107 ctl, igu_addr_ctl); 108 REG_WR(bp, igu_addr_ctl, ctl); 109 mmiowb(); 110 barrier(); 111 } 112 113 static bool bnx2x_validate_vf_sp_objs(struct bnx2x *bp, 114 struct bnx2x_virtf *vf, 115 bool print_err) 116 { 117 if (!bnx2x_leading_vfq(vf, sp_initialized)) { 118 if (print_err) 119 BNX2X_ERR("Slowpath objects not yet initialized!\n"); 120 else 121 DP(BNX2X_MSG_IOV, "Slowpath objects not yet initialized!\n"); 122 return false; 123 } 124 return true; 125 } 126 127 /* VFOP operations states */ 128 void bnx2x_vfop_qctor_dump_tx(struct bnx2x *bp, struct bnx2x_virtf *vf, 129 struct bnx2x_queue_init_params *init_params, 130 struct bnx2x_queue_setup_params *setup_params, 131 u16 q_idx, u16 sb_idx) 132 { 133 DP(BNX2X_MSG_IOV, 134 "VF[%d] Q_SETUP: txq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, flags=0x%lx, traffic-type=%d", 135 vf->abs_vfid, 136 q_idx, 137 sb_idx, 138 init_params->tx.sb_cq_index, 139 init_params->tx.hc_rate, 140 setup_params->flags, 141 setup_params->txq_params.traffic_type); 142 } 143 144 void bnx2x_vfop_qctor_dump_rx(struct bnx2x *bp, struct bnx2x_virtf *vf, 145 struct bnx2x_queue_init_params *init_params, 146 struct bnx2x_queue_setup_params *setup_params, 147 u16 q_idx, u16 sb_idx) 148 { 149 struct bnx2x_rxq_setup_params *rxq_params = &setup_params->rxq_params; 150 151 DP(BNX2X_MSG_IOV, "VF[%d] Q_SETUP: rxq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, mtu=%d, buf-size=%d\n" 152 "sge-size=%d, max_sge_pkt=%d, tpa-agg-size=%d, flags=0x%lx, drop-flags=0x%x, cache-log=%d\n", 153 vf->abs_vfid, 154 q_idx, 155 sb_idx, 156 init_params->rx.sb_cq_index, 157 init_params->rx.hc_rate, 158 setup_params->gen_params.mtu, 159 rxq_params->buf_sz, 160 rxq_params->sge_buf_sz, 161 rxq_params->max_sges_pkt, 162 rxq_params->tpa_agg_sz, 163 setup_params->flags, 164 rxq_params->drop_flags, 165 rxq_params->cache_line_log); 166 } 167 168 void bnx2x_vfop_qctor_prep(struct bnx2x *bp, 169 struct bnx2x_virtf *vf, 170 struct bnx2x_vf_queue *q, 171 struct bnx2x_vf_queue_construct_params *p, 172 unsigned long q_type) 173 { 174 struct bnx2x_queue_init_params *init_p = &p->qstate.params.init; 175 struct bnx2x_queue_setup_params *setup_p = &p->prep_qsetup; 176 177 /* INIT */ 178 179 /* Enable host coalescing in the transition to INIT state */ 180 if (test_bit(BNX2X_Q_FLG_HC, &init_p->rx.flags)) 181 __set_bit(BNX2X_Q_FLG_HC_EN, &init_p->rx.flags); 182 183 if (test_bit(BNX2X_Q_FLG_HC, &init_p->tx.flags)) 184 __set_bit(BNX2X_Q_FLG_HC_EN, &init_p->tx.flags); 185 186 /* FW SB ID */ 187 init_p->rx.fw_sb_id = vf_igu_sb(vf, q->sb_idx); 188 init_p->tx.fw_sb_id = vf_igu_sb(vf, q->sb_idx); 189 190 /* context */ 191 init_p->cxts[0] = q->cxt; 192 193 /* SETUP */ 194 195 /* Setup-op general parameters */ 196 setup_p->gen_params.spcl_id = vf->sp_cl_id; 197 setup_p->gen_params.stat_id = vfq_stat_id(vf, q); 198 setup_p->gen_params.fp_hsi = vf->fp_hsi; 199 200 /* Setup-op flags: 201 * collect statistics, zero statistics, local-switching, security, 202 * OV for Flex10, RSS and MCAST for leading 203 */ 204 if (test_bit(BNX2X_Q_FLG_STATS, &setup_p->flags)) 205 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &setup_p->flags); 206 207 /* for VFs, enable tx switching, bd coherency, and mac address 208 * anti-spoofing 209 */ 210 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &setup_p->flags); 211 __set_bit(BNX2X_Q_FLG_TX_SEC, &setup_p->flags); 212 __set_bit(BNX2X_Q_FLG_ANTI_SPOOF, &setup_p->flags); 213 214 /* Setup-op rx parameters */ 215 if (test_bit(BNX2X_Q_TYPE_HAS_RX, &q_type)) { 216 struct bnx2x_rxq_setup_params *rxq_p = &setup_p->rxq_params; 217 218 rxq_p->cl_qzone_id = vfq_qzone_id(vf, q); 219 rxq_p->fw_sb_id = vf_igu_sb(vf, q->sb_idx); 220 rxq_p->rss_engine_id = FW_VF_HANDLE(vf->abs_vfid); 221 222 if (test_bit(BNX2X_Q_FLG_TPA, &setup_p->flags)) 223 rxq_p->max_tpa_queues = BNX2X_VF_MAX_TPA_AGG_QUEUES; 224 } 225 226 /* Setup-op tx parameters */ 227 if (test_bit(BNX2X_Q_TYPE_HAS_TX, &q_type)) { 228 setup_p->txq_params.tss_leading_cl_id = vf->leading_rss; 229 setup_p->txq_params.fw_sb_id = vf_igu_sb(vf, q->sb_idx); 230 } 231 } 232 233 static int bnx2x_vf_queue_create(struct bnx2x *bp, 234 struct bnx2x_virtf *vf, int qid, 235 struct bnx2x_vf_queue_construct_params *qctor) 236 { 237 struct bnx2x_queue_state_params *q_params; 238 int rc = 0; 239 240 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); 241 242 /* Prepare ramrod information */ 243 q_params = &qctor->qstate; 244 q_params->q_obj = &bnx2x_vfq(vf, qid, sp_obj); 245 set_bit(RAMROD_COMP_WAIT, &q_params->ramrod_flags); 246 247 if (bnx2x_get_q_logical_state(bp, q_params->q_obj) == 248 BNX2X_Q_LOGICAL_STATE_ACTIVE) { 249 DP(BNX2X_MSG_IOV, "queue was already up. Aborting gracefully\n"); 250 goto out; 251 } 252 253 /* Run Queue 'construction' ramrods */ 254 q_params->cmd = BNX2X_Q_CMD_INIT; 255 rc = bnx2x_queue_state_change(bp, q_params); 256 if (rc) 257 goto out; 258 259 memcpy(&q_params->params.setup, &qctor->prep_qsetup, 260 sizeof(struct bnx2x_queue_setup_params)); 261 q_params->cmd = BNX2X_Q_CMD_SETUP; 262 rc = bnx2x_queue_state_change(bp, q_params); 263 if (rc) 264 goto out; 265 266 /* enable interrupts */ 267 bnx2x_vf_igu_ack_sb(bp, vf, vf_igu_sb(vf, bnx2x_vfq(vf, qid, sb_idx)), 268 USTORM_ID, 0, IGU_INT_ENABLE, 0); 269 out: 270 return rc; 271 } 272 273 static int bnx2x_vf_queue_destroy(struct bnx2x *bp, struct bnx2x_virtf *vf, 274 int qid) 275 { 276 enum bnx2x_queue_cmd cmds[] = {BNX2X_Q_CMD_HALT, 277 BNX2X_Q_CMD_TERMINATE, 278 BNX2X_Q_CMD_CFC_DEL}; 279 struct bnx2x_queue_state_params q_params; 280 int rc, i; 281 282 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 283 284 /* Prepare ramrod information */ 285 memset(&q_params, 0, sizeof(struct bnx2x_queue_state_params)); 286 q_params.q_obj = &bnx2x_vfq(vf, qid, sp_obj); 287 set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 288 289 if (bnx2x_get_q_logical_state(bp, q_params.q_obj) == 290 BNX2X_Q_LOGICAL_STATE_STOPPED) { 291 DP(BNX2X_MSG_IOV, "queue was already stopped. Aborting gracefully\n"); 292 goto out; 293 } 294 295 /* Run Queue 'destruction' ramrods */ 296 for (i = 0; i < ARRAY_SIZE(cmds); i++) { 297 q_params.cmd = cmds[i]; 298 rc = bnx2x_queue_state_change(bp, &q_params); 299 if (rc) { 300 BNX2X_ERR("Failed to run Queue command %d\n", cmds[i]); 301 return rc; 302 } 303 } 304 out: 305 /* Clean Context */ 306 if (bnx2x_vfq(vf, qid, cxt)) { 307 bnx2x_vfq(vf, qid, cxt)->ustorm_ag_context.cdu_usage = 0; 308 bnx2x_vfq(vf, qid, cxt)->xstorm_ag_context.cdu_reserved = 0; 309 } 310 311 return 0; 312 } 313 314 static void 315 bnx2x_vf_set_igu_info(struct bnx2x *bp, u8 igu_sb_id, u8 abs_vfid) 316 { 317 struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid); 318 if (vf) { 319 /* the first igu entry belonging to VFs of this PF */ 320 if (!BP_VFDB(bp)->first_vf_igu_entry) 321 BP_VFDB(bp)->first_vf_igu_entry = igu_sb_id; 322 323 /* the first igu entry belonging to this VF */ 324 if (!vf_sb_count(vf)) 325 vf->igu_base_id = igu_sb_id; 326 327 ++vf_sb_count(vf); 328 ++vf->sb_count; 329 } 330 BP_VFDB(bp)->vf_sbs_pool++; 331 } 332 333 static inline void bnx2x_vf_vlan_credit(struct bnx2x *bp, 334 struct bnx2x_vlan_mac_obj *obj, 335 atomic_t *counter) 336 { 337 struct list_head *pos; 338 int read_lock; 339 int cnt = 0; 340 341 read_lock = bnx2x_vlan_mac_h_read_lock(bp, obj); 342 if (read_lock) 343 DP(BNX2X_MSG_SP, "Failed to take vlan mac read head; continuing anyway\n"); 344 345 list_for_each(pos, &obj->head) 346 cnt++; 347 348 if (!read_lock) 349 bnx2x_vlan_mac_h_read_unlock(bp, obj); 350 351 atomic_set(counter, cnt); 352 } 353 354 static int bnx2x_vf_vlan_mac_clear(struct bnx2x *bp, struct bnx2x_virtf *vf, 355 int qid, bool drv_only, int type) 356 { 357 struct bnx2x_vlan_mac_ramrod_params ramrod; 358 int rc; 359 360 DP(BNX2X_MSG_IOV, "vf[%d] - deleting all %s\n", vf->abs_vfid, 361 (type == BNX2X_VF_FILTER_VLAN_MAC) ? "VLAN-MACs" : 362 (type == BNX2X_VF_FILTER_MAC) ? "MACs" : "VLANs"); 363 364 /* Prepare ramrod params */ 365 memset(&ramrod, 0, sizeof(struct bnx2x_vlan_mac_ramrod_params)); 366 if (type == BNX2X_VF_FILTER_VLAN_MAC) { 367 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags); 368 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_mac_obj); 369 } else if (type == BNX2X_VF_FILTER_MAC) { 370 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags); 371 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, mac_obj); 372 } else { 373 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj); 374 } 375 ramrod.user_req.cmd = BNX2X_VLAN_MAC_DEL; 376 377 set_bit(RAMROD_EXEC, &ramrod.ramrod_flags); 378 if (drv_only) 379 set_bit(RAMROD_DRV_CLR_ONLY, &ramrod.ramrod_flags); 380 else 381 set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags); 382 383 /* Start deleting */ 384 rc = ramrod.vlan_mac_obj->delete_all(bp, 385 ramrod.vlan_mac_obj, 386 &ramrod.user_req.vlan_mac_flags, 387 &ramrod.ramrod_flags); 388 if (rc) { 389 BNX2X_ERR("Failed to delete all %s\n", 390 (type == BNX2X_VF_FILTER_VLAN_MAC) ? "VLAN-MACs" : 391 (type == BNX2X_VF_FILTER_MAC) ? "MACs" : "VLANs"); 392 return rc; 393 } 394 395 return 0; 396 } 397 398 static int bnx2x_vf_mac_vlan_config(struct bnx2x *bp, 399 struct bnx2x_virtf *vf, int qid, 400 struct bnx2x_vf_mac_vlan_filter *filter, 401 bool drv_only) 402 { 403 struct bnx2x_vlan_mac_ramrod_params ramrod; 404 int rc; 405 406 DP(BNX2X_MSG_IOV, "vf[%d] - %s a %s filter\n", 407 vf->abs_vfid, filter->add ? "Adding" : "Deleting", 408 (filter->type == BNX2X_VF_FILTER_VLAN_MAC) ? "VLAN-MAC" : 409 (filter->type == BNX2X_VF_FILTER_MAC) ? "MAC" : "VLAN"); 410 411 /* Prepare ramrod params */ 412 memset(&ramrod, 0, sizeof(struct bnx2x_vlan_mac_ramrod_params)); 413 if (filter->type == BNX2X_VF_FILTER_VLAN_MAC) { 414 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_mac_obj); 415 ramrod.user_req.u.vlan.vlan = filter->vid; 416 memcpy(&ramrod.user_req.u.mac.mac, filter->mac, ETH_ALEN); 417 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags); 418 } else if (filter->type == BNX2X_VF_FILTER_VLAN) { 419 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj); 420 ramrod.user_req.u.vlan.vlan = filter->vid; 421 } else { 422 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags); 423 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, mac_obj); 424 memcpy(&ramrod.user_req.u.mac.mac, filter->mac, ETH_ALEN); 425 } 426 ramrod.user_req.cmd = filter->add ? BNX2X_VLAN_MAC_ADD : 427 BNX2X_VLAN_MAC_DEL; 428 429 set_bit(RAMROD_EXEC, &ramrod.ramrod_flags); 430 if (drv_only) 431 set_bit(RAMROD_DRV_CLR_ONLY, &ramrod.ramrod_flags); 432 else 433 set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags); 434 435 /* Add/Remove the filter */ 436 rc = bnx2x_config_vlan_mac(bp, &ramrod); 437 if (rc && rc != -EEXIST) { 438 BNX2X_ERR("Failed to %s %s\n", 439 filter->add ? "add" : "delete", 440 (filter->type == BNX2X_VF_FILTER_VLAN_MAC) ? 441 "VLAN-MAC" : 442 (filter->type == BNX2X_VF_FILTER_MAC) ? 443 "MAC" : "VLAN"); 444 return rc; 445 } 446 447 return 0; 448 } 449 450 int bnx2x_vf_mac_vlan_config_list(struct bnx2x *bp, struct bnx2x_virtf *vf, 451 struct bnx2x_vf_mac_vlan_filters *filters, 452 int qid, bool drv_only) 453 { 454 int rc = 0, i; 455 456 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 457 458 if (!bnx2x_validate_vf_sp_objs(bp, vf, true)) 459 return -EINVAL; 460 461 /* Prepare ramrod params */ 462 for (i = 0; i < filters->count; i++) { 463 rc = bnx2x_vf_mac_vlan_config(bp, vf, qid, 464 &filters->filters[i], drv_only); 465 if (rc) 466 break; 467 } 468 469 /* Rollback if needed */ 470 if (i != filters->count) { 471 BNX2X_ERR("Managed only %d/%d filters - rolling back\n", 472 i, filters->count + 1); 473 while (--i >= 0) { 474 filters->filters[i].add = !filters->filters[i].add; 475 bnx2x_vf_mac_vlan_config(bp, vf, qid, 476 &filters->filters[i], 477 drv_only); 478 } 479 } 480 481 /* It's our responsibility to free the filters */ 482 kfree(filters); 483 484 return rc; 485 } 486 487 int bnx2x_vf_queue_setup(struct bnx2x *bp, struct bnx2x_virtf *vf, int qid, 488 struct bnx2x_vf_queue_construct_params *qctor) 489 { 490 int rc; 491 492 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); 493 494 rc = bnx2x_vf_queue_create(bp, vf, qid, qctor); 495 if (rc) 496 goto op_err; 497 498 /* Schedule the configuration of any pending vlan filters */ 499 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_HYPERVISOR_VLAN, 500 BNX2X_MSG_IOV); 501 return 0; 502 op_err: 503 BNX2X_ERR("QSETUP[%d:%d] error: rc %d\n", vf->abs_vfid, qid, rc); 504 return rc; 505 } 506 507 static int bnx2x_vf_queue_flr(struct bnx2x *bp, struct bnx2x_virtf *vf, 508 int qid) 509 { 510 int rc; 511 512 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); 513 514 /* If needed, clean the filtering data base */ 515 if ((qid == LEADING_IDX) && 516 bnx2x_validate_vf_sp_objs(bp, vf, false)) { 517 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true, 518 BNX2X_VF_FILTER_VLAN_MAC); 519 if (rc) 520 goto op_err; 521 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true, 522 BNX2X_VF_FILTER_VLAN); 523 if (rc) 524 goto op_err; 525 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true, 526 BNX2X_VF_FILTER_MAC); 527 if (rc) 528 goto op_err; 529 } 530 531 /* Terminate queue */ 532 if (bnx2x_vfq(vf, qid, sp_obj).state != BNX2X_Q_STATE_RESET) { 533 struct bnx2x_queue_state_params qstate; 534 535 memset(&qstate, 0, sizeof(struct bnx2x_queue_state_params)); 536 qstate.q_obj = &bnx2x_vfq(vf, qid, sp_obj); 537 qstate.q_obj->state = BNX2X_Q_STATE_STOPPED; 538 qstate.cmd = BNX2X_Q_CMD_TERMINATE; 539 set_bit(RAMROD_COMP_WAIT, &qstate.ramrod_flags); 540 rc = bnx2x_queue_state_change(bp, &qstate); 541 if (rc) 542 goto op_err; 543 } 544 545 return 0; 546 op_err: 547 BNX2X_ERR("vf[%d:%d] error: rc %d\n", vf->abs_vfid, qid, rc); 548 return rc; 549 } 550 551 int bnx2x_vf_mcast(struct bnx2x *bp, struct bnx2x_virtf *vf, 552 bnx2x_mac_addr_t *mcasts, int mc_num, bool drv_only) 553 { 554 struct bnx2x_mcast_list_elem *mc = NULL; 555 struct bnx2x_mcast_ramrod_params mcast; 556 int rc, i; 557 558 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 559 560 /* Prepare Multicast command */ 561 memset(&mcast, 0, sizeof(struct bnx2x_mcast_ramrod_params)); 562 mcast.mcast_obj = &vf->mcast_obj; 563 if (drv_only) 564 set_bit(RAMROD_DRV_CLR_ONLY, &mcast.ramrod_flags); 565 else 566 set_bit(RAMROD_COMP_WAIT, &mcast.ramrod_flags); 567 if (mc_num) { 568 mc = kzalloc(mc_num * sizeof(struct bnx2x_mcast_list_elem), 569 GFP_KERNEL); 570 if (!mc) { 571 BNX2X_ERR("Cannot Configure multicasts due to lack of memory\n"); 572 return -ENOMEM; 573 } 574 } 575 576 /* clear existing mcasts */ 577 mcast.mcast_list_len = vf->mcast_list_len; 578 vf->mcast_list_len = mc_num; 579 rc = bnx2x_config_mcast(bp, &mcast, BNX2X_MCAST_CMD_DEL); 580 if (rc) { 581 BNX2X_ERR("Failed to remove multicasts\n"); 582 kfree(mc); 583 return rc; 584 } 585 586 /* update mcast list on the ramrod params */ 587 if (mc_num) { 588 INIT_LIST_HEAD(&mcast.mcast_list); 589 for (i = 0; i < mc_num; i++) { 590 mc[i].mac = mcasts[i]; 591 list_add_tail(&mc[i].link, 592 &mcast.mcast_list); 593 } 594 595 /* add new mcasts */ 596 mcast.mcast_list_len = mc_num; 597 rc = bnx2x_config_mcast(bp, &mcast, BNX2X_MCAST_CMD_ADD); 598 if (rc) 599 BNX2X_ERR("Faled to add multicasts\n"); 600 kfree(mc); 601 } 602 603 return rc; 604 } 605 606 static void bnx2x_vf_prep_rx_mode(struct bnx2x *bp, u8 qid, 607 struct bnx2x_rx_mode_ramrod_params *ramrod, 608 struct bnx2x_virtf *vf, 609 unsigned long accept_flags) 610 { 611 struct bnx2x_vf_queue *vfq = vfq_get(vf, qid); 612 613 memset(ramrod, 0, sizeof(*ramrod)); 614 ramrod->cid = vfq->cid; 615 ramrod->cl_id = vfq_cl_id(vf, vfq); 616 ramrod->rx_mode_obj = &bp->rx_mode_obj; 617 ramrod->func_id = FW_VF_HANDLE(vf->abs_vfid); 618 ramrod->rx_accept_flags = accept_flags; 619 ramrod->tx_accept_flags = accept_flags; 620 ramrod->pstate = &vf->filter_state; 621 ramrod->state = BNX2X_FILTER_RX_MODE_PENDING; 622 623 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &vf->filter_state); 624 set_bit(RAMROD_RX, &ramrod->ramrod_flags); 625 set_bit(RAMROD_TX, &ramrod->ramrod_flags); 626 627 ramrod->rdata = bnx2x_vf_sp(bp, vf, rx_mode_rdata.e2); 628 ramrod->rdata_mapping = bnx2x_vf_sp_map(bp, vf, rx_mode_rdata.e2); 629 } 630 631 int bnx2x_vf_rxmode(struct bnx2x *bp, struct bnx2x_virtf *vf, 632 int qid, unsigned long accept_flags) 633 { 634 struct bnx2x_rx_mode_ramrod_params ramrod; 635 636 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 637 638 bnx2x_vf_prep_rx_mode(bp, qid, &ramrod, vf, accept_flags); 639 set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags); 640 vfq_get(vf, qid)->accept_flags = ramrod.rx_accept_flags; 641 return bnx2x_config_rx_mode(bp, &ramrod); 642 } 643 644 int bnx2x_vf_queue_teardown(struct bnx2x *bp, struct bnx2x_virtf *vf, int qid) 645 { 646 int rc; 647 648 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); 649 650 /* Remove all classification configuration for leading queue */ 651 if (qid == LEADING_IDX) { 652 rc = bnx2x_vf_rxmode(bp, vf, qid, 0); 653 if (rc) 654 goto op_err; 655 656 /* Remove filtering if feasible */ 657 if (bnx2x_validate_vf_sp_objs(bp, vf, true)) { 658 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, 659 false, 660 BNX2X_VF_FILTER_VLAN_MAC); 661 if (rc) 662 goto op_err; 663 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, 664 false, 665 BNX2X_VF_FILTER_VLAN); 666 if (rc) 667 goto op_err; 668 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, 669 false, 670 BNX2X_VF_FILTER_MAC); 671 if (rc) 672 goto op_err; 673 rc = bnx2x_vf_mcast(bp, vf, NULL, 0, false); 674 if (rc) 675 goto op_err; 676 } 677 } 678 679 /* Destroy queue */ 680 rc = bnx2x_vf_queue_destroy(bp, vf, qid); 681 if (rc) 682 goto op_err; 683 return rc; 684 op_err: 685 BNX2X_ERR("vf[%d:%d] error: rc %d\n", 686 vf->abs_vfid, qid, rc); 687 return rc; 688 } 689 690 /* VF enable primitives 691 * when pretend is required the caller is responsible 692 * for calling pretend prior to calling these routines 693 */ 694 695 /* internal vf enable - until vf is enabled internally all transactions 696 * are blocked. This routine should always be called last with pretend. 697 */ 698 static void bnx2x_vf_enable_internal(struct bnx2x *bp, u8 enable) 699 { 700 REG_WR(bp, PGLUE_B_REG_INTERNAL_VFID_ENABLE, enable ? 1 : 0); 701 } 702 703 /* clears vf error in all semi blocks */ 704 static void bnx2x_vf_semi_clear_err(struct bnx2x *bp, u8 abs_vfid) 705 { 706 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, abs_vfid); 707 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, abs_vfid); 708 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, abs_vfid); 709 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, abs_vfid); 710 } 711 712 static void bnx2x_vf_pglue_clear_err(struct bnx2x *bp, u8 abs_vfid) 713 { 714 u32 was_err_group = (2 * BP_PATH(bp) + abs_vfid) >> 5; 715 u32 was_err_reg = 0; 716 717 switch (was_err_group) { 718 case 0: 719 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR; 720 break; 721 case 1: 722 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR; 723 break; 724 case 2: 725 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR; 726 break; 727 case 3: 728 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR; 729 break; 730 } 731 REG_WR(bp, was_err_reg, 1 << (abs_vfid & 0x1f)); 732 } 733 734 static void bnx2x_vf_igu_reset(struct bnx2x *bp, struct bnx2x_virtf *vf) 735 { 736 int i; 737 u32 val; 738 739 /* Set VF masks and configuration - pretend */ 740 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); 741 742 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 743 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 744 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); 745 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); 746 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); 747 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); 748 749 val = REG_RD(bp, IGU_REG_VF_CONFIGURATION); 750 val |= (IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_MSI_MSIX_EN); 751 val &= ~IGU_VF_CONF_PARENT_MASK; 752 val |= (BP_ABS_FUNC(bp) >> 1) << IGU_VF_CONF_PARENT_SHIFT; 753 REG_WR(bp, IGU_REG_VF_CONFIGURATION, val); 754 755 DP(BNX2X_MSG_IOV, 756 "value in IGU_REG_VF_CONFIGURATION of vf %d after write is 0x%08x\n", 757 vf->abs_vfid, val); 758 759 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 760 761 /* iterate over all queues, clear sb consumer */ 762 for (i = 0; i < vf_sb_count(vf); i++) { 763 u8 igu_sb_id = vf_igu_sb(vf, i); 764 765 /* zero prod memory */ 766 REG_WR(bp, IGU_REG_PROD_CONS_MEMORY + igu_sb_id * 4, 0); 767 768 /* clear sb state machine */ 769 bnx2x_igu_clear_sb_gen(bp, vf->abs_vfid, igu_sb_id, 770 false /* VF */); 771 772 /* disable + update */ 773 bnx2x_vf_igu_ack_sb(bp, vf, igu_sb_id, USTORM_ID, 0, 774 IGU_INT_DISABLE, 1); 775 } 776 } 777 778 void bnx2x_vf_enable_access(struct bnx2x *bp, u8 abs_vfid) 779 { 780 /* set the VF-PF association in the FW */ 781 storm_memset_vf_to_pf(bp, FW_VF_HANDLE(abs_vfid), BP_FUNC(bp)); 782 storm_memset_func_en(bp, FW_VF_HANDLE(abs_vfid), 1); 783 784 /* clear vf errors*/ 785 bnx2x_vf_semi_clear_err(bp, abs_vfid); 786 bnx2x_vf_pglue_clear_err(bp, abs_vfid); 787 788 /* internal vf-enable - pretend */ 789 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, abs_vfid)); 790 DP(BNX2X_MSG_IOV, "enabling internal access for vf %x\n", abs_vfid); 791 bnx2x_vf_enable_internal(bp, true); 792 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 793 } 794 795 static void bnx2x_vf_enable_traffic(struct bnx2x *bp, struct bnx2x_virtf *vf) 796 { 797 /* Reset vf in IGU interrupts are still disabled */ 798 bnx2x_vf_igu_reset(bp, vf); 799 800 /* pretend to enable the vf with the PBF */ 801 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); 802 REG_WR(bp, PBF_REG_DISABLE_VF, 0); 803 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 804 } 805 806 static u8 bnx2x_vf_is_pcie_pending(struct bnx2x *bp, u8 abs_vfid) 807 { 808 struct pci_dev *dev; 809 struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid); 810 811 if (!vf) 812 return false; 813 814 dev = pci_get_bus_and_slot(vf->bus, vf->devfn); 815 if (dev) 816 return bnx2x_is_pcie_pending(dev); 817 return false; 818 } 819 820 int bnx2x_vf_flr_clnup_epilog(struct bnx2x *bp, u8 abs_vfid) 821 { 822 /* Verify no pending pci transactions */ 823 if (bnx2x_vf_is_pcie_pending(bp, abs_vfid)) 824 BNX2X_ERR("PCIE Transactions still pending\n"); 825 826 return 0; 827 } 828 829 /* must be called after the number of PF queues and the number of VFs are 830 * both known 831 */ 832 static void 833 bnx2x_iov_static_resc(struct bnx2x *bp, struct bnx2x_virtf *vf) 834 { 835 struct vf_pf_resc_request *resc = &vf->alloc_resc; 836 837 /* will be set only during VF-ACQUIRE */ 838 resc->num_rxqs = 0; 839 resc->num_txqs = 0; 840 841 resc->num_mac_filters = VF_MAC_CREDIT_CNT; 842 resc->num_vlan_filters = VF_VLAN_CREDIT_CNT; 843 844 /* no real limitation */ 845 resc->num_mc_filters = 0; 846 847 /* num_sbs already set */ 848 resc->num_sbs = vf->sb_count; 849 } 850 851 /* FLR routines: */ 852 static void bnx2x_vf_free_resc(struct bnx2x *bp, struct bnx2x_virtf *vf) 853 { 854 /* reset the state variables */ 855 bnx2x_iov_static_resc(bp, vf); 856 vf->state = VF_FREE; 857 } 858 859 static void bnx2x_vf_flr_clnup_hw(struct bnx2x *bp, struct bnx2x_virtf *vf) 860 { 861 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); 862 863 /* DQ usage counter */ 864 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); 865 bnx2x_flr_clnup_poll_hw_counter(bp, DORQ_REG_VF_USAGE_CNT, 866 "DQ VF usage counter timed out", 867 poll_cnt); 868 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 869 870 /* FW cleanup command - poll for the results */ 871 if (bnx2x_send_final_clnup(bp, (u8)FW_VF_HANDLE(vf->abs_vfid), 872 poll_cnt)) 873 BNX2X_ERR("VF[%d] Final cleanup timed-out\n", vf->abs_vfid); 874 875 /* verify TX hw is flushed */ 876 bnx2x_tx_hw_flushed(bp, poll_cnt); 877 } 878 879 static void bnx2x_vf_flr(struct bnx2x *bp, struct bnx2x_virtf *vf) 880 { 881 int rc, i; 882 883 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 884 885 /* the cleanup operations are valid if and only if the VF 886 * was first acquired. 887 */ 888 for (i = 0; i < vf_rxq_count(vf); i++) { 889 rc = bnx2x_vf_queue_flr(bp, vf, i); 890 if (rc) 891 goto out; 892 } 893 894 /* remove multicasts */ 895 bnx2x_vf_mcast(bp, vf, NULL, 0, true); 896 897 /* dispatch final cleanup and wait for HW queues to flush */ 898 bnx2x_vf_flr_clnup_hw(bp, vf); 899 900 /* release VF resources */ 901 bnx2x_vf_free_resc(bp, vf); 902 903 /* re-open the mailbox */ 904 bnx2x_vf_enable_mbx(bp, vf->abs_vfid); 905 return; 906 out: 907 BNX2X_ERR("vf[%d:%d] failed flr: rc %d\n", 908 vf->abs_vfid, i, rc); 909 } 910 911 static void bnx2x_vf_flr_clnup(struct bnx2x *bp) 912 { 913 struct bnx2x_virtf *vf; 914 int i; 915 916 for (i = 0; i < BNX2X_NR_VIRTFN(bp); i++) { 917 /* VF should be RESET & in FLR cleanup states */ 918 if (bnx2x_vf(bp, i, state) != VF_RESET || 919 !bnx2x_vf(bp, i, flr_clnup_stage)) 920 continue; 921 922 DP(BNX2X_MSG_IOV, "next vf to cleanup: %d. Num of vfs: %d\n", 923 i, BNX2X_NR_VIRTFN(bp)); 924 925 vf = BP_VF(bp, i); 926 927 /* lock the vf pf channel */ 928 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_FLR); 929 930 /* invoke the VF FLR SM */ 931 bnx2x_vf_flr(bp, vf); 932 933 /* mark the VF to be ACKED and continue */ 934 vf->flr_clnup_stage = false; 935 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_FLR); 936 } 937 938 /* Acknowledge the handled VFs. 939 * we are acknowledge all the vfs which an flr was requested for, even 940 * if amongst them there are such that we never opened, since the mcp 941 * will interrupt us immediately again if we only ack some of the bits, 942 * resulting in an endless loop. This can happen for example in KVM 943 * where an 'all ones' flr request is sometimes given by hyper visor 944 */ 945 DP(BNX2X_MSG_MCP, "DRV_STATUS_VF_DISABLED ACK for vfs 0x%x 0x%x\n", 946 bp->vfdb->flrd_vfs[0], bp->vfdb->flrd_vfs[1]); 947 for (i = 0; i < FLRD_VFS_DWORDS; i++) 948 SHMEM2_WR(bp, drv_ack_vf_disabled[BP_FW_MB_IDX(bp)][i], 949 bp->vfdb->flrd_vfs[i]); 950 951 bnx2x_fw_command(bp, DRV_MSG_CODE_VF_DISABLED_DONE, 0); 952 953 /* clear the acked bits - better yet if the MCP implemented 954 * write to clear semantics 955 */ 956 for (i = 0; i < FLRD_VFS_DWORDS; i++) 957 SHMEM2_WR(bp, drv_ack_vf_disabled[BP_FW_MB_IDX(bp)][i], 0); 958 } 959 960 void bnx2x_vf_handle_flr_event(struct bnx2x *bp) 961 { 962 int i; 963 964 /* Read FLR'd VFs */ 965 for (i = 0; i < FLRD_VFS_DWORDS; i++) 966 bp->vfdb->flrd_vfs[i] = SHMEM2_RD(bp, mcp_vf_disabled[i]); 967 968 DP(BNX2X_MSG_MCP, 969 "DRV_STATUS_VF_DISABLED received for vfs 0x%x 0x%x\n", 970 bp->vfdb->flrd_vfs[0], bp->vfdb->flrd_vfs[1]); 971 972 for_each_vf(bp, i) { 973 struct bnx2x_virtf *vf = BP_VF(bp, i); 974 u32 reset = 0; 975 976 if (vf->abs_vfid < 32) 977 reset = bp->vfdb->flrd_vfs[0] & (1 << vf->abs_vfid); 978 else 979 reset = bp->vfdb->flrd_vfs[1] & 980 (1 << (vf->abs_vfid - 32)); 981 982 if (reset) { 983 /* set as reset and ready for cleanup */ 984 vf->state = VF_RESET; 985 vf->flr_clnup_stage = true; 986 987 DP(BNX2X_MSG_IOV, 988 "Initiating Final cleanup for VF %d\n", 989 vf->abs_vfid); 990 } 991 } 992 993 /* do the FLR cleanup for all marked VFs*/ 994 bnx2x_vf_flr_clnup(bp); 995 } 996 997 /* IOV global initialization routines */ 998 void bnx2x_iov_init_dq(struct bnx2x *bp) 999 { 1000 if (!IS_SRIOV(bp)) 1001 return; 1002 1003 /* Set the DQ such that the CID reflect the abs_vfid */ 1004 REG_WR(bp, DORQ_REG_VF_NORM_VF_BASE, 0); 1005 REG_WR(bp, DORQ_REG_MAX_RVFID_SIZE, ilog2(BNX2X_MAX_NUM_OF_VFS)); 1006 1007 /* Set VFs starting CID. If its > 0 the preceding CIDs are belong to 1008 * the PF L2 queues 1009 */ 1010 REG_WR(bp, DORQ_REG_VF_NORM_CID_BASE, BNX2X_FIRST_VF_CID); 1011 1012 /* The VF window size is the log2 of the max number of CIDs per VF */ 1013 REG_WR(bp, DORQ_REG_VF_NORM_CID_WND_SIZE, BNX2X_VF_CID_WND); 1014 1015 /* The VF doorbell size 0 - *B, 4 - 128B. We set it here to match 1016 * the Pf doorbell size although the 2 are independent. 1017 */ 1018 REG_WR(bp, DORQ_REG_VF_NORM_CID_OFST, 3); 1019 1020 /* No security checks for now - 1021 * configure single rule (out of 16) mask = 0x1, value = 0x0, 1022 * CID range 0 - 0x1ffff 1023 */ 1024 REG_WR(bp, DORQ_REG_VF_TYPE_MASK_0, 1); 1025 REG_WR(bp, DORQ_REG_VF_TYPE_VALUE_0, 0); 1026 REG_WR(bp, DORQ_REG_VF_TYPE_MIN_MCID_0, 0); 1027 REG_WR(bp, DORQ_REG_VF_TYPE_MAX_MCID_0, 0x1ffff); 1028 1029 /* set the VF doorbell threshold. This threshold represents the amount 1030 * of doorbells allowed in the main DORQ fifo for a specific VF. 1031 */ 1032 REG_WR(bp, DORQ_REG_VF_USAGE_CT_LIMIT, 64); 1033 } 1034 1035 void bnx2x_iov_init_dmae(struct bnx2x *bp) 1036 { 1037 if (pci_find_ext_capability(bp->pdev, PCI_EXT_CAP_ID_SRIOV)) 1038 REG_WR(bp, DMAE_REG_BACKWARD_COMP_EN, 0); 1039 } 1040 1041 static int bnx2x_vf_bus(struct bnx2x *bp, int vfid) 1042 { 1043 struct pci_dev *dev = bp->pdev; 1044 struct bnx2x_sriov *iov = &bp->vfdb->sriov; 1045 1046 return dev->bus->number + ((dev->devfn + iov->offset + 1047 iov->stride * vfid) >> 8); 1048 } 1049 1050 static int bnx2x_vf_devfn(struct bnx2x *bp, int vfid) 1051 { 1052 struct pci_dev *dev = bp->pdev; 1053 struct bnx2x_sriov *iov = &bp->vfdb->sriov; 1054 1055 return (dev->devfn + iov->offset + iov->stride * vfid) & 0xff; 1056 } 1057 1058 static void bnx2x_vf_set_bars(struct bnx2x *bp, struct bnx2x_virtf *vf) 1059 { 1060 int i, n; 1061 struct pci_dev *dev = bp->pdev; 1062 struct bnx2x_sriov *iov = &bp->vfdb->sriov; 1063 1064 for (i = 0, n = 0; i < PCI_SRIOV_NUM_BARS; i += 2, n++) { 1065 u64 start = pci_resource_start(dev, PCI_IOV_RESOURCES + i); 1066 u32 size = pci_resource_len(dev, PCI_IOV_RESOURCES + i); 1067 1068 size /= iov->total; 1069 vf->bars[n].bar = start + size * vf->abs_vfid; 1070 vf->bars[n].size = size; 1071 } 1072 } 1073 1074 static int bnx2x_ari_enabled(struct pci_dev *dev) 1075 { 1076 return dev->bus->self && dev->bus->self->ari_enabled; 1077 } 1078 1079 static int 1080 bnx2x_get_vf_igu_cam_info(struct bnx2x *bp) 1081 { 1082 int sb_id; 1083 u32 val; 1084 u8 fid, current_pf = 0; 1085 1086 /* IGU in normal mode - read CAM */ 1087 for (sb_id = 0; sb_id < IGU_REG_MAPPING_MEMORY_SIZE; sb_id++) { 1088 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + sb_id * 4); 1089 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) 1090 continue; 1091 fid = GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID); 1092 if (fid & IGU_FID_ENCODE_IS_PF) 1093 current_pf = fid & IGU_FID_PF_NUM_MASK; 1094 else if (current_pf == BP_FUNC(bp)) 1095 bnx2x_vf_set_igu_info(bp, sb_id, 1096 (fid & IGU_FID_VF_NUM_MASK)); 1097 DP(BNX2X_MSG_IOV, "%s[%d], igu_sb_id=%d, msix=%d\n", 1098 ((fid & IGU_FID_ENCODE_IS_PF) ? "PF" : "VF"), 1099 ((fid & IGU_FID_ENCODE_IS_PF) ? (fid & IGU_FID_PF_NUM_MASK) : 1100 (fid & IGU_FID_VF_NUM_MASK)), sb_id, 1101 GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)); 1102 } 1103 DP(BNX2X_MSG_IOV, "vf_sbs_pool is %d\n", BP_VFDB(bp)->vf_sbs_pool); 1104 return BP_VFDB(bp)->vf_sbs_pool; 1105 } 1106 1107 static void __bnx2x_iov_free_vfdb(struct bnx2x *bp) 1108 { 1109 if (bp->vfdb) { 1110 kfree(bp->vfdb->vfqs); 1111 kfree(bp->vfdb->vfs); 1112 kfree(bp->vfdb); 1113 } 1114 bp->vfdb = NULL; 1115 } 1116 1117 static int bnx2x_sriov_pci_cfg_info(struct bnx2x *bp, struct bnx2x_sriov *iov) 1118 { 1119 int pos; 1120 struct pci_dev *dev = bp->pdev; 1121 1122 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV); 1123 if (!pos) { 1124 BNX2X_ERR("failed to find SRIOV capability in device\n"); 1125 return -ENODEV; 1126 } 1127 1128 iov->pos = pos; 1129 DP(BNX2X_MSG_IOV, "sriov ext pos %d\n", pos); 1130 pci_read_config_word(dev, pos + PCI_SRIOV_CTRL, &iov->ctrl); 1131 pci_read_config_word(dev, pos + PCI_SRIOV_TOTAL_VF, &iov->total); 1132 pci_read_config_word(dev, pos + PCI_SRIOV_INITIAL_VF, &iov->initial); 1133 pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &iov->offset); 1134 pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &iov->stride); 1135 pci_read_config_dword(dev, pos + PCI_SRIOV_SUP_PGSIZE, &iov->pgsz); 1136 pci_read_config_dword(dev, pos + PCI_SRIOV_CAP, &iov->cap); 1137 pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link); 1138 1139 return 0; 1140 } 1141 1142 static int bnx2x_sriov_info(struct bnx2x *bp, struct bnx2x_sriov *iov) 1143 { 1144 u32 val; 1145 1146 /* read the SRIOV capability structure 1147 * The fields can be read via configuration read or 1148 * directly from the device (starting at offset PCICFG_OFFSET) 1149 */ 1150 if (bnx2x_sriov_pci_cfg_info(bp, iov)) 1151 return -ENODEV; 1152 1153 /* get the number of SRIOV bars */ 1154 iov->nres = 0; 1155 1156 /* read the first_vfid */ 1157 val = REG_RD(bp, PCICFG_OFFSET + GRC_CONFIG_REG_PF_INIT_VF); 1158 iov->first_vf_in_pf = ((val & GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK) 1159 * 8) - (BNX2X_MAX_NUM_OF_VFS * BP_PATH(bp)); 1160 1161 DP(BNX2X_MSG_IOV, 1162 "IOV info[%d]: first vf %d, nres %d, cap 0x%x, ctrl 0x%x, total %d, initial %d, num vfs %d, offset %d, stride %d, page size 0x%x\n", 1163 BP_FUNC(bp), 1164 iov->first_vf_in_pf, iov->nres, iov->cap, iov->ctrl, iov->total, 1165 iov->initial, iov->nr_virtfn, iov->offset, iov->stride, iov->pgsz); 1166 1167 return 0; 1168 } 1169 1170 /* must be called after PF bars are mapped */ 1171 int bnx2x_iov_init_one(struct bnx2x *bp, int int_mode_param, 1172 int num_vfs_param) 1173 { 1174 int err, i; 1175 struct bnx2x_sriov *iov; 1176 struct pci_dev *dev = bp->pdev; 1177 1178 bp->vfdb = NULL; 1179 1180 /* verify is pf */ 1181 if (IS_VF(bp)) 1182 return 0; 1183 1184 /* verify sriov capability is present in configuration space */ 1185 if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV)) 1186 return 0; 1187 1188 /* verify chip revision */ 1189 if (CHIP_IS_E1x(bp)) 1190 return 0; 1191 1192 /* check if SRIOV support is turned off */ 1193 if (!num_vfs_param) 1194 return 0; 1195 1196 /* SRIOV assumes that num of PF CIDs < BNX2X_FIRST_VF_CID */ 1197 if (BNX2X_L2_MAX_CID(bp) >= BNX2X_FIRST_VF_CID) { 1198 BNX2X_ERR("PF cids %d are overspilling into vf space (starts at %d). Abort SRIOV\n", 1199 BNX2X_L2_MAX_CID(bp), BNX2X_FIRST_VF_CID); 1200 return 0; 1201 } 1202 1203 /* SRIOV can be enabled only with MSIX */ 1204 if (int_mode_param == BNX2X_INT_MODE_MSI || 1205 int_mode_param == BNX2X_INT_MODE_INTX) { 1206 BNX2X_ERR("Forced MSI/INTx mode is incompatible with SRIOV\n"); 1207 return 0; 1208 } 1209 1210 err = -EIO; 1211 /* verify ari is enabled */ 1212 if (!bnx2x_ari_enabled(bp->pdev)) { 1213 BNX2X_ERR("ARI not supported (check pci bridge ARI forwarding), SRIOV can not be enabled\n"); 1214 return 0; 1215 } 1216 1217 /* verify igu is in normal mode */ 1218 if (CHIP_INT_MODE_IS_BC(bp)) { 1219 BNX2X_ERR("IGU not normal mode, SRIOV can not be enabled\n"); 1220 return 0; 1221 } 1222 1223 /* allocate the vfs database */ 1224 bp->vfdb = kzalloc(sizeof(*(bp->vfdb)), GFP_KERNEL); 1225 if (!bp->vfdb) { 1226 BNX2X_ERR("failed to allocate vf database\n"); 1227 err = -ENOMEM; 1228 goto failed; 1229 } 1230 1231 /* get the sriov info - Linux already collected all the pertinent 1232 * information, however the sriov structure is for the private use 1233 * of the pci module. Also we want this information regardless 1234 * of the hyper-visor. 1235 */ 1236 iov = &(bp->vfdb->sriov); 1237 err = bnx2x_sriov_info(bp, iov); 1238 if (err) 1239 goto failed; 1240 1241 /* SR-IOV capability was enabled but there are no VFs*/ 1242 if (iov->total == 0) 1243 goto failed; 1244 1245 iov->nr_virtfn = min_t(u16, iov->total, num_vfs_param); 1246 1247 DP(BNX2X_MSG_IOV, "num_vfs_param was %d, nr_virtfn was %d\n", 1248 num_vfs_param, iov->nr_virtfn); 1249 1250 /* allocate the vf array */ 1251 bp->vfdb->vfs = kzalloc(sizeof(struct bnx2x_virtf) * 1252 BNX2X_NR_VIRTFN(bp), GFP_KERNEL); 1253 if (!bp->vfdb->vfs) { 1254 BNX2X_ERR("failed to allocate vf array\n"); 1255 err = -ENOMEM; 1256 goto failed; 1257 } 1258 1259 /* Initial VF init - index and abs_vfid - nr_virtfn must be set */ 1260 for_each_vf(bp, i) { 1261 bnx2x_vf(bp, i, index) = i; 1262 bnx2x_vf(bp, i, abs_vfid) = iov->first_vf_in_pf + i; 1263 bnx2x_vf(bp, i, state) = VF_FREE; 1264 mutex_init(&bnx2x_vf(bp, i, op_mutex)); 1265 bnx2x_vf(bp, i, op_current) = CHANNEL_TLV_NONE; 1266 } 1267 1268 /* re-read the IGU CAM for VFs - index and abs_vfid must be set */ 1269 if (!bnx2x_get_vf_igu_cam_info(bp)) { 1270 BNX2X_ERR("No entries in IGU CAM for vfs\n"); 1271 err = -EINVAL; 1272 goto failed; 1273 } 1274 1275 /* allocate the queue arrays for all VFs */ 1276 bp->vfdb->vfqs = kzalloc( 1277 BNX2X_MAX_NUM_VF_QUEUES * sizeof(struct bnx2x_vf_queue), 1278 GFP_KERNEL); 1279 1280 if (!bp->vfdb->vfqs) { 1281 BNX2X_ERR("failed to allocate vf queue array\n"); 1282 err = -ENOMEM; 1283 goto failed; 1284 } 1285 1286 /* Prepare the VFs event synchronization mechanism */ 1287 mutex_init(&bp->vfdb->event_mutex); 1288 1289 mutex_init(&bp->vfdb->bulletin_mutex); 1290 1291 if (SHMEM2_HAS(bp, sriov_switch_mode)) 1292 SHMEM2_WR(bp, sriov_switch_mode, SRIOV_SWITCH_MODE_VEB); 1293 1294 return 0; 1295 failed: 1296 DP(BNX2X_MSG_IOV, "Failed err=%d\n", err); 1297 __bnx2x_iov_free_vfdb(bp); 1298 return err; 1299 } 1300 1301 void bnx2x_iov_remove_one(struct bnx2x *bp) 1302 { 1303 int vf_idx; 1304 1305 /* if SRIOV is not enabled there's nothing to do */ 1306 if (!IS_SRIOV(bp)) 1307 return; 1308 1309 bnx2x_disable_sriov(bp); 1310 1311 /* disable access to all VFs */ 1312 for (vf_idx = 0; vf_idx < bp->vfdb->sriov.total; vf_idx++) { 1313 bnx2x_pretend_func(bp, 1314 HW_VF_HANDLE(bp, 1315 bp->vfdb->sriov.first_vf_in_pf + 1316 vf_idx)); 1317 DP(BNX2X_MSG_IOV, "disabling internal access for vf %d\n", 1318 bp->vfdb->sriov.first_vf_in_pf + vf_idx); 1319 bnx2x_vf_enable_internal(bp, 0); 1320 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 1321 } 1322 1323 /* free vf database */ 1324 __bnx2x_iov_free_vfdb(bp); 1325 } 1326 1327 void bnx2x_iov_free_mem(struct bnx2x *bp) 1328 { 1329 int i; 1330 1331 if (!IS_SRIOV(bp)) 1332 return; 1333 1334 /* free vfs hw contexts */ 1335 for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) { 1336 struct hw_dma *cxt = &bp->vfdb->context[i]; 1337 BNX2X_PCI_FREE(cxt->addr, cxt->mapping, cxt->size); 1338 } 1339 1340 BNX2X_PCI_FREE(BP_VFDB(bp)->sp_dma.addr, 1341 BP_VFDB(bp)->sp_dma.mapping, 1342 BP_VFDB(bp)->sp_dma.size); 1343 1344 BNX2X_PCI_FREE(BP_VF_MBX_DMA(bp)->addr, 1345 BP_VF_MBX_DMA(bp)->mapping, 1346 BP_VF_MBX_DMA(bp)->size); 1347 1348 BNX2X_PCI_FREE(BP_VF_BULLETIN_DMA(bp)->addr, 1349 BP_VF_BULLETIN_DMA(bp)->mapping, 1350 BP_VF_BULLETIN_DMA(bp)->size); 1351 } 1352 1353 int bnx2x_iov_alloc_mem(struct bnx2x *bp) 1354 { 1355 size_t tot_size; 1356 int i, rc = 0; 1357 1358 if (!IS_SRIOV(bp)) 1359 return rc; 1360 1361 /* allocate vfs hw contexts */ 1362 tot_size = (BP_VFDB(bp)->sriov.first_vf_in_pf + BNX2X_NR_VIRTFN(bp)) * 1363 BNX2X_CIDS_PER_VF * sizeof(union cdu_context); 1364 1365 for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) { 1366 struct hw_dma *cxt = BP_VF_CXT_PAGE(bp, i); 1367 cxt->size = min_t(size_t, tot_size, CDU_ILT_PAGE_SZ); 1368 1369 if (cxt->size) { 1370 cxt->addr = BNX2X_PCI_ALLOC(&cxt->mapping, cxt->size); 1371 if (!cxt->addr) 1372 goto alloc_mem_err; 1373 } else { 1374 cxt->addr = NULL; 1375 cxt->mapping = 0; 1376 } 1377 tot_size -= cxt->size; 1378 } 1379 1380 /* allocate vfs ramrods dma memory - client_init and set_mac */ 1381 tot_size = BNX2X_NR_VIRTFN(bp) * sizeof(struct bnx2x_vf_sp); 1382 BP_VFDB(bp)->sp_dma.addr = BNX2X_PCI_ALLOC(&BP_VFDB(bp)->sp_dma.mapping, 1383 tot_size); 1384 if (!BP_VFDB(bp)->sp_dma.addr) 1385 goto alloc_mem_err; 1386 BP_VFDB(bp)->sp_dma.size = tot_size; 1387 1388 /* allocate mailboxes */ 1389 tot_size = BNX2X_NR_VIRTFN(bp) * MBX_MSG_ALIGNED_SIZE; 1390 BP_VF_MBX_DMA(bp)->addr = BNX2X_PCI_ALLOC(&BP_VF_MBX_DMA(bp)->mapping, 1391 tot_size); 1392 if (!BP_VF_MBX_DMA(bp)->addr) 1393 goto alloc_mem_err; 1394 1395 BP_VF_MBX_DMA(bp)->size = tot_size; 1396 1397 /* allocate local bulletin boards */ 1398 tot_size = BNX2X_NR_VIRTFN(bp) * BULLETIN_CONTENT_SIZE; 1399 BP_VF_BULLETIN_DMA(bp)->addr = BNX2X_PCI_ALLOC(&BP_VF_BULLETIN_DMA(bp)->mapping, 1400 tot_size); 1401 if (!BP_VF_BULLETIN_DMA(bp)->addr) 1402 goto alloc_mem_err; 1403 1404 BP_VF_BULLETIN_DMA(bp)->size = tot_size; 1405 1406 return 0; 1407 1408 alloc_mem_err: 1409 return -ENOMEM; 1410 } 1411 1412 static void bnx2x_vfq_init(struct bnx2x *bp, struct bnx2x_virtf *vf, 1413 struct bnx2x_vf_queue *q) 1414 { 1415 u8 cl_id = vfq_cl_id(vf, q); 1416 u8 func_id = FW_VF_HANDLE(vf->abs_vfid); 1417 unsigned long q_type = 0; 1418 1419 set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 1420 set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 1421 1422 /* Queue State object */ 1423 bnx2x_init_queue_obj(bp, &q->sp_obj, 1424 cl_id, &q->cid, 1, func_id, 1425 bnx2x_vf_sp(bp, vf, q_data), 1426 bnx2x_vf_sp_map(bp, vf, q_data), 1427 q_type); 1428 1429 /* sp indication is set only when vlan/mac/etc. are initialized */ 1430 q->sp_initialized = false; 1431 1432 DP(BNX2X_MSG_IOV, 1433 "initialized vf %d's queue object. func id set to %d. cid set to 0x%x\n", 1434 vf->abs_vfid, q->sp_obj.func_id, q->cid); 1435 } 1436 1437 static int bnx2x_max_speed_cap(struct bnx2x *bp) 1438 { 1439 u32 supported = bp->port.supported[bnx2x_get_link_cfg_idx(bp)]; 1440 1441 if (supported & 1442 (SUPPORTED_20000baseMLD2_Full | SUPPORTED_20000baseKR2_Full)) 1443 return 20000; 1444 1445 return 10000; /* assume lowest supported speed is 10G */ 1446 } 1447 1448 int bnx2x_iov_link_update_vf(struct bnx2x *bp, int idx) 1449 { 1450 struct bnx2x_link_report_data *state = &bp->last_reported_link; 1451 struct pf_vf_bulletin_content *bulletin; 1452 struct bnx2x_virtf *vf; 1453 bool update = true; 1454 int rc = 0; 1455 1456 /* sanity and init */ 1457 rc = bnx2x_vf_op_prep(bp, idx, &vf, &bulletin, false); 1458 if (rc) 1459 return rc; 1460 1461 mutex_lock(&bp->vfdb->bulletin_mutex); 1462 1463 if (vf->link_cfg == IFLA_VF_LINK_STATE_AUTO) { 1464 bulletin->valid_bitmap |= 1 << LINK_VALID; 1465 1466 bulletin->link_speed = state->line_speed; 1467 bulletin->link_flags = 0; 1468 if (test_bit(BNX2X_LINK_REPORT_LINK_DOWN, 1469 &state->link_report_flags)) 1470 bulletin->link_flags |= VFPF_LINK_REPORT_LINK_DOWN; 1471 if (test_bit(BNX2X_LINK_REPORT_FD, 1472 &state->link_report_flags)) 1473 bulletin->link_flags |= VFPF_LINK_REPORT_FULL_DUPLEX; 1474 if (test_bit(BNX2X_LINK_REPORT_RX_FC_ON, 1475 &state->link_report_flags)) 1476 bulletin->link_flags |= VFPF_LINK_REPORT_RX_FC_ON; 1477 if (test_bit(BNX2X_LINK_REPORT_TX_FC_ON, 1478 &state->link_report_flags)) 1479 bulletin->link_flags |= VFPF_LINK_REPORT_TX_FC_ON; 1480 } else if (vf->link_cfg == IFLA_VF_LINK_STATE_DISABLE && 1481 !(bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN)) { 1482 bulletin->valid_bitmap |= 1 << LINK_VALID; 1483 bulletin->link_flags |= VFPF_LINK_REPORT_LINK_DOWN; 1484 } else if (vf->link_cfg == IFLA_VF_LINK_STATE_ENABLE && 1485 (bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN)) { 1486 bulletin->valid_bitmap |= 1 << LINK_VALID; 1487 bulletin->link_speed = bnx2x_max_speed_cap(bp); 1488 bulletin->link_flags &= ~VFPF_LINK_REPORT_LINK_DOWN; 1489 } else { 1490 update = false; 1491 } 1492 1493 if (update) { 1494 DP(NETIF_MSG_LINK | BNX2X_MSG_IOV, 1495 "vf %d mode %u speed %d flags %x\n", idx, 1496 vf->link_cfg, bulletin->link_speed, bulletin->link_flags); 1497 1498 /* Post update on VF's bulletin board */ 1499 rc = bnx2x_post_vf_bulletin(bp, idx); 1500 if (rc) { 1501 BNX2X_ERR("failed to update VF[%d] bulletin\n", idx); 1502 goto out; 1503 } 1504 } 1505 1506 out: 1507 mutex_unlock(&bp->vfdb->bulletin_mutex); 1508 return rc; 1509 } 1510 1511 int bnx2x_set_vf_link_state(struct net_device *dev, int idx, int link_state) 1512 { 1513 struct bnx2x *bp = netdev_priv(dev); 1514 struct bnx2x_virtf *vf = BP_VF(bp, idx); 1515 1516 if (!vf) 1517 return -EINVAL; 1518 1519 if (vf->link_cfg == link_state) 1520 return 0; /* nothing todo */ 1521 1522 vf->link_cfg = link_state; 1523 1524 return bnx2x_iov_link_update_vf(bp, idx); 1525 } 1526 1527 void bnx2x_iov_link_update(struct bnx2x *bp) 1528 { 1529 int vfid; 1530 1531 if (!IS_SRIOV(bp)) 1532 return; 1533 1534 for_each_vf(bp, vfid) 1535 bnx2x_iov_link_update_vf(bp, vfid); 1536 } 1537 1538 /* called by bnx2x_nic_load */ 1539 int bnx2x_iov_nic_init(struct bnx2x *bp) 1540 { 1541 int vfid; 1542 1543 if (!IS_SRIOV(bp)) { 1544 DP(BNX2X_MSG_IOV, "vfdb was not allocated\n"); 1545 return 0; 1546 } 1547 1548 DP(BNX2X_MSG_IOV, "num of vfs: %d\n", (bp)->vfdb->sriov.nr_virtfn); 1549 1550 /* let FLR complete ... */ 1551 msleep(100); 1552 1553 /* initialize vf database */ 1554 for_each_vf(bp, vfid) { 1555 struct bnx2x_virtf *vf = BP_VF(bp, vfid); 1556 1557 int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vfid) * 1558 BNX2X_CIDS_PER_VF; 1559 1560 union cdu_context *base_cxt = (union cdu_context *) 1561 BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr + 1562 (base_vf_cid & (ILT_PAGE_CIDS-1)); 1563 1564 DP(BNX2X_MSG_IOV, 1565 "VF[%d] Max IGU SBs: %d, base vf cid 0x%x, base cid 0x%x, base cxt %p\n", 1566 vf->abs_vfid, vf_sb_count(vf), base_vf_cid, 1567 BNX2X_FIRST_VF_CID + base_vf_cid, base_cxt); 1568 1569 /* init statically provisioned resources */ 1570 bnx2x_iov_static_resc(bp, vf); 1571 1572 /* queues are initialized during VF-ACQUIRE */ 1573 vf->filter_state = 0; 1574 vf->sp_cl_id = bnx2x_fp(bp, 0, cl_id); 1575 1576 bnx2x_init_credit_pool(&vf->vf_vlans_pool, 0, 1577 vf_vlan_rules_cnt(vf)); 1578 bnx2x_init_credit_pool(&vf->vf_macs_pool, 0, 1579 vf_mac_rules_cnt(vf)); 1580 1581 /* init mcast object - This object will be re-initialized 1582 * during VF-ACQUIRE with the proper cl_id and cid. 1583 * It needs to be initialized here so that it can be safely 1584 * handled by a subsequent FLR flow. 1585 */ 1586 vf->mcast_list_len = 0; 1587 bnx2x_init_mcast_obj(bp, &vf->mcast_obj, 0xFF, 1588 0xFF, 0xFF, 0xFF, 1589 bnx2x_vf_sp(bp, vf, mcast_rdata), 1590 bnx2x_vf_sp_map(bp, vf, mcast_rdata), 1591 BNX2X_FILTER_MCAST_PENDING, 1592 &vf->filter_state, 1593 BNX2X_OBJ_TYPE_RX_TX); 1594 1595 /* set the mailbox message addresses */ 1596 BP_VF_MBX(bp, vfid)->msg = (struct bnx2x_vf_mbx_msg *) 1597 (((u8 *)BP_VF_MBX_DMA(bp)->addr) + vfid * 1598 MBX_MSG_ALIGNED_SIZE); 1599 1600 BP_VF_MBX(bp, vfid)->msg_mapping = BP_VF_MBX_DMA(bp)->mapping + 1601 vfid * MBX_MSG_ALIGNED_SIZE; 1602 1603 /* Enable vf mailbox */ 1604 bnx2x_vf_enable_mbx(bp, vf->abs_vfid); 1605 } 1606 1607 /* Final VF init */ 1608 for_each_vf(bp, vfid) { 1609 struct bnx2x_virtf *vf = BP_VF(bp, vfid); 1610 1611 /* fill in the BDF and bars */ 1612 vf->bus = bnx2x_vf_bus(bp, vfid); 1613 vf->devfn = bnx2x_vf_devfn(bp, vfid); 1614 bnx2x_vf_set_bars(bp, vf); 1615 1616 DP(BNX2X_MSG_IOV, 1617 "VF info[%d]: bus 0x%x, devfn 0x%x, bar0 [0x%x, %d], bar1 [0x%x, %d], bar2 [0x%x, %d]\n", 1618 vf->abs_vfid, vf->bus, vf->devfn, 1619 (unsigned)vf->bars[0].bar, vf->bars[0].size, 1620 (unsigned)vf->bars[1].bar, vf->bars[1].size, 1621 (unsigned)vf->bars[2].bar, vf->bars[2].size); 1622 } 1623 1624 return 0; 1625 } 1626 1627 /* called by bnx2x_chip_cleanup */ 1628 int bnx2x_iov_chip_cleanup(struct bnx2x *bp) 1629 { 1630 int i; 1631 1632 if (!IS_SRIOV(bp)) 1633 return 0; 1634 1635 /* release all the VFs */ 1636 for_each_vf(bp, i) 1637 bnx2x_vf_release(bp, BP_VF(bp, i)); 1638 1639 return 0; 1640 } 1641 1642 /* called by bnx2x_init_hw_func, returns the next ilt line */ 1643 int bnx2x_iov_init_ilt(struct bnx2x *bp, u16 line) 1644 { 1645 int i; 1646 struct bnx2x_ilt *ilt = BP_ILT(bp); 1647 1648 if (!IS_SRIOV(bp)) 1649 return line; 1650 1651 /* set vfs ilt lines */ 1652 for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) { 1653 struct hw_dma *hw_cxt = BP_VF_CXT_PAGE(bp, i); 1654 1655 ilt->lines[line+i].page = hw_cxt->addr; 1656 ilt->lines[line+i].page_mapping = hw_cxt->mapping; 1657 ilt->lines[line+i].size = hw_cxt->size; /* doesn't matter */ 1658 } 1659 return line + i; 1660 } 1661 1662 static u8 bnx2x_iov_is_vf_cid(struct bnx2x *bp, u16 cid) 1663 { 1664 return ((cid >= BNX2X_FIRST_VF_CID) && 1665 ((cid - BNX2X_FIRST_VF_CID) < BNX2X_VF_CIDS)); 1666 } 1667 1668 static 1669 void bnx2x_vf_handle_classification_eqe(struct bnx2x *bp, 1670 struct bnx2x_vf_queue *vfq, 1671 union event_ring_elem *elem) 1672 { 1673 unsigned long ramrod_flags = 0; 1674 int rc = 0; 1675 1676 /* Always push next commands out, don't wait here */ 1677 set_bit(RAMROD_CONT, &ramrod_flags); 1678 1679 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { 1680 case BNX2X_FILTER_MAC_PENDING: 1681 rc = vfq->mac_obj.complete(bp, &vfq->mac_obj, elem, 1682 &ramrod_flags); 1683 break; 1684 case BNX2X_FILTER_VLAN_PENDING: 1685 rc = vfq->vlan_obj.complete(bp, &vfq->vlan_obj, elem, 1686 &ramrod_flags); 1687 break; 1688 default: 1689 BNX2X_ERR("Unsupported classification command: %d\n", 1690 elem->message.data.eth_event.echo); 1691 return; 1692 } 1693 if (rc < 0) 1694 BNX2X_ERR("Failed to schedule new commands: %d\n", rc); 1695 else if (rc > 0) 1696 DP(BNX2X_MSG_IOV, "Scheduled next pending commands...\n"); 1697 } 1698 1699 static 1700 void bnx2x_vf_handle_mcast_eqe(struct bnx2x *bp, 1701 struct bnx2x_virtf *vf) 1702 { 1703 struct bnx2x_mcast_ramrod_params rparam = {NULL}; 1704 int rc; 1705 1706 rparam.mcast_obj = &vf->mcast_obj; 1707 vf->mcast_obj.raw.clear_pending(&vf->mcast_obj.raw); 1708 1709 /* If there are pending mcast commands - send them */ 1710 if (vf->mcast_obj.check_pending(&vf->mcast_obj)) { 1711 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 1712 if (rc < 0) 1713 BNX2X_ERR("Failed to send pending mcast commands: %d\n", 1714 rc); 1715 } 1716 } 1717 1718 static 1719 void bnx2x_vf_handle_filters_eqe(struct bnx2x *bp, 1720 struct bnx2x_virtf *vf) 1721 { 1722 smp_mb__before_atomic(); 1723 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &vf->filter_state); 1724 smp_mb__after_atomic(); 1725 } 1726 1727 static void bnx2x_vf_handle_rss_update_eqe(struct bnx2x *bp, 1728 struct bnx2x_virtf *vf) 1729 { 1730 vf->rss_conf_obj.raw.clear_pending(&vf->rss_conf_obj.raw); 1731 } 1732 1733 int bnx2x_iov_eq_sp_event(struct bnx2x *bp, union event_ring_elem *elem) 1734 { 1735 struct bnx2x_virtf *vf; 1736 int qidx = 0, abs_vfid; 1737 u8 opcode; 1738 u16 cid = 0xffff; 1739 1740 if (!IS_SRIOV(bp)) 1741 return 1; 1742 1743 /* first get the cid - the only events we handle here are cfc-delete 1744 * and set-mac completion 1745 */ 1746 opcode = elem->message.opcode; 1747 1748 switch (opcode) { 1749 case EVENT_RING_OPCODE_CFC_DEL: 1750 cid = SW_CID((__force __le32) 1751 elem->message.data.cfc_del_event.cid); 1752 DP(BNX2X_MSG_IOV, "checking cfc-del comp cid=%d\n", cid); 1753 break; 1754 case EVENT_RING_OPCODE_CLASSIFICATION_RULES: 1755 case EVENT_RING_OPCODE_MULTICAST_RULES: 1756 case EVENT_RING_OPCODE_FILTERS_RULES: 1757 case EVENT_RING_OPCODE_RSS_UPDATE_RULES: 1758 cid = (elem->message.data.eth_event.echo & 1759 BNX2X_SWCID_MASK); 1760 DP(BNX2X_MSG_IOV, "checking filtering comp cid=%d\n", cid); 1761 break; 1762 case EVENT_RING_OPCODE_VF_FLR: 1763 abs_vfid = elem->message.data.vf_flr_event.vf_id; 1764 DP(BNX2X_MSG_IOV, "Got VF FLR notification abs_vfid=%d\n", 1765 abs_vfid); 1766 goto get_vf; 1767 case EVENT_RING_OPCODE_MALICIOUS_VF: 1768 abs_vfid = elem->message.data.malicious_vf_event.vf_id; 1769 BNX2X_ERR("Got VF MALICIOUS notification abs_vfid=%d err_id=0x%x\n", 1770 abs_vfid, 1771 elem->message.data.malicious_vf_event.err_id); 1772 goto get_vf; 1773 default: 1774 return 1; 1775 } 1776 1777 /* check if the cid is the VF range */ 1778 if (!bnx2x_iov_is_vf_cid(bp, cid)) { 1779 DP(BNX2X_MSG_IOV, "cid is outside vf range: %d\n", cid); 1780 return 1; 1781 } 1782 1783 /* extract vf and rxq index from vf_cid - relies on the following: 1784 * 1. vfid on cid reflects the true abs_vfid 1785 * 2. The max number of VFs (per path) is 64 1786 */ 1787 qidx = cid & ((1 << BNX2X_VF_CID_WND)-1); 1788 abs_vfid = (cid >> BNX2X_VF_CID_WND) & (BNX2X_MAX_NUM_OF_VFS-1); 1789 get_vf: 1790 vf = bnx2x_vf_by_abs_fid(bp, abs_vfid); 1791 1792 if (!vf) { 1793 BNX2X_ERR("EQ completion for unknown VF, cid %d, abs_vfid %d\n", 1794 cid, abs_vfid); 1795 return 0; 1796 } 1797 1798 switch (opcode) { 1799 case EVENT_RING_OPCODE_CFC_DEL: 1800 DP(BNX2X_MSG_IOV, "got VF [%d:%d] cfc delete ramrod\n", 1801 vf->abs_vfid, qidx); 1802 vfq_get(vf, qidx)->sp_obj.complete_cmd(bp, 1803 &vfq_get(vf, 1804 qidx)->sp_obj, 1805 BNX2X_Q_CMD_CFC_DEL); 1806 break; 1807 case EVENT_RING_OPCODE_CLASSIFICATION_RULES: 1808 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mac/vlan ramrod\n", 1809 vf->abs_vfid, qidx); 1810 bnx2x_vf_handle_classification_eqe(bp, vfq_get(vf, qidx), elem); 1811 break; 1812 case EVENT_RING_OPCODE_MULTICAST_RULES: 1813 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mcast ramrod\n", 1814 vf->abs_vfid, qidx); 1815 bnx2x_vf_handle_mcast_eqe(bp, vf); 1816 break; 1817 case EVENT_RING_OPCODE_FILTERS_RULES: 1818 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set rx-mode ramrod\n", 1819 vf->abs_vfid, qidx); 1820 bnx2x_vf_handle_filters_eqe(bp, vf); 1821 break; 1822 case EVENT_RING_OPCODE_RSS_UPDATE_RULES: 1823 DP(BNX2X_MSG_IOV, "got VF [%d:%d] RSS update ramrod\n", 1824 vf->abs_vfid, qidx); 1825 bnx2x_vf_handle_rss_update_eqe(bp, vf); 1826 case EVENT_RING_OPCODE_VF_FLR: 1827 case EVENT_RING_OPCODE_MALICIOUS_VF: 1828 /* Do nothing for now */ 1829 return 0; 1830 } 1831 1832 return 0; 1833 } 1834 1835 static struct bnx2x_virtf *bnx2x_vf_by_cid(struct bnx2x *bp, int vf_cid) 1836 { 1837 /* extract the vf from vf_cid - relies on the following: 1838 * 1. vfid on cid reflects the true abs_vfid 1839 * 2. The max number of VFs (per path) is 64 1840 */ 1841 int abs_vfid = (vf_cid >> BNX2X_VF_CID_WND) & (BNX2X_MAX_NUM_OF_VFS-1); 1842 return bnx2x_vf_by_abs_fid(bp, abs_vfid); 1843 } 1844 1845 void bnx2x_iov_set_queue_sp_obj(struct bnx2x *bp, int vf_cid, 1846 struct bnx2x_queue_sp_obj **q_obj) 1847 { 1848 struct bnx2x_virtf *vf; 1849 1850 if (!IS_SRIOV(bp)) 1851 return; 1852 1853 vf = bnx2x_vf_by_cid(bp, vf_cid); 1854 1855 if (vf) { 1856 /* extract queue index from vf_cid - relies on the following: 1857 * 1. vfid on cid reflects the true abs_vfid 1858 * 2. The max number of VFs (per path) is 64 1859 */ 1860 int q_index = vf_cid & ((1 << BNX2X_VF_CID_WND)-1); 1861 *q_obj = &bnx2x_vfq(vf, q_index, sp_obj); 1862 } else { 1863 BNX2X_ERR("No vf matching cid %d\n", vf_cid); 1864 } 1865 } 1866 1867 void bnx2x_iov_adjust_stats_req(struct bnx2x *bp) 1868 { 1869 int i; 1870 int first_queue_query_index, num_queues_req; 1871 dma_addr_t cur_data_offset; 1872 struct stats_query_entry *cur_query_entry; 1873 u8 stats_count = 0; 1874 bool is_fcoe = false; 1875 1876 if (!IS_SRIOV(bp)) 1877 return; 1878 1879 if (!NO_FCOE(bp)) 1880 is_fcoe = true; 1881 1882 /* fcoe adds one global request and one queue request */ 1883 num_queues_req = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe; 1884 first_queue_query_index = BNX2X_FIRST_QUEUE_QUERY_IDX - 1885 (is_fcoe ? 0 : 1); 1886 1887 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS), 1888 "BNX2X_NUM_ETH_QUEUES %d, is_fcoe %d, first_queue_query_index %d => determined the last non virtual statistics query index is %d. Will add queries on top of that\n", 1889 BNX2X_NUM_ETH_QUEUES(bp), is_fcoe, first_queue_query_index, 1890 first_queue_query_index + num_queues_req); 1891 1892 cur_data_offset = bp->fw_stats_data_mapping + 1893 offsetof(struct bnx2x_fw_stats_data, queue_stats) + 1894 num_queues_req * sizeof(struct per_queue_stats); 1895 1896 cur_query_entry = &bp->fw_stats_req-> 1897 query[first_queue_query_index + num_queues_req]; 1898 1899 for_each_vf(bp, i) { 1900 int j; 1901 struct bnx2x_virtf *vf = BP_VF(bp, i); 1902 1903 if (vf->state != VF_ENABLED) { 1904 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS), 1905 "vf %d not enabled so no stats for it\n", 1906 vf->abs_vfid); 1907 continue; 1908 } 1909 1910 DP(BNX2X_MSG_IOV, "add addresses for vf %d\n", vf->abs_vfid); 1911 for_each_vfq(vf, j) { 1912 struct bnx2x_vf_queue *rxq = vfq_get(vf, j); 1913 1914 dma_addr_t q_stats_addr = 1915 vf->fw_stat_map + j * vf->stats_stride; 1916 1917 /* collect stats fro active queues only */ 1918 if (bnx2x_get_q_logical_state(bp, &rxq->sp_obj) == 1919 BNX2X_Q_LOGICAL_STATE_STOPPED) 1920 continue; 1921 1922 /* create stats query entry for this queue */ 1923 cur_query_entry->kind = STATS_TYPE_QUEUE; 1924 cur_query_entry->index = vfq_stat_id(vf, rxq); 1925 cur_query_entry->funcID = 1926 cpu_to_le16(FW_VF_HANDLE(vf->abs_vfid)); 1927 cur_query_entry->address.hi = 1928 cpu_to_le32(U64_HI(q_stats_addr)); 1929 cur_query_entry->address.lo = 1930 cpu_to_le32(U64_LO(q_stats_addr)); 1931 DP(BNX2X_MSG_IOV, 1932 "added address %x %x for vf %d queue %d client %d\n", 1933 cur_query_entry->address.hi, 1934 cur_query_entry->address.lo, cur_query_entry->funcID, 1935 j, cur_query_entry->index); 1936 cur_query_entry++; 1937 cur_data_offset += sizeof(struct per_queue_stats); 1938 stats_count++; 1939 1940 /* all stats are coalesced to the leading queue */ 1941 if (vf->cfg_flags & VF_CFG_STATS_COALESCE) 1942 break; 1943 } 1944 } 1945 bp->fw_stats_req->hdr.cmd_num = bp->fw_stats_num + stats_count; 1946 } 1947 1948 /* VF API helpers */ 1949 static void bnx2x_vf_qtbl_set_q(struct bnx2x *bp, u8 abs_vfid, u8 qid, 1950 u8 enable) 1951 { 1952 u32 reg = PXP_REG_HST_ZONE_PERMISSION_TABLE + qid * 4; 1953 u32 val = enable ? (abs_vfid | (1 << 6)) : 0; 1954 1955 REG_WR(bp, reg, val); 1956 } 1957 1958 static void bnx2x_vf_clr_qtbl(struct bnx2x *bp, struct bnx2x_virtf *vf) 1959 { 1960 int i; 1961 1962 for_each_vfq(vf, i) 1963 bnx2x_vf_qtbl_set_q(bp, vf->abs_vfid, 1964 vfq_qzone_id(vf, vfq_get(vf, i)), false); 1965 } 1966 1967 static void bnx2x_vf_igu_disable(struct bnx2x *bp, struct bnx2x_virtf *vf) 1968 { 1969 u32 val; 1970 1971 /* clear the VF configuration - pretend */ 1972 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); 1973 val = REG_RD(bp, IGU_REG_VF_CONFIGURATION); 1974 val &= ~(IGU_VF_CONF_MSI_MSIX_EN | IGU_VF_CONF_SINGLE_ISR_EN | 1975 IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_PARENT_MASK); 1976 REG_WR(bp, IGU_REG_VF_CONFIGURATION, val); 1977 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 1978 } 1979 1980 u8 bnx2x_vf_max_queue_cnt(struct bnx2x *bp, struct bnx2x_virtf *vf) 1981 { 1982 return min_t(u8, min_t(u8, vf_sb_count(vf), BNX2X_CIDS_PER_VF), 1983 BNX2X_VF_MAX_QUEUES); 1984 } 1985 1986 static 1987 int bnx2x_vf_chk_avail_resc(struct bnx2x *bp, struct bnx2x_virtf *vf, 1988 struct vf_pf_resc_request *req_resc) 1989 { 1990 u8 rxq_cnt = vf_rxq_count(vf) ? : bnx2x_vf_max_queue_cnt(bp, vf); 1991 u8 txq_cnt = vf_txq_count(vf) ? : bnx2x_vf_max_queue_cnt(bp, vf); 1992 1993 return ((req_resc->num_rxqs <= rxq_cnt) && 1994 (req_resc->num_txqs <= txq_cnt) && 1995 (req_resc->num_sbs <= vf_sb_count(vf)) && 1996 (req_resc->num_mac_filters <= vf_mac_rules_cnt(vf)) && 1997 (req_resc->num_vlan_filters <= vf_vlan_rules_cnt(vf))); 1998 } 1999 2000 /* CORE VF API */ 2001 int bnx2x_vf_acquire(struct bnx2x *bp, struct bnx2x_virtf *vf, 2002 struct vf_pf_resc_request *resc) 2003 { 2004 int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vf->index) * 2005 BNX2X_CIDS_PER_VF; 2006 2007 union cdu_context *base_cxt = (union cdu_context *) 2008 BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr + 2009 (base_vf_cid & (ILT_PAGE_CIDS-1)); 2010 int i; 2011 2012 /* if state is 'acquired' the VF was not released or FLR'd, in 2013 * this case the returned resources match the acquired already 2014 * acquired resources. Verify that the requested numbers do 2015 * not exceed the already acquired numbers. 2016 */ 2017 if (vf->state == VF_ACQUIRED) { 2018 DP(BNX2X_MSG_IOV, "VF[%d] Trying to re-acquire resources (VF was not released or FLR'd)\n", 2019 vf->abs_vfid); 2020 2021 if (!bnx2x_vf_chk_avail_resc(bp, vf, resc)) { 2022 BNX2X_ERR("VF[%d] When re-acquiring resources, requested numbers must be <= then previously acquired numbers\n", 2023 vf->abs_vfid); 2024 return -EINVAL; 2025 } 2026 return 0; 2027 } 2028 2029 /* Otherwise vf state must be 'free' or 'reset' */ 2030 if (vf->state != VF_FREE && vf->state != VF_RESET) { 2031 BNX2X_ERR("VF[%d] Can not acquire a VF with state %d\n", 2032 vf->abs_vfid, vf->state); 2033 return -EINVAL; 2034 } 2035 2036 /* static allocation: 2037 * the global maximum number are fixed per VF. Fail the request if 2038 * requested number exceed these globals 2039 */ 2040 if (!bnx2x_vf_chk_avail_resc(bp, vf, resc)) { 2041 DP(BNX2X_MSG_IOV, 2042 "cannot fulfill vf resource request. Placing maximal available values in response\n"); 2043 /* set the max resource in the vf */ 2044 return -ENOMEM; 2045 } 2046 2047 /* Set resources counters - 0 request means max available */ 2048 vf_sb_count(vf) = resc->num_sbs; 2049 vf_rxq_count(vf) = resc->num_rxqs ? : bnx2x_vf_max_queue_cnt(bp, vf); 2050 vf_txq_count(vf) = resc->num_txqs ? : bnx2x_vf_max_queue_cnt(bp, vf); 2051 2052 DP(BNX2X_MSG_IOV, 2053 "Fulfilling vf request: sb count %d, tx_count %d, rx_count %d, mac_rules_count %d, vlan_rules_count %d\n", 2054 vf_sb_count(vf), vf_rxq_count(vf), 2055 vf_txq_count(vf), vf_mac_rules_cnt(vf), 2056 vf_vlan_rules_cnt(vf)); 2057 2058 /* Initialize the queues */ 2059 if (!vf->vfqs) { 2060 DP(BNX2X_MSG_IOV, "vf->vfqs was not allocated\n"); 2061 return -EINVAL; 2062 } 2063 2064 for_each_vfq(vf, i) { 2065 struct bnx2x_vf_queue *q = vfq_get(vf, i); 2066 2067 if (!q) { 2068 BNX2X_ERR("q number %d was not allocated\n", i); 2069 return -EINVAL; 2070 } 2071 2072 q->index = i; 2073 q->cxt = &((base_cxt + i)->eth); 2074 q->cid = BNX2X_FIRST_VF_CID + base_vf_cid + i; 2075 2076 DP(BNX2X_MSG_IOV, "VFQ[%d:%d]: index %d, cid 0x%x, cxt %p\n", 2077 vf->abs_vfid, i, q->index, q->cid, q->cxt); 2078 2079 /* init SP objects */ 2080 bnx2x_vfq_init(bp, vf, q); 2081 } 2082 vf->state = VF_ACQUIRED; 2083 return 0; 2084 } 2085 2086 int bnx2x_vf_init(struct bnx2x *bp, struct bnx2x_virtf *vf, dma_addr_t *sb_map) 2087 { 2088 struct bnx2x_func_init_params func_init = {0}; 2089 int i; 2090 2091 /* the sb resources are initialized at this point, do the 2092 * FW/HW initializations 2093 */ 2094 for_each_vf_sb(vf, i) 2095 bnx2x_init_sb(bp, (dma_addr_t)sb_map[i], vf->abs_vfid, true, 2096 vf_igu_sb(vf, i), vf_igu_sb(vf, i)); 2097 2098 /* Sanity checks */ 2099 if (vf->state != VF_ACQUIRED) { 2100 DP(BNX2X_MSG_IOV, "VF[%d] is not in VF_ACQUIRED, but %d\n", 2101 vf->abs_vfid, vf->state); 2102 return -EINVAL; 2103 } 2104 2105 /* let FLR complete ... */ 2106 msleep(100); 2107 2108 /* FLR cleanup epilogue */ 2109 if (bnx2x_vf_flr_clnup_epilog(bp, vf->abs_vfid)) 2110 return -EBUSY; 2111 2112 /* reset IGU VF statistics: MSIX */ 2113 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + vf->abs_vfid * 4 , 0); 2114 2115 /* function setup */ 2116 func_init.pf_id = BP_FUNC(bp); 2117 func_init.func_id = FW_VF_HANDLE(vf->abs_vfid); 2118 bnx2x_func_init(bp, &func_init); 2119 2120 /* Enable the vf */ 2121 bnx2x_vf_enable_access(bp, vf->abs_vfid); 2122 bnx2x_vf_enable_traffic(bp, vf); 2123 2124 /* queue protection table */ 2125 for_each_vfq(vf, i) 2126 bnx2x_vf_qtbl_set_q(bp, vf->abs_vfid, 2127 vfq_qzone_id(vf, vfq_get(vf, i)), true); 2128 2129 vf->state = VF_ENABLED; 2130 2131 /* update vf bulletin board */ 2132 bnx2x_post_vf_bulletin(bp, vf->index); 2133 2134 return 0; 2135 } 2136 2137 struct set_vf_state_cookie { 2138 struct bnx2x_virtf *vf; 2139 u8 state; 2140 }; 2141 2142 static void bnx2x_set_vf_state(void *cookie) 2143 { 2144 struct set_vf_state_cookie *p = (struct set_vf_state_cookie *)cookie; 2145 2146 p->vf->state = p->state; 2147 } 2148 2149 int bnx2x_vf_close(struct bnx2x *bp, struct bnx2x_virtf *vf) 2150 { 2151 int rc = 0, i; 2152 2153 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 2154 2155 /* Close all queues */ 2156 for (i = 0; i < vf_rxq_count(vf); i++) { 2157 rc = bnx2x_vf_queue_teardown(bp, vf, i); 2158 if (rc) 2159 goto op_err; 2160 } 2161 2162 /* disable the interrupts */ 2163 DP(BNX2X_MSG_IOV, "disabling igu\n"); 2164 bnx2x_vf_igu_disable(bp, vf); 2165 2166 /* disable the VF */ 2167 DP(BNX2X_MSG_IOV, "clearing qtbl\n"); 2168 bnx2x_vf_clr_qtbl(bp, vf); 2169 2170 /* need to make sure there are no outstanding stats ramrods which may 2171 * cause the device to access the VF's stats buffer which it will free 2172 * as soon as we return from the close flow. 2173 */ 2174 { 2175 struct set_vf_state_cookie cookie; 2176 2177 cookie.vf = vf; 2178 cookie.state = VF_ACQUIRED; 2179 rc = bnx2x_stats_safe_exec(bp, bnx2x_set_vf_state, &cookie); 2180 if (rc) 2181 goto op_err; 2182 } 2183 2184 DP(BNX2X_MSG_IOV, "set state to acquired\n"); 2185 2186 return 0; 2187 op_err: 2188 BNX2X_ERR("vf[%d] CLOSE error: rc %d\n", vf->abs_vfid, rc); 2189 return rc; 2190 } 2191 2192 /* VF release can be called either: 1. The VF was acquired but 2193 * not enabled 2. the vf was enabled or in the process of being 2194 * enabled 2195 */ 2196 int bnx2x_vf_free(struct bnx2x *bp, struct bnx2x_virtf *vf) 2197 { 2198 int rc; 2199 2200 DP(BNX2X_MSG_IOV, "VF[%d] STATE: %s\n", vf->abs_vfid, 2201 vf->state == VF_FREE ? "Free" : 2202 vf->state == VF_ACQUIRED ? "Acquired" : 2203 vf->state == VF_ENABLED ? "Enabled" : 2204 vf->state == VF_RESET ? "Reset" : 2205 "Unknown"); 2206 2207 switch (vf->state) { 2208 case VF_ENABLED: 2209 rc = bnx2x_vf_close(bp, vf); 2210 if (rc) 2211 goto op_err; 2212 /* Fallthrough to release resources */ 2213 case VF_ACQUIRED: 2214 DP(BNX2X_MSG_IOV, "about to free resources\n"); 2215 bnx2x_vf_free_resc(bp, vf); 2216 break; 2217 2218 case VF_FREE: 2219 case VF_RESET: 2220 default: 2221 break; 2222 } 2223 return 0; 2224 op_err: 2225 BNX2X_ERR("VF[%d] RELEASE error: rc %d\n", vf->abs_vfid, rc); 2226 return rc; 2227 } 2228 2229 int bnx2x_vf_rss_update(struct bnx2x *bp, struct bnx2x_virtf *vf, 2230 struct bnx2x_config_rss_params *rss) 2231 { 2232 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 2233 set_bit(RAMROD_COMP_WAIT, &rss->ramrod_flags); 2234 return bnx2x_config_rss(bp, rss); 2235 } 2236 2237 int bnx2x_vf_tpa_update(struct bnx2x *bp, struct bnx2x_virtf *vf, 2238 struct vfpf_tpa_tlv *tlv, 2239 struct bnx2x_queue_update_tpa_params *params) 2240 { 2241 aligned_u64 *sge_addr = tlv->tpa_client_info.sge_addr; 2242 struct bnx2x_queue_state_params qstate; 2243 int qid, rc = 0; 2244 2245 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 2246 2247 /* Set ramrod params */ 2248 memset(&qstate, 0, sizeof(struct bnx2x_queue_state_params)); 2249 memcpy(&qstate.params.update_tpa, params, 2250 sizeof(struct bnx2x_queue_update_tpa_params)); 2251 qstate.cmd = BNX2X_Q_CMD_UPDATE_TPA; 2252 set_bit(RAMROD_COMP_WAIT, &qstate.ramrod_flags); 2253 2254 for (qid = 0; qid < vf_rxq_count(vf); qid++) { 2255 qstate.q_obj = &bnx2x_vfq(vf, qid, sp_obj); 2256 qstate.params.update_tpa.sge_map = sge_addr[qid]; 2257 DP(BNX2X_MSG_IOV, "sge_addr[%d:%d] %08x:%08x\n", 2258 vf->abs_vfid, qid, U64_HI(sge_addr[qid]), 2259 U64_LO(sge_addr[qid])); 2260 rc = bnx2x_queue_state_change(bp, &qstate); 2261 if (rc) { 2262 BNX2X_ERR("Failed to configure sge_addr %08x:%08x for [%d:%d]\n", 2263 U64_HI(sge_addr[qid]), U64_LO(sge_addr[qid]), 2264 vf->abs_vfid, qid); 2265 return rc; 2266 } 2267 } 2268 2269 return rc; 2270 } 2271 2272 /* VF release ~ VF close + VF release-resources 2273 * Release is the ultimate SW shutdown and is called whenever an 2274 * irrecoverable error is encountered. 2275 */ 2276 int bnx2x_vf_release(struct bnx2x *bp, struct bnx2x_virtf *vf) 2277 { 2278 int rc; 2279 2280 DP(BNX2X_MSG_IOV, "PF releasing vf %d\n", vf->abs_vfid); 2281 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_RELEASE_VF); 2282 2283 rc = bnx2x_vf_free(bp, vf); 2284 if (rc) 2285 WARN(rc, 2286 "VF[%d] Failed to allocate resources for release op- rc=%d\n", 2287 vf->abs_vfid, rc); 2288 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_RELEASE_VF); 2289 return rc; 2290 } 2291 2292 void bnx2x_lock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf, 2293 enum channel_tlvs tlv) 2294 { 2295 /* we don't lock the channel for unsupported tlvs */ 2296 if (!bnx2x_tlv_supported(tlv)) { 2297 BNX2X_ERR("attempting to lock with unsupported tlv. Aborting\n"); 2298 return; 2299 } 2300 2301 /* lock the channel */ 2302 mutex_lock(&vf->op_mutex); 2303 2304 /* record the locking op */ 2305 vf->op_current = tlv; 2306 2307 /* log the lock */ 2308 DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel locked by %d\n", 2309 vf->abs_vfid, tlv); 2310 } 2311 2312 void bnx2x_unlock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf, 2313 enum channel_tlvs expected_tlv) 2314 { 2315 enum channel_tlvs current_tlv; 2316 2317 if (!vf) { 2318 BNX2X_ERR("VF was %p\n", vf); 2319 return; 2320 } 2321 2322 current_tlv = vf->op_current; 2323 2324 /* we don't unlock the channel for unsupported tlvs */ 2325 if (!bnx2x_tlv_supported(expected_tlv)) 2326 return; 2327 2328 WARN(expected_tlv != vf->op_current, 2329 "lock mismatch: expected %d found %d", expected_tlv, 2330 vf->op_current); 2331 2332 /* record the locking op */ 2333 vf->op_current = CHANNEL_TLV_NONE; 2334 2335 /* lock the channel */ 2336 mutex_unlock(&vf->op_mutex); 2337 2338 /* log the unlock */ 2339 DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel unlocked by %d\n", 2340 vf->abs_vfid, current_tlv); 2341 } 2342 2343 static int bnx2x_set_pf_tx_switching(struct bnx2x *bp, bool enable) 2344 { 2345 struct bnx2x_queue_state_params q_params; 2346 u32 prev_flags; 2347 int i, rc; 2348 2349 /* Verify changes are needed and record current Tx switching state */ 2350 prev_flags = bp->flags; 2351 if (enable) 2352 bp->flags |= TX_SWITCHING; 2353 else 2354 bp->flags &= ~TX_SWITCHING; 2355 if (prev_flags == bp->flags) 2356 return 0; 2357 2358 /* Verify state enables the sending of queue ramrods */ 2359 if ((bp->state != BNX2X_STATE_OPEN) || 2360 (bnx2x_get_q_logical_state(bp, 2361 &bnx2x_sp_obj(bp, &bp->fp[0]).q_obj) != 2362 BNX2X_Q_LOGICAL_STATE_ACTIVE)) 2363 return 0; 2364 2365 /* send q. update ramrod to configure Tx switching */ 2366 memset(&q_params, 0, sizeof(q_params)); 2367 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 2368 q_params.cmd = BNX2X_Q_CMD_UPDATE; 2369 __set_bit(BNX2X_Q_UPDATE_TX_SWITCHING_CHNG, 2370 &q_params.params.update.update_flags); 2371 if (enable) 2372 __set_bit(BNX2X_Q_UPDATE_TX_SWITCHING, 2373 &q_params.params.update.update_flags); 2374 else 2375 __clear_bit(BNX2X_Q_UPDATE_TX_SWITCHING, 2376 &q_params.params.update.update_flags); 2377 2378 /* send the ramrod on all the queues of the PF */ 2379 for_each_eth_queue(bp, i) { 2380 struct bnx2x_fastpath *fp = &bp->fp[i]; 2381 2382 /* Set the appropriate Queue object */ 2383 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 2384 2385 /* Update the Queue state */ 2386 rc = bnx2x_queue_state_change(bp, &q_params); 2387 if (rc) { 2388 BNX2X_ERR("Failed to configure Tx switching\n"); 2389 return rc; 2390 } 2391 } 2392 2393 DP(BNX2X_MSG_IOV, "%s Tx Switching\n", enable ? "Enabled" : "Disabled"); 2394 return 0; 2395 } 2396 2397 int bnx2x_sriov_configure(struct pci_dev *dev, int num_vfs_param) 2398 { 2399 struct bnx2x *bp = netdev_priv(pci_get_drvdata(dev)); 2400 2401 if (!IS_SRIOV(bp)) { 2402 BNX2X_ERR("failed to configure SR-IOV since vfdb was not allocated. Check dmesg for errors in probe stage\n"); 2403 return -EINVAL; 2404 } 2405 2406 DP(BNX2X_MSG_IOV, "bnx2x_sriov_configure called with %d, BNX2X_NR_VIRTFN(bp) was %d\n", 2407 num_vfs_param, BNX2X_NR_VIRTFN(bp)); 2408 2409 /* HW channel is only operational when PF is up */ 2410 if (bp->state != BNX2X_STATE_OPEN) { 2411 BNX2X_ERR("VF num configuration via sysfs not supported while PF is down\n"); 2412 return -EINVAL; 2413 } 2414 2415 /* we are always bound by the total_vfs in the configuration space */ 2416 if (num_vfs_param > BNX2X_NR_VIRTFN(bp)) { 2417 BNX2X_ERR("truncating requested number of VFs (%d) down to maximum allowed (%d)\n", 2418 num_vfs_param, BNX2X_NR_VIRTFN(bp)); 2419 num_vfs_param = BNX2X_NR_VIRTFN(bp); 2420 } 2421 2422 bp->requested_nr_virtfn = num_vfs_param; 2423 if (num_vfs_param == 0) { 2424 bnx2x_set_pf_tx_switching(bp, false); 2425 bnx2x_disable_sriov(bp); 2426 return 0; 2427 } else { 2428 return bnx2x_enable_sriov(bp); 2429 } 2430 } 2431 2432 #define IGU_ENTRY_SIZE 4 2433 2434 int bnx2x_enable_sriov(struct bnx2x *bp) 2435 { 2436 int rc = 0, req_vfs = bp->requested_nr_virtfn; 2437 int vf_idx, sb_idx, vfq_idx, qcount, first_vf; 2438 u32 igu_entry, address; 2439 u16 num_vf_queues; 2440 2441 if (req_vfs == 0) 2442 return 0; 2443 2444 first_vf = bp->vfdb->sriov.first_vf_in_pf; 2445 2446 /* statically distribute vf sb pool between VFs */ 2447 num_vf_queues = min_t(u16, BNX2X_VF_MAX_QUEUES, 2448 BP_VFDB(bp)->vf_sbs_pool / req_vfs); 2449 2450 /* zero previous values learned from igu cam */ 2451 for (vf_idx = 0; vf_idx < req_vfs; vf_idx++) { 2452 struct bnx2x_virtf *vf = BP_VF(bp, vf_idx); 2453 2454 vf->sb_count = 0; 2455 vf_sb_count(BP_VF(bp, vf_idx)) = 0; 2456 } 2457 bp->vfdb->vf_sbs_pool = 0; 2458 2459 /* prepare IGU cam */ 2460 sb_idx = BP_VFDB(bp)->first_vf_igu_entry; 2461 address = IGU_REG_MAPPING_MEMORY + sb_idx * IGU_ENTRY_SIZE; 2462 for (vf_idx = first_vf; vf_idx < first_vf + req_vfs; vf_idx++) { 2463 for (vfq_idx = 0; vfq_idx < num_vf_queues; vfq_idx++) { 2464 igu_entry = vf_idx << IGU_REG_MAPPING_MEMORY_FID_SHIFT | 2465 vfq_idx << IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT | 2466 IGU_REG_MAPPING_MEMORY_VALID; 2467 DP(BNX2X_MSG_IOV, "assigning sb %d to vf %d\n", 2468 sb_idx, vf_idx); 2469 REG_WR(bp, address, igu_entry); 2470 sb_idx++; 2471 address += IGU_ENTRY_SIZE; 2472 } 2473 } 2474 2475 /* Reinitialize vf database according to igu cam */ 2476 bnx2x_get_vf_igu_cam_info(bp); 2477 2478 DP(BNX2X_MSG_IOV, "vf_sbs_pool %d, num_vf_queues %d\n", 2479 BP_VFDB(bp)->vf_sbs_pool, num_vf_queues); 2480 2481 qcount = 0; 2482 for_each_vf(bp, vf_idx) { 2483 struct bnx2x_virtf *vf = BP_VF(bp, vf_idx); 2484 2485 /* set local queue arrays */ 2486 vf->vfqs = &bp->vfdb->vfqs[qcount]; 2487 qcount += vf_sb_count(vf); 2488 bnx2x_iov_static_resc(bp, vf); 2489 } 2490 2491 /* prepare msix vectors in VF configuration space - the value in the 2492 * PCI configuration space should be the index of the last entry, 2493 * namely one less than the actual size of the table 2494 */ 2495 for (vf_idx = first_vf; vf_idx < first_vf + req_vfs; vf_idx++) { 2496 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf_idx)); 2497 REG_WR(bp, PCICFG_OFFSET + GRC_CONFIG_REG_VF_MSIX_CONTROL, 2498 num_vf_queues - 1); 2499 DP(BNX2X_MSG_IOV, "set msix vec num in VF %d cfg space to %d\n", 2500 vf_idx, num_vf_queues - 1); 2501 } 2502 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 2503 2504 /* enable sriov. This will probe all the VFs, and consequentially cause 2505 * the "acquire" messages to appear on the VF PF channel. 2506 */ 2507 DP(BNX2X_MSG_IOV, "about to call enable sriov\n"); 2508 bnx2x_disable_sriov(bp); 2509 2510 rc = bnx2x_set_pf_tx_switching(bp, true); 2511 if (rc) 2512 return rc; 2513 2514 rc = pci_enable_sriov(bp->pdev, req_vfs); 2515 if (rc) { 2516 BNX2X_ERR("pci_enable_sriov failed with %d\n", rc); 2517 return rc; 2518 } 2519 DP(BNX2X_MSG_IOV, "sriov enabled (%d vfs)\n", req_vfs); 2520 return req_vfs; 2521 } 2522 2523 void bnx2x_pf_set_vfs_vlan(struct bnx2x *bp) 2524 { 2525 int vfidx; 2526 struct pf_vf_bulletin_content *bulletin; 2527 2528 DP(BNX2X_MSG_IOV, "configuring vlan for VFs from sp-task\n"); 2529 for_each_vf(bp, vfidx) { 2530 bulletin = BP_VF_BULLETIN(bp, vfidx); 2531 if (bulletin->valid_bitmap & (1 << VLAN_VALID)) 2532 bnx2x_set_vf_vlan(bp->dev, vfidx, bulletin->vlan, 0); 2533 } 2534 } 2535 2536 void bnx2x_disable_sriov(struct bnx2x *bp) 2537 { 2538 if (pci_vfs_assigned(bp->pdev)) { 2539 DP(BNX2X_MSG_IOV, 2540 "Unloading driver while VFs are assigned - VFs will not be deallocated\n"); 2541 return; 2542 } 2543 2544 pci_disable_sriov(bp->pdev); 2545 } 2546 2547 static int bnx2x_vf_op_prep(struct bnx2x *bp, int vfidx, 2548 struct bnx2x_virtf **vf, 2549 struct pf_vf_bulletin_content **bulletin, 2550 bool test_queue) 2551 { 2552 if (bp->state != BNX2X_STATE_OPEN) { 2553 BNX2X_ERR("PF is down - can't utilize iov-related functionality\n"); 2554 return -EINVAL; 2555 } 2556 2557 if (!IS_SRIOV(bp)) { 2558 BNX2X_ERR("sriov is disabled - can't utilize iov-related functionality\n"); 2559 return -EINVAL; 2560 } 2561 2562 if (vfidx >= BNX2X_NR_VIRTFN(bp)) { 2563 BNX2X_ERR("VF is uninitialized - can't utilize iov-related functionality. vfidx was %d BNX2X_NR_VIRTFN was %d\n", 2564 vfidx, BNX2X_NR_VIRTFN(bp)); 2565 return -EINVAL; 2566 } 2567 2568 /* init members */ 2569 *vf = BP_VF(bp, vfidx); 2570 *bulletin = BP_VF_BULLETIN(bp, vfidx); 2571 2572 if (!*vf) { 2573 BNX2X_ERR("Unable to get VF structure for vfidx %d\n", vfidx); 2574 return -EINVAL; 2575 } 2576 2577 if (test_queue && !(*vf)->vfqs) { 2578 BNX2X_ERR("vfqs struct is null. Was this invoked before dynamically enabling SR-IOV? vfidx was %d\n", 2579 vfidx); 2580 return -EINVAL; 2581 } 2582 2583 if (!*bulletin) { 2584 BNX2X_ERR("Bulletin Board struct is null for vfidx %d\n", 2585 vfidx); 2586 return -EINVAL; 2587 } 2588 2589 return 0; 2590 } 2591 2592 int bnx2x_get_vf_config(struct net_device *dev, int vfidx, 2593 struct ifla_vf_info *ivi) 2594 { 2595 struct bnx2x *bp = netdev_priv(dev); 2596 struct bnx2x_virtf *vf = NULL; 2597 struct pf_vf_bulletin_content *bulletin = NULL; 2598 struct bnx2x_vlan_mac_obj *mac_obj; 2599 struct bnx2x_vlan_mac_obj *vlan_obj; 2600 int rc; 2601 2602 /* sanity and init */ 2603 rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true); 2604 if (rc) 2605 return rc; 2606 2607 mac_obj = &bnx2x_leading_vfq(vf, mac_obj); 2608 vlan_obj = &bnx2x_leading_vfq(vf, vlan_obj); 2609 if (!mac_obj || !vlan_obj) { 2610 BNX2X_ERR("VF partially initialized\n"); 2611 return -EINVAL; 2612 } 2613 2614 ivi->vf = vfidx; 2615 ivi->qos = 0; 2616 ivi->max_tx_rate = 10000; /* always 10G. TBA take from link struct */ 2617 ivi->min_tx_rate = 0; 2618 ivi->spoofchk = 1; /*always enabled */ 2619 if (vf->state == VF_ENABLED) { 2620 /* mac and vlan are in vlan_mac objects */ 2621 if (bnx2x_validate_vf_sp_objs(bp, vf, false)) { 2622 mac_obj->get_n_elements(bp, mac_obj, 1, (u8 *)&ivi->mac, 2623 0, ETH_ALEN); 2624 vlan_obj->get_n_elements(bp, vlan_obj, 1, 2625 (u8 *)&ivi->vlan, 0, 2626 VLAN_HLEN); 2627 } 2628 } else { 2629 mutex_lock(&bp->vfdb->bulletin_mutex); 2630 /* mac */ 2631 if (bulletin->valid_bitmap & (1 << MAC_ADDR_VALID)) 2632 /* mac configured by ndo so its in bulletin board */ 2633 memcpy(&ivi->mac, bulletin->mac, ETH_ALEN); 2634 else 2635 /* function has not been loaded yet. Show mac as 0s */ 2636 eth_zero_addr(ivi->mac); 2637 2638 /* vlan */ 2639 if (bulletin->valid_bitmap & (1 << VLAN_VALID)) 2640 /* vlan configured by ndo so its in bulletin board */ 2641 memcpy(&ivi->vlan, &bulletin->vlan, VLAN_HLEN); 2642 else 2643 /* function has not been loaded yet. Show vlans as 0s */ 2644 memset(&ivi->vlan, 0, VLAN_HLEN); 2645 2646 mutex_unlock(&bp->vfdb->bulletin_mutex); 2647 } 2648 2649 return 0; 2650 } 2651 2652 /* New mac for VF. Consider these cases: 2653 * 1. VF hasn't been acquired yet - save the mac in local bulletin board and 2654 * supply at acquire. 2655 * 2. VF has already been acquired but has not yet initialized - store in local 2656 * bulletin board. mac will be posted on VF bulletin board after VF init. VF 2657 * will configure this mac when it is ready. 2658 * 3. VF has already initialized but has not yet setup a queue - post the new 2659 * mac on VF's bulletin board right now. VF will configure this mac when it 2660 * is ready. 2661 * 4. VF has already set a queue - delete any macs already configured for this 2662 * queue and manually config the new mac. 2663 * In any event, once this function has been called refuse any attempts by the 2664 * VF to configure any mac for itself except for this mac. In case of a race 2665 * where the VF fails to see the new post on its bulletin board before sending a 2666 * mac configuration request, the PF will simply fail the request and VF can try 2667 * again after consulting its bulletin board. 2668 */ 2669 int bnx2x_set_vf_mac(struct net_device *dev, int vfidx, u8 *mac) 2670 { 2671 struct bnx2x *bp = netdev_priv(dev); 2672 int rc, q_logical_state; 2673 struct bnx2x_virtf *vf = NULL; 2674 struct pf_vf_bulletin_content *bulletin = NULL; 2675 2676 if (!is_valid_ether_addr(mac)) { 2677 BNX2X_ERR("mac address invalid\n"); 2678 return -EINVAL; 2679 } 2680 2681 /* sanity and init */ 2682 rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true); 2683 if (rc) 2684 return rc; 2685 2686 mutex_lock(&bp->vfdb->bulletin_mutex); 2687 2688 /* update PF's copy of the VF's bulletin. Will no longer accept mac 2689 * configuration requests from vf unless match this mac 2690 */ 2691 bulletin->valid_bitmap |= 1 << MAC_ADDR_VALID; 2692 memcpy(bulletin->mac, mac, ETH_ALEN); 2693 2694 /* Post update on VF's bulletin board */ 2695 rc = bnx2x_post_vf_bulletin(bp, vfidx); 2696 2697 /* release lock before checking return code */ 2698 mutex_unlock(&bp->vfdb->bulletin_mutex); 2699 2700 if (rc) { 2701 BNX2X_ERR("failed to update VF[%d] bulletin\n", vfidx); 2702 return rc; 2703 } 2704 2705 q_logical_state = 2706 bnx2x_get_q_logical_state(bp, &bnx2x_leading_vfq(vf, sp_obj)); 2707 if (vf->state == VF_ENABLED && 2708 q_logical_state == BNX2X_Q_LOGICAL_STATE_ACTIVE) { 2709 /* configure the mac in device on this vf's queue */ 2710 unsigned long ramrod_flags = 0; 2711 struct bnx2x_vlan_mac_obj *mac_obj; 2712 2713 /* User should be able to see failure reason in system logs */ 2714 if (!bnx2x_validate_vf_sp_objs(bp, vf, true)) 2715 return -EINVAL; 2716 2717 /* must lock vfpf channel to protect against vf flows */ 2718 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC); 2719 2720 /* remove existing eth macs */ 2721 mac_obj = &bnx2x_leading_vfq(vf, mac_obj); 2722 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_ETH_MAC, true); 2723 if (rc) { 2724 BNX2X_ERR("failed to delete eth macs\n"); 2725 rc = -EINVAL; 2726 goto out; 2727 } 2728 2729 /* remove existing uc list macs */ 2730 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, true); 2731 if (rc) { 2732 BNX2X_ERR("failed to delete uc_list macs\n"); 2733 rc = -EINVAL; 2734 goto out; 2735 } 2736 2737 /* configure the new mac to device */ 2738 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 2739 bnx2x_set_mac_one(bp, (u8 *)&bulletin->mac, mac_obj, true, 2740 BNX2X_ETH_MAC, &ramrod_flags); 2741 2742 out: 2743 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC); 2744 } 2745 2746 return rc; 2747 } 2748 2749 static void bnx2x_set_vf_vlan_acceptance(struct bnx2x *bp, 2750 struct bnx2x_virtf *vf, bool accept) 2751 { 2752 struct bnx2x_rx_mode_ramrod_params rx_ramrod; 2753 unsigned long accept_flags; 2754 2755 /* need to remove/add the VF's accept_any_vlan bit */ 2756 accept_flags = bnx2x_leading_vfq(vf, accept_flags); 2757 if (accept) 2758 set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 2759 else 2760 clear_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 2761 2762 bnx2x_vf_prep_rx_mode(bp, LEADING_IDX, &rx_ramrod, vf, 2763 accept_flags); 2764 bnx2x_leading_vfq(vf, accept_flags) = accept_flags; 2765 bnx2x_config_rx_mode(bp, &rx_ramrod); 2766 } 2767 2768 static int bnx2x_set_vf_vlan_filter(struct bnx2x *bp, struct bnx2x_virtf *vf, 2769 u16 vlan, bool add) 2770 { 2771 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 2772 unsigned long ramrod_flags = 0; 2773 int rc = 0; 2774 2775 /* configure the new vlan to device */ 2776 memset(&ramrod_param, 0, sizeof(ramrod_param)); 2777 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 2778 ramrod_param.vlan_mac_obj = &bnx2x_leading_vfq(vf, vlan_obj); 2779 ramrod_param.ramrod_flags = ramrod_flags; 2780 ramrod_param.user_req.u.vlan.vlan = vlan; 2781 ramrod_param.user_req.cmd = add ? BNX2X_VLAN_MAC_ADD 2782 : BNX2X_VLAN_MAC_DEL; 2783 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 2784 if (rc) { 2785 BNX2X_ERR("failed to configure vlan\n"); 2786 return -EINVAL; 2787 } 2788 2789 return 0; 2790 } 2791 2792 int bnx2x_set_vf_vlan(struct net_device *dev, int vfidx, u16 vlan, u8 qos) 2793 { 2794 struct pf_vf_bulletin_content *bulletin = NULL; 2795 struct bnx2x *bp = netdev_priv(dev); 2796 struct bnx2x_vlan_mac_obj *vlan_obj; 2797 unsigned long vlan_mac_flags = 0; 2798 unsigned long ramrod_flags = 0; 2799 struct bnx2x_virtf *vf = NULL; 2800 int i, rc; 2801 2802 if (vlan > 4095) { 2803 BNX2X_ERR("illegal vlan value %d\n", vlan); 2804 return -EINVAL; 2805 } 2806 2807 DP(BNX2X_MSG_IOV, "configuring VF %d with VLAN %d qos %d\n", 2808 vfidx, vlan, 0); 2809 2810 /* sanity and init */ 2811 rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true); 2812 if (rc) 2813 return rc; 2814 2815 /* update PF's copy of the VF's bulletin. No point in posting the vlan 2816 * to the VF since it doesn't have anything to do with it. But it useful 2817 * to store it here in case the VF is not up yet and we can only 2818 * configure the vlan later when it does. Treat vlan id 0 as remove the 2819 * Host tag. 2820 */ 2821 mutex_lock(&bp->vfdb->bulletin_mutex); 2822 2823 if (vlan > 0) 2824 bulletin->valid_bitmap |= 1 << VLAN_VALID; 2825 else 2826 bulletin->valid_bitmap &= ~(1 << VLAN_VALID); 2827 bulletin->vlan = vlan; 2828 2829 /* Post update on VF's bulletin board */ 2830 rc = bnx2x_post_vf_bulletin(bp, vfidx); 2831 if (rc) 2832 BNX2X_ERR("failed to update VF[%d] bulletin\n", vfidx); 2833 mutex_unlock(&bp->vfdb->bulletin_mutex); 2834 2835 /* is vf initialized and queue set up? */ 2836 if (vf->state != VF_ENABLED || 2837 bnx2x_get_q_logical_state(bp, &bnx2x_leading_vfq(vf, sp_obj)) != 2838 BNX2X_Q_LOGICAL_STATE_ACTIVE) 2839 return rc; 2840 2841 /* User should be able to see error in system logs */ 2842 if (!bnx2x_validate_vf_sp_objs(bp, vf, true)) 2843 return -EINVAL; 2844 2845 /* must lock vfpf channel to protect against vf flows */ 2846 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN); 2847 2848 /* remove existing vlans */ 2849 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 2850 vlan_obj = &bnx2x_leading_vfq(vf, vlan_obj); 2851 rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_mac_flags, 2852 &ramrod_flags); 2853 if (rc) { 2854 BNX2X_ERR("failed to delete vlans\n"); 2855 rc = -EINVAL; 2856 goto out; 2857 } 2858 2859 /* clear accept_any_vlan when HV forces vlan, otherwise 2860 * according to VF capabilities 2861 */ 2862 if (vlan || !(vf->cfg_flags & VF_CFG_VLAN_FILTER)) 2863 bnx2x_set_vf_vlan_acceptance(bp, vf, !vlan); 2864 2865 rc = bnx2x_set_vf_vlan_filter(bp, vf, vlan, true); 2866 if (rc) 2867 goto out; 2868 2869 /* send queue update ramrods to configure default vlan and 2870 * silent vlan removal 2871 */ 2872 for_each_vfq(vf, i) { 2873 struct bnx2x_queue_state_params q_params = {NULL}; 2874 struct bnx2x_queue_update_params *update_params; 2875 2876 q_params.q_obj = &bnx2x_vfq(vf, i, sp_obj); 2877 2878 /* validate the Q is UP */ 2879 if (bnx2x_get_q_logical_state(bp, q_params.q_obj) != 2880 BNX2X_Q_LOGICAL_STATE_ACTIVE) 2881 continue; 2882 2883 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 2884 q_params.cmd = BNX2X_Q_CMD_UPDATE; 2885 update_params = &q_params.params.update; 2886 __set_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, 2887 &update_params->update_flags); 2888 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 2889 &update_params->update_flags); 2890 if (vlan == 0) { 2891 /* if vlan is 0 then we want to leave the VF traffic 2892 * untagged, and leave the incoming traffic untouched 2893 * (i.e. do not remove any vlan tags). 2894 */ 2895 __clear_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN, 2896 &update_params->update_flags); 2897 __clear_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, 2898 &update_params->update_flags); 2899 } else { 2900 /* configure default vlan to vf queue and set silent 2901 * vlan removal (the vf remains unaware of this vlan). 2902 */ 2903 __set_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN, 2904 &update_params->update_flags); 2905 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, 2906 &update_params->update_flags); 2907 update_params->def_vlan = vlan; 2908 update_params->silent_removal_value = 2909 vlan & VLAN_VID_MASK; 2910 update_params->silent_removal_mask = VLAN_VID_MASK; 2911 } 2912 2913 /* Update the Queue state */ 2914 rc = bnx2x_queue_state_change(bp, &q_params); 2915 if (rc) { 2916 BNX2X_ERR("Failed to configure default VLAN queue %d\n", 2917 i); 2918 goto out; 2919 } 2920 } 2921 out: 2922 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN); 2923 2924 if (rc) 2925 DP(BNX2X_MSG_IOV, 2926 "updated VF[%d] vlan configuration (vlan = %d)\n", 2927 vfidx, vlan); 2928 2929 return rc; 2930 } 2931 2932 /* crc is the first field in the bulletin board. Compute the crc over the 2933 * entire bulletin board excluding the crc field itself. Use the length field 2934 * as the Bulletin Board was posted by a PF with possibly a different version 2935 * from the vf which will sample it. Therefore, the length is computed by the 2936 * PF and then used blindly by the VF. 2937 */ 2938 u32 bnx2x_crc_vf_bulletin(struct pf_vf_bulletin_content *bulletin) 2939 { 2940 return crc32(BULLETIN_CRC_SEED, 2941 ((u8 *)bulletin) + sizeof(bulletin->crc), 2942 bulletin->length - sizeof(bulletin->crc)); 2943 } 2944 2945 /* Check for new posts on the bulletin board */ 2946 enum sample_bulletin_result bnx2x_sample_bulletin(struct bnx2x *bp) 2947 { 2948 struct pf_vf_bulletin_content *bulletin; 2949 int attempts; 2950 2951 /* sampling structure in mid post may result with corrupted data 2952 * validate crc to ensure coherency. 2953 */ 2954 for (attempts = 0; attempts < BULLETIN_ATTEMPTS; attempts++) { 2955 u32 crc; 2956 2957 /* sample the bulletin board */ 2958 memcpy(&bp->shadow_bulletin, bp->pf2vf_bulletin, 2959 sizeof(union pf_vf_bulletin)); 2960 2961 crc = bnx2x_crc_vf_bulletin(&bp->shadow_bulletin.content); 2962 2963 if (bp->shadow_bulletin.content.crc == crc) 2964 break; 2965 2966 BNX2X_ERR("bad crc on bulletin board. Contained %x computed %x\n", 2967 bp->shadow_bulletin.content.crc, crc); 2968 } 2969 2970 if (attempts >= BULLETIN_ATTEMPTS) { 2971 BNX2X_ERR("pf to vf bulletin board crc was wrong %d consecutive times. Aborting\n", 2972 attempts); 2973 return PFVF_BULLETIN_CRC_ERR; 2974 } 2975 bulletin = &bp->shadow_bulletin.content; 2976 2977 /* bulletin board hasn't changed since last sample */ 2978 if (bp->old_bulletin.version == bulletin->version) 2979 return PFVF_BULLETIN_UNCHANGED; 2980 2981 /* the mac address in bulletin board is valid and is new */ 2982 if (bulletin->valid_bitmap & 1 << MAC_ADDR_VALID && 2983 !ether_addr_equal(bulletin->mac, bp->old_bulletin.mac)) { 2984 /* update new mac to net device */ 2985 memcpy(bp->dev->dev_addr, bulletin->mac, ETH_ALEN); 2986 } 2987 2988 if (bulletin->valid_bitmap & (1 << LINK_VALID)) { 2989 DP(BNX2X_MSG_IOV, "link update speed %d flags %x\n", 2990 bulletin->link_speed, bulletin->link_flags); 2991 2992 bp->vf_link_vars.line_speed = bulletin->link_speed; 2993 bp->vf_link_vars.link_report_flags = 0; 2994 /* Link is down */ 2995 if (bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN) 2996 __set_bit(BNX2X_LINK_REPORT_LINK_DOWN, 2997 &bp->vf_link_vars.link_report_flags); 2998 /* Full DUPLEX */ 2999 if (bulletin->link_flags & VFPF_LINK_REPORT_FULL_DUPLEX) 3000 __set_bit(BNX2X_LINK_REPORT_FD, 3001 &bp->vf_link_vars.link_report_flags); 3002 /* Rx Flow Control is ON */ 3003 if (bulletin->link_flags & VFPF_LINK_REPORT_RX_FC_ON) 3004 __set_bit(BNX2X_LINK_REPORT_RX_FC_ON, 3005 &bp->vf_link_vars.link_report_flags); 3006 /* Tx Flow Control is ON */ 3007 if (bulletin->link_flags & VFPF_LINK_REPORT_TX_FC_ON) 3008 __set_bit(BNX2X_LINK_REPORT_TX_FC_ON, 3009 &bp->vf_link_vars.link_report_flags); 3010 __bnx2x_link_report(bp); 3011 } 3012 3013 /* copy new bulletin board to bp */ 3014 memcpy(&bp->old_bulletin, bulletin, 3015 sizeof(struct pf_vf_bulletin_content)); 3016 3017 return PFVF_BULLETIN_UPDATED; 3018 } 3019 3020 void bnx2x_timer_sriov(struct bnx2x *bp) 3021 { 3022 bnx2x_sample_bulletin(bp); 3023 3024 /* if channel is down we need to self destruct */ 3025 if (bp->old_bulletin.valid_bitmap & 1 << CHANNEL_DOWN) 3026 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, 3027 BNX2X_MSG_IOV); 3028 } 3029 3030 void __iomem *bnx2x_vf_doorbells(struct bnx2x *bp) 3031 { 3032 /* vf doorbells are embedded within the regview */ 3033 return bp->regview + PXP_VF_ADDR_DB_START; 3034 } 3035 3036 void bnx2x_vf_pci_dealloc(struct bnx2x *bp) 3037 { 3038 BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->vf2pf_mbox_mapping, 3039 sizeof(struct bnx2x_vf_mbx_msg)); 3040 BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->pf2vf_bulletin_mapping, 3041 sizeof(union pf_vf_bulletin)); 3042 } 3043 3044 int bnx2x_vf_pci_alloc(struct bnx2x *bp) 3045 { 3046 mutex_init(&bp->vf2pf_mutex); 3047 3048 /* allocate vf2pf mailbox for vf to pf channel */ 3049 bp->vf2pf_mbox = BNX2X_PCI_ALLOC(&bp->vf2pf_mbox_mapping, 3050 sizeof(struct bnx2x_vf_mbx_msg)); 3051 if (!bp->vf2pf_mbox) 3052 goto alloc_mem_err; 3053 3054 /* allocate pf 2 vf bulletin board */ 3055 bp->pf2vf_bulletin = BNX2X_PCI_ALLOC(&bp->pf2vf_bulletin_mapping, 3056 sizeof(union pf_vf_bulletin)); 3057 if (!bp->pf2vf_bulletin) 3058 goto alloc_mem_err; 3059 3060 bnx2x_vf_bulletin_finalize(&bp->pf2vf_bulletin->content, true); 3061 3062 return 0; 3063 3064 alloc_mem_err: 3065 bnx2x_vf_pci_dealloc(bp); 3066 return -ENOMEM; 3067 } 3068 3069 void bnx2x_iov_channel_down(struct bnx2x *bp) 3070 { 3071 int vf_idx; 3072 struct pf_vf_bulletin_content *bulletin; 3073 3074 if (!IS_SRIOV(bp)) 3075 return; 3076 3077 for_each_vf(bp, vf_idx) { 3078 /* locate this VFs bulletin board and update the channel down 3079 * bit 3080 */ 3081 bulletin = BP_VF_BULLETIN(bp, vf_idx); 3082 bulletin->valid_bitmap |= 1 << CHANNEL_DOWN; 3083 3084 /* update vf bulletin board */ 3085 bnx2x_post_vf_bulletin(bp, vf_idx); 3086 } 3087 } 3088 3089 void bnx2x_iov_task(struct work_struct *work) 3090 { 3091 struct bnx2x *bp = container_of(work, struct bnx2x, iov_task.work); 3092 3093 if (!netif_running(bp->dev)) 3094 return; 3095 3096 if (test_and_clear_bit(BNX2X_IOV_HANDLE_FLR, 3097 &bp->iov_task_state)) 3098 bnx2x_vf_handle_flr_event(bp); 3099 3100 if (test_and_clear_bit(BNX2X_IOV_HANDLE_VF_MSG, 3101 &bp->iov_task_state)) 3102 bnx2x_vf_mbx(bp); 3103 } 3104 3105 void bnx2x_schedule_iov_task(struct bnx2x *bp, enum bnx2x_iov_flag flag) 3106 { 3107 smp_mb__before_atomic(); 3108 set_bit(flag, &bp->iov_task_state); 3109 smp_mb__after_atomic(); 3110 DP(BNX2X_MSG_IOV, "Scheduling iov task [Flag: %d]\n", flag); 3111 queue_delayed_work(bnx2x_iov_wq, &bp->iov_task, 0); 3112 } 3113