1 /* bnx2x_sp.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2011-2012 Broadcom Corporation 4 * 5 * Unless you and Broadcom execute a separate written software license 6 * agreement governing use of this software, this software is licensed to you 7 * under the terms of the GNU General Public License version 2, available 8 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 9 * 10 * Notwithstanding the above, under no circumstances may you combine this 11 * software in any way with any other Broadcom software provided under a 12 * license other than the GPL, without Broadcom's express prior written 13 * consent. 14 * 15 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 16 * Written by: Vladislav Zolotarov 17 * 18 */ 19 #ifndef BNX2X_SP_VERBS 20 #define BNX2X_SP_VERBS 21 22 struct bnx2x; 23 struct eth_context; 24 25 /* Bits representing general command's configuration */ 26 enum { 27 RAMROD_TX, 28 RAMROD_RX, 29 /* Wait until all pending commands complete */ 30 RAMROD_COMP_WAIT, 31 /* Don't send a ramrod, only update a registry */ 32 RAMROD_DRV_CLR_ONLY, 33 /* Configure HW according to the current object state */ 34 RAMROD_RESTORE, 35 /* Execute the next command now */ 36 RAMROD_EXEC, 37 /* 38 * Don't add a new command and continue execution of posponed 39 * commands. If not set a new command will be added to the 40 * pending commands list. 41 */ 42 RAMROD_CONT, 43 }; 44 45 typedef enum { 46 BNX2X_OBJ_TYPE_RX, 47 BNX2X_OBJ_TYPE_TX, 48 BNX2X_OBJ_TYPE_RX_TX, 49 } bnx2x_obj_type; 50 51 /* Filtering states */ 52 enum { 53 BNX2X_FILTER_MAC_PENDING, 54 BNX2X_FILTER_VLAN_PENDING, 55 BNX2X_FILTER_VLAN_MAC_PENDING, 56 BNX2X_FILTER_RX_MODE_PENDING, 57 BNX2X_FILTER_RX_MODE_SCHED, 58 BNX2X_FILTER_ISCSI_ETH_START_SCHED, 59 BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 60 BNX2X_FILTER_FCOE_ETH_START_SCHED, 61 BNX2X_FILTER_FCOE_ETH_STOP_SCHED, 62 BNX2X_FILTER_MCAST_PENDING, 63 BNX2X_FILTER_MCAST_SCHED, 64 BNX2X_FILTER_RSS_CONF_PENDING, 65 BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, 66 BNX2X_AFEX_PENDING_VIFSET_MCP_ACK 67 }; 68 69 struct bnx2x_raw_obj { 70 u8 func_id; 71 72 /* Queue params */ 73 u8 cl_id; 74 u32 cid; 75 76 /* Ramrod data buffer params */ 77 void *rdata; 78 dma_addr_t rdata_mapping; 79 80 /* Ramrod state params */ 81 int state; /* "ramrod is pending" state bit */ 82 unsigned long *pstate; /* pointer to state buffer */ 83 84 bnx2x_obj_type obj_type; 85 86 int (*wait_comp)(struct bnx2x *bp, 87 struct bnx2x_raw_obj *o); 88 89 bool (*check_pending)(struct bnx2x_raw_obj *o); 90 void (*clear_pending)(struct bnx2x_raw_obj *o); 91 void (*set_pending)(struct bnx2x_raw_obj *o); 92 }; 93 94 /************************* VLAN-MAC commands related parameters ***************/ 95 struct bnx2x_mac_ramrod_data { 96 u8 mac[ETH_ALEN]; 97 }; 98 99 struct bnx2x_vlan_ramrod_data { 100 u16 vlan; 101 }; 102 103 struct bnx2x_vlan_mac_ramrod_data { 104 u8 mac[ETH_ALEN]; 105 u16 vlan; 106 }; 107 108 union bnx2x_classification_ramrod_data { 109 struct bnx2x_mac_ramrod_data mac; 110 struct bnx2x_vlan_ramrod_data vlan; 111 struct bnx2x_vlan_mac_ramrod_data vlan_mac; 112 }; 113 114 /* VLAN_MAC commands */ 115 enum bnx2x_vlan_mac_cmd { 116 BNX2X_VLAN_MAC_ADD, 117 BNX2X_VLAN_MAC_DEL, 118 BNX2X_VLAN_MAC_MOVE, 119 }; 120 121 struct bnx2x_vlan_mac_data { 122 /* Requested command: BNX2X_VLAN_MAC_XX */ 123 enum bnx2x_vlan_mac_cmd cmd; 124 /* 125 * used to contain the data related vlan_mac_flags bits from 126 * ramrod parameters. 127 */ 128 unsigned long vlan_mac_flags; 129 130 /* Needed for MOVE command */ 131 struct bnx2x_vlan_mac_obj *target_obj; 132 133 union bnx2x_classification_ramrod_data u; 134 }; 135 136 /*************************** Exe Queue obj ************************************/ 137 union bnx2x_exe_queue_cmd_data { 138 struct bnx2x_vlan_mac_data vlan_mac; 139 140 struct { 141 /* TODO */ 142 } mcast; 143 }; 144 145 struct bnx2x_exeq_elem { 146 struct list_head link; 147 148 /* Length of this element in the exe_chunk. */ 149 int cmd_len; 150 151 union bnx2x_exe_queue_cmd_data cmd_data; 152 }; 153 154 union bnx2x_qable_obj; 155 156 union bnx2x_exeq_comp_elem { 157 union event_ring_elem *elem; 158 }; 159 160 struct bnx2x_exe_queue_obj; 161 162 typedef int (*exe_q_validate)(struct bnx2x *bp, 163 union bnx2x_qable_obj *o, 164 struct bnx2x_exeq_elem *elem); 165 166 typedef int (*exe_q_remove)(struct bnx2x *bp, 167 union bnx2x_qable_obj *o, 168 struct bnx2x_exeq_elem *elem); 169 170 /* Return positive if entry was optimized, 0 - if not, negative 171 * in case of an error. 172 */ 173 typedef int (*exe_q_optimize)(struct bnx2x *bp, 174 union bnx2x_qable_obj *o, 175 struct bnx2x_exeq_elem *elem); 176 typedef int (*exe_q_execute)(struct bnx2x *bp, 177 union bnx2x_qable_obj *o, 178 struct list_head *exe_chunk, 179 unsigned long *ramrod_flags); 180 typedef struct bnx2x_exeq_elem * 181 (*exe_q_get)(struct bnx2x_exe_queue_obj *o, 182 struct bnx2x_exeq_elem *elem); 183 184 struct bnx2x_exe_queue_obj { 185 /* 186 * Commands pending for an execution. 187 */ 188 struct list_head exe_queue; 189 190 /* 191 * Commands pending for an completion. 192 */ 193 struct list_head pending_comp; 194 195 spinlock_t lock; 196 197 /* Maximum length of commands' list for one execution */ 198 int exe_chunk_len; 199 200 union bnx2x_qable_obj *owner; 201 202 /****** Virtual functions ******/ 203 /** 204 * Called before commands execution for commands that are really 205 * going to be executed (after 'optimize'). 206 * 207 * Must run under exe_queue->lock 208 */ 209 exe_q_validate validate; 210 211 /** 212 * Called before removing pending commands, cleaning allocated 213 * resources (e.g., credits from validate) 214 */ 215 exe_q_remove remove; 216 217 /** 218 * This will try to cancel the current pending commands list 219 * considering the new command. 220 * 221 * Returns the number of optimized commands or a negative error code 222 * 223 * Must run under exe_queue->lock 224 */ 225 exe_q_optimize optimize; 226 227 /** 228 * Run the next commands chunk (owner specific). 229 */ 230 exe_q_execute execute; 231 232 /** 233 * Return the exe_queue element containing the specific command 234 * if any. Otherwise return NULL. 235 */ 236 exe_q_get get; 237 }; 238 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ 239 /* 240 * Element in the VLAN_MAC registry list having all currenty configured 241 * rules. 242 */ 243 struct bnx2x_vlan_mac_registry_elem { 244 struct list_head link; 245 246 /* 247 * Used to store the cam offset used for the mac/vlan/vlan-mac. 248 * Relevant for 57710 and 57711 only. VLANs and MACs share the 249 * same CAM for these chips. 250 */ 251 int cam_offset; 252 253 /* Needed for DEL and RESTORE flows */ 254 unsigned long vlan_mac_flags; 255 256 union bnx2x_classification_ramrod_data u; 257 }; 258 259 /* Bits representing VLAN_MAC commands specific flags */ 260 enum { 261 BNX2X_UC_LIST_MAC, 262 BNX2X_ETH_MAC, 263 BNX2X_ISCSI_ETH_MAC, 264 BNX2X_NETQ_ETH_MAC, 265 BNX2X_DONT_CONSUME_CAM_CREDIT, 266 BNX2X_DONT_CONSUME_CAM_CREDIT_DEST, 267 }; 268 269 struct bnx2x_vlan_mac_ramrod_params { 270 /* Object to run the command from */ 271 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 272 273 /* General command flags: COMP_WAIT, etc. */ 274 unsigned long ramrod_flags; 275 276 /* Command specific configuration request */ 277 struct bnx2x_vlan_mac_data user_req; 278 }; 279 280 struct bnx2x_vlan_mac_obj { 281 struct bnx2x_raw_obj raw; 282 283 /* Bookkeeping list: will prevent the addition of already existing 284 * entries. 285 */ 286 struct list_head head; 287 288 /* TODO: Add it's initialization in the init functions */ 289 struct bnx2x_exe_queue_obj exe_queue; 290 291 /* MACs credit pool */ 292 struct bnx2x_credit_pool_obj *macs_pool; 293 294 /* VLANs credit pool */ 295 struct bnx2x_credit_pool_obj *vlans_pool; 296 297 /* RAMROD command to be used */ 298 int ramrod_cmd; 299 300 /* copy first n elements onto preallocated buffer 301 * 302 * @param n number of elements to get 303 * @param buf buffer preallocated by caller into which elements 304 * will be copied. Note elements are 4-byte aligned 305 * so buffer size must be able to accomodate the 306 * aligned elements. 307 * 308 * @return number of copied bytes 309 */ 310 int (*get_n_elements)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, 311 int n, u8 *buf); 312 313 /** 314 * Checks if ADD-ramrod with the given params may be performed. 315 * 316 * @return zero if the element may be added 317 */ 318 319 int (*check_add)(struct bnx2x *bp, 320 struct bnx2x_vlan_mac_obj *o, 321 union bnx2x_classification_ramrod_data *data); 322 323 /** 324 * Checks if DEL-ramrod with the given params may be performed. 325 * 326 * @return true if the element may be deleted 327 */ 328 struct bnx2x_vlan_mac_registry_elem * 329 (*check_del)(struct bnx2x *bp, 330 struct bnx2x_vlan_mac_obj *o, 331 union bnx2x_classification_ramrod_data *data); 332 333 /** 334 * Checks if DEL-ramrod with the given params may be performed. 335 * 336 * @return true if the element may be deleted 337 */ 338 bool (*check_move)(struct bnx2x *bp, 339 struct bnx2x_vlan_mac_obj *src_o, 340 struct bnx2x_vlan_mac_obj *dst_o, 341 union bnx2x_classification_ramrod_data *data); 342 343 /** 344 * Update the relevant credit object(s) (consume/return 345 * correspondingly). 346 */ 347 bool (*get_credit)(struct bnx2x_vlan_mac_obj *o); 348 bool (*put_credit)(struct bnx2x_vlan_mac_obj *o); 349 bool (*get_cam_offset)(struct bnx2x_vlan_mac_obj *o, int *offset); 350 bool (*put_cam_offset)(struct bnx2x_vlan_mac_obj *o, int offset); 351 352 /** 353 * Configures one rule in the ramrod data buffer. 354 */ 355 void (*set_one_rule)(struct bnx2x *bp, 356 struct bnx2x_vlan_mac_obj *o, 357 struct bnx2x_exeq_elem *elem, int rule_idx, 358 int cam_offset); 359 360 /** 361 * Delete all configured elements having the given 362 * vlan_mac_flags specification. Assumes no pending for 363 * execution commands. Will schedule all all currently 364 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags 365 * specification for deletion and will use the given 366 * ramrod_flags for the last DEL operation. 367 * 368 * @param bp 369 * @param o 370 * @param ramrod_flags RAMROD_XX flags 371 * 372 * @return 0 if the last operation has completed successfully 373 * and there are no more elements left, positive value 374 * if there are pending for completion commands, 375 * negative value in case of failure. 376 */ 377 int (*delete_all)(struct bnx2x *bp, 378 struct bnx2x_vlan_mac_obj *o, 379 unsigned long *vlan_mac_flags, 380 unsigned long *ramrod_flags); 381 382 /** 383 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously 384 * configured elements list. 385 * 386 * @param bp 387 * @param p Command parameters (RAMROD_COMP_WAIT bit in 388 * ramrod_flags is only taken into an account) 389 * @param ppos a pointer to the cooky that should be given back in the 390 * next call to make function handle the next element. If 391 * *ppos is set to NULL it will restart the iterator. 392 * If returned *ppos == NULL this means that the last 393 * element has been handled. 394 * 395 * @return int 396 */ 397 int (*restore)(struct bnx2x *bp, 398 struct bnx2x_vlan_mac_ramrod_params *p, 399 struct bnx2x_vlan_mac_registry_elem **ppos); 400 401 /** 402 * Should be called on a completion arival. 403 * 404 * @param bp 405 * @param o 406 * @param cqe Completion element we are handling 407 * @param ramrod_flags if RAMROD_CONT is set the next bulk of 408 * pending commands will be executed. 409 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE 410 * may also be set if needed. 411 * 412 * @return 0 if there are neither pending nor waiting for 413 * completion commands. Positive value if there are 414 * pending for execution or for completion commands. 415 * Negative value in case of an error (including an 416 * error in the cqe). 417 */ 418 int (*complete)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, 419 union event_ring_elem *cqe, 420 unsigned long *ramrod_flags); 421 422 /** 423 * Wait for completion of all commands. Don't schedule new ones, 424 * just wait. It assumes that the completion code will schedule 425 * for new commands. 426 */ 427 int (*wait)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o); 428 }; 429 430 enum { 431 BNX2X_LLH_CAM_ISCSI_ETH_LINE = 0, 432 BNX2X_LLH_CAM_ETH_LINE, 433 BNX2X_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2 434 }; 435 436 void bnx2x_set_mac_in_nig(struct bnx2x *bp, 437 bool add, unsigned char *dev_addr, int index); 438 439 /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ 440 441 /* RX_MODE ramrod spesial flags: set in rx_mode_flags field in 442 * a bnx2x_rx_mode_ramrod_params. 443 */ 444 enum { 445 BNX2X_RX_MODE_FCOE_ETH, 446 BNX2X_RX_MODE_ISCSI_ETH, 447 }; 448 449 enum { 450 BNX2X_ACCEPT_UNICAST, 451 BNX2X_ACCEPT_MULTICAST, 452 BNX2X_ACCEPT_ALL_UNICAST, 453 BNX2X_ACCEPT_ALL_MULTICAST, 454 BNX2X_ACCEPT_BROADCAST, 455 BNX2X_ACCEPT_UNMATCHED, 456 BNX2X_ACCEPT_ANY_VLAN 457 }; 458 459 struct bnx2x_rx_mode_ramrod_params { 460 struct bnx2x_rx_mode_obj *rx_mode_obj; 461 unsigned long *pstate; 462 int state; 463 u8 cl_id; 464 u32 cid; 465 u8 func_id; 466 unsigned long ramrod_flags; 467 unsigned long rx_mode_flags; 468 469 /* 470 * rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to 471 * a tstorm_eth_mac_filter_config (e1x). 472 */ 473 void *rdata; 474 dma_addr_t rdata_mapping; 475 476 /* Rx mode settings */ 477 unsigned long rx_accept_flags; 478 479 /* internal switching settings */ 480 unsigned long tx_accept_flags; 481 }; 482 483 struct bnx2x_rx_mode_obj { 484 int (*config_rx_mode)(struct bnx2x *bp, 485 struct bnx2x_rx_mode_ramrod_params *p); 486 487 int (*wait_comp)(struct bnx2x *bp, 488 struct bnx2x_rx_mode_ramrod_params *p); 489 }; 490 491 /********************** Set multicast group ***********************************/ 492 493 struct bnx2x_mcast_list_elem { 494 struct list_head link; 495 u8 *mac; 496 }; 497 498 union bnx2x_mcast_config_data { 499 u8 *mac; 500 u8 bin; /* used in a RESTORE flow */ 501 }; 502 503 struct bnx2x_mcast_ramrod_params { 504 struct bnx2x_mcast_obj *mcast_obj; 505 506 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */ 507 unsigned long ramrod_flags; 508 509 struct list_head mcast_list; /* list of struct bnx2x_mcast_list_elem */ 510 /** TODO: 511 * - rename it to macs_num. 512 * - Add a new command type for handling pending commands 513 * (remove "zero semantics"). 514 * 515 * Length of mcast_list. If zero and ADD_CONT command - post 516 * pending commands. 517 */ 518 int mcast_list_len; 519 }; 520 521 enum { 522 BNX2X_MCAST_CMD_ADD, 523 BNX2X_MCAST_CMD_CONT, 524 BNX2X_MCAST_CMD_DEL, 525 BNX2X_MCAST_CMD_RESTORE, 526 }; 527 528 struct bnx2x_mcast_obj { 529 struct bnx2x_raw_obj raw; 530 531 union { 532 struct { 533 #define BNX2X_MCAST_BINS_NUM 256 534 #define BNX2X_MCAST_VEC_SZ (BNX2X_MCAST_BINS_NUM / 64) 535 u64 vec[BNX2X_MCAST_VEC_SZ]; 536 537 /** Number of BINs to clear. Should be updated 538 * immediately when a command arrives in order to 539 * properly create DEL commands. 540 */ 541 int num_bins_set; 542 } aprox_match; 543 544 struct { 545 struct list_head macs; 546 int num_macs_set; 547 } exact_match; 548 } registry; 549 550 /* Pending commands */ 551 struct list_head pending_cmds_head; 552 553 /* A state that is set in raw.pstate, when there are pending commands */ 554 int sched_state; 555 556 /* Maximal number of mcast MACs configured in one command */ 557 int max_cmd_len; 558 559 /* Total number of currently pending MACs to configure: both 560 * in the pending commands list and in the current command. 561 */ 562 int total_pending_num; 563 564 u8 engine_id; 565 566 /** 567 * @param cmd command to execute (BNX2X_MCAST_CMD_X, see above) 568 */ 569 int (*config_mcast)(struct bnx2x *bp, 570 struct bnx2x_mcast_ramrod_params *p, int cmd); 571 572 /** 573 * Fills the ramrod data during the RESTORE flow. 574 * 575 * @param bp 576 * @param o 577 * @param start_idx Registry index to start from 578 * @param rdata_idx Index in the ramrod data to start from 579 * 580 * @return -1 if we handled the whole registry or index of the last 581 * handled registry element. 582 */ 583 int (*hdl_restore)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 584 int start_bin, int *rdata_idx); 585 586 int (*enqueue_cmd)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 587 struct bnx2x_mcast_ramrod_params *p, int cmd); 588 589 void (*set_one_rule)(struct bnx2x *bp, 590 struct bnx2x_mcast_obj *o, int idx, 591 union bnx2x_mcast_config_data *cfg_data, int cmd); 592 593 /** Checks if there are more mcast MACs to be set or a previous 594 * command is still pending. 595 */ 596 bool (*check_pending)(struct bnx2x_mcast_obj *o); 597 598 /** 599 * Set/Clear/Check SCHEDULED state of the object 600 */ 601 void (*set_sched)(struct bnx2x_mcast_obj *o); 602 void (*clear_sched)(struct bnx2x_mcast_obj *o); 603 bool (*check_sched)(struct bnx2x_mcast_obj *o); 604 605 /* Wait until all pending commands complete */ 606 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_mcast_obj *o); 607 608 /** 609 * Handle the internal object counters needed for proper 610 * commands handling. Checks that the provided parameters are 611 * feasible. 612 */ 613 int (*validate)(struct bnx2x *bp, 614 struct bnx2x_mcast_ramrod_params *p, int cmd); 615 616 /** 617 * Restore the values of internal counters in case of a failure. 618 */ 619 void (*revert)(struct bnx2x *bp, 620 struct bnx2x_mcast_ramrod_params *p, 621 int old_num_bins); 622 623 int (*get_registry_size)(struct bnx2x_mcast_obj *o); 624 void (*set_registry_size)(struct bnx2x_mcast_obj *o, int n); 625 }; 626 627 /*************************** Credit handling **********************************/ 628 struct bnx2x_credit_pool_obj { 629 630 /* Current amount of credit in the pool */ 631 atomic_t credit; 632 633 /* Maximum allowed credit. put() will check against it. */ 634 int pool_sz; 635 636 /* 637 * Allocate a pool table statically. 638 * 639 * Currently the mamimum allowed size is MAX_MAC_CREDIT_E2(272) 640 * 641 * The set bit in the table will mean that the entry is available. 642 */ 643 #define BNX2X_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64) 644 u64 pool_mirror[BNX2X_POOL_VEC_SIZE]; 645 646 /* Base pool offset (initialized differently */ 647 int base_pool_offset; 648 649 /** 650 * Get the next free pool entry. 651 * 652 * @return true if there was a free entry in the pool 653 */ 654 bool (*get_entry)(struct bnx2x_credit_pool_obj *o, int *entry); 655 656 /** 657 * Return the entry back to the pool. 658 * 659 * @return true if entry is legal and has been successfully 660 * returned to the pool. 661 */ 662 bool (*put_entry)(struct bnx2x_credit_pool_obj *o, int entry); 663 664 /** 665 * Get the requested amount of credit from the pool. 666 * 667 * @param cnt Amount of requested credit 668 * @return true if the operation is successful 669 */ 670 bool (*get)(struct bnx2x_credit_pool_obj *o, int cnt); 671 672 /** 673 * Returns the credit to the pool. 674 * 675 * @param cnt Amount of credit to return 676 * @return true if the operation is successful 677 */ 678 bool (*put)(struct bnx2x_credit_pool_obj *o, int cnt); 679 680 /** 681 * Reads the current amount of credit. 682 */ 683 int (*check)(struct bnx2x_credit_pool_obj *o); 684 }; 685 686 /*************************** RSS configuration ********************************/ 687 enum { 688 /* RSS_MODE bits are mutually exclusive */ 689 BNX2X_RSS_MODE_DISABLED, 690 BNX2X_RSS_MODE_REGULAR, 691 692 BNX2X_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */ 693 694 BNX2X_RSS_IPV4, 695 BNX2X_RSS_IPV4_TCP, 696 BNX2X_RSS_IPV4_UDP, 697 BNX2X_RSS_IPV6, 698 BNX2X_RSS_IPV6_TCP, 699 BNX2X_RSS_IPV6_UDP, 700 }; 701 702 struct bnx2x_config_rss_params { 703 struct bnx2x_rss_config_obj *rss_obj; 704 705 /* may have RAMROD_COMP_WAIT set only */ 706 unsigned long ramrod_flags; 707 708 /* BNX2X_RSS_X bits */ 709 unsigned long rss_flags; 710 711 /* Number hash bits to take into an account */ 712 u8 rss_result_mask; 713 714 /* Indirection table */ 715 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 716 717 /* RSS hash values */ 718 u32 rss_key[10]; 719 720 /* valid only iff BNX2X_RSS_UPDATE_TOE is set */ 721 u16 toe_rss_bitmap; 722 }; 723 724 struct bnx2x_rss_config_obj { 725 struct bnx2x_raw_obj raw; 726 727 /* RSS engine to use */ 728 u8 engine_id; 729 730 /* Last configured indirection table */ 731 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 732 733 /* flags for enabling 4-tupple hash on UDP */ 734 u8 udp_rss_v4; 735 u8 udp_rss_v6; 736 737 int (*config_rss)(struct bnx2x *bp, 738 struct bnx2x_config_rss_params *p); 739 }; 740 741 /*********************** Queue state update ***********************************/ 742 743 /* UPDATE command options */ 744 enum { 745 BNX2X_Q_UPDATE_IN_VLAN_REM, 746 BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG, 747 BNX2X_Q_UPDATE_OUT_VLAN_REM, 748 BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG, 749 BNX2X_Q_UPDATE_ANTI_SPOOF, 750 BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG, 751 BNX2X_Q_UPDATE_ACTIVATE, 752 BNX2X_Q_UPDATE_ACTIVATE_CHNG, 753 BNX2X_Q_UPDATE_DEF_VLAN_EN, 754 BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, 755 BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 756 BNX2X_Q_UPDATE_SILENT_VLAN_REM 757 }; 758 759 /* Allowed Queue states */ 760 enum bnx2x_q_state { 761 BNX2X_Q_STATE_RESET, 762 BNX2X_Q_STATE_INITIALIZED, 763 BNX2X_Q_STATE_ACTIVE, 764 BNX2X_Q_STATE_MULTI_COS, 765 BNX2X_Q_STATE_MCOS_TERMINATED, 766 BNX2X_Q_STATE_INACTIVE, 767 BNX2X_Q_STATE_STOPPED, 768 BNX2X_Q_STATE_TERMINATED, 769 BNX2X_Q_STATE_FLRED, 770 BNX2X_Q_STATE_MAX, 771 }; 772 773 /* Allowed commands */ 774 enum bnx2x_queue_cmd { 775 BNX2X_Q_CMD_INIT, 776 BNX2X_Q_CMD_SETUP, 777 BNX2X_Q_CMD_SETUP_TX_ONLY, 778 BNX2X_Q_CMD_DEACTIVATE, 779 BNX2X_Q_CMD_ACTIVATE, 780 BNX2X_Q_CMD_UPDATE, 781 BNX2X_Q_CMD_UPDATE_TPA, 782 BNX2X_Q_CMD_HALT, 783 BNX2X_Q_CMD_CFC_DEL, 784 BNX2X_Q_CMD_TERMINATE, 785 BNX2X_Q_CMD_EMPTY, 786 BNX2X_Q_CMD_MAX, 787 }; 788 789 /* queue SETUP + INIT flags */ 790 enum { 791 BNX2X_Q_FLG_TPA, 792 BNX2X_Q_FLG_TPA_IPV6, 793 BNX2X_Q_FLG_TPA_GRO, 794 BNX2X_Q_FLG_STATS, 795 BNX2X_Q_FLG_ZERO_STATS, 796 BNX2X_Q_FLG_ACTIVE, 797 BNX2X_Q_FLG_OV, 798 BNX2X_Q_FLG_VLAN, 799 BNX2X_Q_FLG_COS, 800 BNX2X_Q_FLG_HC, 801 BNX2X_Q_FLG_HC_EN, 802 BNX2X_Q_FLG_DHC, 803 BNX2X_Q_FLG_FCOE, 804 BNX2X_Q_FLG_LEADING_RSS, 805 BNX2X_Q_FLG_MCAST, 806 BNX2X_Q_FLG_DEF_VLAN, 807 BNX2X_Q_FLG_TX_SWITCH, 808 BNX2X_Q_FLG_TX_SEC, 809 BNX2X_Q_FLG_ANTI_SPOOF, 810 BNX2X_Q_FLG_SILENT_VLAN_REM, 811 BNX2X_Q_FLG_FORCE_DEFAULT_PRI 812 }; 813 814 /* Queue type options: queue type may be a compination of below. */ 815 enum bnx2x_q_type { 816 /** TODO: Consider moving both these flags into the init() 817 * ramrod params. 818 */ 819 BNX2X_Q_TYPE_HAS_RX, 820 BNX2X_Q_TYPE_HAS_TX, 821 }; 822 823 #define BNX2X_PRIMARY_CID_INDEX 0 824 #define BNX2X_MULTI_TX_COS_E1X 3 /* QM only */ 825 #define BNX2X_MULTI_TX_COS_E2_E3A0 2 826 #define BNX2X_MULTI_TX_COS_E3B0 3 827 #define BNX2X_MULTI_TX_COS 3 /* Maximum possible */ 828 829 830 struct bnx2x_queue_init_params { 831 struct { 832 unsigned long flags; 833 u16 hc_rate; 834 u8 fw_sb_id; 835 u8 sb_cq_index; 836 } tx; 837 838 struct { 839 unsigned long flags; 840 u16 hc_rate; 841 u8 fw_sb_id; 842 u8 sb_cq_index; 843 } rx; 844 845 /* CID context in the host memory */ 846 struct eth_context *cxts[BNX2X_MULTI_TX_COS]; 847 848 /* maximum number of cos supported by hardware */ 849 u8 max_cos; 850 }; 851 852 struct bnx2x_queue_terminate_params { 853 /* index within the tx_only cids of this queue object */ 854 u8 cid_index; 855 }; 856 857 struct bnx2x_queue_cfc_del_params { 858 /* index within the tx_only cids of this queue object */ 859 u8 cid_index; 860 }; 861 862 struct bnx2x_queue_update_params { 863 unsigned long update_flags; /* BNX2X_Q_UPDATE_XX bits */ 864 u16 def_vlan; 865 u16 silent_removal_value; 866 u16 silent_removal_mask; 867 /* index within the tx_only cids of this queue object */ 868 u8 cid_index; 869 }; 870 871 struct rxq_pause_params { 872 u16 bd_th_lo; 873 u16 bd_th_hi; 874 u16 rcq_th_lo; 875 u16 rcq_th_hi; 876 u16 sge_th_lo; /* valid iff BNX2X_Q_FLG_TPA */ 877 u16 sge_th_hi; /* valid iff BNX2X_Q_FLG_TPA */ 878 u16 pri_map; 879 }; 880 881 /* general */ 882 struct bnx2x_general_setup_params { 883 /* valid iff BNX2X_Q_FLG_STATS */ 884 u8 stat_id; 885 886 u8 spcl_id; 887 u16 mtu; 888 u8 cos; 889 }; 890 891 struct bnx2x_rxq_setup_params { 892 /* dma */ 893 dma_addr_t dscr_map; 894 dma_addr_t sge_map; 895 dma_addr_t rcq_map; 896 dma_addr_t rcq_np_map; 897 898 u16 drop_flags; 899 u16 buf_sz; 900 u8 fw_sb_id; 901 u8 cl_qzone_id; 902 903 /* valid iff BNX2X_Q_FLG_TPA */ 904 u16 tpa_agg_sz; 905 u16 sge_buf_sz; 906 u8 max_sges_pkt; 907 u8 max_tpa_queues; 908 u8 rss_engine_id; 909 910 /* valid iff BNX2X_Q_FLG_MCAST */ 911 u8 mcast_engine_id; 912 913 u8 cache_line_log; 914 915 u8 sb_cq_index; 916 917 /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */ 918 u16 silent_removal_value; 919 u16 silent_removal_mask; 920 }; 921 922 struct bnx2x_txq_setup_params { 923 /* dma */ 924 dma_addr_t dscr_map; 925 926 u8 fw_sb_id; 927 u8 sb_cq_index; 928 u8 cos; /* valid iff BNX2X_Q_FLG_COS */ 929 u16 traffic_type; 930 /* equals to the leading rss client id, used for TX classification*/ 931 u8 tss_leading_cl_id; 932 933 /* valid iff BNX2X_Q_FLG_DEF_VLAN */ 934 u16 default_vlan; 935 }; 936 937 struct bnx2x_queue_setup_params { 938 struct bnx2x_general_setup_params gen_params; 939 struct bnx2x_txq_setup_params txq_params; 940 struct bnx2x_rxq_setup_params rxq_params; 941 struct rxq_pause_params pause_params; 942 unsigned long flags; 943 }; 944 945 struct bnx2x_queue_setup_tx_only_params { 946 struct bnx2x_general_setup_params gen_params; 947 struct bnx2x_txq_setup_params txq_params; 948 unsigned long flags; 949 /* index within the tx_only cids of this queue object */ 950 u8 cid_index; 951 }; 952 953 struct bnx2x_queue_state_params { 954 struct bnx2x_queue_sp_obj *q_obj; 955 956 /* Current command */ 957 enum bnx2x_queue_cmd cmd; 958 959 /* may have RAMROD_COMP_WAIT set only */ 960 unsigned long ramrod_flags; 961 962 /* Params according to the current command */ 963 union { 964 struct bnx2x_queue_update_params update; 965 struct bnx2x_queue_setup_params setup; 966 struct bnx2x_queue_init_params init; 967 struct bnx2x_queue_setup_tx_only_params tx_only; 968 struct bnx2x_queue_terminate_params terminate; 969 struct bnx2x_queue_cfc_del_params cfc_del; 970 } params; 971 }; 972 973 struct bnx2x_viflist_params { 974 u8 echo_res; 975 u8 func_bit_map_res; 976 }; 977 978 struct bnx2x_queue_sp_obj { 979 u32 cids[BNX2X_MULTI_TX_COS]; 980 u8 cl_id; 981 u8 func_id; 982 983 /* 984 * number of traffic classes supported by queue. 985 * The primary connection of the queue suppotrs the first traffic 986 * class. Any further traffic class is suppoted by a tx-only 987 * connection. 988 * 989 * Therefore max_cos is also a number of valid entries in the cids 990 * array. 991 */ 992 u8 max_cos; 993 u8 num_tx_only, next_tx_only; 994 995 enum bnx2x_q_state state, next_state; 996 997 /* bits from enum bnx2x_q_type */ 998 unsigned long type; 999 1000 /* BNX2X_Q_CMD_XX bits. This object implements "one 1001 * pending" paradigm but for debug and tracing purposes it's 1002 * more convinient to have different bits for different 1003 * commands. 1004 */ 1005 unsigned long pending; 1006 1007 /* Buffer to use as a ramrod data and its mapping */ 1008 void *rdata; 1009 dma_addr_t rdata_mapping; 1010 1011 /** 1012 * Performs one state change according to the given parameters. 1013 * 1014 * @return 0 in case of success and negative value otherwise. 1015 */ 1016 int (*send_cmd)(struct bnx2x *bp, 1017 struct bnx2x_queue_state_params *params); 1018 1019 /** 1020 * Sets the pending bit according to the requested transition. 1021 */ 1022 int (*set_pending)(struct bnx2x_queue_sp_obj *o, 1023 struct bnx2x_queue_state_params *params); 1024 1025 /** 1026 * Checks that the requested state transition is legal. 1027 */ 1028 int (*check_transition)(struct bnx2x *bp, 1029 struct bnx2x_queue_sp_obj *o, 1030 struct bnx2x_queue_state_params *params); 1031 1032 /** 1033 * Completes the pending command. 1034 */ 1035 int (*complete_cmd)(struct bnx2x *bp, 1036 struct bnx2x_queue_sp_obj *o, 1037 enum bnx2x_queue_cmd); 1038 1039 int (*wait_comp)(struct bnx2x *bp, 1040 struct bnx2x_queue_sp_obj *o, 1041 enum bnx2x_queue_cmd cmd); 1042 }; 1043 1044 /********************** Function state update *********************************/ 1045 /* Allowed Function states */ 1046 enum bnx2x_func_state { 1047 BNX2X_F_STATE_RESET, 1048 BNX2X_F_STATE_INITIALIZED, 1049 BNX2X_F_STATE_STARTED, 1050 BNX2X_F_STATE_TX_STOPPED, 1051 BNX2X_F_STATE_MAX, 1052 }; 1053 1054 /* Allowed Function commands */ 1055 enum bnx2x_func_cmd { 1056 BNX2X_F_CMD_HW_INIT, 1057 BNX2X_F_CMD_START, 1058 BNX2X_F_CMD_STOP, 1059 BNX2X_F_CMD_HW_RESET, 1060 BNX2X_F_CMD_AFEX_UPDATE, 1061 BNX2X_F_CMD_AFEX_VIFLISTS, 1062 BNX2X_F_CMD_TX_STOP, 1063 BNX2X_F_CMD_TX_START, 1064 BNX2X_F_CMD_MAX, 1065 }; 1066 1067 struct bnx2x_func_hw_init_params { 1068 /* A load phase returned by MCP. 1069 * 1070 * May be: 1071 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1072 * FW_MSG_CODE_DRV_LOAD_COMMON 1073 * FW_MSG_CODE_DRV_LOAD_PORT 1074 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1075 */ 1076 u32 load_phase; 1077 }; 1078 1079 struct bnx2x_func_hw_reset_params { 1080 /* A load phase returned by MCP. 1081 * 1082 * May be: 1083 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1084 * FW_MSG_CODE_DRV_LOAD_COMMON 1085 * FW_MSG_CODE_DRV_LOAD_PORT 1086 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1087 */ 1088 u32 reset_phase; 1089 }; 1090 1091 struct bnx2x_func_start_params { 1092 /* Multi Function mode: 1093 * - Single Function 1094 * - Switch Dependent 1095 * - Switch Independent 1096 */ 1097 u16 mf_mode; 1098 1099 /* Switch Dependent mode outer VLAN tag */ 1100 u16 sd_vlan_tag; 1101 1102 /* Function cos mode */ 1103 u8 network_cos_mode; 1104 }; 1105 1106 struct bnx2x_func_afex_update_params { 1107 u16 vif_id; 1108 u16 afex_default_vlan; 1109 u8 allowed_priorities; 1110 }; 1111 1112 struct bnx2x_func_afex_viflists_params { 1113 u16 vif_list_index; 1114 u8 func_bit_map; 1115 u8 afex_vif_list_command; 1116 u8 func_to_clear; 1117 }; 1118 struct bnx2x_func_tx_start_params { 1119 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 1120 u8 dcb_enabled; 1121 u8 dcb_version; 1122 u8 dont_add_pri_0_en; 1123 }; 1124 1125 struct bnx2x_func_state_params { 1126 struct bnx2x_func_sp_obj *f_obj; 1127 1128 /* Current command */ 1129 enum bnx2x_func_cmd cmd; 1130 1131 /* may have RAMROD_COMP_WAIT set only */ 1132 unsigned long ramrod_flags; 1133 1134 /* Params according to the current command */ 1135 union { 1136 struct bnx2x_func_hw_init_params hw_init; 1137 struct bnx2x_func_hw_reset_params hw_reset; 1138 struct bnx2x_func_start_params start; 1139 struct bnx2x_func_afex_update_params afex_update; 1140 struct bnx2x_func_afex_viflists_params afex_viflists; 1141 struct bnx2x_func_tx_start_params tx_start; 1142 } params; 1143 }; 1144 1145 struct bnx2x_func_sp_drv_ops { 1146 /* Init tool + runtime initialization: 1147 * - Common Chip 1148 * - Common (per Path) 1149 * - Port 1150 * - Function phases 1151 */ 1152 int (*init_hw_cmn_chip)(struct bnx2x *bp); 1153 int (*init_hw_cmn)(struct bnx2x *bp); 1154 int (*init_hw_port)(struct bnx2x *bp); 1155 int (*init_hw_func)(struct bnx2x *bp); 1156 1157 /* Reset Function HW: Common, Port, Function phases. */ 1158 void (*reset_hw_cmn)(struct bnx2x *bp); 1159 void (*reset_hw_port)(struct bnx2x *bp); 1160 void (*reset_hw_func)(struct bnx2x *bp); 1161 1162 /* Init/Free GUNZIP resources */ 1163 int (*gunzip_init)(struct bnx2x *bp); 1164 void (*gunzip_end)(struct bnx2x *bp); 1165 1166 /* Prepare/Release FW resources */ 1167 int (*init_fw)(struct bnx2x *bp); 1168 void (*release_fw)(struct bnx2x *bp); 1169 }; 1170 1171 struct bnx2x_func_sp_obj { 1172 enum bnx2x_func_state state, next_state; 1173 1174 /* BNX2X_FUNC_CMD_XX bits. This object implements "one 1175 * pending" paradigm but for debug and tracing purposes it's 1176 * more convinient to have different bits for different 1177 * commands. 1178 */ 1179 unsigned long pending; 1180 1181 /* Buffer to use as a ramrod data and its mapping */ 1182 void *rdata; 1183 dma_addr_t rdata_mapping; 1184 1185 /* Buffer to use as a afex ramrod data and its mapping. 1186 * This can't be same rdata as above because afex ramrod requests 1187 * can arrive to the object in parallel to other ramrod requests. 1188 */ 1189 void *afex_rdata; 1190 dma_addr_t afex_rdata_mapping; 1191 1192 /* this mutex validates that when pending flag is taken, the next 1193 * ramrod to be sent will be the one set the pending bit 1194 */ 1195 struct mutex one_pending_mutex; 1196 1197 /* Driver interface */ 1198 struct bnx2x_func_sp_drv_ops *drv; 1199 1200 /** 1201 * Performs one state change according to the given parameters. 1202 * 1203 * @return 0 in case of success and negative value otherwise. 1204 */ 1205 int (*send_cmd)(struct bnx2x *bp, 1206 struct bnx2x_func_state_params *params); 1207 1208 /** 1209 * Checks that the requested state transition is legal. 1210 */ 1211 int (*check_transition)(struct bnx2x *bp, 1212 struct bnx2x_func_sp_obj *o, 1213 struct bnx2x_func_state_params *params); 1214 1215 /** 1216 * Completes the pending command. 1217 */ 1218 int (*complete_cmd)(struct bnx2x *bp, 1219 struct bnx2x_func_sp_obj *o, 1220 enum bnx2x_func_cmd cmd); 1221 1222 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_func_sp_obj *o, 1223 enum bnx2x_func_cmd cmd); 1224 }; 1225 1226 /********************** Interfaces ********************************************/ 1227 /* Queueable objects set */ 1228 union bnx2x_qable_obj { 1229 struct bnx2x_vlan_mac_obj vlan_mac; 1230 }; 1231 /************** Function state update *********/ 1232 void bnx2x_init_func_obj(struct bnx2x *bp, 1233 struct bnx2x_func_sp_obj *obj, 1234 void *rdata, dma_addr_t rdata_mapping, 1235 void *afex_rdata, dma_addr_t afex_rdata_mapping, 1236 struct bnx2x_func_sp_drv_ops *drv_iface); 1237 1238 int bnx2x_func_state_change(struct bnx2x *bp, 1239 struct bnx2x_func_state_params *params); 1240 1241 enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp, 1242 struct bnx2x_func_sp_obj *o); 1243 /******************* Queue State **************/ 1244 void bnx2x_init_queue_obj(struct bnx2x *bp, 1245 struct bnx2x_queue_sp_obj *obj, u8 cl_id, u32 *cids, 1246 u8 cid_cnt, u8 func_id, void *rdata, 1247 dma_addr_t rdata_mapping, unsigned long type); 1248 1249 int bnx2x_queue_state_change(struct bnx2x *bp, 1250 struct bnx2x_queue_state_params *params); 1251 1252 /********************* VLAN-MAC ****************/ 1253 void bnx2x_init_mac_obj(struct bnx2x *bp, 1254 struct bnx2x_vlan_mac_obj *mac_obj, 1255 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1256 dma_addr_t rdata_mapping, int state, 1257 unsigned long *pstate, bnx2x_obj_type type, 1258 struct bnx2x_credit_pool_obj *macs_pool); 1259 1260 void bnx2x_init_vlan_obj(struct bnx2x *bp, 1261 struct bnx2x_vlan_mac_obj *vlan_obj, 1262 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1263 dma_addr_t rdata_mapping, int state, 1264 unsigned long *pstate, bnx2x_obj_type type, 1265 struct bnx2x_credit_pool_obj *vlans_pool); 1266 1267 void bnx2x_init_vlan_mac_obj(struct bnx2x *bp, 1268 struct bnx2x_vlan_mac_obj *vlan_mac_obj, 1269 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1270 dma_addr_t rdata_mapping, int state, 1271 unsigned long *pstate, bnx2x_obj_type type, 1272 struct bnx2x_credit_pool_obj *macs_pool, 1273 struct bnx2x_credit_pool_obj *vlans_pool); 1274 1275 int bnx2x_config_vlan_mac(struct bnx2x *bp, 1276 struct bnx2x_vlan_mac_ramrod_params *p); 1277 1278 int bnx2x_vlan_mac_move(struct bnx2x *bp, 1279 struct bnx2x_vlan_mac_ramrod_params *p, 1280 struct bnx2x_vlan_mac_obj *dest_o); 1281 1282 /********************* RX MODE ****************/ 1283 1284 void bnx2x_init_rx_mode_obj(struct bnx2x *bp, 1285 struct bnx2x_rx_mode_obj *o); 1286 1287 /** 1288 * bnx2x_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters. 1289 * 1290 * @p: Command parameters 1291 * 1292 * Return: 0 - if operation was successfull and there is no pending completions, 1293 * positive number - if there are pending completions, 1294 * negative - if there were errors 1295 */ 1296 int bnx2x_config_rx_mode(struct bnx2x *bp, 1297 struct bnx2x_rx_mode_ramrod_params *p); 1298 1299 /****************** MULTICASTS ****************/ 1300 1301 void bnx2x_init_mcast_obj(struct bnx2x *bp, 1302 struct bnx2x_mcast_obj *mcast_obj, 1303 u8 mcast_cl_id, u32 mcast_cid, u8 func_id, 1304 u8 engine_id, void *rdata, dma_addr_t rdata_mapping, 1305 int state, unsigned long *pstate, 1306 bnx2x_obj_type type); 1307 1308 /** 1309 * bnx2x_config_mcast - Configure multicast MACs list. 1310 * 1311 * @cmd: command to execute: BNX2X_MCAST_CMD_X 1312 * 1313 * May configure a new list 1314 * provided in p->mcast_list (BNX2X_MCAST_CMD_ADD), clean up 1315 * (BNX2X_MCAST_CMD_DEL) or restore (BNX2X_MCAST_CMD_RESTORE) a current 1316 * configuration, continue to execute the pending commands 1317 * (BNX2X_MCAST_CMD_CONT). 1318 * 1319 * If previous command is still pending or if number of MACs to 1320 * configure is more that maximum number of MACs in one command, 1321 * the current command will be enqueued to the tail of the 1322 * pending commands list. 1323 * 1324 * Return: 0 is operation was successfull and there are no pending completions, 1325 * negative if there were errors, positive if there are pending 1326 * completions. 1327 */ 1328 int bnx2x_config_mcast(struct bnx2x *bp, 1329 struct bnx2x_mcast_ramrod_params *p, int cmd); 1330 1331 /****************** CREDIT POOL ****************/ 1332 void bnx2x_init_mac_credit_pool(struct bnx2x *bp, 1333 struct bnx2x_credit_pool_obj *p, u8 func_id, 1334 u8 func_num); 1335 void bnx2x_init_vlan_credit_pool(struct bnx2x *bp, 1336 struct bnx2x_credit_pool_obj *p, u8 func_id, 1337 u8 func_num); 1338 1339 1340 /****************** RSS CONFIGURATION ****************/ 1341 void bnx2x_init_rss_config_obj(struct bnx2x *bp, 1342 struct bnx2x_rss_config_obj *rss_obj, 1343 u8 cl_id, u32 cid, u8 func_id, u8 engine_id, 1344 void *rdata, dma_addr_t rdata_mapping, 1345 int state, unsigned long *pstate, 1346 bnx2x_obj_type type); 1347 1348 /** 1349 * bnx2x_config_rss - Updates RSS configuration according to provided parameters 1350 * 1351 * Return: 0 in case of success 1352 */ 1353 int bnx2x_config_rss(struct bnx2x *bp, 1354 struct bnx2x_config_rss_params *p); 1355 1356 /** 1357 * bnx2x_get_rss_ind_table - Return the current ind_table configuration. 1358 * 1359 * @ind_table: buffer to fill with the current indirection 1360 * table content. Should be at least 1361 * T_ETH_INDIRECTION_TABLE_SIZE bytes long. 1362 */ 1363 void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj, 1364 u8 *ind_table); 1365 1366 #endif /* BNX2X_SP_VERBS */ 1367