1 /* bnx2x_reg.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2011 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * The registers description starts with the register Access type followed 10 * by size in bits. For example [RW 32]. The access types are: 11 * R - Read only 12 * RC - Clear on read 13 * RW - Read/Write 14 * ST - Statistics register (clear on read) 15 * W - Write only 16 * WB - Wide bus register - the size is over 32 bits and it should be 17 * read/write in consecutive 32 bits accesses 18 * WR - Write Clear (write 1 to clear the bit) 19 * 20 */ 21 #ifndef BNX2X_REG_H 22 #define BNX2X_REG_H 23 24 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 25 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2) 26 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5) 27 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3) 28 #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4) 29 #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1) 30 /* [RW 1] Initiate the ATC array - reset all the valid bits */ 31 #define ATC_REG_ATC_INIT_ARRAY 0x1100b8 32 /* [R 1] ATC initalization done */ 33 #define ATC_REG_ATC_INIT_DONE 0x1100bc 34 /* [RC 6] Interrupt register #0 read clear */ 35 #define ATC_REG_ATC_INT_STS_CLR 0x1101c0 36 /* [RW 5] Parity mask register #0 read/write */ 37 #define ATC_REG_ATC_PRTY_MASK 0x1101d8 38 /* [RC 5] Parity register #0 read clear */ 39 #define ATC_REG_ATC_PRTY_STS_CLR 0x1101d0 40 /* [RW 19] Interrupt mask register #0 read/write */ 41 #define BRB1_REG_BRB1_INT_MASK 0x60128 42 /* [R 19] Interrupt register #0 read */ 43 #define BRB1_REG_BRB1_INT_STS 0x6011c 44 /* [RW 4] Parity mask register #0 read/write */ 45 #define BRB1_REG_BRB1_PRTY_MASK 0x60138 46 /* [R 4] Parity register #0 read */ 47 #define BRB1_REG_BRB1_PRTY_STS 0x6012c 48 /* [RC 4] Parity register #0 read clear */ 49 #define BRB1_REG_BRB1_PRTY_STS_CLR 0x60130 50 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At 51 * address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address 52 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning - 53 * following reset the first rbc access to this reg must be write; there can 54 * be no more rbc writes after the first one; there can be any number of rbc 55 * read following the first write; rbc access not following these rules will 56 * result in hang condition. */ 57 #define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200 58 /* [RW 10] The number of free blocks below which the full signal to class 0 59 * is asserted */ 60 #define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 0x601d0 61 #define BRB1_REG_FULL_0_XOFF_THRESHOLD_1 0x60230 62 /* [RW 11] The number of free blocks above which the full signal to class 0 63 * is de-asserted */ 64 #define BRB1_REG_FULL_0_XON_THRESHOLD_0 0x601d4 65 #define BRB1_REG_FULL_0_XON_THRESHOLD_1 0x60234 66 /* [RW 11] The number of free blocks below which the full signal to class 1 67 * is asserted */ 68 #define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 0x601d8 69 #define BRB1_REG_FULL_1_XOFF_THRESHOLD_1 0x60238 70 /* [RW 11] The number of free blocks above which the full signal to class 1 71 * is de-asserted */ 72 #define BRB1_REG_FULL_1_XON_THRESHOLD_0 0x601dc 73 #define BRB1_REG_FULL_1_XON_THRESHOLD_1 0x6023c 74 /* [RW 11] The number of free blocks below which the full signal to the LB 75 * port is asserted */ 76 #define BRB1_REG_FULL_LB_XOFF_THRESHOLD 0x601e0 77 /* [RW 10] The number of free blocks above which the full signal to the LB 78 * port is de-asserted */ 79 #define BRB1_REG_FULL_LB_XON_THRESHOLD 0x601e4 80 /* [RW 10] The number of free blocks above which the High_llfc signal to 81 interface #n is de-asserted. */ 82 #define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c 83 /* [RW 10] The number of free blocks below which the High_llfc signal to 84 interface #n is asserted. */ 85 #define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c 86 /* [RW 11] The number of blocks guarantied for the LB port */ 87 #define BRB1_REG_LB_GUARANTIED 0x601ec 88 /* [RW 11] The hysteresis on the guarantied buffer space for the Lb port 89 * before signaling XON. */ 90 #define BRB1_REG_LB_GUARANTIED_HYST 0x60264 91 /* [RW 24] LL RAM data. */ 92 #define BRB1_REG_LL_RAM 0x61000 93 /* [RW 10] The number of free blocks above which the Low_llfc signal to 94 interface #n is de-asserted. */ 95 #define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c 96 /* [RW 10] The number of free blocks below which the Low_llfc signal to 97 interface #n is asserted. */ 98 #define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c 99 /* [RW 11] The number of blocks guarantied for class 0 in MAC 0. The 100 * register is applicable only when per_class_guaranty_mode is set. */ 101 #define BRB1_REG_MAC_0_CLASS_0_GUARANTIED 0x60244 102 /* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC 103 * 1 before signaling XON. The register is applicable only when 104 * per_class_guaranty_mode is set. */ 105 #define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST 0x60254 106 /* [RW 11] The number of blocks guarantied for class 1 in MAC 0. The 107 * register is applicable only when per_class_guaranty_mode is set. */ 108 #define BRB1_REG_MAC_0_CLASS_1_GUARANTIED 0x60248 109 /* [RW 11] The hysteresis on the guarantied buffer space for class 1in MAC 0 110 * before signaling XON. The register is applicable only when 111 * per_class_guaranty_mode is set. */ 112 #define BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST 0x60258 113 /* [RW 11] The number of blocks guarantied for class 0in MAC1.The register 114 * is applicable only when per_class_guaranty_mode is set. */ 115 #define BRB1_REG_MAC_1_CLASS_0_GUARANTIED 0x6024c 116 /* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC 117 * 1 before signaling XON. The register is applicable only when 118 * per_class_guaranty_mode is set. */ 119 #define BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST 0x6025c 120 /* [RW 11] The number of blocks guarantied for class 1 in MAC 1. The 121 * register is applicable only when per_class_guaranty_mode is set. */ 122 #define BRB1_REG_MAC_1_CLASS_1_GUARANTIED 0x60250 123 /* [RW 11] The hysteresis on the guarantied buffer space for class 1 in MAC 124 * 1 before signaling XON. The register is applicable only when 125 * per_class_guaranty_mode is set. */ 126 #define BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST 0x60260 127 /* [RW 11] The number of blocks guarantied for the MAC port. The register is 128 * applicable only when per_class_guaranty_mode is reset. */ 129 #define BRB1_REG_MAC_GUARANTIED_0 0x601e8 130 #define BRB1_REG_MAC_GUARANTIED_1 0x60240 131 /* [R 24] The number of full blocks. */ 132 #define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090 133 /* [ST 32] The number of cycles that the write_full signal towards MAC #0 134 was asserted. */ 135 #define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8 136 #define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc 137 #define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8 138 /* [ST 32] The number of cycles that the pause signal towards MAC #0 was 139 asserted. */ 140 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8 141 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc 142 /* [RW 10] The number of free blocks below which the pause signal to class 0 143 * is asserted */ 144 #define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 0x601c0 145 #define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 0x60220 146 /* [RW 11] The number of free blocks above which the pause signal to class 0 147 * is de-asserted */ 148 #define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 0x601c4 149 #define BRB1_REG_PAUSE_0_XON_THRESHOLD_1 0x60224 150 /* [RW 11] The number of free blocks below which the pause signal to class 1 151 * is asserted */ 152 #define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 0x601c8 153 #define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 0x60228 154 /* [RW 11] The number of free blocks above which the pause signal to class 1 155 * is de-asserted */ 156 #define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 0x601cc 157 #define BRB1_REG_PAUSE_1_XON_THRESHOLD_1 0x6022c 158 /* [RW 10] Write client 0: De-assert pause threshold. Not Functional */ 159 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078 160 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c 161 /* [RW 10] Write client 0: Assert pause threshold. */ 162 #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068 163 #define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c 164 /* [R 24] The number of full blocks occupied by port. */ 165 #define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094 166 /* [RW 1] Reset the design by software. */ 167 #define BRB1_REG_SOFT_RESET 0x600dc 168 /* [R 5] Used to read the value of the XX protection CAM occupancy counter. */ 169 #define CCM_REG_CAM_OCCUP 0xd0188 170 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 171 acknowledge output is deasserted; all other signals are treated as usual; 172 if 1 - normal activity. */ 173 #define CCM_REG_CCM_CFC_IFEN 0xd003c 174 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 175 disregarded; valid is deasserted; all other signals are treated as usual; 176 if 1 - normal activity. */ 177 #define CCM_REG_CCM_CQM_IFEN 0xd000c 178 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. 179 Otherwise 0 is inserted. */ 180 #define CCM_REG_CCM_CQM_USE_Q 0xd00c0 181 /* [RW 11] Interrupt mask register #0 read/write */ 182 #define CCM_REG_CCM_INT_MASK 0xd01e4 183 /* [R 11] Interrupt register #0 read */ 184 #define CCM_REG_CCM_INT_STS 0xd01d8 185 /* [RW 27] Parity mask register #0 read/write */ 186 #define CCM_REG_CCM_PRTY_MASK 0xd01f4 187 /* [R 27] Parity register #0 read */ 188 #define CCM_REG_CCM_PRTY_STS 0xd01e8 189 /* [RC 27] Parity register #0 read clear */ 190 #define CCM_REG_CCM_PRTY_STS_CLR 0xd01ec 191 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS 192 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 193 Is used to determine the number of the AG context REG-pairs written back; 194 when the input message Reg1WbFlg isn't set. */ 195 #define CCM_REG_CCM_REG0_SZ 0xd00c4 196 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 197 disregarded; valid is deasserted; all other signals are treated as usual; 198 if 1 - normal activity. */ 199 #define CCM_REG_CCM_STORM0_IFEN 0xd0004 200 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 201 disregarded; valid is deasserted; all other signals are treated as usual; 202 if 1 - normal activity. */ 203 #define CCM_REG_CCM_STORM1_IFEN 0xd0008 204 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is 205 disregarded; valid output is deasserted; all other signals are treated as 206 usual; if 1 - normal activity. */ 207 #define CCM_REG_CDU_AG_RD_IFEN 0xd0030 208 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 209 are disregarded; all other signals are treated as usual; if 1 - normal 210 activity. */ 211 #define CCM_REG_CDU_AG_WR_IFEN 0xd002c 212 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 213 disregarded; valid output is deasserted; all other signals are treated as 214 usual; if 1 - normal activity. */ 215 #define CCM_REG_CDU_SM_RD_IFEN 0xd0038 216 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 217 input is disregarded; all other signals are treated as usual; if 1 - 218 normal activity. */ 219 #define CCM_REG_CDU_SM_WR_IFEN 0xd0034 220 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 221 the initial credit value; read returns the current value of the credit 222 counter. Must be initialized to 1 at start-up. */ 223 #define CCM_REG_CFC_INIT_CRD 0xd0204 224 /* [RW 2] Auxiliary counter flag Q number 1. */ 225 #define CCM_REG_CNT_AUX1_Q 0xd00c8 226 /* [RW 2] Auxiliary counter flag Q number 2. */ 227 #define CCM_REG_CNT_AUX2_Q 0xd00cc 228 /* [RW 28] The CM header value for QM request (primary). */ 229 #define CCM_REG_CQM_CCM_HDR_P 0xd008c 230 /* [RW 28] The CM header value for QM request (secondary). */ 231 #define CCM_REG_CQM_CCM_HDR_S 0xd0090 232 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 233 acknowledge output is deasserted; all other signals are treated as usual; 234 if 1 - normal activity. */ 235 #define CCM_REG_CQM_CCM_IFEN 0xd0014 236 /* [RW 6] QM output initial credit. Max credit available - 32. Write writes 237 the initial credit value; read returns the current value of the credit 238 counter. Must be initialized to 32 at start-up. */ 239 #define CCM_REG_CQM_INIT_CRD 0xd020c 240 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 241 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 242 prioritised); 2 stands for weight 2; tc. */ 243 #define CCM_REG_CQM_P_WEIGHT 0xd00b8 244 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 245 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 246 prioritised); 2 stands for weight 2; tc. */ 247 #define CCM_REG_CQM_S_WEIGHT 0xd00bc 248 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 249 acknowledge output is deasserted; all other signals are treated as usual; 250 if 1 - normal activity. */ 251 #define CCM_REG_CSDM_IFEN 0xd0018 252 /* [RC 1] Set when the message length mismatch (relative to last indication) 253 at the SDM interface is detected. */ 254 #define CCM_REG_CSDM_LENGTH_MIS 0xd0170 255 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for 256 weight 8 (the most prioritised); 1 stands for weight 1(least 257 prioritised); 2 stands for weight 2; tc. */ 258 #define CCM_REG_CSDM_WEIGHT 0xd00b4 259 /* [RW 28] The CM header for QM formatting in case of an error in the QM 260 inputs. */ 261 #define CCM_REG_ERR_CCM_HDR 0xd0094 262 /* [RW 8] The Event ID in case the input message ErrorFlg is set. */ 263 #define CCM_REG_ERR_EVNT_ID 0xd0098 264 /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write 265 writes the initial credit value; read returns the current value of the 266 credit counter. Must be initialized to 64 at start-up. */ 267 #define CCM_REG_FIC0_INIT_CRD 0xd0210 268 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 269 writes the initial credit value; read returns the current value of the 270 credit counter. Must be initialized to 64 at start-up. */ 271 #define CCM_REG_FIC1_INIT_CRD 0xd0214 272 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 273 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr; 274 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and 275 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and 276 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */ 277 #define CCM_REG_GR_ARB_TYPE 0xd015c 278 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 279 highest priority is 3. It is supposed; that the Store channel priority is 280 the compliment to 4 of the rest priorities - Aggregation channel; Load 281 (FIC0) channel and Load (FIC1). */ 282 #define CCM_REG_GR_LD0_PR 0xd0164 283 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 284 highest priority is 3. It is supposed; that the Store channel priority is 285 the compliment to 4 of the rest priorities - Aggregation channel; Load 286 (FIC0) channel and Load (FIC1). */ 287 #define CCM_REG_GR_LD1_PR 0xd0168 288 /* [RW 2] General flags index. */ 289 #define CCM_REG_INV_DONE_Q 0xd0108 290 /* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM 291 context and sent to STORM; for a specific connection type. The double 292 REG-pairs are used in order to align to STORM context row size of 128 293 bits. The offset of these data in the STORM context is always 0. Index 294 _(0..15) stands for the connection type (one of 16). */ 295 #define CCM_REG_N_SM_CTX_LD_0 0xd004c 296 #define CCM_REG_N_SM_CTX_LD_1 0xd0050 297 #define CCM_REG_N_SM_CTX_LD_2 0xd0054 298 #define CCM_REG_N_SM_CTX_LD_3 0xd0058 299 #define CCM_REG_N_SM_CTX_LD_4 0xd005c 300 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; 301 acknowledge output is deasserted; all other signals are treated as usual; 302 if 1 - normal activity. */ 303 #define CCM_REG_PBF_IFEN 0xd0028 304 /* [RC 1] Set when the message length mismatch (relative to last indication) 305 at the pbf interface is detected. */ 306 #define CCM_REG_PBF_LENGTH_MIS 0xd0180 307 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for 308 weight 8 (the most prioritised); 1 stands for weight 1(least 309 prioritised); 2 stands for weight 2; tc. */ 310 #define CCM_REG_PBF_WEIGHT 0xd00ac 311 #define CCM_REG_PHYS_QNUM1_0 0xd0134 312 #define CCM_REG_PHYS_QNUM1_1 0xd0138 313 #define CCM_REG_PHYS_QNUM2_0 0xd013c 314 #define CCM_REG_PHYS_QNUM2_1 0xd0140 315 #define CCM_REG_PHYS_QNUM3_0 0xd0144 316 #define CCM_REG_PHYS_QNUM3_1 0xd0148 317 #define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114 318 #define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118 319 #define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c 320 #define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120 321 #define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124 322 #define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128 323 #define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c 324 #define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130 325 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 326 disregarded; acknowledge output is deasserted; all other signals are 327 treated as usual; if 1 - normal activity. */ 328 #define CCM_REG_STORM_CCM_IFEN 0xd0010 329 /* [RC 1] Set when the message length mismatch (relative to last indication) 330 at the STORM interface is detected. */ 331 #define CCM_REG_STORM_LENGTH_MIS 0xd016c 332 /* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin) 333 mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for 334 weight 1(least prioritised); 2 stands for weight 2 (more prioritised); 335 tc. */ 336 #define CCM_REG_STORM_WEIGHT 0xd009c 337 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is 338 disregarded; acknowledge output is deasserted; all other signals are 339 treated as usual; if 1 - normal activity. */ 340 #define CCM_REG_TSEM_IFEN 0xd001c 341 /* [RC 1] Set when the message length mismatch (relative to last indication) 342 at the tsem interface is detected. */ 343 #define CCM_REG_TSEM_LENGTH_MIS 0xd0174 344 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for 345 weight 8 (the most prioritised); 1 stands for weight 1(least 346 prioritised); 2 stands for weight 2; tc. */ 347 #define CCM_REG_TSEM_WEIGHT 0xd00a0 348 /* [RW 1] Input usem Interface enable. If 0 - the valid input is 349 disregarded; acknowledge output is deasserted; all other signals are 350 treated as usual; if 1 - normal activity. */ 351 #define CCM_REG_USEM_IFEN 0xd0024 352 /* [RC 1] Set when message length mismatch (relative to last indication) at 353 the usem interface is detected. */ 354 #define CCM_REG_USEM_LENGTH_MIS 0xd017c 355 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for 356 weight 8 (the most prioritised); 1 stands for weight 1(least 357 prioritised); 2 stands for weight 2; tc. */ 358 #define CCM_REG_USEM_WEIGHT 0xd00a8 359 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is 360 disregarded; acknowledge output is deasserted; all other signals are 361 treated as usual; if 1 - normal activity. */ 362 #define CCM_REG_XSEM_IFEN 0xd0020 363 /* [RC 1] Set when the message length mismatch (relative to last indication) 364 at the xsem interface is detected. */ 365 #define CCM_REG_XSEM_LENGTH_MIS 0xd0178 366 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for 367 weight 8 (the most prioritised); 1 stands for weight 1(least 368 prioritised); 2 stands for weight 2; tc. */ 369 #define CCM_REG_XSEM_WEIGHT 0xd00a4 370 /* [RW 19] Indirect access to the descriptor table of the XX protection 371 mechanism. The fields are: [5:0] - message length; [12:6] - message 372 pointer; 18:13] - next pointer. */ 373 #define CCM_REG_XX_DESCR_TABLE 0xd0300 374 #define CCM_REG_XX_DESCR_TABLE_SIZE 24 375 /* [R 7] Used to read the value of XX protection Free counter. */ 376 #define CCM_REG_XX_FREE 0xd0184 377 /* [RW 6] Initial value for the credit counter; responsible for fulfilling 378 of the Input Stage XX protection buffer by the XX protection pending 379 messages. Max credit available - 127. Write writes the initial credit 380 value; read returns the current value of the credit counter. Must be 381 initialized to maximum XX protected message size - 2 at start-up. */ 382 #define CCM_REG_XX_INIT_CRD 0xd0220 383 /* [RW 7] The maximum number of pending messages; which may be stored in XX 384 protection. At read the ~ccm_registers_xx_free.xx_free counter is read. 385 At write comprises the start value of the ~ccm_registers_xx_free.xx_free 386 counter. */ 387 #define CCM_REG_XX_MSG_NUM 0xd0224 388 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 389 #define CCM_REG_XX_OVFL_EVNT_ID 0xd0044 390 /* [RW 18] Indirect access to the XX table of the XX protection mechanism. 391 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] - 392 header pointer. */ 393 #define CCM_REG_XX_TABLE 0xd0280 394 #define CDU_REG_CDU_CHK_MASK0 0x101000 395 #define CDU_REG_CDU_CHK_MASK1 0x101004 396 #define CDU_REG_CDU_CONTROL0 0x101008 397 #define CDU_REG_CDU_DEBUG 0x101010 398 #define CDU_REG_CDU_GLOBAL_PARAMS 0x101020 399 /* [RW 7] Interrupt mask register #0 read/write */ 400 #define CDU_REG_CDU_INT_MASK 0x10103c 401 /* [R 7] Interrupt register #0 read */ 402 #define CDU_REG_CDU_INT_STS 0x101030 403 /* [RW 5] Parity mask register #0 read/write */ 404 #define CDU_REG_CDU_PRTY_MASK 0x10104c 405 /* [R 5] Parity register #0 read */ 406 #define CDU_REG_CDU_PRTY_STS 0x101040 407 /* [RC 5] Parity register #0 read clear */ 408 #define CDU_REG_CDU_PRTY_STS_CLR 0x101044 409 /* [RC 32] logging of error data in case of a CDU load error: 410 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error; 411 ype_error; ctual_active; ctual_compressed_context}; */ 412 #define CDU_REG_ERROR_DATA 0x101014 413 /* [WB 216] L1TT ram access. each entry has the following format : 414 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0]; 415 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */ 416 #define CDU_REG_L1TT 0x101800 417 /* [WB 24] MATT ram access. each entry has the following 418 format:{RegionLength[11:0]; egionOffset[11:0]} */ 419 #define CDU_REG_MATT 0x101100 420 /* [RW 1] when this bit is set the CDU operates in e1hmf mode */ 421 #define CDU_REG_MF_MODE 0x101050 422 /* [R 1] indication the initializing the activity counter by the hardware 423 was done. */ 424 #define CFC_REG_AC_INIT_DONE 0x104078 425 /* [RW 13] activity counter ram access */ 426 #define CFC_REG_ACTIVITY_COUNTER 0x104400 427 #define CFC_REG_ACTIVITY_COUNTER_SIZE 256 428 /* [R 1] indication the initializing the cams by the hardware was done. */ 429 #define CFC_REG_CAM_INIT_DONE 0x10407c 430 /* [RW 2] Interrupt mask register #0 read/write */ 431 #define CFC_REG_CFC_INT_MASK 0x104108 432 /* [R 2] Interrupt register #0 read */ 433 #define CFC_REG_CFC_INT_STS 0x1040fc 434 /* [RC 2] Interrupt register #0 read clear */ 435 #define CFC_REG_CFC_INT_STS_CLR 0x104100 436 /* [RW 4] Parity mask register #0 read/write */ 437 #define CFC_REG_CFC_PRTY_MASK 0x104118 438 /* [R 4] Parity register #0 read */ 439 #define CFC_REG_CFC_PRTY_STS 0x10410c 440 /* [RC 4] Parity register #0 read clear */ 441 #define CFC_REG_CFC_PRTY_STS_CLR 0x104110 442 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */ 443 #define CFC_REG_CID_CAM 0x104800 444 #define CFC_REG_CONTROL0 0x104028 445 #define CFC_REG_DEBUG0 0x104050 446 /* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error 447 vector) whether the cfc should be disabled upon it */ 448 #define CFC_REG_DISABLE_ON_ERROR 0x104044 449 /* [RC 14] CFC error vector. when the CFC detects an internal error it will 450 set one of these bits. the bit description can be found in CFC 451 specifications */ 452 #define CFC_REG_ERROR_VECTOR 0x10403c 453 /* [WB 93] LCID info ram access */ 454 #define CFC_REG_INFO_RAM 0x105000 455 #define CFC_REG_INFO_RAM_SIZE 1024 456 #define CFC_REG_INIT_REG 0x10404c 457 #define CFC_REG_INTERFACES 0x104058 458 /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this 459 field allows changing the priorities of the weighted-round-robin arbiter 460 which selects which CFC load client should be served next */ 461 #define CFC_REG_LCREQ_WEIGHTS 0x104084 462 /* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */ 463 #define CFC_REG_LINK_LIST 0x104c00 464 #define CFC_REG_LINK_LIST_SIZE 256 465 /* [R 1] indication the initializing the link list by the hardware was done. */ 466 #define CFC_REG_LL_INIT_DONE 0x104074 467 /* [R 9] Number of allocated LCIDs which are at empty state */ 468 #define CFC_REG_NUM_LCIDS_ALLOC 0x104020 469 /* [R 9] Number of Arriving LCIDs in Link List Block */ 470 #define CFC_REG_NUM_LCIDS_ARRIVING 0x104004 471 #define CFC_REG_NUM_LCIDS_INSIDE_PF 0x104120 472 /* [R 9] Number of Leaving LCIDs in Link List Block */ 473 #define CFC_REG_NUM_LCIDS_LEAVING 0x104018 474 #define CFC_REG_WEAK_ENABLE_PF 0x104124 475 /* [RW 8] The event id for aggregated interrupt 0 */ 476 #define CSDM_REG_AGG_INT_EVENT_0 0xc2038 477 #define CSDM_REG_AGG_INT_EVENT_10 0xc2060 478 #define CSDM_REG_AGG_INT_EVENT_11 0xc2064 479 #define CSDM_REG_AGG_INT_EVENT_12 0xc2068 480 #define CSDM_REG_AGG_INT_EVENT_13 0xc206c 481 #define CSDM_REG_AGG_INT_EVENT_14 0xc2070 482 #define CSDM_REG_AGG_INT_EVENT_15 0xc2074 483 #define CSDM_REG_AGG_INT_EVENT_16 0xc2078 484 #define CSDM_REG_AGG_INT_EVENT_2 0xc2040 485 #define CSDM_REG_AGG_INT_EVENT_3 0xc2044 486 #define CSDM_REG_AGG_INT_EVENT_4 0xc2048 487 #define CSDM_REG_AGG_INT_EVENT_5 0xc204c 488 #define CSDM_REG_AGG_INT_EVENT_6 0xc2050 489 #define CSDM_REG_AGG_INT_EVENT_7 0xc2054 490 #define CSDM_REG_AGG_INT_EVENT_8 0xc2058 491 #define CSDM_REG_AGG_INT_EVENT_9 0xc205c 492 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0) 493 or auto-mask-mode (1) */ 494 #define CSDM_REG_AGG_INT_MODE_10 0xc21e0 495 #define CSDM_REG_AGG_INT_MODE_11 0xc21e4 496 #define CSDM_REG_AGG_INT_MODE_12 0xc21e8 497 #define CSDM_REG_AGG_INT_MODE_13 0xc21ec 498 #define CSDM_REG_AGG_INT_MODE_14 0xc21f0 499 #define CSDM_REG_AGG_INT_MODE_15 0xc21f4 500 #define CSDM_REG_AGG_INT_MODE_16 0xc21f8 501 #define CSDM_REG_AGG_INT_MODE_6 0xc21d0 502 #define CSDM_REG_AGG_INT_MODE_7 0xc21d4 503 #define CSDM_REG_AGG_INT_MODE_8 0xc21d8 504 #define CSDM_REG_AGG_INT_MODE_9 0xc21dc 505 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 506 #define CSDM_REG_CFC_RSP_START_ADDR 0xc2008 507 /* [RW 16] The maximum value of the completion counter #0 */ 508 #define CSDM_REG_CMP_COUNTER_MAX0 0xc201c 509 /* [RW 16] The maximum value of the completion counter #1 */ 510 #define CSDM_REG_CMP_COUNTER_MAX1 0xc2020 511 /* [RW 16] The maximum value of the completion counter #2 */ 512 #define CSDM_REG_CMP_COUNTER_MAX2 0xc2024 513 /* [RW 16] The maximum value of the completion counter #3 */ 514 #define CSDM_REG_CMP_COUNTER_MAX3 0xc2028 515 /* [RW 13] The start address in the internal RAM for the completion 516 counters. */ 517 #define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c 518 /* [RW 32] Interrupt mask register #0 read/write */ 519 #define CSDM_REG_CSDM_INT_MASK_0 0xc229c 520 #define CSDM_REG_CSDM_INT_MASK_1 0xc22ac 521 /* [R 32] Interrupt register #0 read */ 522 #define CSDM_REG_CSDM_INT_STS_0 0xc2290 523 #define CSDM_REG_CSDM_INT_STS_1 0xc22a0 524 /* [RW 11] Parity mask register #0 read/write */ 525 #define CSDM_REG_CSDM_PRTY_MASK 0xc22bc 526 /* [R 11] Parity register #0 read */ 527 #define CSDM_REG_CSDM_PRTY_STS 0xc22b0 528 /* [RC 11] Parity register #0 read clear */ 529 #define CSDM_REG_CSDM_PRTY_STS_CLR 0xc22b4 530 #define CSDM_REG_ENABLE_IN1 0xc2238 531 #define CSDM_REG_ENABLE_IN2 0xc223c 532 #define CSDM_REG_ENABLE_OUT1 0xc2240 533 #define CSDM_REG_ENABLE_OUT2 0xc2244 534 /* [RW 4] The initial number of messages that can be sent to the pxp control 535 interface without receiving any ACK. */ 536 #define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc 537 /* [ST 32] The number of ACK after placement messages received */ 538 #define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c 539 /* [ST 32] The number of packet end messages received from the parser */ 540 #define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274 541 /* [ST 32] The number of requests received from the pxp async if */ 542 #define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278 543 /* [ST 32] The number of commands received in queue 0 */ 544 #define CSDM_REG_NUM_OF_Q0_CMD 0xc2248 545 /* [ST 32] The number of commands received in queue 10 */ 546 #define CSDM_REG_NUM_OF_Q10_CMD 0xc226c 547 /* [ST 32] The number of commands received in queue 11 */ 548 #define CSDM_REG_NUM_OF_Q11_CMD 0xc2270 549 /* [ST 32] The number of commands received in queue 1 */ 550 #define CSDM_REG_NUM_OF_Q1_CMD 0xc224c 551 /* [ST 32] The number of commands received in queue 3 */ 552 #define CSDM_REG_NUM_OF_Q3_CMD 0xc2250 553 /* [ST 32] The number of commands received in queue 4 */ 554 #define CSDM_REG_NUM_OF_Q4_CMD 0xc2254 555 /* [ST 32] The number of commands received in queue 5 */ 556 #define CSDM_REG_NUM_OF_Q5_CMD 0xc2258 557 /* [ST 32] The number of commands received in queue 6 */ 558 #define CSDM_REG_NUM_OF_Q6_CMD 0xc225c 559 /* [ST 32] The number of commands received in queue 7 */ 560 #define CSDM_REG_NUM_OF_Q7_CMD 0xc2260 561 /* [ST 32] The number of commands received in queue 8 */ 562 #define CSDM_REG_NUM_OF_Q8_CMD 0xc2264 563 /* [ST 32] The number of commands received in queue 9 */ 564 #define CSDM_REG_NUM_OF_Q9_CMD 0xc2268 565 /* [RW 13] The start address in the internal RAM for queue counters */ 566 #define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010 567 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 568 #define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548 569 /* [R 1] parser fifo empty in sdm_sync block */ 570 #define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550 571 /* [R 1] parser serial fifo empty in sdm_sync block */ 572 #define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558 573 /* [RW 32] Tick for timer counter. Applicable only when 574 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */ 575 #define CSDM_REG_TIMER_TICK 0xc2000 576 /* [RW 5] The number of time_slots in the arbitration cycle */ 577 #define CSEM_REG_ARB_CYCLE_SIZE 0x200034 578 /* [RW 3] The source that is associated with arbitration element 0. Source 579 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 580 sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 581 #define CSEM_REG_ARB_ELEMENT0 0x200020 582 /* [RW 3] The source that is associated with arbitration element 1. Source 583 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 584 sleeping thread with priority 1; 4- sleeping thread with priority 2. 585 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */ 586 #define CSEM_REG_ARB_ELEMENT1 0x200024 587 /* [RW 3] The source that is associated with arbitration element 2. Source 588 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 589 sleeping thread with priority 1; 4- sleeping thread with priority 2. 590 Could not be equal to register ~csem_registers_arb_element0.arb_element0 591 and ~csem_registers_arb_element1.arb_element1 */ 592 #define CSEM_REG_ARB_ELEMENT2 0x200028 593 /* [RW 3] The source that is associated with arbitration element 3. Source 594 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 595 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 596 not be equal to register ~csem_registers_arb_element0.arb_element0 and 597 ~csem_registers_arb_element1.arb_element1 and 598 ~csem_registers_arb_element2.arb_element2 */ 599 #define CSEM_REG_ARB_ELEMENT3 0x20002c 600 /* [RW 3] The source that is associated with arbitration element 4. Source 601 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 602 sleeping thread with priority 1; 4- sleeping thread with priority 2. 603 Could not be equal to register ~csem_registers_arb_element0.arb_element0 604 and ~csem_registers_arb_element1.arb_element1 and 605 ~csem_registers_arb_element2.arb_element2 and 606 ~csem_registers_arb_element3.arb_element3 */ 607 #define CSEM_REG_ARB_ELEMENT4 0x200030 608 /* [RW 32] Interrupt mask register #0 read/write */ 609 #define CSEM_REG_CSEM_INT_MASK_0 0x200110 610 #define CSEM_REG_CSEM_INT_MASK_1 0x200120 611 /* [R 32] Interrupt register #0 read */ 612 #define CSEM_REG_CSEM_INT_STS_0 0x200104 613 #define CSEM_REG_CSEM_INT_STS_1 0x200114 614 /* [RW 32] Parity mask register #0 read/write */ 615 #define CSEM_REG_CSEM_PRTY_MASK_0 0x200130 616 #define CSEM_REG_CSEM_PRTY_MASK_1 0x200140 617 /* [R 32] Parity register #0 read */ 618 #define CSEM_REG_CSEM_PRTY_STS_0 0x200124 619 #define CSEM_REG_CSEM_PRTY_STS_1 0x200134 620 /* [RC 32] Parity register #0 read clear */ 621 #define CSEM_REG_CSEM_PRTY_STS_CLR_0 0x200128 622 #define CSEM_REG_CSEM_PRTY_STS_CLR_1 0x200138 623 #define CSEM_REG_ENABLE_IN 0x2000a4 624 #define CSEM_REG_ENABLE_OUT 0x2000a8 625 /* [RW 32] This address space contains all registers and memories that are 626 placed in SEM_FAST block. The SEM_FAST registers are described in 627 appendix B. In order to access the sem_fast registers the base address 628 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 629 #define CSEM_REG_FAST_MEMORY 0x220000 630 /* [RW 1] Disables input messages from FIC0 May be updated during run_time 631 by the microcode */ 632 #define CSEM_REG_FIC0_DISABLE 0x200224 633 /* [RW 1] Disables input messages from FIC1 May be updated during run_time 634 by the microcode */ 635 #define CSEM_REG_FIC1_DISABLE 0x200234 636 /* [RW 15] Interrupt table Read and write access to it is not possible in 637 the middle of the work */ 638 #define CSEM_REG_INT_TABLE 0x200400 639 /* [ST 24] Statistics register. The number of messages that entered through 640 FIC0 */ 641 #define CSEM_REG_MSG_NUM_FIC0 0x200000 642 /* [ST 24] Statistics register. The number of messages that entered through 643 FIC1 */ 644 #define CSEM_REG_MSG_NUM_FIC1 0x200004 645 /* [ST 24] Statistics register. The number of messages that were sent to 646 FOC0 */ 647 #define CSEM_REG_MSG_NUM_FOC0 0x200008 648 /* [ST 24] Statistics register. The number of messages that were sent to 649 FOC1 */ 650 #define CSEM_REG_MSG_NUM_FOC1 0x20000c 651 /* [ST 24] Statistics register. The number of messages that were sent to 652 FOC2 */ 653 #define CSEM_REG_MSG_NUM_FOC2 0x200010 654 /* [ST 24] Statistics register. The number of messages that were sent to 655 FOC3 */ 656 #define CSEM_REG_MSG_NUM_FOC3 0x200014 657 /* [RW 1] Disables input messages from the passive buffer May be updated 658 during run_time by the microcode */ 659 #define CSEM_REG_PAS_DISABLE 0x20024c 660 /* [WB 128] Debug only. Passive buffer memory */ 661 #define CSEM_REG_PASSIVE_BUFFER 0x202000 662 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 663 #define CSEM_REG_PRAM 0x240000 664 /* [R 16] Valid sleeping threads indication have bit per thread */ 665 #define CSEM_REG_SLEEP_THREADS_VALID 0x20026c 666 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 667 #define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0 668 /* [RW 16] List of free threads . There is a bit per thread. */ 669 #define CSEM_REG_THREADS_LIST 0x2002e4 670 /* [RW 3] The arbitration scheme of time_slot 0 */ 671 #define CSEM_REG_TS_0_AS 0x200038 672 /* [RW 3] The arbitration scheme of time_slot 10 */ 673 #define CSEM_REG_TS_10_AS 0x200060 674 /* [RW 3] The arbitration scheme of time_slot 11 */ 675 #define CSEM_REG_TS_11_AS 0x200064 676 /* [RW 3] The arbitration scheme of time_slot 12 */ 677 #define CSEM_REG_TS_12_AS 0x200068 678 /* [RW 3] The arbitration scheme of time_slot 13 */ 679 #define CSEM_REG_TS_13_AS 0x20006c 680 /* [RW 3] The arbitration scheme of time_slot 14 */ 681 #define CSEM_REG_TS_14_AS 0x200070 682 /* [RW 3] The arbitration scheme of time_slot 15 */ 683 #define CSEM_REG_TS_15_AS 0x200074 684 /* [RW 3] The arbitration scheme of time_slot 16 */ 685 #define CSEM_REG_TS_16_AS 0x200078 686 /* [RW 3] The arbitration scheme of time_slot 17 */ 687 #define CSEM_REG_TS_17_AS 0x20007c 688 /* [RW 3] The arbitration scheme of time_slot 18 */ 689 #define CSEM_REG_TS_18_AS 0x200080 690 /* [RW 3] The arbitration scheme of time_slot 1 */ 691 #define CSEM_REG_TS_1_AS 0x20003c 692 /* [RW 3] The arbitration scheme of time_slot 2 */ 693 #define CSEM_REG_TS_2_AS 0x200040 694 /* [RW 3] The arbitration scheme of time_slot 3 */ 695 #define CSEM_REG_TS_3_AS 0x200044 696 /* [RW 3] The arbitration scheme of time_slot 4 */ 697 #define CSEM_REG_TS_4_AS 0x200048 698 /* [RW 3] The arbitration scheme of time_slot 5 */ 699 #define CSEM_REG_TS_5_AS 0x20004c 700 /* [RW 3] The arbitration scheme of time_slot 6 */ 701 #define CSEM_REG_TS_6_AS 0x200050 702 /* [RW 3] The arbitration scheme of time_slot 7 */ 703 #define CSEM_REG_TS_7_AS 0x200054 704 /* [RW 3] The arbitration scheme of time_slot 8 */ 705 #define CSEM_REG_TS_8_AS 0x200058 706 /* [RW 3] The arbitration scheme of time_slot 9 */ 707 #define CSEM_REG_TS_9_AS 0x20005c 708 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 709 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ 710 #define CSEM_REG_VFPF_ERR_NUM 0x200380 711 /* [RW 1] Parity mask register #0 read/write */ 712 #define DBG_REG_DBG_PRTY_MASK 0xc0a8 713 /* [R 1] Parity register #0 read */ 714 #define DBG_REG_DBG_PRTY_STS 0xc09c 715 /* [RC 1] Parity register #0 read clear */ 716 #define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0 717 /* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The 718 * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0; 719 * 4.Completion function=0; 5.Error handling=0 */ 720 #define DMAE_REG_BACKWARD_COMP_EN 0x10207c 721 /* [RW 32] Commands memory. The address to command X; row Y is to calculated 722 as 14*X+Y. */ 723 #define DMAE_REG_CMD_MEM 0x102400 724 #define DMAE_REG_CMD_MEM_SIZE 224 725 /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c 726 initial value is all ones. */ 727 #define DMAE_REG_CRC16C_INIT 0x10201c 728 /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the 729 CRC-16 T10 initial value is all ones. */ 730 #define DMAE_REG_CRC16T10_INIT 0x102020 731 /* [RW 2] Interrupt mask register #0 read/write */ 732 #define DMAE_REG_DMAE_INT_MASK 0x102054 733 /* [RW 4] Parity mask register #0 read/write */ 734 #define DMAE_REG_DMAE_PRTY_MASK 0x102064 735 /* [R 4] Parity register #0 read */ 736 #define DMAE_REG_DMAE_PRTY_STS 0x102058 737 /* [RC 4] Parity register #0 read clear */ 738 #define DMAE_REG_DMAE_PRTY_STS_CLR 0x10205c 739 /* [RW 1] Command 0 go. */ 740 #define DMAE_REG_GO_C0 0x102080 741 /* [RW 1] Command 1 go. */ 742 #define DMAE_REG_GO_C1 0x102084 743 /* [RW 1] Command 10 go. */ 744 #define DMAE_REG_GO_C10 0x102088 745 /* [RW 1] Command 11 go. */ 746 #define DMAE_REG_GO_C11 0x10208c 747 /* [RW 1] Command 12 go. */ 748 #define DMAE_REG_GO_C12 0x102090 749 /* [RW 1] Command 13 go. */ 750 #define DMAE_REG_GO_C13 0x102094 751 /* [RW 1] Command 14 go. */ 752 #define DMAE_REG_GO_C14 0x102098 753 /* [RW 1] Command 15 go. */ 754 #define DMAE_REG_GO_C15 0x10209c 755 /* [RW 1] Command 2 go. */ 756 #define DMAE_REG_GO_C2 0x1020a0 757 /* [RW 1] Command 3 go. */ 758 #define DMAE_REG_GO_C3 0x1020a4 759 /* [RW 1] Command 4 go. */ 760 #define DMAE_REG_GO_C4 0x1020a8 761 /* [RW 1] Command 5 go. */ 762 #define DMAE_REG_GO_C5 0x1020ac 763 /* [RW 1] Command 6 go. */ 764 #define DMAE_REG_GO_C6 0x1020b0 765 /* [RW 1] Command 7 go. */ 766 #define DMAE_REG_GO_C7 0x1020b4 767 /* [RW 1] Command 8 go. */ 768 #define DMAE_REG_GO_C8 0x1020b8 769 /* [RW 1] Command 9 go. */ 770 #define DMAE_REG_GO_C9 0x1020bc 771 /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge 772 input is disregarded; valid is deasserted; all other signals are treated 773 as usual; if 1 - normal activity. */ 774 #define DMAE_REG_GRC_IFEN 0x102008 775 /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the 776 acknowledge input is disregarded; valid is deasserted; full is asserted; 777 all other signals are treated as usual; if 1 - normal activity. */ 778 #define DMAE_REG_PCI_IFEN 0x102004 779 /* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the 780 initial value to the credit counter; related to the address. Read returns 781 the current value of the counter. */ 782 #define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0 783 /* [RW 8] Aggregation command. */ 784 #define DORQ_REG_AGG_CMD0 0x170060 785 /* [RW 8] Aggregation command. */ 786 #define DORQ_REG_AGG_CMD1 0x170064 787 /* [RW 8] Aggregation command. */ 788 #define DORQ_REG_AGG_CMD2 0x170068 789 /* [RW 8] Aggregation command. */ 790 #define DORQ_REG_AGG_CMD3 0x17006c 791 /* [RW 28] UCM Header. */ 792 #define DORQ_REG_CMHEAD_RX 0x170050 793 /* [RW 32] Doorbell address for RBC doorbells (function 0). */ 794 #define DORQ_REG_DB_ADDR0 0x17008c 795 /* [RW 5] Interrupt mask register #0 read/write */ 796 #define DORQ_REG_DORQ_INT_MASK 0x170180 797 /* [R 5] Interrupt register #0 read */ 798 #define DORQ_REG_DORQ_INT_STS 0x170174 799 /* [RC 5] Interrupt register #0 read clear */ 800 #define DORQ_REG_DORQ_INT_STS_CLR 0x170178 801 /* [RW 2] Parity mask register #0 read/write */ 802 #define DORQ_REG_DORQ_PRTY_MASK 0x170190 803 /* [R 2] Parity register #0 read */ 804 #define DORQ_REG_DORQ_PRTY_STS 0x170184 805 /* [RC 2] Parity register #0 read clear */ 806 #define DORQ_REG_DORQ_PRTY_STS_CLR 0x170188 807 /* [RW 8] The address to write the DPM CID to STORM. */ 808 #define DORQ_REG_DPM_CID_ADDR 0x170044 809 /* [RW 5] The DPM mode CID extraction offset. */ 810 #define DORQ_REG_DPM_CID_OFST 0x170030 811 /* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */ 812 #define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c 813 /* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */ 814 #define DORQ_REG_DQ_FIFO_FULL_TH 0x170078 815 /* [R 13] Current value of the DQ FIFO fill level according to following 816 pointer. The range is 0 - 256 FIFO rows; where each row stands for the 817 doorbell. */ 818 #define DORQ_REG_DQ_FILL_LVLF 0x1700a4 819 /* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or 820 equal to full threshold; reset on full clear. */ 821 #define DORQ_REG_DQ_FULL_ST 0x1700c0 822 /* [RW 28] The value sent to CM header in the case of CFC load error. */ 823 #define DORQ_REG_ERR_CMHEAD 0x170058 824 #define DORQ_REG_IF_EN 0x170004 825 #define DORQ_REG_MODE_ACT 0x170008 826 /* [RW 5] The normal mode CID extraction offset. */ 827 #define DORQ_REG_NORM_CID_OFST 0x17002c 828 /* [RW 28] TCM Header when only TCP context is loaded. */ 829 #define DORQ_REG_NORM_CMHEAD_TX 0x17004c 830 /* [RW 3] The number of simultaneous outstanding requests to Context Fetch 831 Interface. */ 832 #define DORQ_REG_OUTST_REQ 0x17003c 833 #define DORQ_REG_PF_USAGE_CNT 0x1701d0 834 #define DORQ_REG_REGN 0x170038 835 /* [R 4] Current value of response A counter credit. Initial credit is 836 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd 837 register. */ 838 #define DORQ_REG_RSPA_CRD_CNT 0x1700ac 839 /* [R 4] Current value of response B counter credit. Initial credit is 840 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd 841 register. */ 842 #define DORQ_REG_RSPB_CRD_CNT 0x1700b0 843 /* [RW 4] The initial credit at the Doorbell Response Interface. The write 844 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The 845 read reads this written value. */ 846 #define DORQ_REG_RSP_INIT_CRD 0x170048 847 /* [RW 4] Initial activity counter value on the load request; when the 848 shortcut is done. */ 849 #define DORQ_REG_SHRT_ACT_CNT 0x170070 850 /* [RW 28] TCM Header when both ULP and TCP context is loaded. */ 851 #define DORQ_REG_SHRT_CMHEAD 0x170054 852 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4) 853 #define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1<<0) 854 #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3) 855 #define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7) 856 #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2) 857 #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1) 858 #define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1<<0) 859 #define HC_REG_AGG_INT_0 0x108050 860 #define HC_REG_AGG_INT_1 0x108054 861 #define HC_REG_ATTN_BIT 0x108120 862 #define HC_REG_ATTN_IDX 0x108100 863 #define HC_REG_ATTN_MSG0_ADDR_L 0x108018 864 #define HC_REG_ATTN_MSG1_ADDR_L 0x108020 865 #define HC_REG_ATTN_NUM_P0 0x108038 866 #define HC_REG_ATTN_NUM_P1 0x10803c 867 #define HC_REG_COMMAND_REG 0x108180 868 #define HC_REG_CONFIG_0 0x108000 869 #define HC_REG_CONFIG_1 0x108004 870 #define HC_REG_FUNC_NUM_P0 0x1080ac 871 #define HC_REG_FUNC_NUM_P1 0x1080b0 872 /* [RW 3] Parity mask register #0 read/write */ 873 #define HC_REG_HC_PRTY_MASK 0x1080a0 874 /* [R 3] Parity register #0 read */ 875 #define HC_REG_HC_PRTY_STS 0x108094 876 /* [RC 3] Parity register #0 read clear */ 877 #define HC_REG_HC_PRTY_STS_CLR 0x108098 878 #define HC_REG_INT_MASK 0x108108 879 #define HC_REG_LEADING_EDGE_0 0x108040 880 #define HC_REG_LEADING_EDGE_1 0x108048 881 #define HC_REG_MAIN_MEMORY 0x108800 882 #define HC_REG_MAIN_MEMORY_SIZE 152 883 #define HC_REG_P0_PROD_CONS 0x108200 884 #define HC_REG_P1_PROD_CONS 0x108400 885 #define HC_REG_PBA_COMMAND 0x108140 886 #define HC_REG_PCI_CONFIG_0 0x108010 887 #define HC_REG_PCI_CONFIG_1 0x108014 888 #define HC_REG_STATISTIC_COUNTERS 0x109000 889 #define HC_REG_TRAILING_EDGE_0 0x108044 890 #define HC_REG_TRAILING_EDGE_1 0x10804c 891 #define HC_REG_UC_RAM_ADDR_0 0x108028 892 #define HC_REG_UC_RAM_ADDR_1 0x108030 893 #define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068 894 #define HC_REG_VQID_0 0x108008 895 #define HC_REG_VQID_1 0x10800c 896 #define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1) 897 #define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1<<0) 898 #define IGU_REG_ATTENTION_ACK_BITS 0x130108 899 /* [R 4] Debug: attn_fsm */ 900 #define IGU_REG_ATTN_FSM 0x130054 901 #define IGU_REG_ATTN_MSG_ADDR_H 0x13011c 902 #define IGU_REG_ATTN_MSG_ADDR_L 0x130120 903 /* [R 4] Debug: [3] - attention write done message is pending (0-no pending; 904 * 1-pending). [2:0] = PFID. Pending means attention message was sent; but 905 * write done didn't receive. */ 906 #define IGU_REG_ATTN_WRITE_DONE_PENDING 0x130030 907 #define IGU_REG_BLOCK_CONFIGURATION 0x130000 908 #define IGU_REG_COMMAND_REG_32LSB_DATA 0x130124 909 #define IGU_REG_COMMAND_REG_CTRL 0x13012c 910 /* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit 911 * is clear. The bits in this registers are set and clear via the producer 912 * command. Data valid only in addresses 0-4. all the rest are zero. */ 913 #define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP 0x130200 914 /* [R 5] Debug: ctrl_fsm */ 915 #define IGU_REG_CTRL_FSM 0x130064 916 /* [R 1] data available for error memory. If this bit is clear do not red 917 * from error_handling_memory. */ 918 #define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130 919 /* [RW 11] Parity mask register #0 read/write */ 920 #define IGU_REG_IGU_PRTY_MASK 0x1300a8 921 /* [R 11] Parity register #0 read */ 922 #define IGU_REG_IGU_PRTY_STS 0x13009c 923 /* [RC 11] Parity register #0 read clear */ 924 #define IGU_REG_IGU_PRTY_STS_CLR 0x1300a0 925 /* [R 4] Debug: int_handle_fsm */ 926 #define IGU_REG_INT_HANDLE_FSM 0x130050 927 #define IGU_REG_LEADING_EDGE_LATCH 0x130134 928 /* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid. 929 * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF 930 * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */ 931 #define IGU_REG_MAPPING_MEMORY 0x131000 932 #define IGU_REG_MAPPING_MEMORY_SIZE 136 933 #define IGU_REG_PBA_STATUS_LSB 0x130138 934 #define IGU_REG_PBA_STATUS_MSB 0x13013c 935 #define IGU_REG_PCI_PF_MSI_EN 0x130140 936 #define IGU_REG_PCI_PF_MSIX_EN 0x130144 937 #define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148 938 /* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no 939 * pending; 1 = pending. Pendings means interrupt was asserted; and write 940 * done was not received. Data valid only in addresses 0-4. all the rest are 941 * zero. */ 942 #define IGU_REG_PENDING_BITS_STATUS 0x130300 943 #define IGU_REG_PF_CONFIGURATION 0x130154 944 /* [RW 20] producers only. E2 mode: address 0-135 match to the mapping 945 * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default 946 * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod; 947 * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode 948 * - In backward compatible mode; for non default SB; each even line in the 949 * memory holds the U producer and each odd line hold the C producer. The 950 * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The 951 * last 20 producers are for the DSB for each PF. each PF has five segments 952 * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 953 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; */ 954 #define IGU_REG_PROD_CONS_MEMORY 0x132000 955 /* [R 3] Debug: pxp_arb_fsm */ 956 #define IGU_REG_PXP_ARB_FSM 0x130068 957 /* [RW 6] Write one for each bit will reset the appropriate memory. When the 958 * memory reset finished the appropriate bit will be clear. Bit 0 - mapping 959 * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3 960 * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; */ 961 #define IGU_REG_RESET_MEMORIES 0x130158 962 /* [R 4] Debug: sb_ctrl_fsm */ 963 #define IGU_REG_SB_CTRL_FSM 0x13004c 964 #define IGU_REG_SB_INT_BEFORE_MASK_LSB 0x13015c 965 #define IGU_REG_SB_INT_BEFORE_MASK_MSB 0x130160 966 #define IGU_REG_SB_MASK_LSB 0x130164 967 #define IGU_REG_SB_MASK_MSB 0x130168 968 /* [RW 16] Number of command that were dropped without causing an interrupt 969 * due to: read access for WO BAR address; or write access for RO BAR 970 * address or any access for reserved address or PCI function error is set 971 * and address is not MSIX; PBA or cleanup */ 972 #define IGU_REG_SILENT_DROP 0x13016c 973 /* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 - 974 * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per 975 * PF; 68-71 number of ATTN messages per PF */ 976 #define IGU_REG_STATISTIC_NUM_MESSAGE_SENT 0x130800 977 /* [RW 32] Number of cycles the timer mask masking the IGU interrupt when a 978 * timer mask command arrives. Value must be bigger than 100. */ 979 #define IGU_REG_TIMER_MASKING_VALUE 0x13003c 980 #define IGU_REG_TRAILING_EDGE_LATCH 0x130104 981 #define IGU_REG_VF_CONFIGURATION 0x130170 982 /* [WB_R 32] Each bit represent write done pending bits status for that SB 983 * (MSI/MSIX message was sent and write done was not received yet). 0 = 984 * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */ 985 #define IGU_REG_WRITE_DONE_PENDING 0x130480 986 #define MCP_A_REG_MCPR_SCRATCH 0x3a0000 987 #define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c 988 #define MCP_REG_MCPR_GP_INPUTS 0x800c0 989 #define MCP_REG_MCPR_GP_OENABLE 0x800c8 990 #define MCP_REG_MCPR_GP_OUTPUTS 0x800c4 991 #define MCP_REG_MCPR_IMC_COMMAND 0x85900 992 #define MCP_REG_MCPR_IMC_DATAREG0 0x85920 993 #define MCP_REG_MCPR_IMC_SLAVE_CONTROL 0x85904 994 #define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c 995 #define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424 996 #define MCP_REG_MCPR_NVM_ADDR 0x8640c 997 #define MCP_REG_MCPR_NVM_CFG4 0x8642c 998 #define MCP_REG_MCPR_NVM_COMMAND 0x86400 999 #define MCP_REG_MCPR_NVM_READ 0x86410 1000 #define MCP_REG_MCPR_NVM_SW_ARB 0x86420 1001 #define MCP_REG_MCPR_NVM_WRITE 0x86408 1002 #define MCP_REG_MCPR_SCRATCH 0xa0000 1003 #define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1<<1) 1004 #define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1<<0) 1005 /* [R 32] read first 32 bit after inversion of function 0. mapped as 1006 follows: [0] NIG attention for function0; [1] NIG attention for 1007 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; 1008 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] 1009 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE 1010 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; 1011 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] 1012 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB 1013 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw 1014 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity 1015 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw 1016 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF 1017 Parity error; [31] PBF Hw interrupt; */ 1018 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c 1019 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430 1020 /* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0] 1021 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 1022 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; 1023 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] 1024 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event 1025 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP 1026 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for 1027 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] 1028 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC 1029 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw 1030 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI 1031 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw 1032 interrupt; */ 1033 #define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434 1034 /* [R 32] read second 32 bit after inversion of function 0. mapped as 1035 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1036 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1037 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1038 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1039 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1040 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1041 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1042 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1043 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1044 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1045 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1046 interrupt; */ 1047 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438 1048 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c 1049 /* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0] 1050 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error; 1051 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; 1052 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] 1053 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] 1054 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity 1055 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux 1056 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; 1057 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; 1058 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; 1059 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; 1060 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */ 1061 #define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440 1062 /* [R 32] read third 32 bit after inversion of function 0. mapped as 1063 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity 1064 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] 1065 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1066 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1067 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1068 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1069 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1070 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1071 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1072 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1073 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1074 attn1; */ 1075 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444 1076 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448 1077 /* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0] 1078 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP 1079 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient 1080 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity 1081 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw 1082 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] 1083 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] 1084 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW 1085 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 1086 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 1087 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW 1088 timers attn_4 func1; [30] General attn0; [31] General attn1; */ 1089 #define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c 1090 /* [R 32] read fourth 32 bit after inversion of function 0. mapped as 1091 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1092 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1093 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1094 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1095 [14] General attn16; [15] General attn17; [16] General attn18; [17] 1096 General attn19; [18] General attn20; [19] General attn21; [20] Main power 1097 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1098 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1099 Latched timeout attention; [27] GRC Latched reserved access attention; 1100 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1101 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1102 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450 1103 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454 1104 /* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0] 1105 General attn2; [1] General attn3; [2] General attn4; [3] General attn5; 1106 [4] General attn6; [5] General attn7; [6] General attn8; [7] General 1107 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] 1108 General attn13; [12] General attn14; [13] General attn15; [14] General 1109 attn16; [15] General attn17; [16] General attn18; [17] General attn19; 1110 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] 1111 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] 1112 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout 1113 attention; [27] GRC Latched reserved access attention; [28] MCP Latched 1114 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched 1115 ump_tx_parity; [31] MCP Latched scpad_parity; */ 1116 #define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458 1117 /* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as 1118 * follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC 1119 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] 1120 * CNIG attention (reserved); [7] CNIG parity (reserved); [31-8] Reserved; */ 1121 #define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 0xa700 1122 /* [W 14] write to this register results with the clear of the latched 1123 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in 1124 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP 1125 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears 1126 GRC Latched reserved access attention; one in d7 clears Latched 1127 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears 1128 Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both 1129 ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears 1130 pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read 1131 from this register return zero */ 1132 #define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c 1133 /* [RW 32] first 32b for enabling the output for function 0 output0. mapped 1134 as follows: [0] NIG attention for function0; [1] NIG attention for 1135 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 1136 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 1137 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1138 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1139 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1140 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X 1141 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 1142 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 1143 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 1144 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 1145 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1146 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c 1147 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c 1148 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c 1149 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c 1150 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc 1151 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc 1152 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc 1153 /* [RW 32] first 32b for enabling the output for function 1 output0. mapped 1154 as follows: [0] NIG attention for function0; [1] NIG attention for 1155 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function 1156 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 1157 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1158 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1159 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1160 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X 1161 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 1162 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 1163 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 1164 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 1165 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1166 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c 1167 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c 1168 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c 1169 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c 1170 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c 1171 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c 1172 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c 1173 /* [RW 32] first 32b for enabling the output for close the gate nig. mapped 1174 as follows: [0] NIG attention for function0; [1] NIG attention for 1175 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 1176 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 1177 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1178 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1179 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1180 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X 1181 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 1182 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 1183 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 1184 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 1185 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1186 #define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec 1187 #define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c 1188 /* [RW 32] first 32b for enabling the output for close the gate pxp. mapped 1189 as follows: [0] NIG attention for function0; [1] NIG attention for 1190 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 1191 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 1192 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1193 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1194 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1195 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X 1196 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 1197 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 1198 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 1199 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 1200 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1201 #define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc 1202 #define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c 1203 /* [RW 32] second 32b for enabling the output for function 0 output0. mapped 1204 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1205 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1206 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1207 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1208 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1209 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1210 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1211 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1212 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1213 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1214 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1215 interrupt; */ 1216 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070 1217 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080 1218 /* [RW 32] second 32b for enabling the output for function 1 output0. mapped 1219 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1220 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1221 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1222 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1223 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1224 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1225 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1226 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1227 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1228 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1229 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1230 interrupt; */ 1231 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110 1232 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120 1233 /* [RW 32] second 32b for enabling the output for close the gate nig. mapped 1234 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1235 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1236 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1237 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1238 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1239 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1240 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1241 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1242 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1243 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1244 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1245 interrupt; */ 1246 #define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0 1247 #define MISC_REG_AEU_ENABLE2_NIG_1 0xa190 1248 /* [RW 32] second 32b for enabling the output for close the gate pxp. mapped 1249 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1250 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1251 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1252 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1253 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1254 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1255 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1256 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1257 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1258 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1259 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1260 interrupt; */ 1261 #define MISC_REG_AEU_ENABLE2_PXP_0 0xa100 1262 #define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0 1263 /* [RW 32] third 32b for enabling the output for function 0 output0. mapped 1264 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP 1265 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; 1266 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1267 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1268 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1269 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1270 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1271 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1272 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1273 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1274 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1275 attn1; */ 1276 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074 1277 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084 1278 /* [RW 32] third 32b for enabling the output for function 1 output0. mapped 1279 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP 1280 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; 1281 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1282 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1283 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1284 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1285 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1286 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1287 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1288 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1289 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1290 attn1; */ 1291 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114 1292 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124 1293 /* [RW 32] third 32b for enabling the output for close the gate nig. mapped 1294 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP 1295 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; 1296 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1297 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1298 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1299 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1300 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1301 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1302 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1303 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1304 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1305 attn1; */ 1306 #define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4 1307 #define MISC_REG_AEU_ENABLE3_NIG_1 0xa194 1308 /* [RW 32] third 32b for enabling the output for close the gate pxp. mapped 1309 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP 1310 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; 1311 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1312 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1313 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1314 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1315 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1316 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1317 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1318 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1319 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1320 attn1; */ 1321 #define MISC_REG_AEU_ENABLE3_PXP_0 0xa104 1322 #define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4 1323 /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped 1324 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1325 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1326 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1327 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1328 [14] General attn16; [15] General attn17; [16] General attn18; [17] 1329 General attn19; [18] General attn20; [19] General attn21; [20] Main power 1330 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1331 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1332 Latched timeout attention; [27] GRC Latched reserved access attention; 1333 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1334 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1335 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078 1336 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098 1337 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8 1338 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8 1339 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8 1340 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8 1341 /* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped 1342 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1343 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1344 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1345 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1346 [14] General attn16; [15] General attn17; [16] General attn18; [17] 1347 General attn19; [18] General attn20; [19] General attn21; [20] Main power 1348 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1349 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1350 Latched timeout attention; [27] GRC Latched reserved access attention; 1351 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1352 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1353 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118 1354 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138 1355 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158 1356 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168 1357 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178 1358 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188 1359 /* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped 1360 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1361 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1362 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1363 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1364 [14] General attn16; [15] General attn17; [16] General attn18; [17] 1365 General attn19; [18] General attn20; [19] General attn21; [20] Main power 1366 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1367 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1368 Latched timeout attention; [27] GRC Latched reserved access attention; 1369 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1370 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1371 #define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8 1372 #define MISC_REG_AEU_ENABLE4_NIG_1 0xa198 1373 /* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped 1374 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1375 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1376 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1377 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1378 [14] General attn16; [15] General attn17; [16] General attn18; [17] 1379 General attn19; [18] General attn20; [19] General attn21; [20] Main power 1380 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1381 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1382 Latched timeout attention; [27] GRC Latched reserved access attention; 1383 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1384 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1385 #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108 1386 #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8 1387 /* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped 1388 * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC 1389 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] 1390 * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 1391 * parity; [31-10] Reserved; */ 1392 #define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 0xa688 1393 /* [RW 32] Fifth 32b for enabling the output for function 1 output0. Mapped 1394 * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC 1395 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] 1396 * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 1397 * parity; [31-10] Reserved; */ 1398 #define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 0xa6b0 1399 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu 1400 128 bit vector */ 1401 #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000 1402 #define MISC_REG_AEU_GENERAL_ATTN_1 0xa004 1403 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028 1404 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c 1405 #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030 1406 #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008 1407 #define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c 1408 #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010 1409 #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014 1410 #define MISC_REG_AEU_GENERAL_ATTN_6 0xa018 1411 #define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c 1412 #define MISC_REG_AEU_GENERAL_ATTN_8 0xa020 1413 #define MISC_REG_AEU_GENERAL_ATTN_9 0xa024 1414 #define MISC_REG_AEU_GENERAL_MASK 0xa61c 1415 /* [RW 32] first 32b for inverting the input for function 0; for each bit: 1416 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for 1417 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; 1418 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; 1419 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1420 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1421 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1422 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication 1423 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS 1424 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw 1425 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM 1426 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI 1427 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1428 #define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c 1429 #define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c 1430 /* [RW 32] second 32b for inverting the input for function 0; for each bit: 1431 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity 1432 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw 1433 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM 1434 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw 1435 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] 1436 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity 1437 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux 1438 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; 1439 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; 1440 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; 1441 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; 1442 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */ 1443 #define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230 1444 #define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240 1445 /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0; 1446 [9:8] = raserved. Zero = mask; one = unmask */ 1447 #define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060 1448 #define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064 1449 /* [RW 1] If set a system kill occurred */ 1450 #define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610 1451 /* [RW 32] Represent the status of the input vector to the AEU when a system 1452 kill occurred. The register is reset in por reset. Mapped as follows: [0] 1453 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 1454 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; 1455 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] 1456 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event 1457 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP 1458 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for 1459 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] 1460 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC 1461 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw 1462 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI 1463 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw 1464 interrupt; */ 1465 #define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600 1466 #define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604 1467 #define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608 1468 #define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c 1469 /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1 1470 Port. */ 1471 #define MISC_REG_BOND_ID 0xa400 1472 /* [R 8] These bits indicate the metal revision of the chip. This value 1473 starts at 0x00 for each all-layer tape-out and increments by one for each 1474 tape-out. */ 1475 #define MISC_REG_CHIP_METAL 0xa404 1476 /* [R 16] These bits indicate the part number for the chip. */ 1477 #define MISC_REG_CHIP_NUM 0xa408 1478 /* [R 4] These bits indicate the base revision of the chip. This value 1479 starts at 0x0 for the A0 tape-out and increments by one for each 1480 all-layer tape-out. */ 1481 #define MISC_REG_CHIP_REV 0xa40c 1482 /* [RW 32] The following driver registers(1...16) represent 16 drivers and 1483 32 clients. Each client can be controlled by one driver only. One in each 1484 bit represent that this driver control the appropriate client (Ex: bit 5 1485 is set means this driver control client number 5). addr1 = set; addr0 = 1486 clear; read from both addresses will give the same result = status. write 1487 to address 1 will set a request to control all the clients that their 1488 appropriate bit (in the write command) is set. if the client is free (the 1489 appropriate bit in all the other drivers is clear) one will be written to 1490 that driver register; if the client isn't free the bit will remain zero. 1491 if the appropriate bit is set (the driver request to gain control on a 1492 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW 1493 interrupt will be asserted). write to address 0 will set a request to 1494 free all the clients that their appropriate bit (in the write command) is 1495 set. if the appropriate bit is clear (the driver request to free a client 1496 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will 1497 be asserted). */ 1498 #define MISC_REG_DRIVER_CONTROL_1 0xa510 1499 #define MISC_REG_DRIVER_CONTROL_7 0xa3c8 1500 /* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0 1501 only. */ 1502 #define MISC_REG_E1HMF_MODE 0xa5f8 1503 /* [R 1] Status of four port mode path swap input pin. */ 1504 #define MISC_REG_FOUR_PORT_PATH_SWAP 0xa75c 1505 /* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 - 1506 the path_swap output is equal to 4 port mode path swap input pin; if it 1507 is 1 - the path_swap output is equal to bit[1] of this register; [1] - 1508 Overwrite value. If bit[0] of this register is 1 this is the value that 1509 receives the path_swap output. Reset on Hard reset. */ 1510 #define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR 0xa738 1511 /* [R 1] Status of 4 port mode port swap input pin. */ 1512 #define MISC_REG_FOUR_PORT_PORT_SWAP 0xa754 1513 /* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 - 1514 the port_swap output is equal to 4 port mode port swap input pin; if it 1515 is 1 - the port_swap output is equal to bit[1] of this register; [1] - 1516 Overwrite value. If bit[0] of this register is 1 this is the value that 1517 receives the port_swap output. Reset on Hard reset. */ 1518 #define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR 0xa734 1519 /* [RW 32] Debug only: spare RW register reset by core reset */ 1520 #define MISC_REG_GENERIC_CR_0 0xa460 1521 #define MISC_REG_GENERIC_CR_1 0xa464 1522 /* [RW 32] Debug only: spare RW register reset by por reset */ 1523 #define MISC_REG_GENERIC_POR_1 0xa474 1524 /* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to 1525 use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO 1526 can not be configured as an output. Each output has its output enable in 1527 the MCP register space; but this bit needs to be set to make use of that. 1528 Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When 1529 set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON. 1530 When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change 1531 the i/o to an output and will drive the TimeSync output. Bit[31:7]: 1532 spare. Global register. Reset by hard reset. */ 1533 #define MISC_REG_GEN_PURP_HWG 0xa9a0 1534 /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of 1535 these bits is written as a '1'; the corresponding SPIO bit will turn off 1536 it's drivers and become an input. This is the reset state of all GPIO 1537 pins. The read value of these bits will be a '1' if that last command 1538 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff). 1539 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written 1540 as a '1'; the corresponding GPIO bit will drive low. The read value of 1541 these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for 1542 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0; 1543 SET When any of these bits is written as a '1'; the corresponding GPIO 1544 bit will drive high (if it has that capability). The read value of these 1545 bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this 1546 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0; 1547 RO; These bits indicate the read value of each of the eight GPIO pins. 1548 This is the result value of the pin; not the drive value. Writing these 1549 bits will have not effect. */ 1550 #define MISC_REG_GPIO 0xa490 1551 /* [RW 8] These bits enable the GPIO_INTs to signals event to the 1552 IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2] 1553 p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2; 1554 [7] p1_gpio_3; */ 1555 #define MISC_REG_GPIO_EVENT_EN 0xa2bc 1556 /* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a 1557 '1' to these bit clears the corresponding bit in the #OLD_VALUE register. 1558 This will acknowledge an interrupt on the falling edge of corresponding 1559 GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0; 1560 Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE 1561 register. This will acknowledge an interrupt on the rising edge of 1562 corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1; 1563 OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input 1564 value. When the ~INT_STATE bit is set; this bit indicates the OLD value 1565 of the pin such that if ~INT_STATE is set and this bit is '0'; then the 1566 interrupt is due to a low to high edge. If ~INT_STATE is set and this bit 1567 is '1'; then the interrupt is due to a high to low edge (reset value 0). 1568 [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the 1569 current GPIO interrupt state for each GPIO pin. This bit is cleared when 1570 the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is 1571 set when the GPIO input does not match the current value in #OLD_VALUE 1572 (reset value 0). */ 1573 #define MISC_REG_GPIO_INT 0xa494 1574 /* [R 28] this field hold the last information that caused reserved 1575 attention. bits [19:0] - address; [22:20] function; [23] reserved; 1576 [27:24] the master that caused the attention - according to the following 1577 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = 1578 dbu; 8 = dmae */ 1579 #define MISC_REG_GRC_RSV_ATTN 0xa3c0 1580 /* [R 28] this field hold the last information that caused timeout 1581 attention. bits [19:0] - address; [22:20] function; [23] reserved; 1582 [27:24] the master that caused the attention - according to the following 1583 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = 1584 dbu; 8 = dmae */ 1585 #define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4 1586 /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any 1587 access that does not finish within 1588 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is 1589 cleared; this timeout is disabled. If this timeout occurs; the GRC shall 1590 assert it attention output. */ 1591 #define MISC_REG_GRC_TIMEOUT_EN 0xa280 1592 /* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of 1593 the bits is: [2:0] OAC reset value 001) CML output buffer bias control; 1594 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl 1595 (reset value 001) Charge pump current control; 111 for 720u; 011 for 1596 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00) 1597 Global bias control; When bit 7 is high bias current will be 10 0gh; When 1598 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8] 1599 Pll_observe (reset value 010) Bits to control observability. bit 10 is 1600 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl 1601 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V 1602 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning 1603 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted 1604 internally). [14] reserved (reset value 0) Reset for VCO sequencer is 1605 connected to RESET input directly. [15] capRetry_en (reset value 0) 1606 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset 1607 value 0) bit to continuously monitor vco freq (inverted). [17] 1608 freqDetRestart_en (reset value 0) bit to enable restart when not freq 1609 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable 1610 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value 1611 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20] 1612 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass 1613 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value 1614 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0) 1615 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to 1616 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force 1617 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to 1618 restart. [27] capSelectM_en (reset value 0) bit to enable cap select 1619 register bits. */ 1620 #define MISC_REG_LCPLL_CTRL_1 0xa2a4 1621 #define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8 1622 /* [RW 4] Interrupt mask register #0 read/write */ 1623 #define MISC_REG_MISC_INT_MASK 0xa388 1624 /* [RW 1] Parity mask register #0 read/write */ 1625 #define MISC_REG_MISC_PRTY_MASK 0xa398 1626 /* [R 1] Parity register #0 read */ 1627 #define MISC_REG_MISC_PRTY_STS 0xa38c 1628 /* [RC 1] Parity register #0 read clear */ 1629 #define MISC_REG_MISC_PRTY_STS_CLR 0xa390 1630 #define MISC_REG_NIG_WOL_P0 0xa270 1631 #define MISC_REG_NIG_WOL_P1 0xa274 1632 /* [R 1] If set indicate that the pcie_rst_b was asserted without perst 1633 assertion */ 1634 #define MISC_REG_PCIE_HOT_RESET 0xa618 1635 /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911. 1636 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1 1637 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1 1638 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2 1639 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2 1640 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9] 1641 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1] 1642 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value 1643 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16] 1644 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset 1645 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value 1646 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0); 1647 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25] 1648 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27] 1649 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29] 1650 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31] 1651 testa_en (reset value 0); */ 1652 #define MISC_REG_PLL_STORM_CTRL_1 0xa294 1653 #define MISC_REG_PLL_STORM_CTRL_2 0xa298 1654 #define MISC_REG_PLL_STORM_CTRL_3 0xa29c 1655 #define MISC_REG_PLL_STORM_CTRL_4 0xa2a0 1656 /* [R 1] Status of 4 port mode enable input pin. */ 1657 #define MISC_REG_PORT4MODE_EN 0xa750 1658 /* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 - 1659 * the port4mode_en output is equal to 4 port mode input pin; if it is 1 - 1660 * the port4mode_en output is equal to bit[1] of this register; [1] - 1661 * Overwrite value. If bit[0] of this register is 1 this is the value that 1662 * receives the port4mode_en output . */ 1663 #define MISC_REG_PORT4MODE_EN_OVWR 0xa720 1664 /* [RW 32] reset reg#2; rite/read one = the specific block is out of reset; 1665 write/read zero = the specific block is in reset; addr 0-wr- the write 1666 value will be written to the register; addr 1-set - one will be written 1667 to all the bits that have the value of one in the data written (bits that 1668 have the value of zero will not be change) ; addr 2-clear - zero will be 1669 written to all the bits that have the value of one in the data written 1670 (bits that have the value of zero will not be change); addr 3-ignore; 1671 read ignore from all addr except addr 00; inside order of the bits is: 1672 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc; 1673 [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7] 1674 rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn; 1675 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13] 1676 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16] 1677 rst_pxp_rq_rd_wr; 31:17] reserved */ 1678 #define MISC_REG_RESET_REG_2 0xa590 1679 /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is 1680 shared with the driver resides */ 1681 #define MISC_REG_SHARED_MEM_ADDR 0xa2b4 1682 /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1'; 1683 the corresponding SPIO bit will turn off it's drivers and become an 1684 input. This is the reset state of all SPIO pins. The read value of these 1685 bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this 1686 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits 1687 is written as a '1'; the corresponding SPIO bit will drive low. The read 1688 value of these bits will be a '1' if that last command (#SET; #CLR; or 1689 #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of 1690 these bits is written as a '1'; the corresponding SPIO bit will drive 1691 high (if it has that capability). The read value of these bits will be a 1692 '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET. 1693 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of 1694 each of the eight SPIO pins. This is the result value of the pin; not the 1695 drive value. Writing these bits will have not effect. Each 8 bits field 1696 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply 1697 from VAUX. (This is an output pin only; the FLOAT field is not applicable 1698 for this pin); [1] VAUX Disable; when pulsed low; disables supply form 1699 VAUX. (This is an output pin only; FLOAT field is not applicable for this 1700 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to 1701 select VAUX supply. (This is an output pin only; it is not controlled by 1702 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT 1703 field is not applicable for this pin; only the VALUE fields is relevant - 1704 it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6] 1705 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP 1706 device ID select; read by UMP firmware. */ 1707 #define MISC_REG_SPIO 0xa4fc 1708 /* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC. 1709 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5; 1710 [7:0] reserved */ 1711 #define MISC_REG_SPIO_EVENT_EN 0xa2b8 1712 /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the 1713 corresponding bit in the #OLD_VALUE register. This will acknowledge an 1714 interrupt on the falling edge of corresponding SPIO input (reset value 1715 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit 1716 in the #OLD_VALUE register. This will acknowledge an interrupt on the 1717 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE 1718 RO; These bits indicate the old value of the SPIO input value. When the 1719 ~INT_STATE bit is set; this bit indicates the OLD value of the pin such 1720 that if ~INT_STATE is set and this bit is '0'; then the interrupt is due 1721 to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the 1722 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE 1723 RO; These bits indicate the current SPIO interrupt state for each SPIO 1724 pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR 1725 command bit is written. This bit is set when the SPIO input does not 1726 match the current value in #OLD_VALUE (reset value 0). */ 1727 #define MISC_REG_SPIO_INT 0xa500 1728 /* [RW 32] reload value for counter 4 if reload; the value will be reload if 1729 the counter reached zero and the reload bit 1730 (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */ 1731 #define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc 1732 /* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses 1733 in this register. address 0 - timer 1; address 1 - timer 2, ... address 7 - 1734 timer 8 */ 1735 #define MISC_REG_SW_TIMER_VAL 0xa5c0 1736 /* [R 1] Status of two port mode path swap input pin. */ 1737 #define MISC_REG_TWO_PORT_PATH_SWAP 0xa758 1738 /* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the 1739 path_swap output is equal to 2 port mode path swap input pin; if it is 1 1740 - the path_swap output is equal to bit[1] of this register; [1] - 1741 Overwrite value. If bit[0] of this register is 1 this is the value that 1742 receives the path_swap output. Reset on Hard reset. */ 1743 #define MISC_REG_TWO_PORT_PATH_SWAP_OVWR 0xa72c 1744 /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are 1745 loaded; 0-prepare; -unprepare */ 1746 #define MISC_REG_UNPREPARED 0xa424 1747 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0) 1748 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1) 1749 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4) 1750 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2) 1751 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3) 1752 /* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or 1753 * not it is the recipient of the message on the MDIO interface. The value 1754 * is compared to the value on ctrl_md_devad. Drives output 1755 * misc_xgxs0_phy_addr. Global register. */ 1756 #define MISC_REG_WC0_CTRL_PHY_ADDR 0xa9cc 1757 /* [RW 2] XMAC Core port mode. Indicates the number of ports on the system 1758 side. This should be less than or equal to phy_port_mode; if some of the 1759 ports are not used. This enables reduction of frequency on the core side. 1760 This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 - 1761 Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap 1762 input for the XMAC_MP core; and should be changed only while reset is 1763 held low. Reset on Hard reset. */ 1764 #define MISC_REG_XMAC_CORE_PORT_MODE 0xa964 1765 /* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp 1766 Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 1767 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the 1768 XMAC_MP core; and should be changed only while reset is held low. Reset 1769 on Hard reset. */ 1770 #define MISC_REG_XMAC_PHY_PORT_MODE 0xa960 1771 /* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0. 1772 * Reads from this register will clear bits 31:0. */ 1773 #define MSTAT_REG_RX_STAT_GR64_LO 0x200 1774 /* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits 1775 * 31:0. Reads from this register will clear bits 31:0. */ 1776 #define MSTAT_REG_TX_STAT_GTXPOK_LO 0 1777 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0) 1778 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1) 1779 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4) 1780 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2) 1781 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3) 1782 #define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0) 1783 #define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0) 1784 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0) 1785 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9) 1786 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15) 1787 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18) 1788 /* [RW 1] Input enable for RX_BMAC0 IF */ 1789 #define NIG_REG_BMAC0_IN_EN 0x100ac 1790 /* [RW 1] output enable for TX_BMAC0 IF */ 1791 #define NIG_REG_BMAC0_OUT_EN 0x100e0 1792 /* [RW 1] output enable for TX BMAC pause port 0 IF */ 1793 #define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110 1794 /* [RW 1] output enable for RX_BMAC0_REGS IF */ 1795 #define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8 1796 /* [RW 1] output enable for RX BRB1 port0 IF */ 1797 #define NIG_REG_BRB0_OUT_EN 0x100f8 1798 /* [RW 1] Input enable for TX BRB1 pause port 0 IF */ 1799 #define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4 1800 /* [RW 1] output enable for RX BRB1 port1 IF */ 1801 #define NIG_REG_BRB1_OUT_EN 0x100fc 1802 /* [RW 1] Input enable for TX BRB1 pause port 1 IF */ 1803 #define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8 1804 /* [RW 1] output enable for RX BRB1 LP IF */ 1805 #define NIG_REG_BRB_LB_OUT_EN 0x10100 1806 /* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64] 1807 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush; 1808 72:73]-vnic_num; 81:74]-sideband_info */ 1809 #define NIG_REG_DEBUG_PACKET_LB 0x10800 1810 /* [RW 1] Input enable for TX Debug packet */ 1811 #define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc 1812 /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all 1813 packets from PBFare not forwarded to the MAC and just deleted from FIFO. 1814 First packet may be deleted from the middle. And last packet will be 1815 always deleted till the end. */ 1816 #define NIG_REG_EGRESS_DRAIN0_MODE 0x10060 1817 /* [RW 1] Output enable to EMAC0 */ 1818 #define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120 1819 /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs 1820 to emac for port0; other way to bmac for port0 */ 1821 #define NIG_REG_EGRESS_EMAC0_PORT 0x10058 1822 /* [RW 1] Input enable for TX PBF user packet port0 IF */ 1823 #define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc 1824 /* [RW 1] Input enable for TX PBF user packet port1 IF */ 1825 #define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0 1826 /* [RW 1] Input enable for TX UMP management packet port0 IF */ 1827 #define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4 1828 /* [RW 1] Input enable for RX_EMAC0 IF */ 1829 #define NIG_REG_EMAC0_IN_EN 0x100a4 1830 /* [RW 1] output enable for TX EMAC pause port 0 IF */ 1831 #define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118 1832 /* [R 1] status from emac0. This bit is set when MDINT from either the 1833 EXT_MDINT pin or from the Copper PHY is driven low. This condition must 1834 be cleared in the attached PHY device that is driving the MINT pin. */ 1835 #define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494 1836 /* [WB 48] This address space contains BMAC0 registers. The BMAC registers 1837 are described in appendix A. In order to access the BMAC0 registers; the 1838 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be 1839 added to each BMAC register offset */ 1840 #define NIG_REG_INGRESS_BMAC0_MEM 0x10c00 1841 /* [WB 48] This address space contains BMAC1 registers. The BMAC registers 1842 are described in appendix A. In order to access the BMAC0 registers; the 1843 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be 1844 added to each BMAC register offset */ 1845 #define NIG_REG_INGRESS_BMAC1_MEM 0x11000 1846 /* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */ 1847 #define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0 1848 /* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data 1849 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */ 1850 #define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4 1851 /* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch 1852 logic for interrupts must be used. Enable per bit of interrupt of 1853 ~latch_status.latch_status */ 1854 #define NIG_REG_LATCH_BC_0 0x16210 1855 /* [RW 27] Latch for each interrupt from Unicore.b[0] 1856 status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete; 1857 b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status; 1858 b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn; 1859 b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete; 1860 b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status; 1861 b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete; 1862 b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet; 1863 b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g; 1864 b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact; 1865 b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx; 1866 b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx; 1867 b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */ 1868 #define NIG_REG_LATCH_STATUS_0 0x18000 1869 /* [RW 1] led 10g for port 0 */ 1870 #define NIG_REG_LED_10G_P0 0x10320 1871 /* [RW 1] led 10g for port 1 */ 1872 #define NIG_REG_LED_10G_P1 0x10324 1873 /* [RW 1] Port0: This bit is set to enable the use of the 1874 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field 1875 defined below. If this bit is cleared; then the blink rate will be about 1876 8Hz. */ 1877 #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318 1878 /* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for 1879 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field 1880 is reset to 0x080; giving a default blink period of approximately 8Hz. */ 1881 #define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310 1882 /* [RW 1] Port0: If set along with the 1883 ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0 1884 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED 1885 bit; the Traffic LED will blink with the blink rate specified in 1886 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and 1887 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0 1888 fields. */ 1889 #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308 1890 /* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The 1891 Traffic LED will then be controlled via bit ~nig_registers_ 1892 led_control_traffic_p0.led_control_traffic_p0 and bit 1893 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */ 1894 #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8 1895 /* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit; 1896 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also 1897 set; the LED will blink with blink rate specified in 1898 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and 1899 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0 1900 fields. */ 1901 #define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300 1902 /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3; 1903 9-11PHY7; 12 MAC4; 13-15 PHY10; */ 1904 #define NIG_REG_LED_MODE_P0 0x102f0 1905 /* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1- 1906 tsdm enable; b2- usdm enable */ 1907 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070 1908 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074 1909 /* [RW 1] SAFC enable for port0. This register may get 1 only when 1910 ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same 1911 port */ 1912 #define NIG_REG_LLFC_ENABLE_0 0x16208 1913 #define NIG_REG_LLFC_ENABLE_1 0x1620c 1914 /* [RW 16] classes are high-priority for port0 */ 1915 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058 1916 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 0x1605c 1917 /* [RW 16] classes are low-priority for port0 */ 1918 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060 1919 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 0x16064 1920 /* [RW 1] Output enable of message to LLFC BMAC IF for port0 */ 1921 #define NIG_REG_LLFC_OUT_EN_0 0x160c8 1922 #define NIG_REG_LLFC_OUT_EN_1 0x160cc 1923 #define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c 1924 #define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154 1925 #define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244 1926 #define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048 1927 /* [RW 1] send to BRB1 if no match on any of RMP rules. */ 1928 #define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c 1929 /* [RW 2] Determine the classification participants. 0: no classification.1: 1930 classification upon VLAN id. 2: classification upon MAC address. 3: 1931 classification upon both VLAN id & MAC addr. */ 1932 #define NIG_REG_LLH0_CLS_TYPE 0x16080 1933 /* [RW 32] cm header for llh0 */ 1934 #define NIG_REG_LLH0_CM_HEADER 0x1007c 1935 #define NIG_REG_LLH0_DEST_IP_0_1 0x101dc 1936 #define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0 1937 /* [RW 16] destination TCP address 1. The LLH will look for this address in 1938 all incoming packets. */ 1939 #define NIG_REG_LLH0_DEST_TCP_0 0x10220 1940 /* [RW 16] destination UDP address 1 The LLH will look for this address in 1941 all incoming packets. */ 1942 #define NIG_REG_LLH0_DEST_UDP_0 0x10214 1943 #define NIG_REG_LLH0_ERROR_MASK 0x1008c 1944 /* [RW 8] event id for llh0 */ 1945 #define NIG_REG_LLH0_EVENT_ID 0x10084 1946 #define NIG_REG_LLH0_FUNC_EN 0x160fc 1947 #define NIG_REG_LLH0_FUNC_MEM 0x16180 1948 #define NIG_REG_LLH0_FUNC_MEM_ENABLE 0x16140 1949 #define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100 1950 /* [RW 1] Determine the IP version to look for in 1951 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */ 1952 #define NIG_REG_LLH0_IPV4_IPV6_0 0x10208 1953 /* [RW 1] t bit for llh0 */ 1954 #define NIG_REG_LLH0_T_BIT 0x10074 1955 /* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */ 1956 #define NIG_REG_LLH0_VLAN_ID_0 0x1022c 1957 /* [RW 8] init credit counter for port0 in LLH */ 1958 #define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554 1959 #define NIG_REG_LLH0_XCM_MASK 0x10130 1960 #define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248 1961 /* [RW 1] send to BRB1 if no match on any of RMP rules. */ 1962 #define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc 1963 /* [RW 2] Determine the classification participants. 0: no classification.1: 1964 classification upon VLAN id. 2: classification upon MAC address. 3: 1965 classification upon both VLAN id & MAC addr. */ 1966 #define NIG_REG_LLH1_CLS_TYPE 0x16084 1967 /* [RW 32] cm header for llh1 */ 1968 #define NIG_REG_LLH1_CM_HEADER 0x10080 1969 #define NIG_REG_LLH1_ERROR_MASK 0x10090 1970 /* [RW 8] event id for llh1 */ 1971 #define NIG_REG_LLH1_EVENT_ID 0x10088 1972 #define NIG_REG_LLH1_FUNC_MEM 0x161c0 1973 #define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160 1974 #define NIG_REG_LLH1_FUNC_MEM_SIZE 16 1975 /* [RW 1] When this bit is set; the LLH will classify the packet before 1976 * sending it to the BRB or calculating WoL on it. This bit controls port 1 1977 * only. The legacy llh_multi_function_mode bit controls port 0. */ 1978 #define NIG_REG_LLH1_MF_MODE 0x18614 1979 /* [RW 8] init credit counter for port1 in LLH */ 1980 #define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564 1981 #define NIG_REG_LLH1_XCM_MASK 0x10134 1982 /* [RW 1] When this bit is set; the LLH will expect all packets to be with 1983 e1hov */ 1984 #define NIG_REG_LLH_E1HOV_MODE 0x160d8 1985 /* [RW 1] When this bit is set; the LLH will classify the packet before 1986 sending it to the BRB or calculating WoL on it. */ 1987 #define NIG_REG_LLH_MF_MODE 0x16024 1988 #define NIG_REG_MASK_INTERRUPT_PORT0 0x10330 1989 #define NIG_REG_MASK_INTERRUPT_PORT1 0x10334 1990 /* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */ 1991 #define NIG_REG_NIG_EMAC0_EN 0x1003c 1992 /* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */ 1993 #define NIG_REG_NIG_EMAC1_EN 0x10040 1994 /* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the 1995 EMAC0 to strip the CRC from the ingress packets. */ 1996 #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044 1997 /* [R 32] Interrupt register #0 read */ 1998 #define NIG_REG_NIG_INT_STS_0 0x103b0 1999 #define NIG_REG_NIG_INT_STS_1 0x103c0 2000 /* [R 32] Legacy E1 and E1H location for parity error mask register. */ 2001 #define NIG_REG_NIG_PRTY_MASK 0x103dc 2002 /* [RW 32] Parity mask register #0 read/write */ 2003 #define NIG_REG_NIG_PRTY_MASK_0 0x183c8 2004 #define NIG_REG_NIG_PRTY_MASK_1 0x183d8 2005 /* [R 32] Legacy E1 and E1H location for parity error status register. */ 2006 #define NIG_REG_NIG_PRTY_STS 0x103d0 2007 /* [R 32] Parity register #0 read */ 2008 #define NIG_REG_NIG_PRTY_STS_0 0x183bc 2009 #define NIG_REG_NIG_PRTY_STS_1 0x183cc 2010 /* [R 32] Legacy E1 and E1H location for parity error status clear register. */ 2011 #define NIG_REG_NIG_PRTY_STS_CLR 0x103d4 2012 /* [RC 32] Parity register #0 read clear */ 2013 #define NIG_REG_NIG_PRTY_STS_CLR_0 0x183c0 2014 #define NIG_REG_NIG_PRTY_STS_CLR_1 0x183d0 2015 #define MCPR_IMC_COMMAND_ENABLE (1L<<31) 2016 #define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16 2017 #define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28 2018 #define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8 2019 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2020 * Ethernet header. */ 2021 #define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038 2022 /* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in 2023 * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be 2024 * disabled when this bit is set. */ 2025 #define NIG_REG_P0_HWPFC_ENABLE 0x18078 2026 #define NIG_REG_P0_LLH_FUNC_MEM2 0x18480 2027 #define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x18440 2028 /* [RW 1] Input enable for RX MAC interface. */ 2029 #define NIG_REG_P0_MAC_IN_EN 0x185ac 2030 /* [RW 1] Output enable for TX MAC interface */ 2031 #define NIG_REG_P0_MAC_OUT_EN 0x185b0 2032 /* [RW 1] Output enable for TX PAUSE signal to the MAC. */ 2033 #define NIG_REG_P0_MAC_PAUSE_OUT_EN 0x185b4 2034 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for 2035 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the 2036 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit 2037 * priority field is extracted from the outer-most VLAN in receive packet. 2038 * Only COS 0 and COS 1 are supported in E2. */ 2039 #define NIG_REG_P0_PKT_PRIORITY_TO_COS 0x18054 2040 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A 2041 * priority is mapped to COS 0 when the corresponding mask bit is 1. More 2042 * than one bit may be set; allowing multiple priorities to be mapped to one 2043 * COS. */ 2044 #define NIG_REG_P0_RX_COS0_PRIORITY_MASK 0x18058 2045 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A 2046 * priority is mapped to COS 1 when the corresponding mask bit is 1. More 2047 * than one bit may be set; allowing multiple priorities to be mapped to one 2048 * COS. */ 2049 #define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805c 2050 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A 2051 * priority is mapped to COS 2 when the corresponding mask bit is 1. More 2052 * than one bit may be set; allowing multiple priorities to be mapped to one 2053 * COS. */ 2054 #define NIG_REG_P0_RX_COS2_PRIORITY_MASK 0x186b0 2055 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A 2056 * priority is mapped to COS 3 when the corresponding mask bit is 1. More 2057 * than one bit may be set; allowing multiple priorities to be mapped to one 2058 * COS. */ 2059 #define NIG_REG_P0_RX_COS3_PRIORITY_MASK 0x186b4 2060 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A 2061 * priority is mapped to COS 4 when the corresponding mask bit is 1. More 2062 * than one bit may be set; allowing multiple priorities to be mapped to one 2063 * COS. */ 2064 #define NIG_REG_P0_RX_COS4_PRIORITY_MASK 0x186b8 2065 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A 2066 * priority is mapped to COS 5 when the corresponding mask bit is 1. More 2067 * than one bit may be set; allowing multiple priorities to be mapped to one 2068 * COS. */ 2069 #define NIG_REG_P0_RX_COS5_PRIORITY_MASK 0x186bc 2070 /* [R 1] RX FIFO for receiving data from MAC is empty. */ 2071 /* [RW 15] Specify which of the credit registers the client is to be mapped 2072 * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For 2073 * clients that are not subject to WFQ credit blocking - their 2074 * specifications here are not used. */ 2075 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f0 2076 /* [RW 32] Specify which of the credit registers the client is to be mapped 2077 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are 2078 * for client 0; bits [35:32] are for client 8. For clients that are not 2079 * subject to WFQ credit blocking - their specifications here are not used. 2080 * This is a new register (with 2_) added in E3 B0 to accommodate the 9 2081 * input clients to ETS arbiter. The reset default is set for management and 2082 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to 2083 * use credit registers 0-5 respectively (0x543210876). Note that credit 2084 * registers can not be shared between clients. */ 2085 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x18688 2086 /* [RW 4] Specify which of the credit registers the client is to be mapped 2087 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are 2088 * for client 0; bits [35:32] are for client 8. For clients that are not 2089 * subject to WFQ credit blocking - their specifications here are not used. 2090 * This is a new register (with 2_) added in E3 B0 to accommodate the 9 2091 * input clients to ETS arbiter. The reset default is set for management and 2092 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to 2093 * use credit registers 0-5 respectively (0x543210876). Note that credit 2094 * registers can not be shared between clients. */ 2095 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x1868c 2096 /* [RW 5] Specify whether the client competes directly in the strict 2097 * priority arbiter. The bits are mapped according to client ID (client IDs 2098 * are defined in tx_arb_priority_client). Default value is set to enable 2099 * strict priorities for clients 0-2 -- management and debug traffic. */ 2100 #define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT 0x180e8 2101 /* [RW 5] Specify whether the client is subject to WFQ credit blocking. The 2102 * bits are mapped according to client ID (client IDs are defined in 2103 * tx_arb_priority_client). Default value is 0 for not using WFQ credit 2104 * blocking. */ 2105 #define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x180ec 2106 /* [RW 32] Specify the upper bound that credit register 0 is allowed to 2107 * reach. */ 2108 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810c 2109 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x18110 2110 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 0x18114 2111 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 0x18118 2112 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 0x1811c 2113 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 0x186a0 2114 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 0x186a4 2115 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 0x186a8 2116 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 0x186ac 2117 /* [RW 32] Specify the weight (in bytes) to be added to credit register 0 2118 * when it is time to increment. */ 2119 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f8 2120 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fc 2121 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 0x18100 2122 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 0x18104 2123 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 0x18108 2124 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 0x18690 2125 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 0x18694 2126 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 0x18698 2127 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 0x1869c 2128 /* [RW 12] Specify the number of strict priority arbitration slots between 2129 * two round-robin arbitration slots to avoid starvation. A value of 0 means 2130 * no strict priority cycles - the strict priority with anti-starvation 2131 * arbiter becomes a round-robin arbiter. */ 2132 #define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS 0x180f4 2133 /* [RW 15] Specify the client number to be assigned to each priority of the 2134 * strict priority arbiter. Priority 0 is the highest priority. Bits [2:0] 2135 * are for priority 0 client; bits [14:12] are for priority 4 client. The 2136 * clients are assigned the following IDs: 0-management; 1-debug traffic 2137 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 2138 * traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000) 2139 * for management at priority 0; debug traffic at priorities 1 and 2; COS0 2140 * traffic at priority 3; and COS1 traffic at priority 4. */ 2141 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e4 2142 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2143 * Ethernet header. */ 2144 #define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818c 2145 #define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0 2146 #define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460 2147 /* [RW 32] Specify the client number to be assigned to each priority of the 2148 * strict priority arbiter. This register specifies bits 31:0 of the 36-bit 2149 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 2150 * client; bits [35-32] are for priority 8 client. The clients are assigned 2151 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug 2152 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 2153 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is 2154 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to 2155 * accommodate the 9 input clients to ETS arbiter. */ 2156 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB 0x18680 2157 /* [RW 4] Specify the client number to be assigned to each priority of the 2158 * strict priority arbiter. This register specifies bits 35:32 of the 36-bit 2159 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 2160 * client; bits [35-32] are for priority 8 client. The clients are assigned 2161 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug 2162 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 2163 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is 2164 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to 2165 * accommodate the 9 input clients to ETS arbiter. */ 2166 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB 0x18684 2167 #define NIG_REG_P1_MAC_IN_EN 0x185c0 2168 /* [RW 1] Output enable for TX MAC interface */ 2169 #define NIG_REG_P1_MAC_OUT_EN 0x185c4 2170 /* [RW 1] Output enable for TX PAUSE signal to the MAC. */ 2171 #define NIG_REG_P1_MAC_PAUSE_OUT_EN 0x185c8 2172 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for 2173 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the 2174 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit 2175 * priority field is extracted from the outer-most VLAN in receive packet. 2176 * Only COS 0 and COS 1 are supported in E2. */ 2177 #define NIG_REG_P1_PKT_PRIORITY_TO_COS 0x181a8 2178 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A 2179 * priority is mapped to COS 0 when the corresponding mask bit is 1. More 2180 * than one bit may be set; allowing multiple priorities to be mapped to one 2181 * COS. */ 2182 #define NIG_REG_P1_RX_COS0_PRIORITY_MASK 0x181ac 2183 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A 2184 * priority is mapped to COS 1 when the corresponding mask bit is 1. More 2185 * than one bit may be set; allowing multiple priorities to be mapped to one 2186 * COS. */ 2187 #define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b0 2188 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A 2189 * priority is mapped to COS 2 when the corresponding mask bit is 1. More 2190 * than one bit may be set; allowing multiple priorities to be mapped to one 2191 * COS. */ 2192 #define NIG_REG_P1_RX_COS2_PRIORITY_MASK 0x186f8 2193 /* [R 1] RX FIFO for receiving data from MAC is empty. */ 2194 #define NIG_REG_P1_RX_MACFIFO_EMPTY 0x1858c 2195 /* [R 1] TLLH FIFO is empty. */ 2196 #define NIG_REG_P1_TLLH_FIFO_EMPTY 0x18338 2197 /* [RW 32] Specify which of the credit registers the client is to be mapped 2198 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are 2199 * for client 0; bits [35:32] are for client 8. For clients that are not 2200 * subject to WFQ credit blocking - their specifications here are not used. 2201 * This is a new register (with 2_) added in E3 B0 to accommodate the 9 2202 * input clients to ETS arbiter. The reset default is set for management and 2203 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to 2204 * use credit registers 0-5 respectively (0x543210876). Note that credit 2205 * registers can not be shared between clients. Note also that there are 2206 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only 2207 * credit registers 0-5 are valid. This register should be configured 2208 * appropriately before enabling WFQ. */ 2209 #define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x186e8 2210 /* [RW 4] Specify which of the credit registers the client is to be mapped 2211 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are 2212 * for client 0; bits [35:32] are for client 8. For clients that are not 2213 * subject to WFQ credit blocking - their specifications here are not used. 2214 * This is a new register (with 2_) added in E3 B0 to accommodate the 9 2215 * input clients to ETS arbiter. The reset default is set for management and 2216 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to 2217 * use credit registers 0-5 respectively (0x543210876). Note that credit 2218 * registers can not be shared between clients. Note also that there are 2219 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only 2220 * credit registers 0-5 are valid. This register should be configured 2221 * appropriately before enabling WFQ. */ 2222 #define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x186ec 2223 /* [RW 9] Specify whether the client competes directly in the strict 2224 * priority arbiter. The bits are mapped according to client ID (client IDs 2225 * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic 2226 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 2227 * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. 2228 * Default value is set to enable strict priorities for all clients. */ 2229 #define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT 0x18234 2230 /* [RW 9] Specify whether the client is subject to WFQ credit blocking. The 2231 * bits are mapped according to client ID (client IDs are defined in 2232 * tx_arb_priority_client2): 0-management; 1-debug traffic from this port; 2233 * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 2234 * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is 2235 * 0 for not using WFQ credit blocking. */ 2236 #define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x18238 2237 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 0x18258 2238 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 0x1825c 2239 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 0x18260 2240 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 0x18264 2241 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 0x18268 2242 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 0x186f4 2243 /* [RW 32] Specify the weight (in bytes) to be added to credit register 0 2244 * when it is time to increment. */ 2245 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 0x18244 2246 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 0x18248 2247 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 0x1824c 2248 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 0x18250 2249 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 0x18254 2250 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 0x186f0 2251 /* [RW 12] Specify the number of strict priority arbitration slots between 2252 two round-robin arbitration slots to avoid starvation. A value of 0 means 2253 no strict priority cycles - the strict priority with anti-starvation 2254 arbiter becomes a round-robin arbiter. */ 2255 #define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS 0x18240 2256 /* [RW 32] Specify the client number to be assigned to each priority of the 2257 strict priority arbiter. This register specifies bits 31:0 of the 36-bit 2258 value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 2259 client; bits [35-32] are for priority 8 client. The clients are assigned 2260 the following IDs: 0-management; 1-debug traffic from this port; 2-debug 2261 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 2262 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is 2263 set to 0x345678021. This is a new register (with 2_) added in E3 B0 to 2264 accommodate the 9 input clients to ETS arbiter. Note that this register 2265 is the same as the one for port 0, except that port 1 only has COS 0-2 2266 traffic. There is no traffic for COS 3-5 of port 1. */ 2267 #define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB 0x186e0 2268 /* [RW 4] Specify the client number to be assigned to each priority of the 2269 strict priority arbiter. This register specifies bits 35:32 of the 36-bit 2270 value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 2271 client; bits [35-32] are for priority 8 client. The clients are assigned 2272 the following IDs: 0-management; 1-debug traffic from this port; 2-debug 2273 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 2274 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is 2275 set to 0x345678021. This is a new register (with 2_) added in E3 B0 to 2276 accommodate the 9 input clients to ETS arbiter. Note that this register 2277 is the same as the one for port 0, except that port 1 only has COS 0-2 2278 traffic. There is no traffic for COS 3-5 of port 1. */ 2279 #define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB 0x186e4 2280 /* [R 1] TX FIFO for transmitting data to MAC is empty. */ 2281 #define NIG_REG_P1_TX_MACFIFO_EMPTY 0x18594 2282 /* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets 2283 forwarded to the host. */ 2284 #define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY 0x182b8 2285 /* [RW 32] Specify the upper bound that credit register 0 is allowed to 2286 * reach. */ 2287 /* [RW 1] Pause enable for port0. This register may get 1 only when 2288 ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same 2289 port */ 2290 #define NIG_REG_PAUSE_ENABLE_0 0x160c0 2291 #define NIG_REG_PAUSE_ENABLE_1 0x160c4 2292 /* [RW 1] Input enable for RX PBF LP IF */ 2293 #define NIG_REG_PBF_LB_IN_EN 0x100b4 2294 /* [RW 1] Value of this register will be transmitted to port swap when 2295 ~nig_registers_strap_override.strap_override =1 */ 2296 #define NIG_REG_PORT_SWAP 0x10394 2297 /* [RW 1] PPP enable for port0. This register may get 1 only when 2298 * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the 2299 * same port */ 2300 #define NIG_REG_PPP_ENABLE_0 0x160b0 2301 #define NIG_REG_PPP_ENABLE_1 0x160b4 2302 /* [RW 1] output enable for RX parser descriptor IF */ 2303 #define NIG_REG_PRS_EOP_OUT_EN 0x10104 2304 /* [RW 1] Input enable for RX parser request IF */ 2305 #define NIG_REG_PRS_REQ_IN_EN 0x100b8 2306 /* [RW 5] control to serdes - CL45 DEVAD */ 2307 #define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370 2308 /* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */ 2309 #define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c 2310 /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */ 2311 #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374 2312 /* [R 1] status from serdes0 that inputs to interrupt logic of link status */ 2313 #define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578 2314 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure 2315 for port0 */ 2316 #define NIG_REG_STAT0_BRB_DISCARD 0x105f0 2317 /* [R 32] Rx statistics : In user packets truncated due to BRB backpressure 2318 for port0 */ 2319 #define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8 2320 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that 2321 between 1024 and 1522 bytes for port0 */ 2322 #define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750 2323 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that 2324 between 1523 bytes and above for port0 */ 2325 #define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760 2326 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure 2327 for port1 */ 2328 #define NIG_REG_STAT1_BRB_DISCARD 0x10628 2329 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that 2330 between 1024 and 1522 bytes for port1 */ 2331 #define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0 2332 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that 2333 between 1523 bytes and above for port1 */ 2334 #define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0 2335 /* [WB_R 64] Rx statistics : User octets received for LP */ 2336 #define NIG_REG_STAT2_BRB_OCTET 0x107e0 2337 #define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328 2338 #define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c 2339 /* [RW 1] port swap mux selection. If this register equal to 0 then port 2340 swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then 2341 ort swap is equal to ~nig_registers_port_swap.port_swap */ 2342 #define NIG_REG_STRAP_OVERRIDE 0x10398 2343 /* [RW 1] output enable for RX_XCM0 IF */ 2344 #define NIG_REG_XCM0_OUT_EN 0x100f0 2345 /* [RW 1] output enable for RX_XCM1 IF */ 2346 #define NIG_REG_XCM1_OUT_EN 0x100f4 2347 /* [RW 1] control to xgxs - remote PHY in-band MDIO */ 2348 #define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348 2349 /* [RW 5] control to xgxs - CL45 DEVAD */ 2350 #define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c 2351 /* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */ 2352 #define NIG_REG_XGXS0_CTRL_MD_ST 0x10338 2353 /* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */ 2354 #define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340 2355 /* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */ 2356 #define NIG_REG_XGXS0_STATUS_LINK10G 0x10680 2357 /* [R 4] status from xgxs0 that inputs to interrupt logic of link status */ 2358 #define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684 2359 /* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */ 2360 #define NIG_REG_XGXS_LANE_SEL_P0 0x102e8 2361 /* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */ 2362 #define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0 2363 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0) 2364 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9) 2365 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15) 2366 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18) 2367 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18 2368 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter. */ 2369 #define PBF_REG_COS0_UPPER_BOUND 0x15c05c 2370 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter 2371 * of port 0. */ 2372 #define PBF_REG_COS0_UPPER_BOUND_P0 0x15c2cc 2373 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter 2374 * of port 1. */ 2375 #define PBF_REG_COS0_UPPER_BOUND_P1 0x15c2e4 2376 /* [RW 31] The weight of COS0 in the ETS command arbiter. */ 2377 #define PBF_REG_COS0_WEIGHT 0x15c054 2378 /* [RW 31] The weight of COS0 in port 0 ETS command arbiter. */ 2379 #define PBF_REG_COS0_WEIGHT_P0 0x15c2a8 2380 /* [RW 31] The weight of COS0 in port 1 ETS command arbiter. */ 2381 #define PBF_REG_COS0_WEIGHT_P1 0x15c2c0 2382 /* [RW 31] The upper bound of the weight of COS1 in the ETS command arbiter. */ 2383 #define PBF_REG_COS1_UPPER_BOUND 0x15c060 2384 /* [RW 31] The weight of COS1 in the ETS command arbiter. */ 2385 #define PBF_REG_COS1_WEIGHT 0x15c058 2386 /* [RW 31] The weight of COS1 in port 0 ETS command arbiter. */ 2387 #define PBF_REG_COS1_WEIGHT_P0 0x15c2ac 2388 /* [RW 31] The weight of COS1 in port 1 ETS command arbiter. */ 2389 #define PBF_REG_COS1_WEIGHT_P1 0x15c2c4 2390 /* [RW 31] The weight of COS2 in port 0 ETS command arbiter. */ 2391 #define PBF_REG_COS2_WEIGHT_P0 0x15c2b0 2392 /* [RW 31] The weight of COS2 in port 1 ETS command arbiter. */ 2393 #define PBF_REG_COS2_WEIGHT_P1 0x15c2c8 2394 /* [RW 31] The weight of COS3 in port 0 ETS command arbiter. */ 2395 #define PBF_REG_COS3_WEIGHT_P0 0x15c2b4 2396 /* [RW 31] The weight of COS4 in port 0 ETS command arbiter. */ 2397 #define PBF_REG_COS4_WEIGHT_P0 0x15c2b8 2398 /* [RW 31] The weight of COS5 in port 0 ETS command arbiter. */ 2399 #define PBF_REG_COS5_WEIGHT_P0 0x15c2bc 2400 /* [R 11] Current credit for the LB queue in the tx port buffers in 16 byte 2401 * lines. */ 2402 #define PBF_REG_CREDIT_LB_Q 0x140338 2403 /* [R 11] Current credit for queue 0 in the tx port buffers in 16 byte 2404 * lines. */ 2405 #define PBF_REG_CREDIT_Q0 0x14033c 2406 /* [R 11] Current credit for queue 1 in the tx port buffers in 16 byte 2407 * lines. */ 2408 #define PBF_REG_CREDIT_Q1 0x140340 2409 /* [RW 1] Disable processing further tasks from port 0 (after ending the 2410 current task in process). */ 2411 #define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c 2412 /* [RW 1] Disable processing further tasks from port 1 (after ending the 2413 current task in process). */ 2414 #define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060 2415 /* [RW 1] Disable processing further tasks from port 4 (after ending the 2416 current task in process). */ 2417 #define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c 2418 #define PBF_REG_DISABLE_PF 0x1402e8 2419 /* [RW 18] For port 0: For each client that is subject to WFQ (the 2420 * corresponding bit is 1); indicates to which of the credit registers this 2421 * client is mapped. For clients which are not credit blocked; their mapping 2422 * is dont care. */ 2423 #define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 0x15c288 2424 /* [RW 9] For port 1: For each client that is subject to WFQ (the 2425 * corresponding bit is 1); indicates to which of the credit registers this 2426 * client is mapped. For clients which are not credit blocked; their mapping 2427 * is dont care. */ 2428 #define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 0x15c28c 2429 /* [RW 6] For port 0: Bit per client to indicate if the client competes in 2430 * the strict priority arbiter directly (corresponding bit = 1); or first 2431 * goes to the RR arbiter (corresponding bit = 0); and then competes in the 2432 * lowest priority in the strict-priority arbiter. */ 2433 #define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 0x15c278 2434 /* [RW 3] For port 1: Bit per client to indicate if the client competes in 2435 * the strict priority arbiter directly (corresponding bit = 1); or first 2436 * goes to the RR arbiter (corresponding bit = 0); and then competes in the 2437 * lowest priority in the strict-priority arbiter. */ 2438 #define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 0x15c27c 2439 /* [RW 6] For port 0: Bit per client to indicate if the client is subject to 2440 * WFQ credit blocking (corresponding bit = 1). */ 2441 #define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 0x15c280 2442 /* [RW 3] For port 0: Bit per client to indicate if the client is subject to 2443 * WFQ credit blocking (corresponding bit = 1). */ 2444 #define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 0x15c284 2445 /* [RW 16] For port 0: The number of strict priority arbitration slots 2446 * between 2 RR arbitration slots. A value of 0 means no strict priority 2447 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR 2448 * arbiter. */ 2449 #define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 0x15c2a0 2450 /* [RW 16] For port 1: The number of strict priority arbitration slots 2451 * between 2 RR arbitration slots. A value of 0 means no strict priority 2452 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR 2453 * arbiter. */ 2454 #define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 0x15c2a4 2455 /* [RW 18] For port 0: Indicates which client is connected to each priority 2456 * in the strict-priority arbiter. Priority 0 is the highest priority, and 2457 * priority 5 is the lowest; to which the RR output is connected to (this is 2458 * not configurable). */ 2459 #define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 0x15c270 2460 /* [RW 9] For port 1: Indicates which client is connected to each priority 2461 * in the strict-priority arbiter. Priority 0 is the highest priority, and 2462 * priority 5 is the lowest; to which the RR output is connected to (this is 2463 * not configurable). */ 2464 #define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 0x15c274 2465 /* [RW 1] Indicates that ETS is performed between the COSes in the command 2466 * arbiter. If reset strict priority w/ anti-starvation will be performed 2467 * w/o WFQ. */ 2468 #define PBF_REG_ETS_ENABLED 0x15c050 2469 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2470 * Ethernet header. */ 2471 #define PBF_REG_HDRS_AFTER_BASIC 0x15c0a8 2472 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */ 2473 #define PBF_REG_HDRS_AFTER_TAG_0 0x15c0b8 2474 /* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest 2475 * priority in the command arbiter. */ 2476 #define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04c 2477 #define PBF_REG_IF_ENABLE_REG 0x140044 2478 /* [RW 1] Init bit. When set the initial credits are copied to the credit 2479 registers (except the port credits). Should be set and then reset after 2480 the configuration of the block has ended. */ 2481 #define PBF_REG_INIT 0x140000 2482 /* [RW 11] Initial credit for the LB queue in the tx port buffers in 16 byte 2483 * lines. */ 2484 #define PBF_REG_INIT_CRD_LB_Q 0x15c248 2485 /* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte 2486 * lines. */ 2487 #define PBF_REG_INIT_CRD_Q0 0x15c230 2488 /* [RW 11] Initial credit for queue 1 in the tx port buffers in 16 byte 2489 * lines. */ 2490 #define PBF_REG_INIT_CRD_Q1 0x15c234 2491 /* [RW 1] Init bit for port 0. When set the initial credit of port 0 is 2492 copied to the credit register. Should be set and then reset after the 2493 configuration of the port has ended. */ 2494 #define PBF_REG_INIT_P0 0x140004 2495 /* [RW 1] Init bit for port 1. When set the initial credit of port 1 is 2496 copied to the credit register. Should be set and then reset after the 2497 configuration of the port has ended. */ 2498 #define PBF_REG_INIT_P1 0x140008 2499 /* [RW 1] Init bit for port 4. When set the initial credit of port 4 is 2500 copied to the credit register. Should be set and then reset after the 2501 configuration of the port has ended. */ 2502 #define PBF_REG_INIT_P4 0x14000c 2503 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2504 * the LB queue. Reset upon init. */ 2505 #define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q 0x140354 2506 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2507 * queue 0. Reset upon init. */ 2508 #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 0x140358 2509 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2510 * queue 1. Reset upon init. */ 2511 #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 0x14035c 2512 /* [RW 1] Enable for mac interface 0. */ 2513 #define PBF_REG_MAC_IF0_ENABLE 0x140030 2514 /* [RW 1] Enable for mac interface 1. */ 2515 #define PBF_REG_MAC_IF1_ENABLE 0x140034 2516 /* [RW 1] Enable for the loopback interface. */ 2517 #define PBF_REG_MAC_LB_ENABLE 0x140040 2518 /* [RW 6] Bit-map indicating which headers must appear in the packet */ 2519 #define PBF_REG_MUST_HAVE_HDRS 0x15c0c4 2520 /* [RW 16] The number of strict priority arbitration slots between 2 RR 2521 * arbitration slots. A value of 0 means no strict priority cycles; i.e. the 2522 * strict-priority w/ anti-starvation arbiter is a RR arbiter. */ 2523 #define PBF_REG_NUM_STRICT_ARB_SLOTS 0x15c064 2524 /* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause 2525 not suppoterd. */ 2526 #define PBF_REG_P0_ARB_THRSH 0x1400e4 2527 /* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */ 2528 #define PBF_REG_P0_CREDIT 0x140200 2529 /* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte 2530 lines. */ 2531 #define PBF_REG_P0_INIT_CRD 0x1400d0 2532 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2533 * port 0. Reset upon init. */ 2534 #define PBF_REG_P0_INTERNAL_CRD_FREED_CNT 0x140308 2535 /* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */ 2536 #define PBF_REG_P0_PAUSE_ENABLE 0x140014 2537 /* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */ 2538 #define PBF_REG_P0_TASK_CNT 0x140204 2539 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines 2540 * freed from the task queue of port 0. Reset upon init. */ 2541 #define PBF_REG_P0_TQ_LINES_FREED_CNT 0x1402f0 2542 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 0. */ 2543 #define PBF_REG_P0_TQ_OCCUPANCY 0x1402fc 2544 /* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port 2545 * buffers in 16 byte lines. */ 2546 #define PBF_REG_P1_CREDIT 0x140208 2547 /* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port 2548 * buffers in 16 byte lines. */ 2549 #define PBF_REG_P1_INIT_CRD 0x1400d4 2550 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2551 * port 1. Reset upon init. */ 2552 #define PBF_REG_P1_INTERNAL_CRD_FREED_CNT 0x14030c 2553 /* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */ 2554 #define PBF_REG_P1_TASK_CNT 0x14020c 2555 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines 2556 * freed from the task queue of port 1. Reset upon init. */ 2557 #define PBF_REG_P1_TQ_LINES_FREED_CNT 0x1402f4 2558 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 1. */ 2559 #define PBF_REG_P1_TQ_OCCUPANCY 0x140300 2560 /* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */ 2561 #define PBF_REG_P4_CREDIT 0x140210 2562 /* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte 2563 lines. */ 2564 #define PBF_REG_P4_INIT_CRD 0x1400e0 2565 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2566 * port 4. Reset upon init. */ 2567 #define PBF_REG_P4_INTERNAL_CRD_FREED_CNT 0x140310 2568 /* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */ 2569 #define PBF_REG_P4_TASK_CNT 0x140214 2570 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines 2571 * freed from the task queue of port 4. Reset upon init. */ 2572 #define PBF_REG_P4_TQ_LINES_FREED_CNT 0x1402f8 2573 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 4. */ 2574 #define PBF_REG_P4_TQ_OCCUPANCY 0x140304 2575 /* [RW 5] Interrupt mask register #0 read/write */ 2576 #define PBF_REG_PBF_INT_MASK 0x1401d4 2577 /* [R 5] Interrupt register #0 read */ 2578 #define PBF_REG_PBF_INT_STS 0x1401c8 2579 /* [RW 20] Parity mask register #0 read/write */ 2580 #define PBF_REG_PBF_PRTY_MASK 0x1401e4 2581 /* [RC 20] Parity register #0 read clear */ 2582 #define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc 2583 /* [RW 16] The Ethernet type value for L2 tag 0 */ 2584 #define PBF_REG_TAG_ETHERTYPE_0 0x15c090 2585 /* [RW 4] The length of the info field for L2 tag 0. The length is between 2586 * 2B and 14B; in 2B granularity */ 2587 #define PBF_REG_TAG_LEN_0 0x15c09c 2588 /* [R 32] Cyclic counter for number of 8 byte lines freed from the LB task 2589 * queue. Reset upon init. */ 2590 #define PBF_REG_TQ_LINES_FREED_CNT_LB_Q 0x14038c 2591 /* [R 32] Cyclic counter for number of 8 byte lines freed from the task 2592 * queue 0. Reset upon init. */ 2593 #define PBF_REG_TQ_LINES_FREED_CNT_Q0 0x140390 2594 /* [R 32] Cyclic counter for number of 8 byte lines freed from task queue 1. 2595 * Reset upon init. */ 2596 #define PBF_REG_TQ_LINES_FREED_CNT_Q1 0x140394 2597 /* [R 13] Number of 8 bytes lines occupied in the task queue of the LB 2598 * queue. */ 2599 #define PBF_REG_TQ_OCCUPANCY_LB_Q 0x1403a8 2600 /* [R 13] Number of 8 bytes lines occupied in the task queue of queue 0. */ 2601 #define PBF_REG_TQ_OCCUPANCY_Q0 0x1403ac 2602 /* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */ 2603 #define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b0 2604 #define PB_REG_CONTROL 0 2605 /* [RW 2] Interrupt mask register #0 read/write */ 2606 #define PB_REG_PB_INT_MASK 0x28 2607 /* [R 2] Interrupt register #0 read */ 2608 #define PB_REG_PB_INT_STS 0x1c 2609 /* [RW 4] Parity mask register #0 read/write */ 2610 #define PB_REG_PB_PRTY_MASK 0x38 2611 /* [R 4] Parity register #0 read */ 2612 #define PB_REG_PB_PRTY_STS 0x2c 2613 /* [RC 4] Parity register #0 read clear */ 2614 #define PB_REG_PB_PRTY_STS_CLR 0x30 2615 #define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 2616 #define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8) 2617 #define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1) 2618 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN (0x1<<6) 2619 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7) 2620 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4) 2621 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3) 2622 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5) 2623 #define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN (0x1<<2) 2624 /* [R 8] Config space A attention dirty bits. Each bit indicates that the 2625 * corresponding PF generates config space A attention. Set by PXP. Reset by 2626 * MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits 2627 * from both paths. */ 2628 #define PGLUE_B_REG_CFG_SPACE_A_REQUEST 0x9010 2629 /* [R 8] Config space B attention dirty bits. Each bit indicates that the 2630 * corresponding PF generates config space B attention. Set by PXP. Reset by 2631 * MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits 2632 * from both paths. */ 2633 #define PGLUE_B_REG_CFG_SPACE_B_REQUEST 0x9014 2634 /* [RW 1] Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1 2635 * - enable. */ 2636 #define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE 0x9194 2637 /* [RW 18] Type B VF inbound interrupt table for CSDM: bits[17:9]-mask; 2638 * its[8:0]-address. Bits [1:0] must be zero (DW resolution address). */ 2639 #define PGLUE_B_REG_CSDM_INB_INT_B_VF 0x916c 2640 /* [RW 1] Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1 2641 * - enable. */ 2642 #define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE 0x919c 2643 /* [RW 16] Start offset of CSDM zone A (queue zone) in the internal RAM */ 2644 #define PGLUE_B_REG_CSDM_START_OFFSET_A 0x9100 2645 /* [RW 16] Start offset of CSDM zone B (legacy zone) in the internal RAM */ 2646 #define PGLUE_B_REG_CSDM_START_OFFSET_B 0x9108 2647 /* [RW 5] VF Shift of CSDM zone B (legacy zone) in the internal RAM */ 2648 #define PGLUE_B_REG_CSDM_VF_SHIFT_B 0x9110 2649 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */ 2650 #define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF 0x91ac 2651 /* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates 2652 * that the FLR register of the corresponding PF was set. Set by PXP. Reset 2653 * by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits 2654 * from both paths. */ 2655 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0 0x9028 2656 /* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1 2657 * to a bit in this register in order to clear the corresponding bit in 2658 * flr_request_pf_7_0 register. Note: register contains bits from both 2659 * paths. */ 2660 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR 0x9418 2661 /* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit 2662 * indicates that the FLR register of the corresponding VF was set. Set by 2663 * PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr. */ 2664 #define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x9024 2665 /* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit 2666 * indicates that the FLR register of the corresponding VF was set. Set by 2667 * PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr. */ 2668 #define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x9018 2669 /* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit 2670 * indicates that the FLR register of the corresponding VF was set. Set by 2671 * PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr. */ 2672 #define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x901c 2673 /* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit 2674 * indicates that the FLR register of the corresponding VF was set. Set by 2675 * PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr. */ 2676 #define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x9020 2677 /* [R 8] Each bit indicates an incorrect behavior in user RX interface. Bit 2678 * 0 - Target memory read arrived with a correctable error. Bit 1 - Target 2679 * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW 2680 * arrived with a correctable error. Bit 3 - Configuration RW arrived with 2681 * an uncorrectable error. Bit 4 - Completion with Configuration Request 2682 * Retry Status. Bit 5 - Expansion ROM access received with a write request. 2683 * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and 2684 * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010; 2685 * and pcie_rx_last not asserted. */ 2686 #define PGLUE_B_REG_INCORRECT_RCV_DETAILS 0x9068 2687 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942c 2688 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x9430 2689 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x9434 2690 #define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x9438 2691 /* [R 9] Interrupt register #0 read */ 2692 #define PGLUE_B_REG_PGLUE_B_INT_STS 0x9298 2693 /* [RC 9] Interrupt register #0 read clear */ 2694 #define PGLUE_B_REG_PGLUE_B_INT_STS_CLR 0x929c 2695 /* [RW 2] Parity mask register #0 read/write */ 2696 #define PGLUE_B_REG_PGLUE_B_PRTY_MASK 0x92b4 2697 /* [R 2] Parity register #0 read */ 2698 #define PGLUE_B_REG_PGLUE_B_PRTY_STS 0x92a8 2699 /* [RC 2] Parity register #0 read clear */ 2700 #define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR 0x92ac 2701 /* [R 13] Details of first request received with error. [2:0] - PFID. [3] - 2702 * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion 2703 * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 - 2704 * completer abort. 3 - Illegal value for this field. [12] valid - indicates 2705 * if there was a completion error since the last time this register was 2706 * cleared. */ 2707 #define PGLUE_B_REG_RX_ERR_DETAILS 0x9080 2708 /* [R 18] Details of first ATS Translation Completion request received with 2709 * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code - 2710 * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 - 2711 * unsupported request. 2 - completer abort. 3 - Illegal value for this 2712 * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a 2713 * completion error since the last time this register was cleared. */ 2714 #define PGLUE_B_REG_RX_TCPL_ERR_DETAILS 0x9084 2715 /* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to 2716 * a bit in this register in order to clear the corresponding bit in 2717 * shadow_bme_pf_7_0 register. MCP should never use this unless a 2718 * work-around is needed. Note: register contains bits from both paths. */ 2719 #define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR 0x9458 2720 /* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the 2721 * VF enable register of the corresponding PF is written to 0 and was 2722 * previously 1. Set by PXP. Reset by MCP writing 1 to 2723 * sr_iov_disabled_request_clr. Note: register contains bits from both 2724 * paths. */ 2725 #define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x9030 2726 /* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read 2727 * completion did not return yet. 1 - tag is unused. Same functionality as 2728 * pxp2_registers_pgl_exp_rom_data2 for tags 0-31. */ 2729 #define PGLUE_B_REG_TAGS_63_32 0x9244 2730 /* [RW 1] Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1 2731 * - enable. */ 2732 #define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE 0x9170 2733 /* [RW 16] Start offset of TSDM zone A (queue zone) in the internal RAM */ 2734 #define PGLUE_B_REG_TSDM_START_OFFSET_A 0x90c4 2735 /* [RW 16] Start offset of TSDM zone B (legacy zone) in the internal RAM */ 2736 #define PGLUE_B_REG_TSDM_START_OFFSET_B 0x90cc 2737 /* [RW 5] VF Shift of TSDM zone B (legacy zone) in the internal RAM */ 2738 #define PGLUE_B_REG_TSDM_VF_SHIFT_B 0x90d4 2739 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */ 2740 #define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF 0x91a0 2741 /* [R 32] Address [31:0] of first read request not submitted due to error */ 2742 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x9098 2743 /* [R 32] Address [63:32] of first read request not submitted due to error */ 2744 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x909c 2745 /* [R 31] Details of first read request not submitted due to error. [4:0] 2746 * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request. 2747 * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] - 2748 * VFID. */ 2749 #define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x90a0 2750 /* [R 26] Details of first read request not submitted due to error. [15:0] 2751 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type - 2752 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared; 2753 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent 2754 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid - 2755 * indicates if there was a request not submitted due to error since the 2756 * last time this register was cleared. */ 2757 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x90a4 2758 /* [R 32] Address [31:0] of first write request not submitted due to error */ 2759 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x9088 2760 /* [R 32] Address [63:32] of first write request not submitted due to error */ 2761 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x908c 2762 /* [R 31] Details of first write request not submitted due to error. [4:0] 2763 * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] 2764 * - VFID. */ 2765 #define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x9090 2766 /* [R 26] Details of first write request not submitted due to error. [15:0] 2767 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type - 2768 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared; 2769 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent 2770 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid - 2771 * indicates if there was a request not submitted due to error since the 2772 * last time this register was cleared. */ 2773 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x9094 2774 /* [RW 10] Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask; 2775 * its[4:0]-address relative to start_offset_a. Bits [1:0] can have any 2776 * value (Byte resolution address). */ 2777 #define PGLUE_B_REG_USDM_INB_INT_A_0 0x9128 2778 #define PGLUE_B_REG_USDM_INB_INT_A_1 0x912c 2779 #define PGLUE_B_REG_USDM_INB_INT_A_2 0x9130 2780 #define PGLUE_B_REG_USDM_INB_INT_A_3 0x9134 2781 #define PGLUE_B_REG_USDM_INB_INT_A_4 0x9138 2782 #define PGLUE_B_REG_USDM_INB_INT_A_5 0x913c 2783 #define PGLUE_B_REG_USDM_INB_INT_A_6 0x9140 2784 /* [RW 1] Type A PF enable inbound interrupt table for USDM. 0 - disable; 1 2785 * - enable. */ 2786 #define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE 0x917c 2787 /* [RW 1] Type A VF enable inbound interrupt table for USDM. 0 - disable; 1 2788 * - enable. */ 2789 #define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE 0x9180 2790 /* [RW 1] Type B VF enable inbound interrupt table for USDM. 0 - disable; 1 2791 * - enable. */ 2792 #define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE 0x9184 2793 /* [RW 16] Start offset of USDM zone A (queue zone) in the internal RAM */ 2794 #define PGLUE_B_REG_USDM_START_OFFSET_A 0x90d8 2795 /* [RW 16] Start offset of USDM zone B (legacy zone) in the internal RAM */ 2796 #define PGLUE_B_REG_USDM_START_OFFSET_B 0x90e0 2797 /* [RW 5] VF Shift of USDM zone B (legacy zone) in the internal RAM */ 2798 #define PGLUE_B_REG_USDM_VF_SHIFT_B 0x90e8 2799 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */ 2800 #define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF 0x91a4 2801 /* [R 26] Details of first target VF request accessing VF GRC space that 2802 * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write. 2803 * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a 2804 * request accessing VF GRC space that failed permission check since the 2805 * last time this register was cleared. Permission checks are: function 2806 * permission; R/W permission; address range permission. */ 2807 #define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS 0x9234 2808 /* [R 31] Details of first target VF request with length violation (too many 2809 * DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address). 2810 * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30] 2811 * valid - indicates if there was a request with length violation since the 2812 * last time this register was cleared. Length violations: length of more 2813 * than 2DWs; length of 2DWs and address not QW aligned; window is GRC and 2814 * length is more than 1 DW. */ 2815 #define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS 0x9230 2816 /* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates 2817 * that there was a completion with uncorrectable error for the 2818 * corresponding PF. Set by PXP. Reset by MCP writing 1 to 2819 * was_error_pf_7_0_clr. */ 2820 #define PGLUE_B_REG_WAS_ERROR_PF_7_0 0x907c 2821 /* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1 2822 * to a bit in this register in order to clear the corresponding bit in 2823 * flr_request_pf_7_0 register. */ 2824 #define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR 0x9470 2825 /* [R 32] Was_error indication dirty bits for VFs 96 to 127. Each bit 2826 * indicates that there was a completion with uncorrectable error for the 2827 * corresponding VF. Set by PXP. Reset by MCP writing 1 to 2828 * was_error_vf_127_96_clr. */ 2829 #define PGLUE_B_REG_WAS_ERROR_VF_127_96 0x9078 2830 /* [W 32] Was_error indication dirty bits clear for VFs 96 to 127. MCP 2831 * writes 1 to a bit in this register in order to clear the corresponding 2832 * bit in was_error_vf_127_96 register. */ 2833 #define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR 0x9474 2834 /* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit 2835 * indicates that there was a completion with uncorrectable error for the 2836 * corresponding VF. Set by PXP. Reset by MCP writing 1 to 2837 * was_error_vf_31_0_clr. */ 2838 #define PGLUE_B_REG_WAS_ERROR_VF_31_0 0x906c 2839 /* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes 2840 * 1 to a bit in this register in order to clear the corresponding bit in 2841 * was_error_vf_31_0 register. */ 2842 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x9478 2843 /* [R 32] Was_error indication dirty bits for VFs 32 to 63. Each bit 2844 * indicates that there was a completion with uncorrectable error for the 2845 * corresponding VF. Set by PXP. Reset by MCP writing 1 to 2846 * was_error_vf_63_32_clr. */ 2847 #define PGLUE_B_REG_WAS_ERROR_VF_63_32 0x9070 2848 /* [W 32] Was_error indication dirty bits clear for VFs 32 to 63. MCP writes 2849 * 1 to a bit in this register in order to clear the corresponding bit in 2850 * was_error_vf_63_32 register. */ 2851 #define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR 0x947c 2852 /* [R 32] Was_error indication dirty bits for VFs 64 to 95. Each bit 2853 * indicates that there was a completion with uncorrectable error for the 2854 * corresponding VF. Set by PXP. Reset by MCP writing 1 to 2855 * was_error_vf_95_64_clr. */ 2856 #define PGLUE_B_REG_WAS_ERROR_VF_95_64 0x9074 2857 /* [W 32] Was_error indication dirty bits clear for VFs 64 to 95. MCP writes 2858 * 1 to a bit in this register in order to clear the corresponding bit in 2859 * was_error_vf_95_64 register. */ 2860 #define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR 0x9480 2861 /* [RW 1] Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1 2862 * - enable. */ 2863 #define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE 0x9188 2864 /* [RW 16] Start offset of XSDM zone A (queue zone) in the internal RAM */ 2865 #define PGLUE_B_REG_XSDM_START_OFFSET_A 0x90ec 2866 /* [RW 16] Start offset of XSDM zone B (legacy zone) in the internal RAM */ 2867 #define PGLUE_B_REG_XSDM_START_OFFSET_B 0x90f4 2868 /* [RW 5] VF Shift of XSDM zone B (legacy zone) in the internal RAM */ 2869 #define PGLUE_B_REG_XSDM_VF_SHIFT_B 0x90fc 2870 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */ 2871 #define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF 0x91a8 2872 #define PRS_REG_A_PRSU_20 0x40134 2873 /* [R 8] debug only: CFC load request current credit. Transaction based. */ 2874 #define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164 2875 /* [R 8] debug only: CFC search request current credit. Transaction based. */ 2876 #define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168 2877 /* [RW 6] The initial credit for the search message to the CFC interface. 2878 Credit is transaction based. */ 2879 #define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c 2880 /* [RW 24] CID for port 0 if no match */ 2881 #define PRS_REG_CID_PORT_0 0x400fc 2882 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC 2883 load response is reset and packet type is 0. Used in packet start message 2884 to TCM. */ 2885 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc 2886 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0 2887 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4 2888 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8 2889 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec 2890 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0 2891 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC 2892 load response is set and packet type is 0. Used in packet start message 2893 to TCM. */ 2894 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc 2895 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0 2896 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4 2897 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8 2898 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc 2899 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0 2900 /* [RW 32] The CM header for a match and packet type 1 for loopback port. 2901 Used in packet start message to TCM. */ 2902 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c 2903 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0 2904 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4 2905 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8 2906 /* [RW 32] The CM header for a match and packet type 0. Used in packet start 2907 message to TCM. */ 2908 #define PRS_REG_CM_HDR_TYPE_0 0x40078 2909 #define PRS_REG_CM_HDR_TYPE_1 0x4007c 2910 #define PRS_REG_CM_HDR_TYPE_2 0x40080 2911 #define PRS_REG_CM_HDR_TYPE_3 0x40084 2912 #define PRS_REG_CM_HDR_TYPE_4 0x40088 2913 /* [RW 32] The CM header in case there was not a match on the connection */ 2914 #define PRS_REG_CM_NO_MATCH_HDR 0x400b8 2915 /* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */ 2916 #define PRS_REG_E1HOV_MODE 0x401c8 2917 /* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet 2918 start message to TCM. */ 2919 #define PRS_REG_EVENT_ID_1 0x40054 2920 #define PRS_REG_EVENT_ID_2 0x40058 2921 #define PRS_REG_EVENT_ID_3 0x4005c 2922 /* [RW 16] The Ethernet type value for FCoE */ 2923 #define PRS_REG_FCOE_TYPE 0x401d0 2924 /* [RW 8] Context region for flush packet with packet type 0. Used in CFC 2925 load request message. */ 2926 #define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004 2927 #define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008 2928 #define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c 2929 #define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010 2930 #define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014 2931 #define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018 2932 #define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c 2933 #define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020 2934 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2935 * Ethernet header. */ 2936 #define PRS_REG_HDRS_AFTER_BASIC 0x40238 2937 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2938 * Ethernet header for port 0 packets. */ 2939 #define PRS_REG_HDRS_AFTER_BASIC_PORT_0 0x40270 2940 #define PRS_REG_HDRS_AFTER_BASIC_PORT_1 0x40290 2941 /* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */ 2942 #define PRS_REG_HDRS_AFTER_TAG_0 0x40248 2943 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for 2944 * port 0 packets */ 2945 #define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 0x40280 2946 #define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 0x402a0 2947 /* [RW 4] The increment value to send in the CFC load request message */ 2948 #define PRS_REG_INC_VALUE 0x40048 2949 /* [RW 6] Bit-map indicating which headers must appear in the packet */ 2950 #define PRS_REG_MUST_HAVE_HDRS 0x40254 2951 /* [RW 6] Bit-map indicating which headers must appear in the packet for 2952 * port 0 packets */ 2953 #define PRS_REG_MUST_HAVE_HDRS_PORT_0 0x4028c 2954 #define PRS_REG_MUST_HAVE_HDRS_PORT_1 0x402ac 2955 #define PRS_REG_NIC_MODE 0x40138 2956 /* [RW 8] The 8-bit event ID for cases where there is no match on the 2957 connection. Used in packet start message to TCM. */ 2958 #define PRS_REG_NO_MATCH_EVENT_ID 0x40070 2959 /* [ST 24] The number of input CFC flush packets */ 2960 #define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128 2961 /* [ST 32] The number of cycles the Parser halted its operation since it 2962 could not allocate the next serial number */ 2963 #define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130 2964 /* [ST 24] The number of input packets */ 2965 #define PRS_REG_NUM_OF_PACKETS 0x40124 2966 /* [ST 24] The number of input transparent flush packets */ 2967 #define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c 2968 /* [RW 8] Context region for received Ethernet packet with a match and 2969 packet type 0. Used in CFC load request message */ 2970 #define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028 2971 #define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c 2972 #define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030 2973 #define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034 2974 #define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038 2975 #define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c 2976 #define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040 2977 #define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044 2978 /* [R 2] debug only: Number of pending requests for CAC on port 0. */ 2979 #define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174 2980 /* [R 2] debug only: Number of pending requests for header parsing. */ 2981 #define PRS_REG_PENDING_BRB_PRS_RQ 0x40170 2982 /* [R 1] Interrupt register #0 read */ 2983 #define PRS_REG_PRS_INT_STS 0x40188 2984 /* [RW 8] Parity mask register #0 read/write */ 2985 #define PRS_REG_PRS_PRTY_MASK 0x401a4 2986 /* [R 8] Parity register #0 read */ 2987 #define PRS_REG_PRS_PRTY_STS 0x40198 2988 /* [RC 8] Parity register #0 read clear */ 2989 #define PRS_REG_PRS_PRTY_STS_CLR 0x4019c 2990 /* [RW 8] Context region for pure acknowledge packets. Used in CFC load 2991 request message */ 2992 #define PRS_REG_PURE_REGIONS 0x40024 2993 /* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this 2994 serail number was released by SDM but cannot be used because a previous 2995 serial number was not released. */ 2996 #define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154 2997 /* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this 2998 serail number was released by SDM but cannot be used because a previous 2999 serial number was not released. */ 3000 #define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158 3001 /* [R 4] debug only: SRC current credit. Transaction based. */ 3002 #define PRS_REG_SRC_CURRENT_CREDIT 0x4016c 3003 /* [RW 16] The Ethernet type value for L2 tag 0 */ 3004 #define PRS_REG_TAG_ETHERTYPE_0 0x401d4 3005 /* [RW 4] The length of the info field for L2 tag 0. The length is between 3006 * 2B and 14B; in 2B granularity */ 3007 #define PRS_REG_TAG_LEN_0 0x4022c 3008 /* [R 8] debug only: TCM current credit. Cycle based. */ 3009 #define PRS_REG_TCM_CURRENT_CREDIT 0x40160 3010 /* [R 8] debug only: TSDM current credit. Transaction based. */ 3011 #define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c 3012 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1<<19) 3013 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1<<20) 3014 #define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1<<22) 3015 #define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED (0x1<<23) 3016 #define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED (0x1<<24) 3017 #define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7) 3018 #define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7) 3019 /* [R 6] Debug only: Number of used entries in the data FIFO */ 3020 #define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c 3021 /* [R 7] Debug only: Number of used entries in the header FIFO */ 3022 #define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478 3023 #define PXP2_REG_PGL_ADDR_88_F0 0x120534 3024 /* [R 32] GRC address for configuration access to PCIE config address 0x88. 3025 * any write to this PCIE address will cause a GRC write access to the 3026 * address that's in t this register */ 3027 #define PXP2_REG_PGL_ADDR_88_F1 0x120544 3028 #define PXP2_REG_PGL_ADDR_8C_F0 0x120538 3029 /* [R 32] GRC address for configuration access to PCIE config address 0x8c. 3030 * any write to this PCIE address will cause a GRC write access to the 3031 * address that's in t this register */ 3032 #define PXP2_REG_PGL_ADDR_8C_F1 0x120548 3033 #define PXP2_REG_PGL_ADDR_90_F0 0x12053c 3034 /* [R 32] GRC address for configuration access to PCIE config address 0x90. 3035 * any write to this PCIE address will cause a GRC write access to the 3036 * address that's in t this register */ 3037 #define PXP2_REG_PGL_ADDR_90_F1 0x12054c 3038 #define PXP2_REG_PGL_ADDR_94_F0 0x120540 3039 /* [R 32] GRC address for configuration access to PCIE config address 0x94. 3040 * any write to this PCIE address will cause a GRC write access to the 3041 * address that's in t this register */ 3042 #define PXP2_REG_PGL_ADDR_94_F1 0x120550 3043 #define PXP2_REG_PGL_CONTROL0 0x120490 3044 #define PXP2_REG_PGL_CONTROL1 0x120514 3045 #define PXP2_REG_PGL_DEBUG 0x120520 3046 /* [RW 32] third dword data of expansion rom request. this register is 3047 special. reading from it provides a vector outstanding read requests. if 3048 a bit is zero it means that a read request on the corresponding tag did 3049 not finish yet (not all completions have arrived for it) */ 3050 #define PXP2_REG_PGL_EXP_ROM2 0x120808 3051 /* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask; 3052 its[15:0]-address */ 3053 #define PXP2_REG_PGL_INT_CSDM_0 0x1204f4 3054 #define PXP2_REG_PGL_INT_CSDM_1 0x1204f8 3055 #define PXP2_REG_PGL_INT_CSDM_2 0x1204fc 3056 #define PXP2_REG_PGL_INT_CSDM_3 0x120500 3057 #define PXP2_REG_PGL_INT_CSDM_4 0x120504 3058 #define PXP2_REG_PGL_INT_CSDM_5 0x120508 3059 #define PXP2_REG_PGL_INT_CSDM_6 0x12050c 3060 #define PXP2_REG_PGL_INT_CSDM_7 0x120510 3061 /* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask; 3062 its[15:0]-address */ 3063 #define PXP2_REG_PGL_INT_TSDM_0 0x120494 3064 #define PXP2_REG_PGL_INT_TSDM_1 0x120498 3065 #define PXP2_REG_PGL_INT_TSDM_2 0x12049c 3066 #define PXP2_REG_PGL_INT_TSDM_3 0x1204a0 3067 #define PXP2_REG_PGL_INT_TSDM_4 0x1204a4 3068 #define PXP2_REG_PGL_INT_TSDM_5 0x1204a8 3069 #define PXP2_REG_PGL_INT_TSDM_6 0x1204ac 3070 #define PXP2_REG_PGL_INT_TSDM_7 0x1204b0 3071 /* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask; 3072 its[15:0]-address */ 3073 #define PXP2_REG_PGL_INT_USDM_0 0x1204b4 3074 #define PXP2_REG_PGL_INT_USDM_1 0x1204b8 3075 #define PXP2_REG_PGL_INT_USDM_2 0x1204bc 3076 #define PXP2_REG_PGL_INT_USDM_3 0x1204c0 3077 #define PXP2_REG_PGL_INT_USDM_4 0x1204c4 3078 #define PXP2_REG_PGL_INT_USDM_5 0x1204c8 3079 #define PXP2_REG_PGL_INT_USDM_6 0x1204cc 3080 #define PXP2_REG_PGL_INT_USDM_7 0x1204d0 3081 /* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask; 3082 its[15:0]-address */ 3083 #define PXP2_REG_PGL_INT_XSDM_0 0x1204d4 3084 #define PXP2_REG_PGL_INT_XSDM_1 0x1204d8 3085 #define PXP2_REG_PGL_INT_XSDM_2 0x1204dc 3086 #define PXP2_REG_PGL_INT_XSDM_3 0x1204e0 3087 #define PXP2_REG_PGL_INT_XSDM_4 0x1204e4 3088 #define PXP2_REG_PGL_INT_XSDM_5 0x1204e8 3089 #define PXP2_REG_PGL_INT_XSDM_6 0x1204ec 3090 #define PXP2_REG_PGL_INT_XSDM_7 0x1204f0 3091 /* [RW 3] this field allows one function to pretend being another function 3092 when accessing any BAR mapped resource within the device. the value of 3093 the field is the number of the function that will be accessed 3094 effectively. after software write to this bit it must read it in order to 3095 know that the new value is updated */ 3096 #define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674 3097 #define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678 3098 #define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067c 3099 #define PXP2_REG_PGL_PRETEND_FUNC_F3 0x120680 3100 #define PXP2_REG_PGL_PRETEND_FUNC_F4 0x120684 3101 #define PXP2_REG_PGL_PRETEND_FUNC_F5 0x120688 3102 #define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068c 3103 #define PXP2_REG_PGL_PRETEND_FUNC_F7 0x120690 3104 /* [R 1] this bit indicates that a read request was blocked because of 3105 bus_master_en was deasserted */ 3106 #define PXP2_REG_PGL_READ_BLOCKED 0x120568 3107 #define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8 3108 /* [R 18] debug only */ 3109 #define PXP2_REG_PGL_TXW_CDTS 0x12052c 3110 /* [R 1] this bit indicates that a write request was blocked because of 3111 bus_master_en was deasserted */ 3112 #define PXP2_REG_PGL_WRITE_BLOCKED 0x120564 3113 #define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0 3114 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4 3115 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8 3116 #define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4 3117 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228 3118 #define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8 3119 #define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4 3120 #define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8 3121 #define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc 3122 #define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0 3123 #define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c 3124 #define PXP2_REG_PSWRQ_BW_L1 0x1202b0 3125 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4 3126 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8 3127 #define PXP2_REG_PSWRQ_BW_L2 0x1202b4 3128 #define PXP2_REG_PSWRQ_BW_L28 0x120318 3129 #define PXP2_REG_PSWRQ_BW_L3 0x1202b8 3130 #define PXP2_REG_PSWRQ_BW_L6 0x1202c4 3131 #define PXP2_REG_PSWRQ_BW_L7 0x1202c8 3132 #define PXP2_REG_PSWRQ_BW_L8 0x1202cc 3133 #define PXP2_REG_PSWRQ_BW_L9 0x1202d0 3134 #define PXP2_REG_PSWRQ_BW_RD 0x120324 3135 #define PXP2_REG_PSWRQ_BW_UB1 0x120238 3136 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c 3137 #define PXP2_REG_PSWRQ_BW_UB11 0x120260 3138 #define PXP2_REG_PSWRQ_BW_UB2 0x12023c 3139 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0 3140 #define PXP2_REG_PSWRQ_BW_UB3 0x120240 3141 #define PXP2_REG_PSWRQ_BW_UB6 0x12024c 3142 #define PXP2_REG_PSWRQ_BW_UB7 0x120250 3143 #define PXP2_REG_PSWRQ_BW_UB8 0x120254 3144 #define PXP2_REG_PSWRQ_BW_UB9 0x120258 3145 #define PXP2_REG_PSWRQ_BW_WR 0x120328 3146 #define PXP2_REG_PSWRQ_CDU0_L2P 0x120000 3147 #define PXP2_REG_PSWRQ_QM0_L2P 0x120038 3148 #define PXP2_REG_PSWRQ_SRC0_L2P 0x120054 3149 #define PXP2_REG_PSWRQ_TM0_L2P 0x12001c 3150 #define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0 3151 /* [RW 32] Interrupt mask register #0 read/write */ 3152 #define PXP2_REG_PXP2_INT_MASK_0 0x120578 3153 /* [R 32] Interrupt register #0 read */ 3154 #define PXP2_REG_PXP2_INT_STS_0 0x12056c 3155 #define PXP2_REG_PXP2_INT_STS_1 0x120608 3156 /* [RC 32] Interrupt register #0 read clear */ 3157 #define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570 3158 /* [RW 32] Parity mask register #0 read/write */ 3159 #define PXP2_REG_PXP2_PRTY_MASK_0 0x120588 3160 #define PXP2_REG_PXP2_PRTY_MASK_1 0x120598 3161 /* [R 32] Parity register #0 read */ 3162 #define PXP2_REG_PXP2_PRTY_STS_0 0x12057c 3163 #define PXP2_REG_PXP2_PRTY_STS_1 0x12058c 3164 /* [RC 32] Parity register #0 read clear */ 3165 #define PXP2_REG_PXP2_PRTY_STS_CLR_0 0x120580 3166 #define PXP2_REG_PXP2_PRTY_STS_CLR_1 0x120590 3167 /* [R 1] Debug only: The 'almost full' indication from each fifo (gives 3168 indication about backpressure) */ 3169 #define PXP2_REG_RD_ALMOST_FULL_0 0x120424 3170 /* [R 8] Debug only: The blocks counter - number of unused block ids */ 3171 #define PXP2_REG_RD_BLK_CNT 0x120418 3172 /* [RW 8] Debug only: Total number of available blocks in Tetris Buffer. 3173 Must be bigger than 6. Normally should not be changed. */ 3174 #define PXP2_REG_RD_BLK_NUM_CFG 0x12040c 3175 /* [RW 2] CDU byte swapping mode configuration for master read requests */ 3176 #define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404 3177 /* [RW 1] When '1'; inputs to the PSWRD block are ignored */ 3178 #define PXP2_REG_RD_DISABLE_INPUTS 0x120374 3179 /* [R 1] PSWRD internal memories initialization is done */ 3180 #define PXP2_REG_RD_INIT_DONE 0x120370 3181 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3182 allocated for vq10 */ 3183 #define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0 3184 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3185 allocated for vq11 */ 3186 #define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4 3187 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3188 allocated for vq17 */ 3189 #define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc 3190 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3191 allocated for vq18 */ 3192 #define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0 3193 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3194 allocated for vq19 */ 3195 #define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4 3196 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3197 allocated for vq22 */ 3198 #define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0 3199 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3200 allocated for vq25 */ 3201 #define PXP2_REG_RD_MAX_BLKS_VQ25 0x1203dc 3202 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3203 allocated for vq6 */ 3204 #define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390 3205 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3206 allocated for vq9 */ 3207 #define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c 3208 /* [RW 2] PBF byte swapping mode configuration for master read requests */ 3209 #define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4 3210 /* [R 1] Debug only: Indication if delivery ports are idle */ 3211 #define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c 3212 #define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420 3213 /* [RW 2] QM byte swapping mode configuration for master read requests */ 3214 #define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8 3215 /* [R 7] Debug only: The SR counter - number of unused sub request ids */ 3216 #define PXP2_REG_RD_SR_CNT 0x120414 3217 /* [RW 2] SRC byte swapping mode configuration for master read requests */ 3218 #define PXP2_REG_RD_SRC_SWAP_MODE 0x120400 3219 /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must 3220 be bigger than 1. Normally should not be changed. */ 3221 #define PXP2_REG_RD_SR_NUM_CFG 0x120408 3222 /* [RW 1] Signals the PSWRD block to start initializing internal memories */ 3223 #define PXP2_REG_RD_START_INIT 0x12036c 3224 /* [RW 2] TM byte swapping mode configuration for master read requests */ 3225 #define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc 3226 /* [RW 10] Bandwidth addition to VQ0 write requests */ 3227 #define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc 3228 /* [RW 10] Bandwidth addition to VQ12 read requests */ 3229 #define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec 3230 /* [RW 10] Bandwidth addition to VQ13 read requests */ 3231 #define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0 3232 /* [RW 10] Bandwidth addition to VQ14 read requests */ 3233 #define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4 3234 /* [RW 10] Bandwidth addition to VQ15 read requests */ 3235 #define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8 3236 /* [RW 10] Bandwidth addition to VQ16 read requests */ 3237 #define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc 3238 /* [RW 10] Bandwidth addition to VQ17 read requests */ 3239 #define PXP2_REG_RQ_BW_RD_ADD17 0x120200 3240 /* [RW 10] Bandwidth addition to VQ18 read requests */ 3241 #define PXP2_REG_RQ_BW_RD_ADD18 0x120204 3242 /* [RW 10] Bandwidth addition to VQ19 read requests */ 3243 #define PXP2_REG_RQ_BW_RD_ADD19 0x120208 3244 /* [RW 10] Bandwidth addition to VQ20 read requests */ 3245 #define PXP2_REG_RQ_BW_RD_ADD20 0x12020c 3246 /* [RW 10] Bandwidth addition to VQ22 read requests */ 3247 #define PXP2_REG_RQ_BW_RD_ADD22 0x120210 3248 /* [RW 10] Bandwidth addition to VQ23 read requests */ 3249 #define PXP2_REG_RQ_BW_RD_ADD23 0x120214 3250 /* [RW 10] Bandwidth addition to VQ24 read requests */ 3251 #define PXP2_REG_RQ_BW_RD_ADD24 0x120218 3252 /* [RW 10] Bandwidth addition to VQ25 read requests */ 3253 #define PXP2_REG_RQ_BW_RD_ADD25 0x12021c 3254 /* [RW 10] Bandwidth addition to VQ26 read requests */ 3255 #define PXP2_REG_RQ_BW_RD_ADD26 0x120220 3256 /* [RW 10] Bandwidth addition to VQ27 read requests */ 3257 #define PXP2_REG_RQ_BW_RD_ADD27 0x120224 3258 /* [RW 10] Bandwidth addition to VQ4 read requests */ 3259 #define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc 3260 /* [RW 10] Bandwidth addition to VQ5 read requests */ 3261 #define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0 3262 /* [RW 10] Bandwidth Typical L for VQ0 Read requests */ 3263 #define PXP2_REG_RQ_BW_RD_L0 0x1202ac 3264 /* [RW 10] Bandwidth Typical L for VQ12 Read requests */ 3265 #define PXP2_REG_RQ_BW_RD_L12 0x1202dc 3266 /* [RW 10] Bandwidth Typical L for VQ13 Read requests */ 3267 #define PXP2_REG_RQ_BW_RD_L13 0x1202e0 3268 /* [RW 10] Bandwidth Typical L for VQ14 Read requests */ 3269 #define PXP2_REG_RQ_BW_RD_L14 0x1202e4 3270 /* [RW 10] Bandwidth Typical L for VQ15 Read requests */ 3271 #define PXP2_REG_RQ_BW_RD_L15 0x1202e8 3272 /* [RW 10] Bandwidth Typical L for VQ16 Read requests */ 3273 #define PXP2_REG_RQ_BW_RD_L16 0x1202ec 3274 /* [RW 10] Bandwidth Typical L for VQ17 Read requests */ 3275 #define PXP2_REG_RQ_BW_RD_L17 0x1202f0 3276 /* [RW 10] Bandwidth Typical L for VQ18 Read requests */ 3277 #define PXP2_REG_RQ_BW_RD_L18 0x1202f4 3278 /* [RW 10] Bandwidth Typical L for VQ19 Read requests */ 3279 #define PXP2_REG_RQ_BW_RD_L19 0x1202f8 3280 /* [RW 10] Bandwidth Typical L for VQ20 Read requests */ 3281 #define PXP2_REG_RQ_BW_RD_L20 0x1202fc 3282 /* [RW 10] Bandwidth Typical L for VQ22 Read requests */ 3283 #define PXP2_REG_RQ_BW_RD_L22 0x120300 3284 /* [RW 10] Bandwidth Typical L for VQ23 Read requests */ 3285 #define PXP2_REG_RQ_BW_RD_L23 0x120304 3286 /* [RW 10] Bandwidth Typical L for VQ24 Read requests */ 3287 #define PXP2_REG_RQ_BW_RD_L24 0x120308 3288 /* [RW 10] Bandwidth Typical L for VQ25 Read requests */ 3289 #define PXP2_REG_RQ_BW_RD_L25 0x12030c 3290 /* [RW 10] Bandwidth Typical L for VQ26 Read requests */ 3291 #define PXP2_REG_RQ_BW_RD_L26 0x120310 3292 /* [RW 10] Bandwidth Typical L for VQ27 Read requests */ 3293 #define PXP2_REG_RQ_BW_RD_L27 0x120314 3294 /* [RW 10] Bandwidth Typical L for VQ4 Read requests */ 3295 #define PXP2_REG_RQ_BW_RD_L4 0x1202bc 3296 /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */ 3297 #define PXP2_REG_RQ_BW_RD_L5 0x1202c0 3298 /* [RW 7] Bandwidth upper bound for VQ0 read requests */ 3299 #define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234 3300 /* [RW 7] Bandwidth upper bound for VQ12 read requests */ 3301 #define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264 3302 /* [RW 7] Bandwidth upper bound for VQ13 read requests */ 3303 #define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268 3304 /* [RW 7] Bandwidth upper bound for VQ14 read requests */ 3305 #define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c 3306 /* [RW 7] Bandwidth upper bound for VQ15 read requests */ 3307 #define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270 3308 /* [RW 7] Bandwidth upper bound for VQ16 read requests */ 3309 #define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274 3310 /* [RW 7] Bandwidth upper bound for VQ17 read requests */ 3311 #define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278 3312 /* [RW 7] Bandwidth upper bound for VQ18 read requests */ 3313 #define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c 3314 /* [RW 7] Bandwidth upper bound for VQ19 read requests */ 3315 #define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280 3316 /* [RW 7] Bandwidth upper bound for VQ20 read requests */ 3317 #define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284 3318 /* [RW 7] Bandwidth upper bound for VQ22 read requests */ 3319 #define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288 3320 /* [RW 7] Bandwidth upper bound for VQ23 read requests */ 3321 #define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c 3322 /* [RW 7] Bandwidth upper bound for VQ24 read requests */ 3323 #define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290 3324 /* [RW 7] Bandwidth upper bound for VQ25 read requests */ 3325 #define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294 3326 /* [RW 7] Bandwidth upper bound for VQ26 read requests */ 3327 #define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298 3328 /* [RW 7] Bandwidth upper bound for VQ27 read requests */ 3329 #define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c 3330 /* [RW 7] Bandwidth upper bound for VQ4 read requests */ 3331 #define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244 3332 /* [RW 7] Bandwidth upper bound for VQ5 read requests */ 3333 #define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248 3334 /* [RW 10] Bandwidth addition to VQ29 write requests */ 3335 #define PXP2_REG_RQ_BW_WR_ADD29 0x12022c 3336 /* [RW 10] Bandwidth addition to VQ30 write requests */ 3337 #define PXP2_REG_RQ_BW_WR_ADD30 0x120230 3338 /* [RW 10] Bandwidth Typical L for VQ29 Write requests */ 3339 #define PXP2_REG_RQ_BW_WR_L29 0x12031c 3340 /* [RW 10] Bandwidth Typical L for VQ30 Write requests */ 3341 #define PXP2_REG_RQ_BW_WR_L30 0x120320 3342 /* [RW 7] Bandwidth upper bound for VQ29 */ 3343 #define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4 3344 /* [RW 7] Bandwidth upper bound for VQ30 */ 3345 #define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8 3346 /* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */ 3347 #define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008 3348 /* [RW 2] Endian mode for cdu */ 3349 #define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0 3350 #define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c 3351 #define PXP2_REG_RQ_CDU_LAST_ILT 0x120620 3352 /* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k; 3353 -128k */ 3354 #define PXP2_REG_RQ_CDU_P_SIZE 0x120018 3355 /* [R 1] 1' indicates that the requester has finished its internal 3356 configuration */ 3357 #define PXP2_REG_RQ_CFG_DONE 0x1201b4 3358 /* [RW 2] Endian mode for debug */ 3359 #define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4 3360 /* [RW 1] When '1'; requests will enter input buffers but wont get out 3361 towards the glue */ 3362 #define PXP2_REG_RQ_DISABLE_INPUTS 0x120330 3363 /* [RW 4] Determines alignment of write SRs when a request is split into 3364 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B 3365 * aligned. 4 - 512B aligned. */ 3366 #define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0 3367 /* [RW 4] Determines alignment of read SRs when a request is split into 3368 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B 3369 * aligned. 4 - 512B aligned. */ 3370 #define PXP2_REG_RQ_DRAM_ALIGN_RD 0x12092c 3371 /* [RW 1] when set the new alignment method (E2) will be applied; when reset 3372 * the original alignment method (E1 E1H) will be applied */ 3373 #define PXP2_REG_RQ_DRAM_ALIGN_SEL 0x120930 3374 /* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will 3375 be asserted */ 3376 #define PXP2_REG_RQ_ELT_DISABLE 0x12066c 3377 /* [RW 2] Endian mode for hc */ 3378 #define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8 3379 /* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back 3380 compatibility needs; Note that different registers are used per mode */ 3381 #define PXP2_REG_RQ_ILT_MODE 0x1205b4 3382 /* [WB 53] Onchip address table */ 3383 #define PXP2_REG_RQ_ONCHIP_AT 0x122000 3384 /* [WB 53] Onchip address table - B0 */ 3385 #define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000 3386 /* [RW 13] Pending read limiter threshold; in Dwords */ 3387 #define PXP2_REG_RQ_PDR_LIMIT 0x12033c 3388 /* [RW 2] Endian mode for qm */ 3389 #define PXP2_REG_RQ_QM_ENDIAN_M 0x120194 3390 #define PXP2_REG_RQ_QM_FIRST_ILT 0x120634 3391 #define PXP2_REG_RQ_QM_LAST_ILT 0x120638 3392 /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k; 3393 -128k */ 3394 #define PXP2_REG_RQ_QM_P_SIZE 0x120050 3395 /* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */ 3396 #define PXP2_REG_RQ_RBC_DONE 0x1201b0 3397 /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B; 3398 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */ 3399 #define PXP2_REG_RQ_RD_MBS0 0x120160 3400 /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B; 3401 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */ 3402 #define PXP2_REG_RQ_RD_MBS1 0x120168 3403 /* [RW 2] Endian mode for src */ 3404 #define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c 3405 #define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c 3406 #define PXP2_REG_RQ_SRC_LAST_ILT 0x120640 3407 /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k; 3408 -128k */ 3409 #define PXP2_REG_RQ_SRC_P_SIZE 0x12006c 3410 /* [RW 2] Endian mode for tm */ 3411 #define PXP2_REG_RQ_TM_ENDIAN_M 0x120198 3412 #define PXP2_REG_RQ_TM_FIRST_ILT 0x120644 3413 #define PXP2_REG_RQ_TM_LAST_ILT 0x120648 3414 /* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k; 3415 -128k */ 3416 #define PXP2_REG_RQ_TM_P_SIZE 0x120034 3417 /* [R 5] Number of entries in the ufifo; his fifo has l2p completions */ 3418 #define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c 3419 /* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */ 3420 #define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094 3421 /* [R 8] Number of entries occupied by vq 0 in pswrq memory */ 3422 #define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810 3423 /* [R 8] Number of entries occupied by vq 10 in pswrq memory */ 3424 #define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818 3425 /* [R 8] Number of entries occupied by vq 11 in pswrq memory */ 3426 #define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820 3427 /* [R 8] Number of entries occupied by vq 12 in pswrq memory */ 3428 #define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828 3429 /* [R 8] Number of entries occupied by vq 13 in pswrq memory */ 3430 #define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830 3431 /* [R 8] Number of entries occupied by vq 14 in pswrq memory */ 3432 #define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838 3433 /* [R 8] Number of entries occupied by vq 15 in pswrq memory */ 3434 #define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840 3435 /* [R 8] Number of entries occupied by vq 16 in pswrq memory */ 3436 #define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848 3437 /* [R 8] Number of entries occupied by vq 17 in pswrq memory */ 3438 #define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850 3439 /* [R 8] Number of entries occupied by vq 18 in pswrq memory */ 3440 #define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858 3441 /* [R 8] Number of entries occupied by vq 19 in pswrq memory */ 3442 #define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860 3443 /* [R 8] Number of entries occupied by vq 1 in pswrq memory */ 3444 #define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868 3445 /* [R 8] Number of entries occupied by vq 20 in pswrq memory */ 3446 #define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870 3447 /* [R 8] Number of entries occupied by vq 21 in pswrq memory */ 3448 #define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878 3449 /* [R 8] Number of entries occupied by vq 22 in pswrq memory */ 3450 #define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880 3451 /* [R 8] Number of entries occupied by vq 23 in pswrq memory */ 3452 #define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888 3453 /* [R 8] Number of entries occupied by vq 24 in pswrq memory */ 3454 #define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890 3455 /* [R 8] Number of entries occupied by vq 25 in pswrq memory */ 3456 #define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898 3457 /* [R 8] Number of entries occupied by vq 26 in pswrq memory */ 3458 #define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0 3459 /* [R 8] Number of entries occupied by vq 27 in pswrq memory */ 3460 #define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8 3461 /* [R 8] Number of entries occupied by vq 28 in pswrq memory */ 3462 #define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0 3463 /* [R 8] Number of entries occupied by vq 29 in pswrq memory */ 3464 #define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8 3465 /* [R 8] Number of entries occupied by vq 2 in pswrq memory */ 3466 #define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0 3467 /* [R 8] Number of entries occupied by vq 30 in pswrq memory */ 3468 #define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8 3469 /* [R 8] Number of entries occupied by vq 31 in pswrq memory */ 3470 #define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0 3471 /* [R 8] Number of entries occupied by vq 3 in pswrq memory */ 3472 #define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8 3473 /* [R 8] Number of entries occupied by vq 4 in pswrq memory */ 3474 #define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0 3475 /* [R 8] Number of entries occupied by vq 5 in pswrq memory */ 3476 #define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8 3477 /* [R 8] Number of entries occupied by vq 6 in pswrq memory */ 3478 #define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0 3479 /* [R 8] Number of entries occupied by vq 7 in pswrq memory */ 3480 #define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8 3481 /* [R 8] Number of entries occupied by vq 8 in pswrq memory */ 3482 #define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900 3483 /* [R 8] Number of entries occupied by vq 9 in pswrq memory */ 3484 #define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908 3485 /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B; 3486 001:256B; 010: 512B; */ 3487 #define PXP2_REG_RQ_WR_MBS0 0x12015c 3488 /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B; 3489 001:256B; 010: 512B; */ 3490 #define PXP2_REG_RQ_WR_MBS1 0x120164 3491 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3492 buffer reaches this number has_payload will be asserted */ 3493 #define PXP2_REG_WR_CDU_MPS 0x1205f0 3494 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3495 buffer reaches this number has_payload will be asserted */ 3496 #define PXP2_REG_WR_CSDM_MPS 0x1205d0 3497 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3498 buffer reaches this number has_payload will be asserted */ 3499 #define PXP2_REG_WR_DBG_MPS 0x1205e8 3500 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3501 buffer reaches this number has_payload will be asserted */ 3502 #define PXP2_REG_WR_DMAE_MPS 0x1205ec 3503 /* [RW 10] if Number of entries in dmae fifo will be higher than this 3504 threshold then has_payload indication will be asserted; the default value 3505 should be equal to > write MBS size! */ 3506 #define PXP2_REG_WR_DMAE_TH 0x120368 3507 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3508 buffer reaches this number has_payload will be asserted */ 3509 #define PXP2_REG_WR_HC_MPS 0x1205c8 3510 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3511 buffer reaches this number has_payload will be asserted */ 3512 #define PXP2_REG_WR_QM_MPS 0x1205dc 3513 /* [RW 1] 0 - working in A0 mode; - working in B0 mode */ 3514 #define PXP2_REG_WR_REV_MODE 0x120670 3515 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3516 buffer reaches this number has_payload will be asserted */ 3517 #define PXP2_REG_WR_SRC_MPS 0x1205e4 3518 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3519 buffer reaches this number has_payload will be asserted */ 3520 #define PXP2_REG_WR_TM_MPS 0x1205e0 3521 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3522 buffer reaches this number has_payload will be asserted */ 3523 #define PXP2_REG_WR_TSDM_MPS 0x1205d4 3524 /* [RW 10] if Number of entries in usdmdp fifo will be higher than this 3525 threshold then has_payload indication will be asserted; the default value 3526 should be equal to > write MBS size! */ 3527 #define PXP2_REG_WR_USDMDP_TH 0x120348 3528 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3529 buffer reaches this number has_payload will be asserted */ 3530 #define PXP2_REG_WR_USDM_MPS 0x1205cc 3531 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3532 buffer reaches this number has_payload will be asserted */ 3533 #define PXP2_REG_WR_XSDM_MPS 0x1205d8 3534 /* [R 1] debug only: Indication if PSWHST arbiter is idle */ 3535 #define PXP_REG_HST_ARB_IS_IDLE 0x103004 3536 /* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means 3537 this client is waiting for the arbiter. */ 3538 #define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008 3539 /* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue 3540 block. Should be used for close the gates. */ 3541 #define PXP_REG_HST_DISCARD_DOORBELLS 0x1030a4 3542 /* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit 3543 should update according to 'hst_discard_doorbells' register when the state 3544 machine is idle */ 3545 #define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0 3546 /* [RW 1] When 1; new internal writes arriving to the block are discarded. 3547 Should be used for close the gates. */ 3548 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES 0x1030a8 3549 /* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1' 3550 means this PSWHST is discarding inputs from this client. Each bit should 3551 update according to 'hst_discard_internal_writes' register when the state 3552 machine is idle. */ 3553 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c 3554 /* [WB 160] Used for initialization of the inbound interrupts memory */ 3555 #define PXP_REG_HST_INBOUND_INT 0x103800 3556 /* [RW 32] Interrupt mask register #0 read/write */ 3557 #define PXP_REG_PXP_INT_MASK_0 0x103074 3558 #define PXP_REG_PXP_INT_MASK_1 0x103084 3559 /* [R 32] Interrupt register #0 read */ 3560 #define PXP_REG_PXP_INT_STS_0 0x103068 3561 #define PXP_REG_PXP_INT_STS_1 0x103078 3562 /* [RC 32] Interrupt register #0 read clear */ 3563 #define PXP_REG_PXP_INT_STS_CLR_0 0x10306c 3564 #define PXP_REG_PXP_INT_STS_CLR_1 0x10307c 3565 /* [RW 27] Parity mask register #0 read/write */ 3566 #define PXP_REG_PXP_PRTY_MASK 0x103094 3567 /* [R 26] Parity register #0 read */ 3568 #define PXP_REG_PXP_PRTY_STS 0x103088 3569 /* [RC 27] Parity register #0 read clear */ 3570 #define PXP_REG_PXP_PRTY_STS_CLR 0x10308c 3571 /* [RW 4] The activity counter initial increment value sent in the load 3572 request */ 3573 #define QM_REG_ACTCTRINITVAL_0 0x168040 3574 #define QM_REG_ACTCTRINITVAL_1 0x168044 3575 #define QM_REG_ACTCTRINITVAL_2 0x168048 3576 #define QM_REG_ACTCTRINITVAL_3 0x16804c 3577 /* [RW 32] The base logical address (in bytes) of each physical queue. The 3578 index I represents the physical queue number. The 12 lsbs are ignore and 3579 considered zero so practically there are only 20 bits in this register; 3580 queues 63-0 */ 3581 #define QM_REG_BASEADDR 0x168900 3582 /* [RW 32] The base logical address (in bytes) of each physical queue. The 3583 index I represents the physical queue number. The 12 lsbs are ignore and 3584 considered zero so practically there are only 20 bits in this register; 3585 queues 127-64 */ 3586 #define QM_REG_BASEADDR_EXT_A 0x16e100 3587 /* [RW 16] The byte credit cost for each task. This value is for both ports */ 3588 #define QM_REG_BYTECRDCOST 0x168234 3589 /* [RW 16] The initial byte credit value for both ports. */ 3590 #define QM_REG_BYTECRDINITVAL 0x168238 3591 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical 3592 queue uses port 0 else it uses port 1; queues 31-0 */ 3593 #define QM_REG_BYTECRDPORT_LSB 0x168228 3594 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical 3595 queue uses port 0 else it uses port 1; queues 95-64 */ 3596 #define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520 3597 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical 3598 queue uses port 0 else it uses port 1; queues 63-32 */ 3599 #define QM_REG_BYTECRDPORT_MSB 0x168224 3600 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical 3601 queue uses port 0 else it uses port 1; queues 127-96 */ 3602 #define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c 3603 /* [RW 16] The byte credit value that if above the QM is considered almost 3604 full */ 3605 #define QM_REG_BYTECREDITAFULLTHR 0x168094 3606 /* [RW 4] The initial credit for interface */ 3607 #define QM_REG_CMINITCRD_0 0x1680cc 3608 #define QM_REG_BYTECRDCMDQ_0 0x16e6e8 3609 #define QM_REG_CMINITCRD_1 0x1680d0 3610 #define QM_REG_CMINITCRD_2 0x1680d4 3611 #define QM_REG_CMINITCRD_3 0x1680d8 3612 #define QM_REG_CMINITCRD_4 0x1680dc 3613 #define QM_REG_CMINITCRD_5 0x1680e0 3614 #define QM_REG_CMINITCRD_6 0x1680e4 3615 #define QM_REG_CMINITCRD_7 0x1680e8 3616 /* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface 3617 is masked */ 3618 #define QM_REG_CMINTEN 0x1680ec 3619 /* [RW 12] A bit vector which indicates which one of the queues are tied to 3620 interface 0 */ 3621 #define QM_REG_CMINTVOQMASK_0 0x1681f4 3622 #define QM_REG_CMINTVOQMASK_1 0x1681f8 3623 #define QM_REG_CMINTVOQMASK_2 0x1681fc 3624 #define QM_REG_CMINTVOQMASK_3 0x168200 3625 #define QM_REG_CMINTVOQMASK_4 0x168204 3626 #define QM_REG_CMINTVOQMASK_5 0x168208 3627 #define QM_REG_CMINTVOQMASK_6 0x16820c 3628 #define QM_REG_CMINTVOQMASK_7 0x168210 3629 /* [RW 20] The number of connections divided by 16 which dictates the size 3630 of each queue which belongs to even function number. */ 3631 #define QM_REG_CONNNUM_0 0x168020 3632 /* [R 6] Keep the fill level of the fifo from write client 4 */ 3633 #define QM_REG_CQM_WRC_FIFOLVL 0x168018 3634 /* [RW 8] The context regions sent in the CFC load request */ 3635 #define QM_REG_CTXREG_0 0x168030 3636 #define QM_REG_CTXREG_1 0x168034 3637 #define QM_REG_CTXREG_2 0x168038 3638 #define QM_REG_CTXREG_3 0x16803c 3639 /* [RW 12] The VOQ mask used to select the VOQs which needs to be full for 3640 bypass enable */ 3641 #define QM_REG_ENBYPVOQMASK 0x16823c 3642 /* [RW 32] A bit mask per each physical queue. If a bit is set then the 3643 physical queue uses the byte credit; queues 31-0 */ 3644 #define QM_REG_ENBYTECRD_LSB 0x168220 3645 /* [RW 32] A bit mask per each physical queue. If a bit is set then the 3646 physical queue uses the byte credit; queues 95-64 */ 3647 #define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518 3648 /* [RW 32] A bit mask per each physical queue. If a bit is set then the 3649 physical queue uses the byte credit; queues 63-32 */ 3650 #define QM_REG_ENBYTECRD_MSB 0x16821c 3651 /* [RW 32] A bit mask per each physical queue. If a bit is set then the 3652 physical queue uses the byte credit; queues 127-96 */ 3653 #define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514 3654 /* [RW 4] If cleared then the secondary interface will not be served by the 3655 RR arbiter */ 3656 #define QM_REG_ENSEC 0x1680f0 3657 /* [RW 32] NA */ 3658 #define QM_REG_FUNCNUMSEL_LSB 0x168230 3659 /* [RW 32] NA */ 3660 #define QM_REG_FUNCNUMSEL_MSB 0x16822c 3661 /* [RW 32] A mask register to mask the Almost empty signals which will not 3662 be use for the almost empty indication to the HW block; queues 31:0 */ 3663 #define QM_REG_HWAEMPTYMASK_LSB 0x168218 3664 /* [RW 32] A mask register to mask the Almost empty signals which will not 3665 be use for the almost empty indication to the HW block; queues 95-64 */ 3666 #define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510 3667 /* [RW 32] A mask register to mask the Almost empty signals which will not 3668 be use for the almost empty indication to the HW block; queues 63:32 */ 3669 #define QM_REG_HWAEMPTYMASK_MSB 0x168214 3670 /* [RW 32] A mask register to mask the Almost empty signals which will not 3671 be use for the almost empty indication to the HW block; queues 127-96 */ 3672 #define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c 3673 /* [RW 4] The number of outstanding request to CFC */ 3674 #define QM_REG_OUTLDREQ 0x168804 3675 /* [RC 1] A flag to indicate that overflow error occurred in one of the 3676 queues. */ 3677 #define QM_REG_OVFERROR 0x16805c 3678 /* [RC 7] the Q where the overflow occurs */ 3679 #define QM_REG_OVFQNUM 0x168058 3680 /* [R 16] Pause state for physical queues 15-0 */ 3681 #define QM_REG_PAUSESTATE0 0x168410 3682 /* [R 16] Pause state for physical queues 31-16 */ 3683 #define QM_REG_PAUSESTATE1 0x168414 3684 /* [R 16] Pause state for physical queues 47-32 */ 3685 #define QM_REG_PAUSESTATE2 0x16e684 3686 /* [R 16] Pause state for physical queues 63-48 */ 3687 #define QM_REG_PAUSESTATE3 0x16e688 3688 /* [R 16] Pause state for physical queues 79-64 */ 3689 #define QM_REG_PAUSESTATE4 0x16e68c 3690 /* [R 16] Pause state for physical queues 95-80 */ 3691 #define QM_REG_PAUSESTATE5 0x16e690 3692 /* [R 16] Pause state for physical queues 111-96 */ 3693 #define QM_REG_PAUSESTATE6 0x16e694 3694 /* [R 16] Pause state for physical queues 127-112 */ 3695 #define QM_REG_PAUSESTATE7 0x16e698 3696 /* [RW 2] The PCI attributes field used in the PCI request. */ 3697 #define QM_REG_PCIREQAT 0x168054 3698 #define QM_REG_PF_EN 0x16e70c 3699 /* [R 24] The number of tasks stored in the QM for the PF. only even 3700 * functions are valid in E2 (odd I registers will be hard wired to 0) */ 3701 #define QM_REG_PF_USG_CNT_0 0x16e040 3702 /* [R 16] NOT USED */ 3703 #define QM_REG_PORT0BYTECRD 0x168300 3704 /* [R 16] The byte credit of port 1 */ 3705 #define QM_REG_PORT1BYTECRD 0x168304 3706 /* [RW 3] pci function number of queues 15-0 */ 3707 #define QM_REG_PQ2PCIFUNC_0 0x16e6bc 3708 #define QM_REG_PQ2PCIFUNC_1 0x16e6c0 3709 #define QM_REG_PQ2PCIFUNC_2 0x16e6c4 3710 #define QM_REG_PQ2PCIFUNC_3 0x16e6c8 3711 #define QM_REG_PQ2PCIFUNC_4 0x16e6cc 3712 #define QM_REG_PQ2PCIFUNC_5 0x16e6d0 3713 #define QM_REG_PQ2PCIFUNC_6 0x16e6d4 3714 #define QM_REG_PQ2PCIFUNC_7 0x16e6d8 3715 /* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow: 3716 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read 3717 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */ 3718 #define QM_REG_PTRTBL 0x168a00 3719 /* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow: 3720 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read 3721 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */ 3722 #define QM_REG_PTRTBL_EXT_A 0x16e200 3723 /* [RW 2] Interrupt mask register #0 read/write */ 3724 #define QM_REG_QM_INT_MASK 0x168444 3725 /* [R 2] Interrupt register #0 read */ 3726 #define QM_REG_QM_INT_STS 0x168438 3727 /* [RW 12] Parity mask register #0 read/write */ 3728 #define QM_REG_QM_PRTY_MASK 0x168454 3729 /* [R 12] Parity register #0 read */ 3730 #define QM_REG_QM_PRTY_STS 0x168448 3731 /* [RC 12] Parity register #0 read clear */ 3732 #define QM_REG_QM_PRTY_STS_CLR 0x16844c 3733 /* [R 32] Current queues in pipeline: Queues from 32 to 63 */ 3734 #define QM_REG_QSTATUS_HIGH 0x16802c 3735 /* [R 32] Current queues in pipeline: Queues from 96 to 127 */ 3736 #define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408 3737 /* [R 32] Current queues in pipeline: Queues from 0 to 31 */ 3738 #define QM_REG_QSTATUS_LOW 0x168028 3739 /* [R 32] Current queues in pipeline: Queues from 64 to 95 */ 3740 #define QM_REG_QSTATUS_LOW_EXT_A 0x16e404 3741 /* [R 24] The number of tasks queued for each queue; queues 63-0 */ 3742 #define QM_REG_QTASKCTR_0 0x168308 3743 /* [R 24] The number of tasks queued for each queue; queues 127-64 */ 3744 #define QM_REG_QTASKCTR_EXT_A_0 0x16e584 3745 /* [RW 4] Queue tied to VOQ */ 3746 #define QM_REG_QVOQIDX_0 0x1680f4 3747 #define QM_REG_QVOQIDX_10 0x16811c 3748 #define QM_REG_QVOQIDX_100 0x16e49c 3749 #define QM_REG_QVOQIDX_101 0x16e4a0 3750 #define QM_REG_QVOQIDX_102 0x16e4a4 3751 #define QM_REG_QVOQIDX_103 0x16e4a8 3752 #define QM_REG_QVOQIDX_104 0x16e4ac 3753 #define QM_REG_QVOQIDX_105 0x16e4b0 3754 #define QM_REG_QVOQIDX_106 0x16e4b4 3755 #define QM_REG_QVOQIDX_107 0x16e4b8 3756 #define QM_REG_QVOQIDX_108 0x16e4bc 3757 #define QM_REG_QVOQIDX_109 0x16e4c0 3758 #define QM_REG_QVOQIDX_11 0x168120 3759 #define QM_REG_QVOQIDX_110 0x16e4c4 3760 #define QM_REG_QVOQIDX_111 0x16e4c8 3761 #define QM_REG_QVOQIDX_112 0x16e4cc 3762 #define QM_REG_QVOQIDX_113 0x16e4d0 3763 #define QM_REG_QVOQIDX_114 0x16e4d4 3764 #define QM_REG_QVOQIDX_115 0x16e4d8 3765 #define QM_REG_QVOQIDX_116 0x16e4dc 3766 #define QM_REG_QVOQIDX_117 0x16e4e0 3767 #define QM_REG_QVOQIDX_118 0x16e4e4 3768 #define QM_REG_QVOQIDX_119 0x16e4e8 3769 #define QM_REG_QVOQIDX_12 0x168124 3770 #define QM_REG_QVOQIDX_120 0x16e4ec 3771 #define QM_REG_QVOQIDX_121 0x16e4f0 3772 #define QM_REG_QVOQIDX_122 0x16e4f4 3773 #define QM_REG_QVOQIDX_123 0x16e4f8 3774 #define QM_REG_QVOQIDX_124 0x16e4fc 3775 #define QM_REG_QVOQIDX_125 0x16e500 3776 #define QM_REG_QVOQIDX_126 0x16e504 3777 #define QM_REG_QVOQIDX_127 0x16e508 3778 #define QM_REG_QVOQIDX_13 0x168128 3779 #define QM_REG_QVOQIDX_14 0x16812c 3780 #define QM_REG_QVOQIDX_15 0x168130 3781 #define QM_REG_QVOQIDX_16 0x168134 3782 #define QM_REG_QVOQIDX_17 0x168138 3783 #define QM_REG_QVOQIDX_21 0x168148 3784 #define QM_REG_QVOQIDX_22 0x16814c 3785 #define QM_REG_QVOQIDX_23 0x168150 3786 #define QM_REG_QVOQIDX_24 0x168154 3787 #define QM_REG_QVOQIDX_25 0x168158 3788 #define QM_REG_QVOQIDX_26 0x16815c 3789 #define QM_REG_QVOQIDX_27 0x168160 3790 #define QM_REG_QVOQIDX_28 0x168164 3791 #define QM_REG_QVOQIDX_29 0x168168 3792 #define QM_REG_QVOQIDX_30 0x16816c 3793 #define QM_REG_QVOQIDX_31 0x168170 3794 #define QM_REG_QVOQIDX_32 0x168174 3795 #define QM_REG_QVOQIDX_33 0x168178 3796 #define QM_REG_QVOQIDX_34 0x16817c 3797 #define QM_REG_QVOQIDX_35 0x168180 3798 #define QM_REG_QVOQIDX_36 0x168184 3799 #define QM_REG_QVOQIDX_37 0x168188 3800 #define QM_REG_QVOQIDX_38 0x16818c 3801 #define QM_REG_QVOQIDX_39 0x168190 3802 #define QM_REG_QVOQIDX_40 0x168194 3803 #define QM_REG_QVOQIDX_41 0x168198 3804 #define QM_REG_QVOQIDX_42 0x16819c 3805 #define QM_REG_QVOQIDX_43 0x1681a0 3806 #define QM_REG_QVOQIDX_44 0x1681a4 3807 #define QM_REG_QVOQIDX_45 0x1681a8 3808 #define QM_REG_QVOQIDX_46 0x1681ac 3809 #define QM_REG_QVOQIDX_47 0x1681b0 3810 #define QM_REG_QVOQIDX_48 0x1681b4 3811 #define QM_REG_QVOQIDX_49 0x1681b8 3812 #define QM_REG_QVOQIDX_5 0x168108 3813 #define QM_REG_QVOQIDX_50 0x1681bc 3814 #define QM_REG_QVOQIDX_51 0x1681c0 3815 #define QM_REG_QVOQIDX_52 0x1681c4 3816 #define QM_REG_QVOQIDX_53 0x1681c8 3817 #define QM_REG_QVOQIDX_54 0x1681cc 3818 #define QM_REG_QVOQIDX_55 0x1681d0 3819 #define QM_REG_QVOQIDX_56 0x1681d4 3820 #define QM_REG_QVOQIDX_57 0x1681d8 3821 #define QM_REG_QVOQIDX_58 0x1681dc 3822 #define QM_REG_QVOQIDX_59 0x1681e0 3823 #define QM_REG_QVOQIDX_6 0x16810c 3824 #define QM_REG_QVOQIDX_60 0x1681e4 3825 #define QM_REG_QVOQIDX_61 0x1681e8 3826 #define QM_REG_QVOQIDX_62 0x1681ec 3827 #define QM_REG_QVOQIDX_63 0x1681f0 3828 #define QM_REG_QVOQIDX_64 0x16e40c 3829 #define QM_REG_QVOQIDX_65 0x16e410 3830 #define QM_REG_QVOQIDX_69 0x16e420 3831 #define QM_REG_QVOQIDX_7 0x168110 3832 #define QM_REG_QVOQIDX_70 0x16e424 3833 #define QM_REG_QVOQIDX_71 0x16e428 3834 #define QM_REG_QVOQIDX_72 0x16e42c 3835 #define QM_REG_QVOQIDX_73 0x16e430 3836 #define QM_REG_QVOQIDX_74 0x16e434 3837 #define QM_REG_QVOQIDX_75 0x16e438 3838 #define QM_REG_QVOQIDX_76 0x16e43c 3839 #define QM_REG_QVOQIDX_77 0x16e440 3840 #define QM_REG_QVOQIDX_78 0x16e444 3841 #define QM_REG_QVOQIDX_79 0x16e448 3842 #define QM_REG_QVOQIDX_8 0x168114 3843 #define QM_REG_QVOQIDX_80 0x16e44c 3844 #define QM_REG_QVOQIDX_81 0x16e450 3845 #define QM_REG_QVOQIDX_85 0x16e460 3846 #define QM_REG_QVOQIDX_86 0x16e464 3847 #define QM_REG_QVOQIDX_87 0x16e468 3848 #define QM_REG_QVOQIDX_88 0x16e46c 3849 #define QM_REG_QVOQIDX_89 0x16e470 3850 #define QM_REG_QVOQIDX_9 0x168118 3851 #define QM_REG_QVOQIDX_90 0x16e474 3852 #define QM_REG_QVOQIDX_91 0x16e478 3853 #define QM_REG_QVOQIDX_92 0x16e47c 3854 #define QM_REG_QVOQIDX_93 0x16e480 3855 #define QM_REG_QVOQIDX_94 0x16e484 3856 #define QM_REG_QVOQIDX_95 0x16e488 3857 #define QM_REG_QVOQIDX_96 0x16e48c 3858 #define QM_REG_QVOQIDX_97 0x16e490 3859 #define QM_REG_QVOQIDX_98 0x16e494 3860 #define QM_REG_QVOQIDX_99 0x16e498 3861 /* [RW 1] Initialization bit command */ 3862 #define QM_REG_SOFT_RESET 0x168428 3863 /* [RW 8] The credit cost per every task in the QM. A value per each VOQ */ 3864 #define QM_REG_TASKCRDCOST_0 0x16809c 3865 #define QM_REG_TASKCRDCOST_1 0x1680a0 3866 #define QM_REG_TASKCRDCOST_2 0x1680a4 3867 #define QM_REG_TASKCRDCOST_4 0x1680ac 3868 #define QM_REG_TASKCRDCOST_5 0x1680b0 3869 /* [R 6] Keep the fill level of the fifo from write client 3 */ 3870 #define QM_REG_TQM_WRC_FIFOLVL 0x168010 3871 /* [R 6] Keep the fill level of the fifo from write client 2 */ 3872 #define QM_REG_UQM_WRC_FIFOLVL 0x168008 3873 /* [RC 32] Credit update error register */ 3874 #define QM_REG_VOQCRDERRREG 0x168408 3875 /* [R 16] The credit value for each VOQ */ 3876 #define QM_REG_VOQCREDIT_0 0x1682d0 3877 #define QM_REG_VOQCREDIT_1 0x1682d4 3878 #define QM_REG_VOQCREDIT_4 0x1682e0 3879 /* [RW 16] The credit value that if above the QM is considered almost full */ 3880 #define QM_REG_VOQCREDITAFULLTHR 0x168090 3881 /* [RW 16] The init and maximum credit for each VoQ */ 3882 #define QM_REG_VOQINITCREDIT_0 0x168060 3883 #define QM_REG_VOQINITCREDIT_1 0x168064 3884 #define QM_REG_VOQINITCREDIT_2 0x168068 3885 #define QM_REG_VOQINITCREDIT_4 0x168070 3886 #define QM_REG_VOQINITCREDIT_5 0x168074 3887 /* [RW 1] The port of which VOQ belongs */ 3888 #define QM_REG_VOQPORT_0 0x1682a0 3889 #define QM_REG_VOQPORT_1 0x1682a4 3890 #define QM_REG_VOQPORT_2 0x1682a8 3891 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3892 #define QM_REG_VOQQMASK_0_LSB 0x168240 3893 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3894 #define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524 3895 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3896 #define QM_REG_VOQQMASK_0_MSB 0x168244 3897 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3898 #define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528 3899 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3900 #define QM_REG_VOQQMASK_10_LSB 0x168290 3901 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3902 #define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574 3903 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3904 #define QM_REG_VOQQMASK_10_MSB 0x168294 3905 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3906 #define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578 3907 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3908 #define QM_REG_VOQQMASK_11_LSB 0x168298 3909 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3910 #define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c 3911 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3912 #define QM_REG_VOQQMASK_11_MSB 0x16829c 3913 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3914 #define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580 3915 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3916 #define QM_REG_VOQQMASK_1_LSB 0x168248 3917 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3918 #define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c 3919 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3920 #define QM_REG_VOQQMASK_1_MSB 0x16824c 3921 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3922 #define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530 3923 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3924 #define QM_REG_VOQQMASK_2_LSB 0x168250 3925 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3926 #define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534 3927 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3928 #define QM_REG_VOQQMASK_2_MSB 0x168254 3929 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3930 #define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538 3931 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3932 #define QM_REG_VOQQMASK_3_LSB 0x168258 3933 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3934 #define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c 3935 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3936 #define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540 3937 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3938 #define QM_REG_VOQQMASK_4_LSB 0x168260 3939 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3940 #define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544 3941 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3942 #define QM_REG_VOQQMASK_4_MSB 0x168264 3943 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3944 #define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548 3945 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3946 #define QM_REG_VOQQMASK_5_LSB 0x168268 3947 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3948 #define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c 3949 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3950 #define QM_REG_VOQQMASK_5_MSB 0x16826c 3951 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3952 #define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550 3953 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3954 #define QM_REG_VOQQMASK_6_LSB 0x168270 3955 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3956 #define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554 3957 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3958 #define QM_REG_VOQQMASK_6_MSB 0x168274 3959 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3960 #define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558 3961 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3962 #define QM_REG_VOQQMASK_7_LSB 0x168278 3963 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3964 #define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c 3965 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3966 #define QM_REG_VOQQMASK_7_MSB 0x16827c 3967 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3968 #define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560 3969 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3970 #define QM_REG_VOQQMASK_8_LSB 0x168280 3971 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3972 #define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564 3973 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3974 #define QM_REG_VOQQMASK_8_MSB 0x168284 3975 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3976 #define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568 3977 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3978 #define QM_REG_VOQQMASK_9_LSB 0x168288 3979 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3980 #define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c 3981 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3982 #define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570 3983 /* [RW 32] Wrr weights */ 3984 #define QM_REG_WRRWEIGHTS_0 0x16880c 3985 #define QM_REG_WRRWEIGHTS_1 0x168810 3986 #define QM_REG_WRRWEIGHTS_10 0x168814 3987 #define QM_REG_WRRWEIGHTS_11 0x168818 3988 #define QM_REG_WRRWEIGHTS_12 0x16881c 3989 #define QM_REG_WRRWEIGHTS_13 0x168820 3990 #define QM_REG_WRRWEIGHTS_14 0x168824 3991 #define QM_REG_WRRWEIGHTS_15 0x168828 3992 #define QM_REG_WRRWEIGHTS_16 0x16e000 3993 #define QM_REG_WRRWEIGHTS_17 0x16e004 3994 #define QM_REG_WRRWEIGHTS_18 0x16e008 3995 #define QM_REG_WRRWEIGHTS_19 0x16e00c 3996 #define QM_REG_WRRWEIGHTS_2 0x16882c 3997 #define QM_REG_WRRWEIGHTS_20 0x16e010 3998 #define QM_REG_WRRWEIGHTS_21 0x16e014 3999 #define QM_REG_WRRWEIGHTS_22 0x16e018 4000 #define QM_REG_WRRWEIGHTS_23 0x16e01c 4001 #define QM_REG_WRRWEIGHTS_24 0x16e020 4002 #define QM_REG_WRRWEIGHTS_25 0x16e024 4003 #define QM_REG_WRRWEIGHTS_26 0x16e028 4004 #define QM_REG_WRRWEIGHTS_27 0x16e02c 4005 #define QM_REG_WRRWEIGHTS_28 0x16e030 4006 #define QM_REG_WRRWEIGHTS_29 0x16e034 4007 #define QM_REG_WRRWEIGHTS_3 0x168830 4008 #define QM_REG_WRRWEIGHTS_30 0x16e038 4009 #define QM_REG_WRRWEIGHTS_31 0x16e03c 4010 #define QM_REG_WRRWEIGHTS_4 0x168834 4011 #define QM_REG_WRRWEIGHTS_5 0x168838 4012 #define QM_REG_WRRWEIGHTS_6 0x16883c 4013 #define QM_REG_WRRWEIGHTS_7 0x168840 4014 #define QM_REG_WRRWEIGHTS_8 0x168844 4015 #define QM_REG_WRRWEIGHTS_9 0x168848 4016 /* [R 6] Keep the fill level of the fifo from write client 1 */ 4017 #define QM_REG_XQM_WRC_FIFOLVL 0x168000 4018 /* [W 1] reset to parity interrupt */ 4019 #define SEM_FAST_REG_PARITY_RST 0x18840 4020 #define SRC_REG_COUNTFREE0 0x40500 4021 /* [RW 1] If clr the searcher is compatible to E1 A0 - support only two 4022 ports. If set the searcher support 8 functions. */ 4023 #define SRC_REG_E1HMF_ENABLE 0x404cc 4024 #define SRC_REG_FIRSTFREE0 0x40510 4025 #define SRC_REG_KEYRSS0_0 0x40408 4026 #define SRC_REG_KEYRSS0_7 0x40424 4027 #define SRC_REG_KEYRSS1_9 0x40454 4028 #define SRC_REG_KEYSEARCH_0 0x40458 4029 #define SRC_REG_KEYSEARCH_1 0x4045c 4030 #define SRC_REG_KEYSEARCH_2 0x40460 4031 #define SRC_REG_KEYSEARCH_3 0x40464 4032 #define SRC_REG_KEYSEARCH_4 0x40468 4033 #define SRC_REG_KEYSEARCH_5 0x4046c 4034 #define SRC_REG_KEYSEARCH_6 0x40470 4035 #define SRC_REG_KEYSEARCH_7 0x40474 4036 #define SRC_REG_KEYSEARCH_8 0x40478 4037 #define SRC_REG_KEYSEARCH_9 0x4047c 4038 #define SRC_REG_LASTFREE0 0x40530 4039 #define SRC_REG_NUMBER_HASH_BITS0 0x40400 4040 /* [RW 1] Reset internal state machines. */ 4041 #define SRC_REG_SOFT_RST 0x4049c 4042 /* [R 3] Interrupt register #0 read */ 4043 #define SRC_REG_SRC_INT_STS 0x404ac 4044 /* [RW 3] Parity mask register #0 read/write */ 4045 #define SRC_REG_SRC_PRTY_MASK 0x404c8 4046 /* [R 3] Parity register #0 read */ 4047 #define SRC_REG_SRC_PRTY_STS 0x404bc 4048 /* [RC 3] Parity register #0 read clear */ 4049 #define SRC_REG_SRC_PRTY_STS_CLR 0x404c0 4050 /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */ 4051 #define TCM_REG_CAM_OCCUP 0x5017c 4052 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is 4053 disregarded; valid output is deasserted; all other signals are treated as 4054 usual; if 1 - normal activity. */ 4055 #define TCM_REG_CDU_AG_RD_IFEN 0x50034 4056 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 4057 are disregarded; all other signals are treated as usual; if 1 - normal 4058 activity. */ 4059 #define TCM_REG_CDU_AG_WR_IFEN 0x50030 4060 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 4061 disregarded; valid output is deasserted; all other signals are treated as 4062 usual; if 1 - normal activity. */ 4063 #define TCM_REG_CDU_SM_RD_IFEN 0x5003c 4064 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 4065 input is disregarded; all other signals are treated as usual; if 1 - 4066 normal activity. */ 4067 #define TCM_REG_CDU_SM_WR_IFEN 0x50038 4068 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 4069 the initial credit value; read returns the current value of the credit 4070 counter. Must be initialized to 1 at start-up. */ 4071 #define TCM_REG_CFC_INIT_CRD 0x50204 4072 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for 4073 weight 8 (the most prioritised); 1 stands for weight 1(least 4074 prioritised); 2 stands for weight 2; tc. */ 4075 #define TCM_REG_CP_WEIGHT 0x500c0 4076 /* [RW 1] Input csem Interface enable. If 0 - the valid input is 4077 disregarded; acknowledge output is deasserted; all other signals are 4078 treated as usual; if 1 - normal activity. */ 4079 #define TCM_REG_CSEM_IFEN 0x5002c 4080 /* [RC 1] Message length mismatch (relative to last indication) at the In#9 4081 interface. */ 4082 #define TCM_REG_CSEM_LENGTH_MIS 0x50174 4083 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for 4084 weight 8 (the most prioritised); 1 stands for weight 1(least 4085 prioritised); 2 stands for weight 2; tc. */ 4086 #define TCM_REG_CSEM_WEIGHT 0x500bc 4087 /* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */ 4088 #define TCM_REG_ERR_EVNT_ID 0x500a0 4089 /* [RW 28] The CM erroneous header for QM and Timers formatting. */ 4090 #define TCM_REG_ERR_TCM_HDR 0x5009c 4091 /* [RW 8] The Event ID for Timers expiration. */ 4092 #define TCM_REG_EXPR_EVNT_ID 0x500a4 4093 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write 4094 writes the initial credit value; read returns the current value of the 4095 credit counter. Must be initialized to 64 at start-up. */ 4096 #define TCM_REG_FIC0_INIT_CRD 0x5020c 4097 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 4098 writes the initial credit value; read returns the current value of the 4099 credit counter. Must be initialized to 64 at start-up. */ 4100 #define TCM_REG_FIC1_INIT_CRD 0x50210 4101 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 4102 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr; 4103 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and 4104 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */ 4105 #define TCM_REG_GR_ARB_TYPE 0x50114 4106 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 4107 highest priority is 3. It is supposed that the Store channel is the 4108 compliment of the other 3 groups. */ 4109 #define TCM_REG_GR_LD0_PR 0x5011c 4110 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 4111 highest priority is 3. It is supposed that the Store channel is the 4112 compliment of the other 3 groups. */ 4113 #define TCM_REG_GR_LD1_PR 0x50120 4114 /* [RW 4] The number of double REG-pairs; loaded from the STORM context and 4115 sent to STORM; for a specific connection type. The double REG-pairs are 4116 used to align to STORM context row size of 128 bits. The offset of these 4117 data in the STORM context is always 0. Index _i stands for the connection 4118 type (one of 16). */ 4119 #define TCM_REG_N_SM_CTX_LD_0 0x50050 4120 #define TCM_REG_N_SM_CTX_LD_1 0x50054 4121 #define TCM_REG_N_SM_CTX_LD_2 0x50058 4122 #define TCM_REG_N_SM_CTX_LD_3 0x5005c 4123 #define TCM_REG_N_SM_CTX_LD_4 0x50060 4124 #define TCM_REG_N_SM_CTX_LD_5 0x50064 4125 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; 4126 acknowledge output is deasserted; all other signals are treated as usual; 4127 if 1 - normal activity. */ 4128 #define TCM_REG_PBF_IFEN 0x50024 4129 /* [RC 1] Message length mismatch (relative to last indication) at the In#7 4130 interface. */ 4131 #define TCM_REG_PBF_LENGTH_MIS 0x5016c 4132 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for 4133 weight 8 (the most prioritised); 1 stands for weight 1(least 4134 prioritised); 2 stands for weight 2; tc. */ 4135 #define TCM_REG_PBF_WEIGHT 0x500b4 4136 #define TCM_REG_PHYS_QNUM0_0 0x500e0 4137 #define TCM_REG_PHYS_QNUM0_1 0x500e4 4138 #define TCM_REG_PHYS_QNUM1_0 0x500e8 4139 #define TCM_REG_PHYS_QNUM1_1 0x500ec 4140 #define TCM_REG_PHYS_QNUM2_0 0x500f0 4141 #define TCM_REG_PHYS_QNUM2_1 0x500f4 4142 #define TCM_REG_PHYS_QNUM3_0 0x500f8 4143 #define TCM_REG_PHYS_QNUM3_1 0x500fc 4144 /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded; 4145 acknowledge output is deasserted; all other signals are treated as usual; 4146 if 1 - normal activity. */ 4147 #define TCM_REG_PRS_IFEN 0x50020 4148 /* [RC 1] Message length mismatch (relative to last indication) at the In#6 4149 interface. */ 4150 #define TCM_REG_PRS_LENGTH_MIS 0x50168 4151 /* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for 4152 weight 8 (the most prioritised); 1 stands for weight 1(least 4153 prioritised); 2 stands for weight 2; tc. */ 4154 #define TCM_REG_PRS_WEIGHT 0x500b0 4155 /* [RW 8] The Event ID for Timers formatting in case of stop done. */ 4156 #define TCM_REG_STOP_EVNT_ID 0x500a8 4157 /* [RC 1] Message length mismatch (relative to last indication) at the STORM 4158 interface. */ 4159 #define TCM_REG_STORM_LENGTH_MIS 0x50160 4160 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 4161 disregarded; acknowledge output is deasserted; all other signals are 4162 treated as usual; if 1 - normal activity. */ 4163 #define TCM_REG_STORM_TCM_IFEN 0x50010 4164 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for 4165 weight 8 (the most prioritised); 1 stands for weight 1(least 4166 prioritised); 2 stands for weight 2; tc. */ 4167 #define TCM_REG_STORM_WEIGHT 0x500ac 4168 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 4169 acknowledge output is deasserted; all other signals are treated as usual; 4170 if 1 - normal activity. */ 4171 #define TCM_REG_TCM_CFC_IFEN 0x50040 4172 /* [RW 11] Interrupt mask register #0 read/write */ 4173 #define TCM_REG_TCM_INT_MASK 0x501dc 4174 /* [R 11] Interrupt register #0 read */ 4175 #define TCM_REG_TCM_INT_STS 0x501d0 4176 /* [RW 27] Parity mask register #0 read/write */ 4177 #define TCM_REG_TCM_PRTY_MASK 0x501ec 4178 /* [R 27] Parity register #0 read */ 4179 #define TCM_REG_TCM_PRTY_STS 0x501e0 4180 /* [RC 27] Parity register #0 read clear */ 4181 #define TCM_REG_TCM_PRTY_STS_CLR 0x501e4 4182 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS 4183 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 4184 Is used to determine the number of the AG context REG-pairs written back; 4185 when the input message Reg1WbFlg isn't set. */ 4186 #define TCM_REG_TCM_REG0_SZ 0x500d8 4187 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 4188 disregarded; valid is deasserted; all other signals are treated as usual; 4189 if 1 - normal activity. */ 4190 #define TCM_REG_TCM_STORM0_IFEN 0x50004 4191 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 4192 disregarded; valid is deasserted; all other signals are treated as usual; 4193 if 1 - normal activity. */ 4194 #define TCM_REG_TCM_STORM1_IFEN 0x50008 4195 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 4196 disregarded; valid is deasserted; all other signals are treated as usual; 4197 if 1 - normal activity. */ 4198 #define TCM_REG_TCM_TQM_IFEN 0x5000c 4199 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */ 4200 #define TCM_REG_TCM_TQM_USE_Q 0x500d4 4201 /* [RW 28] The CM header for Timers expiration command. */ 4202 #define TCM_REG_TM_TCM_HDR 0x50098 4203 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is 4204 disregarded; acknowledge output is deasserted; all other signals are 4205 treated as usual; if 1 - normal activity. */ 4206 #define TCM_REG_TM_TCM_IFEN 0x5001c 4207 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for 4208 weight 8 (the most prioritised); 1 stands for weight 1(least 4209 prioritised); 2 stands for weight 2; tc. */ 4210 #define TCM_REG_TM_WEIGHT 0x500d0 4211 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes 4212 the initial credit value; read returns the current value of the credit 4213 counter. Must be initialized to 32 at start-up. */ 4214 #define TCM_REG_TQM_INIT_CRD 0x5021c 4215 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 4216 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 4217 prioritised); 2 stands for weight 2; tc. */ 4218 #define TCM_REG_TQM_P_WEIGHT 0x500c8 4219 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 4220 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 4221 prioritised); 2 stands for weight 2; tc. */ 4222 #define TCM_REG_TQM_S_WEIGHT 0x500cc 4223 /* [RW 28] The CM header value for QM request (primary). */ 4224 #define TCM_REG_TQM_TCM_HDR_P 0x50090 4225 /* [RW 28] The CM header value for QM request (secondary). */ 4226 #define TCM_REG_TQM_TCM_HDR_S 0x50094 4227 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 4228 acknowledge output is deasserted; all other signals are treated as usual; 4229 if 1 - normal activity. */ 4230 #define TCM_REG_TQM_TCM_IFEN 0x50014 4231 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 4232 acknowledge output is deasserted; all other signals are treated as usual; 4233 if 1 - normal activity. */ 4234 #define TCM_REG_TSDM_IFEN 0x50018 4235 /* [RC 1] Message length mismatch (relative to last indication) at the SDM 4236 interface. */ 4237 #define TCM_REG_TSDM_LENGTH_MIS 0x50164 4238 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for 4239 weight 8 (the most prioritised); 1 stands for weight 1(least 4240 prioritised); 2 stands for weight 2; tc. */ 4241 #define TCM_REG_TSDM_WEIGHT 0x500c4 4242 /* [RW 1] Input usem Interface enable. If 0 - the valid input is 4243 disregarded; acknowledge output is deasserted; all other signals are 4244 treated as usual; if 1 - normal activity. */ 4245 #define TCM_REG_USEM_IFEN 0x50028 4246 /* [RC 1] Message length mismatch (relative to last indication) at the In#8 4247 interface. */ 4248 #define TCM_REG_USEM_LENGTH_MIS 0x50170 4249 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for 4250 weight 8 (the most prioritised); 1 stands for weight 1(least 4251 prioritised); 2 stands for weight 2; tc. */ 4252 #define TCM_REG_USEM_WEIGHT 0x500b8 4253 /* [RW 21] Indirect access to the descriptor table of the XX protection 4254 mechanism. The fields are: [5:0] - length of the message; 15:6] - message 4255 pointer; 20:16] - next pointer. */ 4256 #define TCM_REG_XX_DESCR_TABLE 0x50280 4257 #define TCM_REG_XX_DESCR_TABLE_SIZE 29 4258 /* [R 6] Use to read the value of XX protection Free counter. */ 4259 #define TCM_REG_XX_FREE 0x50178 4260 /* [RW 6] Initial value for the credit counter; responsible for fulfilling 4261 of the Input Stage XX protection buffer by the XX protection pending 4262 messages. Max credit available - 127.Write writes the initial credit 4263 value; read returns the current value of the credit counter. Must be 4264 initialized to 19 at start-up. */ 4265 #define TCM_REG_XX_INIT_CRD 0x50220 4266 /* [RW 6] Maximum link list size (messages locked) per connection in the XX 4267 protection. */ 4268 #define TCM_REG_XX_MAX_LL_SZ 0x50044 4269 /* [RW 6] The maximum number of pending messages; which may be stored in XX 4270 protection. ~tcm_registers_xx_free.xx_free is read on read. */ 4271 #define TCM_REG_XX_MSG_NUM 0x50224 4272 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 4273 #define TCM_REG_XX_OVFL_EVNT_ID 0x50048 4274 /* [RW 16] Indirect access to the XX table of the XX protection mechanism. 4275 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] - 4276 header pointer. */ 4277 #define TCM_REG_XX_TABLE 0x50240 4278 /* [RW 4] Load value for cfc ac credit cnt. */ 4279 #define TM_REG_CFC_AC_CRDCNT_VAL 0x164208 4280 /* [RW 4] Load value for cfc cld credit cnt. */ 4281 #define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210 4282 /* [RW 8] Client0 context region. */ 4283 #define TM_REG_CL0_CONT_REGION 0x164030 4284 /* [RW 8] Client1 context region. */ 4285 #define TM_REG_CL1_CONT_REGION 0x164034 4286 /* [RW 8] Client2 context region. */ 4287 #define TM_REG_CL2_CONT_REGION 0x164038 4288 /* [RW 2] Client in High priority client number. */ 4289 #define TM_REG_CLIN_PRIOR0_CLIENT 0x164024 4290 /* [RW 4] Load value for clout0 cred cnt. */ 4291 #define TM_REG_CLOUT_CRDCNT0_VAL 0x164220 4292 /* [RW 4] Load value for clout1 cred cnt. */ 4293 #define TM_REG_CLOUT_CRDCNT1_VAL 0x164228 4294 /* [RW 4] Load value for clout2 cred cnt. */ 4295 #define TM_REG_CLOUT_CRDCNT2_VAL 0x164230 4296 /* [RW 1] Enable client0 input. */ 4297 #define TM_REG_EN_CL0_INPUT 0x164008 4298 /* [RW 1] Enable client1 input. */ 4299 #define TM_REG_EN_CL1_INPUT 0x16400c 4300 /* [RW 1] Enable client2 input. */ 4301 #define TM_REG_EN_CL2_INPUT 0x164010 4302 #define TM_REG_EN_LINEAR0_TIMER 0x164014 4303 /* [RW 1] Enable real time counter. */ 4304 #define TM_REG_EN_REAL_TIME_CNT 0x1640d8 4305 /* [RW 1] Enable for Timers state machines. */ 4306 #define TM_REG_EN_TIMERS 0x164000 4307 /* [RW 4] Load value for expiration credit cnt. CFC max number of 4308 outstanding load requests for timers (expiration) context loading. */ 4309 #define TM_REG_EXP_CRDCNT_VAL 0x164238 4310 /* [RW 32] Linear0 logic address. */ 4311 #define TM_REG_LIN0_LOGIC_ADDR 0x164240 4312 /* [RW 18] Linear0 Max active cid (in banks of 32 entries). */ 4313 #define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048 4314 /* [ST 16] Linear0 Number of scans counter. */ 4315 #define TM_REG_LIN0_NUM_SCANS 0x1640a0 4316 /* [WB 64] Linear0 phy address. */ 4317 #define TM_REG_LIN0_PHY_ADDR 0x164270 4318 /* [RW 1] Linear0 physical address valid. */ 4319 #define TM_REG_LIN0_PHY_ADDR_VALID 0x164248 4320 #define TM_REG_LIN0_SCAN_ON 0x1640d0 4321 /* [RW 24] Linear0 array scan timeout. */ 4322 #define TM_REG_LIN0_SCAN_TIME 0x16403c 4323 #define TM_REG_LIN0_VNIC_UC 0x164128 4324 /* [RW 32] Linear1 logic address. */ 4325 #define TM_REG_LIN1_LOGIC_ADDR 0x164250 4326 /* [WB 64] Linear1 phy address. */ 4327 #define TM_REG_LIN1_PHY_ADDR 0x164280 4328 /* [RW 1] Linear1 physical address valid. */ 4329 #define TM_REG_LIN1_PHY_ADDR_VALID 0x164258 4330 /* [RW 6] Linear timer set_clear fifo threshold. */ 4331 #define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070 4332 /* [RW 2] Load value for pci arbiter credit cnt. */ 4333 #define TM_REG_PCIARB_CRDCNT_VAL 0x164260 4334 /* [RW 20] The amount of hardware cycles for each timer tick. */ 4335 #define TM_REG_TIMER_TICK_SIZE 0x16401c 4336 /* [RW 8] Timers Context region. */ 4337 #define TM_REG_TM_CONTEXT_REGION 0x164044 4338 /* [RW 1] Interrupt mask register #0 read/write */ 4339 #define TM_REG_TM_INT_MASK 0x1640fc 4340 /* [R 1] Interrupt register #0 read */ 4341 #define TM_REG_TM_INT_STS 0x1640f0 4342 /* [RW 7] Parity mask register #0 read/write */ 4343 #define TM_REG_TM_PRTY_MASK 0x16410c 4344 /* [RC 7] Parity register #0 read clear */ 4345 #define TM_REG_TM_PRTY_STS_CLR 0x164104 4346 /* [RW 8] The event id for aggregated interrupt 0 */ 4347 #define TSDM_REG_AGG_INT_EVENT_0 0x42038 4348 #define TSDM_REG_AGG_INT_EVENT_1 0x4203c 4349 #define TSDM_REG_AGG_INT_EVENT_2 0x42040 4350 #define TSDM_REG_AGG_INT_EVENT_3 0x42044 4351 #define TSDM_REG_AGG_INT_EVENT_4 0x42048 4352 /* [RW 1] The T bit for aggregated interrupt 0 */ 4353 #define TSDM_REG_AGG_INT_T_0 0x420b8 4354 #define TSDM_REG_AGG_INT_T_1 0x420bc 4355 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 4356 #define TSDM_REG_CFC_RSP_START_ADDR 0x42008 4357 /* [RW 16] The maximum value of the completion counter #0 */ 4358 #define TSDM_REG_CMP_COUNTER_MAX0 0x4201c 4359 /* [RW 16] The maximum value of the completion counter #1 */ 4360 #define TSDM_REG_CMP_COUNTER_MAX1 0x42020 4361 /* [RW 16] The maximum value of the completion counter #2 */ 4362 #define TSDM_REG_CMP_COUNTER_MAX2 0x42024 4363 /* [RW 16] The maximum value of the completion counter #3 */ 4364 #define TSDM_REG_CMP_COUNTER_MAX3 0x42028 4365 /* [RW 13] The start address in the internal RAM for the completion 4366 counters. */ 4367 #define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c 4368 #define TSDM_REG_ENABLE_IN1 0x42238 4369 #define TSDM_REG_ENABLE_IN2 0x4223c 4370 #define TSDM_REG_ENABLE_OUT1 0x42240 4371 #define TSDM_REG_ENABLE_OUT2 0x42244 4372 /* [RW 4] The initial number of messages that can be sent to the pxp control 4373 interface without receiving any ACK. */ 4374 #define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc 4375 /* [ST 32] The number of ACK after placement messages received */ 4376 #define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c 4377 /* [ST 32] The number of packet end messages received from the parser */ 4378 #define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274 4379 /* [ST 32] The number of requests received from the pxp async if */ 4380 #define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278 4381 /* [ST 32] The number of commands received in queue 0 */ 4382 #define TSDM_REG_NUM_OF_Q0_CMD 0x42248 4383 /* [ST 32] The number of commands received in queue 10 */ 4384 #define TSDM_REG_NUM_OF_Q10_CMD 0x4226c 4385 /* [ST 32] The number of commands received in queue 11 */ 4386 #define TSDM_REG_NUM_OF_Q11_CMD 0x42270 4387 /* [ST 32] The number of commands received in queue 1 */ 4388 #define TSDM_REG_NUM_OF_Q1_CMD 0x4224c 4389 /* [ST 32] The number of commands received in queue 3 */ 4390 #define TSDM_REG_NUM_OF_Q3_CMD 0x42250 4391 /* [ST 32] The number of commands received in queue 4 */ 4392 #define TSDM_REG_NUM_OF_Q4_CMD 0x42254 4393 /* [ST 32] The number of commands received in queue 5 */ 4394 #define TSDM_REG_NUM_OF_Q5_CMD 0x42258 4395 /* [ST 32] The number of commands received in queue 6 */ 4396 #define TSDM_REG_NUM_OF_Q6_CMD 0x4225c 4397 /* [ST 32] The number of commands received in queue 7 */ 4398 #define TSDM_REG_NUM_OF_Q7_CMD 0x42260 4399 /* [ST 32] The number of commands received in queue 8 */ 4400 #define TSDM_REG_NUM_OF_Q8_CMD 0x42264 4401 /* [ST 32] The number of commands received in queue 9 */ 4402 #define TSDM_REG_NUM_OF_Q9_CMD 0x42268 4403 /* [RW 13] The start address in the internal RAM for the packet end message */ 4404 #define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014 4405 /* [RW 13] The start address in the internal RAM for queue counters */ 4406 #define TSDM_REG_Q_COUNTER_START_ADDR 0x42010 4407 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 4408 #define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548 4409 /* [R 1] parser fifo empty in sdm_sync block */ 4410 #define TSDM_REG_SYNC_PARSER_EMPTY 0x42550 4411 /* [R 1] parser serial fifo empty in sdm_sync block */ 4412 #define TSDM_REG_SYNC_SYNC_EMPTY 0x42558 4413 /* [RW 32] Tick for timer counter. Applicable only when 4414 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */ 4415 #define TSDM_REG_TIMER_TICK 0x42000 4416 /* [RW 32] Interrupt mask register #0 read/write */ 4417 #define TSDM_REG_TSDM_INT_MASK_0 0x4229c 4418 #define TSDM_REG_TSDM_INT_MASK_1 0x422ac 4419 /* [R 32] Interrupt register #0 read */ 4420 #define TSDM_REG_TSDM_INT_STS_0 0x42290 4421 #define TSDM_REG_TSDM_INT_STS_1 0x422a0 4422 /* [RW 11] Parity mask register #0 read/write */ 4423 #define TSDM_REG_TSDM_PRTY_MASK 0x422bc 4424 /* [R 11] Parity register #0 read */ 4425 #define TSDM_REG_TSDM_PRTY_STS 0x422b0 4426 /* [RC 11] Parity register #0 read clear */ 4427 #define TSDM_REG_TSDM_PRTY_STS_CLR 0x422b4 4428 /* [RW 5] The number of time_slots in the arbitration cycle */ 4429 #define TSEM_REG_ARB_CYCLE_SIZE 0x180034 4430 /* [RW 3] The source that is associated with arbitration element 0. Source 4431 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4432 sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 4433 #define TSEM_REG_ARB_ELEMENT0 0x180020 4434 /* [RW 3] The source that is associated with arbitration element 1. Source 4435 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4436 sleeping thread with priority 1; 4- sleeping thread with priority 2. 4437 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */ 4438 #define TSEM_REG_ARB_ELEMENT1 0x180024 4439 /* [RW 3] The source that is associated with arbitration element 2. Source 4440 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4441 sleeping thread with priority 1; 4- sleeping thread with priority 2. 4442 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 4443 and ~tsem_registers_arb_element1.arb_element1 */ 4444 #define TSEM_REG_ARB_ELEMENT2 0x180028 4445 /* [RW 3] The source that is associated with arbitration element 3. Source 4446 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4447 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 4448 not be equal to register ~tsem_registers_arb_element0.arb_element0 and 4449 ~tsem_registers_arb_element1.arb_element1 and 4450 ~tsem_registers_arb_element2.arb_element2 */ 4451 #define TSEM_REG_ARB_ELEMENT3 0x18002c 4452 /* [RW 3] The source that is associated with arbitration element 4. Source 4453 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4454 sleeping thread with priority 1; 4- sleeping thread with priority 2. 4455 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 4456 and ~tsem_registers_arb_element1.arb_element1 and 4457 ~tsem_registers_arb_element2.arb_element2 and 4458 ~tsem_registers_arb_element3.arb_element3 */ 4459 #define TSEM_REG_ARB_ELEMENT4 0x180030 4460 #define TSEM_REG_ENABLE_IN 0x1800a4 4461 #define TSEM_REG_ENABLE_OUT 0x1800a8 4462 /* [RW 32] This address space contains all registers and memories that are 4463 placed in SEM_FAST block. The SEM_FAST registers are described in 4464 appendix B. In order to access the sem_fast registers the base address 4465 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 4466 #define TSEM_REG_FAST_MEMORY 0x1a0000 4467 /* [RW 1] Disables input messages from FIC0 May be updated during run_time 4468 by the microcode */ 4469 #define TSEM_REG_FIC0_DISABLE 0x180224 4470 /* [RW 1] Disables input messages from FIC1 May be updated during run_time 4471 by the microcode */ 4472 #define TSEM_REG_FIC1_DISABLE 0x180234 4473 /* [RW 15] Interrupt table Read and write access to it is not possible in 4474 the middle of the work */ 4475 #define TSEM_REG_INT_TABLE 0x180400 4476 /* [ST 24] Statistics register. The number of messages that entered through 4477 FIC0 */ 4478 #define TSEM_REG_MSG_NUM_FIC0 0x180000 4479 /* [ST 24] Statistics register. The number of messages that entered through 4480 FIC1 */ 4481 #define TSEM_REG_MSG_NUM_FIC1 0x180004 4482 /* [ST 24] Statistics register. The number of messages that were sent to 4483 FOC0 */ 4484 #define TSEM_REG_MSG_NUM_FOC0 0x180008 4485 /* [ST 24] Statistics register. The number of messages that were sent to 4486 FOC1 */ 4487 #define TSEM_REG_MSG_NUM_FOC1 0x18000c 4488 /* [ST 24] Statistics register. The number of messages that were sent to 4489 FOC2 */ 4490 #define TSEM_REG_MSG_NUM_FOC2 0x180010 4491 /* [ST 24] Statistics register. The number of messages that were sent to 4492 FOC3 */ 4493 #define TSEM_REG_MSG_NUM_FOC3 0x180014 4494 /* [RW 1] Disables input messages from the passive buffer May be updated 4495 during run_time by the microcode */ 4496 #define TSEM_REG_PAS_DISABLE 0x18024c 4497 /* [WB 128] Debug only. Passive buffer memory */ 4498 #define TSEM_REG_PASSIVE_BUFFER 0x181000 4499 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 4500 #define TSEM_REG_PRAM 0x1c0000 4501 /* [R 8] Valid sleeping threads indication have bit per thread */ 4502 #define TSEM_REG_SLEEP_THREADS_VALID 0x18026c 4503 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 4504 #define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0 4505 /* [RW 8] List of free threads . There is a bit per thread. */ 4506 #define TSEM_REG_THREADS_LIST 0x1802e4 4507 /* [RC 32] Parity register #0 read clear */ 4508 #define TSEM_REG_TSEM_PRTY_STS_CLR_0 0x180118 4509 #define TSEM_REG_TSEM_PRTY_STS_CLR_1 0x180128 4510 /* [RW 3] The arbitration scheme of time_slot 0 */ 4511 #define TSEM_REG_TS_0_AS 0x180038 4512 /* [RW 3] The arbitration scheme of time_slot 10 */ 4513 #define TSEM_REG_TS_10_AS 0x180060 4514 /* [RW 3] The arbitration scheme of time_slot 11 */ 4515 #define TSEM_REG_TS_11_AS 0x180064 4516 /* [RW 3] The arbitration scheme of time_slot 12 */ 4517 #define TSEM_REG_TS_12_AS 0x180068 4518 /* [RW 3] The arbitration scheme of time_slot 13 */ 4519 #define TSEM_REG_TS_13_AS 0x18006c 4520 /* [RW 3] The arbitration scheme of time_slot 14 */ 4521 #define TSEM_REG_TS_14_AS 0x180070 4522 /* [RW 3] The arbitration scheme of time_slot 15 */ 4523 #define TSEM_REG_TS_15_AS 0x180074 4524 /* [RW 3] The arbitration scheme of time_slot 16 */ 4525 #define TSEM_REG_TS_16_AS 0x180078 4526 /* [RW 3] The arbitration scheme of time_slot 17 */ 4527 #define TSEM_REG_TS_17_AS 0x18007c 4528 /* [RW 3] The arbitration scheme of time_slot 18 */ 4529 #define TSEM_REG_TS_18_AS 0x180080 4530 /* [RW 3] The arbitration scheme of time_slot 1 */ 4531 #define TSEM_REG_TS_1_AS 0x18003c 4532 /* [RW 3] The arbitration scheme of time_slot 2 */ 4533 #define TSEM_REG_TS_2_AS 0x180040 4534 /* [RW 3] The arbitration scheme of time_slot 3 */ 4535 #define TSEM_REG_TS_3_AS 0x180044 4536 /* [RW 3] The arbitration scheme of time_slot 4 */ 4537 #define TSEM_REG_TS_4_AS 0x180048 4538 /* [RW 3] The arbitration scheme of time_slot 5 */ 4539 #define TSEM_REG_TS_5_AS 0x18004c 4540 /* [RW 3] The arbitration scheme of time_slot 6 */ 4541 #define TSEM_REG_TS_6_AS 0x180050 4542 /* [RW 3] The arbitration scheme of time_slot 7 */ 4543 #define TSEM_REG_TS_7_AS 0x180054 4544 /* [RW 3] The arbitration scheme of time_slot 8 */ 4545 #define TSEM_REG_TS_8_AS 0x180058 4546 /* [RW 3] The arbitration scheme of time_slot 9 */ 4547 #define TSEM_REG_TS_9_AS 0x18005c 4548 /* [RW 32] Interrupt mask register #0 read/write */ 4549 #define TSEM_REG_TSEM_INT_MASK_0 0x180100 4550 #define TSEM_REG_TSEM_INT_MASK_1 0x180110 4551 /* [R 32] Interrupt register #0 read */ 4552 #define TSEM_REG_TSEM_INT_STS_0 0x1800f4 4553 #define TSEM_REG_TSEM_INT_STS_1 0x180104 4554 /* [RW 32] Parity mask register #0 read/write */ 4555 #define TSEM_REG_TSEM_PRTY_MASK_0 0x180120 4556 #define TSEM_REG_TSEM_PRTY_MASK_1 0x180130 4557 /* [R 32] Parity register #0 read */ 4558 #define TSEM_REG_TSEM_PRTY_STS_0 0x180114 4559 #define TSEM_REG_TSEM_PRTY_STS_1 0x180124 4560 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 4561 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ 4562 #define TSEM_REG_VFPF_ERR_NUM 0x180380 4563 /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits 4564 * [10:8] of the address should be the offset within the accessed LCID 4565 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10 4566 * LCID100. The RBC address should be 12'ha64. */ 4567 #define UCM_REG_AG_CTX 0xe2000 4568 /* [R 5] Used to read the XX protection CAM occupancy counter. */ 4569 #define UCM_REG_CAM_OCCUP 0xe0170 4570 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is 4571 disregarded; valid output is deasserted; all other signals are treated as 4572 usual; if 1 - normal activity. */ 4573 #define UCM_REG_CDU_AG_RD_IFEN 0xe0038 4574 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 4575 are disregarded; all other signals are treated as usual; if 1 - normal 4576 activity. */ 4577 #define UCM_REG_CDU_AG_WR_IFEN 0xe0034 4578 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 4579 disregarded; valid output is deasserted; all other signals are treated as 4580 usual; if 1 - normal activity. */ 4581 #define UCM_REG_CDU_SM_RD_IFEN 0xe0040 4582 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 4583 input is disregarded; all other signals are treated as usual; if 1 - 4584 normal activity. */ 4585 #define UCM_REG_CDU_SM_WR_IFEN 0xe003c 4586 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 4587 the initial credit value; read returns the current value of the credit 4588 counter. Must be initialized to 1 at start-up. */ 4589 #define UCM_REG_CFC_INIT_CRD 0xe0204 4590 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for 4591 weight 8 (the most prioritised); 1 stands for weight 1(least 4592 prioritised); 2 stands for weight 2; tc. */ 4593 #define UCM_REG_CP_WEIGHT 0xe00c4 4594 /* [RW 1] Input csem Interface enable. If 0 - the valid input is 4595 disregarded; acknowledge output is deasserted; all other signals are 4596 treated as usual; if 1 - normal activity. */ 4597 #define UCM_REG_CSEM_IFEN 0xe0028 4598 /* [RC 1] Set when the message length mismatch (relative to last indication) 4599 at the csem interface is detected. */ 4600 #define UCM_REG_CSEM_LENGTH_MIS 0xe0160 4601 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for 4602 weight 8 (the most prioritised); 1 stands for weight 1(least 4603 prioritised); 2 stands for weight 2; tc. */ 4604 #define UCM_REG_CSEM_WEIGHT 0xe00b8 4605 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is 4606 disregarded; acknowledge output is deasserted; all other signals are 4607 treated as usual; if 1 - normal activity. */ 4608 #define UCM_REG_DORQ_IFEN 0xe0030 4609 /* [RC 1] Set when the message length mismatch (relative to last indication) 4610 at the dorq interface is detected. */ 4611 #define UCM_REG_DORQ_LENGTH_MIS 0xe0168 4612 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for 4613 weight 8 (the most prioritised); 1 stands for weight 1(least 4614 prioritised); 2 stands for weight 2; tc. */ 4615 #define UCM_REG_DORQ_WEIGHT 0xe00c0 4616 /* [RW 8] The Event ID in case ErrorFlg input message bit is set. */ 4617 #define UCM_REG_ERR_EVNT_ID 0xe00a4 4618 /* [RW 28] The CM erroneous header for QM and Timers formatting. */ 4619 #define UCM_REG_ERR_UCM_HDR 0xe00a0 4620 /* [RW 8] The Event ID for Timers expiration. */ 4621 #define UCM_REG_EXPR_EVNT_ID 0xe00a8 4622 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write 4623 writes the initial credit value; read returns the current value of the 4624 credit counter. Must be initialized to 64 at start-up. */ 4625 #define UCM_REG_FIC0_INIT_CRD 0xe020c 4626 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 4627 writes the initial credit value; read returns the current value of the 4628 credit counter. Must be initialized to 64 at start-up. */ 4629 #define UCM_REG_FIC1_INIT_CRD 0xe0210 4630 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 4631 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr; 4632 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and 4633 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */ 4634 #define UCM_REG_GR_ARB_TYPE 0xe0144 4635 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 4636 highest priority is 3. It is supposed that the Store channel group is 4637 compliment to the others. */ 4638 #define UCM_REG_GR_LD0_PR 0xe014c 4639 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 4640 highest priority is 3. It is supposed that the Store channel group is 4641 compliment to the others. */ 4642 #define UCM_REG_GR_LD1_PR 0xe0150 4643 /* [RW 2] The queue index for invalidate counter flag decision. */ 4644 #define UCM_REG_INV_CFLG_Q 0xe00e4 4645 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and 4646 sent to STORM; for a specific connection type. the double REG-pairs are 4647 used in order to align to STORM context row size of 128 bits. The offset 4648 of these data in the STORM context is always 0. Index _i stands for the 4649 connection type (one of 16). */ 4650 #define UCM_REG_N_SM_CTX_LD_0 0xe0054 4651 #define UCM_REG_N_SM_CTX_LD_1 0xe0058 4652 #define UCM_REG_N_SM_CTX_LD_2 0xe005c 4653 #define UCM_REG_N_SM_CTX_LD_3 0xe0060 4654 #define UCM_REG_N_SM_CTX_LD_4 0xe0064 4655 #define UCM_REG_N_SM_CTX_LD_5 0xe0068 4656 #define UCM_REG_PHYS_QNUM0_0 0xe0110 4657 #define UCM_REG_PHYS_QNUM0_1 0xe0114 4658 #define UCM_REG_PHYS_QNUM1_0 0xe0118 4659 #define UCM_REG_PHYS_QNUM1_1 0xe011c 4660 #define UCM_REG_PHYS_QNUM2_0 0xe0120 4661 #define UCM_REG_PHYS_QNUM2_1 0xe0124 4662 #define UCM_REG_PHYS_QNUM3_0 0xe0128 4663 #define UCM_REG_PHYS_QNUM3_1 0xe012c 4664 /* [RW 8] The Event ID for Timers formatting in case of stop done. */ 4665 #define UCM_REG_STOP_EVNT_ID 0xe00ac 4666 /* [RC 1] Set when the message length mismatch (relative to last indication) 4667 at the STORM interface is detected. */ 4668 #define UCM_REG_STORM_LENGTH_MIS 0xe0154 4669 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 4670 disregarded; acknowledge output is deasserted; all other signals are 4671 treated as usual; if 1 - normal activity. */ 4672 #define UCM_REG_STORM_UCM_IFEN 0xe0010 4673 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for 4674 weight 8 (the most prioritised); 1 stands for weight 1(least 4675 prioritised); 2 stands for weight 2; tc. */ 4676 #define UCM_REG_STORM_WEIGHT 0xe00b0 4677 /* [RW 4] Timers output initial credit. Max credit available - 15.Write 4678 writes the initial credit value; read returns the current value of the 4679 credit counter. Must be initialized to 4 at start-up. */ 4680 #define UCM_REG_TM_INIT_CRD 0xe021c 4681 /* [RW 28] The CM header for Timers expiration command. */ 4682 #define UCM_REG_TM_UCM_HDR 0xe009c 4683 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is 4684 disregarded; acknowledge output is deasserted; all other signals are 4685 treated as usual; if 1 - normal activity. */ 4686 #define UCM_REG_TM_UCM_IFEN 0xe001c 4687 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for 4688 weight 8 (the most prioritised); 1 stands for weight 1(least 4689 prioritised); 2 stands for weight 2; tc. */ 4690 #define UCM_REG_TM_WEIGHT 0xe00d4 4691 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is 4692 disregarded; acknowledge output is deasserted; all other signals are 4693 treated as usual; if 1 - normal activity. */ 4694 #define UCM_REG_TSEM_IFEN 0xe0024 4695 /* [RC 1] Set when the message length mismatch (relative to last indication) 4696 at the tsem interface is detected. */ 4697 #define UCM_REG_TSEM_LENGTH_MIS 0xe015c 4698 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for 4699 weight 8 (the most prioritised); 1 stands for weight 1(least 4700 prioritised); 2 stands for weight 2; tc. */ 4701 #define UCM_REG_TSEM_WEIGHT 0xe00b4 4702 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 4703 acknowledge output is deasserted; all other signals are treated as usual; 4704 if 1 - normal activity. */ 4705 #define UCM_REG_UCM_CFC_IFEN 0xe0044 4706 /* [RW 11] Interrupt mask register #0 read/write */ 4707 #define UCM_REG_UCM_INT_MASK 0xe01d4 4708 /* [R 11] Interrupt register #0 read */ 4709 #define UCM_REG_UCM_INT_STS 0xe01c8 4710 /* [RW 27] Parity mask register #0 read/write */ 4711 #define UCM_REG_UCM_PRTY_MASK 0xe01e4 4712 /* [R 27] Parity register #0 read */ 4713 #define UCM_REG_UCM_PRTY_STS 0xe01d8 4714 /* [RC 27] Parity register #0 read clear */ 4715 #define UCM_REG_UCM_PRTY_STS_CLR 0xe01dc 4716 /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS 4717 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 4718 Is used to determine the number of the AG context REG-pairs written back; 4719 when the Reg1WbFlg isn't set. */ 4720 #define UCM_REG_UCM_REG0_SZ 0xe00dc 4721 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 4722 disregarded; valid is deasserted; all other signals are treated as usual; 4723 if 1 - normal activity. */ 4724 #define UCM_REG_UCM_STORM0_IFEN 0xe0004 4725 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 4726 disregarded; valid is deasserted; all other signals are treated as usual; 4727 if 1 - normal activity. */ 4728 #define UCM_REG_UCM_STORM1_IFEN 0xe0008 4729 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is 4730 disregarded; acknowledge output is deasserted; all other signals are 4731 treated as usual; if 1 - normal activity. */ 4732 #define UCM_REG_UCM_TM_IFEN 0xe0020 4733 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 4734 disregarded; valid is deasserted; all other signals are treated as usual; 4735 if 1 - normal activity. */ 4736 #define UCM_REG_UCM_UQM_IFEN 0xe000c 4737 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */ 4738 #define UCM_REG_UCM_UQM_USE_Q 0xe00d8 4739 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes 4740 the initial credit value; read returns the current value of the credit 4741 counter. Must be initialized to 32 at start-up. */ 4742 #define UCM_REG_UQM_INIT_CRD 0xe0220 4743 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 4744 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 4745 prioritised); 2 stands for weight 2; tc. */ 4746 #define UCM_REG_UQM_P_WEIGHT 0xe00cc 4747 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 4748 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 4749 prioritised); 2 stands for weight 2; tc. */ 4750 #define UCM_REG_UQM_S_WEIGHT 0xe00d0 4751 /* [RW 28] The CM header value for QM request (primary). */ 4752 #define UCM_REG_UQM_UCM_HDR_P 0xe0094 4753 /* [RW 28] The CM header value for QM request (secondary). */ 4754 #define UCM_REG_UQM_UCM_HDR_S 0xe0098 4755 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 4756 acknowledge output is deasserted; all other signals are treated as usual; 4757 if 1 - normal activity. */ 4758 #define UCM_REG_UQM_UCM_IFEN 0xe0014 4759 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 4760 acknowledge output is deasserted; all other signals are treated as usual; 4761 if 1 - normal activity. */ 4762 #define UCM_REG_USDM_IFEN 0xe0018 4763 /* [RC 1] Set when the message length mismatch (relative to last indication) 4764 at the SDM interface is detected. */ 4765 #define UCM_REG_USDM_LENGTH_MIS 0xe0158 4766 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for 4767 weight 8 (the most prioritised); 1 stands for weight 1(least 4768 prioritised); 2 stands for weight 2; tc. */ 4769 #define UCM_REG_USDM_WEIGHT 0xe00c8 4770 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is 4771 disregarded; acknowledge output is deasserted; all other signals are 4772 treated as usual; if 1 - normal activity. */ 4773 #define UCM_REG_XSEM_IFEN 0xe002c 4774 /* [RC 1] Set when the message length mismatch (relative to last indication) 4775 at the xsem interface isdetected. */ 4776 #define UCM_REG_XSEM_LENGTH_MIS 0xe0164 4777 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for 4778 weight 8 (the most prioritised); 1 stands for weight 1(least 4779 prioritised); 2 stands for weight 2; tc. */ 4780 #define UCM_REG_XSEM_WEIGHT 0xe00bc 4781 /* [RW 20] Indirect access to the descriptor table of the XX protection 4782 mechanism. The fields are:[5:0] - message length; 14:6] - message 4783 pointer; 19:15] - next pointer. */ 4784 #define UCM_REG_XX_DESCR_TABLE 0xe0280 4785 #define UCM_REG_XX_DESCR_TABLE_SIZE 27 4786 /* [R 6] Use to read the XX protection Free counter. */ 4787 #define UCM_REG_XX_FREE 0xe016c 4788 /* [RW 6] Initial value for the credit counter; responsible for fulfilling 4789 of the Input Stage XX protection buffer by the XX protection pending 4790 messages. Write writes the initial credit value; read returns the current 4791 value of the credit counter. Must be initialized to 12 at start-up. */ 4792 #define UCM_REG_XX_INIT_CRD 0xe0224 4793 /* [RW 6] The maximum number of pending messages; which may be stored in XX 4794 protection. ~ucm_registers_xx_free.xx_free read on read. */ 4795 #define UCM_REG_XX_MSG_NUM 0xe0228 4796 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 4797 #define UCM_REG_XX_OVFL_EVNT_ID 0xe004c 4798 /* [RW 16] Indirect access to the XX table of the XX protection mechanism. 4799 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] - 4800 header pointer. */ 4801 #define UCM_REG_XX_TABLE 0xe0300 4802 #define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE (0x1<<28) 4803 #define UMAC_COMMAND_CONFIG_REG_LOOP_ENA (0x1<<15) 4804 #define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK (0x1<<24) 4805 #define UMAC_COMMAND_CONFIG_REG_PAD_EN (0x1<<5) 4806 #define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE (0x1<<8) 4807 #define UMAC_COMMAND_CONFIG_REG_PROMIS_EN (0x1<<4) 4808 #define UMAC_COMMAND_CONFIG_REG_RX_ENA (0x1<<1) 4809 #define UMAC_COMMAND_CONFIG_REG_SW_RESET (0x1<<13) 4810 #define UMAC_COMMAND_CONFIG_REG_TX_ENA (0x1<<0) 4811 #define UMAC_REG_COMMAND_CONFIG 0x8 4812 /* [RW 32] Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refers 4813 * to bit 17 of the MAC address etc. */ 4814 #define UMAC_REG_MAC_ADDR0 0xc 4815 /* [RW 16] Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 1 4816 * refers to Bit 1 of the MAC address etc. Bits 16 to 31 are reserved. */ 4817 #define UMAC_REG_MAC_ADDR1 0x10 4818 /* [RW 14] Defines a 14-Bit maximum frame length used by the MAC receive 4819 * logic to check frames. */ 4820 #define UMAC_REG_MAXFR 0x14 4821 /* [RW 8] The event id for aggregated interrupt 0 */ 4822 #define USDM_REG_AGG_INT_EVENT_0 0xc4038 4823 #define USDM_REG_AGG_INT_EVENT_1 0xc403c 4824 #define USDM_REG_AGG_INT_EVENT_2 0xc4040 4825 #define USDM_REG_AGG_INT_EVENT_4 0xc4048 4826 #define USDM_REG_AGG_INT_EVENT_5 0xc404c 4827 #define USDM_REG_AGG_INT_EVENT_6 0xc4050 4828 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0) 4829 or auto-mask-mode (1) */ 4830 #define USDM_REG_AGG_INT_MODE_0 0xc41b8 4831 #define USDM_REG_AGG_INT_MODE_1 0xc41bc 4832 #define USDM_REG_AGG_INT_MODE_4 0xc41c8 4833 #define USDM_REG_AGG_INT_MODE_5 0xc41cc 4834 #define USDM_REG_AGG_INT_MODE_6 0xc41d0 4835 /* [RW 1] The T bit for aggregated interrupt 5 */ 4836 #define USDM_REG_AGG_INT_T_5 0xc40cc 4837 #define USDM_REG_AGG_INT_T_6 0xc40d0 4838 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 4839 #define USDM_REG_CFC_RSP_START_ADDR 0xc4008 4840 /* [RW 16] The maximum value of the completion counter #0 */ 4841 #define USDM_REG_CMP_COUNTER_MAX0 0xc401c 4842 /* [RW 16] The maximum value of the completion counter #1 */ 4843 #define USDM_REG_CMP_COUNTER_MAX1 0xc4020 4844 /* [RW 16] The maximum value of the completion counter #2 */ 4845 #define USDM_REG_CMP_COUNTER_MAX2 0xc4024 4846 /* [RW 16] The maximum value of the completion counter #3 */ 4847 #define USDM_REG_CMP_COUNTER_MAX3 0xc4028 4848 /* [RW 13] The start address in the internal RAM for the completion 4849 counters. */ 4850 #define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c 4851 #define USDM_REG_ENABLE_IN1 0xc4238 4852 #define USDM_REG_ENABLE_IN2 0xc423c 4853 #define USDM_REG_ENABLE_OUT1 0xc4240 4854 #define USDM_REG_ENABLE_OUT2 0xc4244 4855 /* [RW 4] The initial number of messages that can be sent to the pxp control 4856 interface without receiving any ACK. */ 4857 #define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0 4858 /* [ST 32] The number of ACK after placement messages received */ 4859 #define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280 4860 /* [ST 32] The number of packet end messages received from the parser */ 4861 #define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278 4862 /* [ST 32] The number of requests received from the pxp async if */ 4863 #define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c 4864 /* [ST 32] The number of commands received in queue 0 */ 4865 #define USDM_REG_NUM_OF_Q0_CMD 0xc4248 4866 /* [ST 32] The number of commands received in queue 10 */ 4867 #define USDM_REG_NUM_OF_Q10_CMD 0xc4270 4868 /* [ST 32] The number of commands received in queue 11 */ 4869 #define USDM_REG_NUM_OF_Q11_CMD 0xc4274 4870 /* [ST 32] The number of commands received in queue 1 */ 4871 #define USDM_REG_NUM_OF_Q1_CMD 0xc424c 4872 /* [ST 32] The number of commands received in queue 2 */ 4873 #define USDM_REG_NUM_OF_Q2_CMD 0xc4250 4874 /* [ST 32] The number of commands received in queue 3 */ 4875 #define USDM_REG_NUM_OF_Q3_CMD 0xc4254 4876 /* [ST 32] The number of commands received in queue 4 */ 4877 #define USDM_REG_NUM_OF_Q4_CMD 0xc4258 4878 /* [ST 32] The number of commands received in queue 5 */ 4879 #define USDM_REG_NUM_OF_Q5_CMD 0xc425c 4880 /* [ST 32] The number of commands received in queue 6 */ 4881 #define USDM_REG_NUM_OF_Q6_CMD 0xc4260 4882 /* [ST 32] The number of commands received in queue 7 */ 4883 #define USDM_REG_NUM_OF_Q7_CMD 0xc4264 4884 /* [ST 32] The number of commands received in queue 8 */ 4885 #define USDM_REG_NUM_OF_Q8_CMD 0xc4268 4886 /* [ST 32] The number of commands received in queue 9 */ 4887 #define USDM_REG_NUM_OF_Q9_CMD 0xc426c 4888 /* [RW 13] The start address in the internal RAM for the packet end message */ 4889 #define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014 4890 /* [RW 13] The start address in the internal RAM for queue counters */ 4891 #define USDM_REG_Q_COUNTER_START_ADDR 0xc4010 4892 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 4893 #define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550 4894 /* [R 1] parser fifo empty in sdm_sync block */ 4895 #define USDM_REG_SYNC_PARSER_EMPTY 0xc4558 4896 /* [R 1] parser serial fifo empty in sdm_sync block */ 4897 #define USDM_REG_SYNC_SYNC_EMPTY 0xc4560 4898 /* [RW 32] Tick for timer counter. Applicable only when 4899 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */ 4900 #define USDM_REG_TIMER_TICK 0xc4000 4901 /* [RW 32] Interrupt mask register #0 read/write */ 4902 #define USDM_REG_USDM_INT_MASK_0 0xc42a0 4903 #define USDM_REG_USDM_INT_MASK_1 0xc42b0 4904 /* [R 32] Interrupt register #0 read */ 4905 #define USDM_REG_USDM_INT_STS_0 0xc4294 4906 #define USDM_REG_USDM_INT_STS_1 0xc42a4 4907 /* [RW 11] Parity mask register #0 read/write */ 4908 #define USDM_REG_USDM_PRTY_MASK 0xc42c0 4909 /* [R 11] Parity register #0 read */ 4910 #define USDM_REG_USDM_PRTY_STS 0xc42b4 4911 /* [RC 11] Parity register #0 read clear */ 4912 #define USDM_REG_USDM_PRTY_STS_CLR 0xc42b8 4913 /* [RW 5] The number of time_slots in the arbitration cycle */ 4914 #define USEM_REG_ARB_CYCLE_SIZE 0x300034 4915 /* [RW 3] The source that is associated with arbitration element 0. Source 4916 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4917 sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 4918 #define USEM_REG_ARB_ELEMENT0 0x300020 4919 /* [RW 3] The source that is associated with arbitration element 1. Source 4920 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4921 sleeping thread with priority 1; 4- sleeping thread with priority 2. 4922 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */ 4923 #define USEM_REG_ARB_ELEMENT1 0x300024 4924 /* [RW 3] The source that is associated with arbitration element 2. Source 4925 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4926 sleeping thread with priority 1; 4- sleeping thread with priority 2. 4927 Could not be equal to register ~usem_registers_arb_element0.arb_element0 4928 and ~usem_registers_arb_element1.arb_element1 */ 4929 #define USEM_REG_ARB_ELEMENT2 0x300028 4930 /* [RW 3] The source that is associated with arbitration element 3. Source 4931 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4932 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 4933 not be equal to register ~usem_registers_arb_element0.arb_element0 and 4934 ~usem_registers_arb_element1.arb_element1 and 4935 ~usem_registers_arb_element2.arb_element2 */ 4936 #define USEM_REG_ARB_ELEMENT3 0x30002c 4937 /* [RW 3] The source that is associated with arbitration element 4. Source 4938 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4939 sleeping thread with priority 1; 4- sleeping thread with priority 2. 4940 Could not be equal to register ~usem_registers_arb_element0.arb_element0 4941 and ~usem_registers_arb_element1.arb_element1 and 4942 ~usem_registers_arb_element2.arb_element2 and 4943 ~usem_registers_arb_element3.arb_element3 */ 4944 #define USEM_REG_ARB_ELEMENT4 0x300030 4945 #define USEM_REG_ENABLE_IN 0x3000a4 4946 #define USEM_REG_ENABLE_OUT 0x3000a8 4947 /* [RW 32] This address space contains all registers and memories that are 4948 placed in SEM_FAST block. The SEM_FAST registers are described in 4949 appendix B. In order to access the sem_fast registers the base address 4950 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 4951 #define USEM_REG_FAST_MEMORY 0x320000 4952 /* [RW 1] Disables input messages from FIC0 May be updated during run_time 4953 by the microcode */ 4954 #define USEM_REG_FIC0_DISABLE 0x300224 4955 /* [RW 1] Disables input messages from FIC1 May be updated during run_time 4956 by the microcode */ 4957 #define USEM_REG_FIC1_DISABLE 0x300234 4958 /* [RW 15] Interrupt table Read and write access to it is not possible in 4959 the middle of the work */ 4960 #define USEM_REG_INT_TABLE 0x300400 4961 /* [ST 24] Statistics register. The number of messages that entered through 4962 FIC0 */ 4963 #define USEM_REG_MSG_NUM_FIC0 0x300000 4964 /* [ST 24] Statistics register. The number of messages that entered through 4965 FIC1 */ 4966 #define USEM_REG_MSG_NUM_FIC1 0x300004 4967 /* [ST 24] Statistics register. The number of messages that were sent to 4968 FOC0 */ 4969 #define USEM_REG_MSG_NUM_FOC0 0x300008 4970 /* [ST 24] Statistics register. The number of messages that were sent to 4971 FOC1 */ 4972 #define USEM_REG_MSG_NUM_FOC1 0x30000c 4973 /* [ST 24] Statistics register. The number of messages that were sent to 4974 FOC2 */ 4975 #define USEM_REG_MSG_NUM_FOC2 0x300010 4976 /* [ST 24] Statistics register. The number of messages that were sent to 4977 FOC3 */ 4978 #define USEM_REG_MSG_NUM_FOC3 0x300014 4979 /* [RW 1] Disables input messages from the passive buffer May be updated 4980 during run_time by the microcode */ 4981 #define USEM_REG_PAS_DISABLE 0x30024c 4982 /* [WB 128] Debug only. Passive buffer memory */ 4983 #define USEM_REG_PASSIVE_BUFFER 0x302000 4984 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 4985 #define USEM_REG_PRAM 0x340000 4986 /* [R 16] Valid sleeping threads indication have bit per thread */ 4987 #define USEM_REG_SLEEP_THREADS_VALID 0x30026c 4988 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 4989 #define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0 4990 /* [RW 16] List of free threads . There is a bit per thread. */ 4991 #define USEM_REG_THREADS_LIST 0x3002e4 4992 /* [RW 3] The arbitration scheme of time_slot 0 */ 4993 #define USEM_REG_TS_0_AS 0x300038 4994 /* [RW 3] The arbitration scheme of time_slot 10 */ 4995 #define USEM_REG_TS_10_AS 0x300060 4996 /* [RW 3] The arbitration scheme of time_slot 11 */ 4997 #define USEM_REG_TS_11_AS 0x300064 4998 /* [RW 3] The arbitration scheme of time_slot 12 */ 4999 #define USEM_REG_TS_12_AS 0x300068 5000 /* [RW 3] The arbitration scheme of time_slot 13 */ 5001 #define USEM_REG_TS_13_AS 0x30006c 5002 /* [RW 3] The arbitration scheme of time_slot 14 */ 5003 #define USEM_REG_TS_14_AS 0x300070 5004 /* [RW 3] The arbitration scheme of time_slot 15 */ 5005 #define USEM_REG_TS_15_AS 0x300074 5006 /* [RW 3] The arbitration scheme of time_slot 16 */ 5007 #define USEM_REG_TS_16_AS 0x300078 5008 /* [RW 3] The arbitration scheme of time_slot 17 */ 5009 #define USEM_REG_TS_17_AS 0x30007c 5010 /* [RW 3] The arbitration scheme of time_slot 18 */ 5011 #define USEM_REG_TS_18_AS 0x300080 5012 /* [RW 3] The arbitration scheme of time_slot 1 */ 5013 #define USEM_REG_TS_1_AS 0x30003c 5014 /* [RW 3] The arbitration scheme of time_slot 2 */ 5015 #define USEM_REG_TS_2_AS 0x300040 5016 /* [RW 3] The arbitration scheme of time_slot 3 */ 5017 #define USEM_REG_TS_3_AS 0x300044 5018 /* [RW 3] The arbitration scheme of time_slot 4 */ 5019 #define USEM_REG_TS_4_AS 0x300048 5020 /* [RW 3] The arbitration scheme of time_slot 5 */ 5021 #define USEM_REG_TS_5_AS 0x30004c 5022 /* [RW 3] The arbitration scheme of time_slot 6 */ 5023 #define USEM_REG_TS_6_AS 0x300050 5024 /* [RW 3] The arbitration scheme of time_slot 7 */ 5025 #define USEM_REG_TS_7_AS 0x300054 5026 /* [RW 3] The arbitration scheme of time_slot 8 */ 5027 #define USEM_REG_TS_8_AS 0x300058 5028 /* [RW 3] The arbitration scheme of time_slot 9 */ 5029 #define USEM_REG_TS_9_AS 0x30005c 5030 /* [RW 32] Interrupt mask register #0 read/write */ 5031 #define USEM_REG_USEM_INT_MASK_0 0x300110 5032 #define USEM_REG_USEM_INT_MASK_1 0x300120 5033 /* [R 32] Interrupt register #0 read */ 5034 #define USEM_REG_USEM_INT_STS_0 0x300104 5035 #define USEM_REG_USEM_INT_STS_1 0x300114 5036 /* [RW 32] Parity mask register #0 read/write */ 5037 #define USEM_REG_USEM_PRTY_MASK_0 0x300130 5038 #define USEM_REG_USEM_PRTY_MASK_1 0x300140 5039 /* [R 32] Parity register #0 read */ 5040 #define USEM_REG_USEM_PRTY_STS_0 0x300124 5041 #define USEM_REG_USEM_PRTY_STS_1 0x300134 5042 /* [RC 32] Parity register #0 read clear */ 5043 #define USEM_REG_USEM_PRTY_STS_CLR_0 0x300128 5044 #define USEM_REG_USEM_PRTY_STS_CLR_1 0x300138 5045 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 5046 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ 5047 #define USEM_REG_VFPF_ERR_NUM 0x300380 5048 #define VFC_MEMORIES_RST_REG_CAM_RST (0x1<<0) 5049 #define VFC_MEMORIES_RST_REG_RAM_RST (0x1<<1) 5050 #define VFC_REG_MEMORIES_RST 0x1943c 5051 /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits 5052 * [12:8] of the address should be the offset within the accessed LCID 5053 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10 5054 * LCID100. The RBC address should be 13'ha64. */ 5055 #define XCM_REG_AG_CTX 0x28000 5056 /* [RW 2] The queue index for registration on Aux1 counter flag. */ 5057 #define XCM_REG_AUX1_Q 0x20134 5058 /* [RW 2] Per each decision rule the queue index to register to. */ 5059 #define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0 5060 /* [R 5] Used to read the XX protection CAM occupancy counter. */ 5061 #define XCM_REG_CAM_OCCUP 0x20244 5062 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is 5063 disregarded; valid output is deasserted; all other signals are treated as 5064 usual; if 1 - normal activity. */ 5065 #define XCM_REG_CDU_AG_RD_IFEN 0x20044 5066 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 5067 are disregarded; all other signals are treated as usual; if 1 - normal 5068 activity. */ 5069 #define XCM_REG_CDU_AG_WR_IFEN 0x20040 5070 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 5071 disregarded; valid output is deasserted; all other signals are treated as 5072 usual; if 1 - normal activity. */ 5073 #define XCM_REG_CDU_SM_RD_IFEN 0x2004c 5074 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 5075 input is disregarded; all other signals are treated as usual; if 1 - 5076 normal activity. */ 5077 #define XCM_REG_CDU_SM_WR_IFEN 0x20048 5078 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 5079 the initial credit value; read returns the current value of the credit 5080 counter. Must be initialized to 1 at start-up. */ 5081 #define XCM_REG_CFC_INIT_CRD 0x20404 5082 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for 5083 weight 8 (the most prioritised); 1 stands for weight 1(least 5084 prioritised); 2 stands for weight 2; tc. */ 5085 #define XCM_REG_CP_WEIGHT 0x200dc 5086 /* [RW 1] Input csem Interface enable. If 0 - the valid input is 5087 disregarded; acknowledge output is deasserted; all other signals are 5088 treated as usual; if 1 - normal activity. */ 5089 #define XCM_REG_CSEM_IFEN 0x20028 5090 /* [RC 1] Set at message length mismatch (relative to last indication) at 5091 the csem interface. */ 5092 #define XCM_REG_CSEM_LENGTH_MIS 0x20228 5093 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for 5094 weight 8 (the most prioritised); 1 stands for weight 1(least 5095 prioritised); 2 stands for weight 2; tc. */ 5096 #define XCM_REG_CSEM_WEIGHT 0x200c4 5097 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is 5098 disregarded; acknowledge output is deasserted; all other signals are 5099 treated as usual; if 1 - normal activity. */ 5100 #define XCM_REG_DORQ_IFEN 0x20030 5101 /* [RC 1] Set at message length mismatch (relative to last indication) at 5102 the dorq interface. */ 5103 #define XCM_REG_DORQ_LENGTH_MIS 0x20230 5104 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for 5105 weight 8 (the most prioritised); 1 stands for weight 1(least 5106 prioritised); 2 stands for weight 2; tc. */ 5107 #define XCM_REG_DORQ_WEIGHT 0x200cc 5108 /* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */ 5109 #define XCM_REG_ERR_EVNT_ID 0x200b0 5110 /* [RW 28] The CM erroneous header for QM and Timers formatting. */ 5111 #define XCM_REG_ERR_XCM_HDR 0x200ac 5112 /* [RW 8] The Event ID for Timers expiration. */ 5113 #define XCM_REG_EXPR_EVNT_ID 0x200b4 5114 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write 5115 writes the initial credit value; read returns the current value of the 5116 credit counter. Must be initialized to 64 at start-up. */ 5117 #define XCM_REG_FIC0_INIT_CRD 0x2040c 5118 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 5119 writes the initial credit value; read returns the current value of the 5120 credit counter. Must be initialized to 64 at start-up. */ 5121 #define XCM_REG_FIC1_INIT_CRD 0x20410 5122 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118 5123 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c 5124 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108 5125 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c 5126 /* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1 5127 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr; 5128 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and 5129 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */ 5130 #define XCM_REG_GR_ARB_TYPE 0x2020c 5131 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 5132 highest priority is 3. It is supposed that the Channel group is the 5133 compliment of the other 3 groups. */ 5134 #define XCM_REG_GR_LD0_PR 0x20214 5135 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 5136 highest priority is 3. It is supposed that the Channel group is the 5137 compliment of the other 3 groups. */ 5138 #define XCM_REG_GR_LD1_PR 0x20218 5139 /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is 5140 disregarded; acknowledge output is deasserted; all other signals are 5141 treated as usual; if 1 - normal activity. */ 5142 #define XCM_REG_NIG0_IFEN 0x20038 5143 /* [RC 1] Set at message length mismatch (relative to last indication) at 5144 the nig0 interface. */ 5145 #define XCM_REG_NIG0_LENGTH_MIS 0x20238 5146 /* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for 5147 weight 8 (the most prioritised); 1 stands for weight 1(least 5148 prioritised); 2 stands for weight 2; tc. */ 5149 #define XCM_REG_NIG0_WEIGHT 0x200d4 5150 /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is 5151 disregarded; acknowledge output is deasserted; all other signals are 5152 treated as usual; if 1 - normal activity. */ 5153 #define XCM_REG_NIG1_IFEN 0x2003c 5154 /* [RC 1] Set at message length mismatch (relative to last indication) at 5155 the nig1 interface. */ 5156 #define XCM_REG_NIG1_LENGTH_MIS 0x2023c 5157 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and 5158 sent to STORM; for a specific connection type. The double REG-pairs are 5159 used in order to align to STORM context row size of 128 bits. The offset 5160 of these data in the STORM context is always 0. Index _i stands for the 5161 connection type (one of 16). */ 5162 #define XCM_REG_N_SM_CTX_LD_0 0x20060 5163 #define XCM_REG_N_SM_CTX_LD_1 0x20064 5164 #define XCM_REG_N_SM_CTX_LD_2 0x20068 5165 #define XCM_REG_N_SM_CTX_LD_3 0x2006c 5166 #define XCM_REG_N_SM_CTX_LD_4 0x20070 5167 #define XCM_REG_N_SM_CTX_LD_5 0x20074 5168 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; 5169 acknowledge output is deasserted; all other signals are treated as usual; 5170 if 1 - normal activity. */ 5171 #define XCM_REG_PBF_IFEN 0x20034 5172 /* [RC 1] Set at message length mismatch (relative to last indication) at 5173 the pbf interface. */ 5174 #define XCM_REG_PBF_LENGTH_MIS 0x20234 5175 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for 5176 weight 8 (the most prioritised); 1 stands for weight 1(least 5177 prioritised); 2 stands for weight 2; tc. */ 5178 #define XCM_REG_PBF_WEIGHT 0x200d0 5179 #define XCM_REG_PHYS_QNUM3_0 0x20100 5180 #define XCM_REG_PHYS_QNUM3_1 0x20104 5181 /* [RW 8] The Event ID for Timers formatting in case of stop done. */ 5182 #define XCM_REG_STOP_EVNT_ID 0x200b8 5183 /* [RC 1] Set at message length mismatch (relative to last indication) at 5184 the STORM interface. */ 5185 #define XCM_REG_STORM_LENGTH_MIS 0x2021c 5186 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for 5187 weight 8 (the most prioritised); 1 stands for weight 1(least 5188 prioritised); 2 stands for weight 2; tc. */ 5189 #define XCM_REG_STORM_WEIGHT 0x200bc 5190 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 5191 disregarded; acknowledge output is deasserted; all other signals are 5192 treated as usual; if 1 - normal activity. */ 5193 #define XCM_REG_STORM_XCM_IFEN 0x20010 5194 /* [RW 4] Timers output initial credit. Max credit available - 15.Write 5195 writes the initial credit value; read returns the current value of the 5196 credit counter. Must be initialized to 4 at start-up. */ 5197 #define XCM_REG_TM_INIT_CRD 0x2041c 5198 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for 5199 weight 8 (the most prioritised); 1 stands for weight 1(least 5200 prioritised); 2 stands for weight 2; tc. */ 5201 #define XCM_REG_TM_WEIGHT 0x200ec 5202 /* [RW 28] The CM header for Timers expiration command. */ 5203 #define XCM_REG_TM_XCM_HDR 0x200a8 5204 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is 5205 disregarded; acknowledge output is deasserted; all other signals are 5206 treated as usual; if 1 - normal activity. */ 5207 #define XCM_REG_TM_XCM_IFEN 0x2001c 5208 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is 5209 disregarded; acknowledge output is deasserted; all other signals are 5210 treated as usual; if 1 - normal activity. */ 5211 #define XCM_REG_TSEM_IFEN 0x20024 5212 /* [RC 1] Set at message length mismatch (relative to last indication) at 5213 the tsem interface. */ 5214 #define XCM_REG_TSEM_LENGTH_MIS 0x20224 5215 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for 5216 weight 8 (the most prioritised); 1 stands for weight 1(least 5217 prioritised); 2 stands for weight 2; tc. */ 5218 #define XCM_REG_TSEM_WEIGHT 0x200c0 5219 /* [RW 2] The queue index for registration on UNA greater NXT decision rule. */ 5220 #define XCM_REG_UNA_GT_NXT_Q 0x20120 5221 /* [RW 1] Input usem Interface enable. If 0 - the valid input is 5222 disregarded; acknowledge output is deasserted; all other signals are 5223 treated as usual; if 1 - normal activity. */ 5224 #define XCM_REG_USEM_IFEN 0x2002c 5225 /* [RC 1] Message length mismatch (relative to last indication) at the usem 5226 interface. */ 5227 #define XCM_REG_USEM_LENGTH_MIS 0x2022c 5228 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for 5229 weight 8 (the most prioritised); 1 stands for weight 1(least 5230 prioritised); 2 stands for weight 2; tc. */ 5231 #define XCM_REG_USEM_WEIGHT 0x200c8 5232 #define XCM_REG_WU_DA_CNT_CMD00 0x201d4 5233 #define XCM_REG_WU_DA_CNT_CMD01 0x201d8 5234 #define XCM_REG_WU_DA_CNT_CMD10 0x201dc 5235 #define XCM_REG_WU_DA_CNT_CMD11 0x201e0 5236 #define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4 5237 #define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8 5238 #define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec 5239 #define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0 5240 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4 5241 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8 5242 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc 5243 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0 5244 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 5245 acknowledge output is deasserted; all other signals are treated as usual; 5246 if 1 - normal activity. */ 5247 #define XCM_REG_XCM_CFC_IFEN 0x20050 5248 /* [RW 14] Interrupt mask register #0 read/write */ 5249 #define XCM_REG_XCM_INT_MASK 0x202b4 5250 /* [R 14] Interrupt register #0 read */ 5251 #define XCM_REG_XCM_INT_STS 0x202a8 5252 /* [RW 30] Parity mask register #0 read/write */ 5253 #define XCM_REG_XCM_PRTY_MASK 0x202c4 5254 /* [R 30] Parity register #0 read */ 5255 #define XCM_REG_XCM_PRTY_STS 0x202b8 5256 /* [RC 30] Parity register #0 read clear */ 5257 #define XCM_REG_XCM_PRTY_STS_CLR 0x202bc 5258 5259 /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS 5260 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 5261 Is used to determine the number of the AG context REG-pairs written back; 5262 when the Reg1WbFlg isn't set. */ 5263 #define XCM_REG_XCM_REG0_SZ 0x200f4 5264 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 5265 disregarded; valid is deasserted; all other signals are treated as usual; 5266 if 1 - normal activity. */ 5267 #define XCM_REG_XCM_STORM0_IFEN 0x20004 5268 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 5269 disregarded; valid is deasserted; all other signals are treated as usual; 5270 if 1 - normal activity. */ 5271 #define XCM_REG_XCM_STORM1_IFEN 0x20008 5272 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is 5273 disregarded; acknowledge output is deasserted; all other signals are 5274 treated as usual; if 1 - normal activity. */ 5275 #define XCM_REG_XCM_TM_IFEN 0x20020 5276 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 5277 disregarded; valid is deasserted; all other signals are treated as usual; 5278 if 1 - normal activity. */ 5279 #define XCM_REG_XCM_XQM_IFEN 0x2000c 5280 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */ 5281 #define XCM_REG_XCM_XQM_USE_Q 0x200f0 5282 /* [RW 4] The value by which CFC updates the activity counter at QM bypass. */ 5283 #define XCM_REG_XQM_BYP_ACT_UPD 0x200fc 5284 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes 5285 the initial credit value; read returns the current value of the credit 5286 counter. Must be initialized to 32 at start-up. */ 5287 #define XCM_REG_XQM_INIT_CRD 0x20420 5288 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 5289 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 5290 prioritised); 2 stands for weight 2; tc. */ 5291 #define XCM_REG_XQM_P_WEIGHT 0x200e4 5292 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 5293 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 5294 prioritised); 2 stands for weight 2; tc. */ 5295 #define XCM_REG_XQM_S_WEIGHT 0x200e8 5296 /* [RW 28] The CM header value for QM request (primary). */ 5297 #define XCM_REG_XQM_XCM_HDR_P 0x200a0 5298 /* [RW 28] The CM header value for QM request (secondary). */ 5299 #define XCM_REG_XQM_XCM_HDR_S 0x200a4 5300 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 5301 acknowledge output is deasserted; all other signals are treated as usual; 5302 if 1 - normal activity. */ 5303 #define XCM_REG_XQM_XCM_IFEN 0x20014 5304 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 5305 acknowledge output is deasserted; all other signals are treated as usual; 5306 if 1 - normal activity. */ 5307 #define XCM_REG_XSDM_IFEN 0x20018 5308 /* [RC 1] Set at message length mismatch (relative to last indication) at 5309 the SDM interface. */ 5310 #define XCM_REG_XSDM_LENGTH_MIS 0x20220 5311 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for 5312 weight 8 (the most prioritised); 1 stands for weight 1(least 5313 prioritised); 2 stands for weight 2; tc. */ 5314 #define XCM_REG_XSDM_WEIGHT 0x200e0 5315 /* [RW 17] Indirect access to the descriptor table of the XX protection 5316 mechanism. The fields are: [5:0] - message length; 11:6] - message 5317 pointer; 16:12] - next pointer. */ 5318 #define XCM_REG_XX_DESCR_TABLE 0x20480 5319 #define XCM_REG_XX_DESCR_TABLE_SIZE 32 5320 /* [R 6] Used to read the XX protection Free counter. */ 5321 #define XCM_REG_XX_FREE 0x20240 5322 /* [RW 6] Initial value for the credit counter; responsible for fulfilling 5323 of the Input Stage XX protection buffer by the XX protection pending 5324 messages. Max credit available - 3.Write writes the initial credit value; 5325 read returns the current value of the credit counter. Must be initialized 5326 to 2 at start-up. */ 5327 #define XCM_REG_XX_INIT_CRD 0x20424 5328 /* [RW 6] The maximum number of pending messages; which may be stored in XX 5329 protection. ~xcm_registers_xx_free.xx_free read on read. */ 5330 #define XCM_REG_XX_MSG_NUM 0x20428 5331 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 5332 #define XCM_REG_XX_OVFL_EVNT_ID 0x20058 5333 #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS (0x1<<0) 5334 #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS (0x1<<1) 5335 #define XMAC_CTRL_REG_LINE_LOCAL_LPBK (0x1<<2) 5336 #define XMAC_CTRL_REG_RX_EN (0x1<<1) 5337 #define XMAC_CTRL_REG_SOFT_RESET (0x1<<6) 5338 #define XMAC_CTRL_REG_TX_EN (0x1<<0) 5339 #define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN (0x1<<18) 5340 #define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN (0x1<<17) 5341 #define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN (0x1<<0) 5342 #define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN (0x1<<3) 5343 #define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN (0x1<<4) 5344 #define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN (0x1<<5) 5345 #define XMAC_REG_CLEAR_RX_LSS_STATUS 0x60 5346 #define XMAC_REG_CTRL 0 5347 /* [RW 16] Upper 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC 5348 * packets transmitted by the MAC */ 5349 #define XMAC_REG_CTRL_SA_HI 0x2c 5350 /* [RW 32] Lower 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC 5351 * packets transmitted by the MAC */ 5352 #define XMAC_REG_CTRL_SA_LO 0x28 5353 #define XMAC_REG_PAUSE_CTRL 0x68 5354 #define XMAC_REG_PFC_CTRL 0x70 5355 #define XMAC_REG_PFC_CTRL_HI 0x74 5356 #define XMAC_REG_RX_LSS_STATUS 0x58 5357 /* [RW 14] Maximum packet size in receive direction; exclusive of preamble & 5358 * CRC in strip mode */ 5359 #define XMAC_REG_RX_MAX_SIZE 0x40 5360 #define XMAC_REG_TX_CTRL 0x20 5361 /* [RW 16] Indirect access to the XX table of the XX protection mechanism. 5362 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] - 5363 header pointer. */ 5364 #define XCM_REG_XX_TABLE 0x20500 5365 /* [RW 8] The event id for aggregated interrupt 0 */ 5366 #define XSDM_REG_AGG_INT_EVENT_0 0x166038 5367 #define XSDM_REG_AGG_INT_EVENT_1 0x16603c 5368 #define XSDM_REG_AGG_INT_EVENT_10 0x166060 5369 #define XSDM_REG_AGG_INT_EVENT_11 0x166064 5370 #define XSDM_REG_AGG_INT_EVENT_12 0x166068 5371 #define XSDM_REG_AGG_INT_EVENT_13 0x16606c 5372 #define XSDM_REG_AGG_INT_EVENT_14 0x166070 5373 #define XSDM_REG_AGG_INT_EVENT_2 0x166040 5374 #define XSDM_REG_AGG_INT_EVENT_3 0x166044 5375 #define XSDM_REG_AGG_INT_EVENT_4 0x166048 5376 #define XSDM_REG_AGG_INT_EVENT_5 0x16604c 5377 #define XSDM_REG_AGG_INT_EVENT_6 0x166050 5378 #define XSDM_REG_AGG_INT_EVENT_7 0x166054 5379 #define XSDM_REG_AGG_INT_EVENT_8 0x166058 5380 #define XSDM_REG_AGG_INT_EVENT_9 0x16605c 5381 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0) 5382 or auto-mask-mode (1) */ 5383 #define XSDM_REG_AGG_INT_MODE_0 0x1661b8 5384 #define XSDM_REG_AGG_INT_MODE_1 0x1661bc 5385 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 5386 #define XSDM_REG_CFC_RSP_START_ADDR 0x166008 5387 /* [RW 16] The maximum value of the completion counter #0 */ 5388 #define XSDM_REG_CMP_COUNTER_MAX0 0x16601c 5389 /* [RW 16] The maximum value of the completion counter #1 */ 5390 #define XSDM_REG_CMP_COUNTER_MAX1 0x166020 5391 /* [RW 16] The maximum value of the completion counter #2 */ 5392 #define XSDM_REG_CMP_COUNTER_MAX2 0x166024 5393 /* [RW 16] The maximum value of the completion counter #3 */ 5394 #define XSDM_REG_CMP_COUNTER_MAX3 0x166028 5395 /* [RW 13] The start address in the internal RAM for the completion 5396 counters. */ 5397 #define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c 5398 #define XSDM_REG_ENABLE_IN1 0x166238 5399 #define XSDM_REG_ENABLE_IN2 0x16623c 5400 #define XSDM_REG_ENABLE_OUT1 0x166240 5401 #define XSDM_REG_ENABLE_OUT2 0x166244 5402 /* [RW 4] The initial number of messages that can be sent to the pxp control 5403 interface without receiving any ACK. */ 5404 #define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc 5405 /* [ST 32] The number of ACK after placement messages received */ 5406 #define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c 5407 /* [ST 32] The number of packet end messages received from the parser */ 5408 #define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274 5409 /* [ST 32] The number of requests received from the pxp async if */ 5410 #define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278 5411 /* [ST 32] The number of commands received in queue 0 */ 5412 #define XSDM_REG_NUM_OF_Q0_CMD 0x166248 5413 /* [ST 32] The number of commands received in queue 10 */ 5414 #define XSDM_REG_NUM_OF_Q10_CMD 0x16626c 5415 /* [ST 32] The number of commands received in queue 11 */ 5416 #define XSDM_REG_NUM_OF_Q11_CMD 0x166270 5417 /* [ST 32] The number of commands received in queue 1 */ 5418 #define XSDM_REG_NUM_OF_Q1_CMD 0x16624c 5419 /* [ST 32] The number of commands received in queue 3 */ 5420 #define XSDM_REG_NUM_OF_Q3_CMD 0x166250 5421 /* [ST 32] The number of commands received in queue 4 */ 5422 #define XSDM_REG_NUM_OF_Q4_CMD 0x166254 5423 /* [ST 32] The number of commands received in queue 5 */ 5424 #define XSDM_REG_NUM_OF_Q5_CMD 0x166258 5425 /* [ST 32] The number of commands received in queue 6 */ 5426 #define XSDM_REG_NUM_OF_Q6_CMD 0x16625c 5427 /* [ST 32] The number of commands received in queue 7 */ 5428 #define XSDM_REG_NUM_OF_Q7_CMD 0x166260 5429 /* [ST 32] The number of commands received in queue 8 */ 5430 #define XSDM_REG_NUM_OF_Q8_CMD 0x166264 5431 /* [ST 32] The number of commands received in queue 9 */ 5432 #define XSDM_REG_NUM_OF_Q9_CMD 0x166268 5433 /* [RW 13] The start address in the internal RAM for queue counters */ 5434 #define XSDM_REG_Q_COUNTER_START_ADDR 0x166010 5435 /* [W 17] Generate an operation after completion; bit-16 is 5436 * AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and 5437 * bits 4:0 are the T124Param[4:0] */ 5438 #define XSDM_REG_OPERATION_GEN 0x1664c4 5439 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 5440 #define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548 5441 /* [R 1] parser fifo empty in sdm_sync block */ 5442 #define XSDM_REG_SYNC_PARSER_EMPTY 0x166550 5443 /* [R 1] parser serial fifo empty in sdm_sync block */ 5444 #define XSDM_REG_SYNC_SYNC_EMPTY 0x166558 5445 /* [RW 32] Tick for timer counter. Applicable only when 5446 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */ 5447 #define XSDM_REG_TIMER_TICK 0x166000 5448 /* [RW 32] Interrupt mask register #0 read/write */ 5449 #define XSDM_REG_XSDM_INT_MASK_0 0x16629c 5450 #define XSDM_REG_XSDM_INT_MASK_1 0x1662ac 5451 /* [R 32] Interrupt register #0 read */ 5452 #define XSDM_REG_XSDM_INT_STS_0 0x166290 5453 #define XSDM_REG_XSDM_INT_STS_1 0x1662a0 5454 /* [RW 11] Parity mask register #0 read/write */ 5455 #define XSDM_REG_XSDM_PRTY_MASK 0x1662bc 5456 /* [R 11] Parity register #0 read */ 5457 #define XSDM_REG_XSDM_PRTY_STS 0x1662b0 5458 /* [RC 11] Parity register #0 read clear */ 5459 #define XSDM_REG_XSDM_PRTY_STS_CLR 0x1662b4 5460 /* [RW 5] The number of time_slots in the arbitration cycle */ 5461 #define XSEM_REG_ARB_CYCLE_SIZE 0x280034 5462 /* [RW 3] The source that is associated with arbitration element 0. Source 5463 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5464 sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 5465 #define XSEM_REG_ARB_ELEMENT0 0x280020 5466 /* [RW 3] The source that is associated with arbitration element 1. Source 5467 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5468 sleeping thread with priority 1; 4- sleeping thread with priority 2. 5469 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */ 5470 #define XSEM_REG_ARB_ELEMENT1 0x280024 5471 /* [RW 3] The source that is associated with arbitration element 2. Source 5472 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5473 sleeping thread with priority 1; 4- sleeping thread with priority 2. 5474 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 5475 and ~xsem_registers_arb_element1.arb_element1 */ 5476 #define XSEM_REG_ARB_ELEMENT2 0x280028 5477 /* [RW 3] The source that is associated with arbitration element 3. Source 5478 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5479 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 5480 not be equal to register ~xsem_registers_arb_element0.arb_element0 and 5481 ~xsem_registers_arb_element1.arb_element1 and 5482 ~xsem_registers_arb_element2.arb_element2 */ 5483 #define XSEM_REG_ARB_ELEMENT3 0x28002c 5484 /* [RW 3] The source that is associated with arbitration element 4. Source 5485 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5486 sleeping thread with priority 1; 4- sleeping thread with priority 2. 5487 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 5488 and ~xsem_registers_arb_element1.arb_element1 and 5489 ~xsem_registers_arb_element2.arb_element2 and 5490 ~xsem_registers_arb_element3.arb_element3 */ 5491 #define XSEM_REG_ARB_ELEMENT4 0x280030 5492 #define XSEM_REG_ENABLE_IN 0x2800a4 5493 #define XSEM_REG_ENABLE_OUT 0x2800a8 5494 /* [RW 32] This address space contains all registers and memories that are 5495 placed in SEM_FAST block. The SEM_FAST registers are described in 5496 appendix B. In order to access the sem_fast registers the base address 5497 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 5498 #define XSEM_REG_FAST_MEMORY 0x2a0000 5499 /* [RW 1] Disables input messages from FIC0 May be updated during run_time 5500 by the microcode */ 5501 #define XSEM_REG_FIC0_DISABLE 0x280224 5502 /* [RW 1] Disables input messages from FIC1 May be updated during run_time 5503 by the microcode */ 5504 #define XSEM_REG_FIC1_DISABLE 0x280234 5505 /* [RW 15] Interrupt table Read and write access to it is not possible in 5506 the middle of the work */ 5507 #define XSEM_REG_INT_TABLE 0x280400 5508 /* [ST 24] Statistics register. The number of messages that entered through 5509 FIC0 */ 5510 #define XSEM_REG_MSG_NUM_FIC0 0x280000 5511 /* [ST 24] Statistics register. The number of messages that entered through 5512 FIC1 */ 5513 #define XSEM_REG_MSG_NUM_FIC1 0x280004 5514 /* [ST 24] Statistics register. The number of messages that were sent to 5515 FOC0 */ 5516 #define XSEM_REG_MSG_NUM_FOC0 0x280008 5517 /* [ST 24] Statistics register. The number of messages that were sent to 5518 FOC1 */ 5519 #define XSEM_REG_MSG_NUM_FOC1 0x28000c 5520 /* [ST 24] Statistics register. The number of messages that were sent to 5521 FOC2 */ 5522 #define XSEM_REG_MSG_NUM_FOC2 0x280010 5523 /* [ST 24] Statistics register. The number of messages that were sent to 5524 FOC3 */ 5525 #define XSEM_REG_MSG_NUM_FOC3 0x280014 5526 /* [RW 1] Disables input messages from the passive buffer May be updated 5527 during run_time by the microcode */ 5528 #define XSEM_REG_PAS_DISABLE 0x28024c 5529 /* [WB 128] Debug only. Passive buffer memory */ 5530 #define XSEM_REG_PASSIVE_BUFFER 0x282000 5531 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 5532 #define XSEM_REG_PRAM 0x2c0000 5533 /* [R 16] Valid sleeping threads indication have bit per thread */ 5534 #define XSEM_REG_SLEEP_THREADS_VALID 0x28026c 5535 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 5536 #define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0 5537 /* [RW 16] List of free threads . There is a bit per thread. */ 5538 #define XSEM_REG_THREADS_LIST 0x2802e4 5539 /* [RW 3] The arbitration scheme of time_slot 0 */ 5540 #define XSEM_REG_TS_0_AS 0x280038 5541 /* [RW 3] The arbitration scheme of time_slot 10 */ 5542 #define XSEM_REG_TS_10_AS 0x280060 5543 /* [RW 3] The arbitration scheme of time_slot 11 */ 5544 #define XSEM_REG_TS_11_AS 0x280064 5545 /* [RW 3] The arbitration scheme of time_slot 12 */ 5546 #define XSEM_REG_TS_12_AS 0x280068 5547 /* [RW 3] The arbitration scheme of time_slot 13 */ 5548 #define XSEM_REG_TS_13_AS 0x28006c 5549 /* [RW 3] The arbitration scheme of time_slot 14 */ 5550 #define XSEM_REG_TS_14_AS 0x280070 5551 /* [RW 3] The arbitration scheme of time_slot 15 */ 5552 #define XSEM_REG_TS_15_AS 0x280074 5553 /* [RW 3] The arbitration scheme of time_slot 16 */ 5554 #define XSEM_REG_TS_16_AS 0x280078 5555 /* [RW 3] The arbitration scheme of time_slot 17 */ 5556 #define XSEM_REG_TS_17_AS 0x28007c 5557 /* [RW 3] The arbitration scheme of time_slot 18 */ 5558 #define XSEM_REG_TS_18_AS 0x280080 5559 /* [RW 3] The arbitration scheme of time_slot 1 */ 5560 #define XSEM_REG_TS_1_AS 0x28003c 5561 /* [RW 3] The arbitration scheme of time_slot 2 */ 5562 #define XSEM_REG_TS_2_AS 0x280040 5563 /* [RW 3] The arbitration scheme of time_slot 3 */ 5564 #define XSEM_REG_TS_3_AS 0x280044 5565 /* [RW 3] The arbitration scheme of time_slot 4 */ 5566 #define XSEM_REG_TS_4_AS 0x280048 5567 /* [RW 3] The arbitration scheme of time_slot 5 */ 5568 #define XSEM_REG_TS_5_AS 0x28004c 5569 /* [RW 3] The arbitration scheme of time_slot 6 */ 5570 #define XSEM_REG_TS_6_AS 0x280050 5571 /* [RW 3] The arbitration scheme of time_slot 7 */ 5572 #define XSEM_REG_TS_7_AS 0x280054 5573 /* [RW 3] The arbitration scheme of time_slot 8 */ 5574 #define XSEM_REG_TS_8_AS 0x280058 5575 /* [RW 3] The arbitration scheme of time_slot 9 */ 5576 #define XSEM_REG_TS_9_AS 0x28005c 5577 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 5578 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ 5579 #define XSEM_REG_VFPF_ERR_NUM 0x280380 5580 /* [RW 32] Interrupt mask register #0 read/write */ 5581 #define XSEM_REG_XSEM_INT_MASK_0 0x280110 5582 #define XSEM_REG_XSEM_INT_MASK_1 0x280120 5583 /* [R 32] Interrupt register #0 read */ 5584 #define XSEM_REG_XSEM_INT_STS_0 0x280104 5585 #define XSEM_REG_XSEM_INT_STS_1 0x280114 5586 /* [RW 32] Parity mask register #0 read/write */ 5587 #define XSEM_REG_XSEM_PRTY_MASK_0 0x280130 5588 #define XSEM_REG_XSEM_PRTY_MASK_1 0x280140 5589 /* [R 32] Parity register #0 read */ 5590 #define XSEM_REG_XSEM_PRTY_STS_0 0x280124 5591 #define XSEM_REG_XSEM_PRTY_STS_1 0x280134 5592 /* [RC 32] Parity register #0 read clear */ 5593 #define XSEM_REG_XSEM_PRTY_STS_CLR_0 0x280128 5594 #define XSEM_REG_XSEM_PRTY_STS_CLR_1 0x280138 5595 #define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0) 5596 #define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1) 5597 #define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) 5598 #define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0) 5599 #define MCPR_NVM_COMMAND_DOIT (1L<<4) 5600 #define MCPR_NVM_COMMAND_DONE (1L<<3) 5601 #define MCPR_NVM_COMMAND_FIRST (1L<<7) 5602 #define MCPR_NVM_COMMAND_LAST (1L<<8) 5603 #define MCPR_NVM_COMMAND_WR (1L<<5) 5604 #define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9) 5605 #define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) 5606 #define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) 5607 #define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3) 5608 #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3) 5609 #define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3) 5610 #define BIGMAC_REGISTER_RX_CONTROL (0x21<<3) 5611 #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3) 5612 #define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3) 5613 #define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3) 5614 #define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3) 5615 #define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3) 5616 #define BIGMAC_REGISTER_TX_CONTROL (0x07<<3) 5617 #define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3) 5618 #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3) 5619 #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3) 5620 #define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3) 5621 #define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3) 5622 #define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3) 5623 #define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3) 5624 #define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3) 5625 #define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3) 5626 #define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3) 5627 #define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3) 5628 #define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3) 5629 #define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3) 5630 #define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3) 5631 #define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3) 5632 #define BIGMAC2_REGISTER_RX_STAT_GRPP (0x51<<3) 5633 #define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3) 5634 #define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3) 5635 #define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3) 5636 #define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3) 5637 #define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3) 5638 #define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3) 5639 #define BIGMAC2_REGISTER_TX_STAT_GTPP (0x24<<3) 5640 #define EMAC_LED_1000MB_OVERRIDE (1L<<1) 5641 #define EMAC_LED_100MB_OVERRIDE (1L<<2) 5642 #define EMAC_LED_10MB_OVERRIDE (1L<<3) 5643 #define EMAC_LED_2500MB_OVERRIDE (1L<<12) 5644 #define EMAC_LED_OVERRIDE (1L<<0) 5645 #define EMAC_LED_TRAFFIC (1L<<6) 5646 #define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26) 5647 #define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26) 5648 #define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26) 5649 #define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26) 5650 #define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26) 5651 #define EMAC_MDIO_COMM_DATA (0xffffL<<0) 5652 #define EMAC_MDIO_COMM_START_BUSY (1L<<29) 5653 #define EMAC_MDIO_MODE_AUTO_POLL (1L<<4) 5654 #define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31) 5655 #define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL<<16) 5656 #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16 5657 #define EMAC_MDIO_STATUS_10MB (1L<<1) 5658 #define EMAC_MODE_25G_MODE (1L<<5) 5659 #define EMAC_MODE_HALF_DUPLEX (1L<<1) 5660 #define EMAC_MODE_PORT_GMII (2L<<2) 5661 #define EMAC_MODE_PORT_MII (1L<<2) 5662 #define EMAC_MODE_PORT_MII_10M (3L<<2) 5663 #define EMAC_MODE_RESET (1L<<0) 5664 #define EMAC_REG_EMAC_LED 0xc 5665 #define EMAC_REG_EMAC_MAC_MATCH 0x10 5666 #define EMAC_REG_EMAC_MDIO_COMM 0xac 5667 #define EMAC_REG_EMAC_MDIO_MODE 0xb4 5668 #define EMAC_REG_EMAC_MDIO_STATUS 0xb0 5669 #define EMAC_REG_EMAC_MODE 0x0 5670 #define EMAC_REG_EMAC_RX_MODE 0xc8 5671 #define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c 5672 #define EMAC_REG_EMAC_RX_STAT_AC 0x180 5673 #define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4 5674 #define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23 5675 #define EMAC_REG_EMAC_TX_MODE 0xbc 5676 #define EMAC_REG_EMAC_TX_STAT_AC 0x280 5677 #define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22 5678 #define EMAC_REG_RX_PFC_MODE 0x320 5679 #define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L<<2) 5680 #define EMAC_REG_RX_PFC_MODE_RX_EN (1L<<1) 5681 #define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0) 5682 #define EMAC_REG_RX_PFC_PARAM 0x324 5683 #define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0 5684 #define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16 5685 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328 5686 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0) 5687 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330 5688 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0) 5689 #define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c 5690 #define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0) 5691 #define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334 5692 #define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0) 5693 #define EMAC_RX_MODE_FLOW_EN (1L<<2) 5694 #define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3) 5695 #define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) 5696 #define EMAC_RX_MODE_PROMISCUOUS (1L<<8) 5697 #define EMAC_RX_MODE_RESET (1L<<0) 5698 #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) 5699 #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) 5700 #define EMAC_TX_MODE_FLOW_EN (1L<<4) 5701 #define EMAC_TX_MODE_RESET (1L<<0) 5702 #define MISC_REGISTERS_GPIO_0 0 5703 #define MISC_REGISTERS_GPIO_1 1 5704 #define MISC_REGISTERS_GPIO_2 2 5705 #define MISC_REGISTERS_GPIO_3 3 5706 #define MISC_REGISTERS_GPIO_CLR_POS 16 5707 #define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24) 5708 #define MISC_REGISTERS_GPIO_FLOAT_POS 24 5709 #define MISC_REGISTERS_GPIO_HIGH 1 5710 #define MISC_REGISTERS_GPIO_INPUT_HI_Z 2 5711 #define MISC_REGISTERS_GPIO_INT_CLR_POS 24 5712 #define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0 5713 #define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1 5714 #define MISC_REGISTERS_GPIO_INT_SET_POS 16 5715 #define MISC_REGISTERS_GPIO_LOW 0 5716 #define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1 5717 #define MISC_REGISTERS_GPIO_OUTPUT_LOW 0 5718 #define MISC_REGISTERS_GPIO_PORT_SHIFT 4 5719 #define MISC_REGISTERS_GPIO_SET_POS 8 5720 #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588 5721 #define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29) 5722 #define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7) 5723 #define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1<<26) 5724 #define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27) 5725 #define MISC_REGISTERS_RESET_REG_1_SET 0x584 5726 #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598 5727 #define MISC_REGISTERS_RESET_REG_2_MSTAT0 (0x1<<24) 5728 #define MISC_REGISTERS_RESET_REG_2_MSTAT1 (0x1<<25) 5729 #define MISC_REGISTERS_RESET_REG_2_PGLC (0x1<<19) 5730 #define MISC_REGISTERS_RESET_REG_2_RST_ATC (0x1<<17) 5731 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0) 5732 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1) 5733 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2) 5734 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14) 5735 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3) 5736 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15) 5737 #define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4) 5738 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6) 5739 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8) 5740 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7) 5741 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5) 5742 #define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13) 5743 #define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11) 5744 #define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO (0x1<<13) 5745 #define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9) 5746 #define MISC_REGISTERS_RESET_REG_2_SET 0x594 5747 #define MISC_REGISTERS_RESET_REG_2_UMAC0 (0x1<<20) 5748 #define MISC_REGISTERS_RESET_REG_2_UMAC1 (0x1<<21) 5749 #define MISC_REGISTERS_RESET_REG_2_XMAC (0x1<<22) 5750 #define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT (0x1<<23) 5751 #define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8 5752 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1) 5753 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2) 5754 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3) 5755 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0) 5756 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5) 5757 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6) 5758 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7) 5759 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4) 5760 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8) 5761 #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4 5762 #define MISC_REGISTERS_SPIO_4 4 5763 #define MISC_REGISTERS_SPIO_5 5 5764 #define MISC_REGISTERS_SPIO_7 7 5765 #define MISC_REGISTERS_SPIO_CLR_POS 16 5766 #define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24) 5767 #define MISC_REGISTERS_SPIO_FLOAT_POS 24 5768 #define MISC_REGISTERS_SPIO_INPUT_HI_Z 2 5769 #define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16 5770 #define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1 5771 #define MISC_REGISTERS_SPIO_OUTPUT_LOW 0 5772 #define MISC_REGISTERS_SPIO_SET_POS 8 5773 #define HW_LOCK_DRV_FLAGS 10 5774 #define HW_LOCK_MAX_RESOURCE_VALUE 31 5775 #define HW_LOCK_RESOURCE_GPIO 1 5776 #define HW_LOCK_RESOURCE_MDIO 0 5777 #define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3 5778 #define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8 5779 #define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9 5780 #define HW_LOCK_RESOURCE_SPIO 2 5781 #define HW_LOCK_RESOURCE_RESET 5 5782 #define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4) 5783 #define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5) 5784 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18) 5785 #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31) 5786 #define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30) 5787 #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9) 5788 #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8) 5789 #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7) 5790 #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6) 5791 #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29) 5792 #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28) 5793 #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1) 5794 #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0) 5795 #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18) 5796 #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11) 5797 #define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10) 5798 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13) 5799 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12) 5800 #define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2) 5801 #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12) 5802 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28) 5803 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1<<31) 5804 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29) 5805 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30) 5806 #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15) 5807 #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14) 5808 #define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14) 5809 #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20) 5810 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1<<31) 5811 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30) 5812 #define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0) 5813 #define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2) 5814 #define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3) 5815 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5) 5816 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4) 5817 #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3) 5818 #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2) 5819 #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3) 5820 #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2) 5821 #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22) 5822 #define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15) 5823 #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27) 5824 #define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26) 5825 #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5) 5826 #define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4) 5827 #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25) 5828 #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24) 5829 #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29) 5830 #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28) 5831 #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23) 5832 #define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22) 5833 #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27) 5834 #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26) 5835 #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21) 5836 #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20) 5837 #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25) 5838 #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24) 5839 #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16) 5840 #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9) 5841 #define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8) 5842 #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7) 5843 #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6) 5844 #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11) 5845 #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10) 5846 5847 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (0x1<<5) 5848 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (0x1<<9) 5849 5850 #define RESERVED_GENERAL_ATTENTION_BIT_0 0 5851 5852 #define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0 5853 #define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000 5854 5855 #define RESERVED_GENERAL_ATTENTION_BIT_6 6 5856 #define RESERVED_GENERAL_ATTENTION_BIT_7 7 5857 #define RESERVED_GENERAL_ATTENTION_BIT_8 8 5858 #define RESERVED_GENERAL_ATTENTION_BIT_9 9 5859 #define RESERVED_GENERAL_ATTENTION_BIT_10 10 5860 #define RESERVED_GENERAL_ATTENTION_BIT_11 11 5861 #define RESERVED_GENERAL_ATTENTION_BIT_12 12 5862 #define RESERVED_GENERAL_ATTENTION_BIT_13 13 5863 #define RESERVED_GENERAL_ATTENTION_BIT_14 14 5864 #define RESERVED_GENERAL_ATTENTION_BIT_15 15 5865 #define RESERVED_GENERAL_ATTENTION_BIT_16 16 5866 #define RESERVED_GENERAL_ATTENTION_BIT_17 17 5867 #define RESERVED_GENERAL_ATTENTION_BIT_18 18 5868 #define RESERVED_GENERAL_ATTENTION_BIT_19 19 5869 #define RESERVED_GENERAL_ATTENTION_BIT_20 20 5870 #define RESERVED_GENERAL_ATTENTION_BIT_21 21 5871 5872 /* storm asserts attention bits */ 5873 #define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7 5874 #define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8 5875 #define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9 5876 #define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10 5877 5878 /* mcp error attention bit */ 5879 #define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11 5880 5881 /*E1H NIG status sync attention mapped to group 4-7*/ 5882 #define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12 5883 #define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13 5884 #define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14 5885 #define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15 5886 #define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16 5887 #define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17 5888 #define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18 5889 #define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19 5890 5891 5892 #define LATCHED_ATTN_RBCR 23 5893 #define LATCHED_ATTN_RBCT 24 5894 #define LATCHED_ATTN_RBCN 25 5895 #define LATCHED_ATTN_RBCU 26 5896 #define LATCHED_ATTN_RBCP 27 5897 #define LATCHED_ATTN_TIMEOUT_GRC 28 5898 #define LATCHED_ATTN_RSVD_GRC 29 5899 #define LATCHED_ATTN_ROM_PARITY_MCP 30 5900 #define LATCHED_ATTN_UM_RX_PARITY_MCP 31 5901 #define LATCHED_ATTN_UM_TX_PARITY_MCP 32 5902 #define LATCHED_ATTN_SCPAD_PARITY_MCP 33 5903 5904 #define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32) 5905 #define GENERAL_ATTEN_OFFSET(atten_name)\ 5906 (1UL << ((94 + atten_name) % 32)) 5907 /* 5908 * This file defines GRC base address for every block. 5909 * This file is included by chipsim, asm microcode and cpp microcode. 5910 * These values are used in Design.xml on regBase attribute 5911 * Use the base with the generated offsets of specific registers. 5912 */ 5913 5914 #define GRCBASE_PXPCS 0x000000 5915 #define GRCBASE_PCICONFIG 0x002000 5916 #define GRCBASE_PCIREG 0x002400 5917 #define GRCBASE_EMAC0 0x008000 5918 #define GRCBASE_EMAC1 0x008400 5919 #define GRCBASE_DBU 0x008800 5920 #define GRCBASE_MISC 0x00A000 5921 #define GRCBASE_DBG 0x00C000 5922 #define GRCBASE_NIG 0x010000 5923 #define GRCBASE_XCM 0x020000 5924 #define GRCBASE_PRS 0x040000 5925 #define GRCBASE_SRCH 0x040400 5926 #define GRCBASE_TSDM 0x042000 5927 #define GRCBASE_TCM 0x050000 5928 #define GRCBASE_BRB1 0x060000 5929 #define GRCBASE_MCP 0x080000 5930 #define GRCBASE_UPB 0x0C1000 5931 #define GRCBASE_CSDM 0x0C2000 5932 #define GRCBASE_USDM 0x0C4000 5933 #define GRCBASE_CCM 0x0D0000 5934 #define GRCBASE_UCM 0x0E0000 5935 #define GRCBASE_CDU 0x101000 5936 #define GRCBASE_DMAE 0x102000 5937 #define GRCBASE_PXP 0x103000 5938 #define GRCBASE_CFC 0x104000 5939 #define GRCBASE_HC 0x108000 5940 #define GRCBASE_PXP2 0x120000 5941 #define GRCBASE_PBF 0x140000 5942 #define GRCBASE_UMAC0 0x160000 5943 #define GRCBASE_UMAC1 0x160400 5944 #define GRCBASE_XPB 0x161000 5945 #define GRCBASE_MSTAT0 0x162000 5946 #define GRCBASE_MSTAT1 0x162800 5947 #define GRCBASE_XMAC0 0x163000 5948 #define GRCBASE_XMAC1 0x163800 5949 #define GRCBASE_TIMERS 0x164000 5950 #define GRCBASE_XSDM 0x166000 5951 #define GRCBASE_QM 0x168000 5952 #define GRCBASE_DQ 0x170000 5953 #define GRCBASE_TSEM 0x180000 5954 #define GRCBASE_CSEM 0x200000 5955 #define GRCBASE_XSEM 0x280000 5956 #define GRCBASE_USEM 0x300000 5957 #define GRCBASE_MISC_AEU GRCBASE_MISC 5958 5959 5960 /* offset of configuration space in the pci core register */ 5961 #define PCICFG_OFFSET 0x2000 5962 #define PCICFG_VENDOR_ID_OFFSET 0x00 5963 #define PCICFG_DEVICE_ID_OFFSET 0x02 5964 #define PCICFG_COMMAND_OFFSET 0x04 5965 #define PCICFG_COMMAND_IO_SPACE (1<<0) 5966 #define PCICFG_COMMAND_MEM_SPACE (1<<1) 5967 #define PCICFG_COMMAND_BUS_MASTER (1<<2) 5968 #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3) 5969 #define PCICFG_COMMAND_MWI_CYCLES (1<<4) 5970 #define PCICFG_COMMAND_VGA_SNOOP (1<<5) 5971 #define PCICFG_COMMAND_PERR_ENA (1<<6) 5972 #define PCICFG_COMMAND_STEPPING (1<<7) 5973 #define PCICFG_COMMAND_SERR_ENA (1<<8) 5974 #define PCICFG_COMMAND_FAST_B2B (1<<9) 5975 #define PCICFG_COMMAND_INT_DISABLE (1<<10) 5976 #define PCICFG_COMMAND_RESERVED (0x1f<<11) 5977 #define PCICFG_STATUS_OFFSET 0x06 5978 #define PCICFG_REVESION_ID_OFFSET 0x08 5979 #define PCICFG_CACHE_LINE_SIZE 0x0c 5980 #define PCICFG_LATENCY_TIMER 0x0d 5981 #define PCICFG_BAR_1_LOW 0x10 5982 #define PCICFG_BAR_1_HIGH 0x14 5983 #define PCICFG_BAR_2_LOW 0x18 5984 #define PCICFG_BAR_2_HIGH 0x1c 5985 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c 5986 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e 5987 #define PCICFG_INT_LINE 0x3c 5988 #define PCICFG_INT_PIN 0x3d 5989 #define PCICFG_PM_CAPABILITY 0x48 5990 #define PCICFG_PM_CAPABILITY_VERSION (0x3<<16) 5991 #define PCICFG_PM_CAPABILITY_CLOCK (1<<19) 5992 #define PCICFG_PM_CAPABILITY_RESERVED (1<<20) 5993 #define PCICFG_PM_CAPABILITY_DSI (1<<21) 5994 #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22) 5995 #define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25) 5996 #define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26) 5997 #define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27) 5998 #define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28) 5999 #define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29) 6000 #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30) 6001 #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31) 6002 #define PCICFG_PM_CSR_OFFSET 0x4c 6003 #define PCICFG_PM_CSR_STATE (0x3<<0) 6004 #define PCICFG_PM_CSR_PME_ENABLE (1<<8) 6005 #define PCICFG_PM_CSR_PME_STATUS (1<<15) 6006 #define PCICFG_MSI_CAP_ID_OFFSET 0x58 6007 #define PCICFG_MSI_CONTROL_ENABLE (0x1<<16) 6008 #define PCICFG_MSI_CONTROL_MCAP (0x7<<17) 6009 #define PCICFG_MSI_CONTROL_MENA (0x7<<20) 6010 #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23) 6011 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24) 6012 #define PCICFG_GRC_ADDRESS 0x78 6013 #define PCICFG_GRC_DATA 0x80 6014 #define PCICFG_MSIX_CAP_ID_OFFSET 0xa0 6015 #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16) 6016 #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27) 6017 #define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30) 6018 #define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31) 6019 6020 #define PCICFG_DEVICE_CONTROL 0xb4 6021 #define PCICFG_DEVICE_STATUS 0xb6 6022 #define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0) 6023 #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1) 6024 #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2) 6025 #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3) 6026 #define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4) 6027 #define PCICFG_DEVICE_STATUS_NO_PEND (1<<5) 6028 #define PCICFG_LINK_CONTROL 0xbc 6029 6030 6031 #define BAR_USTRORM_INTMEM 0x400000 6032 #define BAR_CSTRORM_INTMEM 0x410000 6033 #define BAR_XSTRORM_INTMEM 0x420000 6034 #define BAR_TSTRORM_INTMEM 0x430000 6035 6036 /* for accessing the IGU in case of status block ACK */ 6037 #define BAR_IGU_INTMEM 0x440000 6038 6039 #define BAR_DOORBELL_OFFSET 0x800000 6040 6041 #define BAR_ME_REGISTER 0x450000 6042 6043 /* config_2 offset */ 6044 #define GRC_CONFIG_2_SIZE_REG 0x408 6045 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 6046 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 6047 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 6048 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 6049 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) 6050 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) 6051 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) 6052 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) 6053 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) 6054 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) 6055 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) 6056 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) 6057 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) 6058 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) 6059 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 6060 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 6061 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 6062 #define PCI_CONFIG_2_BAR1_64ENA (1L<<4) 6063 #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 6064 #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 6065 #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 6066 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 6067 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 6068 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8) 6069 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8) 6070 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8) 6071 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8) 6072 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8) 6073 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8) 6074 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8) 6075 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8) 6076 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8) 6077 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8) 6078 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8) 6079 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8) 6080 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8) 6081 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8) 6082 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8) 6083 #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16) 6084 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17) 6085 6086 /* config_3 offset */ 6087 #define GRC_CONFIG_3_SIZE_REG 0x40c 6088 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 6089 #define PCI_CONFIG_3_FORCE_PME (1L<<24) 6090 #define PCI_CONFIG_3_PME_STATUS (1L<<25) 6091 #define PCI_CONFIG_3_PME_ENABLE (1L<<26) 6092 #define PCI_CONFIG_3_PM_STATE (0x3L<<27) 6093 #define PCI_CONFIG_3_VAUX_PRESET (1L<<30) 6094 #define PCI_CONFIG_3_PCI_POWER (1L<<31) 6095 6096 #define GRC_BAR2_CONFIG 0x4e0 6097 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0) 6098 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0) 6099 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0) 6100 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0) 6101 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0) 6102 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0) 6103 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0) 6104 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0) 6105 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0) 6106 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0) 6107 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0) 6108 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0) 6109 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0) 6110 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0) 6111 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0) 6112 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0) 6113 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0) 6114 #define PCI_CONFIG_2_BAR2_64ENA (1L<<4) 6115 6116 #define PCI_PM_DATA_A 0x410 6117 #define PCI_PM_DATA_B 0x414 6118 #define PCI_ID_VAL1 0x434 6119 #define PCI_ID_VAL2 0x438 6120 6121 #define PXPCS_TL_CONTROL_5 0x814 6122 #define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/ 6123 #define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/ 6124 #define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/ 6125 #define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/ 6126 #define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/ 6127 #define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/ 6128 #define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/ 6129 #define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/ 6130 #define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/ 6131 #define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/ 6132 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/ 6133 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/ 6134 #define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/ 6135 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/ 6136 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/ 6137 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/ 6138 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/ 6139 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/ 6140 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/ 6141 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/ 6142 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/ 6143 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/ 6144 #define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/ 6145 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/ 6146 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/ 6147 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/ 6148 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/ 6149 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/ 6150 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/ 6151 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/ 6152 6153 6154 #define PXPCS_TL_FUNC345_STAT 0x854 6155 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */ 6156 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4\ 6157 (1 << 28) /* Unsupported Request Error Status in function4, if \ 6158 set, generate pcie_err_attn output when this error is seen. WC */ 6159 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC4\ 6160 (1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \ 6161 generate pcie_err_attn output when this error is seen.. WC */ 6162 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4\ 6163 (1 << 26) /* Malformed TLP Status Status in function 4, if set, \ 6164 generate pcie_err_attn output when this error is seen.. WC */ 6165 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4\ 6166 (1 << 25) /* Receiver Overflow Status Status in function 4, if \ 6167 set, generate pcie_err_attn output when this error is seen.. WC \ 6168 */ 6169 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4\ 6170 (1 << 24) /* Unexpected Completion Status Status in function 4, \ 6171 if set, generate pcie_err_attn output when this error is seen. WC \ 6172 */ 6173 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4\ 6174 (1 << 23) /* Receive UR Statusin function 4. If set, generate \ 6175 pcie_err_attn output when this error is seen. WC */ 6176 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4\ 6177 (1 << 22) /* Completer Timeout Status Status in function 4, if \ 6178 set, generate pcie_err_attn output when this error is seen. WC */ 6179 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4\ 6180 (1 << 21) /* Flow Control Protocol Error Status Status in \ 6181 function 4, if set, generate pcie_err_attn output when this error \ 6182 is seen. WC */ 6183 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4\ 6184 (1 << 20) /* Poisoned Error Status Status in function 4, if set, \ 6185 generate pcie_err_attn output when this error is seen.. WC */ 6186 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */ 6187 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3\ 6188 (1 << 18) /* Unsupported Request Error Status in function3, if \ 6189 set, generate pcie_err_attn output when this error is seen. WC */ 6190 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC3\ 6191 (1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \ 6192 generate pcie_err_attn output when this error is seen.. WC */ 6193 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3\ 6194 (1 << 16) /* Malformed TLP Status Status in function 3, if set, \ 6195 generate pcie_err_attn output when this error is seen.. WC */ 6196 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3\ 6197 (1 << 15) /* Receiver Overflow Status Status in function 3, if \ 6198 set, generate pcie_err_attn output when this error is seen.. WC \ 6199 */ 6200 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3\ 6201 (1 << 14) /* Unexpected Completion Status Status in function 3, \ 6202 if set, generate pcie_err_attn output when this error is seen. WC \ 6203 */ 6204 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3\ 6205 (1 << 13) /* Receive UR Statusin function 3. If set, generate \ 6206 pcie_err_attn output when this error is seen. WC */ 6207 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3\ 6208 (1 << 12) /* Completer Timeout Status Status in function 3, if \ 6209 set, generate pcie_err_attn output when this error is seen. WC */ 6210 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3\ 6211 (1 << 11) /* Flow Control Protocol Error Status Status in \ 6212 function 3, if set, generate pcie_err_attn output when this error \ 6213 is seen. WC */ 6214 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3\ 6215 (1 << 10) /* Poisoned Error Status Status in function 3, if set, \ 6216 generate pcie_err_attn output when this error is seen.. WC */ 6217 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */ 6218 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2\ 6219 (1 << 8) /* Unsupported Request Error Status for Function 2, if \ 6220 set, generate pcie_err_attn output when this error is seen. WC */ 6221 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC2\ 6222 (1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \ 6223 generate pcie_err_attn output when this error is seen.. WC */ 6224 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2\ 6225 (1 << 6) /* Malformed TLP Status Status for Function 2, if set, \ 6226 generate pcie_err_attn output when this error is seen.. WC */ 6227 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2\ 6228 (1 << 5) /* Receiver Overflow Status Status for Function 2, if \ 6229 set, generate pcie_err_attn output when this error is seen.. WC \ 6230 */ 6231 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2\ 6232 (1 << 4) /* Unexpected Completion Status Status for Function 2, \ 6233 if set, generate pcie_err_attn output when this error is seen. WC \ 6234 */ 6235 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2\ 6236 (1 << 3) /* Receive UR Statusfor Function 2. If set, generate \ 6237 pcie_err_attn output when this error is seen. WC */ 6238 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2\ 6239 (1 << 2) /* Completer Timeout Status Status for Function 2, if \ 6240 set, generate pcie_err_attn output when this error is seen. WC */ 6241 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2\ 6242 (1 << 1) /* Flow Control Protocol Error Status Status for \ 6243 Function 2, if set, generate pcie_err_attn output when this error \ 6244 is seen. WC */ 6245 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2\ 6246 (1 << 0) /* Poisoned Error Status Status for Function 2, if set, \ 6247 generate pcie_err_attn output when this error is seen.. WC */ 6248 6249 6250 #define PXPCS_TL_FUNC678_STAT 0x85C 6251 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */ 6252 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7\ 6253 (1 << 28) /* Unsupported Request Error Status in function7, if \ 6254 set, generate pcie_err_attn output when this error is seen. WC */ 6255 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC7\ 6256 (1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \ 6257 generate pcie_err_attn output when this error is seen.. WC */ 6258 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7\ 6259 (1 << 26) /* Malformed TLP Status Status in function 7, if set, \ 6260 generate pcie_err_attn output when this error is seen.. WC */ 6261 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7\ 6262 (1 << 25) /* Receiver Overflow Status Status in function 7, if \ 6263 set, generate pcie_err_attn output when this error is seen.. WC \ 6264 */ 6265 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7\ 6266 (1 << 24) /* Unexpected Completion Status Status in function 7, \ 6267 if set, generate pcie_err_attn output when this error is seen. WC \ 6268 */ 6269 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7\ 6270 (1 << 23) /* Receive UR Statusin function 7. If set, generate \ 6271 pcie_err_attn output when this error is seen. WC */ 6272 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7\ 6273 (1 << 22) /* Completer Timeout Status Status in function 7, if \ 6274 set, generate pcie_err_attn output when this error is seen. WC */ 6275 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7\ 6276 (1 << 21) /* Flow Control Protocol Error Status Status in \ 6277 function 7, if set, generate pcie_err_attn output when this error \ 6278 is seen. WC */ 6279 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7\ 6280 (1 << 20) /* Poisoned Error Status Status in function 7, if set, \ 6281 generate pcie_err_attn output when this error is seen.. WC */ 6282 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */ 6283 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6\ 6284 (1 << 18) /* Unsupported Request Error Status in function6, if \ 6285 set, generate pcie_err_attn output when this error is seen. WC */ 6286 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC6\ 6287 (1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \ 6288 generate pcie_err_attn output when this error is seen.. WC */ 6289 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6\ 6290 (1 << 16) /* Malformed TLP Status Status in function 6, if set, \ 6291 generate pcie_err_attn output when this error is seen.. WC */ 6292 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6\ 6293 (1 << 15) /* Receiver Overflow Status Status in function 6, if \ 6294 set, generate pcie_err_attn output when this error is seen.. WC \ 6295 */ 6296 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6\ 6297 (1 << 14) /* Unexpected Completion Status Status in function 6, \ 6298 if set, generate pcie_err_attn output when this error is seen. WC \ 6299 */ 6300 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6\ 6301 (1 << 13) /* Receive UR Statusin function 6. If set, generate \ 6302 pcie_err_attn output when this error is seen. WC */ 6303 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6\ 6304 (1 << 12) /* Completer Timeout Status Status in function 6, if \ 6305 set, generate pcie_err_attn output when this error is seen. WC */ 6306 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6\ 6307 (1 << 11) /* Flow Control Protocol Error Status Status in \ 6308 function 6, if set, generate pcie_err_attn output when this error \ 6309 is seen. WC */ 6310 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6\ 6311 (1 << 10) /* Poisoned Error Status Status in function 6, if set, \ 6312 generate pcie_err_attn output when this error is seen.. WC */ 6313 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */ 6314 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5\ 6315 (1 << 8) /* Unsupported Request Error Status for Function 5, if \ 6316 set, generate pcie_err_attn output when this error is seen. WC */ 6317 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC5\ 6318 (1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \ 6319 generate pcie_err_attn output when this error is seen.. WC */ 6320 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5\ 6321 (1 << 6) /* Malformed TLP Status Status for Function 5, if set, \ 6322 generate pcie_err_attn output when this error is seen.. WC */ 6323 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5\ 6324 (1 << 5) /* Receiver Overflow Status Status for Function 5, if \ 6325 set, generate pcie_err_attn output when this error is seen.. WC \ 6326 */ 6327 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5\ 6328 (1 << 4) /* Unexpected Completion Status Status for Function 5, \ 6329 if set, generate pcie_err_attn output when this error is seen. WC \ 6330 */ 6331 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5\ 6332 (1 << 3) /* Receive UR Statusfor Function 5. If set, generate \ 6333 pcie_err_attn output when this error is seen. WC */ 6334 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5\ 6335 (1 << 2) /* Completer Timeout Status Status for Function 5, if \ 6336 set, generate pcie_err_attn output when this error is seen. WC */ 6337 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5\ 6338 (1 << 1) /* Flow Control Protocol Error Status Status for \ 6339 Function 5, if set, generate pcie_err_attn output when this error \ 6340 is seen. WC */ 6341 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5\ 6342 (1 << 0) /* Poisoned Error Status Status for Function 5, if set, \ 6343 generate pcie_err_attn output when this error is seen.. WC */ 6344 6345 6346 #define BAR_USTRORM_INTMEM 0x400000 6347 #define BAR_CSTRORM_INTMEM 0x410000 6348 #define BAR_XSTRORM_INTMEM 0x420000 6349 #define BAR_TSTRORM_INTMEM 0x430000 6350 6351 /* for accessing the IGU in case of status block ACK */ 6352 #define BAR_IGU_INTMEM 0x440000 6353 6354 #define BAR_DOORBELL_OFFSET 0x800000 6355 6356 #define BAR_ME_REGISTER 0x450000 6357 #define ME_REG_PF_NUM_SHIFT 0 6358 #define ME_REG_PF_NUM\ 6359 (7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */ 6360 #define ME_REG_VF_VALID (1<<8) 6361 #define ME_REG_VF_NUM_SHIFT 9 6362 #define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT) 6363 #define ME_REG_VF_ERR (0x1<<3) 6364 #define ME_REG_ABS_PF_NUM_SHIFT 16 6365 #define ME_REG_ABS_PF_NUM\ 6366 (7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */ 6367 6368 6369 #define MDIO_REG_BANK_CL73_IEEEB0 0x0 6370 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0 6371 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200 6372 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000 6373 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000 6374 6375 #define MDIO_REG_BANK_CL73_IEEEB1 0x10 6376 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00 6377 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400 6378 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800 6379 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00 6380 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00 6381 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01 6382 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000 6383 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020 6384 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040 6385 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080 6386 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03 6387 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400 6388 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800 6389 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00 6390 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00 6391 6392 #define MDIO_REG_BANK_RX0 0x80b0 6393 #define MDIO_RX0_RX_STATUS 0x10 6394 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000 6395 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000 6396 #define MDIO_RX0_RX_EQ_BOOST 0x1c 6397 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6398 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10 6399 6400 #define MDIO_REG_BANK_RX1 0x80c0 6401 #define MDIO_RX1_RX_EQ_BOOST 0x1c 6402 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6403 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10 6404 6405 #define MDIO_REG_BANK_RX2 0x80d0 6406 #define MDIO_RX2_RX_EQ_BOOST 0x1c 6407 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6408 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10 6409 6410 #define MDIO_REG_BANK_RX3 0x80e0 6411 #define MDIO_RX3_RX_EQ_BOOST 0x1c 6412 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6413 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10 6414 6415 #define MDIO_REG_BANK_RX_ALL 0x80f0 6416 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c 6417 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6418 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10 6419 6420 #define MDIO_REG_BANK_TX0 0x8060 6421 #define MDIO_TX0_TX_DRIVER 0x17 6422 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 6423 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 6424 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 6425 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 6426 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 6427 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 6428 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 6429 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 6430 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 6431 6432 #define MDIO_REG_BANK_TX1 0x8070 6433 #define MDIO_TX1_TX_DRIVER 0x17 6434 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 6435 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 6436 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 6437 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 6438 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 6439 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 6440 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 6441 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 6442 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 6443 6444 #define MDIO_REG_BANK_TX2 0x8080 6445 #define MDIO_TX2_TX_DRIVER 0x17 6446 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 6447 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 6448 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 6449 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 6450 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 6451 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 6452 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 6453 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 6454 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 6455 6456 #define MDIO_REG_BANK_TX3 0x8090 6457 #define MDIO_TX3_TX_DRIVER 0x17 6458 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 6459 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 6460 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 6461 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 6462 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 6463 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 6464 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 6465 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 6466 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 6467 6468 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000 6469 #define MDIO_BLOCK0_XGXS_CONTROL 0x10 6470 6471 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010 6472 #define MDIO_BLOCK1_LANE_CTRL0 0x15 6473 #define MDIO_BLOCK1_LANE_CTRL1 0x16 6474 #define MDIO_BLOCK1_LANE_CTRL2 0x17 6475 #define MDIO_BLOCK1_LANE_PRBS 0x19 6476 6477 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100 6478 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10 6479 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000 6480 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000 6481 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11 6482 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000 6483 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14 6484 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001 6485 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010 6486 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15 6487 6488 #define MDIO_REG_BANK_GP_STATUS 0x8120 6489 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B 6490 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001 6491 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002 6492 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004 6493 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008 6494 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010 6495 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020 6496 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040 6497 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080 6498 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00 6499 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000 6500 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100 6501 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200 6502 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300 6503 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400 6504 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500 6505 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600 6506 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700 6507 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800 6508 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900 6509 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00 6510 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00 6511 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00 6512 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00 6513 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00 6514 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00 6515 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00 6516 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00 6517 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00 6518 6519 6520 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130 6521 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10 6522 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000 6523 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11 6524 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1 6525 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13 6526 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1) 6527 6528 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300 6529 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10 6530 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001 6531 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002 6532 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004 6533 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008 6534 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010 6535 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020 6536 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11 6537 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001 6538 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040 6539 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14 6540 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001 6541 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002 6542 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004 6543 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018 6544 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3 6545 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018 6546 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010 6547 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008 6548 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000 6549 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15 6550 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002 6551 #define MDIO_SERDES_DIGITAL_MISC1 0x18 6552 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000 6553 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000 6554 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000 6555 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000 6556 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000 6557 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000 6558 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010 6559 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f 6560 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000 6561 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001 6562 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002 6563 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003 6564 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004 6565 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005 6566 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006 6567 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007 6568 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008 6569 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009 6570 6571 #define MDIO_REG_BANK_OVER_1G 0x8320 6572 #define MDIO_OVER_1G_DIGCTL_3_4 0x14 6573 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0 6574 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5 6575 #define MDIO_OVER_1G_UP1 0x19 6576 #define MDIO_OVER_1G_UP1_2_5G 0x0001 6577 #define MDIO_OVER_1G_UP1_5G 0x0002 6578 #define MDIO_OVER_1G_UP1_6G 0x0004 6579 #define MDIO_OVER_1G_UP1_10G 0x0010 6580 #define MDIO_OVER_1G_UP1_10GH 0x0008 6581 #define MDIO_OVER_1G_UP1_12G 0x0020 6582 #define MDIO_OVER_1G_UP1_12_5G 0x0040 6583 #define MDIO_OVER_1G_UP1_13G 0x0080 6584 #define MDIO_OVER_1G_UP1_15G 0x0100 6585 #define MDIO_OVER_1G_UP1_16G 0x0200 6586 #define MDIO_OVER_1G_UP2 0x1A 6587 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007 6588 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038 6589 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0 6590 #define MDIO_OVER_1G_UP3 0x1B 6591 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001 6592 #define MDIO_OVER_1G_LP_UP1 0x1C 6593 #define MDIO_OVER_1G_LP_UP2 0x1D 6594 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff 6595 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780 6596 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7 6597 #define MDIO_OVER_1G_LP_UP3 0x1E 6598 6599 #define MDIO_REG_BANK_REMOTE_PHY 0x8330 6600 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10 6601 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010 6602 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600 6603 6604 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350 6605 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10 6606 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001 6607 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002 6608 6609 #define MDIO_REG_BANK_CL73_USERB0 0x8370 6610 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10 6611 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002 6612 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11 6613 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100 6614 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400 6615 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12 6616 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000 6617 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000 6618 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000 6619 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14 6620 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001 6621 6622 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0 6623 #define MDIO_AER_BLOCK_AER_REG 0x1E 6624 6625 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0 6626 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10 6627 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040 6628 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000 6629 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000 6630 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040 6631 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100 6632 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200 6633 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000 6634 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000 6635 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000 6636 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11 6637 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004 6638 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020 6639 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14 6640 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020 6641 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040 6642 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180 6643 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000 6644 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080 6645 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100 6646 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180 6647 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000 6648 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15 6649 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000 6650 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000 6651 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180 6652 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000 6653 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180 6654 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040 6655 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020 6656 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then 6657 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge. 6658 Theotherbitsarereservedandshouldbezero*/ 6659 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001 6660 6661 6662 #define MDIO_PMA_DEVAD 0x1 6663 /*ieee*/ 6664 #define MDIO_PMA_REG_CTRL 0x0 6665 #define MDIO_PMA_REG_STATUS 0x1 6666 #define MDIO_PMA_REG_10G_CTRL2 0x7 6667 #define MDIO_PMA_REG_TX_DISABLE 0x0009 6668 #define MDIO_PMA_REG_RX_SD 0xa 6669 /*bcm*/ 6670 #define MDIO_PMA_REG_BCM_CTRL 0x0096 6671 #define MDIO_PMA_REG_FEC_CTRL 0x00ab 6672 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800 6673 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808 6674 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809 6675 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02 6676 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09 6677 #define MDIO_PMA_REG_MISC_CTRL 0xca0a 6678 #define MDIO_PMA_REG_GEN_CTRL 0xca10 6679 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188 6680 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a 6681 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12 6682 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13 6683 #define MDIO_PMA_REG_ROM_VER1 0xca19 6684 #define MDIO_PMA_REG_ROM_VER2 0xca1a 6685 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b 6686 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d 6687 #define MDIO_PMA_REG_PLL_CTRL 0xca1e 6688 #define MDIO_PMA_REG_MISC_CTRL0 0xca23 6689 #define MDIO_PMA_REG_LRM_MODE 0xca3f 6690 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46 6691 #define MDIO_PMA_REG_MISC_CTRL1 0xca85 6692 6693 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000 6694 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c 6695 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000 6696 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004 6697 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008 6698 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c 6699 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002 6700 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003 6701 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820 6702 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff 6703 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01 6704 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05 6705 6706 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005 6707 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007 6708 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff 6709 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02 6710 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05 6711 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808 6712 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e 6713 #define MDIO_PMA_REG_8727_PCS_GP 0xc842 6714 #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4 6715 6716 #define MDIO_AN_REG_8727_MISC_CTRL 0x8309 6717 6718 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801 6719 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820 6720 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841 6721 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08 6722 6723 #define MDIO_PMA_REG_7101_RESET 0xc000 6724 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007 6725 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009 6726 #define MDIO_PMA_REG_7101_VER1 0xc026 6727 #define MDIO_PMA_REG_7101_VER2 0xc027 6728 6729 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811 6730 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c 6731 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f 6732 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832 6733 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834 6734 #define MDIO_PMA_REG_8481_LED5_MASK 0xa838 6735 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835 6736 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b 6737 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800 6738 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11 6739 6740 6741 #define MDIO_WIS_DEVAD 0x2 6742 /*bcm*/ 6743 #define MDIO_WIS_REG_LASI_CNTL 0x9002 6744 #define MDIO_WIS_REG_LASI_STATUS 0x9005 6745 6746 #define MDIO_PCS_DEVAD 0x3 6747 #define MDIO_PCS_REG_STATUS 0x0020 6748 #define MDIO_PCS_REG_LASI_STATUS 0x9005 6749 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000 6750 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008 6751 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A 6752 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5) 6753 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A 6754 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6) 6755 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7) 6756 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2) 6757 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028 6758 6759 6760 #define MDIO_XS_DEVAD 0x4 6761 #define MDIO_XS_PLL_SEQUENCER 0x8000 6762 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a 6763 6764 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc 6765 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc 6766 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc 6767 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec 6768 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc 6769 6770 #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA 6771 6772 #define MDIO_AN_DEVAD 0x7 6773 /*ieee*/ 6774 #define MDIO_AN_REG_CTRL 0x0000 6775 #define MDIO_AN_REG_STATUS 0x0001 6776 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020 6777 #define MDIO_AN_REG_ADV_PAUSE 0x0010 6778 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400 6779 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800 6780 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00 6781 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00 6782 #define MDIO_AN_REG_ADV 0x0011 6783 #define MDIO_AN_REG_ADV2 0x0012 6784 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013 6785 #define MDIO_AN_REG_MASTER_STATUS 0x0021 6786 /*bcm*/ 6787 #define MDIO_AN_REG_LINK_STATUS 0x8304 6788 #define MDIO_AN_REG_CL37_CL73 0x8370 6789 #define MDIO_AN_REG_CL37_AN 0xffe0 6790 #define MDIO_AN_REG_CL37_FC_LD 0xffe4 6791 #define MDIO_AN_REG_CL37_FC_LP 0xffe5 6792 6793 #define MDIO_AN_REG_8073_2_5G 0x8329 6794 #define MDIO_AN_REG_8073_BAM 0x8350 6795 6796 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020 6797 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0 6798 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1 6799 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4 6800 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6 6801 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9 6802 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5 6803 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7 6804 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8 6805 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc 6806 6807 /* BCM84823 only */ 6808 #define MDIO_CTL_DEVAD 0x1e 6809 #define MDIO_CTL_REG_84823_MEDIA 0x401a 6810 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018 6811 /* These pins configure the BCM84823 interface to MAC after reset. */ 6812 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008 6813 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010 6814 /* These pins configure the BCM84823 interface to Line after reset. */ 6815 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060 6816 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020 6817 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040 6818 /* When this pin is active high during reset, 10GBASE-T core is power 6819 * down, When it is active low the 10GBASE-T is power up 6820 */ 6821 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080 6822 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100 6823 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000 6824 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100 6825 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000 6826 #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005 6827 #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080 6828 6829 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3 6830 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080 6831 6832 /* BCM84833 only */ 6833 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a 6834 #define MDIO_84833_SUPER_ISOLATE 0x8000 6835 /* These are mailbox register set used by 84833. */ 6836 #define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005 6837 #define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006 6838 #define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007 6839 #define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008 6840 #define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009 6841 #define MDIO_84833_TOP_CFG_DATA3_REG 0x4011 6842 #define MDIO_84833_TOP_CFG_DATA4_REG 0x4012 6843 6844 /* Mailbox command set used by 84833. */ 6845 #define PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE 0x2 6846 /* Mailbox status set used by 84833. */ 6847 #define PHY84833_CMD_RECEIVED 0x0001 6848 #define PHY84833_CMD_IN_PROGRESS 0x0002 6849 #define PHY84833_CMD_COMPLETE_PASS 0x0004 6850 #define PHY84833_CMD_COMPLETE_ERROR 0x0008 6851 #define PHY84833_CMD_OPEN_FOR_CMDS 0x0010 6852 #define PHY84833_CMD_SYSTEM_BOOT 0x0020 6853 #define PHY84833_CMD_NOT_OPEN_FOR_CMDS 0x0040 6854 #define PHY84833_CMD_CLEAR_COMPLETE 0x0080 6855 #define PHY84833_CMD_OPEN_OVERRIDE 0xa5a5 6856 6857 6858 /* 84833 F/W Feature Commands */ 6859 #define PHY84833_DIAG_CMD_GET_EEE_MODE 0x27 6860 #define PHY84833_DIAG_CMD_SET_EEE_MODE 0x28 6861 6862 /* Warpcore clause 45 addressing */ 6863 #define MDIO_WC_DEVAD 0x3 6864 #define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0 6865 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7 6866 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10 6867 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11 6868 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12 6869 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000 6870 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000 6871 #define MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150 0x96 6872 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000 6873 #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e 6874 #define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010 6875 #define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015 6876 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016 6877 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017 6878 #define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061 6879 #define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071 6880 #define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081 6881 #define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091 6882 #define MDIO_WC_REG_TX0_TX_DRIVER 0x8067 6883 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04 6884 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0 6885 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08 6886 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 6887 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c 6888 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000 6889 #define MDIO_WC_REG_TX1_TX_DRIVER 0x8077 6890 #define MDIO_WC_REG_TX2_TX_DRIVER 0x8087 6891 #define MDIO_WC_REG_TX3_TX_DRIVER 0x8097 6892 #define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9 6893 #define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9 6894 #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba 6895 #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca 6896 #define MDIO_WC_REG_RX2_PCI_CTRL 0x80da 6897 #define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea 6898 #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104 6899 #define MDIO_WC_REG_XGXS_STATUS3 0x8129 6900 #define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130 6901 #define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131 6902 #define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141 6903 #define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B 6904 #define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169 6905 #define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0 6906 #define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1 6907 #define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2 6908 #define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3 6909 #define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4 6910 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE 6911 #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0 6912 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2 6913 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0 6914 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0 6915 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1 6916 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2 6917 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3 6918 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4 6919 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4 6920 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8 6921 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc 6922 #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE 6923 #define MDIO_WC_REG_DSC_SMC 0x8213 6924 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e 6925 #define MDIO_WC_REG_TX_FIR_TAP 0x82e2 6926 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00 6927 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f 6928 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04 6929 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0 6930 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a 6931 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00 6932 #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000 6933 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3 6934 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6 6935 #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7 6936 #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8 6937 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec 6938 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300 6939 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301 6940 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302 6941 #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304 6942 #define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308 6943 #define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309 6944 #define MDIO_WC_REG_DIGITAL3_UP1 0x8329 6945 #define MDIO_WC_REG_DIGITAL4_MISC3 0x833c 6946 #define MDIO_WC_REG_DIGITAL5_MISC6 0x8345 6947 #define MDIO_WC_REG_DIGITAL5_MISC7 0x8349 6948 #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e 6949 #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350 6950 #define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368 6951 #define MDIO_WC_REG_TX66_CONTROL 0x83b0 6952 #define MDIO_WC_REG_RX66_CONTROL 0x83c0 6953 #define MDIO_WC_REG_RX66_SCW0 0x83c2 6954 #define MDIO_WC_REG_RX66_SCW1 0x83c3 6955 #define MDIO_WC_REG_RX66_SCW2 0x83c4 6956 #define MDIO_WC_REG_RX66_SCW3 0x83c5 6957 #define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6 6958 #define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7 6959 #define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8 6960 #define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9 6961 #define MDIO_WC_REG_FX100_CTRL1 0x8400 6962 #define MDIO_WC_REG_FX100_CTRL3 0x8402 6963 6964 #define MDIO_WC_REG_MICROBLK_CMD 0xffc2 6965 #define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5 6966 #define MDIO_WC_REG_MICROBLK_CMD3 0xffcc 6967 6968 #define MDIO_WC_REG_AERBLK_AER 0xffde 6969 #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0 6970 #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1 6971 6972 #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A 6973 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0 6974 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4 6975 6976 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141 6977 6978 #define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f 6979 6980 /* 54618se */ 6981 #define MDIO_REG_GPHY_PHYID_LSB 0x3 6982 #define MDIO_REG_GPHY_ID_54618SE 0x5cd5 6983 #define MDIO_REG_GPHY_CL45_ADDR_REG 0xd 6984 #define MDIO_REG_GPHY_CL45_DATA_REG 0xe 6985 #define MDIO_REG_GPHY_EEE_ADV 0x3c 6986 #define MDIO_REG_GPHY_EEE_1G (0x1 << 2) 6987 #define MDIO_REG_GPHY_EEE_100 (0x1 << 1) 6988 #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e 6989 #define MDIO_REG_INTR_STATUS 0x1a 6990 #define MDIO_REG_INTR_MASK 0x1b 6991 #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1) 6992 #define MDIO_REG_GPHY_SHADOW 0x1c 6993 #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10) 6994 #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15) 6995 #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10) 6996 #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8) 6997 6998 #define IGU_FUNC_BASE 0x0400 6999 7000 #define IGU_ADDR_MSIX 0x0000 7001 #define IGU_ADDR_INT_ACK 0x0200 7002 #define IGU_ADDR_PROD_UPD 0x0201 7003 #define IGU_ADDR_ATTN_BITS_UPD 0x0202 7004 #define IGU_ADDR_ATTN_BITS_SET 0x0203 7005 #define IGU_ADDR_ATTN_BITS_CLR 0x0204 7006 #define IGU_ADDR_COALESCE_NOW 0x0205 7007 #define IGU_ADDR_SIMD_MASK 0x0206 7008 #define IGU_ADDR_SIMD_NOMASK 0x0207 7009 #define IGU_ADDR_MSI_CTL 0x0210 7010 #define IGU_ADDR_MSI_ADDR_LO 0x0211 7011 #define IGU_ADDR_MSI_ADDR_HI 0x0212 7012 #define IGU_ADDR_MSI_DATA 0x0213 7013 7014 #define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0 7015 #define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup 1 7016 #define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 2 7017 #define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup 3 7018 7019 #define COMMAND_REG_INT_ACK 0x0 7020 #define COMMAND_REG_PROD_UPD 0x4 7021 #define COMMAND_REG_ATTN_BITS_UPD 0x8 7022 #define COMMAND_REG_ATTN_BITS_SET 0xc 7023 #define COMMAND_REG_ATTN_BITS_CLR 0x10 7024 #define COMMAND_REG_COALESCE_NOW 0x14 7025 #define COMMAND_REG_SIMD_MASK 0x18 7026 #define COMMAND_REG_SIMD_NOMASK 0x1c 7027 7028 7029 #define IGU_MEM_BASE 0x0000 7030 7031 #define IGU_MEM_MSIX_BASE 0x0000 7032 #define IGU_MEM_MSIX_UPPER 0x007f 7033 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff 7034 7035 #define IGU_MEM_PBA_MSIX_BASE 0x0200 7036 #define IGU_MEM_PBA_MSIX_UPPER 0x0200 7037 7038 #define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201 7039 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff 7040 7041 #define IGU_CMD_INT_ACK_BASE 0x0400 7042 #define IGU_CMD_INT_ACK_UPPER\ 7043 (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1) 7044 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff 7045 7046 #define IGU_CMD_E2_PROD_UPD_BASE 0x0500 7047 #define IGU_CMD_E2_PROD_UPD_UPPER\ 7048 (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1) 7049 #define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f 7050 7051 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0 7052 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1 7053 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2 7054 7055 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3 7056 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4 7057 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5 7058 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6 7059 7060 #define IGU_REG_RESERVED_UPPER 0x05ff 7061 /* Fields of IGU PF CONFIGRATION REGISTER */ 7062 #define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */ 7063 #define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */ 7064 #define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */ 7065 #define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */ 7066 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */ 7067 #define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */ 7068 7069 /* Fields of IGU VF CONFIGRATION REGISTER */ 7070 #define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */ 7071 #define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */ 7072 #define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */ 7073 #define IGU_VF_CONF_PARENT_SHIFT 2 /* Parent PF */ 7074 #define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */ 7075 7076 7077 #define IGU_BC_DSB_NUM_SEGS 5 7078 #define IGU_BC_NDSB_NUM_SEGS 2 7079 #define IGU_NORM_DSB_NUM_SEGS 2 7080 #define IGU_NORM_NDSB_NUM_SEGS 1 7081 #define IGU_BC_BASE_DSB_PROD 128 7082 #define IGU_NORM_BASE_DSB_PROD 136 7083 7084 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \ 7085 [5:2] = 0; [1:0] = PF number) */ 7086 #define IGU_FID_ENCODE_IS_PF (0x1<<6) 7087 #define IGU_FID_ENCODE_IS_PF_SHIFT 6 7088 #define IGU_FID_VF_NUM_MASK (0x3f) 7089 #define IGU_FID_PF_NUM_MASK (0x7) 7090 7091 #define IGU_REG_MAPPING_MEMORY_VALID (1<<0) 7092 #define IGU_REG_MAPPING_MEMORY_VECTOR_MASK (0x3F<<1) 7093 #define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT 1 7094 #define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7) 7095 #define IGU_REG_MAPPING_MEMORY_FID_SHIFT 7 7096 7097 7098 #define CDU_REGION_NUMBER_XCM_AG 2 7099 #define CDU_REGION_NUMBER_UCM_AG 4 7100 7101 7102 /** 7103 * String-to-compress [31:8] = CID (all 24 bits) 7104 * String-to-compress [7:4] = Region 7105 * String-to-compress [3:0] = Type 7106 */ 7107 #define CDU_VALID_DATA(_cid, _region, _type)\ 7108 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf))) 7109 #define CDU_CRC8(_cid, _region, _type)\ 7110 (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff)) 7111 #define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)\ 7112 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f)) 7113 #define CDU_RSRVD_VALUE_TYPE_B(_crc, _type)\ 7114 (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7)) 7115 #define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80) 7116 7117 /****************************************************************************** 7118 * Description: 7119 * Calculates crc 8 on a word value: polynomial 0-1-2-8 7120 * Code was translated from Verilog. 7121 * Return: 7122 *****************************************************************************/ 7123 static inline u8 calc_crc8(u32 data, u8 crc) 7124 { 7125 u8 D[32]; 7126 u8 NewCRC[8]; 7127 u8 C[8]; 7128 u8 crc_res; 7129 u8 i; 7130 7131 /* split the data into 31 bits */ 7132 for (i = 0; i < 32; i++) { 7133 D[i] = (u8)(data & 1); 7134 data = data >> 1; 7135 } 7136 7137 /* split the crc into 8 bits */ 7138 for (i = 0; i < 8; i++) { 7139 C[i] = crc & 1; 7140 crc = crc >> 1; 7141 } 7142 7143 NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^ 7144 D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^ 7145 C[6] ^ C[7]; 7146 NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^ 7147 D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^ 7148 D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ 7149 C[6]; 7150 NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^ 7151 D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ 7152 C[0] ^ C[1] ^ C[4] ^ C[5]; 7153 NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^ 7154 D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^ 7155 C[1] ^ C[2] ^ C[5] ^ C[6]; 7156 NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^ 7157 D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^ 7158 C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7]; 7159 NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^ 7160 D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^ 7161 C[3] ^ C[4] ^ C[7]; 7162 NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^ 7163 D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^ 7164 C[5]; 7165 NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^ 7166 D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^ 7167 C[6]; 7168 7169 crc_res = 0; 7170 for (i = 0; i < 8; i++) 7171 crc_res |= (NewCRC[i] << i); 7172 7173 return crc_res; 7174 } 7175 7176 7177 #endif /* BNX2X_REG_H */ 7178