1 /* bnx2x_reg.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2012 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * The registers description starts with the register Access type followed 10 * by size in bits. For example [RW 32]. The access types are: 11 * R - Read only 12 * RC - Clear on read 13 * RW - Read/Write 14 * ST - Statistics register (clear on read) 15 * W - Write only 16 * WB - Wide bus register - the size is over 32 bits and it should be 17 * read/write in consecutive 32 bits accesses 18 * WR - Write Clear (write 1 to clear the bit) 19 * 20 */ 21 #ifndef BNX2X_REG_H 22 #define BNX2X_REG_H 23 24 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 25 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2) 26 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5) 27 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3) 28 #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4) 29 #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1) 30 /* [RW 1] Initiate the ATC array - reset all the valid bits */ 31 #define ATC_REG_ATC_INIT_ARRAY 0x1100b8 32 /* [R 1] ATC initalization done */ 33 #define ATC_REG_ATC_INIT_DONE 0x1100bc 34 /* [RC 6] Interrupt register #0 read clear */ 35 #define ATC_REG_ATC_INT_STS_CLR 0x1101c0 36 /* [RW 5] Parity mask register #0 read/write */ 37 #define ATC_REG_ATC_PRTY_MASK 0x1101d8 38 /* [RC 5] Parity register #0 read clear */ 39 #define ATC_REG_ATC_PRTY_STS_CLR 0x1101d0 40 /* [RW 19] Interrupt mask register #0 read/write */ 41 #define BRB1_REG_BRB1_INT_MASK 0x60128 42 /* [R 19] Interrupt register #0 read */ 43 #define BRB1_REG_BRB1_INT_STS 0x6011c 44 /* [RW 4] Parity mask register #0 read/write */ 45 #define BRB1_REG_BRB1_PRTY_MASK 0x60138 46 /* [R 4] Parity register #0 read */ 47 #define BRB1_REG_BRB1_PRTY_STS 0x6012c 48 /* [RC 4] Parity register #0 read clear */ 49 #define BRB1_REG_BRB1_PRTY_STS_CLR 0x60130 50 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At 51 * address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address 52 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning - 53 * following reset the first rbc access to this reg must be write; there can 54 * be no more rbc writes after the first one; there can be any number of rbc 55 * read following the first write; rbc access not following these rules will 56 * result in hang condition. */ 57 #define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200 58 /* [RW 10] The number of free blocks below which the full signal to class 0 59 * is asserted */ 60 #define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 0x601d0 61 #define BRB1_REG_FULL_0_XOFF_THRESHOLD_1 0x60230 62 /* [RW 11] The number of free blocks above which the full signal to class 0 63 * is de-asserted */ 64 #define BRB1_REG_FULL_0_XON_THRESHOLD_0 0x601d4 65 #define BRB1_REG_FULL_0_XON_THRESHOLD_1 0x60234 66 /* [RW 11] The number of free blocks below which the full signal to class 1 67 * is asserted */ 68 #define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 0x601d8 69 #define BRB1_REG_FULL_1_XOFF_THRESHOLD_1 0x60238 70 /* [RW 11] The number of free blocks above which the full signal to class 1 71 * is de-asserted */ 72 #define BRB1_REG_FULL_1_XON_THRESHOLD_0 0x601dc 73 #define BRB1_REG_FULL_1_XON_THRESHOLD_1 0x6023c 74 /* [RW 11] The number of free blocks below which the full signal to the LB 75 * port is asserted */ 76 #define BRB1_REG_FULL_LB_XOFF_THRESHOLD 0x601e0 77 /* [RW 10] The number of free blocks above which the full signal to the LB 78 * port is de-asserted */ 79 #define BRB1_REG_FULL_LB_XON_THRESHOLD 0x601e4 80 /* [RW 10] The number of free blocks above which the High_llfc signal to 81 interface #n is de-asserted. */ 82 #define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c 83 /* [RW 10] The number of free blocks below which the High_llfc signal to 84 interface #n is asserted. */ 85 #define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c 86 /* [RW 11] The number of blocks guarantied for the LB port */ 87 #define BRB1_REG_LB_GUARANTIED 0x601ec 88 /* [RW 11] The hysteresis on the guarantied buffer space for the Lb port 89 * before signaling XON. */ 90 #define BRB1_REG_LB_GUARANTIED_HYST 0x60264 91 /* [RW 24] LL RAM data. */ 92 #define BRB1_REG_LL_RAM 0x61000 93 /* [RW 10] The number of free blocks above which the Low_llfc signal to 94 interface #n is de-asserted. */ 95 #define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c 96 /* [RW 10] The number of free blocks below which the Low_llfc signal to 97 interface #n is asserted. */ 98 #define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c 99 /* [RW 11] The number of blocks guarantied for class 0 in MAC 0. The 100 * register is applicable only when per_class_guaranty_mode is set. */ 101 #define BRB1_REG_MAC_0_CLASS_0_GUARANTIED 0x60244 102 /* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC 103 * 1 before signaling XON. The register is applicable only when 104 * per_class_guaranty_mode is set. */ 105 #define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST 0x60254 106 /* [RW 11] The number of blocks guarantied for class 1 in MAC 0. The 107 * register is applicable only when per_class_guaranty_mode is set. */ 108 #define BRB1_REG_MAC_0_CLASS_1_GUARANTIED 0x60248 109 /* [RW 11] The hysteresis on the guarantied buffer space for class 1in MAC 0 110 * before signaling XON. The register is applicable only when 111 * per_class_guaranty_mode is set. */ 112 #define BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST 0x60258 113 /* [RW 11] The number of blocks guarantied for class 0in MAC1.The register 114 * is applicable only when per_class_guaranty_mode is set. */ 115 #define BRB1_REG_MAC_1_CLASS_0_GUARANTIED 0x6024c 116 /* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC 117 * 1 before signaling XON. The register is applicable only when 118 * per_class_guaranty_mode is set. */ 119 #define BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST 0x6025c 120 /* [RW 11] The number of blocks guarantied for class 1 in MAC 1. The 121 * register is applicable only when per_class_guaranty_mode is set. */ 122 #define BRB1_REG_MAC_1_CLASS_1_GUARANTIED 0x60250 123 /* [RW 11] The hysteresis on the guarantied buffer space for class 1 in MAC 124 * 1 before signaling XON. The register is applicable only when 125 * per_class_guaranty_mode is set. */ 126 #define BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST 0x60260 127 /* [RW 11] The number of blocks guarantied for the MAC port. The register is 128 * applicable only when per_class_guaranty_mode is reset. */ 129 #define BRB1_REG_MAC_GUARANTIED_0 0x601e8 130 #define BRB1_REG_MAC_GUARANTIED_1 0x60240 131 /* [R 24] The number of full blocks. */ 132 #define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090 133 /* [ST 32] The number of cycles that the write_full signal towards MAC #0 134 was asserted. */ 135 #define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8 136 #define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc 137 #define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8 138 /* [ST 32] The number of cycles that the pause signal towards MAC #0 was 139 asserted. */ 140 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8 141 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc 142 /* [RW 10] The number of free blocks below which the pause signal to class 0 143 * is asserted */ 144 #define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 0x601c0 145 #define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 0x60220 146 /* [RW 11] The number of free blocks above which the pause signal to class 0 147 * is de-asserted */ 148 #define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 0x601c4 149 #define BRB1_REG_PAUSE_0_XON_THRESHOLD_1 0x60224 150 /* [RW 11] The number of free blocks below which the pause signal to class 1 151 * is asserted */ 152 #define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 0x601c8 153 #define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 0x60228 154 /* [RW 11] The number of free blocks above which the pause signal to class 1 155 * is de-asserted */ 156 #define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 0x601cc 157 #define BRB1_REG_PAUSE_1_XON_THRESHOLD_1 0x6022c 158 /* [RW 10] Write client 0: De-assert pause threshold. Not Functional */ 159 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078 160 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c 161 /* [RW 10] Write client 0: Assert pause threshold. */ 162 #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068 163 /* [RW 1] Indicates if to use per-class guaranty mode (new mode) or per-MAC 164 * guaranty mode (backwards-compatible mode). 0=per-MAC guaranty mode (BC 165 * mode). 1=per-class guaranty mode (new mode). */ 166 #define BRB1_REG_PER_CLASS_GUARANTY_MODE 0x60268 167 /* [R 24] The number of full blocks occpied by port. */ 168 #define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094 169 /* [RW 1] Reset the design by software. */ 170 #define BRB1_REG_SOFT_RESET 0x600dc 171 /* [R 5] Used to read the value of the XX protection CAM occupancy counter. */ 172 #define CCM_REG_CAM_OCCUP 0xd0188 173 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 174 acknowledge output is deasserted; all other signals are treated as usual; 175 if 1 - normal activity. */ 176 #define CCM_REG_CCM_CFC_IFEN 0xd003c 177 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 178 disregarded; valid is deasserted; all other signals are treated as usual; 179 if 1 - normal activity. */ 180 #define CCM_REG_CCM_CQM_IFEN 0xd000c 181 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. 182 Otherwise 0 is inserted. */ 183 #define CCM_REG_CCM_CQM_USE_Q 0xd00c0 184 /* [RW 11] Interrupt mask register #0 read/write */ 185 #define CCM_REG_CCM_INT_MASK 0xd01e4 186 /* [R 11] Interrupt register #0 read */ 187 #define CCM_REG_CCM_INT_STS 0xd01d8 188 /* [RW 27] Parity mask register #0 read/write */ 189 #define CCM_REG_CCM_PRTY_MASK 0xd01f4 190 /* [R 27] Parity register #0 read */ 191 #define CCM_REG_CCM_PRTY_STS 0xd01e8 192 /* [RC 27] Parity register #0 read clear */ 193 #define CCM_REG_CCM_PRTY_STS_CLR 0xd01ec 194 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS 195 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 196 Is used to determine the number of the AG context REG-pairs written back; 197 when the input message Reg1WbFlg isn't set. */ 198 #define CCM_REG_CCM_REG0_SZ 0xd00c4 199 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 200 disregarded; valid is deasserted; all other signals are treated as usual; 201 if 1 - normal activity. */ 202 #define CCM_REG_CCM_STORM0_IFEN 0xd0004 203 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 204 disregarded; valid is deasserted; all other signals are treated as usual; 205 if 1 - normal activity. */ 206 #define CCM_REG_CCM_STORM1_IFEN 0xd0008 207 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is 208 disregarded; valid output is deasserted; all other signals are treated as 209 usual; if 1 - normal activity. */ 210 #define CCM_REG_CDU_AG_RD_IFEN 0xd0030 211 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 212 are disregarded; all other signals are treated as usual; if 1 - normal 213 activity. */ 214 #define CCM_REG_CDU_AG_WR_IFEN 0xd002c 215 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 216 disregarded; valid output is deasserted; all other signals are treated as 217 usual; if 1 - normal activity. */ 218 #define CCM_REG_CDU_SM_RD_IFEN 0xd0038 219 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 220 input is disregarded; all other signals are treated as usual; if 1 - 221 normal activity. */ 222 #define CCM_REG_CDU_SM_WR_IFEN 0xd0034 223 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 224 the initial credit value; read returns the current value of the credit 225 counter. Must be initialized to 1 at start-up. */ 226 #define CCM_REG_CFC_INIT_CRD 0xd0204 227 /* [RW 2] Auxiliary counter flag Q number 1. */ 228 #define CCM_REG_CNT_AUX1_Q 0xd00c8 229 /* [RW 2] Auxiliary counter flag Q number 2. */ 230 #define CCM_REG_CNT_AUX2_Q 0xd00cc 231 /* [RW 28] The CM header value for QM request (primary). */ 232 #define CCM_REG_CQM_CCM_HDR_P 0xd008c 233 /* [RW 28] The CM header value for QM request (secondary). */ 234 #define CCM_REG_CQM_CCM_HDR_S 0xd0090 235 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 236 acknowledge output is deasserted; all other signals are treated as usual; 237 if 1 - normal activity. */ 238 #define CCM_REG_CQM_CCM_IFEN 0xd0014 239 /* [RW 6] QM output initial credit. Max credit available - 32. Write writes 240 the initial credit value; read returns the current value of the credit 241 counter. Must be initialized to 32 at start-up. */ 242 #define CCM_REG_CQM_INIT_CRD 0xd020c 243 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 244 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 245 prioritised); 2 stands for weight 2; tc. */ 246 #define CCM_REG_CQM_P_WEIGHT 0xd00b8 247 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 248 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 249 prioritised); 2 stands for weight 2; tc. */ 250 #define CCM_REG_CQM_S_WEIGHT 0xd00bc 251 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 252 acknowledge output is deasserted; all other signals are treated as usual; 253 if 1 - normal activity. */ 254 #define CCM_REG_CSDM_IFEN 0xd0018 255 /* [RC 1] Set when the message length mismatch (relative to last indication) 256 at the SDM interface is detected. */ 257 #define CCM_REG_CSDM_LENGTH_MIS 0xd0170 258 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for 259 weight 8 (the most prioritised); 1 stands for weight 1(least 260 prioritised); 2 stands for weight 2; tc. */ 261 #define CCM_REG_CSDM_WEIGHT 0xd00b4 262 /* [RW 28] The CM header for QM formatting in case of an error in the QM 263 inputs. */ 264 #define CCM_REG_ERR_CCM_HDR 0xd0094 265 /* [RW 8] The Event ID in case the input message ErrorFlg is set. */ 266 #define CCM_REG_ERR_EVNT_ID 0xd0098 267 /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write 268 writes the initial credit value; read returns the current value of the 269 credit counter. Must be initialized to 64 at start-up. */ 270 #define CCM_REG_FIC0_INIT_CRD 0xd0210 271 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 272 writes the initial credit value; read returns the current value of the 273 credit counter. Must be initialized to 64 at start-up. */ 274 #define CCM_REG_FIC1_INIT_CRD 0xd0214 275 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 276 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr; 277 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and 278 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and 279 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */ 280 #define CCM_REG_GR_ARB_TYPE 0xd015c 281 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 282 highest priority is 3. It is supposed; that the Store channel priority is 283 the compliment to 4 of the rest priorities - Aggregation channel; Load 284 (FIC0) channel and Load (FIC1). */ 285 #define CCM_REG_GR_LD0_PR 0xd0164 286 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 287 highest priority is 3. It is supposed; that the Store channel priority is 288 the compliment to 4 of the rest priorities - Aggregation channel; Load 289 (FIC0) channel and Load (FIC1). */ 290 #define CCM_REG_GR_LD1_PR 0xd0168 291 /* [RW 2] General flags index. */ 292 #define CCM_REG_INV_DONE_Q 0xd0108 293 /* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM 294 context and sent to STORM; for a specific connection type. The double 295 REG-pairs are used in order to align to STORM context row size of 128 296 bits. The offset of these data in the STORM context is always 0. Index 297 _(0..15) stands for the connection type (one of 16). */ 298 #define CCM_REG_N_SM_CTX_LD_0 0xd004c 299 #define CCM_REG_N_SM_CTX_LD_1 0xd0050 300 #define CCM_REG_N_SM_CTX_LD_2 0xd0054 301 #define CCM_REG_N_SM_CTX_LD_3 0xd0058 302 #define CCM_REG_N_SM_CTX_LD_4 0xd005c 303 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; 304 acknowledge output is deasserted; all other signals are treated as usual; 305 if 1 - normal activity. */ 306 #define CCM_REG_PBF_IFEN 0xd0028 307 /* [RC 1] Set when the message length mismatch (relative to last indication) 308 at the pbf interface is detected. */ 309 #define CCM_REG_PBF_LENGTH_MIS 0xd0180 310 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for 311 weight 8 (the most prioritised); 1 stands for weight 1(least 312 prioritised); 2 stands for weight 2; tc. */ 313 #define CCM_REG_PBF_WEIGHT 0xd00ac 314 #define CCM_REG_PHYS_QNUM1_0 0xd0134 315 #define CCM_REG_PHYS_QNUM1_1 0xd0138 316 #define CCM_REG_PHYS_QNUM2_0 0xd013c 317 #define CCM_REG_PHYS_QNUM2_1 0xd0140 318 #define CCM_REG_PHYS_QNUM3_0 0xd0144 319 #define CCM_REG_PHYS_QNUM3_1 0xd0148 320 #define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114 321 #define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118 322 #define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c 323 #define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120 324 #define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124 325 #define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128 326 #define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c 327 #define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130 328 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 329 disregarded; acknowledge output is deasserted; all other signals are 330 treated as usual; if 1 - normal activity. */ 331 #define CCM_REG_STORM_CCM_IFEN 0xd0010 332 /* [RC 1] Set when the message length mismatch (relative to last indication) 333 at the STORM interface is detected. */ 334 #define CCM_REG_STORM_LENGTH_MIS 0xd016c 335 /* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin) 336 mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for 337 weight 1(least prioritised); 2 stands for weight 2 (more prioritised); 338 tc. */ 339 #define CCM_REG_STORM_WEIGHT 0xd009c 340 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is 341 disregarded; acknowledge output is deasserted; all other signals are 342 treated as usual; if 1 - normal activity. */ 343 #define CCM_REG_TSEM_IFEN 0xd001c 344 /* [RC 1] Set when the message length mismatch (relative to last indication) 345 at the tsem interface is detected. */ 346 #define CCM_REG_TSEM_LENGTH_MIS 0xd0174 347 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for 348 weight 8 (the most prioritised); 1 stands for weight 1(least 349 prioritised); 2 stands for weight 2; tc. */ 350 #define CCM_REG_TSEM_WEIGHT 0xd00a0 351 /* [RW 1] Input usem Interface enable. If 0 - the valid input is 352 disregarded; acknowledge output is deasserted; all other signals are 353 treated as usual; if 1 - normal activity. */ 354 #define CCM_REG_USEM_IFEN 0xd0024 355 /* [RC 1] Set when message length mismatch (relative to last indication) at 356 the usem interface is detected. */ 357 #define CCM_REG_USEM_LENGTH_MIS 0xd017c 358 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for 359 weight 8 (the most prioritised); 1 stands for weight 1(least 360 prioritised); 2 stands for weight 2; tc. */ 361 #define CCM_REG_USEM_WEIGHT 0xd00a8 362 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is 363 disregarded; acknowledge output is deasserted; all other signals are 364 treated as usual; if 1 - normal activity. */ 365 #define CCM_REG_XSEM_IFEN 0xd0020 366 /* [RC 1] Set when the message length mismatch (relative to last indication) 367 at the xsem interface is detected. */ 368 #define CCM_REG_XSEM_LENGTH_MIS 0xd0178 369 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for 370 weight 8 (the most prioritised); 1 stands for weight 1(least 371 prioritised); 2 stands for weight 2; tc. */ 372 #define CCM_REG_XSEM_WEIGHT 0xd00a4 373 /* [RW 19] Indirect access to the descriptor table of the XX protection 374 mechanism. The fields are: [5:0] - message length; [12:6] - message 375 pointer; 18:13] - next pointer. */ 376 #define CCM_REG_XX_DESCR_TABLE 0xd0300 377 #define CCM_REG_XX_DESCR_TABLE_SIZE 24 378 /* [R 7] Used to read the value of XX protection Free counter. */ 379 #define CCM_REG_XX_FREE 0xd0184 380 /* [RW 6] Initial value for the credit counter; responsible for fulfilling 381 of the Input Stage XX protection buffer by the XX protection pending 382 messages. Max credit available - 127. Write writes the initial credit 383 value; read returns the current value of the credit counter. Must be 384 initialized to maximum XX protected message size - 2 at start-up. */ 385 #define CCM_REG_XX_INIT_CRD 0xd0220 386 /* [RW 7] The maximum number of pending messages; which may be stored in XX 387 protection. At read the ~ccm_registers_xx_free.xx_free counter is read. 388 At write comprises the start value of the ~ccm_registers_xx_free.xx_free 389 counter. */ 390 #define CCM_REG_XX_MSG_NUM 0xd0224 391 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 392 #define CCM_REG_XX_OVFL_EVNT_ID 0xd0044 393 /* [RW 18] Indirect access to the XX table of the XX protection mechanism. 394 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] - 395 header pointer. */ 396 #define CCM_REG_XX_TABLE 0xd0280 397 #define CDU_REG_CDU_CHK_MASK0 0x101000 398 #define CDU_REG_CDU_CHK_MASK1 0x101004 399 #define CDU_REG_CDU_CONTROL0 0x101008 400 #define CDU_REG_CDU_DEBUG 0x101010 401 #define CDU_REG_CDU_GLOBAL_PARAMS 0x101020 402 /* [RW 7] Interrupt mask register #0 read/write */ 403 #define CDU_REG_CDU_INT_MASK 0x10103c 404 /* [R 7] Interrupt register #0 read */ 405 #define CDU_REG_CDU_INT_STS 0x101030 406 /* [RW 5] Parity mask register #0 read/write */ 407 #define CDU_REG_CDU_PRTY_MASK 0x10104c 408 /* [R 5] Parity register #0 read */ 409 #define CDU_REG_CDU_PRTY_STS 0x101040 410 /* [RC 5] Parity register #0 read clear */ 411 #define CDU_REG_CDU_PRTY_STS_CLR 0x101044 412 /* [RC 32] logging of error data in case of a CDU load error: 413 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error; 414 ype_error; ctual_active; ctual_compressed_context}; */ 415 #define CDU_REG_ERROR_DATA 0x101014 416 /* [WB 216] L1TT ram access. each entry has the following format : 417 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0]; 418 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */ 419 #define CDU_REG_L1TT 0x101800 420 /* [WB 24] MATT ram access. each entry has the following 421 format:{RegionLength[11:0]; egionOffset[11:0]} */ 422 #define CDU_REG_MATT 0x101100 423 /* [RW 1] when this bit is set the CDU operates in e1hmf mode */ 424 #define CDU_REG_MF_MODE 0x101050 425 /* [R 1] indication the initializing the activity counter by the hardware 426 was done. */ 427 #define CFC_REG_AC_INIT_DONE 0x104078 428 /* [RW 13] activity counter ram access */ 429 #define CFC_REG_ACTIVITY_COUNTER 0x104400 430 #define CFC_REG_ACTIVITY_COUNTER_SIZE 256 431 /* [R 1] indication the initializing the cams by the hardware was done. */ 432 #define CFC_REG_CAM_INIT_DONE 0x10407c 433 /* [RW 2] Interrupt mask register #0 read/write */ 434 #define CFC_REG_CFC_INT_MASK 0x104108 435 /* [R 2] Interrupt register #0 read */ 436 #define CFC_REG_CFC_INT_STS 0x1040fc 437 /* [RC 2] Interrupt register #0 read clear */ 438 #define CFC_REG_CFC_INT_STS_CLR 0x104100 439 /* [RW 4] Parity mask register #0 read/write */ 440 #define CFC_REG_CFC_PRTY_MASK 0x104118 441 /* [R 4] Parity register #0 read */ 442 #define CFC_REG_CFC_PRTY_STS 0x10410c 443 /* [RC 4] Parity register #0 read clear */ 444 #define CFC_REG_CFC_PRTY_STS_CLR 0x104110 445 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */ 446 #define CFC_REG_CID_CAM 0x104800 447 #define CFC_REG_CONTROL0 0x104028 448 #define CFC_REG_DEBUG0 0x104050 449 /* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error 450 vector) whether the cfc should be disabled upon it */ 451 #define CFC_REG_DISABLE_ON_ERROR 0x104044 452 /* [RC 14] CFC error vector. when the CFC detects an internal error it will 453 set one of these bits. the bit description can be found in CFC 454 specifications */ 455 #define CFC_REG_ERROR_VECTOR 0x10403c 456 /* [WB 93] LCID info ram access */ 457 #define CFC_REG_INFO_RAM 0x105000 458 #define CFC_REG_INFO_RAM_SIZE 1024 459 #define CFC_REG_INIT_REG 0x10404c 460 #define CFC_REG_INTERFACES 0x104058 461 /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this 462 field allows changing the priorities of the weighted-round-robin arbiter 463 which selects which CFC load client should be served next */ 464 #define CFC_REG_LCREQ_WEIGHTS 0x104084 465 /* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */ 466 #define CFC_REG_LINK_LIST 0x104c00 467 #define CFC_REG_LINK_LIST_SIZE 256 468 /* [R 1] indication the initializing the link list by the hardware was done. */ 469 #define CFC_REG_LL_INIT_DONE 0x104074 470 /* [R 9] Number of allocated LCIDs which are at empty state */ 471 #define CFC_REG_NUM_LCIDS_ALLOC 0x104020 472 /* [R 9] Number of Arriving LCIDs in Link List Block */ 473 #define CFC_REG_NUM_LCIDS_ARRIVING 0x104004 474 #define CFC_REG_NUM_LCIDS_INSIDE_PF 0x104120 475 /* [R 9] Number of Leaving LCIDs in Link List Block */ 476 #define CFC_REG_NUM_LCIDS_LEAVING 0x104018 477 #define CFC_REG_WEAK_ENABLE_PF 0x104124 478 /* [RW 8] The event id for aggregated interrupt 0 */ 479 #define CSDM_REG_AGG_INT_EVENT_0 0xc2038 480 #define CSDM_REG_AGG_INT_EVENT_10 0xc2060 481 #define CSDM_REG_AGG_INT_EVENT_11 0xc2064 482 #define CSDM_REG_AGG_INT_EVENT_12 0xc2068 483 #define CSDM_REG_AGG_INT_EVENT_13 0xc206c 484 #define CSDM_REG_AGG_INT_EVENT_14 0xc2070 485 #define CSDM_REG_AGG_INT_EVENT_15 0xc2074 486 #define CSDM_REG_AGG_INT_EVENT_16 0xc2078 487 #define CSDM_REG_AGG_INT_EVENT_2 0xc2040 488 #define CSDM_REG_AGG_INT_EVENT_3 0xc2044 489 #define CSDM_REG_AGG_INT_EVENT_4 0xc2048 490 #define CSDM_REG_AGG_INT_EVENT_5 0xc204c 491 #define CSDM_REG_AGG_INT_EVENT_6 0xc2050 492 #define CSDM_REG_AGG_INT_EVENT_7 0xc2054 493 #define CSDM_REG_AGG_INT_EVENT_8 0xc2058 494 #define CSDM_REG_AGG_INT_EVENT_9 0xc205c 495 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0) 496 or auto-mask-mode (1) */ 497 #define CSDM_REG_AGG_INT_MODE_10 0xc21e0 498 #define CSDM_REG_AGG_INT_MODE_11 0xc21e4 499 #define CSDM_REG_AGG_INT_MODE_12 0xc21e8 500 #define CSDM_REG_AGG_INT_MODE_13 0xc21ec 501 #define CSDM_REG_AGG_INT_MODE_14 0xc21f0 502 #define CSDM_REG_AGG_INT_MODE_15 0xc21f4 503 #define CSDM_REG_AGG_INT_MODE_16 0xc21f8 504 #define CSDM_REG_AGG_INT_MODE_6 0xc21d0 505 #define CSDM_REG_AGG_INT_MODE_7 0xc21d4 506 #define CSDM_REG_AGG_INT_MODE_8 0xc21d8 507 #define CSDM_REG_AGG_INT_MODE_9 0xc21dc 508 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 509 #define CSDM_REG_CFC_RSP_START_ADDR 0xc2008 510 /* [RW 16] The maximum value of the completion counter #0 */ 511 #define CSDM_REG_CMP_COUNTER_MAX0 0xc201c 512 /* [RW 16] The maximum value of the completion counter #1 */ 513 #define CSDM_REG_CMP_COUNTER_MAX1 0xc2020 514 /* [RW 16] The maximum value of the completion counter #2 */ 515 #define CSDM_REG_CMP_COUNTER_MAX2 0xc2024 516 /* [RW 16] The maximum value of the completion counter #3 */ 517 #define CSDM_REG_CMP_COUNTER_MAX3 0xc2028 518 /* [RW 13] The start address in the internal RAM for the completion 519 counters. */ 520 #define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c 521 /* [RW 32] Interrupt mask register #0 read/write */ 522 #define CSDM_REG_CSDM_INT_MASK_0 0xc229c 523 #define CSDM_REG_CSDM_INT_MASK_1 0xc22ac 524 /* [R 32] Interrupt register #0 read */ 525 #define CSDM_REG_CSDM_INT_STS_0 0xc2290 526 #define CSDM_REG_CSDM_INT_STS_1 0xc22a0 527 /* [RW 11] Parity mask register #0 read/write */ 528 #define CSDM_REG_CSDM_PRTY_MASK 0xc22bc 529 /* [R 11] Parity register #0 read */ 530 #define CSDM_REG_CSDM_PRTY_STS 0xc22b0 531 /* [RC 11] Parity register #0 read clear */ 532 #define CSDM_REG_CSDM_PRTY_STS_CLR 0xc22b4 533 #define CSDM_REG_ENABLE_IN1 0xc2238 534 #define CSDM_REG_ENABLE_IN2 0xc223c 535 #define CSDM_REG_ENABLE_OUT1 0xc2240 536 #define CSDM_REG_ENABLE_OUT2 0xc2244 537 /* [RW 4] The initial number of messages that can be sent to the pxp control 538 interface without receiving any ACK. */ 539 #define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc 540 /* [ST 32] The number of ACK after placement messages received */ 541 #define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c 542 /* [ST 32] The number of packet end messages received from the parser */ 543 #define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274 544 /* [ST 32] The number of requests received from the pxp async if */ 545 #define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278 546 /* [ST 32] The number of commands received in queue 0 */ 547 #define CSDM_REG_NUM_OF_Q0_CMD 0xc2248 548 /* [ST 32] The number of commands received in queue 10 */ 549 #define CSDM_REG_NUM_OF_Q10_CMD 0xc226c 550 /* [ST 32] The number of commands received in queue 11 */ 551 #define CSDM_REG_NUM_OF_Q11_CMD 0xc2270 552 /* [ST 32] The number of commands received in queue 1 */ 553 #define CSDM_REG_NUM_OF_Q1_CMD 0xc224c 554 /* [ST 32] The number of commands received in queue 3 */ 555 #define CSDM_REG_NUM_OF_Q3_CMD 0xc2250 556 /* [ST 32] The number of commands received in queue 4 */ 557 #define CSDM_REG_NUM_OF_Q4_CMD 0xc2254 558 /* [ST 32] The number of commands received in queue 5 */ 559 #define CSDM_REG_NUM_OF_Q5_CMD 0xc2258 560 /* [ST 32] The number of commands received in queue 6 */ 561 #define CSDM_REG_NUM_OF_Q6_CMD 0xc225c 562 /* [ST 32] The number of commands received in queue 7 */ 563 #define CSDM_REG_NUM_OF_Q7_CMD 0xc2260 564 /* [ST 32] The number of commands received in queue 8 */ 565 #define CSDM_REG_NUM_OF_Q8_CMD 0xc2264 566 /* [ST 32] The number of commands received in queue 9 */ 567 #define CSDM_REG_NUM_OF_Q9_CMD 0xc2268 568 /* [RW 13] The start address in the internal RAM for queue counters */ 569 #define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010 570 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 571 #define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548 572 /* [R 1] parser fifo empty in sdm_sync block */ 573 #define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550 574 /* [R 1] parser serial fifo empty in sdm_sync block */ 575 #define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558 576 /* [RW 32] Tick for timer counter. Applicable only when 577 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */ 578 #define CSDM_REG_TIMER_TICK 0xc2000 579 /* [RW 5] The number of time_slots in the arbitration cycle */ 580 #define CSEM_REG_ARB_CYCLE_SIZE 0x200034 581 /* [RW 3] The source that is associated with arbitration element 0. Source 582 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 583 sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 584 #define CSEM_REG_ARB_ELEMENT0 0x200020 585 /* [RW 3] The source that is associated with arbitration element 1. Source 586 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 587 sleeping thread with priority 1; 4- sleeping thread with priority 2. 588 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */ 589 #define CSEM_REG_ARB_ELEMENT1 0x200024 590 /* [RW 3] The source that is associated with arbitration element 2. Source 591 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 592 sleeping thread with priority 1; 4- sleeping thread with priority 2. 593 Could not be equal to register ~csem_registers_arb_element0.arb_element0 594 and ~csem_registers_arb_element1.arb_element1 */ 595 #define CSEM_REG_ARB_ELEMENT2 0x200028 596 /* [RW 3] The source that is associated with arbitration element 3. Source 597 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 598 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 599 not be equal to register ~csem_registers_arb_element0.arb_element0 and 600 ~csem_registers_arb_element1.arb_element1 and 601 ~csem_registers_arb_element2.arb_element2 */ 602 #define CSEM_REG_ARB_ELEMENT3 0x20002c 603 /* [RW 3] The source that is associated with arbitration element 4. Source 604 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 605 sleeping thread with priority 1; 4- sleeping thread with priority 2. 606 Could not be equal to register ~csem_registers_arb_element0.arb_element0 607 and ~csem_registers_arb_element1.arb_element1 and 608 ~csem_registers_arb_element2.arb_element2 and 609 ~csem_registers_arb_element3.arb_element3 */ 610 #define CSEM_REG_ARB_ELEMENT4 0x200030 611 /* [RW 32] Interrupt mask register #0 read/write */ 612 #define CSEM_REG_CSEM_INT_MASK_0 0x200110 613 #define CSEM_REG_CSEM_INT_MASK_1 0x200120 614 /* [R 32] Interrupt register #0 read */ 615 #define CSEM_REG_CSEM_INT_STS_0 0x200104 616 #define CSEM_REG_CSEM_INT_STS_1 0x200114 617 /* [RW 32] Parity mask register #0 read/write */ 618 #define CSEM_REG_CSEM_PRTY_MASK_0 0x200130 619 #define CSEM_REG_CSEM_PRTY_MASK_1 0x200140 620 /* [R 32] Parity register #0 read */ 621 #define CSEM_REG_CSEM_PRTY_STS_0 0x200124 622 #define CSEM_REG_CSEM_PRTY_STS_1 0x200134 623 /* [RC 32] Parity register #0 read clear */ 624 #define CSEM_REG_CSEM_PRTY_STS_CLR_0 0x200128 625 #define CSEM_REG_CSEM_PRTY_STS_CLR_1 0x200138 626 #define CSEM_REG_ENABLE_IN 0x2000a4 627 #define CSEM_REG_ENABLE_OUT 0x2000a8 628 /* [RW 32] This address space contains all registers and memories that are 629 placed in SEM_FAST block. The SEM_FAST registers are described in 630 appendix B. In order to access the sem_fast registers the base address 631 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 632 #define CSEM_REG_FAST_MEMORY 0x220000 633 /* [RW 1] Disables input messages from FIC0 May be updated during run_time 634 by the microcode */ 635 #define CSEM_REG_FIC0_DISABLE 0x200224 636 /* [RW 1] Disables input messages from FIC1 May be updated during run_time 637 by the microcode */ 638 #define CSEM_REG_FIC1_DISABLE 0x200234 639 /* [RW 15] Interrupt table Read and write access to it is not possible in 640 the middle of the work */ 641 #define CSEM_REG_INT_TABLE 0x200400 642 /* [ST 24] Statistics register. The number of messages that entered through 643 FIC0 */ 644 #define CSEM_REG_MSG_NUM_FIC0 0x200000 645 /* [ST 24] Statistics register. The number of messages that entered through 646 FIC1 */ 647 #define CSEM_REG_MSG_NUM_FIC1 0x200004 648 /* [ST 24] Statistics register. The number of messages that were sent to 649 FOC0 */ 650 #define CSEM_REG_MSG_NUM_FOC0 0x200008 651 /* [ST 24] Statistics register. The number of messages that were sent to 652 FOC1 */ 653 #define CSEM_REG_MSG_NUM_FOC1 0x20000c 654 /* [ST 24] Statistics register. The number of messages that were sent to 655 FOC2 */ 656 #define CSEM_REG_MSG_NUM_FOC2 0x200010 657 /* [ST 24] Statistics register. The number of messages that were sent to 658 FOC3 */ 659 #define CSEM_REG_MSG_NUM_FOC3 0x200014 660 /* [RW 1] Disables input messages from the passive buffer May be updated 661 during run_time by the microcode */ 662 #define CSEM_REG_PAS_DISABLE 0x20024c 663 /* [WB 128] Debug only. Passive buffer memory */ 664 #define CSEM_REG_PASSIVE_BUFFER 0x202000 665 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 666 #define CSEM_REG_PRAM 0x240000 667 /* [R 16] Valid sleeping threads indication have bit per thread */ 668 #define CSEM_REG_SLEEP_THREADS_VALID 0x20026c 669 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 670 #define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0 671 /* [RW 16] List of free threads . There is a bit per thread. */ 672 #define CSEM_REG_THREADS_LIST 0x2002e4 673 /* [RW 3] The arbitration scheme of time_slot 0 */ 674 #define CSEM_REG_TS_0_AS 0x200038 675 /* [RW 3] The arbitration scheme of time_slot 10 */ 676 #define CSEM_REG_TS_10_AS 0x200060 677 /* [RW 3] The arbitration scheme of time_slot 11 */ 678 #define CSEM_REG_TS_11_AS 0x200064 679 /* [RW 3] The arbitration scheme of time_slot 12 */ 680 #define CSEM_REG_TS_12_AS 0x200068 681 /* [RW 3] The arbitration scheme of time_slot 13 */ 682 #define CSEM_REG_TS_13_AS 0x20006c 683 /* [RW 3] The arbitration scheme of time_slot 14 */ 684 #define CSEM_REG_TS_14_AS 0x200070 685 /* [RW 3] The arbitration scheme of time_slot 15 */ 686 #define CSEM_REG_TS_15_AS 0x200074 687 /* [RW 3] The arbitration scheme of time_slot 16 */ 688 #define CSEM_REG_TS_16_AS 0x200078 689 /* [RW 3] The arbitration scheme of time_slot 17 */ 690 #define CSEM_REG_TS_17_AS 0x20007c 691 /* [RW 3] The arbitration scheme of time_slot 18 */ 692 #define CSEM_REG_TS_18_AS 0x200080 693 /* [RW 3] The arbitration scheme of time_slot 1 */ 694 #define CSEM_REG_TS_1_AS 0x20003c 695 /* [RW 3] The arbitration scheme of time_slot 2 */ 696 #define CSEM_REG_TS_2_AS 0x200040 697 /* [RW 3] The arbitration scheme of time_slot 3 */ 698 #define CSEM_REG_TS_3_AS 0x200044 699 /* [RW 3] The arbitration scheme of time_slot 4 */ 700 #define CSEM_REG_TS_4_AS 0x200048 701 /* [RW 3] The arbitration scheme of time_slot 5 */ 702 #define CSEM_REG_TS_5_AS 0x20004c 703 /* [RW 3] The arbitration scheme of time_slot 6 */ 704 #define CSEM_REG_TS_6_AS 0x200050 705 /* [RW 3] The arbitration scheme of time_slot 7 */ 706 #define CSEM_REG_TS_7_AS 0x200054 707 /* [RW 3] The arbitration scheme of time_slot 8 */ 708 #define CSEM_REG_TS_8_AS 0x200058 709 /* [RW 3] The arbitration scheme of time_slot 9 */ 710 #define CSEM_REG_TS_9_AS 0x20005c 711 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 712 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ 713 #define CSEM_REG_VFPF_ERR_NUM 0x200380 714 /* [RW 1] Parity mask register #0 read/write */ 715 #define DBG_REG_DBG_PRTY_MASK 0xc0a8 716 /* [R 1] Parity register #0 read */ 717 #define DBG_REG_DBG_PRTY_STS 0xc09c 718 /* [RC 1] Parity register #0 read clear */ 719 #define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0 720 /* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The 721 * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0; 722 * 4.Completion function=0; 5.Error handling=0 */ 723 #define DMAE_REG_BACKWARD_COMP_EN 0x10207c 724 /* [RW 32] Commands memory. The address to command X; row Y is to calculated 725 as 14*X+Y. */ 726 #define DMAE_REG_CMD_MEM 0x102400 727 #define DMAE_REG_CMD_MEM_SIZE 224 728 /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c 729 initial value is all ones. */ 730 #define DMAE_REG_CRC16C_INIT 0x10201c 731 /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the 732 CRC-16 T10 initial value is all ones. */ 733 #define DMAE_REG_CRC16T10_INIT 0x102020 734 /* [RW 2] Interrupt mask register #0 read/write */ 735 #define DMAE_REG_DMAE_INT_MASK 0x102054 736 /* [RW 4] Parity mask register #0 read/write */ 737 #define DMAE_REG_DMAE_PRTY_MASK 0x102064 738 /* [R 4] Parity register #0 read */ 739 #define DMAE_REG_DMAE_PRTY_STS 0x102058 740 /* [RC 4] Parity register #0 read clear */ 741 #define DMAE_REG_DMAE_PRTY_STS_CLR 0x10205c 742 /* [RW 1] Command 0 go. */ 743 #define DMAE_REG_GO_C0 0x102080 744 /* [RW 1] Command 1 go. */ 745 #define DMAE_REG_GO_C1 0x102084 746 /* [RW 1] Command 10 go. */ 747 #define DMAE_REG_GO_C10 0x102088 748 /* [RW 1] Command 11 go. */ 749 #define DMAE_REG_GO_C11 0x10208c 750 /* [RW 1] Command 12 go. */ 751 #define DMAE_REG_GO_C12 0x102090 752 /* [RW 1] Command 13 go. */ 753 #define DMAE_REG_GO_C13 0x102094 754 /* [RW 1] Command 14 go. */ 755 #define DMAE_REG_GO_C14 0x102098 756 /* [RW 1] Command 15 go. */ 757 #define DMAE_REG_GO_C15 0x10209c 758 /* [RW 1] Command 2 go. */ 759 #define DMAE_REG_GO_C2 0x1020a0 760 /* [RW 1] Command 3 go. */ 761 #define DMAE_REG_GO_C3 0x1020a4 762 /* [RW 1] Command 4 go. */ 763 #define DMAE_REG_GO_C4 0x1020a8 764 /* [RW 1] Command 5 go. */ 765 #define DMAE_REG_GO_C5 0x1020ac 766 /* [RW 1] Command 6 go. */ 767 #define DMAE_REG_GO_C6 0x1020b0 768 /* [RW 1] Command 7 go. */ 769 #define DMAE_REG_GO_C7 0x1020b4 770 /* [RW 1] Command 8 go. */ 771 #define DMAE_REG_GO_C8 0x1020b8 772 /* [RW 1] Command 9 go. */ 773 #define DMAE_REG_GO_C9 0x1020bc 774 /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge 775 input is disregarded; valid is deasserted; all other signals are treated 776 as usual; if 1 - normal activity. */ 777 #define DMAE_REG_GRC_IFEN 0x102008 778 /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the 779 acknowledge input is disregarded; valid is deasserted; full is asserted; 780 all other signals are treated as usual; if 1 - normal activity. */ 781 #define DMAE_REG_PCI_IFEN 0x102004 782 /* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the 783 initial value to the credit counter; related to the address. Read returns 784 the current value of the counter. */ 785 #define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0 786 /* [RW 8] Aggregation command. */ 787 #define DORQ_REG_AGG_CMD0 0x170060 788 /* [RW 8] Aggregation command. */ 789 #define DORQ_REG_AGG_CMD1 0x170064 790 /* [RW 8] Aggregation command. */ 791 #define DORQ_REG_AGG_CMD2 0x170068 792 /* [RW 8] Aggregation command. */ 793 #define DORQ_REG_AGG_CMD3 0x17006c 794 /* [RW 28] UCM Header. */ 795 #define DORQ_REG_CMHEAD_RX 0x170050 796 /* [RW 32] Doorbell address for RBC doorbells (function 0). */ 797 #define DORQ_REG_DB_ADDR0 0x17008c 798 /* [RW 5] Interrupt mask register #0 read/write */ 799 #define DORQ_REG_DORQ_INT_MASK 0x170180 800 /* [R 5] Interrupt register #0 read */ 801 #define DORQ_REG_DORQ_INT_STS 0x170174 802 /* [RC 5] Interrupt register #0 read clear */ 803 #define DORQ_REG_DORQ_INT_STS_CLR 0x170178 804 /* [RW 2] Parity mask register #0 read/write */ 805 #define DORQ_REG_DORQ_PRTY_MASK 0x170190 806 /* [R 2] Parity register #0 read */ 807 #define DORQ_REG_DORQ_PRTY_STS 0x170184 808 /* [RC 2] Parity register #0 read clear */ 809 #define DORQ_REG_DORQ_PRTY_STS_CLR 0x170188 810 /* [RW 8] The address to write the DPM CID to STORM. */ 811 #define DORQ_REG_DPM_CID_ADDR 0x170044 812 /* [RW 5] The DPM mode CID extraction offset. */ 813 #define DORQ_REG_DPM_CID_OFST 0x170030 814 /* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */ 815 #define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c 816 /* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */ 817 #define DORQ_REG_DQ_FIFO_FULL_TH 0x170078 818 /* [R 13] Current value of the DQ FIFO fill level according to following 819 pointer. The range is 0 - 256 FIFO rows; where each row stands for the 820 doorbell. */ 821 #define DORQ_REG_DQ_FILL_LVLF 0x1700a4 822 /* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or 823 equal to full threshold; reset on full clear. */ 824 #define DORQ_REG_DQ_FULL_ST 0x1700c0 825 /* [RW 28] The value sent to CM header in the case of CFC load error. */ 826 #define DORQ_REG_ERR_CMHEAD 0x170058 827 #define DORQ_REG_IF_EN 0x170004 828 #define DORQ_REG_MODE_ACT 0x170008 829 /* [RW 5] The normal mode CID extraction offset. */ 830 #define DORQ_REG_NORM_CID_OFST 0x17002c 831 /* [RW 28] TCM Header when only TCP context is loaded. */ 832 #define DORQ_REG_NORM_CMHEAD_TX 0x17004c 833 /* [RW 3] The number of simultaneous outstanding requests to Context Fetch 834 Interface. */ 835 #define DORQ_REG_OUTST_REQ 0x17003c 836 #define DORQ_REG_PF_USAGE_CNT 0x1701d0 837 #define DORQ_REG_REGN 0x170038 838 /* [R 4] Current value of response A counter credit. Initial credit is 839 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd 840 register. */ 841 #define DORQ_REG_RSPA_CRD_CNT 0x1700ac 842 /* [R 4] Current value of response B counter credit. Initial credit is 843 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd 844 register. */ 845 #define DORQ_REG_RSPB_CRD_CNT 0x1700b0 846 /* [RW 4] The initial credit at the Doorbell Response Interface. The write 847 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The 848 read reads this written value. */ 849 #define DORQ_REG_RSP_INIT_CRD 0x170048 850 /* [RW 4] Initial activity counter value on the load request; when the 851 shortcut is done. */ 852 #define DORQ_REG_SHRT_ACT_CNT 0x170070 853 /* [RW 28] TCM Header when both ULP and TCP context is loaded. */ 854 #define DORQ_REG_SHRT_CMHEAD 0x170054 855 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4) 856 #define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1<<0) 857 #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3) 858 #define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7) 859 #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2) 860 #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1) 861 #define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1<<0) 862 #define HC_REG_AGG_INT_0 0x108050 863 #define HC_REG_AGG_INT_1 0x108054 864 #define HC_REG_ATTN_BIT 0x108120 865 #define HC_REG_ATTN_IDX 0x108100 866 #define HC_REG_ATTN_MSG0_ADDR_L 0x108018 867 #define HC_REG_ATTN_MSG1_ADDR_L 0x108020 868 #define HC_REG_ATTN_NUM_P0 0x108038 869 #define HC_REG_ATTN_NUM_P1 0x10803c 870 #define HC_REG_COMMAND_REG 0x108180 871 #define HC_REG_CONFIG_0 0x108000 872 #define HC_REG_CONFIG_1 0x108004 873 #define HC_REG_FUNC_NUM_P0 0x1080ac 874 #define HC_REG_FUNC_NUM_P1 0x1080b0 875 /* [RW 3] Parity mask register #0 read/write */ 876 #define HC_REG_HC_PRTY_MASK 0x1080a0 877 /* [R 3] Parity register #0 read */ 878 #define HC_REG_HC_PRTY_STS 0x108094 879 /* [RC 3] Parity register #0 read clear */ 880 #define HC_REG_HC_PRTY_STS_CLR 0x108098 881 #define HC_REG_INT_MASK 0x108108 882 #define HC_REG_LEADING_EDGE_0 0x108040 883 #define HC_REG_LEADING_EDGE_1 0x108048 884 #define HC_REG_MAIN_MEMORY 0x108800 885 #define HC_REG_MAIN_MEMORY_SIZE 152 886 #define HC_REG_P0_PROD_CONS 0x108200 887 #define HC_REG_P1_PROD_CONS 0x108400 888 #define HC_REG_PBA_COMMAND 0x108140 889 #define HC_REG_PCI_CONFIG_0 0x108010 890 #define HC_REG_PCI_CONFIG_1 0x108014 891 #define HC_REG_STATISTIC_COUNTERS 0x109000 892 #define HC_REG_TRAILING_EDGE_0 0x108044 893 #define HC_REG_TRAILING_EDGE_1 0x10804c 894 #define HC_REG_UC_RAM_ADDR_0 0x108028 895 #define HC_REG_UC_RAM_ADDR_1 0x108030 896 #define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068 897 #define HC_REG_VQID_0 0x108008 898 #define HC_REG_VQID_1 0x10800c 899 #define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1) 900 #define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1<<0) 901 #define IGU_REG_ATTENTION_ACK_BITS 0x130108 902 /* [R 4] Debug: attn_fsm */ 903 #define IGU_REG_ATTN_FSM 0x130054 904 #define IGU_REG_ATTN_MSG_ADDR_H 0x13011c 905 #define IGU_REG_ATTN_MSG_ADDR_L 0x130120 906 /* [R 4] Debug: [3] - attention write done message is pending (0-no pending; 907 * 1-pending). [2:0] = PFID. Pending means attention message was sent; but 908 * write done didn't receive. */ 909 #define IGU_REG_ATTN_WRITE_DONE_PENDING 0x130030 910 #define IGU_REG_BLOCK_CONFIGURATION 0x130000 911 #define IGU_REG_COMMAND_REG_32LSB_DATA 0x130124 912 #define IGU_REG_COMMAND_REG_CTRL 0x13012c 913 /* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit 914 * is clear. The bits in this registers are set and clear via the producer 915 * command. Data valid only in addresses 0-4. all the rest are zero. */ 916 #define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP 0x130200 917 /* [R 5] Debug: ctrl_fsm */ 918 #define IGU_REG_CTRL_FSM 0x130064 919 /* [R 1] data available for error memory. If this bit is clear do not red 920 * from error_handling_memory. */ 921 #define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130 922 /* [RW 11] Parity mask register #0 read/write */ 923 #define IGU_REG_IGU_PRTY_MASK 0x1300a8 924 /* [R 11] Parity register #0 read */ 925 #define IGU_REG_IGU_PRTY_STS 0x13009c 926 /* [RC 11] Parity register #0 read clear */ 927 #define IGU_REG_IGU_PRTY_STS_CLR 0x1300a0 928 /* [R 4] Debug: int_handle_fsm */ 929 #define IGU_REG_INT_HANDLE_FSM 0x130050 930 #define IGU_REG_LEADING_EDGE_LATCH 0x130134 931 /* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid. 932 * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF 933 * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */ 934 #define IGU_REG_MAPPING_MEMORY 0x131000 935 #define IGU_REG_MAPPING_MEMORY_SIZE 136 936 #define IGU_REG_PBA_STATUS_LSB 0x130138 937 #define IGU_REG_PBA_STATUS_MSB 0x13013c 938 #define IGU_REG_PCI_PF_MSI_EN 0x130140 939 #define IGU_REG_PCI_PF_MSIX_EN 0x130144 940 #define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148 941 /* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no 942 * pending; 1 = pending. Pendings means interrupt was asserted; and write 943 * done was not received. Data valid only in addresses 0-4. all the rest are 944 * zero. */ 945 #define IGU_REG_PENDING_BITS_STATUS 0x130300 946 #define IGU_REG_PF_CONFIGURATION 0x130154 947 /* [RW 20] producers only. E2 mode: address 0-135 match to the mapping 948 * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default 949 * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod; 950 * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode 951 * - In backward compatible mode; for non default SB; each even line in the 952 * memory holds the U producer and each odd line hold the C producer. The 953 * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The 954 * last 20 producers are for the DSB for each PF. each PF has five segments 955 * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 956 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; */ 957 #define IGU_REG_PROD_CONS_MEMORY 0x132000 958 /* [R 3] Debug: pxp_arb_fsm */ 959 #define IGU_REG_PXP_ARB_FSM 0x130068 960 /* [RW 6] Write one for each bit will reset the appropriate memory. When the 961 * memory reset finished the appropriate bit will be clear. Bit 0 - mapping 962 * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3 963 * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; */ 964 #define IGU_REG_RESET_MEMORIES 0x130158 965 /* [R 4] Debug: sb_ctrl_fsm */ 966 #define IGU_REG_SB_CTRL_FSM 0x13004c 967 #define IGU_REG_SB_INT_BEFORE_MASK_LSB 0x13015c 968 #define IGU_REG_SB_INT_BEFORE_MASK_MSB 0x130160 969 #define IGU_REG_SB_MASK_LSB 0x130164 970 #define IGU_REG_SB_MASK_MSB 0x130168 971 /* [RW 16] Number of command that were dropped without causing an interrupt 972 * due to: read access for WO BAR address; or write access for RO BAR 973 * address or any access for reserved address or PCI function error is set 974 * and address is not MSIX; PBA or cleanup */ 975 #define IGU_REG_SILENT_DROP 0x13016c 976 /* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 - 977 * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per 978 * PF; 68-71 number of ATTN messages per PF */ 979 #define IGU_REG_STATISTIC_NUM_MESSAGE_SENT 0x130800 980 /* [RW 32] Number of cycles the timer mask masking the IGU interrupt when a 981 * timer mask command arrives. Value must be bigger than 100. */ 982 #define IGU_REG_TIMER_MASKING_VALUE 0x13003c 983 #define IGU_REG_TRAILING_EDGE_LATCH 0x130104 984 #define IGU_REG_VF_CONFIGURATION 0x130170 985 /* [WB_R 32] Each bit represent write done pending bits status for that SB 986 * (MSI/MSIX message was sent and write done was not received yet). 0 = 987 * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */ 988 #define IGU_REG_WRITE_DONE_PENDING 0x130480 989 #define MCP_A_REG_MCPR_SCRATCH 0x3a0000 990 #define MCP_REG_MCPR_ACCESS_LOCK 0x8009c 991 #define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c 992 #define MCP_REG_MCPR_GP_INPUTS 0x800c0 993 #define MCP_REG_MCPR_GP_OENABLE 0x800c8 994 #define MCP_REG_MCPR_GP_OUTPUTS 0x800c4 995 #define MCP_REG_MCPR_IMC_COMMAND 0x85900 996 #define MCP_REG_MCPR_IMC_DATAREG0 0x85920 997 #define MCP_REG_MCPR_IMC_SLAVE_CONTROL 0x85904 998 #define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c 999 #define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424 1000 #define MCP_REG_MCPR_NVM_ADDR 0x8640c 1001 #define MCP_REG_MCPR_NVM_CFG4 0x8642c 1002 #define MCP_REG_MCPR_NVM_COMMAND 0x86400 1003 #define MCP_REG_MCPR_NVM_READ 0x86410 1004 #define MCP_REG_MCPR_NVM_SW_ARB 0x86420 1005 #define MCP_REG_MCPR_NVM_WRITE 0x86408 1006 #define MCP_REG_MCPR_SCRATCH 0xa0000 1007 #define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1<<1) 1008 #define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1<<0) 1009 /* [R 32] read first 32 bit after inversion of function 0. mapped as 1010 follows: [0] NIG attention for function0; [1] NIG attention for 1011 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; 1012 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] 1013 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE 1014 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; 1015 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] 1016 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB 1017 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw 1018 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity 1019 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw 1020 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF 1021 Parity error; [31] PBF Hw interrupt; */ 1022 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c 1023 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430 1024 /* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0] 1025 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 1026 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; 1027 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] 1028 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event 1029 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP 1030 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for 1031 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] 1032 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC 1033 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw 1034 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI 1035 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw 1036 interrupt; */ 1037 #define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434 1038 /* [R 32] read second 32 bit after inversion of function 0. mapped as 1039 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1040 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1041 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1042 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1043 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1044 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1045 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1046 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1047 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1048 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1049 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1050 interrupt; */ 1051 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438 1052 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c 1053 /* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0] 1054 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error; 1055 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; 1056 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] 1057 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] 1058 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity 1059 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux 1060 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; 1061 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; 1062 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; 1063 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; 1064 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */ 1065 #define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440 1066 /* [R 32] read third 32 bit after inversion of function 0. mapped as 1067 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity 1068 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] 1069 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1070 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1071 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1072 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1073 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1074 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1075 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1076 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1077 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1078 attn1; */ 1079 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444 1080 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448 1081 /* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0] 1082 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP 1083 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient 1084 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity 1085 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw 1086 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] 1087 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] 1088 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW 1089 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 1090 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 1091 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW 1092 timers attn_4 func1; [30] General attn0; [31] General attn1; */ 1093 #define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c 1094 /* [R 32] read fourth 32 bit after inversion of function 0. mapped as 1095 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1096 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1097 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1098 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1099 [14] General attn16; [15] General attn17; [16] General attn18; [17] 1100 General attn19; [18] General attn20; [19] General attn21; [20] Main power 1101 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1102 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1103 Latched timeout attention; [27] GRC Latched reserved access attention; 1104 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1105 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1106 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450 1107 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454 1108 /* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0] 1109 General attn2; [1] General attn3; [2] General attn4; [3] General attn5; 1110 [4] General attn6; [5] General attn7; [6] General attn8; [7] General 1111 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] 1112 General attn13; [12] General attn14; [13] General attn15; [14] General 1113 attn16; [15] General attn17; [16] General attn18; [17] General attn19; 1114 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] 1115 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] 1116 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout 1117 attention; [27] GRC Latched reserved access attention; [28] MCP Latched 1118 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched 1119 ump_tx_parity; [31] MCP Latched scpad_parity; */ 1120 #define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458 1121 /* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as 1122 * follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC 1123 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] 1124 * CNIG attention (reserved); [7] CNIG parity (reserved); [31-8] Reserved; */ 1125 #define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 0xa700 1126 /* [W 14] write to this register results with the clear of the latched 1127 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in 1128 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP 1129 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears 1130 GRC Latched reserved access attention; one in d7 clears Latched 1131 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears 1132 Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both 1133 ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears 1134 pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read 1135 from this register return zero */ 1136 #define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c 1137 /* [RW 32] first 32b for enabling the output for function 0 output0. mapped 1138 as follows: [0] NIG attention for function0; [1] NIG attention for 1139 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 1140 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 1141 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1142 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1143 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1144 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X 1145 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 1146 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 1147 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 1148 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 1149 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1150 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c 1151 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c 1152 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c 1153 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c 1154 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc 1155 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc 1156 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc 1157 /* [RW 32] first 32b for enabling the output for function 1 output0. mapped 1158 as follows: [0] NIG attention for function0; [1] NIG attention for 1159 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function 1160 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 1161 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1162 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1163 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1164 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X 1165 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 1166 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 1167 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 1168 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 1169 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1170 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c 1171 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c 1172 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c 1173 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c 1174 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c 1175 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c 1176 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c 1177 /* [RW 32] first 32b for enabling the output for close the gate nig. mapped 1178 as follows: [0] NIG attention for function0; [1] NIG attention for 1179 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 1180 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 1181 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1182 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1183 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1184 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X 1185 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 1186 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 1187 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 1188 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 1189 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1190 #define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec 1191 #define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c 1192 /* [RW 32] first 32b for enabling the output for close the gate pxp. mapped 1193 as follows: [0] NIG attention for function0; [1] NIG attention for 1194 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 1195 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 1196 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1197 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1198 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1199 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X 1200 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 1201 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 1202 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 1203 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 1204 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1205 #define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc 1206 #define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c 1207 /* [RW 32] second 32b for enabling the output for function 0 output0. mapped 1208 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1209 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1210 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1211 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1212 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1213 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1214 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1215 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1216 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1217 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1218 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1219 interrupt; */ 1220 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070 1221 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080 1222 /* [RW 32] second 32b for enabling the output for function 1 output0. mapped 1223 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1224 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1225 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1226 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1227 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1228 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1229 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1230 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1231 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1232 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1233 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1234 interrupt; */ 1235 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110 1236 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120 1237 /* [RW 32] second 32b for enabling the output for close the gate nig. mapped 1238 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1239 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1240 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1241 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1242 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1243 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1244 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1245 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1246 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1247 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1248 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1249 interrupt; */ 1250 #define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0 1251 #define MISC_REG_AEU_ENABLE2_NIG_1 0xa190 1252 /* [RW 32] second 32b for enabling the output for close the gate pxp. mapped 1253 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1254 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1255 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1256 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1257 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1258 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1259 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1260 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1261 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1262 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1263 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1264 interrupt; */ 1265 #define MISC_REG_AEU_ENABLE2_PXP_0 0xa100 1266 #define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0 1267 /* [RW 32] third 32b for enabling the output for function 0 output0. mapped 1268 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP 1269 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; 1270 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1271 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1272 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1273 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1274 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1275 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1276 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1277 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1278 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1279 attn1; */ 1280 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074 1281 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084 1282 /* [RW 32] third 32b for enabling the output for function 1 output0. mapped 1283 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP 1284 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; 1285 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1286 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1287 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1288 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1289 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1290 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1291 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1292 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1293 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1294 attn1; */ 1295 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114 1296 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124 1297 /* [RW 32] third 32b for enabling the output for close the gate nig. mapped 1298 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP 1299 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; 1300 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1301 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1302 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1303 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1304 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1305 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1306 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1307 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1308 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1309 attn1; */ 1310 #define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4 1311 #define MISC_REG_AEU_ENABLE3_NIG_1 0xa194 1312 /* [RW 32] third 32b for enabling the output for close the gate pxp. mapped 1313 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP 1314 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; 1315 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1316 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1317 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1318 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1319 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1320 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1321 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1322 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1323 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1324 attn1; */ 1325 #define MISC_REG_AEU_ENABLE3_PXP_0 0xa104 1326 #define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4 1327 /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped 1328 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1329 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1330 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1331 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1332 [14] General attn16; [15] General attn17; [16] General attn18; [17] 1333 General attn19; [18] General attn20; [19] General attn21; [20] Main power 1334 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1335 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1336 Latched timeout attention; [27] GRC Latched reserved access attention; 1337 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1338 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1339 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078 1340 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098 1341 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8 1342 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8 1343 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8 1344 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8 1345 /* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped 1346 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1347 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1348 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1349 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1350 [14] General attn16; [15] General attn17; [16] General attn18; [17] 1351 General attn19; [18] General attn20; [19] General attn21; [20] Main power 1352 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1353 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1354 Latched timeout attention; [27] GRC Latched reserved access attention; 1355 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1356 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1357 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118 1358 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138 1359 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158 1360 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168 1361 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178 1362 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188 1363 /* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped 1364 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1365 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1366 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1367 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1368 [14] General attn16; [15] General attn17; [16] General attn18; [17] 1369 General attn19; [18] General attn20; [19] General attn21; [20] Main power 1370 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1371 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1372 Latched timeout attention; [27] GRC Latched reserved access attention; 1373 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1374 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1375 #define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8 1376 #define MISC_REG_AEU_ENABLE4_NIG_1 0xa198 1377 /* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped 1378 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1379 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1380 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1381 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1382 [14] General attn16; [15] General attn17; [16] General attn18; [17] 1383 General attn19; [18] General attn20; [19] General attn21; [20] Main power 1384 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1385 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1386 Latched timeout attention; [27] GRC Latched reserved access attention; 1387 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1388 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1389 #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108 1390 #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8 1391 /* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped 1392 * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC 1393 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] 1394 * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 1395 * parity; [31-10] Reserved; */ 1396 #define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 0xa688 1397 /* [RW 32] Fifth 32b for enabling the output for function 1 output0. Mapped 1398 * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC 1399 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] 1400 * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 1401 * parity; [31-10] Reserved; */ 1402 #define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 0xa6b0 1403 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu 1404 128 bit vector */ 1405 #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000 1406 #define MISC_REG_AEU_GENERAL_ATTN_1 0xa004 1407 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028 1408 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c 1409 #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030 1410 #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008 1411 #define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c 1412 #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010 1413 #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014 1414 #define MISC_REG_AEU_GENERAL_ATTN_6 0xa018 1415 #define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c 1416 #define MISC_REG_AEU_GENERAL_ATTN_8 0xa020 1417 #define MISC_REG_AEU_GENERAL_ATTN_9 0xa024 1418 #define MISC_REG_AEU_GENERAL_MASK 0xa61c 1419 /* [RW 32] first 32b for inverting the input for function 0; for each bit: 1420 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for 1421 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; 1422 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; 1423 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1424 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1425 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1426 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication 1427 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS 1428 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw 1429 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM 1430 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI 1431 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1432 #define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c 1433 #define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c 1434 /* [RW 32] second 32b for inverting the input for function 0; for each bit: 1435 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity 1436 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw 1437 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM 1438 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw 1439 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] 1440 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity 1441 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux 1442 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; 1443 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; 1444 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; 1445 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; 1446 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */ 1447 #define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230 1448 #define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240 1449 /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0; 1450 [9:8] = raserved. Zero = mask; one = unmask */ 1451 #define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060 1452 #define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064 1453 /* [RW 1] If set a system kill occurred */ 1454 #define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610 1455 /* [RW 32] Represent the status of the input vector to the AEU when a system 1456 kill occurred. The register is reset in por reset. Mapped as follows: [0] 1457 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 1458 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; 1459 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] 1460 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event 1461 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP 1462 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for 1463 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] 1464 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC 1465 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw 1466 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI 1467 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw 1468 interrupt; */ 1469 #define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600 1470 #define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604 1471 #define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608 1472 #define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c 1473 /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1 1474 Port. */ 1475 #define MISC_REG_BOND_ID 0xa400 1476 /* [R 8] These bits indicate the metal revision of the chip. This value 1477 starts at 0x00 for each all-layer tape-out and increments by one for each 1478 tape-out. */ 1479 #define MISC_REG_CHIP_METAL 0xa404 1480 /* [R 16] These bits indicate the part number for the chip. */ 1481 #define MISC_REG_CHIP_NUM 0xa408 1482 /* [R 4] These bits indicate the base revision of the chip. This value 1483 starts at 0x0 for the A0 tape-out and increments by one for each 1484 all-layer tape-out. */ 1485 #define MISC_REG_CHIP_REV 0xa40c 1486 /* [R 14] otp_misc_do[100:0] spare bits collection: 13:11- 1487 * otp_misc_do[100:98]; 10:7 - otp_misc_do[87:84]; 6:3 - otp_misc_do[75:72]; 1488 * 2:1 - otp_misc_do[51:50]; 0 - otp_misc_do[1]. */ 1489 #define MISC_REG_CHIP_TYPE 0xac60 1490 #define MISC_REG_CHIP_TYPE_57811_MASK (1<<1) 1491 #define MISC_REG_CPMU_LP_DR_ENABLE 0xa858 1492 /* [RW 1] FW EEE LPI Enable. When 1 indicates that EEE LPI mode is enabled 1493 * by FW. When 0 indicates that the EEE LPI mode is disabled by FW. Clk 1494 * 25MHz. Reset on hard reset. */ 1495 #define MISC_REG_CPMU_LP_FW_ENABLE_P0 0xa84c 1496 /* [RW 32] EEE LPI Idle Threshold. The threshold value for the idle EEE LPI 1497 * counter. Timer tick is 1 us. Clock 25MHz. Reset on hard reset. */ 1498 #define MISC_REG_CPMU_LP_IDLE_THR_P0 0xa8a0 1499 /* [RW 18] LPI entry events mask. [0] - Vmain SM Mask. When 1 indicates that 1500 * the Vmain SM end state is disabled. When 0 indicates that the Vmain SM 1501 * end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates that 1502 * the FW command that all Queues are empty is disabled. When 0 indicates 1503 * that the FW command that all Queues are empty is enabled. [2] - FW Early 1504 * Exit Mask / Reserved (Entry mask). When 1 indicates that the FW Early 1505 * Exit command is disabled. When 0 indicates that the FW Early Exit command 1506 * is enabled. This bit applicable only in the EXIT Events Mask registers. 1507 * [3] - PBF Request Mask. When 1 indicates that the PBF Request indication 1508 * is disabled. When 0 indicates that the PBF Request indication is enabled. 1509 * [4] - Tx Request Mask. When =1 indicates that the Tx other Than PBF 1510 * Request indication is disabled. When 0 indicates that the Tx Other Than 1511 * PBF Request indication is enabled. [5] - Rx EEE LPI Status Mask. When 1 1512 * indicates that the RX EEE LPI Status indication is disabled. When 0 1513 * indicates that the RX EEE LPI Status indication is enabled. In the EXIT 1514 * Events Masks registers; this bit masks the falling edge detect of the LPI 1515 * Status (Rx LPI is on - off). [6] - Tx Pause Mask. When 1 indicates that 1516 * the Tx Pause indication is disabled. When 0 indicates that the Tx Pause 1517 * indication is enabled. [7] - BRB1 Empty Mask. When 1 indicates that the 1518 * BRB1 EMPTY indication is disabled. When 0 indicates that the BRB1 EMPTY 1519 * indication is enabled. [8] - QM Idle Mask. When 1 indicates that the QM 1520 * IDLE indication is disabled. When 0 indicates that the QM IDLE indication 1521 * is enabled. (One bit for both VOQ0 and VOQ1). [9] - QM LB Idle Mask. When 1522 * 1 indicates that the QM IDLE indication for LOOPBACK is disabled. When 0 1523 * indicates that the QM IDLE indication for LOOPBACK is enabled. [10] - L1 1524 * Status Mask. When 1 indicates that the L1 Status indication from the PCIE 1525 * CORE is disabled. When 0 indicates that the RX EEE LPI Status indication 1526 * from the PCIE CORE is enabled. In the EXIT Events Masks registers; this 1527 * bit masks the falling edge detect of the L1 status (L1 is on - off). [11] 1528 * - P0 E0 EEE EEE LPI REQ Mask. When =1 indicates that the P0 E0 EEE EEE 1529 * LPI REQ indication is disabled. When =0 indicates that the P0 E0 EEE LPI 1530 * REQ indication is enabled. [12] - P1 E0 EEE LPI REQ Mask. When =1 1531 * indicates that the P0 EEE LPI REQ indication is disabled. When =0 1532 * indicates that the P0 EEE LPI REQ indication is enabled. [13] - P0 E1 EEE 1533 * LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is 1534 * disabled. When =0 indicates that the P0 EEE LPI REQ indication is 1535 * enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE 1536 * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ 1537 * indication is enabled. [15] - L1 REQ Mask. When =1 indicates that the L1 1538 * REQ indication is disabled. When =0 indicates that the L1 indication is 1539 * enabled. [16] - Rx EEE LPI Status Edge Detect Mask. When =1 indicates 1540 * that the RX EEE LPI Status Falling Edge Detect indication is disabled (Rx 1541 * EEE LPI is on - off). When =0 indicates that the RX EEE LPI Status 1542 * Falling Edge Detec indication is enabled (Rx EEE LPI is on - off). This 1543 * bit is applicable only in the EXIT Events Masks registers. [17] - L1 1544 * Status Edge Detect Mask. When =1 indicates that the L1 Status Falling 1545 * Edge Detect indication from the PCIE CORE is disabled (L1 is on - off). 1546 * When =0 indicates that the L1 Status Falling Edge Detect indication from 1547 * the PCIE CORE is enabled (L1 is on - off). This bit is applicable only in 1548 * the EXIT Events Masks registers. Clock 25MHz. Reset on hard reset. */ 1549 #define MISC_REG_CPMU_LP_MASK_ENT_P0 0xa880 1550 /* [RW 18] EEE LPI exit events mask. [0] - Vmain SM Mask. When 1 indicates 1551 * that the Vmain SM end state is disabled. When 0 indicates that the Vmain 1552 * SM end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates 1553 * that the FW command that all Queues are empty is disabled. When 0 1554 * indicates that the FW command that all Queues are empty is enabled. [2] - 1555 * FW Early Exit Mask / Reserved (Entry mask). When 1 indicates that the FW 1556 * Early Exit command is disabled. When 0 indicates that the FW Early Exit 1557 * command is enabled. This bit applicable only in the EXIT Events Mask 1558 * registers. [3] - PBF Request Mask. When 1 indicates that the PBF Request 1559 * indication is disabled. When 0 indicates that the PBF Request indication 1560 * is enabled. [4] - Tx Request Mask. When =1 indicates that the Tx other 1561 * Than PBF Request indication is disabled. When 0 indicates that the Tx 1562 * Other Than PBF Request indication is enabled. [5] - Rx EEE LPI Status 1563 * Mask. When 1 indicates that the RX EEE LPI Status indication is disabled. 1564 * When 0 indicates that the RX LPI Status indication is enabled. In the 1565 * EXIT Events Masks registers; this bit masks the falling edge detect of 1566 * the EEE LPI Status (Rx EEE LPI is on - off). [6] - Tx Pause Mask. When 1 1567 * indicates that the Tx Pause indication is disabled. When 0 indicates that 1568 * the Tx Pause indication is enabled. [7] - BRB1 Empty Mask. When 1 1569 * indicates that the BRB1 EMPTY indication is disabled. When 0 indicates 1570 * that the BRB1 EMPTY indication is enabled. [8] - QM Idle Mask. When 1 1571 * indicates that the QM IDLE indication is disabled. When 0 indicates that 1572 * the QM IDLE indication is enabled. (One bit for both VOQ0 and VOQ1). [9] 1573 * - QM LB Idle Mask. When 1 indicates that the QM IDLE indication for 1574 * LOOPBACK is disabled. When 0 indicates that the QM IDLE indication for 1575 * LOOPBACK is enabled. [10] - L1 Status Mask. When 1 indicates that the L1 1576 * Status indication from the PCIE CORE is disabled. When 0 indicates that 1577 * the RX EEE LPI Status indication from the PCIE CORE is enabled. In the 1578 * EXIT Events Masks registers; this bit masks the falling edge detect of 1579 * the L1 status (L1 is on - off). [11] - P0 E0 EEE EEE LPI REQ Mask. When 1580 * =1 indicates that the P0 E0 EEE EEE LPI REQ indication is disabled. When 1581 * =0 indicates that the P0 E0 EEE LPI REQ indication is enabled. [12] - P1 1582 * E0 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication 1583 * is disabled. When =0 indicates that the P0 EEE LPI REQ indication is 1584 * enabled. [13] - P0 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE 1585 * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ 1586 * indication is enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates 1587 * that the P0 EEE LPI REQ indication is disabled. When =0 indicates that 1588 * the P0 EEE LPI REQ indication is enabled. [15] - L1 REQ Mask. When =1 1589 * indicates that the L1 REQ indication is disabled. When =0 indicates that 1590 * the L1 indication is enabled. [16] - Rx EEE LPI Status Edge Detect Mask. 1591 * When =1 indicates that the RX EEE LPI Status Falling Edge Detect 1592 * indication is disabled (Rx EEE LPI is on - off). When =0 indicates that 1593 * the RX EEE LPI Status Falling Edge Detec indication is enabled (Rx EEE 1594 * LPI is on - off). This bit is applicable only in the EXIT Events Masks 1595 * registers. [17] - L1 Status Edge Detect Mask. When =1 indicates that the 1596 * L1 Status Falling Edge Detect indication from the PCIE CORE is disabled 1597 * (L1 is on - off). When =0 indicates that the L1 Status Falling Edge 1598 * Detect indication from the PCIE CORE is enabled (L1 is on - off). This 1599 * bit is applicable only in the EXIT Events Masks registers.Clock 25MHz. 1600 * Reset on hard reset. */ 1601 #define MISC_REG_CPMU_LP_MASK_EXT_P0 0xa888 1602 /* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number 1603 * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only 1604 * register. Reset on hard reset. */ 1605 #define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 0xa8b8 1606 /* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number 1607 * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only 1608 * register. Reset on hard reset. */ 1609 #define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 0xa8bc 1610 /* [RW 32] The following driver registers(1...16) represent 16 drivers and 1611 32 clients. Each client can be controlled by one driver only. One in each 1612 bit represent that this driver control the appropriate client (Ex: bit 5 1613 is set means this driver control client number 5). addr1 = set; addr0 = 1614 clear; read from both addresses will give the same result = status. write 1615 to address 1 will set a request to control all the clients that their 1616 appropriate bit (in the write command) is set. if the client is free (the 1617 appropriate bit in all the other drivers is clear) one will be written to 1618 that driver register; if the client isn't free the bit will remain zero. 1619 if the appropriate bit is set (the driver request to gain control on a 1620 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW 1621 interrupt will be asserted). write to address 0 will set a request to 1622 free all the clients that their appropriate bit (in the write command) is 1623 set. if the appropriate bit is clear (the driver request to free a client 1624 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will 1625 be asserted). */ 1626 #define MISC_REG_DRIVER_CONTROL_1 0xa510 1627 #define MISC_REG_DRIVER_CONTROL_7 0xa3c8 1628 /* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0 1629 only. */ 1630 #define MISC_REG_E1HMF_MODE 0xa5f8 1631 /* [R 1] Status of four port mode path swap input pin. */ 1632 #define MISC_REG_FOUR_PORT_PATH_SWAP 0xa75c 1633 /* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 - 1634 the path_swap output is equal to 4 port mode path swap input pin; if it 1635 is 1 - the path_swap output is equal to bit[1] of this register; [1] - 1636 Overwrite value. If bit[0] of this register is 1 this is the value that 1637 receives the path_swap output. Reset on Hard reset. */ 1638 #define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR 0xa738 1639 /* [R 1] Status of 4 port mode port swap input pin. */ 1640 #define MISC_REG_FOUR_PORT_PORT_SWAP 0xa754 1641 /* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 - 1642 the port_swap output is equal to 4 port mode port swap input pin; if it 1643 is 1 - the port_swap output is equal to bit[1] of this register; [1] - 1644 Overwrite value. If bit[0] of this register is 1 this is the value that 1645 receives the port_swap output. Reset on Hard reset. */ 1646 #define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR 0xa734 1647 /* [RW 32] Debug only: spare RW register reset by core reset */ 1648 #define MISC_REG_GENERIC_CR_0 0xa460 1649 #define MISC_REG_GENERIC_CR_1 0xa464 1650 /* [RW 32] Debug only: spare RW register reset by por reset */ 1651 #define MISC_REG_GENERIC_POR_1 0xa474 1652 /* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to 1653 use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO 1654 can not be configured as an output. Each output has its output enable in 1655 the MCP register space; but this bit needs to be set to make use of that. 1656 Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When 1657 set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON. 1658 When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change 1659 the i/o to an output and will drive the TimeSync output. Bit[31:7]: 1660 spare. Global register. Reset by hard reset. */ 1661 #define MISC_REG_GEN_PURP_HWG 0xa9a0 1662 /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of 1663 these bits is written as a '1'; the corresponding SPIO bit will turn off 1664 it's drivers and become an input. This is the reset state of all GPIO 1665 pins. The read value of these bits will be a '1' if that last command 1666 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff). 1667 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written 1668 as a '1'; the corresponding GPIO bit will drive low. The read value of 1669 these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for 1670 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0; 1671 SET When any of these bits is written as a '1'; the corresponding GPIO 1672 bit will drive high (if it has that capability). The read value of these 1673 bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this 1674 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0; 1675 RO; These bits indicate the read value of each of the eight GPIO pins. 1676 This is the result value of the pin; not the drive value. Writing these 1677 bits will have not effect. */ 1678 #define MISC_REG_GPIO 0xa490 1679 /* [RW 8] These bits enable the GPIO_INTs to signals event to the 1680 IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2] 1681 p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2; 1682 [7] p1_gpio_3; */ 1683 #define MISC_REG_GPIO_EVENT_EN 0xa2bc 1684 /* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a 1685 '1' to these bit clears the corresponding bit in the #OLD_VALUE register. 1686 This will acknowledge an interrupt on the falling edge of corresponding 1687 GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0; 1688 Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE 1689 register. This will acknowledge an interrupt on the rising edge of 1690 corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1; 1691 OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input 1692 value. When the ~INT_STATE bit is set; this bit indicates the OLD value 1693 of the pin such that if ~INT_STATE is set and this bit is '0'; then the 1694 interrupt is due to a low to high edge. If ~INT_STATE is set and this bit 1695 is '1'; then the interrupt is due to a high to low edge (reset value 0). 1696 [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the 1697 current GPIO interrupt state for each GPIO pin. This bit is cleared when 1698 the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is 1699 set when the GPIO input does not match the current value in #OLD_VALUE 1700 (reset value 0). */ 1701 #define MISC_REG_GPIO_INT 0xa494 1702 /* [R 28] this field hold the last information that caused reserved 1703 attention. bits [19:0] - address; [22:20] function; [23] reserved; 1704 [27:24] the master that caused the attention - according to the following 1705 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = 1706 dbu; 8 = dmae */ 1707 #define MISC_REG_GRC_RSV_ATTN 0xa3c0 1708 /* [R 28] this field hold the last information that caused timeout 1709 attention. bits [19:0] - address; [22:20] function; [23] reserved; 1710 [27:24] the master that caused the attention - according to the following 1711 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = 1712 dbu; 8 = dmae */ 1713 #define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4 1714 /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any 1715 access that does not finish within 1716 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is 1717 cleared; this timeout is disabled. If this timeout occurs; the GRC shall 1718 assert it attention output. */ 1719 #define MISC_REG_GRC_TIMEOUT_EN 0xa280 1720 /* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of 1721 the bits is: [2:0] OAC reset value 001) CML output buffer bias control; 1722 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl 1723 (reset value 001) Charge pump current control; 111 for 720u; 011 for 1724 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00) 1725 Global bias control; When bit 7 is high bias current will be 10 0gh; When 1726 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8] 1727 Pll_observe (reset value 010) Bits to control observability. bit 10 is 1728 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl 1729 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V 1730 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning 1731 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted 1732 internally). [14] reserved (reset value 0) Reset for VCO sequencer is 1733 connected to RESET input directly. [15] capRetry_en (reset value 0) 1734 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset 1735 value 0) bit to continuously monitor vco freq (inverted). [17] 1736 freqDetRestart_en (reset value 0) bit to enable restart when not freq 1737 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable 1738 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value 1739 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20] 1740 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass 1741 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value 1742 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0) 1743 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to 1744 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force 1745 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to 1746 restart. [27] capSelectM_en (reset value 0) bit to enable cap select 1747 register bits. */ 1748 #define MISC_REG_LCPLL_CTRL_1 0xa2a4 1749 #define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8 1750 /* [RW 1] LCPLL power down. Global register. Active High. Reset on POR 1751 * reset. */ 1752 #define MISC_REG_LCPLL_E40_PWRDWN 0xaa74 1753 /* [RW 1] LCPLL VCO reset. Global register. Active Low Reset on POR reset. */ 1754 #define MISC_REG_LCPLL_E40_RESETB_ANA 0xaa78 1755 /* [RW 1] LCPLL post-divider reset. Global register. Active Low Reset on POR 1756 * reset. */ 1757 #define MISC_REG_LCPLL_E40_RESETB_DIG 0xaa7c 1758 /* [RW 4] Interrupt mask register #0 read/write */ 1759 #define MISC_REG_MISC_INT_MASK 0xa388 1760 /* [RW 1] Parity mask register #0 read/write */ 1761 #define MISC_REG_MISC_PRTY_MASK 0xa398 1762 /* [R 1] Parity register #0 read */ 1763 #define MISC_REG_MISC_PRTY_STS 0xa38c 1764 /* [RC 1] Parity register #0 read clear */ 1765 #define MISC_REG_MISC_PRTY_STS_CLR 0xa390 1766 #define MISC_REG_NIG_WOL_P0 0xa270 1767 #define MISC_REG_NIG_WOL_P1 0xa274 1768 /* [R 1] If set indicate that the pcie_rst_b was asserted without perst 1769 assertion */ 1770 #define MISC_REG_PCIE_HOT_RESET 0xa618 1771 /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911. 1772 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1 1773 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1 1774 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2 1775 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2 1776 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9] 1777 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1] 1778 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value 1779 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16] 1780 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset 1781 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value 1782 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0); 1783 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25] 1784 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27] 1785 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29] 1786 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31] 1787 testa_en (reset value 0); */ 1788 #define MISC_REG_PLL_STORM_CTRL_1 0xa294 1789 #define MISC_REG_PLL_STORM_CTRL_2 0xa298 1790 #define MISC_REG_PLL_STORM_CTRL_3 0xa29c 1791 #define MISC_REG_PLL_STORM_CTRL_4 0xa2a0 1792 /* [R 1] Status of 4 port mode enable input pin. */ 1793 #define MISC_REG_PORT4MODE_EN 0xa750 1794 /* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 - 1795 * the port4mode_en output is equal to 4 port mode input pin; if it is 1 - 1796 * the port4mode_en output is equal to bit[1] of this register; [1] - 1797 * Overwrite value. If bit[0] of this register is 1 this is the value that 1798 * receives the port4mode_en output . */ 1799 #define MISC_REG_PORT4MODE_EN_OVWR 0xa720 1800 /* [RW 32] reset reg#2; rite/read one = the specific block is out of reset; 1801 write/read zero = the specific block is in reset; addr 0-wr- the write 1802 value will be written to the register; addr 1-set - one will be written 1803 to all the bits that have the value of one in the data written (bits that 1804 have the value of zero will not be change) ; addr 2-clear - zero will be 1805 written to all the bits that have the value of one in the data written 1806 (bits that have the value of zero will not be change); addr 3-ignore; 1807 read ignore from all addr except addr 00; inside order of the bits is: 1808 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc; 1809 [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7] 1810 rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn; 1811 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13] 1812 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16] 1813 rst_pxp_rq_rd_wr; 31:17] reserved */ 1814 #define MISC_REG_RESET_REG_1 0xa580 1815 #define MISC_REG_RESET_REG_2 0xa590 1816 /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is 1817 shared with the driver resides */ 1818 #define MISC_REG_SHARED_MEM_ADDR 0xa2b4 1819 /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1'; 1820 the corresponding SPIO bit will turn off it's drivers and become an 1821 input. This is the reset state of all SPIO pins. The read value of these 1822 bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this 1823 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits 1824 is written as a '1'; the corresponding SPIO bit will drive low. The read 1825 value of these bits will be a '1' if that last command (#SET; #CLR; or 1826 #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of 1827 these bits is written as a '1'; the corresponding SPIO bit will drive 1828 high (if it has that capability). The read value of these bits will be a 1829 '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET. 1830 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of 1831 each of the eight SPIO pins. This is the result value of the pin; not the 1832 drive value. Writing these bits will have not effect. Each 8 bits field 1833 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply 1834 from VAUX. (This is an output pin only; the FLOAT field is not applicable 1835 for this pin); [1] VAUX Disable; when pulsed low; disables supply form 1836 VAUX. (This is an output pin only; FLOAT field is not applicable for this 1837 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to 1838 select VAUX supply. (This is an output pin only; it is not controlled by 1839 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT 1840 field is not applicable for this pin; only the VALUE fields is relevant - 1841 it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6] 1842 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP 1843 device ID select; read by UMP firmware. */ 1844 #define MISC_REG_SPIO 0xa4fc 1845 /* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC. 1846 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5; 1847 [7:0] reserved */ 1848 #define MISC_REG_SPIO_EVENT_EN 0xa2b8 1849 /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the 1850 corresponding bit in the #OLD_VALUE register. This will acknowledge an 1851 interrupt on the falling edge of corresponding SPIO input (reset value 1852 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit 1853 in the #OLD_VALUE register. This will acknowledge an interrupt on the 1854 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE 1855 RO; These bits indicate the old value of the SPIO input value. When the 1856 ~INT_STATE bit is set; this bit indicates the OLD value of the pin such 1857 that if ~INT_STATE is set and this bit is '0'; then the interrupt is due 1858 to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the 1859 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE 1860 RO; These bits indicate the current SPIO interrupt state for each SPIO 1861 pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR 1862 command bit is written. This bit is set when the SPIO input does not 1863 match the current value in #OLD_VALUE (reset value 0). */ 1864 #define MISC_REG_SPIO_INT 0xa500 1865 /* [RW 32] reload value for counter 4 if reload; the value will be reload if 1866 the counter reached zero and the reload bit 1867 (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */ 1868 #define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc 1869 /* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses 1870 in this register. address 0 - timer 1; address 1 - timer 2, ... address 7 - 1871 timer 8 */ 1872 #define MISC_REG_SW_TIMER_VAL 0xa5c0 1873 /* [R 1] Status of two port mode path swap input pin. */ 1874 #define MISC_REG_TWO_PORT_PATH_SWAP 0xa758 1875 /* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the 1876 path_swap output is equal to 2 port mode path swap input pin; if it is 1 1877 - the path_swap output is equal to bit[1] of this register; [1] - 1878 Overwrite value. If bit[0] of this register is 1 this is the value that 1879 receives the path_swap output. Reset on Hard reset. */ 1880 #define MISC_REG_TWO_PORT_PATH_SWAP_OVWR 0xa72c 1881 /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are 1882 loaded; 0-prepare; -unprepare */ 1883 #define MISC_REG_UNPREPARED 0xa424 1884 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0) 1885 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1) 1886 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4) 1887 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2) 1888 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3) 1889 /* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or 1890 * not it is the recipient of the message on the MDIO interface. The value 1891 * is compared to the value on ctrl_md_devad. Drives output 1892 * misc_xgxs0_phy_addr. Global register. */ 1893 #define MISC_REG_WC0_CTRL_PHY_ADDR 0xa9cc 1894 #define MISC_REG_WC0_RESET 0xac30 1895 /* [RW 2] XMAC Core port mode. Indicates the number of ports on the system 1896 side. This should be less than or equal to phy_port_mode; if some of the 1897 ports are not used. This enables reduction of frequency on the core side. 1898 This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 - 1899 Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap 1900 input for the XMAC_MP core; and should be changed only while reset is 1901 held low. Reset on Hard reset. */ 1902 #define MISC_REG_XMAC_CORE_PORT_MODE 0xa964 1903 /* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp 1904 Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 1905 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the 1906 XMAC_MP core; and should be changed only while reset is held low. Reset 1907 on Hard reset. */ 1908 #define MISC_REG_XMAC_PHY_PORT_MODE 0xa960 1909 /* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0. 1910 * Reads from this register will clear bits 31:0. */ 1911 #define MSTAT_REG_RX_STAT_GR64_LO 0x200 1912 /* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits 1913 * 31:0. Reads from this register will clear bits 31:0. */ 1914 #define MSTAT_REG_TX_STAT_GTXPOK_LO 0 1915 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0) 1916 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1) 1917 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4) 1918 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2) 1919 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3) 1920 #define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0) 1921 #define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0) 1922 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0) 1923 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9) 1924 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15) 1925 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18) 1926 /* [RW 1] Input enable for RX_BMAC0 IF */ 1927 #define NIG_REG_BMAC0_IN_EN 0x100ac 1928 /* [RW 1] output enable for TX_BMAC0 IF */ 1929 #define NIG_REG_BMAC0_OUT_EN 0x100e0 1930 /* [RW 1] output enable for TX BMAC pause port 0 IF */ 1931 #define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110 1932 /* [RW 1] output enable for RX_BMAC0_REGS IF */ 1933 #define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8 1934 /* [RW 1] output enable for RX BRB1 port0 IF */ 1935 #define NIG_REG_BRB0_OUT_EN 0x100f8 1936 /* [RW 1] Input enable for TX BRB1 pause port 0 IF */ 1937 #define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4 1938 /* [RW 1] output enable for RX BRB1 port1 IF */ 1939 #define NIG_REG_BRB1_OUT_EN 0x100fc 1940 /* [RW 1] Input enable for TX BRB1 pause port 1 IF */ 1941 #define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8 1942 /* [RW 1] output enable for RX BRB1 LP IF */ 1943 #define NIG_REG_BRB_LB_OUT_EN 0x10100 1944 /* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64] 1945 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush; 1946 72:73]-vnic_num; 81:74]-sideband_info */ 1947 #define NIG_REG_DEBUG_PACKET_LB 0x10800 1948 /* [RW 1] Input enable for TX Debug packet */ 1949 #define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc 1950 /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all 1951 packets from PBFare not forwarded to the MAC and just deleted from FIFO. 1952 First packet may be deleted from the middle. And last packet will be 1953 always deleted till the end. */ 1954 #define NIG_REG_EGRESS_DRAIN0_MODE 0x10060 1955 /* [RW 1] Output enable to EMAC0 */ 1956 #define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120 1957 /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs 1958 to emac for port0; other way to bmac for port0 */ 1959 #define NIG_REG_EGRESS_EMAC0_PORT 0x10058 1960 /* [RW 1] Input enable for TX PBF user packet port0 IF */ 1961 #define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc 1962 /* [RW 1] Input enable for TX PBF user packet port1 IF */ 1963 #define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0 1964 /* [RW 1] Input enable for TX UMP management packet port0 IF */ 1965 #define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4 1966 /* [RW 1] Input enable for RX_EMAC0 IF */ 1967 #define NIG_REG_EMAC0_IN_EN 0x100a4 1968 /* [RW 1] output enable for TX EMAC pause port 0 IF */ 1969 #define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118 1970 /* [R 1] status from emac0. This bit is set when MDINT from either the 1971 EXT_MDINT pin or from the Copper PHY is driven low. This condition must 1972 be cleared in the attached PHY device that is driving the MINT pin. */ 1973 #define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494 1974 /* [WB 48] This address space contains BMAC0 registers. The BMAC registers 1975 are described in appendix A. In order to access the BMAC0 registers; the 1976 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be 1977 added to each BMAC register offset */ 1978 #define NIG_REG_INGRESS_BMAC0_MEM 0x10c00 1979 /* [WB 48] This address space contains BMAC1 registers. The BMAC registers 1980 are described in appendix A. In order to access the BMAC0 registers; the 1981 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be 1982 added to each BMAC register offset */ 1983 #define NIG_REG_INGRESS_BMAC1_MEM 0x11000 1984 /* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */ 1985 #define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0 1986 /* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data 1987 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */ 1988 #define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4 1989 /* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch 1990 logic for interrupts must be used. Enable per bit of interrupt of 1991 ~latch_status.latch_status */ 1992 #define NIG_REG_LATCH_BC_0 0x16210 1993 /* [RW 27] Latch for each interrupt from Unicore.b[0] 1994 status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete; 1995 b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status; 1996 b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn; 1997 b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete; 1998 b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status; 1999 b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete; 2000 b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet; 2001 b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g; 2002 b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact; 2003 b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx; 2004 b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx; 2005 b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */ 2006 #define NIG_REG_LATCH_STATUS_0 0x18000 2007 /* [RW 1] led 10g for port 0 */ 2008 #define NIG_REG_LED_10G_P0 0x10320 2009 /* [RW 1] led 10g for port 1 */ 2010 #define NIG_REG_LED_10G_P1 0x10324 2011 /* [RW 1] Port0: This bit is set to enable the use of the 2012 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field 2013 defined below. If this bit is cleared; then the blink rate will be about 2014 8Hz. */ 2015 #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318 2016 /* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for 2017 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field 2018 is reset to 0x080; giving a default blink period of approximately 8Hz. */ 2019 #define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310 2020 /* [RW 1] Port0: If set along with the 2021 ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0 2022 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED 2023 bit; the Traffic LED will blink with the blink rate specified in 2024 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and 2025 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0 2026 fields. */ 2027 #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308 2028 /* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The 2029 Traffic LED will then be controlled via bit ~nig_registers_ 2030 led_control_traffic_p0.led_control_traffic_p0 and bit 2031 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */ 2032 #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8 2033 /* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit; 2034 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also 2035 set; the LED will blink with blink rate specified in 2036 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and 2037 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0 2038 fields. */ 2039 #define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300 2040 /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3; 2041 9-11PHY7; 12 MAC4; 13-15 PHY10; */ 2042 #define NIG_REG_LED_MODE_P0 0x102f0 2043 /* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1- 2044 tsdm enable; b2- usdm enable */ 2045 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070 2046 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074 2047 /* [RW 1] SAFC enable for port0. This register may get 1 only when 2048 ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same 2049 port */ 2050 #define NIG_REG_LLFC_ENABLE_0 0x16208 2051 #define NIG_REG_LLFC_ENABLE_1 0x1620c 2052 /* [RW 16] classes are high-priority for port0 */ 2053 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058 2054 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 0x1605c 2055 /* [RW 16] classes are low-priority for port0 */ 2056 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060 2057 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 0x16064 2058 /* [RW 1] Output enable of message to LLFC BMAC IF for port0 */ 2059 #define NIG_REG_LLFC_OUT_EN_0 0x160c8 2060 #define NIG_REG_LLFC_OUT_EN_1 0x160cc 2061 #define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c 2062 #define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154 2063 #define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244 2064 #define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048 2065 /* [RW 1] send to BRB1 if no match on any of RMP rules. */ 2066 #define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c 2067 /* [RW 2] Determine the classification participants. 0: no classification.1: 2068 classification upon VLAN id. 2: classification upon MAC address. 3: 2069 classification upon both VLAN id & MAC addr. */ 2070 #define NIG_REG_LLH0_CLS_TYPE 0x16080 2071 /* [RW 32] cm header for llh0 */ 2072 #define NIG_REG_LLH0_CM_HEADER 0x1007c 2073 #define NIG_REG_LLH0_DEST_IP_0_1 0x101dc 2074 #define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0 2075 /* [RW 16] destination TCP address 1. The LLH will look for this address in 2076 all incoming packets. */ 2077 #define NIG_REG_LLH0_DEST_TCP_0 0x10220 2078 /* [RW 16] destination UDP address 1 The LLH will look for this address in 2079 all incoming packets. */ 2080 #define NIG_REG_LLH0_DEST_UDP_0 0x10214 2081 #define NIG_REG_LLH0_ERROR_MASK 0x1008c 2082 /* [RW 8] event id for llh0 */ 2083 #define NIG_REG_LLH0_EVENT_ID 0x10084 2084 #define NIG_REG_LLH0_FUNC_EN 0x160fc 2085 #define NIG_REG_LLH0_FUNC_MEM 0x16180 2086 #define NIG_REG_LLH0_FUNC_MEM_ENABLE 0x16140 2087 #define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100 2088 /* [RW 1] Determine the IP version to look for in 2089 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */ 2090 #define NIG_REG_LLH0_IPV4_IPV6_0 0x10208 2091 /* [RW 1] t bit for llh0 */ 2092 #define NIG_REG_LLH0_T_BIT 0x10074 2093 /* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */ 2094 #define NIG_REG_LLH0_VLAN_ID_0 0x1022c 2095 /* [RW 8] init credit counter for port0 in LLH */ 2096 #define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554 2097 #define NIG_REG_LLH0_XCM_MASK 0x10130 2098 #define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248 2099 /* [RW 1] send to BRB1 if no match on any of RMP rules. */ 2100 #define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc 2101 /* [RW 2] Determine the classification participants. 0: no classification.1: 2102 classification upon VLAN id. 2: classification upon MAC address. 3: 2103 classification upon both VLAN id & MAC addr. */ 2104 #define NIG_REG_LLH1_CLS_TYPE 0x16084 2105 /* [RW 32] cm header for llh1 */ 2106 #define NIG_REG_LLH1_CM_HEADER 0x10080 2107 #define NIG_REG_LLH1_ERROR_MASK 0x10090 2108 /* [RW 8] event id for llh1 */ 2109 #define NIG_REG_LLH1_EVENT_ID 0x10088 2110 #define NIG_REG_LLH1_FUNC_EN 0x16104 2111 #define NIG_REG_LLH1_FUNC_MEM 0x161c0 2112 #define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160 2113 #define NIG_REG_LLH1_FUNC_MEM_SIZE 16 2114 /* [RW 1] When this bit is set; the LLH will classify the packet before 2115 * sending it to the BRB or calculating WoL on it. This bit controls port 1 2116 * only. The legacy llh_multi_function_mode bit controls port 0. */ 2117 #define NIG_REG_LLH1_MF_MODE 0x18614 2118 /* [RW 8] init credit counter for port1 in LLH */ 2119 #define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564 2120 #define NIG_REG_LLH1_XCM_MASK 0x10134 2121 /* [RW 1] When this bit is set; the LLH will expect all packets to be with 2122 e1hov */ 2123 #define NIG_REG_LLH_E1HOV_MODE 0x160d8 2124 /* [RW 1] When this bit is set; the LLH will classify the packet before 2125 sending it to the BRB or calculating WoL on it. */ 2126 #define NIG_REG_LLH_MF_MODE 0x16024 2127 #define NIG_REG_MASK_INTERRUPT_PORT0 0x10330 2128 #define NIG_REG_MASK_INTERRUPT_PORT1 0x10334 2129 /* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */ 2130 #define NIG_REG_NIG_EMAC0_EN 0x1003c 2131 /* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */ 2132 #define NIG_REG_NIG_EMAC1_EN 0x10040 2133 /* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the 2134 EMAC0 to strip the CRC from the ingress packets. */ 2135 #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044 2136 /* [R 32] Interrupt register #0 read */ 2137 #define NIG_REG_NIG_INT_STS_0 0x103b0 2138 #define NIG_REG_NIG_INT_STS_1 0x103c0 2139 /* [R 32] Legacy E1 and E1H location for parity error mask register. */ 2140 #define NIG_REG_NIG_PRTY_MASK 0x103dc 2141 /* [RW 32] Parity mask register #0 read/write */ 2142 #define NIG_REG_NIG_PRTY_MASK_0 0x183c8 2143 #define NIG_REG_NIG_PRTY_MASK_1 0x183d8 2144 /* [R 32] Legacy E1 and E1H location for parity error status register. */ 2145 #define NIG_REG_NIG_PRTY_STS 0x103d0 2146 /* [R 32] Parity register #0 read */ 2147 #define NIG_REG_NIG_PRTY_STS_0 0x183bc 2148 #define NIG_REG_NIG_PRTY_STS_1 0x183cc 2149 /* [R 32] Legacy E1 and E1H location for parity error status clear register. */ 2150 #define NIG_REG_NIG_PRTY_STS_CLR 0x103d4 2151 /* [RC 32] Parity register #0 read clear */ 2152 #define NIG_REG_NIG_PRTY_STS_CLR_0 0x183c0 2153 #define NIG_REG_NIG_PRTY_STS_CLR_1 0x183d0 2154 #define MCPR_IMC_COMMAND_ENABLE (1L<<31) 2155 #define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16 2156 #define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28 2157 #define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8 2158 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2159 * Ethernet header. */ 2160 #define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038 2161 /* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in 2162 * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be 2163 * disabled when this bit is set. */ 2164 #define NIG_REG_P0_HWPFC_ENABLE 0x18078 2165 #define NIG_REG_P0_LLH_FUNC_MEM2 0x18480 2166 #define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x18440 2167 /* [RW 1] Input enable for RX MAC interface. */ 2168 #define NIG_REG_P0_MAC_IN_EN 0x185ac 2169 /* [RW 1] Output enable for TX MAC interface */ 2170 #define NIG_REG_P0_MAC_OUT_EN 0x185b0 2171 /* [RW 1] Output enable for TX PAUSE signal to the MAC. */ 2172 #define NIG_REG_P0_MAC_PAUSE_OUT_EN 0x185b4 2173 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for 2174 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the 2175 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit 2176 * priority field is extracted from the outer-most VLAN in receive packet. 2177 * Only COS 0 and COS 1 are supported in E2. */ 2178 #define NIG_REG_P0_PKT_PRIORITY_TO_COS 0x18054 2179 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A 2180 * priority is mapped to COS 0 when the corresponding mask bit is 1. More 2181 * than one bit may be set; allowing multiple priorities to be mapped to one 2182 * COS. */ 2183 #define NIG_REG_P0_RX_COS0_PRIORITY_MASK 0x18058 2184 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A 2185 * priority is mapped to COS 1 when the corresponding mask bit is 1. More 2186 * than one bit may be set; allowing multiple priorities to be mapped to one 2187 * COS. */ 2188 #define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805c 2189 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A 2190 * priority is mapped to COS 2 when the corresponding mask bit is 1. More 2191 * than one bit may be set; allowing multiple priorities to be mapped to one 2192 * COS. */ 2193 #define NIG_REG_P0_RX_COS2_PRIORITY_MASK 0x186b0 2194 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A 2195 * priority is mapped to COS 3 when the corresponding mask bit is 1. More 2196 * than one bit may be set; allowing multiple priorities to be mapped to one 2197 * COS. */ 2198 #define NIG_REG_P0_RX_COS3_PRIORITY_MASK 0x186b4 2199 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A 2200 * priority is mapped to COS 4 when the corresponding mask bit is 1. More 2201 * than one bit may be set; allowing multiple priorities to be mapped to one 2202 * COS. */ 2203 #define NIG_REG_P0_RX_COS4_PRIORITY_MASK 0x186b8 2204 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A 2205 * priority is mapped to COS 5 when the corresponding mask bit is 1. More 2206 * than one bit may be set; allowing multiple priorities to be mapped to one 2207 * COS. */ 2208 #define NIG_REG_P0_RX_COS5_PRIORITY_MASK 0x186bc 2209 /* [R 1] RX FIFO for receiving data from MAC is empty. */ 2210 /* [RW 15] Specify which of the credit registers the client is to be mapped 2211 * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For 2212 * clients that are not subject to WFQ credit blocking - their 2213 * specifications here are not used. */ 2214 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f0 2215 /* [RW 32] Specify which of the credit registers the client is to be mapped 2216 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are 2217 * for client 0; bits [35:32] are for client 8. For clients that are not 2218 * subject to WFQ credit blocking - their specifications here are not used. 2219 * This is a new register (with 2_) added in E3 B0 to accommodate the 9 2220 * input clients to ETS arbiter. The reset default is set for management and 2221 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to 2222 * use credit registers 0-5 respectively (0x543210876). Note that credit 2223 * registers can not be shared between clients. */ 2224 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x18688 2225 /* [RW 4] Specify which of the credit registers the client is to be mapped 2226 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are 2227 * for client 0; bits [35:32] are for client 8. For clients that are not 2228 * subject to WFQ credit blocking - their specifications here are not used. 2229 * This is a new register (with 2_) added in E3 B0 to accommodate the 9 2230 * input clients to ETS arbiter. The reset default is set for management and 2231 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to 2232 * use credit registers 0-5 respectively (0x543210876). Note that credit 2233 * registers can not be shared between clients. */ 2234 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x1868c 2235 /* [RW 5] Specify whether the client competes directly in the strict 2236 * priority arbiter. The bits are mapped according to client ID (client IDs 2237 * are defined in tx_arb_priority_client). Default value is set to enable 2238 * strict priorities for clients 0-2 -- management and debug traffic. */ 2239 #define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT 0x180e8 2240 /* [RW 5] Specify whether the client is subject to WFQ credit blocking. The 2241 * bits are mapped according to client ID (client IDs are defined in 2242 * tx_arb_priority_client). Default value is 0 for not using WFQ credit 2243 * blocking. */ 2244 #define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x180ec 2245 /* [RW 32] Specify the upper bound that credit register 0 is allowed to 2246 * reach. */ 2247 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810c 2248 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x18110 2249 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 0x18114 2250 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 0x18118 2251 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 0x1811c 2252 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 0x186a0 2253 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 0x186a4 2254 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 0x186a8 2255 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 0x186ac 2256 /* [RW 32] Specify the weight (in bytes) to be added to credit register 0 2257 * when it is time to increment. */ 2258 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f8 2259 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fc 2260 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 0x18100 2261 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 0x18104 2262 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 0x18108 2263 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 0x18690 2264 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 0x18694 2265 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 0x18698 2266 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 0x1869c 2267 /* [RW 12] Specify the number of strict priority arbitration slots between 2268 * two round-robin arbitration slots to avoid starvation. A value of 0 means 2269 * no strict priority cycles - the strict priority with anti-starvation 2270 * arbiter becomes a round-robin arbiter. */ 2271 #define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS 0x180f4 2272 /* [RW 15] Specify the client number to be assigned to each priority of the 2273 * strict priority arbiter. Priority 0 is the highest priority. Bits [2:0] 2274 * are for priority 0 client; bits [14:12] are for priority 4 client. The 2275 * clients are assigned the following IDs: 0-management; 1-debug traffic 2276 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 2277 * traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000) 2278 * for management at priority 0; debug traffic at priorities 1 and 2; COS0 2279 * traffic at priority 3; and COS1 traffic at priority 4. */ 2280 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e4 2281 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2282 * Ethernet header. */ 2283 #define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818c 2284 #define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0 2285 #define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460 2286 /* [RW 32] Specify the client number to be assigned to each priority of the 2287 * strict priority arbiter. This register specifies bits 31:0 of the 36-bit 2288 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 2289 * client; bits [35-32] are for priority 8 client. The clients are assigned 2290 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug 2291 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 2292 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is 2293 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to 2294 * accommodate the 9 input clients to ETS arbiter. */ 2295 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB 0x18680 2296 /* [RW 4] Specify the client number to be assigned to each priority of the 2297 * strict priority arbiter. This register specifies bits 35:32 of the 36-bit 2298 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 2299 * client; bits [35-32] are for priority 8 client. The clients are assigned 2300 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug 2301 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 2302 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is 2303 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to 2304 * accommodate the 9 input clients to ETS arbiter. */ 2305 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB 0x18684 2306 /* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP 2307 * packets to BRB LB interface to forward the packet to the host. All 2308 * packets from MCP are forwarded to the network when this bit is cleared - 2309 * regardless of the configured destination in tx_mng_destination register. 2310 * When MCP-to-host paths for both ports 0 and 1 are disabled - the arbiter 2311 * for BRB LB interface is bypassed and PBF LB traffic is always selected to 2312 * send to BRB LB. 2313 */ 2314 #define NIG_REG_P0_TX_MNG_HOST_ENABLE 0x182f4 2315 #define NIG_REG_P1_HWPFC_ENABLE 0x181d0 2316 #define NIG_REG_P1_MAC_IN_EN 0x185c0 2317 /* [RW 1] Output enable for TX MAC interface */ 2318 #define NIG_REG_P1_MAC_OUT_EN 0x185c4 2319 /* [RW 1] Output enable for TX PAUSE signal to the MAC. */ 2320 #define NIG_REG_P1_MAC_PAUSE_OUT_EN 0x185c8 2321 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for 2322 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the 2323 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit 2324 * priority field is extracted from the outer-most VLAN in receive packet. 2325 * Only COS 0 and COS 1 are supported in E2. */ 2326 #define NIG_REG_P1_PKT_PRIORITY_TO_COS 0x181a8 2327 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A 2328 * priority is mapped to COS 0 when the corresponding mask bit is 1. More 2329 * than one bit may be set; allowing multiple priorities to be mapped to one 2330 * COS. */ 2331 #define NIG_REG_P1_RX_COS0_PRIORITY_MASK 0x181ac 2332 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A 2333 * priority is mapped to COS 1 when the corresponding mask bit is 1. More 2334 * than one bit may be set; allowing multiple priorities to be mapped to one 2335 * COS. */ 2336 #define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b0 2337 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A 2338 * priority is mapped to COS 2 when the corresponding mask bit is 1. More 2339 * than one bit may be set; allowing multiple priorities to be mapped to one 2340 * COS. */ 2341 #define NIG_REG_P1_RX_COS2_PRIORITY_MASK 0x186f8 2342 /* [R 1] RX FIFO for receiving data from MAC is empty. */ 2343 #define NIG_REG_P1_RX_MACFIFO_EMPTY 0x1858c 2344 /* [R 1] TLLH FIFO is empty. */ 2345 #define NIG_REG_P1_TLLH_FIFO_EMPTY 0x18338 2346 /* [RW 32] Specify which of the credit registers the client is to be mapped 2347 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are 2348 * for client 0; bits [35:32] are for client 8. For clients that are not 2349 * subject to WFQ credit blocking - their specifications here are not used. 2350 * This is a new register (with 2_) added in E3 B0 to accommodate the 9 2351 * input clients to ETS arbiter. The reset default is set for management and 2352 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to 2353 * use credit registers 0-5 respectively (0x543210876). Note that credit 2354 * registers can not be shared between clients. Note also that there are 2355 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only 2356 * credit registers 0-5 are valid. This register should be configured 2357 * appropriately before enabling WFQ. */ 2358 #define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x186e8 2359 /* [RW 4] Specify which of the credit registers the client is to be mapped 2360 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are 2361 * for client 0; bits [35:32] are for client 8. For clients that are not 2362 * subject to WFQ credit blocking - their specifications here are not used. 2363 * This is a new register (with 2_) added in E3 B0 to accommodate the 9 2364 * input clients to ETS arbiter. The reset default is set for management and 2365 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to 2366 * use credit registers 0-5 respectively (0x543210876). Note that credit 2367 * registers can not be shared between clients. Note also that there are 2368 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only 2369 * credit registers 0-5 are valid. This register should be configured 2370 * appropriately before enabling WFQ. */ 2371 #define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x186ec 2372 /* [RW 9] Specify whether the client competes directly in the strict 2373 * priority arbiter. The bits are mapped according to client ID (client IDs 2374 * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic 2375 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 2376 * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. 2377 * Default value is set to enable strict priorities for all clients. */ 2378 #define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT 0x18234 2379 /* [RW 9] Specify whether the client is subject to WFQ credit blocking. The 2380 * bits are mapped according to client ID (client IDs are defined in 2381 * tx_arb_priority_client2): 0-management; 1-debug traffic from this port; 2382 * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 2383 * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is 2384 * 0 for not using WFQ credit blocking. */ 2385 #define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x18238 2386 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 0x18258 2387 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 0x1825c 2388 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 0x18260 2389 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 0x18264 2390 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 0x18268 2391 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 0x186f4 2392 /* [RW 32] Specify the weight (in bytes) to be added to credit register 0 2393 * when it is time to increment. */ 2394 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 0x18244 2395 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 0x18248 2396 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 0x1824c 2397 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 0x18250 2398 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 0x18254 2399 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 0x186f0 2400 /* [RW 12] Specify the number of strict priority arbitration slots between 2401 two round-robin arbitration slots to avoid starvation. A value of 0 means 2402 no strict priority cycles - the strict priority with anti-starvation 2403 arbiter becomes a round-robin arbiter. */ 2404 #define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS 0x18240 2405 /* [RW 32] Specify the client number to be assigned to each priority of the 2406 strict priority arbiter. This register specifies bits 31:0 of the 36-bit 2407 value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 2408 client; bits [35-32] are for priority 8 client. The clients are assigned 2409 the following IDs: 0-management; 1-debug traffic from this port; 2-debug 2410 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 2411 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is 2412 set to 0x345678021. This is a new register (with 2_) added in E3 B0 to 2413 accommodate the 9 input clients to ETS arbiter. Note that this register 2414 is the same as the one for port 0, except that port 1 only has COS 0-2 2415 traffic. There is no traffic for COS 3-5 of port 1. */ 2416 #define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB 0x186e0 2417 /* [RW 4] Specify the client number to be assigned to each priority of the 2418 strict priority arbiter. This register specifies bits 35:32 of the 36-bit 2419 value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 2420 client; bits [35-32] are for priority 8 client. The clients are assigned 2421 the following IDs: 0-management; 1-debug traffic from this port; 2-debug 2422 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 2423 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is 2424 set to 0x345678021. This is a new register (with 2_) added in E3 B0 to 2425 accommodate the 9 input clients to ETS arbiter. Note that this register 2426 is the same as the one for port 0, except that port 1 only has COS 0-2 2427 traffic. There is no traffic for COS 3-5 of port 1. */ 2428 #define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB 0x186e4 2429 /* [R 1] TX FIFO for transmitting data to MAC is empty. */ 2430 #define NIG_REG_P1_TX_MACFIFO_EMPTY 0x18594 2431 /* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP 2432 * packets to BRB LB interface to forward the packet to the host. All 2433 * packets from MCP are forwarded to the network when this bit is cleared - 2434 * regardless of the configured destination in tx_mng_destination register. 2435 */ 2436 #define NIG_REG_P1_TX_MNG_HOST_ENABLE 0x182f8 2437 /* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets 2438 forwarded to the host. */ 2439 #define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY 0x182b8 2440 /* [RW 32] Specify the upper bound that credit register 0 is allowed to 2441 * reach. */ 2442 /* [RW 1] Pause enable for port0. This register may get 1 only when 2443 ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same 2444 port */ 2445 #define NIG_REG_PAUSE_ENABLE_0 0x160c0 2446 #define NIG_REG_PAUSE_ENABLE_1 0x160c4 2447 /* [RW 1] Input enable for RX PBF LP IF */ 2448 #define NIG_REG_PBF_LB_IN_EN 0x100b4 2449 /* [RW 1] Value of this register will be transmitted to port swap when 2450 ~nig_registers_strap_override.strap_override =1 */ 2451 #define NIG_REG_PORT_SWAP 0x10394 2452 /* [RW 1] PPP enable for port0. This register may get 1 only when 2453 * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the 2454 * same port */ 2455 #define NIG_REG_PPP_ENABLE_0 0x160b0 2456 #define NIG_REG_PPP_ENABLE_1 0x160b4 2457 /* [RW 1] output enable for RX parser descriptor IF */ 2458 #define NIG_REG_PRS_EOP_OUT_EN 0x10104 2459 /* [RW 1] Input enable for RX parser request IF */ 2460 #define NIG_REG_PRS_REQ_IN_EN 0x100b8 2461 /* [RW 5] control to serdes - CL45 DEVAD */ 2462 #define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370 2463 /* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */ 2464 #define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c 2465 /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */ 2466 #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374 2467 /* [R 1] status from serdes0 that inputs to interrupt logic of link status */ 2468 #define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578 2469 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure 2470 for port0 */ 2471 #define NIG_REG_STAT0_BRB_DISCARD 0x105f0 2472 /* [R 32] Rx statistics : In user packets truncated due to BRB backpressure 2473 for port0 */ 2474 #define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8 2475 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that 2476 between 1024 and 1522 bytes for port0 */ 2477 #define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750 2478 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that 2479 between 1523 bytes and above for port0 */ 2480 #define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760 2481 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure 2482 for port1 */ 2483 #define NIG_REG_STAT1_BRB_DISCARD 0x10628 2484 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that 2485 between 1024 and 1522 bytes for port1 */ 2486 #define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0 2487 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that 2488 between 1523 bytes and above for port1 */ 2489 #define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0 2490 /* [WB_R 64] Rx statistics : User octets received for LP */ 2491 #define NIG_REG_STAT2_BRB_OCTET 0x107e0 2492 #define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328 2493 #define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c 2494 /* [RW 1] port swap mux selection. If this register equal to 0 then port 2495 swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then 2496 ort swap is equal to ~nig_registers_port_swap.port_swap */ 2497 #define NIG_REG_STRAP_OVERRIDE 0x10398 2498 /* [RW 1] output enable for RX_XCM0 IF */ 2499 #define NIG_REG_XCM0_OUT_EN 0x100f0 2500 /* [RW 1] output enable for RX_XCM1 IF */ 2501 #define NIG_REG_XCM1_OUT_EN 0x100f4 2502 /* [RW 1] control to xgxs - remote PHY in-band MDIO */ 2503 #define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348 2504 /* [RW 5] control to xgxs - CL45 DEVAD */ 2505 #define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c 2506 /* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */ 2507 #define NIG_REG_XGXS0_CTRL_MD_ST 0x10338 2508 /* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */ 2509 #define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340 2510 /* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */ 2511 #define NIG_REG_XGXS0_STATUS_LINK10G 0x10680 2512 /* [R 4] status from xgxs0 that inputs to interrupt logic of link status */ 2513 #define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684 2514 /* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */ 2515 #define NIG_REG_XGXS_LANE_SEL_P0 0x102e8 2516 /* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */ 2517 #define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0 2518 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0) 2519 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9) 2520 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15) 2521 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18) 2522 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18 2523 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter. */ 2524 #define PBF_REG_COS0_UPPER_BOUND 0x15c05c 2525 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter 2526 * of port 0. */ 2527 #define PBF_REG_COS0_UPPER_BOUND_P0 0x15c2cc 2528 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter 2529 * of port 1. */ 2530 #define PBF_REG_COS0_UPPER_BOUND_P1 0x15c2e4 2531 /* [RW 31] The weight of COS0 in the ETS command arbiter. */ 2532 #define PBF_REG_COS0_WEIGHT 0x15c054 2533 /* [RW 31] The weight of COS0 in port 0 ETS command arbiter. */ 2534 #define PBF_REG_COS0_WEIGHT_P0 0x15c2a8 2535 /* [RW 31] The weight of COS0 in port 1 ETS command arbiter. */ 2536 #define PBF_REG_COS0_WEIGHT_P1 0x15c2c0 2537 /* [RW 31] The upper bound of the weight of COS1 in the ETS command arbiter. */ 2538 #define PBF_REG_COS1_UPPER_BOUND 0x15c060 2539 /* [RW 31] The weight of COS1 in the ETS command arbiter. */ 2540 #define PBF_REG_COS1_WEIGHT 0x15c058 2541 /* [RW 31] The weight of COS1 in port 0 ETS command arbiter. */ 2542 #define PBF_REG_COS1_WEIGHT_P0 0x15c2ac 2543 /* [RW 31] The weight of COS1 in port 1 ETS command arbiter. */ 2544 #define PBF_REG_COS1_WEIGHT_P1 0x15c2c4 2545 /* [RW 31] The weight of COS2 in port 0 ETS command arbiter. */ 2546 #define PBF_REG_COS2_WEIGHT_P0 0x15c2b0 2547 /* [RW 31] The weight of COS2 in port 1 ETS command arbiter. */ 2548 #define PBF_REG_COS2_WEIGHT_P1 0x15c2c8 2549 /* [RW 31] The weight of COS3 in port 0 ETS command arbiter. */ 2550 #define PBF_REG_COS3_WEIGHT_P0 0x15c2b4 2551 /* [RW 31] The weight of COS4 in port 0 ETS command arbiter. */ 2552 #define PBF_REG_COS4_WEIGHT_P0 0x15c2b8 2553 /* [RW 31] The weight of COS5 in port 0 ETS command arbiter. */ 2554 #define PBF_REG_COS5_WEIGHT_P0 0x15c2bc 2555 /* [R 11] Current credit for the LB queue in the tx port buffers in 16 byte 2556 * lines. */ 2557 #define PBF_REG_CREDIT_LB_Q 0x140338 2558 /* [R 11] Current credit for queue 0 in the tx port buffers in 16 byte 2559 * lines. */ 2560 #define PBF_REG_CREDIT_Q0 0x14033c 2561 /* [R 11] Current credit for queue 1 in the tx port buffers in 16 byte 2562 * lines. */ 2563 #define PBF_REG_CREDIT_Q1 0x140340 2564 /* [RW 1] Disable processing further tasks from port 0 (after ending the 2565 current task in process). */ 2566 #define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c 2567 /* [RW 1] Disable processing further tasks from port 1 (after ending the 2568 current task in process). */ 2569 #define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060 2570 /* [RW 1] Disable processing further tasks from port 4 (after ending the 2571 current task in process). */ 2572 #define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c 2573 #define PBF_REG_DISABLE_PF 0x1402e8 2574 /* [RW 18] For port 0: For each client that is subject to WFQ (the 2575 * corresponding bit is 1); indicates to which of the credit registers this 2576 * client is mapped. For clients which are not credit blocked; their mapping 2577 * is dont care. */ 2578 #define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 0x15c288 2579 /* [RW 9] For port 1: For each client that is subject to WFQ (the 2580 * corresponding bit is 1); indicates to which of the credit registers this 2581 * client is mapped. For clients which are not credit blocked; their mapping 2582 * is dont care. */ 2583 #define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 0x15c28c 2584 /* [RW 6] For port 0: Bit per client to indicate if the client competes in 2585 * the strict priority arbiter directly (corresponding bit = 1); or first 2586 * goes to the RR arbiter (corresponding bit = 0); and then competes in the 2587 * lowest priority in the strict-priority arbiter. */ 2588 #define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 0x15c278 2589 /* [RW 3] For port 1: Bit per client to indicate if the client competes in 2590 * the strict priority arbiter directly (corresponding bit = 1); or first 2591 * goes to the RR arbiter (corresponding bit = 0); and then competes in the 2592 * lowest priority in the strict-priority arbiter. */ 2593 #define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 0x15c27c 2594 /* [RW 6] For port 0: Bit per client to indicate if the client is subject to 2595 * WFQ credit blocking (corresponding bit = 1). */ 2596 #define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 0x15c280 2597 /* [RW 3] For port 0: Bit per client to indicate if the client is subject to 2598 * WFQ credit blocking (corresponding bit = 1). */ 2599 #define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 0x15c284 2600 /* [RW 16] For port 0: The number of strict priority arbitration slots 2601 * between 2 RR arbitration slots. A value of 0 means no strict priority 2602 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR 2603 * arbiter. */ 2604 #define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 0x15c2a0 2605 /* [RW 16] For port 1: The number of strict priority arbitration slots 2606 * between 2 RR arbitration slots. A value of 0 means no strict priority 2607 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR 2608 * arbiter. */ 2609 #define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 0x15c2a4 2610 /* [RW 18] For port 0: Indicates which client is connected to each priority 2611 * in the strict-priority arbiter. Priority 0 is the highest priority, and 2612 * priority 5 is the lowest; to which the RR output is connected to (this is 2613 * not configurable). */ 2614 #define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 0x15c270 2615 /* [RW 9] For port 1: Indicates which client is connected to each priority 2616 * in the strict-priority arbiter. Priority 0 is the highest priority, and 2617 * priority 5 is the lowest; to which the RR output is connected to (this is 2618 * not configurable). */ 2619 #define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 0x15c274 2620 /* [RW 1] Indicates that ETS is performed between the COSes in the command 2621 * arbiter. If reset strict priority w/ anti-starvation will be performed 2622 * w/o WFQ. */ 2623 #define PBF_REG_ETS_ENABLED 0x15c050 2624 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2625 * Ethernet header. */ 2626 #define PBF_REG_HDRS_AFTER_BASIC 0x15c0a8 2627 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */ 2628 #define PBF_REG_HDRS_AFTER_TAG_0 0x15c0b8 2629 /* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest 2630 * priority in the command arbiter. */ 2631 #define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04c 2632 #define PBF_REG_IF_ENABLE_REG 0x140044 2633 /* [RW 1] Init bit. When set the initial credits are copied to the credit 2634 registers (except the port credits). Should be set and then reset after 2635 the configuration of the block has ended. */ 2636 #define PBF_REG_INIT 0x140000 2637 /* [RW 11] Initial credit for the LB queue in the tx port buffers in 16 byte 2638 * lines. */ 2639 #define PBF_REG_INIT_CRD_LB_Q 0x15c248 2640 /* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte 2641 * lines. */ 2642 #define PBF_REG_INIT_CRD_Q0 0x15c230 2643 /* [RW 11] Initial credit for queue 1 in the tx port buffers in 16 byte 2644 * lines. */ 2645 #define PBF_REG_INIT_CRD_Q1 0x15c234 2646 /* [RW 1] Init bit for port 0. When set the initial credit of port 0 is 2647 copied to the credit register. Should be set and then reset after the 2648 configuration of the port has ended. */ 2649 #define PBF_REG_INIT_P0 0x140004 2650 /* [RW 1] Init bit for port 1. When set the initial credit of port 1 is 2651 copied to the credit register. Should be set and then reset after the 2652 configuration of the port has ended. */ 2653 #define PBF_REG_INIT_P1 0x140008 2654 /* [RW 1] Init bit for port 4. When set the initial credit of port 4 is 2655 copied to the credit register. Should be set and then reset after the 2656 configuration of the port has ended. */ 2657 #define PBF_REG_INIT_P4 0x14000c 2658 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2659 * the LB queue. Reset upon init. */ 2660 #define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q 0x140354 2661 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2662 * queue 0. Reset upon init. */ 2663 #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 0x140358 2664 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2665 * queue 1. Reset upon init. */ 2666 #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 0x14035c 2667 /* [RW 1] Enable for mac interface 0. */ 2668 #define PBF_REG_MAC_IF0_ENABLE 0x140030 2669 /* [RW 1] Enable for mac interface 1. */ 2670 #define PBF_REG_MAC_IF1_ENABLE 0x140034 2671 /* [RW 1] Enable for the loopback interface. */ 2672 #define PBF_REG_MAC_LB_ENABLE 0x140040 2673 /* [RW 6] Bit-map indicating which headers must appear in the packet */ 2674 #define PBF_REG_MUST_HAVE_HDRS 0x15c0c4 2675 /* [RW 16] The number of strict priority arbitration slots between 2 RR 2676 * arbitration slots. A value of 0 means no strict priority cycles; i.e. the 2677 * strict-priority w/ anti-starvation arbiter is a RR arbiter. */ 2678 #define PBF_REG_NUM_STRICT_ARB_SLOTS 0x15c064 2679 /* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause 2680 not suppoterd. */ 2681 #define PBF_REG_P0_ARB_THRSH 0x1400e4 2682 /* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */ 2683 #define PBF_REG_P0_CREDIT 0x140200 2684 /* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte 2685 lines. */ 2686 #define PBF_REG_P0_INIT_CRD 0x1400d0 2687 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2688 * port 0. Reset upon init. */ 2689 #define PBF_REG_P0_INTERNAL_CRD_FREED_CNT 0x140308 2690 /* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */ 2691 #define PBF_REG_P0_PAUSE_ENABLE 0x140014 2692 /* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */ 2693 #define PBF_REG_P0_TASK_CNT 0x140204 2694 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines 2695 * freed from the task queue of port 0. Reset upon init. */ 2696 #define PBF_REG_P0_TQ_LINES_FREED_CNT 0x1402f0 2697 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 0. */ 2698 #define PBF_REG_P0_TQ_OCCUPANCY 0x1402fc 2699 /* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port 2700 * buffers in 16 byte lines. */ 2701 #define PBF_REG_P1_CREDIT 0x140208 2702 /* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port 2703 * buffers in 16 byte lines. */ 2704 #define PBF_REG_P1_INIT_CRD 0x1400d4 2705 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2706 * port 1. Reset upon init. */ 2707 #define PBF_REG_P1_INTERNAL_CRD_FREED_CNT 0x14030c 2708 /* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */ 2709 #define PBF_REG_P1_TASK_CNT 0x14020c 2710 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines 2711 * freed from the task queue of port 1. Reset upon init. */ 2712 #define PBF_REG_P1_TQ_LINES_FREED_CNT 0x1402f4 2713 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 1. */ 2714 #define PBF_REG_P1_TQ_OCCUPANCY 0x140300 2715 /* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */ 2716 #define PBF_REG_P4_CREDIT 0x140210 2717 /* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte 2718 lines. */ 2719 #define PBF_REG_P4_INIT_CRD 0x1400e0 2720 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2721 * port 4. Reset upon init. */ 2722 #define PBF_REG_P4_INTERNAL_CRD_FREED_CNT 0x140310 2723 /* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */ 2724 #define PBF_REG_P4_TASK_CNT 0x140214 2725 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines 2726 * freed from the task queue of port 4. Reset upon init. */ 2727 #define PBF_REG_P4_TQ_LINES_FREED_CNT 0x1402f8 2728 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 4. */ 2729 #define PBF_REG_P4_TQ_OCCUPANCY 0x140304 2730 /* [RW 5] Interrupt mask register #0 read/write */ 2731 #define PBF_REG_PBF_INT_MASK 0x1401d4 2732 /* [R 5] Interrupt register #0 read */ 2733 #define PBF_REG_PBF_INT_STS 0x1401c8 2734 /* [RW 20] Parity mask register #0 read/write */ 2735 #define PBF_REG_PBF_PRTY_MASK 0x1401e4 2736 /* [RC 20] Parity register #0 read clear */ 2737 #define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc 2738 /* [RW 16] The Ethernet type value for L2 tag 0 */ 2739 #define PBF_REG_TAG_ETHERTYPE_0 0x15c090 2740 /* [RW 4] The length of the info field for L2 tag 0. The length is between 2741 * 2B and 14B; in 2B granularity */ 2742 #define PBF_REG_TAG_LEN_0 0x15c09c 2743 /* [R 32] Cyclic counter for number of 8 byte lines freed from the LB task 2744 * queue. Reset upon init. */ 2745 #define PBF_REG_TQ_LINES_FREED_CNT_LB_Q 0x14038c 2746 /* [R 32] Cyclic counter for number of 8 byte lines freed from the task 2747 * queue 0. Reset upon init. */ 2748 #define PBF_REG_TQ_LINES_FREED_CNT_Q0 0x140390 2749 /* [R 32] Cyclic counter for number of 8 byte lines freed from task queue 1. 2750 * Reset upon init. */ 2751 #define PBF_REG_TQ_LINES_FREED_CNT_Q1 0x140394 2752 /* [R 13] Number of 8 bytes lines occupied in the task queue of the LB 2753 * queue. */ 2754 #define PBF_REG_TQ_OCCUPANCY_LB_Q 0x1403a8 2755 /* [R 13] Number of 8 bytes lines occupied in the task queue of queue 0. */ 2756 #define PBF_REG_TQ_OCCUPANCY_Q0 0x1403ac 2757 /* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */ 2758 #define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b0 2759 #define PB_REG_CONTROL 0 2760 /* [RW 2] Interrupt mask register #0 read/write */ 2761 #define PB_REG_PB_INT_MASK 0x28 2762 /* [R 2] Interrupt register #0 read */ 2763 #define PB_REG_PB_INT_STS 0x1c 2764 /* [RW 4] Parity mask register #0 read/write */ 2765 #define PB_REG_PB_PRTY_MASK 0x38 2766 /* [R 4] Parity register #0 read */ 2767 #define PB_REG_PB_PRTY_STS 0x2c 2768 /* [RC 4] Parity register #0 read clear */ 2769 #define PB_REG_PB_PRTY_STS_CLR 0x30 2770 #define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 2771 #define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8) 2772 #define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1) 2773 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN (0x1<<6) 2774 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7) 2775 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4) 2776 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3) 2777 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5) 2778 #define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN (0x1<<2) 2779 /* [R 8] Config space A attention dirty bits. Each bit indicates that the 2780 * corresponding PF generates config space A attention. Set by PXP. Reset by 2781 * MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits 2782 * from both paths. */ 2783 #define PGLUE_B_REG_CFG_SPACE_A_REQUEST 0x9010 2784 /* [R 8] Config space B attention dirty bits. Each bit indicates that the 2785 * corresponding PF generates config space B attention. Set by PXP. Reset by 2786 * MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits 2787 * from both paths. */ 2788 #define PGLUE_B_REG_CFG_SPACE_B_REQUEST 0x9014 2789 /* [RW 1] Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1 2790 * - enable. */ 2791 #define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE 0x9194 2792 /* [RW 18] Type B VF inbound interrupt table for CSDM: bits[17:9]-mask; 2793 * its[8:0]-address. Bits [1:0] must be zero (DW resolution address). */ 2794 #define PGLUE_B_REG_CSDM_INB_INT_B_VF 0x916c 2795 /* [RW 1] Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1 2796 * - enable. */ 2797 #define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE 0x919c 2798 /* [RW 16] Start offset of CSDM zone A (queue zone) in the internal RAM */ 2799 #define PGLUE_B_REG_CSDM_START_OFFSET_A 0x9100 2800 /* [RW 16] Start offset of CSDM zone B (legacy zone) in the internal RAM */ 2801 #define PGLUE_B_REG_CSDM_START_OFFSET_B 0x9108 2802 /* [RW 5] VF Shift of CSDM zone B (legacy zone) in the internal RAM */ 2803 #define PGLUE_B_REG_CSDM_VF_SHIFT_B 0x9110 2804 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */ 2805 #define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF 0x91ac 2806 /* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates 2807 * that the FLR register of the corresponding PF was set. Set by PXP. Reset 2808 * by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits 2809 * from both paths. */ 2810 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0 0x9028 2811 /* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1 2812 * to a bit in this register in order to clear the corresponding bit in 2813 * flr_request_pf_7_0 register. Note: register contains bits from both 2814 * paths. */ 2815 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR 0x9418 2816 /* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit 2817 * indicates that the FLR register of the corresponding VF was set. Set by 2818 * PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr. */ 2819 #define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x9024 2820 /* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit 2821 * indicates that the FLR register of the corresponding VF was set. Set by 2822 * PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr. */ 2823 #define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x9018 2824 /* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit 2825 * indicates that the FLR register of the corresponding VF was set. Set by 2826 * PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr. */ 2827 #define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x901c 2828 /* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit 2829 * indicates that the FLR register of the corresponding VF was set. Set by 2830 * PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr. */ 2831 #define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x9020 2832 /* [R 8] Each bit indicates an incorrect behavior in user RX interface. Bit 2833 * 0 - Target memory read arrived with a correctable error. Bit 1 - Target 2834 * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW 2835 * arrived with a correctable error. Bit 3 - Configuration RW arrived with 2836 * an uncorrectable error. Bit 4 - Completion with Configuration Request 2837 * Retry Status. Bit 5 - Expansion ROM access received with a write request. 2838 * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and 2839 * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010; 2840 * and pcie_rx_last not asserted. */ 2841 #define PGLUE_B_REG_INCORRECT_RCV_DETAILS 0x9068 2842 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942c 2843 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x9430 2844 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x9434 2845 #define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x9438 2846 /* [R 9] Interrupt register #0 read */ 2847 #define PGLUE_B_REG_PGLUE_B_INT_STS 0x9298 2848 /* [RC 9] Interrupt register #0 read clear */ 2849 #define PGLUE_B_REG_PGLUE_B_INT_STS_CLR 0x929c 2850 /* [RW 2] Parity mask register #0 read/write */ 2851 #define PGLUE_B_REG_PGLUE_B_PRTY_MASK 0x92b4 2852 /* [R 2] Parity register #0 read */ 2853 #define PGLUE_B_REG_PGLUE_B_PRTY_STS 0x92a8 2854 /* [RC 2] Parity register #0 read clear */ 2855 #define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR 0x92ac 2856 /* [R 13] Details of first request received with error. [2:0] - PFID. [3] - 2857 * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion 2858 * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 - 2859 * completer abort. 3 - Illegal value for this field. [12] valid - indicates 2860 * if there was a completion error since the last time this register was 2861 * cleared. */ 2862 #define PGLUE_B_REG_RX_ERR_DETAILS 0x9080 2863 /* [R 18] Details of first ATS Translation Completion request received with 2864 * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code - 2865 * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 - 2866 * unsupported request. 2 - completer abort. 3 - Illegal value for this 2867 * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a 2868 * completion error since the last time this register was cleared. */ 2869 #define PGLUE_B_REG_RX_TCPL_ERR_DETAILS 0x9084 2870 /* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to 2871 * a bit in this register in order to clear the corresponding bit in 2872 * shadow_bme_pf_7_0 register. MCP should never use this unless a 2873 * work-around is needed. Note: register contains bits from both paths. */ 2874 #define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR 0x9458 2875 /* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the 2876 * VF enable register of the corresponding PF is written to 0 and was 2877 * previously 1. Set by PXP. Reset by MCP writing 1 to 2878 * sr_iov_disabled_request_clr. Note: register contains bits from both 2879 * paths. */ 2880 #define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x9030 2881 /* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read 2882 * completion did not return yet. 1 - tag is unused. Same functionality as 2883 * pxp2_registers_pgl_exp_rom_data2 for tags 0-31. */ 2884 #define PGLUE_B_REG_TAGS_63_32 0x9244 2885 /* [RW 1] Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1 2886 * - enable. */ 2887 #define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE 0x9170 2888 /* [RW 16] Start offset of TSDM zone A (queue zone) in the internal RAM */ 2889 #define PGLUE_B_REG_TSDM_START_OFFSET_A 0x90c4 2890 /* [RW 16] Start offset of TSDM zone B (legacy zone) in the internal RAM */ 2891 #define PGLUE_B_REG_TSDM_START_OFFSET_B 0x90cc 2892 /* [RW 5] VF Shift of TSDM zone B (legacy zone) in the internal RAM */ 2893 #define PGLUE_B_REG_TSDM_VF_SHIFT_B 0x90d4 2894 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */ 2895 #define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF 0x91a0 2896 /* [R 32] Address [31:0] of first read request not submitted due to error */ 2897 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x9098 2898 /* [R 32] Address [63:32] of first read request not submitted due to error */ 2899 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x909c 2900 /* [R 31] Details of first read request not submitted due to error. [4:0] 2901 * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request. 2902 * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] - 2903 * VFID. */ 2904 #define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x90a0 2905 /* [R 26] Details of first read request not submitted due to error. [15:0] 2906 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type - 2907 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared; 2908 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent 2909 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid - 2910 * indicates if there was a request not submitted due to error since the 2911 * last time this register was cleared. */ 2912 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x90a4 2913 /* [R 32] Address [31:0] of first write request not submitted due to error */ 2914 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x9088 2915 /* [R 32] Address [63:32] of first write request not submitted due to error */ 2916 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x908c 2917 /* [R 31] Details of first write request not submitted due to error. [4:0] 2918 * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] 2919 * - VFID. */ 2920 #define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x9090 2921 /* [R 26] Details of first write request not submitted due to error. [15:0] 2922 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type - 2923 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared; 2924 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent 2925 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid - 2926 * indicates if there was a request not submitted due to error since the 2927 * last time this register was cleared. */ 2928 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x9094 2929 /* [RW 10] Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask; 2930 * its[4:0]-address relative to start_offset_a. Bits [1:0] can have any 2931 * value (Byte resolution address). */ 2932 #define PGLUE_B_REG_USDM_INB_INT_A_0 0x9128 2933 #define PGLUE_B_REG_USDM_INB_INT_A_1 0x912c 2934 #define PGLUE_B_REG_USDM_INB_INT_A_2 0x9130 2935 #define PGLUE_B_REG_USDM_INB_INT_A_3 0x9134 2936 #define PGLUE_B_REG_USDM_INB_INT_A_4 0x9138 2937 #define PGLUE_B_REG_USDM_INB_INT_A_5 0x913c 2938 #define PGLUE_B_REG_USDM_INB_INT_A_6 0x9140 2939 /* [RW 1] Type A PF enable inbound interrupt table for USDM. 0 - disable; 1 2940 * - enable. */ 2941 #define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE 0x917c 2942 /* [RW 1] Type A VF enable inbound interrupt table for USDM. 0 - disable; 1 2943 * - enable. */ 2944 #define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE 0x9180 2945 /* [RW 1] Type B VF enable inbound interrupt table for USDM. 0 - disable; 1 2946 * - enable. */ 2947 #define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE 0x9184 2948 /* [RW 16] Start offset of USDM zone A (queue zone) in the internal RAM */ 2949 #define PGLUE_B_REG_USDM_START_OFFSET_A 0x90d8 2950 /* [RW 16] Start offset of USDM zone B (legacy zone) in the internal RAM */ 2951 #define PGLUE_B_REG_USDM_START_OFFSET_B 0x90e0 2952 /* [RW 5] VF Shift of USDM zone B (legacy zone) in the internal RAM */ 2953 #define PGLUE_B_REG_USDM_VF_SHIFT_B 0x90e8 2954 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */ 2955 #define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF 0x91a4 2956 /* [R 26] Details of first target VF request accessing VF GRC space that 2957 * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write. 2958 * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a 2959 * request accessing VF GRC space that failed permission check since the 2960 * last time this register was cleared. Permission checks are: function 2961 * permission; R/W permission; address range permission. */ 2962 #define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS 0x9234 2963 /* [R 31] Details of first target VF request with length violation (too many 2964 * DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address). 2965 * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30] 2966 * valid - indicates if there was a request with length violation since the 2967 * last time this register was cleared. Length violations: length of more 2968 * than 2DWs; length of 2DWs and address not QW aligned; window is GRC and 2969 * length is more than 1 DW. */ 2970 #define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS 0x9230 2971 /* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates 2972 * that there was a completion with uncorrectable error for the 2973 * corresponding PF. Set by PXP. Reset by MCP writing 1 to 2974 * was_error_pf_7_0_clr. */ 2975 #define PGLUE_B_REG_WAS_ERROR_PF_7_0 0x907c 2976 /* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1 2977 * to a bit in this register in order to clear the corresponding bit in 2978 * flr_request_pf_7_0 register. */ 2979 #define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR 0x9470 2980 /* [R 32] Was_error indication dirty bits for VFs 96 to 127. Each bit 2981 * indicates that there was a completion with uncorrectable error for the 2982 * corresponding VF. Set by PXP. Reset by MCP writing 1 to 2983 * was_error_vf_127_96_clr. */ 2984 #define PGLUE_B_REG_WAS_ERROR_VF_127_96 0x9078 2985 /* [W 32] Was_error indication dirty bits clear for VFs 96 to 127. MCP 2986 * writes 1 to a bit in this register in order to clear the corresponding 2987 * bit in was_error_vf_127_96 register. */ 2988 #define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR 0x9474 2989 /* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit 2990 * indicates that there was a completion with uncorrectable error for the 2991 * corresponding VF. Set by PXP. Reset by MCP writing 1 to 2992 * was_error_vf_31_0_clr. */ 2993 #define PGLUE_B_REG_WAS_ERROR_VF_31_0 0x906c 2994 /* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes 2995 * 1 to a bit in this register in order to clear the corresponding bit in 2996 * was_error_vf_31_0 register. */ 2997 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x9478 2998 /* [R 32] Was_error indication dirty bits for VFs 32 to 63. Each bit 2999 * indicates that there was a completion with uncorrectable error for the 3000 * corresponding VF. Set by PXP. Reset by MCP writing 1 to 3001 * was_error_vf_63_32_clr. */ 3002 #define PGLUE_B_REG_WAS_ERROR_VF_63_32 0x9070 3003 /* [W 32] Was_error indication dirty bits clear for VFs 32 to 63. MCP writes 3004 * 1 to a bit in this register in order to clear the corresponding bit in 3005 * was_error_vf_63_32 register. */ 3006 #define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR 0x947c 3007 /* [R 32] Was_error indication dirty bits for VFs 64 to 95. Each bit 3008 * indicates that there was a completion with uncorrectable error for the 3009 * corresponding VF. Set by PXP. Reset by MCP writing 1 to 3010 * was_error_vf_95_64_clr. */ 3011 #define PGLUE_B_REG_WAS_ERROR_VF_95_64 0x9074 3012 /* [W 32] Was_error indication dirty bits clear for VFs 64 to 95. MCP writes 3013 * 1 to a bit in this register in order to clear the corresponding bit in 3014 * was_error_vf_95_64 register. */ 3015 #define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR 0x9480 3016 /* [RW 1] Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1 3017 * - enable. */ 3018 #define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE 0x9188 3019 /* [RW 16] Start offset of XSDM zone A (queue zone) in the internal RAM */ 3020 #define PGLUE_B_REG_XSDM_START_OFFSET_A 0x90ec 3021 /* [RW 16] Start offset of XSDM zone B (legacy zone) in the internal RAM */ 3022 #define PGLUE_B_REG_XSDM_START_OFFSET_B 0x90f4 3023 /* [RW 5] VF Shift of XSDM zone B (legacy zone) in the internal RAM */ 3024 #define PGLUE_B_REG_XSDM_VF_SHIFT_B 0x90fc 3025 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */ 3026 #define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF 0x91a8 3027 #define PRS_REG_A_PRSU_20 0x40134 3028 /* [R 8] debug only: CFC load request current credit. Transaction based. */ 3029 #define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164 3030 /* [R 8] debug only: CFC search request current credit. Transaction based. */ 3031 #define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168 3032 /* [RW 6] The initial credit for the search message to the CFC interface. 3033 Credit is transaction based. */ 3034 #define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c 3035 /* [RW 24] CID for port 0 if no match */ 3036 #define PRS_REG_CID_PORT_0 0x400fc 3037 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC 3038 load response is reset and packet type is 0. Used in packet start message 3039 to TCM. */ 3040 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc 3041 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0 3042 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4 3043 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8 3044 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec 3045 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0 3046 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC 3047 load response is set and packet type is 0. Used in packet start message 3048 to TCM. */ 3049 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc 3050 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0 3051 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4 3052 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8 3053 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc 3054 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0 3055 /* [RW 32] The CM header for a match and packet type 1 for loopback port. 3056 Used in packet start message to TCM. */ 3057 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c 3058 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0 3059 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4 3060 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8 3061 /* [RW 32] The CM header for a match and packet type 0. Used in packet start 3062 message to TCM. */ 3063 #define PRS_REG_CM_HDR_TYPE_0 0x40078 3064 #define PRS_REG_CM_HDR_TYPE_1 0x4007c 3065 #define PRS_REG_CM_HDR_TYPE_2 0x40080 3066 #define PRS_REG_CM_HDR_TYPE_3 0x40084 3067 #define PRS_REG_CM_HDR_TYPE_4 0x40088 3068 /* [RW 32] The CM header in case there was not a match on the connection */ 3069 #define PRS_REG_CM_NO_MATCH_HDR 0x400b8 3070 /* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */ 3071 #define PRS_REG_E1HOV_MODE 0x401c8 3072 /* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet 3073 start message to TCM. */ 3074 #define PRS_REG_EVENT_ID_1 0x40054 3075 #define PRS_REG_EVENT_ID_2 0x40058 3076 #define PRS_REG_EVENT_ID_3 0x4005c 3077 /* [RW 16] The Ethernet type value for FCoE */ 3078 #define PRS_REG_FCOE_TYPE 0x401d0 3079 /* [RW 8] Context region for flush packet with packet type 0. Used in CFC 3080 load request message. */ 3081 #define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004 3082 #define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008 3083 #define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c 3084 #define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010 3085 #define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014 3086 #define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018 3087 #define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c 3088 #define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020 3089 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 3090 * Ethernet header. */ 3091 #define PRS_REG_HDRS_AFTER_BASIC 0x40238 3092 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 3093 * Ethernet header for port 0 packets. */ 3094 #define PRS_REG_HDRS_AFTER_BASIC_PORT_0 0x40270 3095 #define PRS_REG_HDRS_AFTER_BASIC_PORT_1 0x40290 3096 /* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */ 3097 #define PRS_REG_HDRS_AFTER_TAG_0 0x40248 3098 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for 3099 * port 0 packets */ 3100 #define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 0x40280 3101 #define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 0x402a0 3102 /* [RW 4] The increment value to send in the CFC load request message */ 3103 #define PRS_REG_INC_VALUE 0x40048 3104 /* [RW 6] Bit-map indicating which headers must appear in the packet */ 3105 #define PRS_REG_MUST_HAVE_HDRS 0x40254 3106 /* [RW 6] Bit-map indicating which headers must appear in the packet for 3107 * port 0 packets */ 3108 #define PRS_REG_MUST_HAVE_HDRS_PORT_0 0x4028c 3109 #define PRS_REG_MUST_HAVE_HDRS_PORT_1 0x402ac 3110 #define PRS_REG_NIC_MODE 0x40138 3111 /* [RW 8] The 8-bit event ID for cases where there is no match on the 3112 connection. Used in packet start message to TCM. */ 3113 #define PRS_REG_NO_MATCH_EVENT_ID 0x40070 3114 /* [ST 24] The number of input CFC flush packets */ 3115 #define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128 3116 /* [ST 32] The number of cycles the Parser halted its operation since it 3117 could not allocate the next serial number */ 3118 #define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130 3119 /* [ST 24] The number of input packets */ 3120 #define PRS_REG_NUM_OF_PACKETS 0x40124 3121 /* [ST 24] The number of input transparent flush packets */ 3122 #define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c 3123 /* [RW 8] Context region for received Ethernet packet with a match and 3124 packet type 0. Used in CFC load request message */ 3125 #define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028 3126 #define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c 3127 #define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030 3128 #define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034 3129 #define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038 3130 #define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c 3131 #define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040 3132 #define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044 3133 /* [R 2] debug only: Number of pending requests for CAC on port 0. */ 3134 #define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174 3135 /* [R 2] debug only: Number of pending requests for header parsing. */ 3136 #define PRS_REG_PENDING_BRB_PRS_RQ 0x40170 3137 /* [R 1] Interrupt register #0 read */ 3138 #define PRS_REG_PRS_INT_STS 0x40188 3139 /* [RW 8] Parity mask register #0 read/write */ 3140 #define PRS_REG_PRS_PRTY_MASK 0x401a4 3141 /* [R 8] Parity register #0 read */ 3142 #define PRS_REG_PRS_PRTY_STS 0x40198 3143 /* [RC 8] Parity register #0 read clear */ 3144 #define PRS_REG_PRS_PRTY_STS_CLR 0x4019c 3145 /* [RW 8] Context region for pure acknowledge packets. Used in CFC load 3146 request message */ 3147 #define PRS_REG_PURE_REGIONS 0x40024 3148 /* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this 3149 serail number was released by SDM but cannot be used because a previous 3150 serial number was not released. */ 3151 #define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154 3152 /* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this 3153 serail number was released by SDM but cannot be used because a previous 3154 serial number was not released. */ 3155 #define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158 3156 /* [R 4] debug only: SRC current credit. Transaction based. */ 3157 #define PRS_REG_SRC_CURRENT_CREDIT 0x4016c 3158 /* [RW 16] The Ethernet type value for L2 tag 0 */ 3159 #define PRS_REG_TAG_ETHERTYPE_0 0x401d4 3160 /* [RW 4] The length of the info field for L2 tag 0. The length is between 3161 * 2B and 14B; in 2B granularity */ 3162 #define PRS_REG_TAG_LEN_0 0x4022c 3163 /* [R 8] debug only: TCM current credit. Cycle based. */ 3164 #define PRS_REG_TCM_CURRENT_CREDIT 0x40160 3165 /* [R 8] debug only: TSDM current credit. Transaction based. */ 3166 #define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c 3167 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1<<19) 3168 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1<<20) 3169 #define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1<<22) 3170 #define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED (0x1<<23) 3171 #define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED (0x1<<24) 3172 #define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7) 3173 #define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7) 3174 /* [R 6] Debug only: Number of used entries in the data FIFO */ 3175 #define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c 3176 /* [R 7] Debug only: Number of used entries in the header FIFO */ 3177 #define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478 3178 #define PXP2_REG_PGL_ADDR_88_F0 0x120534 3179 /* [R 32] GRC address for configuration access to PCIE config address 0x88. 3180 * any write to this PCIE address will cause a GRC write access to the 3181 * address that's in t this register */ 3182 #define PXP2_REG_PGL_ADDR_88_F1 0x120544 3183 #define PXP2_REG_PGL_ADDR_8C_F0 0x120538 3184 /* [R 32] GRC address for configuration access to PCIE config address 0x8c. 3185 * any write to this PCIE address will cause a GRC write access to the 3186 * address that's in t this register */ 3187 #define PXP2_REG_PGL_ADDR_8C_F1 0x120548 3188 #define PXP2_REG_PGL_ADDR_90_F0 0x12053c 3189 /* [R 32] GRC address for configuration access to PCIE config address 0x90. 3190 * any write to this PCIE address will cause a GRC write access to the 3191 * address that's in t this register */ 3192 #define PXP2_REG_PGL_ADDR_90_F1 0x12054c 3193 #define PXP2_REG_PGL_ADDR_94_F0 0x120540 3194 /* [R 32] GRC address for configuration access to PCIE config address 0x94. 3195 * any write to this PCIE address will cause a GRC write access to the 3196 * address that's in t this register */ 3197 #define PXP2_REG_PGL_ADDR_94_F1 0x120550 3198 #define PXP2_REG_PGL_CONTROL0 0x120490 3199 #define PXP2_REG_PGL_CONTROL1 0x120514 3200 #define PXP2_REG_PGL_DEBUG 0x120520 3201 /* [RW 32] third dword data of expansion rom request. this register is 3202 special. reading from it provides a vector outstanding read requests. if 3203 a bit is zero it means that a read request on the corresponding tag did 3204 not finish yet (not all completions have arrived for it) */ 3205 #define PXP2_REG_PGL_EXP_ROM2 0x120808 3206 /* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask; 3207 its[15:0]-address */ 3208 #define PXP2_REG_PGL_INT_CSDM_0 0x1204f4 3209 #define PXP2_REG_PGL_INT_CSDM_1 0x1204f8 3210 #define PXP2_REG_PGL_INT_CSDM_2 0x1204fc 3211 #define PXP2_REG_PGL_INT_CSDM_3 0x120500 3212 #define PXP2_REG_PGL_INT_CSDM_4 0x120504 3213 #define PXP2_REG_PGL_INT_CSDM_5 0x120508 3214 #define PXP2_REG_PGL_INT_CSDM_6 0x12050c 3215 #define PXP2_REG_PGL_INT_CSDM_7 0x120510 3216 /* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask; 3217 its[15:0]-address */ 3218 #define PXP2_REG_PGL_INT_TSDM_0 0x120494 3219 #define PXP2_REG_PGL_INT_TSDM_1 0x120498 3220 #define PXP2_REG_PGL_INT_TSDM_2 0x12049c 3221 #define PXP2_REG_PGL_INT_TSDM_3 0x1204a0 3222 #define PXP2_REG_PGL_INT_TSDM_4 0x1204a4 3223 #define PXP2_REG_PGL_INT_TSDM_5 0x1204a8 3224 #define PXP2_REG_PGL_INT_TSDM_6 0x1204ac 3225 #define PXP2_REG_PGL_INT_TSDM_7 0x1204b0 3226 /* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask; 3227 its[15:0]-address */ 3228 #define PXP2_REG_PGL_INT_USDM_0 0x1204b4 3229 #define PXP2_REG_PGL_INT_USDM_1 0x1204b8 3230 #define PXP2_REG_PGL_INT_USDM_2 0x1204bc 3231 #define PXP2_REG_PGL_INT_USDM_3 0x1204c0 3232 #define PXP2_REG_PGL_INT_USDM_4 0x1204c4 3233 #define PXP2_REG_PGL_INT_USDM_5 0x1204c8 3234 #define PXP2_REG_PGL_INT_USDM_6 0x1204cc 3235 #define PXP2_REG_PGL_INT_USDM_7 0x1204d0 3236 /* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask; 3237 its[15:0]-address */ 3238 #define PXP2_REG_PGL_INT_XSDM_0 0x1204d4 3239 #define PXP2_REG_PGL_INT_XSDM_1 0x1204d8 3240 #define PXP2_REG_PGL_INT_XSDM_2 0x1204dc 3241 #define PXP2_REG_PGL_INT_XSDM_3 0x1204e0 3242 #define PXP2_REG_PGL_INT_XSDM_4 0x1204e4 3243 #define PXP2_REG_PGL_INT_XSDM_5 0x1204e8 3244 #define PXP2_REG_PGL_INT_XSDM_6 0x1204ec 3245 #define PXP2_REG_PGL_INT_XSDM_7 0x1204f0 3246 /* [RW 3] this field allows one function to pretend being another function 3247 when accessing any BAR mapped resource within the device. the value of 3248 the field is the number of the function that will be accessed 3249 effectively. after software write to this bit it must read it in order to 3250 know that the new value is updated */ 3251 #define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674 3252 #define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678 3253 #define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067c 3254 #define PXP2_REG_PGL_PRETEND_FUNC_F3 0x120680 3255 #define PXP2_REG_PGL_PRETEND_FUNC_F4 0x120684 3256 #define PXP2_REG_PGL_PRETEND_FUNC_F5 0x120688 3257 #define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068c 3258 #define PXP2_REG_PGL_PRETEND_FUNC_F7 0x120690 3259 /* [R 1] this bit indicates that a read request was blocked because of 3260 bus_master_en was deasserted */ 3261 #define PXP2_REG_PGL_READ_BLOCKED 0x120568 3262 #define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8 3263 /* [R 18] debug only */ 3264 #define PXP2_REG_PGL_TXW_CDTS 0x12052c 3265 /* [R 1] this bit indicates that a write request was blocked because of 3266 bus_master_en was deasserted */ 3267 #define PXP2_REG_PGL_WRITE_BLOCKED 0x120564 3268 #define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0 3269 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4 3270 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8 3271 #define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4 3272 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228 3273 #define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8 3274 #define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4 3275 #define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8 3276 #define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc 3277 #define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0 3278 #define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c 3279 #define PXP2_REG_PSWRQ_BW_L1 0x1202b0 3280 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4 3281 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8 3282 #define PXP2_REG_PSWRQ_BW_L2 0x1202b4 3283 #define PXP2_REG_PSWRQ_BW_L28 0x120318 3284 #define PXP2_REG_PSWRQ_BW_L3 0x1202b8 3285 #define PXP2_REG_PSWRQ_BW_L6 0x1202c4 3286 #define PXP2_REG_PSWRQ_BW_L7 0x1202c8 3287 #define PXP2_REG_PSWRQ_BW_L8 0x1202cc 3288 #define PXP2_REG_PSWRQ_BW_L9 0x1202d0 3289 #define PXP2_REG_PSWRQ_BW_RD 0x120324 3290 #define PXP2_REG_PSWRQ_BW_UB1 0x120238 3291 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c 3292 #define PXP2_REG_PSWRQ_BW_UB11 0x120260 3293 #define PXP2_REG_PSWRQ_BW_UB2 0x12023c 3294 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0 3295 #define PXP2_REG_PSWRQ_BW_UB3 0x120240 3296 #define PXP2_REG_PSWRQ_BW_UB6 0x12024c 3297 #define PXP2_REG_PSWRQ_BW_UB7 0x120250 3298 #define PXP2_REG_PSWRQ_BW_UB8 0x120254 3299 #define PXP2_REG_PSWRQ_BW_UB9 0x120258 3300 #define PXP2_REG_PSWRQ_BW_WR 0x120328 3301 #define PXP2_REG_PSWRQ_CDU0_L2P 0x120000 3302 #define PXP2_REG_PSWRQ_QM0_L2P 0x120038 3303 #define PXP2_REG_PSWRQ_SRC0_L2P 0x120054 3304 #define PXP2_REG_PSWRQ_TM0_L2P 0x12001c 3305 #define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0 3306 /* [RW 32] Interrupt mask register #0 read/write */ 3307 #define PXP2_REG_PXP2_INT_MASK_0 0x120578 3308 /* [R 32] Interrupt register #0 read */ 3309 #define PXP2_REG_PXP2_INT_STS_0 0x12056c 3310 #define PXP2_REG_PXP2_INT_STS_1 0x120608 3311 /* [RC 32] Interrupt register #0 read clear */ 3312 #define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570 3313 /* [RW 32] Parity mask register #0 read/write */ 3314 #define PXP2_REG_PXP2_PRTY_MASK_0 0x120588 3315 #define PXP2_REG_PXP2_PRTY_MASK_1 0x120598 3316 /* [R 32] Parity register #0 read */ 3317 #define PXP2_REG_PXP2_PRTY_STS_0 0x12057c 3318 #define PXP2_REG_PXP2_PRTY_STS_1 0x12058c 3319 /* [RC 32] Parity register #0 read clear */ 3320 #define PXP2_REG_PXP2_PRTY_STS_CLR_0 0x120580 3321 #define PXP2_REG_PXP2_PRTY_STS_CLR_1 0x120590 3322 /* [R 1] Debug only: The 'almost full' indication from each fifo (gives 3323 indication about backpressure) */ 3324 #define PXP2_REG_RD_ALMOST_FULL_0 0x120424 3325 /* [R 8] Debug only: The blocks counter - number of unused block ids */ 3326 #define PXP2_REG_RD_BLK_CNT 0x120418 3327 /* [RW 8] Debug only: Total number of available blocks in Tetris Buffer. 3328 Must be bigger than 6. Normally should not be changed. */ 3329 #define PXP2_REG_RD_BLK_NUM_CFG 0x12040c 3330 /* [RW 2] CDU byte swapping mode configuration for master read requests */ 3331 #define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404 3332 /* [RW 1] When '1'; inputs to the PSWRD block are ignored */ 3333 #define PXP2_REG_RD_DISABLE_INPUTS 0x120374 3334 /* [R 1] PSWRD internal memories initialization is done */ 3335 #define PXP2_REG_RD_INIT_DONE 0x120370 3336 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3337 allocated for vq10 */ 3338 #define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0 3339 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3340 allocated for vq11 */ 3341 #define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4 3342 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3343 allocated for vq17 */ 3344 #define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc 3345 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3346 allocated for vq18 */ 3347 #define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0 3348 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3349 allocated for vq19 */ 3350 #define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4 3351 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3352 allocated for vq22 */ 3353 #define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0 3354 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3355 allocated for vq25 */ 3356 #define PXP2_REG_RD_MAX_BLKS_VQ25 0x1203dc 3357 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3358 allocated for vq6 */ 3359 #define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390 3360 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3361 allocated for vq9 */ 3362 #define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c 3363 /* [RW 2] PBF byte swapping mode configuration for master read requests */ 3364 #define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4 3365 /* [R 1] Debug only: Indication if delivery ports are idle */ 3366 #define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c 3367 #define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420 3368 /* [RW 2] QM byte swapping mode configuration for master read requests */ 3369 #define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8 3370 /* [R 7] Debug only: The SR counter - number of unused sub request ids */ 3371 #define PXP2_REG_RD_SR_CNT 0x120414 3372 /* [RW 2] SRC byte swapping mode configuration for master read requests */ 3373 #define PXP2_REG_RD_SRC_SWAP_MODE 0x120400 3374 /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must 3375 be bigger than 1. Normally should not be changed. */ 3376 #define PXP2_REG_RD_SR_NUM_CFG 0x120408 3377 /* [RW 1] Signals the PSWRD block to start initializing internal memories */ 3378 #define PXP2_REG_RD_START_INIT 0x12036c 3379 /* [RW 2] TM byte swapping mode configuration for master read requests */ 3380 #define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc 3381 /* [RW 10] Bandwidth addition to VQ0 write requests */ 3382 #define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc 3383 /* [RW 10] Bandwidth addition to VQ12 read requests */ 3384 #define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec 3385 /* [RW 10] Bandwidth addition to VQ13 read requests */ 3386 #define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0 3387 /* [RW 10] Bandwidth addition to VQ14 read requests */ 3388 #define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4 3389 /* [RW 10] Bandwidth addition to VQ15 read requests */ 3390 #define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8 3391 /* [RW 10] Bandwidth addition to VQ16 read requests */ 3392 #define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc 3393 /* [RW 10] Bandwidth addition to VQ17 read requests */ 3394 #define PXP2_REG_RQ_BW_RD_ADD17 0x120200 3395 /* [RW 10] Bandwidth addition to VQ18 read requests */ 3396 #define PXP2_REG_RQ_BW_RD_ADD18 0x120204 3397 /* [RW 10] Bandwidth addition to VQ19 read requests */ 3398 #define PXP2_REG_RQ_BW_RD_ADD19 0x120208 3399 /* [RW 10] Bandwidth addition to VQ20 read requests */ 3400 #define PXP2_REG_RQ_BW_RD_ADD20 0x12020c 3401 /* [RW 10] Bandwidth addition to VQ22 read requests */ 3402 #define PXP2_REG_RQ_BW_RD_ADD22 0x120210 3403 /* [RW 10] Bandwidth addition to VQ23 read requests */ 3404 #define PXP2_REG_RQ_BW_RD_ADD23 0x120214 3405 /* [RW 10] Bandwidth addition to VQ24 read requests */ 3406 #define PXP2_REG_RQ_BW_RD_ADD24 0x120218 3407 /* [RW 10] Bandwidth addition to VQ25 read requests */ 3408 #define PXP2_REG_RQ_BW_RD_ADD25 0x12021c 3409 /* [RW 10] Bandwidth addition to VQ26 read requests */ 3410 #define PXP2_REG_RQ_BW_RD_ADD26 0x120220 3411 /* [RW 10] Bandwidth addition to VQ27 read requests */ 3412 #define PXP2_REG_RQ_BW_RD_ADD27 0x120224 3413 /* [RW 10] Bandwidth addition to VQ4 read requests */ 3414 #define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc 3415 /* [RW 10] Bandwidth addition to VQ5 read requests */ 3416 #define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0 3417 /* [RW 10] Bandwidth Typical L for VQ0 Read requests */ 3418 #define PXP2_REG_RQ_BW_RD_L0 0x1202ac 3419 /* [RW 10] Bandwidth Typical L for VQ12 Read requests */ 3420 #define PXP2_REG_RQ_BW_RD_L12 0x1202dc 3421 /* [RW 10] Bandwidth Typical L for VQ13 Read requests */ 3422 #define PXP2_REG_RQ_BW_RD_L13 0x1202e0 3423 /* [RW 10] Bandwidth Typical L for VQ14 Read requests */ 3424 #define PXP2_REG_RQ_BW_RD_L14 0x1202e4 3425 /* [RW 10] Bandwidth Typical L for VQ15 Read requests */ 3426 #define PXP2_REG_RQ_BW_RD_L15 0x1202e8 3427 /* [RW 10] Bandwidth Typical L for VQ16 Read requests */ 3428 #define PXP2_REG_RQ_BW_RD_L16 0x1202ec 3429 /* [RW 10] Bandwidth Typical L for VQ17 Read requests */ 3430 #define PXP2_REG_RQ_BW_RD_L17 0x1202f0 3431 /* [RW 10] Bandwidth Typical L for VQ18 Read requests */ 3432 #define PXP2_REG_RQ_BW_RD_L18 0x1202f4 3433 /* [RW 10] Bandwidth Typical L for VQ19 Read requests */ 3434 #define PXP2_REG_RQ_BW_RD_L19 0x1202f8 3435 /* [RW 10] Bandwidth Typical L for VQ20 Read requests */ 3436 #define PXP2_REG_RQ_BW_RD_L20 0x1202fc 3437 /* [RW 10] Bandwidth Typical L for VQ22 Read requests */ 3438 #define PXP2_REG_RQ_BW_RD_L22 0x120300 3439 /* [RW 10] Bandwidth Typical L for VQ23 Read requests */ 3440 #define PXP2_REG_RQ_BW_RD_L23 0x120304 3441 /* [RW 10] Bandwidth Typical L for VQ24 Read requests */ 3442 #define PXP2_REG_RQ_BW_RD_L24 0x120308 3443 /* [RW 10] Bandwidth Typical L for VQ25 Read requests */ 3444 #define PXP2_REG_RQ_BW_RD_L25 0x12030c 3445 /* [RW 10] Bandwidth Typical L for VQ26 Read requests */ 3446 #define PXP2_REG_RQ_BW_RD_L26 0x120310 3447 /* [RW 10] Bandwidth Typical L for VQ27 Read requests */ 3448 #define PXP2_REG_RQ_BW_RD_L27 0x120314 3449 /* [RW 10] Bandwidth Typical L for VQ4 Read requests */ 3450 #define PXP2_REG_RQ_BW_RD_L4 0x1202bc 3451 /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */ 3452 #define PXP2_REG_RQ_BW_RD_L5 0x1202c0 3453 /* [RW 7] Bandwidth upper bound for VQ0 read requests */ 3454 #define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234 3455 /* [RW 7] Bandwidth upper bound for VQ12 read requests */ 3456 #define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264 3457 /* [RW 7] Bandwidth upper bound for VQ13 read requests */ 3458 #define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268 3459 /* [RW 7] Bandwidth upper bound for VQ14 read requests */ 3460 #define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c 3461 /* [RW 7] Bandwidth upper bound for VQ15 read requests */ 3462 #define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270 3463 /* [RW 7] Bandwidth upper bound for VQ16 read requests */ 3464 #define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274 3465 /* [RW 7] Bandwidth upper bound for VQ17 read requests */ 3466 #define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278 3467 /* [RW 7] Bandwidth upper bound for VQ18 read requests */ 3468 #define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c 3469 /* [RW 7] Bandwidth upper bound for VQ19 read requests */ 3470 #define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280 3471 /* [RW 7] Bandwidth upper bound for VQ20 read requests */ 3472 #define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284 3473 /* [RW 7] Bandwidth upper bound for VQ22 read requests */ 3474 #define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288 3475 /* [RW 7] Bandwidth upper bound for VQ23 read requests */ 3476 #define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c 3477 /* [RW 7] Bandwidth upper bound for VQ24 read requests */ 3478 #define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290 3479 /* [RW 7] Bandwidth upper bound for VQ25 read requests */ 3480 #define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294 3481 /* [RW 7] Bandwidth upper bound for VQ26 read requests */ 3482 #define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298 3483 /* [RW 7] Bandwidth upper bound for VQ27 read requests */ 3484 #define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c 3485 /* [RW 7] Bandwidth upper bound for VQ4 read requests */ 3486 #define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244 3487 /* [RW 7] Bandwidth upper bound for VQ5 read requests */ 3488 #define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248 3489 /* [RW 10] Bandwidth addition to VQ29 write requests */ 3490 #define PXP2_REG_RQ_BW_WR_ADD29 0x12022c 3491 /* [RW 10] Bandwidth addition to VQ30 write requests */ 3492 #define PXP2_REG_RQ_BW_WR_ADD30 0x120230 3493 /* [RW 10] Bandwidth Typical L for VQ29 Write requests */ 3494 #define PXP2_REG_RQ_BW_WR_L29 0x12031c 3495 /* [RW 10] Bandwidth Typical L for VQ30 Write requests */ 3496 #define PXP2_REG_RQ_BW_WR_L30 0x120320 3497 /* [RW 7] Bandwidth upper bound for VQ29 */ 3498 #define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4 3499 /* [RW 7] Bandwidth upper bound for VQ30 */ 3500 #define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8 3501 /* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */ 3502 #define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008 3503 /* [RW 2] Endian mode for cdu */ 3504 #define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0 3505 #define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c 3506 #define PXP2_REG_RQ_CDU_LAST_ILT 0x120620 3507 /* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k; 3508 -128k */ 3509 #define PXP2_REG_RQ_CDU_P_SIZE 0x120018 3510 /* [R 1] 1' indicates that the requester has finished its internal 3511 configuration */ 3512 #define PXP2_REG_RQ_CFG_DONE 0x1201b4 3513 /* [RW 2] Endian mode for debug */ 3514 #define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4 3515 /* [RW 1] When '1'; requests will enter input buffers but wont get out 3516 towards the glue */ 3517 #define PXP2_REG_RQ_DISABLE_INPUTS 0x120330 3518 /* [RW 4] Determines alignment of write SRs when a request is split into 3519 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B 3520 * aligned. 4 - 512B aligned. */ 3521 #define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0 3522 /* [RW 4] Determines alignment of read SRs when a request is split into 3523 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B 3524 * aligned. 4 - 512B aligned. */ 3525 #define PXP2_REG_RQ_DRAM_ALIGN_RD 0x12092c 3526 /* [RW 1] when set the new alignment method (E2) will be applied; when reset 3527 * the original alignment method (E1 E1H) will be applied */ 3528 #define PXP2_REG_RQ_DRAM_ALIGN_SEL 0x120930 3529 /* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will 3530 be asserted */ 3531 #define PXP2_REG_RQ_ELT_DISABLE 0x12066c 3532 /* [RW 2] Endian mode for hc */ 3533 #define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8 3534 /* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back 3535 compatibility needs; Note that different registers are used per mode */ 3536 #define PXP2_REG_RQ_ILT_MODE 0x1205b4 3537 /* [WB 53] Onchip address table */ 3538 #define PXP2_REG_RQ_ONCHIP_AT 0x122000 3539 /* [WB 53] Onchip address table - B0 */ 3540 #define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000 3541 /* [RW 13] Pending read limiter threshold; in Dwords */ 3542 #define PXP2_REG_RQ_PDR_LIMIT 0x12033c 3543 /* [RW 2] Endian mode for qm */ 3544 #define PXP2_REG_RQ_QM_ENDIAN_M 0x120194 3545 #define PXP2_REG_RQ_QM_FIRST_ILT 0x120634 3546 #define PXP2_REG_RQ_QM_LAST_ILT 0x120638 3547 /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k; 3548 -128k */ 3549 #define PXP2_REG_RQ_QM_P_SIZE 0x120050 3550 /* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */ 3551 #define PXP2_REG_RQ_RBC_DONE 0x1201b0 3552 /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B; 3553 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */ 3554 #define PXP2_REG_RQ_RD_MBS0 0x120160 3555 /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B; 3556 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */ 3557 #define PXP2_REG_RQ_RD_MBS1 0x120168 3558 /* [RW 2] Endian mode for src */ 3559 #define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c 3560 #define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c 3561 #define PXP2_REG_RQ_SRC_LAST_ILT 0x120640 3562 /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k; 3563 -128k */ 3564 #define PXP2_REG_RQ_SRC_P_SIZE 0x12006c 3565 /* [RW 2] Endian mode for tm */ 3566 #define PXP2_REG_RQ_TM_ENDIAN_M 0x120198 3567 #define PXP2_REG_RQ_TM_FIRST_ILT 0x120644 3568 #define PXP2_REG_RQ_TM_LAST_ILT 0x120648 3569 /* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k; 3570 -128k */ 3571 #define PXP2_REG_RQ_TM_P_SIZE 0x120034 3572 /* [R 5] Number of entries in the ufifo; his fifo has l2p completions */ 3573 #define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c 3574 /* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */ 3575 #define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094 3576 /* [R 8] Number of entries occupied by vq 0 in pswrq memory */ 3577 #define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810 3578 /* [R 8] Number of entries occupied by vq 10 in pswrq memory */ 3579 #define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818 3580 /* [R 8] Number of entries occupied by vq 11 in pswrq memory */ 3581 #define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820 3582 /* [R 8] Number of entries occupied by vq 12 in pswrq memory */ 3583 #define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828 3584 /* [R 8] Number of entries occupied by vq 13 in pswrq memory */ 3585 #define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830 3586 /* [R 8] Number of entries occupied by vq 14 in pswrq memory */ 3587 #define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838 3588 /* [R 8] Number of entries occupied by vq 15 in pswrq memory */ 3589 #define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840 3590 /* [R 8] Number of entries occupied by vq 16 in pswrq memory */ 3591 #define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848 3592 /* [R 8] Number of entries occupied by vq 17 in pswrq memory */ 3593 #define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850 3594 /* [R 8] Number of entries occupied by vq 18 in pswrq memory */ 3595 #define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858 3596 /* [R 8] Number of entries occupied by vq 19 in pswrq memory */ 3597 #define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860 3598 /* [R 8] Number of entries occupied by vq 1 in pswrq memory */ 3599 #define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868 3600 /* [R 8] Number of entries occupied by vq 20 in pswrq memory */ 3601 #define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870 3602 /* [R 8] Number of entries occupied by vq 21 in pswrq memory */ 3603 #define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878 3604 /* [R 8] Number of entries occupied by vq 22 in pswrq memory */ 3605 #define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880 3606 /* [R 8] Number of entries occupied by vq 23 in pswrq memory */ 3607 #define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888 3608 /* [R 8] Number of entries occupied by vq 24 in pswrq memory */ 3609 #define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890 3610 /* [R 8] Number of entries occupied by vq 25 in pswrq memory */ 3611 #define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898 3612 /* [R 8] Number of entries occupied by vq 26 in pswrq memory */ 3613 #define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0 3614 /* [R 8] Number of entries occupied by vq 27 in pswrq memory */ 3615 #define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8 3616 /* [R 8] Number of entries occupied by vq 28 in pswrq memory */ 3617 #define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0 3618 /* [R 8] Number of entries occupied by vq 29 in pswrq memory */ 3619 #define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8 3620 /* [R 8] Number of entries occupied by vq 2 in pswrq memory */ 3621 #define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0 3622 /* [R 8] Number of entries occupied by vq 30 in pswrq memory */ 3623 #define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8 3624 /* [R 8] Number of entries occupied by vq 31 in pswrq memory */ 3625 #define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0 3626 /* [R 8] Number of entries occupied by vq 3 in pswrq memory */ 3627 #define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8 3628 /* [R 8] Number of entries occupied by vq 4 in pswrq memory */ 3629 #define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0 3630 /* [R 8] Number of entries occupied by vq 5 in pswrq memory */ 3631 #define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8 3632 /* [R 8] Number of entries occupied by vq 6 in pswrq memory */ 3633 #define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0 3634 /* [R 8] Number of entries occupied by vq 7 in pswrq memory */ 3635 #define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8 3636 /* [R 8] Number of entries occupied by vq 8 in pswrq memory */ 3637 #define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900 3638 /* [R 8] Number of entries occupied by vq 9 in pswrq memory */ 3639 #define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908 3640 /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B; 3641 001:256B; 010: 512B; */ 3642 #define PXP2_REG_RQ_WR_MBS0 0x12015c 3643 /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B; 3644 001:256B; 010: 512B; */ 3645 #define PXP2_REG_RQ_WR_MBS1 0x120164 3646 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3647 buffer reaches this number has_payload will be asserted */ 3648 #define PXP2_REG_WR_CDU_MPS 0x1205f0 3649 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3650 buffer reaches this number has_payload will be asserted */ 3651 #define PXP2_REG_WR_CSDM_MPS 0x1205d0 3652 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3653 buffer reaches this number has_payload will be asserted */ 3654 #define PXP2_REG_WR_DBG_MPS 0x1205e8 3655 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3656 buffer reaches this number has_payload will be asserted */ 3657 #define PXP2_REG_WR_DMAE_MPS 0x1205ec 3658 /* [RW 10] if Number of entries in dmae fifo will be higher than this 3659 threshold then has_payload indication will be asserted; the default value 3660 should be equal to > write MBS size! */ 3661 #define PXP2_REG_WR_DMAE_TH 0x120368 3662 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3663 buffer reaches this number has_payload will be asserted */ 3664 #define PXP2_REG_WR_HC_MPS 0x1205c8 3665 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3666 buffer reaches this number has_payload will be asserted */ 3667 #define PXP2_REG_WR_QM_MPS 0x1205dc 3668 /* [RW 1] 0 - working in A0 mode; - working in B0 mode */ 3669 #define PXP2_REG_WR_REV_MODE 0x120670 3670 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3671 buffer reaches this number has_payload will be asserted */ 3672 #define PXP2_REG_WR_SRC_MPS 0x1205e4 3673 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3674 buffer reaches this number has_payload will be asserted */ 3675 #define PXP2_REG_WR_TM_MPS 0x1205e0 3676 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3677 buffer reaches this number has_payload will be asserted */ 3678 #define PXP2_REG_WR_TSDM_MPS 0x1205d4 3679 /* [RW 10] if Number of entries in usdmdp fifo will be higher than this 3680 threshold then has_payload indication will be asserted; the default value 3681 should be equal to > write MBS size! */ 3682 #define PXP2_REG_WR_USDMDP_TH 0x120348 3683 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3684 buffer reaches this number has_payload will be asserted */ 3685 #define PXP2_REG_WR_USDM_MPS 0x1205cc 3686 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3687 buffer reaches this number has_payload will be asserted */ 3688 #define PXP2_REG_WR_XSDM_MPS 0x1205d8 3689 /* [R 1] debug only: Indication if PSWHST arbiter is idle */ 3690 #define PXP_REG_HST_ARB_IS_IDLE 0x103004 3691 /* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means 3692 this client is waiting for the arbiter. */ 3693 #define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008 3694 /* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue 3695 block. Should be used for close the gates. */ 3696 #define PXP_REG_HST_DISCARD_DOORBELLS 0x1030a4 3697 /* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit 3698 should update according to 'hst_discard_doorbells' register when the state 3699 machine is idle */ 3700 #define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0 3701 /* [RW 1] When 1; new internal writes arriving to the block are discarded. 3702 Should be used for close the gates. */ 3703 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES 0x1030a8 3704 /* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1' 3705 means this PSWHST is discarding inputs from this client. Each bit should 3706 update according to 'hst_discard_internal_writes' register when the state 3707 machine is idle. */ 3708 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c 3709 /* [WB 160] Used for initialization of the inbound interrupts memory */ 3710 #define PXP_REG_HST_INBOUND_INT 0x103800 3711 /* [RW 32] Interrupt mask register #0 read/write */ 3712 #define PXP_REG_PXP_INT_MASK_0 0x103074 3713 #define PXP_REG_PXP_INT_MASK_1 0x103084 3714 /* [R 32] Interrupt register #0 read */ 3715 #define PXP_REG_PXP_INT_STS_0 0x103068 3716 #define PXP_REG_PXP_INT_STS_1 0x103078 3717 /* [RC 32] Interrupt register #0 read clear */ 3718 #define PXP_REG_PXP_INT_STS_CLR_0 0x10306c 3719 #define PXP_REG_PXP_INT_STS_CLR_1 0x10307c 3720 /* [RW 27] Parity mask register #0 read/write */ 3721 #define PXP_REG_PXP_PRTY_MASK 0x103094 3722 /* [R 26] Parity register #0 read */ 3723 #define PXP_REG_PXP_PRTY_STS 0x103088 3724 /* [RC 27] Parity register #0 read clear */ 3725 #define PXP_REG_PXP_PRTY_STS_CLR 0x10308c 3726 /* [RW 4] The activity counter initial increment value sent in the load 3727 request */ 3728 #define QM_REG_ACTCTRINITVAL_0 0x168040 3729 #define QM_REG_ACTCTRINITVAL_1 0x168044 3730 #define QM_REG_ACTCTRINITVAL_2 0x168048 3731 #define QM_REG_ACTCTRINITVAL_3 0x16804c 3732 /* [RW 32] The base logical address (in bytes) of each physical queue. The 3733 index I represents the physical queue number. The 12 lsbs are ignore and 3734 considered zero so practically there are only 20 bits in this register; 3735 queues 63-0 */ 3736 #define QM_REG_BASEADDR 0x168900 3737 /* [RW 32] The base logical address (in bytes) of each physical queue. The 3738 index I represents the physical queue number. The 12 lsbs are ignore and 3739 considered zero so practically there are only 20 bits in this register; 3740 queues 127-64 */ 3741 #define QM_REG_BASEADDR_EXT_A 0x16e100 3742 /* [RW 16] The byte credit cost for each task. This value is for both ports */ 3743 #define QM_REG_BYTECRDCOST 0x168234 3744 /* [RW 16] The initial byte credit value for both ports. */ 3745 #define QM_REG_BYTECRDINITVAL 0x168238 3746 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical 3747 queue uses port 0 else it uses port 1; queues 31-0 */ 3748 #define QM_REG_BYTECRDPORT_LSB 0x168228 3749 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical 3750 queue uses port 0 else it uses port 1; queues 95-64 */ 3751 #define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520 3752 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical 3753 queue uses port 0 else it uses port 1; queues 63-32 */ 3754 #define QM_REG_BYTECRDPORT_MSB 0x168224 3755 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical 3756 queue uses port 0 else it uses port 1; queues 127-96 */ 3757 #define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c 3758 /* [RW 16] The byte credit value that if above the QM is considered almost 3759 full */ 3760 #define QM_REG_BYTECREDITAFULLTHR 0x168094 3761 /* [RW 4] The initial credit for interface */ 3762 #define QM_REG_CMINITCRD_0 0x1680cc 3763 #define QM_REG_BYTECRDCMDQ_0 0x16e6e8 3764 #define QM_REG_CMINITCRD_1 0x1680d0 3765 #define QM_REG_CMINITCRD_2 0x1680d4 3766 #define QM_REG_CMINITCRD_3 0x1680d8 3767 #define QM_REG_CMINITCRD_4 0x1680dc 3768 #define QM_REG_CMINITCRD_5 0x1680e0 3769 #define QM_REG_CMINITCRD_6 0x1680e4 3770 #define QM_REG_CMINITCRD_7 0x1680e8 3771 /* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface 3772 is masked */ 3773 #define QM_REG_CMINTEN 0x1680ec 3774 /* [RW 12] A bit vector which indicates which one of the queues are tied to 3775 interface 0 */ 3776 #define QM_REG_CMINTVOQMASK_0 0x1681f4 3777 #define QM_REG_CMINTVOQMASK_1 0x1681f8 3778 #define QM_REG_CMINTVOQMASK_2 0x1681fc 3779 #define QM_REG_CMINTVOQMASK_3 0x168200 3780 #define QM_REG_CMINTVOQMASK_4 0x168204 3781 #define QM_REG_CMINTVOQMASK_5 0x168208 3782 #define QM_REG_CMINTVOQMASK_6 0x16820c 3783 #define QM_REG_CMINTVOQMASK_7 0x168210 3784 /* [RW 20] The number of connections divided by 16 which dictates the size 3785 of each queue which belongs to even function number. */ 3786 #define QM_REG_CONNNUM_0 0x168020 3787 /* [R 6] Keep the fill level of the fifo from write client 4 */ 3788 #define QM_REG_CQM_WRC_FIFOLVL 0x168018 3789 /* [RW 8] The context regions sent in the CFC load request */ 3790 #define QM_REG_CTXREG_0 0x168030 3791 #define QM_REG_CTXREG_1 0x168034 3792 #define QM_REG_CTXREG_2 0x168038 3793 #define QM_REG_CTXREG_3 0x16803c 3794 /* [RW 12] The VOQ mask used to select the VOQs which needs to be full for 3795 bypass enable */ 3796 #define QM_REG_ENBYPVOQMASK 0x16823c 3797 /* [RW 32] A bit mask per each physical queue. If a bit is set then the 3798 physical queue uses the byte credit; queues 31-0 */ 3799 #define QM_REG_ENBYTECRD_LSB 0x168220 3800 /* [RW 32] A bit mask per each physical queue. If a bit is set then the 3801 physical queue uses the byte credit; queues 95-64 */ 3802 #define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518 3803 /* [RW 32] A bit mask per each physical queue. If a bit is set then the 3804 physical queue uses the byte credit; queues 63-32 */ 3805 #define QM_REG_ENBYTECRD_MSB 0x16821c 3806 /* [RW 32] A bit mask per each physical queue. If a bit is set then the 3807 physical queue uses the byte credit; queues 127-96 */ 3808 #define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514 3809 /* [RW 4] If cleared then the secondary interface will not be served by the 3810 RR arbiter */ 3811 #define QM_REG_ENSEC 0x1680f0 3812 /* [RW 32] NA */ 3813 #define QM_REG_FUNCNUMSEL_LSB 0x168230 3814 /* [RW 32] NA */ 3815 #define QM_REG_FUNCNUMSEL_MSB 0x16822c 3816 /* [RW 32] A mask register to mask the Almost empty signals which will not 3817 be use for the almost empty indication to the HW block; queues 31:0 */ 3818 #define QM_REG_HWAEMPTYMASK_LSB 0x168218 3819 /* [RW 32] A mask register to mask the Almost empty signals which will not 3820 be use for the almost empty indication to the HW block; queues 95-64 */ 3821 #define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510 3822 /* [RW 32] A mask register to mask the Almost empty signals which will not 3823 be use for the almost empty indication to the HW block; queues 63:32 */ 3824 #define QM_REG_HWAEMPTYMASK_MSB 0x168214 3825 /* [RW 32] A mask register to mask the Almost empty signals which will not 3826 be use for the almost empty indication to the HW block; queues 127-96 */ 3827 #define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c 3828 /* [RW 4] The number of outstanding request to CFC */ 3829 #define QM_REG_OUTLDREQ 0x168804 3830 /* [RC 1] A flag to indicate that overflow error occurred in one of the 3831 queues. */ 3832 #define QM_REG_OVFERROR 0x16805c 3833 /* [RC 7] the Q where the overflow occurs */ 3834 #define QM_REG_OVFQNUM 0x168058 3835 /* [R 16] Pause state for physical queues 15-0 */ 3836 #define QM_REG_PAUSESTATE0 0x168410 3837 /* [R 16] Pause state for physical queues 31-16 */ 3838 #define QM_REG_PAUSESTATE1 0x168414 3839 /* [R 16] Pause state for physical queues 47-32 */ 3840 #define QM_REG_PAUSESTATE2 0x16e684 3841 /* [R 16] Pause state for physical queues 63-48 */ 3842 #define QM_REG_PAUSESTATE3 0x16e688 3843 /* [R 16] Pause state for physical queues 79-64 */ 3844 #define QM_REG_PAUSESTATE4 0x16e68c 3845 /* [R 16] Pause state for physical queues 95-80 */ 3846 #define QM_REG_PAUSESTATE5 0x16e690 3847 /* [R 16] Pause state for physical queues 111-96 */ 3848 #define QM_REG_PAUSESTATE6 0x16e694 3849 /* [R 16] Pause state for physical queues 127-112 */ 3850 #define QM_REG_PAUSESTATE7 0x16e698 3851 /* [RW 2] The PCI attributes field used in the PCI request. */ 3852 #define QM_REG_PCIREQAT 0x168054 3853 #define QM_REG_PF_EN 0x16e70c 3854 /* [R 24] The number of tasks stored in the QM for the PF. only even 3855 * functions are valid in E2 (odd I registers will be hard wired to 0) */ 3856 #define QM_REG_PF_USG_CNT_0 0x16e040 3857 /* [R 16] NOT USED */ 3858 #define QM_REG_PORT0BYTECRD 0x168300 3859 /* [R 16] The byte credit of port 1 */ 3860 #define QM_REG_PORT1BYTECRD 0x168304 3861 /* [RW 3] pci function number of queues 15-0 */ 3862 #define QM_REG_PQ2PCIFUNC_0 0x16e6bc 3863 #define QM_REG_PQ2PCIFUNC_1 0x16e6c0 3864 #define QM_REG_PQ2PCIFUNC_2 0x16e6c4 3865 #define QM_REG_PQ2PCIFUNC_3 0x16e6c8 3866 #define QM_REG_PQ2PCIFUNC_4 0x16e6cc 3867 #define QM_REG_PQ2PCIFUNC_5 0x16e6d0 3868 #define QM_REG_PQ2PCIFUNC_6 0x16e6d4 3869 #define QM_REG_PQ2PCIFUNC_7 0x16e6d8 3870 /* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow: 3871 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read 3872 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */ 3873 #define QM_REG_PTRTBL 0x168a00 3874 /* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow: 3875 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read 3876 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */ 3877 #define QM_REG_PTRTBL_EXT_A 0x16e200 3878 /* [RW 2] Interrupt mask register #0 read/write */ 3879 #define QM_REG_QM_INT_MASK 0x168444 3880 /* [R 2] Interrupt register #0 read */ 3881 #define QM_REG_QM_INT_STS 0x168438 3882 /* [RW 12] Parity mask register #0 read/write */ 3883 #define QM_REG_QM_PRTY_MASK 0x168454 3884 /* [R 12] Parity register #0 read */ 3885 #define QM_REG_QM_PRTY_STS 0x168448 3886 /* [RC 12] Parity register #0 read clear */ 3887 #define QM_REG_QM_PRTY_STS_CLR 0x16844c 3888 /* [R 32] Current queues in pipeline: Queues from 32 to 63 */ 3889 #define QM_REG_QSTATUS_HIGH 0x16802c 3890 /* [R 32] Current queues in pipeline: Queues from 96 to 127 */ 3891 #define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408 3892 /* [R 32] Current queues in pipeline: Queues from 0 to 31 */ 3893 #define QM_REG_QSTATUS_LOW 0x168028 3894 /* [R 32] Current queues in pipeline: Queues from 64 to 95 */ 3895 #define QM_REG_QSTATUS_LOW_EXT_A 0x16e404 3896 /* [R 24] The number of tasks queued for each queue; queues 63-0 */ 3897 #define QM_REG_QTASKCTR_0 0x168308 3898 /* [R 24] The number of tasks queued for each queue; queues 127-64 */ 3899 #define QM_REG_QTASKCTR_EXT_A_0 0x16e584 3900 /* [RW 4] Queue tied to VOQ */ 3901 #define QM_REG_QVOQIDX_0 0x1680f4 3902 #define QM_REG_QVOQIDX_10 0x16811c 3903 #define QM_REG_QVOQIDX_100 0x16e49c 3904 #define QM_REG_QVOQIDX_101 0x16e4a0 3905 #define QM_REG_QVOQIDX_102 0x16e4a4 3906 #define QM_REG_QVOQIDX_103 0x16e4a8 3907 #define QM_REG_QVOQIDX_104 0x16e4ac 3908 #define QM_REG_QVOQIDX_105 0x16e4b0 3909 #define QM_REG_QVOQIDX_106 0x16e4b4 3910 #define QM_REG_QVOQIDX_107 0x16e4b8 3911 #define QM_REG_QVOQIDX_108 0x16e4bc 3912 #define QM_REG_QVOQIDX_109 0x16e4c0 3913 #define QM_REG_QVOQIDX_11 0x168120 3914 #define QM_REG_QVOQIDX_110 0x16e4c4 3915 #define QM_REG_QVOQIDX_111 0x16e4c8 3916 #define QM_REG_QVOQIDX_112 0x16e4cc 3917 #define QM_REG_QVOQIDX_113 0x16e4d0 3918 #define QM_REG_QVOQIDX_114 0x16e4d4 3919 #define QM_REG_QVOQIDX_115 0x16e4d8 3920 #define QM_REG_QVOQIDX_116 0x16e4dc 3921 #define QM_REG_QVOQIDX_117 0x16e4e0 3922 #define QM_REG_QVOQIDX_118 0x16e4e4 3923 #define QM_REG_QVOQIDX_119 0x16e4e8 3924 #define QM_REG_QVOQIDX_12 0x168124 3925 #define QM_REG_QVOQIDX_120 0x16e4ec 3926 #define QM_REG_QVOQIDX_121 0x16e4f0 3927 #define QM_REG_QVOQIDX_122 0x16e4f4 3928 #define QM_REG_QVOQIDX_123 0x16e4f8 3929 #define QM_REG_QVOQIDX_124 0x16e4fc 3930 #define QM_REG_QVOQIDX_125 0x16e500 3931 #define QM_REG_QVOQIDX_126 0x16e504 3932 #define QM_REG_QVOQIDX_127 0x16e508 3933 #define QM_REG_QVOQIDX_13 0x168128 3934 #define QM_REG_QVOQIDX_14 0x16812c 3935 #define QM_REG_QVOQIDX_15 0x168130 3936 #define QM_REG_QVOQIDX_16 0x168134 3937 #define QM_REG_QVOQIDX_17 0x168138 3938 #define QM_REG_QVOQIDX_21 0x168148 3939 #define QM_REG_QVOQIDX_22 0x16814c 3940 #define QM_REG_QVOQIDX_23 0x168150 3941 #define QM_REG_QVOQIDX_24 0x168154 3942 #define QM_REG_QVOQIDX_25 0x168158 3943 #define QM_REG_QVOQIDX_26 0x16815c 3944 #define QM_REG_QVOQIDX_27 0x168160 3945 #define QM_REG_QVOQIDX_28 0x168164 3946 #define QM_REG_QVOQIDX_29 0x168168 3947 #define QM_REG_QVOQIDX_30 0x16816c 3948 #define QM_REG_QVOQIDX_31 0x168170 3949 #define QM_REG_QVOQIDX_32 0x168174 3950 #define QM_REG_QVOQIDX_33 0x168178 3951 #define QM_REG_QVOQIDX_34 0x16817c 3952 #define QM_REG_QVOQIDX_35 0x168180 3953 #define QM_REG_QVOQIDX_36 0x168184 3954 #define QM_REG_QVOQIDX_37 0x168188 3955 #define QM_REG_QVOQIDX_38 0x16818c 3956 #define QM_REG_QVOQIDX_39 0x168190 3957 #define QM_REG_QVOQIDX_40 0x168194 3958 #define QM_REG_QVOQIDX_41 0x168198 3959 #define QM_REG_QVOQIDX_42 0x16819c 3960 #define QM_REG_QVOQIDX_43 0x1681a0 3961 #define QM_REG_QVOQIDX_44 0x1681a4 3962 #define QM_REG_QVOQIDX_45 0x1681a8 3963 #define QM_REG_QVOQIDX_46 0x1681ac 3964 #define QM_REG_QVOQIDX_47 0x1681b0 3965 #define QM_REG_QVOQIDX_48 0x1681b4 3966 #define QM_REG_QVOQIDX_49 0x1681b8 3967 #define QM_REG_QVOQIDX_5 0x168108 3968 #define QM_REG_QVOQIDX_50 0x1681bc 3969 #define QM_REG_QVOQIDX_51 0x1681c0 3970 #define QM_REG_QVOQIDX_52 0x1681c4 3971 #define QM_REG_QVOQIDX_53 0x1681c8 3972 #define QM_REG_QVOQIDX_54 0x1681cc 3973 #define QM_REG_QVOQIDX_55 0x1681d0 3974 #define QM_REG_QVOQIDX_56 0x1681d4 3975 #define QM_REG_QVOQIDX_57 0x1681d8 3976 #define QM_REG_QVOQIDX_58 0x1681dc 3977 #define QM_REG_QVOQIDX_59 0x1681e0 3978 #define QM_REG_QVOQIDX_6 0x16810c 3979 #define QM_REG_QVOQIDX_60 0x1681e4 3980 #define QM_REG_QVOQIDX_61 0x1681e8 3981 #define QM_REG_QVOQIDX_62 0x1681ec 3982 #define QM_REG_QVOQIDX_63 0x1681f0 3983 #define QM_REG_QVOQIDX_64 0x16e40c 3984 #define QM_REG_QVOQIDX_65 0x16e410 3985 #define QM_REG_QVOQIDX_69 0x16e420 3986 #define QM_REG_QVOQIDX_7 0x168110 3987 #define QM_REG_QVOQIDX_70 0x16e424 3988 #define QM_REG_QVOQIDX_71 0x16e428 3989 #define QM_REG_QVOQIDX_72 0x16e42c 3990 #define QM_REG_QVOQIDX_73 0x16e430 3991 #define QM_REG_QVOQIDX_74 0x16e434 3992 #define QM_REG_QVOQIDX_75 0x16e438 3993 #define QM_REG_QVOQIDX_76 0x16e43c 3994 #define QM_REG_QVOQIDX_77 0x16e440 3995 #define QM_REG_QVOQIDX_78 0x16e444 3996 #define QM_REG_QVOQIDX_79 0x16e448 3997 #define QM_REG_QVOQIDX_8 0x168114 3998 #define QM_REG_QVOQIDX_80 0x16e44c 3999 #define QM_REG_QVOQIDX_81 0x16e450 4000 #define QM_REG_QVOQIDX_85 0x16e460 4001 #define QM_REG_QVOQIDX_86 0x16e464 4002 #define QM_REG_QVOQIDX_87 0x16e468 4003 #define QM_REG_QVOQIDX_88 0x16e46c 4004 #define QM_REG_QVOQIDX_89 0x16e470 4005 #define QM_REG_QVOQIDX_9 0x168118 4006 #define QM_REG_QVOQIDX_90 0x16e474 4007 #define QM_REG_QVOQIDX_91 0x16e478 4008 #define QM_REG_QVOQIDX_92 0x16e47c 4009 #define QM_REG_QVOQIDX_93 0x16e480 4010 #define QM_REG_QVOQIDX_94 0x16e484 4011 #define QM_REG_QVOQIDX_95 0x16e488 4012 #define QM_REG_QVOQIDX_96 0x16e48c 4013 #define QM_REG_QVOQIDX_97 0x16e490 4014 #define QM_REG_QVOQIDX_98 0x16e494 4015 #define QM_REG_QVOQIDX_99 0x16e498 4016 /* [RW 1] Initialization bit command */ 4017 #define QM_REG_SOFT_RESET 0x168428 4018 /* [RW 8] The credit cost per every task in the QM. A value per each VOQ */ 4019 #define QM_REG_TASKCRDCOST_0 0x16809c 4020 #define QM_REG_TASKCRDCOST_1 0x1680a0 4021 #define QM_REG_TASKCRDCOST_2 0x1680a4 4022 #define QM_REG_TASKCRDCOST_4 0x1680ac 4023 #define QM_REG_TASKCRDCOST_5 0x1680b0 4024 /* [R 6] Keep the fill level of the fifo from write client 3 */ 4025 #define QM_REG_TQM_WRC_FIFOLVL 0x168010 4026 /* [R 6] Keep the fill level of the fifo from write client 2 */ 4027 #define QM_REG_UQM_WRC_FIFOLVL 0x168008 4028 /* [RC 32] Credit update error register */ 4029 #define QM_REG_VOQCRDERRREG 0x168408 4030 /* [R 16] The credit value for each VOQ */ 4031 #define QM_REG_VOQCREDIT_0 0x1682d0 4032 #define QM_REG_VOQCREDIT_1 0x1682d4 4033 #define QM_REG_VOQCREDIT_4 0x1682e0 4034 /* [RW 16] The credit value that if above the QM is considered almost full */ 4035 #define QM_REG_VOQCREDITAFULLTHR 0x168090 4036 /* [RW 16] The init and maximum credit for each VoQ */ 4037 #define QM_REG_VOQINITCREDIT_0 0x168060 4038 #define QM_REG_VOQINITCREDIT_1 0x168064 4039 #define QM_REG_VOQINITCREDIT_2 0x168068 4040 #define QM_REG_VOQINITCREDIT_4 0x168070 4041 #define QM_REG_VOQINITCREDIT_5 0x168074 4042 /* [RW 1] The port of which VOQ belongs */ 4043 #define QM_REG_VOQPORT_0 0x1682a0 4044 #define QM_REG_VOQPORT_1 0x1682a4 4045 #define QM_REG_VOQPORT_2 0x1682a8 4046 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 4047 #define QM_REG_VOQQMASK_0_LSB 0x168240 4048 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 4049 #define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524 4050 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 4051 #define QM_REG_VOQQMASK_0_MSB 0x168244 4052 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 4053 #define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528 4054 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 4055 #define QM_REG_VOQQMASK_10_LSB 0x168290 4056 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 4057 #define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574 4058 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 4059 #define QM_REG_VOQQMASK_10_MSB 0x168294 4060 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 4061 #define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578 4062 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 4063 #define QM_REG_VOQQMASK_11_LSB 0x168298 4064 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 4065 #define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c 4066 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 4067 #define QM_REG_VOQQMASK_11_MSB 0x16829c 4068 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 4069 #define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580 4070 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 4071 #define QM_REG_VOQQMASK_1_LSB 0x168248 4072 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 4073 #define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c 4074 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 4075 #define QM_REG_VOQQMASK_1_MSB 0x16824c 4076 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 4077 #define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530 4078 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 4079 #define QM_REG_VOQQMASK_2_LSB 0x168250 4080 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 4081 #define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534 4082 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 4083 #define QM_REG_VOQQMASK_2_MSB 0x168254 4084 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 4085 #define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538 4086 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 4087 #define QM_REG_VOQQMASK_3_LSB 0x168258 4088 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 4089 #define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c 4090 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 4091 #define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540 4092 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 4093 #define QM_REG_VOQQMASK_4_LSB 0x168260 4094 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 4095 #define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544 4096 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 4097 #define QM_REG_VOQQMASK_4_MSB 0x168264 4098 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 4099 #define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548 4100 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 4101 #define QM_REG_VOQQMASK_5_LSB 0x168268 4102 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 4103 #define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c 4104 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 4105 #define QM_REG_VOQQMASK_5_MSB 0x16826c 4106 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 4107 #define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550 4108 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 4109 #define QM_REG_VOQQMASK_6_LSB 0x168270 4110 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 4111 #define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554 4112 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 4113 #define QM_REG_VOQQMASK_6_MSB 0x168274 4114 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 4115 #define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558 4116 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 4117 #define QM_REG_VOQQMASK_7_LSB 0x168278 4118 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 4119 #define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c 4120 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 4121 #define QM_REG_VOQQMASK_7_MSB 0x16827c 4122 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 4123 #define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560 4124 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 4125 #define QM_REG_VOQQMASK_8_LSB 0x168280 4126 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 4127 #define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564 4128 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 4129 #define QM_REG_VOQQMASK_8_MSB 0x168284 4130 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 4131 #define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568 4132 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 4133 #define QM_REG_VOQQMASK_9_LSB 0x168288 4134 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 4135 #define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c 4136 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 4137 #define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570 4138 /* [RW 32] Wrr weights */ 4139 #define QM_REG_WRRWEIGHTS_0 0x16880c 4140 #define QM_REG_WRRWEIGHTS_1 0x168810 4141 #define QM_REG_WRRWEIGHTS_10 0x168814 4142 #define QM_REG_WRRWEIGHTS_11 0x168818 4143 #define QM_REG_WRRWEIGHTS_12 0x16881c 4144 #define QM_REG_WRRWEIGHTS_13 0x168820 4145 #define QM_REG_WRRWEIGHTS_14 0x168824 4146 #define QM_REG_WRRWEIGHTS_15 0x168828 4147 #define QM_REG_WRRWEIGHTS_16 0x16e000 4148 #define QM_REG_WRRWEIGHTS_17 0x16e004 4149 #define QM_REG_WRRWEIGHTS_18 0x16e008 4150 #define QM_REG_WRRWEIGHTS_19 0x16e00c 4151 #define QM_REG_WRRWEIGHTS_2 0x16882c 4152 #define QM_REG_WRRWEIGHTS_20 0x16e010 4153 #define QM_REG_WRRWEIGHTS_21 0x16e014 4154 #define QM_REG_WRRWEIGHTS_22 0x16e018 4155 #define QM_REG_WRRWEIGHTS_23 0x16e01c 4156 #define QM_REG_WRRWEIGHTS_24 0x16e020 4157 #define QM_REG_WRRWEIGHTS_25 0x16e024 4158 #define QM_REG_WRRWEIGHTS_26 0x16e028 4159 #define QM_REG_WRRWEIGHTS_27 0x16e02c 4160 #define QM_REG_WRRWEIGHTS_28 0x16e030 4161 #define QM_REG_WRRWEIGHTS_29 0x16e034 4162 #define QM_REG_WRRWEIGHTS_3 0x168830 4163 #define QM_REG_WRRWEIGHTS_30 0x16e038 4164 #define QM_REG_WRRWEIGHTS_31 0x16e03c 4165 #define QM_REG_WRRWEIGHTS_4 0x168834 4166 #define QM_REG_WRRWEIGHTS_5 0x168838 4167 #define QM_REG_WRRWEIGHTS_6 0x16883c 4168 #define QM_REG_WRRWEIGHTS_7 0x168840 4169 #define QM_REG_WRRWEIGHTS_8 0x168844 4170 #define QM_REG_WRRWEIGHTS_9 0x168848 4171 /* [R 6] Keep the fill level of the fifo from write client 1 */ 4172 #define QM_REG_XQM_WRC_FIFOLVL 0x168000 4173 /* [W 1] reset to parity interrupt */ 4174 #define SEM_FAST_REG_PARITY_RST 0x18840 4175 #define SRC_REG_COUNTFREE0 0x40500 4176 /* [RW 1] If clr the searcher is compatible to E1 A0 - support only two 4177 ports. If set the searcher support 8 functions. */ 4178 #define SRC_REG_E1HMF_ENABLE 0x404cc 4179 #define SRC_REG_FIRSTFREE0 0x40510 4180 #define SRC_REG_KEYRSS0_0 0x40408 4181 #define SRC_REG_KEYRSS0_7 0x40424 4182 #define SRC_REG_KEYRSS1_9 0x40454 4183 #define SRC_REG_KEYSEARCH_0 0x40458 4184 #define SRC_REG_KEYSEARCH_1 0x4045c 4185 #define SRC_REG_KEYSEARCH_2 0x40460 4186 #define SRC_REG_KEYSEARCH_3 0x40464 4187 #define SRC_REG_KEYSEARCH_4 0x40468 4188 #define SRC_REG_KEYSEARCH_5 0x4046c 4189 #define SRC_REG_KEYSEARCH_6 0x40470 4190 #define SRC_REG_KEYSEARCH_7 0x40474 4191 #define SRC_REG_KEYSEARCH_8 0x40478 4192 #define SRC_REG_KEYSEARCH_9 0x4047c 4193 #define SRC_REG_LASTFREE0 0x40530 4194 #define SRC_REG_NUMBER_HASH_BITS0 0x40400 4195 /* [RW 1] Reset internal state machines. */ 4196 #define SRC_REG_SOFT_RST 0x4049c 4197 /* [R 3] Interrupt register #0 read */ 4198 #define SRC_REG_SRC_INT_STS 0x404ac 4199 /* [RW 3] Parity mask register #0 read/write */ 4200 #define SRC_REG_SRC_PRTY_MASK 0x404c8 4201 /* [R 3] Parity register #0 read */ 4202 #define SRC_REG_SRC_PRTY_STS 0x404bc 4203 /* [RC 3] Parity register #0 read clear */ 4204 #define SRC_REG_SRC_PRTY_STS_CLR 0x404c0 4205 /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */ 4206 #define TCM_REG_CAM_OCCUP 0x5017c 4207 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is 4208 disregarded; valid output is deasserted; all other signals are treated as 4209 usual; if 1 - normal activity. */ 4210 #define TCM_REG_CDU_AG_RD_IFEN 0x50034 4211 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 4212 are disregarded; all other signals are treated as usual; if 1 - normal 4213 activity. */ 4214 #define TCM_REG_CDU_AG_WR_IFEN 0x50030 4215 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 4216 disregarded; valid output is deasserted; all other signals are treated as 4217 usual; if 1 - normal activity. */ 4218 #define TCM_REG_CDU_SM_RD_IFEN 0x5003c 4219 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 4220 input is disregarded; all other signals are treated as usual; if 1 - 4221 normal activity. */ 4222 #define TCM_REG_CDU_SM_WR_IFEN 0x50038 4223 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 4224 the initial credit value; read returns the current value of the credit 4225 counter. Must be initialized to 1 at start-up. */ 4226 #define TCM_REG_CFC_INIT_CRD 0x50204 4227 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for 4228 weight 8 (the most prioritised); 1 stands for weight 1(least 4229 prioritised); 2 stands for weight 2; tc. */ 4230 #define TCM_REG_CP_WEIGHT 0x500c0 4231 /* [RW 1] Input csem Interface enable. If 0 - the valid input is 4232 disregarded; acknowledge output is deasserted; all other signals are 4233 treated as usual; if 1 - normal activity. */ 4234 #define TCM_REG_CSEM_IFEN 0x5002c 4235 /* [RC 1] Message length mismatch (relative to last indication) at the In#9 4236 interface. */ 4237 #define TCM_REG_CSEM_LENGTH_MIS 0x50174 4238 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for 4239 weight 8 (the most prioritised); 1 stands for weight 1(least 4240 prioritised); 2 stands for weight 2; tc. */ 4241 #define TCM_REG_CSEM_WEIGHT 0x500bc 4242 /* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */ 4243 #define TCM_REG_ERR_EVNT_ID 0x500a0 4244 /* [RW 28] The CM erroneous header for QM and Timers formatting. */ 4245 #define TCM_REG_ERR_TCM_HDR 0x5009c 4246 /* [RW 8] The Event ID for Timers expiration. */ 4247 #define TCM_REG_EXPR_EVNT_ID 0x500a4 4248 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write 4249 writes the initial credit value; read returns the current value of the 4250 credit counter. Must be initialized to 64 at start-up. */ 4251 #define TCM_REG_FIC0_INIT_CRD 0x5020c 4252 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 4253 writes the initial credit value; read returns the current value of the 4254 credit counter. Must be initialized to 64 at start-up. */ 4255 #define TCM_REG_FIC1_INIT_CRD 0x50210 4256 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 4257 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr; 4258 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and 4259 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */ 4260 #define TCM_REG_GR_ARB_TYPE 0x50114 4261 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 4262 highest priority is 3. It is supposed that the Store channel is the 4263 compliment of the other 3 groups. */ 4264 #define TCM_REG_GR_LD0_PR 0x5011c 4265 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 4266 highest priority is 3. It is supposed that the Store channel is the 4267 compliment of the other 3 groups. */ 4268 #define TCM_REG_GR_LD1_PR 0x50120 4269 /* [RW 4] The number of double REG-pairs; loaded from the STORM context and 4270 sent to STORM; for a specific connection type. The double REG-pairs are 4271 used to align to STORM context row size of 128 bits. The offset of these 4272 data in the STORM context is always 0. Index _i stands for the connection 4273 type (one of 16). */ 4274 #define TCM_REG_N_SM_CTX_LD_0 0x50050 4275 #define TCM_REG_N_SM_CTX_LD_1 0x50054 4276 #define TCM_REG_N_SM_CTX_LD_2 0x50058 4277 #define TCM_REG_N_SM_CTX_LD_3 0x5005c 4278 #define TCM_REG_N_SM_CTX_LD_4 0x50060 4279 #define TCM_REG_N_SM_CTX_LD_5 0x50064 4280 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; 4281 acknowledge output is deasserted; all other signals are treated as usual; 4282 if 1 - normal activity. */ 4283 #define TCM_REG_PBF_IFEN 0x50024 4284 /* [RC 1] Message length mismatch (relative to last indication) at the In#7 4285 interface. */ 4286 #define TCM_REG_PBF_LENGTH_MIS 0x5016c 4287 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for 4288 weight 8 (the most prioritised); 1 stands for weight 1(least 4289 prioritised); 2 stands for weight 2; tc. */ 4290 #define TCM_REG_PBF_WEIGHT 0x500b4 4291 #define TCM_REG_PHYS_QNUM0_0 0x500e0 4292 #define TCM_REG_PHYS_QNUM0_1 0x500e4 4293 #define TCM_REG_PHYS_QNUM1_0 0x500e8 4294 #define TCM_REG_PHYS_QNUM1_1 0x500ec 4295 #define TCM_REG_PHYS_QNUM2_0 0x500f0 4296 #define TCM_REG_PHYS_QNUM2_1 0x500f4 4297 #define TCM_REG_PHYS_QNUM3_0 0x500f8 4298 #define TCM_REG_PHYS_QNUM3_1 0x500fc 4299 /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded; 4300 acknowledge output is deasserted; all other signals are treated as usual; 4301 if 1 - normal activity. */ 4302 #define TCM_REG_PRS_IFEN 0x50020 4303 /* [RC 1] Message length mismatch (relative to last indication) at the In#6 4304 interface. */ 4305 #define TCM_REG_PRS_LENGTH_MIS 0x50168 4306 /* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for 4307 weight 8 (the most prioritised); 1 stands for weight 1(least 4308 prioritised); 2 stands for weight 2; tc. */ 4309 #define TCM_REG_PRS_WEIGHT 0x500b0 4310 /* [RW 8] The Event ID for Timers formatting in case of stop done. */ 4311 #define TCM_REG_STOP_EVNT_ID 0x500a8 4312 /* [RC 1] Message length mismatch (relative to last indication) at the STORM 4313 interface. */ 4314 #define TCM_REG_STORM_LENGTH_MIS 0x50160 4315 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 4316 disregarded; acknowledge output is deasserted; all other signals are 4317 treated as usual; if 1 - normal activity. */ 4318 #define TCM_REG_STORM_TCM_IFEN 0x50010 4319 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for 4320 weight 8 (the most prioritised); 1 stands for weight 1(least 4321 prioritised); 2 stands for weight 2; tc. */ 4322 #define TCM_REG_STORM_WEIGHT 0x500ac 4323 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 4324 acknowledge output is deasserted; all other signals are treated as usual; 4325 if 1 - normal activity. */ 4326 #define TCM_REG_TCM_CFC_IFEN 0x50040 4327 /* [RW 11] Interrupt mask register #0 read/write */ 4328 #define TCM_REG_TCM_INT_MASK 0x501dc 4329 /* [R 11] Interrupt register #0 read */ 4330 #define TCM_REG_TCM_INT_STS 0x501d0 4331 /* [RW 27] Parity mask register #0 read/write */ 4332 #define TCM_REG_TCM_PRTY_MASK 0x501ec 4333 /* [R 27] Parity register #0 read */ 4334 #define TCM_REG_TCM_PRTY_STS 0x501e0 4335 /* [RC 27] Parity register #0 read clear */ 4336 #define TCM_REG_TCM_PRTY_STS_CLR 0x501e4 4337 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS 4338 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 4339 Is used to determine the number of the AG context REG-pairs written back; 4340 when the input message Reg1WbFlg isn't set. */ 4341 #define TCM_REG_TCM_REG0_SZ 0x500d8 4342 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 4343 disregarded; valid is deasserted; all other signals are treated as usual; 4344 if 1 - normal activity. */ 4345 #define TCM_REG_TCM_STORM0_IFEN 0x50004 4346 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 4347 disregarded; valid is deasserted; all other signals are treated as usual; 4348 if 1 - normal activity. */ 4349 #define TCM_REG_TCM_STORM1_IFEN 0x50008 4350 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 4351 disregarded; valid is deasserted; all other signals are treated as usual; 4352 if 1 - normal activity. */ 4353 #define TCM_REG_TCM_TQM_IFEN 0x5000c 4354 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */ 4355 #define TCM_REG_TCM_TQM_USE_Q 0x500d4 4356 /* [RW 28] The CM header for Timers expiration command. */ 4357 #define TCM_REG_TM_TCM_HDR 0x50098 4358 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is 4359 disregarded; acknowledge output is deasserted; all other signals are 4360 treated as usual; if 1 - normal activity. */ 4361 #define TCM_REG_TM_TCM_IFEN 0x5001c 4362 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for 4363 weight 8 (the most prioritised); 1 stands for weight 1(least 4364 prioritised); 2 stands for weight 2; tc. */ 4365 #define TCM_REG_TM_WEIGHT 0x500d0 4366 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes 4367 the initial credit value; read returns the current value of the credit 4368 counter. Must be initialized to 32 at start-up. */ 4369 #define TCM_REG_TQM_INIT_CRD 0x5021c 4370 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 4371 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 4372 prioritised); 2 stands for weight 2; tc. */ 4373 #define TCM_REG_TQM_P_WEIGHT 0x500c8 4374 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 4375 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 4376 prioritised); 2 stands for weight 2; tc. */ 4377 #define TCM_REG_TQM_S_WEIGHT 0x500cc 4378 /* [RW 28] The CM header value for QM request (primary). */ 4379 #define TCM_REG_TQM_TCM_HDR_P 0x50090 4380 /* [RW 28] The CM header value for QM request (secondary). */ 4381 #define TCM_REG_TQM_TCM_HDR_S 0x50094 4382 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 4383 acknowledge output is deasserted; all other signals are treated as usual; 4384 if 1 - normal activity. */ 4385 #define TCM_REG_TQM_TCM_IFEN 0x50014 4386 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 4387 acknowledge output is deasserted; all other signals are treated as usual; 4388 if 1 - normal activity. */ 4389 #define TCM_REG_TSDM_IFEN 0x50018 4390 /* [RC 1] Message length mismatch (relative to last indication) at the SDM 4391 interface. */ 4392 #define TCM_REG_TSDM_LENGTH_MIS 0x50164 4393 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for 4394 weight 8 (the most prioritised); 1 stands for weight 1(least 4395 prioritised); 2 stands for weight 2; tc. */ 4396 #define TCM_REG_TSDM_WEIGHT 0x500c4 4397 /* [RW 1] Input usem Interface enable. If 0 - the valid input is 4398 disregarded; acknowledge output is deasserted; all other signals are 4399 treated as usual; if 1 - normal activity. */ 4400 #define TCM_REG_USEM_IFEN 0x50028 4401 /* [RC 1] Message length mismatch (relative to last indication) at the In#8 4402 interface. */ 4403 #define TCM_REG_USEM_LENGTH_MIS 0x50170 4404 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for 4405 weight 8 (the most prioritised); 1 stands for weight 1(least 4406 prioritised); 2 stands for weight 2; tc. */ 4407 #define TCM_REG_USEM_WEIGHT 0x500b8 4408 /* [RW 21] Indirect access to the descriptor table of the XX protection 4409 mechanism. The fields are: [5:0] - length of the message; 15:6] - message 4410 pointer; 20:16] - next pointer. */ 4411 #define TCM_REG_XX_DESCR_TABLE 0x50280 4412 #define TCM_REG_XX_DESCR_TABLE_SIZE 29 4413 /* [R 6] Use to read the value of XX protection Free counter. */ 4414 #define TCM_REG_XX_FREE 0x50178 4415 /* [RW 6] Initial value for the credit counter; responsible for fulfilling 4416 of the Input Stage XX protection buffer by the XX protection pending 4417 messages. Max credit available - 127.Write writes the initial credit 4418 value; read returns the current value of the credit counter. Must be 4419 initialized to 19 at start-up. */ 4420 #define TCM_REG_XX_INIT_CRD 0x50220 4421 /* [RW 6] Maximum link list size (messages locked) per connection in the XX 4422 protection. */ 4423 #define TCM_REG_XX_MAX_LL_SZ 0x50044 4424 /* [RW 6] The maximum number of pending messages; which may be stored in XX 4425 protection. ~tcm_registers_xx_free.xx_free is read on read. */ 4426 #define TCM_REG_XX_MSG_NUM 0x50224 4427 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 4428 #define TCM_REG_XX_OVFL_EVNT_ID 0x50048 4429 /* [RW 16] Indirect access to the XX table of the XX protection mechanism. 4430 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] - 4431 header pointer. */ 4432 #define TCM_REG_XX_TABLE 0x50240 4433 /* [RW 4] Load value for cfc ac credit cnt. */ 4434 #define TM_REG_CFC_AC_CRDCNT_VAL 0x164208 4435 /* [RW 4] Load value for cfc cld credit cnt. */ 4436 #define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210 4437 /* [RW 8] Client0 context region. */ 4438 #define TM_REG_CL0_CONT_REGION 0x164030 4439 /* [RW 8] Client1 context region. */ 4440 #define TM_REG_CL1_CONT_REGION 0x164034 4441 /* [RW 8] Client2 context region. */ 4442 #define TM_REG_CL2_CONT_REGION 0x164038 4443 /* [RW 2] Client in High priority client number. */ 4444 #define TM_REG_CLIN_PRIOR0_CLIENT 0x164024 4445 /* [RW 4] Load value for clout0 cred cnt. */ 4446 #define TM_REG_CLOUT_CRDCNT0_VAL 0x164220 4447 /* [RW 4] Load value for clout1 cred cnt. */ 4448 #define TM_REG_CLOUT_CRDCNT1_VAL 0x164228 4449 /* [RW 4] Load value for clout2 cred cnt. */ 4450 #define TM_REG_CLOUT_CRDCNT2_VAL 0x164230 4451 /* [RW 1] Enable client0 input. */ 4452 #define TM_REG_EN_CL0_INPUT 0x164008 4453 /* [RW 1] Enable client1 input. */ 4454 #define TM_REG_EN_CL1_INPUT 0x16400c 4455 /* [RW 1] Enable client2 input. */ 4456 #define TM_REG_EN_CL2_INPUT 0x164010 4457 #define TM_REG_EN_LINEAR0_TIMER 0x164014 4458 /* [RW 1] Enable real time counter. */ 4459 #define TM_REG_EN_REAL_TIME_CNT 0x1640d8 4460 /* [RW 1] Enable for Timers state machines. */ 4461 #define TM_REG_EN_TIMERS 0x164000 4462 /* [RW 4] Load value for expiration credit cnt. CFC max number of 4463 outstanding load requests for timers (expiration) context loading. */ 4464 #define TM_REG_EXP_CRDCNT_VAL 0x164238 4465 /* [RW 32] Linear0 logic address. */ 4466 #define TM_REG_LIN0_LOGIC_ADDR 0x164240 4467 /* [RW 18] Linear0 Max active cid (in banks of 32 entries). */ 4468 #define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048 4469 /* [ST 16] Linear0 Number of scans counter. */ 4470 #define TM_REG_LIN0_NUM_SCANS 0x1640a0 4471 /* [WB 64] Linear0 phy address. */ 4472 #define TM_REG_LIN0_PHY_ADDR 0x164270 4473 /* [RW 1] Linear0 physical address valid. */ 4474 #define TM_REG_LIN0_PHY_ADDR_VALID 0x164248 4475 #define TM_REG_LIN0_SCAN_ON 0x1640d0 4476 /* [RW 24] Linear0 array scan timeout. */ 4477 #define TM_REG_LIN0_SCAN_TIME 0x16403c 4478 #define TM_REG_LIN0_VNIC_UC 0x164128 4479 /* [RW 32] Linear1 logic address. */ 4480 #define TM_REG_LIN1_LOGIC_ADDR 0x164250 4481 /* [WB 64] Linear1 phy address. */ 4482 #define TM_REG_LIN1_PHY_ADDR 0x164280 4483 /* [RW 1] Linear1 physical address valid. */ 4484 #define TM_REG_LIN1_PHY_ADDR_VALID 0x164258 4485 /* [RW 6] Linear timer set_clear fifo threshold. */ 4486 #define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070 4487 /* [RW 2] Load value for pci arbiter credit cnt. */ 4488 #define TM_REG_PCIARB_CRDCNT_VAL 0x164260 4489 /* [RW 20] The amount of hardware cycles for each timer tick. */ 4490 #define TM_REG_TIMER_TICK_SIZE 0x16401c 4491 /* [RW 8] Timers Context region. */ 4492 #define TM_REG_TM_CONTEXT_REGION 0x164044 4493 /* [RW 1] Interrupt mask register #0 read/write */ 4494 #define TM_REG_TM_INT_MASK 0x1640fc 4495 /* [R 1] Interrupt register #0 read */ 4496 #define TM_REG_TM_INT_STS 0x1640f0 4497 /* [RW 7] Parity mask register #0 read/write */ 4498 #define TM_REG_TM_PRTY_MASK 0x16410c 4499 /* [RC 7] Parity register #0 read clear */ 4500 #define TM_REG_TM_PRTY_STS_CLR 0x164104 4501 /* [RW 8] The event id for aggregated interrupt 0 */ 4502 #define TSDM_REG_AGG_INT_EVENT_0 0x42038 4503 #define TSDM_REG_AGG_INT_EVENT_1 0x4203c 4504 #define TSDM_REG_AGG_INT_EVENT_2 0x42040 4505 #define TSDM_REG_AGG_INT_EVENT_3 0x42044 4506 #define TSDM_REG_AGG_INT_EVENT_4 0x42048 4507 /* [RW 1] The T bit for aggregated interrupt 0 */ 4508 #define TSDM_REG_AGG_INT_T_0 0x420b8 4509 #define TSDM_REG_AGG_INT_T_1 0x420bc 4510 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 4511 #define TSDM_REG_CFC_RSP_START_ADDR 0x42008 4512 /* [RW 16] The maximum value of the completion counter #0 */ 4513 #define TSDM_REG_CMP_COUNTER_MAX0 0x4201c 4514 /* [RW 16] The maximum value of the completion counter #1 */ 4515 #define TSDM_REG_CMP_COUNTER_MAX1 0x42020 4516 /* [RW 16] The maximum value of the completion counter #2 */ 4517 #define TSDM_REG_CMP_COUNTER_MAX2 0x42024 4518 /* [RW 16] The maximum value of the completion counter #3 */ 4519 #define TSDM_REG_CMP_COUNTER_MAX3 0x42028 4520 /* [RW 13] The start address in the internal RAM for the completion 4521 counters. */ 4522 #define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c 4523 #define TSDM_REG_ENABLE_IN1 0x42238 4524 #define TSDM_REG_ENABLE_IN2 0x4223c 4525 #define TSDM_REG_ENABLE_OUT1 0x42240 4526 #define TSDM_REG_ENABLE_OUT2 0x42244 4527 /* [RW 4] The initial number of messages that can be sent to the pxp control 4528 interface without receiving any ACK. */ 4529 #define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc 4530 /* [ST 32] The number of ACK after placement messages received */ 4531 #define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c 4532 /* [ST 32] The number of packet end messages received from the parser */ 4533 #define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274 4534 /* [ST 32] The number of requests received from the pxp async if */ 4535 #define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278 4536 /* [ST 32] The number of commands received in queue 0 */ 4537 #define TSDM_REG_NUM_OF_Q0_CMD 0x42248 4538 /* [ST 32] The number of commands received in queue 10 */ 4539 #define TSDM_REG_NUM_OF_Q10_CMD 0x4226c 4540 /* [ST 32] The number of commands received in queue 11 */ 4541 #define TSDM_REG_NUM_OF_Q11_CMD 0x42270 4542 /* [ST 32] The number of commands received in queue 1 */ 4543 #define TSDM_REG_NUM_OF_Q1_CMD 0x4224c 4544 /* [ST 32] The number of commands received in queue 3 */ 4545 #define TSDM_REG_NUM_OF_Q3_CMD 0x42250 4546 /* [ST 32] The number of commands received in queue 4 */ 4547 #define TSDM_REG_NUM_OF_Q4_CMD 0x42254 4548 /* [ST 32] The number of commands received in queue 5 */ 4549 #define TSDM_REG_NUM_OF_Q5_CMD 0x42258 4550 /* [ST 32] The number of commands received in queue 6 */ 4551 #define TSDM_REG_NUM_OF_Q6_CMD 0x4225c 4552 /* [ST 32] The number of commands received in queue 7 */ 4553 #define TSDM_REG_NUM_OF_Q7_CMD 0x42260 4554 /* [ST 32] The number of commands received in queue 8 */ 4555 #define TSDM_REG_NUM_OF_Q8_CMD 0x42264 4556 /* [ST 32] The number of commands received in queue 9 */ 4557 #define TSDM_REG_NUM_OF_Q9_CMD 0x42268 4558 /* [RW 13] The start address in the internal RAM for the packet end message */ 4559 #define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014 4560 /* [RW 13] The start address in the internal RAM for queue counters */ 4561 #define TSDM_REG_Q_COUNTER_START_ADDR 0x42010 4562 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 4563 #define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548 4564 /* [R 1] parser fifo empty in sdm_sync block */ 4565 #define TSDM_REG_SYNC_PARSER_EMPTY 0x42550 4566 /* [R 1] parser serial fifo empty in sdm_sync block */ 4567 #define TSDM_REG_SYNC_SYNC_EMPTY 0x42558 4568 /* [RW 32] Tick for timer counter. Applicable only when 4569 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */ 4570 #define TSDM_REG_TIMER_TICK 0x42000 4571 /* [RW 32] Interrupt mask register #0 read/write */ 4572 #define TSDM_REG_TSDM_INT_MASK_0 0x4229c 4573 #define TSDM_REG_TSDM_INT_MASK_1 0x422ac 4574 /* [R 32] Interrupt register #0 read */ 4575 #define TSDM_REG_TSDM_INT_STS_0 0x42290 4576 #define TSDM_REG_TSDM_INT_STS_1 0x422a0 4577 /* [RW 11] Parity mask register #0 read/write */ 4578 #define TSDM_REG_TSDM_PRTY_MASK 0x422bc 4579 /* [R 11] Parity register #0 read */ 4580 #define TSDM_REG_TSDM_PRTY_STS 0x422b0 4581 /* [RC 11] Parity register #0 read clear */ 4582 #define TSDM_REG_TSDM_PRTY_STS_CLR 0x422b4 4583 /* [RW 5] The number of time_slots in the arbitration cycle */ 4584 #define TSEM_REG_ARB_CYCLE_SIZE 0x180034 4585 /* [RW 3] The source that is associated with arbitration element 0. Source 4586 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4587 sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 4588 #define TSEM_REG_ARB_ELEMENT0 0x180020 4589 /* [RW 3] The source that is associated with arbitration element 1. Source 4590 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4591 sleeping thread with priority 1; 4- sleeping thread with priority 2. 4592 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */ 4593 #define TSEM_REG_ARB_ELEMENT1 0x180024 4594 /* [RW 3] The source that is associated with arbitration element 2. Source 4595 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4596 sleeping thread with priority 1; 4- sleeping thread with priority 2. 4597 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 4598 and ~tsem_registers_arb_element1.arb_element1 */ 4599 #define TSEM_REG_ARB_ELEMENT2 0x180028 4600 /* [RW 3] The source that is associated with arbitration element 3. Source 4601 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4602 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 4603 not be equal to register ~tsem_registers_arb_element0.arb_element0 and 4604 ~tsem_registers_arb_element1.arb_element1 and 4605 ~tsem_registers_arb_element2.arb_element2 */ 4606 #define TSEM_REG_ARB_ELEMENT3 0x18002c 4607 /* [RW 3] The source that is associated with arbitration element 4. Source 4608 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4609 sleeping thread with priority 1; 4- sleeping thread with priority 2. 4610 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 4611 and ~tsem_registers_arb_element1.arb_element1 and 4612 ~tsem_registers_arb_element2.arb_element2 and 4613 ~tsem_registers_arb_element3.arb_element3 */ 4614 #define TSEM_REG_ARB_ELEMENT4 0x180030 4615 #define TSEM_REG_ENABLE_IN 0x1800a4 4616 #define TSEM_REG_ENABLE_OUT 0x1800a8 4617 /* [RW 32] This address space contains all registers and memories that are 4618 placed in SEM_FAST block. The SEM_FAST registers are described in 4619 appendix B. In order to access the sem_fast registers the base address 4620 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 4621 #define TSEM_REG_FAST_MEMORY 0x1a0000 4622 /* [RW 1] Disables input messages from FIC0 May be updated during run_time 4623 by the microcode */ 4624 #define TSEM_REG_FIC0_DISABLE 0x180224 4625 /* [RW 1] Disables input messages from FIC1 May be updated during run_time 4626 by the microcode */ 4627 #define TSEM_REG_FIC1_DISABLE 0x180234 4628 /* [RW 15] Interrupt table Read and write access to it is not possible in 4629 the middle of the work */ 4630 #define TSEM_REG_INT_TABLE 0x180400 4631 /* [ST 24] Statistics register. The number of messages that entered through 4632 FIC0 */ 4633 #define TSEM_REG_MSG_NUM_FIC0 0x180000 4634 /* [ST 24] Statistics register. The number of messages that entered through 4635 FIC1 */ 4636 #define TSEM_REG_MSG_NUM_FIC1 0x180004 4637 /* [ST 24] Statistics register. The number of messages that were sent to 4638 FOC0 */ 4639 #define TSEM_REG_MSG_NUM_FOC0 0x180008 4640 /* [ST 24] Statistics register. The number of messages that were sent to 4641 FOC1 */ 4642 #define TSEM_REG_MSG_NUM_FOC1 0x18000c 4643 /* [ST 24] Statistics register. The number of messages that were sent to 4644 FOC2 */ 4645 #define TSEM_REG_MSG_NUM_FOC2 0x180010 4646 /* [ST 24] Statistics register. The number of messages that were sent to 4647 FOC3 */ 4648 #define TSEM_REG_MSG_NUM_FOC3 0x180014 4649 /* [RW 1] Disables input messages from the passive buffer May be updated 4650 during run_time by the microcode */ 4651 #define TSEM_REG_PAS_DISABLE 0x18024c 4652 /* [WB 128] Debug only. Passive buffer memory */ 4653 #define TSEM_REG_PASSIVE_BUFFER 0x181000 4654 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 4655 #define TSEM_REG_PRAM 0x1c0000 4656 /* [R 8] Valid sleeping threads indication have bit per thread */ 4657 #define TSEM_REG_SLEEP_THREADS_VALID 0x18026c 4658 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 4659 #define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0 4660 /* [RW 8] List of free threads . There is a bit per thread. */ 4661 #define TSEM_REG_THREADS_LIST 0x1802e4 4662 /* [RC 32] Parity register #0 read clear */ 4663 #define TSEM_REG_TSEM_PRTY_STS_CLR_0 0x180118 4664 #define TSEM_REG_TSEM_PRTY_STS_CLR_1 0x180128 4665 /* [RW 3] The arbitration scheme of time_slot 0 */ 4666 #define TSEM_REG_TS_0_AS 0x180038 4667 /* [RW 3] The arbitration scheme of time_slot 10 */ 4668 #define TSEM_REG_TS_10_AS 0x180060 4669 /* [RW 3] The arbitration scheme of time_slot 11 */ 4670 #define TSEM_REG_TS_11_AS 0x180064 4671 /* [RW 3] The arbitration scheme of time_slot 12 */ 4672 #define TSEM_REG_TS_12_AS 0x180068 4673 /* [RW 3] The arbitration scheme of time_slot 13 */ 4674 #define TSEM_REG_TS_13_AS 0x18006c 4675 /* [RW 3] The arbitration scheme of time_slot 14 */ 4676 #define TSEM_REG_TS_14_AS 0x180070 4677 /* [RW 3] The arbitration scheme of time_slot 15 */ 4678 #define TSEM_REG_TS_15_AS 0x180074 4679 /* [RW 3] The arbitration scheme of time_slot 16 */ 4680 #define TSEM_REG_TS_16_AS 0x180078 4681 /* [RW 3] The arbitration scheme of time_slot 17 */ 4682 #define TSEM_REG_TS_17_AS 0x18007c 4683 /* [RW 3] The arbitration scheme of time_slot 18 */ 4684 #define TSEM_REG_TS_18_AS 0x180080 4685 /* [RW 3] The arbitration scheme of time_slot 1 */ 4686 #define TSEM_REG_TS_1_AS 0x18003c 4687 /* [RW 3] The arbitration scheme of time_slot 2 */ 4688 #define TSEM_REG_TS_2_AS 0x180040 4689 /* [RW 3] The arbitration scheme of time_slot 3 */ 4690 #define TSEM_REG_TS_3_AS 0x180044 4691 /* [RW 3] The arbitration scheme of time_slot 4 */ 4692 #define TSEM_REG_TS_4_AS 0x180048 4693 /* [RW 3] The arbitration scheme of time_slot 5 */ 4694 #define TSEM_REG_TS_5_AS 0x18004c 4695 /* [RW 3] The arbitration scheme of time_slot 6 */ 4696 #define TSEM_REG_TS_6_AS 0x180050 4697 /* [RW 3] The arbitration scheme of time_slot 7 */ 4698 #define TSEM_REG_TS_7_AS 0x180054 4699 /* [RW 3] The arbitration scheme of time_slot 8 */ 4700 #define TSEM_REG_TS_8_AS 0x180058 4701 /* [RW 3] The arbitration scheme of time_slot 9 */ 4702 #define TSEM_REG_TS_9_AS 0x18005c 4703 /* [RW 32] Interrupt mask register #0 read/write */ 4704 #define TSEM_REG_TSEM_INT_MASK_0 0x180100 4705 #define TSEM_REG_TSEM_INT_MASK_1 0x180110 4706 /* [R 32] Interrupt register #0 read */ 4707 #define TSEM_REG_TSEM_INT_STS_0 0x1800f4 4708 #define TSEM_REG_TSEM_INT_STS_1 0x180104 4709 /* [RW 32] Parity mask register #0 read/write */ 4710 #define TSEM_REG_TSEM_PRTY_MASK_0 0x180120 4711 #define TSEM_REG_TSEM_PRTY_MASK_1 0x180130 4712 /* [R 32] Parity register #0 read */ 4713 #define TSEM_REG_TSEM_PRTY_STS_0 0x180114 4714 #define TSEM_REG_TSEM_PRTY_STS_1 0x180124 4715 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 4716 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ 4717 #define TSEM_REG_VFPF_ERR_NUM 0x180380 4718 /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits 4719 * [10:8] of the address should be the offset within the accessed LCID 4720 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10 4721 * LCID100. The RBC address should be 12'ha64. */ 4722 #define UCM_REG_AG_CTX 0xe2000 4723 /* [R 5] Used to read the XX protection CAM occupancy counter. */ 4724 #define UCM_REG_CAM_OCCUP 0xe0170 4725 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is 4726 disregarded; valid output is deasserted; all other signals are treated as 4727 usual; if 1 - normal activity. */ 4728 #define UCM_REG_CDU_AG_RD_IFEN 0xe0038 4729 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 4730 are disregarded; all other signals are treated as usual; if 1 - normal 4731 activity. */ 4732 #define UCM_REG_CDU_AG_WR_IFEN 0xe0034 4733 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 4734 disregarded; valid output is deasserted; all other signals are treated as 4735 usual; if 1 - normal activity. */ 4736 #define UCM_REG_CDU_SM_RD_IFEN 0xe0040 4737 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 4738 input is disregarded; all other signals are treated as usual; if 1 - 4739 normal activity. */ 4740 #define UCM_REG_CDU_SM_WR_IFEN 0xe003c 4741 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 4742 the initial credit value; read returns the current value of the credit 4743 counter. Must be initialized to 1 at start-up. */ 4744 #define UCM_REG_CFC_INIT_CRD 0xe0204 4745 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for 4746 weight 8 (the most prioritised); 1 stands for weight 1(least 4747 prioritised); 2 stands for weight 2; tc. */ 4748 #define UCM_REG_CP_WEIGHT 0xe00c4 4749 /* [RW 1] Input csem Interface enable. If 0 - the valid input is 4750 disregarded; acknowledge output is deasserted; all other signals are 4751 treated as usual; if 1 - normal activity. */ 4752 #define UCM_REG_CSEM_IFEN 0xe0028 4753 /* [RC 1] Set when the message length mismatch (relative to last indication) 4754 at the csem interface is detected. */ 4755 #define UCM_REG_CSEM_LENGTH_MIS 0xe0160 4756 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for 4757 weight 8 (the most prioritised); 1 stands for weight 1(least 4758 prioritised); 2 stands for weight 2; tc. */ 4759 #define UCM_REG_CSEM_WEIGHT 0xe00b8 4760 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is 4761 disregarded; acknowledge output is deasserted; all other signals are 4762 treated as usual; if 1 - normal activity. */ 4763 #define UCM_REG_DORQ_IFEN 0xe0030 4764 /* [RC 1] Set when the message length mismatch (relative to last indication) 4765 at the dorq interface is detected. */ 4766 #define UCM_REG_DORQ_LENGTH_MIS 0xe0168 4767 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for 4768 weight 8 (the most prioritised); 1 stands for weight 1(least 4769 prioritised); 2 stands for weight 2; tc. */ 4770 #define UCM_REG_DORQ_WEIGHT 0xe00c0 4771 /* [RW 8] The Event ID in case ErrorFlg input message bit is set. */ 4772 #define UCM_REG_ERR_EVNT_ID 0xe00a4 4773 /* [RW 28] The CM erroneous header for QM and Timers formatting. */ 4774 #define UCM_REG_ERR_UCM_HDR 0xe00a0 4775 /* [RW 8] The Event ID for Timers expiration. */ 4776 #define UCM_REG_EXPR_EVNT_ID 0xe00a8 4777 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write 4778 writes the initial credit value; read returns the current value of the 4779 credit counter. Must be initialized to 64 at start-up. */ 4780 #define UCM_REG_FIC0_INIT_CRD 0xe020c 4781 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 4782 writes the initial credit value; read returns the current value of the 4783 credit counter. Must be initialized to 64 at start-up. */ 4784 #define UCM_REG_FIC1_INIT_CRD 0xe0210 4785 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 4786 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr; 4787 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and 4788 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */ 4789 #define UCM_REG_GR_ARB_TYPE 0xe0144 4790 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 4791 highest priority is 3. It is supposed that the Store channel group is 4792 compliment to the others. */ 4793 #define UCM_REG_GR_LD0_PR 0xe014c 4794 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 4795 highest priority is 3. It is supposed that the Store channel group is 4796 compliment to the others. */ 4797 #define UCM_REG_GR_LD1_PR 0xe0150 4798 /* [RW 2] The queue index for invalidate counter flag decision. */ 4799 #define UCM_REG_INV_CFLG_Q 0xe00e4 4800 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and 4801 sent to STORM; for a specific connection type. the double REG-pairs are 4802 used in order to align to STORM context row size of 128 bits. The offset 4803 of these data in the STORM context is always 0. Index _i stands for the 4804 connection type (one of 16). */ 4805 #define UCM_REG_N_SM_CTX_LD_0 0xe0054 4806 #define UCM_REG_N_SM_CTX_LD_1 0xe0058 4807 #define UCM_REG_N_SM_CTX_LD_2 0xe005c 4808 #define UCM_REG_N_SM_CTX_LD_3 0xe0060 4809 #define UCM_REG_N_SM_CTX_LD_4 0xe0064 4810 #define UCM_REG_N_SM_CTX_LD_5 0xe0068 4811 #define UCM_REG_PHYS_QNUM0_0 0xe0110 4812 #define UCM_REG_PHYS_QNUM0_1 0xe0114 4813 #define UCM_REG_PHYS_QNUM1_0 0xe0118 4814 #define UCM_REG_PHYS_QNUM1_1 0xe011c 4815 #define UCM_REG_PHYS_QNUM2_0 0xe0120 4816 #define UCM_REG_PHYS_QNUM2_1 0xe0124 4817 #define UCM_REG_PHYS_QNUM3_0 0xe0128 4818 #define UCM_REG_PHYS_QNUM3_1 0xe012c 4819 /* [RW 8] The Event ID for Timers formatting in case of stop done. */ 4820 #define UCM_REG_STOP_EVNT_ID 0xe00ac 4821 /* [RC 1] Set when the message length mismatch (relative to last indication) 4822 at the STORM interface is detected. */ 4823 #define UCM_REG_STORM_LENGTH_MIS 0xe0154 4824 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 4825 disregarded; acknowledge output is deasserted; all other signals are 4826 treated as usual; if 1 - normal activity. */ 4827 #define UCM_REG_STORM_UCM_IFEN 0xe0010 4828 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for 4829 weight 8 (the most prioritised); 1 stands for weight 1(least 4830 prioritised); 2 stands for weight 2; tc. */ 4831 #define UCM_REG_STORM_WEIGHT 0xe00b0 4832 /* [RW 4] Timers output initial credit. Max credit available - 15.Write 4833 writes the initial credit value; read returns the current value of the 4834 credit counter. Must be initialized to 4 at start-up. */ 4835 #define UCM_REG_TM_INIT_CRD 0xe021c 4836 /* [RW 28] The CM header for Timers expiration command. */ 4837 #define UCM_REG_TM_UCM_HDR 0xe009c 4838 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is 4839 disregarded; acknowledge output is deasserted; all other signals are 4840 treated as usual; if 1 - normal activity. */ 4841 #define UCM_REG_TM_UCM_IFEN 0xe001c 4842 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for 4843 weight 8 (the most prioritised); 1 stands for weight 1(least 4844 prioritised); 2 stands for weight 2; tc. */ 4845 #define UCM_REG_TM_WEIGHT 0xe00d4 4846 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is 4847 disregarded; acknowledge output is deasserted; all other signals are 4848 treated as usual; if 1 - normal activity. */ 4849 #define UCM_REG_TSEM_IFEN 0xe0024 4850 /* [RC 1] Set when the message length mismatch (relative to last indication) 4851 at the tsem interface is detected. */ 4852 #define UCM_REG_TSEM_LENGTH_MIS 0xe015c 4853 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for 4854 weight 8 (the most prioritised); 1 stands for weight 1(least 4855 prioritised); 2 stands for weight 2; tc. */ 4856 #define UCM_REG_TSEM_WEIGHT 0xe00b4 4857 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 4858 acknowledge output is deasserted; all other signals are treated as usual; 4859 if 1 - normal activity. */ 4860 #define UCM_REG_UCM_CFC_IFEN 0xe0044 4861 /* [RW 11] Interrupt mask register #0 read/write */ 4862 #define UCM_REG_UCM_INT_MASK 0xe01d4 4863 /* [R 11] Interrupt register #0 read */ 4864 #define UCM_REG_UCM_INT_STS 0xe01c8 4865 /* [RW 27] Parity mask register #0 read/write */ 4866 #define UCM_REG_UCM_PRTY_MASK 0xe01e4 4867 /* [R 27] Parity register #0 read */ 4868 #define UCM_REG_UCM_PRTY_STS 0xe01d8 4869 /* [RC 27] Parity register #0 read clear */ 4870 #define UCM_REG_UCM_PRTY_STS_CLR 0xe01dc 4871 /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS 4872 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 4873 Is used to determine the number of the AG context REG-pairs written back; 4874 when the Reg1WbFlg isn't set. */ 4875 #define UCM_REG_UCM_REG0_SZ 0xe00dc 4876 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 4877 disregarded; valid is deasserted; all other signals are treated as usual; 4878 if 1 - normal activity. */ 4879 #define UCM_REG_UCM_STORM0_IFEN 0xe0004 4880 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 4881 disregarded; valid is deasserted; all other signals are treated as usual; 4882 if 1 - normal activity. */ 4883 #define UCM_REG_UCM_STORM1_IFEN 0xe0008 4884 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is 4885 disregarded; acknowledge output is deasserted; all other signals are 4886 treated as usual; if 1 - normal activity. */ 4887 #define UCM_REG_UCM_TM_IFEN 0xe0020 4888 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 4889 disregarded; valid is deasserted; all other signals are treated as usual; 4890 if 1 - normal activity. */ 4891 #define UCM_REG_UCM_UQM_IFEN 0xe000c 4892 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */ 4893 #define UCM_REG_UCM_UQM_USE_Q 0xe00d8 4894 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes 4895 the initial credit value; read returns the current value of the credit 4896 counter. Must be initialized to 32 at start-up. */ 4897 #define UCM_REG_UQM_INIT_CRD 0xe0220 4898 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 4899 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 4900 prioritised); 2 stands for weight 2; tc. */ 4901 #define UCM_REG_UQM_P_WEIGHT 0xe00cc 4902 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 4903 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 4904 prioritised); 2 stands for weight 2; tc. */ 4905 #define UCM_REG_UQM_S_WEIGHT 0xe00d0 4906 /* [RW 28] The CM header value for QM request (primary). */ 4907 #define UCM_REG_UQM_UCM_HDR_P 0xe0094 4908 /* [RW 28] The CM header value for QM request (secondary). */ 4909 #define UCM_REG_UQM_UCM_HDR_S 0xe0098 4910 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 4911 acknowledge output is deasserted; all other signals are treated as usual; 4912 if 1 - normal activity. */ 4913 #define UCM_REG_UQM_UCM_IFEN 0xe0014 4914 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 4915 acknowledge output is deasserted; all other signals are treated as usual; 4916 if 1 - normal activity. */ 4917 #define UCM_REG_USDM_IFEN 0xe0018 4918 /* [RC 1] Set when the message length mismatch (relative to last indication) 4919 at the SDM interface is detected. */ 4920 #define UCM_REG_USDM_LENGTH_MIS 0xe0158 4921 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for 4922 weight 8 (the most prioritised); 1 stands for weight 1(least 4923 prioritised); 2 stands for weight 2; tc. */ 4924 #define UCM_REG_USDM_WEIGHT 0xe00c8 4925 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is 4926 disregarded; acknowledge output is deasserted; all other signals are 4927 treated as usual; if 1 - normal activity. */ 4928 #define UCM_REG_XSEM_IFEN 0xe002c 4929 /* [RC 1] Set when the message length mismatch (relative to last indication) 4930 at the xsem interface isdetected. */ 4931 #define UCM_REG_XSEM_LENGTH_MIS 0xe0164 4932 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for 4933 weight 8 (the most prioritised); 1 stands for weight 1(least 4934 prioritised); 2 stands for weight 2; tc. */ 4935 #define UCM_REG_XSEM_WEIGHT 0xe00bc 4936 /* [RW 20] Indirect access to the descriptor table of the XX protection 4937 mechanism. The fields are:[5:0] - message length; 14:6] - message 4938 pointer; 19:15] - next pointer. */ 4939 #define UCM_REG_XX_DESCR_TABLE 0xe0280 4940 #define UCM_REG_XX_DESCR_TABLE_SIZE 27 4941 /* [R 6] Use to read the XX protection Free counter. */ 4942 #define UCM_REG_XX_FREE 0xe016c 4943 /* [RW 6] Initial value for the credit counter; responsible for fulfilling 4944 of the Input Stage XX protection buffer by the XX protection pending 4945 messages. Write writes the initial credit value; read returns the current 4946 value of the credit counter. Must be initialized to 12 at start-up. */ 4947 #define UCM_REG_XX_INIT_CRD 0xe0224 4948 /* [RW 6] The maximum number of pending messages; which may be stored in XX 4949 protection. ~ucm_registers_xx_free.xx_free read on read. */ 4950 #define UCM_REG_XX_MSG_NUM 0xe0228 4951 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 4952 #define UCM_REG_XX_OVFL_EVNT_ID 0xe004c 4953 /* [RW 16] Indirect access to the XX table of the XX protection mechanism. 4954 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] - 4955 header pointer. */ 4956 #define UCM_REG_XX_TABLE 0xe0300 4957 #define UMAC_COMMAND_CONFIG_REG_HD_ENA (0x1<<10) 4958 #define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE (0x1<<28) 4959 #define UMAC_COMMAND_CONFIG_REG_LOOP_ENA (0x1<<15) 4960 #define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK (0x1<<24) 4961 #define UMAC_COMMAND_CONFIG_REG_PAD_EN (0x1<<5) 4962 #define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE (0x1<<8) 4963 #define UMAC_COMMAND_CONFIG_REG_PROMIS_EN (0x1<<4) 4964 #define UMAC_COMMAND_CONFIG_REG_RX_ENA (0x1<<1) 4965 #define UMAC_COMMAND_CONFIG_REG_SW_RESET (0x1<<13) 4966 #define UMAC_COMMAND_CONFIG_REG_TX_ENA (0x1<<0) 4967 #define UMAC_REG_COMMAND_CONFIG 0x8 4968 /* [RW 16] This is the duration for which MAC must wait to go back to ACTIVE 4969 * state from LPI state when it receives packet for transmission. The 4970 * decrement unit is 1 micro-second. */ 4971 #define UMAC_REG_EEE_WAKE_TIMER 0x6c 4972 /* [RW 32] Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refers 4973 * to bit 17 of the MAC address etc. */ 4974 #define UMAC_REG_MAC_ADDR0 0xc 4975 /* [RW 16] Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 1 4976 * refers to Bit 1 of the MAC address etc. Bits 16 to 31 are reserved. */ 4977 #define UMAC_REG_MAC_ADDR1 0x10 4978 /* [RW 14] Defines a 14-Bit maximum frame length used by the MAC receive 4979 * logic to check frames. */ 4980 #define UMAC_REG_MAXFR 0x14 4981 #define UMAC_REG_UMAC_EEE_CTRL 0x64 4982 #define UMAC_UMAC_EEE_CTRL_REG_EEE_EN (0x1<<3) 4983 /* [RW 8] The event id for aggregated interrupt 0 */ 4984 #define USDM_REG_AGG_INT_EVENT_0 0xc4038 4985 #define USDM_REG_AGG_INT_EVENT_1 0xc403c 4986 #define USDM_REG_AGG_INT_EVENT_2 0xc4040 4987 #define USDM_REG_AGG_INT_EVENT_4 0xc4048 4988 #define USDM_REG_AGG_INT_EVENT_5 0xc404c 4989 #define USDM_REG_AGG_INT_EVENT_6 0xc4050 4990 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0) 4991 or auto-mask-mode (1) */ 4992 #define USDM_REG_AGG_INT_MODE_0 0xc41b8 4993 #define USDM_REG_AGG_INT_MODE_1 0xc41bc 4994 #define USDM_REG_AGG_INT_MODE_4 0xc41c8 4995 #define USDM_REG_AGG_INT_MODE_5 0xc41cc 4996 #define USDM_REG_AGG_INT_MODE_6 0xc41d0 4997 /* [RW 1] The T bit for aggregated interrupt 5 */ 4998 #define USDM_REG_AGG_INT_T_5 0xc40cc 4999 #define USDM_REG_AGG_INT_T_6 0xc40d0 5000 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 5001 #define USDM_REG_CFC_RSP_START_ADDR 0xc4008 5002 /* [RW 16] The maximum value of the completion counter #0 */ 5003 #define USDM_REG_CMP_COUNTER_MAX0 0xc401c 5004 /* [RW 16] The maximum value of the completion counter #1 */ 5005 #define USDM_REG_CMP_COUNTER_MAX1 0xc4020 5006 /* [RW 16] The maximum value of the completion counter #2 */ 5007 #define USDM_REG_CMP_COUNTER_MAX2 0xc4024 5008 /* [RW 16] The maximum value of the completion counter #3 */ 5009 #define USDM_REG_CMP_COUNTER_MAX3 0xc4028 5010 /* [RW 13] The start address in the internal RAM for the completion 5011 counters. */ 5012 #define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c 5013 #define USDM_REG_ENABLE_IN1 0xc4238 5014 #define USDM_REG_ENABLE_IN2 0xc423c 5015 #define USDM_REG_ENABLE_OUT1 0xc4240 5016 #define USDM_REG_ENABLE_OUT2 0xc4244 5017 /* [RW 4] The initial number of messages that can be sent to the pxp control 5018 interface without receiving any ACK. */ 5019 #define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0 5020 /* [ST 32] The number of ACK after placement messages received */ 5021 #define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280 5022 /* [ST 32] The number of packet end messages received from the parser */ 5023 #define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278 5024 /* [ST 32] The number of requests received from the pxp async if */ 5025 #define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c 5026 /* [ST 32] The number of commands received in queue 0 */ 5027 #define USDM_REG_NUM_OF_Q0_CMD 0xc4248 5028 /* [ST 32] The number of commands received in queue 10 */ 5029 #define USDM_REG_NUM_OF_Q10_CMD 0xc4270 5030 /* [ST 32] The number of commands received in queue 11 */ 5031 #define USDM_REG_NUM_OF_Q11_CMD 0xc4274 5032 /* [ST 32] The number of commands received in queue 1 */ 5033 #define USDM_REG_NUM_OF_Q1_CMD 0xc424c 5034 /* [ST 32] The number of commands received in queue 2 */ 5035 #define USDM_REG_NUM_OF_Q2_CMD 0xc4250 5036 /* [ST 32] The number of commands received in queue 3 */ 5037 #define USDM_REG_NUM_OF_Q3_CMD 0xc4254 5038 /* [ST 32] The number of commands received in queue 4 */ 5039 #define USDM_REG_NUM_OF_Q4_CMD 0xc4258 5040 /* [ST 32] The number of commands received in queue 5 */ 5041 #define USDM_REG_NUM_OF_Q5_CMD 0xc425c 5042 /* [ST 32] The number of commands received in queue 6 */ 5043 #define USDM_REG_NUM_OF_Q6_CMD 0xc4260 5044 /* [ST 32] The number of commands received in queue 7 */ 5045 #define USDM_REG_NUM_OF_Q7_CMD 0xc4264 5046 /* [ST 32] The number of commands received in queue 8 */ 5047 #define USDM_REG_NUM_OF_Q8_CMD 0xc4268 5048 /* [ST 32] The number of commands received in queue 9 */ 5049 #define USDM_REG_NUM_OF_Q9_CMD 0xc426c 5050 /* [RW 13] The start address in the internal RAM for the packet end message */ 5051 #define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014 5052 /* [RW 13] The start address in the internal RAM for queue counters */ 5053 #define USDM_REG_Q_COUNTER_START_ADDR 0xc4010 5054 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 5055 #define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550 5056 /* [R 1] parser fifo empty in sdm_sync block */ 5057 #define USDM_REG_SYNC_PARSER_EMPTY 0xc4558 5058 /* [R 1] parser serial fifo empty in sdm_sync block */ 5059 #define USDM_REG_SYNC_SYNC_EMPTY 0xc4560 5060 /* [RW 32] Tick for timer counter. Applicable only when 5061 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */ 5062 #define USDM_REG_TIMER_TICK 0xc4000 5063 /* [RW 32] Interrupt mask register #0 read/write */ 5064 #define USDM_REG_USDM_INT_MASK_0 0xc42a0 5065 #define USDM_REG_USDM_INT_MASK_1 0xc42b0 5066 /* [R 32] Interrupt register #0 read */ 5067 #define USDM_REG_USDM_INT_STS_0 0xc4294 5068 #define USDM_REG_USDM_INT_STS_1 0xc42a4 5069 /* [RW 11] Parity mask register #0 read/write */ 5070 #define USDM_REG_USDM_PRTY_MASK 0xc42c0 5071 /* [R 11] Parity register #0 read */ 5072 #define USDM_REG_USDM_PRTY_STS 0xc42b4 5073 /* [RC 11] Parity register #0 read clear */ 5074 #define USDM_REG_USDM_PRTY_STS_CLR 0xc42b8 5075 /* [RW 5] The number of time_slots in the arbitration cycle */ 5076 #define USEM_REG_ARB_CYCLE_SIZE 0x300034 5077 /* [RW 3] The source that is associated with arbitration element 0. Source 5078 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5079 sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 5080 #define USEM_REG_ARB_ELEMENT0 0x300020 5081 /* [RW 3] The source that is associated with arbitration element 1. Source 5082 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5083 sleeping thread with priority 1; 4- sleeping thread with priority 2. 5084 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */ 5085 #define USEM_REG_ARB_ELEMENT1 0x300024 5086 /* [RW 3] The source that is associated with arbitration element 2. Source 5087 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5088 sleeping thread with priority 1; 4- sleeping thread with priority 2. 5089 Could not be equal to register ~usem_registers_arb_element0.arb_element0 5090 and ~usem_registers_arb_element1.arb_element1 */ 5091 #define USEM_REG_ARB_ELEMENT2 0x300028 5092 /* [RW 3] The source that is associated with arbitration element 3. Source 5093 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5094 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 5095 not be equal to register ~usem_registers_arb_element0.arb_element0 and 5096 ~usem_registers_arb_element1.arb_element1 and 5097 ~usem_registers_arb_element2.arb_element2 */ 5098 #define USEM_REG_ARB_ELEMENT3 0x30002c 5099 /* [RW 3] The source that is associated with arbitration element 4. Source 5100 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5101 sleeping thread with priority 1; 4- sleeping thread with priority 2. 5102 Could not be equal to register ~usem_registers_arb_element0.arb_element0 5103 and ~usem_registers_arb_element1.arb_element1 and 5104 ~usem_registers_arb_element2.arb_element2 and 5105 ~usem_registers_arb_element3.arb_element3 */ 5106 #define USEM_REG_ARB_ELEMENT4 0x300030 5107 #define USEM_REG_ENABLE_IN 0x3000a4 5108 #define USEM_REG_ENABLE_OUT 0x3000a8 5109 /* [RW 32] This address space contains all registers and memories that are 5110 placed in SEM_FAST block. The SEM_FAST registers are described in 5111 appendix B. In order to access the sem_fast registers the base address 5112 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 5113 #define USEM_REG_FAST_MEMORY 0x320000 5114 /* [RW 1] Disables input messages from FIC0 May be updated during run_time 5115 by the microcode */ 5116 #define USEM_REG_FIC0_DISABLE 0x300224 5117 /* [RW 1] Disables input messages from FIC1 May be updated during run_time 5118 by the microcode */ 5119 #define USEM_REG_FIC1_DISABLE 0x300234 5120 /* [RW 15] Interrupt table Read and write access to it is not possible in 5121 the middle of the work */ 5122 #define USEM_REG_INT_TABLE 0x300400 5123 /* [ST 24] Statistics register. The number of messages that entered through 5124 FIC0 */ 5125 #define USEM_REG_MSG_NUM_FIC0 0x300000 5126 /* [ST 24] Statistics register. The number of messages that entered through 5127 FIC1 */ 5128 #define USEM_REG_MSG_NUM_FIC1 0x300004 5129 /* [ST 24] Statistics register. The number of messages that were sent to 5130 FOC0 */ 5131 #define USEM_REG_MSG_NUM_FOC0 0x300008 5132 /* [ST 24] Statistics register. The number of messages that were sent to 5133 FOC1 */ 5134 #define USEM_REG_MSG_NUM_FOC1 0x30000c 5135 /* [ST 24] Statistics register. The number of messages that were sent to 5136 FOC2 */ 5137 #define USEM_REG_MSG_NUM_FOC2 0x300010 5138 /* [ST 24] Statistics register. The number of messages that were sent to 5139 FOC3 */ 5140 #define USEM_REG_MSG_NUM_FOC3 0x300014 5141 /* [RW 1] Disables input messages from the passive buffer May be updated 5142 during run_time by the microcode */ 5143 #define USEM_REG_PAS_DISABLE 0x30024c 5144 /* [WB 128] Debug only. Passive buffer memory */ 5145 #define USEM_REG_PASSIVE_BUFFER 0x302000 5146 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 5147 #define USEM_REG_PRAM 0x340000 5148 /* [R 16] Valid sleeping threads indication have bit per thread */ 5149 #define USEM_REG_SLEEP_THREADS_VALID 0x30026c 5150 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 5151 #define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0 5152 /* [RW 16] List of free threads . There is a bit per thread. */ 5153 #define USEM_REG_THREADS_LIST 0x3002e4 5154 /* [RW 3] The arbitration scheme of time_slot 0 */ 5155 #define USEM_REG_TS_0_AS 0x300038 5156 /* [RW 3] The arbitration scheme of time_slot 10 */ 5157 #define USEM_REG_TS_10_AS 0x300060 5158 /* [RW 3] The arbitration scheme of time_slot 11 */ 5159 #define USEM_REG_TS_11_AS 0x300064 5160 /* [RW 3] The arbitration scheme of time_slot 12 */ 5161 #define USEM_REG_TS_12_AS 0x300068 5162 /* [RW 3] The arbitration scheme of time_slot 13 */ 5163 #define USEM_REG_TS_13_AS 0x30006c 5164 /* [RW 3] The arbitration scheme of time_slot 14 */ 5165 #define USEM_REG_TS_14_AS 0x300070 5166 /* [RW 3] The arbitration scheme of time_slot 15 */ 5167 #define USEM_REG_TS_15_AS 0x300074 5168 /* [RW 3] The arbitration scheme of time_slot 16 */ 5169 #define USEM_REG_TS_16_AS 0x300078 5170 /* [RW 3] The arbitration scheme of time_slot 17 */ 5171 #define USEM_REG_TS_17_AS 0x30007c 5172 /* [RW 3] The arbitration scheme of time_slot 18 */ 5173 #define USEM_REG_TS_18_AS 0x300080 5174 /* [RW 3] The arbitration scheme of time_slot 1 */ 5175 #define USEM_REG_TS_1_AS 0x30003c 5176 /* [RW 3] The arbitration scheme of time_slot 2 */ 5177 #define USEM_REG_TS_2_AS 0x300040 5178 /* [RW 3] The arbitration scheme of time_slot 3 */ 5179 #define USEM_REG_TS_3_AS 0x300044 5180 /* [RW 3] The arbitration scheme of time_slot 4 */ 5181 #define USEM_REG_TS_4_AS 0x300048 5182 /* [RW 3] The arbitration scheme of time_slot 5 */ 5183 #define USEM_REG_TS_5_AS 0x30004c 5184 /* [RW 3] The arbitration scheme of time_slot 6 */ 5185 #define USEM_REG_TS_6_AS 0x300050 5186 /* [RW 3] The arbitration scheme of time_slot 7 */ 5187 #define USEM_REG_TS_7_AS 0x300054 5188 /* [RW 3] The arbitration scheme of time_slot 8 */ 5189 #define USEM_REG_TS_8_AS 0x300058 5190 /* [RW 3] The arbitration scheme of time_slot 9 */ 5191 #define USEM_REG_TS_9_AS 0x30005c 5192 /* [RW 32] Interrupt mask register #0 read/write */ 5193 #define USEM_REG_USEM_INT_MASK_0 0x300110 5194 #define USEM_REG_USEM_INT_MASK_1 0x300120 5195 /* [R 32] Interrupt register #0 read */ 5196 #define USEM_REG_USEM_INT_STS_0 0x300104 5197 #define USEM_REG_USEM_INT_STS_1 0x300114 5198 /* [RW 32] Parity mask register #0 read/write */ 5199 #define USEM_REG_USEM_PRTY_MASK_0 0x300130 5200 #define USEM_REG_USEM_PRTY_MASK_1 0x300140 5201 /* [R 32] Parity register #0 read */ 5202 #define USEM_REG_USEM_PRTY_STS_0 0x300124 5203 #define USEM_REG_USEM_PRTY_STS_1 0x300134 5204 /* [RC 32] Parity register #0 read clear */ 5205 #define USEM_REG_USEM_PRTY_STS_CLR_0 0x300128 5206 #define USEM_REG_USEM_PRTY_STS_CLR_1 0x300138 5207 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 5208 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ 5209 #define USEM_REG_VFPF_ERR_NUM 0x300380 5210 #define VFC_MEMORIES_RST_REG_CAM_RST (0x1<<0) 5211 #define VFC_MEMORIES_RST_REG_RAM_RST (0x1<<1) 5212 #define VFC_REG_MEMORIES_RST 0x1943c 5213 /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits 5214 * [12:8] of the address should be the offset within the accessed LCID 5215 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10 5216 * LCID100. The RBC address should be 13'ha64. */ 5217 #define XCM_REG_AG_CTX 0x28000 5218 /* [RW 2] The queue index for registration on Aux1 counter flag. */ 5219 #define XCM_REG_AUX1_Q 0x20134 5220 /* [RW 2] Per each decision rule the queue index to register to. */ 5221 #define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0 5222 /* [R 5] Used to read the XX protection CAM occupancy counter. */ 5223 #define XCM_REG_CAM_OCCUP 0x20244 5224 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is 5225 disregarded; valid output is deasserted; all other signals are treated as 5226 usual; if 1 - normal activity. */ 5227 #define XCM_REG_CDU_AG_RD_IFEN 0x20044 5228 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 5229 are disregarded; all other signals are treated as usual; if 1 - normal 5230 activity. */ 5231 #define XCM_REG_CDU_AG_WR_IFEN 0x20040 5232 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 5233 disregarded; valid output is deasserted; all other signals are treated as 5234 usual; if 1 - normal activity. */ 5235 #define XCM_REG_CDU_SM_RD_IFEN 0x2004c 5236 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 5237 input is disregarded; all other signals are treated as usual; if 1 - 5238 normal activity. */ 5239 #define XCM_REG_CDU_SM_WR_IFEN 0x20048 5240 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 5241 the initial credit value; read returns the current value of the credit 5242 counter. Must be initialized to 1 at start-up. */ 5243 #define XCM_REG_CFC_INIT_CRD 0x20404 5244 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for 5245 weight 8 (the most prioritised); 1 stands for weight 1(least 5246 prioritised); 2 stands for weight 2; tc. */ 5247 #define XCM_REG_CP_WEIGHT 0x200dc 5248 /* [RW 1] Input csem Interface enable. If 0 - the valid input is 5249 disregarded; acknowledge output is deasserted; all other signals are 5250 treated as usual; if 1 - normal activity. */ 5251 #define XCM_REG_CSEM_IFEN 0x20028 5252 /* [RC 1] Set at message length mismatch (relative to last indication) at 5253 the csem interface. */ 5254 #define XCM_REG_CSEM_LENGTH_MIS 0x20228 5255 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for 5256 weight 8 (the most prioritised); 1 stands for weight 1(least 5257 prioritised); 2 stands for weight 2; tc. */ 5258 #define XCM_REG_CSEM_WEIGHT 0x200c4 5259 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is 5260 disregarded; acknowledge output is deasserted; all other signals are 5261 treated as usual; if 1 - normal activity. */ 5262 #define XCM_REG_DORQ_IFEN 0x20030 5263 /* [RC 1] Set at message length mismatch (relative to last indication) at 5264 the dorq interface. */ 5265 #define XCM_REG_DORQ_LENGTH_MIS 0x20230 5266 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for 5267 weight 8 (the most prioritised); 1 stands for weight 1(least 5268 prioritised); 2 stands for weight 2; tc. */ 5269 #define XCM_REG_DORQ_WEIGHT 0x200cc 5270 /* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */ 5271 #define XCM_REG_ERR_EVNT_ID 0x200b0 5272 /* [RW 28] The CM erroneous header for QM and Timers formatting. */ 5273 #define XCM_REG_ERR_XCM_HDR 0x200ac 5274 /* [RW 8] The Event ID for Timers expiration. */ 5275 #define XCM_REG_EXPR_EVNT_ID 0x200b4 5276 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write 5277 writes the initial credit value; read returns the current value of the 5278 credit counter. Must be initialized to 64 at start-up. */ 5279 #define XCM_REG_FIC0_INIT_CRD 0x2040c 5280 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 5281 writes the initial credit value; read returns the current value of the 5282 credit counter. Must be initialized to 64 at start-up. */ 5283 #define XCM_REG_FIC1_INIT_CRD 0x20410 5284 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118 5285 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c 5286 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108 5287 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c 5288 /* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1 5289 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr; 5290 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and 5291 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */ 5292 #define XCM_REG_GR_ARB_TYPE 0x2020c 5293 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 5294 highest priority is 3. It is supposed that the Channel group is the 5295 compliment of the other 3 groups. */ 5296 #define XCM_REG_GR_LD0_PR 0x20214 5297 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 5298 highest priority is 3. It is supposed that the Channel group is the 5299 compliment of the other 3 groups. */ 5300 #define XCM_REG_GR_LD1_PR 0x20218 5301 /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is 5302 disregarded; acknowledge output is deasserted; all other signals are 5303 treated as usual; if 1 - normal activity. */ 5304 #define XCM_REG_NIG0_IFEN 0x20038 5305 /* [RC 1] Set at message length mismatch (relative to last indication) at 5306 the nig0 interface. */ 5307 #define XCM_REG_NIG0_LENGTH_MIS 0x20238 5308 /* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for 5309 weight 8 (the most prioritised); 1 stands for weight 1(least 5310 prioritised); 2 stands for weight 2; tc. */ 5311 #define XCM_REG_NIG0_WEIGHT 0x200d4 5312 /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is 5313 disregarded; acknowledge output is deasserted; all other signals are 5314 treated as usual; if 1 - normal activity. */ 5315 #define XCM_REG_NIG1_IFEN 0x2003c 5316 /* [RC 1] Set at message length mismatch (relative to last indication) at 5317 the nig1 interface. */ 5318 #define XCM_REG_NIG1_LENGTH_MIS 0x2023c 5319 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and 5320 sent to STORM; for a specific connection type. The double REG-pairs are 5321 used in order to align to STORM context row size of 128 bits. The offset 5322 of these data in the STORM context is always 0. Index _i stands for the 5323 connection type (one of 16). */ 5324 #define XCM_REG_N_SM_CTX_LD_0 0x20060 5325 #define XCM_REG_N_SM_CTX_LD_1 0x20064 5326 #define XCM_REG_N_SM_CTX_LD_2 0x20068 5327 #define XCM_REG_N_SM_CTX_LD_3 0x2006c 5328 #define XCM_REG_N_SM_CTX_LD_4 0x20070 5329 #define XCM_REG_N_SM_CTX_LD_5 0x20074 5330 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; 5331 acknowledge output is deasserted; all other signals are treated as usual; 5332 if 1 - normal activity. */ 5333 #define XCM_REG_PBF_IFEN 0x20034 5334 /* [RC 1] Set at message length mismatch (relative to last indication) at 5335 the pbf interface. */ 5336 #define XCM_REG_PBF_LENGTH_MIS 0x20234 5337 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for 5338 weight 8 (the most prioritised); 1 stands for weight 1(least 5339 prioritised); 2 stands for weight 2; tc. */ 5340 #define XCM_REG_PBF_WEIGHT 0x200d0 5341 #define XCM_REG_PHYS_QNUM3_0 0x20100 5342 #define XCM_REG_PHYS_QNUM3_1 0x20104 5343 /* [RW 8] The Event ID for Timers formatting in case of stop done. */ 5344 #define XCM_REG_STOP_EVNT_ID 0x200b8 5345 /* [RC 1] Set at message length mismatch (relative to last indication) at 5346 the STORM interface. */ 5347 #define XCM_REG_STORM_LENGTH_MIS 0x2021c 5348 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for 5349 weight 8 (the most prioritised); 1 stands for weight 1(least 5350 prioritised); 2 stands for weight 2; tc. */ 5351 #define XCM_REG_STORM_WEIGHT 0x200bc 5352 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 5353 disregarded; acknowledge output is deasserted; all other signals are 5354 treated as usual; if 1 - normal activity. */ 5355 #define XCM_REG_STORM_XCM_IFEN 0x20010 5356 /* [RW 4] Timers output initial credit. Max credit available - 15.Write 5357 writes the initial credit value; read returns the current value of the 5358 credit counter. Must be initialized to 4 at start-up. */ 5359 #define XCM_REG_TM_INIT_CRD 0x2041c 5360 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for 5361 weight 8 (the most prioritised); 1 stands for weight 1(least 5362 prioritised); 2 stands for weight 2; tc. */ 5363 #define XCM_REG_TM_WEIGHT 0x200ec 5364 /* [RW 28] The CM header for Timers expiration command. */ 5365 #define XCM_REG_TM_XCM_HDR 0x200a8 5366 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is 5367 disregarded; acknowledge output is deasserted; all other signals are 5368 treated as usual; if 1 - normal activity. */ 5369 #define XCM_REG_TM_XCM_IFEN 0x2001c 5370 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is 5371 disregarded; acknowledge output is deasserted; all other signals are 5372 treated as usual; if 1 - normal activity. */ 5373 #define XCM_REG_TSEM_IFEN 0x20024 5374 /* [RC 1] Set at message length mismatch (relative to last indication) at 5375 the tsem interface. */ 5376 #define XCM_REG_TSEM_LENGTH_MIS 0x20224 5377 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for 5378 weight 8 (the most prioritised); 1 stands for weight 1(least 5379 prioritised); 2 stands for weight 2; tc. */ 5380 #define XCM_REG_TSEM_WEIGHT 0x200c0 5381 /* [RW 2] The queue index for registration on UNA greater NXT decision rule. */ 5382 #define XCM_REG_UNA_GT_NXT_Q 0x20120 5383 /* [RW 1] Input usem Interface enable. If 0 - the valid input is 5384 disregarded; acknowledge output is deasserted; all other signals are 5385 treated as usual; if 1 - normal activity. */ 5386 #define XCM_REG_USEM_IFEN 0x2002c 5387 /* [RC 1] Message length mismatch (relative to last indication) at the usem 5388 interface. */ 5389 #define XCM_REG_USEM_LENGTH_MIS 0x2022c 5390 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for 5391 weight 8 (the most prioritised); 1 stands for weight 1(least 5392 prioritised); 2 stands for weight 2; tc. */ 5393 #define XCM_REG_USEM_WEIGHT 0x200c8 5394 #define XCM_REG_WU_DA_CNT_CMD00 0x201d4 5395 #define XCM_REG_WU_DA_CNT_CMD01 0x201d8 5396 #define XCM_REG_WU_DA_CNT_CMD10 0x201dc 5397 #define XCM_REG_WU_DA_CNT_CMD11 0x201e0 5398 #define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4 5399 #define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8 5400 #define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec 5401 #define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0 5402 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4 5403 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8 5404 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc 5405 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0 5406 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 5407 acknowledge output is deasserted; all other signals are treated as usual; 5408 if 1 - normal activity. */ 5409 #define XCM_REG_XCM_CFC_IFEN 0x20050 5410 /* [RW 14] Interrupt mask register #0 read/write */ 5411 #define XCM_REG_XCM_INT_MASK 0x202b4 5412 /* [R 14] Interrupt register #0 read */ 5413 #define XCM_REG_XCM_INT_STS 0x202a8 5414 /* [RW 30] Parity mask register #0 read/write */ 5415 #define XCM_REG_XCM_PRTY_MASK 0x202c4 5416 /* [R 30] Parity register #0 read */ 5417 #define XCM_REG_XCM_PRTY_STS 0x202b8 5418 /* [RC 30] Parity register #0 read clear */ 5419 #define XCM_REG_XCM_PRTY_STS_CLR 0x202bc 5420 5421 /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS 5422 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 5423 Is used to determine the number of the AG context REG-pairs written back; 5424 when the Reg1WbFlg isn't set. */ 5425 #define XCM_REG_XCM_REG0_SZ 0x200f4 5426 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 5427 disregarded; valid is deasserted; all other signals are treated as usual; 5428 if 1 - normal activity. */ 5429 #define XCM_REG_XCM_STORM0_IFEN 0x20004 5430 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 5431 disregarded; valid is deasserted; all other signals are treated as usual; 5432 if 1 - normal activity. */ 5433 #define XCM_REG_XCM_STORM1_IFEN 0x20008 5434 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is 5435 disregarded; acknowledge output is deasserted; all other signals are 5436 treated as usual; if 1 - normal activity. */ 5437 #define XCM_REG_XCM_TM_IFEN 0x20020 5438 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 5439 disregarded; valid is deasserted; all other signals are treated as usual; 5440 if 1 - normal activity. */ 5441 #define XCM_REG_XCM_XQM_IFEN 0x2000c 5442 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */ 5443 #define XCM_REG_XCM_XQM_USE_Q 0x200f0 5444 /* [RW 4] The value by which CFC updates the activity counter at QM bypass. */ 5445 #define XCM_REG_XQM_BYP_ACT_UPD 0x200fc 5446 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes 5447 the initial credit value; read returns the current value of the credit 5448 counter. Must be initialized to 32 at start-up. */ 5449 #define XCM_REG_XQM_INIT_CRD 0x20420 5450 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 5451 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 5452 prioritised); 2 stands for weight 2; tc. */ 5453 #define XCM_REG_XQM_P_WEIGHT 0x200e4 5454 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 5455 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 5456 prioritised); 2 stands for weight 2; tc. */ 5457 #define XCM_REG_XQM_S_WEIGHT 0x200e8 5458 /* [RW 28] The CM header value for QM request (primary). */ 5459 #define XCM_REG_XQM_XCM_HDR_P 0x200a0 5460 /* [RW 28] The CM header value for QM request (secondary). */ 5461 #define XCM_REG_XQM_XCM_HDR_S 0x200a4 5462 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 5463 acknowledge output is deasserted; all other signals are treated as usual; 5464 if 1 - normal activity. */ 5465 #define XCM_REG_XQM_XCM_IFEN 0x20014 5466 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 5467 acknowledge output is deasserted; all other signals are treated as usual; 5468 if 1 - normal activity. */ 5469 #define XCM_REG_XSDM_IFEN 0x20018 5470 /* [RC 1] Set at message length mismatch (relative to last indication) at 5471 the SDM interface. */ 5472 #define XCM_REG_XSDM_LENGTH_MIS 0x20220 5473 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for 5474 weight 8 (the most prioritised); 1 stands for weight 1(least 5475 prioritised); 2 stands for weight 2; tc. */ 5476 #define XCM_REG_XSDM_WEIGHT 0x200e0 5477 /* [RW 17] Indirect access to the descriptor table of the XX protection 5478 mechanism. The fields are: [5:0] - message length; 11:6] - message 5479 pointer; 16:12] - next pointer. */ 5480 #define XCM_REG_XX_DESCR_TABLE 0x20480 5481 #define XCM_REG_XX_DESCR_TABLE_SIZE 32 5482 /* [R 6] Used to read the XX protection Free counter. */ 5483 #define XCM_REG_XX_FREE 0x20240 5484 /* [RW 6] Initial value for the credit counter; responsible for fulfilling 5485 of the Input Stage XX protection buffer by the XX protection pending 5486 messages. Max credit available - 3.Write writes the initial credit value; 5487 read returns the current value of the credit counter. Must be initialized 5488 to 2 at start-up. */ 5489 #define XCM_REG_XX_INIT_CRD 0x20424 5490 /* [RW 6] The maximum number of pending messages; which may be stored in XX 5491 protection. ~xcm_registers_xx_free.xx_free read on read. */ 5492 #define XCM_REG_XX_MSG_NUM 0x20428 5493 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 5494 #define XCM_REG_XX_OVFL_EVNT_ID 0x20058 5495 #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS (0x1<<0) 5496 #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS (0x1<<1) 5497 #define XMAC_CTRL_REG_LINE_LOCAL_LPBK (0x1<<2) 5498 #define XMAC_CTRL_REG_RX_EN (0x1<<1) 5499 #define XMAC_CTRL_REG_SOFT_RESET (0x1<<6) 5500 #define XMAC_CTRL_REG_TX_EN (0x1<<0) 5501 #define XMAC_CTRL_REG_XLGMII_ALIGN_ENB (0x1<<7) 5502 #define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN (0x1<<18) 5503 #define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN (0x1<<17) 5504 #define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON (0x1<<1) 5505 #define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN (0x1<<0) 5506 #define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN (0x1<<3) 5507 #define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN (0x1<<4) 5508 #define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN (0x1<<5) 5509 #define XMAC_REG_CLEAR_RX_LSS_STATUS 0x60 5510 #define XMAC_REG_CTRL 0 5511 /* [RW 16] Upper 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC 5512 * packets transmitted by the MAC */ 5513 #define XMAC_REG_CTRL_SA_HI 0x2c 5514 /* [RW 32] Lower 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC 5515 * packets transmitted by the MAC */ 5516 #define XMAC_REG_CTRL_SA_LO 0x28 5517 #define XMAC_REG_EEE_CTRL 0xd8 5518 #define XMAC_REG_EEE_TIMERS_HI 0xe4 5519 #define XMAC_REG_PAUSE_CTRL 0x68 5520 #define XMAC_REG_PFC_CTRL 0x70 5521 #define XMAC_REG_PFC_CTRL_HI 0x74 5522 #define XMAC_REG_RX_LSS_CTRL 0x50 5523 #define XMAC_REG_RX_LSS_STATUS 0x58 5524 /* [RW 14] Maximum packet size in receive direction; exclusive of preamble & 5525 * CRC in strip mode */ 5526 #define XMAC_REG_RX_MAX_SIZE 0x40 5527 #define XMAC_REG_TX_CTRL 0x20 5528 #define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE (0x1<<0) 5529 #define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE (0x1<<1) 5530 /* [RW 16] Indirect access to the XX table of the XX protection mechanism. 5531 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] - 5532 header pointer. */ 5533 #define XCM_REG_XX_TABLE 0x20500 5534 /* [RW 8] The event id for aggregated interrupt 0 */ 5535 #define XSDM_REG_AGG_INT_EVENT_0 0x166038 5536 #define XSDM_REG_AGG_INT_EVENT_1 0x16603c 5537 #define XSDM_REG_AGG_INT_EVENT_10 0x166060 5538 #define XSDM_REG_AGG_INT_EVENT_11 0x166064 5539 #define XSDM_REG_AGG_INT_EVENT_12 0x166068 5540 #define XSDM_REG_AGG_INT_EVENT_13 0x16606c 5541 #define XSDM_REG_AGG_INT_EVENT_14 0x166070 5542 #define XSDM_REG_AGG_INT_EVENT_2 0x166040 5543 #define XSDM_REG_AGG_INT_EVENT_3 0x166044 5544 #define XSDM_REG_AGG_INT_EVENT_4 0x166048 5545 #define XSDM_REG_AGG_INT_EVENT_5 0x16604c 5546 #define XSDM_REG_AGG_INT_EVENT_6 0x166050 5547 #define XSDM_REG_AGG_INT_EVENT_7 0x166054 5548 #define XSDM_REG_AGG_INT_EVENT_8 0x166058 5549 #define XSDM_REG_AGG_INT_EVENT_9 0x16605c 5550 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0) 5551 or auto-mask-mode (1) */ 5552 #define XSDM_REG_AGG_INT_MODE_0 0x1661b8 5553 #define XSDM_REG_AGG_INT_MODE_1 0x1661bc 5554 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 5555 #define XSDM_REG_CFC_RSP_START_ADDR 0x166008 5556 /* [RW 16] The maximum value of the completion counter #0 */ 5557 #define XSDM_REG_CMP_COUNTER_MAX0 0x16601c 5558 /* [RW 16] The maximum value of the completion counter #1 */ 5559 #define XSDM_REG_CMP_COUNTER_MAX1 0x166020 5560 /* [RW 16] The maximum value of the completion counter #2 */ 5561 #define XSDM_REG_CMP_COUNTER_MAX2 0x166024 5562 /* [RW 16] The maximum value of the completion counter #3 */ 5563 #define XSDM_REG_CMP_COUNTER_MAX3 0x166028 5564 /* [RW 13] The start address in the internal RAM for the completion 5565 counters. */ 5566 #define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c 5567 #define XSDM_REG_ENABLE_IN1 0x166238 5568 #define XSDM_REG_ENABLE_IN2 0x16623c 5569 #define XSDM_REG_ENABLE_OUT1 0x166240 5570 #define XSDM_REG_ENABLE_OUT2 0x166244 5571 /* [RW 4] The initial number of messages that can be sent to the pxp control 5572 interface without receiving any ACK. */ 5573 #define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc 5574 /* [ST 32] The number of ACK after placement messages received */ 5575 #define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c 5576 /* [ST 32] The number of packet end messages received from the parser */ 5577 #define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274 5578 /* [ST 32] The number of requests received from the pxp async if */ 5579 #define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278 5580 /* [ST 32] The number of commands received in queue 0 */ 5581 #define XSDM_REG_NUM_OF_Q0_CMD 0x166248 5582 /* [ST 32] The number of commands received in queue 10 */ 5583 #define XSDM_REG_NUM_OF_Q10_CMD 0x16626c 5584 /* [ST 32] The number of commands received in queue 11 */ 5585 #define XSDM_REG_NUM_OF_Q11_CMD 0x166270 5586 /* [ST 32] The number of commands received in queue 1 */ 5587 #define XSDM_REG_NUM_OF_Q1_CMD 0x16624c 5588 /* [ST 32] The number of commands received in queue 3 */ 5589 #define XSDM_REG_NUM_OF_Q3_CMD 0x166250 5590 /* [ST 32] The number of commands received in queue 4 */ 5591 #define XSDM_REG_NUM_OF_Q4_CMD 0x166254 5592 /* [ST 32] The number of commands received in queue 5 */ 5593 #define XSDM_REG_NUM_OF_Q5_CMD 0x166258 5594 /* [ST 32] The number of commands received in queue 6 */ 5595 #define XSDM_REG_NUM_OF_Q6_CMD 0x16625c 5596 /* [ST 32] The number of commands received in queue 7 */ 5597 #define XSDM_REG_NUM_OF_Q7_CMD 0x166260 5598 /* [ST 32] The number of commands received in queue 8 */ 5599 #define XSDM_REG_NUM_OF_Q8_CMD 0x166264 5600 /* [ST 32] The number of commands received in queue 9 */ 5601 #define XSDM_REG_NUM_OF_Q9_CMD 0x166268 5602 /* [RW 13] The start address in the internal RAM for queue counters */ 5603 #define XSDM_REG_Q_COUNTER_START_ADDR 0x166010 5604 /* [W 17] Generate an operation after completion; bit-16 is 5605 * AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and 5606 * bits 4:0 are the T124Param[4:0] */ 5607 #define XSDM_REG_OPERATION_GEN 0x1664c4 5608 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 5609 #define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548 5610 /* [R 1] parser fifo empty in sdm_sync block */ 5611 #define XSDM_REG_SYNC_PARSER_EMPTY 0x166550 5612 /* [R 1] parser serial fifo empty in sdm_sync block */ 5613 #define XSDM_REG_SYNC_SYNC_EMPTY 0x166558 5614 /* [RW 32] Tick for timer counter. Applicable only when 5615 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */ 5616 #define XSDM_REG_TIMER_TICK 0x166000 5617 /* [RW 32] Interrupt mask register #0 read/write */ 5618 #define XSDM_REG_XSDM_INT_MASK_0 0x16629c 5619 #define XSDM_REG_XSDM_INT_MASK_1 0x1662ac 5620 /* [R 32] Interrupt register #0 read */ 5621 #define XSDM_REG_XSDM_INT_STS_0 0x166290 5622 #define XSDM_REG_XSDM_INT_STS_1 0x1662a0 5623 /* [RW 11] Parity mask register #0 read/write */ 5624 #define XSDM_REG_XSDM_PRTY_MASK 0x1662bc 5625 /* [R 11] Parity register #0 read */ 5626 #define XSDM_REG_XSDM_PRTY_STS 0x1662b0 5627 /* [RC 11] Parity register #0 read clear */ 5628 #define XSDM_REG_XSDM_PRTY_STS_CLR 0x1662b4 5629 /* [RW 5] The number of time_slots in the arbitration cycle */ 5630 #define XSEM_REG_ARB_CYCLE_SIZE 0x280034 5631 /* [RW 3] The source that is associated with arbitration element 0. Source 5632 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5633 sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 5634 #define XSEM_REG_ARB_ELEMENT0 0x280020 5635 /* [RW 3] The source that is associated with arbitration element 1. Source 5636 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5637 sleeping thread with priority 1; 4- sleeping thread with priority 2. 5638 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */ 5639 #define XSEM_REG_ARB_ELEMENT1 0x280024 5640 /* [RW 3] The source that is associated with arbitration element 2. Source 5641 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5642 sleeping thread with priority 1; 4- sleeping thread with priority 2. 5643 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 5644 and ~xsem_registers_arb_element1.arb_element1 */ 5645 #define XSEM_REG_ARB_ELEMENT2 0x280028 5646 /* [RW 3] The source that is associated with arbitration element 3. Source 5647 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5648 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 5649 not be equal to register ~xsem_registers_arb_element0.arb_element0 and 5650 ~xsem_registers_arb_element1.arb_element1 and 5651 ~xsem_registers_arb_element2.arb_element2 */ 5652 #define XSEM_REG_ARB_ELEMENT3 0x28002c 5653 /* [RW 3] The source that is associated with arbitration element 4. Source 5654 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5655 sleeping thread with priority 1; 4- sleeping thread with priority 2. 5656 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 5657 and ~xsem_registers_arb_element1.arb_element1 and 5658 ~xsem_registers_arb_element2.arb_element2 and 5659 ~xsem_registers_arb_element3.arb_element3 */ 5660 #define XSEM_REG_ARB_ELEMENT4 0x280030 5661 #define XSEM_REG_ENABLE_IN 0x2800a4 5662 #define XSEM_REG_ENABLE_OUT 0x2800a8 5663 /* [RW 32] This address space contains all registers and memories that are 5664 placed in SEM_FAST block. The SEM_FAST registers are described in 5665 appendix B. In order to access the sem_fast registers the base address 5666 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 5667 #define XSEM_REG_FAST_MEMORY 0x2a0000 5668 /* [RW 1] Disables input messages from FIC0 May be updated during run_time 5669 by the microcode */ 5670 #define XSEM_REG_FIC0_DISABLE 0x280224 5671 /* [RW 1] Disables input messages from FIC1 May be updated during run_time 5672 by the microcode */ 5673 #define XSEM_REG_FIC1_DISABLE 0x280234 5674 /* [RW 15] Interrupt table Read and write access to it is not possible in 5675 the middle of the work */ 5676 #define XSEM_REG_INT_TABLE 0x280400 5677 /* [ST 24] Statistics register. The number of messages that entered through 5678 FIC0 */ 5679 #define XSEM_REG_MSG_NUM_FIC0 0x280000 5680 /* [ST 24] Statistics register. The number of messages that entered through 5681 FIC1 */ 5682 #define XSEM_REG_MSG_NUM_FIC1 0x280004 5683 /* [ST 24] Statistics register. The number of messages that were sent to 5684 FOC0 */ 5685 #define XSEM_REG_MSG_NUM_FOC0 0x280008 5686 /* [ST 24] Statistics register. The number of messages that were sent to 5687 FOC1 */ 5688 #define XSEM_REG_MSG_NUM_FOC1 0x28000c 5689 /* [ST 24] Statistics register. The number of messages that were sent to 5690 FOC2 */ 5691 #define XSEM_REG_MSG_NUM_FOC2 0x280010 5692 /* [ST 24] Statistics register. The number of messages that were sent to 5693 FOC3 */ 5694 #define XSEM_REG_MSG_NUM_FOC3 0x280014 5695 /* [RW 1] Disables input messages from the passive buffer May be updated 5696 during run_time by the microcode */ 5697 #define XSEM_REG_PAS_DISABLE 0x28024c 5698 /* [WB 128] Debug only. Passive buffer memory */ 5699 #define XSEM_REG_PASSIVE_BUFFER 0x282000 5700 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 5701 #define XSEM_REG_PRAM 0x2c0000 5702 /* [R 16] Valid sleeping threads indication have bit per thread */ 5703 #define XSEM_REG_SLEEP_THREADS_VALID 0x28026c 5704 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 5705 #define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0 5706 /* [RW 16] List of free threads . There is a bit per thread. */ 5707 #define XSEM_REG_THREADS_LIST 0x2802e4 5708 /* [RW 3] The arbitration scheme of time_slot 0 */ 5709 #define XSEM_REG_TS_0_AS 0x280038 5710 /* [RW 3] The arbitration scheme of time_slot 10 */ 5711 #define XSEM_REG_TS_10_AS 0x280060 5712 /* [RW 3] The arbitration scheme of time_slot 11 */ 5713 #define XSEM_REG_TS_11_AS 0x280064 5714 /* [RW 3] The arbitration scheme of time_slot 12 */ 5715 #define XSEM_REG_TS_12_AS 0x280068 5716 /* [RW 3] The arbitration scheme of time_slot 13 */ 5717 #define XSEM_REG_TS_13_AS 0x28006c 5718 /* [RW 3] The arbitration scheme of time_slot 14 */ 5719 #define XSEM_REG_TS_14_AS 0x280070 5720 /* [RW 3] The arbitration scheme of time_slot 15 */ 5721 #define XSEM_REG_TS_15_AS 0x280074 5722 /* [RW 3] The arbitration scheme of time_slot 16 */ 5723 #define XSEM_REG_TS_16_AS 0x280078 5724 /* [RW 3] The arbitration scheme of time_slot 17 */ 5725 #define XSEM_REG_TS_17_AS 0x28007c 5726 /* [RW 3] The arbitration scheme of time_slot 18 */ 5727 #define XSEM_REG_TS_18_AS 0x280080 5728 /* [RW 3] The arbitration scheme of time_slot 1 */ 5729 #define XSEM_REG_TS_1_AS 0x28003c 5730 /* [RW 3] The arbitration scheme of time_slot 2 */ 5731 #define XSEM_REG_TS_2_AS 0x280040 5732 /* [RW 3] The arbitration scheme of time_slot 3 */ 5733 #define XSEM_REG_TS_3_AS 0x280044 5734 /* [RW 3] The arbitration scheme of time_slot 4 */ 5735 #define XSEM_REG_TS_4_AS 0x280048 5736 /* [RW 3] The arbitration scheme of time_slot 5 */ 5737 #define XSEM_REG_TS_5_AS 0x28004c 5738 /* [RW 3] The arbitration scheme of time_slot 6 */ 5739 #define XSEM_REG_TS_6_AS 0x280050 5740 /* [RW 3] The arbitration scheme of time_slot 7 */ 5741 #define XSEM_REG_TS_7_AS 0x280054 5742 /* [RW 3] The arbitration scheme of time_slot 8 */ 5743 #define XSEM_REG_TS_8_AS 0x280058 5744 /* [RW 3] The arbitration scheme of time_slot 9 */ 5745 #define XSEM_REG_TS_9_AS 0x28005c 5746 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 5747 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ 5748 #define XSEM_REG_VFPF_ERR_NUM 0x280380 5749 /* [RW 32] Interrupt mask register #0 read/write */ 5750 #define XSEM_REG_XSEM_INT_MASK_0 0x280110 5751 #define XSEM_REG_XSEM_INT_MASK_1 0x280120 5752 /* [R 32] Interrupt register #0 read */ 5753 #define XSEM_REG_XSEM_INT_STS_0 0x280104 5754 #define XSEM_REG_XSEM_INT_STS_1 0x280114 5755 /* [RW 32] Parity mask register #0 read/write */ 5756 #define XSEM_REG_XSEM_PRTY_MASK_0 0x280130 5757 #define XSEM_REG_XSEM_PRTY_MASK_1 0x280140 5758 /* [R 32] Parity register #0 read */ 5759 #define XSEM_REG_XSEM_PRTY_STS_0 0x280124 5760 #define XSEM_REG_XSEM_PRTY_STS_1 0x280134 5761 /* [RC 32] Parity register #0 read clear */ 5762 #define XSEM_REG_XSEM_PRTY_STS_CLR_0 0x280128 5763 #define XSEM_REG_XSEM_PRTY_STS_CLR_1 0x280138 5764 #define MCPR_ACCESS_LOCK_LOCK (1L<<31) 5765 #define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0) 5766 #define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1) 5767 #define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) 5768 #define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0) 5769 #define MCPR_NVM_COMMAND_DOIT (1L<<4) 5770 #define MCPR_NVM_COMMAND_DONE (1L<<3) 5771 #define MCPR_NVM_COMMAND_FIRST (1L<<7) 5772 #define MCPR_NVM_COMMAND_LAST (1L<<8) 5773 #define MCPR_NVM_COMMAND_WR (1L<<5) 5774 #define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9) 5775 #define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) 5776 #define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) 5777 #define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3) 5778 #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3) 5779 #define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3) 5780 #define BIGMAC_REGISTER_RX_CONTROL (0x21<<3) 5781 #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3) 5782 #define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3) 5783 #define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3) 5784 #define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3) 5785 #define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3) 5786 #define BIGMAC_REGISTER_TX_CONTROL (0x07<<3) 5787 #define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3) 5788 #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3) 5789 #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3) 5790 #define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3) 5791 #define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3) 5792 #define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3) 5793 #define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3) 5794 #define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3) 5795 #define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3) 5796 #define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3) 5797 #define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3) 5798 #define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3) 5799 #define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3) 5800 #define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3) 5801 #define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3) 5802 #define BIGMAC2_REGISTER_RX_STAT_GRPP (0x51<<3) 5803 #define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3) 5804 #define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3) 5805 #define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3) 5806 #define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3) 5807 #define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3) 5808 #define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3) 5809 #define BIGMAC2_REGISTER_TX_STAT_GTPP (0x24<<3) 5810 #define EMAC_LED_1000MB_OVERRIDE (1L<<1) 5811 #define EMAC_LED_100MB_OVERRIDE (1L<<2) 5812 #define EMAC_LED_10MB_OVERRIDE (1L<<3) 5813 #define EMAC_LED_2500MB_OVERRIDE (1L<<12) 5814 #define EMAC_LED_OVERRIDE (1L<<0) 5815 #define EMAC_LED_TRAFFIC (1L<<6) 5816 #define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26) 5817 #define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26) 5818 #define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26) 5819 #define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26) 5820 #define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26) 5821 #define EMAC_MDIO_COMM_DATA (0xffffL<<0) 5822 #define EMAC_MDIO_COMM_START_BUSY (1L<<29) 5823 #define EMAC_MDIO_MODE_AUTO_POLL (1L<<4) 5824 #define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31) 5825 #define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL<<16) 5826 #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16 5827 #define EMAC_MDIO_STATUS_10MB (1L<<1) 5828 #define EMAC_MODE_25G_MODE (1L<<5) 5829 #define EMAC_MODE_HALF_DUPLEX (1L<<1) 5830 #define EMAC_MODE_PORT_GMII (2L<<2) 5831 #define EMAC_MODE_PORT_MII (1L<<2) 5832 #define EMAC_MODE_PORT_MII_10M (3L<<2) 5833 #define EMAC_MODE_RESET (1L<<0) 5834 #define EMAC_REG_EMAC_LED 0xc 5835 #define EMAC_REG_EMAC_MAC_MATCH 0x10 5836 #define EMAC_REG_EMAC_MDIO_COMM 0xac 5837 #define EMAC_REG_EMAC_MDIO_MODE 0xb4 5838 #define EMAC_REG_EMAC_MDIO_STATUS 0xb0 5839 #define EMAC_REG_EMAC_MODE 0x0 5840 #define EMAC_REG_EMAC_RX_MODE 0xc8 5841 #define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c 5842 #define EMAC_REG_EMAC_RX_STAT_AC 0x180 5843 #define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4 5844 #define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23 5845 #define EMAC_REG_EMAC_TX_MODE 0xbc 5846 #define EMAC_REG_EMAC_TX_STAT_AC 0x280 5847 #define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22 5848 #define EMAC_REG_RX_PFC_MODE 0x320 5849 #define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L<<2) 5850 #define EMAC_REG_RX_PFC_MODE_RX_EN (1L<<1) 5851 #define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0) 5852 #define EMAC_REG_RX_PFC_PARAM 0x324 5853 #define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0 5854 #define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16 5855 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328 5856 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0) 5857 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330 5858 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0) 5859 #define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c 5860 #define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0) 5861 #define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334 5862 #define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0) 5863 #define EMAC_RX_MODE_FLOW_EN (1L<<2) 5864 #define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3) 5865 #define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) 5866 #define EMAC_RX_MODE_PROMISCUOUS (1L<<8) 5867 #define EMAC_RX_MODE_RESET (1L<<0) 5868 #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) 5869 #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) 5870 #define EMAC_TX_MODE_FLOW_EN (1L<<4) 5871 #define EMAC_TX_MODE_RESET (1L<<0) 5872 #define MISC_REGISTERS_GPIO_0 0 5873 #define MISC_REGISTERS_GPIO_1 1 5874 #define MISC_REGISTERS_GPIO_2 2 5875 #define MISC_REGISTERS_GPIO_3 3 5876 #define MISC_REGISTERS_GPIO_CLR_POS 16 5877 #define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24) 5878 #define MISC_REGISTERS_GPIO_FLOAT_POS 24 5879 #define MISC_REGISTERS_GPIO_HIGH 1 5880 #define MISC_REGISTERS_GPIO_INPUT_HI_Z 2 5881 #define MISC_REGISTERS_GPIO_INT_CLR_POS 24 5882 #define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0 5883 #define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1 5884 #define MISC_REGISTERS_GPIO_INT_SET_POS 16 5885 #define MISC_REGISTERS_GPIO_LOW 0 5886 #define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1 5887 #define MISC_REGISTERS_GPIO_OUTPUT_LOW 0 5888 #define MISC_REGISTERS_GPIO_PORT_SHIFT 4 5889 #define MISC_REGISTERS_GPIO_SET_POS 8 5890 #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588 5891 #define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0) 5892 #define MISC_REGISTERS_RESET_REG_1_RST_DORQ (0x1<<19) 5893 #define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29) 5894 #define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7) 5895 #define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1<<26) 5896 #define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27) 5897 #define MISC_REGISTERS_RESET_REG_1_SET 0x584 5898 #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598 5899 #define MISC_REGISTERS_RESET_REG_2_MSTAT0 (0x1<<24) 5900 #define MISC_REGISTERS_RESET_REG_2_MSTAT1 (0x1<<25) 5901 #define MISC_REGISTERS_RESET_REG_2_PGLC (0x1<<19) 5902 #define MISC_REGISTERS_RESET_REG_2_RST_ATC (0x1<<17) 5903 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0) 5904 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1) 5905 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2) 5906 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14) 5907 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3) 5908 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15) 5909 #define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4) 5910 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6) 5911 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8) 5912 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7) 5913 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5) 5914 #define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13) 5915 #define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11) 5916 #define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO (0x1<<13) 5917 #define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9) 5918 #define MISC_REGISTERS_RESET_REG_2_SET 0x594 5919 #define MISC_REGISTERS_RESET_REG_2_UMAC0 (0x1<<20) 5920 #define MISC_REGISTERS_RESET_REG_2_UMAC1 (0x1<<21) 5921 #define MISC_REGISTERS_RESET_REG_2_XMAC (0x1<<22) 5922 #define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT (0x1<<23) 5923 #define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8 5924 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1) 5925 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2) 5926 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3) 5927 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0) 5928 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5) 5929 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6) 5930 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7) 5931 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4) 5932 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8) 5933 #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4 5934 #define MISC_REGISTERS_SPIO_4 4 5935 #define MISC_REGISTERS_SPIO_5 5 5936 #define MISC_REGISTERS_SPIO_7 7 5937 #define MISC_REGISTERS_SPIO_CLR_POS 16 5938 #define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24) 5939 #define MISC_REGISTERS_SPIO_FLOAT_POS 24 5940 #define MISC_REGISTERS_SPIO_INPUT_HI_Z 2 5941 #define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16 5942 #define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1 5943 #define MISC_REGISTERS_SPIO_OUTPUT_LOW 0 5944 #define MISC_REGISTERS_SPIO_SET_POS 8 5945 #define MISC_SPIO_CLR_POS 16 5946 #define MISC_SPIO_FLOAT (0xffL<<24) 5947 #define MISC_SPIO_FLOAT_POS 24 5948 #define MISC_SPIO_INPUT_HI_Z 2 5949 #define MISC_SPIO_INT_OLD_SET_POS 16 5950 #define MISC_SPIO_OUTPUT_HIGH 1 5951 #define MISC_SPIO_OUTPUT_LOW 0 5952 #define MISC_SPIO_SET_POS 8 5953 #define MISC_SPIO_SPIO4 0x10 5954 #define MISC_SPIO_SPIO5 0x20 5955 #define HW_LOCK_MAX_RESOURCE_VALUE 31 5956 #define HW_LOCK_RESOURCE_DCBX_ADMIN_MIB 13 5957 #define HW_LOCK_RESOURCE_DRV_FLAGS 10 5958 #define HW_LOCK_RESOURCE_GPIO 1 5959 #define HW_LOCK_RESOURCE_MDIO 0 5960 #define HW_LOCK_RESOURCE_NVRAM 12 5961 #define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3 5962 #define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8 5963 #define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9 5964 #define HW_LOCK_RESOURCE_RECOVERY_REG 11 5965 #define HW_LOCK_RESOURCE_RESET 5 5966 #define HW_LOCK_RESOURCE_SPIO 2 5967 #define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4) 5968 #define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5) 5969 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18) 5970 #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31) 5971 #define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30) 5972 #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9) 5973 #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8) 5974 #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7) 5975 #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6) 5976 #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29) 5977 #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28) 5978 #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1) 5979 #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0) 5980 #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18) 5981 #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11) 5982 #define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10) 5983 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13) 5984 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12) 5985 #define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2) 5986 #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12) 5987 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28) 5988 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1<<31) 5989 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29) 5990 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30) 5991 #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15) 5992 #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14) 5993 #define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14) 5994 #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20) 5995 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1<<31) 5996 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30) 5997 #define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0) 5998 #define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2) 5999 #define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3) 6000 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5) 6001 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4) 6002 #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3) 6003 #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2) 6004 #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3) 6005 #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2) 6006 #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22) 6007 #define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15) 6008 #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27) 6009 #define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26) 6010 #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5) 6011 #define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4) 6012 #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25) 6013 #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24) 6014 #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29) 6015 #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28) 6016 #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23) 6017 #define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22) 6018 #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27) 6019 #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26) 6020 #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21) 6021 #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20) 6022 #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25) 6023 #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24) 6024 #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16) 6025 #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9) 6026 #define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8) 6027 #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7) 6028 #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6) 6029 #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11) 6030 #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10) 6031 6032 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (0x1<<5) 6033 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (0x1<<9) 6034 6035 #define RESERVED_GENERAL_ATTENTION_BIT_0 0 6036 6037 #define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0 6038 #define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000 6039 6040 #define RESERVED_GENERAL_ATTENTION_BIT_6 6 6041 #define RESERVED_GENERAL_ATTENTION_BIT_7 7 6042 #define RESERVED_GENERAL_ATTENTION_BIT_8 8 6043 #define RESERVED_GENERAL_ATTENTION_BIT_9 9 6044 #define RESERVED_GENERAL_ATTENTION_BIT_10 10 6045 #define RESERVED_GENERAL_ATTENTION_BIT_11 11 6046 #define RESERVED_GENERAL_ATTENTION_BIT_12 12 6047 #define RESERVED_GENERAL_ATTENTION_BIT_13 13 6048 #define RESERVED_GENERAL_ATTENTION_BIT_14 14 6049 #define RESERVED_GENERAL_ATTENTION_BIT_15 15 6050 #define RESERVED_GENERAL_ATTENTION_BIT_16 16 6051 #define RESERVED_GENERAL_ATTENTION_BIT_17 17 6052 #define RESERVED_GENERAL_ATTENTION_BIT_18 18 6053 #define RESERVED_GENERAL_ATTENTION_BIT_19 19 6054 #define RESERVED_GENERAL_ATTENTION_BIT_20 20 6055 #define RESERVED_GENERAL_ATTENTION_BIT_21 21 6056 6057 /* storm asserts attention bits */ 6058 #define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7 6059 #define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8 6060 #define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9 6061 #define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10 6062 6063 /* mcp error attention bit */ 6064 #define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11 6065 6066 /*E1H NIG status sync attention mapped to group 4-7*/ 6067 #define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12 6068 #define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13 6069 #define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14 6070 #define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15 6071 #define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16 6072 #define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17 6073 #define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18 6074 #define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19 6075 6076 6077 #define LATCHED_ATTN_RBCR 23 6078 #define LATCHED_ATTN_RBCT 24 6079 #define LATCHED_ATTN_RBCN 25 6080 #define LATCHED_ATTN_RBCU 26 6081 #define LATCHED_ATTN_RBCP 27 6082 #define LATCHED_ATTN_TIMEOUT_GRC 28 6083 #define LATCHED_ATTN_RSVD_GRC 29 6084 #define LATCHED_ATTN_ROM_PARITY_MCP 30 6085 #define LATCHED_ATTN_UM_RX_PARITY_MCP 31 6086 #define LATCHED_ATTN_UM_TX_PARITY_MCP 32 6087 #define LATCHED_ATTN_SCPAD_PARITY_MCP 33 6088 6089 #define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32) 6090 #define GENERAL_ATTEN_OFFSET(atten_name)\ 6091 (1UL << ((94 + atten_name) % 32)) 6092 /* 6093 * This file defines GRC base address for every block. 6094 * This file is included by chipsim, asm microcode and cpp microcode. 6095 * These values are used in Design.xml on regBase attribute 6096 * Use the base with the generated offsets of specific registers. 6097 */ 6098 6099 #define GRCBASE_PXPCS 0x000000 6100 #define GRCBASE_PCICONFIG 0x002000 6101 #define GRCBASE_PCIREG 0x002400 6102 #define GRCBASE_EMAC0 0x008000 6103 #define GRCBASE_EMAC1 0x008400 6104 #define GRCBASE_DBU 0x008800 6105 #define GRCBASE_MISC 0x00A000 6106 #define GRCBASE_DBG 0x00C000 6107 #define GRCBASE_NIG 0x010000 6108 #define GRCBASE_XCM 0x020000 6109 #define GRCBASE_PRS 0x040000 6110 #define GRCBASE_SRCH 0x040400 6111 #define GRCBASE_TSDM 0x042000 6112 #define GRCBASE_TCM 0x050000 6113 #define GRCBASE_BRB1 0x060000 6114 #define GRCBASE_MCP 0x080000 6115 #define GRCBASE_UPB 0x0C1000 6116 #define GRCBASE_CSDM 0x0C2000 6117 #define GRCBASE_USDM 0x0C4000 6118 #define GRCBASE_CCM 0x0D0000 6119 #define GRCBASE_UCM 0x0E0000 6120 #define GRCBASE_CDU 0x101000 6121 #define GRCBASE_DMAE 0x102000 6122 #define GRCBASE_PXP 0x103000 6123 #define GRCBASE_CFC 0x104000 6124 #define GRCBASE_HC 0x108000 6125 #define GRCBASE_PXP2 0x120000 6126 #define GRCBASE_PBF 0x140000 6127 #define GRCBASE_UMAC0 0x160000 6128 #define GRCBASE_UMAC1 0x160400 6129 #define GRCBASE_XPB 0x161000 6130 #define GRCBASE_MSTAT0 0x162000 6131 #define GRCBASE_MSTAT1 0x162800 6132 #define GRCBASE_XMAC0 0x163000 6133 #define GRCBASE_XMAC1 0x163800 6134 #define GRCBASE_TIMERS 0x164000 6135 #define GRCBASE_XSDM 0x166000 6136 #define GRCBASE_QM 0x168000 6137 #define GRCBASE_DQ 0x170000 6138 #define GRCBASE_TSEM 0x180000 6139 #define GRCBASE_CSEM 0x200000 6140 #define GRCBASE_XSEM 0x280000 6141 #define GRCBASE_USEM 0x300000 6142 #define GRCBASE_MISC_AEU GRCBASE_MISC 6143 6144 6145 /* offset of configuration space in the pci core register */ 6146 #define PCICFG_OFFSET 0x2000 6147 #define PCICFG_VENDOR_ID_OFFSET 0x00 6148 #define PCICFG_DEVICE_ID_OFFSET 0x02 6149 #define PCICFG_COMMAND_OFFSET 0x04 6150 #define PCICFG_COMMAND_IO_SPACE (1<<0) 6151 #define PCICFG_COMMAND_MEM_SPACE (1<<1) 6152 #define PCICFG_COMMAND_BUS_MASTER (1<<2) 6153 #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3) 6154 #define PCICFG_COMMAND_MWI_CYCLES (1<<4) 6155 #define PCICFG_COMMAND_VGA_SNOOP (1<<5) 6156 #define PCICFG_COMMAND_PERR_ENA (1<<6) 6157 #define PCICFG_COMMAND_STEPPING (1<<7) 6158 #define PCICFG_COMMAND_SERR_ENA (1<<8) 6159 #define PCICFG_COMMAND_FAST_B2B (1<<9) 6160 #define PCICFG_COMMAND_INT_DISABLE (1<<10) 6161 #define PCICFG_COMMAND_RESERVED (0x1f<<11) 6162 #define PCICFG_STATUS_OFFSET 0x06 6163 #define PCICFG_REVISION_ID_OFFSET 0x08 6164 #define PCICFG_REVESION_ID_MASK 0xff 6165 #define PCICFG_REVESION_ID_ERROR_VAL 0xff 6166 #define PCICFG_CACHE_LINE_SIZE 0x0c 6167 #define PCICFG_LATENCY_TIMER 0x0d 6168 #define PCICFG_BAR_1_LOW 0x10 6169 #define PCICFG_BAR_1_HIGH 0x14 6170 #define PCICFG_BAR_2_LOW 0x18 6171 #define PCICFG_BAR_2_HIGH 0x1c 6172 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c 6173 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e 6174 #define PCICFG_INT_LINE 0x3c 6175 #define PCICFG_INT_PIN 0x3d 6176 #define PCICFG_PM_CAPABILITY 0x48 6177 #define PCICFG_PM_CAPABILITY_VERSION (0x3<<16) 6178 #define PCICFG_PM_CAPABILITY_CLOCK (1<<19) 6179 #define PCICFG_PM_CAPABILITY_RESERVED (1<<20) 6180 #define PCICFG_PM_CAPABILITY_DSI (1<<21) 6181 #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22) 6182 #define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25) 6183 #define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26) 6184 #define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27) 6185 #define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28) 6186 #define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29) 6187 #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30) 6188 #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31) 6189 #define PCICFG_PM_CSR_OFFSET 0x4c 6190 #define PCICFG_PM_CSR_STATE (0x3<<0) 6191 #define PCICFG_PM_CSR_PME_ENABLE (1<<8) 6192 #define PCICFG_PM_CSR_PME_STATUS (1<<15) 6193 #define PCICFG_MSI_CAP_ID_OFFSET 0x58 6194 #define PCICFG_MSI_CONTROL_ENABLE (0x1<<16) 6195 #define PCICFG_MSI_CONTROL_MCAP (0x7<<17) 6196 #define PCICFG_MSI_CONTROL_MENA (0x7<<20) 6197 #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23) 6198 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24) 6199 #define PCICFG_GRC_ADDRESS 0x78 6200 #define PCICFG_GRC_DATA 0x80 6201 #define PCICFG_ME_REGISTER 0x98 6202 #define PCICFG_MSIX_CAP_ID_OFFSET 0xa0 6203 #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16) 6204 #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27) 6205 #define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30) 6206 #define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31) 6207 6208 #define PCICFG_DEVICE_CONTROL 0xb4 6209 #define PCICFG_DEVICE_STATUS 0xb6 6210 #define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0) 6211 #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1) 6212 #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2) 6213 #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3) 6214 #define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4) 6215 #define PCICFG_DEVICE_STATUS_NO_PEND (1<<5) 6216 #define PCICFG_LINK_CONTROL 0xbc 6217 6218 6219 #define BAR_USTRORM_INTMEM 0x400000 6220 #define BAR_CSTRORM_INTMEM 0x410000 6221 #define BAR_XSTRORM_INTMEM 0x420000 6222 #define BAR_TSTRORM_INTMEM 0x430000 6223 6224 /* for accessing the IGU in case of status block ACK */ 6225 #define BAR_IGU_INTMEM 0x440000 6226 6227 #define BAR_DOORBELL_OFFSET 0x800000 6228 6229 #define BAR_ME_REGISTER 0x450000 6230 6231 /* config_2 offset */ 6232 #define GRC_CONFIG_2_SIZE_REG 0x408 6233 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 6234 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 6235 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 6236 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 6237 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) 6238 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) 6239 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) 6240 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) 6241 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) 6242 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) 6243 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) 6244 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) 6245 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) 6246 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) 6247 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 6248 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 6249 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 6250 #define PCI_CONFIG_2_BAR1_64ENA (1L<<4) 6251 #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 6252 #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 6253 #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 6254 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 6255 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 6256 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8) 6257 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8) 6258 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8) 6259 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8) 6260 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8) 6261 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8) 6262 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8) 6263 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8) 6264 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8) 6265 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8) 6266 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8) 6267 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8) 6268 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8) 6269 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8) 6270 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8) 6271 #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16) 6272 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17) 6273 6274 /* config_3 offset */ 6275 #define GRC_CONFIG_3_SIZE_REG 0x40c 6276 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 6277 #define PCI_CONFIG_3_FORCE_PME (1L<<24) 6278 #define PCI_CONFIG_3_PME_STATUS (1L<<25) 6279 #define PCI_CONFIG_3_PME_ENABLE (1L<<26) 6280 #define PCI_CONFIG_3_PM_STATE (0x3L<<27) 6281 #define PCI_CONFIG_3_VAUX_PRESET (1L<<30) 6282 #define PCI_CONFIG_3_PCI_POWER (1L<<31) 6283 6284 #define GRC_BAR2_CONFIG 0x4e0 6285 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0) 6286 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0) 6287 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0) 6288 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0) 6289 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0) 6290 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0) 6291 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0) 6292 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0) 6293 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0) 6294 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0) 6295 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0) 6296 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0) 6297 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0) 6298 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0) 6299 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0) 6300 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0) 6301 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0) 6302 #define PCI_CONFIG_2_BAR2_64ENA (1L<<4) 6303 6304 #define PCI_PM_DATA_A 0x410 6305 #define PCI_PM_DATA_B 0x414 6306 #define PCI_ID_VAL1 0x434 6307 #define PCI_ID_VAL2 0x438 6308 6309 #define PXPCS_TL_CONTROL_5 0x814 6310 #define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/ 6311 #define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/ 6312 #define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/ 6313 #define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/ 6314 #define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/ 6315 #define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/ 6316 #define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/ 6317 #define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/ 6318 #define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/ 6319 #define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/ 6320 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/ 6321 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/ 6322 #define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/ 6323 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/ 6324 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/ 6325 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/ 6326 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/ 6327 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/ 6328 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/ 6329 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/ 6330 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/ 6331 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/ 6332 #define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/ 6333 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/ 6334 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/ 6335 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/ 6336 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/ 6337 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/ 6338 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/ 6339 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/ 6340 6341 6342 #define PXPCS_TL_FUNC345_STAT 0x854 6343 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */ 6344 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4\ 6345 (1 << 28) /* Unsupported Request Error Status in function4, if \ 6346 set, generate pcie_err_attn output when this error is seen. WC */ 6347 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC4\ 6348 (1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \ 6349 generate pcie_err_attn output when this error is seen.. WC */ 6350 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4\ 6351 (1 << 26) /* Malformed TLP Status Status in function 4, if set, \ 6352 generate pcie_err_attn output when this error is seen.. WC */ 6353 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4\ 6354 (1 << 25) /* Receiver Overflow Status Status in function 4, if \ 6355 set, generate pcie_err_attn output when this error is seen.. WC \ 6356 */ 6357 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4\ 6358 (1 << 24) /* Unexpected Completion Status Status in function 4, \ 6359 if set, generate pcie_err_attn output when this error is seen. WC \ 6360 */ 6361 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4\ 6362 (1 << 23) /* Receive UR Statusin function 4. If set, generate \ 6363 pcie_err_attn output when this error is seen. WC */ 6364 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4\ 6365 (1 << 22) /* Completer Timeout Status Status in function 4, if \ 6366 set, generate pcie_err_attn output when this error is seen. WC */ 6367 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4\ 6368 (1 << 21) /* Flow Control Protocol Error Status Status in \ 6369 function 4, if set, generate pcie_err_attn output when this error \ 6370 is seen. WC */ 6371 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4\ 6372 (1 << 20) /* Poisoned Error Status Status in function 4, if set, \ 6373 generate pcie_err_attn output when this error is seen.. WC */ 6374 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */ 6375 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3\ 6376 (1 << 18) /* Unsupported Request Error Status in function3, if \ 6377 set, generate pcie_err_attn output when this error is seen. WC */ 6378 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC3\ 6379 (1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \ 6380 generate pcie_err_attn output when this error is seen.. WC */ 6381 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3\ 6382 (1 << 16) /* Malformed TLP Status Status in function 3, if set, \ 6383 generate pcie_err_attn output when this error is seen.. WC */ 6384 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3\ 6385 (1 << 15) /* Receiver Overflow Status Status in function 3, if \ 6386 set, generate pcie_err_attn output when this error is seen.. WC \ 6387 */ 6388 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3\ 6389 (1 << 14) /* Unexpected Completion Status Status in function 3, \ 6390 if set, generate pcie_err_attn output when this error is seen. WC \ 6391 */ 6392 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3\ 6393 (1 << 13) /* Receive UR Statusin function 3. If set, generate \ 6394 pcie_err_attn output when this error is seen. WC */ 6395 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3\ 6396 (1 << 12) /* Completer Timeout Status Status in function 3, if \ 6397 set, generate pcie_err_attn output when this error is seen. WC */ 6398 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3\ 6399 (1 << 11) /* Flow Control Protocol Error Status Status in \ 6400 function 3, if set, generate pcie_err_attn output when this error \ 6401 is seen. WC */ 6402 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3\ 6403 (1 << 10) /* Poisoned Error Status Status in function 3, if set, \ 6404 generate pcie_err_attn output when this error is seen.. WC */ 6405 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */ 6406 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2\ 6407 (1 << 8) /* Unsupported Request Error Status for Function 2, if \ 6408 set, generate pcie_err_attn output when this error is seen. WC */ 6409 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC2\ 6410 (1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \ 6411 generate pcie_err_attn output when this error is seen.. WC */ 6412 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2\ 6413 (1 << 6) /* Malformed TLP Status Status for Function 2, if set, \ 6414 generate pcie_err_attn output when this error is seen.. WC */ 6415 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2\ 6416 (1 << 5) /* Receiver Overflow Status Status for Function 2, if \ 6417 set, generate pcie_err_attn output when this error is seen.. WC \ 6418 */ 6419 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2\ 6420 (1 << 4) /* Unexpected Completion Status Status for Function 2, \ 6421 if set, generate pcie_err_attn output when this error is seen. WC \ 6422 */ 6423 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2\ 6424 (1 << 3) /* Receive UR Statusfor Function 2. If set, generate \ 6425 pcie_err_attn output when this error is seen. WC */ 6426 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2\ 6427 (1 << 2) /* Completer Timeout Status Status for Function 2, if \ 6428 set, generate pcie_err_attn output when this error is seen. WC */ 6429 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2\ 6430 (1 << 1) /* Flow Control Protocol Error Status Status for \ 6431 Function 2, if set, generate pcie_err_attn output when this error \ 6432 is seen. WC */ 6433 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2\ 6434 (1 << 0) /* Poisoned Error Status Status for Function 2, if set, \ 6435 generate pcie_err_attn output when this error is seen.. WC */ 6436 6437 6438 #define PXPCS_TL_FUNC678_STAT 0x85C 6439 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */ 6440 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7\ 6441 (1 << 28) /* Unsupported Request Error Status in function7, if \ 6442 set, generate pcie_err_attn output when this error is seen. WC */ 6443 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC7\ 6444 (1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \ 6445 generate pcie_err_attn output when this error is seen.. WC */ 6446 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7\ 6447 (1 << 26) /* Malformed TLP Status Status in function 7, if set, \ 6448 generate pcie_err_attn output when this error is seen.. WC */ 6449 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7\ 6450 (1 << 25) /* Receiver Overflow Status Status in function 7, if \ 6451 set, generate pcie_err_attn output when this error is seen.. WC \ 6452 */ 6453 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7\ 6454 (1 << 24) /* Unexpected Completion Status Status in function 7, \ 6455 if set, generate pcie_err_attn output when this error is seen. WC \ 6456 */ 6457 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7\ 6458 (1 << 23) /* Receive UR Statusin function 7. If set, generate \ 6459 pcie_err_attn output when this error is seen. WC */ 6460 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7\ 6461 (1 << 22) /* Completer Timeout Status Status in function 7, if \ 6462 set, generate pcie_err_attn output when this error is seen. WC */ 6463 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7\ 6464 (1 << 21) /* Flow Control Protocol Error Status Status in \ 6465 function 7, if set, generate pcie_err_attn output when this error \ 6466 is seen. WC */ 6467 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7\ 6468 (1 << 20) /* Poisoned Error Status Status in function 7, if set, \ 6469 generate pcie_err_attn output when this error is seen.. WC */ 6470 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */ 6471 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6\ 6472 (1 << 18) /* Unsupported Request Error Status in function6, if \ 6473 set, generate pcie_err_attn output when this error is seen. WC */ 6474 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC6\ 6475 (1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \ 6476 generate pcie_err_attn output when this error is seen.. WC */ 6477 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6\ 6478 (1 << 16) /* Malformed TLP Status Status in function 6, if set, \ 6479 generate pcie_err_attn output when this error is seen.. WC */ 6480 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6\ 6481 (1 << 15) /* Receiver Overflow Status Status in function 6, if \ 6482 set, generate pcie_err_attn output when this error is seen.. WC \ 6483 */ 6484 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6\ 6485 (1 << 14) /* Unexpected Completion Status Status in function 6, \ 6486 if set, generate pcie_err_attn output when this error is seen. WC \ 6487 */ 6488 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6\ 6489 (1 << 13) /* Receive UR Statusin function 6. If set, generate \ 6490 pcie_err_attn output when this error is seen. WC */ 6491 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6\ 6492 (1 << 12) /* Completer Timeout Status Status in function 6, if \ 6493 set, generate pcie_err_attn output when this error is seen. WC */ 6494 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6\ 6495 (1 << 11) /* Flow Control Protocol Error Status Status in \ 6496 function 6, if set, generate pcie_err_attn output when this error \ 6497 is seen. WC */ 6498 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6\ 6499 (1 << 10) /* Poisoned Error Status Status in function 6, if set, \ 6500 generate pcie_err_attn output when this error is seen.. WC */ 6501 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */ 6502 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5\ 6503 (1 << 8) /* Unsupported Request Error Status for Function 5, if \ 6504 set, generate pcie_err_attn output when this error is seen. WC */ 6505 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC5\ 6506 (1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \ 6507 generate pcie_err_attn output when this error is seen.. WC */ 6508 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5\ 6509 (1 << 6) /* Malformed TLP Status Status for Function 5, if set, \ 6510 generate pcie_err_attn output when this error is seen.. WC */ 6511 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5\ 6512 (1 << 5) /* Receiver Overflow Status Status for Function 5, if \ 6513 set, generate pcie_err_attn output when this error is seen.. WC \ 6514 */ 6515 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5\ 6516 (1 << 4) /* Unexpected Completion Status Status for Function 5, \ 6517 if set, generate pcie_err_attn output when this error is seen. WC \ 6518 */ 6519 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5\ 6520 (1 << 3) /* Receive UR Statusfor Function 5. If set, generate \ 6521 pcie_err_attn output when this error is seen. WC */ 6522 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5\ 6523 (1 << 2) /* Completer Timeout Status Status for Function 5, if \ 6524 set, generate pcie_err_attn output when this error is seen. WC */ 6525 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5\ 6526 (1 << 1) /* Flow Control Protocol Error Status Status for \ 6527 Function 5, if set, generate pcie_err_attn output when this error \ 6528 is seen. WC */ 6529 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5\ 6530 (1 << 0) /* Poisoned Error Status Status for Function 5, if set, \ 6531 generate pcie_err_attn output when this error is seen.. WC */ 6532 6533 6534 #define BAR_USTRORM_INTMEM 0x400000 6535 #define BAR_CSTRORM_INTMEM 0x410000 6536 #define BAR_XSTRORM_INTMEM 0x420000 6537 #define BAR_TSTRORM_INTMEM 0x430000 6538 6539 /* for accessing the IGU in case of status block ACK */ 6540 #define BAR_IGU_INTMEM 0x440000 6541 6542 #define BAR_DOORBELL_OFFSET 0x800000 6543 6544 #define BAR_ME_REGISTER 0x450000 6545 #define ME_REG_PF_NUM_SHIFT 0 6546 #define ME_REG_PF_NUM\ 6547 (7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */ 6548 #define ME_REG_VF_VALID (1<<8) 6549 #define ME_REG_VF_NUM_SHIFT 9 6550 #define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT) 6551 #define ME_REG_VF_ERR (0x1<<3) 6552 #define ME_REG_ABS_PF_NUM_SHIFT 16 6553 #define ME_REG_ABS_PF_NUM\ 6554 (7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */ 6555 6556 6557 #define MDIO_REG_BANK_CL73_IEEEB0 0x0 6558 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0 6559 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200 6560 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000 6561 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000 6562 6563 #define MDIO_REG_BANK_CL73_IEEEB1 0x10 6564 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00 6565 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400 6566 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800 6567 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00 6568 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00 6569 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01 6570 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000 6571 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020 6572 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040 6573 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080 6574 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03 6575 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400 6576 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800 6577 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00 6578 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00 6579 #define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04 6580 6581 #define MDIO_REG_BANK_RX0 0x80b0 6582 #define MDIO_RX0_RX_STATUS 0x10 6583 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000 6584 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000 6585 #define MDIO_RX0_RX_EQ_BOOST 0x1c 6586 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6587 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10 6588 6589 #define MDIO_REG_BANK_RX1 0x80c0 6590 #define MDIO_RX1_RX_EQ_BOOST 0x1c 6591 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6592 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10 6593 6594 #define MDIO_REG_BANK_RX2 0x80d0 6595 #define MDIO_RX2_RX_EQ_BOOST 0x1c 6596 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6597 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10 6598 6599 #define MDIO_REG_BANK_RX3 0x80e0 6600 #define MDIO_RX3_RX_EQ_BOOST 0x1c 6601 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6602 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10 6603 6604 #define MDIO_REG_BANK_RX_ALL 0x80f0 6605 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c 6606 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6607 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10 6608 6609 #define MDIO_REG_BANK_TX0 0x8060 6610 #define MDIO_TX0_TX_DRIVER 0x17 6611 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 6612 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 6613 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 6614 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 6615 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 6616 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 6617 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 6618 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 6619 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 6620 6621 #define MDIO_REG_BANK_TX1 0x8070 6622 #define MDIO_TX1_TX_DRIVER 0x17 6623 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 6624 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 6625 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 6626 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 6627 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 6628 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 6629 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 6630 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 6631 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 6632 6633 #define MDIO_REG_BANK_TX2 0x8080 6634 #define MDIO_TX2_TX_DRIVER 0x17 6635 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 6636 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 6637 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 6638 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 6639 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 6640 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 6641 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 6642 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 6643 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 6644 6645 #define MDIO_REG_BANK_TX3 0x8090 6646 #define MDIO_TX3_TX_DRIVER 0x17 6647 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 6648 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 6649 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 6650 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 6651 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 6652 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 6653 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 6654 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 6655 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 6656 6657 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000 6658 #define MDIO_BLOCK0_XGXS_CONTROL 0x10 6659 6660 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010 6661 #define MDIO_BLOCK1_LANE_CTRL0 0x15 6662 #define MDIO_BLOCK1_LANE_CTRL1 0x16 6663 #define MDIO_BLOCK1_LANE_CTRL2 0x17 6664 #define MDIO_BLOCK1_LANE_PRBS 0x19 6665 6666 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100 6667 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10 6668 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000 6669 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000 6670 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11 6671 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000 6672 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14 6673 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001 6674 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010 6675 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15 6676 6677 #define MDIO_REG_BANK_GP_STATUS 0x8120 6678 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B 6679 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001 6680 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002 6681 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004 6682 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008 6683 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010 6684 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020 6685 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040 6686 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080 6687 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00 6688 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000 6689 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100 6690 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200 6691 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300 6692 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400 6693 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500 6694 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600 6695 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700 6696 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800 6697 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900 6698 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00 6699 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00 6700 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00 6701 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00 6702 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00 6703 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00 6704 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00 6705 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00 6706 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00 6707 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900 6708 6709 6710 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130 6711 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10 6712 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000 6713 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11 6714 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1 6715 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13 6716 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1) 6717 6718 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300 6719 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10 6720 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001 6721 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002 6722 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004 6723 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008 6724 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010 6725 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020 6726 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11 6727 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001 6728 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040 6729 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14 6730 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001 6731 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002 6732 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004 6733 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018 6734 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3 6735 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018 6736 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010 6737 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008 6738 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000 6739 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15 6740 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002 6741 #define MDIO_SERDES_DIGITAL_MISC1 0x18 6742 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000 6743 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000 6744 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000 6745 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000 6746 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000 6747 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000 6748 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010 6749 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f 6750 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000 6751 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001 6752 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002 6753 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003 6754 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004 6755 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005 6756 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006 6757 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007 6758 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008 6759 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009 6760 6761 #define MDIO_REG_BANK_OVER_1G 0x8320 6762 #define MDIO_OVER_1G_DIGCTL_3_4 0x14 6763 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0 6764 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5 6765 #define MDIO_OVER_1G_UP1 0x19 6766 #define MDIO_OVER_1G_UP1_2_5G 0x0001 6767 #define MDIO_OVER_1G_UP1_5G 0x0002 6768 #define MDIO_OVER_1G_UP1_6G 0x0004 6769 #define MDIO_OVER_1G_UP1_10G 0x0010 6770 #define MDIO_OVER_1G_UP1_10GH 0x0008 6771 #define MDIO_OVER_1G_UP1_12G 0x0020 6772 #define MDIO_OVER_1G_UP1_12_5G 0x0040 6773 #define MDIO_OVER_1G_UP1_13G 0x0080 6774 #define MDIO_OVER_1G_UP1_15G 0x0100 6775 #define MDIO_OVER_1G_UP1_16G 0x0200 6776 #define MDIO_OVER_1G_UP2 0x1A 6777 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007 6778 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038 6779 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0 6780 #define MDIO_OVER_1G_UP3 0x1B 6781 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001 6782 #define MDIO_OVER_1G_LP_UP1 0x1C 6783 #define MDIO_OVER_1G_LP_UP2 0x1D 6784 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff 6785 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780 6786 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7 6787 #define MDIO_OVER_1G_LP_UP3 0x1E 6788 6789 #define MDIO_REG_BANK_REMOTE_PHY 0x8330 6790 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10 6791 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010 6792 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600 6793 6794 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350 6795 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10 6796 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001 6797 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002 6798 6799 #define MDIO_REG_BANK_CL73_USERB0 0x8370 6800 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10 6801 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002 6802 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11 6803 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100 6804 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400 6805 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12 6806 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000 6807 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000 6808 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000 6809 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14 6810 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001 6811 6812 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0 6813 #define MDIO_AER_BLOCK_AER_REG 0x1E 6814 6815 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0 6816 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10 6817 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040 6818 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000 6819 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000 6820 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040 6821 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100 6822 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200 6823 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000 6824 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000 6825 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000 6826 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11 6827 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004 6828 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020 6829 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14 6830 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020 6831 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040 6832 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180 6833 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000 6834 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080 6835 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100 6836 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180 6837 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000 6838 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15 6839 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000 6840 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000 6841 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180 6842 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000 6843 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180 6844 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040 6845 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020 6846 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then 6847 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge. 6848 Theotherbitsarereservedandshouldbezero*/ 6849 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001 6850 6851 6852 #define MDIO_PMA_DEVAD 0x1 6853 /*ieee*/ 6854 #define MDIO_PMA_REG_CTRL 0x0 6855 #define MDIO_PMA_REG_STATUS 0x1 6856 #define MDIO_PMA_REG_10G_CTRL2 0x7 6857 #define MDIO_PMA_REG_TX_DISABLE 0x0009 6858 #define MDIO_PMA_REG_RX_SD 0xa 6859 /*bcm*/ 6860 #define MDIO_PMA_REG_BCM_CTRL 0x0096 6861 #define MDIO_PMA_REG_FEC_CTRL 0x00ab 6862 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800 6863 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808 6864 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809 6865 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02 6866 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09 6867 #define MDIO_PMA_REG_MISC_CTRL 0xca0a 6868 #define MDIO_PMA_REG_GEN_CTRL 0xca10 6869 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188 6870 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a 6871 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12 6872 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13 6873 #define MDIO_PMA_REG_ROM_VER1 0xca19 6874 #define MDIO_PMA_REG_ROM_VER2 0xca1a 6875 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b 6876 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d 6877 #define MDIO_PMA_REG_PLL_CTRL 0xca1e 6878 #define MDIO_PMA_REG_MISC_CTRL0 0xca23 6879 #define MDIO_PMA_REG_LRM_MODE 0xca3f 6880 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46 6881 #define MDIO_PMA_REG_MISC_CTRL1 0xca85 6882 6883 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000 6884 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c 6885 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000 6886 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004 6887 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008 6888 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c 6889 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002 6890 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003 6891 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820 6892 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff 6893 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01 6894 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05 6895 6896 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005 6897 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007 6898 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff 6899 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02 6900 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05 6901 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808 6902 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e 6903 #define MDIO_PMA_REG_8727_PCS_GP 0xc842 6904 #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4 6905 6906 #define MDIO_AN_REG_8727_MISC_CTRL 0x8309 6907 6908 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801 6909 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820 6910 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841 6911 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08 6912 6913 #define MDIO_PMA_REG_7101_RESET 0xc000 6914 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007 6915 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009 6916 #define MDIO_PMA_REG_7101_VER1 0xc026 6917 #define MDIO_PMA_REG_7101_VER2 0xc027 6918 6919 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811 6920 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c 6921 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f 6922 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832 6923 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834 6924 #define MDIO_PMA_REG_8481_LED5_MASK 0xa838 6925 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835 6926 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b 6927 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800 6928 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11 6929 6930 6931 #define MDIO_WIS_DEVAD 0x2 6932 /*bcm*/ 6933 #define MDIO_WIS_REG_LASI_CNTL 0x9002 6934 #define MDIO_WIS_REG_LASI_STATUS 0x9005 6935 6936 #define MDIO_PCS_DEVAD 0x3 6937 #define MDIO_PCS_REG_STATUS 0x0020 6938 #define MDIO_PCS_REG_LASI_STATUS 0x9005 6939 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000 6940 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008 6941 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A 6942 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5) 6943 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A 6944 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6) 6945 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7) 6946 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2) 6947 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028 6948 6949 6950 #define MDIO_XS_DEVAD 0x4 6951 #define MDIO_XS_PLL_SEQUENCER 0x8000 6952 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a 6953 6954 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc 6955 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc 6956 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc 6957 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec 6958 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc 6959 6960 #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA 6961 6962 #define MDIO_AN_DEVAD 0x7 6963 /*ieee*/ 6964 #define MDIO_AN_REG_CTRL 0x0000 6965 #define MDIO_AN_REG_STATUS 0x0001 6966 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020 6967 #define MDIO_AN_REG_ADV_PAUSE 0x0010 6968 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400 6969 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800 6970 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00 6971 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00 6972 #define MDIO_AN_REG_ADV 0x0011 6973 #define MDIO_AN_REG_ADV2 0x0012 6974 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013 6975 #define MDIO_AN_REG_LP_AUTO_NEG2 0x0014 6976 #define MDIO_AN_REG_MASTER_STATUS 0x0021 6977 #define MDIO_AN_REG_EEE_ADV 0x003c 6978 #define MDIO_AN_REG_LP_EEE_ADV 0x003d 6979 /*bcm*/ 6980 #define MDIO_AN_REG_LINK_STATUS 0x8304 6981 #define MDIO_AN_REG_CL37_CL73 0x8370 6982 #define MDIO_AN_REG_CL37_AN 0xffe0 6983 #define MDIO_AN_REG_CL37_FC_LD 0xffe4 6984 #define MDIO_AN_REG_CL37_FC_LP 0xffe5 6985 #define MDIO_AN_REG_1000T_STATUS 0xffea 6986 6987 #define MDIO_AN_REG_8073_2_5G 0x8329 6988 #define MDIO_AN_REG_8073_BAM 0x8350 6989 6990 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020 6991 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0 6992 #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40 6993 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1 6994 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4 6995 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6 6996 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9 6997 #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0 6998 #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008 6999 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5 7000 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7 7001 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8 7002 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc 7003 7004 /* BCM84823 only */ 7005 #define MDIO_CTL_DEVAD 0x1e 7006 #define MDIO_CTL_REG_84823_MEDIA 0x401a 7007 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018 7008 /* These pins configure the BCM84823 interface to MAC after reset. */ 7009 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008 7010 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010 7011 /* These pins configure the BCM84823 interface to Line after reset. */ 7012 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060 7013 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020 7014 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040 7015 /* When this pin is active high during reset, 10GBASE-T core is power 7016 * down, When it is active low the 10GBASE-T is power up 7017 */ 7018 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080 7019 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100 7020 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000 7021 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100 7022 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000 7023 #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005 7024 #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080 7025 #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b 7026 #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f 7027 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3 7028 #define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec 7029 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080 7030 7031 /* BCM84833 only */ 7032 #define MDIO_84833_TOP_CFG_FW_REV 0x400f 7033 #define MDIO_84833_TOP_CFG_FW_EEE 0x10b1 7034 #define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81 7035 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a 7036 #define MDIO_84833_SUPER_ISOLATE 0x8000 7037 /* These are mailbox register set used by 84833. */ 7038 #define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005 7039 #define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006 7040 #define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007 7041 #define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008 7042 #define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009 7043 #define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037 7044 #define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038 7045 #define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039 7046 #define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a 7047 #define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b 7048 #define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c 7049 #define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0 7050 #define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26 7051 #define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27 7052 #define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28 7053 #define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29 7054 #define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30 7055 #define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31 7056 7057 /* Mailbox command set used by 84833. */ 7058 #define PHY84833_CMD_SET_PAIR_SWAP 0x8001 7059 #define PHY84833_CMD_GET_EEE_MODE 0x8008 7060 #define PHY84833_CMD_SET_EEE_MODE 0x8009 7061 /* Mailbox status set used by 84833. */ 7062 #define PHY84833_STATUS_CMD_RECEIVED 0x0001 7063 #define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002 7064 #define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004 7065 #define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008 7066 #define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010 7067 #define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020 7068 #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040 7069 #define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080 7070 #define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5 7071 7072 7073 /* Warpcore clause 45 addressing */ 7074 #define MDIO_WC_DEVAD 0x3 7075 #define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0 7076 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7 7077 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10 7078 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11 7079 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12 7080 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000 7081 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000 7082 #define MDIO_WC_REG_PCS_STATUS2 0x0021 7083 #define MDIO_WC_REG_PMD_KR_CONTROL 0x0096 7084 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000 7085 #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e 7086 #define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010 7087 #define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015 7088 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016 7089 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017 7090 #define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061 7091 #define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071 7092 #define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081 7093 #define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091 7094 #define MDIO_WC_REG_TX0_TX_DRIVER 0x8067 7095 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04 7096 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0 7097 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08 7098 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 7099 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c 7100 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000 7101 #define MDIO_WC_REG_TX1_TX_DRIVER 0x8077 7102 #define MDIO_WC_REG_TX2_TX_DRIVER 0x8087 7103 #define MDIO_WC_REG_TX3_TX_DRIVER 0x8097 7104 #define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9 7105 #define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9 7106 #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba 7107 #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca 7108 #define MDIO_WC_REG_RX2_PCI_CTRL 0x80da 7109 #define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea 7110 #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104 7111 #define MDIO_WC_REG_XGXS_STATUS3 0x8129 7112 #define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130 7113 #define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131 7114 #define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141 7115 #define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142 7116 #define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B 7117 #define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169 7118 #define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0 7119 #define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1 7120 #define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2 7121 #define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3 7122 #define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4 7123 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000 7124 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100 7125 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010 7126 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1 7127 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE 7128 #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0 7129 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2 7130 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0 7131 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0 7132 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1 7133 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2 7134 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3 7135 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4 7136 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4 7137 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8 7138 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc 7139 #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE 7140 #define MDIO_WC_REG_DSC_SMC 0x8213 7141 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e 7142 #define MDIO_WC_REG_TX_FIR_TAP 0x82e2 7143 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00 7144 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f 7145 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04 7146 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0 7147 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a 7148 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00 7149 #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000 7150 #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2 7151 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3 7152 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6 7153 #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7 7154 #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8 7155 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec 7156 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300 7157 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301 7158 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302 7159 #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304 7160 #define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308 7161 #define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309 7162 #define MDIO_WC_REG_DIGITAL3_UP1 0x8329 7163 #define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c 7164 #define MDIO_WC_REG_DIGITAL4_MISC3 0x833c 7165 #define MDIO_WC_REG_DIGITAL4_MISC5 0x833e 7166 #define MDIO_WC_REG_DIGITAL5_MISC6 0x8345 7167 #define MDIO_WC_REG_DIGITAL5_MISC7 0x8349 7168 #define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d 7169 #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e 7170 #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350 7171 #define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368 7172 #define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370 7173 #define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371 7174 #define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372 7175 #define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373 7176 #define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374 7177 #define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b 7178 #define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390 7179 #define MDIO_WC_REG_TX66_CONTROL 0x83b0 7180 #define MDIO_WC_REG_RX66_CONTROL 0x83c0 7181 #define MDIO_WC_REG_RX66_SCW0 0x83c2 7182 #define MDIO_WC_REG_RX66_SCW1 0x83c3 7183 #define MDIO_WC_REG_RX66_SCW2 0x83c4 7184 #define MDIO_WC_REG_RX66_SCW3 0x83c5 7185 #define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6 7186 #define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7 7187 #define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8 7188 #define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9 7189 #define MDIO_WC_REG_FX100_CTRL1 0x8400 7190 #define MDIO_WC_REG_FX100_CTRL3 0x8402 7191 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436 7192 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437 7193 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438 7194 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439 7195 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a 7196 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b 7197 #define MDIO_WC_REG_ETA_CL73_OUI1 0x8453 7198 #define MDIO_WC_REG_ETA_CL73_OUI2 0x8454 7199 #define MDIO_WC_REG_ETA_CL73_OUI3 0x8455 7200 #define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456 7201 #define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457 7202 #define MDIO_WC_REG_MICROBLK_CMD 0xffc2 7203 #define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5 7204 #define MDIO_WC_REG_MICROBLK_CMD3 0xffcc 7205 7206 #define MDIO_WC_REG_AERBLK_AER 0xffde 7207 #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0 7208 #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1 7209 7210 #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A 7211 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0 7212 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4 7213 7214 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141 7215 7216 #define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f 7217 7218 /* 54618se */ 7219 #define MDIO_REG_GPHY_PHYID_LSB 0x3 7220 #define MDIO_REG_GPHY_ID_54618SE 0x5cd5 7221 #define MDIO_REG_GPHY_CL45_ADDR_REG 0xd 7222 #define MDIO_REG_GPHY_CL45_DATA_REG 0xe 7223 #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e 7224 #define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15 7225 #define MDIO_REG_GPHY_EXP_ACCESS 0x17 7226 #define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00 7227 #define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40 7228 #define MDIO_REG_GPHY_AUX_STATUS 0x19 7229 #define MDIO_REG_INTR_STATUS 0x1a 7230 #define MDIO_REG_INTR_MASK 0x1b 7231 #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1) 7232 #define MDIO_REG_GPHY_SHADOW 0x1c 7233 #define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10) 7234 #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10) 7235 #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15) 7236 #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10) 7237 #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8) 7238 7239 #define IGU_FUNC_BASE 0x0400 7240 7241 #define IGU_ADDR_MSIX 0x0000 7242 #define IGU_ADDR_INT_ACK 0x0200 7243 #define IGU_ADDR_PROD_UPD 0x0201 7244 #define IGU_ADDR_ATTN_BITS_UPD 0x0202 7245 #define IGU_ADDR_ATTN_BITS_SET 0x0203 7246 #define IGU_ADDR_ATTN_BITS_CLR 0x0204 7247 #define IGU_ADDR_COALESCE_NOW 0x0205 7248 #define IGU_ADDR_SIMD_MASK 0x0206 7249 #define IGU_ADDR_SIMD_NOMASK 0x0207 7250 #define IGU_ADDR_MSI_CTL 0x0210 7251 #define IGU_ADDR_MSI_ADDR_LO 0x0211 7252 #define IGU_ADDR_MSI_ADDR_HI 0x0212 7253 #define IGU_ADDR_MSI_DATA 0x0213 7254 7255 #define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0 7256 #define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup 1 7257 #define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 2 7258 #define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup 3 7259 7260 #define COMMAND_REG_INT_ACK 0x0 7261 #define COMMAND_REG_PROD_UPD 0x4 7262 #define COMMAND_REG_ATTN_BITS_UPD 0x8 7263 #define COMMAND_REG_ATTN_BITS_SET 0xc 7264 #define COMMAND_REG_ATTN_BITS_CLR 0x10 7265 #define COMMAND_REG_COALESCE_NOW 0x14 7266 #define COMMAND_REG_SIMD_MASK 0x18 7267 #define COMMAND_REG_SIMD_NOMASK 0x1c 7268 7269 7270 #define IGU_MEM_BASE 0x0000 7271 7272 #define IGU_MEM_MSIX_BASE 0x0000 7273 #define IGU_MEM_MSIX_UPPER 0x007f 7274 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff 7275 7276 #define IGU_MEM_PBA_MSIX_BASE 0x0200 7277 #define IGU_MEM_PBA_MSIX_UPPER 0x0200 7278 7279 #define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201 7280 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff 7281 7282 #define IGU_CMD_INT_ACK_BASE 0x0400 7283 #define IGU_CMD_INT_ACK_UPPER\ 7284 (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1) 7285 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff 7286 7287 #define IGU_CMD_E2_PROD_UPD_BASE 0x0500 7288 #define IGU_CMD_E2_PROD_UPD_UPPER\ 7289 (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1) 7290 #define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f 7291 7292 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0 7293 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1 7294 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2 7295 7296 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3 7297 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4 7298 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5 7299 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6 7300 7301 #define IGU_REG_RESERVED_UPPER 0x05ff 7302 /* Fields of IGU PF CONFIGRATION REGISTER */ 7303 #define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */ 7304 #define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */ 7305 #define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */ 7306 #define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */ 7307 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */ 7308 #define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */ 7309 7310 /* Fields of IGU VF CONFIGRATION REGISTER */ 7311 #define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */ 7312 #define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */ 7313 #define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */ 7314 #define IGU_VF_CONF_PARENT_SHIFT 2 /* Parent PF */ 7315 #define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */ 7316 7317 7318 #define IGU_BC_DSB_NUM_SEGS 5 7319 #define IGU_BC_NDSB_NUM_SEGS 2 7320 #define IGU_NORM_DSB_NUM_SEGS 2 7321 #define IGU_NORM_NDSB_NUM_SEGS 1 7322 #define IGU_BC_BASE_DSB_PROD 128 7323 #define IGU_NORM_BASE_DSB_PROD 136 7324 7325 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \ 7326 [5:2] = 0; [1:0] = PF number) */ 7327 #define IGU_FID_ENCODE_IS_PF (0x1<<6) 7328 #define IGU_FID_ENCODE_IS_PF_SHIFT 6 7329 #define IGU_FID_VF_NUM_MASK (0x3f) 7330 #define IGU_FID_PF_NUM_MASK (0x7) 7331 7332 #define IGU_REG_MAPPING_MEMORY_VALID (1<<0) 7333 #define IGU_REG_MAPPING_MEMORY_VECTOR_MASK (0x3F<<1) 7334 #define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT 1 7335 #define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7) 7336 #define IGU_REG_MAPPING_MEMORY_FID_SHIFT 7 7337 7338 7339 #define CDU_REGION_NUMBER_XCM_AG 2 7340 #define CDU_REGION_NUMBER_UCM_AG 4 7341 7342 7343 /* String-to-compress [31:8] = CID (all 24 bits) 7344 * String-to-compress [7:4] = Region 7345 * String-to-compress [3:0] = Type 7346 */ 7347 #define CDU_VALID_DATA(_cid, _region, _type)\ 7348 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf))) 7349 #define CDU_CRC8(_cid, _region, _type)\ 7350 (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff)) 7351 #define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)\ 7352 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f)) 7353 #define CDU_RSRVD_VALUE_TYPE_B(_crc, _type)\ 7354 (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7)) 7355 #define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80) 7356 7357 /****************************************************************************** 7358 * Description: 7359 * Calculates crc 8 on a word value: polynomial 0-1-2-8 7360 * Code was translated from Verilog. 7361 * Return: 7362 *****************************************************************************/ 7363 static inline u8 calc_crc8(u32 data, u8 crc) 7364 { 7365 u8 D[32]; 7366 u8 NewCRC[8]; 7367 u8 C[8]; 7368 u8 crc_res; 7369 u8 i; 7370 7371 /* split the data into 31 bits */ 7372 for (i = 0; i < 32; i++) { 7373 D[i] = (u8)(data & 1); 7374 data = data >> 1; 7375 } 7376 7377 /* split the crc into 8 bits */ 7378 for (i = 0; i < 8; i++) { 7379 C[i] = crc & 1; 7380 crc = crc >> 1; 7381 } 7382 7383 NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^ 7384 D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^ 7385 C[6] ^ C[7]; 7386 NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^ 7387 D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^ 7388 D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ 7389 C[6]; 7390 NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^ 7391 D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ 7392 C[0] ^ C[1] ^ C[4] ^ C[5]; 7393 NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^ 7394 D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^ 7395 C[1] ^ C[2] ^ C[5] ^ C[6]; 7396 NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^ 7397 D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^ 7398 C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7]; 7399 NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^ 7400 D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^ 7401 C[3] ^ C[4] ^ C[7]; 7402 NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^ 7403 D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^ 7404 C[5]; 7405 NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^ 7406 D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^ 7407 C[6]; 7408 7409 crc_res = 0; 7410 for (i = 0; i < 8; i++) 7411 crc_res |= (NewCRC[i] << i); 7412 7413 return crc_res; 7414 } 7415 7416 7417 #endif /* BNX2X_REG_H */ 7418