1*adfc5217SJeff Kirsher /* bnx2x_reg.h: Broadcom Everest network driver. 2*adfc5217SJeff Kirsher * 3*adfc5217SJeff Kirsher * Copyright (c) 2007-2011 Broadcom Corporation 4*adfc5217SJeff Kirsher * 5*adfc5217SJeff Kirsher * This program is free software; you can redistribute it and/or modify 6*adfc5217SJeff Kirsher * it under the terms of the GNU General Public License as published by 7*adfc5217SJeff Kirsher * the Free Software Foundation. 8*adfc5217SJeff Kirsher * 9*adfc5217SJeff Kirsher * The registers description starts with the register Access type followed 10*adfc5217SJeff Kirsher * by size in bits. For example [RW 32]. The access types are: 11*adfc5217SJeff Kirsher * R - Read only 12*adfc5217SJeff Kirsher * RC - Clear on read 13*adfc5217SJeff Kirsher * RW - Read/Write 14*adfc5217SJeff Kirsher * ST - Statistics register (clear on read) 15*adfc5217SJeff Kirsher * W - Write only 16*adfc5217SJeff Kirsher * WB - Wide bus register - the size is over 32 bits and it should be 17*adfc5217SJeff Kirsher * read/write in consecutive 32 bits accesses 18*adfc5217SJeff Kirsher * WR - Write Clear (write 1 to clear the bit) 19*adfc5217SJeff Kirsher * 20*adfc5217SJeff Kirsher */ 21*adfc5217SJeff Kirsher #ifndef BNX2X_REG_H 22*adfc5217SJeff Kirsher #define BNX2X_REG_H 23*adfc5217SJeff Kirsher 24*adfc5217SJeff Kirsher #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 25*adfc5217SJeff Kirsher #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2) 26*adfc5217SJeff Kirsher #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5) 27*adfc5217SJeff Kirsher #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3) 28*adfc5217SJeff Kirsher #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4) 29*adfc5217SJeff Kirsher #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1) 30*adfc5217SJeff Kirsher /* [RW 1] Initiate the ATC array - reset all the valid bits */ 31*adfc5217SJeff Kirsher #define ATC_REG_ATC_INIT_ARRAY 0x1100b8 32*adfc5217SJeff Kirsher /* [R 1] ATC initalization done */ 33*adfc5217SJeff Kirsher #define ATC_REG_ATC_INIT_DONE 0x1100bc 34*adfc5217SJeff Kirsher /* [RC 6] Interrupt register #0 read clear */ 35*adfc5217SJeff Kirsher #define ATC_REG_ATC_INT_STS_CLR 0x1101c0 36*adfc5217SJeff Kirsher /* [RW 5] Parity mask register #0 read/write */ 37*adfc5217SJeff Kirsher #define ATC_REG_ATC_PRTY_MASK 0x1101d8 38*adfc5217SJeff Kirsher /* [RC 5] Parity register #0 read clear */ 39*adfc5217SJeff Kirsher #define ATC_REG_ATC_PRTY_STS_CLR 0x1101d0 40*adfc5217SJeff Kirsher /* [RW 19] Interrupt mask register #0 read/write */ 41*adfc5217SJeff Kirsher #define BRB1_REG_BRB1_INT_MASK 0x60128 42*adfc5217SJeff Kirsher /* [R 19] Interrupt register #0 read */ 43*adfc5217SJeff Kirsher #define BRB1_REG_BRB1_INT_STS 0x6011c 44*adfc5217SJeff Kirsher /* [RW 4] Parity mask register #0 read/write */ 45*adfc5217SJeff Kirsher #define BRB1_REG_BRB1_PRTY_MASK 0x60138 46*adfc5217SJeff Kirsher /* [R 4] Parity register #0 read */ 47*adfc5217SJeff Kirsher #define BRB1_REG_BRB1_PRTY_STS 0x6012c 48*adfc5217SJeff Kirsher /* [RC 4] Parity register #0 read clear */ 49*adfc5217SJeff Kirsher #define BRB1_REG_BRB1_PRTY_STS_CLR 0x60130 50*adfc5217SJeff Kirsher /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At 51*adfc5217SJeff Kirsher * address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address 52*adfc5217SJeff Kirsher * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning - 53*adfc5217SJeff Kirsher * following reset the first rbc access to this reg must be write; there can 54*adfc5217SJeff Kirsher * be no more rbc writes after the first one; there can be any number of rbc 55*adfc5217SJeff Kirsher * read following the first write; rbc access not following these rules will 56*adfc5217SJeff Kirsher * result in hang condition. */ 57*adfc5217SJeff Kirsher #define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200 58*adfc5217SJeff Kirsher /* [RW 10] The number of free blocks below which the full signal to class 0 59*adfc5217SJeff Kirsher * is asserted */ 60*adfc5217SJeff Kirsher #define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 0x601d0 61*adfc5217SJeff Kirsher #define BRB1_REG_FULL_0_XOFF_THRESHOLD_1 0x60230 62*adfc5217SJeff Kirsher /* [RW 11] The number of free blocks above which the full signal to class 0 63*adfc5217SJeff Kirsher * is de-asserted */ 64*adfc5217SJeff Kirsher #define BRB1_REG_FULL_0_XON_THRESHOLD_0 0x601d4 65*adfc5217SJeff Kirsher #define BRB1_REG_FULL_0_XON_THRESHOLD_1 0x60234 66*adfc5217SJeff Kirsher /* [RW 11] The number of free blocks below which the full signal to class 1 67*adfc5217SJeff Kirsher * is asserted */ 68*adfc5217SJeff Kirsher #define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 0x601d8 69*adfc5217SJeff Kirsher #define BRB1_REG_FULL_1_XOFF_THRESHOLD_1 0x60238 70*adfc5217SJeff Kirsher /* [RW 11] The number of free blocks above which the full signal to class 1 71*adfc5217SJeff Kirsher * is de-asserted */ 72*adfc5217SJeff Kirsher #define BRB1_REG_FULL_1_XON_THRESHOLD_0 0x601dc 73*adfc5217SJeff Kirsher #define BRB1_REG_FULL_1_XON_THRESHOLD_1 0x6023c 74*adfc5217SJeff Kirsher /* [RW 11] The number of free blocks below which the full signal to the LB 75*adfc5217SJeff Kirsher * port is asserted */ 76*adfc5217SJeff Kirsher #define BRB1_REG_FULL_LB_XOFF_THRESHOLD 0x601e0 77*adfc5217SJeff Kirsher /* [RW 10] The number of free blocks above which the full signal to the LB 78*adfc5217SJeff Kirsher * port is de-asserted */ 79*adfc5217SJeff Kirsher #define BRB1_REG_FULL_LB_XON_THRESHOLD 0x601e4 80*adfc5217SJeff Kirsher /* [RW 10] The number of free blocks above which the High_llfc signal to 81*adfc5217SJeff Kirsher interface #n is de-asserted. */ 82*adfc5217SJeff Kirsher #define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c 83*adfc5217SJeff Kirsher /* [RW 10] The number of free blocks below which the High_llfc signal to 84*adfc5217SJeff Kirsher interface #n is asserted. */ 85*adfc5217SJeff Kirsher #define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c 86*adfc5217SJeff Kirsher /* [RW 11] The number of blocks guarantied for the LB port */ 87*adfc5217SJeff Kirsher #define BRB1_REG_LB_GUARANTIED 0x601ec 88*adfc5217SJeff Kirsher /* [RW 11] The hysteresis on the guarantied buffer space for the Lb port 89*adfc5217SJeff Kirsher * before signaling XON. */ 90*adfc5217SJeff Kirsher #define BRB1_REG_LB_GUARANTIED_HYST 0x60264 91*adfc5217SJeff Kirsher /* [RW 24] LL RAM data. */ 92*adfc5217SJeff Kirsher #define BRB1_REG_LL_RAM 0x61000 93*adfc5217SJeff Kirsher /* [RW 10] The number of free blocks above which the Low_llfc signal to 94*adfc5217SJeff Kirsher interface #n is de-asserted. */ 95*adfc5217SJeff Kirsher #define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c 96*adfc5217SJeff Kirsher /* [RW 10] The number of free blocks below which the Low_llfc signal to 97*adfc5217SJeff Kirsher interface #n is asserted. */ 98*adfc5217SJeff Kirsher #define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c 99*adfc5217SJeff Kirsher /* [RW 11] The number of blocks guarantied for class 0 in MAC 0. The 100*adfc5217SJeff Kirsher * register is applicable only when per_class_guaranty_mode is set. */ 101*adfc5217SJeff Kirsher #define BRB1_REG_MAC_0_CLASS_0_GUARANTIED 0x60244 102*adfc5217SJeff Kirsher /* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC 103*adfc5217SJeff Kirsher * 1 before signaling XON. The register is applicable only when 104*adfc5217SJeff Kirsher * per_class_guaranty_mode is set. */ 105*adfc5217SJeff Kirsher #define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST 0x60254 106*adfc5217SJeff Kirsher /* [RW 11] The number of blocks guarantied for class 1 in MAC 0. The 107*adfc5217SJeff Kirsher * register is applicable only when per_class_guaranty_mode is set. */ 108*adfc5217SJeff Kirsher #define BRB1_REG_MAC_0_CLASS_1_GUARANTIED 0x60248 109*adfc5217SJeff Kirsher /* [RW 11] The hysteresis on the guarantied buffer space for class 1in MAC 0 110*adfc5217SJeff Kirsher * before signaling XON. The register is applicable only when 111*adfc5217SJeff Kirsher * per_class_guaranty_mode is set. */ 112*adfc5217SJeff Kirsher #define BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST 0x60258 113*adfc5217SJeff Kirsher /* [RW 11] The number of blocks guarantied for class 0in MAC1.The register 114*adfc5217SJeff Kirsher * is applicable only when per_class_guaranty_mode is set. */ 115*adfc5217SJeff Kirsher #define BRB1_REG_MAC_1_CLASS_0_GUARANTIED 0x6024c 116*adfc5217SJeff Kirsher /* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC 117*adfc5217SJeff Kirsher * 1 before signaling XON. The register is applicable only when 118*adfc5217SJeff Kirsher * per_class_guaranty_mode is set. */ 119*adfc5217SJeff Kirsher #define BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST 0x6025c 120*adfc5217SJeff Kirsher /* [RW 11] The number of blocks guarantied for class 1 in MAC 1. The 121*adfc5217SJeff Kirsher * register is applicable only when per_class_guaranty_mode is set. */ 122*adfc5217SJeff Kirsher #define BRB1_REG_MAC_1_CLASS_1_GUARANTIED 0x60250 123*adfc5217SJeff Kirsher /* [RW 11] The hysteresis on the guarantied buffer space for class 1 in MAC 124*adfc5217SJeff Kirsher * 1 before signaling XON. The register is applicable only when 125*adfc5217SJeff Kirsher * per_class_guaranty_mode is set. */ 126*adfc5217SJeff Kirsher #define BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST 0x60260 127*adfc5217SJeff Kirsher /* [RW 11] The number of blocks guarantied for the MAC port. The register is 128*adfc5217SJeff Kirsher * applicable only when per_class_guaranty_mode is reset. */ 129*adfc5217SJeff Kirsher #define BRB1_REG_MAC_GUARANTIED_0 0x601e8 130*adfc5217SJeff Kirsher #define BRB1_REG_MAC_GUARANTIED_1 0x60240 131*adfc5217SJeff Kirsher /* [R 24] The number of full blocks. */ 132*adfc5217SJeff Kirsher #define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090 133*adfc5217SJeff Kirsher /* [ST 32] The number of cycles that the write_full signal towards MAC #0 134*adfc5217SJeff Kirsher was asserted. */ 135*adfc5217SJeff Kirsher #define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8 136*adfc5217SJeff Kirsher #define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc 137*adfc5217SJeff Kirsher #define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8 138*adfc5217SJeff Kirsher /* [ST 32] The number of cycles that the pause signal towards MAC #0 was 139*adfc5217SJeff Kirsher asserted. */ 140*adfc5217SJeff Kirsher #define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8 141*adfc5217SJeff Kirsher #define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc 142*adfc5217SJeff Kirsher /* [RW 10] The number of free blocks below which the pause signal to class 0 143*adfc5217SJeff Kirsher * is asserted */ 144*adfc5217SJeff Kirsher #define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 0x601c0 145*adfc5217SJeff Kirsher #define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 0x60220 146*adfc5217SJeff Kirsher /* [RW 11] The number of free blocks above which the pause signal to class 0 147*adfc5217SJeff Kirsher * is de-asserted */ 148*adfc5217SJeff Kirsher #define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 0x601c4 149*adfc5217SJeff Kirsher #define BRB1_REG_PAUSE_0_XON_THRESHOLD_1 0x60224 150*adfc5217SJeff Kirsher /* [RW 11] The number of free blocks below which the pause signal to class 1 151*adfc5217SJeff Kirsher * is asserted */ 152*adfc5217SJeff Kirsher #define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 0x601c8 153*adfc5217SJeff Kirsher #define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 0x60228 154*adfc5217SJeff Kirsher /* [RW 11] The number of free blocks above which the pause signal to class 1 155*adfc5217SJeff Kirsher * is de-asserted */ 156*adfc5217SJeff Kirsher #define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 0x601cc 157*adfc5217SJeff Kirsher #define BRB1_REG_PAUSE_1_XON_THRESHOLD_1 0x6022c 158*adfc5217SJeff Kirsher /* [RW 10] Write client 0: De-assert pause threshold. Not Functional */ 159*adfc5217SJeff Kirsher #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078 160*adfc5217SJeff Kirsher #define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c 161*adfc5217SJeff Kirsher /* [RW 10] Write client 0: Assert pause threshold. */ 162*adfc5217SJeff Kirsher #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068 163*adfc5217SJeff Kirsher #define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c 164*adfc5217SJeff Kirsher /* [R 24] The number of full blocks occupied by port. */ 165*adfc5217SJeff Kirsher #define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094 166*adfc5217SJeff Kirsher /* [RW 1] Reset the design by software. */ 167*adfc5217SJeff Kirsher #define BRB1_REG_SOFT_RESET 0x600dc 168*adfc5217SJeff Kirsher /* [R 5] Used to read the value of the XX protection CAM occupancy counter. */ 169*adfc5217SJeff Kirsher #define CCM_REG_CAM_OCCUP 0xd0188 170*adfc5217SJeff Kirsher /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 171*adfc5217SJeff Kirsher acknowledge output is deasserted; all other signals are treated as usual; 172*adfc5217SJeff Kirsher if 1 - normal activity. */ 173*adfc5217SJeff Kirsher #define CCM_REG_CCM_CFC_IFEN 0xd003c 174*adfc5217SJeff Kirsher /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 175*adfc5217SJeff Kirsher disregarded; valid is deasserted; all other signals are treated as usual; 176*adfc5217SJeff Kirsher if 1 - normal activity. */ 177*adfc5217SJeff Kirsher #define CCM_REG_CCM_CQM_IFEN 0xd000c 178*adfc5217SJeff Kirsher /* [RW 1] If set the Q index; received from the QM is inserted to event ID. 179*adfc5217SJeff Kirsher Otherwise 0 is inserted. */ 180*adfc5217SJeff Kirsher #define CCM_REG_CCM_CQM_USE_Q 0xd00c0 181*adfc5217SJeff Kirsher /* [RW 11] Interrupt mask register #0 read/write */ 182*adfc5217SJeff Kirsher #define CCM_REG_CCM_INT_MASK 0xd01e4 183*adfc5217SJeff Kirsher /* [R 11] Interrupt register #0 read */ 184*adfc5217SJeff Kirsher #define CCM_REG_CCM_INT_STS 0xd01d8 185*adfc5217SJeff Kirsher /* [RW 27] Parity mask register #0 read/write */ 186*adfc5217SJeff Kirsher #define CCM_REG_CCM_PRTY_MASK 0xd01f4 187*adfc5217SJeff Kirsher /* [R 27] Parity register #0 read */ 188*adfc5217SJeff Kirsher #define CCM_REG_CCM_PRTY_STS 0xd01e8 189*adfc5217SJeff Kirsher /* [RC 27] Parity register #0 read clear */ 190*adfc5217SJeff Kirsher #define CCM_REG_CCM_PRTY_STS_CLR 0xd01ec 191*adfc5217SJeff Kirsher /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS 192*adfc5217SJeff Kirsher REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 193*adfc5217SJeff Kirsher Is used to determine the number of the AG context REG-pairs written back; 194*adfc5217SJeff Kirsher when the input message Reg1WbFlg isn't set. */ 195*adfc5217SJeff Kirsher #define CCM_REG_CCM_REG0_SZ 0xd00c4 196*adfc5217SJeff Kirsher /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 197*adfc5217SJeff Kirsher disregarded; valid is deasserted; all other signals are treated as usual; 198*adfc5217SJeff Kirsher if 1 - normal activity. */ 199*adfc5217SJeff Kirsher #define CCM_REG_CCM_STORM0_IFEN 0xd0004 200*adfc5217SJeff Kirsher /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 201*adfc5217SJeff Kirsher disregarded; valid is deasserted; all other signals are treated as usual; 202*adfc5217SJeff Kirsher if 1 - normal activity. */ 203*adfc5217SJeff Kirsher #define CCM_REG_CCM_STORM1_IFEN 0xd0008 204*adfc5217SJeff Kirsher /* [RW 1] CDU AG read Interface enable. If 0 - the request input is 205*adfc5217SJeff Kirsher disregarded; valid output is deasserted; all other signals are treated as 206*adfc5217SJeff Kirsher usual; if 1 - normal activity. */ 207*adfc5217SJeff Kirsher #define CCM_REG_CDU_AG_RD_IFEN 0xd0030 208*adfc5217SJeff Kirsher /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 209*adfc5217SJeff Kirsher are disregarded; all other signals are treated as usual; if 1 - normal 210*adfc5217SJeff Kirsher activity. */ 211*adfc5217SJeff Kirsher #define CCM_REG_CDU_AG_WR_IFEN 0xd002c 212*adfc5217SJeff Kirsher /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 213*adfc5217SJeff Kirsher disregarded; valid output is deasserted; all other signals are treated as 214*adfc5217SJeff Kirsher usual; if 1 - normal activity. */ 215*adfc5217SJeff Kirsher #define CCM_REG_CDU_SM_RD_IFEN 0xd0038 216*adfc5217SJeff Kirsher /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 217*adfc5217SJeff Kirsher input is disregarded; all other signals are treated as usual; if 1 - 218*adfc5217SJeff Kirsher normal activity. */ 219*adfc5217SJeff Kirsher #define CCM_REG_CDU_SM_WR_IFEN 0xd0034 220*adfc5217SJeff Kirsher /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 221*adfc5217SJeff Kirsher the initial credit value; read returns the current value of the credit 222*adfc5217SJeff Kirsher counter. Must be initialized to 1 at start-up. */ 223*adfc5217SJeff Kirsher #define CCM_REG_CFC_INIT_CRD 0xd0204 224*adfc5217SJeff Kirsher /* [RW 2] Auxiliary counter flag Q number 1. */ 225*adfc5217SJeff Kirsher #define CCM_REG_CNT_AUX1_Q 0xd00c8 226*adfc5217SJeff Kirsher /* [RW 2] Auxiliary counter flag Q number 2. */ 227*adfc5217SJeff Kirsher #define CCM_REG_CNT_AUX2_Q 0xd00cc 228*adfc5217SJeff Kirsher /* [RW 28] The CM header value for QM request (primary). */ 229*adfc5217SJeff Kirsher #define CCM_REG_CQM_CCM_HDR_P 0xd008c 230*adfc5217SJeff Kirsher /* [RW 28] The CM header value for QM request (secondary). */ 231*adfc5217SJeff Kirsher #define CCM_REG_CQM_CCM_HDR_S 0xd0090 232*adfc5217SJeff Kirsher /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 233*adfc5217SJeff Kirsher acknowledge output is deasserted; all other signals are treated as usual; 234*adfc5217SJeff Kirsher if 1 - normal activity. */ 235*adfc5217SJeff Kirsher #define CCM_REG_CQM_CCM_IFEN 0xd0014 236*adfc5217SJeff Kirsher /* [RW 6] QM output initial credit. Max credit available - 32. Write writes 237*adfc5217SJeff Kirsher the initial credit value; read returns the current value of the credit 238*adfc5217SJeff Kirsher counter. Must be initialized to 32 at start-up. */ 239*adfc5217SJeff Kirsher #define CCM_REG_CQM_INIT_CRD 0xd020c 240*adfc5217SJeff Kirsher /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 241*adfc5217SJeff Kirsher stands for weight 8 (the most prioritised); 1 stands for weight 1(least 242*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 243*adfc5217SJeff Kirsher #define CCM_REG_CQM_P_WEIGHT 0xd00b8 244*adfc5217SJeff Kirsher /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 245*adfc5217SJeff Kirsher stands for weight 8 (the most prioritised); 1 stands for weight 1(least 246*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 247*adfc5217SJeff Kirsher #define CCM_REG_CQM_S_WEIGHT 0xd00bc 248*adfc5217SJeff Kirsher /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 249*adfc5217SJeff Kirsher acknowledge output is deasserted; all other signals are treated as usual; 250*adfc5217SJeff Kirsher if 1 - normal activity. */ 251*adfc5217SJeff Kirsher #define CCM_REG_CSDM_IFEN 0xd0018 252*adfc5217SJeff Kirsher /* [RC 1] Set when the message length mismatch (relative to last indication) 253*adfc5217SJeff Kirsher at the SDM interface is detected. */ 254*adfc5217SJeff Kirsher #define CCM_REG_CSDM_LENGTH_MIS 0xd0170 255*adfc5217SJeff Kirsher /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for 256*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 257*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 258*adfc5217SJeff Kirsher #define CCM_REG_CSDM_WEIGHT 0xd00b4 259*adfc5217SJeff Kirsher /* [RW 28] The CM header for QM formatting in case of an error in the QM 260*adfc5217SJeff Kirsher inputs. */ 261*adfc5217SJeff Kirsher #define CCM_REG_ERR_CCM_HDR 0xd0094 262*adfc5217SJeff Kirsher /* [RW 8] The Event ID in case the input message ErrorFlg is set. */ 263*adfc5217SJeff Kirsher #define CCM_REG_ERR_EVNT_ID 0xd0098 264*adfc5217SJeff Kirsher /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write 265*adfc5217SJeff Kirsher writes the initial credit value; read returns the current value of the 266*adfc5217SJeff Kirsher credit counter. Must be initialized to 64 at start-up. */ 267*adfc5217SJeff Kirsher #define CCM_REG_FIC0_INIT_CRD 0xd0210 268*adfc5217SJeff Kirsher /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 269*adfc5217SJeff Kirsher writes the initial credit value; read returns the current value of the 270*adfc5217SJeff Kirsher credit counter. Must be initialized to 64 at start-up. */ 271*adfc5217SJeff Kirsher #define CCM_REG_FIC1_INIT_CRD 0xd0214 272*adfc5217SJeff Kirsher /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 273*adfc5217SJeff Kirsher - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr; 274*adfc5217SJeff Kirsher ~ccm_registers_gr_ld0_pr.gr_ld0_pr and 275*adfc5217SJeff Kirsher ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and 276*adfc5217SJeff Kirsher outputs to STORM: aggregation; load FIC0; load FIC1 and store. */ 277*adfc5217SJeff Kirsher #define CCM_REG_GR_ARB_TYPE 0xd015c 278*adfc5217SJeff Kirsher /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 279*adfc5217SJeff Kirsher highest priority is 3. It is supposed; that the Store channel priority is 280*adfc5217SJeff Kirsher the compliment to 4 of the rest priorities - Aggregation channel; Load 281*adfc5217SJeff Kirsher (FIC0) channel and Load (FIC1). */ 282*adfc5217SJeff Kirsher #define CCM_REG_GR_LD0_PR 0xd0164 283*adfc5217SJeff Kirsher /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 284*adfc5217SJeff Kirsher highest priority is 3. It is supposed; that the Store channel priority is 285*adfc5217SJeff Kirsher the compliment to 4 of the rest priorities - Aggregation channel; Load 286*adfc5217SJeff Kirsher (FIC0) channel and Load (FIC1). */ 287*adfc5217SJeff Kirsher #define CCM_REG_GR_LD1_PR 0xd0168 288*adfc5217SJeff Kirsher /* [RW 2] General flags index. */ 289*adfc5217SJeff Kirsher #define CCM_REG_INV_DONE_Q 0xd0108 290*adfc5217SJeff Kirsher /* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM 291*adfc5217SJeff Kirsher context and sent to STORM; for a specific connection type. The double 292*adfc5217SJeff Kirsher REG-pairs are used in order to align to STORM context row size of 128 293*adfc5217SJeff Kirsher bits. The offset of these data in the STORM context is always 0. Index 294*adfc5217SJeff Kirsher _(0..15) stands for the connection type (one of 16). */ 295*adfc5217SJeff Kirsher #define CCM_REG_N_SM_CTX_LD_0 0xd004c 296*adfc5217SJeff Kirsher #define CCM_REG_N_SM_CTX_LD_1 0xd0050 297*adfc5217SJeff Kirsher #define CCM_REG_N_SM_CTX_LD_2 0xd0054 298*adfc5217SJeff Kirsher #define CCM_REG_N_SM_CTX_LD_3 0xd0058 299*adfc5217SJeff Kirsher #define CCM_REG_N_SM_CTX_LD_4 0xd005c 300*adfc5217SJeff Kirsher /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; 301*adfc5217SJeff Kirsher acknowledge output is deasserted; all other signals are treated as usual; 302*adfc5217SJeff Kirsher if 1 - normal activity. */ 303*adfc5217SJeff Kirsher #define CCM_REG_PBF_IFEN 0xd0028 304*adfc5217SJeff Kirsher /* [RC 1] Set when the message length mismatch (relative to last indication) 305*adfc5217SJeff Kirsher at the pbf interface is detected. */ 306*adfc5217SJeff Kirsher #define CCM_REG_PBF_LENGTH_MIS 0xd0180 307*adfc5217SJeff Kirsher /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for 308*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 309*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 310*adfc5217SJeff Kirsher #define CCM_REG_PBF_WEIGHT 0xd00ac 311*adfc5217SJeff Kirsher #define CCM_REG_PHYS_QNUM1_0 0xd0134 312*adfc5217SJeff Kirsher #define CCM_REG_PHYS_QNUM1_1 0xd0138 313*adfc5217SJeff Kirsher #define CCM_REG_PHYS_QNUM2_0 0xd013c 314*adfc5217SJeff Kirsher #define CCM_REG_PHYS_QNUM2_1 0xd0140 315*adfc5217SJeff Kirsher #define CCM_REG_PHYS_QNUM3_0 0xd0144 316*adfc5217SJeff Kirsher #define CCM_REG_PHYS_QNUM3_1 0xd0148 317*adfc5217SJeff Kirsher #define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114 318*adfc5217SJeff Kirsher #define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118 319*adfc5217SJeff Kirsher #define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c 320*adfc5217SJeff Kirsher #define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120 321*adfc5217SJeff Kirsher #define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124 322*adfc5217SJeff Kirsher #define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128 323*adfc5217SJeff Kirsher #define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c 324*adfc5217SJeff Kirsher #define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130 325*adfc5217SJeff Kirsher /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 326*adfc5217SJeff Kirsher disregarded; acknowledge output is deasserted; all other signals are 327*adfc5217SJeff Kirsher treated as usual; if 1 - normal activity. */ 328*adfc5217SJeff Kirsher #define CCM_REG_STORM_CCM_IFEN 0xd0010 329*adfc5217SJeff Kirsher /* [RC 1] Set when the message length mismatch (relative to last indication) 330*adfc5217SJeff Kirsher at the STORM interface is detected. */ 331*adfc5217SJeff Kirsher #define CCM_REG_STORM_LENGTH_MIS 0xd016c 332*adfc5217SJeff Kirsher /* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin) 333*adfc5217SJeff Kirsher mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for 334*adfc5217SJeff Kirsher weight 1(least prioritised); 2 stands for weight 2 (more prioritised); 335*adfc5217SJeff Kirsher tc. */ 336*adfc5217SJeff Kirsher #define CCM_REG_STORM_WEIGHT 0xd009c 337*adfc5217SJeff Kirsher /* [RW 1] Input tsem Interface enable. If 0 - the valid input is 338*adfc5217SJeff Kirsher disregarded; acknowledge output is deasserted; all other signals are 339*adfc5217SJeff Kirsher treated as usual; if 1 - normal activity. */ 340*adfc5217SJeff Kirsher #define CCM_REG_TSEM_IFEN 0xd001c 341*adfc5217SJeff Kirsher /* [RC 1] Set when the message length mismatch (relative to last indication) 342*adfc5217SJeff Kirsher at the tsem interface is detected. */ 343*adfc5217SJeff Kirsher #define CCM_REG_TSEM_LENGTH_MIS 0xd0174 344*adfc5217SJeff Kirsher /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for 345*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 346*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 347*adfc5217SJeff Kirsher #define CCM_REG_TSEM_WEIGHT 0xd00a0 348*adfc5217SJeff Kirsher /* [RW 1] Input usem Interface enable. If 0 - the valid input is 349*adfc5217SJeff Kirsher disregarded; acknowledge output is deasserted; all other signals are 350*adfc5217SJeff Kirsher treated as usual; if 1 - normal activity. */ 351*adfc5217SJeff Kirsher #define CCM_REG_USEM_IFEN 0xd0024 352*adfc5217SJeff Kirsher /* [RC 1] Set when message length mismatch (relative to last indication) at 353*adfc5217SJeff Kirsher the usem interface is detected. */ 354*adfc5217SJeff Kirsher #define CCM_REG_USEM_LENGTH_MIS 0xd017c 355*adfc5217SJeff Kirsher /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for 356*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 357*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 358*adfc5217SJeff Kirsher #define CCM_REG_USEM_WEIGHT 0xd00a8 359*adfc5217SJeff Kirsher /* [RW 1] Input xsem Interface enable. If 0 - the valid input is 360*adfc5217SJeff Kirsher disregarded; acknowledge output is deasserted; all other signals are 361*adfc5217SJeff Kirsher treated as usual; if 1 - normal activity. */ 362*adfc5217SJeff Kirsher #define CCM_REG_XSEM_IFEN 0xd0020 363*adfc5217SJeff Kirsher /* [RC 1] Set when the message length mismatch (relative to last indication) 364*adfc5217SJeff Kirsher at the xsem interface is detected. */ 365*adfc5217SJeff Kirsher #define CCM_REG_XSEM_LENGTH_MIS 0xd0178 366*adfc5217SJeff Kirsher /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for 367*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 368*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 369*adfc5217SJeff Kirsher #define CCM_REG_XSEM_WEIGHT 0xd00a4 370*adfc5217SJeff Kirsher /* [RW 19] Indirect access to the descriptor table of the XX protection 371*adfc5217SJeff Kirsher mechanism. The fields are: [5:0] - message length; [12:6] - message 372*adfc5217SJeff Kirsher pointer; 18:13] - next pointer. */ 373*adfc5217SJeff Kirsher #define CCM_REG_XX_DESCR_TABLE 0xd0300 374*adfc5217SJeff Kirsher #define CCM_REG_XX_DESCR_TABLE_SIZE 24 375*adfc5217SJeff Kirsher /* [R 7] Used to read the value of XX protection Free counter. */ 376*adfc5217SJeff Kirsher #define CCM_REG_XX_FREE 0xd0184 377*adfc5217SJeff Kirsher /* [RW 6] Initial value for the credit counter; responsible for fulfilling 378*adfc5217SJeff Kirsher of the Input Stage XX protection buffer by the XX protection pending 379*adfc5217SJeff Kirsher messages. Max credit available - 127. Write writes the initial credit 380*adfc5217SJeff Kirsher value; read returns the current value of the credit counter. Must be 381*adfc5217SJeff Kirsher initialized to maximum XX protected message size - 2 at start-up. */ 382*adfc5217SJeff Kirsher #define CCM_REG_XX_INIT_CRD 0xd0220 383*adfc5217SJeff Kirsher /* [RW 7] The maximum number of pending messages; which may be stored in XX 384*adfc5217SJeff Kirsher protection. At read the ~ccm_registers_xx_free.xx_free counter is read. 385*adfc5217SJeff Kirsher At write comprises the start value of the ~ccm_registers_xx_free.xx_free 386*adfc5217SJeff Kirsher counter. */ 387*adfc5217SJeff Kirsher #define CCM_REG_XX_MSG_NUM 0xd0224 388*adfc5217SJeff Kirsher /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 389*adfc5217SJeff Kirsher #define CCM_REG_XX_OVFL_EVNT_ID 0xd0044 390*adfc5217SJeff Kirsher /* [RW 18] Indirect access to the XX table of the XX protection mechanism. 391*adfc5217SJeff Kirsher The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] - 392*adfc5217SJeff Kirsher header pointer. */ 393*adfc5217SJeff Kirsher #define CCM_REG_XX_TABLE 0xd0280 394*adfc5217SJeff Kirsher #define CDU_REG_CDU_CHK_MASK0 0x101000 395*adfc5217SJeff Kirsher #define CDU_REG_CDU_CHK_MASK1 0x101004 396*adfc5217SJeff Kirsher #define CDU_REG_CDU_CONTROL0 0x101008 397*adfc5217SJeff Kirsher #define CDU_REG_CDU_DEBUG 0x101010 398*adfc5217SJeff Kirsher #define CDU_REG_CDU_GLOBAL_PARAMS 0x101020 399*adfc5217SJeff Kirsher /* [RW 7] Interrupt mask register #0 read/write */ 400*adfc5217SJeff Kirsher #define CDU_REG_CDU_INT_MASK 0x10103c 401*adfc5217SJeff Kirsher /* [R 7] Interrupt register #0 read */ 402*adfc5217SJeff Kirsher #define CDU_REG_CDU_INT_STS 0x101030 403*adfc5217SJeff Kirsher /* [RW 5] Parity mask register #0 read/write */ 404*adfc5217SJeff Kirsher #define CDU_REG_CDU_PRTY_MASK 0x10104c 405*adfc5217SJeff Kirsher /* [R 5] Parity register #0 read */ 406*adfc5217SJeff Kirsher #define CDU_REG_CDU_PRTY_STS 0x101040 407*adfc5217SJeff Kirsher /* [RC 5] Parity register #0 read clear */ 408*adfc5217SJeff Kirsher #define CDU_REG_CDU_PRTY_STS_CLR 0x101044 409*adfc5217SJeff Kirsher /* [RC 32] logging of error data in case of a CDU load error: 410*adfc5217SJeff Kirsher {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error; 411*adfc5217SJeff Kirsher ype_error; ctual_active; ctual_compressed_context}; */ 412*adfc5217SJeff Kirsher #define CDU_REG_ERROR_DATA 0x101014 413*adfc5217SJeff Kirsher /* [WB 216] L1TT ram access. each entry has the following format : 414*adfc5217SJeff Kirsher {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0]; 415*adfc5217SJeff Kirsher ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */ 416*adfc5217SJeff Kirsher #define CDU_REG_L1TT 0x101800 417*adfc5217SJeff Kirsher /* [WB 24] MATT ram access. each entry has the following 418*adfc5217SJeff Kirsher format:{RegionLength[11:0]; egionOffset[11:0]} */ 419*adfc5217SJeff Kirsher #define CDU_REG_MATT 0x101100 420*adfc5217SJeff Kirsher /* [RW 1] when this bit is set the CDU operates in e1hmf mode */ 421*adfc5217SJeff Kirsher #define CDU_REG_MF_MODE 0x101050 422*adfc5217SJeff Kirsher /* [R 1] indication the initializing the activity counter by the hardware 423*adfc5217SJeff Kirsher was done. */ 424*adfc5217SJeff Kirsher #define CFC_REG_AC_INIT_DONE 0x104078 425*adfc5217SJeff Kirsher /* [RW 13] activity counter ram access */ 426*adfc5217SJeff Kirsher #define CFC_REG_ACTIVITY_COUNTER 0x104400 427*adfc5217SJeff Kirsher #define CFC_REG_ACTIVITY_COUNTER_SIZE 256 428*adfc5217SJeff Kirsher /* [R 1] indication the initializing the cams by the hardware was done. */ 429*adfc5217SJeff Kirsher #define CFC_REG_CAM_INIT_DONE 0x10407c 430*adfc5217SJeff Kirsher /* [RW 2] Interrupt mask register #0 read/write */ 431*adfc5217SJeff Kirsher #define CFC_REG_CFC_INT_MASK 0x104108 432*adfc5217SJeff Kirsher /* [R 2] Interrupt register #0 read */ 433*adfc5217SJeff Kirsher #define CFC_REG_CFC_INT_STS 0x1040fc 434*adfc5217SJeff Kirsher /* [RC 2] Interrupt register #0 read clear */ 435*adfc5217SJeff Kirsher #define CFC_REG_CFC_INT_STS_CLR 0x104100 436*adfc5217SJeff Kirsher /* [RW 4] Parity mask register #0 read/write */ 437*adfc5217SJeff Kirsher #define CFC_REG_CFC_PRTY_MASK 0x104118 438*adfc5217SJeff Kirsher /* [R 4] Parity register #0 read */ 439*adfc5217SJeff Kirsher #define CFC_REG_CFC_PRTY_STS 0x10410c 440*adfc5217SJeff Kirsher /* [RC 4] Parity register #0 read clear */ 441*adfc5217SJeff Kirsher #define CFC_REG_CFC_PRTY_STS_CLR 0x104110 442*adfc5217SJeff Kirsher /* [RW 21] CID cam access (21:1 - Data; alid - 0) */ 443*adfc5217SJeff Kirsher #define CFC_REG_CID_CAM 0x104800 444*adfc5217SJeff Kirsher #define CFC_REG_CONTROL0 0x104028 445*adfc5217SJeff Kirsher #define CFC_REG_DEBUG0 0x104050 446*adfc5217SJeff Kirsher /* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error 447*adfc5217SJeff Kirsher vector) whether the cfc should be disabled upon it */ 448*adfc5217SJeff Kirsher #define CFC_REG_DISABLE_ON_ERROR 0x104044 449*adfc5217SJeff Kirsher /* [RC 14] CFC error vector. when the CFC detects an internal error it will 450*adfc5217SJeff Kirsher set one of these bits. the bit description can be found in CFC 451*adfc5217SJeff Kirsher specifications */ 452*adfc5217SJeff Kirsher #define CFC_REG_ERROR_VECTOR 0x10403c 453*adfc5217SJeff Kirsher /* [WB 93] LCID info ram access */ 454*adfc5217SJeff Kirsher #define CFC_REG_INFO_RAM 0x105000 455*adfc5217SJeff Kirsher #define CFC_REG_INFO_RAM_SIZE 1024 456*adfc5217SJeff Kirsher #define CFC_REG_INIT_REG 0x10404c 457*adfc5217SJeff Kirsher #define CFC_REG_INTERFACES 0x104058 458*adfc5217SJeff Kirsher /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this 459*adfc5217SJeff Kirsher field allows changing the priorities of the weighted-round-robin arbiter 460*adfc5217SJeff Kirsher which selects which CFC load client should be served next */ 461*adfc5217SJeff Kirsher #define CFC_REG_LCREQ_WEIGHTS 0x104084 462*adfc5217SJeff Kirsher /* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */ 463*adfc5217SJeff Kirsher #define CFC_REG_LINK_LIST 0x104c00 464*adfc5217SJeff Kirsher #define CFC_REG_LINK_LIST_SIZE 256 465*adfc5217SJeff Kirsher /* [R 1] indication the initializing the link list by the hardware was done. */ 466*adfc5217SJeff Kirsher #define CFC_REG_LL_INIT_DONE 0x104074 467*adfc5217SJeff Kirsher /* [R 9] Number of allocated LCIDs which are at empty state */ 468*adfc5217SJeff Kirsher #define CFC_REG_NUM_LCIDS_ALLOC 0x104020 469*adfc5217SJeff Kirsher /* [R 9] Number of Arriving LCIDs in Link List Block */ 470*adfc5217SJeff Kirsher #define CFC_REG_NUM_LCIDS_ARRIVING 0x104004 471*adfc5217SJeff Kirsher #define CFC_REG_NUM_LCIDS_INSIDE_PF 0x104120 472*adfc5217SJeff Kirsher /* [R 9] Number of Leaving LCIDs in Link List Block */ 473*adfc5217SJeff Kirsher #define CFC_REG_NUM_LCIDS_LEAVING 0x104018 474*adfc5217SJeff Kirsher #define CFC_REG_WEAK_ENABLE_PF 0x104124 475*adfc5217SJeff Kirsher /* [RW 8] The event id for aggregated interrupt 0 */ 476*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_EVENT_0 0xc2038 477*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_EVENT_10 0xc2060 478*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_EVENT_11 0xc2064 479*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_EVENT_12 0xc2068 480*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_EVENT_13 0xc206c 481*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_EVENT_14 0xc2070 482*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_EVENT_15 0xc2074 483*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_EVENT_16 0xc2078 484*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_EVENT_2 0xc2040 485*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_EVENT_3 0xc2044 486*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_EVENT_4 0xc2048 487*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_EVENT_5 0xc204c 488*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_EVENT_6 0xc2050 489*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_EVENT_7 0xc2054 490*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_EVENT_8 0xc2058 491*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_EVENT_9 0xc205c 492*adfc5217SJeff Kirsher /* [RW 1] For each aggregated interrupt index whether the mode is normal (0) 493*adfc5217SJeff Kirsher or auto-mask-mode (1) */ 494*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_MODE_10 0xc21e0 495*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_MODE_11 0xc21e4 496*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_MODE_12 0xc21e8 497*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_MODE_13 0xc21ec 498*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_MODE_14 0xc21f0 499*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_MODE_15 0xc21f4 500*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_MODE_16 0xc21f8 501*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_MODE_6 0xc21d0 502*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_MODE_7 0xc21d4 503*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_MODE_8 0xc21d8 504*adfc5217SJeff Kirsher #define CSDM_REG_AGG_INT_MODE_9 0xc21dc 505*adfc5217SJeff Kirsher /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 506*adfc5217SJeff Kirsher #define CSDM_REG_CFC_RSP_START_ADDR 0xc2008 507*adfc5217SJeff Kirsher /* [RW 16] The maximum value of the completion counter #0 */ 508*adfc5217SJeff Kirsher #define CSDM_REG_CMP_COUNTER_MAX0 0xc201c 509*adfc5217SJeff Kirsher /* [RW 16] The maximum value of the completion counter #1 */ 510*adfc5217SJeff Kirsher #define CSDM_REG_CMP_COUNTER_MAX1 0xc2020 511*adfc5217SJeff Kirsher /* [RW 16] The maximum value of the completion counter #2 */ 512*adfc5217SJeff Kirsher #define CSDM_REG_CMP_COUNTER_MAX2 0xc2024 513*adfc5217SJeff Kirsher /* [RW 16] The maximum value of the completion counter #3 */ 514*adfc5217SJeff Kirsher #define CSDM_REG_CMP_COUNTER_MAX3 0xc2028 515*adfc5217SJeff Kirsher /* [RW 13] The start address in the internal RAM for the completion 516*adfc5217SJeff Kirsher counters. */ 517*adfc5217SJeff Kirsher #define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c 518*adfc5217SJeff Kirsher /* [RW 32] Interrupt mask register #0 read/write */ 519*adfc5217SJeff Kirsher #define CSDM_REG_CSDM_INT_MASK_0 0xc229c 520*adfc5217SJeff Kirsher #define CSDM_REG_CSDM_INT_MASK_1 0xc22ac 521*adfc5217SJeff Kirsher /* [R 32] Interrupt register #0 read */ 522*adfc5217SJeff Kirsher #define CSDM_REG_CSDM_INT_STS_0 0xc2290 523*adfc5217SJeff Kirsher #define CSDM_REG_CSDM_INT_STS_1 0xc22a0 524*adfc5217SJeff Kirsher /* [RW 11] Parity mask register #0 read/write */ 525*adfc5217SJeff Kirsher #define CSDM_REG_CSDM_PRTY_MASK 0xc22bc 526*adfc5217SJeff Kirsher /* [R 11] Parity register #0 read */ 527*adfc5217SJeff Kirsher #define CSDM_REG_CSDM_PRTY_STS 0xc22b0 528*adfc5217SJeff Kirsher /* [RC 11] Parity register #0 read clear */ 529*adfc5217SJeff Kirsher #define CSDM_REG_CSDM_PRTY_STS_CLR 0xc22b4 530*adfc5217SJeff Kirsher #define CSDM_REG_ENABLE_IN1 0xc2238 531*adfc5217SJeff Kirsher #define CSDM_REG_ENABLE_IN2 0xc223c 532*adfc5217SJeff Kirsher #define CSDM_REG_ENABLE_OUT1 0xc2240 533*adfc5217SJeff Kirsher #define CSDM_REG_ENABLE_OUT2 0xc2244 534*adfc5217SJeff Kirsher /* [RW 4] The initial number of messages that can be sent to the pxp control 535*adfc5217SJeff Kirsher interface without receiving any ACK. */ 536*adfc5217SJeff Kirsher #define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc 537*adfc5217SJeff Kirsher /* [ST 32] The number of ACK after placement messages received */ 538*adfc5217SJeff Kirsher #define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c 539*adfc5217SJeff Kirsher /* [ST 32] The number of packet end messages received from the parser */ 540*adfc5217SJeff Kirsher #define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274 541*adfc5217SJeff Kirsher /* [ST 32] The number of requests received from the pxp async if */ 542*adfc5217SJeff Kirsher #define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278 543*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 0 */ 544*adfc5217SJeff Kirsher #define CSDM_REG_NUM_OF_Q0_CMD 0xc2248 545*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 10 */ 546*adfc5217SJeff Kirsher #define CSDM_REG_NUM_OF_Q10_CMD 0xc226c 547*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 11 */ 548*adfc5217SJeff Kirsher #define CSDM_REG_NUM_OF_Q11_CMD 0xc2270 549*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 1 */ 550*adfc5217SJeff Kirsher #define CSDM_REG_NUM_OF_Q1_CMD 0xc224c 551*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 3 */ 552*adfc5217SJeff Kirsher #define CSDM_REG_NUM_OF_Q3_CMD 0xc2250 553*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 4 */ 554*adfc5217SJeff Kirsher #define CSDM_REG_NUM_OF_Q4_CMD 0xc2254 555*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 5 */ 556*adfc5217SJeff Kirsher #define CSDM_REG_NUM_OF_Q5_CMD 0xc2258 557*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 6 */ 558*adfc5217SJeff Kirsher #define CSDM_REG_NUM_OF_Q6_CMD 0xc225c 559*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 7 */ 560*adfc5217SJeff Kirsher #define CSDM_REG_NUM_OF_Q7_CMD 0xc2260 561*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 8 */ 562*adfc5217SJeff Kirsher #define CSDM_REG_NUM_OF_Q8_CMD 0xc2264 563*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 9 */ 564*adfc5217SJeff Kirsher #define CSDM_REG_NUM_OF_Q9_CMD 0xc2268 565*adfc5217SJeff Kirsher /* [RW 13] The start address in the internal RAM for queue counters */ 566*adfc5217SJeff Kirsher #define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010 567*adfc5217SJeff Kirsher /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 568*adfc5217SJeff Kirsher #define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548 569*adfc5217SJeff Kirsher /* [R 1] parser fifo empty in sdm_sync block */ 570*adfc5217SJeff Kirsher #define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550 571*adfc5217SJeff Kirsher /* [R 1] parser serial fifo empty in sdm_sync block */ 572*adfc5217SJeff Kirsher #define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558 573*adfc5217SJeff Kirsher /* [RW 32] Tick for timer counter. Applicable only when 574*adfc5217SJeff Kirsher ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */ 575*adfc5217SJeff Kirsher #define CSDM_REG_TIMER_TICK 0xc2000 576*adfc5217SJeff Kirsher /* [RW 5] The number of time_slots in the arbitration cycle */ 577*adfc5217SJeff Kirsher #define CSEM_REG_ARB_CYCLE_SIZE 0x200034 578*adfc5217SJeff Kirsher /* [RW 3] The source that is associated with arbitration element 0. Source 579*adfc5217SJeff Kirsher decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 580*adfc5217SJeff Kirsher sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 581*adfc5217SJeff Kirsher #define CSEM_REG_ARB_ELEMENT0 0x200020 582*adfc5217SJeff Kirsher /* [RW 3] The source that is associated with arbitration element 1. Source 583*adfc5217SJeff Kirsher decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 584*adfc5217SJeff Kirsher sleeping thread with priority 1; 4- sleeping thread with priority 2. 585*adfc5217SJeff Kirsher Could not be equal to register ~csem_registers_arb_element0.arb_element0 */ 586*adfc5217SJeff Kirsher #define CSEM_REG_ARB_ELEMENT1 0x200024 587*adfc5217SJeff Kirsher /* [RW 3] The source that is associated with arbitration element 2. Source 588*adfc5217SJeff Kirsher decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 589*adfc5217SJeff Kirsher sleeping thread with priority 1; 4- sleeping thread with priority 2. 590*adfc5217SJeff Kirsher Could not be equal to register ~csem_registers_arb_element0.arb_element0 591*adfc5217SJeff Kirsher and ~csem_registers_arb_element1.arb_element1 */ 592*adfc5217SJeff Kirsher #define CSEM_REG_ARB_ELEMENT2 0x200028 593*adfc5217SJeff Kirsher /* [RW 3] The source that is associated with arbitration element 3. Source 594*adfc5217SJeff Kirsher decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 595*adfc5217SJeff Kirsher sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 596*adfc5217SJeff Kirsher not be equal to register ~csem_registers_arb_element0.arb_element0 and 597*adfc5217SJeff Kirsher ~csem_registers_arb_element1.arb_element1 and 598*adfc5217SJeff Kirsher ~csem_registers_arb_element2.arb_element2 */ 599*adfc5217SJeff Kirsher #define CSEM_REG_ARB_ELEMENT3 0x20002c 600*adfc5217SJeff Kirsher /* [RW 3] The source that is associated with arbitration element 4. Source 601*adfc5217SJeff Kirsher decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 602*adfc5217SJeff Kirsher sleeping thread with priority 1; 4- sleeping thread with priority 2. 603*adfc5217SJeff Kirsher Could not be equal to register ~csem_registers_arb_element0.arb_element0 604*adfc5217SJeff Kirsher and ~csem_registers_arb_element1.arb_element1 and 605*adfc5217SJeff Kirsher ~csem_registers_arb_element2.arb_element2 and 606*adfc5217SJeff Kirsher ~csem_registers_arb_element3.arb_element3 */ 607*adfc5217SJeff Kirsher #define CSEM_REG_ARB_ELEMENT4 0x200030 608*adfc5217SJeff Kirsher /* [RW 32] Interrupt mask register #0 read/write */ 609*adfc5217SJeff Kirsher #define CSEM_REG_CSEM_INT_MASK_0 0x200110 610*adfc5217SJeff Kirsher #define CSEM_REG_CSEM_INT_MASK_1 0x200120 611*adfc5217SJeff Kirsher /* [R 32] Interrupt register #0 read */ 612*adfc5217SJeff Kirsher #define CSEM_REG_CSEM_INT_STS_0 0x200104 613*adfc5217SJeff Kirsher #define CSEM_REG_CSEM_INT_STS_1 0x200114 614*adfc5217SJeff Kirsher /* [RW 32] Parity mask register #0 read/write */ 615*adfc5217SJeff Kirsher #define CSEM_REG_CSEM_PRTY_MASK_0 0x200130 616*adfc5217SJeff Kirsher #define CSEM_REG_CSEM_PRTY_MASK_1 0x200140 617*adfc5217SJeff Kirsher /* [R 32] Parity register #0 read */ 618*adfc5217SJeff Kirsher #define CSEM_REG_CSEM_PRTY_STS_0 0x200124 619*adfc5217SJeff Kirsher #define CSEM_REG_CSEM_PRTY_STS_1 0x200134 620*adfc5217SJeff Kirsher /* [RC 32] Parity register #0 read clear */ 621*adfc5217SJeff Kirsher #define CSEM_REG_CSEM_PRTY_STS_CLR_0 0x200128 622*adfc5217SJeff Kirsher #define CSEM_REG_CSEM_PRTY_STS_CLR_1 0x200138 623*adfc5217SJeff Kirsher #define CSEM_REG_ENABLE_IN 0x2000a4 624*adfc5217SJeff Kirsher #define CSEM_REG_ENABLE_OUT 0x2000a8 625*adfc5217SJeff Kirsher /* [RW 32] This address space contains all registers and memories that are 626*adfc5217SJeff Kirsher placed in SEM_FAST block. The SEM_FAST registers are described in 627*adfc5217SJeff Kirsher appendix B. In order to access the sem_fast registers the base address 628*adfc5217SJeff Kirsher ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 629*adfc5217SJeff Kirsher #define CSEM_REG_FAST_MEMORY 0x220000 630*adfc5217SJeff Kirsher /* [RW 1] Disables input messages from FIC0 May be updated during run_time 631*adfc5217SJeff Kirsher by the microcode */ 632*adfc5217SJeff Kirsher #define CSEM_REG_FIC0_DISABLE 0x200224 633*adfc5217SJeff Kirsher /* [RW 1] Disables input messages from FIC1 May be updated during run_time 634*adfc5217SJeff Kirsher by the microcode */ 635*adfc5217SJeff Kirsher #define CSEM_REG_FIC1_DISABLE 0x200234 636*adfc5217SJeff Kirsher /* [RW 15] Interrupt table Read and write access to it is not possible in 637*adfc5217SJeff Kirsher the middle of the work */ 638*adfc5217SJeff Kirsher #define CSEM_REG_INT_TABLE 0x200400 639*adfc5217SJeff Kirsher /* [ST 24] Statistics register. The number of messages that entered through 640*adfc5217SJeff Kirsher FIC0 */ 641*adfc5217SJeff Kirsher #define CSEM_REG_MSG_NUM_FIC0 0x200000 642*adfc5217SJeff Kirsher /* [ST 24] Statistics register. The number of messages that entered through 643*adfc5217SJeff Kirsher FIC1 */ 644*adfc5217SJeff Kirsher #define CSEM_REG_MSG_NUM_FIC1 0x200004 645*adfc5217SJeff Kirsher /* [ST 24] Statistics register. The number of messages that were sent to 646*adfc5217SJeff Kirsher FOC0 */ 647*adfc5217SJeff Kirsher #define CSEM_REG_MSG_NUM_FOC0 0x200008 648*adfc5217SJeff Kirsher /* [ST 24] Statistics register. The number of messages that were sent to 649*adfc5217SJeff Kirsher FOC1 */ 650*adfc5217SJeff Kirsher #define CSEM_REG_MSG_NUM_FOC1 0x20000c 651*adfc5217SJeff Kirsher /* [ST 24] Statistics register. The number of messages that were sent to 652*adfc5217SJeff Kirsher FOC2 */ 653*adfc5217SJeff Kirsher #define CSEM_REG_MSG_NUM_FOC2 0x200010 654*adfc5217SJeff Kirsher /* [ST 24] Statistics register. The number of messages that were sent to 655*adfc5217SJeff Kirsher FOC3 */ 656*adfc5217SJeff Kirsher #define CSEM_REG_MSG_NUM_FOC3 0x200014 657*adfc5217SJeff Kirsher /* [RW 1] Disables input messages from the passive buffer May be updated 658*adfc5217SJeff Kirsher during run_time by the microcode */ 659*adfc5217SJeff Kirsher #define CSEM_REG_PAS_DISABLE 0x20024c 660*adfc5217SJeff Kirsher /* [WB 128] Debug only. Passive buffer memory */ 661*adfc5217SJeff Kirsher #define CSEM_REG_PASSIVE_BUFFER 0x202000 662*adfc5217SJeff Kirsher /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 663*adfc5217SJeff Kirsher #define CSEM_REG_PRAM 0x240000 664*adfc5217SJeff Kirsher /* [R 16] Valid sleeping threads indication have bit per thread */ 665*adfc5217SJeff Kirsher #define CSEM_REG_SLEEP_THREADS_VALID 0x20026c 666*adfc5217SJeff Kirsher /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 667*adfc5217SJeff Kirsher #define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0 668*adfc5217SJeff Kirsher /* [RW 16] List of free threads . There is a bit per thread. */ 669*adfc5217SJeff Kirsher #define CSEM_REG_THREADS_LIST 0x2002e4 670*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 0 */ 671*adfc5217SJeff Kirsher #define CSEM_REG_TS_0_AS 0x200038 672*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 10 */ 673*adfc5217SJeff Kirsher #define CSEM_REG_TS_10_AS 0x200060 674*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 11 */ 675*adfc5217SJeff Kirsher #define CSEM_REG_TS_11_AS 0x200064 676*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 12 */ 677*adfc5217SJeff Kirsher #define CSEM_REG_TS_12_AS 0x200068 678*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 13 */ 679*adfc5217SJeff Kirsher #define CSEM_REG_TS_13_AS 0x20006c 680*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 14 */ 681*adfc5217SJeff Kirsher #define CSEM_REG_TS_14_AS 0x200070 682*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 15 */ 683*adfc5217SJeff Kirsher #define CSEM_REG_TS_15_AS 0x200074 684*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 16 */ 685*adfc5217SJeff Kirsher #define CSEM_REG_TS_16_AS 0x200078 686*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 17 */ 687*adfc5217SJeff Kirsher #define CSEM_REG_TS_17_AS 0x20007c 688*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 18 */ 689*adfc5217SJeff Kirsher #define CSEM_REG_TS_18_AS 0x200080 690*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 1 */ 691*adfc5217SJeff Kirsher #define CSEM_REG_TS_1_AS 0x20003c 692*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 2 */ 693*adfc5217SJeff Kirsher #define CSEM_REG_TS_2_AS 0x200040 694*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 3 */ 695*adfc5217SJeff Kirsher #define CSEM_REG_TS_3_AS 0x200044 696*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 4 */ 697*adfc5217SJeff Kirsher #define CSEM_REG_TS_4_AS 0x200048 698*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 5 */ 699*adfc5217SJeff Kirsher #define CSEM_REG_TS_5_AS 0x20004c 700*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 6 */ 701*adfc5217SJeff Kirsher #define CSEM_REG_TS_6_AS 0x200050 702*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 7 */ 703*adfc5217SJeff Kirsher #define CSEM_REG_TS_7_AS 0x200054 704*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 8 */ 705*adfc5217SJeff Kirsher #define CSEM_REG_TS_8_AS 0x200058 706*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 9 */ 707*adfc5217SJeff Kirsher #define CSEM_REG_TS_9_AS 0x20005c 708*adfc5217SJeff Kirsher /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 709*adfc5217SJeff Kirsher * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ 710*adfc5217SJeff Kirsher #define CSEM_REG_VFPF_ERR_NUM 0x200380 711*adfc5217SJeff Kirsher /* [RW 1] Parity mask register #0 read/write */ 712*adfc5217SJeff Kirsher #define DBG_REG_DBG_PRTY_MASK 0xc0a8 713*adfc5217SJeff Kirsher /* [R 1] Parity register #0 read */ 714*adfc5217SJeff Kirsher #define DBG_REG_DBG_PRTY_STS 0xc09c 715*adfc5217SJeff Kirsher /* [RC 1] Parity register #0 read clear */ 716*adfc5217SJeff Kirsher #define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0 717*adfc5217SJeff Kirsher /* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The 718*adfc5217SJeff Kirsher * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0; 719*adfc5217SJeff Kirsher * 4.Completion function=0; 5.Error handling=0 */ 720*adfc5217SJeff Kirsher #define DMAE_REG_BACKWARD_COMP_EN 0x10207c 721*adfc5217SJeff Kirsher /* [RW 32] Commands memory. The address to command X; row Y is to calculated 722*adfc5217SJeff Kirsher as 14*X+Y. */ 723*adfc5217SJeff Kirsher #define DMAE_REG_CMD_MEM 0x102400 724*adfc5217SJeff Kirsher #define DMAE_REG_CMD_MEM_SIZE 224 725*adfc5217SJeff Kirsher /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c 726*adfc5217SJeff Kirsher initial value is all ones. */ 727*adfc5217SJeff Kirsher #define DMAE_REG_CRC16C_INIT 0x10201c 728*adfc5217SJeff Kirsher /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the 729*adfc5217SJeff Kirsher CRC-16 T10 initial value is all ones. */ 730*adfc5217SJeff Kirsher #define DMAE_REG_CRC16T10_INIT 0x102020 731*adfc5217SJeff Kirsher /* [RW 2] Interrupt mask register #0 read/write */ 732*adfc5217SJeff Kirsher #define DMAE_REG_DMAE_INT_MASK 0x102054 733*adfc5217SJeff Kirsher /* [RW 4] Parity mask register #0 read/write */ 734*adfc5217SJeff Kirsher #define DMAE_REG_DMAE_PRTY_MASK 0x102064 735*adfc5217SJeff Kirsher /* [R 4] Parity register #0 read */ 736*adfc5217SJeff Kirsher #define DMAE_REG_DMAE_PRTY_STS 0x102058 737*adfc5217SJeff Kirsher /* [RC 4] Parity register #0 read clear */ 738*adfc5217SJeff Kirsher #define DMAE_REG_DMAE_PRTY_STS_CLR 0x10205c 739*adfc5217SJeff Kirsher /* [RW 1] Command 0 go. */ 740*adfc5217SJeff Kirsher #define DMAE_REG_GO_C0 0x102080 741*adfc5217SJeff Kirsher /* [RW 1] Command 1 go. */ 742*adfc5217SJeff Kirsher #define DMAE_REG_GO_C1 0x102084 743*adfc5217SJeff Kirsher /* [RW 1] Command 10 go. */ 744*adfc5217SJeff Kirsher #define DMAE_REG_GO_C10 0x102088 745*adfc5217SJeff Kirsher /* [RW 1] Command 11 go. */ 746*adfc5217SJeff Kirsher #define DMAE_REG_GO_C11 0x10208c 747*adfc5217SJeff Kirsher /* [RW 1] Command 12 go. */ 748*adfc5217SJeff Kirsher #define DMAE_REG_GO_C12 0x102090 749*adfc5217SJeff Kirsher /* [RW 1] Command 13 go. */ 750*adfc5217SJeff Kirsher #define DMAE_REG_GO_C13 0x102094 751*adfc5217SJeff Kirsher /* [RW 1] Command 14 go. */ 752*adfc5217SJeff Kirsher #define DMAE_REG_GO_C14 0x102098 753*adfc5217SJeff Kirsher /* [RW 1] Command 15 go. */ 754*adfc5217SJeff Kirsher #define DMAE_REG_GO_C15 0x10209c 755*adfc5217SJeff Kirsher /* [RW 1] Command 2 go. */ 756*adfc5217SJeff Kirsher #define DMAE_REG_GO_C2 0x1020a0 757*adfc5217SJeff Kirsher /* [RW 1] Command 3 go. */ 758*adfc5217SJeff Kirsher #define DMAE_REG_GO_C3 0x1020a4 759*adfc5217SJeff Kirsher /* [RW 1] Command 4 go. */ 760*adfc5217SJeff Kirsher #define DMAE_REG_GO_C4 0x1020a8 761*adfc5217SJeff Kirsher /* [RW 1] Command 5 go. */ 762*adfc5217SJeff Kirsher #define DMAE_REG_GO_C5 0x1020ac 763*adfc5217SJeff Kirsher /* [RW 1] Command 6 go. */ 764*adfc5217SJeff Kirsher #define DMAE_REG_GO_C6 0x1020b0 765*adfc5217SJeff Kirsher /* [RW 1] Command 7 go. */ 766*adfc5217SJeff Kirsher #define DMAE_REG_GO_C7 0x1020b4 767*adfc5217SJeff Kirsher /* [RW 1] Command 8 go. */ 768*adfc5217SJeff Kirsher #define DMAE_REG_GO_C8 0x1020b8 769*adfc5217SJeff Kirsher /* [RW 1] Command 9 go. */ 770*adfc5217SJeff Kirsher #define DMAE_REG_GO_C9 0x1020bc 771*adfc5217SJeff Kirsher /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge 772*adfc5217SJeff Kirsher input is disregarded; valid is deasserted; all other signals are treated 773*adfc5217SJeff Kirsher as usual; if 1 - normal activity. */ 774*adfc5217SJeff Kirsher #define DMAE_REG_GRC_IFEN 0x102008 775*adfc5217SJeff Kirsher /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the 776*adfc5217SJeff Kirsher acknowledge input is disregarded; valid is deasserted; full is asserted; 777*adfc5217SJeff Kirsher all other signals are treated as usual; if 1 - normal activity. */ 778*adfc5217SJeff Kirsher #define DMAE_REG_PCI_IFEN 0x102004 779*adfc5217SJeff Kirsher /* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the 780*adfc5217SJeff Kirsher initial value to the credit counter; related to the address. Read returns 781*adfc5217SJeff Kirsher the current value of the counter. */ 782*adfc5217SJeff Kirsher #define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0 783*adfc5217SJeff Kirsher /* [RW 8] Aggregation command. */ 784*adfc5217SJeff Kirsher #define DORQ_REG_AGG_CMD0 0x170060 785*adfc5217SJeff Kirsher /* [RW 8] Aggregation command. */ 786*adfc5217SJeff Kirsher #define DORQ_REG_AGG_CMD1 0x170064 787*adfc5217SJeff Kirsher /* [RW 8] Aggregation command. */ 788*adfc5217SJeff Kirsher #define DORQ_REG_AGG_CMD2 0x170068 789*adfc5217SJeff Kirsher /* [RW 8] Aggregation command. */ 790*adfc5217SJeff Kirsher #define DORQ_REG_AGG_CMD3 0x17006c 791*adfc5217SJeff Kirsher /* [RW 28] UCM Header. */ 792*adfc5217SJeff Kirsher #define DORQ_REG_CMHEAD_RX 0x170050 793*adfc5217SJeff Kirsher /* [RW 32] Doorbell address for RBC doorbells (function 0). */ 794*adfc5217SJeff Kirsher #define DORQ_REG_DB_ADDR0 0x17008c 795*adfc5217SJeff Kirsher /* [RW 5] Interrupt mask register #0 read/write */ 796*adfc5217SJeff Kirsher #define DORQ_REG_DORQ_INT_MASK 0x170180 797*adfc5217SJeff Kirsher /* [R 5] Interrupt register #0 read */ 798*adfc5217SJeff Kirsher #define DORQ_REG_DORQ_INT_STS 0x170174 799*adfc5217SJeff Kirsher /* [RC 5] Interrupt register #0 read clear */ 800*adfc5217SJeff Kirsher #define DORQ_REG_DORQ_INT_STS_CLR 0x170178 801*adfc5217SJeff Kirsher /* [RW 2] Parity mask register #0 read/write */ 802*adfc5217SJeff Kirsher #define DORQ_REG_DORQ_PRTY_MASK 0x170190 803*adfc5217SJeff Kirsher /* [R 2] Parity register #0 read */ 804*adfc5217SJeff Kirsher #define DORQ_REG_DORQ_PRTY_STS 0x170184 805*adfc5217SJeff Kirsher /* [RC 2] Parity register #0 read clear */ 806*adfc5217SJeff Kirsher #define DORQ_REG_DORQ_PRTY_STS_CLR 0x170188 807*adfc5217SJeff Kirsher /* [RW 8] The address to write the DPM CID to STORM. */ 808*adfc5217SJeff Kirsher #define DORQ_REG_DPM_CID_ADDR 0x170044 809*adfc5217SJeff Kirsher /* [RW 5] The DPM mode CID extraction offset. */ 810*adfc5217SJeff Kirsher #define DORQ_REG_DPM_CID_OFST 0x170030 811*adfc5217SJeff Kirsher /* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */ 812*adfc5217SJeff Kirsher #define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c 813*adfc5217SJeff Kirsher /* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */ 814*adfc5217SJeff Kirsher #define DORQ_REG_DQ_FIFO_FULL_TH 0x170078 815*adfc5217SJeff Kirsher /* [R 13] Current value of the DQ FIFO fill level according to following 816*adfc5217SJeff Kirsher pointer. The range is 0 - 256 FIFO rows; where each row stands for the 817*adfc5217SJeff Kirsher doorbell. */ 818*adfc5217SJeff Kirsher #define DORQ_REG_DQ_FILL_LVLF 0x1700a4 819*adfc5217SJeff Kirsher /* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or 820*adfc5217SJeff Kirsher equal to full threshold; reset on full clear. */ 821*adfc5217SJeff Kirsher #define DORQ_REG_DQ_FULL_ST 0x1700c0 822*adfc5217SJeff Kirsher /* [RW 28] The value sent to CM header in the case of CFC load error. */ 823*adfc5217SJeff Kirsher #define DORQ_REG_ERR_CMHEAD 0x170058 824*adfc5217SJeff Kirsher #define DORQ_REG_IF_EN 0x170004 825*adfc5217SJeff Kirsher #define DORQ_REG_MODE_ACT 0x170008 826*adfc5217SJeff Kirsher /* [RW 5] The normal mode CID extraction offset. */ 827*adfc5217SJeff Kirsher #define DORQ_REG_NORM_CID_OFST 0x17002c 828*adfc5217SJeff Kirsher /* [RW 28] TCM Header when only TCP context is loaded. */ 829*adfc5217SJeff Kirsher #define DORQ_REG_NORM_CMHEAD_TX 0x17004c 830*adfc5217SJeff Kirsher /* [RW 3] The number of simultaneous outstanding requests to Context Fetch 831*adfc5217SJeff Kirsher Interface. */ 832*adfc5217SJeff Kirsher #define DORQ_REG_OUTST_REQ 0x17003c 833*adfc5217SJeff Kirsher #define DORQ_REG_PF_USAGE_CNT 0x1701d0 834*adfc5217SJeff Kirsher #define DORQ_REG_REGN 0x170038 835*adfc5217SJeff Kirsher /* [R 4] Current value of response A counter credit. Initial credit is 836*adfc5217SJeff Kirsher configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd 837*adfc5217SJeff Kirsher register. */ 838*adfc5217SJeff Kirsher #define DORQ_REG_RSPA_CRD_CNT 0x1700ac 839*adfc5217SJeff Kirsher /* [R 4] Current value of response B counter credit. Initial credit is 840*adfc5217SJeff Kirsher configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd 841*adfc5217SJeff Kirsher register. */ 842*adfc5217SJeff Kirsher #define DORQ_REG_RSPB_CRD_CNT 0x1700b0 843*adfc5217SJeff Kirsher /* [RW 4] The initial credit at the Doorbell Response Interface. The write 844*adfc5217SJeff Kirsher writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The 845*adfc5217SJeff Kirsher read reads this written value. */ 846*adfc5217SJeff Kirsher #define DORQ_REG_RSP_INIT_CRD 0x170048 847*adfc5217SJeff Kirsher /* [RW 4] Initial activity counter value on the load request; when the 848*adfc5217SJeff Kirsher shortcut is done. */ 849*adfc5217SJeff Kirsher #define DORQ_REG_SHRT_ACT_CNT 0x170070 850*adfc5217SJeff Kirsher /* [RW 28] TCM Header when both ULP and TCP context is loaded. */ 851*adfc5217SJeff Kirsher #define DORQ_REG_SHRT_CMHEAD 0x170054 852*adfc5217SJeff Kirsher #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4) 853*adfc5217SJeff Kirsher #define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1<<0) 854*adfc5217SJeff Kirsher #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3) 855*adfc5217SJeff Kirsher #define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7) 856*adfc5217SJeff Kirsher #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2) 857*adfc5217SJeff Kirsher #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1) 858*adfc5217SJeff Kirsher #define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1<<0) 859*adfc5217SJeff Kirsher #define HC_REG_AGG_INT_0 0x108050 860*adfc5217SJeff Kirsher #define HC_REG_AGG_INT_1 0x108054 861*adfc5217SJeff Kirsher #define HC_REG_ATTN_BIT 0x108120 862*adfc5217SJeff Kirsher #define HC_REG_ATTN_IDX 0x108100 863*adfc5217SJeff Kirsher #define HC_REG_ATTN_MSG0_ADDR_L 0x108018 864*adfc5217SJeff Kirsher #define HC_REG_ATTN_MSG1_ADDR_L 0x108020 865*adfc5217SJeff Kirsher #define HC_REG_ATTN_NUM_P0 0x108038 866*adfc5217SJeff Kirsher #define HC_REG_ATTN_NUM_P1 0x10803c 867*adfc5217SJeff Kirsher #define HC_REG_COMMAND_REG 0x108180 868*adfc5217SJeff Kirsher #define HC_REG_CONFIG_0 0x108000 869*adfc5217SJeff Kirsher #define HC_REG_CONFIG_1 0x108004 870*adfc5217SJeff Kirsher #define HC_REG_FUNC_NUM_P0 0x1080ac 871*adfc5217SJeff Kirsher #define HC_REG_FUNC_NUM_P1 0x1080b0 872*adfc5217SJeff Kirsher /* [RW 3] Parity mask register #0 read/write */ 873*adfc5217SJeff Kirsher #define HC_REG_HC_PRTY_MASK 0x1080a0 874*adfc5217SJeff Kirsher /* [R 3] Parity register #0 read */ 875*adfc5217SJeff Kirsher #define HC_REG_HC_PRTY_STS 0x108094 876*adfc5217SJeff Kirsher /* [RC 3] Parity register #0 read clear */ 877*adfc5217SJeff Kirsher #define HC_REG_HC_PRTY_STS_CLR 0x108098 878*adfc5217SJeff Kirsher #define HC_REG_INT_MASK 0x108108 879*adfc5217SJeff Kirsher #define HC_REG_LEADING_EDGE_0 0x108040 880*adfc5217SJeff Kirsher #define HC_REG_LEADING_EDGE_1 0x108048 881*adfc5217SJeff Kirsher #define HC_REG_MAIN_MEMORY 0x108800 882*adfc5217SJeff Kirsher #define HC_REG_MAIN_MEMORY_SIZE 152 883*adfc5217SJeff Kirsher #define HC_REG_P0_PROD_CONS 0x108200 884*adfc5217SJeff Kirsher #define HC_REG_P1_PROD_CONS 0x108400 885*adfc5217SJeff Kirsher #define HC_REG_PBA_COMMAND 0x108140 886*adfc5217SJeff Kirsher #define HC_REG_PCI_CONFIG_0 0x108010 887*adfc5217SJeff Kirsher #define HC_REG_PCI_CONFIG_1 0x108014 888*adfc5217SJeff Kirsher #define HC_REG_STATISTIC_COUNTERS 0x109000 889*adfc5217SJeff Kirsher #define HC_REG_TRAILING_EDGE_0 0x108044 890*adfc5217SJeff Kirsher #define HC_REG_TRAILING_EDGE_1 0x10804c 891*adfc5217SJeff Kirsher #define HC_REG_UC_RAM_ADDR_0 0x108028 892*adfc5217SJeff Kirsher #define HC_REG_UC_RAM_ADDR_1 0x108030 893*adfc5217SJeff Kirsher #define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068 894*adfc5217SJeff Kirsher #define HC_REG_VQID_0 0x108008 895*adfc5217SJeff Kirsher #define HC_REG_VQID_1 0x10800c 896*adfc5217SJeff Kirsher #define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1) 897*adfc5217SJeff Kirsher #define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1<<0) 898*adfc5217SJeff Kirsher #define IGU_REG_ATTENTION_ACK_BITS 0x130108 899*adfc5217SJeff Kirsher /* [R 4] Debug: attn_fsm */ 900*adfc5217SJeff Kirsher #define IGU_REG_ATTN_FSM 0x130054 901*adfc5217SJeff Kirsher #define IGU_REG_ATTN_MSG_ADDR_H 0x13011c 902*adfc5217SJeff Kirsher #define IGU_REG_ATTN_MSG_ADDR_L 0x130120 903*adfc5217SJeff Kirsher /* [R 4] Debug: [3] - attention write done message is pending (0-no pending; 904*adfc5217SJeff Kirsher * 1-pending). [2:0] = PFID. Pending means attention message was sent; but 905*adfc5217SJeff Kirsher * write done didn't receive. */ 906*adfc5217SJeff Kirsher #define IGU_REG_ATTN_WRITE_DONE_PENDING 0x130030 907*adfc5217SJeff Kirsher #define IGU_REG_BLOCK_CONFIGURATION 0x130000 908*adfc5217SJeff Kirsher #define IGU_REG_COMMAND_REG_32LSB_DATA 0x130124 909*adfc5217SJeff Kirsher #define IGU_REG_COMMAND_REG_CTRL 0x13012c 910*adfc5217SJeff Kirsher /* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit 911*adfc5217SJeff Kirsher * is clear. The bits in this registers are set and clear via the producer 912*adfc5217SJeff Kirsher * command. Data valid only in addresses 0-4. all the rest are zero. */ 913*adfc5217SJeff Kirsher #define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP 0x130200 914*adfc5217SJeff Kirsher /* [R 5] Debug: ctrl_fsm */ 915*adfc5217SJeff Kirsher #define IGU_REG_CTRL_FSM 0x130064 916*adfc5217SJeff Kirsher /* [R 1] data available for error memory. If this bit is clear do not red 917*adfc5217SJeff Kirsher * from error_handling_memory. */ 918*adfc5217SJeff Kirsher #define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130 919*adfc5217SJeff Kirsher /* [RW 11] Parity mask register #0 read/write */ 920*adfc5217SJeff Kirsher #define IGU_REG_IGU_PRTY_MASK 0x1300a8 921*adfc5217SJeff Kirsher /* [R 11] Parity register #0 read */ 922*adfc5217SJeff Kirsher #define IGU_REG_IGU_PRTY_STS 0x13009c 923*adfc5217SJeff Kirsher /* [RC 11] Parity register #0 read clear */ 924*adfc5217SJeff Kirsher #define IGU_REG_IGU_PRTY_STS_CLR 0x1300a0 925*adfc5217SJeff Kirsher /* [R 4] Debug: int_handle_fsm */ 926*adfc5217SJeff Kirsher #define IGU_REG_INT_HANDLE_FSM 0x130050 927*adfc5217SJeff Kirsher #define IGU_REG_LEADING_EDGE_LATCH 0x130134 928*adfc5217SJeff Kirsher /* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid. 929*adfc5217SJeff Kirsher * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF 930*adfc5217SJeff Kirsher * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */ 931*adfc5217SJeff Kirsher #define IGU_REG_MAPPING_MEMORY 0x131000 932*adfc5217SJeff Kirsher #define IGU_REG_MAPPING_MEMORY_SIZE 136 933*adfc5217SJeff Kirsher #define IGU_REG_PBA_STATUS_LSB 0x130138 934*adfc5217SJeff Kirsher #define IGU_REG_PBA_STATUS_MSB 0x13013c 935*adfc5217SJeff Kirsher #define IGU_REG_PCI_PF_MSI_EN 0x130140 936*adfc5217SJeff Kirsher #define IGU_REG_PCI_PF_MSIX_EN 0x130144 937*adfc5217SJeff Kirsher #define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148 938*adfc5217SJeff Kirsher /* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no 939*adfc5217SJeff Kirsher * pending; 1 = pending. Pendings means interrupt was asserted; and write 940*adfc5217SJeff Kirsher * done was not received. Data valid only in addresses 0-4. all the rest are 941*adfc5217SJeff Kirsher * zero. */ 942*adfc5217SJeff Kirsher #define IGU_REG_PENDING_BITS_STATUS 0x130300 943*adfc5217SJeff Kirsher #define IGU_REG_PF_CONFIGURATION 0x130154 944*adfc5217SJeff Kirsher /* [RW 20] producers only. E2 mode: address 0-135 match to the mapping 945*adfc5217SJeff Kirsher * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default 946*adfc5217SJeff Kirsher * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod; 947*adfc5217SJeff Kirsher * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode 948*adfc5217SJeff Kirsher * - In backward compatible mode; for non default SB; each even line in the 949*adfc5217SJeff Kirsher * memory holds the U producer and each odd line hold the C producer. The 950*adfc5217SJeff Kirsher * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The 951*adfc5217SJeff Kirsher * last 20 producers are for the DSB for each PF. each PF has five segments 952*adfc5217SJeff Kirsher * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 953*adfc5217SJeff Kirsher * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; */ 954*adfc5217SJeff Kirsher #define IGU_REG_PROD_CONS_MEMORY 0x132000 955*adfc5217SJeff Kirsher /* [R 3] Debug: pxp_arb_fsm */ 956*adfc5217SJeff Kirsher #define IGU_REG_PXP_ARB_FSM 0x130068 957*adfc5217SJeff Kirsher /* [RW 6] Write one for each bit will reset the appropriate memory. When the 958*adfc5217SJeff Kirsher * memory reset finished the appropriate bit will be clear. Bit 0 - mapping 959*adfc5217SJeff Kirsher * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3 960*adfc5217SJeff Kirsher * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; */ 961*adfc5217SJeff Kirsher #define IGU_REG_RESET_MEMORIES 0x130158 962*adfc5217SJeff Kirsher /* [R 4] Debug: sb_ctrl_fsm */ 963*adfc5217SJeff Kirsher #define IGU_REG_SB_CTRL_FSM 0x13004c 964*adfc5217SJeff Kirsher #define IGU_REG_SB_INT_BEFORE_MASK_LSB 0x13015c 965*adfc5217SJeff Kirsher #define IGU_REG_SB_INT_BEFORE_MASK_MSB 0x130160 966*adfc5217SJeff Kirsher #define IGU_REG_SB_MASK_LSB 0x130164 967*adfc5217SJeff Kirsher #define IGU_REG_SB_MASK_MSB 0x130168 968*adfc5217SJeff Kirsher /* [RW 16] Number of command that were dropped without causing an interrupt 969*adfc5217SJeff Kirsher * due to: read access for WO BAR address; or write access for RO BAR 970*adfc5217SJeff Kirsher * address or any access for reserved address or PCI function error is set 971*adfc5217SJeff Kirsher * and address is not MSIX; PBA or cleanup */ 972*adfc5217SJeff Kirsher #define IGU_REG_SILENT_DROP 0x13016c 973*adfc5217SJeff Kirsher /* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 - 974*adfc5217SJeff Kirsher * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per 975*adfc5217SJeff Kirsher * PF; 68-71 number of ATTN messages per PF */ 976*adfc5217SJeff Kirsher #define IGU_REG_STATISTIC_NUM_MESSAGE_SENT 0x130800 977*adfc5217SJeff Kirsher /* [RW 32] Number of cycles the timer mask masking the IGU interrupt when a 978*adfc5217SJeff Kirsher * timer mask command arrives. Value must be bigger than 100. */ 979*adfc5217SJeff Kirsher #define IGU_REG_TIMER_MASKING_VALUE 0x13003c 980*adfc5217SJeff Kirsher #define IGU_REG_TRAILING_EDGE_LATCH 0x130104 981*adfc5217SJeff Kirsher #define IGU_REG_VF_CONFIGURATION 0x130170 982*adfc5217SJeff Kirsher /* [WB_R 32] Each bit represent write done pending bits status for that SB 983*adfc5217SJeff Kirsher * (MSI/MSIX message was sent and write done was not received yet). 0 = 984*adfc5217SJeff Kirsher * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */ 985*adfc5217SJeff Kirsher #define IGU_REG_WRITE_DONE_PENDING 0x130480 986*adfc5217SJeff Kirsher #define MCP_A_REG_MCPR_SCRATCH 0x3a0000 987*adfc5217SJeff Kirsher #define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c 988*adfc5217SJeff Kirsher #define MCP_REG_MCPR_GP_INPUTS 0x800c0 989*adfc5217SJeff Kirsher #define MCP_REG_MCPR_GP_OENABLE 0x800c8 990*adfc5217SJeff Kirsher #define MCP_REG_MCPR_GP_OUTPUTS 0x800c4 991*adfc5217SJeff Kirsher #define MCP_REG_MCPR_IMC_COMMAND 0x85900 992*adfc5217SJeff Kirsher #define MCP_REG_MCPR_IMC_DATAREG0 0x85920 993*adfc5217SJeff Kirsher #define MCP_REG_MCPR_IMC_SLAVE_CONTROL 0x85904 994*adfc5217SJeff Kirsher #define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c 995*adfc5217SJeff Kirsher #define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424 996*adfc5217SJeff Kirsher #define MCP_REG_MCPR_NVM_ADDR 0x8640c 997*adfc5217SJeff Kirsher #define MCP_REG_MCPR_NVM_CFG4 0x8642c 998*adfc5217SJeff Kirsher #define MCP_REG_MCPR_NVM_COMMAND 0x86400 999*adfc5217SJeff Kirsher #define MCP_REG_MCPR_NVM_READ 0x86410 1000*adfc5217SJeff Kirsher #define MCP_REG_MCPR_NVM_SW_ARB 0x86420 1001*adfc5217SJeff Kirsher #define MCP_REG_MCPR_NVM_WRITE 0x86408 1002*adfc5217SJeff Kirsher #define MCP_REG_MCPR_SCRATCH 0xa0000 1003*adfc5217SJeff Kirsher #define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1<<1) 1004*adfc5217SJeff Kirsher #define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1<<0) 1005*adfc5217SJeff Kirsher /* [R 32] read first 32 bit after inversion of function 0. mapped as 1006*adfc5217SJeff Kirsher follows: [0] NIG attention for function0; [1] NIG attention for 1007*adfc5217SJeff Kirsher function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; 1008*adfc5217SJeff Kirsher [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] 1009*adfc5217SJeff Kirsher GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE 1010*adfc5217SJeff Kirsher glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; 1011*adfc5217SJeff Kirsher [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] 1012*adfc5217SJeff Kirsher MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB 1013*adfc5217SJeff Kirsher Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw 1014*adfc5217SJeff Kirsher interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity 1015*adfc5217SJeff Kirsher error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw 1016*adfc5217SJeff Kirsher interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF 1017*adfc5217SJeff Kirsher Parity error; [31] PBF Hw interrupt; */ 1018*adfc5217SJeff Kirsher #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c 1019*adfc5217SJeff Kirsher #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430 1020*adfc5217SJeff Kirsher /* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0] 1021*adfc5217SJeff Kirsher NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 1022*adfc5217SJeff Kirsher mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; 1023*adfc5217SJeff Kirsher [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] 1024*adfc5217SJeff Kirsher PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event 1025*adfc5217SJeff Kirsher function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP 1026*adfc5217SJeff Kirsher Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for 1027*adfc5217SJeff Kirsher mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] 1028*adfc5217SJeff Kirsher BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC 1029*adfc5217SJeff Kirsher Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw 1030*adfc5217SJeff Kirsher interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI 1031*adfc5217SJeff Kirsher Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw 1032*adfc5217SJeff Kirsher interrupt; */ 1033*adfc5217SJeff Kirsher #define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434 1034*adfc5217SJeff Kirsher /* [R 32] read second 32 bit after inversion of function 0. mapped as 1035*adfc5217SJeff Kirsher follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1036*adfc5217SJeff Kirsher Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1037*adfc5217SJeff Kirsher interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1038*adfc5217SJeff Kirsher error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1039*adfc5217SJeff Kirsher interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1040*adfc5217SJeff Kirsher NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1041*adfc5217SJeff Kirsher [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1042*adfc5217SJeff Kirsher interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1043*adfc5217SJeff Kirsher Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1044*adfc5217SJeff Kirsher Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1045*adfc5217SJeff Kirsher Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1046*adfc5217SJeff Kirsher interrupt; */ 1047*adfc5217SJeff Kirsher #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438 1048*adfc5217SJeff Kirsher #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c 1049*adfc5217SJeff Kirsher /* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0] 1050*adfc5217SJeff Kirsher PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error; 1051*adfc5217SJeff Kirsher [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; 1052*adfc5217SJeff Kirsher [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] 1053*adfc5217SJeff Kirsher XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] 1054*adfc5217SJeff Kirsher DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity 1055*adfc5217SJeff Kirsher error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux 1056*adfc5217SJeff Kirsher PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; 1057*adfc5217SJeff Kirsher [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; 1058*adfc5217SJeff Kirsher [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; 1059*adfc5217SJeff Kirsher [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; 1060*adfc5217SJeff Kirsher [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */ 1061*adfc5217SJeff Kirsher #define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440 1062*adfc5217SJeff Kirsher /* [R 32] read third 32 bit after inversion of function 0. mapped as 1063*adfc5217SJeff Kirsher follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity 1064*adfc5217SJeff Kirsher error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] 1065*adfc5217SJeff Kirsher PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1066*adfc5217SJeff Kirsher interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1067*adfc5217SJeff Kirsher error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1068*adfc5217SJeff Kirsher Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1069*adfc5217SJeff Kirsher pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1070*adfc5217SJeff Kirsher MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1071*adfc5217SJeff Kirsher SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1072*adfc5217SJeff Kirsher timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1073*adfc5217SJeff Kirsher func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1074*adfc5217SJeff Kirsher attn1; */ 1075*adfc5217SJeff Kirsher #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444 1076*adfc5217SJeff Kirsher #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448 1077*adfc5217SJeff Kirsher /* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0] 1078*adfc5217SJeff Kirsher CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP 1079*adfc5217SJeff Kirsher Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient 1080*adfc5217SJeff Kirsher Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity 1081*adfc5217SJeff Kirsher error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw 1082*adfc5217SJeff Kirsher interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] 1083*adfc5217SJeff Kirsher MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] 1084*adfc5217SJeff Kirsher Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW 1085*adfc5217SJeff Kirsher timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 1086*adfc5217SJeff Kirsher func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 1087*adfc5217SJeff Kirsher func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW 1088*adfc5217SJeff Kirsher timers attn_4 func1; [30] General attn0; [31] General attn1; */ 1089*adfc5217SJeff Kirsher #define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c 1090*adfc5217SJeff Kirsher /* [R 32] read fourth 32 bit after inversion of function 0. mapped as 1091*adfc5217SJeff Kirsher follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1092*adfc5217SJeff Kirsher General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1093*adfc5217SJeff Kirsher [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1094*adfc5217SJeff Kirsher attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1095*adfc5217SJeff Kirsher [14] General attn16; [15] General attn17; [16] General attn18; [17] 1096*adfc5217SJeff Kirsher General attn19; [18] General attn20; [19] General attn21; [20] Main power 1097*adfc5217SJeff Kirsher interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1098*adfc5217SJeff Kirsher Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1099*adfc5217SJeff Kirsher Latched timeout attention; [27] GRC Latched reserved access attention; 1100*adfc5217SJeff Kirsher [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1101*adfc5217SJeff Kirsher Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1102*adfc5217SJeff Kirsher #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450 1103*adfc5217SJeff Kirsher #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454 1104*adfc5217SJeff Kirsher /* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0] 1105*adfc5217SJeff Kirsher General attn2; [1] General attn3; [2] General attn4; [3] General attn5; 1106*adfc5217SJeff Kirsher [4] General attn6; [5] General attn7; [6] General attn8; [7] General 1107*adfc5217SJeff Kirsher attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] 1108*adfc5217SJeff Kirsher General attn13; [12] General attn14; [13] General attn15; [14] General 1109*adfc5217SJeff Kirsher attn16; [15] General attn17; [16] General attn18; [17] General attn19; 1110*adfc5217SJeff Kirsher [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] 1111*adfc5217SJeff Kirsher RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] 1112*adfc5217SJeff Kirsher RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout 1113*adfc5217SJeff Kirsher attention; [27] GRC Latched reserved access attention; [28] MCP Latched 1114*adfc5217SJeff Kirsher rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched 1115*adfc5217SJeff Kirsher ump_tx_parity; [31] MCP Latched scpad_parity; */ 1116*adfc5217SJeff Kirsher #define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458 1117*adfc5217SJeff Kirsher /* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as 1118*adfc5217SJeff Kirsher * follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC 1119*adfc5217SJeff Kirsher * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] 1120*adfc5217SJeff Kirsher * CNIG attention (reserved); [7] CNIG parity (reserved); [31-8] Reserved; */ 1121*adfc5217SJeff Kirsher #define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 0xa700 1122*adfc5217SJeff Kirsher /* [W 14] write to this register results with the clear of the latched 1123*adfc5217SJeff Kirsher signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in 1124*adfc5217SJeff Kirsher d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP 1125*adfc5217SJeff Kirsher latch; one in d5 clears GRC Latched timeout attention; one in d6 clears 1126*adfc5217SJeff Kirsher GRC Latched reserved access attention; one in d7 clears Latched 1127*adfc5217SJeff Kirsher rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears 1128*adfc5217SJeff Kirsher Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both 1129*adfc5217SJeff Kirsher ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears 1130*adfc5217SJeff Kirsher pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read 1131*adfc5217SJeff Kirsher from this register return zero */ 1132*adfc5217SJeff Kirsher #define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c 1133*adfc5217SJeff Kirsher /* [RW 32] first 32b for enabling the output for function 0 output0. mapped 1134*adfc5217SJeff Kirsher as follows: [0] NIG attention for function0; [1] NIG attention for 1135*adfc5217SJeff Kirsher function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 1136*adfc5217SJeff Kirsher 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 1137*adfc5217SJeff Kirsher GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1138*adfc5217SJeff Kirsher function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1139*adfc5217SJeff Kirsher Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1140*adfc5217SJeff Kirsher SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X 1141*adfc5217SJeff Kirsher indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 1142*adfc5217SJeff Kirsher [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 1143*adfc5217SJeff Kirsher SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 1144*adfc5217SJeff Kirsher TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 1145*adfc5217SJeff Kirsher TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1146*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c 1147*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c 1148*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c 1149*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c 1150*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc 1151*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc 1152*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc 1153*adfc5217SJeff Kirsher /* [RW 32] first 32b for enabling the output for function 1 output0. mapped 1154*adfc5217SJeff Kirsher as follows: [0] NIG attention for function0; [1] NIG attention for 1155*adfc5217SJeff Kirsher function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function 1156*adfc5217SJeff Kirsher 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 1157*adfc5217SJeff Kirsher GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1158*adfc5217SJeff Kirsher function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1159*adfc5217SJeff Kirsher Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1160*adfc5217SJeff Kirsher SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X 1161*adfc5217SJeff Kirsher indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 1162*adfc5217SJeff Kirsher [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 1163*adfc5217SJeff Kirsher SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 1164*adfc5217SJeff Kirsher TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 1165*adfc5217SJeff Kirsher TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1166*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c 1167*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c 1168*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c 1169*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c 1170*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c 1171*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c 1172*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c 1173*adfc5217SJeff Kirsher /* [RW 32] first 32b for enabling the output for close the gate nig. mapped 1174*adfc5217SJeff Kirsher as follows: [0] NIG attention for function0; [1] NIG attention for 1175*adfc5217SJeff Kirsher function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 1176*adfc5217SJeff Kirsher 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 1177*adfc5217SJeff Kirsher GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1178*adfc5217SJeff Kirsher function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1179*adfc5217SJeff Kirsher Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1180*adfc5217SJeff Kirsher SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X 1181*adfc5217SJeff Kirsher indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 1182*adfc5217SJeff Kirsher [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 1183*adfc5217SJeff Kirsher SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 1184*adfc5217SJeff Kirsher TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 1185*adfc5217SJeff Kirsher TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1186*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec 1187*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c 1188*adfc5217SJeff Kirsher /* [RW 32] first 32b for enabling the output for close the gate pxp. mapped 1189*adfc5217SJeff Kirsher as follows: [0] NIG attention for function0; [1] NIG attention for 1190*adfc5217SJeff Kirsher function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 1191*adfc5217SJeff Kirsher 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 1192*adfc5217SJeff Kirsher GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1193*adfc5217SJeff Kirsher function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1194*adfc5217SJeff Kirsher Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1195*adfc5217SJeff Kirsher SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X 1196*adfc5217SJeff Kirsher indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 1197*adfc5217SJeff Kirsher [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 1198*adfc5217SJeff Kirsher SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 1199*adfc5217SJeff Kirsher TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 1200*adfc5217SJeff Kirsher TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1201*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc 1202*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c 1203*adfc5217SJeff Kirsher /* [RW 32] second 32b for enabling the output for function 0 output0. mapped 1204*adfc5217SJeff Kirsher as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1205*adfc5217SJeff Kirsher Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1206*adfc5217SJeff Kirsher interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1207*adfc5217SJeff Kirsher error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1208*adfc5217SJeff Kirsher interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1209*adfc5217SJeff Kirsher NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1210*adfc5217SJeff Kirsher [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1211*adfc5217SJeff Kirsher interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1212*adfc5217SJeff Kirsher Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1213*adfc5217SJeff Kirsher Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1214*adfc5217SJeff Kirsher Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1215*adfc5217SJeff Kirsher interrupt; */ 1216*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070 1217*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080 1218*adfc5217SJeff Kirsher /* [RW 32] second 32b for enabling the output for function 1 output0. mapped 1219*adfc5217SJeff Kirsher as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1220*adfc5217SJeff Kirsher Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1221*adfc5217SJeff Kirsher interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1222*adfc5217SJeff Kirsher error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1223*adfc5217SJeff Kirsher interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1224*adfc5217SJeff Kirsher NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1225*adfc5217SJeff Kirsher [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1226*adfc5217SJeff Kirsher interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1227*adfc5217SJeff Kirsher Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1228*adfc5217SJeff Kirsher Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1229*adfc5217SJeff Kirsher Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1230*adfc5217SJeff Kirsher interrupt; */ 1231*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110 1232*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120 1233*adfc5217SJeff Kirsher /* [RW 32] second 32b for enabling the output for close the gate nig. mapped 1234*adfc5217SJeff Kirsher as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1235*adfc5217SJeff Kirsher Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1236*adfc5217SJeff Kirsher interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1237*adfc5217SJeff Kirsher error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1238*adfc5217SJeff Kirsher interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1239*adfc5217SJeff Kirsher NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1240*adfc5217SJeff Kirsher [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1241*adfc5217SJeff Kirsher interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1242*adfc5217SJeff Kirsher Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1243*adfc5217SJeff Kirsher Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1244*adfc5217SJeff Kirsher Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1245*adfc5217SJeff Kirsher interrupt; */ 1246*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0 1247*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE2_NIG_1 0xa190 1248*adfc5217SJeff Kirsher /* [RW 32] second 32b for enabling the output for close the gate pxp. mapped 1249*adfc5217SJeff Kirsher as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1250*adfc5217SJeff Kirsher Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1251*adfc5217SJeff Kirsher interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1252*adfc5217SJeff Kirsher error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1253*adfc5217SJeff Kirsher interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1254*adfc5217SJeff Kirsher NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1255*adfc5217SJeff Kirsher [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1256*adfc5217SJeff Kirsher interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1257*adfc5217SJeff Kirsher Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1258*adfc5217SJeff Kirsher Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1259*adfc5217SJeff Kirsher Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1260*adfc5217SJeff Kirsher interrupt; */ 1261*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE2_PXP_0 0xa100 1262*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0 1263*adfc5217SJeff Kirsher /* [RW 32] third 32b for enabling the output for function 0 output0. mapped 1264*adfc5217SJeff Kirsher as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP 1265*adfc5217SJeff Kirsher Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; 1266*adfc5217SJeff Kirsher [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1267*adfc5217SJeff Kirsher interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1268*adfc5217SJeff Kirsher error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1269*adfc5217SJeff Kirsher Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1270*adfc5217SJeff Kirsher pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1271*adfc5217SJeff Kirsher MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1272*adfc5217SJeff Kirsher SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1273*adfc5217SJeff Kirsher timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1274*adfc5217SJeff Kirsher func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1275*adfc5217SJeff Kirsher attn1; */ 1276*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074 1277*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084 1278*adfc5217SJeff Kirsher /* [RW 32] third 32b for enabling the output for function 1 output0. mapped 1279*adfc5217SJeff Kirsher as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP 1280*adfc5217SJeff Kirsher Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; 1281*adfc5217SJeff Kirsher [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1282*adfc5217SJeff Kirsher interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1283*adfc5217SJeff Kirsher error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1284*adfc5217SJeff Kirsher Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1285*adfc5217SJeff Kirsher pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1286*adfc5217SJeff Kirsher MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1287*adfc5217SJeff Kirsher SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1288*adfc5217SJeff Kirsher timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1289*adfc5217SJeff Kirsher func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1290*adfc5217SJeff Kirsher attn1; */ 1291*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114 1292*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124 1293*adfc5217SJeff Kirsher /* [RW 32] third 32b for enabling the output for close the gate nig. mapped 1294*adfc5217SJeff Kirsher as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP 1295*adfc5217SJeff Kirsher Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; 1296*adfc5217SJeff Kirsher [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1297*adfc5217SJeff Kirsher interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1298*adfc5217SJeff Kirsher error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1299*adfc5217SJeff Kirsher Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1300*adfc5217SJeff Kirsher pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1301*adfc5217SJeff Kirsher MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1302*adfc5217SJeff Kirsher SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1303*adfc5217SJeff Kirsher timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1304*adfc5217SJeff Kirsher func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1305*adfc5217SJeff Kirsher attn1; */ 1306*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4 1307*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE3_NIG_1 0xa194 1308*adfc5217SJeff Kirsher /* [RW 32] third 32b for enabling the output for close the gate pxp. mapped 1309*adfc5217SJeff Kirsher as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP 1310*adfc5217SJeff Kirsher Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; 1311*adfc5217SJeff Kirsher [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1312*adfc5217SJeff Kirsher interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1313*adfc5217SJeff Kirsher error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1314*adfc5217SJeff Kirsher Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1315*adfc5217SJeff Kirsher pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1316*adfc5217SJeff Kirsher MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1317*adfc5217SJeff Kirsher SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1318*adfc5217SJeff Kirsher timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1319*adfc5217SJeff Kirsher func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1320*adfc5217SJeff Kirsher attn1; */ 1321*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE3_PXP_0 0xa104 1322*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4 1323*adfc5217SJeff Kirsher /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped 1324*adfc5217SJeff Kirsher as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1325*adfc5217SJeff Kirsher General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1326*adfc5217SJeff Kirsher [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1327*adfc5217SJeff Kirsher attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1328*adfc5217SJeff Kirsher [14] General attn16; [15] General attn17; [16] General attn18; [17] 1329*adfc5217SJeff Kirsher General attn19; [18] General attn20; [19] General attn21; [20] Main power 1330*adfc5217SJeff Kirsher interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1331*adfc5217SJeff Kirsher Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1332*adfc5217SJeff Kirsher Latched timeout attention; [27] GRC Latched reserved access attention; 1333*adfc5217SJeff Kirsher [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1334*adfc5217SJeff Kirsher Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1335*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078 1336*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098 1337*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8 1338*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8 1339*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8 1340*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8 1341*adfc5217SJeff Kirsher /* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped 1342*adfc5217SJeff Kirsher as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1343*adfc5217SJeff Kirsher General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1344*adfc5217SJeff Kirsher [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1345*adfc5217SJeff Kirsher attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1346*adfc5217SJeff Kirsher [14] General attn16; [15] General attn17; [16] General attn18; [17] 1347*adfc5217SJeff Kirsher General attn19; [18] General attn20; [19] General attn21; [20] Main power 1348*adfc5217SJeff Kirsher interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1349*adfc5217SJeff Kirsher Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1350*adfc5217SJeff Kirsher Latched timeout attention; [27] GRC Latched reserved access attention; 1351*adfc5217SJeff Kirsher [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1352*adfc5217SJeff Kirsher Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1353*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118 1354*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138 1355*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158 1356*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168 1357*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178 1358*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188 1359*adfc5217SJeff Kirsher /* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped 1360*adfc5217SJeff Kirsher as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1361*adfc5217SJeff Kirsher General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1362*adfc5217SJeff Kirsher [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1363*adfc5217SJeff Kirsher attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1364*adfc5217SJeff Kirsher [14] General attn16; [15] General attn17; [16] General attn18; [17] 1365*adfc5217SJeff Kirsher General attn19; [18] General attn20; [19] General attn21; [20] Main power 1366*adfc5217SJeff Kirsher interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1367*adfc5217SJeff Kirsher Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1368*adfc5217SJeff Kirsher Latched timeout attention; [27] GRC Latched reserved access attention; 1369*adfc5217SJeff Kirsher [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1370*adfc5217SJeff Kirsher Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1371*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8 1372*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE4_NIG_1 0xa198 1373*adfc5217SJeff Kirsher /* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped 1374*adfc5217SJeff Kirsher as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1375*adfc5217SJeff Kirsher General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1376*adfc5217SJeff Kirsher [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1377*adfc5217SJeff Kirsher attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1378*adfc5217SJeff Kirsher [14] General attn16; [15] General attn17; [16] General attn18; [17] 1379*adfc5217SJeff Kirsher General attn19; [18] General attn20; [19] General attn21; [20] Main power 1380*adfc5217SJeff Kirsher interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1381*adfc5217SJeff Kirsher Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1382*adfc5217SJeff Kirsher Latched timeout attention; [27] GRC Latched reserved access attention; 1383*adfc5217SJeff Kirsher [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1384*adfc5217SJeff Kirsher Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1385*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108 1386*adfc5217SJeff Kirsher #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8 1387*adfc5217SJeff Kirsher /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu 1388*adfc5217SJeff Kirsher 128 bit vector */ 1389*adfc5217SJeff Kirsher #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000 1390*adfc5217SJeff Kirsher #define MISC_REG_AEU_GENERAL_ATTN_1 0xa004 1391*adfc5217SJeff Kirsher #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028 1392*adfc5217SJeff Kirsher #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c 1393*adfc5217SJeff Kirsher #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030 1394*adfc5217SJeff Kirsher #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008 1395*adfc5217SJeff Kirsher #define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c 1396*adfc5217SJeff Kirsher #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010 1397*adfc5217SJeff Kirsher #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014 1398*adfc5217SJeff Kirsher #define MISC_REG_AEU_GENERAL_ATTN_6 0xa018 1399*adfc5217SJeff Kirsher #define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c 1400*adfc5217SJeff Kirsher #define MISC_REG_AEU_GENERAL_ATTN_8 0xa020 1401*adfc5217SJeff Kirsher #define MISC_REG_AEU_GENERAL_ATTN_9 0xa024 1402*adfc5217SJeff Kirsher #define MISC_REG_AEU_GENERAL_MASK 0xa61c 1403*adfc5217SJeff Kirsher /* [RW 32] first 32b for inverting the input for function 0; for each bit: 1404*adfc5217SJeff Kirsher 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for 1405*adfc5217SJeff Kirsher function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; 1406*adfc5217SJeff Kirsher [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; 1407*adfc5217SJeff Kirsher [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1408*adfc5217SJeff Kirsher function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1409*adfc5217SJeff Kirsher Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1410*adfc5217SJeff Kirsher SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication 1411*adfc5217SJeff Kirsher for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS 1412*adfc5217SJeff Kirsher Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw 1413*adfc5217SJeff Kirsher interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM 1414*adfc5217SJeff Kirsher Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI 1415*adfc5217SJeff Kirsher Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1416*adfc5217SJeff Kirsher #define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c 1417*adfc5217SJeff Kirsher #define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c 1418*adfc5217SJeff Kirsher /* [RW 32] second 32b for inverting the input for function 0; for each bit: 1419*adfc5217SJeff Kirsher 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity 1420*adfc5217SJeff Kirsher error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw 1421*adfc5217SJeff Kirsher interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM 1422*adfc5217SJeff Kirsher Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw 1423*adfc5217SJeff Kirsher interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] 1424*adfc5217SJeff Kirsher DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity 1425*adfc5217SJeff Kirsher error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux 1426*adfc5217SJeff Kirsher PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; 1427*adfc5217SJeff Kirsher [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; 1428*adfc5217SJeff Kirsher [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; 1429*adfc5217SJeff Kirsher [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; 1430*adfc5217SJeff Kirsher [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */ 1431*adfc5217SJeff Kirsher #define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230 1432*adfc5217SJeff Kirsher #define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240 1433*adfc5217SJeff Kirsher /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0; 1434*adfc5217SJeff Kirsher [9:8] = raserved. Zero = mask; one = unmask */ 1435*adfc5217SJeff Kirsher #define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060 1436*adfc5217SJeff Kirsher #define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064 1437*adfc5217SJeff Kirsher /* [RW 1] If set a system kill occurred */ 1438*adfc5217SJeff Kirsher #define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610 1439*adfc5217SJeff Kirsher /* [RW 32] Represent the status of the input vector to the AEU when a system 1440*adfc5217SJeff Kirsher kill occurred. The register is reset in por reset. Mapped as follows: [0] 1441*adfc5217SJeff Kirsher NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 1442*adfc5217SJeff Kirsher mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; 1443*adfc5217SJeff Kirsher [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] 1444*adfc5217SJeff Kirsher PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event 1445*adfc5217SJeff Kirsher function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP 1446*adfc5217SJeff Kirsher Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for 1447*adfc5217SJeff Kirsher mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] 1448*adfc5217SJeff Kirsher BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC 1449*adfc5217SJeff Kirsher Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw 1450*adfc5217SJeff Kirsher interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI 1451*adfc5217SJeff Kirsher Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw 1452*adfc5217SJeff Kirsher interrupt; */ 1453*adfc5217SJeff Kirsher #define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600 1454*adfc5217SJeff Kirsher #define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604 1455*adfc5217SJeff Kirsher #define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608 1456*adfc5217SJeff Kirsher #define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c 1457*adfc5217SJeff Kirsher /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1 1458*adfc5217SJeff Kirsher Port. */ 1459*adfc5217SJeff Kirsher #define MISC_REG_BOND_ID 0xa400 1460*adfc5217SJeff Kirsher /* [R 8] These bits indicate the metal revision of the chip. This value 1461*adfc5217SJeff Kirsher starts at 0x00 for each all-layer tape-out and increments by one for each 1462*adfc5217SJeff Kirsher tape-out. */ 1463*adfc5217SJeff Kirsher #define MISC_REG_CHIP_METAL 0xa404 1464*adfc5217SJeff Kirsher /* [R 16] These bits indicate the part number for the chip. */ 1465*adfc5217SJeff Kirsher #define MISC_REG_CHIP_NUM 0xa408 1466*adfc5217SJeff Kirsher /* [R 4] These bits indicate the base revision of the chip. This value 1467*adfc5217SJeff Kirsher starts at 0x0 for the A0 tape-out and increments by one for each 1468*adfc5217SJeff Kirsher all-layer tape-out. */ 1469*adfc5217SJeff Kirsher #define MISC_REG_CHIP_REV 0xa40c 1470*adfc5217SJeff Kirsher /* [RW 32] The following driver registers(1...16) represent 16 drivers and 1471*adfc5217SJeff Kirsher 32 clients. Each client can be controlled by one driver only. One in each 1472*adfc5217SJeff Kirsher bit represent that this driver control the appropriate client (Ex: bit 5 1473*adfc5217SJeff Kirsher is set means this driver control client number 5). addr1 = set; addr0 = 1474*adfc5217SJeff Kirsher clear; read from both addresses will give the same result = status. write 1475*adfc5217SJeff Kirsher to address 1 will set a request to control all the clients that their 1476*adfc5217SJeff Kirsher appropriate bit (in the write command) is set. if the client is free (the 1477*adfc5217SJeff Kirsher appropriate bit in all the other drivers is clear) one will be written to 1478*adfc5217SJeff Kirsher that driver register; if the client isn't free the bit will remain zero. 1479*adfc5217SJeff Kirsher if the appropriate bit is set (the driver request to gain control on a 1480*adfc5217SJeff Kirsher client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW 1481*adfc5217SJeff Kirsher interrupt will be asserted). write to address 0 will set a request to 1482*adfc5217SJeff Kirsher free all the clients that their appropriate bit (in the write command) is 1483*adfc5217SJeff Kirsher set. if the appropriate bit is clear (the driver request to free a client 1484*adfc5217SJeff Kirsher it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will 1485*adfc5217SJeff Kirsher be asserted). */ 1486*adfc5217SJeff Kirsher #define MISC_REG_DRIVER_CONTROL_1 0xa510 1487*adfc5217SJeff Kirsher #define MISC_REG_DRIVER_CONTROL_7 0xa3c8 1488*adfc5217SJeff Kirsher /* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0 1489*adfc5217SJeff Kirsher only. */ 1490*adfc5217SJeff Kirsher #define MISC_REG_E1HMF_MODE 0xa5f8 1491*adfc5217SJeff Kirsher /* [R 1] Status of four port mode path swap input pin. */ 1492*adfc5217SJeff Kirsher #define MISC_REG_FOUR_PORT_PATH_SWAP 0xa75c 1493*adfc5217SJeff Kirsher /* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 - 1494*adfc5217SJeff Kirsher the path_swap output is equal to 4 port mode path swap input pin; if it 1495*adfc5217SJeff Kirsher is 1 - the path_swap output is equal to bit[1] of this register; [1] - 1496*adfc5217SJeff Kirsher Overwrite value. If bit[0] of this register is 1 this is the value that 1497*adfc5217SJeff Kirsher receives the path_swap output. Reset on Hard reset. */ 1498*adfc5217SJeff Kirsher #define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR 0xa738 1499*adfc5217SJeff Kirsher /* [R 1] Status of 4 port mode port swap input pin. */ 1500*adfc5217SJeff Kirsher #define MISC_REG_FOUR_PORT_PORT_SWAP 0xa754 1501*adfc5217SJeff Kirsher /* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 - 1502*adfc5217SJeff Kirsher the port_swap output is equal to 4 port mode port swap input pin; if it 1503*adfc5217SJeff Kirsher is 1 - the port_swap output is equal to bit[1] of this register; [1] - 1504*adfc5217SJeff Kirsher Overwrite value. If bit[0] of this register is 1 this is the value that 1505*adfc5217SJeff Kirsher receives the port_swap output. Reset on Hard reset. */ 1506*adfc5217SJeff Kirsher #define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR 0xa734 1507*adfc5217SJeff Kirsher /* [RW 32] Debug only: spare RW register reset by core reset */ 1508*adfc5217SJeff Kirsher #define MISC_REG_GENERIC_CR_0 0xa460 1509*adfc5217SJeff Kirsher #define MISC_REG_GENERIC_CR_1 0xa464 1510*adfc5217SJeff Kirsher /* [RW 32] Debug only: spare RW register reset by por reset */ 1511*adfc5217SJeff Kirsher #define MISC_REG_GENERIC_POR_1 0xa474 1512*adfc5217SJeff Kirsher /* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to 1513*adfc5217SJeff Kirsher use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO 1514*adfc5217SJeff Kirsher can not be configured as an output. Each output has its output enable in 1515*adfc5217SJeff Kirsher the MCP register space; but this bit needs to be set to make use of that. 1516*adfc5217SJeff Kirsher Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When 1517*adfc5217SJeff Kirsher set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON. 1518*adfc5217SJeff Kirsher When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change 1519*adfc5217SJeff Kirsher the i/o to an output and will drive the TimeSync output. Bit[31:7]: 1520*adfc5217SJeff Kirsher spare. Global register. Reset by hard reset. */ 1521*adfc5217SJeff Kirsher #define MISC_REG_GEN_PURP_HWG 0xa9a0 1522*adfc5217SJeff Kirsher /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of 1523*adfc5217SJeff Kirsher these bits is written as a '1'; the corresponding SPIO bit will turn off 1524*adfc5217SJeff Kirsher it's drivers and become an input. This is the reset state of all GPIO 1525*adfc5217SJeff Kirsher pins. The read value of these bits will be a '1' if that last command 1526*adfc5217SJeff Kirsher (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff). 1527*adfc5217SJeff Kirsher [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written 1528*adfc5217SJeff Kirsher as a '1'; the corresponding GPIO bit will drive low. The read value of 1529*adfc5217SJeff Kirsher these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for 1530*adfc5217SJeff Kirsher this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0; 1531*adfc5217SJeff Kirsher SET When any of these bits is written as a '1'; the corresponding GPIO 1532*adfc5217SJeff Kirsher bit will drive high (if it has that capability). The read value of these 1533*adfc5217SJeff Kirsher bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this 1534*adfc5217SJeff Kirsher bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0; 1535*adfc5217SJeff Kirsher RO; These bits indicate the read value of each of the eight GPIO pins. 1536*adfc5217SJeff Kirsher This is the result value of the pin; not the drive value. Writing these 1537*adfc5217SJeff Kirsher bits will have not effect. */ 1538*adfc5217SJeff Kirsher #define MISC_REG_GPIO 0xa490 1539*adfc5217SJeff Kirsher /* [RW 8] These bits enable the GPIO_INTs to signals event to the 1540*adfc5217SJeff Kirsher IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2] 1541*adfc5217SJeff Kirsher p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2; 1542*adfc5217SJeff Kirsher [7] p1_gpio_3; */ 1543*adfc5217SJeff Kirsher #define MISC_REG_GPIO_EVENT_EN 0xa2bc 1544*adfc5217SJeff Kirsher /* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a 1545*adfc5217SJeff Kirsher '1' to these bit clears the corresponding bit in the #OLD_VALUE register. 1546*adfc5217SJeff Kirsher This will acknowledge an interrupt on the falling edge of corresponding 1547*adfc5217SJeff Kirsher GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0; 1548*adfc5217SJeff Kirsher Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE 1549*adfc5217SJeff Kirsher register. This will acknowledge an interrupt on the rising edge of 1550*adfc5217SJeff Kirsher corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1; 1551*adfc5217SJeff Kirsher OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input 1552*adfc5217SJeff Kirsher value. When the ~INT_STATE bit is set; this bit indicates the OLD value 1553*adfc5217SJeff Kirsher of the pin such that if ~INT_STATE is set and this bit is '0'; then the 1554*adfc5217SJeff Kirsher interrupt is due to a low to high edge. If ~INT_STATE is set and this bit 1555*adfc5217SJeff Kirsher is '1'; then the interrupt is due to a high to low edge (reset value 0). 1556*adfc5217SJeff Kirsher [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the 1557*adfc5217SJeff Kirsher current GPIO interrupt state for each GPIO pin. This bit is cleared when 1558*adfc5217SJeff Kirsher the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is 1559*adfc5217SJeff Kirsher set when the GPIO input does not match the current value in #OLD_VALUE 1560*adfc5217SJeff Kirsher (reset value 0). */ 1561*adfc5217SJeff Kirsher #define MISC_REG_GPIO_INT 0xa494 1562*adfc5217SJeff Kirsher /* [R 28] this field hold the last information that caused reserved 1563*adfc5217SJeff Kirsher attention. bits [19:0] - address; [22:20] function; [23] reserved; 1564*adfc5217SJeff Kirsher [27:24] the master that caused the attention - according to the following 1565*adfc5217SJeff Kirsher encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = 1566*adfc5217SJeff Kirsher dbu; 8 = dmae */ 1567*adfc5217SJeff Kirsher #define MISC_REG_GRC_RSV_ATTN 0xa3c0 1568*adfc5217SJeff Kirsher /* [R 28] this field hold the last information that caused timeout 1569*adfc5217SJeff Kirsher attention. bits [19:0] - address; [22:20] function; [23] reserved; 1570*adfc5217SJeff Kirsher [27:24] the master that caused the attention - according to the following 1571*adfc5217SJeff Kirsher encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = 1572*adfc5217SJeff Kirsher dbu; 8 = dmae */ 1573*adfc5217SJeff Kirsher #define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4 1574*adfc5217SJeff Kirsher /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any 1575*adfc5217SJeff Kirsher access that does not finish within 1576*adfc5217SJeff Kirsher ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is 1577*adfc5217SJeff Kirsher cleared; this timeout is disabled. If this timeout occurs; the GRC shall 1578*adfc5217SJeff Kirsher assert it attention output. */ 1579*adfc5217SJeff Kirsher #define MISC_REG_GRC_TIMEOUT_EN 0xa280 1580*adfc5217SJeff Kirsher /* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of 1581*adfc5217SJeff Kirsher the bits is: [2:0] OAC reset value 001) CML output buffer bias control; 1582*adfc5217SJeff Kirsher 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl 1583*adfc5217SJeff Kirsher (reset value 001) Charge pump current control; 111 for 720u; 011 for 1584*adfc5217SJeff Kirsher 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00) 1585*adfc5217SJeff Kirsher Global bias control; When bit 7 is high bias current will be 10 0gh; When 1586*adfc5217SJeff Kirsher bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8] 1587*adfc5217SJeff Kirsher Pll_observe (reset value 010) Bits to control observability. bit 10 is 1588*adfc5217SJeff Kirsher for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl 1589*adfc5217SJeff Kirsher (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V 1590*adfc5217SJeff Kirsher and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning 1591*adfc5217SJeff Kirsher sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted 1592*adfc5217SJeff Kirsher internally). [14] reserved (reset value 0) Reset for VCO sequencer is 1593*adfc5217SJeff Kirsher connected to RESET input directly. [15] capRetry_en (reset value 0) 1594*adfc5217SJeff Kirsher enable retry on cap search failure (inverted). [16] freqMonitor_e (reset 1595*adfc5217SJeff Kirsher value 0) bit to continuously monitor vco freq (inverted). [17] 1596*adfc5217SJeff Kirsher freqDetRestart_en (reset value 0) bit to enable restart when not freq 1597*adfc5217SJeff Kirsher locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable 1598*adfc5217SJeff Kirsher retry on freq det failure(inverted). [19] pllForceFdone_en (reset value 1599*adfc5217SJeff Kirsher 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20] 1600*adfc5217SJeff Kirsher pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass 1601*adfc5217SJeff Kirsher (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value 1602*adfc5217SJeff Kirsher 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0) 1603*adfc5217SJeff Kirsher bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to 1604*adfc5217SJeff Kirsher enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force 1605*adfc5217SJeff Kirsher capPass. [26] capRestart (reset value 0) bit to force cap sequencer to 1606*adfc5217SJeff Kirsher restart. [27] capSelectM_en (reset value 0) bit to enable cap select 1607*adfc5217SJeff Kirsher register bits. */ 1608*adfc5217SJeff Kirsher #define MISC_REG_LCPLL_CTRL_1 0xa2a4 1609*adfc5217SJeff Kirsher #define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8 1610*adfc5217SJeff Kirsher /* [RW 4] Interrupt mask register #0 read/write */ 1611*adfc5217SJeff Kirsher #define MISC_REG_MISC_INT_MASK 0xa388 1612*adfc5217SJeff Kirsher /* [RW 1] Parity mask register #0 read/write */ 1613*adfc5217SJeff Kirsher #define MISC_REG_MISC_PRTY_MASK 0xa398 1614*adfc5217SJeff Kirsher /* [R 1] Parity register #0 read */ 1615*adfc5217SJeff Kirsher #define MISC_REG_MISC_PRTY_STS 0xa38c 1616*adfc5217SJeff Kirsher /* [RC 1] Parity register #0 read clear */ 1617*adfc5217SJeff Kirsher #define MISC_REG_MISC_PRTY_STS_CLR 0xa390 1618*adfc5217SJeff Kirsher #define MISC_REG_NIG_WOL_P0 0xa270 1619*adfc5217SJeff Kirsher #define MISC_REG_NIG_WOL_P1 0xa274 1620*adfc5217SJeff Kirsher /* [R 1] If set indicate that the pcie_rst_b was asserted without perst 1621*adfc5217SJeff Kirsher assertion */ 1622*adfc5217SJeff Kirsher #define MISC_REG_PCIE_HOT_RESET 0xa618 1623*adfc5217SJeff Kirsher /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911. 1624*adfc5217SJeff Kirsher inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1 1625*adfc5217SJeff Kirsher divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1 1626*adfc5217SJeff Kirsher divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2 1627*adfc5217SJeff Kirsher divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2 1628*adfc5217SJeff Kirsher divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9] 1629*adfc5217SJeff Kirsher freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1] 1630*adfc5217SJeff Kirsher (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value 1631*adfc5217SJeff Kirsher 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16] 1632*adfc5217SJeff Kirsher Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset 1633*adfc5217SJeff Kirsher value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value 1634*adfc5217SJeff Kirsher 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0); 1635*adfc5217SJeff Kirsher [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25] 1636*adfc5217SJeff Kirsher Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27] 1637*adfc5217SJeff Kirsher testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29] 1638*adfc5217SJeff Kirsher testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31] 1639*adfc5217SJeff Kirsher testa_en (reset value 0); */ 1640*adfc5217SJeff Kirsher #define MISC_REG_PLL_STORM_CTRL_1 0xa294 1641*adfc5217SJeff Kirsher #define MISC_REG_PLL_STORM_CTRL_2 0xa298 1642*adfc5217SJeff Kirsher #define MISC_REG_PLL_STORM_CTRL_3 0xa29c 1643*adfc5217SJeff Kirsher #define MISC_REG_PLL_STORM_CTRL_4 0xa2a0 1644*adfc5217SJeff Kirsher /* [R 1] Status of 4 port mode enable input pin. */ 1645*adfc5217SJeff Kirsher #define MISC_REG_PORT4MODE_EN 0xa750 1646*adfc5217SJeff Kirsher /* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 - 1647*adfc5217SJeff Kirsher * the port4mode_en output is equal to 4 port mode input pin; if it is 1 - 1648*adfc5217SJeff Kirsher * the port4mode_en output is equal to bit[1] of this register; [1] - 1649*adfc5217SJeff Kirsher * Overwrite value. If bit[0] of this register is 1 this is the value that 1650*adfc5217SJeff Kirsher * receives the port4mode_en output . */ 1651*adfc5217SJeff Kirsher #define MISC_REG_PORT4MODE_EN_OVWR 0xa720 1652*adfc5217SJeff Kirsher /* [RW 32] reset reg#2; rite/read one = the specific block is out of reset; 1653*adfc5217SJeff Kirsher write/read zero = the specific block is in reset; addr 0-wr- the write 1654*adfc5217SJeff Kirsher value will be written to the register; addr 1-set - one will be written 1655*adfc5217SJeff Kirsher to all the bits that have the value of one in the data written (bits that 1656*adfc5217SJeff Kirsher have the value of zero will not be change) ; addr 2-clear - zero will be 1657*adfc5217SJeff Kirsher written to all the bits that have the value of one in the data written 1658*adfc5217SJeff Kirsher (bits that have the value of zero will not be change); addr 3-ignore; 1659*adfc5217SJeff Kirsher read ignore from all addr except addr 00; inside order of the bits is: 1660*adfc5217SJeff Kirsher [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc; 1661*adfc5217SJeff Kirsher [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7] 1662*adfc5217SJeff Kirsher rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn; 1663*adfc5217SJeff Kirsher [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13] 1664*adfc5217SJeff Kirsher Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16] 1665*adfc5217SJeff Kirsher rst_pxp_rq_rd_wr; 31:17] reserved */ 1666*adfc5217SJeff Kirsher #define MISC_REG_RESET_REG_2 0xa590 1667*adfc5217SJeff Kirsher /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is 1668*adfc5217SJeff Kirsher shared with the driver resides */ 1669*adfc5217SJeff Kirsher #define MISC_REG_SHARED_MEM_ADDR 0xa2b4 1670*adfc5217SJeff Kirsher /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1'; 1671*adfc5217SJeff Kirsher the corresponding SPIO bit will turn off it's drivers and become an 1672*adfc5217SJeff Kirsher input. This is the reset state of all SPIO pins. The read value of these 1673*adfc5217SJeff Kirsher bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this 1674*adfc5217SJeff Kirsher bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits 1675*adfc5217SJeff Kirsher is written as a '1'; the corresponding SPIO bit will drive low. The read 1676*adfc5217SJeff Kirsher value of these bits will be a '1' if that last command (#SET; #CLR; or 1677*adfc5217SJeff Kirsher #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of 1678*adfc5217SJeff Kirsher these bits is written as a '1'; the corresponding SPIO bit will drive 1679*adfc5217SJeff Kirsher high (if it has that capability). The read value of these bits will be a 1680*adfc5217SJeff Kirsher '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET. 1681*adfc5217SJeff Kirsher (reset value 0). [7-0] VALUE RO; These bits indicate the read value of 1682*adfc5217SJeff Kirsher each of the eight SPIO pins. This is the result value of the pin; not the 1683*adfc5217SJeff Kirsher drive value. Writing these bits will have not effect. Each 8 bits field 1684*adfc5217SJeff Kirsher is divided as follows: [0] VAUX Enable; when pulsed low; enables supply 1685*adfc5217SJeff Kirsher from VAUX. (This is an output pin only; the FLOAT field is not applicable 1686*adfc5217SJeff Kirsher for this pin); [1] VAUX Disable; when pulsed low; disables supply form 1687*adfc5217SJeff Kirsher VAUX. (This is an output pin only; FLOAT field is not applicable for this 1688*adfc5217SJeff Kirsher pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to 1689*adfc5217SJeff Kirsher select VAUX supply. (This is an output pin only; it is not controlled by 1690*adfc5217SJeff Kirsher the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT 1691*adfc5217SJeff Kirsher field is not applicable for this pin; only the VALUE fields is relevant - 1692*adfc5217SJeff Kirsher it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6] 1693*adfc5217SJeff Kirsher Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP 1694*adfc5217SJeff Kirsher device ID select; read by UMP firmware. */ 1695*adfc5217SJeff Kirsher #define MISC_REG_SPIO 0xa4fc 1696*adfc5217SJeff Kirsher /* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC. 1697*adfc5217SJeff Kirsher according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5; 1698*adfc5217SJeff Kirsher [7:0] reserved */ 1699*adfc5217SJeff Kirsher #define MISC_REG_SPIO_EVENT_EN 0xa2b8 1700*adfc5217SJeff Kirsher /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the 1701*adfc5217SJeff Kirsher corresponding bit in the #OLD_VALUE register. This will acknowledge an 1702*adfc5217SJeff Kirsher interrupt on the falling edge of corresponding SPIO input (reset value 1703*adfc5217SJeff Kirsher 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit 1704*adfc5217SJeff Kirsher in the #OLD_VALUE register. This will acknowledge an interrupt on the 1705*adfc5217SJeff Kirsher rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE 1706*adfc5217SJeff Kirsher RO; These bits indicate the old value of the SPIO input value. When the 1707*adfc5217SJeff Kirsher ~INT_STATE bit is set; this bit indicates the OLD value of the pin such 1708*adfc5217SJeff Kirsher that if ~INT_STATE is set and this bit is '0'; then the interrupt is due 1709*adfc5217SJeff Kirsher to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the 1710*adfc5217SJeff Kirsher interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE 1711*adfc5217SJeff Kirsher RO; These bits indicate the current SPIO interrupt state for each SPIO 1712*adfc5217SJeff Kirsher pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR 1713*adfc5217SJeff Kirsher command bit is written. This bit is set when the SPIO input does not 1714*adfc5217SJeff Kirsher match the current value in #OLD_VALUE (reset value 0). */ 1715*adfc5217SJeff Kirsher #define MISC_REG_SPIO_INT 0xa500 1716*adfc5217SJeff Kirsher /* [RW 32] reload value for counter 4 if reload; the value will be reload if 1717*adfc5217SJeff Kirsher the counter reached zero and the reload bit 1718*adfc5217SJeff Kirsher (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */ 1719*adfc5217SJeff Kirsher #define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc 1720*adfc5217SJeff Kirsher /* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses 1721*adfc5217SJeff Kirsher in this register. address 0 - timer 1; address 1 - timer 2, ... address 7 - 1722*adfc5217SJeff Kirsher timer 8 */ 1723*adfc5217SJeff Kirsher #define MISC_REG_SW_TIMER_VAL 0xa5c0 1724*adfc5217SJeff Kirsher /* [R 1] Status of two port mode path swap input pin. */ 1725*adfc5217SJeff Kirsher #define MISC_REG_TWO_PORT_PATH_SWAP 0xa758 1726*adfc5217SJeff Kirsher /* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the 1727*adfc5217SJeff Kirsher path_swap output is equal to 2 port mode path swap input pin; if it is 1 1728*adfc5217SJeff Kirsher - the path_swap output is equal to bit[1] of this register; [1] - 1729*adfc5217SJeff Kirsher Overwrite value. If bit[0] of this register is 1 this is the value that 1730*adfc5217SJeff Kirsher receives the path_swap output. Reset on Hard reset. */ 1731*adfc5217SJeff Kirsher #define MISC_REG_TWO_PORT_PATH_SWAP_OVWR 0xa72c 1732*adfc5217SJeff Kirsher /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are 1733*adfc5217SJeff Kirsher loaded; 0-prepare; -unprepare */ 1734*adfc5217SJeff Kirsher #define MISC_REG_UNPREPARED 0xa424 1735*adfc5217SJeff Kirsher #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0) 1736*adfc5217SJeff Kirsher #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1) 1737*adfc5217SJeff Kirsher #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4) 1738*adfc5217SJeff Kirsher #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2) 1739*adfc5217SJeff Kirsher #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3) 1740*adfc5217SJeff Kirsher /* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or 1741*adfc5217SJeff Kirsher * not it is the recipient of the message on the MDIO interface. The value 1742*adfc5217SJeff Kirsher * is compared to the value on ctrl_md_devad. Drives output 1743*adfc5217SJeff Kirsher * misc_xgxs0_phy_addr. Global register. */ 1744*adfc5217SJeff Kirsher #define MISC_REG_WC0_CTRL_PHY_ADDR 0xa9cc 1745*adfc5217SJeff Kirsher /* [RW 2] XMAC Core port mode. Indicates the number of ports on the system 1746*adfc5217SJeff Kirsher side. This should be less than or equal to phy_port_mode; if some of the 1747*adfc5217SJeff Kirsher ports are not used. This enables reduction of frequency on the core side. 1748*adfc5217SJeff Kirsher This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 - 1749*adfc5217SJeff Kirsher Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap 1750*adfc5217SJeff Kirsher input for the XMAC_MP core; and should be changed only while reset is 1751*adfc5217SJeff Kirsher held low. Reset on Hard reset. */ 1752*adfc5217SJeff Kirsher #define MISC_REG_XMAC_CORE_PORT_MODE 0xa964 1753*adfc5217SJeff Kirsher /* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp 1754*adfc5217SJeff Kirsher Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 1755*adfc5217SJeff Kirsher 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the 1756*adfc5217SJeff Kirsher XMAC_MP core; and should be changed only while reset is held low. Reset 1757*adfc5217SJeff Kirsher on Hard reset. */ 1758*adfc5217SJeff Kirsher #define MISC_REG_XMAC_PHY_PORT_MODE 0xa960 1759*adfc5217SJeff Kirsher /* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0. 1760*adfc5217SJeff Kirsher * Reads from this register will clear bits 31:0. */ 1761*adfc5217SJeff Kirsher #define MSTAT_REG_RX_STAT_GR64_LO 0x200 1762*adfc5217SJeff Kirsher /* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits 1763*adfc5217SJeff Kirsher * 31:0. Reads from this register will clear bits 31:0. */ 1764*adfc5217SJeff Kirsher #define MSTAT_REG_TX_STAT_GTXPOK_LO 0 1765*adfc5217SJeff Kirsher #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0) 1766*adfc5217SJeff Kirsher #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1) 1767*adfc5217SJeff Kirsher #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4) 1768*adfc5217SJeff Kirsher #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2) 1769*adfc5217SJeff Kirsher #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3) 1770*adfc5217SJeff Kirsher #define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0) 1771*adfc5217SJeff Kirsher #define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0) 1772*adfc5217SJeff Kirsher #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0) 1773*adfc5217SJeff Kirsher #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9) 1774*adfc5217SJeff Kirsher #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15) 1775*adfc5217SJeff Kirsher #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18) 1776*adfc5217SJeff Kirsher /* [RW 1] Input enable for RX_BMAC0 IF */ 1777*adfc5217SJeff Kirsher #define NIG_REG_BMAC0_IN_EN 0x100ac 1778*adfc5217SJeff Kirsher /* [RW 1] output enable for TX_BMAC0 IF */ 1779*adfc5217SJeff Kirsher #define NIG_REG_BMAC0_OUT_EN 0x100e0 1780*adfc5217SJeff Kirsher /* [RW 1] output enable for TX BMAC pause port 0 IF */ 1781*adfc5217SJeff Kirsher #define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110 1782*adfc5217SJeff Kirsher /* [RW 1] output enable for RX_BMAC0_REGS IF */ 1783*adfc5217SJeff Kirsher #define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8 1784*adfc5217SJeff Kirsher /* [RW 1] output enable for RX BRB1 port0 IF */ 1785*adfc5217SJeff Kirsher #define NIG_REG_BRB0_OUT_EN 0x100f8 1786*adfc5217SJeff Kirsher /* [RW 1] Input enable for TX BRB1 pause port 0 IF */ 1787*adfc5217SJeff Kirsher #define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4 1788*adfc5217SJeff Kirsher /* [RW 1] output enable for RX BRB1 port1 IF */ 1789*adfc5217SJeff Kirsher #define NIG_REG_BRB1_OUT_EN 0x100fc 1790*adfc5217SJeff Kirsher /* [RW 1] Input enable for TX BRB1 pause port 1 IF */ 1791*adfc5217SJeff Kirsher #define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8 1792*adfc5217SJeff Kirsher /* [RW 1] output enable for RX BRB1 LP IF */ 1793*adfc5217SJeff Kirsher #define NIG_REG_BRB_LB_OUT_EN 0x10100 1794*adfc5217SJeff Kirsher /* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64] 1795*adfc5217SJeff Kirsher error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush; 1796*adfc5217SJeff Kirsher 72:73]-vnic_num; 81:74]-sideband_info */ 1797*adfc5217SJeff Kirsher #define NIG_REG_DEBUG_PACKET_LB 0x10800 1798*adfc5217SJeff Kirsher /* [RW 1] Input enable for TX Debug packet */ 1799*adfc5217SJeff Kirsher #define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc 1800*adfc5217SJeff Kirsher /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all 1801*adfc5217SJeff Kirsher packets from PBFare not forwarded to the MAC and just deleted from FIFO. 1802*adfc5217SJeff Kirsher First packet may be deleted from the middle. And last packet will be 1803*adfc5217SJeff Kirsher always deleted till the end. */ 1804*adfc5217SJeff Kirsher #define NIG_REG_EGRESS_DRAIN0_MODE 0x10060 1805*adfc5217SJeff Kirsher /* [RW 1] Output enable to EMAC0 */ 1806*adfc5217SJeff Kirsher #define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120 1807*adfc5217SJeff Kirsher /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs 1808*adfc5217SJeff Kirsher to emac for port0; other way to bmac for port0 */ 1809*adfc5217SJeff Kirsher #define NIG_REG_EGRESS_EMAC0_PORT 0x10058 1810*adfc5217SJeff Kirsher /* [RW 1] Input enable for TX PBF user packet port0 IF */ 1811*adfc5217SJeff Kirsher #define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc 1812*adfc5217SJeff Kirsher /* [RW 1] Input enable for TX PBF user packet port1 IF */ 1813*adfc5217SJeff Kirsher #define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0 1814*adfc5217SJeff Kirsher /* [RW 1] Input enable for TX UMP management packet port0 IF */ 1815*adfc5217SJeff Kirsher #define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4 1816*adfc5217SJeff Kirsher /* [RW 1] Input enable for RX_EMAC0 IF */ 1817*adfc5217SJeff Kirsher #define NIG_REG_EMAC0_IN_EN 0x100a4 1818*adfc5217SJeff Kirsher /* [RW 1] output enable for TX EMAC pause port 0 IF */ 1819*adfc5217SJeff Kirsher #define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118 1820*adfc5217SJeff Kirsher /* [R 1] status from emac0. This bit is set when MDINT from either the 1821*adfc5217SJeff Kirsher EXT_MDINT pin or from the Copper PHY is driven low. This condition must 1822*adfc5217SJeff Kirsher be cleared in the attached PHY device that is driving the MINT pin. */ 1823*adfc5217SJeff Kirsher #define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494 1824*adfc5217SJeff Kirsher /* [WB 48] This address space contains BMAC0 registers. The BMAC registers 1825*adfc5217SJeff Kirsher are described in appendix A. In order to access the BMAC0 registers; the 1826*adfc5217SJeff Kirsher base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be 1827*adfc5217SJeff Kirsher added to each BMAC register offset */ 1828*adfc5217SJeff Kirsher #define NIG_REG_INGRESS_BMAC0_MEM 0x10c00 1829*adfc5217SJeff Kirsher /* [WB 48] This address space contains BMAC1 registers. The BMAC registers 1830*adfc5217SJeff Kirsher are described in appendix A. In order to access the BMAC0 registers; the 1831*adfc5217SJeff Kirsher base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be 1832*adfc5217SJeff Kirsher added to each BMAC register offset */ 1833*adfc5217SJeff Kirsher #define NIG_REG_INGRESS_BMAC1_MEM 0x11000 1834*adfc5217SJeff Kirsher /* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */ 1835*adfc5217SJeff Kirsher #define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0 1836*adfc5217SJeff Kirsher /* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data 1837*adfc5217SJeff Kirsher packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */ 1838*adfc5217SJeff Kirsher #define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4 1839*adfc5217SJeff Kirsher /* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch 1840*adfc5217SJeff Kirsher logic for interrupts must be used. Enable per bit of interrupt of 1841*adfc5217SJeff Kirsher ~latch_status.latch_status */ 1842*adfc5217SJeff Kirsher #define NIG_REG_LATCH_BC_0 0x16210 1843*adfc5217SJeff Kirsher /* [RW 27] Latch for each interrupt from Unicore.b[0] 1844*adfc5217SJeff Kirsher status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete; 1845*adfc5217SJeff Kirsher b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status; 1846*adfc5217SJeff Kirsher b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn; 1847*adfc5217SJeff Kirsher b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete; 1848*adfc5217SJeff Kirsher b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status; 1849*adfc5217SJeff Kirsher b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete; 1850*adfc5217SJeff Kirsher b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet; 1851*adfc5217SJeff Kirsher b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g; 1852*adfc5217SJeff Kirsher b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact; 1853*adfc5217SJeff Kirsher b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx; 1854*adfc5217SJeff Kirsher b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx; 1855*adfc5217SJeff Kirsher b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */ 1856*adfc5217SJeff Kirsher #define NIG_REG_LATCH_STATUS_0 0x18000 1857*adfc5217SJeff Kirsher /* [RW 1] led 10g for port 0 */ 1858*adfc5217SJeff Kirsher #define NIG_REG_LED_10G_P0 0x10320 1859*adfc5217SJeff Kirsher /* [RW 1] led 10g for port 1 */ 1860*adfc5217SJeff Kirsher #define NIG_REG_LED_10G_P1 0x10324 1861*adfc5217SJeff Kirsher /* [RW 1] Port0: This bit is set to enable the use of the 1862*adfc5217SJeff Kirsher ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field 1863*adfc5217SJeff Kirsher defined below. If this bit is cleared; then the blink rate will be about 1864*adfc5217SJeff Kirsher 8Hz. */ 1865*adfc5217SJeff Kirsher #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318 1866*adfc5217SJeff Kirsher /* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for 1867*adfc5217SJeff Kirsher Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field 1868*adfc5217SJeff Kirsher is reset to 0x080; giving a default blink period of approximately 8Hz. */ 1869*adfc5217SJeff Kirsher #define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310 1870*adfc5217SJeff Kirsher /* [RW 1] Port0: If set along with the 1871*adfc5217SJeff Kirsher ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0 1872*adfc5217SJeff Kirsher bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED 1873*adfc5217SJeff Kirsher bit; the Traffic LED will blink with the blink rate specified in 1874*adfc5217SJeff Kirsher ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and 1875*adfc5217SJeff Kirsher ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0 1876*adfc5217SJeff Kirsher fields. */ 1877*adfc5217SJeff Kirsher #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308 1878*adfc5217SJeff Kirsher /* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The 1879*adfc5217SJeff Kirsher Traffic LED will then be controlled via bit ~nig_registers_ 1880*adfc5217SJeff Kirsher led_control_traffic_p0.led_control_traffic_p0 and bit 1881*adfc5217SJeff Kirsher ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */ 1882*adfc5217SJeff Kirsher #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8 1883*adfc5217SJeff Kirsher /* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit; 1884*adfc5217SJeff Kirsher turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also 1885*adfc5217SJeff Kirsher set; the LED will blink with blink rate specified in 1886*adfc5217SJeff Kirsher ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and 1887*adfc5217SJeff Kirsher ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0 1888*adfc5217SJeff Kirsher fields. */ 1889*adfc5217SJeff Kirsher #define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300 1890*adfc5217SJeff Kirsher /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3; 1891*adfc5217SJeff Kirsher 9-11PHY7; 12 MAC4; 13-15 PHY10; */ 1892*adfc5217SJeff Kirsher #define NIG_REG_LED_MODE_P0 0x102f0 1893*adfc5217SJeff Kirsher /* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1- 1894*adfc5217SJeff Kirsher tsdm enable; b2- usdm enable */ 1895*adfc5217SJeff Kirsher #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070 1896*adfc5217SJeff Kirsher #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074 1897*adfc5217SJeff Kirsher /* [RW 1] SAFC enable for port0. This register may get 1 only when 1898*adfc5217SJeff Kirsher ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same 1899*adfc5217SJeff Kirsher port */ 1900*adfc5217SJeff Kirsher #define NIG_REG_LLFC_ENABLE_0 0x16208 1901*adfc5217SJeff Kirsher #define NIG_REG_LLFC_ENABLE_1 0x1620c 1902*adfc5217SJeff Kirsher /* [RW 16] classes are high-priority for port0 */ 1903*adfc5217SJeff Kirsher #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058 1904*adfc5217SJeff Kirsher #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 0x1605c 1905*adfc5217SJeff Kirsher /* [RW 16] classes are low-priority for port0 */ 1906*adfc5217SJeff Kirsher #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060 1907*adfc5217SJeff Kirsher #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 0x16064 1908*adfc5217SJeff Kirsher /* [RW 1] Output enable of message to LLFC BMAC IF for port0 */ 1909*adfc5217SJeff Kirsher #define NIG_REG_LLFC_OUT_EN_0 0x160c8 1910*adfc5217SJeff Kirsher #define NIG_REG_LLFC_OUT_EN_1 0x160cc 1911*adfc5217SJeff Kirsher #define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c 1912*adfc5217SJeff Kirsher #define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154 1913*adfc5217SJeff Kirsher #define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244 1914*adfc5217SJeff Kirsher #define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048 1915*adfc5217SJeff Kirsher /* [RW 1] send to BRB1 if no match on any of RMP rules. */ 1916*adfc5217SJeff Kirsher #define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c 1917*adfc5217SJeff Kirsher /* [RW 2] Determine the classification participants. 0: no classification.1: 1918*adfc5217SJeff Kirsher classification upon VLAN id. 2: classification upon MAC address. 3: 1919*adfc5217SJeff Kirsher classification upon both VLAN id & MAC addr. */ 1920*adfc5217SJeff Kirsher #define NIG_REG_LLH0_CLS_TYPE 0x16080 1921*adfc5217SJeff Kirsher /* [RW 32] cm header for llh0 */ 1922*adfc5217SJeff Kirsher #define NIG_REG_LLH0_CM_HEADER 0x1007c 1923*adfc5217SJeff Kirsher #define NIG_REG_LLH0_DEST_IP_0_1 0x101dc 1924*adfc5217SJeff Kirsher #define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0 1925*adfc5217SJeff Kirsher /* [RW 16] destination TCP address 1. The LLH will look for this address in 1926*adfc5217SJeff Kirsher all incoming packets. */ 1927*adfc5217SJeff Kirsher #define NIG_REG_LLH0_DEST_TCP_0 0x10220 1928*adfc5217SJeff Kirsher /* [RW 16] destination UDP address 1 The LLH will look for this address in 1929*adfc5217SJeff Kirsher all incoming packets. */ 1930*adfc5217SJeff Kirsher #define NIG_REG_LLH0_DEST_UDP_0 0x10214 1931*adfc5217SJeff Kirsher #define NIG_REG_LLH0_ERROR_MASK 0x1008c 1932*adfc5217SJeff Kirsher /* [RW 8] event id for llh0 */ 1933*adfc5217SJeff Kirsher #define NIG_REG_LLH0_EVENT_ID 0x10084 1934*adfc5217SJeff Kirsher #define NIG_REG_LLH0_FUNC_EN 0x160fc 1935*adfc5217SJeff Kirsher #define NIG_REG_LLH0_FUNC_MEM 0x16180 1936*adfc5217SJeff Kirsher #define NIG_REG_LLH0_FUNC_MEM_ENABLE 0x16140 1937*adfc5217SJeff Kirsher #define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100 1938*adfc5217SJeff Kirsher /* [RW 1] Determine the IP version to look for in 1939*adfc5217SJeff Kirsher ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */ 1940*adfc5217SJeff Kirsher #define NIG_REG_LLH0_IPV4_IPV6_0 0x10208 1941*adfc5217SJeff Kirsher /* [RW 1] t bit for llh0 */ 1942*adfc5217SJeff Kirsher #define NIG_REG_LLH0_T_BIT 0x10074 1943*adfc5217SJeff Kirsher /* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */ 1944*adfc5217SJeff Kirsher #define NIG_REG_LLH0_VLAN_ID_0 0x1022c 1945*adfc5217SJeff Kirsher /* [RW 8] init credit counter for port0 in LLH */ 1946*adfc5217SJeff Kirsher #define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554 1947*adfc5217SJeff Kirsher #define NIG_REG_LLH0_XCM_MASK 0x10130 1948*adfc5217SJeff Kirsher #define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248 1949*adfc5217SJeff Kirsher /* [RW 1] send to BRB1 if no match on any of RMP rules. */ 1950*adfc5217SJeff Kirsher #define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc 1951*adfc5217SJeff Kirsher /* [RW 2] Determine the classification participants. 0: no classification.1: 1952*adfc5217SJeff Kirsher classification upon VLAN id. 2: classification upon MAC address. 3: 1953*adfc5217SJeff Kirsher classification upon both VLAN id & MAC addr. */ 1954*adfc5217SJeff Kirsher #define NIG_REG_LLH1_CLS_TYPE 0x16084 1955*adfc5217SJeff Kirsher /* [RW 32] cm header for llh1 */ 1956*adfc5217SJeff Kirsher #define NIG_REG_LLH1_CM_HEADER 0x10080 1957*adfc5217SJeff Kirsher #define NIG_REG_LLH1_ERROR_MASK 0x10090 1958*adfc5217SJeff Kirsher /* [RW 8] event id for llh1 */ 1959*adfc5217SJeff Kirsher #define NIG_REG_LLH1_EVENT_ID 0x10088 1960*adfc5217SJeff Kirsher #define NIG_REG_LLH1_FUNC_MEM 0x161c0 1961*adfc5217SJeff Kirsher #define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160 1962*adfc5217SJeff Kirsher #define NIG_REG_LLH1_FUNC_MEM_SIZE 16 1963*adfc5217SJeff Kirsher /* [RW 1] When this bit is set; the LLH will classify the packet before 1964*adfc5217SJeff Kirsher * sending it to the BRB or calculating WoL on it. This bit controls port 1 1965*adfc5217SJeff Kirsher * only. The legacy llh_multi_function_mode bit controls port 0. */ 1966*adfc5217SJeff Kirsher #define NIG_REG_LLH1_MF_MODE 0x18614 1967*adfc5217SJeff Kirsher /* [RW 8] init credit counter for port1 in LLH */ 1968*adfc5217SJeff Kirsher #define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564 1969*adfc5217SJeff Kirsher #define NIG_REG_LLH1_XCM_MASK 0x10134 1970*adfc5217SJeff Kirsher /* [RW 1] When this bit is set; the LLH will expect all packets to be with 1971*adfc5217SJeff Kirsher e1hov */ 1972*adfc5217SJeff Kirsher #define NIG_REG_LLH_E1HOV_MODE 0x160d8 1973*adfc5217SJeff Kirsher /* [RW 1] When this bit is set; the LLH will classify the packet before 1974*adfc5217SJeff Kirsher sending it to the BRB or calculating WoL on it. */ 1975*adfc5217SJeff Kirsher #define NIG_REG_LLH_MF_MODE 0x16024 1976*adfc5217SJeff Kirsher #define NIG_REG_MASK_INTERRUPT_PORT0 0x10330 1977*adfc5217SJeff Kirsher #define NIG_REG_MASK_INTERRUPT_PORT1 0x10334 1978*adfc5217SJeff Kirsher /* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */ 1979*adfc5217SJeff Kirsher #define NIG_REG_NIG_EMAC0_EN 0x1003c 1980*adfc5217SJeff Kirsher /* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */ 1981*adfc5217SJeff Kirsher #define NIG_REG_NIG_EMAC1_EN 0x10040 1982*adfc5217SJeff Kirsher /* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the 1983*adfc5217SJeff Kirsher EMAC0 to strip the CRC from the ingress packets. */ 1984*adfc5217SJeff Kirsher #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044 1985*adfc5217SJeff Kirsher /* [R 32] Interrupt register #0 read */ 1986*adfc5217SJeff Kirsher #define NIG_REG_NIG_INT_STS_0 0x103b0 1987*adfc5217SJeff Kirsher #define NIG_REG_NIG_INT_STS_1 0x103c0 1988*adfc5217SJeff Kirsher /* [R 32] Legacy E1 and E1H location for parity error mask register. */ 1989*adfc5217SJeff Kirsher #define NIG_REG_NIG_PRTY_MASK 0x103dc 1990*adfc5217SJeff Kirsher /* [RW 32] Parity mask register #0 read/write */ 1991*adfc5217SJeff Kirsher #define NIG_REG_NIG_PRTY_MASK_0 0x183c8 1992*adfc5217SJeff Kirsher #define NIG_REG_NIG_PRTY_MASK_1 0x183d8 1993*adfc5217SJeff Kirsher /* [R 32] Legacy E1 and E1H location for parity error status register. */ 1994*adfc5217SJeff Kirsher #define NIG_REG_NIG_PRTY_STS 0x103d0 1995*adfc5217SJeff Kirsher /* [R 32] Parity register #0 read */ 1996*adfc5217SJeff Kirsher #define NIG_REG_NIG_PRTY_STS_0 0x183bc 1997*adfc5217SJeff Kirsher #define NIG_REG_NIG_PRTY_STS_1 0x183cc 1998*adfc5217SJeff Kirsher /* [R 32] Legacy E1 and E1H location for parity error status clear register. */ 1999*adfc5217SJeff Kirsher #define NIG_REG_NIG_PRTY_STS_CLR 0x103d4 2000*adfc5217SJeff Kirsher /* [RC 32] Parity register #0 read clear */ 2001*adfc5217SJeff Kirsher #define NIG_REG_NIG_PRTY_STS_CLR_0 0x183c0 2002*adfc5217SJeff Kirsher #define NIG_REG_NIG_PRTY_STS_CLR_1 0x183d0 2003*adfc5217SJeff Kirsher #define MCPR_IMC_COMMAND_ENABLE (1L<<31) 2004*adfc5217SJeff Kirsher #define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16 2005*adfc5217SJeff Kirsher #define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28 2006*adfc5217SJeff Kirsher #define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8 2007*adfc5217SJeff Kirsher /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2008*adfc5217SJeff Kirsher * Ethernet header. */ 2009*adfc5217SJeff Kirsher #define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038 2010*adfc5217SJeff Kirsher /* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in 2011*adfc5217SJeff Kirsher * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be 2012*adfc5217SJeff Kirsher * disabled when this bit is set. */ 2013*adfc5217SJeff Kirsher #define NIG_REG_P0_HWPFC_ENABLE 0x18078 2014*adfc5217SJeff Kirsher #define NIG_REG_P0_LLH_FUNC_MEM2 0x18480 2015*adfc5217SJeff Kirsher #define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x18440 2016*adfc5217SJeff Kirsher /* [RW 1] Input enable for RX MAC interface. */ 2017*adfc5217SJeff Kirsher #define NIG_REG_P0_MAC_IN_EN 0x185ac 2018*adfc5217SJeff Kirsher /* [RW 1] Output enable for TX MAC interface */ 2019*adfc5217SJeff Kirsher #define NIG_REG_P0_MAC_OUT_EN 0x185b0 2020*adfc5217SJeff Kirsher /* [RW 1] Output enable for TX PAUSE signal to the MAC. */ 2021*adfc5217SJeff Kirsher #define NIG_REG_P0_MAC_PAUSE_OUT_EN 0x185b4 2022*adfc5217SJeff Kirsher /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for 2023*adfc5217SJeff Kirsher * future expansion) each priorty is to be mapped to. Bits 3:0 specify the 2024*adfc5217SJeff Kirsher * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit 2025*adfc5217SJeff Kirsher * priority field is extracted from the outer-most VLAN in receive packet. 2026*adfc5217SJeff Kirsher * Only COS 0 and COS 1 are supported in E2. */ 2027*adfc5217SJeff Kirsher #define NIG_REG_P0_PKT_PRIORITY_TO_COS 0x18054 2028*adfc5217SJeff Kirsher /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A 2029*adfc5217SJeff Kirsher * priority is mapped to COS 0 when the corresponding mask bit is 1. More 2030*adfc5217SJeff Kirsher * than one bit may be set; allowing multiple priorities to be mapped to one 2031*adfc5217SJeff Kirsher * COS. */ 2032*adfc5217SJeff Kirsher #define NIG_REG_P0_RX_COS0_PRIORITY_MASK 0x18058 2033*adfc5217SJeff Kirsher /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A 2034*adfc5217SJeff Kirsher * priority is mapped to COS 1 when the corresponding mask bit is 1. More 2035*adfc5217SJeff Kirsher * than one bit may be set; allowing multiple priorities to be mapped to one 2036*adfc5217SJeff Kirsher * COS. */ 2037*adfc5217SJeff Kirsher #define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805c 2038*adfc5217SJeff Kirsher /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A 2039*adfc5217SJeff Kirsher * priority is mapped to COS 2 when the corresponding mask bit is 1. More 2040*adfc5217SJeff Kirsher * than one bit may be set; allowing multiple priorities to be mapped to one 2041*adfc5217SJeff Kirsher * COS. */ 2042*adfc5217SJeff Kirsher #define NIG_REG_P0_RX_COS2_PRIORITY_MASK 0x186b0 2043*adfc5217SJeff Kirsher /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A 2044*adfc5217SJeff Kirsher * priority is mapped to COS 3 when the corresponding mask bit is 1. More 2045*adfc5217SJeff Kirsher * than one bit may be set; allowing multiple priorities to be mapped to one 2046*adfc5217SJeff Kirsher * COS. */ 2047*adfc5217SJeff Kirsher #define NIG_REG_P0_RX_COS3_PRIORITY_MASK 0x186b4 2048*adfc5217SJeff Kirsher /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A 2049*adfc5217SJeff Kirsher * priority is mapped to COS 4 when the corresponding mask bit is 1. More 2050*adfc5217SJeff Kirsher * than one bit may be set; allowing multiple priorities to be mapped to one 2051*adfc5217SJeff Kirsher * COS. */ 2052*adfc5217SJeff Kirsher #define NIG_REG_P0_RX_COS4_PRIORITY_MASK 0x186b8 2053*adfc5217SJeff Kirsher /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A 2054*adfc5217SJeff Kirsher * priority is mapped to COS 5 when the corresponding mask bit is 1. More 2055*adfc5217SJeff Kirsher * than one bit may be set; allowing multiple priorities to be mapped to one 2056*adfc5217SJeff Kirsher * COS. */ 2057*adfc5217SJeff Kirsher #define NIG_REG_P0_RX_COS5_PRIORITY_MASK 0x186bc 2058*adfc5217SJeff Kirsher /* [R 1] RX FIFO for receiving data from MAC is empty. */ 2059*adfc5217SJeff Kirsher /* [RW 15] Specify which of the credit registers the client is to be mapped 2060*adfc5217SJeff Kirsher * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For 2061*adfc5217SJeff Kirsher * clients that are not subject to WFQ credit blocking - their 2062*adfc5217SJeff Kirsher * specifications here are not used. */ 2063*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f0 2064*adfc5217SJeff Kirsher /* [RW 32] Specify which of the credit registers the client is to be mapped 2065*adfc5217SJeff Kirsher * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are 2066*adfc5217SJeff Kirsher * for client 0; bits [35:32] are for client 8. For clients that are not 2067*adfc5217SJeff Kirsher * subject to WFQ credit blocking - their specifications here are not used. 2068*adfc5217SJeff Kirsher * This is a new register (with 2_) added in E3 B0 to accommodate the 9 2069*adfc5217SJeff Kirsher * input clients to ETS arbiter. The reset default is set for management and 2070*adfc5217SJeff Kirsher * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to 2071*adfc5217SJeff Kirsher * use credit registers 0-5 respectively (0x543210876). Note that credit 2072*adfc5217SJeff Kirsher * registers can not be shared between clients. */ 2073*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x18688 2074*adfc5217SJeff Kirsher /* [RW 4] Specify which of the credit registers the client is to be mapped 2075*adfc5217SJeff Kirsher * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are 2076*adfc5217SJeff Kirsher * for client 0; bits [35:32] are for client 8. For clients that are not 2077*adfc5217SJeff Kirsher * subject to WFQ credit blocking - their specifications here are not used. 2078*adfc5217SJeff Kirsher * This is a new register (with 2_) added in E3 B0 to accommodate the 9 2079*adfc5217SJeff Kirsher * input clients to ETS arbiter. The reset default is set for management and 2080*adfc5217SJeff Kirsher * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to 2081*adfc5217SJeff Kirsher * use credit registers 0-5 respectively (0x543210876). Note that credit 2082*adfc5217SJeff Kirsher * registers can not be shared between clients. */ 2083*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x1868c 2084*adfc5217SJeff Kirsher /* [RW 5] Specify whether the client competes directly in the strict 2085*adfc5217SJeff Kirsher * priority arbiter. The bits are mapped according to client ID (client IDs 2086*adfc5217SJeff Kirsher * are defined in tx_arb_priority_client). Default value is set to enable 2087*adfc5217SJeff Kirsher * strict priorities for clients 0-2 -- management and debug traffic. */ 2088*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT 0x180e8 2089*adfc5217SJeff Kirsher /* [RW 5] Specify whether the client is subject to WFQ credit blocking. The 2090*adfc5217SJeff Kirsher * bits are mapped according to client ID (client IDs are defined in 2091*adfc5217SJeff Kirsher * tx_arb_priority_client). Default value is 0 for not using WFQ credit 2092*adfc5217SJeff Kirsher * blocking. */ 2093*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x180ec 2094*adfc5217SJeff Kirsher /* [RW 32] Specify the upper bound that credit register 0 is allowed to 2095*adfc5217SJeff Kirsher * reach. */ 2096*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810c 2097*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x18110 2098*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 0x18114 2099*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 0x18118 2100*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 0x1811c 2101*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 0x186a0 2102*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 0x186a4 2103*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 0x186a8 2104*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 0x186ac 2105*adfc5217SJeff Kirsher /* [RW 32] Specify the weight (in bytes) to be added to credit register 0 2106*adfc5217SJeff Kirsher * when it is time to increment. */ 2107*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f8 2108*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fc 2109*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 0x18100 2110*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 0x18104 2111*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 0x18108 2112*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 0x18690 2113*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 0x18694 2114*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 0x18698 2115*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 0x1869c 2116*adfc5217SJeff Kirsher /* [RW 12] Specify the number of strict priority arbitration slots between 2117*adfc5217SJeff Kirsher * two round-robin arbitration slots to avoid starvation. A value of 0 means 2118*adfc5217SJeff Kirsher * no strict priority cycles - the strict priority with anti-starvation 2119*adfc5217SJeff Kirsher * arbiter becomes a round-robin arbiter. */ 2120*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS 0x180f4 2121*adfc5217SJeff Kirsher /* [RW 15] Specify the client number to be assigned to each priority of the 2122*adfc5217SJeff Kirsher * strict priority arbiter. Priority 0 is the highest priority. Bits [2:0] 2123*adfc5217SJeff Kirsher * are for priority 0 client; bits [14:12] are for priority 4 client. The 2124*adfc5217SJeff Kirsher * clients are assigned the following IDs: 0-management; 1-debug traffic 2125*adfc5217SJeff Kirsher * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 2126*adfc5217SJeff Kirsher * traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000) 2127*adfc5217SJeff Kirsher * for management at priority 0; debug traffic at priorities 1 and 2; COS0 2128*adfc5217SJeff Kirsher * traffic at priority 3; and COS1 traffic at priority 4. */ 2129*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e4 2130*adfc5217SJeff Kirsher /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2131*adfc5217SJeff Kirsher * Ethernet header. */ 2132*adfc5217SJeff Kirsher #define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818c 2133*adfc5217SJeff Kirsher #define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0 2134*adfc5217SJeff Kirsher #define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460 2135*adfc5217SJeff Kirsher /* [RW 32] Specify the client number to be assigned to each priority of the 2136*adfc5217SJeff Kirsher * strict priority arbiter. This register specifies bits 31:0 of the 36-bit 2137*adfc5217SJeff Kirsher * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 2138*adfc5217SJeff Kirsher * client; bits [35-32] are for priority 8 client. The clients are assigned 2139*adfc5217SJeff Kirsher * the following IDs: 0-management; 1-debug traffic from this port; 2-debug 2140*adfc5217SJeff Kirsher * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 2141*adfc5217SJeff Kirsher * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is 2142*adfc5217SJeff Kirsher * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to 2143*adfc5217SJeff Kirsher * accommodate the 9 input clients to ETS arbiter. */ 2144*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB 0x18680 2145*adfc5217SJeff Kirsher /* [RW 4] Specify the client number to be assigned to each priority of the 2146*adfc5217SJeff Kirsher * strict priority arbiter. This register specifies bits 35:32 of the 36-bit 2147*adfc5217SJeff Kirsher * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 2148*adfc5217SJeff Kirsher * client; bits [35-32] are for priority 8 client. The clients are assigned 2149*adfc5217SJeff Kirsher * the following IDs: 0-management; 1-debug traffic from this port; 2-debug 2150*adfc5217SJeff Kirsher * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 2151*adfc5217SJeff Kirsher * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is 2152*adfc5217SJeff Kirsher * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to 2153*adfc5217SJeff Kirsher * accommodate the 9 input clients to ETS arbiter. */ 2154*adfc5217SJeff Kirsher #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB 0x18684 2155*adfc5217SJeff Kirsher #define NIG_REG_P1_MAC_IN_EN 0x185c0 2156*adfc5217SJeff Kirsher /* [RW 1] Output enable for TX MAC interface */ 2157*adfc5217SJeff Kirsher #define NIG_REG_P1_MAC_OUT_EN 0x185c4 2158*adfc5217SJeff Kirsher /* [RW 1] Output enable for TX PAUSE signal to the MAC. */ 2159*adfc5217SJeff Kirsher #define NIG_REG_P1_MAC_PAUSE_OUT_EN 0x185c8 2160*adfc5217SJeff Kirsher /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for 2161*adfc5217SJeff Kirsher * future expansion) each priorty is to be mapped to. Bits 3:0 specify the 2162*adfc5217SJeff Kirsher * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit 2163*adfc5217SJeff Kirsher * priority field is extracted from the outer-most VLAN in receive packet. 2164*adfc5217SJeff Kirsher * Only COS 0 and COS 1 are supported in E2. */ 2165*adfc5217SJeff Kirsher #define NIG_REG_P1_PKT_PRIORITY_TO_COS 0x181a8 2166*adfc5217SJeff Kirsher /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A 2167*adfc5217SJeff Kirsher * priority is mapped to COS 0 when the corresponding mask bit is 1. More 2168*adfc5217SJeff Kirsher * than one bit may be set; allowing multiple priorities to be mapped to one 2169*adfc5217SJeff Kirsher * COS. */ 2170*adfc5217SJeff Kirsher #define NIG_REG_P1_RX_COS0_PRIORITY_MASK 0x181ac 2171*adfc5217SJeff Kirsher /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A 2172*adfc5217SJeff Kirsher * priority is mapped to COS 1 when the corresponding mask bit is 1. More 2173*adfc5217SJeff Kirsher * than one bit may be set; allowing multiple priorities to be mapped to one 2174*adfc5217SJeff Kirsher * COS. */ 2175*adfc5217SJeff Kirsher #define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b0 2176*adfc5217SJeff Kirsher /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A 2177*adfc5217SJeff Kirsher * priority is mapped to COS 2 when the corresponding mask bit is 1. More 2178*adfc5217SJeff Kirsher * than one bit may be set; allowing multiple priorities to be mapped to one 2179*adfc5217SJeff Kirsher * COS. */ 2180*adfc5217SJeff Kirsher #define NIG_REG_P1_RX_COS2_PRIORITY_MASK 0x186f8 2181*adfc5217SJeff Kirsher /* [R 1] RX FIFO for receiving data from MAC is empty. */ 2182*adfc5217SJeff Kirsher #define NIG_REG_P1_RX_MACFIFO_EMPTY 0x1858c 2183*adfc5217SJeff Kirsher /* [R 1] TLLH FIFO is empty. */ 2184*adfc5217SJeff Kirsher #define NIG_REG_P1_TLLH_FIFO_EMPTY 0x18338 2185*adfc5217SJeff Kirsher /* [RW 32] Specify which of the credit registers the client is to be mapped 2186*adfc5217SJeff Kirsher * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are 2187*adfc5217SJeff Kirsher * for client 0; bits [35:32] are for client 8. For clients that are not 2188*adfc5217SJeff Kirsher * subject to WFQ credit blocking - their specifications here are not used. 2189*adfc5217SJeff Kirsher * This is a new register (with 2_) added in E3 B0 to accommodate the 9 2190*adfc5217SJeff Kirsher * input clients to ETS arbiter. The reset default is set for management and 2191*adfc5217SJeff Kirsher * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to 2192*adfc5217SJeff Kirsher * use credit registers 0-5 respectively (0x543210876). Note that credit 2193*adfc5217SJeff Kirsher * registers can not be shared between clients. Note also that there are 2194*adfc5217SJeff Kirsher * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only 2195*adfc5217SJeff Kirsher * credit registers 0-5 are valid. This register should be configured 2196*adfc5217SJeff Kirsher * appropriately before enabling WFQ. */ 2197*adfc5217SJeff Kirsher #define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x186e8 2198*adfc5217SJeff Kirsher /* [RW 4] Specify which of the credit registers the client is to be mapped 2199*adfc5217SJeff Kirsher * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are 2200*adfc5217SJeff Kirsher * for client 0; bits [35:32] are for client 8. For clients that are not 2201*adfc5217SJeff Kirsher * subject to WFQ credit blocking - their specifications here are not used. 2202*adfc5217SJeff Kirsher * This is a new register (with 2_) added in E3 B0 to accommodate the 9 2203*adfc5217SJeff Kirsher * input clients to ETS arbiter. The reset default is set for management and 2204*adfc5217SJeff Kirsher * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to 2205*adfc5217SJeff Kirsher * use credit registers 0-5 respectively (0x543210876). Note that credit 2206*adfc5217SJeff Kirsher * registers can not be shared between clients. Note also that there are 2207*adfc5217SJeff Kirsher * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only 2208*adfc5217SJeff Kirsher * credit registers 0-5 are valid. This register should be configured 2209*adfc5217SJeff Kirsher * appropriately before enabling WFQ. */ 2210*adfc5217SJeff Kirsher #define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x186ec 2211*adfc5217SJeff Kirsher /* [RW 9] Specify whether the client competes directly in the strict 2212*adfc5217SJeff Kirsher * priority arbiter. The bits are mapped according to client ID (client IDs 2213*adfc5217SJeff Kirsher * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic 2214*adfc5217SJeff Kirsher * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 2215*adfc5217SJeff Kirsher * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. 2216*adfc5217SJeff Kirsher * Default value is set to enable strict priorities for all clients. */ 2217*adfc5217SJeff Kirsher #define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT 0x18234 2218*adfc5217SJeff Kirsher /* [RW 9] Specify whether the client is subject to WFQ credit blocking. The 2219*adfc5217SJeff Kirsher * bits are mapped according to client ID (client IDs are defined in 2220*adfc5217SJeff Kirsher * tx_arb_priority_client2): 0-management; 1-debug traffic from this port; 2221*adfc5217SJeff Kirsher * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 2222*adfc5217SJeff Kirsher * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is 2223*adfc5217SJeff Kirsher * 0 for not using WFQ credit blocking. */ 2224*adfc5217SJeff Kirsher #define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x18238 2225*adfc5217SJeff Kirsher #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 0x18258 2226*adfc5217SJeff Kirsher #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 0x1825c 2227*adfc5217SJeff Kirsher #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 0x18260 2228*adfc5217SJeff Kirsher #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 0x18264 2229*adfc5217SJeff Kirsher #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 0x18268 2230*adfc5217SJeff Kirsher #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 0x186f4 2231*adfc5217SJeff Kirsher /* [RW 32] Specify the weight (in bytes) to be added to credit register 0 2232*adfc5217SJeff Kirsher * when it is time to increment. */ 2233*adfc5217SJeff Kirsher #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 0x18244 2234*adfc5217SJeff Kirsher #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 0x18248 2235*adfc5217SJeff Kirsher #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 0x1824c 2236*adfc5217SJeff Kirsher #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 0x18250 2237*adfc5217SJeff Kirsher #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 0x18254 2238*adfc5217SJeff Kirsher #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 0x186f0 2239*adfc5217SJeff Kirsher /* [RW 12] Specify the number of strict priority arbitration slots between 2240*adfc5217SJeff Kirsher two round-robin arbitration slots to avoid starvation. A value of 0 means 2241*adfc5217SJeff Kirsher no strict priority cycles - the strict priority with anti-starvation 2242*adfc5217SJeff Kirsher arbiter becomes a round-robin arbiter. */ 2243*adfc5217SJeff Kirsher #define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS 0x18240 2244*adfc5217SJeff Kirsher /* [RW 32] Specify the client number to be assigned to each priority of the 2245*adfc5217SJeff Kirsher strict priority arbiter. This register specifies bits 31:0 of the 36-bit 2246*adfc5217SJeff Kirsher value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 2247*adfc5217SJeff Kirsher client; bits [35-32] are for priority 8 client. The clients are assigned 2248*adfc5217SJeff Kirsher the following IDs: 0-management; 1-debug traffic from this port; 2-debug 2249*adfc5217SJeff Kirsher traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 2250*adfc5217SJeff Kirsher 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is 2251*adfc5217SJeff Kirsher set to 0x345678021. This is a new register (with 2_) added in E3 B0 to 2252*adfc5217SJeff Kirsher accommodate the 9 input clients to ETS arbiter. Note that this register 2253*adfc5217SJeff Kirsher is the same as the one for port 0, except that port 1 only has COS 0-2 2254*adfc5217SJeff Kirsher traffic. There is no traffic for COS 3-5 of port 1. */ 2255*adfc5217SJeff Kirsher #define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB 0x186e0 2256*adfc5217SJeff Kirsher /* [RW 4] Specify the client number to be assigned to each priority of the 2257*adfc5217SJeff Kirsher strict priority arbiter. This register specifies bits 35:32 of the 36-bit 2258*adfc5217SJeff Kirsher value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 2259*adfc5217SJeff Kirsher client; bits [35-32] are for priority 8 client. The clients are assigned 2260*adfc5217SJeff Kirsher the following IDs: 0-management; 1-debug traffic from this port; 2-debug 2261*adfc5217SJeff Kirsher traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 2262*adfc5217SJeff Kirsher 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is 2263*adfc5217SJeff Kirsher set to 0x345678021. This is a new register (with 2_) added in E3 B0 to 2264*adfc5217SJeff Kirsher accommodate the 9 input clients to ETS arbiter. Note that this register 2265*adfc5217SJeff Kirsher is the same as the one for port 0, except that port 1 only has COS 0-2 2266*adfc5217SJeff Kirsher traffic. There is no traffic for COS 3-5 of port 1. */ 2267*adfc5217SJeff Kirsher #define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB 0x186e4 2268*adfc5217SJeff Kirsher /* [R 1] TX FIFO for transmitting data to MAC is empty. */ 2269*adfc5217SJeff Kirsher #define NIG_REG_P1_TX_MACFIFO_EMPTY 0x18594 2270*adfc5217SJeff Kirsher /* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets 2271*adfc5217SJeff Kirsher forwarded to the host. */ 2272*adfc5217SJeff Kirsher #define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY 0x182b8 2273*adfc5217SJeff Kirsher /* [RW 32] Specify the upper bound that credit register 0 is allowed to 2274*adfc5217SJeff Kirsher * reach. */ 2275*adfc5217SJeff Kirsher /* [RW 1] Pause enable for port0. This register may get 1 only when 2276*adfc5217SJeff Kirsher ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same 2277*adfc5217SJeff Kirsher port */ 2278*adfc5217SJeff Kirsher #define NIG_REG_PAUSE_ENABLE_0 0x160c0 2279*adfc5217SJeff Kirsher #define NIG_REG_PAUSE_ENABLE_1 0x160c4 2280*adfc5217SJeff Kirsher /* [RW 1] Input enable for RX PBF LP IF */ 2281*adfc5217SJeff Kirsher #define NIG_REG_PBF_LB_IN_EN 0x100b4 2282*adfc5217SJeff Kirsher /* [RW 1] Value of this register will be transmitted to port swap when 2283*adfc5217SJeff Kirsher ~nig_registers_strap_override.strap_override =1 */ 2284*adfc5217SJeff Kirsher #define NIG_REG_PORT_SWAP 0x10394 2285*adfc5217SJeff Kirsher /* [RW 1] PPP enable for port0. This register may get 1 only when 2286*adfc5217SJeff Kirsher * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the 2287*adfc5217SJeff Kirsher * same port */ 2288*adfc5217SJeff Kirsher #define NIG_REG_PPP_ENABLE_0 0x160b0 2289*adfc5217SJeff Kirsher #define NIG_REG_PPP_ENABLE_1 0x160b4 2290*adfc5217SJeff Kirsher /* [RW 1] output enable for RX parser descriptor IF */ 2291*adfc5217SJeff Kirsher #define NIG_REG_PRS_EOP_OUT_EN 0x10104 2292*adfc5217SJeff Kirsher /* [RW 1] Input enable for RX parser request IF */ 2293*adfc5217SJeff Kirsher #define NIG_REG_PRS_REQ_IN_EN 0x100b8 2294*adfc5217SJeff Kirsher /* [RW 5] control to serdes - CL45 DEVAD */ 2295*adfc5217SJeff Kirsher #define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370 2296*adfc5217SJeff Kirsher /* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */ 2297*adfc5217SJeff Kirsher #define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c 2298*adfc5217SJeff Kirsher /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */ 2299*adfc5217SJeff Kirsher #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374 2300*adfc5217SJeff Kirsher /* [R 1] status from serdes0 that inputs to interrupt logic of link status */ 2301*adfc5217SJeff Kirsher #define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578 2302*adfc5217SJeff Kirsher /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure 2303*adfc5217SJeff Kirsher for port0 */ 2304*adfc5217SJeff Kirsher #define NIG_REG_STAT0_BRB_DISCARD 0x105f0 2305*adfc5217SJeff Kirsher /* [R 32] Rx statistics : In user packets truncated due to BRB backpressure 2306*adfc5217SJeff Kirsher for port0 */ 2307*adfc5217SJeff Kirsher #define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8 2308*adfc5217SJeff Kirsher /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that 2309*adfc5217SJeff Kirsher between 1024 and 1522 bytes for port0 */ 2310*adfc5217SJeff Kirsher #define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750 2311*adfc5217SJeff Kirsher /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that 2312*adfc5217SJeff Kirsher between 1523 bytes and above for port0 */ 2313*adfc5217SJeff Kirsher #define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760 2314*adfc5217SJeff Kirsher /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure 2315*adfc5217SJeff Kirsher for port1 */ 2316*adfc5217SJeff Kirsher #define NIG_REG_STAT1_BRB_DISCARD 0x10628 2317*adfc5217SJeff Kirsher /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that 2318*adfc5217SJeff Kirsher between 1024 and 1522 bytes for port1 */ 2319*adfc5217SJeff Kirsher #define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0 2320*adfc5217SJeff Kirsher /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that 2321*adfc5217SJeff Kirsher between 1523 bytes and above for port1 */ 2322*adfc5217SJeff Kirsher #define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0 2323*adfc5217SJeff Kirsher /* [WB_R 64] Rx statistics : User octets received for LP */ 2324*adfc5217SJeff Kirsher #define NIG_REG_STAT2_BRB_OCTET 0x107e0 2325*adfc5217SJeff Kirsher #define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328 2326*adfc5217SJeff Kirsher #define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c 2327*adfc5217SJeff Kirsher /* [RW 1] port swap mux selection. If this register equal to 0 then port 2328*adfc5217SJeff Kirsher swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then 2329*adfc5217SJeff Kirsher ort swap is equal to ~nig_registers_port_swap.port_swap */ 2330*adfc5217SJeff Kirsher #define NIG_REG_STRAP_OVERRIDE 0x10398 2331*adfc5217SJeff Kirsher /* [RW 1] output enable for RX_XCM0 IF */ 2332*adfc5217SJeff Kirsher #define NIG_REG_XCM0_OUT_EN 0x100f0 2333*adfc5217SJeff Kirsher /* [RW 1] output enable for RX_XCM1 IF */ 2334*adfc5217SJeff Kirsher #define NIG_REG_XCM1_OUT_EN 0x100f4 2335*adfc5217SJeff Kirsher /* [RW 1] control to xgxs - remote PHY in-band MDIO */ 2336*adfc5217SJeff Kirsher #define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348 2337*adfc5217SJeff Kirsher /* [RW 5] control to xgxs - CL45 DEVAD */ 2338*adfc5217SJeff Kirsher #define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c 2339*adfc5217SJeff Kirsher /* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */ 2340*adfc5217SJeff Kirsher #define NIG_REG_XGXS0_CTRL_MD_ST 0x10338 2341*adfc5217SJeff Kirsher /* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */ 2342*adfc5217SJeff Kirsher #define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340 2343*adfc5217SJeff Kirsher /* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */ 2344*adfc5217SJeff Kirsher #define NIG_REG_XGXS0_STATUS_LINK10G 0x10680 2345*adfc5217SJeff Kirsher /* [R 4] status from xgxs0 that inputs to interrupt logic of link status */ 2346*adfc5217SJeff Kirsher #define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684 2347*adfc5217SJeff Kirsher /* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */ 2348*adfc5217SJeff Kirsher #define NIG_REG_XGXS_LANE_SEL_P0 0x102e8 2349*adfc5217SJeff Kirsher /* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */ 2350*adfc5217SJeff Kirsher #define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0 2351*adfc5217SJeff Kirsher #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0) 2352*adfc5217SJeff Kirsher #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9) 2353*adfc5217SJeff Kirsher #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15) 2354*adfc5217SJeff Kirsher #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18) 2355*adfc5217SJeff Kirsher #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18 2356*adfc5217SJeff Kirsher /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter. */ 2357*adfc5217SJeff Kirsher #define PBF_REG_COS0_UPPER_BOUND 0x15c05c 2358*adfc5217SJeff Kirsher /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter 2359*adfc5217SJeff Kirsher * of port 0. */ 2360*adfc5217SJeff Kirsher #define PBF_REG_COS0_UPPER_BOUND_P0 0x15c2cc 2361*adfc5217SJeff Kirsher /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter 2362*adfc5217SJeff Kirsher * of port 1. */ 2363*adfc5217SJeff Kirsher #define PBF_REG_COS0_UPPER_BOUND_P1 0x15c2e4 2364*adfc5217SJeff Kirsher /* [RW 31] The weight of COS0 in the ETS command arbiter. */ 2365*adfc5217SJeff Kirsher #define PBF_REG_COS0_WEIGHT 0x15c054 2366*adfc5217SJeff Kirsher /* [RW 31] The weight of COS0 in port 0 ETS command arbiter. */ 2367*adfc5217SJeff Kirsher #define PBF_REG_COS0_WEIGHT_P0 0x15c2a8 2368*adfc5217SJeff Kirsher /* [RW 31] The weight of COS0 in port 1 ETS command arbiter. */ 2369*adfc5217SJeff Kirsher #define PBF_REG_COS0_WEIGHT_P1 0x15c2c0 2370*adfc5217SJeff Kirsher /* [RW 31] The upper bound of the weight of COS1 in the ETS command arbiter. */ 2371*adfc5217SJeff Kirsher #define PBF_REG_COS1_UPPER_BOUND 0x15c060 2372*adfc5217SJeff Kirsher /* [RW 31] The weight of COS1 in the ETS command arbiter. */ 2373*adfc5217SJeff Kirsher #define PBF_REG_COS1_WEIGHT 0x15c058 2374*adfc5217SJeff Kirsher /* [RW 31] The weight of COS1 in port 0 ETS command arbiter. */ 2375*adfc5217SJeff Kirsher #define PBF_REG_COS1_WEIGHT_P0 0x15c2ac 2376*adfc5217SJeff Kirsher /* [RW 31] The weight of COS1 in port 1 ETS command arbiter. */ 2377*adfc5217SJeff Kirsher #define PBF_REG_COS1_WEIGHT_P1 0x15c2c4 2378*adfc5217SJeff Kirsher /* [RW 31] The weight of COS2 in port 0 ETS command arbiter. */ 2379*adfc5217SJeff Kirsher #define PBF_REG_COS2_WEIGHT_P0 0x15c2b0 2380*adfc5217SJeff Kirsher /* [RW 31] The weight of COS2 in port 1 ETS command arbiter. */ 2381*adfc5217SJeff Kirsher #define PBF_REG_COS2_WEIGHT_P1 0x15c2c8 2382*adfc5217SJeff Kirsher /* [RW 31] The weight of COS3 in port 0 ETS command arbiter. */ 2383*adfc5217SJeff Kirsher #define PBF_REG_COS3_WEIGHT_P0 0x15c2b4 2384*adfc5217SJeff Kirsher /* [RW 31] The weight of COS4 in port 0 ETS command arbiter. */ 2385*adfc5217SJeff Kirsher #define PBF_REG_COS4_WEIGHT_P0 0x15c2b8 2386*adfc5217SJeff Kirsher /* [RW 31] The weight of COS5 in port 0 ETS command arbiter. */ 2387*adfc5217SJeff Kirsher #define PBF_REG_COS5_WEIGHT_P0 0x15c2bc 2388*adfc5217SJeff Kirsher /* [R 11] Current credit for the LB queue in the tx port buffers in 16 byte 2389*adfc5217SJeff Kirsher * lines. */ 2390*adfc5217SJeff Kirsher #define PBF_REG_CREDIT_LB_Q 0x140338 2391*adfc5217SJeff Kirsher /* [R 11] Current credit for queue 0 in the tx port buffers in 16 byte 2392*adfc5217SJeff Kirsher * lines. */ 2393*adfc5217SJeff Kirsher #define PBF_REG_CREDIT_Q0 0x14033c 2394*adfc5217SJeff Kirsher /* [R 11] Current credit for queue 1 in the tx port buffers in 16 byte 2395*adfc5217SJeff Kirsher * lines. */ 2396*adfc5217SJeff Kirsher #define PBF_REG_CREDIT_Q1 0x140340 2397*adfc5217SJeff Kirsher /* [RW 1] Disable processing further tasks from port 0 (after ending the 2398*adfc5217SJeff Kirsher current task in process). */ 2399*adfc5217SJeff Kirsher #define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c 2400*adfc5217SJeff Kirsher /* [RW 1] Disable processing further tasks from port 1 (after ending the 2401*adfc5217SJeff Kirsher current task in process). */ 2402*adfc5217SJeff Kirsher #define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060 2403*adfc5217SJeff Kirsher /* [RW 1] Disable processing further tasks from port 4 (after ending the 2404*adfc5217SJeff Kirsher current task in process). */ 2405*adfc5217SJeff Kirsher #define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c 2406*adfc5217SJeff Kirsher #define PBF_REG_DISABLE_PF 0x1402e8 2407*adfc5217SJeff Kirsher /* [RW 18] For port 0: For each client that is subject to WFQ (the 2408*adfc5217SJeff Kirsher * corresponding bit is 1); indicates to which of the credit registers this 2409*adfc5217SJeff Kirsher * client is mapped. For clients which are not credit blocked; their mapping 2410*adfc5217SJeff Kirsher * is dont care. */ 2411*adfc5217SJeff Kirsher #define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 0x15c288 2412*adfc5217SJeff Kirsher /* [RW 9] For port 1: For each client that is subject to WFQ (the 2413*adfc5217SJeff Kirsher * corresponding bit is 1); indicates to which of the credit registers this 2414*adfc5217SJeff Kirsher * client is mapped. For clients which are not credit blocked; their mapping 2415*adfc5217SJeff Kirsher * is dont care. */ 2416*adfc5217SJeff Kirsher #define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 0x15c28c 2417*adfc5217SJeff Kirsher /* [RW 6] For port 0: Bit per client to indicate if the client competes in 2418*adfc5217SJeff Kirsher * the strict priority arbiter directly (corresponding bit = 1); or first 2419*adfc5217SJeff Kirsher * goes to the RR arbiter (corresponding bit = 0); and then competes in the 2420*adfc5217SJeff Kirsher * lowest priority in the strict-priority arbiter. */ 2421*adfc5217SJeff Kirsher #define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 0x15c278 2422*adfc5217SJeff Kirsher /* [RW 3] For port 1: Bit per client to indicate if the client competes in 2423*adfc5217SJeff Kirsher * the strict priority arbiter directly (corresponding bit = 1); or first 2424*adfc5217SJeff Kirsher * goes to the RR arbiter (corresponding bit = 0); and then competes in the 2425*adfc5217SJeff Kirsher * lowest priority in the strict-priority arbiter. */ 2426*adfc5217SJeff Kirsher #define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 0x15c27c 2427*adfc5217SJeff Kirsher /* [RW 6] For port 0: Bit per client to indicate if the client is subject to 2428*adfc5217SJeff Kirsher * WFQ credit blocking (corresponding bit = 1). */ 2429*adfc5217SJeff Kirsher #define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 0x15c280 2430*adfc5217SJeff Kirsher /* [RW 3] For port 0: Bit per client to indicate if the client is subject to 2431*adfc5217SJeff Kirsher * WFQ credit blocking (corresponding bit = 1). */ 2432*adfc5217SJeff Kirsher #define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 0x15c284 2433*adfc5217SJeff Kirsher /* [RW 16] For port 0: The number of strict priority arbitration slots 2434*adfc5217SJeff Kirsher * between 2 RR arbitration slots. A value of 0 means no strict priority 2435*adfc5217SJeff Kirsher * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR 2436*adfc5217SJeff Kirsher * arbiter. */ 2437*adfc5217SJeff Kirsher #define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 0x15c2a0 2438*adfc5217SJeff Kirsher /* [RW 16] For port 1: The number of strict priority arbitration slots 2439*adfc5217SJeff Kirsher * between 2 RR arbitration slots. A value of 0 means no strict priority 2440*adfc5217SJeff Kirsher * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR 2441*adfc5217SJeff Kirsher * arbiter. */ 2442*adfc5217SJeff Kirsher #define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 0x15c2a4 2443*adfc5217SJeff Kirsher /* [RW 18] For port 0: Indicates which client is connected to each priority 2444*adfc5217SJeff Kirsher * in the strict-priority arbiter. Priority 0 is the highest priority, and 2445*adfc5217SJeff Kirsher * priority 5 is the lowest; to which the RR output is connected to (this is 2446*adfc5217SJeff Kirsher * not configurable). */ 2447*adfc5217SJeff Kirsher #define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 0x15c270 2448*adfc5217SJeff Kirsher /* [RW 9] For port 1: Indicates which client is connected to each priority 2449*adfc5217SJeff Kirsher * in the strict-priority arbiter. Priority 0 is the highest priority, and 2450*adfc5217SJeff Kirsher * priority 5 is the lowest; to which the RR output is connected to (this is 2451*adfc5217SJeff Kirsher * not configurable). */ 2452*adfc5217SJeff Kirsher #define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 0x15c274 2453*adfc5217SJeff Kirsher /* [RW 1] Indicates that ETS is performed between the COSes in the command 2454*adfc5217SJeff Kirsher * arbiter. If reset strict priority w/ anti-starvation will be performed 2455*adfc5217SJeff Kirsher * w/o WFQ. */ 2456*adfc5217SJeff Kirsher #define PBF_REG_ETS_ENABLED 0x15c050 2457*adfc5217SJeff Kirsher /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2458*adfc5217SJeff Kirsher * Ethernet header. */ 2459*adfc5217SJeff Kirsher #define PBF_REG_HDRS_AFTER_BASIC 0x15c0a8 2460*adfc5217SJeff Kirsher /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */ 2461*adfc5217SJeff Kirsher #define PBF_REG_HDRS_AFTER_TAG_0 0x15c0b8 2462*adfc5217SJeff Kirsher /* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest 2463*adfc5217SJeff Kirsher * priority in the command arbiter. */ 2464*adfc5217SJeff Kirsher #define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04c 2465*adfc5217SJeff Kirsher #define PBF_REG_IF_ENABLE_REG 0x140044 2466*adfc5217SJeff Kirsher /* [RW 1] Init bit. When set the initial credits are copied to the credit 2467*adfc5217SJeff Kirsher registers (except the port credits). Should be set and then reset after 2468*adfc5217SJeff Kirsher the configuration of the block has ended. */ 2469*adfc5217SJeff Kirsher #define PBF_REG_INIT 0x140000 2470*adfc5217SJeff Kirsher /* [RW 11] Initial credit for the LB queue in the tx port buffers in 16 byte 2471*adfc5217SJeff Kirsher * lines. */ 2472*adfc5217SJeff Kirsher #define PBF_REG_INIT_CRD_LB_Q 0x15c248 2473*adfc5217SJeff Kirsher /* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte 2474*adfc5217SJeff Kirsher * lines. */ 2475*adfc5217SJeff Kirsher #define PBF_REG_INIT_CRD_Q0 0x15c230 2476*adfc5217SJeff Kirsher /* [RW 11] Initial credit for queue 1 in the tx port buffers in 16 byte 2477*adfc5217SJeff Kirsher * lines. */ 2478*adfc5217SJeff Kirsher #define PBF_REG_INIT_CRD_Q1 0x15c234 2479*adfc5217SJeff Kirsher /* [RW 1] Init bit for port 0. When set the initial credit of port 0 is 2480*adfc5217SJeff Kirsher copied to the credit register. Should be set and then reset after the 2481*adfc5217SJeff Kirsher configuration of the port has ended. */ 2482*adfc5217SJeff Kirsher #define PBF_REG_INIT_P0 0x140004 2483*adfc5217SJeff Kirsher /* [RW 1] Init bit for port 1. When set the initial credit of port 1 is 2484*adfc5217SJeff Kirsher copied to the credit register. Should be set and then reset after the 2485*adfc5217SJeff Kirsher configuration of the port has ended. */ 2486*adfc5217SJeff Kirsher #define PBF_REG_INIT_P1 0x140008 2487*adfc5217SJeff Kirsher /* [RW 1] Init bit for port 4. When set the initial credit of port 4 is 2488*adfc5217SJeff Kirsher copied to the credit register. Should be set and then reset after the 2489*adfc5217SJeff Kirsher configuration of the port has ended. */ 2490*adfc5217SJeff Kirsher #define PBF_REG_INIT_P4 0x14000c 2491*adfc5217SJeff Kirsher /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2492*adfc5217SJeff Kirsher * the LB queue. Reset upon init. */ 2493*adfc5217SJeff Kirsher #define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q 0x140354 2494*adfc5217SJeff Kirsher /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2495*adfc5217SJeff Kirsher * queue 0. Reset upon init. */ 2496*adfc5217SJeff Kirsher #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 0x140358 2497*adfc5217SJeff Kirsher /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2498*adfc5217SJeff Kirsher * queue 1. Reset upon init. */ 2499*adfc5217SJeff Kirsher #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 0x14035c 2500*adfc5217SJeff Kirsher /* [RW 1] Enable for mac interface 0. */ 2501*adfc5217SJeff Kirsher #define PBF_REG_MAC_IF0_ENABLE 0x140030 2502*adfc5217SJeff Kirsher /* [RW 1] Enable for mac interface 1. */ 2503*adfc5217SJeff Kirsher #define PBF_REG_MAC_IF1_ENABLE 0x140034 2504*adfc5217SJeff Kirsher /* [RW 1] Enable for the loopback interface. */ 2505*adfc5217SJeff Kirsher #define PBF_REG_MAC_LB_ENABLE 0x140040 2506*adfc5217SJeff Kirsher /* [RW 6] Bit-map indicating which headers must appear in the packet */ 2507*adfc5217SJeff Kirsher #define PBF_REG_MUST_HAVE_HDRS 0x15c0c4 2508*adfc5217SJeff Kirsher /* [RW 16] The number of strict priority arbitration slots between 2 RR 2509*adfc5217SJeff Kirsher * arbitration slots. A value of 0 means no strict priority cycles; i.e. the 2510*adfc5217SJeff Kirsher * strict-priority w/ anti-starvation arbiter is a RR arbiter. */ 2511*adfc5217SJeff Kirsher #define PBF_REG_NUM_STRICT_ARB_SLOTS 0x15c064 2512*adfc5217SJeff Kirsher /* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause 2513*adfc5217SJeff Kirsher not suppoterd. */ 2514*adfc5217SJeff Kirsher #define PBF_REG_P0_ARB_THRSH 0x1400e4 2515*adfc5217SJeff Kirsher /* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */ 2516*adfc5217SJeff Kirsher #define PBF_REG_P0_CREDIT 0x140200 2517*adfc5217SJeff Kirsher /* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte 2518*adfc5217SJeff Kirsher lines. */ 2519*adfc5217SJeff Kirsher #define PBF_REG_P0_INIT_CRD 0x1400d0 2520*adfc5217SJeff Kirsher /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2521*adfc5217SJeff Kirsher * port 0. Reset upon init. */ 2522*adfc5217SJeff Kirsher #define PBF_REG_P0_INTERNAL_CRD_FREED_CNT 0x140308 2523*adfc5217SJeff Kirsher /* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */ 2524*adfc5217SJeff Kirsher #define PBF_REG_P0_PAUSE_ENABLE 0x140014 2525*adfc5217SJeff Kirsher /* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */ 2526*adfc5217SJeff Kirsher #define PBF_REG_P0_TASK_CNT 0x140204 2527*adfc5217SJeff Kirsher /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines 2528*adfc5217SJeff Kirsher * freed from the task queue of port 0. Reset upon init. */ 2529*adfc5217SJeff Kirsher #define PBF_REG_P0_TQ_LINES_FREED_CNT 0x1402f0 2530*adfc5217SJeff Kirsher /* [R 12] Number of 8 bytes lines occupied in the task queue of port 0. */ 2531*adfc5217SJeff Kirsher #define PBF_REG_P0_TQ_OCCUPANCY 0x1402fc 2532*adfc5217SJeff Kirsher /* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port 2533*adfc5217SJeff Kirsher * buffers in 16 byte lines. */ 2534*adfc5217SJeff Kirsher #define PBF_REG_P1_CREDIT 0x140208 2535*adfc5217SJeff Kirsher /* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port 2536*adfc5217SJeff Kirsher * buffers in 16 byte lines. */ 2537*adfc5217SJeff Kirsher #define PBF_REG_P1_INIT_CRD 0x1400d4 2538*adfc5217SJeff Kirsher /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2539*adfc5217SJeff Kirsher * port 1. Reset upon init. */ 2540*adfc5217SJeff Kirsher #define PBF_REG_P1_INTERNAL_CRD_FREED_CNT 0x14030c 2541*adfc5217SJeff Kirsher /* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */ 2542*adfc5217SJeff Kirsher #define PBF_REG_P1_TASK_CNT 0x14020c 2543*adfc5217SJeff Kirsher /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines 2544*adfc5217SJeff Kirsher * freed from the task queue of port 1. Reset upon init. */ 2545*adfc5217SJeff Kirsher #define PBF_REG_P1_TQ_LINES_FREED_CNT 0x1402f4 2546*adfc5217SJeff Kirsher /* [R 12] Number of 8 bytes lines occupied in the task queue of port 1. */ 2547*adfc5217SJeff Kirsher #define PBF_REG_P1_TQ_OCCUPANCY 0x140300 2548*adfc5217SJeff Kirsher /* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */ 2549*adfc5217SJeff Kirsher #define PBF_REG_P4_CREDIT 0x140210 2550*adfc5217SJeff Kirsher /* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte 2551*adfc5217SJeff Kirsher lines. */ 2552*adfc5217SJeff Kirsher #define PBF_REG_P4_INIT_CRD 0x1400e0 2553*adfc5217SJeff Kirsher /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2554*adfc5217SJeff Kirsher * port 4. Reset upon init. */ 2555*adfc5217SJeff Kirsher #define PBF_REG_P4_INTERNAL_CRD_FREED_CNT 0x140310 2556*adfc5217SJeff Kirsher /* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */ 2557*adfc5217SJeff Kirsher #define PBF_REG_P4_TASK_CNT 0x140214 2558*adfc5217SJeff Kirsher /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines 2559*adfc5217SJeff Kirsher * freed from the task queue of port 4. Reset upon init. */ 2560*adfc5217SJeff Kirsher #define PBF_REG_P4_TQ_LINES_FREED_CNT 0x1402f8 2561*adfc5217SJeff Kirsher /* [R 12] Number of 8 bytes lines occupied in the task queue of port 4. */ 2562*adfc5217SJeff Kirsher #define PBF_REG_P4_TQ_OCCUPANCY 0x140304 2563*adfc5217SJeff Kirsher /* [RW 5] Interrupt mask register #0 read/write */ 2564*adfc5217SJeff Kirsher #define PBF_REG_PBF_INT_MASK 0x1401d4 2565*adfc5217SJeff Kirsher /* [R 5] Interrupt register #0 read */ 2566*adfc5217SJeff Kirsher #define PBF_REG_PBF_INT_STS 0x1401c8 2567*adfc5217SJeff Kirsher /* [RW 20] Parity mask register #0 read/write */ 2568*adfc5217SJeff Kirsher #define PBF_REG_PBF_PRTY_MASK 0x1401e4 2569*adfc5217SJeff Kirsher /* [RC 20] Parity register #0 read clear */ 2570*adfc5217SJeff Kirsher #define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc 2571*adfc5217SJeff Kirsher /* [RW 16] The Ethernet type value for L2 tag 0 */ 2572*adfc5217SJeff Kirsher #define PBF_REG_TAG_ETHERTYPE_0 0x15c090 2573*adfc5217SJeff Kirsher /* [RW 4] The length of the info field for L2 tag 0. The length is between 2574*adfc5217SJeff Kirsher * 2B and 14B; in 2B granularity */ 2575*adfc5217SJeff Kirsher #define PBF_REG_TAG_LEN_0 0x15c09c 2576*adfc5217SJeff Kirsher /* [R 32] Cyclic counter for number of 8 byte lines freed from the LB task 2577*adfc5217SJeff Kirsher * queue. Reset upon init. */ 2578*adfc5217SJeff Kirsher #define PBF_REG_TQ_LINES_FREED_CNT_LB_Q 0x14038c 2579*adfc5217SJeff Kirsher /* [R 32] Cyclic counter for number of 8 byte lines freed from the task 2580*adfc5217SJeff Kirsher * queue 0. Reset upon init. */ 2581*adfc5217SJeff Kirsher #define PBF_REG_TQ_LINES_FREED_CNT_Q0 0x140390 2582*adfc5217SJeff Kirsher /* [R 32] Cyclic counter for number of 8 byte lines freed from task queue 1. 2583*adfc5217SJeff Kirsher * Reset upon init. */ 2584*adfc5217SJeff Kirsher #define PBF_REG_TQ_LINES_FREED_CNT_Q1 0x140394 2585*adfc5217SJeff Kirsher /* [R 13] Number of 8 bytes lines occupied in the task queue of the LB 2586*adfc5217SJeff Kirsher * queue. */ 2587*adfc5217SJeff Kirsher #define PBF_REG_TQ_OCCUPANCY_LB_Q 0x1403a8 2588*adfc5217SJeff Kirsher /* [R 13] Number of 8 bytes lines occupied in the task queue of queue 0. */ 2589*adfc5217SJeff Kirsher #define PBF_REG_TQ_OCCUPANCY_Q0 0x1403ac 2590*adfc5217SJeff Kirsher /* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */ 2591*adfc5217SJeff Kirsher #define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b0 2592*adfc5217SJeff Kirsher #define PB_REG_CONTROL 0 2593*adfc5217SJeff Kirsher /* [RW 2] Interrupt mask register #0 read/write */ 2594*adfc5217SJeff Kirsher #define PB_REG_PB_INT_MASK 0x28 2595*adfc5217SJeff Kirsher /* [R 2] Interrupt register #0 read */ 2596*adfc5217SJeff Kirsher #define PB_REG_PB_INT_STS 0x1c 2597*adfc5217SJeff Kirsher /* [RW 4] Parity mask register #0 read/write */ 2598*adfc5217SJeff Kirsher #define PB_REG_PB_PRTY_MASK 0x38 2599*adfc5217SJeff Kirsher /* [R 4] Parity register #0 read */ 2600*adfc5217SJeff Kirsher #define PB_REG_PB_PRTY_STS 0x2c 2601*adfc5217SJeff Kirsher /* [RC 4] Parity register #0 read clear */ 2602*adfc5217SJeff Kirsher #define PB_REG_PB_PRTY_STS_CLR 0x30 2603*adfc5217SJeff Kirsher #define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 2604*adfc5217SJeff Kirsher #define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8) 2605*adfc5217SJeff Kirsher #define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1) 2606*adfc5217SJeff Kirsher #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN (0x1<<6) 2607*adfc5217SJeff Kirsher #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7) 2608*adfc5217SJeff Kirsher #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4) 2609*adfc5217SJeff Kirsher #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3) 2610*adfc5217SJeff Kirsher #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5) 2611*adfc5217SJeff Kirsher #define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN (0x1<<2) 2612*adfc5217SJeff Kirsher /* [R 8] Config space A attention dirty bits. Each bit indicates that the 2613*adfc5217SJeff Kirsher * corresponding PF generates config space A attention. Set by PXP. Reset by 2614*adfc5217SJeff Kirsher * MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits 2615*adfc5217SJeff Kirsher * from both paths. */ 2616*adfc5217SJeff Kirsher #define PGLUE_B_REG_CFG_SPACE_A_REQUEST 0x9010 2617*adfc5217SJeff Kirsher /* [R 8] Config space B attention dirty bits. Each bit indicates that the 2618*adfc5217SJeff Kirsher * corresponding PF generates config space B attention. Set by PXP. Reset by 2619*adfc5217SJeff Kirsher * MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits 2620*adfc5217SJeff Kirsher * from both paths. */ 2621*adfc5217SJeff Kirsher #define PGLUE_B_REG_CFG_SPACE_B_REQUEST 0x9014 2622*adfc5217SJeff Kirsher /* [RW 1] Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1 2623*adfc5217SJeff Kirsher * - enable. */ 2624*adfc5217SJeff Kirsher #define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE 0x9194 2625*adfc5217SJeff Kirsher /* [RW 18] Type B VF inbound interrupt table for CSDM: bits[17:9]-mask; 2626*adfc5217SJeff Kirsher * its[8:0]-address. Bits [1:0] must be zero (DW resolution address). */ 2627*adfc5217SJeff Kirsher #define PGLUE_B_REG_CSDM_INB_INT_B_VF 0x916c 2628*adfc5217SJeff Kirsher /* [RW 1] Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1 2629*adfc5217SJeff Kirsher * - enable. */ 2630*adfc5217SJeff Kirsher #define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE 0x919c 2631*adfc5217SJeff Kirsher /* [RW 16] Start offset of CSDM zone A (queue zone) in the internal RAM */ 2632*adfc5217SJeff Kirsher #define PGLUE_B_REG_CSDM_START_OFFSET_A 0x9100 2633*adfc5217SJeff Kirsher /* [RW 16] Start offset of CSDM zone B (legacy zone) in the internal RAM */ 2634*adfc5217SJeff Kirsher #define PGLUE_B_REG_CSDM_START_OFFSET_B 0x9108 2635*adfc5217SJeff Kirsher /* [RW 5] VF Shift of CSDM zone B (legacy zone) in the internal RAM */ 2636*adfc5217SJeff Kirsher #define PGLUE_B_REG_CSDM_VF_SHIFT_B 0x9110 2637*adfc5217SJeff Kirsher /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */ 2638*adfc5217SJeff Kirsher #define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF 0x91ac 2639*adfc5217SJeff Kirsher /* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates 2640*adfc5217SJeff Kirsher * that the FLR register of the corresponding PF was set. Set by PXP. Reset 2641*adfc5217SJeff Kirsher * by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits 2642*adfc5217SJeff Kirsher * from both paths. */ 2643*adfc5217SJeff Kirsher #define PGLUE_B_REG_FLR_REQUEST_PF_7_0 0x9028 2644*adfc5217SJeff Kirsher /* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1 2645*adfc5217SJeff Kirsher * to a bit in this register in order to clear the corresponding bit in 2646*adfc5217SJeff Kirsher * flr_request_pf_7_0 register. Note: register contains bits from both 2647*adfc5217SJeff Kirsher * paths. */ 2648*adfc5217SJeff Kirsher #define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR 0x9418 2649*adfc5217SJeff Kirsher /* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit 2650*adfc5217SJeff Kirsher * indicates that the FLR register of the corresponding VF was set. Set by 2651*adfc5217SJeff Kirsher * PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr. */ 2652*adfc5217SJeff Kirsher #define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x9024 2653*adfc5217SJeff Kirsher /* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit 2654*adfc5217SJeff Kirsher * indicates that the FLR register of the corresponding VF was set. Set by 2655*adfc5217SJeff Kirsher * PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr. */ 2656*adfc5217SJeff Kirsher #define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x9018 2657*adfc5217SJeff Kirsher /* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit 2658*adfc5217SJeff Kirsher * indicates that the FLR register of the corresponding VF was set. Set by 2659*adfc5217SJeff Kirsher * PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr. */ 2660*adfc5217SJeff Kirsher #define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x901c 2661*adfc5217SJeff Kirsher /* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit 2662*adfc5217SJeff Kirsher * indicates that the FLR register of the corresponding VF was set. Set by 2663*adfc5217SJeff Kirsher * PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr. */ 2664*adfc5217SJeff Kirsher #define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x9020 2665*adfc5217SJeff Kirsher /* [R 8] Each bit indicates an incorrect behavior in user RX interface. Bit 2666*adfc5217SJeff Kirsher * 0 - Target memory read arrived with a correctable error. Bit 1 - Target 2667*adfc5217SJeff Kirsher * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW 2668*adfc5217SJeff Kirsher * arrived with a correctable error. Bit 3 - Configuration RW arrived with 2669*adfc5217SJeff Kirsher * an uncorrectable error. Bit 4 - Completion with Configuration Request 2670*adfc5217SJeff Kirsher * Retry Status. Bit 5 - Expansion ROM access received with a write request. 2671*adfc5217SJeff Kirsher * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and 2672*adfc5217SJeff Kirsher * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010; 2673*adfc5217SJeff Kirsher * and pcie_rx_last not asserted. */ 2674*adfc5217SJeff Kirsher #define PGLUE_B_REG_INCORRECT_RCV_DETAILS 0x9068 2675*adfc5217SJeff Kirsher #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942c 2676*adfc5217SJeff Kirsher #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x9430 2677*adfc5217SJeff Kirsher #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x9434 2678*adfc5217SJeff Kirsher #define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x9438 2679*adfc5217SJeff Kirsher /* [R 9] Interrupt register #0 read */ 2680*adfc5217SJeff Kirsher #define PGLUE_B_REG_PGLUE_B_INT_STS 0x9298 2681*adfc5217SJeff Kirsher /* [RC 9] Interrupt register #0 read clear */ 2682*adfc5217SJeff Kirsher #define PGLUE_B_REG_PGLUE_B_INT_STS_CLR 0x929c 2683*adfc5217SJeff Kirsher /* [RW 2] Parity mask register #0 read/write */ 2684*adfc5217SJeff Kirsher #define PGLUE_B_REG_PGLUE_B_PRTY_MASK 0x92b4 2685*adfc5217SJeff Kirsher /* [R 2] Parity register #0 read */ 2686*adfc5217SJeff Kirsher #define PGLUE_B_REG_PGLUE_B_PRTY_STS 0x92a8 2687*adfc5217SJeff Kirsher /* [RC 2] Parity register #0 read clear */ 2688*adfc5217SJeff Kirsher #define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR 0x92ac 2689*adfc5217SJeff Kirsher /* [R 13] Details of first request received with error. [2:0] - PFID. [3] - 2690*adfc5217SJeff Kirsher * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion 2691*adfc5217SJeff Kirsher * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 - 2692*adfc5217SJeff Kirsher * completer abort. 3 - Illegal value for this field. [12] valid - indicates 2693*adfc5217SJeff Kirsher * if there was a completion error since the last time this register was 2694*adfc5217SJeff Kirsher * cleared. */ 2695*adfc5217SJeff Kirsher #define PGLUE_B_REG_RX_ERR_DETAILS 0x9080 2696*adfc5217SJeff Kirsher /* [R 18] Details of first ATS Translation Completion request received with 2697*adfc5217SJeff Kirsher * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code - 2698*adfc5217SJeff Kirsher * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 - 2699*adfc5217SJeff Kirsher * unsupported request. 2 - completer abort. 3 - Illegal value for this 2700*adfc5217SJeff Kirsher * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a 2701*adfc5217SJeff Kirsher * completion error since the last time this register was cleared. */ 2702*adfc5217SJeff Kirsher #define PGLUE_B_REG_RX_TCPL_ERR_DETAILS 0x9084 2703*adfc5217SJeff Kirsher /* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to 2704*adfc5217SJeff Kirsher * a bit in this register in order to clear the corresponding bit in 2705*adfc5217SJeff Kirsher * shadow_bme_pf_7_0 register. MCP should never use this unless a 2706*adfc5217SJeff Kirsher * work-around is needed. Note: register contains bits from both paths. */ 2707*adfc5217SJeff Kirsher #define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR 0x9458 2708*adfc5217SJeff Kirsher /* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the 2709*adfc5217SJeff Kirsher * VF enable register of the corresponding PF is written to 0 and was 2710*adfc5217SJeff Kirsher * previously 1. Set by PXP. Reset by MCP writing 1 to 2711*adfc5217SJeff Kirsher * sr_iov_disabled_request_clr. Note: register contains bits from both 2712*adfc5217SJeff Kirsher * paths. */ 2713*adfc5217SJeff Kirsher #define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x9030 2714*adfc5217SJeff Kirsher /* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read 2715*adfc5217SJeff Kirsher * completion did not return yet. 1 - tag is unused. Same functionality as 2716*adfc5217SJeff Kirsher * pxp2_registers_pgl_exp_rom_data2 for tags 0-31. */ 2717*adfc5217SJeff Kirsher #define PGLUE_B_REG_TAGS_63_32 0x9244 2718*adfc5217SJeff Kirsher /* [RW 1] Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1 2719*adfc5217SJeff Kirsher * - enable. */ 2720*adfc5217SJeff Kirsher #define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE 0x9170 2721*adfc5217SJeff Kirsher /* [RW 16] Start offset of TSDM zone A (queue zone) in the internal RAM */ 2722*adfc5217SJeff Kirsher #define PGLUE_B_REG_TSDM_START_OFFSET_A 0x90c4 2723*adfc5217SJeff Kirsher /* [RW 16] Start offset of TSDM zone B (legacy zone) in the internal RAM */ 2724*adfc5217SJeff Kirsher #define PGLUE_B_REG_TSDM_START_OFFSET_B 0x90cc 2725*adfc5217SJeff Kirsher /* [RW 5] VF Shift of TSDM zone B (legacy zone) in the internal RAM */ 2726*adfc5217SJeff Kirsher #define PGLUE_B_REG_TSDM_VF_SHIFT_B 0x90d4 2727*adfc5217SJeff Kirsher /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */ 2728*adfc5217SJeff Kirsher #define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF 0x91a0 2729*adfc5217SJeff Kirsher /* [R 32] Address [31:0] of first read request not submitted due to error */ 2730*adfc5217SJeff Kirsher #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x9098 2731*adfc5217SJeff Kirsher /* [R 32] Address [63:32] of first read request not submitted due to error */ 2732*adfc5217SJeff Kirsher #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x909c 2733*adfc5217SJeff Kirsher /* [R 31] Details of first read request not submitted due to error. [4:0] 2734*adfc5217SJeff Kirsher * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request. 2735*adfc5217SJeff Kirsher * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] - 2736*adfc5217SJeff Kirsher * VFID. */ 2737*adfc5217SJeff Kirsher #define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x90a0 2738*adfc5217SJeff Kirsher /* [R 26] Details of first read request not submitted due to error. [15:0] 2739*adfc5217SJeff Kirsher * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type - 2740*adfc5217SJeff Kirsher * [21] - Indicates was_error was set; [22] - Indicates BME was cleared; 2741*adfc5217SJeff Kirsher * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent 2742*adfc5217SJeff Kirsher * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid - 2743*adfc5217SJeff Kirsher * indicates if there was a request not submitted due to error since the 2744*adfc5217SJeff Kirsher * last time this register was cleared. */ 2745*adfc5217SJeff Kirsher #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x90a4 2746*adfc5217SJeff Kirsher /* [R 32] Address [31:0] of first write request not submitted due to error */ 2747*adfc5217SJeff Kirsher #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x9088 2748*adfc5217SJeff Kirsher /* [R 32] Address [63:32] of first write request not submitted due to error */ 2749*adfc5217SJeff Kirsher #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x908c 2750*adfc5217SJeff Kirsher /* [R 31] Details of first write request not submitted due to error. [4:0] 2751*adfc5217SJeff Kirsher * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] 2752*adfc5217SJeff Kirsher * - VFID. */ 2753*adfc5217SJeff Kirsher #define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x9090 2754*adfc5217SJeff Kirsher /* [R 26] Details of first write request not submitted due to error. [15:0] 2755*adfc5217SJeff Kirsher * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type - 2756*adfc5217SJeff Kirsher * [21] - Indicates was_error was set; [22] - Indicates BME was cleared; 2757*adfc5217SJeff Kirsher * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent 2758*adfc5217SJeff Kirsher * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid - 2759*adfc5217SJeff Kirsher * indicates if there was a request not submitted due to error since the 2760*adfc5217SJeff Kirsher * last time this register was cleared. */ 2761*adfc5217SJeff Kirsher #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x9094 2762*adfc5217SJeff Kirsher /* [RW 10] Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask; 2763*adfc5217SJeff Kirsher * its[4:0]-address relative to start_offset_a. Bits [1:0] can have any 2764*adfc5217SJeff Kirsher * value (Byte resolution address). */ 2765*adfc5217SJeff Kirsher #define PGLUE_B_REG_USDM_INB_INT_A_0 0x9128 2766*adfc5217SJeff Kirsher #define PGLUE_B_REG_USDM_INB_INT_A_1 0x912c 2767*adfc5217SJeff Kirsher #define PGLUE_B_REG_USDM_INB_INT_A_2 0x9130 2768*adfc5217SJeff Kirsher #define PGLUE_B_REG_USDM_INB_INT_A_3 0x9134 2769*adfc5217SJeff Kirsher #define PGLUE_B_REG_USDM_INB_INT_A_4 0x9138 2770*adfc5217SJeff Kirsher #define PGLUE_B_REG_USDM_INB_INT_A_5 0x913c 2771*adfc5217SJeff Kirsher #define PGLUE_B_REG_USDM_INB_INT_A_6 0x9140 2772*adfc5217SJeff Kirsher /* [RW 1] Type A PF enable inbound interrupt table for USDM. 0 - disable; 1 2773*adfc5217SJeff Kirsher * - enable. */ 2774*adfc5217SJeff Kirsher #define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE 0x917c 2775*adfc5217SJeff Kirsher /* [RW 1] Type A VF enable inbound interrupt table for USDM. 0 - disable; 1 2776*adfc5217SJeff Kirsher * - enable. */ 2777*adfc5217SJeff Kirsher #define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE 0x9180 2778*adfc5217SJeff Kirsher /* [RW 1] Type B VF enable inbound interrupt table for USDM. 0 - disable; 1 2779*adfc5217SJeff Kirsher * - enable. */ 2780*adfc5217SJeff Kirsher #define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE 0x9184 2781*adfc5217SJeff Kirsher /* [RW 16] Start offset of USDM zone A (queue zone) in the internal RAM */ 2782*adfc5217SJeff Kirsher #define PGLUE_B_REG_USDM_START_OFFSET_A 0x90d8 2783*adfc5217SJeff Kirsher /* [RW 16] Start offset of USDM zone B (legacy zone) in the internal RAM */ 2784*adfc5217SJeff Kirsher #define PGLUE_B_REG_USDM_START_OFFSET_B 0x90e0 2785*adfc5217SJeff Kirsher /* [RW 5] VF Shift of USDM zone B (legacy zone) in the internal RAM */ 2786*adfc5217SJeff Kirsher #define PGLUE_B_REG_USDM_VF_SHIFT_B 0x90e8 2787*adfc5217SJeff Kirsher /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */ 2788*adfc5217SJeff Kirsher #define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF 0x91a4 2789*adfc5217SJeff Kirsher /* [R 26] Details of first target VF request accessing VF GRC space that 2790*adfc5217SJeff Kirsher * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write. 2791*adfc5217SJeff Kirsher * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a 2792*adfc5217SJeff Kirsher * request accessing VF GRC space that failed permission check since the 2793*adfc5217SJeff Kirsher * last time this register was cleared. Permission checks are: function 2794*adfc5217SJeff Kirsher * permission; R/W permission; address range permission. */ 2795*adfc5217SJeff Kirsher #define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS 0x9234 2796*adfc5217SJeff Kirsher /* [R 31] Details of first target VF request with length violation (too many 2797*adfc5217SJeff Kirsher * DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address). 2798*adfc5217SJeff Kirsher * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30] 2799*adfc5217SJeff Kirsher * valid - indicates if there was a request with length violation since the 2800*adfc5217SJeff Kirsher * last time this register was cleared. Length violations: length of more 2801*adfc5217SJeff Kirsher * than 2DWs; length of 2DWs and address not QW aligned; window is GRC and 2802*adfc5217SJeff Kirsher * length is more than 1 DW. */ 2803*adfc5217SJeff Kirsher #define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS 0x9230 2804*adfc5217SJeff Kirsher /* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates 2805*adfc5217SJeff Kirsher * that there was a completion with uncorrectable error for the 2806*adfc5217SJeff Kirsher * corresponding PF. Set by PXP. Reset by MCP writing 1 to 2807*adfc5217SJeff Kirsher * was_error_pf_7_0_clr. */ 2808*adfc5217SJeff Kirsher #define PGLUE_B_REG_WAS_ERROR_PF_7_0 0x907c 2809*adfc5217SJeff Kirsher /* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1 2810*adfc5217SJeff Kirsher * to a bit in this register in order to clear the corresponding bit in 2811*adfc5217SJeff Kirsher * flr_request_pf_7_0 register. */ 2812*adfc5217SJeff Kirsher #define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR 0x9470 2813*adfc5217SJeff Kirsher /* [R 32] Was_error indication dirty bits for VFs 96 to 127. Each bit 2814*adfc5217SJeff Kirsher * indicates that there was a completion with uncorrectable error for the 2815*adfc5217SJeff Kirsher * corresponding VF. Set by PXP. Reset by MCP writing 1 to 2816*adfc5217SJeff Kirsher * was_error_vf_127_96_clr. */ 2817*adfc5217SJeff Kirsher #define PGLUE_B_REG_WAS_ERROR_VF_127_96 0x9078 2818*adfc5217SJeff Kirsher /* [W 32] Was_error indication dirty bits clear for VFs 96 to 127. MCP 2819*adfc5217SJeff Kirsher * writes 1 to a bit in this register in order to clear the corresponding 2820*adfc5217SJeff Kirsher * bit in was_error_vf_127_96 register. */ 2821*adfc5217SJeff Kirsher #define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR 0x9474 2822*adfc5217SJeff Kirsher /* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit 2823*adfc5217SJeff Kirsher * indicates that there was a completion with uncorrectable error for the 2824*adfc5217SJeff Kirsher * corresponding VF. Set by PXP. Reset by MCP writing 1 to 2825*adfc5217SJeff Kirsher * was_error_vf_31_0_clr. */ 2826*adfc5217SJeff Kirsher #define PGLUE_B_REG_WAS_ERROR_VF_31_0 0x906c 2827*adfc5217SJeff Kirsher /* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes 2828*adfc5217SJeff Kirsher * 1 to a bit in this register in order to clear the corresponding bit in 2829*adfc5217SJeff Kirsher * was_error_vf_31_0 register. */ 2830*adfc5217SJeff Kirsher #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x9478 2831*adfc5217SJeff Kirsher /* [R 32] Was_error indication dirty bits for VFs 32 to 63. Each bit 2832*adfc5217SJeff Kirsher * indicates that there was a completion with uncorrectable error for the 2833*adfc5217SJeff Kirsher * corresponding VF. Set by PXP. Reset by MCP writing 1 to 2834*adfc5217SJeff Kirsher * was_error_vf_63_32_clr. */ 2835*adfc5217SJeff Kirsher #define PGLUE_B_REG_WAS_ERROR_VF_63_32 0x9070 2836*adfc5217SJeff Kirsher /* [W 32] Was_error indication dirty bits clear for VFs 32 to 63. MCP writes 2837*adfc5217SJeff Kirsher * 1 to a bit in this register in order to clear the corresponding bit in 2838*adfc5217SJeff Kirsher * was_error_vf_63_32 register. */ 2839*adfc5217SJeff Kirsher #define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR 0x947c 2840*adfc5217SJeff Kirsher /* [R 32] Was_error indication dirty bits for VFs 64 to 95. Each bit 2841*adfc5217SJeff Kirsher * indicates that there was a completion with uncorrectable error for the 2842*adfc5217SJeff Kirsher * corresponding VF. Set by PXP. Reset by MCP writing 1 to 2843*adfc5217SJeff Kirsher * was_error_vf_95_64_clr. */ 2844*adfc5217SJeff Kirsher #define PGLUE_B_REG_WAS_ERROR_VF_95_64 0x9074 2845*adfc5217SJeff Kirsher /* [W 32] Was_error indication dirty bits clear for VFs 64 to 95. MCP writes 2846*adfc5217SJeff Kirsher * 1 to a bit in this register in order to clear the corresponding bit in 2847*adfc5217SJeff Kirsher * was_error_vf_95_64 register. */ 2848*adfc5217SJeff Kirsher #define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR 0x9480 2849*adfc5217SJeff Kirsher /* [RW 1] Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1 2850*adfc5217SJeff Kirsher * - enable. */ 2851*adfc5217SJeff Kirsher #define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE 0x9188 2852*adfc5217SJeff Kirsher /* [RW 16] Start offset of XSDM zone A (queue zone) in the internal RAM */ 2853*adfc5217SJeff Kirsher #define PGLUE_B_REG_XSDM_START_OFFSET_A 0x90ec 2854*adfc5217SJeff Kirsher /* [RW 16] Start offset of XSDM zone B (legacy zone) in the internal RAM */ 2855*adfc5217SJeff Kirsher #define PGLUE_B_REG_XSDM_START_OFFSET_B 0x90f4 2856*adfc5217SJeff Kirsher /* [RW 5] VF Shift of XSDM zone B (legacy zone) in the internal RAM */ 2857*adfc5217SJeff Kirsher #define PGLUE_B_REG_XSDM_VF_SHIFT_B 0x90fc 2858*adfc5217SJeff Kirsher /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */ 2859*adfc5217SJeff Kirsher #define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF 0x91a8 2860*adfc5217SJeff Kirsher #define PRS_REG_A_PRSU_20 0x40134 2861*adfc5217SJeff Kirsher /* [R 8] debug only: CFC load request current credit. Transaction based. */ 2862*adfc5217SJeff Kirsher #define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164 2863*adfc5217SJeff Kirsher /* [R 8] debug only: CFC search request current credit. Transaction based. */ 2864*adfc5217SJeff Kirsher #define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168 2865*adfc5217SJeff Kirsher /* [RW 6] The initial credit for the search message to the CFC interface. 2866*adfc5217SJeff Kirsher Credit is transaction based. */ 2867*adfc5217SJeff Kirsher #define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c 2868*adfc5217SJeff Kirsher /* [RW 24] CID for port 0 if no match */ 2869*adfc5217SJeff Kirsher #define PRS_REG_CID_PORT_0 0x400fc 2870*adfc5217SJeff Kirsher /* [RW 32] The CM header for flush message where 'load existed' bit in CFC 2871*adfc5217SJeff Kirsher load response is reset and packet type is 0. Used in packet start message 2872*adfc5217SJeff Kirsher to TCM. */ 2873*adfc5217SJeff Kirsher #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc 2874*adfc5217SJeff Kirsher #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0 2875*adfc5217SJeff Kirsher #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4 2876*adfc5217SJeff Kirsher #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8 2877*adfc5217SJeff Kirsher #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec 2878*adfc5217SJeff Kirsher #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0 2879*adfc5217SJeff Kirsher /* [RW 32] The CM header for flush message where 'load existed' bit in CFC 2880*adfc5217SJeff Kirsher load response is set and packet type is 0. Used in packet start message 2881*adfc5217SJeff Kirsher to TCM. */ 2882*adfc5217SJeff Kirsher #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc 2883*adfc5217SJeff Kirsher #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0 2884*adfc5217SJeff Kirsher #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4 2885*adfc5217SJeff Kirsher #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8 2886*adfc5217SJeff Kirsher #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc 2887*adfc5217SJeff Kirsher #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0 2888*adfc5217SJeff Kirsher /* [RW 32] The CM header for a match and packet type 1 for loopback port. 2889*adfc5217SJeff Kirsher Used in packet start message to TCM. */ 2890*adfc5217SJeff Kirsher #define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c 2891*adfc5217SJeff Kirsher #define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0 2892*adfc5217SJeff Kirsher #define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4 2893*adfc5217SJeff Kirsher #define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8 2894*adfc5217SJeff Kirsher /* [RW 32] The CM header for a match and packet type 0. Used in packet start 2895*adfc5217SJeff Kirsher message to TCM. */ 2896*adfc5217SJeff Kirsher #define PRS_REG_CM_HDR_TYPE_0 0x40078 2897*adfc5217SJeff Kirsher #define PRS_REG_CM_HDR_TYPE_1 0x4007c 2898*adfc5217SJeff Kirsher #define PRS_REG_CM_HDR_TYPE_2 0x40080 2899*adfc5217SJeff Kirsher #define PRS_REG_CM_HDR_TYPE_3 0x40084 2900*adfc5217SJeff Kirsher #define PRS_REG_CM_HDR_TYPE_4 0x40088 2901*adfc5217SJeff Kirsher /* [RW 32] The CM header in case there was not a match on the connection */ 2902*adfc5217SJeff Kirsher #define PRS_REG_CM_NO_MATCH_HDR 0x400b8 2903*adfc5217SJeff Kirsher /* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */ 2904*adfc5217SJeff Kirsher #define PRS_REG_E1HOV_MODE 0x401c8 2905*adfc5217SJeff Kirsher /* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet 2906*adfc5217SJeff Kirsher start message to TCM. */ 2907*adfc5217SJeff Kirsher #define PRS_REG_EVENT_ID_1 0x40054 2908*adfc5217SJeff Kirsher #define PRS_REG_EVENT_ID_2 0x40058 2909*adfc5217SJeff Kirsher #define PRS_REG_EVENT_ID_3 0x4005c 2910*adfc5217SJeff Kirsher /* [RW 16] The Ethernet type value for FCoE */ 2911*adfc5217SJeff Kirsher #define PRS_REG_FCOE_TYPE 0x401d0 2912*adfc5217SJeff Kirsher /* [RW 8] Context region for flush packet with packet type 0. Used in CFC 2913*adfc5217SJeff Kirsher load request message. */ 2914*adfc5217SJeff Kirsher #define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004 2915*adfc5217SJeff Kirsher #define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008 2916*adfc5217SJeff Kirsher #define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c 2917*adfc5217SJeff Kirsher #define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010 2918*adfc5217SJeff Kirsher #define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014 2919*adfc5217SJeff Kirsher #define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018 2920*adfc5217SJeff Kirsher #define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c 2921*adfc5217SJeff Kirsher #define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020 2922*adfc5217SJeff Kirsher /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2923*adfc5217SJeff Kirsher * Ethernet header. */ 2924*adfc5217SJeff Kirsher #define PRS_REG_HDRS_AFTER_BASIC 0x40238 2925*adfc5217SJeff Kirsher /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2926*adfc5217SJeff Kirsher * Ethernet header for port 0 packets. */ 2927*adfc5217SJeff Kirsher #define PRS_REG_HDRS_AFTER_BASIC_PORT_0 0x40270 2928*adfc5217SJeff Kirsher #define PRS_REG_HDRS_AFTER_BASIC_PORT_1 0x40290 2929*adfc5217SJeff Kirsher /* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */ 2930*adfc5217SJeff Kirsher #define PRS_REG_HDRS_AFTER_TAG_0 0x40248 2931*adfc5217SJeff Kirsher /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for 2932*adfc5217SJeff Kirsher * port 0 packets */ 2933*adfc5217SJeff Kirsher #define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 0x40280 2934*adfc5217SJeff Kirsher #define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 0x402a0 2935*adfc5217SJeff Kirsher /* [RW 4] The increment value to send in the CFC load request message */ 2936*adfc5217SJeff Kirsher #define PRS_REG_INC_VALUE 0x40048 2937*adfc5217SJeff Kirsher /* [RW 6] Bit-map indicating which headers must appear in the packet */ 2938*adfc5217SJeff Kirsher #define PRS_REG_MUST_HAVE_HDRS 0x40254 2939*adfc5217SJeff Kirsher /* [RW 6] Bit-map indicating which headers must appear in the packet for 2940*adfc5217SJeff Kirsher * port 0 packets */ 2941*adfc5217SJeff Kirsher #define PRS_REG_MUST_HAVE_HDRS_PORT_0 0x4028c 2942*adfc5217SJeff Kirsher #define PRS_REG_MUST_HAVE_HDRS_PORT_1 0x402ac 2943*adfc5217SJeff Kirsher #define PRS_REG_NIC_MODE 0x40138 2944*adfc5217SJeff Kirsher /* [RW 8] The 8-bit event ID for cases where there is no match on the 2945*adfc5217SJeff Kirsher connection. Used in packet start message to TCM. */ 2946*adfc5217SJeff Kirsher #define PRS_REG_NO_MATCH_EVENT_ID 0x40070 2947*adfc5217SJeff Kirsher /* [ST 24] The number of input CFC flush packets */ 2948*adfc5217SJeff Kirsher #define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128 2949*adfc5217SJeff Kirsher /* [ST 32] The number of cycles the Parser halted its operation since it 2950*adfc5217SJeff Kirsher could not allocate the next serial number */ 2951*adfc5217SJeff Kirsher #define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130 2952*adfc5217SJeff Kirsher /* [ST 24] The number of input packets */ 2953*adfc5217SJeff Kirsher #define PRS_REG_NUM_OF_PACKETS 0x40124 2954*adfc5217SJeff Kirsher /* [ST 24] The number of input transparent flush packets */ 2955*adfc5217SJeff Kirsher #define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c 2956*adfc5217SJeff Kirsher /* [RW 8] Context region for received Ethernet packet with a match and 2957*adfc5217SJeff Kirsher packet type 0. Used in CFC load request message */ 2958*adfc5217SJeff Kirsher #define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028 2959*adfc5217SJeff Kirsher #define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c 2960*adfc5217SJeff Kirsher #define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030 2961*adfc5217SJeff Kirsher #define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034 2962*adfc5217SJeff Kirsher #define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038 2963*adfc5217SJeff Kirsher #define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c 2964*adfc5217SJeff Kirsher #define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040 2965*adfc5217SJeff Kirsher #define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044 2966*adfc5217SJeff Kirsher /* [R 2] debug only: Number of pending requests for CAC on port 0. */ 2967*adfc5217SJeff Kirsher #define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174 2968*adfc5217SJeff Kirsher /* [R 2] debug only: Number of pending requests for header parsing. */ 2969*adfc5217SJeff Kirsher #define PRS_REG_PENDING_BRB_PRS_RQ 0x40170 2970*adfc5217SJeff Kirsher /* [R 1] Interrupt register #0 read */ 2971*adfc5217SJeff Kirsher #define PRS_REG_PRS_INT_STS 0x40188 2972*adfc5217SJeff Kirsher /* [RW 8] Parity mask register #0 read/write */ 2973*adfc5217SJeff Kirsher #define PRS_REG_PRS_PRTY_MASK 0x401a4 2974*adfc5217SJeff Kirsher /* [R 8] Parity register #0 read */ 2975*adfc5217SJeff Kirsher #define PRS_REG_PRS_PRTY_STS 0x40198 2976*adfc5217SJeff Kirsher /* [RC 8] Parity register #0 read clear */ 2977*adfc5217SJeff Kirsher #define PRS_REG_PRS_PRTY_STS_CLR 0x4019c 2978*adfc5217SJeff Kirsher /* [RW 8] Context region for pure acknowledge packets. Used in CFC load 2979*adfc5217SJeff Kirsher request message */ 2980*adfc5217SJeff Kirsher #define PRS_REG_PURE_REGIONS 0x40024 2981*adfc5217SJeff Kirsher /* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this 2982*adfc5217SJeff Kirsher serail number was released by SDM but cannot be used because a previous 2983*adfc5217SJeff Kirsher serial number was not released. */ 2984*adfc5217SJeff Kirsher #define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154 2985*adfc5217SJeff Kirsher /* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this 2986*adfc5217SJeff Kirsher serail number was released by SDM but cannot be used because a previous 2987*adfc5217SJeff Kirsher serial number was not released. */ 2988*adfc5217SJeff Kirsher #define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158 2989*adfc5217SJeff Kirsher /* [R 4] debug only: SRC current credit. Transaction based. */ 2990*adfc5217SJeff Kirsher #define PRS_REG_SRC_CURRENT_CREDIT 0x4016c 2991*adfc5217SJeff Kirsher /* [RW 16] The Ethernet type value for L2 tag 0 */ 2992*adfc5217SJeff Kirsher #define PRS_REG_TAG_ETHERTYPE_0 0x401d4 2993*adfc5217SJeff Kirsher /* [RW 4] The length of the info field for L2 tag 0. The length is between 2994*adfc5217SJeff Kirsher * 2B and 14B; in 2B granularity */ 2995*adfc5217SJeff Kirsher #define PRS_REG_TAG_LEN_0 0x4022c 2996*adfc5217SJeff Kirsher /* [R 8] debug only: TCM current credit. Cycle based. */ 2997*adfc5217SJeff Kirsher #define PRS_REG_TCM_CURRENT_CREDIT 0x40160 2998*adfc5217SJeff Kirsher /* [R 8] debug only: TSDM current credit. Transaction based. */ 2999*adfc5217SJeff Kirsher #define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c 3000*adfc5217SJeff Kirsher #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1<<19) 3001*adfc5217SJeff Kirsher #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1<<20) 3002*adfc5217SJeff Kirsher #define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1<<22) 3003*adfc5217SJeff Kirsher #define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED (0x1<<23) 3004*adfc5217SJeff Kirsher #define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED (0x1<<24) 3005*adfc5217SJeff Kirsher #define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7) 3006*adfc5217SJeff Kirsher #define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7) 3007*adfc5217SJeff Kirsher /* [R 6] Debug only: Number of used entries in the data FIFO */ 3008*adfc5217SJeff Kirsher #define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c 3009*adfc5217SJeff Kirsher /* [R 7] Debug only: Number of used entries in the header FIFO */ 3010*adfc5217SJeff Kirsher #define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478 3011*adfc5217SJeff Kirsher #define PXP2_REG_PGL_ADDR_88_F0 0x120534 3012*adfc5217SJeff Kirsher #define PXP2_REG_PGL_ADDR_8C_F0 0x120538 3013*adfc5217SJeff Kirsher #define PXP2_REG_PGL_ADDR_90_F0 0x12053c 3014*adfc5217SJeff Kirsher #define PXP2_REG_PGL_ADDR_94_F0 0x120540 3015*adfc5217SJeff Kirsher #define PXP2_REG_PGL_CONTROL0 0x120490 3016*adfc5217SJeff Kirsher #define PXP2_REG_PGL_CONTROL1 0x120514 3017*adfc5217SJeff Kirsher #define PXP2_REG_PGL_DEBUG 0x120520 3018*adfc5217SJeff Kirsher /* [RW 32] third dword data of expansion rom request. this register is 3019*adfc5217SJeff Kirsher special. reading from it provides a vector outstanding read requests. if 3020*adfc5217SJeff Kirsher a bit is zero it means that a read request on the corresponding tag did 3021*adfc5217SJeff Kirsher not finish yet (not all completions have arrived for it) */ 3022*adfc5217SJeff Kirsher #define PXP2_REG_PGL_EXP_ROM2 0x120808 3023*adfc5217SJeff Kirsher /* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask; 3024*adfc5217SJeff Kirsher its[15:0]-address */ 3025*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_CSDM_0 0x1204f4 3026*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_CSDM_1 0x1204f8 3027*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_CSDM_2 0x1204fc 3028*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_CSDM_3 0x120500 3029*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_CSDM_4 0x120504 3030*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_CSDM_5 0x120508 3031*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_CSDM_6 0x12050c 3032*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_CSDM_7 0x120510 3033*adfc5217SJeff Kirsher /* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask; 3034*adfc5217SJeff Kirsher its[15:0]-address */ 3035*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_TSDM_0 0x120494 3036*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_TSDM_1 0x120498 3037*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_TSDM_2 0x12049c 3038*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_TSDM_3 0x1204a0 3039*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_TSDM_4 0x1204a4 3040*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_TSDM_5 0x1204a8 3041*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_TSDM_6 0x1204ac 3042*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_TSDM_7 0x1204b0 3043*adfc5217SJeff Kirsher /* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask; 3044*adfc5217SJeff Kirsher its[15:0]-address */ 3045*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_USDM_0 0x1204b4 3046*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_USDM_1 0x1204b8 3047*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_USDM_2 0x1204bc 3048*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_USDM_3 0x1204c0 3049*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_USDM_4 0x1204c4 3050*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_USDM_5 0x1204c8 3051*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_USDM_6 0x1204cc 3052*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_USDM_7 0x1204d0 3053*adfc5217SJeff Kirsher /* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask; 3054*adfc5217SJeff Kirsher its[15:0]-address */ 3055*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_XSDM_0 0x1204d4 3056*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_XSDM_1 0x1204d8 3057*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_XSDM_2 0x1204dc 3058*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_XSDM_3 0x1204e0 3059*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_XSDM_4 0x1204e4 3060*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_XSDM_5 0x1204e8 3061*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_XSDM_6 0x1204ec 3062*adfc5217SJeff Kirsher #define PXP2_REG_PGL_INT_XSDM_7 0x1204f0 3063*adfc5217SJeff Kirsher /* [RW 3] this field allows one function to pretend being another function 3064*adfc5217SJeff Kirsher when accessing any BAR mapped resource within the device. the value of 3065*adfc5217SJeff Kirsher the field is the number of the function that will be accessed 3066*adfc5217SJeff Kirsher effectively. after software write to this bit it must read it in order to 3067*adfc5217SJeff Kirsher know that the new value is updated */ 3068*adfc5217SJeff Kirsher #define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674 3069*adfc5217SJeff Kirsher #define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678 3070*adfc5217SJeff Kirsher #define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067c 3071*adfc5217SJeff Kirsher #define PXP2_REG_PGL_PRETEND_FUNC_F3 0x120680 3072*adfc5217SJeff Kirsher #define PXP2_REG_PGL_PRETEND_FUNC_F4 0x120684 3073*adfc5217SJeff Kirsher #define PXP2_REG_PGL_PRETEND_FUNC_F5 0x120688 3074*adfc5217SJeff Kirsher #define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068c 3075*adfc5217SJeff Kirsher #define PXP2_REG_PGL_PRETEND_FUNC_F7 0x120690 3076*adfc5217SJeff Kirsher /* [R 1] this bit indicates that a read request was blocked because of 3077*adfc5217SJeff Kirsher bus_master_en was deasserted */ 3078*adfc5217SJeff Kirsher #define PXP2_REG_PGL_READ_BLOCKED 0x120568 3079*adfc5217SJeff Kirsher #define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8 3080*adfc5217SJeff Kirsher /* [R 18] debug only */ 3081*adfc5217SJeff Kirsher #define PXP2_REG_PGL_TXW_CDTS 0x12052c 3082*adfc5217SJeff Kirsher /* [R 1] this bit indicates that a write request was blocked because of 3083*adfc5217SJeff Kirsher bus_master_en was deasserted */ 3084*adfc5217SJeff Kirsher #define PXP2_REG_PGL_WRITE_BLOCKED 0x120564 3085*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0 3086*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4 3087*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8 3088*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4 3089*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_ADD28 0x120228 3090*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8 3091*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4 3092*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8 3093*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc 3094*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0 3095*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c 3096*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_L1 0x1202b0 3097*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_L10 0x1202d4 3098*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_L11 0x1202d8 3099*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_L2 0x1202b4 3100*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_L28 0x120318 3101*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_L3 0x1202b8 3102*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_L6 0x1202c4 3103*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_L7 0x1202c8 3104*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_L8 0x1202cc 3105*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_L9 0x1202d0 3106*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_RD 0x120324 3107*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_UB1 0x120238 3108*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_UB10 0x12025c 3109*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_UB11 0x120260 3110*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_UB2 0x12023c 3111*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0 3112*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_UB3 0x120240 3113*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_UB6 0x12024c 3114*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_UB7 0x120250 3115*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_UB8 0x120254 3116*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_UB9 0x120258 3117*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_BW_WR 0x120328 3118*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_CDU0_L2P 0x120000 3119*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_QM0_L2P 0x120038 3120*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_SRC0_L2P 0x120054 3121*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_TM0_L2P 0x12001c 3122*adfc5217SJeff Kirsher #define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0 3123*adfc5217SJeff Kirsher /* [RW 32] Interrupt mask register #0 read/write */ 3124*adfc5217SJeff Kirsher #define PXP2_REG_PXP2_INT_MASK_0 0x120578 3125*adfc5217SJeff Kirsher /* [R 32] Interrupt register #0 read */ 3126*adfc5217SJeff Kirsher #define PXP2_REG_PXP2_INT_STS_0 0x12056c 3127*adfc5217SJeff Kirsher #define PXP2_REG_PXP2_INT_STS_1 0x120608 3128*adfc5217SJeff Kirsher /* [RC 32] Interrupt register #0 read clear */ 3129*adfc5217SJeff Kirsher #define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570 3130*adfc5217SJeff Kirsher /* [RW 32] Parity mask register #0 read/write */ 3131*adfc5217SJeff Kirsher #define PXP2_REG_PXP2_PRTY_MASK_0 0x120588 3132*adfc5217SJeff Kirsher #define PXP2_REG_PXP2_PRTY_MASK_1 0x120598 3133*adfc5217SJeff Kirsher /* [R 32] Parity register #0 read */ 3134*adfc5217SJeff Kirsher #define PXP2_REG_PXP2_PRTY_STS_0 0x12057c 3135*adfc5217SJeff Kirsher #define PXP2_REG_PXP2_PRTY_STS_1 0x12058c 3136*adfc5217SJeff Kirsher /* [RC 32] Parity register #0 read clear */ 3137*adfc5217SJeff Kirsher #define PXP2_REG_PXP2_PRTY_STS_CLR_0 0x120580 3138*adfc5217SJeff Kirsher #define PXP2_REG_PXP2_PRTY_STS_CLR_1 0x120590 3139*adfc5217SJeff Kirsher /* [R 1] Debug only: The 'almost full' indication from each fifo (gives 3140*adfc5217SJeff Kirsher indication about backpressure) */ 3141*adfc5217SJeff Kirsher #define PXP2_REG_RD_ALMOST_FULL_0 0x120424 3142*adfc5217SJeff Kirsher /* [R 8] Debug only: The blocks counter - number of unused block ids */ 3143*adfc5217SJeff Kirsher #define PXP2_REG_RD_BLK_CNT 0x120418 3144*adfc5217SJeff Kirsher /* [RW 8] Debug only: Total number of available blocks in Tetris Buffer. 3145*adfc5217SJeff Kirsher Must be bigger than 6. Normally should not be changed. */ 3146*adfc5217SJeff Kirsher #define PXP2_REG_RD_BLK_NUM_CFG 0x12040c 3147*adfc5217SJeff Kirsher /* [RW 2] CDU byte swapping mode configuration for master read requests */ 3148*adfc5217SJeff Kirsher #define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404 3149*adfc5217SJeff Kirsher /* [RW 1] When '1'; inputs to the PSWRD block are ignored */ 3150*adfc5217SJeff Kirsher #define PXP2_REG_RD_DISABLE_INPUTS 0x120374 3151*adfc5217SJeff Kirsher /* [R 1] PSWRD internal memories initialization is done */ 3152*adfc5217SJeff Kirsher #define PXP2_REG_RD_INIT_DONE 0x120370 3153*adfc5217SJeff Kirsher /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3154*adfc5217SJeff Kirsher allocated for vq10 */ 3155*adfc5217SJeff Kirsher #define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0 3156*adfc5217SJeff Kirsher /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3157*adfc5217SJeff Kirsher allocated for vq11 */ 3158*adfc5217SJeff Kirsher #define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4 3159*adfc5217SJeff Kirsher /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3160*adfc5217SJeff Kirsher allocated for vq17 */ 3161*adfc5217SJeff Kirsher #define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc 3162*adfc5217SJeff Kirsher /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3163*adfc5217SJeff Kirsher allocated for vq18 */ 3164*adfc5217SJeff Kirsher #define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0 3165*adfc5217SJeff Kirsher /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3166*adfc5217SJeff Kirsher allocated for vq19 */ 3167*adfc5217SJeff Kirsher #define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4 3168*adfc5217SJeff Kirsher /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3169*adfc5217SJeff Kirsher allocated for vq22 */ 3170*adfc5217SJeff Kirsher #define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0 3171*adfc5217SJeff Kirsher /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3172*adfc5217SJeff Kirsher allocated for vq25 */ 3173*adfc5217SJeff Kirsher #define PXP2_REG_RD_MAX_BLKS_VQ25 0x1203dc 3174*adfc5217SJeff Kirsher /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3175*adfc5217SJeff Kirsher allocated for vq6 */ 3176*adfc5217SJeff Kirsher #define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390 3177*adfc5217SJeff Kirsher /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3178*adfc5217SJeff Kirsher allocated for vq9 */ 3179*adfc5217SJeff Kirsher #define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c 3180*adfc5217SJeff Kirsher /* [RW 2] PBF byte swapping mode configuration for master read requests */ 3181*adfc5217SJeff Kirsher #define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4 3182*adfc5217SJeff Kirsher /* [R 1] Debug only: Indication if delivery ports are idle */ 3183*adfc5217SJeff Kirsher #define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c 3184*adfc5217SJeff Kirsher #define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420 3185*adfc5217SJeff Kirsher /* [RW 2] QM byte swapping mode configuration for master read requests */ 3186*adfc5217SJeff Kirsher #define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8 3187*adfc5217SJeff Kirsher /* [R 7] Debug only: The SR counter - number of unused sub request ids */ 3188*adfc5217SJeff Kirsher #define PXP2_REG_RD_SR_CNT 0x120414 3189*adfc5217SJeff Kirsher /* [RW 2] SRC byte swapping mode configuration for master read requests */ 3190*adfc5217SJeff Kirsher #define PXP2_REG_RD_SRC_SWAP_MODE 0x120400 3191*adfc5217SJeff Kirsher /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must 3192*adfc5217SJeff Kirsher be bigger than 1. Normally should not be changed. */ 3193*adfc5217SJeff Kirsher #define PXP2_REG_RD_SR_NUM_CFG 0x120408 3194*adfc5217SJeff Kirsher /* [RW 1] Signals the PSWRD block to start initializing internal memories */ 3195*adfc5217SJeff Kirsher #define PXP2_REG_RD_START_INIT 0x12036c 3196*adfc5217SJeff Kirsher /* [RW 2] TM byte swapping mode configuration for master read requests */ 3197*adfc5217SJeff Kirsher #define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc 3198*adfc5217SJeff Kirsher /* [RW 10] Bandwidth addition to VQ0 write requests */ 3199*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc 3200*adfc5217SJeff Kirsher /* [RW 10] Bandwidth addition to VQ12 read requests */ 3201*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec 3202*adfc5217SJeff Kirsher /* [RW 10] Bandwidth addition to VQ13 read requests */ 3203*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0 3204*adfc5217SJeff Kirsher /* [RW 10] Bandwidth addition to VQ14 read requests */ 3205*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4 3206*adfc5217SJeff Kirsher /* [RW 10] Bandwidth addition to VQ15 read requests */ 3207*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8 3208*adfc5217SJeff Kirsher /* [RW 10] Bandwidth addition to VQ16 read requests */ 3209*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc 3210*adfc5217SJeff Kirsher /* [RW 10] Bandwidth addition to VQ17 read requests */ 3211*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_ADD17 0x120200 3212*adfc5217SJeff Kirsher /* [RW 10] Bandwidth addition to VQ18 read requests */ 3213*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_ADD18 0x120204 3214*adfc5217SJeff Kirsher /* [RW 10] Bandwidth addition to VQ19 read requests */ 3215*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_ADD19 0x120208 3216*adfc5217SJeff Kirsher /* [RW 10] Bandwidth addition to VQ20 read requests */ 3217*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_ADD20 0x12020c 3218*adfc5217SJeff Kirsher /* [RW 10] Bandwidth addition to VQ22 read requests */ 3219*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_ADD22 0x120210 3220*adfc5217SJeff Kirsher /* [RW 10] Bandwidth addition to VQ23 read requests */ 3221*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_ADD23 0x120214 3222*adfc5217SJeff Kirsher /* [RW 10] Bandwidth addition to VQ24 read requests */ 3223*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_ADD24 0x120218 3224*adfc5217SJeff Kirsher /* [RW 10] Bandwidth addition to VQ25 read requests */ 3225*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_ADD25 0x12021c 3226*adfc5217SJeff Kirsher /* [RW 10] Bandwidth addition to VQ26 read requests */ 3227*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_ADD26 0x120220 3228*adfc5217SJeff Kirsher /* [RW 10] Bandwidth addition to VQ27 read requests */ 3229*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_ADD27 0x120224 3230*adfc5217SJeff Kirsher /* [RW 10] Bandwidth addition to VQ4 read requests */ 3231*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc 3232*adfc5217SJeff Kirsher /* [RW 10] Bandwidth addition to VQ5 read requests */ 3233*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0 3234*adfc5217SJeff Kirsher /* [RW 10] Bandwidth Typical L for VQ0 Read requests */ 3235*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_L0 0x1202ac 3236*adfc5217SJeff Kirsher /* [RW 10] Bandwidth Typical L for VQ12 Read requests */ 3237*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_L12 0x1202dc 3238*adfc5217SJeff Kirsher /* [RW 10] Bandwidth Typical L for VQ13 Read requests */ 3239*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_L13 0x1202e0 3240*adfc5217SJeff Kirsher /* [RW 10] Bandwidth Typical L for VQ14 Read requests */ 3241*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_L14 0x1202e4 3242*adfc5217SJeff Kirsher /* [RW 10] Bandwidth Typical L for VQ15 Read requests */ 3243*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_L15 0x1202e8 3244*adfc5217SJeff Kirsher /* [RW 10] Bandwidth Typical L for VQ16 Read requests */ 3245*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_L16 0x1202ec 3246*adfc5217SJeff Kirsher /* [RW 10] Bandwidth Typical L for VQ17 Read requests */ 3247*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_L17 0x1202f0 3248*adfc5217SJeff Kirsher /* [RW 10] Bandwidth Typical L for VQ18 Read requests */ 3249*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_L18 0x1202f4 3250*adfc5217SJeff Kirsher /* [RW 10] Bandwidth Typical L for VQ19 Read requests */ 3251*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_L19 0x1202f8 3252*adfc5217SJeff Kirsher /* [RW 10] Bandwidth Typical L for VQ20 Read requests */ 3253*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_L20 0x1202fc 3254*adfc5217SJeff Kirsher /* [RW 10] Bandwidth Typical L for VQ22 Read requests */ 3255*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_L22 0x120300 3256*adfc5217SJeff Kirsher /* [RW 10] Bandwidth Typical L for VQ23 Read requests */ 3257*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_L23 0x120304 3258*adfc5217SJeff Kirsher /* [RW 10] Bandwidth Typical L for VQ24 Read requests */ 3259*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_L24 0x120308 3260*adfc5217SJeff Kirsher /* [RW 10] Bandwidth Typical L for VQ25 Read requests */ 3261*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_L25 0x12030c 3262*adfc5217SJeff Kirsher /* [RW 10] Bandwidth Typical L for VQ26 Read requests */ 3263*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_L26 0x120310 3264*adfc5217SJeff Kirsher /* [RW 10] Bandwidth Typical L for VQ27 Read requests */ 3265*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_L27 0x120314 3266*adfc5217SJeff Kirsher /* [RW 10] Bandwidth Typical L for VQ4 Read requests */ 3267*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_L4 0x1202bc 3268*adfc5217SJeff Kirsher /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */ 3269*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_L5 0x1202c0 3270*adfc5217SJeff Kirsher /* [RW 7] Bandwidth upper bound for VQ0 read requests */ 3271*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234 3272*adfc5217SJeff Kirsher /* [RW 7] Bandwidth upper bound for VQ12 read requests */ 3273*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264 3274*adfc5217SJeff Kirsher /* [RW 7] Bandwidth upper bound for VQ13 read requests */ 3275*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268 3276*adfc5217SJeff Kirsher /* [RW 7] Bandwidth upper bound for VQ14 read requests */ 3277*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c 3278*adfc5217SJeff Kirsher /* [RW 7] Bandwidth upper bound for VQ15 read requests */ 3279*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270 3280*adfc5217SJeff Kirsher /* [RW 7] Bandwidth upper bound for VQ16 read requests */ 3281*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274 3282*adfc5217SJeff Kirsher /* [RW 7] Bandwidth upper bound for VQ17 read requests */ 3283*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278 3284*adfc5217SJeff Kirsher /* [RW 7] Bandwidth upper bound for VQ18 read requests */ 3285*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c 3286*adfc5217SJeff Kirsher /* [RW 7] Bandwidth upper bound for VQ19 read requests */ 3287*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280 3288*adfc5217SJeff Kirsher /* [RW 7] Bandwidth upper bound for VQ20 read requests */ 3289*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284 3290*adfc5217SJeff Kirsher /* [RW 7] Bandwidth upper bound for VQ22 read requests */ 3291*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288 3292*adfc5217SJeff Kirsher /* [RW 7] Bandwidth upper bound for VQ23 read requests */ 3293*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c 3294*adfc5217SJeff Kirsher /* [RW 7] Bandwidth upper bound for VQ24 read requests */ 3295*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290 3296*adfc5217SJeff Kirsher /* [RW 7] Bandwidth upper bound for VQ25 read requests */ 3297*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294 3298*adfc5217SJeff Kirsher /* [RW 7] Bandwidth upper bound for VQ26 read requests */ 3299*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298 3300*adfc5217SJeff Kirsher /* [RW 7] Bandwidth upper bound for VQ27 read requests */ 3301*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c 3302*adfc5217SJeff Kirsher /* [RW 7] Bandwidth upper bound for VQ4 read requests */ 3303*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244 3304*adfc5217SJeff Kirsher /* [RW 7] Bandwidth upper bound for VQ5 read requests */ 3305*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248 3306*adfc5217SJeff Kirsher /* [RW 10] Bandwidth addition to VQ29 write requests */ 3307*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_WR_ADD29 0x12022c 3308*adfc5217SJeff Kirsher /* [RW 10] Bandwidth addition to VQ30 write requests */ 3309*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_WR_ADD30 0x120230 3310*adfc5217SJeff Kirsher /* [RW 10] Bandwidth Typical L for VQ29 Write requests */ 3311*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_WR_L29 0x12031c 3312*adfc5217SJeff Kirsher /* [RW 10] Bandwidth Typical L for VQ30 Write requests */ 3313*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_WR_L30 0x120320 3314*adfc5217SJeff Kirsher /* [RW 7] Bandwidth upper bound for VQ29 */ 3315*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4 3316*adfc5217SJeff Kirsher /* [RW 7] Bandwidth upper bound for VQ30 */ 3317*adfc5217SJeff Kirsher #define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8 3318*adfc5217SJeff Kirsher /* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */ 3319*adfc5217SJeff Kirsher #define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008 3320*adfc5217SJeff Kirsher /* [RW 2] Endian mode for cdu */ 3321*adfc5217SJeff Kirsher #define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0 3322*adfc5217SJeff Kirsher #define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c 3323*adfc5217SJeff Kirsher #define PXP2_REG_RQ_CDU_LAST_ILT 0x120620 3324*adfc5217SJeff Kirsher /* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k; 3325*adfc5217SJeff Kirsher -128k */ 3326*adfc5217SJeff Kirsher #define PXP2_REG_RQ_CDU_P_SIZE 0x120018 3327*adfc5217SJeff Kirsher /* [R 1] 1' indicates that the requester has finished its internal 3328*adfc5217SJeff Kirsher configuration */ 3329*adfc5217SJeff Kirsher #define PXP2_REG_RQ_CFG_DONE 0x1201b4 3330*adfc5217SJeff Kirsher /* [RW 2] Endian mode for debug */ 3331*adfc5217SJeff Kirsher #define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4 3332*adfc5217SJeff Kirsher /* [RW 1] When '1'; requests will enter input buffers but wont get out 3333*adfc5217SJeff Kirsher towards the glue */ 3334*adfc5217SJeff Kirsher #define PXP2_REG_RQ_DISABLE_INPUTS 0x120330 3335*adfc5217SJeff Kirsher /* [RW 4] Determines alignment of write SRs when a request is split into 3336*adfc5217SJeff Kirsher * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B 3337*adfc5217SJeff Kirsher * aligned. 4 - 512B aligned. */ 3338*adfc5217SJeff Kirsher #define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0 3339*adfc5217SJeff Kirsher /* [RW 4] Determines alignment of read SRs when a request is split into 3340*adfc5217SJeff Kirsher * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B 3341*adfc5217SJeff Kirsher * aligned. 4 - 512B aligned. */ 3342*adfc5217SJeff Kirsher #define PXP2_REG_RQ_DRAM_ALIGN_RD 0x12092c 3343*adfc5217SJeff Kirsher /* [RW 1] when set the new alignment method (E2) will be applied; when reset 3344*adfc5217SJeff Kirsher * the original alignment method (E1 E1H) will be applied */ 3345*adfc5217SJeff Kirsher #define PXP2_REG_RQ_DRAM_ALIGN_SEL 0x120930 3346*adfc5217SJeff Kirsher /* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will 3347*adfc5217SJeff Kirsher be asserted */ 3348*adfc5217SJeff Kirsher #define PXP2_REG_RQ_ELT_DISABLE 0x12066c 3349*adfc5217SJeff Kirsher /* [RW 2] Endian mode for hc */ 3350*adfc5217SJeff Kirsher #define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8 3351*adfc5217SJeff Kirsher /* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back 3352*adfc5217SJeff Kirsher compatibility needs; Note that different registers are used per mode */ 3353*adfc5217SJeff Kirsher #define PXP2_REG_RQ_ILT_MODE 0x1205b4 3354*adfc5217SJeff Kirsher /* [WB 53] Onchip address table */ 3355*adfc5217SJeff Kirsher #define PXP2_REG_RQ_ONCHIP_AT 0x122000 3356*adfc5217SJeff Kirsher /* [WB 53] Onchip address table - B0 */ 3357*adfc5217SJeff Kirsher #define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000 3358*adfc5217SJeff Kirsher /* [RW 13] Pending read limiter threshold; in Dwords */ 3359*adfc5217SJeff Kirsher #define PXP2_REG_RQ_PDR_LIMIT 0x12033c 3360*adfc5217SJeff Kirsher /* [RW 2] Endian mode for qm */ 3361*adfc5217SJeff Kirsher #define PXP2_REG_RQ_QM_ENDIAN_M 0x120194 3362*adfc5217SJeff Kirsher #define PXP2_REG_RQ_QM_FIRST_ILT 0x120634 3363*adfc5217SJeff Kirsher #define PXP2_REG_RQ_QM_LAST_ILT 0x120638 3364*adfc5217SJeff Kirsher /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k; 3365*adfc5217SJeff Kirsher -128k */ 3366*adfc5217SJeff Kirsher #define PXP2_REG_RQ_QM_P_SIZE 0x120050 3367*adfc5217SJeff Kirsher /* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */ 3368*adfc5217SJeff Kirsher #define PXP2_REG_RQ_RBC_DONE 0x1201b0 3369*adfc5217SJeff Kirsher /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B; 3370*adfc5217SJeff Kirsher 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */ 3371*adfc5217SJeff Kirsher #define PXP2_REG_RQ_RD_MBS0 0x120160 3372*adfc5217SJeff Kirsher /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B; 3373*adfc5217SJeff Kirsher 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */ 3374*adfc5217SJeff Kirsher #define PXP2_REG_RQ_RD_MBS1 0x120168 3375*adfc5217SJeff Kirsher /* [RW 2] Endian mode for src */ 3376*adfc5217SJeff Kirsher #define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c 3377*adfc5217SJeff Kirsher #define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c 3378*adfc5217SJeff Kirsher #define PXP2_REG_RQ_SRC_LAST_ILT 0x120640 3379*adfc5217SJeff Kirsher /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k; 3380*adfc5217SJeff Kirsher -128k */ 3381*adfc5217SJeff Kirsher #define PXP2_REG_RQ_SRC_P_SIZE 0x12006c 3382*adfc5217SJeff Kirsher /* [RW 2] Endian mode for tm */ 3383*adfc5217SJeff Kirsher #define PXP2_REG_RQ_TM_ENDIAN_M 0x120198 3384*adfc5217SJeff Kirsher #define PXP2_REG_RQ_TM_FIRST_ILT 0x120644 3385*adfc5217SJeff Kirsher #define PXP2_REG_RQ_TM_LAST_ILT 0x120648 3386*adfc5217SJeff Kirsher /* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k; 3387*adfc5217SJeff Kirsher -128k */ 3388*adfc5217SJeff Kirsher #define PXP2_REG_RQ_TM_P_SIZE 0x120034 3389*adfc5217SJeff Kirsher /* [R 5] Number of entries in the ufifo; his fifo has l2p completions */ 3390*adfc5217SJeff Kirsher #define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c 3391*adfc5217SJeff Kirsher /* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */ 3392*adfc5217SJeff Kirsher #define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094 3393*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 0 in pswrq memory */ 3394*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810 3395*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 10 in pswrq memory */ 3396*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818 3397*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 11 in pswrq memory */ 3398*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820 3399*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 12 in pswrq memory */ 3400*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828 3401*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 13 in pswrq memory */ 3402*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830 3403*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 14 in pswrq memory */ 3404*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838 3405*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 15 in pswrq memory */ 3406*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840 3407*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 16 in pswrq memory */ 3408*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848 3409*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 17 in pswrq memory */ 3410*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850 3411*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 18 in pswrq memory */ 3412*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858 3413*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 19 in pswrq memory */ 3414*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860 3415*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 1 in pswrq memory */ 3416*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868 3417*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 20 in pswrq memory */ 3418*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870 3419*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 21 in pswrq memory */ 3420*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878 3421*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 22 in pswrq memory */ 3422*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880 3423*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 23 in pswrq memory */ 3424*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888 3425*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 24 in pswrq memory */ 3426*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890 3427*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 25 in pswrq memory */ 3428*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898 3429*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 26 in pswrq memory */ 3430*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0 3431*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 27 in pswrq memory */ 3432*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8 3433*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 28 in pswrq memory */ 3434*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0 3435*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 29 in pswrq memory */ 3436*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8 3437*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 2 in pswrq memory */ 3438*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0 3439*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 30 in pswrq memory */ 3440*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8 3441*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 31 in pswrq memory */ 3442*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0 3443*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 3 in pswrq memory */ 3444*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8 3445*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 4 in pswrq memory */ 3446*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0 3447*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 5 in pswrq memory */ 3448*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8 3449*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 6 in pswrq memory */ 3450*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0 3451*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 7 in pswrq memory */ 3452*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8 3453*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 8 in pswrq memory */ 3454*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900 3455*adfc5217SJeff Kirsher /* [R 8] Number of entries occupied by vq 9 in pswrq memory */ 3456*adfc5217SJeff Kirsher #define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908 3457*adfc5217SJeff Kirsher /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B; 3458*adfc5217SJeff Kirsher 001:256B; 010: 512B; */ 3459*adfc5217SJeff Kirsher #define PXP2_REG_RQ_WR_MBS0 0x12015c 3460*adfc5217SJeff Kirsher /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B; 3461*adfc5217SJeff Kirsher 001:256B; 010: 512B; */ 3462*adfc5217SJeff Kirsher #define PXP2_REG_RQ_WR_MBS1 0x120164 3463*adfc5217SJeff Kirsher /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3464*adfc5217SJeff Kirsher buffer reaches this number has_payload will be asserted */ 3465*adfc5217SJeff Kirsher #define PXP2_REG_WR_CDU_MPS 0x1205f0 3466*adfc5217SJeff Kirsher /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3467*adfc5217SJeff Kirsher buffer reaches this number has_payload will be asserted */ 3468*adfc5217SJeff Kirsher #define PXP2_REG_WR_CSDM_MPS 0x1205d0 3469*adfc5217SJeff Kirsher /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3470*adfc5217SJeff Kirsher buffer reaches this number has_payload will be asserted */ 3471*adfc5217SJeff Kirsher #define PXP2_REG_WR_DBG_MPS 0x1205e8 3472*adfc5217SJeff Kirsher /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3473*adfc5217SJeff Kirsher buffer reaches this number has_payload will be asserted */ 3474*adfc5217SJeff Kirsher #define PXP2_REG_WR_DMAE_MPS 0x1205ec 3475*adfc5217SJeff Kirsher /* [RW 10] if Number of entries in dmae fifo will be higher than this 3476*adfc5217SJeff Kirsher threshold then has_payload indication will be asserted; the default value 3477*adfc5217SJeff Kirsher should be equal to > write MBS size! */ 3478*adfc5217SJeff Kirsher #define PXP2_REG_WR_DMAE_TH 0x120368 3479*adfc5217SJeff Kirsher /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3480*adfc5217SJeff Kirsher buffer reaches this number has_payload will be asserted */ 3481*adfc5217SJeff Kirsher #define PXP2_REG_WR_HC_MPS 0x1205c8 3482*adfc5217SJeff Kirsher /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3483*adfc5217SJeff Kirsher buffer reaches this number has_payload will be asserted */ 3484*adfc5217SJeff Kirsher #define PXP2_REG_WR_QM_MPS 0x1205dc 3485*adfc5217SJeff Kirsher /* [RW 1] 0 - working in A0 mode; - working in B0 mode */ 3486*adfc5217SJeff Kirsher #define PXP2_REG_WR_REV_MODE 0x120670 3487*adfc5217SJeff Kirsher /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3488*adfc5217SJeff Kirsher buffer reaches this number has_payload will be asserted */ 3489*adfc5217SJeff Kirsher #define PXP2_REG_WR_SRC_MPS 0x1205e4 3490*adfc5217SJeff Kirsher /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3491*adfc5217SJeff Kirsher buffer reaches this number has_payload will be asserted */ 3492*adfc5217SJeff Kirsher #define PXP2_REG_WR_TM_MPS 0x1205e0 3493*adfc5217SJeff Kirsher /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3494*adfc5217SJeff Kirsher buffer reaches this number has_payload will be asserted */ 3495*adfc5217SJeff Kirsher #define PXP2_REG_WR_TSDM_MPS 0x1205d4 3496*adfc5217SJeff Kirsher /* [RW 10] if Number of entries in usdmdp fifo will be higher than this 3497*adfc5217SJeff Kirsher threshold then has_payload indication will be asserted; the default value 3498*adfc5217SJeff Kirsher should be equal to > write MBS size! */ 3499*adfc5217SJeff Kirsher #define PXP2_REG_WR_USDMDP_TH 0x120348 3500*adfc5217SJeff Kirsher /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3501*adfc5217SJeff Kirsher buffer reaches this number has_payload will be asserted */ 3502*adfc5217SJeff Kirsher #define PXP2_REG_WR_USDM_MPS 0x1205cc 3503*adfc5217SJeff Kirsher /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3504*adfc5217SJeff Kirsher buffer reaches this number has_payload will be asserted */ 3505*adfc5217SJeff Kirsher #define PXP2_REG_WR_XSDM_MPS 0x1205d8 3506*adfc5217SJeff Kirsher /* [R 1] debug only: Indication if PSWHST arbiter is idle */ 3507*adfc5217SJeff Kirsher #define PXP_REG_HST_ARB_IS_IDLE 0x103004 3508*adfc5217SJeff Kirsher /* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means 3509*adfc5217SJeff Kirsher this client is waiting for the arbiter. */ 3510*adfc5217SJeff Kirsher #define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008 3511*adfc5217SJeff Kirsher /* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue 3512*adfc5217SJeff Kirsher block. Should be used for close the gates. */ 3513*adfc5217SJeff Kirsher #define PXP_REG_HST_DISCARD_DOORBELLS 0x1030a4 3514*adfc5217SJeff Kirsher /* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit 3515*adfc5217SJeff Kirsher should update according to 'hst_discard_doorbells' register when the state 3516*adfc5217SJeff Kirsher machine is idle */ 3517*adfc5217SJeff Kirsher #define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0 3518*adfc5217SJeff Kirsher /* [RW 1] When 1; new internal writes arriving to the block are discarded. 3519*adfc5217SJeff Kirsher Should be used for close the gates. */ 3520*adfc5217SJeff Kirsher #define PXP_REG_HST_DISCARD_INTERNAL_WRITES 0x1030a8 3521*adfc5217SJeff Kirsher /* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1' 3522*adfc5217SJeff Kirsher means this PSWHST is discarding inputs from this client. Each bit should 3523*adfc5217SJeff Kirsher update according to 'hst_discard_internal_writes' register when the state 3524*adfc5217SJeff Kirsher machine is idle. */ 3525*adfc5217SJeff Kirsher #define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c 3526*adfc5217SJeff Kirsher /* [WB 160] Used for initialization of the inbound interrupts memory */ 3527*adfc5217SJeff Kirsher #define PXP_REG_HST_INBOUND_INT 0x103800 3528*adfc5217SJeff Kirsher /* [RW 32] Interrupt mask register #0 read/write */ 3529*adfc5217SJeff Kirsher #define PXP_REG_PXP_INT_MASK_0 0x103074 3530*adfc5217SJeff Kirsher #define PXP_REG_PXP_INT_MASK_1 0x103084 3531*adfc5217SJeff Kirsher /* [R 32] Interrupt register #0 read */ 3532*adfc5217SJeff Kirsher #define PXP_REG_PXP_INT_STS_0 0x103068 3533*adfc5217SJeff Kirsher #define PXP_REG_PXP_INT_STS_1 0x103078 3534*adfc5217SJeff Kirsher /* [RC 32] Interrupt register #0 read clear */ 3535*adfc5217SJeff Kirsher #define PXP_REG_PXP_INT_STS_CLR_0 0x10306c 3536*adfc5217SJeff Kirsher #define PXP_REG_PXP_INT_STS_CLR_1 0x10307c 3537*adfc5217SJeff Kirsher /* [RW 27] Parity mask register #0 read/write */ 3538*adfc5217SJeff Kirsher #define PXP_REG_PXP_PRTY_MASK 0x103094 3539*adfc5217SJeff Kirsher /* [R 26] Parity register #0 read */ 3540*adfc5217SJeff Kirsher #define PXP_REG_PXP_PRTY_STS 0x103088 3541*adfc5217SJeff Kirsher /* [RC 27] Parity register #0 read clear */ 3542*adfc5217SJeff Kirsher #define PXP_REG_PXP_PRTY_STS_CLR 0x10308c 3543*adfc5217SJeff Kirsher /* [RW 4] The activity counter initial increment value sent in the load 3544*adfc5217SJeff Kirsher request */ 3545*adfc5217SJeff Kirsher #define QM_REG_ACTCTRINITVAL_0 0x168040 3546*adfc5217SJeff Kirsher #define QM_REG_ACTCTRINITVAL_1 0x168044 3547*adfc5217SJeff Kirsher #define QM_REG_ACTCTRINITVAL_2 0x168048 3548*adfc5217SJeff Kirsher #define QM_REG_ACTCTRINITVAL_3 0x16804c 3549*adfc5217SJeff Kirsher /* [RW 32] The base logical address (in bytes) of each physical queue. The 3550*adfc5217SJeff Kirsher index I represents the physical queue number. The 12 lsbs are ignore and 3551*adfc5217SJeff Kirsher considered zero so practically there are only 20 bits in this register; 3552*adfc5217SJeff Kirsher queues 63-0 */ 3553*adfc5217SJeff Kirsher #define QM_REG_BASEADDR 0x168900 3554*adfc5217SJeff Kirsher /* [RW 32] The base logical address (in bytes) of each physical queue. The 3555*adfc5217SJeff Kirsher index I represents the physical queue number. The 12 lsbs are ignore and 3556*adfc5217SJeff Kirsher considered zero so practically there are only 20 bits in this register; 3557*adfc5217SJeff Kirsher queues 127-64 */ 3558*adfc5217SJeff Kirsher #define QM_REG_BASEADDR_EXT_A 0x16e100 3559*adfc5217SJeff Kirsher /* [RW 16] The byte credit cost for each task. This value is for both ports */ 3560*adfc5217SJeff Kirsher #define QM_REG_BYTECRDCOST 0x168234 3561*adfc5217SJeff Kirsher /* [RW 16] The initial byte credit value for both ports. */ 3562*adfc5217SJeff Kirsher #define QM_REG_BYTECRDINITVAL 0x168238 3563*adfc5217SJeff Kirsher /* [RW 32] A bit per physical queue. If the bit is cleared then the physical 3564*adfc5217SJeff Kirsher queue uses port 0 else it uses port 1; queues 31-0 */ 3565*adfc5217SJeff Kirsher #define QM_REG_BYTECRDPORT_LSB 0x168228 3566*adfc5217SJeff Kirsher /* [RW 32] A bit per physical queue. If the bit is cleared then the physical 3567*adfc5217SJeff Kirsher queue uses port 0 else it uses port 1; queues 95-64 */ 3568*adfc5217SJeff Kirsher #define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520 3569*adfc5217SJeff Kirsher /* [RW 32] A bit per physical queue. If the bit is cleared then the physical 3570*adfc5217SJeff Kirsher queue uses port 0 else it uses port 1; queues 63-32 */ 3571*adfc5217SJeff Kirsher #define QM_REG_BYTECRDPORT_MSB 0x168224 3572*adfc5217SJeff Kirsher /* [RW 32] A bit per physical queue. If the bit is cleared then the physical 3573*adfc5217SJeff Kirsher queue uses port 0 else it uses port 1; queues 127-96 */ 3574*adfc5217SJeff Kirsher #define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c 3575*adfc5217SJeff Kirsher /* [RW 16] The byte credit value that if above the QM is considered almost 3576*adfc5217SJeff Kirsher full */ 3577*adfc5217SJeff Kirsher #define QM_REG_BYTECREDITAFULLTHR 0x168094 3578*adfc5217SJeff Kirsher /* [RW 4] The initial credit for interface */ 3579*adfc5217SJeff Kirsher #define QM_REG_CMINITCRD_0 0x1680cc 3580*adfc5217SJeff Kirsher #define QM_REG_BYTECRDCMDQ_0 0x16e6e8 3581*adfc5217SJeff Kirsher #define QM_REG_CMINITCRD_1 0x1680d0 3582*adfc5217SJeff Kirsher #define QM_REG_CMINITCRD_2 0x1680d4 3583*adfc5217SJeff Kirsher #define QM_REG_CMINITCRD_3 0x1680d8 3584*adfc5217SJeff Kirsher #define QM_REG_CMINITCRD_4 0x1680dc 3585*adfc5217SJeff Kirsher #define QM_REG_CMINITCRD_5 0x1680e0 3586*adfc5217SJeff Kirsher #define QM_REG_CMINITCRD_6 0x1680e4 3587*adfc5217SJeff Kirsher #define QM_REG_CMINITCRD_7 0x1680e8 3588*adfc5217SJeff Kirsher /* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface 3589*adfc5217SJeff Kirsher is masked */ 3590*adfc5217SJeff Kirsher #define QM_REG_CMINTEN 0x1680ec 3591*adfc5217SJeff Kirsher /* [RW 12] A bit vector which indicates which one of the queues are tied to 3592*adfc5217SJeff Kirsher interface 0 */ 3593*adfc5217SJeff Kirsher #define QM_REG_CMINTVOQMASK_0 0x1681f4 3594*adfc5217SJeff Kirsher #define QM_REG_CMINTVOQMASK_1 0x1681f8 3595*adfc5217SJeff Kirsher #define QM_REG_CMINTVOQMASK_2 0x1681fc 3596*adfc5217SJeff Kirsher #define QM_REG_CMINTVOQMASK_3 0x168200 3597*adfc5217SJeff Kirsher #define QM_REG_CMINTVOQMASK_4 0x168204 3598*adfc5217SJeff Kirsher #define QM_REG_CMINTVOQMASK_5 0x168208 3599*adfc5217SJeff Kirsher #define QM_REG_CMINTVOQMASK_6 0x16820c 3600*adfc5217SJeff Kirsher #define QM_REG_CMINTVOQMASK_7 0x168210 3601*adfc5217SJeff Kirsher /* [RW 20] The number of connections divided by 16 which dictates the size 3602*adfc5217SJeff Kirsher of each queue which belongs to even function number. */ 3603*adfc5217SJeff Kirsher #define QM_REG_CONNNUM_0 0x168020 3604*adfc5217SJeff Kirsher /* [R 6] Keep the fill level of the fifo from write client 4 */ 3605*adfc5217SJeff Kirsher #define QM_REG_CQM_WRC_FIFOLVL 0x168018 3606*adfc5217SJeff Kirsher /* [RW 8] The context regions sent in the CFC load request */ 3607*adfc5217SJeff Kirsher #define QM_REG_CTXREG_0 0x168030 3608*adfc5217SJeff Kirsher #define QM_REG_CTXREG_1 0x168034 3609*adfc5217SJeff Kirsher #define QM_REG_CTXREG_2 0x168038 3610*adfc5217SJeff Kirsher #define QM_REG_CTXREG_3 0x16803c 3611*adfc5217SJeff Kirsher /* [RW 12] The VOQ mask used to select the VOQs which needs to be full for 3612*adfc5217SJeff Kirsher bypass enable */ 3613*adfc5217SJeff Kirsher #define QM_REG_ENBYPVOQMASK 0x16823c 3614*adfc5217SJeff Kirsher /* [RW 32] A bit mask per each physical queue. If a bit is set then the 3615*adfc5217SJeff Kirsher physical queue uses the byte credit; queues 31-0 */ 3616*adfc5217SJeff Kirsher #define QM_REG_ENBYTECRD_LSB 0x168220 3617*adfc5217SJeff Kirsher /* [RW 32] A bit mask per each physical queue. If a bit is set then the 3618*adfc5217SJeff Kirsher physical queue uses the byte credit; queues 95-64 */ 3619*adfc5217SJeff Kirsher #define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518 3620*adfc5217SJeff Kirsher /* [RW 32] A bit mask per each physical queue. If a bit is set then the 3621*adfc5217SJeff Kirsher physical queue uses the byte credit; queues 63-32 */ 3622*adfc5217SJeff Kirsher #define QM_REG_ENBYTECRD_MSB 0x16821c 3623*adfc5217SJeff Kirsher /* [RW 32] A bit mask per each physical queue. If a bit is set then the 3624*adfc5217SJeff Kirsher physical queue uses the byte credit; queues 127-96 */ 3625*adfc5217SJeff Kirsher #define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514 3626*adfc5217SJeff Kirsher /* [RW 4] If cleared then the secondary interface will not be served by the 3627*adfc5217SJeff Kirsher RR arbiter */ 3628*adfc5217SJeff Kirsher #define QM_REG_ENSEC 0x1680f0 3629*adfc5217SJeff Kirsher /* [RW 32] NA */ 3630*adfc5217SJeff Kirsher #define QM_REG_FUNCNUMSEL_LSB 0x168230 3631*adfc5217SJeff Kirsher /* [RW 32] NA */ 3632*adfc5217SJeff Kirsher #define QM_REG_FUNCNUMSEL_MSB 0x16822c 3633*adfc5217SJeff Kirsher /* [RW 32] A mask register to mask the Almost empty signals which will not 3634*adfc5217SJeff Kirsher be use for the almost empty indication to the HW block; queues 31:0 */ 3635*adfc5217SJeff Kirsher #define QM_REG_HWAEMPTYMASK_LSB 0x168218 3636*adfc5217SJeff Kirsher /* [RW 32] A mask register to mask the Almost empty signals which will not 3637*adfc5217SJeff Kirsher be use for the almost empty indication to the HW block; queues 95-64 */ 3638*adfc5217SJeff Kirsher #define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510 3639*adfc5217SJeff Kirsher /* [RW 32] A mask register to mask the Almost empty signals which will not 3640*adfc5217SJeff Kirsher be use for the almost empty indication to the HW block; queues 63:32 */ 3641*adfc5217SJeff Kirsher #define QM_REG_HWAEMPTYMASK_MSB 0x168214 3642*adfc5217SJeff Kirsher /* [RW 32] A mask register to mask the Almost empty signals which will not 3643*adfc5217SJeff Kirsher be use for the almost empty indication to the HW block; queues 127-96 */ 3644*adfc5217SJeff Kirsher #define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c 3645*adfc5217SJeff Kirsher /* [RW 4] The number of outstanding request to CFC */ 3646*adfc5217SJeff Kirsher #define QM_REG_OUTLDREQ 0x168804 3647*adfc5217SJeff Kirsher /* [RC 1] A flag to indicate that overflow error occurred in one of the 3648*adfc5217SJeff Kirsher queues. */ 3649*adfc5217SJeff Kirsher #define QM_REG_OVFERROR 0x16805c 3650*adfc5217SJeff Kirsher /* [RC 7] the Q where the overflow occurs */ 3651*adfc5217SJeff Kirsher #define QM_REG_OVFQNUM 0x168058 3652*adfc5217SJeff Kirsher /* [R 16] Pause state for physical queues 15-0 */ 3653*adfc5217SJeff Kirsher #define QM_REG_PAUSESTATE0 0x168410 3654*adfc5217SJeff Kirsher /* [R 16] Pause state for physical queues 31-16 */ 3655*adfc5217SJeff Kirsher #define QM_REG_PAUSESTATE1 0x168414 3656*adfc5217SJeff Kirsher /* [R 16] Pause state for physical queues 47-32 */ 3657*adfc5217SJeff Kirsher #define QM_REG_PAUSESTATE2 0x16e684 3658*adfc5217SJeff Kirsher /* [R 16] Pause state for physical queues 63-48 */ 3659*adfc5217SJeff Kirsher #define QM_REG_PAUSESTATE3 0x16e688 3660*adfc5217SJeff Kirsher /* [R 16] Pause state for physical queues 79-64 */ 3661*adfc5217SJeff Kirsher #define QM_REG_PAUSESTATE4 0x16e68c 3662*adfc5217SJeff Kirsher /* [R 16] Pause state for physical queues 95-80 */ 3663*adfc5217SJeff Kirsher #define QM_REG_PAUSESTATE5 0x16e690 3664*adfc5217SJeff Kirsher /* [R 16] Pause state for physical queues 111-96 */ 3665*adfc5217SJeff Kirsher #define QM_REG_PAUSESTATE6 0x16e694 3666*adfc5217SJeff Kirsher /* [R 16] Pause state for physical queues 127-112 */ 3667*adfc5217SJeff Kirsher #define QM_REG_PAUSESTATE7 0x16e698 3668*adfc5217SJeff Kirsher /* [RW 2] The PCI attributes field used in the PCI request. */ 3669*adfc5217SJeff Kirsher #define QM_REG_PCIREQAT 0x168054 3670*adfc5217SJeff Kirsher #define QM_REG_PF_EN 0x16e70c 3671*adfc5217SJeff Kirsher /* [R 24] The number of tasks stored in the QM for the PF. only even 3672*adfc5217SJeff Kirsher * functions are valid in E2 (odd I registers will be hard wired to 0) */ 3673*adfc5217SJeff Kirsher #define QM_REG_PF_USG_CNT_0 0x16e040 3674*adfc5217SJeff Kirsher /* [R 16] NOT USED */ 3675*adfc5217SJeff Kirsher #define QM_REG_PORT0BYTECRD 0x168300 3676*adfc5217SJeff Kirsher /* [R 16] The byte credit of port 1 */ 3677*adfc5217SJeff Kirsher #define QM_REG_PORT1BYTECRD 0x168304 3678*adfc5217SJeff Kirsher /* [RW 3] pci function number of queues 15-0 */ 3679*adfc5217SJeff Kirsher #define QM_REG_PQ2PCIFUNC_0 0x16e6bc 3680*adfc5217SJeff Kirsher #define QM_REG_PQ2PCIFUNC_1 0x16e6c0 3681*adfc5217SJeff Kirsher #define QM_REG_PQ2PCIFUNC_2 0x16e6c4 3682*adfc5217SJeff Kirsher #define QM_REG_PQ2PCIFUNC_3 0x16e6c8 3683*adfc5217SJeff Kirsher #define QM_REG_PQ2PCIFUNC_4 0x16e6cc 3684*adfc5217SJeff Kirsher #define QM_REG_PQ2PCIFUNC_5 0x16e6d0 3685*adfc5217SJeff Kirsher #define QM_REG_PQ2PCIFUNC_6 0x16e6d4 3686*adfc5217SJeff Kirsher #define QM_REG_PQ2PCIFUNC_7 0x16e6d8 3687*adfc5217SJeff Kirsher /* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow: 3688*adfc5217SJeff Kirsher ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read 3689*adfc5217SJeff Kirsher bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */ 3690*adfc5217SJeff Kirsher #define QM_REG_PTRTBL 0x168a00 3691*adfc5217SJeff Kirsher /* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow: 3692*adfc5217SJeff Kirsher ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read 3693*adfc5217SJeff Kirsher bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */ 3694*adfc5217SJeff Kirsher #define QM_REG_PTRTBL_EXT_A 0x16e200 3695*adfc5217SJeff Kirsher /* [RW 2] Interrupt mask register #0 read/write */ 3696*adfc5217SJeff Kirsher #define QM_REG_QM_INT_MASK 0x168444 3697*adfc5217SJeff Kirsher /* [R 2] Interrupt register #0 read */ 3698*adfc5217SJeff Kirsher #define QM_REG_QM_INT_STS 0x168438 3699*adfc5217SJeff Kirsher /* [RW 12] Parity mask register #0 read/write */ 3700*adfc5217SJeff Kirsher #define QM_REG_QM_PRTY_MASK 0x168454 3701*adfc5217SJeff Kirsher /* [R 12] Parity register #0 read */ 3702*adfc5217SJeff Kirsher #define QM_REG_QM_PRTY_STS 0x168448 3703*adfc5217SJeff Kirsher /* [RC 12] Parity register #0 read clear */ 3704*adfc5217SJeff Kirsher #define QM_REG_QM_PRTY_STS_CLR 0x16844c 3705*adfc5217SJeff Kirsher /* [R 32] Current queues in pipeline: Queues from 32 to 63 */ 3706*adfc5217SJeff Kirsher #define QM_REG_QSTATUS_HIGH 0x16802c 3707*adfc5217SJeff Kirsher /* [R 32] Current queues in pipeline: Queues from 96 to 127 */ 3708*adfc5217SJeff Kirsher #define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408 3709*adfc5217SJeff Kirsher /* [R 32] Current queues in pipeline: Queues from 0 to 31 */ 3710*adfc5217SJeff Kirsher #define QM_REG_QSTATUS_LOW 0x168028 3711*adfc5217SJeff Kirsher /* [R 32] Current queues in pipeline: Queues from 64 to 95 */ 3712*adfc5217SJeff Kirsher #define QM_REG_QSTATUS_LOW_EXT_A 0x16e404 3713*adfc5217SJeff Kirsher /* [R 24] The number of tasks queued for each queue; queues 63-0 */ 3714*adfc5217SJeff Kirsher #define QM_REG_QTASKCTR_0 0x168308 3715*adfc5217SJeff Kirsher /* [R 24] The number of tasks queued for each queue; queues 127-64 */ 3716*adfc5217SJeff Kirsher #define QM_REG_QTASKCTR_EXT_A_0 0x16e584 3717*adfc5217SJeff Kirsher /* [RW 4] Queue tied to VOQ */ 3718*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_0 0x1680f4 3719*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_10 0x16811c 3720*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_100 0x16e49c 3721*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_101 0x16e4a0 3722*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_102 0x16e4a4 3723*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_103 0x16e4a8 3724*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_104 0x16e4ac 3725*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_105 0x16e4b0 3726*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_106 0x16e4b4 3727*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_107 0x16e4b8 3728*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_108 0x16e4bc 3729*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_109 0x16e4c0 3730*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_11 0x168120 3731*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_110 0x16e4c4 3732*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_111 0x16e4c8 3733*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_112 0x16e4cc 3734*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_113 0x16e4d0 3735*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_114 0x16e4d4 3736*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_115 0x16e4d8 3737*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_116 0x16e4dc 3738*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_117 0x16e4e0 3739*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_118 0x16e4e4 3740*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_119 0x16e4e8 3741*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_12 0x168124 3742*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_120 0x16e4ec 3743*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_121 0x16e4f0 3744*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_122 0x16e4f4 3745*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_123 0x16e4f8 3746*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_124 0x16e4fc 3747*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_125 0x16e500 3748*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_126 0x16e504 3749*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_127 0x16e508 3750*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_13 0x168128 3751*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_14 0x16812c 3752*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_15 0x168130 3753*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_16 0x168134 3754*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_17 0x168138 3755*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_21 0x168148 3756*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_22 0x16814c 3757*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_23 0x168150 3758*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_24 0x168154 3759*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_25 0x168158 3760*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_26 0x16815c 3761*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_27 0x168160 3762*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_28 0x168164 3763*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_29 0x168168 3764*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_30 0x16816c 3765*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_31 0x168170 3766*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_32 0x168174 3767*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_33 0x168178 3768*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_34 0x16817c 3769*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_35 0x168180 3770*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_36 0x168184 3771*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_37 0x168188 3772*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_38 0x16818c 3773*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_39 0x168190 3774*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_40 0x168194 3775*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_41 0x168198 3776*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_42 0x16819c 3777*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_43 0x1681a0 3778*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_44 0x1681a4 3779*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_45 0x1681a8 3780*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_46 0x1681ac 3781*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_47 0x1681b0 3782*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_48 0x1681b4 3783*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_49 0x1681b8 3784*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_5 0x168108 3785*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_50 0x1681bc 3786*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_51 0x1681c0 3787*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_52 0x1681c4 3788*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_53 0x1681c8 3789*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_54 0x1681cc 3790*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_55 0x1681d0 3791*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_56 0x1681d4 3792*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_57 0x1681d8 3793*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_58 0x1681dc 3794*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_59 0x1681e0 3795*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_6 0x16810c 3796*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_60 0x1681e4 3797*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_61 0x1681e8 3798*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_62 0x1681ec 3799*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_63 0x1681f0 3800*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_64 0x16e40c 3801*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_65 0x16e410 3802*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_69 0x16e420 3803*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_7 0x168110 3804*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_70 0x16e424 3805*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_71 0x16e428 3806*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_72 0x16e42c 3807*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_73 0x16e430 3808*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_74 0x16e434 3809*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_75 0x16e438 3810*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_76 0x16e43c 3811*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_77 0x16e440 3812*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_78 0x16e444 3813*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_79 0x16e448 3814*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_8 0x168114 3815*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_80 0x16e44c 3816*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_81 0x16e450 3817*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_85 0x16e460 3818*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_86 0x16e464 3819*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_87 0x16e468 3820*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_88 0x16e46c 3821*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_89 0x16e470 3822*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_9 0x168118 3823*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_90 0x16e474 3824*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_91 0x16e478 3825*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_92 0x16e47c 3826*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_93 0x16e480 3827*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_94 0x16e484 3828*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_95 0x16e488 3829*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_96 0x16e48c 3830*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_97 0x16e490 3831*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_98 0x16e494 3832*adfc5217SJeff Kirsher #define QM_REG_QVOQIDX_99 0x16e498 3833*adfc5217SJeff Kirsher /* [RW 1] Initialization bit command */ 3834*adfc5217SJeff Kirsher #define QM_REG_SOFT_RESET 0x168428 3835*adfc5217SJeff Kirsher /* [RW 8] The credit cost per every task in the QM. A value per each VOQ */ 3836*adfc5217SJeff Kirsher #define QM_REG_TASKCRDCOST_0 0x16809c 3837*adfc5217SJeff Kirsher #define QM_REG_TASKCRDCOST_1 0x1680a0 3838*adfc5217SJeff Kirsher #define QM_REG_TASKCRDCOST_2 0x1680a4 3839*adfc5217SJeff Kirsher #define QM_REG_TASKCRDCOST_4 0x1680ac 3840*adfc5217SJeff Kirsher #define QM_REG_TASKCRDCOST_5 0x1680b0 3841*adfc5217SJeff Kirsher /* [R 6] Keep the fill level of the fifo from write client 3 */ 3842*adfc5217SJeff Kirsher #define QM_REG_TQM_WRC_FIFOLVL 0x168010 3843*adfc5217SJeff Kirsher /* [R 6] Keep the fill level of the fifo from write client 2 */ 3844*adfc5217SJeff Kirsher #define QM_REG_UQM_WRC_FIFOLVL 0x168008 3845*adfc5217SJeff Kirsher /* [RC 32] Credit update error register */ 3846*adfc5217SJeff Kirsher #define QM_REG_VOQCRDERRREG 0x168408 3847*adfc5217SJeff Kirsher /* [R 16] The credit value for each VOQ */ 3848*adfc5217SJeff Kirsher #define QM_REG_VOQCREDIT_0 0x1682d0 3849*adfc5217SJeff Kirsher #define QM_REG_VOQCREDIT_1 0x1682d4 3850*adfc5217SJeff Kirsher #define QM_REG_VOQCREDIT_4 0x1682e0 3851*adfc5217SJeff Kirsher /* [RW 16] The credit value that if above the QM is considered almost full */ 3852*adfc5217SJeff Kirsher #define QM_REG_VOQCREDITAFULLTHR 0x168090 3853*adfc5217SJeff Kirsher /* [RW 16] The init and maximum credit for each VoQ */ 3854*adfc5217SJeff Kirsher #define QM_REG_VOQINITCREDIT_0 0x168060 3855*adfc5217SJeff Kirsher #define QM_REG_VOQINITCREDIT_1 0x168064 3856*adfc5217SJeff Kirsher #define QM_REG_VOQINITCREDIT_2 0x168068 3857*adfc5217SJeff Kirsher #define QM_REG_VOQINITCREDIT_4 0x168070 3858*adfc5217SJeff Kirsher #define QM_REG_VOQINITCREDIT_5 0x168074 3859*adfc5217SJeff Kirsher /* [RW 1] The port of which VOQ belongs */ 3860*adfc5217SJeff Kirsher #define QM_REG_VOQPORT_0 0x1682a0 3861*adfc5217SJeff Kirsher #define QM_REG_VOQPORT_1 0x1682a4 3862*adfc5217SJeff Kirsher #define QM_REG_VOQPORT_2 0x1682a8 3863*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3864*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_0_LSB 0x168240 3865*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3866*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524 3867*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3868*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_0_MSB 0x168244 3869*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3870*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528 3871*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3872*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_10_LSB 0x168290 3873*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3874*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574 3875*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3876*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_10_MSB 0x168294 3877*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3878*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578 3879*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3880*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_11_LSB 0x168298 3881*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3882*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c 3883*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3884*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_11_MSB 0x16829c 3885*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3886*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580 3887*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3888*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_1_LSB 0x168248 3889*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3890*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c 3891*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3892*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_1_MSB 0x16824c 3893*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3894*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530 3895*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3896*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_2_LSB 0x168250 3897*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3898*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534 3899*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3900*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_2_MSB 0x168254 3901*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3902*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538 3903*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3904*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_3_LSB 0x168258 3905*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3906*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c 3907*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3908*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540 3909*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3910*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_4_LSB 0x168260 3911*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3912*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544 3913*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3914*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_4_MSB 0x168264 3915*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3916*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548 3917*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3918*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_5_LSB 0x168268 3919*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3920*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c 3921*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3922*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_5_MSB 0x16826c 3923*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3924*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550 3925*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3926*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_6_LSB 0x168270 3927*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3928*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554 3929*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3930*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_6_MSB 0x168274 3931*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3932*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558 3933*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3934*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_7_LSB 0x168278 3935*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3936*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c 3937*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3938*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_7_MSB 0x16827c 3939*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3940*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560 3941*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3942*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_8_LSB 0x168280 3943*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3944*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564 3945*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 3946*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_8_MSB 0x168284 3947*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3948*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568 3949*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3950*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_9_LSB 0x168288 3951*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 3952*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c 3953*adfc5217SJeff Kirsher /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 3954*adfc5217SJeff Kirsher #define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570 3955*adfc5217SJeff Kirsher /* [RW 32] Wrr weights */ 3956*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_0 0x16880c 3957*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_1 0x168810 3958*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_10 0x168814 3959*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_11 0x168818 3960*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_12 0x16881c 3961*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_13 0x168820 3962*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_14 0x168824 3963*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_15 0x168828 3964*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_16 0x16e000 3965*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_17 0x16e004 3966*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_18 0x16e008 3967*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_19 0x16e00c 3968*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_2 0x16882c 3969*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_20 0x16e010 3970*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_21 0x16e014 3971*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_22 0x16e018 3972*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_23 0x16e01c 3973*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_24 0x16e020 3974*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_25 0x16e024 3975*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_26 0x16e028 3976*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_27 0x16e02c 3977*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_28 0x16e030 3978*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_29 0x16e034 3979*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_3 0x168830 3980*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_30 0x16e038 3981*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_31 0x16e03c 3982*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_4 0x168834 3983*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_5 0x168838 3984*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_6 0x16883c 3985*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_7 0x168840 3986*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_8 0x168844 3987*adfc5217SJeff Kirsher #define QM_REG_WRRWEIGHTS_9 0x168848 3988*adfc5217SJeff Kirsher /* [R 6] Keep the fill level of the fifo from write client 1 */ 3989*adfc5217SJeff Kirsher #define QM_REG_XQM_WRC_FIFOLVL 0x168000 3990*adfc5217SJeff Kirsher /* [W 1] reset to parity interrupt */ 3991*adfc5217SJeff Kirsher #define SEM_FAST_REG_PARITY_RST 0x18840 3992*adfc5217SJeff Kirsher #define SRC_REG_COUNTFREE0 0x40500 3993*adfc5217SJeff Kirsher /* [RW 1] If clr the searcher is compatible to E1 A0 - support only two 3994*adfc5217SJeff Kirsher ports. If set the searcher support 8 functions. */ 3995*adfc5217SJeff Kirsher #define SRC_REG_E1HMF_ENABLE 0x404cc 3996*adfc5217SJeff Kirsher #define SRC_REG_FIRSTFREE0 0x40510 3997*adfc5217SJeff Kirsher #define SRC_REG_KEYRSS0_0 0x40408 3998*adfc5217SJeff Kirsher #define SRC_REG_KEYRSS0_7 0x40424 3999*adfc5217SJeff Kirsher #define SRC_REG_KEYRSS1_9 0x40454 4000*adfc5217SJeff Kirsher #define SRC_REG_KEYSEARCH_0 0x40458 4001*adfc5217SJeff Kirsher #define SRC_REG_KEYSEARCH_1 0x4045c 4002*adfc5217SJeff Kirsher #define SRC_REG_KEYSEARCH_2 0x40460 4003*adfc5217SJeff Kirsher #define SRC_REG_KEYSEARCH_3 0x40464 4004*adfc5217SJeff Kirsher #define SRC_REG_KEYSEARCH_4 0x40468 4005*adfc5217SJeff Kirsher #define SRC_REG_KEYSEARCH_5 0x4046c 4006*adfc5217SJeff Kirsher #define SRC_REG_KEYSEARCH_6 0x40470 4007*adfc5217SJeff Kirsher #define SRC_REG_KEYSEARCH_7 0x40474 4008*adfc5217SJeff Kirsher #define SRC_REG_KEYSEARCH_8 0x40478 4009*adfc5217SJeff Kirsher #define SRC_REG_KEYSEARCH_9 0x4047c 4010*adfc5217SJeff Kirsher #define SRC_REG_LASTFREE0 0x40530 4011*adfc5217SJeff Kirsher #define SRC_REG_NUMBER_HASH_BITS0 0x40400 4012*adfc5217SJeff Kirsher /* [RW 1] Reset internal state machines. */ 4013*adfc5217SJeff Kirsher #define SRC_REG_SOFT_RST 0x4049c 4014*adfc5217SJeff Kirsher /* [R 3] Interrupt register #0 read */ 4015*adfc5217SJeff Kirsher #define SRC_REG_SRC_INT_STS 0x404ac 4016*adfc5217SJeff Kirsher /* [RW 3] Parity mask register #0 read/write */ 4017*adfc5217SJeff Kirsher #define SRC_REG_SRC_PRTY_MASK 0x404c8 4018*adfc5217SJeff Kirsher /* [R 3] Parity register #0 read */ 4019*adfc5217SJeff Kirsher #define SRC_REG_SRC_PRTY_STS 0x404bc 4020*adfc5217SJeff Kirsher /* [RC 3] Parity register #0 read clear */ 4021*adfc5217SJeff Kirsher #define SRC_REG_SRC_PRTY_STS_CLR 0x404c0 4022*adfc5217SJeff Kirsher /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */ 4023*adfc5217SJeff Kirsher #define TCM_REG_CAM_OCCUP 0x5017c 4024*adfc5217SJeff Kirsher /* [RW 1] CDU AG read Interface enable. If 0 - the request input is 4025*adfc5217SJeff Kirsher disregarded; valid output is deasserted; all other signals are treated as 4026*adfc5217SJeff Kirsher usual; if 1 - normal activity. */ 4027*adfc5217SJeff Kirsher #define TCM_REG_CDU_AG_RD_IFEN 0x50034 4028*adfc5217SJeff Kirsher /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 4029*adfc5217SJeff Kirsher are disregarded; all other signals are treated as usual; if 1 - normal 4030*adfc5217SJeff Kirsher activity. */ 4031*adfc5217SJeff Kirsher #define TCM_REG_CDU_AG_WR_IFEN 0x50030 4032*adfc5217SJeff Kirsher /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 4033*adfc5217SJeff Kirsher disregarded; valid output is deasserted; all other signals are treated as 4034*adfc5217SJeff Kirsher usual; if 1 - normal activity. */ 4035*adfc5217SJeff Kirsher #define TCM_REG_CDU_SM_RD_IFEN 0x5003c 4036*adfc5217SJeff Kirsher /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 4037*adfc5217SJeff Kirsher input is disregarded; all other signals are treated as usual; if 1 - 4038*adfc5217SJeff Kirsher normal activity. */ 4039*adfc5217SJeff Kirsher #define TCM_REG_CDU_SM_WR_IFEN 0x50038 4040*adfc5217SJeff Kirsher /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 4041*adfc5217SJeff Kirsher the initial credit value; read returns the current value of the credit 4042*adfc5217SJeff Kirsher counter. Must be initialized to 1 at start-up. */ 4043*adfc5217SJeff Kirsher #define TCM_REG_CFC_INIT_CRD 0x50204 4044*adfc5217SJeff Kirsher /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for 4045*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 4046*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 4047*adfc5217SJeff Kirsher #define TCM_REG_CP_WEIGHT 0x500c0 4048*adfc5217SJeff Kirsher /* [RW 1] Input csem Interface enable. If 0 - the valid input is 4049*adfc5217SJeff Kirsher disregarded; acknowledge output is deasserted; all other signals are 4050*adfc5217SJeff Kirsher treated as usual; if 1 - normal activity. */ 4051*adfc5217SJeff Kirsher #define TCM_REG_CSEM_IFEN 0x5002c 4052*adfc5217SJeff Kirsher /* [RC 1] Message length mismatch (relative to last indication) at the In#9 4053*adfc5217SJeff Kirsher interface. */ 4054*adfc5217SJeff Kirsher #define TCM_REG_CSEM_LENGTH_MIS 0x50174 4055*adfc5217SJeff Kirsher /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for 4056*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 4057*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 4058*adfc5217SJeff Kirsher #define TCM_REG_CSEM_WEIGHT 0x500bc 4059*adfc5217SJeff Kirsher /* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */ 4060*adfc5217SJeff Kirsher #define TCM_REG_ERR_EVNT_ID 0x500a0 4061*adfc5217SJeff Kirsher /* [RW 28] The CM erroneous header for QM and Timers formatting. */ 4062*adfc5217SJeff Kirsher #define TCM_REG_ERR_TCM_HDR 0x5009c 4063*adfc5217SJeff Kirsher /* [RW 8] The Event ID for Timers expiration. */ 4064*adfc5217SJeff Kirsher #define TCM_REG_EXPR_EVNT_ID 0x500a4 4065*adfc5217SJeff Kirsher /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write 4066*adfc5217SJeff Kirsher writes the initial credit value; read returns the current value of the 4067*adfc5217SJeff Kirsher credit counter. Must be initialized to 64 at start-up. */ 4068*adfc5217SJeff Kirsher #define TCM_REG_FIC0_INIT_CRD 0x5020c 4069*adfc5217SJeff Kirsher /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 4070*adfc5217SJeff Kirsher writes the initial credit value; read returns the current value of the 4071*adfc5217SJeff Kirsher credit counter. Must be initialized to 64 at start-up. */ 4072*adfc5217SJeff Kirsher #define TCM_REG_FIC1_INIT_CRD 0x50210 4073*adfc5217SJeff Kirsher /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 4074*adfc5217SJeff Kirsher - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr; 4075*adfc5217SJeff Kirsher ~tcm_registers_gr_ld0_pr.gr_ld0_pr and 4076*adfc5217SJeff Kirsher ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */ 4077*adfc5217SJeff Kirsher #define TCM_REG_GR_ARB_TYPE 0x50114 4078*adfc5217SJeff Kirsher /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 4079*adfc5217SJeff Kirsher highest priority is 3. It is supposed that the Store channel is the 4080*adfc5217SJeff Kirsher compliment of the other 3 groups. */ 4081*adfc5217SJeff Kirsher #define TCM_REG_GR_LD0_PR 0x5011c 4082*adfc5217SJeff Kirsher /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 4083*adfc5217SJeff Kirsher highest priority is 3. It is supposed that the Store channel is the 4084*adfc5217SJeff Kirsher compliment of the other 3 groups. */ 4085*adfc5217SJeff Kirsher #define TCM_REG_GR_LD1_PR 0x50120 4086*adfc5217SJeff Kirsher /* [RW 4] The number of double REG-pairs; loaded from the STORM context and 4087*adfc5217SJeff Kirsher sent to STORM; for a specific connection type. The double REG-pairs are 4088*adfc5217SJeff Kirsher used to align to STORM context row size of 128 bits. The offset of these 4089*adfc5217SJeff Kirsher data in the STORM context is always 0. Index _i stands for the connection 4090*adfc5217SJeff Kirsher type (one of 16). */ 4091*adfc5217SJeff Kirsher #define TCM_REG_N_SM_CTX_LD_0 0x50050 4092*adfc5217SJeff Kirsher #define TCM_REG_N_SM_CTX_LD_1 0x50054 4093*adfc5217SJeff Kirsher #define TCM_REG_N_SM_CTX_LD_2 0x50058 4094*adfc5217SJeff Kirsher #define TCM_REG_N_SM_CTX_LD_3 0x5005c 4095*adfc5217SJeff Kirsher #define TCM_REG_N_SM_CTX_LD_4 0x50060 4096*adfc5217SJeff Kirsher #define TCM_REG_N_SM_CTX_LD_5 0x50064 4097*adfc5217SJeff Kirsher /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; 4098*adfc5217SJeff Kirsher acknowledge output is deasserted; all other signals are treated as usual; 4099*adfc5217SJeff Kirsher if 1 - normal activity. */ 4100*adfc5217SJeff Kirsher #define TCM_REG_PBF_IFEN 0x50024 4101*adfc5217SJeff Kirsher /* [RC 1] Message length mismatch (relative to last indication) at the In#7 4102*adfc5217SJeff Kirsher interface. */ 4103*adfc5217SJeff Kirsher #define TCM_REG_PBF_LENGTH_MIS 0x5016c 4104*adfc5217SJeff Kirsher /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for 4105*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 4106*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 4107*adfc5217SJeff Kirsher #define TCM_REG_PBF_WEIGHT 0x500b4 4108*adfc5217SJeff Kirsher #define TCM_REG_PHYS_QNUM0_0 0x500e0 4109*adfc5217SJeff Kirsher #define TCM_REG_PHYS_QNUM0_1 0x500e4 4110*adfc5217SJeff Kirsher #define TCM_REG_PHYS_QNUM1_0 0x500e8 4111*adfc5217SJeff Kirsher #define TCM_REG_PHYS_QNUM1_1 0x500ec 4112*adfc5217SJeff Kirsher #define TCM_REG_PHYS_QNUM2_0 0x500f0 4113*adfc5217SJeff Kirsher #define TCM_REG_PHYS_QNUM2_1 0x500f4 4114*adfc5217SJeff Kirsher #define TCM_REG_PHYS_QNUM3_0 0x500f8 4115*adfc5217SJeff Kirsher #define TCM_REG_PHYS_QNUM3_1 0x500fc 4116*adfc5217SJeff Kirsher /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded; 4117*adfc5217SJeff Kirsher acknowledge output is deasserted; all other signals are treated as usual; 4118*adfc5217SJeff Kirsher if 1 - normal activity. */ 4119*adfc5217SJeff Kirsher #define TCM_REG_PRS_IFEN 0x50020 4120*adfc5217SJeff Kirsher /* [RC 1] Message length mismatch (relative to last indication) at the In#6 4121*adfc5217SJeff Kirsher interface. */ 4122*adfc5217SJeff Kirsher #define TCM_REG_PRS_LENGTH_MIS 0x50168 4123*adfc5217SJeff Kirsher /* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for 4124*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 4125*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 4126*adfc5217SJeff Kirsher #define TCM_REG_PRS_WEIGHT 0x500b0 4127*adfc5217SJeff Kirsher /* [RW 8] The Event ID for Timers formatting in case of stop done. */ 4128*adfc5217SJeff Kirsher #define TCM_REG_STOP_EVNT_ID 0x500a8 4129*adfc5217SJeff Kirsher /* [RC 1] Message length mismatch (relative to last indication) at the STORM 4130*adfc5217SJeff Kirsher interface. */ 4131*adfc5217SJeff Kirsher #define TCM_REG_STORM_LENGTH_MIS 0x50160 4132*adfc5217SJeff Kirsher /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 4133*adfc5217SJeff Kirsher disregarded; acknowledge output is deasserted; all other signals are 4134*adfc5217SJeff Kirsher treated as usual; if 1 - normal activity. */ 4135*adfc5217SJeff Kirsher #define TCM_REG_STORM_TCM_IFEN 0x50010 4136*adfc5217SJeff Kirsher /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for 4137*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 4138*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 4139*adfc5217SJeff Kirsher #define TCM_REG_STORM_WEIGHT 0x500ac 4140*adfc5217SJeff Kirsher /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 4141*adfc5217SJeff Kirsher acknowledge output is deasserted; all other signals are treated as usual; 4142*adfc5217SJeff Kirsher if 1 - normal activity. */ 4143*adfc5217SJeff Kirsher #define TCM_REG_TCM_CFC_IFEN 0x50040 4144*adfc5217SJeff Kirsher /* [RW 11] Interrupt mask register #0 read/write */ 4145*adfc5217SJeff Kirsher #define TCM_REG_TCM_INT_MASK 0x501dc 4146*adfc5217SJeff Kirsher /* [R 11] Interrupt register #0 read */ 4147*adfc5217SJeff Kirsher #define TCM_REG_TCM_INT_STS 0x501d0 4148*adfc5217SJeff Kirsher /* [RW 27] Parity mask register #0 read/write */ 4149*adfc5217SJeff Kirsher #define TCM_REG_TCM_PRTY_MASK 0x501ec 4150*adfc5217SJeff Kirsher /* [R 27] Parity register #0 read */ 4151*adfc5217SJeff Kirsher #define TCM_REG_TCM_PRTY_STS 0x501e0 4152*adfc5217SJeff Kirsher /* [RC 27] Parity register #0 read clear */ 4153*adfc5217SJeff Kirsher #define TCM_REG_TCM_PRTY_STS_CLR 0x501e4 4154*adfc5217SJeff Kirsher /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS 4155*adfc5217SJeff Kirsher REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 4156*adfc5217SJeff Kirsher Is used to determine the number of the AG context REG-pairs written back; 4157*adfc5217SJeff Kirsher when the input message Reg1WbFlg isn't set. */ 4158*adfc5217SJeff Kirsher #define TCM_REG_TCM_REG0_SZ 0x500d8 4159*adfc5217SJeff Kirsher /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 4160*adfc5217SJeff Kirsher disregarded; valid is deasserted; all other signals are treated as usual; 4161*adfc5217SJeff Kirsher if 1 - normal activity. */ 4162*adfc5217SJeff Kirsher #define TCM_REG_TCM_STORM0_IFEN 0x50004 4163*adfc5217SJeff Kirsher /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 4164*adfc5217SJeff Kirsher disregarded; valid is deasserted; all other signals are treated as usual; 4165*adfc5217SJeff Kirsher if 1 - normal activity. */ 4166*adfc5217SJeff Kirsher #define TCM_REG_TCM_STORM1_IFEN 0x50008 4167*adfc5217SJeff Kirsher /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 4168*adfc5217SJeff Kirsher disregarded; valid is deasserted; all other signals are treated as usual; 4169*adfc5217SJeff Kirsher if 1 - normal activity. */ 4170*adfc5217SJeff Kirsher #define TCM_REG_TCM_TQM_IFEN 0x5000c 4171*adfc5217SJeff Kirsher /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */ 4172*adfc5217SJeff Kirsher #define TCM_REG_TCM_TQM_USE_Q 0x500d4 4173*adfc5217SJeff Kirsher /* [RW 28] The CM header for Timers expiration command. */ 4174*adfc5217SJeff Kirsher #define TCM_REG_TM_TCM_HDR 0x50098 4175*adfc5217SJeff Kirsher /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is 4176*adfc5217SJeff Kirsher disregarded; acknowledge output is deasserted; all other signals are 4177*adfc5217SJeff Kirsher treated as usual; if 1 - normal activity. */ 4178*adfc5217SJeff Kirsher #define TCM_REG_TM_TCM_IFEN 0x5001c 4179*adfc5217SJeff Kirsher /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for 4180*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 4181*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 4182*adfc5217SJeff Kirsher #define TCM_REG_TM_WEIGHT 0x500d0 4183*adfc5217SJeff Kirsher /* [RW 6] QM output initial credit. Max credit available - 32.Write writes 4184*adfc5217SJeff Kirsher the initial credit value; read returns the current value of the credit 4185*adfc5217SJeff Kirsher counter. Must be initialized to 32 at start-up. */ 4186*adfc5217SJeff Kirsher #define TCM_REG_TQM_INIT_CRD 0x5021c 4187*adfc5217SJeff Kirsher /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 4188*adfc5217SJeff Kirsher stands for weight 8 (the most prioritised); 1 stands for weight 1(least 4189*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 4190*adfc5217SJeff Kirsher #define TCM_REG_TQM_P_WEIGHT 0x500c8 4191*adfc5217SJeff Kirsher /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 4192*adfc5217SJeff Kirsher stands for weight 8 (the most prioritised); 1 stands for weight 1(least 4193*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 4194*adfc5217SJeff Kirsher #define TCM_REG_TQM_S_WEIGHT 0x500cc 4195*adfc5217SJeff Kirsher /* [RW 28] The CM header value for QM request (primary). */ 4196*adfc5217SJeff Kirsher #define TCM_REG_TQM_TCM_HDR_P 0x50090 4197*adfc5217SJeff Kirsher /* [RW 28] The CM header value for QM request (secondary). */ 4198*adfc5217SJeff Kirsher #define TCM_REG_TQM_TCM_HDR_S 0x50094 4199*adfc5217SJeff Kirsher /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 4200*adfc5217SJeff Kirsher acknowledge output is deasserted; all other signals are treated as usual; 4201*adfc5217SJeff Kirsher if 1 - normal activity. */ 4202*adfc5217SJeff Kirsher #define TCM_REG_TQM_TCM_IFEN 0x50014 4203*adfc5217SJeff Kirsher /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 4204*adfc5217SJeff Kirsher acknowledge output is deasserted; all other signals are treated as usual; 4205*adfc5217SJeff Kirsher if 1 - normal activity. */ 4206*adfc5217SJeff Kirsher #define TCM_REG_TSDM_IFEN 0x50018 4207*adfc5217SJeff Kirsher /* [RC 1] Message length mismatch (relative to last indication) at the SDM 4208*adfc5217SJeff Kirsher interface. */ 4209*adfc5217SJeff Kirsher #define TCM_REG_TSDM_LENGTH_MIS 0x50164 4210*adfc5217SJeff Kirsher /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for 4211*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 4212*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 4213*adfc5217SJeff Kirsher #define TCM_REG_TSDM_WEIGHT 0x500c4 4214*adfc5217SJeff Kirsher /* [RW 1] Input usem Interface enable. If 0 - the valid input is 4215*adfc5217SJeff Kirsher disregarded; acknowledge output is deasserted; all other signals are 4216*adfc5217SJeff Kirsher treated as usual; if 1 - normal activity. */ 4217*adfc5217SJeff Kirsher #define TCM_REG_USEM_IFEN 0x50028 4218*adfc5217SJeff Kirsher /* [RC 1] Message length mismatch (relative to last indication) at the In#8 4219*adfc5217SJeff Kirsher interface. */ 4220*adfc5217SJeff Kirsher #define TCM_REG_USEM_LENGTH_MIS 0x50170 4221*adfc5217SJeff Kirsher /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for 4222*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 4223*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 4224*adfc5217SJeff Kirsher #define TCM_REG_USEM_WEIGHT 0x500b8 4225*adfc5217SJeff Kirsher /* [RW 21] Indirect access to the descriptor table of the XX protection 4226*adfc5217SJeff Kirsher mechanism. The fields are: [5:0] - length of the message; 15:6] - message 4227*adfc5217SJeff Kirsher pointer; 20:16] - next pointer. */ 4228*adfc5217SJeff Kirsher #define TCM_REG_XX_DESCR_TABLE 0x50280 4229*adfc5217SJeff Kirsher #define TCM_REG_XX_DESCR_TABLE_SIZE 29 4230*adfc5217SJeff Kirsher /* [R 6] Use to read the value of XX protection Free counter. */ 4231*adfc5217SJeff Kirsher #define TCM_REG_XX_FREE 0x50178 4232*adfc5217SJeff Kirsher /* [RW 6] Initial value for the credit counter; responsible for fulfilling 4233*adfc5217SJeff Kirsher of the Input Stage XX protection buffer by the XX protection pending 4234*adfc5217SJeff Kirsher messages. Max credit available - 127.Write writes the initial credit 4235*adfc5217SJeff Kirsher value; read returns the current value of the credit counter. Must be 4236*adfc5217SJeff Kirsher initialized to 19 at start-up. */ 4237*adfc5217SJeff Kirsher #define TCM_REG_XX_INIT_CRD 0x50220 4238*adfc5217SJeff Kirsher /* [RW 6] Maximum link list size (messages locked) per connection in the XX 4239*adfc5217SJeff Kirsher protection. */ 4240*adfc5217SJeff Kirsher #define TCM_REG_XX_MAX_LL_SZ 0x50044 4241*adfc5217SJeff Kirsher /* [RW 6] The maximum number of pending messages; which may be stored in XX 4242*adfc5217SJeff Kirsher protection. ~tcm_registers_xx_free.xx_free is read on read. */ 4243*adfc5217SJeff Kirsher #define TCM_REG_XX_MSG_NUM 0x50224 4244*adfc5217SJeff Kirsher /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 4245*adfc5217SJeff Kirsher #define TCM_REG_XX_OVFL_EVNT_ID 0x50048 4246*adfc5217SJeff Kirsher /* [RW 16] Indirect access to the XX table of the XX protection mechanism. 4247*adfc5217SJeff Kirsher The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] - 4248*adfc5217SJeff Kirsher header pointer. */ 4249*adfc5217SJeff Kirsher #define TCM_REG_XX_TABLE 0x50240 4250*adfc5217SJeff Kirsher /* [RW 4] Load value for cfc ac credit cnt. */ 4251*adfc5217SJeff Kirsher #define TM_REG_CFC_AC_CRDCNT_VAL 0x164208 4252*adfc5217SJeff Kirsher /* [RW 4] Load value for cfc cld credit cnt. */ 4253*adfc5217SJeff Kirsher #define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210 4254*adfc5217SJeff Kirsher /* [RW 8] Client0 context region. */ 4255*adfc5217SJeff Kirsher #define TM_REG_CL0_CONT_REGION 0x164030 4256*adfc5217SJeff Kirsher /* [RW 8] Client1 context region. */ 4257*adfc5217SJeff Kirsher #define TM_REG_CL1_CONT_REGION 0x164034 4258*adfc5217SJeff Kirsher /* [RW 8] Client2 context region. */ 4259*adfc5217SJeff Kirsher #define TM_REG_CL2_CONT_REGION 0x164038 4260*adfc5217SJeff Kirsher /* [RW 2] Client in High priority client number. */ 4261*adfc5217SJeff Kirsher #define TM_REG_CLIN_PRIOR0_CLIENT 0x164024 4262*adfc5217SJeff Kirsher /* [RW 4] Load value for clout0 cred cnt. */ 4263*adfc5217SJeff Kirsher #define TM_REG_CLOUT_CRDCNT0_VAL 0x164220 4264*adfc5217SJeff Kirsher /* [RW 4] Load value for clout1 cred cnt. */ 4265*adfc5217SJeff Kirsher #define TM_REG_CLOUT_CRDCNT1_VAL 0x164228 4266*adfc5217SJeff Kirsher /* [RW 4] Load value for clout2 cred cnt. */ 4267*adfc5217SJeff Kirsher #define TM_REG_CLOUT_CRDCNT2_VAL 0x164230 4268*adfc5217SJeff Kirsher /* [RW 1] Enable client0 input. */ 4269*adfc5217SJeff Kirsher #define TM_REG_EN_CL0_INPUT 0x164008 4270*adfc5217SJeff Kirsher /* [RW 1] Enable client1 input. */ 4271*adfc5217SJeff Kirsher #define TM_REG_EN_CL1_INPUT 0x16400c 4272*adfc5217SJeff Kirsher /* [RW 1] Enable client2 input. */ 4273*adfc5217SJeff Kirsher #define TM_REG_EN_CL2_INPUT 0x164010 4274*adfc5217SJeff Kirsher #define TM_REG_EN_LINEAR0_TIMER 0x164014 4275*adfc5217SJeff Kirsher /* [RW 1] Enable real time counter. */ 4276*adfc5217SJeff Kirsher #define TM_REG_EN_REAL_TIME_CNT 0x1640d8 4277*adfc5217SJeff Kirsher /* [RW 1] Enable for Timers state machines. */ 4278*adfc5217SJeff Kirsher #define TM_REG_EN_TIMERS 0x164000 4279*adfc5217SJeff Kirsher /* [RW 4] Load value for expiration credit cnt. CFC max number of 4280*adfc5217SJeff Kirsher outstanding load requests for timers (expiration) context loading. */ 4281*adfc5217SJeff Kirsher #define TM_REG_EXP_CRDCNT_VAL 0x164238 4282*adfc5217SJeff Kirsher /* [RW 32] Linear0 logic address. */ 4283*adfc5217SJeff Kirsher #define TM_REG_LIN0_LOGIC_ADDR 0x164240 4284*adfc5217SJeff Kirsher /* [RW 18] Linear0 Max active cid (in banks of 32 entries). */ 4285*adfc5217SJeff Kirsher #define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048 4286*adfc5217SJeff Kirsher /* [ST 16] Linear0 Number of scans counter. */ 4287*adfc5217SJeff Kirsher #define TM_REG_LIN0_NUM_SCANS 0x1640a0 4288*adfc5217SJeff Kirsher /* [WB 64] Linear0 phy address. */ 4289*adfc5217SJeff Kirsher #define TM_REG_LIN0_PHY_ADDR 0x164270 4290*adfc5217SJeff Kirsher /* [RW 1] Linear0 physical address valid. */ 4291*adfc5217SJeff Kirsher #define TM_REG_LIN0_PHY_ADDR_VALID 0x164248 4292*adfc5217SJeff Kirsher #define TM_REG_LIN0_SCAN_ON 0x1640d0 4293*adfc5217SJeff Kirsher /* [RW 24] Linear0 array scan timeout. */ 4294*adfc5217SJeff Kirsher #define TM_REG_LIN0_SCAN_TIME 0x16403c 4295*adfc5217SJeff Kirsher #define TM_REG_LIN0_VNIC_UC 0x164128 4296*adfc5217SJeff Kirsher /* [RW 32] Linear1 logic address. */ 4297*adfc5217SJeff Kirsher #define TM_REG_LIN1_LOGIC_ADDR 0x164250 4298*adfc5217SJeff Kirsher /* [WB 64] Linear1 phy address. */ 4299*adfc5217SJeff Kirsher #define TM_REG_LIN1_PHY_ADDR 0x164280 4300*adfc5217SJeff Kirsher /* [RW 1] Linear1 physical address valid. */ 4301*adfc5217SJeff Kirsher #define TM_REG_LIN1_PHY_ADDR_VALID 0x164258 4302*adfc5217SJeff Kirsher /* [RW 6] Linear timer set_clear fifo threshold. */ 4303*adfc5217SJeff Kirsher #define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070 4304*adfc5217SJeff Kirsher /* [RW 2] Load value for pci arbiter credit cnt. */ 4305*adfc5217SJeff Kirsher #define TM_REG_PCIARB_CRDCNT_VAL 0x164260 4306*adfc5217SJeff Kirsher /* [RW 20] The amount of hardware cycles for each timer tick. */ 4307*adfc5217SJeff Kirsher #define TM_REG_TIMER_TICK_SIZE 0x16401c 4308*adfc5217SJeff Kirsher /* [RW 8] Timers Context region. */ 4309*adfc5217SJeff Kirsher #define TM_REG_TM_CONTEXT_REGION 0x164044 4310*adfc5217SJeff Kirsher /* [RW 1] Interrupt mask register #0 read/write */ 4311*adfc5217SJeff Kirsher #define TM_REG_TM_INT_MASK 0x1640fc 4312*adfc5217SJeff Kirsher /* [R 1] Interrupt register #0 read */ 4313*adfc5217SJeff Kirsher #define TM_REG_TM_INT_STS 0x1640f0 4314*adfc5217SJeff Kirsher /* [RW 7] Parity mask register #0 read/write */ 4315*adfc5217SJeff Kirsher #define TM_REG_TM_PRTY_MASK 0x16410c 4316*adfc5217SJeff Kirsher /* [RC 7] Parity register #0 read clear */ 4317*adfc5217SJeff Kirsher #define TM_REG_TM_PRTY_STS_CLR 0x164104 4318*adfc5217SJeff Kirsher /* [RW 8] The event id for aggregated interrupt 0 */ 4319*adfc5217SJeff Kirsher #define TSDM_REG_AGG_INT_EVENT_0 0x42038 4320*adfc5217SJeff Kirsher #define TSDM_REG_AGG_INT_EVENT_1 0x4203c 4321*adfc5217SJeff Kirsher #define TSDM_REG_AGG_INT_EVENT_2 0x42040 4322*adfc5217SJeff Kirsher #define TSDM_REG_AGG_INT_EVENT_3 0x42044 4323*adfc5217SJeff Kirsher #define TSDM_REG_AGG_INT_EVENT_4 0x42048 4324*adfc5217SJeff Kirsher /* [RW 1] The T bit for aggregated interrupt 0 */ 4325*adfc5217SJeff Kirsher #define TSDM_REG_AGG_INT_T_0 0x420b8 4326*adfc5217SJeff Kirsher #define TSDM_REG_AGG_INT_T_1 0x420bc 4327*adfc5217SJeff Kirsher /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 4328*adfc5217SJeff Kirsher #define TSDM_REG_CFC_RSP_START_ADDR 0x42008 4329*adfc5217SJeff Kirsher /* [RW 16] The maximum value of the completion counter #0 */ 4330*adfc5217SJeff Kirsher #define TSDM_REG_CMP_COUNTER_MAX0 0x4201c 4331*adfc5217SJeff Kirsher /* [RW 16] The maximum value of the completion counter #1 */ 4332*adfc5217SJeff Kirsher #define TSDM_REG_CMP_COUNTER_MAX1 0x42020 4333*adfc5217SJeff Kirsher /* [RW 16] The maximum value of the completion counter #2 */ 4334*adfc5217SJeff Kirsher #define TSDM_REG_CMP_COUNTER_MAX2 0x42024 4335*adfc5217SJeff Kirsher /* [RW 16] The maximum value of the completion counter #3 */ 4336*adfc5217SJeff Kirsher #define TSDM_REG_CMP_COUNTER_MAX3 0x42028 4337*adfc5217SJeff Kirsher /* [RW 13] The start address in the internal RAM for the completion 4338*adfc5217SJeff Kirsher counters. */ 4339*adfc5217SJeff Kirsher #define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c 4340*adfc5217SJeff Kirsher #define TSDM_REG_ENABLE_IN1 0x42238 4341*adfc5217SJeff Kirsher #define TSDM_REG_ENABLE_IN2 0x4223c 4342*adfc5217SJeff Kirsher #define TSDM_REG_ENABLE_OUT1 0x42240 4343*adfc5217SJeff Kirsher #define TSDM_REG_ENABLE_OUT2 0x42244 4344*adfc5217SJeff Kirsher /* [RW 4] The initial number of messages that can be sent to the pxp control 4345*adfc5217SJeff Kirsher interface without receiving any ACK. */ 4346*adfc5217SJeff Kirsher #define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc 4347*adfc5217SJeff Kirsher /* [ST 32] The number of ACK after placement messages received */ 4348*adfc5217SJeff Kirsher #define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c 4349*adfc5217SJeff Kirsher /* [ST 32] The number of packet end messages received from the parser */ 4350*adfc5217SJeff Kirsher #define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274 4351*adfc5217SJeff Kirsher /* [ST 32] The number of requests received from the pxp async if */ 4352*adfc5217SJeff Kirsher #define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278 4353*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 0 */ 4354*adfc5217SJeff Kirsher #define TSDM_REG_NUM_OF_Q0_CMD 0x42248 4355*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 10 */ 4356*adfc5217SJeff Kirsher #define TSDM_REG_NUM_OF_Q10_CMD 0x4226c 4357*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 11 */ 4358*adfc5217SJeff Kirsher #define TSDM_REG_NUM_OF_Q11_CMD 0x42270 4359*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 1 */ 4360*adfc5217SJeff Kirsher #define TSDM_REG_NUM_OF_Q1_CMD 0x4224c 4361*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 3 */ 4362*adfc5217SJeff Kirsher #define TSDM_REG_NUM_OF_Q3_CMD 0x42250 4363*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 4 */ 4364*adfc5217SJeff Kirsher #define TSDM_REG_NUM_OF_Q4_CMD 0x42254 4365*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 5 */ 4366*adfc5217SJeff Kirsher #define TSDM_REG_NUM_OF_Q5_CMD 0x42258 4367*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 6 */ 4368*adfc5217SJeff Kirsher #define TSDM_REG_NUM_OF_Q6_CMD 0x4225c 4369*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 7 */ 4370*adfc5217SJeff Kirsher #define TSDM_REG_NUM_OF_Q7_CMD 0x42260 4371*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 8 */ 4372*adfc5217SJeff Kirsher #define TSDM_REG_NUM_OF_Q8_CMD 0x42264 4373*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 9 */ 4374*adfc5217SJeff Kirsher #define TSDM_REG_NUM_OF_Q9_CMD 0x42268 4375*adfc5217SJeff Kirsher /* [RW 13] The start address in the internal RAM for the packet end message */ 4376*adfc5217SJeff Kirsher #define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014 4377*adfc5217SJeff Kirsher /* [RW 13] The start address in the internal RAM for queue counters */ 4378*adfc5217SJeff Kirsher #define TSDM_REG_Q_COUNTER_START_ADDR 0x42010 4379*adfc5217SJeff Kirsher /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 4380*adfc5217SJeff Kirsher #define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548 4381*adfc5217SJeff Kirsher /* [R 1] parser fifo empty in sdm_sync block */ 4382*adfc5217SJeff Kirsher #define TSDM_REG_SYNC_PARSER_EMPTY 0x42550 4383*adfc5217SJeff Kirsher /* [R 1] parser serial fifo empty in sdm_sync block */ 4384*adfc5217SJeff Kirsher #define TSDM_REG_SYNC_SYNC_EMPTY 0x42558 4385*adfc5217SJeff Kirsher /* [RW 32] Tick for timer counter. Applicable only when 4386*adfc5217SJeff Kirsher ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */ 4387*adfc5217SJeff Kirsher #define TSDM_REG_TIMER_TICK 0x42000 4388*adfc5217SJeff Kirsher /* [RW 32] Interrupt mask register #0 read/write */ 4389*adfc5217SJeff Kirsher #define TSDM_REG_TSDM_INT_MASK_0 0x4229c 4390*adfc5217SJeff Kirsher #define TSDM_REG_TSDM_INT_MASK_1 0x422ac 4391*adfc5217SJeff Kirsher /* [R 32] Interrupt register #0 read */ 4392*adfc5217SJeff Kirsher #define TSDM_REG_TSDM_INT_STS_0 0x42290 4393*adfc5217SJeff Kirsher #define TSDM_REG_TSDM_INT_STS_1 0x422a0 4394*adfc5217SJeff Kirsher /* [RW 11] Parity mask register #0 read/write */ 4395*adfc5217SJeff Kirsher #define TSDM_REG_TSDM_PRTY_MASK 0x422bc 4396*adfc5217SJeff Kirsher /* [R 11] Parity register #0 read */ 4397*adfc5217SJeff Kirsher #define TSDM_REG_TSDM_PRTY_STS 0x422b0 4398*adfc5217SJeff Kirsher /* [RC 11] Parity register #0 read clear */ 4399*adfc5217SJeff Kirsher #define TSDM_REG_TSDM_PRTY_STS_CLR 0x422b4 4400*adfc5217SJeff Kirsher /* [RW 5] The number of time_slots in the arbitration cycle */ 4401*adfc5217SJeff Kirsher #define TSEM_REG_ARB_CYCLE_SIZE 0x180034 4402*adfc5217SJeff Kirsher /* [RW 3] The source that is associated with arbitration element 0. Source 4403*adfc5217SJeff Kirsher decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4404*adfc5217SJeff Kirsher sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 4405*adfc5217SJeff Kirsher #define TSEM_REG_ARB_ELEMENT0 0x180020 4406*adfc5217SJeff Kirsher /* [RW 3] The source that is associated with arbitration element 1. Source 4407*adfc5217SJeff Kirsher decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4408*adfc5217SJeff Kirsher sleeping thread with priority 1; 4- sleeping thread with priority 2. 4409*adfc5217SJeff Kirsher Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */ 4410*adfc5217SJeff Kirsher #define TSEM_REG_ARB_ELEMENT1 0x180024 4411*adfc5217SJeff Kirsher /* [RW 3] The source that is associated with arbitration element 2. Source 4412*adfc5217SJeff Kirsher decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4413*adfc5217SJeff Kirsher sleeping thread with priority 1; 4- sleeping thread with priority 2. 4414*adfc5217SJeff Kirsher Could not be equal to register ~tsem_registers_arb_element0.arb_element0 4415*adfc5217SJeff Kirsher and ~tsem_registers_arb_element1.arb_element1 */ 4416*adfc5217SJeff Kirsher #define TSEM_REG_ARB_ELEMENT2 0x180028 4417*adfc5217SJeff Kirsher /* [RW 3] The source that is associated with arbitration element 3. Source 4418*adfc5217SJeff Kirsher decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4419*adfc5217SJeff Kirsher sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 4420*adfc5217SJeff Kirsher not be equal to register ~tsem_registers_arb_element0.arb_element0 and 4421*adfc5217SJeff Kirsher ~tsem_registers_arb_element1.arb_element1 and 4422*adfc5217SJeff Kirsher ~tsem_registers_arb_element2.arb_element2 */ 4423*adfc5217SJeff Kirsher #define TSEM_REG_ARB_ELEMENT3 0x18002c 4424*adfc5217SJeff Kirsher /* [RW 3] The source that is associated with arbitration element 4. Source 4425*adfc5217SJeff Kirsher decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4426*adfc5217SJeff Kirsher sleeping thread with priority 1; 4- sleeping thread with priority 2. 4427*adfc5217SJeff Kirsher Could not be equal to register ~tsem_registers_arb_element0.arb_element0 4428*adfc5217SJeff Kirsher and ~tsem_registers_arb_element1.arb_element1 and 4429*adfc5217SJeff Kirsher ~tsem_registers_arb_element2.arb_element2 and 4430*adfc5217SJeff Kirsher ~tsem_registers_arb_element3.arb_element3 */ 4431*adfc5217SJeff Kirsher #define TSEM_REG_ARB_ELEMENT4 0x180030 4432*adfc5217SJeff Kirsher #define TSEM_REG_ENABLE_IN 0x1800a4 4433*adfc5217SJeff Kirsher #define TSEM_REG_ENABLE_OUT 0x1800a8 4434*adfc5217SJeff Kirsher /* [RW 32] This address space contains all registers and memories that are 4435*adfc5217SJeff Kirsher placed in SEM_FAST block. The SEM_FAST registers are described in 4436*adfc5217SJeff Kirsher appendix B. In order to access the sem_fast registers the base address 4437*adfc5217SJeff Kirsher ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 4438*adfc5217SJeff Kirsher #define TSEM_REG_FAST_MEMORY 0x1a0000 4439*adfc5217SJeff Kirsher /* [RW 1] Disables input messages from FIC0 May be updated during run_time 4440*adfc5217SJeff Kirsher by the microcode */ 4441*adfc5217SJeff Kirsher #define TSEM_REG_FIC0_DISABLE 0x180224 4442*adfc5217SJeff Kirsher /* [RW 1] Disables input messages from FIC1 May be updated during run_time 4443*adfc5217SJeff Kirsher by the microcode */ 4444*adfc5217SJeff Kirsher #define TSEM_REG_FIC1_DISABLE 0x180234 4445*adfc5217SJeff Kirsher /* [RW 15] Interrupt table Read and write access to it is not possible in 4446*adfc5217SJeff Kirsher the middle of the work */ 4447*adfc5217SJeff Kirsher #define TSEM_REG_INT_TABLE 0x180400 4448*adfc5217SJeff Kirsher /* [ST 24] Statistics register. The number of messages that entered through 4449*adfc5217SJeff Kirsher FIC0 */ 4450*adfc5217SJeff Kirsher #define TSEM_REG_MSG_NUM_FIC0 0x180000 4451*adfc5217SJeff Kirsher /* [ST 24] Statistics register. The number of messages that entered through 4452*adfc5217SJeff Kirsher FIC1 */ 4453*adfc5217SJeff Kirsher #define TSEM_REG_MSG_NUM_FIC1 0x180004 4454*adfc5217SJeff Kirsher /* [ST 24] Statistics register. The number of messages that were sent to 4455*adfc5217SJeff Kirsher FOC0 */ 4456*adfc5217SJeff Kirsher #define TSEM_REG_MSG_NUM_FOC0 0x180008 4457*adfc5217SJeff Kirsher /* [ST 24] Statistics register. The number of messages that were sent to 4458*adfc5217SJeff Kirsher FOC1 */ 4459*adfc5217SJeff Kirsher #define TSEM_REG_MSG_NUM_FOC1 0x18000c 4460*adfc5217SJeff Kirsher /* [ST 24] Statistics register. The number of messages that were sent to 4461*adfc5217SJeff Kirsher FOC2 */ 4462*adfc5217SJeff Kirsher #define TSEM_REG_MSG_NUM_FOC2 0x180010 4463*adfc5217SJeff Kirsher /* [ST 24] Statistics register. The number of messages that were sent to 4464*adfc5217SJeff Kirsher FOC3 */ 4465*adfc5217SJeff Kirsher #define TSEM_REG_MSG_NUM_FOC3 0x180014 4466*adfc5217SJeff Kirsher /* [RW 1] Disables input messages from the passive buffer May be updated 4467*adfc5217SJeff Kirsher during run_time by the microcode */ 4468*adfc5217SJeff Kirsher #define TSEM_REG_PAS_DISABLE 0x18024c 4469*adfc5217SJeff Kirsher /* [WB 128] Debug only. Passive buffer memory */ 4470*adfc5217SJeff Kirsher #define TSEM_REG_PASSIVE_BUFFER 0x181000 4471*adfc5217SJeff Kirsher /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 4472*adfc5217SJeff Kirsher #define TSEM_REG_PRAM 0x1c0000 4473*adfc5217SJeff Kirsher /* [R 8] Valid sleeping threads indication have bit per thread */ 4474*adfc5217SJeff Kirsher #define TSEM_REG_SLEEP_THREADS_VALID 0x18026c 4475*adfc5217SJeff Kirsher /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 4476*adfc5217SJeff Kirsher #define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0 4477*adfc5217SJeff Kirsher /* [RW 8] List of free threads . There is a bit per thread. */ 4478*adfc5217SJeff Kirsher #define TSEM_REG_THREADS_LIST 0x1802e4 4479*adfc5217SJeff Kirsher /* [RC 32] Parity register #0 read clear */ 4480*adfc5217SJeff Kirsher #define TSEM_REG_TSEM_PRTY_STS_CLR_0 0x180118 4481*adfc5217SJeff Kirsher #define TSEM_REG_TSEM_PRTY_STS_CLR_1 0x180128 4482*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 0 */ 4483*adfc5217SJeff Kirsher #define TSEM_REG_TS_0_AS 0x180038 4484*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 10 */ 4485*adfc5217SJeff Kirsher #define TSEM_REG_TS_10_AS 0x180060 4486*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 11 */ 4487*adfc5217SJeff Kirsher #define TSEM_REG_TS_11_AS 0x180064 4488*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 12 */ 4489*adfc5217SJeff Kirsher #define TSEM_REG_TS_12_AS 0x180068 4490*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 13 */ 4491*adfc5217SJeff Kirsher #define TSEM_REG_TS_13_AS 0x18006c 4492*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 14 */ 4493*adfc5217SJeff Kirsher #define TSEM_REG_TS_14_AS 0x180070 4494*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 15 */ 4495*adfc5217SJeff Kirsher #define TSEM_REG_TS_15_AS 0x180074 4496*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 16 */ 4497*adfc5217SJeff Kirsher #define TSEM_REG_TS_16_AS 0x180078 4498*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 17 */ 4499*adfc5217SJeff Kirsher #define TSEM_REG_TS_17_AS 0x18007c 4500*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 18 */ 4501*adfc5217SJeff Kirsher #define TSEM_REG_TS_18_AS 0x180080 4502*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 1 */ 4503*adfc5217SJeff Kirsher #define TSEM_REG_TS_1_AS 0x18003c 4504*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 2 */ 4505*adfc5217SJeff Kirsher #define TSEM_REG_TS_2_AS 0x180040 4506*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 3 */ 4507*adfc5217SJeff Kirsher #define TSEM_REG_TS_3_AS 0x180044 4508*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 4 */ 4509*adfc5217SJeff Kirsher #define TSEM_REG_TS_4_AS 0x180048 4510*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 5 */ 4511*adfc5217SJeff Kirsher #define TSEM_REG_TS_5_AS 0x18004c 4512*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 6 */ 4513*adfc5217SJeff Kirsher #define TSEM_REG_TS_6_AS 0x180050 4514*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 7 */ 4515*adfc5217SJeff Kirsher #define TSEM_REG_TS_7_AS 0x180054 4516*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 8 */ 4517*adfc5217SJeff Kirsher #define TSEM_REG_TS_8_AS 0x180058 4518*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 9 */ 4519*adfc5217SJeff Kirsher #define TSEM_REG_TS_9_AS 0x18005c 4520*adfc5217SJeff Kirsher /* [RW 32] Interrupt mask register #0 read/write */ 4521*adfc5217SJeff Kirsher #define TSEM_REG_TSEM_INT_MASK_0 0x180100 4522*adfc5217SJeff Kirsher #define TSEM_REG_TSEM_INT_MASK_1 0x180110 4523*adfc5217SJeff Kirsher /* [R 32] Interrupt register #0 read */ 4524*adfc5217SJeff Kirsher #define TSEM_REG_TSEM_INT_STS_0 0x1800f4 4525*adfc5217SJeff Kirsher #define TSEM_REG_TSEM_INT_STS_1 0x180104 4526*adfc5217SJeff Kirsher /* [RW 32] Parity mask register #0 read/write */ 4527*adfc5217SJeff Kirsher #define TSEM_REG_TSEM_PRTY_MASK_0 0x180120 4528*adfc5217SJeff Kirsher #define TSEM_REG_TSEM_PRTY_MASK_1 0x180130 4529*adfc5217SJeff Kirsher /* [R 32] Parity register #0 read */ 4530*adfc5217SJeff Kirsher #define TSEM_REG_TSEM_PRTY_STS_0 0x180114 4531*adfc5217SJeff Kirsher #define TSEM_REG_TSEM_PRTY_STS_1 0x180124 4532*adfc5217SJeff Kirsher /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 4533*adfc5217SJeff Kirsher * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ 4534*adfc5217SJeff Kirsher #define TSEM_REG_VFPF_ERR_NUM 0x180380 4535*adfc5217SJeff Kirsher /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits 4536*adfc5217SJeff Kirsher * [10:8] of the address should be the offset within the accessed LCID 4537*adfc5217SJeff Kirsher * context; the bits [7:0] are the accessed LCID.Example: to write to REG10 4538*adfc5217SJeff Kirsher * LCID100. The RBC address should be 12'ha64. */ 4539*adfc5217SJeff Kirsher #define UCM_REG_AG_CTX 0xe2000 4540*adfc5217SJeff Kirsher /* [R 5] Used to read the XX protection CAM occupancy counter. */ 4541*adfc5217SJeff Kirsher #define UCM_REG_CAM_OCCUP 0xe0170 4542*adfc5217SJeff Kirsher /* [RW 1] CDU AG read Interface enable. If 0 - the request input is 4543*adfc5217SJeff Kirsher disregarded; valid output is deasserted; all other signals are treated as 4544*adfc5217SJeff Kirsher usual; if 1 - normal activity. */ 4545*adfc5217SJeff Kirsher #define UCM_REG_CDU_AG_RD_IFEN 0xe0038 4546*adfc5217SJeff Kirsher /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 4547*adfc5217SJeff Kirsher are disregarded; all other signals are treated as usual; if 1 - normal 4548*adfc5217SJeff Kirsher activity. */ 4549*adfc5217SJeff Kirsher #define UCM_REG_CDU_AG_WR_IFEN 0xe0034 4550*adfc5217SJeff Kirsher /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 4551*adfc5217SJeff Kirsher disregarded; valid output is deasserted; all other signals are treated as 4552*adfc5217SJeff Kirsher usual; if 1 - normal activity. */ 4553*adfc5217SJeff Kirsher #define UCM_REG_CDU_SM_RD_IFEN 0xe0040 4554*adfc5217SJeff Kirsher /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 4555*adfc5217SJeff Kirsher input is disregarded; all other signals are treated as usual; if 1 - 4556*adfc5217SJeff Kirsher normal activity. */ 4557*adfc5217SJeff Kirsher #define UCM_REG_CDU_SM_WR_IFEN 0xe003c 4558*adfc5217SJeff Kirsher /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 4559*adfc5217SJeff Kirsher the initial credit value; read returns the current value of the credit 4560*adfc5217SJeff Kirsher counter. Must be initialized to 1 at start-up. */ 4561*adfc5217SJeff Kirsher #define UCM_REG_CFC_INIT_CRD 0xe0204 4562*adfc5217SJeff Kirsher /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for 4563*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 4564*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 4565*adfc5217SJeff Kirsher #define UCM_REG_CP_WEIGHT 0xe00c4 4566*adfc5217SJeff Kirsher /* [RW 1] Input csem Interface enable. If 0 - the valid input is 4567*adfc5217SJeff Kirsher disregarded; acknowledge output is deasserted; all other signals are 4568*adfc5217SJeff Kirsher treated as usual; if 1 - normal activity. */ 4569*adfc5217SJeff Kirsher #define UCM_REG_CSEM_IFEN 0xe0028 4570*adfc5217SJeff Kirsher /* [RC 1] Set when the message length mismatch (relative to last indication) 4571*adfc5217SJeff Kirsher at the csem interface is detected. */ 4572*adfc5217SJeff Kirsher #define UCM_REG_CSEM_LENGTH_MIS 0xe0160 4573*adfc5217SJeff Kirsher /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for 4574*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 4575*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 4576*adfc5217SJeff Kirsher #define UCM_REG_CSEM_WEIGHT 0xe00b8 4577*adfc5217SJeff Kirsher /* [RW 1] Input dorq Interface enable. If 0 - the valid input is 4578*adfc5217SJeff Kirsher disregarded; acknowledge output is deasserted; all other signals are 4579*adfc5217SJeff Kirsher treated as usual; if 1 - normal activity. */ 4580*adfc5217SJeff Kirsher #define UCM_REG_DORQ_IFEN 0xe0030 4581*adfc5217SJeff Kirsher /* [RC 1] Set when the message length mismatch (relative to last indication) 4582*adfc5217SJeff Kirsher at the dorq interface is detected. */ 4583*adfc5217SJeff Kirsher #define UCM_REG_DORQ_LENGTH_MIS 0xe0168 4584*adfc5217SJeff Kirsher /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for 4585*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 4586*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 4587*adfc5217SJeff Kirsher #define UCM_REG_DORQ_WEIGHT 0xe00c0 4588*adfc5217SJeff Kirsher /* [RW 8] The Event ID in case ErrorFlg input message bit is set. */ 4589*adfc5217SJeff Kirsher #define UCM_REG_ERR_EVNT_ID 0xe00a4 4590*adfc5217SJeff Kirsher /* [RW 28] The CM erroneous header for QM and Timers formatting. */ 4591*adfc5217SJeff Kirsher #define UCM_REG_ERR_UCM_HDR 0xe00a0 4592*adfc5217SJeff Kirsher /* [RW 8] The Event ID for Timers expiration. */ 4593*adfc5217SJeff Kirsher #define UCM_REG_EXPR_EVNT_ID 0xe00a8 4594*adfc5217SJeff Kirsher /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write 4595*adfc5217SJeff Kirsher writes the initial credit value; read returns the current value of the 4596*adfc5217SJeff Kirsher credit counter. Must be initialized to 64 at start-up. */ 4597*adfc5217SJeff Kirsher #define UCM_REG_FIC0_INIT_CRD 0xe020c 4598*adfc5217SJeff Kirsher /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 4599*adfc5217SJeff Kirsher writes the initial credit value; read returns the current value of the 4600*adfc5217SJeff Kirsher credit counter. Must be initialized to 64 at start-up. */ 4601*adfc5217SJeff Kirsher #define UCM_REG_FIC1_INIT_CRD 0xe0210 4602*adfc5217SJeff Kirsher /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 4603*adfc5217SJeff Kirsher - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr; 4604*adfc5217SJeff Kirsher ~ucm_registers_gr_ld0_pr.gr_ld0_pr and 4605*adfc5217SJeff Kirsher ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */ 4606*adfc5217SJeff Kirsher #define UCM_REG_GR_ARB_TYPE 0xe0144 4607*adfc5217SJeff Kirsher /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 4608*adfc5217SJeff Kirsher highest priority is 3. It is supposed that the Store channel group is 4609*adfc5217SJeff Kirsher compliment to the others. */ 4610*adfc5217SJeff Kirsher #define UCM_REG_GR_LD0_PR 0xe014c 4611*adfc5217SJeff Kirsher /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 4612*adfc5217SJeff Kirsher highest priority is 3. It is supposed that the Store channel group is 4613*adfc5217SJeff Kirsher compliment to the others. */ 4614*adfc5217SJeff Kirsher #define UCM_REG_GR_LD1_PR 0xe0150 4615*adfc5217SJeff Kirsher /* [RW 2] The queue index for invalidate counter flag decision. */ 4616*adfc5217SJeff Kirsher #define UCM_REG_INV_CFLG_Q 0xe00e4 4617*adfc5217SJeff Kirsher /* [RW 5] The number of double REG-pairs; loaded from the STORM context and 4618*adfc5217SJeff Kirsher sent to STORM; for a specific connection type. the double REG-pairs are 4619*adfc5217SJeff Kirsher used in order to align to STORM context row size of 128 bits. The offset 4620*adfc5217SJeff Kirsher of these data in the STORM context is always 0. Index _i stands for the 4621*adfc5217SJeff Kirsher connection type (one of 16). */ 4622*adfc5217SJeff Kirsher #define UCM_REG_N_SM_CTX_LD_0 0xe0054 4623*adfc5217SJeff Kirsher #define UCM_REG_N_SM_CTX_LD_1 0xe0058 4624*adfc5217SJeff Kirsher #define UCM_REG_N_SM_CTX_LD_2 0xe005c 4625*adfc5217SJeff Kirsher #define UCM_REG_N_SM_CTX_LD_3 0xe0060 4626*adfc5217SJeff Kirsher #define UCM_REG_N_SM_CTX_LD_4 0xe0064 4627*adfc5217SJeff Kirsher #define UCM_REG_N_SM_CTX_LD_5 0xe0068 4628*adfc5217SJeff Kirsher #define UCM_REG_PHYS_QNUM0_0 0xe0110 4629*adfc5217SJeff Kirsher #define UCM_REG_PHYS_QNUM0_1 0xe0114 4630*adfc5217SJeff Kirsher #define UCM_REG_PHYS_QNUM1_0 0xe0118 4631*adfc5217SJeff Kirsher #define UCM_REG_PHYS_QNUM1_1 0xe011c 4632*adfc5217SJeff Kirsher #define UCM_REG_PHYS_QNUM2_0 0xe0120 4633*adfc5217SJeff Kirsher #define UCM_REG_PHYS_QNUM2_1 0xe0124 4634*adfc5217SJeff Kirsher #define UCM_REG_PHYS_QNUM3_0 0xe0128 4635*adfc5217SJeff Kirsher #define UCM_REG_PHYS_QNUM3_1 0xe012c 4636*adfc5217SJeff Kirsher /* [RW 8] The Event ID for Timers formatting in case of stop done. */ 4637*adfc5217SJeff Kirsher #define UCM_REG_STOP_EVNT_ID 0xe00ac 4638*adfc5217SJeff Kirsher /* [RC 1] Set when the message length mismatch (relative to last indication) 4639*adfc5217SJeff Kirsher at the STORM interface is detected. */ 4640*adfc5217SJeff Kirsher #define UCM_REG_STORM_LENGTH_MIS 0xe0154 4641*adfc5217SJeff Kirsher /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 4642*adfc5217SJeff Kirsher disregarded; acknowledge output is deasserted; all other signals are 4643*adfc5217SJeff Kirsher treated as usual; if 1 - normal activity. */ 4644*adfc5217SJeff Kirsher #define UCM_REG_STORM_UCM_IFEN 0xe0010 4645*adfc5217SJeff Kirsher /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for 4646*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 4647*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 4648*adfc5217SJeff Kirsher #define UCM_REG_STORM_WEIGHT 0xe00b0 4649*adfc5217SJeff Kirsher /* [RW 4] Timers output initial credit. Max credit available - 15.Write 4650*adfc5217SJeff Kirsher writes the initial credit value; read returns the current value of the 4651*adfc5217SJeff Kirsher credit counter. Must be initialized to 4 at start-up. */ 4652*adfc5217SJeff Kirsher #define UCM_REG_TM_INIT_CRD 0xe021c 4653*adfc5217SJeff Kirsher /* [RW 28] The CM header for Timers expiration command. */ 4654*adfc5217SJeff Kirsher #define UCM_REG_TM_UCM_HDR 0xe009c 4655*adfc5217SJeff Kirsher /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is 4656*adfc5217SJeff Kirsher disregarded; acknowledge output is deasserted; all other signals are 4657*adfc5217SJeff Kirsher treated as usual; if 1 - normal activity. */ 4658*adfc5217SJeff Kirsher #define UCM_REG_TM_UCM_IFEN 0xe001c 4659*adfc5217SJeff Kirsher /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for 4660*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 4661*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 4662*adfc5217SJeff Kirsher #define UCM_REG_TM_WEIGHT 0xe00d4 4663*adfc5217SJeff Kirsher /* [RW 1] Input tsem Interface enable. If 0 - the valid input is 4664*adfc5217SJeff Kirsher disregarded; acknowledge output is deasserted; all other signals are 4665*adfc5217SJeff Kirsher treated as usual; if 1 - normal activity. */ 4666*adfc5217SJeff Kirsher #define UCM_REG_TSEM_IFEN 0xe0024 4667*adfc5217SJeff Kirsher /* [RC 1] Set when the message length mismatch (relative to last indication) 4668*adfc5217SJeff Kirsher at the tsem interface is detected. */ 4669*adfc5217SJeff Kirsher #define UCM_REG_TSEM_LENGTH_MIS 0xe015c 4670*adfc5217SJeff Kirsher /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for 4671*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 4672*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 4673*adfc5217SJeff Kirsher #define UCM_REG_TSEM_WEIGHT 0xe00b4 4674*adfc5217SJeff Kirsher /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 4675*adfc5217SJeff Kirsher acknowledge output is deasserted; all other signals are treated as usual; 4676*adfc5217SJeff Kirsher if 1 - normal activity. */ 4677*adfc5217SJeff Kirsher #define UCM_REG_UCM_CFC_IFEN 0xe0044 4678*adfc5217SJeff Kirsher /* [RW 11] Interrupt mask register #0 read/write */ 4679*adfc5217SJeff Kirsher #define UCM_REG_UCM_INT_MASK 0xe01d4 4680*adfc5217SJeff Kirsher /* [R 11] Interrupt register #0 read */ 4681*adfc5217SJeff Kirsher #define UCM_REG_UCM_INT_STS 0xe01c8 4682*adfc5217SJeff Kirsher /* [RW 27] Parity mask register #0 read/write */ 4683*adfc5217SJeff Kirsher #define UCM_REG_UCM_PRTY_MASK 0xe01e4 4684*adfc5217SJeff Kirsher /* [R 27] Parity register #0 read */ 4685*adfc5217SJeff Kirsher #define UCM_REG_UCM_PRTY_STS 0xe01d8 4686*adfc5217SJeff Kirsher /* [RC 27] Parity register #0 read clear */ 4687*adfc5217SJeff Kirsher #define UCM_REG_UCM_PRTY_STS_CLR 0xe01dc 4688*adfc5217SJeff Kirsher /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS 4689*adfc5217SJeff Kirsher REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 4690*adfc5217SJeff Kirsher Is used to determine the number of the AG context REG-pairs written back; 4691*adfc5217SJeff Kirsher when the Reg1WbFlg isn't set. */ 4692*adfc5217SJeff Kirsher #define UCM_REG_UCM_REG0_SZ 0xe00dc 4693*adfc5217SJeff Kirsher /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 4694*adfc5217SJeff Kirsher disregarded; valid is deasserted; all other signals are treated as usual; 4695*adfc5217SJeff Kirsher if 1 - normal activity. */ 4696*adfc5217SJeff Kirsher #define UCM_REG_UCM_STORM0_IFEN 0xe0004 4697*adfc5217SJeff Kirsher /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 4698*adfc5217SJeff Kirsher disregarded; valid is deasserted; all other signals are treated as usual; 4699*adfc5217SJeff Kirsher if 1 - normal activity. */ 4700*adfc5217SJeff Kirsher #define UCM_REG_UCM_STORM1_IFEN 0xe0008 4701*adfc5217SJeff Kirsher /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is 4702*adfc5217SJeff Kirsher disregarded; acknowledge output is deasserted; all other signals are 4703*adfc5217SJeff Kirsher treated as usual; if 1 - normal activity. */ 4704*adfc5217SJeff Kirsher #define UCM_REG_UCM_TM_IFEN 0xe0020 4705*adfc5217SJeff Kirsher /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 4706*adfc5217SJeff Kirsher disregarded; valid is deasserted; all other signals are treated as usual; 4707*adfc5217SJeff Kirsher if 1 - normal activity. */ 4708*adfc5217SJeff Kirsher #define UCM_REG_UCM_UQM_IFEN 0xe000c 4709*adfc5217SJeff Kirsher /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */ 4710*adfc5217SJeff Kirsher #define UCM_REG_UCM_UQM_USE_Q 0xe00d8 4711*adfc5217SJeff Kirsher /* [RW 6] QM output initial credit. Max credit available - 32.Write writes 4712*adfc5217SJeff Kirsher the initial credit value; read returns the current value of the credit 4713*adfc5217SJeff Kirsher counter. Must be initialized to 32 at start-up. */ 4714*adfc5217SJeff Kirsher #define UCM_REG_UQM_INIT_CRD 0xe0220 4715*adfc5217SJeff Kirsher /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 4716*adfc5217SJeff Kirsher stands for weight 8 (the most prioritised); 1 stands for weight 1(least 4717*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 4718*adfc5217SJeff Kirsher #define UCM_REG_UQM_P_WEIGHT 0xe00cc 4719*adfc5217SJeff Kirsher /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 4720*adfc5217SJeff Kirsher stands for weight 8 (the most prioritised); 1 stands for weight 1(least 4721*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 4722*adfc5217SJeff Kirsher #define UCM_REG_UQM_S_WEIGHT 0xe00d0 4723*adfc5217SJeff Kirsher /* [RW 28] The CM header value for QM request (primary). */ 4724*adfc5217SJeff Kirsher #define UCM_REG_UQM_UCM_HDR_P 0xe0094 4725*adfc5217SJeff Kirsher /* [RW 28] The CM header value for QM request (secondary). */ 4726*adfc5217SJeff Kirsher #define UCM_REG_UQM_UCM_HDR_S 0xe0098 4727*adfc5217SJeff Kirsher /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 4728*adfc5217SJeff Kirsher acknowledge output is deasserted; all other signals are treated as usual; 4729*adfc5217SJeff Kirsher if 1 - normal activity. */ 4730*adfc5217SJeff Kirsher #define UCM_REG_UQM_UCM_IFEN 0xe0014 4731*adfc5217SJeff Kirsher /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 4732*adfc5217SJeff Kirsher acknowledge output is deasserted; all other signals are treated as usual; 4733*adfc5217SJeff Kirsher if 1 - normal activity. */ 4734*adfc5217SJeff Kirsher #define UCM_REG_USDM_IFEN 0xe0018 4735*adfc5217SJeff Kirsher /* [RC 1] Set when the message length mismatch (relative to last indication) 4736*adfc5217SJeff Kirsher at the SDM interface is detected. */ 4737*adfc5217SJeff Kirsher #define UCM_REG_USDM_LENGTH_MIS 0xe0158 4738*adfc5217SJeff Kirsher /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for 4739*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 4740*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 4741*adfc5217SJeff Kirsher #define UCM_REG_USDM_WEIGHT 0xe00c8 4742*adfc5217SJeff Kirsher /* [RW 1] Input xsem Interface enable. If 0 - the valid input is 4743*adfc5217SJeff Kirsher disregarded; acknowledge output is deasserted; all other signals are 4744*adfc5217SJeff Kirsher treated as usual; if 1 - normal activity. */ 4745*adfc5217SJeff Kirsher #define UCM_REG_XSEM_IFEN 0xe002c 4746*adfc5217SJeff Kirsher /* [RC 1] Set when the message length mismatch (relative to last indication) 4747*adfc5217SJeff Kirsher at the xsem interface isdetected. */ 4748*adfc5217SJeff Kirsher #define UCM_REG_XSEM_LENGTH_MIS 0xe0164 4749*adfc5217SJeff Kirsher /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for 4750*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 4751*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 4752*adfc5217SJeff Kirsher #define UCM_REG_XSEM_WEIGHT 0xe00bc 4753*adfc5217SJeff Kirsher /* [RW 20] Indirect access to the descriptor table of the XX protection 4754*adfc5217SJeff Kirsher mechanism. The fields are:[5:0] - message length; 14:6] - message 4755*adfc5217SJeff Kirsher pointer; 19:15] - next pointer. */ 4756*adfc5217SJeff Kirsher #define UCM_REG_XX_DESCR_TABLE 0xe0280 4757*adfc5217SJeff Kirsher #define UCM_REG_XX_DESCR_TABLE_SIZE 27 4758*adfc5217SJeff Kirsher /* [R 6] Use to read the XX protection Free counter. */ 4759*adfc5217SJeff Kirsher #define UCM_REG_XX_FREE 0xe016c 4760*adfc5217SJeff Kirsher /* [RW 6] Initial value for the credit counter; responsible for fulfilling 4761*adfc5217SJeff Kirsher of the Input Stage XX protection buffer by the XX protection pending 4762*adfc5217SJeff Kirsher messages. Write writes the initial credit value; read returns the current 4763*adfc5217SJeff Kirsher value of the credit counter. Must be initialized to 12 at start-up. */ 4764*adfc5217SJeff Kirsher #define UCM_REG_XX_INIT_CRD 0xe0224 4765*adfc5217SJeff Kirsher /* [RW 6] The maximum number of pending messages; which may be stored in XX 4766*adfc5217SJeff Kirsher protection. ~ucm_registers_xx_free.xx_free read on read. */ 4767*adfc5217SJeff Kirsher #define UCM_REG_XX_MSG_NUM 0xe0228 4768*adfc5217SJeff Kirsher /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 4769*adfc5217SJeff Kirsher #define UCM_REG_XX_OVFL_EVNT_ID 0xe004c 4770*adfc5217SJeff Kirsher /* [RW 16] Indirect access to the XX table of the XX protection mechanism. 4771*adfc5217SJeff Kirsher The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] - 4772*adfc5217SJeff Kirsher header pointer. */ 4773*adfc5217SJeff Kirsher #define UCM_REG_XX_TABLE 0xe0300 4774*adfc5217SJeff Kirsher #define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE (0x1<<28) 4775*adfc5217SJeff Kirsher #define UMAC_COMMAND_CONFIG_REG_LOOP_ENA (0x1<<15) 4776*adfc5217SJeff Kirsher #define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK (0x1<<24) 4777*adfc5217SJeff Kirsher #define UMAC_COMMAND_CONFIG_REG_PAD_EN (0x1<<5) 4778*adfc5217SJeff Kirsher #define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE (0x1<<8) 4779*adfc5217SJeff Kirsher #define UMAC_COMMAND_CONFIG_REG_PROMIS_EN (0x1<<4) 4780*adfc5217SJeff Kirsher #define UMAC_COMMAND_CONFIG_REG_RX_ENA (0x1<<1) 4781*adfc5217SJeff Kirsher #define UMAC_COMMAND_CONFIG_REG_SW_RESET (0x1<<13) 4782*adfc5217SJeff Kirsher #define UMAC_COMMAND_CONFIG_REG_TX_ENA (0x1<<0) 4783*adfc5217SJeff Kirsher #define UMAC_REG_COMMAND_CONFIG 0x8 4784*adfc5217SJeff Kirsher /* [RW 32] Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refers 4785*adfc5217SJeff Kirsher * to bit 17 of the MAC address etc. */ 4786*adfc5217SJeff Kirsher #define UMAC_REG_MAC_ADDR0 0xc 4787*adfc5217SJeff Kirsher /* [RW 16] Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 1 4788*adfc5217SJeff Kirsher * refers to Bit 1 of the MAC address etc. Bits 16 to 31 are reserved. */ 4789*adfc5217SJeff Kirsher #define UMAC_REG_MAC_ADDR1 0x10 4790*adfc5217SJeff Kirsher /* [RW 14] Defines a 14-Bit maximum frame length used by the MAC receive 4791*adfc5217SJeff Kirsher * logic to check frames. */ 4792*adfc5217SJeff Kirsher #define UMAC_REG_MAXFR 0x14 4793*adfc5217SJeff Kirsher /* [RW 8] The event id for aggregated interrupt 0 */ 4794*adfc5217SJeff Kirsher #define USDM_REG_AGG_INT_EVENT_0 0xc4038 4795*adfc5217SJeff Kirsher #define USDM_REG_AGG_INT_EVENT_1 0xc403c 4796*adfc5217SJeff Kirsher #define USDM_REG_AGG_INT_EVENT_2 0xc4040 4797*adfc5217SJeff Kirsher #define USDM_REG_AGG_INT_EVENT_4 0xc4048 4798*adfc5217SJeff Kirsher #define USDM_REG_AGG_INT_EVENT_5 0xc404c 4799*adfc5217SJeff Kirsher #define USDM_REG_AGG_INT_EVENT_6 0xc4050 4800*adfc5217SJeff Kirsher /* [RW 1] For each aggregated interrupt index whether the mode is normal (0) 4801*adfc5217SJeff Kirsher or auto-mask-mode (1) */ 4802*adfc5217SJeff Kirsher #define USDM_REG_AGG_INT_MODE_0 0xc41b8 4803*adfc5217SJeff Kirsher #define USDM_REG_AGG_INT_MODE_1 0xc41bc 4804*adfc5217SJeff Kirsher #define USDM_REG_AGG_INT_MODE_4 0xc41c8 4805*adfc5217SJeff Kirsher #define USDM_REG_AGG_INT_MODE_5 0xc41cc 4806*adfc5217SJeff Kirsher #define USDM_REG_AGG_INT_MODE_6 0xc41d0 4807*adfc5217SJeff Kirsher /* [RW 1] The T bit for aggregated interrupt 5 */ 4808*adfc5217SJeff Kirsher #define USDM_REG_AGG_INT_T_5 0xc40cc 4809*adfc5217SJeff Kirsher #define USDM_REG_AGG_INT_T_6 0xc40d0 4810*adfc5217SJeff Kirsher /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 4811*adfc5217SJeff Kirsher #define USDM_REG_CFC_RSP_START_ADDR 0xc4008 4812*adfc5217SJeff Kirsher /* [RW 16] The maximum value of the completion counter #0 */ 4813*adfc5217SJeff Kirsher #define USDM_REG_CMP_COUNTER_MAX0 0xc401c 4814*adfc5217SJeff Kirsher /* [RW 16] The maximum value of the completion counter #1 */ 4815*adfc5217SJeff Kirsher #define USDM_REG_CMP_COUNTER_MAX1 0xc4020 4816*adfc5217SJeff Kirsher /* [RW 16] The maximum value of the completion counter #2 */ 4817*adfc5217SJeff Kirsher #define USDM_REG_CMP_COUNTER_MAX2 0xc4024 4818*adfc5217SJeff Kirsher /* [RW 16] The maximum value of the completion counter #3 */ 4819*adfc5217SJeff Kirsher #define USDM_REG_CMP_COUNTER_MAX3 0xc4028 4820*adfc5217SJeff Kirsher /* [RW 13] The start address in the internal RAM for the completion 4821*adfc5217SJeff Kirsher counters. */ 4822*adfc5217SJeff Kirsher #define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c 4823*adfc5217SJeff Kirsher #define USDM_REG_ENABLE_IN1 0xc4238 4824*adfc5217SJeff Kirsher #define USDM_REG_ENABLE_IN2 0xc423c 4825*adfc5217SJeff Kirsher #define USDM_REG_ENABLE_OUT1 0xc4240 4826*adfc5217SJeff Kirsher #define USDM_REG_ENABLE_OUT2 0xc4244 4827*adfc5217SJeff Kirsher /* [RW 4] The initial number of messages that can be sent to the pxp control 4828*adfc5217SJeff Kirsher interface without receiving any ACK. */ 4829*adfc5217SJeff Kirsher #define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0 4830*adfc5217SJeff Kirsher /* [ST 32] The number of ACK after placement messages received */ 4831*adfc5217SJeff Kirsher #define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280 4832*adfc5217SJeff Kirsher /* [ST 32] The number of packet end messages received from the parser */ 4833*adfc5217SJeff Kirsher #define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278 4834*adfc5217SJeff Kirsher /* [ST 32] The number of requests received from the pxp async if */ 4835*adfc5217SJeff Kirsher #define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c 4836*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 0 */ 4837*adfc5217SJeff Kirsher #define USDM_REG_NUM_OF_Q0_CMD 0xc4248 4838*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 10 */ 4839*adfc5217SJeff Kirsher #define USDM_REG_NUM_OF_Q10_CMD 0xc4270 4840*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 11 */ 4841*adfc5217SJeff Kirsher #define USDM_REG_NUM_OF_Q11_CMD 0xc4274 4842*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 1 */ 4843*adfc5217SJeff Kirsher #define USDM_REG_NUM_OF_Q1_CMD 0xc424c 4844*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 2 */ 4845*adfc5217SJeff Kirsher #define USDM_REG_NUM_OF_Q2_CMD 0xc4250 4846*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 3 */ 4847*adfc5217SJeff Kirsher #define USDM_REG_NUM_OF_Q3_CMD 0xc4254 4848*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 4 */ 4849*adfc5217SJeff Kirsher #define USDM_REG_NUM_OF_Q4_CMD 0xc4258 4850*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 5 */ 4851*adfc5217SJeff Kirsher #define USDM_REG_NUM_OF_Q5_CMD 0xc425c 4852*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 6 */ 4853*adfc5217SJeff Kirsher #define USDM_REG_NUM_OF_Q6_CMD 0xc4260 4854*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 7 */ 4855*adfc5217SJeff Kirsher #define USDM_REG_NUM_OF_Q7_CMD 0xc4264 4856*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 8 */ 4857*adfc5217SJeff Kirsher #define USDM_REG_NUM_OF_Q8_CMD 0xc4268 4858*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 9 */ 4859*adfc5217SJeff Kirsher #define USDM_REG_NUM_OF_Q9_CMD 0xc426c 4860*adfc5217SJeff Kirsher /* [RW 13] The start address in the internal RAM for the packet end message */ 4861*adfc5217SJeff Kirsher #define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014 4862*adfc5217SJeff Kirsher /* [RW 13] The start address in the internal RAM for queue counters */ 4863*adfc5217SJeff Kirsher #define USDM_REG_Q_COUNTER_START_ADDR 0xc4010 4864*adfc5217SJeff Kirsher /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 4865*adfc5217SJeff Kirsher #define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550 4866*adfc5217SJeff Kirsher /* [R 1] parser fifo empty in sdm_sync block */ 4867*adfc5217SJeff Kirsher #define USDM_REG_SYNC_PARSER_EMPTY 0xc4558 4868*adfc5217SJeff Kirsher /* [R 1] parser serial fifo empty in sdm_sync block */ 4869*adfc5217SJeff Kirsher #define USDM_REG_SYNC_SYNC_EMPTY 0xc4560 4870*adfc5217SJeff Kirsher /* [RW 32] Tick for timer counter. Applicable only when 4871*adfc5217SJeff Kirsher ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */ 4872*adfc5217SJeff Kirsher #define USDM_REG_TIMER_TICK 0xc4000 4873*adfc5217SJeff Kirsher /* [RW 32] Interrupt mask register #0 read/write */ 4874*adfc5217SJeff Kirsher #define USDM_REG_USDM_INT_MASK_0 0xc42a0 4875*adfc5217SJeff Kirsher #define USDM_REG_USDM_INT_MASK_1 0xc42b0 4876*adfc5217SJeff Kirsher /* [R 32] Interrupt register #0 read */ 4877*adfc5217SJeff Kirsher #define USDM_REG_USDM_INT_STS_0 0xc4294 4878*adfc5217SJeff Kirsher #define USDM_REG_USDM_INT_STS_1 0xc42a4 4879*adfc5217SJeff Kirsher /* [RW 11] Parity mask register #0 read/write */ 4880*adfc5217SJeff Kirsher #define USDM_REG_USDM_PRTY_MASK 0xc42c0 4881*adfc5217SJeff Kirsher /* [R 11] Parity register #0 read */ 4882*adfc5217SJeff Kirsher #define USDM_REG_USDM_PRTY_STS 0xc42b4 4883*adfc5217SJeff Kirsher /* [RC 11] Parity register #0 read clear */ 4884*adfc5217SJeff Kirsher #define USDM_REG_USDM_PRTY_STS_CLR 0xc42b8 4885*adfc5217SJeff Kirsher /* [RW 5] The number of time_slots in the arbitration cycle */ 4886*adfc5217SJeff Kirsher #define USEM_REG_ARB_CYCLE_SIZE 0x300034 4887*adfc5217SJeff Kirsher /* [RW 3] The source that is associated with arbitration element 0. Source 4888*adfc5217SJeff Kirsher decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4889*adfc5217SJeff Kirsher sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 4890*adfc5217SJeff Kirsher #define USEM_REG_ARB_ELEMENT0 0x300020 4891*adfc5217SJeff Kirsher /* [RW 3] The source that is associated with arbitration element 1. Source 4892*adfc5217SJeff Kirsher decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4893*adfc5217SJeff Kirsher sleeping thread with priority 1; 4- sleeping thread with priority 2. 4894*adfc5217SJeff Kirsher Could not be equal to register ~usem_registers_arb_element0.arb_element0 */ 4895*adfc5217SJeff Kirsher #define USEM_REG_ARB_ELEMENT1 0x300024 4896*adfc5217SJeff Kirsher /* [RW 3] The source that is associated with arbitration element 2. Source 4897*adfc5217SJeff Kirsher decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4898*adfc5217SJeff Kirsher sleeping thread with priority 1; 4- sleeping thread with priority 2. 4899*adfc5217SJeff Kirsher Could not be equal to register ~usem_registers_arb_element0.arb_element0 4900*adfc5217SJeff Kirsher and ~usem_registers_arb_element1.arb_element1 */ 4901*adfc5217SJeff Kirsher #define USEM_REG_ARB_ELEMENT2 0x300028 4902*adfc5217SJeff Kirsher /* [RW 3] The source that is associated with arbitration element 3. Source 4903*adfc5217SJeff Kirsher decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4904*adfc5217SJeff Kirsher sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 4905*adfc5217SJeff Kirsher not be equal to register ~usem_registers_arb_element0.arb_element0 and 4906*adfc5217SJeff Kirsher ~usem_registers_arb_element1.arb_element1 and 4907*adfc5217SJeff Kirsher ~usem_registers_arb_element2.arb_element2 */ 4908*adfc5217SJeff Kirsher #define USEM_REG_ARB_ELEMENT3 0x30002c 4909*adfc5217SJeff Kirsher /* [RW 3] The source that is associated with arbitration element 4. Source 4910*adfc5217SJeff Kirsher decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4911*adfc5217SJeff Kirsher sleeping thread with priority 1; 4- sleeping thread with priority 2. 4912*adfc5217SJeff Kirsher Could not be equal to register ~usem_registers_arb_element0.arb_element0 4913*adfc5217SJeff Kirsher and ~usem_registers_arb_element1.arb_element1 and 4914*adfc5217SJeff Kirsher ~usem_registers_arb_element2.arb_element2 and 4915*adfc5217SJeff Kirsher ~usem_registers_arb_element3.arb_element3 */ 4916*adfc5217SJeff Kirsher #define USEM_REG_ARB_ELEMENT4 0x300030 4917*adfc5217SJeff Kirsher #define USEM_REG_ENABLE_IN 0x3000a4 4918*adfc5217SJeff Kirsher #define USEM_REG_ENABLE_OUT 0x3000a8 4919*adfc5217SJeff Kirsher /* [RW 32] This address space contains all registers and memories that are 4920*adfc5217SJeff Kirsher placed in SEM_FAST block. The SEM_FAST registers are described in 4921*adfc5217SJeff Kirsher appendix B. In order to access the sem_fast registers the base address 4922*adfc5217SJeff Kirsher ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 4923*adfc5217SJeff Kirsher #define USEM_REG_FAST_MEMORY 0x320000 4924*adfc5217SJeff Kirsher /* [RW 1] Disables input messages from FIC0 May be updated during run_time 4925*adfc5217SJeff Kirsher by the microcode */ 4926*adfc5217SJeff Kirsher #define USEM_REG_FIC0_DISABLE 0x300224 4927*adfc5217SJeff Kirsher /* [RW 1] Disables input messages from FIC1 May be updated during run_time 4928*adfc5217SJeff Kirsher by the microcode */ 4929*adfc5217SJeff Kirsher #define USEM_REG_FIC1_DISABLE 0x300234 4930*adfc5217SJeff Kirsher /* [RW 15] Interrupt table Read and write access to it is not possible in 4931*adfc5217SJeff Kirsher the middle of the work */ 4932*adfc5217SJeff Kirsher #define USEM_REG_INT_TABLE 0x300400 4933*adfc5217SJeff Kirsher /* [ST 24] Statistics register. The number of messages that entered through 4934*adfc5217SJeff Kirsher FIC0 */ 4935*adfc5217SJeff Kirsher #define USEM_REG_MSG_NUM_FIC0 0x300000 4936*adfc5217SJeff Kirsher /* [ST 24] Statistics register. The number of messages that entered through 4937*adfc5217SJeff Kirsher FIC1 */ 4938*adfc5217SJeff Kirsher #define USEM_REG_MSG_NUM_FIC1 0x300004 4939*adfc5217SJeff Kirsher /* [ST 24] Statistics register. The number of messages that were sent to 4940*adfc5217SJeff Kirsher FOC0 */ 4941*adfc5217SJeff Kirsher #define USEM_REG_MSG_NUM_FOC0 0x300008 4942*adfc5217SJeff Kirsher /* [ST 24] Statistics register. The number of messages that were sent to 4943*adfc5217SJeff Kirsher FOC1 */ 4944*adfc5217SJeff Kirsher #define USEM_REG_MSG_NUM_FOC1 0x30000c 4945*adfc5217SJeff Kirsher /* [ST 24] Statistics register. The number of messages that were sent to 4946*adfc5217SJeff Kirsher FOC2 */ 4947*adfc5217SJeff Kirsher #define USEM_REG_MSG_NUM_FOC2 0x300010 4948*adfc5217SJeff Kirsher /* [ST 24] Statistics register. The number of messages that were sent to 4949*adfc5217SJeff Kirsher FOC3 */ 4950*adfc5217SJeff Kirsher #define USEM_REG_MSG_NUM_FOC3 0x300014 4951*adfc5217SJeff Kirsher /* [RW 1] Disables input messages from the passive buffer May be updated 4952*adfc5217SJeff Kirsher during run_time by the microcode */ 4953*adfc5217SJeff Kirsher #define USEM_REG_PAS_DISABLE 0x30024c 4954*adfc5217SJeff Kirsher /* [WB 128] Debug only. Passive buffer memory */ 4955*adfc5217SJeff Kirsher #define USEM_REG_PASSIVE_BUFFER 0x302000 4956*adfc5217SJeff Kirsher /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 4957*adfc5217SJeff Kirsher #define USEM_REG_PRAM 0x340000 4958*adfc5217SJeff Kirsher /* [R 16] Valid sleeping threads indication have bit per thread */ 4959*adfc5217SJeff Kirsher #define USEM_REG_SLEEP_THREADS_VALID 0x30026c 4960*adfc5217SJeff Kirsher /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 4961*adfc5217SJeff Kirsher #define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0 4962*adfc5217SJeff Kirsher /* [RW 16] List of free threads . There is a bit per thread. */ 4963*adfc5217SJeff Kirsher #define USEM_REG_THREADS_LIST 0x3002e4 4964*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 0 */ 4965*adfc5217SJeff Kirsher #define USEM_REG_TS_0_AS 0x300038 4966*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 10 */ 4967*adfc5217SJeff Kirsher #define USEM_REG_TS_10_AS 0x300060 4968*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 11 */ 4969*adfc5217SJeff Kirsher #define USEM_REG_TS_11_AS 0x300064 4970*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 12 */ 4971*adfc5217SJeff Kirsher #define USEM_REG_TS_12_AS 0x300068 4972*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 13 */ 4973*adfc5217SJeff Kirsher #define USEM_REG_TS_13_AS 0x30006c 4974*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 14 */ 4975*adfc5217SJeff Kirsher #define USEM_REG_TS_14_AS 0x300070 4976*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 15 */ 4977*adfc5217SJeff Kirsher #define USEM_REG_TS_15_AS 0x300074 4978*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 16 */ 4979*adfc5217SJeff Kirsher #define USEM_REG_TS_16_AS 0x300078 4980*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 17 */ 4981*adfc5217SJeff Kirsher #define USEM_REG_TS_17_AS 0x30007c 4982*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 18 */ 4983*adfc5217SJeff Kirsher #define USEM_REG_TS_18_AS 0x300080 4984*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 1 */ 4985*adfc5217SJeff Kirsher #define USEM_REG_TS_1_AS 0x30003c 4986*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 2 */ 4987*adfc5217SJeff Kirsher #define USEM_REG_TS_2_AS 0x300040 4988*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 3 */ 4989*adfc5217SJeff Kirsher #define USEM_REG_TS_3_AS 0x300044 4990*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 4 */ 4991*adfc5217SJeff Kirsher #define USEM_REG_TS_4_AS 0x300048 4992*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 5 */ 4993*adfc5217SJeff Kirsher #define USEM_REG_TS_5_AS 0x30004c 4994*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 6 */ 4995*adfc5217SJeff Kirsher #define USEM_REG_TS_6_AS 0x300050 4996*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 7 */ 4997*adfc5217SJeff Kirsher #define USEM_REG_TS_7_AS 0x300054 4998*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 8 */ 4999*adfc5217SJeff Kirsher #define USEM_REG_TS_8_AS 0x300058 5000*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 9 */ 5001*adfc5217SJeff Kirsher #define USEM_REG_TS_9_AS 0x30005c 5002*adfc5217SJeff Kirsher /* [RW 32] Interrupt mask register #0 read/write */ 5003*adfc5217SJeff Kirsher #define USEM_REG_USEM_INT_MASK_0 0x300110 5004*adfc5217SJeff Kirsher #define USEM_REG_USEM_INT_MASK_1 0x300120 5005*adfc5217SJeff Kirsher /* [R 32] Interrupt register #0 read */ 5006*adfc5217SJeff Kirsher #define USEM_REG_USEM_INT_STS_0 0x300104 5007*adfc5217SJeff Kirsher #define USEM_REG_USEM_INT_STS_1 0x300114 5008*adfc5217SJeff Kirsher /* [RW 32] Parity mask register #0 read/write */ 5009*adfc5217SJeff Kirsher #define USEM_REG_USEM_PRTY_MASK_0 0x300130 5010*adfc5217SJeff Kirsher #define USEM_REG_USEM_PRTY_MASK_1 0x300140 5011*adfc5217SJeff Kirsher /* [R 32] Parity register #0 read */ 5012*adfc5217SJeff Kirsher #define USEM_REG_USEM_PRTY_STS_0 0x300124 5013*adfc5217SJeff Kirsher #define USEM_REG_USEM_PRTY_STS_1 0x300134 5014*adfc5217SJeff Kirsher /* [RC 32] Parity register #0 read clear */ 5015*adfc5217SJeff Kirsher #define USEM_REG_USEM_PRTY_STS_CLR_0 0x300128 5016*adfc5217SJeff Kirsher #define USEM_REG_USEM_PRTY_STS_CLR_1 0x300138 5017*adfc5217SJeff Kirsher /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 5018*adfc5217SJeff Kirsher * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ 5019*adfc5217SJeff Kirsher #define USEM_REG_VFPF_ERR_NUM 0x300380 5020*adfc5217SJeff Kirsher #define VFC_MEMORIES_RST_REG_CAM_RST (0x1<<0) 5021*adfc5217SJeff Kirsher #define VFC_MEMORIES_RST_REG_RAM_RST (0x1<<1) 5022*adfc5217SJeff Kirsher #define VFC_REG_MEMORIES_RST 0x1943c 5023*adfc5217SJeff Kirsher /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits 5024*adfc5217SJeff Kirsher * [12:8] of the address should be the offset within the accessed LCID 5025*adfc5217SJeff Kirsher * context; the bits [7:0] are the accessed LCID.Example: to write to REG10 5026*adfc5217SJeff Kirsher * LCID100. The RBC address should be 13'ha64. */ 5027*adfc5217SJeff Kirsher #define XCM_REG_AG_CTX 0x28000 5028*adfc5217SJeff Kirsher /* [RW 2] The queue index for registration on Aux1 counter flag. */ 5029*adfc5217SJeff Kirsher #define XCM_REG_AUX1_Q 0x20134 5030*adfc5217SJeff Kirsher /* [RW 2] Per each decision rule the queue index to register to. */ 5031*adfc5217SJeff Kirsher #define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0 5032*adfc5217SJeff Kirsher /* [R 5] Used to read the XX protection CAM occupancy counter. */ 5033*adfc5217SJeff Kirsher #define XCM_REG_CAM_OCCUP 0x20244 5034*adfc5217SJeff Kirsher /* [RW 1] CDU AG read Interface enable. If 0 - the request input is 5035*adfc5217SJeff Kirsher disregarded; valid output is deasserted; all other signals are treated as 5036*adfc5217SJeff Kirsher usual; if 1 - normal activity. */ 5037*adfc5217SJeff Kirsher #define XCM_REG_CDU_AG_RD_IFEN 0x20044 5038*adfc5217SJeff Kirsher /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 5039*adfc5217SJeff Kirsher are disregarded; all other signals are treated as usual; if 1 - normal 5040*adfc5217SJeff Kirsher activity. */ 5041*adfc5217SJeff Kirsher #define XCM_REG_CDU_AG_WR_IFEN 0x20040 5042*adfc5217SJeff Kirsher /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 5043*adfc5217SJeff Kirsher disregarded; valid output is deasserted; all other signals are treated as 5044*adfc5217SJeff Kirsher usual; if 1 - normal activity. */ 5045*adfc5217SJeff Kirsher #define XCM_REG_CDU_SM_RD_IFEN 0x2004c 5046*adfc5217SJeff Kirsher /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 5047*adfc5217SJeff Kirsher input is disregarded; all other signals are treated as usual; if 1 - 5048*adfc5217SJeff Kirsher normal activity. */ 5049*adfc5217SJeff Kirsher #define XCM_REG_CDU_SM_WR_IFEN 0x20048 5050*adfc5217SJeff Kirsher /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 5051*adfc5217SJeff Kirsher the initial credit value; read returns the current value of the credit 5052*adfc5217SJeff Kirsher counter. Must be initialized to 1 at start-up. */ 5053*adfc5217SJeff Kirsher #define XCM_REG_CFC_INIT_CRD 0x20404 5054*adfc5217SJeff Kirsher /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for 5055*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 5056*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 5057*adfc5217SJeff Kirsher #define XCM_REG_CP_WEIGHT 0x200dc 5058*adfc5217SJeff Kirsher /* [RW 1] Input csem Interface enable. If 0 - the valid input is 5059*adfc5217SJeff Kirsher disregarded; acknowledge output is deasserted; all other signals are 5060*adfc5217SJeff Kirsher treated as usual; if 1 - normal activity. */ 5061*adfc5217SJeff Kirsher #define XCM_REG_CSEM_IFEN 0x20028 5062*adfc5217SJeff Kirsher /* [RC 1] Set at message length mismatch (relative to last indication) at 5063*adfc5217SJeff Kirsher the csem interface. */ 5064*adfc5217SJeff Kirsher #define XCM_REG_CSEM_LENGTH_MIS 0x20228 5065*adfc5217SJeff Kirsher /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for 5066*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 5067*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 5068*adfc5217SJeff Kirsher #define XCM_REG_CSEM_WEIGHT 0x200c4 5069*adfc5217SJeff Kirsher /* [RW 1] Input dorq Interface enable. If 0 - the valid input is 5070*adfc5217SJeff Kirsher disregarded; acknowledge output is deasserted; all other signals are 5071*adfc5217SJeff Kirsher treated as usual; if 1 - normal activity. */ 5072*adfc5217SJeff Kirsher #define XCM_REG_DORQ_IFEN 0x20030 5073*adfc5217SJeff Kirsher /* [RC 1] Set at message length mismatch (relative to last indication) at 5074*adfc5217SJeff Kirsher the dorq interface. */ 5075*adfc5217SJeff Kirsher #define XCM_REG_DORQ_LENGTH_MIS 0x20230 5076*adfc5217SJeff Kirsher /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for 5077*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 5078*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 5079*adfc5217SJeff Kirsher #define XCM_REG_DORQ_WEIGHT 0x200cc 5080*adfc5217SJeff Kirsher /* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */ 5081*adfc5217SJeff Kirsher #define XCM_REG_ERR_EVNT_ID 0x200b0 5082*adfc5217SJeff Kirsher /* [RW 28] The CM erroneous header for QM and Timers formatting. */ 5083*adfc5217SJeff Kirsher #define XCM_REG_ERR_XCM_HDR 0x200ac 5084*adfc5217SJeff Kirsher /* [RW 8] The Event ID for Timers expiration. */ 5085*adfc5217SJeff Kirsher #define XCM_REG_EXPR_EVNT_ID 0x200b4 5086*adfc5217SJeff Kirsher /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write 5087*adfc5217SJeff Kirsher writes the initial credit value; read returns the current value of the 5088*adfc5217SJeff Kirsher credit counter. Must be initialized to 64 at start-up. */ 5089*adfc5217SJeff Kirsher #define XCM_REG_FIC0_INIT_CRD 0x2040c 5090*adfc5217SJeff Kirsher /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 5091*adfc5217SJeff Kirsher writes the initial credit value; read returns the current value of the 5092*adfc5217SJeff Kirsher credit counter. Must be initialized to 64 at start-up. */ 5093*adfc5217SJeff Kirsher #define XCM_REG_FIC1_INIT_CRD 0x20410 5094*adfc5217SJeff Kirsher #define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118 5095*adfc5217SJeff Kirsher #define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c 5096*adfc5217SJeff Kirsher #define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108 5097*adfc5217SJeff Kirsher #define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c 5098*adfc5217SJeff Kirsher /* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1 5099*adfc5217SJeff Kirsher - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr; 5100*adfc5217SJeff Kirsher ~xcm_registers_gr_ld0_pr.gr_ld0_pr and 5101*adfc5217SJeff Kirsher ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */ 5102*adfc5217SJeff Kirsher #define XCM_REG_GR_ARB_TYPE 0x2020c 5103*adfc5217SJeff Kirsher /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 5104*adfc5217SJeff Kirsher highest priority is 3. It is supposed that the Channel group is the 5105*adfc5217SJeff Kirsher compliment of the other 3 groups. */ 5106*adfc5217SJeff Kirsher #define XCM_REG_GR_LD0_PR 0x20214 5107*adfc5217SJeff Kirsher /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 5108*adfc5217SJeff Kirsher highest priority is 3. It is supposed that the Channel group is the 5109*adfc5217SJeff Kirsher compliment of the other 3 groups. */ 5110*adfc5217SJeff Kirsher #define XCM_REG_GR_LD1_PR 0x20218 5111*adfc5217SJeff Kirsher /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is 5112*adfc5217SJeff Kirsher disregarded; acknowledge output is deasserted; all other signals are 5113*adfc5217SJeff Kirsher treated as usual; if 1 - normal activity. */ 5114*adfc5217SJeff Kirsher #define XCM_REG_NIG0_IFEN 0x20038 5115*adfc5217SJeff Kirsher /* [RC 1] Set at message length mismatch (relative to last indication) at 5116*adfc5217SJeff Kirsher the nig0 interface. */ 5117*adfc5217SJeff Kirsher #define XCM_REG_NIG0_LENGTH_MIS 0x20238 5118*adfc5217SJeff Kirsher /* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for 5119*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 5120*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 5121*adfc5217SJeff Kirsher #define XCM_REG_NIG0_WEIGHT 0x200d4 5122*adfc5217SJeff Kirsher /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is 5123*adfc5217SJeff Kirsher disregarded; acknowledge output is deasserted; all other signals are 5124*adfc5217SJeff Kirsher treated as usual; if 1 - normal activity. */ 5125*adfc5217SJeff Kirsher #define XCM_REG_NIG1_IFEN 0x2003c 5126*adfc5217SJeff Kirsher /* [RC 1] Set at message length mismatch (relative to last indication) at 5127*adfc5217SJeff Kirsher the nig1 interface. */ 5128*adfc5217SJeff Kirsher #define XCM_REG_NIG1_LENGTH_MIS 0x2023c 5129*adfc5217SJeff Kirsher /* [RW 5] The number of double REG-pairs; loaded from the STORM context and 5130*adfc5217SJeff Kirsher sent to STORM; for a specific connection type. The double REG-pairs are 5131*adfc5217SJeff Kirsher used in order to align to STORM context row size of 128 bits. The offset 5132*adfc5217SJeff Kirsher of these data in the STORM context is always 0. Index _i stands for the 5133*adfc5217SJeff Kirsher connection type (one of 16). */ 5134*adfc5217SJeff Kirsher #define XCM_REG_N_SM_CTX_LD_0 0x20060 5135*adfc5217SJeff Kirsher #define XCM_REG_N_SM_CTX_LD_1 0x20064 5136*adfc5217SJeff Kirsher #define XCM_REG_N_SM_CTX_LD_2 0x20068 5137*adfc5217SJeff Kirsher #define XCM_REG_N_SM_CTX_LD_3 0x2006c 5138*adfc5217SJeff Kirsher #define XCM_REG_N_SM_CTX_LD_4 0x20070 5139*adfc5217SJeff Kirsher #define XCM_REG_N_SM_CTX_LD_5 0x20074 5140*adfc5217SJeff Kirsher /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; 5141*adfc5217SJeff Kirsher acknowledge output is deasserted; all other signals are treated as usual; 5142*adfc5217SJeff Kirsher if 1 - normal activity. */ 5143*adfc5217SJeff Kirsher #define XCM_REG_PBF_IFEN 0x20034 5144*adfc5217SJeff Kirsher /* [RC 1] Set at message length mismatch (relative to last indication) at 5145*adfc5217SJeff Kirsher the pbf interface. */ 5146*adfc5217SJeff Kirsher #define XCM_REG_PBF_LENGTH_MIS 0x20234 5147*adfc5217SJeff Kirsher /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for 5148*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 5149*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 5150*adfc5217SJeff Kirsher #define XCM_REG_PBF_WEIGHT 0x200d0 5151*adfc5217SJeff Kirsher #define XCM_REG_PHYS_QNUM3_0 0x20100 5152*adfc5217SJeff Kirsher #define XCM_REG_PHYS_QNUM3_1 0x20104 5153*adfc5217SJeff Kirsher /* [RW 8] The Event ID for Timers formatting in case of stop done. */ 5154*adfc5217SJeff Kirsher #define XCM_REG_STOP_EVNT_ID 0x200b8 5155*adfc5217SJeff Kirsher /* [RC 1] Set at message length mismatch (relative to last indication) at 5156*adfc5217SJeff Kirsher the STORM interface. */ 5157*adfc5217SJeff Kirsher #define XCM_REG_STORM_LENGTH_MIS 0x2021c 5158*adfc5217SJeff Kirsher /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for 5159*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 5160*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 5161*adfc5217SJeff Kirsher #define XCM_REG_STORM_WEIGHT 0x200bc 5162*adfc5217SJeff Kirsher /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 5163*adfc5217SJeff Kirsher disregarded; acknowledge output is deasserted; all other signals are 5164*adfc5217SJeff Kirsher treated as usual; if 1 - normal activity. */ 5165*adfc5217SJeff Kirsher #define XCM_REG_STORM_XCM_IFEN 0x20010 5166*adfc5217SJeff Kirsher /* [RW 4] Timers output initial credit. Max credit available - 15.Write 5167*adfc5217SJeff Kirsher writes the initial credit value; read returns the current value of the 5168*adfc5217SJeff Kirsher credit counter. Must be initialized to 4 at start-up. */ 5169*adfc5217SJeff Kirsher #define XCM_REG_TM_INIT_CRD 0x2041c 5170*adfc5217SJeff Kirsher /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for 5171*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 5172*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 5173*adfc5217SJeff Kirsher #define XCM_REG_TM_WEIGHT 0x200ec 5174*adfc5217SJeff Kirsher /* [RW 28] The CM header for Timers expiration command. */ 5175*adfc5217SJeff Kirsher #define XCM_REG_TM_XCM_HDR 0x200a8 5176*adfc5217SJeff Kirsher /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is 5177*adfc5217SJeff Kirsher disregarded; acknowledge output is deasserted; all other signals are 5178*adfc5217SJeff Kirsher treated as usual; if 1 - normal activity. */ 5179*adfc5217SJeff Kirsher #define XCM_REG_TM_XCM_IFEN 0x2001c 5180*adfc5217SJeff Kirsher /* [RW 1] Input tsem Interface enable. If 0 - the valid input is 5181*adfc5217SJeff Kirsher disregarded; acknowledge output is deasserted; all other signals are 5182*adfc5217SJeff Kirsher treated as usual; if 1 - normal activity. */ 5183*adfc5217SJeff Kirsher #define XCM_REG_TSEM_IFEN 0x20024 5184*adfc5217SJeff Kirsher /* [RC 1] Set at message length mismatch (relative to last indication) at 5185*adfc5217SJeff Kirsher the tsem interface. */ 5186*adfc5217SJeff Kirsher #define XCM_REG_TSEM_LENGTH_MIS 0x20224 5187*adfc5217SJeff Kirsher /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for 5188*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 5189*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 5190*adfc5217SJeff Kirsher #define XCM_REG_TSEM_WEIGHT 0x200c0 5191*adfc5217SJeff Kirsher /* [RW 2] The queue index for registration on UNA greater NXT decision rule. */ 5192*adfc5217SJeff Kirsher #define XCM_REG_UNA_GT_NXT_Q 0x20120 5193*adfc5217SJeff Kirsher /* [RW 1] Input usem Interface enable. If 0 - the valid input is 5194*adfc5217SJeff Kirsher disregarded; acknowledge output is deasserted; all other signals are 5195*adfc5217SJeff Kirsher treated as usual; if 1 - normal activity. */ 5196*adfc5217SJeff Kirsher #define XCM_REG_USEM_IFEN 0x2002c 5197*adfc5217SJeff Kirsher /* [RC 1] Message length mismatch (relative to last indication) at the usem 5198*adfc5217SJeff Kirsher interface. */ 5199*adfc5217SJeff Kirsher #define XCM_REG_USEM_LENGTH_MIS 0x2022c 5200*adfc5217SJeff Kirsher /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for 5201*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 5202*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 5203*adfc5217SJeff Kirsher #define XCM_REG_USEM_WEIGHT 0x200c8 5204*adfc5217SJeff Kirsher #define XCM_REG_WU_DA_CNT_CMD00 0x201d4 5205*adfc5217SJeff Kirsher #define XCM_REG_WU_DA_CNT_CMD01 0x201d8 5206*adfc5217SJeff Kirsher #define XCM_REG_WU_DA_CNT_CMD10 0x201dc 5207*adfc5217SJeff Kirsher #define XCM_REG_WU_DA_CNT_CMD11 0x201e0 5208*adfc5217SJeff Kirsher #define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4 5209*adfc5217SJeff Kirsher #define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8 5210*adfc5217SJeff Kirsher #define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec 5211*adfc5217SJeff Kirsher #define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0 5212*adfc5217SJeff Kirsher #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4 5213*adfc5217SJeff Kirsher #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8 5214*adfc5217SJeff Kirsher #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc 5215*adfc5217SJeff Kirsher #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0 5216*adfc5217SJeff Kirsher /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 5217*adfc5217SJeff Kirsher acknowledge output is deasserted; all other signals are treated as usual; 5218*adfc5217SJeff Kirsher if 1 - normal activity. */ 5219*adfc5217SJeff Kirsher #define XCM_REG_XCM_CFC_IFEN 0x20050 5220*adfc5217SJeff Kirsher /* [RW 14] Interrupt mask register #0 read/write */ 5221*adfc5217SJeff Kirsher #define XCM_REG_XCM_INT_MASK 0x202b4 5222*adfc5217SJeff Kirsher /* [R 14] Interrupt register #0 read */ 5223*adfc5217SJeff Kirsher #define XCM_REG_XCM_INT_STS 0x202a8 5224*adfc5217SJeff Kirsher /* [RW 30] Parity mask register #0 read/write */ 5225*adfc5217SJeff Kirsher #define XCM_REG_XCM_PRTY_MASK 0x202c4 5226*adfc5217SJeff Kirsher /* [R 30] Parity register #0 read */ 5227*adfc5217SJeff Kirsher #define XCM_REG_XCM_PRTY_STS 0x202b8 5228*adfc5217SJeff Kirsher /* [RC 30] Parity register #0 read clear */ 5229*adfc5217SJeff Kirsher #define XCM_REG_XCM_PRTY_STS_CLR 0x202bc 5230*adfc5217SJeff Kirsher 5231*adfc5217SJeff Kirsher /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS 5232*adfc5217SJeff Kirsher REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 5233*adfc5217SJeff Kirsher Is used to determine the number of the AG context REG-pairs written back; 5234*adfc5217SJeff Kirsher when the Reg1WbFlg isn't set. */ 5235*adfc5217SJeff Kirsher #define XCM_REG_XCM_REG0_SZ 0x200f4 5236*adfc5217SJeff Kirsher /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 5237*adfc5217SJeff Kirsher disregarded; valid is deasserted; all other signals are treated as usual; 5238*adfc5217SJeff Kirsher if 1 - normal activity. */ 5239*adfc5217SJeff Kirsher #define XCM_REG_XCM_STORM0_IFEN 0x20004 5240*adfc5217SJeff Kirsher /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 5241*adfc5217SJeff Kirsher disregarded; valid is deasserted; all other signals are treated as usual; 5242*adfc5217SJeff Kirsher if 1 - normal activity. */ 5243*adfc5217SJeff Kirsher #define XCM_REG_XCM_STORM1_IFEN 0x20008 5244*adfc5217SJeff Kirsher /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is 5245*adfc5217SJeff Kirsher disregarded; acknowledge output is deasserted; all other signals are 5246*adfc5217SJeff Kirsher treated as usual; if 1 - normal activity. */ 5247*adfc5217SJeff Kirsher #define XCM_REG_XCM_TM_IFEN 0x20020 5248*adfc5217SJeff Kirsher /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 5249*adfc5217SJeff Kirsher disregarded; valid is deasserted; all other signals are treated as usual; 5250*adfc5217SJeff Kirsher if 1 - normal activity. */ 5251*adfc5217SJeff Kirsher #define XCM_REG_XCM_XQM_IFEN 0x2000c 5252*adfc5217SJeff Kirsher /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */ 5253*adfc5217SJeff Kirsher #define XCM_REG_XCM_XQM_USE_Q 0x200f0 5254*adfc5217SJeff Kirsher /* [RW 4] The value by which CFC updates the activity counter at QM bypass. */ 5255*adfc5217SJeff Kirsher #define XCM_REG_XQM_BYP_ACT_UPD 0x200fc 5256*adfc5217SJeff Kirsher /* [RW 6] QM output initial credit. Max credit available - 32.Write writes 5257*adfc5217SJeff Kirsher the initial credit value; read returns the current value of the credit 5258*adfc5217SJeff Kirsher counter. Must be initialized to 32 at start-up. */ 5259*adfc5217SJeff Kirsher #define XCM_REG_XQM_INIT_CRD 0x20420 5260*adfc5217SJeff Kirsher /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 5261*adfc5217SJeff Kirsher stands for weight 8 (the most prioritised); 1 stands for weight 1(least 5262*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 5263*adfc5217SJeff Kirsher #define XCM_REG_XQM_P_WEIGHT 0x200e4 5264*adfc5217SJeff Kirsher /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 5265*adfc5217SJeff Kirsher stands for weight 8 (the most prioritised); 1 stands for weight 1(least 5266*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 5267*adfc5217SJeff Kirsher #define XCM_REG_XQM_S_WEIGHT 0x200e8 5268*adfc5217SJeff Kirsher /* [RW 28] The CM header value for QM request (primary). */ 5269*adfc5217SJeff Kirsher #define XCM_REG_XQM_XCM_HDR_P 0x200a0 5270*adfc5217SJeff Kirsher /* [RW 28] The CM header value for QM request (secondary). */ 5271*adfc5217SJeff Kirsher #define XCM_REG_XQM_XCM_HDR_S 0x200a4 5272*adfc5217SJeff Kirsher /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 5273*adfc5217SJeff Kirsher acknowledge output is deasserted; all other signals are treated as usual; 5274*adfc5217SJeff Kirsher if 1 - normal activity. */ 5275*adfc5217SJeff Kirsher #define XCM_REG_XQM_XCM_IFEN 0x20014 5276*adfc5217SJeff Kirsher /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 5277*adfc5217SJeff Kirsher acknowledge output is deasserted; all other signals are treated as usual; 5278*adfc5217SJeff Kirsher if 1 - normal activity. */ 5279*adfc5217SJeff Kirsher #define XCM_REG_XSDM_IFEN 0x20018 5280*adfc5217SJeff Kirsher /* [RC 1] Set at message length mismatch (relative to last indication) at 5281*adfc5217SJeff Kirsher the SDM interface. */ 5282*adfc5217SJeff Kirsher #define XCM_REG_XSDM_LENGTH_MIS 0x20220 5283*adfc5217SJeff Kirsher /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for 5284*adfc5217SJeff Kirsher weight 8 (the most prioritised); 1 stands for weight 1(least 5285*adfc5217SJeff Kirsher prioritised); 2 stands for weight 2; tc. */ 5286*adfc5217SJeff Kirsher #define XCM_REG_XSDM_WEIGHT 0x200e0 5287*adfc5217SJeff Kirsher /* [RW 17] Indirect access to the descriptor table of the XX protection 5288*adfc5217SJeff Kirsher mechanism. The fields are: [5:0] - message length; 11:6] - message 5289*adfc5217SJeff Kirsher pointer; 16:12] - next pointer. */ 5290*adfc5217SJeff Kirsher #define XCM_REG_XX_DESCR_TABLE 0x20480 5291*adfc5217SJeff Kirsher #define XCM_REG_XX_DESCR_TABLE_SIZE 32 5292*adfc5217SJeff Kirsher /* [R 6] Used to read the XX protection Free counter. */ 5293*adfc5217SJeff Kirsher #define XCM_REG_XX_FREE 0x20240 5294*adfc5217SJeff Kirsher /* [RW 6] Initial value for the credit counter; responsible for fulfilling 5295*adfc5217SJeff Kirsher of the Input Stage XX protection buffer by the XX protection pending 5296*adfc5217SJeff Kirsher messages. Max credit available - 3.Write writes the initial credit value; 5297*adfc5217SJeff Kirsher read returns the current value of the credit counter. Must be initialized 5298*adfc5217SJeff Kirsher to 2 at start-up. */ 5299*adfc5217SJeff Kirsher #define XCM_REG_XX_INIT_CRD 0x20424 5300*adfc5217SJeff Kirsher /* [RW 6] The maximum number of pending messages; which may be stored in XX 5301*adfc5217SJeff Kirsher protection. ~xcm_registers_xx_free.xx_free read on read. */ 5302*adfc5217SJeff Kirsher #define XCM_REG_XX_MSG_NUM 0x20428 5303*adfc5217SJeff Kirsher /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 5304*adfc5217SJeff Kirsher #define XCM_REG_XX_OVFL_EVNT_ID 0x20058 5305*adfc5217SJeff Kirsher #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS (0x1<<0) 5306*adfc5217SJeff Kirsher #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS (0x1<<1) 5307*adfc5217SJeff Kirsher #define XMAC_CTRL_REG_CORE_LOCAL_LPBK (0x1<<3) 5308*adfc5217SJeff Kirsher #define XMAC_CTRL_REG_RX_EN (0x1<<1) 5309*adfc5217SJeff Kirsher #define XMAC_CTRL_REG_SOFT_RESET (0x1<<6) 5310*adfc5217SJeff Kirsher #define XMAC_CTRL_REG_TX_EN (0x1<<0) 5311*adfc5217SJeff Kirsher #define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN (0x1<<18) 5312*adfc5217SJeff Kirsher #define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN (0x1<<17) 5313*adfc5217SJeff Kirsher #define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN (0x1<<0) 5314*adfc5217SJeff Kirsher #define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN (0x1<<3) 5315*adfc5217SJeff Kirsher #define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN (0x1<<4) 5316*adfc5217SJeff Kirsher #define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN (0x1<<5) 5317*adfc5217SJeff Kirsher #define XMAC_REG_CLEAR_RX_LSS_STATUS 0x60 5318*adfc5217SJeff Kirsher #define XMAC_REG_CTRL 0 5319*adfc5217SJeff Kirsher /* [RW 16] Upper 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC 5320*adfc5217SJeff Kirsher * packets transmitted by the MAC */ 5321*adfc5217SJeff Kirsher #define XMAC_REG_CTRL_SA_HI 0x2c 5322*adfc5217SJeff Kirsher /* [RW 32] Lower 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC 5323*adfc5217SJeff Kirsher * packets transmitted by the MAC */ 5324*adfc5217SJeff Kirsher #define XMAC_REG_CTRL_SA_LO 0x28 5325*adfc5217SJeff Kirsher #define XMAC_REG_PAUSE_CTRL 0x68 5326*adfc5217SJeff Kirsher #define XMAC_REG_PFC_CTRL 0x70 5327*adfc5217SJeff Kirsher #define XMAC_REG_PFC_CTRL_HI 0x74 5328*adfc5217SJeff Kirsher #define XMAC_REG_RX_LSS_STATUS 0x58 5329*adfc5217SJeff Kirsher /* [RW 14] Maximum packet size in receive direction; exclusive of preamble & 5330*adfc5217SJeff Kirsher * CRC in strip mode */ 5331*adfc5217SJeff Kirsher #define XMAC_REG_RX_MAX_SIZE 0x40 5332*adfc5217SJeff Kirsher #define XMAC_REG_TX_CTRL 0x20 5333*adfc5217SJeff Kirsher /* [RW 16] Indirect access to the XX table of the XX protection mechanism. 5334*adfc5217SJeff Kirsher The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] - 5335*adfc5217SJeff Kirsher header pointer. */ 5336*adfc5217SJeff Kirsher #define XCM_REG_XX_TABLE 0x20500 5337*adfc5217SJeff Kirsher /* [RW 8] The event id for aggregated interrupt 0 */ 5338*adfc5217SJeff Kirsher #define XSDM_REG_AGG_INT_EVENT_0 0x166038 5339*adfc5217SJeff Kirsher #define XSDM_REG_AGG_INT_EVENT_1 0x16603c 5340*adfc5217SJeff Kirsher #define XSDM_REG_AGG_INT_EVENT_10 0x166060 5341*adfc5217SJeff Kirsher #define XSDM_REG_AGG_INT_EVENT_11 0x166064 5342*adfc5217SJeff Kirsher #define XSDM_REG_AGG_INT_EVENT_12 0x166068 5343*adfc5217SJeff Kirsher #define XSDM_REG_AGG_INT_EVENT_13 0x16606c 5344*adfc5217SJeff Kirsher #define XSDM_REG_AGG_INT_EVENT_14 0x166070 5345*adfc5217SJeff Kirsher #define XSDM_REG_AGG_INT_EVENT_2 0x166040 5346*adfc5217SJeff Kirsher #define XSDM_REG_AGG_INT_EVENT_3 0x166044 5347*adfc5217SJeff Kirsher #define XSDM_REG_AGG_INT_EVENT_4 0x166048 5348*adfc5217SJeff Kirsher #define XSDM_REG_AGG_INT_EVENT_5 0x16604c 5349*adfc5217SJeff Kirsher #define XSDM_REG_AGG_INT_EVENT_6 0x166050 5350*adfc5217SJeff Kirsher #define XSDM_REG_AGG_INT_EVENT_7 0x166054 5351*adfc5217SJeff Kirsher #define XSDM_REG_AGG_INT_EVENT_8 0x166058 5352*adfc5217SJeff Kirsher #define XSDM_REG_AGG_INT_EVENT_9 0x16605c 5353*adfc5217SJeff Kirsher /* [RW 1] For each aggregated interrupt index whether the mode is normal (0) 5354*adfc5217SJeff Kirsher or auto-mask-mode (1) */ 5355*adfc5217SJeff Kirsher #define XSDM_REG_AGG_INT_MODE_0 0x1661b8 5356*adfc5217SJeff Kirsher #define XSDM_REG_AGG_INT_MODE_1 0x1661bc 5357*adfc5217SJeff Kirsher /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 5358*adfc5217SJeff Kirsher #define XSDM_REG_CFC_RSP_START_ADDR 0x166008 5359*adfc5217SJeff Kirsher /* [RW 16] The maximum value of the completion counter #0 */ 5360*adfc5217SJeff Kirsher #define XSDM_REG_CMP_COUNTER_MAX0 0x16601c 5361*adfc5217SJeff Kirsher /* [RW 16] The maximum value of the completion counter #1 */ 5362*adfc5217SJeff Kirsher #define XSDM_REG_CMP_COUNTER_MAX1 0x166020 5363*adfc5217SJeff Kirsher /* [RW 16] The maximum value of the completion counter #2 */ 5364*adfc5217SJeff Kirsher #define XSDM_REG_CMP_COUNTER_MAX2 0x166024 5365*adfc5217SJeff Kirsher /* [RW 16] The maximum value of the completion counter #3 */ 5366*adfc5217SJeff Kirsher #define XSDM_REG_CMP_COUNTER_MAX3 0x166028 5367*adfc5217SJeff Kirsher /* [RW 13] The start address in the internal RAM for the completion 5368*adfc5217SJeff Kirsher counters. */ 5369*adfc5217SJeff Kirsher #define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c 5370*adfc5217SJeff Kirsher #define XSDM_REG_ENABLE_IN1 0x166238 5371*adfc5217SJeff Kirsher #define XSDM_REG_ENABLE_IN2 0x16623c 5372*adfc5217SJeff Kirsher #define XSDM_REG_ENABLE_OUT1 0x166240 5373*adfc5217SJeff Kirsher #define XSDM_REG_ENABLE_OUT2 0x166244 5374*adfc5217SJeff Kirsher /* [RW 4] The initial number of messages that can be sent to the pxp control 5375*adfc5217SJeff Kirsher interface without receiving any ACK. */ 5376*adfc5217SJeff Kirsher #define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc 5377*adfc5217SJeff Kirsher /* [ST 32] The number of ACK after placement messages received */ 5378*adfc5217SJeff Kirsher #define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c 5379*adfc5217SJeff Kirsher /* [ST 32] The number of packet end messages received from the parser */ 5380*adfc5217SJeff Kirsher #define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274 5381*adfc5217SJeff Kirsher /* [ST 32] The number of requests received from the pxp async if */ 5382*adfc5217SJeff Kirsher #define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278 5383*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 0 */ 5384*adfc5217SJeff Kirsher #define XSDM_REG_NUM_OF_Q0_CMD 0x166248 5385*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 10 */ 5386*adfc5217SJeff Kirsher #define XSDM_REG_NUM_OF_Q10_CMD 0x16626c 5387*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 11 */ 5388*adfc5217SJeff Kirsher #define XSDM_REG_NUM_OF_Q11_CMD 0x166270 5389*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 1 */ 5390*adfc5217SJeff Kirsher #define XSDM_REG_NUM_OF_Q1_CMD 0x16624c 5391*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 3 */ 5392*adfc5217SJeff Kirsher #define XSDM_REG_NUM_OF_Q3_CMD 0x166250 5393*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 4 */ 5394*adfc5217SJeff Kirsher #define XSDM_REG_NUM_OF_Q4_CMD 0x166254 5395*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 5 */ 5396*adfc5217SJeff Kirsher #define XSDM_REG_NUM_OF_Q5_CMD 0x166258 5397*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 6 */ 5398*adfc5217SJeff Kirsher #define XSDM_REG_NUM_OF_Q6_CMD 0x16625c 5399*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 7 */ 5400*adfc5217SJeff Kirsher #define XSDM_REG_NUM_OF_Q7_CMD 0x166260 5401*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 8 */ 5402*adfc5217SJeff Kirsher #define XSDM_REG_NUM_OF_Q8_CMD 0x166264 5403*adfc5217SJeff Kirsher /* [ST 32] The number of commands received in queue 9 */ 5404*adfc5217SJeff Kirsher #define XSDM_REG_NUM_OF_Q9_CMD 0x166268 5405*adfc5217SJeff Kirsher /* [RW 13] The start address in the internal RAM for queue counters */ 5406*adfc5217SJeff Kirsher #define XSDM_REG_Q_COUNTER_START_ADDR 0x166010 5407*adfc5217SJeff Kirsher /* [W 17] Generate an operation after completion; bit-16 is 5408*adfc5217SJeff Kirsher * AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and 5409*adfc5217SJeff Kirsher * bits 4:0 are the T124Param[4:0] */ 5410*adfc5217SJeff Kirsher #define XSDM_REG_OPERATION_GEN 0x1664c4 5411*adfc5217SJeff Kirsher /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 5412*adfc5217SJeff Kirsher #define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548 5413*adfc5217SJeff Kirsher /* [R 1] parser fifo empty in sdm_sync block */ 5414*adfc5217SJeff Kirsher #define XSDM_REG_SYNC_PARSER_EMPTY 0x166550 5415*adfc5217SJeff Kirsher /* [R 1] parser serial fifo empty in sdm_sync block */ 5416*adfc5217SJeff Kirsher #define XSDM_REG_SYNC_SYNC_EMPTY 0x166558 5417*adfc5217SJeff Kirsher /* [RW 32] Tick for timer counter. Applicable only when 5418*adfc5217SJeff Kirsher ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */ 5419*adfc5217SJeff Kirsher #define XSDM_REG_TIMER_TICK 0x166000 5420*adfc5217SJeff Kirsher /* [RW 32] Interrupt mask register #0 read/write */ 5421*adfc5217SJeff Kirsher #define XSDM_REG_XSDM_INT_MASK_0 0x16629c 5422*adfc5217SJeff Kirsher #define XSDM_REG_XSDM_INT_MASK_1 0x1662ac 5423*adfc5217SJeff Kirsher /* [R 32] Interrupt register #0 read */ 5424*adfc5217SJeff Kirsher #define XSDM_REG_XSDM_INT_STS_0 0x166290 5425*adfc5217SJeff Kirsher #define XSDM_REG_XSDM_INT_STS_1 0x1662a0 5426*adfc5217SJeff Kirsher /* [RW 11] Parity mask register #0 read/write */ 5427*adfc5217SJeff Kirsher #define XSDM_REG_XSDM_PRTY_MASK 0x1662bc 5428*adfc5217SJeff Kirsher /* [R 11] Parity register #0 read */ 5429*adfc5217SJeff Kirsher #define XSDM_REG_XSDM_PRTY_STS 0x1662b0 5430*adfc5217SJeff Kirsher /* [RC 11] Parity register #0 read clear */ 5431*adfc5217SJeff Kirsher #define XSDM_REG_XSDM_PRTY_STS_CLR 0x1662b4 5432*adfc5217SJeff Kirsher /* [RW 5] The number of time_slots in the arbitration cycle */ 5433*adfc5217SJeff Kirsher #define XSEM_REG_ARB_CYCLE_SIZE 0x280034 5434*adfc5217SJeff Kirsher /* [RW 3] The source that is associated with arbitration element 0. Source 5435*adfc5217SJeff Kirsher decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5436*adfc5217SJeff Kirsher sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 5437*adfc5217SJeff Kirsher #define XSEM_REG_ARB_ELEMENT0 0x280020 5438*adfc5217SJeff Kirsher /* [RW 3] The source that is associated with arbitration element 1. Source 5439*adfc5217SJeff Kirsher decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5440*adfc5217SJeff Kirsher sleeping thread with priority 1; 4- sleeping thread with priority 2. 5441*adfc5217SJeff Kirsher Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */ 5442*adfc5217SJeff Kirsher #define XSEM_REG_ARB_ELEMENT1 0x280024 5443*adfc5217SJeff Kirsher /* [RW 3] The source that is associated with arbitration element 2. Source 5444*adfc5217SJeff Kirsher decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5445*adfc5217SJeff Kirsher sleeping thread with priority 1; 4- sleeping thread with priority 2. 5446*adfc5217SJeff Kirsher Could not be equal to register ~xsem_registers_arb_element0.arb_element0 5447*adfc5217SJeff Kirsher and ~xsem_registers_arb_element1.arb_element1 */ 5448*adfc5217SJeff Kirsher #define XSEM_REG_ARB_ELEMENT2 0x280028 5449*adfc5217SJeff Kirsher /* [RW 3] The source that is associated with arbitration element 3. Source 5450*adfc5217SJeff Kirsher decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5451*adfc5217SJeff Kirsher sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 5452*adfc5217SJeff Kirsher not be equal to register ~xsem_registers_arb_element0.arb_element0 and 5453*adfc5217SJeff Kirsher ~xsem_registers_arb_element1.arb_element1 and 5454*adfc5217SJeff Kirsher ~xsem_registers_arb_element2.arb_element2 */ 5455*adfc5217SJeff Kirsher #define XSEM_REG_ARB_ELEMENT3 0x28002c 5456*adfc5217SJeff Kirsher /* [RW 3] The source that is associated with arbitration element 4. Source 5457*adfc5217SJeff Kirsher decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5458*adfc5217SJeff Kirsher sleeping thread with priority 1; 4- sleeping thread with priority 2. 5459*adfc5217SJeff Kirsher Could not be equal to register ~xsem_registers_arb_element0.arb_element0 5460*adfc5217SJeff Kirsher and ~xsem_registers_arb_element1.arb_element1 and 5461*adfc5217SJeff Kirsher ~xsem_registers_arb_element2.arb_element2 and 5462*adfc5217SJeff Kirsher ~xsem_registers_arb_element3.arb_element3 */ 5463*adfc5217SJeff Kirsher #define XSEM_REG_ARB_ELEMENT4 0x280030 5464*adfc5217SJeff Kirsher #define XSEM_REG_ENABLE_IN 0x2800a4 5465*adfc5217SJeff Kirsher #define XSEM_REG_ENABLE_OUT 0x2800a8 5466*adfc5217SJeff Kirsher /* [RW 32] This address space contains all registers and memories that are 5467*adfc5217SJeff Kirsher placed in SEM_FAST block. The SEM_FAST registers are described in 5468*adfc5217SJeff Kirsher appendix B. In order to access the sem_fast registers the base address 5469*adfc5217SJeff Kirsher ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 5470*adfc5217SJeff Kirsher #define XSEM_REG_FAST_MEMORY 0x2a0000 5471*adfc5217SJeff Kirsher /* [RW 1] Disables input messages from FIC0 May be updated during run_time 5472*adfc5217SJeff Kirsher by the microcode */ 5473*adfc5217SJeff Kirsher #define XSEM_REG_FIC0_DISABLE 0x280224 5474*adfc5217SJeff Kirsher /* [RW 1] Disables input messages from FIC1 May be updated during run_time 5475*adfc5217SJeff Kirsher by the microcode */ 5476*adfc5217SJeff Kirsher #define XSEM_REG_FIC1_DISABLE 0x280234 5477*adfc5217SJeff Kirsher /* [RW 15] Interrupt table Read and write access to it is not possible in 5478*adfc5217SJeff Kirsher the middle of the work */ 5479*adfc5217SJeff Kirsher #define XSEM_REG_INT_TABLE 0x280400 5480*adfc5217SJeff Kirsher /* [ST 24] Statistics register. The number of messages that entered through 5481*adfc5217SJeff Kirsher FIC0 */ 5482*adfc5217SJeff Kirsher #define XSEM_REG_MSG_NUM_FIC0 0x280000 5483*adfc5217SJeff Kirsher /* [ST 24] Statistics register. The number of messages that entered through 5484*adfc5217SJeff Kirsher FIC1 */ 5485*adfc5217SJeff Kirsher #define XSEM_REG_MSG_NUM_FIC1 0x280004 5486*adfc5217SJeff Kirsher /* [ST 24] Statistics register. The number of messages that were sent to 5487*adfc5217SJeff Kirsher FOC0 */ 5488*adfc5217SJeff Kirsher #define XSEM_REG_MSG_NUM_FOC0 0x280008 5489*adfc5217SJeff Kirsher /* [ST 24] Statistics register. The number of messages that were sent to 5490*adfc5217SJeff Kirsher FOC1 */ 5491*adfc5217SJeff Kirsher #define XSEM_REG_MSG_NUM_FOC1 0x28000c 5492*adfc5217SJeff Kirsher /* [ST 24] Statistics register. The number of messages that were sent to 5493*adfc5217SJeff Kirsher FOC2 */ 5494*adfc5217SJeff Kirsher #define XSEM_REG_MSG_NUM_FOC2 0x280010 5495*adfc5217SJeff Kirsher /* [ST 24] Statistics register. The number of messages that were sent to 5496*adfc5217SJeff Kirsher FOC3 */ 5497*adfc5217SJeff Kirsher #define XSEM_REG_MSG_NUM_FOC3 0x280014 5498*adfc5217SJeff Kirsher /* [RW 1] Disables input messages from the passive buffer May be updated 5499*adfc5217SJeff Kirsher during run_time by the microcode */ 5500*adfc5217SJeff Kirsher #define XSEM_REG_PAS_DISABLE 0x28024c 5501*adfc5217SJeff Kirsher /* [WB 128] Debug only. Passive buffer memory */ 5502*adfc5217SJeff Kirsher #define XSEM_REG_PASSIVE_BUFFER 0x282000 5503*adfc5217SJeff Kirsher /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 5504*adfc5217SJeff Kirsher #define XSEM_REG_PRAM 0x2c0000 5505*adfc5217SJeff Kirsher /* [R 16] Valid sleeping threads indication have bit per thread */ 5506*adfc5217SJeff Kirsher #define XSEM_REG_SLEEP_THREADS_VALID 0x28026c 5507*adfc5217SJeff Kirsher /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 5508*adfc5217SJeff Kirsher #define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0 5509*adfc5217SJeff Kirsher /* [RW 16] List of free threads . There is a bit per thread. */ 5510*adfc5217SJeff Kirsher #define XSEM_REG_THREADS_LIST 0x2802e4 5511*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 0 */ 5512*adfc5217SJeff Kirsher #define XSEM_REG_TS_0_AS 0x280038 5513*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 10 */ 5514*adfc5217SJeff Kirsher #define XSEM_REG_TS_10_AS 0x280060 5515*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 11 */ 5516*adfc5217SJeff Kirsher #define XSEM_REG_TS_11_AS 0x280064 5517*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 12 */ 5518*adfc5217SJeff Kirsher #define XSEM_REG_TS_12_AS 0x280068 5519*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 13 */ 5520*adfc5217SJeff Kirsher #define XSEM_REG_TS_13_AS 0x28006c 5521*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 14 */ 5522*adfc5217SJeff Kirsher #define XSEM_REG_TS_14_AS 0x280070 5523*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 15 */ 5524*adfc5217SJeff Kirsher #define XSEM_REG_TS_15_AS 0x280074 5525*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 16 */ 5526*adfc5217SJeff Kirsher #define XSEM_REG_TS_16_AS 0x280078 5527*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 17 */ 5528*adfc5217SJeff Kirsher #define XSEM_REG_TS_17_AS 0x28007c 5529*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 18 */ 5530*adfc5217SJeff Kirsher #define XSEM_REG_TS_18_AS 0x280080 5531*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 1 */ 5532*adfc5217SJeff Kirsher #define XSEM_REG_TS_1_AS 0x28003c 5533*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 2 */ 5534*adfc5217SJeff Kirsher #define XSEM_REG_TS_2_AS 0x280040 5535*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 3 */ 5536*adfc5217SJeff Kirsher #define XSEM_REG_TS_3_AS 0x280044 5537*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 4 */ 5538*adfc5217SJeff Kirsher #define XSEM_REG_TS_4_AS 0x280048 5539*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 5 */ 5540*adfc5217SJeff Kirsher #define XSEM_REG_TS_5_AS 0x28004c 5541*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 6 */ 5542*adfc5217SJeff Kirsher #define XSEM_REG_TS_6_AS 0x280050 5543*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 7 */ 5544*adfc5217SJeff Kirsher #define XSEM_REG_TS_7_AS 0x280054 5545*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 8 */ 5546*adfc5217SJeff Kirsher #define XSEM_REG_TS_8_AS 0x280058 5547*adfc5217SJeff Kirsher /* [RW 3] The arbitration scheme of time_slot 9 */ 5548*adfc5217SJeff Kirsher #define XSEM_REG_TS_9_AS 0x28005c 5549*adfc5217SJeff Kirsher /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 5550*adfc5217SJeff Kirsher * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ 5551*adfc5217SJeff Kirsher #define XSEM_REG_VFPF_ERR_NUM 0x280380 5552*adfc5217SJeff Kirsher /* [RW 32] Interrupt mask register #0 read/write */ 5553*adfc5217SJeff Kirsher #define XSEM_REG_XSEM_INT_MASK_0 0x280110 5554*adfc5217SJeff Kirsher #define XSEM_REG_XSEM_INT_MASK_1 0x280120 5555*adfc5217SJeff Kirsher /* [R 32] Interrupt register #0 read */ 5556*adfc5217SJeff Kirsher #define XSEM_REG_XSEM_INT_STS_0 0x280104 5557*adfc5217SJeff Kirsher #define XSEM_REG_XSEM_INT_STS_1 0x280114 5558*adfc5217SJeff Kirsher /* [RW 32] Parity mask register #0 read/write */ 5559*adfc5217SJeff Kirsher #define XSEM_REG_XSEM_PRTY_MASK_0 0x280130 5560*adfc5217SJeff Kirsher #define XSEM_REG_XSEM_PRTY_MASK_1 0x280140 5561*adfc5217SJeff Kirsher /* [R 32] Parity register #0 read */ 5562*adfc5217SJeff Kirsher #define XSEM_REG_XSEM_PRTY_STS_0 0x280124 5563*adfc5217SJeff Kirsher #define XSEM_REG_XSEM_PRTY_STS_1 0x280134 5564*adfc5217SJeff Kirsher /* [RC 32] Parity register #0 read clear */ 5565*adfc5217SJeff Kirsher #define XSEM_REG_XSEM_PRTY_STS_CLR_0 0x280128 5566*adfc5217SJeff Kirsher #define XSEM_REG_XSEM_PRTY_STS_CLR_1 0x280138 5567*adfc5217SJeff Kirsher #define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0) 5568*adfc5217SJeff Kirsher #define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1) 5569*adfc5217SJeff Kirsher #define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) 5570*adfc5217SJeff Kirsher #define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0) 5571*adfc5217SJeff Kirsher #define MCPR_NVM_COMMAND_DOIT (1L<<4) 5572*adfc5217SJeff Kirsher #define MCPR_NVM_COMMAND_DONE (1L<<3) 5573*adfc5217SJeff Kirsher #define MCPR_NVM_COMMAND_FIRST (1L<<7) 5574*adfc5217SJeff Kirsher #define MCPR_NVM_COMMAND_LAST (1L<<8) 5575*adfc5217SJeff Kirsher #define MCPR_NVM_COMMAND_WR (1L<<5) 5576*adfc5217SJeff Kirsher #define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9) 5577*adfc5217SJeff Kirsher #define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) 5578*adfc5217SJeff Kirsher #define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) 5579*adfc5217SJeff Kirsher #define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3) 5580*adfc5217SJeff Kirsher #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3) 5581*adfc5217SJeff Kirsher #define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3) 5582*adfc5217SJeff Kirsher #define BIGMAC_REGISTER_RX_CONTROL (0x21<<3) 5583*adfc5217SJeff Kirsher #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3) 5584*adfc5217SJeff Kirsher #define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3) 5585*adfc5217SJeff Kirsher #define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3) 5586*adfc5217SJeff Kirsher #define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3) 5587*adfc5217SJeff Kirsher #define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3) 5588*adfc5217SJeff Kirsher #define BIGMAC_REGISTER_TX_CONTROL (0x07<<3) 5589*adfc5217SJeff Kirsher #define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3) 5590*adfc5217SJeff Kirsher #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3) 5591*adfc5217SJeff Kirsher #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3) 5592*adfc5217SJeff Kirsher #define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3) 5593*adfc5217SJeff Kirsher #define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3) 5594*adfc5217SJeff Kirsher #define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3) 5595*adfc5217SJeff Kirsher #define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3) 5596*adfc5217SJeff Kirsher #define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3) 5597*adfc5217SJeff Kirsher #define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3) 5598*adfc5217SJeff Kirsher #define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3) 5599*adfc5217SJeff Kirsher #define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3) 5600*adfc5217SJeff Kirsher #define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3) 5601*adfc5217SJeff Kirsher #define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3) 5602*adfc5217SJeff Kirsher #define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3) 5603*adfc5217SJeff Kirsher #define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3) 5604*adfc5217SJeff Kirsher #define BIGMAC2_REGISTER_RX_STAT_GRPP (0x51<<3) 5605*adfc5217SJeff Kirsher #define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3) 5606*adfc5217SJeff Kirsher #define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3) 5607*adfc5217SJeff Kirsher #define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3) 5608*adfc5217SJeff Kirsher #define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3) 5609*adfc5217SJeff Kirsher #define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3) 5610*adfc5217SJeff Kirsher #define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3) 5611*adfc5217SJeff Kirsher #define BIGMAC2_REGISTER_TX_STAT_GTPP (0x24<<3) 5612*adfc5217SJeff Kirsher #define EMAC_LED_1000MB_OVERRIDE (1L<<1) 5613*adfc5217SJeff Kirsher #define EMAC_LED_100MB_OVERRIDE (1L<<2) 5614*adfc5217SJeff Kirsher #define EMAC_LED_10MB_OVERRIDE (1L<<3) 5615*adfc5217SJeff Kirsher #define EMAC_LED_2500MB_OVERRIDE (1L<<12) 5616*adfc5217SJeff Kirsher #define EMAC_LED_OVERRIDE (1L<<0) 5617*adfc5217SJeff Kirsher #define EMAC_LED_TRAFFIC (1L<<6) 5618*adfc5217SJeff Kirsher #define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26) 5619*adfc5217SJeff Kirsher #define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26) 5620*adfc5217SJeff Kirsher #define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26) 5621*adfc5217SJeff Kirsher #define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26) 5622*adfc5217SJeff Kirsher #define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26) 5623*adfc5217SJeff Kirsher #define EMAC_MDIO_COMM_DATA (0xffffL<<0) 5624*adfc5217SJeff Kirsher #define EMAC_MDIO_COMM_START_BUSY (1L<<29) 5625*adfc5217SJeff Kirsher #define EMAC_MDIO_MODE_AUTO_POLL (1L<<4) 5626*adfc5217SJeff Kirsher #define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31) 5627*adfc5217SJeff Kirsher #define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL<<16) 5628*adfc5217SJeff Kirsher #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16 5629*adfc5217SJeff Kirsher #define EMAC_MDIO_STATUS_10MB (1L<<1) 5630*adfc5217SJeff Kirsher #define EMAC_MODE_25G_MODE (1L<<5) 5631*adfc5217SJeff Kirsher #define EMAC_MODE_HALF_DUPLEX (1L<<1) 5632*adfc5217SJeff Kirsher #define EMAC_MODE_PORT_GMII (2L<<2) 5633*adfc5217SJeff Kirsher #define EMAC_MODE_PORT_MII (1L<<2) 5634*adfc5217SJeff Kirsher #define EMAC_MODE_PORT_MII_10M (3L<<2) 5635*adfc5217SJeff Kirsher #define EMAC_MODE_RESET (1L<<0) 5636*adfc5217SJeff Kirsher #define EMAC_REG_EMAC_LED 0xc 5637*adfc5217SJeff Kirsher #define EMAC_REG_EMAC_MAC_MATCH 0x10 5638*adfc5217SJeff Kirsher #define EMAC_REG_EMAC_MDIO_COMM 0xac 5639*adfc5217SJeff Kirsher #define EMAC_REG_EMAC_MDIO_MODE 0xb4 5640*adfc5217SJeff Kirsher #define EMAC_REG_EMAC_MDIO_STATUS 0xb0 5641*adfc5217SJeff Kirsher #define EMAC_REG_EMAC_MODE 0x0 5642*adfc5217SJeff Kirsher #define EMAC_REG_EMAC_RX_MODE 0xc8 5643*adfc5217SJeff Kirsher #define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c 5644*adfc5217SJeff Kirsher #define EMAC_REG_EMAC_RX_STAT_AC 0x180 5645*adfc5217SJeff Kirsher #define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4 5646*adfc5217SJeff Kirsher #define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23 5647*adfc5217SJeff Kirsher #define EMAC_REG_EMAC_TX_MODE 0xbc 5648*adfc5217SJeff Kirsher #define EMAC_REG_EMAC_TX_STAT_AC 0x280 5649*adfc5217SJeff Kirsher #define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22 5650*adfc5217SJeff Kirsher #define EMAC_REG_RX_PFC_MODE 0x320 5651*adfc5217SJeff Kirsher #define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L<<2) 5652*adfc5217SJeff Kirsher #define EMAC_REG_RX_PFC_MODE_RX_EN (1L<<1) 5653*adfc5217SJeff Kirsher #define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0) 5654*adfc5217SJeff Kirsher #define EMAC_REG_RX_PFC_PARAM 0x324 5655*adfc5217SJeff Kirsher #define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0 5656*adfc5217SJeff Kirsher #define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16 5657*adfc5217SJeff Kirsher #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328 5658*adfc5217SJeff Kirsher #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0) 5659*adfc5217SJeff Kirsher #define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330 5660*adfc5217SJeff Kirsher #define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0) 5661*adfc5217SJeff Kirsher #define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c 5662*adfc5217SJeff Kirsher #define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0) 5663*adfc5217SJeff Kirsher #define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334 5664*adfc5217SJeff Kirsher #define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0) 5665*adfc5217SJeff Kirsher #define EMAC_RX_MODE_FLOW_EN (1L<<2) 5666*adfc5217SJeff Kirsher #define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3) 5667*adfc5217SJeff Kirsher #define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) 5668*adfc5217SJeff Kirsher #define EMAC_RX_MODE_PROMISCUOUS (1L<<8) 5669*adfc5217SJeff Kirsher #define EMAC_RX_MODE_RESET (1L<<0) 5670*adfc5217SJeff Kirsher #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) 5671*adfc5217SJeff Kirsher #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) 5672*adfc5217SJeff Kirsher #define EMAC_TX_MODE_FLOW_EN (1L<<4) 5673*adfc5217SJeff Kirsher #define EMAC_TX_MODE_RESET (1L<<0) 5674*adfc5217SJeff Kirsher #define MISC_REGISTERS_GPIO_0 0 5675*adfc5217SJeff Kirsher #define MISC_REGISTERS_GPIO_1 1 5676*adfc5217SJeff Kirsher #define MISC_REGISTERS_GPIO_2 2 5677*adfc5217SJeff Kirsher #define MISC_REGISTERS_GPIO_3 3 5678*adfc5217SJeff Kirsher #define MISC_REGISTERS_GPIO_CLR_POS 16 5679*adfc5217SJeff Kirsher #define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24) 5680*adfc5217SJeff Kirsher #define MISC_REGISTERS_GPIO_FLOAT_POS 24 5681*adfc5217SJeff Kirsher #define MISC_REGISTERS_GPIO_HIGH 1 5682*adfc5217SJeff Kirsher #define MISC_REGISTERS_GPIO_INPUT_HI_Z 2 5683*adfc5217SJeff Kirsher #define MISC_REGISTERS_GPIO_INT_CLR_POS 24 5684*adfc5217SJeff Kirsher #define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0 5685*adfc5217SJeff Kirsher #define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1 5686*adfc5217SJeff Kirsher #define MISC_REGISTERS_GPIO_INT_SET_POS 16 5687*adfc5217SJeff Kirsher #define MISC_REGISTERS_GPIO_LOW 0 5688*adfc5217SJeff Kirsher #define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1 5689*adfc5217SJeff Kirsher #define MISC_REGISTERS_GPIO_OUTPUT_LOW 0 5690*adfc5217SJeff Kirsher #define MISC_REGISTERS_GPIO_PORT_SHIFT 4 5691*adfc5217SJeff Kirsher #define MISC_REGISTERS_GPIO_SET_POS 8 5692*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588 5693*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29) 5694*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7) 5695*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1<<26) 5696*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27) 5697*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_1_SET 0x584 5698*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598 5699*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_MSTAT0 (0x1<<24) 5700*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_MSTAT1 (0x1<<25) 5701*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_PGLC (0x1<<19) 5702*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_RST_ATC (0x1<<17) 5703*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0) 5704*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1) 5705*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2) 5706*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14) 5707*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3) 5708*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15) 5709*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4) 5710*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6) 5711*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8) 5712*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7) 5713*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5) 5714*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13) 5715*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11) 5716*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO (0x1<<13) 5717*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9) 5718*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_SET 0x594 5719*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_UMAC0 (0x1<<20) 5720*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_UMAC1 (0x1<<21) 5721*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_XMAC (0x1<<22) 5722*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT (0x1<<23) 5723*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8 5724*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1) 5725*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2) 5726*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3) 5727*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0) 5728*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5) 5729*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6) 5730*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7) 5731*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4) 5732*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8) 5733*adfc5217SJeff Kirsher #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4 5734*adfc5217SJeff Kirsher #define MISC_REGISTERS_SPIO_4 4 5735*adfc5217SJeff Kirsher #define MISC_REGISTERS_SPIO_5 5 5736*adfc5217SJeff Kirsher #define MISC_REGISTERS_SPIO_7 7 5737*adfc5217SJeff Kirsher #define MISC_REGISTERS_SPIO_CLR_POS 16 5738*adfc5217SJeff Kirsher #define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24) 5739*adfc5217SJeff Kirsher #define MISC_REGISTERS_SPIO_FLOAT_POS 24 5740*adfc5217SJeff Kirsher #define MISC_REGISTERS_SPIO_INPUT_HI_Z 2 5741*adfc5217SJeff Kirsher #define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16 5742*adfc5217SJeff Kirsher #define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1 5743*adfc5217SJeff Kirsher #define MISC_REGISTERS_SPIO_OUTPUT_LOW 0 5744*adfc5217SJeff Kirsher #define MISC_REGISTERS_SPIO_SET_POS 8 5745*adfc5217SJeff Kirsher #define HW_LOCK_DRV_FLAGS 10 5746*adfc5217SJeff Kirsher #define HW_LOCK_MAX_RESOURCE_VALUE 31 5747*adfc5217SJeff Kirsher #define HW_LOCK_RESOURCE_GPIO 1 5748*adfc5217SJeff Kirsher #define HW_LOCK_RESOURCE_MDIO 0 5749*adfc5217SJeff Kirsher #define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3 5750*adfc5217SJeff Kirsher #define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8 5751*adfc5217SJeff Kirsher #define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9 5752*adfc5217SJeff Kirsher #define HW_LOCK_RESOURCE_SPIO 2 5753*adfc5217SJeff Kirsher #define HW_LOCK_RESOURCE_UNDI 5 5754*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4) 5755*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5) 5756*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18) 5757*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31) 5758*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30) 5759*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9) 5760*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8) 5761*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7) 5762*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6) 5763*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29) 5764*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28) 5765*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1) 5766*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0) 5767*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18) 5768*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11) 5769*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10) 5770*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13) 5771*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12) 5772*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2) 5773*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12) 5774*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28) 5775*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1<<31) 5776*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29) 5777*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30) 5778*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15) 5779*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14) 5780*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14) 5781*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20) 5782*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1<<31) 5783*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30) 5784*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0) 5785*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2) 5786*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3) 5787*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5) 5788*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4) 5789*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3) 5790*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2) 5791*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3) 5792*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2) 5793*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22) 5794*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15) 5795*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27) 5796*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26) 5797*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5) 5798*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4) 5799*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25) 5800*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24) 5801*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29) 5802*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28) 5803*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23) 5804*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22) 5805*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27) 5806*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26) 5807*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21) 5808*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20) 5809*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25) 5810*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24) 5811*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16) 5812*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9) 5813*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8) 5814*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7) 5815*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6) 5816*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11) 5817*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10) 5818*adfc5217SJeff Kirsher 5819*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (0x1<<5) 5820*adfc5217SJeff Kirsher #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (0x1<<9) 5821*adfc5217SJeff Kirsher 5822*adfc5217SJeff Kirsher #define RESERVED_GENERAL_ATTENTION_BIT_0 0 5823*adfc5217SJeff Kirsher 5824*adfc5217SJeff Kirsher #define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0 5825*adfc5217SJeff Kirsher #define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000 5826*adfc5217SJeff Kirsher 5827*adfc5217SJeff Kirsher #define RESERVED_GENERAL_ATTENTION_BIT_6 6 5828*adfc5217SJeff Kirsher #define RESERVED_GENERAL_ATTENTION_BIT_7 7 5829*adfc5217SJeff Kirsher #define RESERVED_GENERAL_ATTENTION_BIT_8 8 5830*adfc5217SJeff Kirsher #define RESERVED_GENERAL_ATTENTION_BIT_9 9 5831*adfc5217SJeff Kirsher #define RESERVED_GENERAL_ATTENTION_BIT_10 10 5832*adfc5217SJeff Kirsher #define RESERVED_GENERAL_ATTENTION_BIT_11 11 5833*adfc5217SJeff Kirsher #define RESERVED_GENERAL_ATTENTION_BIT_12 12 5834*adfc5217SJeff Kirsher #define RESERVED_GENERAL_ATTENTION_BIT_13 13 5835*adfc5217SJeff Kirsher #define RESERVED_GENERAL_ATTENTION_BIT_14 14 5836*adfc5217SJeff Kirsher #define RESERVED_GENERAL_ATTENTION_BIT_15 15 5837*adfc5217SJeff Kirsher #define RESERVED_GENERAL_ATTENTION_BIT_16 16 5838*adfc5217SJeff Kirsher #define RESERVED_GENERAL_ATTENTION_BIT_17 17 5839*adfc5217SJeff Kirsher #define RESERVED_GENERAL_ATTENTION_BIT_18 18 5840*adfc5217SJeff Kirsher #define RESERVED_GENERAL_ATTENTION_BIT_19 19 5841*adfc5217SJeff Kirsher #define RESERVED_GENERAL_ATTENTION_BIT_20 20 5842*adfc5217SJeff Kirsher #define RESERVED_GENERAL_ATTENTION_BIT_21 21 5843*adfc5217SJeff Kirsher 5844*adfc5217SJeff Kirsher /* storm asserts attention bits */ 5845*adfc5217SJeff Kirsher #define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7 5846*adfc5217SJeff Kirsher #define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8 5847*adfc5217SJeff Kirsher #define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9 5848*adfc5217SJeff Kirsher #define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10 5849*adfc5217SJeff Kirsher 5850*adfc5217SJeff Kirsher /* mcp error attention bit */ 5851*adfc5217SJeff Kirsher #define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11 5852*adfc5217SJeff Kirsher 5853*adfc5217SJeff Kirsher /*E1H NIG status sync attention mapped to group 4-7*/ 5854*adfc5217SJeff Kirsher #define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12 5855*adfc5217SJeff Kirsher #define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13 5856*adfc5217SJeff Kirsher #define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14 5857*adfc5217SJeff Kirsher #define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15 5858*adfc5217SJeff Kirsher #define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16 5859*adfc5217SJeff Kirsher #define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17 5860*adfc5217SJeff Kirsher #define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18 5861*adfc5217SJeff Kirsher #define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19 5862*adfc5217SJeff Kirsher 5863*adfc5217SJeff Kirsher 5864*adfc5217SJeff Kirsher #define LATCHED_ATTN_RBCR 23 5865*adfc5217SJeff Kirsher #define LATCHED_ATTN_RBCT 24 5866*adfc5217SJeff Kirsher #define LATCHED_ATTN_RBCN 25 5867*adfc5217SJeff Kirsher #define LATCHED_ATTN_RBCU 26 5868*adfc5217SJeff Kirsher #define LATCHED_ATTN_RBCP 27 5869*adfc5217SJeff Kirsher #define LATCHED_ATTN_TIMEOUT_GRC 28 5870*adfc5217SJeff Kirsher #define LATCHED_ATTN_RSVD_GRC 29 5871*adfc5217SJeff Kirsher #define LATCHED_ATTN_ROM_PARITY_MCP 30 5872*adfc5217SJeff Kirsher #define LATCHED_ATTN_UM_RX_PARITY_MCP 31 5873*adfc5217SJeff Kirsher #define LATCHED_ATTN_UM_TX_PARITY_MCP 32 5874*adfc5217SJeff Kirsher #define LATCHED_ATTN_SCPAD_PARITY_MCP 33 5875*adfc5217SJeff Kirsher 5876*adfc5217SJeff Kirsher #define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32) 5877*adfc5217SJeff Kirsher #define GENERAL_ATTEN_OFFSET(atten_name)\ 5878*adfc5217SJeff Kirsher (1UL << ((94 + atten_name) % 32)) 5879*adfc5217SJeff Kirsher /* 5880*adfc5217SJeff Kirsher * This file defines GRC base address for every block. 5881*adfc5217SJeff Kirsher * This file is included by chipsim, asm microcode and cpp microcode. 5882*adfc5217SJeff Kirsher * These values are used in Design.xml on regBase attribute 5883*adfc5217SJeff Kirsher * Use the base with the generated offsets of specific registers. 5884*adfc5217SJeff Kirsher */ 5885*adfc5217SJeff Kirsher 5886*adfc5217SJeff Kirsher #define GRCBASE_PXPCS 0x000000 5887*adfc5217SJeff Kirsher #define GRCBASE_PCICONFIG 0x002000 5888*adfc5217SJeff Kirsher #define GRCBASE_PCIREG 0x002400 5889*adfc5217SJeff Kirsher #define GRCBASE_EMAC0 0x008000 5890*adfc5217SJeff Kirsher #define GRCBASE_EMAC1 0x008400 5891*adfc5217SJeff Kirsher #define GRCBASE_DBU 0x008800 5892*adfc5217SJeff Kirsher #define GRCBASE_MISC 0x00A000 5893*adfc5217SJeff Kirsher #define GRCBASE_DBG 0x00C000 5894*adfc5217SJeff Kirsher #define GRCBASE_NIG 0x010000 5895*adfc5217SJeff Kirsher #define GRCBASE_XCM 0x020000 5896*adfc5217SJeff Kirsher #define GRCBASE_PRS 0x040000 5897*adfc5217SJeff Kirsher #define GRCBASE_SRCH 0x040400 5898*adfc5217SJeff Kirsher #define GRCBASE_TSDM 0x042000 5899*adfc5217SJeff Kirsher #define GRCBASE_TCM 0x050000 5900*adfc5217SJeff Kirsher #define GRCBASE_BRB1 0x060000 5901*adfc5217SJeff Kirsher #define GRCBASE_MCP 0x080000 5902*adfc5217SJeff Kirsher #define GRCBASE_UPB 0x0C1000 5903*adfc5217SJeff Kirsher #define GRCBASE_CSDM 0x0C2000 5904*adfc5217SJeff Kirsher #define GRCBASE_USDM 0x0C4000 5905*adfc5217SJeff Kirsher #define GRCBASE_CCM 0x0D0000 5906*adfc5217SJeff Kirsher #define GRCBASE_UCM 0x0E0000 5907*adfc5217SJeff Kirsher #define GRCBASE_CDU 0x101000 5908*adfc5217SJeff Kirsher #define GRCBASE_DMAE 0x102000 5909*adfc5217SJeff Kirsher #define GRCBASE_PXP 0x103000 5910*adfc5217SJeff Kirsher #define GRCBASE_CFC 0x104000 5911*adfc5217SJeff Kirsher #define GRCBASE_HC 0x108000 5912*adfc5217SJeff Kirsher #define GRCBASE_PXP2 0x120000 5913*adfc5217SJeff Kirsher #define GRCBASE_PBF 0x140000 5914*adfc5217SJeff Kirsher #define GRCBASE_UMAC0 0x160000 5915*adfc5217SJeff Kirsher #define GRCBASE_UMAC1 0x160400 5916*adfc5217SJeff Kirsher #define GRCBASE_XPB 0x161000 5917*adfc5217SJeff Kirsher #define GRCBASE_MSTAT0 0x162000 5918*adfc5217SJeff Kirsher #define GRCBASE_MSTAT1 0x162800 5919*adfc5217SJeff Kirsher #define GRCBASE_XMAC0 0x163000 5920*adfc5217SJeff Kirsher #define GRCBASE_XMAC1 0x163800 5921*adfc5217SJeff Kirsher #define GRCBASE_TIMERS 0x164000 5922*adfc5217SJeff Kirsher #define GRCBASE_XSDM 0x166000 5923*adfc5217SJeff Kirsher #define GRCBASE_QM 0x168000 5924*adfc5217SJeff Kirsher #define GRCBASE_DQ 0x170000 5925*adfc5217SJeff Kirsher #define GRCBASE_TSEM 0x180000 5926*adfc5217SJeff Kirsher #define GRCBASE_CSEM 0x200000 5927*adfc5217SJeff Kirsher #define GRCBASE_XSEM 0x280000 5928*adfc5217SJeff Kirsher #define GRCBASE_USEM 0x300000 5929*adfc5217SJeff Kirsher #define GRCBASE_MISC_AEU GRCBASE_MISC 5930*adfc5217SJeff Kirsher 5931*adfc5217SJeff Kirsher 5932*adfc5217SJeff Kirsher /* offset of configuration space in the pci core register */ 5933*adfc5217SJeff Kirsher #define PCICFG_OFFSET 0x2000 5934*adfc5217SJeff Kirsher #define PCICFG_VENDOR_ID_OFFSET 0x00 5935*adfc5217SJeff Kirsher #define PCICFG_DEVICE_ID_OFFSET 0x02 5936*adfc5217SJeff Kirsher #define PCICFG_COMMAND_OFFSET 0x04 5937*adfc5217SJeff Kirsher #define PCICFG_COMMAND_IO_SPACE (1<<0) 5938*adfc5217SJeff Kirsher #define PCICFG_COMMAND_MEM_SPACE (1<<1) 5939*adfc5217SJeff Kirsher #define PCICFG_COMMAND_BUS_MASTER (1<<2) 5940*adfc5217SJeff Kirsher #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3) 5941*adfc5217SJeff Kirsher #define PCICFG_COMMAND_MWI_CYCLES (1<<4) 5942*adfc5217SJeff Kirsher #define PCICFG_COMMAND_VGA_SNOOP (1<<5) 5943*adfc5217SJeff Kirsher #define PCICFG_COMMAND_PERR_ENA (1<<6) 5944*adfc5217SJeff Kirsher #define PCICFG_COMMAND_STEPPING (1<<7) 5945*adfc5217SJeff Kirsher #define PCICFG_COMMAND_SERR_ENA (1<<8) 5946*adfc5217SJeff Kirsher #define PCICFG_COMMAND_FAST_B2B (1<<9) 5947*adfc5217SJeff Kirsher #define PCICFG_COMMAND_INT_DISABLE (1<<10) 5948*adfc5217SJeff Kirsher #define PCICFG_COMMAND_RESERVED (0x1f<<11) 5949*adfc5217SJeff Kirsher #define PCICFG_STATUS_OFFSET 0x06 5950*adfc5217SJeff Kirsher #define PCICFG_REVESION_ID_OFFSET 0x08 5951*adfc5217SJeff Kirsher #define PCICFG_CACHE_LINE_SIZE 0x0c 5952*adfc5217SJeff Kirsher #define PCICFG_LATENCY_TIMER 0x0d 5953*adfc5217SJeff Kirsher #define PCICFG_BAR_1_LOW 0x10 5954*adfc5217SJeff Kirsher #define PCICFG_BAR_1_HIGH 0x14 5955*adfc5217SJeff Kirsher #define PCICFG_BAR_2_LOW 0x18 5956*adfc5217SJeff Kirsher #define PCICFG_BAR_2_HIGH 0x1c 5957*adfc5217SJeff Kirsher #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c 5958*adfc5217SJeff Kirsher #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e 5959*adfc5217SJeff Kirsher #define PCICFG_INT_LINE 0x3c 5960*adfc5217SJeff Kirsher #define PCICFG_INT_PIN 0x3d 5961*adfc5217SJeff Kirsher #define PCICFG_PM_CAPABILITY 0x48 5962*adfc5217SJeff Kirsher #define PCICFG_PM_CAPABILITY_VERSION (0x3<<16) 5963*adfc5217SJeff Kirsher #define PCICFG_PM_CAPABILITY_CLOCK (1<<19) 5964*adfc5217SJeff Kirsher #define PCICFG_PM_CAPABILITY_RESERVED (1<<20) 5965*adfc5217SJeff Kirsher #define PCICFG_PM_CAPABILITY_DSI (1<<21) 5966*adfc5217SJeff Kirsher #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22) 5967*adfc5217SJeff Kirsher #define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25) 5968*adfc5217SJeff Kirsher #define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26) 5969*adfc5217SJeff Kirsher #define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27) 5970*adfc5217SJeff Kirsher #define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28) 5971*adfc5217SJeff Kirsher #define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29) 5972*adfc5217SJeff Kirsher #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30) 5973*adfc5217SJeff Kirsher #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31) 5974*adfc5217SJeff Kirsher #define PCICFG_PM_CSR_OFFSET 0x4c 5975*adfc5217SJeff Kirsher #define PCICFG_PM_CSR_STATE (0x3<<0) 5976*adfc5217SJeff Kirsher #define PCICFG_PM_CSR_PME_ENABLE (1<<8) 5977*adfc5217SJeff Kirsher #define PCICFG_PM_CSR_PME_STATUS (1<<15) 5978*adfc5217SJeff Kirsher #define PCICFG_MSI_CAP_ID_OFFSET 0x58 5979*adfc5217SJeff Kirsher #define PCICFG_MSI_CONTROL_ENABLE (0x1<<16) 5980*adfc5217SJeff Kirsher #define PCICFG_MSI_CONTROL_MCAP (0x7<<17) 5981*adfc5217SJeff Kirsher #define PCICFG_MSI_CONTROL_MENA (0x7<<20) 5982*adfc5217SJeff Kirsher #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23) 5983*adfc5217SJeff Kirsher #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24) 5984*adfc5217SJeff Kirsher #define PCICFG_GRC_ADDRESS 0x78 5985*adfc5217SJeff Kirsher #define PCICFG_GRC_DATA 0x80 5986*adfc5217SJeff Kirsher #define PCICFG_MSIX_CAP_ID_OFFSET 0xa0 5987*adfc5217SJeff Kirsher #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16) 5988*adfc5217SJeff Kirsher #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27) 5989*adfc5217SJeff Kirsher #define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30) 5990*adfc5217SJeff Kirsher #define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31) 5991*adfc5217SJeff Kirsher 5992*adfc5217SJeff Kirsher #define PCICFG_DEVICE_CONTROL 0xb4 5993*adfc5217SJeff Kirsher #define PCICFG_DEVICE_STATUS 0xb6 5994*adfc5217SJeff Kirsher #define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0) 5995*adfc5217SJeff Kirsher #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1) 5996*adfc5217SJeff Kirsher #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2) 5997*adfc5217SJeff Kirsher #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3) 5998*adfc5217SJeff Kirsher #define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4) 5999*adfc5217SJeff Kirsher #define PCICFG_DEVICE_STATUS_NO_PEND (1<<5) 6000*adfc5217SJeff Kirsher #define PCICFG_LINK_CONTROL 0xbc 6001*adfc5217SJeff Kirsher 6002*adfc5217SJeff Kirsher 6003*adfc5217SJeff Kirsher #define BAR_USTRORM_INTMEM 0x400000 6004*adfc5217SJeff Kirsher #define BAR_CSTRORM_INTMEM 0x410000 6005*adfc5217SJeff Kirsher #define BAR_XSTRORM_INTMEM 0x420000 6006*adfc5217SJeff Kirsher #define BAR_TSTRORM_INTMEM 0x430000 6007*adfc5217SJeff Kirsher 6008*adfc5217SJeff Kirsher /* for accessing the IGU in case of status block ACK */ 6009*adfc5217SJeff Kirsher #define BAR_IGU_INTMEM 0x440000 6010*adfc5217SJeff Kirsher 6011*adfc5217SJeff Kirsher #define BAR_DOORBELL_OFFSET 0x800000 6012*adfc5217SJeff Kirsher 6013*adfc5217SJeff Kirsher #define BAR_ME_REGISTER 0x450000 6014*adfc5217SJeff Kirsher 6015*adfc5217SJeff Kirsher /* config_2 offset */ 6016*adfc5217SJeff Kirsher #define GRC_CONFIG_2_SIZE_REG 0x408 6017*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 6018*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 6019*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 6020*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 6021*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) 6022*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) 6023*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) 6024*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) 6025*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) 6026*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) 6027*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) 6028*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) 6029*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) 6030*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) 6031*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 6032*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 6033*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 6034*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR1_64ENA (1L<<4) 6035*adfc5217SJeff Kirsher #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 6036*adfc5217SJeff Kirsher #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 6037*adfc5217SJeff Kirsher #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 6038*adfc5217SJeff Kirsher #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 6039*adfc5217SJeff Kirsher #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 6040*adfc5217SJeff Kirsher #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8) 6041*adfc5217SJeff Kirsher #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8) 6042*adfc5217SJeff Kirsher #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8) 6043*adfc5217SJeff Kirsher #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8) 6044*adfc5217SJeff Kirsher #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8) 6045*adfc5217SJeff Kirsher #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8) 6046*adfc5217SJeff Kirsher #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8) 6047*adfc5217SJeff Kirsher #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8) 6048*adfc5217SJeff Kirsher #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8) 6049*adfc5217SJeff Kirsher #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8) 6050*adfc5217SJeff Kirsher #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8) 6051*adfc5217SJeff Kirsher #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8) 6052*adfc5217SJeff Kirsher #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8) 6053*adfc5217SJeff Kirsher #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8) 6054*adfc5217SJeff Kirsher #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8) 6055*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16) 6056*adfc5217SJeff Kirsher #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17) 6057*adfc5217SJeff Kirsher 6058*adfc5217SJeff Kirsher /* config_3 offset */ 6059*adfc5217SJeff Kirsher #define GRC_CONFIG_3_SIZE_REG 0x40c 6060*adfc5217SJeff Kirsher #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 6061*adfc5217SJeff Kirsher #define PCI_CONFIG_3_FORCE_PME (1L<<24) 6062*adfc5217SJeff Kirsher #define PCI_CONFIG_3_PME_STATUS (1L<<25) 6063*adfc5217SJeff Kirsher #define PCI_CONFIG_3_PME_ENABLE (1L<<26) 6064*adfc5217SJeff Kirsher #define PCI_CONFIG_3_PM_STATE (0x3L<<27) 6065*adfc5217SJeff Kirsher #define PCI_CONFIG_3_VAUX_PRESET (1L<<30) 6066*adfc5217SJeff Kirsher #define PCI_CONFIG_3_PCI_POWER (1L<<31) 6067*adfc5217SJeff Kirsher 6068*adfc5217SJeff Kirsher #define GRC_BAR2_CONFIG 0x4e0 6069*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0) 6070*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0) 6071*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0) 6072*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0) 6073*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0) 6074*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0) 6075*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0) 6076*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0) 6077*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0) 6078*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0) 6079*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0) 6080*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0) 6081*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0) 6082*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0) 6083*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0) 6084*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0) 6085*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0) 6086*adfc5217SJeff Kirsher #define PCI_CONFIG_2_BAR2_64ENA (1L<<4) 6087*adfc5217SJeff Kirsher 6088*adfc5217SJeff Kirsher #define PCI_PM_DATA_A 0x410 6089*adfc5217SJeff Kirsher #define PCI_PM_DATA_B 0x414 6090*adfc5217SJeff Kirsher #define PCI_ID_VAL1 0x434 6091*adfc5217SJeff Kirsher #define PCI_ID_VAL2 0x438 6092*adfc5217SJeff Kirsher 6093*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5 0x814 6094*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/ 6095*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/ 6096*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/ 6097*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/ 6098*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/ 6099*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/ 6100*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/ 6101*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/ 6102*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/ 6103*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/ 6104*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/ 6105*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/ 6106*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/ 6107*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/ 6108*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/ 6109*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/ 6110*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/ 6111*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/ 6112*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/ 6113*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/ 6114*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/ 6115*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/ 6116*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/ 6117*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/ 6118*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/ 6119*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/ 6120*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/ 6121*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/ 6122*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/ 6123*adfc5217SJeff Kirsher #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/ 6124*adfc5217SJeff Kirsher 6125*adfc5217SJeff Kirsher 6126*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT 0x854 6127*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */ 6128*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4\ 6129*adfc5217SJeff Kirsher (1 << 28) /* Unsupported Request Error Status in function4, if \ 6130*adfc5217SJeff Kirsher set, generate pcie_err_attn output when this error is seen. WC */ 6131*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_ECRC4\ 6132*adfc5217SJeff Kirsher (1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \ 6133*adfc5217SJeff Kirsher generate pcie_err_attn output when this error is seen.. WC */ 6134*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4\ 6135*adfc5217SJeff Kirsher (1 << 26) /* Malformed TLP Status Status in function 4, if set, \ 6136*adfc5217SJeff Kirsher generate pcie_err_attn output when this error is seen.. WC */ 6137*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4\ 6138*adfc5217SJeff Kirsher (1 << 25) /* Receiver Overflow Status Status in function 4, if \ 6139*adfc5217SJeff Kirsher set, generate pcie_err_attn output when this error is seen.. WC \ 6140*adfc5217SJeff Kirsher */ 6141*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4\ 6142*adfc5217SJeff Kirsher (1 << 24) /* Unexpected Completion Status Status in function 4, \ 6143*adfc5217SJeff Kirsher if set, generate pcie_err_attn output when this error is seen. WC \ 6144*adfc5217SJeff Kirsher */ 6145*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4\ 6146*adfc5217SJeff Kirsher (1 << 23) /* Receive UR Statusin function 4. If set, generate \ 6147*adfc5217SJeff Kirsher pcie_err_attn output when this error is seen. WC */ 6148*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4\ 6149*adfc5217SJeff Kirsher (1 << 22) /* Completer Timeout Status Status in function 4, if \ 6150*adfc5217SJeff Kirsher set, generate pcie_err_attn output when this error is seen. WC */ 6151*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4\ 6152*adfc5217SJeff Kirsher (1 << 21) /* Flow Control Protocol Error Status Status in \ 6153*adfc5217SJeff Kirsher function 4, if set, generate pcie_err_attn output when this error \ 6154*adfc5217SJeff Kirsher is seen. WC */ 6155*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4\ 6156*adfc5217SJeff Kirsher (1 << 20) /* Poisoned Error Status Status in function 4, if set, \ 6157*adfc5217SJeff Kirsher generate pcie_err_attn output when this error is seen.. WC */ 6158*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */ 6159*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3\ 6160*adfc5217SJeff Kirsher (1 << 18) /* Unsupported Request Error Status in function3, if \ 6161*adfc5217SJeff Kirsher set, generate pcie_err_attn output when this error is seen. WC */ 6162*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_ECRC3\ 6163*adfc5217SJeff Kirsher (1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \ 6164*adfc5217SJeff Kirsher generate pcie_err_attn output when this error is seen.. WC */ 6165*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3\ 6166*adfc5217SJeff Kirsher (1 << 16) /* Malformed TLP Status Status in function 3, if set, \ 6167*adfc5217SJeff Kirsher generate pcie_err_attn output when this error is seen.. WC */ 6168*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3\ 6169*adfc5217SJeff Kirsher (1 << 15) /* Receiver Overflow Status Status in function 3, if \ 6170*adfc5217SJeff Kirsher set, generate pcie_err_attn output when this error is seen.. WC \ 6171*adfc5217SJeff Kirsher */ 6172*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3\ 6173*adfc5217SJeff Kirsher (1 << 14) /* Unexpected Completion Status Status in function 3, \ 6174*adfc5217SJeff Kirsher if set, generate pcie_err_attn output when this error is seen. WC \ 6175*adfc5217SJeff Kirsher */ 6176*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3\ 6177*adfc5217SJeff Kirsher (1 << 13) /* Receive UR Statusin function 3. If set, generate \ 6178*adfc5217SJeff Kirsher pcie_err_attn output when this error is seen. WC */ 6179*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3\ 6180*adfc5217SJeff Kirsher (1 << 12) /* Completer Timeout Status Status in function 3, if \ 6181*adfc5217SJeff Kirsher set, generate pcie_err_attn output when this error is seen. WC */ 6182*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3\ 6183*adfc5217SJeff Kirsher (1 << 11) /* Flow Control Protocol Error Status Status in \ 6184*adfc5217SJeff Kirsher function 3, if set, generate pcie_err_attn output when this error \ 6185*adfc5217SJeff Kirsher is seen. WC */ 6186*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3\ 6187*adfc5217SJeff Kirsher (1 << 10) /* Poisoned Error Status Status in function 3, if set, \ 6188*adfc5217SJeff Kirsher generate pcie_err_attn output when this error is seen.. WC */ 6189*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */ 6190*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2\ 6191*adfc5217SJeff Kirsher (1 << 8) /* Unsupported Request Error Status for Function 2, if \ 6192*adfc5217SJeff Kirsher set, generate pcie_err_attn output when this error is seen. WC */ 6193*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_ECRC2\ 6194*adfc5217SJeff Kirsher (1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \ 6195*adfc5217SJeff Kirsher generate pcie_err_attn output when this error is seen.. WC */ 6196*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2\ 6197*adfc5217SJeff Kirsher (1 << 6) /* Malformed TLP Status Status for Function 2, if set, \ 6198*adfc5217SJeff Kirsher generate pcie_err_attn output when this error is seen.. WC */ 6199*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2\ 6200*adfc5217SJeff Kirsher (1 << 5) /* Receiver Overflow Status Status for Function 2, if \ 6201*adfc5217SJeff Kirsher set, generate pcie_err_attn output when this error is seen.. WC \ 6202*adfc5217SJeff Kirsher */ 6203*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2\ 6204*adfc5217SJeff Kirsher (1 << 4) /* Unexpected Completion Status Status for Function 2, \ 6205*adfc5217SJeff Kirsher if set, generate pcie_err_attn output when this error is seen. WC \ 6206*adfc5217SJeff Kirsher */ 6207*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2\ 6208*adfc5217SJeff Kirsher (1 << 3) /* Receive UR Statusfor Function 2. If set, generate \ 6209*adfc5217SJeff Kirsher pcie_err_attn output when this error is seen. WC */ 6210*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2\ 6211*adfc5217SJeff Kirsher (1 << 2) /* Completer Timeout Status Status for Function 2, if \ 6212*adfc5217SJeff Kirsher set, generate pcie_err_attn output when this error is seen. WC */ 6213*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2\ 6214*adfc5217SJeff Kirsher (1 << 1) /* Flow Control Protocol Error Status Status for \ 6215*adfc5217SJeff Kirsher Function 2, if set, generate pcie_err_attn output when this error \ 6216*adfc5217SJeff Kirsher is seen. WC */ 6217*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2\ 6218*adfc5217SJeff Kirsher (1 << 0) /* Poisoned Error Status Status for Function 2, if set, \ 6219*adfc5217SJeff Kirsher generate pcie_err_attn output when this error is seen.. WC */ 6220*adfc5217SJeff Kirsher 6221*adfc5217SJeff Kirsher 6222*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT 0x85C 6223*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */ 6224*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7\ 6225*adfc5217SJeff Kirsher (1 << 28) /* Unsupported Request Error Status in function7, if \ 6226*adfc5217SJeff Kirsher set, generate pcie_err_attn output when this error is seen. WC */ 6227*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_ECRC7\ 6228*adfc5217SJeff Kirsher (1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \ 6229*adfc5217SJeff Kirsher generate pcie_err_attn output when this error is seen.. WC */ 6230*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7\ 6231*adfc5217SJeff Kirsher (1 << 26) /* Malformed TLP Status Status in function 7, if set, \ 6232*adfc5217SJeff Kirsher generate pcie_err_attn output when this error is seen.. WC */ 6233*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7\ 6234*adfc5217SJeff Kirsher (1 << 25) /* Receiver Overflow Status Status in function 7, if \ 6235*adfc5217SJeff Kirsher set, generate pcie_err_attn output when this error is seen.. WC \ 6236*adfc5217SJeff Kirsher */ 6237*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7\ 6238*adfc5217SJeff Kirsher (1 << 24) /* Unexpected Completion Status Status in function 7, \ 6239*adfc5217SJeff Kirsher if set, generate pcie_err_attn output when this error is seen. WC \ 6240*adfc5217SJeff Kirsher */ 6241*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7\ 6242*adfc5217SJeff Kirsher (1 << 23) /* Receive UR Statusin function 7. If set, generate \ 6243*adfc5217SJeff Kirsher pcie_err_attn output when this error is seen. WC */ 6244*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7\ 6245*adfc5217SJeff Kirsher (1 << 22) /* Completer Timeout Status Status in function 7, if \ 6246*adfc5217SJeff Kirsher set, generate pcie_err_attn output when this error is seen. WC */ 6247*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7\ 6248*adfc5217SJeff Kirsher (1 << 21) /* Flow Control Protocol Error Status Status in \ 6249*adfc5217SJeff Kirsher function 7, if set, generate pcie_err_attn output when this error \ 6250*adfc5217SJeff Kirsher is seen. WC */ 6251*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7\ 6252*adfc5217SJeff Kirsher (1 << 20) /* Poisoned Error Status Status in function 7, if set, \ 6253*adfc5217SJeff Kirsher generate pcie_err_attn output when this error is seen.. WC */ 6254*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */ 6255*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6\ 6256*adfc5217SJeff Kirsher (1 << 18) /* Unsupported Request Error Status in function6, if \ 6257*adfc5217SJeff Kirsher set, generate pcie_err_attn output when this error is seen. WC */ 6258*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_ECRC6\ 6259*adfc5217SJeff Kirsher (1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \ 6260*adfc5217SJeff Kirsher generate pcie_err_attn output when this error is seen.. WC */ 6261*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6\ 6262*adfc5217SJeff Kirsher (1 << 16) /* Malformed TLP Status Status in function 6, if set, \ 6263*adfc5217SJeff Kirsher generate pcie_err_attn output when this error is seen.. WC */ 6264*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6\ 6265*adfc5217SJeff Kirsher (1 << 15) /* Receiver Overflow Status Status in function 6, if \ 6266*adfc5217SJeff Kirsher set, generate pcie_err_attn output when this error is seen.. WC \ 6267*adfc5217SJeff Kirsher */ 6268*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6\ 6269*adfc5217SJeff Kirsher (1 << 14) /* Unexpected Completion Status Status in function 6, \ 6270*adfc5217SJeff Kirsher if set, generate pcie_err_attn output when this error is seen. WC \ 6271*adfc5217SJeff Kirsher */ 6272*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6\ 6273*adfc5217SJeff Kirsher (1 << 13) /* Receive UR Statusin function 6. If set, generate \ 6274*adfc5217SJeff Kirsher pcie_err_attn output when this error is seen. WC */ 6275*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6\ 6276*adfc5217SJeff Kirsher (1 << 12) /* Completer Timeout Status Status in function 6, if \ 6277*adfc5217SJeff Kirsher set, generate pcie_err_attn output when this error is seen. WC */ 6278*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6\ 6279*adfc5217SJeff Kirsher (1 << 11) /* Flow Control Protocol Error Status Status in \ 6280*adfc5217SJeff Kirsher function 6, if set, generate pcie_err_attn output when this error \ 6281*adfc5217SJeff Kirsher is seen. WC */ 6282*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6\ 6283*adfc5217SJeff Kirsher (1 << 10) /* Poisoned Error Status Status in function 6, if set, \ 6284*adfc5217SJeff Kirsher generate pcie_err_attn output when this error is seen.. WC */ 6285*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */ 6286*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5\ 6287*adfc5217SJeff Kirsher (1 << 8) /* Unsupported Request Error Status for Function 5, if \ 6288*adfc5217SJeff Kirsher set, generate pcie_err_attn output when this error is seen. WC */ 6289*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_ECRC5\ 6290*adfc5217SJeff Kirsher (1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \ 6291*adfc5217SJeff Kirsher generate pcie_err_attn output when this error is seen.. WC */ 6292*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5\ 6293*adfc5217SJeff Kirsher (1 << 6) /* Malformed TLP Status Status for Function 5, if set, \ 6294*adfc5217SJeff Kirsher generate pcie_err_attn output when this error is seen.. WC */ 6295*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5\ 6296*adfc5217SJeff Kirsher (1 << 5) /* Receiver Overflow Status Status for Function 5, if \ 6297*adfc5217SJeff Kirsher set, generate pcie_err_attn output when this error is seen.. WC \ 6298*adfc5217SJeff Kirsher */ 6299*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5\ 6300*adfc5217SJeff Kirsher (1 << 4) /* Unexpected Completion Status Status for Function 5, \ 6301*adfc5217SJeff Kirsher if set, generate pcie_err_attn output when this error is seen. WC \ 6302*adfc5217SJeff Kirsher */ 6303*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5\ 6304*adfc5217SJeff Kirsher (1 << 3) /* Receive UR Statusfor Function 5. If set, generate \ 6305*adfc5217SJeff Kirsher pcie_err_attn output when this error is seen. WC */ 6306*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5\ 6307*adfc5217SJeff Kirsher (1 << 2) /* Completer Timeout Status Status for Function 5, if \ 6308*adfc5217SJeff Kirsher set, generate pcie_err_attn output when this error is seen. WC */ 6309*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5\ 6310*adfc5217SJeff Kirsher (1 << 1) /* Flow Control Protocol Error Status Status for \ 6311*adfc5217SJeff Kirsher Function 5, if set, generate pcie_err_attn output when this error \ 6312*adfc5217SJeff Kirsher is seen. WC */ 6313*adfc5217SJeff Kirsher #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5\ 6314*adfc5217SJeff Kirsher (1 << 0) /* Poisoned Error Status Status for Function 5, if set, \ 6315*adfc5217SJeff Kirsher generate pcie_err_attn output when this error is seen.. WC */ 6316*adfc5217SJeff Kirsher 6317*adfc5217SJeff Kirsher 6318*adfc5217SJeff Kirsher #define BAR_USTRORM_INTMEM 0x400000 6319*adfc5217SJeff Kirsher #define BAR_CSTRORM_INTMEM 0x410000 6320*adfc5217SJeff Kirsher #define BAR_XSTRORM_INTMEM 0x420000 6321*adfc5217SJeff Kirsher #define BAR_TSTRORM_INTMEM 0x430000 6322*adfc5217SJeff Kirsher 6323*adfc5217SJeff Kirsher /* for accessing the IGU in case of status block ACK */ 6324*adfc5217SJeff Kirsher #define BAR_IGU_INTMEM 0x440000 6325*adfc5217SJeff Kirsher 6326*adfc5217SJeff Kirsher #define BAR_DOORBELL_OFFSET 0x800000 6327*adfc5217SJeff Kirsher 6328*adfc5217SJeff Kirsher #define BAR_ME_REGISTER 0x450000 6329*adfc5217SJeff Kirsher #define ME_REG_PF_NUM_SHIFT 0 6330*adfc5217SJeff Kirsher #define ME_REG_PF_NUM\ 6331*adfc5217SJeff Kirsher (7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */ 6332*adfc5217SJeff Kirsher #define ME_REG_VF_VALID (1<<8) 6333*adfc5217SJeff Kirsher #define ME_REG_VF_NUM_SHIFT 9 6334*adfc5217SJeff Kirsher #define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT) 6335*adfc5217SJeff Kirsher #define ME_REG_VF_ERR (0x1<<3) 6336*adfc5217SJeff Kirsher #define ME_REG_ABS_PF_NUM_SHIFT 16 6337*adfc5217SJeff Kirsher #define ME_REG_ABS_PF_NUM\ 6338*adfc5217SJeff Kirsher (7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */ 6339*adfc5217SJeff Kirsher 6340*adfc5217SJeff Kirsher 6341*adfc5217SJeff Kirsher #define MDIO_REG_BANK_CL73_IEEEB0 0x0 6342*adfc5217SJeff Kirsher #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0 6343*adfc5217SJeff Kirsher #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200 6344*adfc5217SJeff Kirsher #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000 6345*adfc5217SJeff Kirsher #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000 6346*adfc5217SJeff Kirsher 6347*adfc5217SJeff Kirsher #define MDIO_REG_BANK_CL73_IEEEB1 0x10 6348*adfc5217SJeff Kirsher #define MDIO_CL73_IEEEB1_AN_ADV1 0x00 6349*adfc5217SJeff Kirsher #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400 6350*adfc5217SJeff Kirsher #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800 6351*adfc5217SJeff Kirsher #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00 6352*adfc5217SJeff Kirsher #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00 6353*adfc5217SJeff Kirsher #define MDIO_CL73_IEEEB1_AN_ADV2 0x01 6354*adfc5217SJeff Kirsher #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000 6355*adfc5217SJeff Kirsher #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020 6356*adfc5217SJeff Kirsher #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040 6357*adfc5217SJeff Kirsher #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080 6358*adfc5217SJeff Kirsher #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03 6359*adfc5217SJeff Kirsher #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400 6360*adfc5217SJeff Kirsher #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800 6361*adfc5217SJeff Kirsher #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00 6362*adfc5217SJeff Kirsher #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00 6363*adfc5217SJeff Kirsher 6364*adfc5217SJeff Kirsher #define MDIO_REG_BANK_RX0 0x80b0 6365*adfc5217SJeff Kirsher #define MDIO_RX0_RX_STATUS 0x10 6366*adfc5217SJeff Kirsher #define MDIO_RX0_RX_STATUS_SIGDET 0x8000 6367*adfc5217SJeff Kirsher #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000 6368*adfc5217SJeff Kirsher #define MDIO_RX0_RX_EQ_BOOST 0x1c 6369*adfc5217SJeff Kirsher #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6370*adfc5217SJeff Kirsher #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10 6371*adfc5217SJeff Kirsher 6372*adfc5217SJeff Kirsher #define MDIO_REG_BANK_RX1 0x80c0 6373*adfc5217SJeff Kirsher #define MDIO_RX1_RX_EQ_BOOST 0x1c 6374*adfc5217SJeff Kirsher #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6375*adfc5217SJeff Kirsher #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10 6376*adfc5217SJeff Kirsher 6377*adfc5217SJeff Kirsher #define MDIO_REG_BANK_RX2 0x80d0 6378*adfc5217SJeff Kirsher #define MDIO_RX2_RX_EQ_BOOST 0x1c 6379*adfc5217SJeff Kirsher #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6380*adfc5217SJeff Kirsher #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10 6381*adfc5217SJeff Kirsher 6382*adfc5217SJeff Kirsher #define MDIO_REG_BANK_RX3 0x80e0 6383*adfc5217SJeff Kirsher #define MDIO_RX3_RX_EQ_BOOST 0x1c 6384*adfc5217SJeff Kirsher #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6385*adfc5217SJeff Kirsher #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10 6386*adfc5217SJeff Kirsher 6387*adfc5217SJeff Kirsher #define MDIO_REG_BANK_RX_ALL 0x80f0 6388*adfc5217SJeff Kirsher #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c 6389*adfc5217SJeff Kirsher #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6390*adfc5217SJeff Kirsher #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10 6391*adfc5217SJeff Kirsher 6392*adfc5217SJeff Kirsher #define MDIO_REG_BANK_TX0 0x8060 6393*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER 0x17 6394*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 6395*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 6396*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 6397*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 6398*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 6399*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 6400*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 6401*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 6402*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 6403*adfc5217SJeff Kirsher 6404*adfc5217SJeff Kirsher #define MDIO_REG_BANK_TX1 0x8070 6405*adfc5217SJeff Kirsher #define MDIO_TX1_TX_DRIVER 0x17 6406*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 6407*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 6408*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 6409*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 6410*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 6411*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 6412*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 6413*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 6414*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 6415*adfc5217SJeff Kirsher 6416*adfc5217SJeff Kirsher #define MDIO_REG_BANK_TX2 0x8080 6417*adfc5217SJeff Kirsher #define MDIO_TX2_TX_DRIVER 0x17 6418*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 6419*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 6420*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 6421*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 6422*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 6423*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 6424*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 6425*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 6426*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 6427*adfc5217SJeff Kirsher 6428*adfc5217SJeff Kirsher #define MDIO_REG_BANK_TX3 0x8090 6429*adfc5217SJeff Kirsher #define MDIO_TX3_TX_DRIVER 0x17 6430*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 6431*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 6432*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 6433*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 6434*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 6435*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 6436*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 6437*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 6438*adfc5217SJeff Kirsher #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 6439*adfc5217SJeff Kirsher 6440*adfc5217SJeff Kirsher #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000 6441*adfc5217SJeff Kirsher #define MDIO_BLOCK0_XGXS_CONTROL 0x10 6442*adfc5217SJeff Kirsher 6443*adfc5217SJeff Kirsher #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010 6444*adfc5217SJeff Kirsher #define MDIO_BLOCK1_LANE_CTRL0 0x15 6445*adfc5217SJeff Kirsher #define MDIO_BLOCK1_LANE_CTRL1 0x16 6446*adfc5217SJeff Kirsher #define MDIO_BLOCK1_LANE_CTRL2 0x17 6447*adfc5217SJeff Kirsher #define MDIO_BLOCK1_LANE_PRBS 0x19 6448*adfc5217SJeff Kirsher 6449*adfc5217SJeff Kirsher #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100 6450*adfc5217SJeff Kirsher #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10 6451*adfc5217SJeff Kirsher #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000 6452*adfc5217SJeff Kirsher #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000 6453*adfc5217SJeff Kirsher #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11 6454*adfc5217SJeff Kirsher #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000 6455*adfc5217SJeff Kirsher #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14 6456*adfc5217SJeff Kirsher #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001 6457*adfc5217SJeff Kirsher #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010 6458*adfc5217SJeff Kirsher #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15 6459*adfc5217SJeff Kirsher 6460*adfc5217SJeff Kirsher #define MDIO_REG_BANK_GP_STATUS 0x8120 6461*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B 6462*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001 6463*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002 6464*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004 6465*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008 6466*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010 6467*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020 6468*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040 6469*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080 6470*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00 6471*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000 6472*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100 6473*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200 6474*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300 6475*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400 6476*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500 6477*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600 6478*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700 6479*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800 6480*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900 6481*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00 6482*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00 6483*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00 6484*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00 6485*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00 6486*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00 6487*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00 6488*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00 6489*adfc5217SJeff Kirsher #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00 6490*adfc5217SJeff Kirsher 6491*adfc5217SJeff Kirsher 6492*adfc5217SJeff Kirsher #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130 6493*adfc5217SJeff Kirsher #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10 6494*adfc5217SJeff Kirsher #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000 6495*adfc5217SJeff Kirsher #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11 6496*adfc5217SJeff Kirsher #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1 6497*adfc5217SJeff Kirsher #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13 6498*adfc5217SJeff Kirsher #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1) 6499*adfc5217SJeff Kirsher 6500*adfc5217SJeff Kirsher #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300 6501*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10 6502*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001 6503*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002 6504*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004 6505*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008 6506*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010 6507*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020 6508*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11 6509*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001 6510*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040 6511*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14 6512*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001 6513*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002 6514*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004 6515*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018 6516*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3 6517*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018 6518*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010 6519*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008 6520*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000 6521*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15 6522*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002 6523*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_MISC1 0x18 6524*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000 6525*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000 6526*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000 6527*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000 6528*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000 6529*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000 6530*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010 6531*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f 6532*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000 6533*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001 6534*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002 6535*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003 6536*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004 6537*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005 6538*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006 6539*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007 6540*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008 6541*adfc5217SJeff Kirsher #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009 6542*adfc5217SJeff Kirsher 6543*adfc5217SJeff Kirsher #define MDIO_REG_BANK_OVER_1G 0x8320 6544*adfc5217SJeff Kirsher #define MDIO_OVER_1G_DIGCTL_3_4 0x14 6545*adfc5217SJeff Kirsher #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0 6546*adfc5217SJeff Kirsher #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5 6547*adfc5217SJeff Kirsher #define MDIO_OVER_1G_UP1 0x19 6548*adfc5217SJeff Kirsher #define MDIO_OVER_1G_UP1_2_5G 0x0001 6549*adfc5217SJeff Kirsher #define MDIO_OVER_1G_UP1_5G 0x0002 6550*adfc5217SJeff Kirsher #define MDIO_OVER_1G_UP1_6G 0x0004 6551*adfc5217SJeff Kirsher #define MDIO_OVER_1G_UP1_10G 0x0010 6552*adfc5217SJeff Kirsher #define MDIO_OVER_1G_UP1_10GH 0x0008 6553*adfc5217SJeff Kirsher #define MDIO_OVER_1G_UP1_12G 0x0020 6554*adfc5217SJeff Kirsher #define MDIO_OVER_1G_UP1_12_5G 0x0040 6555*adfc5217SJeff Kirsher #define MDIO_OVER_1G_UP1_13G 0x0080 6556*adfc5217SJeff Kirsher #define MDIO_OVER_1G_UP1_15G 0x0100 6557*adfc5217SJeff Kirsher #define MDIO_OVER_1G_UP1_16G 0x0200 6558*adfc5217SJeff Kirsher #define MDIO_OVER_1G_UP2 0x1A 6559*adfc5217SJeff Kirsher #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007 6560*adfc5217SJeff Kirsher #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038 6561*adfc5217SJeff Kirsher #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0 6562*adfc5217SJeff Kirsher #define MDIO_OVER_1G_UP3 0x1B 6563*adfc5217SJeff Kirsher #define MDIO_OVER_1G_UP3_HIGIG2 0x0001 6564*adfc5217SJeff Kirsher #define MDIO_OVER_1G_LP_UP1 0x1C 6565*adfc5217SJeff Kirsher #define MDIO_OVER_1G_LP_UP2 0x1D 6566*adfc5217SJeff Kirsher #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff 6567*adfc5217SJeff Kirsher #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780 6568*adfc5217SJeff Kirsher #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7 6569*adfc5217SJeff Kirsher #define MDIO_OVER_1G_LP_UP3 0x1E 6570*adfc5217SJeff Kirsher 6571*adfc5217SJeff Kirsher #define MDIO_REG_BANK_REMOTE_PHY 0x8330 6572*adfc5217SJeff Kirsher #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10 6573*adfc5217SJeff Kirsher #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010 6574*adfc5217SJeff Kirsher #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600 6575*adfc5217SJeff Kirsher 6576*adfc5217SJeff Kirsher #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350 6577*adfc5217SJeff Kirsher #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10 6578*adfc5217SJeff Kirsher #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001 6579*adfc5217SJeff Kirsher #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002 6580*adfc5217SJeff Kirsher 6581*adfc5217SJeff Kirsher #define MDIO_REG_BANK_CL73_USERB0 0x8370 6582*adfc5217SJeff Kirsher #define MDIO_CL73_USERB0_CL73_UCTRL 0x10 6583*adfc5217SJeff Kirsher #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002 6584*adfc5217SJeff Kirsher #define MDIO_CL73_USERB0_CL73_USTAT1 0x11 6585*adfc5217SJeff Kirsher #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100 6586*adfc5217SJeff Kirsher #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400 6587*adfc5217SJeff Kirsher #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12 6588*adfc5217SJeff Kirsher #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000 6589*adfc5217SJeff Kirsher #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000 6590*adfc5217SJeff Kirsher #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000 6591*adfc5217SJeff Kirsher #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14 6592*adfc5217SJeff Kirsher #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001 6593*adfc5217SJeff Kirsher 6594*adfc5217SJeff Kirsher #define MDIO_REG_BANK_AER_BLOCK 0xFFD0 6595*adfc5217SJeff Kirsher #define MDIO_AER_BLOCK_AER_REG 0x1E 6596*adfc5217SJeff Kirsher 6597*adfc5217SJeff Kirsher #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0 6598*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10 6599*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040 6600*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000 6601*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000 6602*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040 6603*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100 6604*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200 6605*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000 6606*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000 6607*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000 6608*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEE0_MII_STATUS 0x11 6609*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004 6610*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020 6611*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14 6612*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020 6613*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040 6614*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180 6615*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000 6616*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080 6617*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100 6618*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180 6619*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000 6620*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15 6621*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000 6622*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000 6623*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180 6624*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000 6625*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180 6626*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040 6627*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020 6628*adfc5217SJeff Kirsher /*WhenthelinkpartnerisinSGMIImode(bit0=1),then 6629*adfc5217SJeff Kirsher bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge. 6630*adfc5217SJeff Kirsher Theotherbitsarereservedandshouldbezero*/ 6631*adfc5217SJeff Kirsher #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001 6632*adfc5217SJeff Kirsher 6633*adfc5217SJeff Kirsher 6634*adfc5217SJeff Kirsher #define MDIO_PMA_DEVAD 0x1 6635*adfc5217SJeff Kirsher /*ieee*/ 6636*adfc5217SJeff Kirsher #define MDIO_PMA_REG_CTRL 0x0 6637*adfc5217SJeff Kirsher #define MDIO_PMA_REG_STATUS 0x1 6638*adfc5217SJeff Kirsher #define MDIO_PMA_REG_10G_CTRL2 0x7 6639*adfc5217SJeff Kirsher #define MDIO_PMA_REG_TX_DISABLE 0x0009 6640*adfc5217SJeff Kirsher #define MDIO_PMA_REG_RX_SD 0xa 6641*adfc5217SJeff Kirsher /*bcm*/ 6642*adfc5217SJeff Kirsher #define MDIO_PMA_REG_BCM_CTRL 0x0096 6643*adfc5217SJeff Kirsher #define MDIO_PMA_REG_FEC_CTRL 0x00ab 6644*adfc5217SJeff Kirsher #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800 6645*adfc5217SJeff Kirsher #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808 6646*adfc5217SJeff Kirsher #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809 6647*adfc5217SJeff Kirsher #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02 6648*adfc5217SJeff Kirsher #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09 6649*adfc5217SJeff Kirsher #define MDIO_PMA_REG_MISC_CTRL 0xca0a 6650*adfc5217SJeff Kirsher #define MDIO_PMA_REG_GEN_CTRL 0xca10 6651*adfc5217SJeff Kirsher #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188 6652*adfc5217SJeff Kirsher #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a 6653*adfc5217SJeff Kirsher #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12 6654*adfc5217SJeff Kirsher #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13 6655*adfc5217SJeff Kirsher #define MDIO_PMA_REG_ROM_VER1 0xca19 6656*adfc5217SJeff Kirsher #define MDIO_PMA_REG_ROM_VER2 0xca1a 6657*adfc5217SJeff Kirsher #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b 6658*adfc5217SJeff Kirsher #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d 6659*adfc5217SJeff Kirsher #define MDIO_PMA_REG_PLL_CTRL 0xca1e 6660*adfc5217SJeff Kirsher #define MDIO_PMA_REG_MISC_CTRL0 0xca23 6661*adfc5217SJeff Kirsher #define MDIO_PMA_REG_LRM_MODE 0xca3f 6662*adfc5217SJeff Kirsher #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46 6663*adfc5217SJeff Kirsher #define MDIO_PMA_REG_MISC_CTRL1 0xca85 6664*adfc5217SJeff Kirsher 6665*adfc5217SJeff Kirsher #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000 6666*adfc5217SJeff Kirsher #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c 6667*adfc5217SJeff Kirsher #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000 6668*adfc5217SJeff Kirsher #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004 6669*adfc5217SJeff Kirsher #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008 6670*adfc5217SJeff Kirsher #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c 6671*adfc5217SJeff Kirsher #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002 6672*adfc5217SJeff Kirsher #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003 6673*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820 6674*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff 6675*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01 6676*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05 6677*adfc5217SJeff Kirsher 6678*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005 6679*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007 6680*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff 6681*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02 6682*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05 6683*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808 6684*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e 6685*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8727_PCS_GP 0xc842 6686*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4 6687*adfc5217SJeff Kirsher 6688*adfc5217SJeff Kirsher #define MDIO_AN_REG_8727_MISC_CTRL 0x8309 6689*adfc5217SJeff Kirsher 6690*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8073_CHIP_REV 0xc801 6691*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820 6692*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8073_XAUI_WA 0xc841 6693*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08 6694*adfc5217SJeff Kirsher 6695*adfc5217SJeff Kirsher #define MDIO_PMA_REG_7101_RESET 0xc000 6696*adfc5217SJeff Kirsher #define MDIO_PMA_REG_7107_LED_CNTL 0xc007 6697*adfc5217SJeff Kirsher #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009 6698*adfc5217SJeff Kirsher #define MDIO_PMA_REG_7101_VER1 0xc026 6699*adfc5217SJeff Kirsher #define MDIO_PMA_REG_7101_VER2 0xc027 6700*adfc5217SJeff Kirsher 6701*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811 6702*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c 6703*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f 6704*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8481_LED3_MASK 0xa832 6705*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834 6706*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8481_LED5_MASK 0xa838 6707*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835 6708*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b 6709*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800 6710*adfc5217SJeff Kirsher #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11 6711*adfc5217SJeff Kirsher 6712*adfc5217SJeff Kirsher 6713*adfc5217SJeff Kirsher #define MDIO_WIS_DEVAD 0x2 6714*adfc5217SJeff Kirsher /*bcm*/ 6715*adfc5217SJeff Kirsher #define MDIO_WIS_REG_LASI_CNTL 0x9002 6716*adfc5217SJeff Kirsher #define MDIO_WIS_REG_LASI_STATUS 0x9005 6717*adfc5217SJeff Kirsher 6718*adfc5217SJeff Kirsher #define MDIO_PCS_DEVAD 0x3 6719*adfc5217SJeff Kirsher #define MDIO_PCS_REG_STATUS 0x0020 6720*adfc5217SJeff Kirsher #define MDIO_PCS_REG_LASI_STATUS 0x9005 6721*adfc5217SJeff Kirsher #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000 6722*adfc5217SJeff Kirsher #define MDIO_PCS_REG_7101_SPI_MUX 0xD008 6723*adfc5217SJeff Kirsher #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A 6724*adfc5217SJeff Kirsher #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5) 6725*adfc5217SJeff Kirsher #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A 6726*adfc5217SJeff Kirsher #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6) 6727*adfc5217SJeff Kirsher #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7) 6728*adfc5217SJeff Kirsher #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2) 6729*adfc5217SJeff Kirsher #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028 6730*adfc5217SJeff Kirsher 6731*adfc5217SJeff Kirsher 6732*adfc5217SJeff Kirsher #define MDIO_XS_DEVAD 0x4 6733*adfc5217SJeff Kirsher #define MDIO_XS_PLL_SEQUENCER 0x8000 6734*adfc5217SJeff Kirsher #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a 6735*adfc5217SJeff Kirsher 6736*adfc5217SJeff Kirsher #define MDIO_XS_8706_REG_BANK_RX0 0x80bc 6737*adfc5217SJeff Kirsher #define MDIO_XS_8706_REG_BANK_RX1 0x80cc 6738*adfc5217SJeff Kirsher #define MDIO_XS_8706_REG_BANK_RX2 0x80dc 6739*adfc5217SJeff Kirsher #define MDIO_XS_8706_REG_BANK_RX3 0x80ec 6740*adfc5217SJeff Kirsher #define MDIO_XS_8706_REG_BANK_RXA 0x80fc 6741*adfc5217SJeff Kirsher 6742*adfc5217SJeff Kirsher #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA 6743*adfc5217SJeff Kirsher 6744*adfc5217SJeff Kirsher #define MDIO_AN_DEVAD 0x7 6745*adfc5217SJeff Kirsher /*ieee*/ 6746*adfc5217SJeff Kirsher #define MDIO_AN_REG_CTRL 0x0000 6747*adfc5217SJeff Kirsher #define MDIO_AN_REG_STATUS 0x0001 6748*adfc5217SJeff Kirsher #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020 6749*adfc5217SJeff Kirsher #define MDIO_AN_REG_ADV_PAUSE 0x0010 6750*adfc5217SJeff Kirsher #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400 6751*adfc5217SJeff Kirsher #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800 6752*adfc5217SJeff Kirsher #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00 6753*adfc5217SJeff Kirsher #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00 6754*adfc5217SJeff Kirsher #define MDIO_AN_REG_ADV 0x0011 6755*adfc5217SJeff Kirsher #define MDIO_AN_REG_ADV2 0x0012 6756*adfc5217SJeff Kirsher #define MDIO_AN_REG_LP_AUTO_NEG 0x0013 6757*adfc5217SJeff Kirsher #define MDIO_AN_REG_MASTER_STATUS 0x0021 6758*adfc5217SJeff Kirsher /*bcm*/ 6759*adfc5217SJeff Kirsher #define MDIO_AN_REG_LINK_STATUS 0x8304 6760*adfc5217SJeff Kirsher #define MDIO_AN_REG_CL37_CL73 0x8370 6761*adfc5217SJeff Kirsher #define MDIO_AN_REG_CL37_AN 0xffe0 6762*adfc5217SJeff Kirsher #define MDIO_AN_REG_CL37_FC_LD 0xffe4 6763*adfc5217SJeff Kirsher #define MDIO_AN_REG_CL37_FC_LP 0xffe5 6764*adfc5217SJeff Kirsher 6765*adfc5217SJeff Kirsher #define MDIO_AN_REG_8073_2_5G 0x8329 6766*adfc5217SJeff Kirsher #define MDIO_AN_REG_8073_BAM 0x8350 6767*adfc5217SJeff Kirsher 6768*adfc5217SJeff Kirsher #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020 6769*adfc5217SJeff Kirsher #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0 6770*adfc5217SJeff Kirsher #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1 6771*adfc5217SJeff Kirsher #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4 6772*adfc5217SJeff Kirsher #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6 6773*adfc5217SJeff Kirsher #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9 6774*adfc5217SJeff Kirsher #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5 6775*adfc5217SJeff Kirsher #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7 6776*adfc5217SJeff Kirsher #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8 6777*adfc5217SJeff Kirsher #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc 6778*adfc5217SJeff Kirsher 6779*adfc5217SJeff Kirsher /* BCM84823 only */ 6780*adfc5217SJeff Kirsher #define MDIO_CTL_DEVAD 0x1e 6781*adfc5217SJeff Kirsher #define MDIO_CTL_REG_84823_MEDIA 0x401a 6782*adfc5217SJeff Kirsher #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018 6783*adfc5217SJeff Kirsher /* These pins configure the BCM84823 interface to MAC after reset. */ 6784*adfc5217SJeff Kirsher #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008 6785*adfc5217SJeff Kirsher #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010 6786*adfc5217SJeff Kirsher /* These pins configure the BCM84823 interface to Line after reset. */ 6787*adfc5217SJeff Kirsher #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060 6788*adfc5217SJeff Kirsher #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020 6789*adfc5217SJeff Kirsher #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040 6790*adfc5217SJeff Kirsher /* When this pin is active high during reset, 10GBASE-T core is power 6791*adfc5217SJeff Kirsher * down, When it is active low the 10GBASE-T is power up 6792*adfc5217SJeff Kirsher */ 6793*adfc5217SJeff Kirsher #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080 6794*adfc5217SJeff Kirsher #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100 6795*adfc5217SJeff Kirsher #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000 6796*adfc5217SJeff Kirsher #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100 6797*adfc5217SJeff Kirsher #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000 6798*adfc5217SJeff Kirsher #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005 6799*adfc5217SJeff Kirsher #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080 6800*adfc5217SJeff Kirsher 6801*adfc5217SJeff Kirsher #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3 6802*adfc5217SJeff Kirsher #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080 6803*adfc5217SJeff Kirsher 6804*adfc5217SJeff Kirsher /* BCM84833 only */ 6805*adfc5217SJeff Kirsher #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a 6806*adfc5217SJeff Kirsher #define MDIO_84833_SUPER_ISOLATE 0x8000 6807*adfc5217SJeff Kirsher /* These are mailbox register set used by 84833. */ 6808*adfc5217SJeff Kirsher #define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005 6809*adfc5217SJeff Kirsher #define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006 6810*adfc5217SJeff Kirsher #define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007 6811*adfc5217SJeff Kirsher #define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008 6812*adfc5217SJeff Kirsher #define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009 6813*adfc5217SJeff Kirsher #define MDIO_84833_TOP_CFG_DATA3_REG 0x4011 6814*adfc5217SJeff Kirsher #define MDIO_84833_TOP_CFG_DATA4_REG 0x4012 6815*adfc5217SJeff Kirsher 6816*adfc5217SJeff Kirsher /* Mailbox command set used by 84833. */ 6817*adfc5217SJeff Kirsher #define PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE 0x2 6818*adfc5217SJeff Kirsher /* Mailbox status set used by 84833. */ 6819*adfc5217SJeff Kirsher #define PHY84833_CMD_RECEIVED 0x0001 6820*adfc5217SJeff Kirsher #define PHY84833_CMD_IN_PROGRESS 0x0002 6821*adfc5217SJeff Kirsher #define PHY84833_CMD_COMPLETE_PASS 0x0004 6822*adfc5217SJeff Kirsher #define PHY84833_CMD_COMPLETE_ERROR 0x0008 6823*adfc5217SJeff Kirsher #define PHY84833_CMD_OPEN_FOR_CMDS 0x0010 6824*adfc5217SJeff Kirsher #define PHY84833_CMD_SYSTEM_BOOT 0x0020 6825*adfc5217SJeff Kirsher #define PHY84833_CMD_NOT_OPEN_FOR_CMDS 0x0040 6826*adfc5217SJeff Kirsher #define PHY84833_CMD_CLEAR_COMPLETE 0x0080 6827*adfc5217SJeff Kirsher #define PHY84833_CMD_OPEN_OVERRIDE 0xa5a5 6828*adfc5217SJeff Kirsher 6829*adfc5217SJeff Kirsher 6830*adfc5217SJeff Kirsher /* 84833 F/W Feature Commands */ 6831*adfc5217SJeff Kirsher #define PHY84833_DIAG_CMD_GET_EEE_MODE 0x27 6832*adfc5217SJeff Kirsher #define PHY84833_DIAG_CMD_SET_EEE_MODE 0x28 6833*adfc5217SJeff Kirsher 6834*adfc5217SJeff Kirsher /* Warpcore clause 45 addressing */ 6835*adfc5217SJeff Kirsher #define MDIO_WC_DEVAD 0x3 6836*adfc5217SJeff Kirsher #define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0 6837*adfc5217SJeff Kirsher #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7 6838*adfc5217SJeff Kirsher #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10 6839*adfc5217SJeff Kirsher #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11 6840*adfc5217SJeff Kirsher #define MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150 0x96 6841*adfc5217SJeff Kirsher #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000 6842*adfc5217SJeff Kirsher #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e 6843*adfc5217SJeff Kirsher #define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010 6844*adfc5217SJeff Kirsher #define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015 6845*adfc5217SJeff Kirsher #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016 6846*adfc5217SJeff Kirsher #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017 6847*adfc5217SJeff Kirsher #define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061 6848*adfc5217SJeff Kirsher #define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071 6849*adfc5217SJeff Kirsher #define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081 6850*adfc5217SJeff Kirsher #define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091 6851*adfc5217SJeff Kirsher #define MDIO_WC_REG_TX0_TX_DRIVER 0x8067 6852*adfc5217SJeff Kirsher #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04 6853*adfc5217SJeff Kirsher #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0 6854*adfc5217SJeff Kirsher #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08 6855*adfc5217SJeff Kirsher #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 6856*adfc5217SJeff Kirsher #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c 6857*adfc5217SJeff Kirsher #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000 6858*adfc5217SJeff Kirsher #define MDIO_WC_REG_TX1_TX_DRIVER 0x8077 6859*adfc5217SJeff Kirsher #define MDIO_WC_REG_TX2_TX_DRIVER 0x8087 6860*adfc5217SJeff Kirsher #define MDIO_WC_REG_TX3_TX_DRIVER 0x8097 6861*adfc5217SJeff Kirsher #define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9 6862*adfc5217SJeff Kirsher #define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9 6863*adfc5217SJeff Kirsher #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba 6864*adfc5217SJeff Kirsher #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca 6865*adfc5217SJeff Kirsher #define MDIO_WC_REG_RX2_PCI_CTRL 0x80da 6866*adfc5217SJeff Kirsher #define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea 6867*adfc5217SJeff Kirsher #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104 6868*adfc5217SJeff Kirsher #define MDIO_WC_REG_XGXS_STATUS3 0x8129 6869*adfc5217SJeff Kirsher #define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130 6870*adfc5217SJeff Kirsher #define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131 6871*adfc5217SJeff Kirsher #define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141 6872*adfc5217SJeff Kirsher #define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B 6873*adfc5217SJeff Kirsher #define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169 6874*adfc5217SJeff Kirsher #define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0 6875*adfc5217SJeff Kirsher #define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1 6876*adfc5217SJeff Kirsher #define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2 6877*adfc5217SJeff Kirsher #define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3 6878*adfc5217SJeff Kirsher #define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4 6879*adfc5217SJeff Kirsher #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE 6880*adfc5217SJeff Kirsher #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0 6881*adfc5217SJeff Kirsher #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2 6882*adfc5217SJeff Kirsher #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0 6883*adfc5217SJeff Kirsher #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0 6884*adfc5217SJeff Kirsher #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1 6885*adfc5217SJeff Kirsher #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2 6886*adfc5217SJeff Kirsher #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3 6887*adfc5217SJeff Kirsher #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4 6888*adfc5217SJeff Kirsher #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4 6889*adfc5217SJeff Kirsher #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8 6890*adfc5217SJeff Kirsher #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc 6891*adfc5217SJeff Kirsher #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE 6892*adfc5217SJeff Kirsher #define MDIO_WC_REG_DSC_SMC 0x8213 6893*adfc5217SJeff Kirsher #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e 6894*adfc5217SJeff Kirsher #define MDIO_WC_REG_TX_FIR_TAP 0x82e2 6895*adfc5217SJeff Kirsher #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00 6896*adfc5217SJeff Kirsher #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f 6897*adfc5217SJeff Kirsher #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04 6898*adfc5217SJeff Kirsher #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0 6899*adfc5217SJeff Kirsher #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a 6900*adfc5217SJeff Kirsher #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00 6901*adfc5217SJeff Kirsher #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000 6902*adfc5217SJeff Kirsher #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3 6903*adfc5217SJeff Kirsher #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6 6904*adfc5217SJeff Kirsher #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7 6905*adfc5217SJeff Kirsher #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8 6906*adfc5217SJeff Kirsher #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec 6907*adfc5217SJeff Kirsher #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300 6908*adfc5217SJeff Kirsher #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301 6909*adfc5217SJeff Kirsher #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302 6910*adfc5217SJeff Kirsher #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304 6911*adfc5217SJeff Kirsher #define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308 6912*adfc5217SJeff Kirsher #define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309 6913*adfc5217SJeff Kirsher #define MDIO_WC_REG_DIGITAL3_UP1 0x8329 6914*adfc5217SJeff Kirsher #define MDIO_WC_REG_DIGITAL4_MISC3 0x833c 6915*adfc5217SJeff Kirsher #define MDIO_WC_REG_DIGITAL5_MISC6 0x8345 6916*adfc5217SJeff Kirsher #define MDIO_WC_REG_DIGITAL5_MISC7 0x8349 6917*adfc5217SJeff Kirsher #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e 6918*adfc5217SJeff Kirsher #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350 6919*adfc5217SJeff Kirsher #define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368 6920*adfc5217SJeff Kirsher #define MDIO_WC_REG_TX66_CONTROL 0x83b0 6921*adfc5217SJeff Kirsher #define MDIO_WC_REG_RX66_CONTROL 0x83c0 6922*adfc5217SJeff Kirsher #define MDIO_WC_REG_RX66_SCW0 0x83c2 6923*adfc5217SJeff Kirsher #define MDIO_WC_REG_RX66_SCW1 0x83c3 6924*adfc5217SJeff Kirsher #define MDIO_WC_REG_RX66_SCW2 0x83c4 6925*adfc5217SJeff Kirsher #define MDIO_WC_REG_RX66_SCW3 0x83c5 6926*adfc5217SJeff Kirsher #define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6 6927*adfc5217SJeff Kirsher #define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7 6928*adfc5217SJeff Kirsher #define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8 6929*adfc5217SJeff Kirsher #define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9 6930*adfc5217SJeff Kirsher #define MDIO_WC_REG_FX100_CTRL1 0x8400 6931*adfc5217SJeff Kirsher #define MDIO_WC_REG_FX100_CTRL3 0x8402 6932*adfc5217SJeff Kirsher 6933*adfc5217SJeff Kirsher #define MDIO_WC_REG_MICROBLK_CMD 0xffc2 6934*adfc5217SJeff Kirsher #define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5 6935*adfc5217SJeff Kirsher #define MDIO_WC_REG_MICROBLK_CMD3 0xffcc 6936*adfc5217SJeff Kirsher 6937*adfc5217SJeff Kirsher #define MDIO_WC_REG_AERBLK_AER 0xffde 6938*adfc5217SJeff Kirsher #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0 6939*adfc5217SJeff Kirsher #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1 6940*adfc5217SJeff Kirsher 6941*adfc5217SJeff Kirsher #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A 6942*adfc5217SJeff Kirsher #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0 6943*adfc5217SJeff Kirsher #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4 6944*adfc5217SJeff Kirsher 6945*adfc5217SJeff Kirsher #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141 6946*adfc5217SJeff Kirsher 6947*adfc5217SJeff Kirsher #define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f 6948*adfc5217SJeff Kirsher 6949*adfc5217SJeff Kirsher /* 54618se */ 6950*adfc5217SJeff Kirsher #define MDIO_REG_GPHY_PHYID_LSB 0x3 6951*adfc5217SJeff Kirsher #define MDIO_REG_GPHY_ID_54618SE 0x5cd5 6952*adfc5217SJeff Kirsher #define MDIO_REG_GPHY_CL45_ADDR_REG 0xd 6953*adfc5217SJeff Kirsher #define MDIO_REG_GPHY_CL45_DATA_REG 0xe 6954*adfc5217SJeff Kirsher #define MDIO_REG_GPHY_EEE_ADV 0x3c 6955*adfc5217SJeff Kirsher #define MDIO_REG_GPHY_EEE_1G (0x1 << 2) 6956*adfc5217SJeff Kirsher #define MDIO_REG_GPHY_EEE_100 (0x1 << 1) 6957*adfc5217SJeff Kirsher #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e 6958*adfc5217SJeff Kirsher #define MDIO_REG_INTR_STATUS 0x1a 6959*adfc5217SJeff Kirsher #define MDIO_REG_INTR_MASK 0x1b 6960*adfc5217SJeff Kirsher #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1) 6961*adfc5217SJeff Kirsher #define MDIO_REG_GPHY_SHADOW 0x1c 6962*adfc5217SJeff Kirsher #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10) 6963*adfc5217SJeff Kirsher #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15) 6964*adfc5217SJeff Kirsher #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10) 6965*adfc5217SJeff Kirsher #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8) 6966*adfc5217SJeff Kirsher 6967*adfc5217SJeff Kirsher #define IGU_FUNC_BASE 0x0400 6968*adfc5217SJeff Kirsher 6969*adfc5217SJeff Kirsher #define IGU_ADDR_MSIX 0x0000 6970*adfc5217SJeff Kirsher #define IGU_ADDR_INT_ACK 0x0200 6971*adfc5217SJeff Kirsher #define IGU_ADDR_PROD_UPD 0x0201 6972*adfc5217SJeff Kirsher #define IGU_ADDR_ATTN_BITS_UPD 0x0202 6973*adfc5217SJeff Kirsher #define IGU_ADDR_ATTN_BITS_SET 0x0203 6974*adfc5217SJeff Kirsher #define IGU_ADDR_ATTN_BITS_CLR 0x0204 6975*adfc5217SJeff Kirsher #define IGU_ADDR_COALESCE_NOW 0x0205 6976*adfc5217SJeff Kirsher #define IGU_ADDR_SIMD_MASK 0x0206 6977*adfc5217SJeff Kirsher #define IGU_ADDR_SIMD_NOMASK 0x0207 6978*adfc5217SJeff Kirsher #define IGU_ADDR_MSI_CTL 0x0210 6979*adfc5217SJeff Kirsher #define IGU_ADDR_MSI_ADDR_LO 0x0211 6980*adfc5217SJeff Kirsher #define IGU_ADDR_MSI_ADDR_HI 0x0212 6981*adfc5217SJeff Kirsher #define IGU_ADDR_MSI_DATA 0x0213 6982*adfc5217SJeff Kirsher 6983*adfc5217SJeff Kirsher #define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0 6984*adfc5217SJeff Kirsher #define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup 1 6985*adfc5217SJeff Kirsher #define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 2 6986*adfc5217SJeff Kirsher #define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup 3 6987*adfc5217SJeff Kirsher 6988*adfc5217SJeff Kirsher #define COMMAND_REG_INT_ACK 0x0 6989*adfc5217SJeff Kirsher #define COMMAND_REG_PROD_UPD 0x4 6990*adfc5217SJeff Kirsher #define COMMAND_REG_ATTN_BITS_UPD 0x8 6991*adfc5217SJeff Kirsher #define COMMAND_REG_ATTN_BITS_SET 0xc 6992*adfc5217SJeff Kirsher #define COMMAND_REG_ATTN_BITS_CLR 0x10 6993*adfc5217SJeff Kirsher #define COMMAND_REG_COALESCE_NOW 0x14 6994*adfc5217SJeff Kirsher #define COMMAND_REG_SIMD_MASK 0x18 6995*adfc5217SJeff Kirsher #define COMMAND_REG_SIMD_NOMASK 0x1c 6996*adfc5217SJeff Kirsher 6997*adfc5217SJeff Kirsher 6998*adfc5217SJeff Kirsher #define IGU_MEM_BASE 0x0000 6999*adfc5217SJeff Kirsher 7000*adfc5217SJeff Kirsher #define IGU_MEM_MSIX_BASE 0x0000 7001*adfc5217SJeff Kirsher #define IGU_MEM_MSIX_UPPER 0x007f 7002*adfc5217SJeff Kirsher #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff 7003*adfc5217SJeff Kirsher 7004*adfc5217SJeff Kirsher #define IGU_MEM_PBA_MSIX_BASE 0x0200 7005*adfc5217SJeff Kirsher #define IGU_MEM_PBA_MSIX_UPPER 0x0200 7006*adfc5217SJeff Kirsher 7007*adfc5217SJeff Kirsher #define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201 7008*adfc5217SJeff Kirsher #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff 7009*adfc5217SJeff Kirsher 7010*adfc5217SJeff Kirsher #define IGU_CMD_INT_ACK_BASE 0x0400 7011*adfc5217SJeff Kirsher #define IGU_CMD_INT_ACK_UPPER\ 7012*adfc5217SJeff Kirsher (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1) 7013*adfc5217SJeff Kirsher #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff 7014*adfc5217SJeff Kirsher 7015*adfc5217SJeff Kirsher #define IGU_CMD_E2_PROD_UPD_BASE 0x0500 7016*adfc5217SJeff Kirsher #define IGU_CMD_E2_PROD_UPD_UPPER\ 7017*adfc5217SJeff Kirsher (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1) 7018*adfc5217SJeff Kirsher #define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f 7019*adfc5217SJeff Kirsher 7020*adfc5217SJeff Kirsher #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0 7021*adfc5217SJeff Kirsher #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1 7022*adfc5217SJeff Kirsher #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2 7023*adfc5217SJeff Kirsher 7024*adfc5217SJeff Kirsher #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3 7025*adfc5217SJeff Kirsher #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4 7026*adfc5217SJeff Kirsher #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5 7027*adfc5217SJeff Kirsher #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6 7028*adfc5217SJeff Kirsher 7029*adfc5217SJeff Kirsher #define IGU_REG_RESERVED_UPPER 0x05ff 7030*adfc5217SJeff Kirsher /* Fields of IGU PF CONFIGRATION REGISTER */ 7031*adfc5217SJeff Kirsher #define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */ 7032*adfc5217SJeff Kirsher #define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */ 7033*adfc5217SJeff Kirsher #define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */ 7034*adfc5217SJeff Kirsher #define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */ 7035*adfc5217SJeff Kirsher #define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */ 7036*adfc5217SJeff Kirsher #define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */ 7037*adfc5217SJeff Kirsher 7038*adfc5217SJeff Kirsher /* Fields of IGU VF CONFIGRATION REGISTER */ 7039*adfc5217SJeff Kirsher #define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */ 7040*adfc5217SJeff Kirsher #define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */ 7041*adfc5217SJeff Kirsher #define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */ 7042*adfc5217SJeff Kirsher #define IGU_VF_CONF_PARENT_SHIFT 2 /* Parent PF */ 7043*adfc5217SJeff Kirsher #define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */ 7044*adfc5217SJeff Kirsher 7045*adfc5217SJeff Kirsher 7046*adfc5217SJeff Kirsher #define IGU_BC_DSB_NUM_SEGS 5 7047*adfc5217SJeff Kirsher #define IGU_BC_NDSB_NUM_SEGS 2 7048*adfc5217SJeff Kirsher #define IGU_NORM_DSB_NUM_SEGS 2 7049*adfc5217SJeff Kirsher #define IGU_NORM_NDSB_NUM_SEGS 1 7050*adfc5217SJeff Kirsher #define IGU_BC_BASE_DSB_PROD 128 7051*adfc5217SJeff Kirsher #define IGU_NORM_BASE_DSB_PROD 136 7052*adfc5217SJeff Kirsher 7053*adfc5217SJeff Kirsher /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \ 7054*adfc5217SJeff Kirsher [5:2] = 0; [1:0] = PF number) */ 7055*adfc5217SJeff Kirsher #define IGU_FID_ENCODE_IS_PF (0x1<<6) 7056*adfc5217SJeff Kirsher #define IGU_FID_ENCODE_IS_PF_SHIFT 6 7057*adfc5217SJeff Kirsher #define IGU_FID_VF_NUM_MASK (0x3f) 7058*adfc5217SJeff Kirsher #define IGU_FID_PF_NUM_MASK (0x7) 7059*adfc5217SJeff Kirsher 7060*adfc5217SJeff Kirsher #define IGU_REG_MAPPING_MEMORY_VALID (1<<0) 7061*adfc5217SJeff Kirsher #define IGU_REG_MAPPING_MEMORY_VECTOR_MASK (0x3F<<1) 7062*adfc5217SJeff Kirsher #define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT 1 7063*adfc5217SJeff Kirsher #define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7) 7064*adfc5217SJeff Kirsher #define IGU_REG_MAPPING_MEMORY_FID_SHIFT 7 7065*adfc5217SJeff Kirsher 7066*adfc5217SJeff Kirsher 7067*adfc5217SJeff Kirsher #define CDU_REGION_NUMBER_XCM_AG 2 7068*adfc5217SJeff Kirsher #define CDU_REGION_NUMBER_UCM_AG 4 7069*adfc5217SJeff Kirsher 7070*adfc5217SJeff Kirsher 7071*adfc5217SJeff Kirsher /** 7072*adfc5217SJeff Kirsher * String-to-compress [31:8] = CID (all 24 bits) 7073*adfc5217SJeff Kirsher * String-to-compress [7:4] = Region 7074*adfc5217SJeff Kirsher * String-to-compress [3:0] = Type 7075*adfc5217SJeff Kirsher */ 7076*adfc5217SJeff Kirsher #define CDU_VALID_DATA(_cid, _region, _type)\ 7077*adfc5217SJeff Kirsher (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf))) 7078*adfc5217SJeff Kirsher #define CDU_CRC8(_cid, _region, _type)\ 7079*adfc5217SJeff Kirsher (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff)) 7080*adfc5217SJeff Kirsher #define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)\ 7081*adfc5217SJeff Kirsher (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f)) 7082*adfc5217SJeff Kirsher #define CDU_RSRVD_VALUE_TYPE_B(_crc, _type)\ 7083*adfc5217SJeff Kirsher (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7)) 7084*adfc5217SJeff Kirsher #define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80) 7085*adfc5217SJeff Kirsher 7086*adfc5217SJeff Kirsher /****************************************************************************** 7087*adfc5217SJeff Kirsher * Description: 7088*adfc5217SJeff Kirsher * Calculates crc 8 on a word value: polynomial 0-1-2-8 7089*adfc5217SJeff Kirsher * Code was translated from Verilog. 7090*adfc5217SJeff Kirsher * Return: 7091*adfc5217SJeff Kirsher *****************************************************************************/ 7092*adfc5217SJeff Kirsher static inline u8 calc_crc8(u32 data, u8 crc) 7093*adfc5217SJeff Kirsher { 7094*adfc5217SJeff Kirsher u8 D[32]; 7095*adfc5217SJeff Kirsher u8 NewCRC[8]; 7096*adfc5217SJeff Kirsher u8 C[8]; 7097*adfc5217SJeff Kirsher u8 crc_res; 7098*adfc5217SJeff Kirsher u8 i; 7099*adfc5217SJeff Kirsher 7100*adfc5217SJeff Kirsher /* split the data into 31 bits */ 7101*adfc5217SJeff Kirsher for (i = 0; i < 32; i++) { 7102*adfc5217SJeff Kirsher D[i] = (u8)(data & 1); 7103*adfc5217SJeff Kirsher data = data >> 1; 7104*adfc5217SJeff Kirsher } 7105*adfc5217SJeff Kirsher 7106*adfc5217SJeff Kirsher /* split the crc into 8 bits */ 7107*adfc5217SJeff Kirsher for (i = 0; i < 8; i++) { 7108*adfc5217SJeff Kirsher C[i] = crc & 1; 7109*adfc5217SJeff Kirsher crc = crc >> 1; 7110*adfc5217SJeff Kirsher } 7111*adfc5217SJeff Kirsher 7112*adfc5217SJeff Kirsher NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^ 7113*adfc5217SJeff Kirsher D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^ 7114*adfc5217SJeff Kirsher C[6] ^ C[7]; 7115*adfc5217SJeff Kirsher NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^ 7116*adfc5217SJeff Kirsher D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^ 7117*adfc5217SJeff Kirsher D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ 7118*adfc5217SJeff Kirsher C[6]; 7119*adfc5217SJeff Kirsher NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^ 7120*adfc5217SJeff Kirsher D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ 7121*adfc5217SJeff Kirsher C[0] ^ C[1] ^ C[4] ^ C[5]; 7122*adfc5217SJeff Kirsher NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^ 7123*adfc5217SJeff Kirsher D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^ 7124*adfc5217SJeff Kirsher C[1] ^ C[2] ^ C[5] ^ C[6]; 7125*adfc5217SJeff Kirsher NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^ 7126*adfc5217SJeff Kirsher D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^ 7127*adfc5217SJeff Kirsher C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7]; 7128*adfc5217SJeff Kirsher NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^ 7129*adfc5217SJeff Kirsher D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^ 7130*adfc5217SJeff Kirsher C[3] ^ C[4] ^ C[7]; 7131*adfc5217SJeff Kirsher NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^ 7132*adfc5217SJeff Kirsher D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^ 7133*adfc5217SJeff Kirsher C[5]; 7134*adfc5217SJeff Kirsher NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^ 7135*adfc5217SJeff Kirsher D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^ 7136*adfc5217SJeff Kirsher C[6]; 7137*adfc5217SJeff Kirsher 7138*adfc5217SJeff Kirsher crc_res = 0; 7139*adfc5217SJeff Kirsher for (i = 0; i < 8; i++) 7140*adfc5217SJeff Kirsher crc_res |= (NewCRC[i] << i); 7141*adfc5217SJeff Kirsher 7142*adfc5217SJeff Kirsher return crc_res; 7143*adfc5217SJeff Kirsher } 7144*adfc5217SJeff Kirsher 7145*adfc5217SJeff Kirsher 7146*adfc5217SJeff Kirsher #endif /* BNX2X_REG_H */ 7147