1 /* bnx2x_main.c: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2011 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17 18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19 20 #include <linux/module.h> 21 #include <linux/moduleparam.h> 22 #include <linux/kernel.h> 23 #include <linux/device.h> /* for dev_info() */ 24 #include <linux/timer.h> 25 #include <linux/errno.h> 26 #include <linux/ioport.h> 27 #include <linux/slab.h> 28 #include <linux/interrupt.h> 29 #include <linux/pci.h> 30 #include <linux/init.h> 31 #include <linux/netdevice.h> 32 #include <linux/etherdevice.h> 33 #include <linux/skbuff.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/bitops.h> 36 #include <linux/irq.h> 37 #include <linux/delay.h> 38 #include <asm/byteorder.h> 39 #include <linux/time.h> 40 #include <linux/ethtool.h> 41 #include <linux/mii.h> 42 #include <linux/if.h> 43 #include <linux/if_vlan.h> 44 #include <net/ip.h> 45 #include <net/ipv6.h> 46 #include <net/tcp.h> 47 #include <net/checksum.h> 48 #include <net/ip6_checksum.h> 49 #include <linux/workqueue.h> 50 #include <linux/crc32.h> 51 #include <linux/crc32c.h> 52 #include <linux/prefetch.h> 53 #include <linux/zlib.h> 54 #include <linux/io.h> 55 #include <linux/stringify.h> 56 #include <linux/vmalloc.h> 57 58 #include "bnx2x.h" 59 #include "bnx2x_init.h" 60 #include "bnx2x_init_ops.h" 61 #include "bnx2x_cmn.h" 62 #include "bnx2x_dcb.h" 63 #include "bnx2x_sp.h" 64 65 #include <linux/firmware.h> 66 #include "bnx2x_fw_file_hdr.h" 67 /* FW files */ 68 #define FW_FILE_VERSION \ 69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ 70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \ 71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \ 72 __stringify(BCM_5710_FW_ENGINEERING_VERSION) 73 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" 74 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" 75 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" 76 77 /* Time in jiffies before concluding the transmitter is hung */ 78 #define TX_TIMEOUT (5*HZ) 79 80 static char version[] __devinitdata = 81 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " 82 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 83 84 MODULE_AUTHOR("Eliezer Tamir"); 85 MODULE_DESCRIPTION("Broadcom NetXtreme II " 86 "BCM57710/57711/57711E/" 87 "57712/57712_MF/57800/57800_MF/57810/57810_MF/" 88 "57840/57840_MF Driver"); 89 MODULE_LICENSE("GPL"); 90 MODULE_VERSION(DRV_MODULE_VERSION); 91 MODULE_FIRMWARE(FW_FILE_NAME_E1); 92 MODULE_FIRMWARE(FW_FILE_NAME_E1H); 93 MODULE_FIRMWARE(FW_FILE_NAME_E2); 94 95 static int multi_mode = 1; 96 module_param(multi_mode, int, 0); 97 MODULE_PARM_DESC(multi_mode, " Multi queue mode " 98 "(0 Disable; 1 Enable (default))"); 99 100 int num_queues; 101 module_param(num_queues, int, 0); 102 MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1" 103 " (default is as a number of CPUs)"); 104 105 static int disable_tpa; 106 module_param(disable_tpa, int, 0); 107 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); 108 109 #define INT_MODE_INTx 1 110 #define INT_MODE_MSI 2 111 static int int_mode; 112 module_param(int_mode, int, 0); 113 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " 114 "(1 INT#x; 2 MSI)"); 115 116 static int dropless_fc; 117 module_param(dropless_fc, int, 0); 118 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); 119 120 static int poll; 121 module_param(poll, int, 0); 122 MODULE_PARM_DESC(poll, " Use polling (for debug)"); 123 124 static int mrrs = -1; 125 module_param(mrrs, int, 0); 126 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); 127 128 static int debug; 129 module_param(debug, int, 0); 130 MODULE_PARM_DESC(debug, " Default debug msglevel"); 131 132 133 134 struct workqueue_struct *bnx2x_wq; 135 136 enum bnx2x_board_type { 137 BCM57710 = 0, 138 BCM57711, 139 BCM57711E, 140 BCM57712, 141 BCM57712_MF, 142 BCM57800, 143 BCM57800_MF, 144 BCM57810, 145 BCM57810_MF, 146 BCM57840, 147 BCM57840_MF 148 }; 149 150 /* indexed by board_type, above */ 151 static struct { 152 char *name; 153 } board_info[] __devinitdata = { 154 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, 155 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, 156 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, 157 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, 158 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, 159 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, 160 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, 161 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, 162 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, 163 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, 164 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit " 165 "Ethernet Multi Function"} 166 }; 167 168 #ifndef PCI_DEVICE_ID_NX2_57710 169 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 170 #endif 171 #ifndef PCI_DEVICE_ID_NX2_57711 172 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 173 #endif 174 #ifndef PCI_DEVICE_ID_NX2_57711E 175 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E 176 #endif 177 #ifndef PCI_DEVICE_ID_NX2_57712 178 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 179 #endif 180 #ifndef PCI_DEVICE_ID_NX2_57712_MF 181 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF 182 #endif 183 #ifndef PCI_DEVICE_ID_NX2_57800 184 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 185 #endif 186 #ifndef PCI_DEVICE_ID_NX2_57800_MF 187 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF 188 #endif 189 #ifndef PCI_DEVICE_ID_NX2_57810 190 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 191 #endif 192 #ifndef PCI_DEVICE_ID_NX2_57810_MF 193 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF 194 #endif 195 #ifndef PCI_DEVICE_ID_NX2_57840 196 #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840 197 #endif 198 #ifndef PCI_DEVICE_ID_NX2_57840_MF 199 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF 200 #endif 201 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { 202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, 203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, 204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, 205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, 206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, 207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, 208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, 209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, 210 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, 211 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 }, 212 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, 213 { 0 } 214 }; 215 216 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); 217 218 /**************************************************************************** 219 * General service functions 220 ****************************************************************************/ 221 222 static inline void __storm_memset_dma_mapping(struct bnx2x *bp, 223 u32 addr, dma_addr_t mapping) 224 { 225 REG_WR(bp, addr, U64_LO(mapping)); 226 REG_WR(bp, addr + 4, U64_HI(mapping)); 227 } 228 229 static inline void storm_memset_spq_addr(struct bnx2x *bp, 230 dma_addr_t mapping, u16 abs_fid) 231 { 232 u32 addr = XSEM_REG_FAST_MEMORY + 233 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); 234 235 __storm_memset_dma_mapping(bp, addr, mapping); 236 } 237 238 static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, 239 u16 pf_id) 240 { 241 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), 242 pf_id); 243 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), 244 pf_id); 245 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), 246 pf_id); 247 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), 248 pf_id); 249 } 250 251 static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, 252 u8 enable) 253 { 254 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), 255 enable); 256 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), 257 enable); 258 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), 259 enable); 260 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), 261 enable); 262 } 263 264 static inline void storm_memset_eq_data(struct bnx2x *bp, 265 struct event_ring_data *eq_data, 266 u16 pfid) 267 { 268 size_t size = sizeof(struct event_ring_data); 269 270 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); 271 272 __storm_memset_struct(bp, addr, size, (u32 *)eq_data); 273 } 274 275 static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, 276 u16 pfid) 277 { 278 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); 279 REG_WR16(bp, addr, eq_prod); 280 } 281 282 /* used only at init 283 * locking is done by mcp 284 */ 285 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) 286 { 287 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 288 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); 289 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 290 PCICFG_VENDOR_ID_OFFSET); 291 } 292 293 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) 294 { 295 u32 val; 296 297 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 298 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); 299 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 300 PCICFG_VENDOR_ID_OFFSET); 301 302 return val; 303 } 304 305 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]" 306 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" 307 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]" 308 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" 309 #define DMAE_DP_DST_NONE "dst_addr [none]" 310 311 static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, 312 int msglvl) 313 { 314 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; 315 316 switch (dmae->opcode & DMAE_COMMAND_DST) { 317 case DMAE_CMD_DST_PCI: 318 if (src_type == DMAE_CMD_SRC_PCI) 319 DP(msglvl, "DMAE: opcode 0x%08x\n" 320 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" 321 "comp_addr [%x:%08x], comp_val 0x%08x\n", 322 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 323 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 324 dmae->comp_addr_hi, dmae->comp_addr_lo, 325 dmae->comp_val); 326 else 327 DP(msglvl, "DMAE: opcode 0x%08x\n" 328 "src [%08x], len [%d*4], dst [%x:%08x]\n" 329 "comp_addr [%x:%08x], comp_val 0x%08x\n", 330 dmae->opcode, dmae->src_addr_lo >> 2, 331 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 332 dmae->comp_addr_hi, dmae->comp_addr_lo, 333 dmae->comp_val); 334 break; 335 case DMAE_CMD_DST_GRC: 336 if (src_type == DMAE_CMD_SRC_PCI) 337 DP(msglvl, "DMAE: opcode 0x%08x\n" 338 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" 339 "comp_addr [%x:%08x], comp_val 0x%08x\n", 340 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 341 dmae->len, dmae->dst_addr_lo >> 2, 342 dmae->comp_addr_hi, dmae->comp_addr_lo, 343 dmae->comp_val); 344 else 345 DP(msglvl, "DMAE: opcode 0x%08x\n" 346 "src [%08x], len [%d*4], dst [%08x]\n" 347 "comp_addr [%x:%08x], comp_val 0x%08x\n", 348 dmae->opcode, dmae->src_addr_lo >> 2, 349 dmae->len, dmae->dst_addr_lo >> 2, 350 dmae->comp_addr_hi, dmae->comp_addr_lo, 351 dmae->comp_val); 352 break; 353 default: 354 if (src_type == DMAE_CMD_SRC_PCI) 355 DP(msglvl, "DMAE: opcode 0x%08x\n" 356 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" 357 "comp_addr [%x:%08x] comp_val 0x%08x\n", 358 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 359 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 360 dmae->comp_val); 361 else 362 DP(msglvl, "DMAE: opcode 0x%08x\n" 363 "src_addr [%08x] len [%d * 4] dst_addr [none]\n" 364 "comp_addr [%x:%08x] comp_val 0x%08x\n", 365 dmae->opcode, dmae->src_addr_lo >> 2, 366 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 367 dmae->comp_val); 368 break; 369 } 370 371 } 372 373 /* copy command into DMAE command memory and set DMAE command go */ 374 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) 375 { 376 u32 cmd_offset; 377 int i; 378 379 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); 380 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { 381 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); 382 383 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n", 384 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i)); 385 } 386 REG_WR(bp, dmae_reg_go_c[idx], 1); 387 } 388 389 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) 390 { 391 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | 392 DMAE_CMD_C_ENABLE); 393 } 394 395 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) 396 { 397 return opcode & ~DMAE_CMD_SRC_RESET; 398 } 399 400 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 401 bool with_comp, u8 comp_type) 402 { 403 u32 opcode = 0; 404 405 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | 406 (dst_type << DMAE_COMMAND_DST_SHIFT)); 407 408 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); 409 410 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); 411 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | 412 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); 413 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); 414 415 #ifdef __BIG_ENDIAN 416 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; 417 #else 418 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; 419 #endif 420 if (with_comp) 421 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); 422 return opcode; 423 } 424 425 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, 426 struct dmae_command *dmae, 427 u8 src_type, u8 dst_type) 428 { 429 memset(dmae, 0, sizeof(struct dmae_command)); 430 431 /* set the opcode */ 432 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, 433 true, DMAE_COMP_PCI); 434 435 /* fill in the completion parameters */ 436 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); 437 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); 438 dmae->comp_val = DMAE_COMP_VAL; 439 } 440 441 /* issue a dmae command over the init-channel and wailt for completion */ 442 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, 443 struct dmae_command *dmae) 444 { 445 u32 *wb_comp = bnx2x_sp(bp, wb_comp); 446 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; 447 int rc = 0; 448 449 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n", 450 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 451 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 452 453 /* 454 * Lock the dmae channel. Disable BHs to prevent a dead-lock 455 * as long as this code is called both from syscall context and 456 * from ndo_set_rx_mode() flow that may be called from BH. 457 */ 458 spin_lock_bh(&bp->dmae_lock); 459 460 /* reset completion */ 461 *wb_comp = 0; 462 463 /* post the command on the channel used for initializations */ 464 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); 465 466 /* wait for completion */ 467 udelay(5); 468 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { 469 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp); 470 471 if (!cnt) { 472 BNX2X_ERR("DMAE timeout!\n"); 473 rc = DMAE_TIMEOUT; 474 goto unlock; 475 } 476 cnt--; 477 udelay(50); 478 } 479 if (*wb_comp & DMAE_PCI_ERR_FLAG) { 480 BNX2X_ERR("DMAE PCI error!\n"); 481 rc = DMAE_PCI_ERROR; 482 } 483 484 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n", 485 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 486 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 487 488 unlock: 489 spin_unlock_bh(&bp->dmae_lock); 490 return rc; 491 } 492 493 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 494 u32 len32) 495 { 496 struct dmae_command dmae; 497 498 if (!bp->dmae_ready) { 499 u32 *data = bnx2x_sp(bp, wb_data[0]); 500 501 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)" 502 " using indirect\n", dst_addr, len32); 503 bnx2x_init_ind_wr(bp, dst_addr, data, len32); 504 return; 505 } 506 507 /* set opcode and fixed command fields */ 508 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); 509 510 /* fill in addresses and len */ 511 dmae.src_addr_lo = U64_LO(dma_addr); 512 dmae.src_addr_hi = U64_HI(dma_addr); 513 dmae.dst_addr_lo = dst_addr >> 2; 514 dmae.dst_addr_hi = 0; 515 dmae.len = len32; 516 517 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); 518 519 /* issue the command and wait for completion */ 520 bnx2x_issue_dmae_with_comp(bp, &dmae); 521 } 522 523 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) 524 { 525 struct dmae_command dmae; 526 527 if (!bp->dmae_ready) { 528 u32 *data = bnx2x_sp(bp, wb_data[0]); 529 int i; 530 531 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)" 532 " using indirect\n", src_addr, len32); 533 for (i = 0; i < len32; i++) 534 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); 535 return; 536 } 537 538 /* set opcode and fixed command fields */ 539 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); 540 541 /* fill in addresses and len */ 542 dmae.src_addr_lo = src_addr >> 2; 543 dmae.src_addr_hi = 0; 544 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); 545 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); 546 dmae.len = len32; 547 548 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); 549 550 /* issue the command and wait for completion */ 551 bnx2x_issue_dmae_with_comp(bp, &dmae); 552 } 553 554 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, 555 u32 addr, u32 len) 556 { 557 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); 558 int offset = 0; 559 560 while (len > dmae_wr_max) { 561 bnx2x_write_dmae(bp, phys_addr + offset, 562 addr + offset, dmae_wr_max); 563 offset += dmae_wr_max * 4; 564 len -= dmae_wr_max; 565 } 566 567 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); 568 } 569 570 /* used only for slowpath so not inlined */ 571 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo) 572 { 573 u32 wb_write[2]; 574 575 wb_write[0] = val_hi; 576 wb_write[1] = val_lo; 577 REG_WR_DMAE(bp, reg, wb_write, 2); 578 } 579 580 #ifdef USE_WB_RD 581 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg) 582 { 583 u32 wb_data[2]; 584 585 REG_RD_DMAE(bp, reg, wb_data, 2); 586 587 return HILO_U64(wb_data[0], wb_data[1]); 588 } 589 #endif 590 591 static int bnx2x_mc_assert(struct bnx2x *bp) 592 { 593 char last_idx; 594 int i, rc = 0; 595 u32 row0, row1, row2, row3; 596 597 /* XSTORM */ 598 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + 599 XSTORM_ASSERT_LIST_INDEX_OFFSET); 600 if (last_idx) 601 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 602 603 /* print the asserts */ 604 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 605 606 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + 607 XSTORM_ASSERT_LIST_OFFSET(i)); 608 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + 609 XSTORM_ASSERT_LIST_OFFSET(i) + 4); 610 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + 611 XSTORM_ASSERT_LIST_OFFSET(i) + 8); 612 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + 613 XSTORM_ASSERT_LIST_OFFSET(i) + 12); 614 615 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 616 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x" 617 " 0x%08x 0x%08x 0x%08x\n", 618 i, row3, row2, row1, row0); 619 rc++; 620 } else { 621 break; 622 } 623 } 624 625 /* TSTORM */ 626 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + 627 TSTORM_ASSERT_LIST_INDEX_OFFSET); 628 if (last_idx) 629 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 630 631 /* print the asserts */ 632 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 633 634 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + 635 TSTORM_ASSERT_LIST_OFFSET(i)); 636 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + 637 TSTORM_ASSERT_LIST_OFFSET(i) + 4); 638 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + 639 TSTORM_ASSERT_LIST_OFFSET(i) + 8); 640 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + 641 TSTORM_ASSERT_LIST_OFFSET(i) + 12); 642 643 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 644 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x" 645 " 0x%08x 0x%08x 0x%08x\n", 646 i, row3, row2, row1, row0); 647 rc++; 648 } else { 649 break; 650 } 651 } 652 653 /* CSTORM */ 654 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + 655 CSTORM_ASSERT_LIST_INDEX_OFFSET); 656 if (last_idx) 657 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 658 659 /* print the asserts */ 660 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 661 662 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + 663 CSTORM_ASSERT_LIST_OFFSET(i)); 664 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + 665 CSTORM_ASSERT_LIST_OFFSET(i) + 4); 666 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + 667 CSTORM_ASSERT_LIST_OFFSET(i) + 8); 668 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + 669 CSTORM_ASSERT_LIST_OFFSET(i) + 12); 670 671 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 672 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x" 673 " 0x%08x 0x%08x 0x%08x\n", 674 i, row3, row2, row1, row0); 675 rc++; 676 } else { 677 break; 678 } 679 } 680 681 /* USTORM */ 682 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + 683 USTORM_ASSERT_LIST_INDEX_OFFSET); 684 if (last_idx) 685 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 686 687 /* print the asserts */ 688 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 689 690 row0 = REG_RD(bp, BAR_USTRORM_INTMEM + 691 USTORM_ASSERT_LIST_OFFSET(i)); 692 row1 = REG_RD(bp, BAR_USTRORM_INTMEM + 693 USTORM_ASSERT_LIST_OFFSET(i) + 4); 694 row2 = REG_RD(bp, BAR_USTRORM_INTMEM + 695 USTORM_ASSERT_LIST_OFFSET(i) + 8); 696 row3 = REG_RD(bp, BAR_USTRORM_INTMEM + 697 USTORM_ASSERT_LIST_OFFSET(i) + 12); 698 699 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 700 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x" 701 " 0x%08x 0x%08x 0x%08x\n", 702 i, row3, row2, row1, row0); 703 rc++; 704 } else { 705 break; 706 } 707 } 708 709 return rc; 710 } 711 712 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) 713 { 714 u32 addr, val; 715 u32 mark, offset; 716 __be32 data[9]; 717 int word; 718 u32 trace_shmem_base; 719 if (BP_NOMCP(bp)) { 720 BNX2X_ERR("NO MCP - can not dump\n"); 721 return; 722 } 723 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", 724 (bp->common.bc_ver & 0xff0000) >> 16, 725 (bp->common.bc_ver & 0xff00) >> 8, 726 (bp->common.bc_ver & 0xff)); 727 728 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); 729 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) 730 printk("%s" "MCP PC at 0x%x\n", lvl, val); 731 732 if (BP_PATH(bp) == 0) 733 trace_shmem_base = bp->common.shmem_base; 734 else 735 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); 736 addr = trace_shmem_base - 0x0800 + 4; 737 mark = REG_RD(bp, addr); 738 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 739 + ((mark + 0x3) & ~0x3) - 0x08000000; 740 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); 741 742 printk("%s", lvl); 743 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { 744 for (word = 0; word < 8; word++) 745 data[word] = htonl(REG_RD(bp, offset + 4*word)); 746 data[8] = 0x0; 747 pr_cont("%s", (char *)data); 748 } 749 for (offset = addr + 4; offset <= mark; offset += 0x8*4) { 750 for (word = 0; word < 8; word++) 751 data[word] = htonl(REG_RD(bp, offset + 4*word)); 752 data[8] = 0x0; 753 pr_cont("%s", (char *)data); 754 } 755 printk("%s" "end of fw dump\n", lvl); 756 } 757 758 static inline void bnx2x_fw_dump(struct bnx2x *bp) 759 { 760 bnx2x_fw_dump_lvl(bp, KERN_ERR); 761 } 762 763 void bnx2x_panic_dump(struct bnx2x *bp) 764 { 765 int i; 766 u16 j; 767 struct hc_sp_status_block_data sp_sb_data; 768 int func = BP_FUNC(bp); 769 #ifdef BNX2X_STOP_ON_ERROR 770 u16 start = 0, end = 0; 771 u8 cos; 772 #endif 773 774 bp->stats_state = STATS_STATE_DISABLED; 775 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); 776 777 BNX2X_ERR("begin crash dump -----------------\n"); 778 779 /* Indices */ 780 /* Common */ 781 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)" 782 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", 783 bp->def_idx, bp->def_att_idx, bp->attn_state, 784 bp->spq_prod_idx, bp->stats_counter); 785 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", 786 bp->def_status_blk->atten_status_block.attn_bits, 787 bp->def_status_blk->atten_status_block.attn_bits_ack, 788 bp->def_status_blk->atten_status_block.status_block_id, 789 bp->def_status_blk->atten_status_block.attn_bits_index); 790 BNX2X_ERR(" def ("); 791 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) 792 pr_cont("0x%x%s", 793 bp->def_status_blk->sp_sb.index_values[i], 794 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); 795 796 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 797 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + 798 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 799 i*sizeof(u32)); 800 801 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", 802 sp_sb_data.igu_sb_id, 803 sp_sb_data.igu_seg_id, 804 sp_sb_data.p_func.pf_id, 805 sp_sb_data.p_func.vnic_id, 806 sp_sb_data.p_func.vf_id, 807 sp_sb_data.p_func.vf_valid, 808 sp_sb_data.state); 809 810 811 for_each_eth_queue(bp, i) { 812 struct bnx2x_fastpath *fp = &bp->fp[i]; 813 int loop; 814 struct hc_status_block_data_e2 sb_data_e2; 815 struct hc_status_block_data_e1x sb_data_e1x; 816 struct hc_status_block_sm *hc_sm_p = 817 CHIP_IS_E1x(bp) ? 818 sb_data_e1x.common.state_machine : 819 sb_data_e2.common.state_machine; 820 struct hc_index_data *hc_index_p = 821 CHIP_IS_E1x(bp) ? 822 sb_data_e1x.index_data : 823 sb_data_e2.index_data; 824 u8 data_size, cos; 825 u32 *sb_data_p; 826 struct bnx2x_fp_txdata txdata; 827 828 /* Rx */ 829 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)" 830 " rx_comp_prod(0x%x)" 831 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", 832 i, fp->rx_bd_prod, fp->rx_bd_cons, 833 fp->rx_comp_prod, 834 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); 835 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)" 836 " fp_hc_idx(0x%x)\n", 837 fp->rx_sge_prod, fp->last_max_sge, 838 le16_to_cpu(fp->fp_hc_idx)); 839 840 /* Tx */ 841 for_each_cos_in_tx_queue(fp, cos) 842 { 843 txdata = fp->txdata[cos]; 844 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)" 845 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)" 846 " *tx_cons_sb(0x%x)\n", 847 i, txdata.tx_pkt_prod, 848 txdata.tx_pkt_cons, txdata.tx_bd_prod, 849 txdata.tx_bd_cons, 850 le16_to_cpu(*txdata.tx_cons_sb)); 851 } 852 853 loop = CHIP_IS_E1x(bp) ? 854 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; 855 856 /* host sb data */ 857 858 #ifdef BCM_CNIC 859 if (IS_FCOE_FP(fp)) 860 continue; 861 #endif 862 BNX2X_ERR(" run indexes ("); 863 for (j = 0; j < HC_SB_MAX_SM; j++) 864 pr_cont("0x%x%s", 865 fp->sb_running_index[j], 866 (j == HC_SB_MAX_SM - 1) ? ")" : " "); 867 868 BNX2X_ERR(" indexes ("); 869 for (j = 0; j < loop; j++) 870 pr_cont("0x%x%s", 871 fp->sb_index_values[j], 872 (j == loop - 1) ? ")" : " "); 873 /* fw sb data */ 874 data_size = CHIP_IS_E1x(bp) ? 875 sizeof(struct hc_status_block_data_e1x) : 876 sizeof(struct hc_status_block_data_e2); 877 data_size /= sizeof(u32); 878 sb_data_p = CHIP_IS_E1x(bp) ? 879 (u32 *)&sb_data_e1x : 880 (u32 *)&sb_data_e2; 881 /* copy sb data in here */ 882 for (j = 0; j < data_size; j++) 883 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + 884 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + 885 j * sizeof(u32)); 886 887 if (!CHIP_IS_E1x(bp)) { 888 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " 889 "vnic_id(0x%x) same_igu_sb_1b(0x%x) " 890 "state(0x%x)\n", 891 sb_data_e2.common.p_func.pf_id, 892 sb_data_e2.common.p_func.vf_id, 893 sb_data_e2.common.p_func.vf_valid, 894 sb_data_e2.common.p_func.vnic_id, 895 sb_data_e2.common.same_igu_sb_1b, 896 sb_data_e2.common.state); 897 } else { 898 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " 899 "vnic_id(0x%x) same_igu_sb_1b(0x%x) " 900 "state(0x%x)\n", 901 sb_data_e1x.common.p_func.pf_id, 902 sb_data_e1x.common.p_func.vf_id, 903 sb_data_e1x.common.p_func.vf_valid, 904 sb_data_e1x.common.p_func.vnic_id, 905 sb_data_e1x.common.same_igu_sb_1b, 906 sb_data_e1x.common.state); 907 } 908 909 /* SB_SMs data */ 910 for (j = 0; j < HC_SB_MAX_SM; j++) { 911 pr_cont("SM[%d] __flags (0x%x) " 912 "igu_sb_id (0x%x) igu_seg_id(0x%x) " 913 "time_to_expire (0x%x) " 914 "timer_value(0x%x)\n", j, 915 hc_sm_p[j].__flags, 916 hc_sm_p[j].igu_sb_id, 917 hc_sm_p[j].igu_seg_id, 918 hc_sm_p[j].time_to_expire, 919 hc_sm_p[j].timer_value); 920 } 921 922 /* Indecies data */ 923 for (j = 0; j < loop; j++) { 924 pr_cont("INDEX[%d] flags (0x%x) " 925 "timeout (0x%x)\n", j, 926 hc_index_p[j].flags, 927 hc_index_p[j].timeout); 928 } 929 } 930 931 #ifdef BNX2X_STOP_ON_ERROR 932 /* Rings */ 933 /* Rx */ 934 for_each_rx_queue(bp, i) { 935 struct bnx2x_fastpath *fp = &bp->fp[i]; 936 937 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); 938 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); 939 for (j = start; j != end; j = RX_BD(j + 1)) { 940 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; 941 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; 942 943 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", 944 i, j, rx_bd[1], rx_bd[0], sw_bd->skb); 945 } 946 947 start = RX_SGE(fp->rx_sge_prod); 948 end = RX_SGE(fp->last_max_sge); 949 for (j = start; j != end; j = RX_SGE(j + 1)) { 950 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; 951 struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; 952 953 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", 954 i, j, rx_sge[1], rx_sge[0], sw_page->page); 955 } 956 957 start = RCQ_BD(fp->rx_comp_cons - 10); 958 end = RCQ_BD(fp->rx_comp_cons + 503); 959 for (j = start; j != end; j = RCQ_BD(j + 1)) { 960 u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; 961 962 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", 963 i, j, cqe[0], cqe[1], cqe[2], cqe[3]); 964 } 965 } 966 967 /* Tx */ 968 for_each_tx_queue(bp, i) { 969 struct bnx2x_fastpath *fp = &bp->fp[i]; 970 for_each_cos_in_tx_queue(fp, cos) { 971 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos]; 972 973 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); 974 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); 975 for (j = start; j != end; j = TX_BD(j + 1)) { 976 struct sw_tx_bd *sw_bd = 977 &txdata->tx_buf_ring[j]; 978 979 BNX2X_ERR("fp%d: txdata %d, " 980 "packet[%x]=[%p,%x]\n", 981 i, cos, j, sw_bd->skb, 982 sw_bd->first_bd); 983 } 984 985 start = TX_BD(txdata->tx_bd_cons - 10); 986 end = TX_BD(txdata->tx_bd_cons + 254); 987 for (j = start; j != end; j = TX_BD(j + 1)) { 988 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; 989 990 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=" 991 "[%x:%x:%x:%x]\n", 992 i, cos, j, tx_bd[0], tx_bd[1], 993 tx_bd[2], tx_bd[3]); 994 } 995 } 996 } 997 #endif 998 bnx2x_fw_dump(bp); 999 bnx2x_mc_assert(bp); 1000 BNX2X_ERR("end crash dump -----------------\n"); 1001 } 1002 1003 /* 1004 * FLR Support for E2 1005 * 1006 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW 1007 * initialization. 1008 */ 1009 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */ 1010 #define FLR_WAIT_INTERAVAL 50 /* usec */ 1011 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */ 1012 1013 struct pbf_pN_buf_regs { 1014 int pN; 1015 u32 init_crd; 1016 u32 crd; 1017 u32 crd_freed; 1018 }; 1019 1020 struct pbf_pN_cmd_regs { 1021 int pN; 1022 u32 lines_occup; 1023 u32 lines_freed; 1024 }; 1025 1026 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, 1027 struct pbf_pN_buf_regs *regs, 1028 u32 poll_count) 1029 { 1030 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; 1031 u32 cur_cnt = poll_count; 1032 1033 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); 1034 crd = crd_start = REG_RD(bp, regs->crd); 1035 init_crd = REG_RD(bp, regs->init_crd); 1036 1037 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); 1038 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); 1039 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); 1040 1041 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < 1042 (init_crd - crd_start))) { 1043 if (cur_cnt--) { 1044 udelay(FLR_WAIT_INTERAVAL); 1045 crd = REG_RD(bp, regs->crd); 1046 crd_freed = REG_RD(bp, regs->crd_freed); 1047 } else { 1048 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", 1049 regs->pN); 1050 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", 1051 regs->pN, crd); 1052 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", 1053 regs->pN, crd_freed); 1054 break; 1055 } 1056 } 1057 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", 1058 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN); 1059 } 1060 1061 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, 1062 struct pbf_pN_cmd_regs *regs, 1063 u32 poll_count) 1064 { 1065 u32 occup, to_free, freed, freed_start; 1066 u32 cur_cnt = poll_count; 1067 1068 occup = to_free = REG_RD(bp, regs->lines_occup); 1069 freed = freed_start = REG_RD(bp, regs->lines_freed); 1070 1071 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); 1072 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); 1073 1074 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { 1075 if (cur_cnt--) { 1076 udelay(FLR_WAIT_INTERAVAL); 1077 occup = REG_RD(bp, regs->lines_occup); 1078 freed = REG_RD(bp, regs->lines_freed); 1079 } else { 1080 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", 1081 regs->pN); 1082 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", 1083 regs->pN, occup); 1084 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", 1085 regs->pN, freed); 1086 break; 1087 } 1088 } 1089 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", 1090 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN); 1091 } 1092 1093 static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, 1094 u32 expected, u32 poll_count) 1095 { 1096 u32 cur_cnt = poll_count; 1097 u32 val; 1098 1099 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) 1100 udelay(FLR_WAIT_INTERAVAL); 1101 1102 return val; 1103 } 1104 1105 static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 1106 char *msg, u32 poll_cnt) 1107 { 1108 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); 1109 if (val != 0) { 1110 BNX2X_ERR("%s usage count=%d\n", msg, val); 1111 return 1; 1112 } 1113 return 0; 1114 } 1115 1116 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) 1117 { 1118 /* adjust polling timeout */ 1119 if (CHIP_REV_IS_EMUL(bp)) 1120 return FLR_POLL_CNT * 2000; 1121 1122 if (CHIP_REV_IS_FPGA(bp)) 1123 return FLR_POLL_CNT * 120; 1124 1125 return FLR_POLL_CNT; 1126 } 1127 1128 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) 1129 { 1130 struct pbf_pN_cmd_regs cmd_regs[] = { 1131 {0, (CHIP_IS_E3B0(bp)) ? 1132 PBF_REG_TQ_OCCUPANCY_Q0 : 1133 PBF_REG_P0_TQ_OCCUPANCY, 1134 (CHIP_IS_E3B0(bp)) ? 1135 PBF_REG_TQ_LINES_FREED_CNT_Q0 : 1136 PBF_REG_P0_TQ_LINES_FREED_CNT}, 1137 {1, (CHIP_IS_E3B0(bp)) ? 1138 PBF_REG_TQ_OCCUPANCY_Q1 : 1139 PBF_REG_P1_TQ_OCCUPANCY, 1140 (CHIP_IS_E3B0(bp)) ? 1141 PBF_REG_TQ_LINES_FREED_CNT_Q1 : 1142 PBF_REG_P1_TQ_LINES_FREED_CNT}, 1143 {4, (CHIP_IS_E3B0(bp)) ? 1144 PBF_REG_TQ_OCCUPANCY_LB_Q : 1145 PBF_REG_P4_TQ_OCCUPANCY, 1146 (CHIP_IS_E3B0(bp)) ? 1147 PBF_REG_TQ_LINES_FREED_CNT_LB_Q : 1148 PBF_REG_P4_TQ_LINES_FREED_CNT} 1149 }; 1150 1151 struct pbf_pN_buf_regs buf_regs[] = { 1152 {0, (CHIP_IS_E3B0(bp)) ? 1153 PBF_REG_INIT_CRD_Q0 : 1154 PBF_REG_P0_INIT_CRD , 1155 (CHIP_IS_E3B0(bp)) ? 1156 PBF_REG_CREDIT_Q0 : 1157 PBF_REG_P0_CREDIT, 1158 (CHIP_IS_E3B0(bp)) ? 1159 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : 1160 PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, 1161 {1, (CHIP_IS_E3B0(bp)) ? 1162 PBF_REG_INIT_CRD_Q1 : 1163 PBF_REG_P1_INIT_CRD, 1164 (CHIP_IS_E3B0(bp)) ? 1165 PBF_REG_CREDIT_Q1 : 1166 PBF_REG_P1_CREDIT, 1167 (CHIP_IS_E3B0(bp)) ? 1168 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : 1169 PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, 1170 {4, (CHIP_IS_E3B0(bp)) ? 1171 PBF_REG_INIT_CRD_LB_Q : 1172 PBF_REG_P4_INIT_CRD, 1173 (CHIP_IS_E3B0(bp)) ? 1174 PBF_REG_CREDIT_LB_Q : 1175 PBF_REG_P4_CREDIT, 1176 (CHIP_IS_E3B0(bp)) ? 1177 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : 1178 PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, 1179 }; 1180 1181 int i; 1182 1183 /* Verify the command queues are flushed P0, P1, P4 */ 1184 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) 1185 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); 1186 1187 1188 /* Verify the transmission buffers are flushed P0, P1, P4 */ 1189 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) 1190 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); 1191 } 1192 1193 #define OP_GEN_PARAM(param) \ 1194 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) 1195 1196 #define OP_GEN_TYPE(type) \ 1197 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) 1198 1199 #define OP_GEN_AGG_VECT(index) \ 1200 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) 1201 1202 1203 static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, 1204 u32 poll_cnt) 1205 { 1206 struct sdm_op_gen op_gen = {0}; 1207 1208 u32 comp_addr = BAR_CSTRORM_INTMEM + 1209 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); 1210 int ret = 0; 1211 1212 if (REG_RD(bp, comp_addr)) { 1213 BNX2X_ERR("Cleanup complete is not 0\n"); 1214 return 1; 1215 } 1216 1217 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); 1218 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); 1219 op_gen.command |= OP_GEN_AGG_VECT(clnup_func); 1220 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; 1221 1222 DP(BNX2X_MSG_SP, "FW Final cleanup\n"); 1223 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command); 1224 1225 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { 1226 BNX2X_ERR("FW final cleanup did not succeed\n"); 1227 ret = 1; 1228 } 1229 /* Zero completion for nxt FLR */ 1230 REG_WR(bp, comp_addr, 0); 1231 1232 return ret; 1233 } 1234 1235 static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev) 1236 { 1237 int pos; 1238 u16 status; 1239 1240 pos = pci_pcie_cap(dev); 1241 if (!pos) 1242 return false; 1243 1244 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); 1245 return status & PCI_EXP_DEVSTA_TRPND; 1246 } 1247 1248 /* PF FLR specific routines 1249 */ 1250 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) 1251 { 1252 1253 /* wait for CFC PF usage-counter to zero (includes all the VFs) */ 1254 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1255 CFC_REG_NUM_LCIDS_INSIDE_PF, 1256 "CFC PF usage counter timed out", 1257 poll_cnt)) 1258 return 1; 1259 1260 1261 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ 1262 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1263 DORQ_REG_PF_USAGE_CNT, 1264 "DQ PF usage counter timed out", 1265 poll_cnt)) 1266 return 1; 1267 1268 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ 1269 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1270 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), 1271 "QM PF usage counter timed out", 1272 poll_cnt)) 1273 return 1; 1274 1275 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ 1276 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1277 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), 1278 "Timers VNIC usage counter timed out", 1279 poll_cnt)) 1280 return 1; 1281 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1282 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), 1283 "Timers NUM_SCANS usage counter timed out", 1284 poll_cnt)) 1285 return 1; 1286 1287 /* Wait DMAE PF usage counter to zero */ 1288 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1289 dmae_reg_go_c[INIT_DMAE_C(bp)], 1290 "DMAE dommand register timed out", 1291 poll_cnt)) 1292 return 1; 1293 1294 return 0; 1295 } 1296 1297 static void bnx2x_hw_enable_status(struct bnx2x *bp) 1298 { 1299 u32 val; 1300 1301 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); 1302 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); 1303 1304 val = REG_RD(bp, PBF_REG_DISABLE_PF); 1305 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); 1306 1307 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); 1308 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); 1309 1310 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); 1311 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); 1312 1313 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); 1314 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); 1315 1316 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); 1317 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); 1318 1319 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); 1320 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); 1321 1322 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1323 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", 1324 val); 1325 } 1326 1327 static int bnx2x_pf_flr_clnup(struct bnx2x *bp) 1328 { 1329 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); 1330 1331 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); 1332 1333 /* Re-enable PF target read access */ 1334 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1335 1336 /* Poll HW usage counters */ 1337 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) 1338 return -EBUSY; 1339 1340 /* Zero the igu 'trailing edge' and 'leading edge' */ 1341 1342 /* Send the FW cleanup command */ 1343 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) 1344 return -EBUSY; 1345 1346 /* ATC cleanup */ 1347 1348 /* Verify TX hw is flushed */ 1349 bnx2x_tx_hw_flushed(bp, poll_cnt); 1350 1351 /* Wait 100ms (not adjusted according to platform) */ 1352 msleep(100); 1353 1354 /* Verify no pending pci transactions */ 1355 if (bnx2x_is_pcie_pending(bp->pdev)) 1356 BNX2X_ERR("PCIE Transactions still pending\n"); 1357 1358 /* Debug */ 1359 bnx2x_hw_enable_status(bp); 1360 1361 /* 1362 * Master enable - Due to WB DMAE writes performed before this 1363 * register is re-initialized as part of the regular function init 1364 */ 1365 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 1366 1367 return 0; 1368 } 1369 1370 static void bnx2x_hc_int_enable(struct bnx2x *bp) 1371 { 1372 int port = BP_PORT(bp); 1373 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1374 u32 val = REG_RD(bp, addr); 1375 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1376 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; 1377 1378 if (msix) { 1379 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1380 HC_CONFIG_0_REG_INT_LINE_EN_0); 1381 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1382 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1383 } else if (msi) { 1384 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; 1385 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1386 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1387 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1388 } else { 1389 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1390 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1391 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1392 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1393 1394 if (!CHIP_IS_E1(bp)) { 1395 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", 1396 val, port, addr); 1397 1398 REG_WR(bp, addr, val); 1399 1400 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; 1401 } 1402 } 1403 1404 if (CHIP_IS_E1(bp)) 1405 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); 1406 1407 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n", 1408 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1409 1410 REG_WR(bp, addr, val); 1411 /* 1412 * Ensure that HC_CONFIG is written before leading/trailing edge config 1413 */ 1414 mmiowb(); 1415 barrier(); 1416 1417 if (!CHIP_IS_E1(bp)) { 1418 /* init leading/trailing edge */ 1419 if (IS_MF(bp)) { 1420 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1421 if (bp->port.pmf) 1422 /* enable nig and gpio3 attention */ 1423 val |= 0x1100; 1424 } else 1425 val = 0xffff; 1426 1427 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 1428 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 1429 } 1430 1431 /* Make sure that interrupts are indeed enabled from here on */ 1432 mmiowb(); 1433 } 1434 1435 static void bnx2x_igu_int_enable(struct bnx2x *bp) 1436 { 1437 u32 val; 1438 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1439 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; 1440 1441 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1442 1443 if (msix) { 1444 val &= ~(IGU_PF_CONF_INT_LINE_EN | 1445 IGU_PF_CONF_SINGLE_ISR_EN); 1446 val |= (IGU_PF_CONF_FUNC_EN | 1447 IGU_PF_CONF_MSI_MSIX_EN | 1448 IGU_PF_CONF_ATTN_BIT_EN); 1449 } else if (msi) { 1450 val &= ~IGU_PF_CONF_INT_LINE_EN; 1451 val |= (IGU_PF_CONF_FUNC_EN | 1452 IGU_PF_CONF_MSI_MSIX_EN | 1453 IGU_PF_CONF_ATTN_BIT_EN | 1454 IGU_PF_CONF_SINGLE_ISR_EN); 1455 } else { 1456 val &= ~IGU_PF_CONF_MSI_MSIX_EN; 1457 val |= (IGU_PF_CONF_FUNC_EN | 1458 IGU_PF_CONF_INT_LINE_EN | 1459 IGU_PF_CONF_ATTN_BIT_EN | 1460 IGU_PF_CONF_SINGLE_ISR_EN); 1461 } 1462 1463 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n", 1464 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1465 1466 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1467 1468 barrier(); 1469 1470 /* init leading/trailing edge */ 1471 if (IS_MF(bp)) { 1472 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1473 if (bp->port.pmf) 1474 /* enable nig and gpio3 attention */ 1475 val |= 0x1100; 1476 } else 1477 val = 0xffff; 1478 1479 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 1480 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 1481 1482 /* Make sure that interrupts are indeed enabled from here on */ 1483 mmiowb(); 1484 } 1485 1486 void bnx2x_int_enable(struct bnx2x *bp) 1487 { 1488 if (bp->common.int_block == INT_BLOCK_HC) 1489 bnx2x_hc_int_enable(bp); 1490 else 1491 bnx2x_igu_int_enable(bp); 1492 } 1493 1494 static void bnx2x_hc_int_disable(struct bnx2x *bp) 1495 { 1496 int port = BP_PORT(bp); 1497 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1498 u32 val = REG_RD(bp, addr); 1499 1500 /* 1501 * in E1 we must use only PCI configuration space to disable 1502 * MSI/MSIX capablility 1503 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block 1504 */ 1505 if (CHIP_IS_E1(bp)) { 1506 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on 1507 * Use mask register to prevent from HC sending interrupts 1508 * after we exit the function 1509 */ 1510 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); 1511 1512 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1513 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1514 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1515 } else 1516 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1517 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1518 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1519 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1520 1521 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", 1522 val, port, addr); 1523 1524 /* flush all outstanding writes */ 1525 mmiowb(); 1526 1527 REG_WR(bp, addr, val); 1528 if (REG_RD(bp, addr) != val) 1529 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1530 } 1531 1532 static void bnx2x_igu_int_disable(struct bnx2x *bp) 1533 { 1534 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1535 1536 val &= ~(IGU_PF_CONF_MSI_MSIX_EN | 1537 IGU_PF_CONF_INT_LINE_EN | 1538 IGU_PF_CONF_ATTN_BIT_EN); 1539 1540 DP(NETIF_MSG_INTR, "write %x to IGU\n", val); 1541 1542 /* flush all outstanding writes */ 1543 mmiowb(); 1544 1545 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1546 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) 1547 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1548 } 1549 1550 void bnx2x_int_disable(struct bnx2x *bp) 1551 { 1552 if (bp->common.int_block == INT_BLOCK_HC) 1553 bnx2x_hc_int_disable(bp); 1554 else 1555 bnx2x_igu_int_disable(bp); 1556 } 1557 1558 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) 1559 { 1560 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1561 int i, offset; 1562 1563 if (disable_hw) 1564 /* prevent the HW from sending interrupts */ 1565 bnx2x_int_disable(bp); 1566 1567 /* make sure all ISRs are done */ 1568 if (msix) { 1569 synchronize_irq(bp->msix_table[0].vector); 1570 offset = 1; 1571 #ifdef BCM_CNIC 1572 offset++; 1573 #endif 1574 for_each_eth_queue(bp, i) 1575 synchronize_irq(bp->msix_table[offset++].vector); 1576 } else 1577 synchronize_irq(bp->pdev->irq); 1578 1579 /* make sure sp_task is not running */ 1580 cancel_delayed_work(&bp->sp_task); 1581 cancel_delayed_work(&bp->period_task); 1582 flush_workqueue(bnx2x_wq); 1583 } 1584 1585 /* fast path */ 1586 1587 /* 1588 * General service functions 1589 */ 1590 1591 /* Return true if succeeded to acquire the lock */ 1592 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) 1593 { 1594 u32 lock_status; 1595 u32 resource_bit = (1 << resource); 1596 int func = BP_FUNC(bp); 1597 u32 hw_lock_control_reg; 1598 1599 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource); 1600 1601 /* Validating that the resource is within range */ 1602 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1603 DP(NETIF_MSG_HW, 1604 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1605 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1606 return false; 1607 } 1608 1609 if (func <= 5) 1610 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1611 else 1612 hw_lock_control_reg = 1613 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1614 1615 /* Try to acquire the lock */ 1616 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1617 lock_status = REG_RD(bp, hw_lock_control_reg); 1618 if (lock_status & resource_bit) 1619 return true; 1620 1621 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource); 1622 return false; 1623 } 1624 1625 /** 1626 * bnx2x_get_leader_lock_resource - get the recovery leader resource id 1627 * 1628 * @bp: driver handle 1629 * 1630 * Returns the recovery leader resource id according to the engine this function 1631 * belongs to. Currently only only 2 engines is supported. 1632 */ 1633 static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp) 1634 { 1635 if (BP_PATH(bp)) 1636 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; 1637 else 1638 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; 1639 } 1640 1641 /** 1642 * bnx2x_trylock_leader_lock- try to aquire a leader lock. 1643 * 1644 * @bp: driver handle 1645 * 1646 * Tries to aquire a leader lock for cuurent engine. 1647 */ 1648 static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp) 1649 { 1650 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1651 } 1652 1653 #ifdef BCM_CNIC 1654 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); 1655 #endif 1656 1657 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) 1658 { 1659 struct bnx2x *bp = fp->bp; 1660 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1661 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1662 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; 1663 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj; 1664 1665 DP(BNX2X_MSG_SP, 1666 "fp %d cid %d got ramrod #%d state is %x type is %d\n", 1667 fp->index, cid, command, bp->state, 1668 rr_cqe->ramrod_cqe.ramrod_type); 1669 1670 switch (command) { 1671 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): 1672 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); 1673 drv_cmd = BNX2X_Q_CMD_UPDATE; 1674 break; 1675 1676 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): 1677 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); 1678 drv_cmd = BNX2X_Q_CMD_SETUP; 1679 break; 1680 1681 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): 1682 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid); 1683 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 1684 break; 1685 1686 case (RAMROD_CMD_ID_ETH_HALT): 1687 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); 1688 drv_cmd = BNX2X_Q_CMD_HALT; 1689 break; 1690 1691 case (RAMROD_CMD_ID_ETH_TERMINATE): 1692 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid); 1693 drv_cmd = BNX2X_Q_CMD_TERMINATE; 1694 break; 1695 1696 case (RAMROD_CMD_ID_ETH_EMPTY): 1697 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); 1698 drv_cmd = BNX2X_Q_CMD_EMPTY; 1699 break; 1700 1701 default: 1702 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", 1703 command, fp->index); 1704 return; 1705 } 1706 1707 if ((drv_cmd != BNX2X_Q_CMD_MAX) && 1708 q_obj->complete_cmd(bp, q_obj, drv_cmd)) 1709 /* q_obj->complete_cmd() failure means that this was 1710 * an unexpected completion. 1711 * 1712 * In this case we don't want to increase the bp->spq_left 1713 * because apparently we haven't sent this command the first 1714 * place. 1715 */ 1716 #ifdef BNX2X_STOP_ON_ERROR 1717 bnx2x_panic(); 1718 #else 1719 return; 1720 #endif 1721 1722 smp_mb__before_atomic_inc(); 1723 atomic_inc(&bp->cq_spq_left); 1724 /* push the change in bp->spq_left and towards the memory */ 1725 smp_mb__after_atomic_inc(); 1726 1727 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); 1728 1729 return; 1730 } 1731 1732 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, 1733 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod) 1734 { 1735 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset; 1736 1737 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod, 1738 start); 1739 } 1740 1741 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) 1742 { 1743 struct bnx2x *bp = netdev_priv(dev_instance); 1744 u16 status = bnx2x_ack_int(bp); 1745 u16 mask; 1746 int i; 1747 u8 cos; 1748 1749 /* Return here if interrupt is shared and it's not for us */ 1750 if (unlikely(status == 0)) { 1751 DP(NETIF_MSG_INTR, "not our interrupt!\n"); 1752 return IRQ_NONE; 1753 } 1754 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); 1755 1756 #ifdef BNX2X_STOP_ON_ERROR 1757 if (unlikely(bp->panic)) 1758 return IRQ_HANDLED; 1759 #endif 1760 1761 for_each_eth_queue(bp, i) { 1762 struct bnx2x_fastpath *fp = &bp->fp[i]; 1763 1764 mask = 0x2 << (fp->index + CNIC_PRESENT); 1765 if (status & mask) { 1766 /* Handle Rx or Tx according to SB id */ 1767 prefetch(fp->rx_cons_sb); 1768 for_each_cos_in_tx_queue(fp, cos) 1769 prefetch(fp->txdata[cos].tx_cons_sb); 1770 prefetch(&fp->sb_running_index[SM_RX_ID]); 1771 napi_schedule(&bnx2x_fp(bp, fp->index, napi)); 1772 status &= ~mask; 1773 } 1774 } 1775 1776 #ifdef BCM_CNIC 1777 mask = 0x2; 1778 if (status & (mask | 0x1)) { 1779 struct cnic_ops *c_ops = NULL; 1780 1781 if (likely(bp->state == BNX2X_STATE_OPEN)) { 1782 rcu_read_lock(); 1783 c_ops = rcu_dereference(bp->cnic_ops); 1784 if (c_ops) 1785 c_ops->cnic_handler(bp->cnic_data, NULL); 1786 rcu_read_unlock(); 1787 } 1788 1789 status &= ~mask; 1790 } 1791 #endif 1792 1793 if (unlikely(status & 0x1)) { 1794 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 1795 1796 status &= ~0x1; 1797 if (!status) 1798 return IRQ_HANDLED; 1799 } 1800 1801 if (unlikely(status)) 1802 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 1803 status); 1804 1805 return IRQ_HANDLED; 1806 } 1807 1808 /* Link */ 1809 1810 /* 1811 * General service functions 1812 */ 1813 1814 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) 1815 { 1816 u32 lock_status; 1817 u32 resource_bit = (1 << resource); 1818 int func = BP_FUNC(bp); 1819 u32 hw_lock_control_reg; 1820 int cnt; 1821 1822 /* Validating that the resource is within range */ 1823 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1824 DP(NETIF_MSG_HW, 1825 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1826 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1827 return -EINVAL; 1828 } 1829 1830 if (func <= 5) { 1831 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1832 } else { 1833 hw_lock_control_reg = 1834 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1835 } 1836 1837 /* Validating that the resource is not already taken */ 1838 lock_status = REG_RD(bp, hw_lock_control_reg); 1839 if (lock_status & resource_bit) { 1840 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1841 lock_status, resource_bit); 1842 return -EEXIST; 1843 } 1844 1845 /* Try for 5 second every 5ms */ 1846 for (cnt = 0; cnt < 1000; cnt++) { 1847 /* Try to acquire the lock */ 1848 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1849 lock_status = REG_RD(bp, hw_lock_control_reg); 1850 if (lock_status & resource_bit) 1851 return 0; 1852 1853 msleep(5); 1854 } 1855 DP(NETIF_MSG_HW, "Timeout\n"); 1856 return -EAGAIN; 1857 } 1858 1859 int bnx2x_release_leader_lock(struct bnx2x *bp) 1860 { 1861 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1862 } 1863 1864 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) 1865 { 1866 u32 lock_status; 1867 u32 resource_bit = (1 << resource); 1868 int func = BP_FUNC(bp); 1869 u32 hw_lock_control_reg; 1870 1871 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource); 1872 1873 /* Validating that the resource is within range */ 1874 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1875 DP(NETIF_MSG_HW, 1876 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1877 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1878 return -EINVAL; 1879 } 1880 1881 if (func <= 5) { 1882 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1883 } else { 1884 hw_lock_control_reg = 1885 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1886 } 1887 1888 /* Validating that the resource is currently taken */ 1889 lock_status = REG_RD(bp, hw_lock_control_reg); 1890 if (!(lock_status & resource_bit)) { 1891 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1892 lock_status, resource_bit); 1893 return -EFAULT; 1894 } 1895 1896 REG_WR(bp, hw_lock_control_reg, resource_bit); 1897 return 0; 1898 } 1899 1900 1901 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) 1902 { 1903 /* The GPIO should be swapped if swap register is set and active */ 1904 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1905 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1906 int gpio_shift = gpio_num + 1907 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1908 u32 gpio_mask = (1 << gpio_shift); 1909 u32 gpio_reg; 1910 int value; 1911 1912 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1913 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1914 return -EINVAL; 1915 } 1916 1917 /* read GPIO value */ 1918 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 1919 1920 /* get the requested pin value */ 1921 if ((gpio_reg & gpio_mask) == gpio_mask) 1922 value = 1; 1923 else 1924 value = 0; 1925 1926 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); 1927 1928 return value; 1929 } 1930 1931 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 1932 { 1933 /* The GPIO should be swapped if swap register is set and active */ 1934 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1935 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1936 int gpio_shift = gpio_num + 1937 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1938 u32 gpio_mask = (1 << gpio_shift); 1939 u32 gpio_reg; 1940 1941 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1942 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1943 return -EINVAL; 1944 } 1945 1946 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1947 /* read GPIO and mask except the float bits */ 1948 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 1949 1950 switch (mode) { 1951 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 1952 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n", 1953 gpio_num, gpio_shift); 1954 /* clear FLOAT and set CLR */ 1955 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1956 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); 1957 break; 1958 1959 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 1960 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n", 1961 gpio_num, gpio_shift); 1962 /* clear FLOAT and set SET */ 1963 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1964 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); 1965 break; 1966 1967 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 1968 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n", 1969 gpio_num, gpio_shift); 1970 /* set FLOAT */ 1971 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1972 break; 1973 1974 default: 1975 break; 1976 } 1977 1978 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 1979 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1980 1981 return 0; 1982 } 1983 1984 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) 1985 { 1986 u32 gpio_reg = 0; 1987 int rc = 0; 1988 1989 /* Any port swapping should be handled by caller. */ 1990 1991 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1992 /* read GPIO and mask except the float bits */ 1993 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 1994 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); 1995 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); 1996 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); 1997 1998 switch (mode) { 1999 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2000 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); 2001 /* set CLR */ 2002 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); 2003 break; 2004 2005 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2006 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); 2007 /* set SET */ 2008 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); 2009 break; 2010 2011 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2012 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); 2013 /* set FLOAT */ 2014 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2015 break; 2016 2017 default: 2018 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); 2019 rc = -EINVAL; 2020 break; 2021 } 2022 2023 if (rc == 0) 2024 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 2025 2026 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2027 2028 return rc; 2029 } 2030 2031 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 2032 { 2033 /* The GPIO should be swapped if swap register is set and active */ 2034 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2035 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2036 int gpio_shift = gpio_num + 2037 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2038 u32 gpio_mask = (1 << gpio_shift); 2039 u32 gpio_reg; 2040 2041 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2042 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2043 return -EINVAL; 2044 } 2045 2046 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2047 /* read GPIO int */ 2048 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); 2049 2050 switch (mode) { 2051 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: 2052 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> " 2053 "output low\n", gpio_num, gpio_shift); 2054 /* clear SET and set CLR */ 2055 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2056 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2057 break; 2058 2059 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: 2060 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> " 2061 "output high\n", gpio_num, gpio_shift); 2062 /* clear CLR and set SET */ 2063 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2064 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2065 break; 2066 2067 default: 2068 break; 2069 } 2070 2071 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); 2072 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2073 2074 return 0; 2075 } 2076 2077 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) 2078 { 2079 u32 spio_mask = (1 << spio_num); 2080 u32 spio_reg; 2081 2082 if ((spio_num < MISC_REGISTERS_SPIO_4) || 2083 (spio_num > MISC_REGISTERS_SPIO_7)) { 2084 BNX2X_ERR("Invalid SPIO %d\n", spio_num); 2085 return -EINVAL; 2086 } 2087 2088 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2089 /* read SPIO and mask except the float bits */ 2090 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); 2091 2092 switch (mode) { 2093 case MISC_REGISTERS_SPIO_OUTPUT_LOW: 2094 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num); 2095 /* clear FLOAT and set CLR */ 2096 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2097 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); 2098 break; 2099 2100 case MISC_REGISTERS_SPIO_OUTPUT_HIGH: 2101 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num); 2102 /* clear FLOAT and set SET */ 2103 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2104 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS); 2105 break; 2106 2107 case MISC_REGISTERS_SPIO_INPUT_HI_Z: 2108 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num); 2109 /* set FLOAT */ 2110 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2111 break; 2112 2113 default: 2114 break; 2115 } 2116 2117 REG_WR(bp, MISC_REG_SPIO, spio_reg); 2118 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2119 2120 return 0; 2121 } 2122 2123 void bnx2x_calc_fc_adv(struct bnx2x *bp) 2124 { 2125 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); 2126 switch (bp->link_vars.ieee_fc & 2127 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { 2128 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: 2129 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2130 ADVERTISED_Pause); 2131 break; 2132 2133 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: 2134 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | 2135 ADVERTISED_Pause); 2136 break; 2137 2138 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: 2139 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; 2140 break; 2141 2142 default: 2143 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2144 ADVERTISED_Pause); 2145 break; 2146 } 2147 } 2148 2149 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) 2150 { 2151 if (!BP_NOMCP(bp)) { 2152 u8 rc; 2153 int cfx_idx = bnx2x_get_link_cfg_idx(bp); 2154 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; 2155 /* 2156 * Initialize link parameters structure variables 2157 * It is recommended to turn off RX FC for jumbo frames 2158 * for better performance 2159 */ 2160 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) 2161 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; 2162 else 2163 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; 2164 2165 bnx2x_acquire_phy_lock(bp); 2166 2167 if (load_mode == LOAD_DIAG) { 2168 struct link_params *lp = &bp->link_params; 2169 lp->loopback_mode = LOOPBACK_XGXS; 2170 /* do PHY loopback at 10G speed, if possible */ 2171 if (lp->req_line_speed[cfx_idx] < SPEED_10000) { 2172 if (lp->speed_cap_mask[cfx_idx] & 2173 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 2174 lp->req_line_speed[cfx_idx] = 2175 SPEED_10000; 2176 else 2177 lp->req_line_speed[cfx_idx] = 2178 SPEED_1000; 2179 } 2180 } 2181 2182 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2183 2184 bnx2x_release_phy_lock(bp); 2185 2186 bnx2x_calc_fc_adv(bp); 2187 2188 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) { 2189 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2190 bnx2x_link_report(bp); 2191 } else 2192 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2193 bp->link_params.req_line_speed[cfx_idx] = req_line_speed; 2194 return rc; 2195 } 2196 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 2197 return -EINVAL; 2198 } 2199 2200 void bnx2x_link_set(struct bnx2x *bp) 2201 { 2202 if (!BP_NOMCP(bp)) { 2203 bnx2x_acquire_phy_lock(bp); 2204 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2205 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2206 bnx2x_release_phy_lock(bp); 2207 2208 bnx2x_calc_fc_adv(bp); 2209 } else 2210 BNX2X_ERR("Bootcode is missing - can not set link\n"); 2211 } 2212 2213 static void bnx2x__link_reset(struct bnx2x *bp) 2214 { 2215 if (!BP_NOMCP(bp)) { 2216 bnx2x_acquire_phy_lock(bp); 2217 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2218 bnx2x_release_phy_lock(bp); 2219 } else 2220 BNX2X_ERR("Bootcode is missing - can not reset link\n"); 2221 } 2222 2223 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) 2224 { 2225 u8 rc = 0; 2226 2227 if (!BP_NOMCP(bp)) { 2228 bnx2x_acquire_phy_lock(bp); 2229 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, 2230 is_serdes); 2231 bnx2x_release_phy_lock(bp); 2232 } else 2233 BNX2X_ERR("Bootcode is missing - can not test link\n"); 2234 2235 return rc; 2236 } 2237 2238 static void bnx2x_init_port_minmax(struct bnx2x *bp) 2239 { 2240 u32 r_param = bp->link_vars.line_speed / 8; 2241 u32 fair_periodic_timeout_usec; 2242 u32 t_fair; 2243 2244 memset(&(bp->cmng.rs_vars), 0, 2245 sizeof(struct rate_shaping_vars_per_port)); 2246 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port)); 2247 2248 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */ 2249 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4; 2250 2251 /* this is the threshold below which no timer arming will occur 2252 1.25 coefficient is for the threshold to be a little bigger 2253 than the real time, to compensate for timer in-accuracy */ 2254 bp->cmng.rs_vars.rs_threshold = 2255 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4; 2256 2257 /* resolution of fairness timer */ 2258 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param; 2259 /* for 10G it is 1000usec. for 1G it is 10000usec. */ 2260 t_fair = T_FAIR_COEF / bp->link_vars.line_speed; 2261 2262 /* this is the threshold below which we won't arm the timer anymore */ 2263 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES; 2264 2265 /* we multiply by 1e3/8 to get bytes/msec. 2266 We don't want the credits to pass a credit 2267 of the t_fair*FAIR_MEM (algorithm resolution) */ 2268 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM; 2269 /* since each tick is 4 usec */ 2270 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4; 2271 } 2272 2273 /* Calculates the sum of vn_min_rates. 2274 It's needed for further normalizing of the min_rates. 2275 Returns: 2276 sum of vn_min_rates. 2277 or 2278 0 - if all the min_rates are 0. 2279 In the later case fainess algorithm should be deactivated. 2280 If not all min_rates are zero then those that are zeroes will be set to 1. 2281 */ 2282 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp) 2283 { 2284 int all_zero = 1; 2285 int vn; 2286 2287 bp->vn_weight_sum = 0; 2288 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2289 u32 vn_cfg = bp->mf_config[vn]; 2290 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2291 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2292 2293 /* Skip hidden vns */ 2294 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) 2295 continue; 2296 2297 /* If min rate is zero - set it to 1 */ 2298 if (!vn_min_rate) 2299 vn_min_rate = DEF_MIN_RATE; 2300 else 2301 all_zero = 0; 2302 2303 bp->vn_weight_sum += vn_min_rate; 2304 } 2305 2306 /* if ETS or all min rates are zeros - disable fairness */ 2307 if (BNX2X_IS_ETS_ENABLED(bp)) { 2308 bp->cmng.flags.cmng_enables &= 2309 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2310 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); 2311 } else if (all_zero) { 2312 bp->cmng.flags.cmng_enables &= 2313 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2314 DP(NETIF_MSG_IFUP, "All MIN values are zeroes" 2315 " fairness will be disabled\n"); 2316 } else 2317 bp->cmng.flags.cmng_enables |= 2318 CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2319 } 2320 2321 /* returns func by VN for current port */ 2322 static inline int func_by_vn(struct bnx2x *bp, int vn) 2323 { 2324 return 2 * vn + BP_PORT(bp); 2325 } 2326 2327 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn) 2328 { 2329 struct rate_shaping_vars_per_vn m_rs_vn; 2330 struct fairness_vars_per_vn m_fair_vn; 2331 u32 vn_cfg = bp->mf_config[vn]; 2332 int func = func_by_vn(bp, vn); 2333 u16 vn_min_rate, vn_max_rate; 2334 int i; 2335 2336 /* If function is hidden - set min and max to zeroes */ 2337 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) { 2338 vn_min_rate = 0; 2339 vn_max_rate = 0; 2340 2341 } else { 2342 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); 2343 2344 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2345 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2346 /* If fairness is enabled (not all min rates are zeroes) and 2347 if current min rate is zero - set it to 1. 2348 This is a requirement of the algorithm. */ 2349 if (bp->vn_weight_sum && (vn_min_rate == 0)) 2350 vn_min_rate = DEF_MIN_RATE; 2351 2352 if (IS_MF_SI(bp)) 2353 /* maxCfg in percents of linkspeed */ 2354 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; 2355 else 2356 /* maxCfg is absolute in 100Mb units */ 2357 vn_max_rate = maxCfg * 100; 2358 } 2359 2360 DP(NETIF_MSG_IFUP, 2361 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n", 2362 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum); 2363 2364 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn)); 2365 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn)); 2366 2367 /* global vn counter - maximal Mbps for this vn */ 2368 m_rs_vn.vn_counter.rate = vn_max_rate; 2369 2370 /* quota - number of bytes transmitted in this period */ 2371 m_rs_vn.vn_counter.quota = 2372 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8; 2373 2374 if (bp->vn_weight_sum) { 2375 /* credit for each period of the fairness algorithm: 2376 number of bytes in T_FAIR (the vn share the port rate). 2377 vn_weight_sum should not be larger than 10000, thus 2378 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater 2379 than zero */ 2380 m_fair_vn.vn_credit_delta = 2381 max_t(u32, (vn_min_rate * (T_FAIR_COEF / 2382 (8 * bp->vn_weight_sum))), 2383 (bp->cmng.fair_vars.fair_threshold + 2384 MIN_ABOVE_THRESH)); 2385 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n", 2386 m_fair_vn.vn_credit_delta); 2387 } 2388 2389 /* Store it to internal memory */ 2390 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++) 2391 REG_WR(bp, BAR_XSTRORM_INTMEM + 2392 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4, 2393 ((u32 *)(&m_rs_vn))[i]); 2394 2395 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++) 2396 REG_WR(bp, BAR_XSTRORM_INTMEM + 2397 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4, 2398 ((u32 *)(&m_fair_vn))[i]); 2399 } 2400 2401 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) 2402 { 2403 if (CHIP_REV_IS_SLOW(bp)) 2404 return CMNG_FNS_NONE; 2405 if (IS_MF(bp)) 2406 return CMNG_FNS_MINMAX; 2407 2408 return CMNG_FNS_NONE; 2409 } 2410 2411 void bnx2x_read_mf_cfg(struct bnx2x *bp) 2412 { 2413 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); 2414 2415 if (BP_NOMCP(bp)) 2416 return; /* what should be the default bvalue in this case */ 2417 2418 /* For 2 port configuration the absolute function number formula 2419 * is: 2420 * abs_func = 2 * vn + BP_PORT + BP_PATH 2421 * 2422 * and there are 4 functions per port 2423 * 2424 * For 4 port configuration it is 2425 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH 2426 * 2427 * and there are 2 functions per port 2428 */ 2429 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2430 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); 2431 2432 if (func >= E1H_FUNC_MAX) 2433 break; 2434 2435 bp->mf_config[vn] = 2436 MF_CFG_RD(bp, func_mf_config[func].config); 2437 } 2438 } 2439 2440 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) 2441 { 2442 2443 if (cmng_type == CMNG_FNS_MINMAX) { 2444 int vn; 2445 2446 /* clear cmng_enables */ 2447 bp->cmng.flags.cmng_enables = 0; 2448 2449 /* read mf conf from shmem */ 2450 if (read_cfg) 2451 bnx2x_read_mf_cfg(bp); 2452 2453 /* Init rate shaping and fairness contexts */ 2454 bnx2x_init_port_minmax(bp); 2455 2456 /* vn_weight_sum and enable fairness if not 0 */ 2457 bnx2x_calc_vn_weight_sum(bp); 2458 2459 /* calculate and set min-max rate for each vn */ 2460 if (bp->port.pmf) 2461 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) 2462 bnx2x_init_vn_minmax(bp, vn); 2463 2464 /* always enable rate shaping and fairness */ 2465 bp->cmng.flags.cmng_enables |= 2466 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; 2467 if (!bp->vn_weight_sum) 2468 DP(NETIF_MSG_IFUP, "All MIN values are zeroes" 2469 " fairness will be disabled\n"); 2470 return; 2471 } 2472 2473 /* rate shaping and fairness are disabled */ 2474 DP(NETIF_MSG_IFUP, 2475 "rate shaping and fairness are disabled\n"); 2476 } 2477 2478 static inline void bnx2x_link_sync_notify(struct bnx2x *bp) 2479 { 2480 int func; 2481 int vn; 2482 2483 /* Set the attention towards other drivers on the same port */ 2484 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2485 if (vn == BP_VN(bp)) 2486 continue; 2487 2488 func = func_by_vn(bp, vn); 2489 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + 2490 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); 2491 } 2492 } 2493 2494 /* This function is called upon link interrupt */ 2495 static void bnx2x_link_attn(struct bnx2x *bp) 2496 { 2497 /* Make sure that we are synced with the current statistics */ 2498 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2499 2500 bnx2x_link_update(&bp->link_params, &bp->link_vars); 2501 2502 if (bp->link_vars.link_up) { 2503 2504 /* dropless flow control */ 2505 if (!CHIP_IS_E1(bp) && bp->dropless_fc) { 2506 int port = BP_PORT(bp); 2507 u32 pause_enabled = 0; 2508 2509 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) 2510 pause_enabled = 1; 2511 2512 REG_WR(bp, BAR_USTRORM_INTMEM + 2513 USTORM_ETH_PAUSE_ENABLED_OFFSET(port), 2514 pause_enabled); 2515 } 2516 2517 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { 2518 struct host_port_stats *pstats; 2519 2520 pstats = bnx2x_sp(bp, port_stats); 2521 /* reset old mac stats */ 2522 memset(&(pstats->mac_stx[0]), 0, 2523 sizeof(struct mac_stx)); 2524 } 2525 if (bp->state == BNX2X_STATE_OPEN) 2526 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2527 } 2528 2529 if (bp->link_vars.link_up && bp->link_vars.line_speed) { 2530 int cmng_fns = bnx2x_get_cmng_fns_mode(bp); 2531 2532 if (cmng_fns != CMNG_FNS_NONE) { 2533 bnx2x_cmng_fns_init(bp, false, cmng_fns); 2534 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2535 } else 2536 /* rate shaping and fairness are disabled */ 2537 DP(NETIF_MSG_IFUP, 2538 "single function mode without fairness\n"); 2539 } 2540 2541 __bnx2x_link_report(bp); 2542 2543 if (IS_MF(bp)) 2544 bnx2x_link_sync_notify(bp); 2545 } 2546 2547 void bnx2x__link_status_update(struct bnx2x *bp) 2548 { 2549 if (bp->state != BNX2X_STATE_OPEN) 2550 return; 2551 2552 bnx2x_link_status_update(&bp->link_params, &bp->link_vars); 2553 2554 if (bp->link_vars.link_up) 2555 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2556 else 2557 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2558 2559 /* indicate link status */ 2560 bnx2x_link_report(bp); 2561 } 2562 2563 static void bnx2x_pmf_update(struct bnx2x *bp) 2564 { 2565 int port = BP_PORT(bp); 2566 u32 val; 2567 2568 bp->port.pmf = 1; 2569 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf); 2570 2571 /* 2572 * We need the mb() to ensure the ordering between the writing to 2573 * bp->port.pmf here and reading it from the bnx2x_periodic_task(). 2574 */ 2575 smp_mb(); 2576 2577 /* queue a periodic task */ 2578 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2579 2580 bnx2x_dcbx_pmf_update(bp); 2581 2582 /* enable nig attention */ 2583 val = (0xff0f | (1 << (BP_VN(bp) + 4))); 2584 if (bp->common.int_block == INT_BLOCK_HC) { 2585 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 2586 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 2587 } else if (!CHIP_IS_E1x(bp)) { 2588 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 2589 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 2590 } 2591 2592 bnx2x_stats_handle(bp, STATS_EVENT_PMF); 2593 } 2594 2595 /* end of Link */ 2596 2597 /* slow path */ 2598 2599 /* 2600 * General service functions 2601 */ 2602 2603 /* send the MCP a request, block until there is a reply */ 2604 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) 2605 { 2606 int mb_idx = BP_FW_MB_IDX(bp); 2607 u32 seq; 2608 u32 rc = 0; 2609 u32 cnt = 1; 2610 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; 2611 2612 mutex_lock(&bp->fw_mb_mutex); 2613 seq = ++bp->fw_seq; 2614 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); 2615 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); 2616 2617 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", 2618 (command | seq), param); 2619 2620 do { 2621 /* let the FW do it's magic ... */ 2622 msleep(delay); 2623 2624 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); 2625 2626 /* Give the FW up to 5 second (500*10ms) */ 2627 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); 2628 2629 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", 2630 cnt*delay, rc, seq); 2631 2632 /* is this a reply to our command? */ 2633 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) 2634 rc &= FW_MSG_CODE_MASK; 2635 else { 2636 /* FW BUG! */ 2637 BNX2X_ERR("FW failed to respond!\n"); 2638 bnx2x_fw_dump(bp); 2639 rc = 0; 2640 } 2641 mutex_unlock(&bp->fw_mb_mutex); 2642 2643 return rc; 2644 } 2645 2646 static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp) 2647 { 2648 #ifdef BCM_CNIC 2649 /* Statistics are not supported for CNIC Clients at the moment */ 2650 if (IS_FCOE_FP(fp)) 2651 return false; 2652 #endif 2653 return true; 2654 } 2655 2656 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) 2657 { 2658 if (CHIP_IS_E1x(bp)) { 2659 struct tstorm_eth_function_common_config tcfg = {0}; 2660 2661 storm_memset_func_cfg(bp, &tcfg, p->func_id); 2662 } 2663 2664 /* Enable the function in the FW */ 2665 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); 2666 storm_memset_func_en(bp, p->func_id, 1); 2667 2668 /* spq */ 2669 if (p->func_flgs & FUNC_FLG_SPQ) { 2670 storm_memset_spq_addr(bp, p->spq_map, p->func_id); 2671 REG_WR(bp, XSEM_REG_FAST_MEMORY + 2672 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); 2673 } 2674 } 2675 2676 /** 2677 * bnx2x_get_tx_only_flags - Return common flags 2678 * 2679 * @bp device handle 2680 * @fp queue handle 2681 * @zero_stats TRUE if statistics zeroing is needed 2682 * 2683 * Return the flags that are common for the Tx-only and not normal connections. 2684 */ 2685 static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp, 2686 struct bnx2x_fastpath *fp, 2687 bool zero_stats) 2688 { 2689 unsigned long flags = 0; 2690 2691 /* PF driver will always initialize the Queue to an ACTIVE state */ 2692 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); 2693 2694 /* tx only connections collect statistics (on the same index as the 2695 * parent connection). The statistics are zeroed when the parent 2696 * connection is initialized. 2697 */ 2698 if (stat_counter_valid(bp, fp)) { 2699 __set_bit(BNX2X_Q_FLG_STATS, &flags); 2700 if (zero_stats) 2701 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); 2702 } 2703 2704 return flags; 2705 } 2706 2707 static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp, 2708 struct bnx2x_fastpath *fp, 2709 bool leading) 2710 { 2711 unsigned long flags = 0; 2712 2713 /* calculate other queue flags */ 2714 if (IS_MF_SD(bp)) 2715 __set_bit(BNX2X_Q_FLG_OV, &flags); 2716 2717 if (IS_FCOE_FP(fp)) 2718 __set_bit(BNX2X_Q_FLG_FCOE, &flags); 2719 2720 if (!fp->disable_tpa) { 2721 __set_bit(BNX2X_Q_FLG_TPA, &flags); 2722 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); 2723 } 2724 2725 if (leading) { 2726 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); 2727 __set_bit(BNX2X_Q_FLG_MCAST, &flags); 2728 } 2729 2730 /* Always set HW VLAN stripping */ 2731 __set_bit(BNX2X_Q_FLG_VLAN, &flags); 2732 2733 2734 return flags | bnx2x_get_common_flags(bp, fp, true); 2735 } 2736 2737 static void bnx2x_pf_q_prep_general(struct bnx2x *bp, 2738 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, 2739 u8 cos) 2740 { 2741 gen_init->stat_id = bnx2x_stats_id(fp); 2742 gen_init->spcl_id = fp->cl_id; 2743 2744 /* Always use mini-jumbo MTU for FCoE L2 ring */ 2745 if (IS_FCOE_FP(fp)) 2746 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; 2747 else 2748 gen_init->mtu = bp->dev->mtu; 2749 2750 gen_init->cos = cos; 2751 } 2752 2753 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, 2754 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, 2755 struct bnx2x_rxq_setup_params *rxq_init) 2756 { 2757 u8 max_sge = 0; 2758 u16 sge_sz = 0; 2759 u16 tpa_agg_size = 0; 2760 2761 if (!fp->disable_tpa) { 2762 pause->sge_th_lo = SGE_TH_LO(bp); 2763 pause->sge_th_hi = SGE_TH_HI(bp); 2764 2765 /* validate SGE ring has enough to cross high threshold */ 2766 WARN_ON(bp->dropless_fc && 2767 pause->sge_th_hi + FW_PREFETCH_CNT > 2768 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); 2769 2770 tpa_agg_size = min_t(u32, 2771 (min_t(u32, 8, MAX_SKB_FRAGS) * 2772 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); 2773 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> 2774 SGE_PAGE_SHIFT; 2775 max_sge = ((max_sge + PAGES_PER_SGE - 1) & 2776 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; 2777 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE, 2778 0xffff); 2779 } 2780 2781 /* pause - not for e1 */ 2782 if (!CHIP_IS_E1(bp)) { 2783 pause->bd_th_lo = BD_TH_LO(bp); 2784 pause->bd_th_hi = BD_TH_HI(bp); 2785 2786 pause->rcq_th_lo = RCQ_TH_LO(bp); 2787 pause->rcq_th_hi = RCQ_TH_HI(bp); 2788 /* 2789 * validate that rings have enough entries to cross 2790 * high thresholds 2791 */ 2792 WARN_ON(bp->dropless_fc && 2793 pause->bd_th_hi + FW_PREFETCH_CNT > 2794 bp->rx_ring_size); 2795 WARN_ON(bp->dropless_fc && 2796 pause->rcq_th_hi + FW_PREFETCH_CNT > 2797 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); 2798 2799 pause->pri_map = 1; 2800 } 2801 2802 /* rxq setup */ 2803 rxq_init->dscr_map = fp->rx_desc_mapping; 2804 rxq_init->sge_map = fp->rx_sge_mapping; 2805 rxq_init->rcq_map = fp->rx_comp_mapping; 2806 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; 2807 2808 /* This should be a maximum number of data bytes that may be 2809 * placed on the BD (not including paddings). 2810 */ 2811 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN - 2812 IP_HEADER_ALIGNMENT_PADDING; 2813 2814 rxq_init->cl_qzone_id = fp->cl_qzone_id; 2815 rxq_init->tpa_agg_sz = tpa_agg_size; 2816 rxq_init->sge_buf_sz = sge_sz; 2817 rxq_init->max_sges_pkt = max_sge; 2818 rxq_init->rss_engine_id = BP_FUNC(bp); 2819 2820 /* Maximum number or simultaneous TPA aggregation for this Queue. 2821 * 2822 * For PF Clients it should be the maximum avaliable number. 2823 * VF driver(s) may want to define it to a smaller value. 2824 */ 2825 rxq_init->max_tpa_queues = MAX_AGG_QS(bp); 2826 2827 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; 2828 rxq_init->fw_sb_id = fp->fw_sb_id; 2829 2830 if (IS_FCOE_FP(fp)) 2831 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; 2832 else 2833 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 2834 } 2835 2836 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, 2837 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, 2838 u8 cos) 2839 { 2840 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping; 2841 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; 2842 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; 2843 txq_init->fw_sb_id = fp->fw_sb_id; 2844 2845 /* 2846 * set the tss leading client id for TX classfication == 2847 * leading RSS client id 2848 */ 2849 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); 2850 2851 if (IS_FCOE_FP(fp)) { 2852 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; 2853 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; 2854 } 2855 } 2856 2857 static void bnx2x_pf_init(struct bnx2x *bp) 2858 { 2859 struct bnx2x_func_init_params func_init = {0}; 2860 struct event_ring_data eq_data = { {0} }; 2861 u16 flags; 2862 2863 if (!CHIP_IS_E1x(bp)) { 2864 /* reset IGU PF statistics: MSIX + ATTN */ 2865 /* PF */ 2866 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 2867 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 2868 (CHIP_MODE_IS_4_PORT(bp) ? 2869 BP_FUNC(bp) : BP_VN(bp))*4, 0); 2870 /* ATTN */ 2871 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 2872 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 2873 BNX2X_IGU_STAS_MSG_PF_CNT*4 + 2874 (CHIP_MODE_IS_4_PORT(bp) ? 2875 BP_FUNC(bp) : BP_VN(bp))*4, 0); 2876 } 2877 2878 /* function setup flags */ 2879 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); 2880 2881 /* This flag is relevant for E1x only. 2882 * E2 doesn't have a TPA configuration in a function level. 2883 */ 2884 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; 2885 2886 func_init.func_flgs = flags; 2887 func_init.pf_id = BP_FUNC(bp); 2888 func_init.func_id = BP_FUNC(bp); 2889 func_init.spq_map = bp->spq_mapping; 2890 func_init.spq_prod = bp->spq_prod_idx; 2891 2892 bnx2x_func_init(bp, &func_init); 2893 2894 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); 2895 2896 /* 2897 * Congestion management values depend on the link rate 2898 * There is no active link so initial link rate is set to 10 Gbps. 2899 * When the link comes up The congestion management values are 2900 * re-calculated according to the actual link rate. 2901 */ 2902 bp->link_vars.line_speed = SPEED_10000; 2903 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); 2904 2905 /* Only the PMF sets the HW */ 2906 if (bp->port.pmf) 2907 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2908 2909 /* init Event Queue */ 2910 eq_data.base_addr.hi = U64_HI(bp->eq_mapping); 2911 eq_data.base_addr.lo = U64_LO(bp->eq_mapping); 2912 eq_data.producer = bp->eq_prod; 2913 eq_data.index_id = HC_SP_INDEX_EQ_CONS; 2914 eq_data.sb_id = DEF_SB_ID; 2915 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); 2916 } 2917 2918 2919 static void bnx2x_e1h_disable(struct bnx2x *bp) 2920 { 2921 int port = BP_PORT(bp); 2922 2923 bnx2x_tx_disable(bp); 2924 2925 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 2926 } 2927 2928 static void bnx2x_e1h_enable(struct bnx2x *bp) 2929 { 2930 int port = BP_PORT(bp); 2931 2932 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 2933 2934 /* Tx queue should be only reenabled */ 2935 netif_tx_wake_all_queues(bp->dev); 2936 2937 /* 2938 * Should not call netif_carrier_on since it will be called if the link 2939 * is up when checking for link state 2940 */ 2941 } 2942 2943 /* called due to MCP event (on pmf): 2944 * reread new bandwidth configuration 2945 * configure FW 2946 * notify others function about the change 2947 */ 2948 static inline void bnx2x_config_mf_bw(struct bnx2x *bp) 2949 { 2950 if (bp->link_vars.link_up) { 2951 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); 2952 bnx2x_link_sync_notify(bp); 2953 } 2954 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2955 } 2956 2957 static inline void bnx2x_set_mf_bw(struct bnx2x *bp) 2958 { 2959 bnx2x_config_mf_bw(bp); 2960 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); 2961 } 2962 2963 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) 2964 { 2965 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); 2966 2967 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { 2968 2969 /* 2970 * This is the only place besides the function initialization 2971 * where the bp->flags can change so it is done without any 2972 * locks 2973 */ 2974 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 2975 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n"); 2976 bp->flags |= MF_FUNC_DIS; 2977 2978 bnx2x_e1h_disable(bp); 2979 } else { 2980 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); 2981 bp->flags &= ~MF_FUNC_DIS; 2982 2983 bnx2x_e1h_enable(bp); 2984 } 2985 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; 2986 } 2987 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { 2988 bnx2x_config_mf_bw(bp); 2989 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; 2990 } 2991 2992 /* Report results to MCP */ 2993 if (dcc_event) 2994 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); 2995 else 2996 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); 2997 } 2998 2999 /* must be called under the spq lock */ 3000 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) 3001 { 3002 struct eth_spe *next_spe = bp->spq_prod_bd; 3003 3004 if (bp->spq_prod_bd == bp->spq_last_bd) { 3005 bp->spq_prod_bd = bp->spq; 3006 bp->spq_prod_idx = 0; 3007 DP(NETIF_MSG_TIMER, "end of spq\n"); 3008 } else { 3009 bp->spq_prod_bd++; 3010 bp->spq_prod_idx++; 3011 } 3012 return next_spe; 3013 } 3014 3015 /* must be called under the spq lock */ 3016 static inline void bnx2x_sp_prod_update(struct bnx2x *bp) 3017 { 3018 int func = BP_FUNC(bp); 3019 3020 /* 3021 * Make sure that BD data is updated before writing the producer: 3022 * BD data is written to the memory, the producer is read from the 3023 * memory, thus we need a full memory barrier to ensure the ordering. 3024 */ 3025 mb(); 3026 3027 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), 3028 bp->spq_prod_idx); 3029 mmiowb(); 3030 } 3031 3032 /** 3033 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ 3034 * 3035 * @cmd: command to check 3036 * @cmd_type: command type 3037 */ 3038 static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) 3039 { 3040 if ((cmd_type == NONE_CONNECTION_TYPE) || 3041 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || 3042 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || 3043 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || 3044 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || 3045 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || 3046 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) 3047 return true; 3048 else 3049 return false; 3050 3051 } 3052 3053 3054 /** 3055 * bnx2x_sp_post - place a single command on an SP ring 3056 * 3057 * @bp: driver handle 3058 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) 3059 * @cid: SW CID the command is related to 3060 * @data_hi: command private data address (high 32 bits) 3061 * @data_lo: command private data address (low 32 bits) 3062 * @cmd_type: command type (e.g. NONE, ETH) 3063 * 3064 * SP data is handled as if it's always an address pair, thus data fields are 3065 * not swapped to little endian in upper functions. Instead this function swaps 3066 * data as if it's two u32 fields. 3067 */ 3068 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 3069 u32 data_hi, u32 data_lo, int cmd_type) 3070 { 3071 struct eth_spe *spe; 3072 u16 type; 3073 bool common = bnx2x_is_contextless_ramrod(command, cmd_type); 3074 3075 #ifdef BNX2X_STOP_ON_ERROR 3076 if (unlikely(bp->panic)) 3077 return -EIO; 3078 #endif 3079 3080 spin_lock_bh(&bp->spq_lock); 3081 3082 if (common) { 3083 if (!atomic_read(&bp->eq_spq_left)) { 3084 BNX2X_ERR("BUG! EQ ring full!\n"); 3085 spin_unlock_bh(&bp->spq_lock); 3086 bnx2x_panic(); 3087 return -EBUSY; 3088 } 3089 } else if (!atomic_read(&bp->cq_spq_left)) { 3090 BNX2X_ERR("BUG! SPQ ring full!\n"); 3091 spin_unlock_bh(&bp->spq_lock); 3092 bnx2x_panic(); 3093 return -EBUSY; 3094 } 3095 3096 spe = bnx2x_sp_get_next(bp); 3097 3098 /* CID needs port number to be encoded int it */ 3099 spe->hdr.conn_and_cmd_data = 3100 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | 3101 HW_CID(bp, cid)); 3102 3103 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; 3104 3105 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & 3106 SPE_HDR_FUNCTION_ID); 3107 3108 spe->hdr.type = cpu_to_le16(type); 3109 3110 spe->data.update_data_addr.hi = cpu_to_le32(data_hi); 3111 spe->data.update_data_addr.lo = cpu_to_le32(data_lo); 3112 3113 /* 3114 * It's ok if the actual decrement is issued towards the memory 3115 * somewhere between the spin_lock and spin_unlock. Thus no 3116 * more explict memory barrier is needed. 3117 */ 3118 if (common) 3119 atomic_dec(&bp->eq_spq_left); 3120 else 3121 atomic_dec(&bp->cq_spq_left); 3122 3123 3124 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/, 3125 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) " 3126 "type(0x%x) left (CQ, EQ) (%x,%x)\n", 3127 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), 3128 (u32)(U64_LO(bp->spq_mapping) + 3129 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, 3130 HW_CID(bp, cid), data_hi, data_lo, type, 3131 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); 3132 3133 bnx2x_sp_prod_update(bp); 3134 spin_unlock_bh(&bp->spq_lock); 3135 return 0; 3136 } 3137 3138 /* acquire split MCP access lock register */ 3139 static int bnx2x_acquire_alr(struct bnx2x *bp) 3140 { 3141 u32 j, val; 3142 int rc = 0; 3143 3144 might_sleep(); 3145 for (j = 0; j < 1000; j++) { 3146 val = (1UL << 31); 3147 REG_WR(bp, GRCBASE_MCP + 0x9c, val); 3148 val = REG_RD(bp, GRCBASE_MCP + 0x9c); 3149 if (val & (1L << 31)) 3150 break; 3151 3152 msleep(5); 3153 } 3154 if (!(val & (1L << 31))) { 3155 BNX2X_ERR("Cannot acquire MCP access lock register\n"); 3156 rc = -EBUSY; 3157 } 3158 3159 return rc; 3160 } 3161 3162 /* release split MCP access lock register */ 3163 static void bnx2x_release_alr(struct bnx2x *bp) 3164 { 3165 REG_WR(bp, GRCBASE_MCP + 0x9c, 0); 3166 } 3167 3168 #define BNX2X_DEF_SB_ATT_IDX 0x0001 3169 #define BNX2X_DEF_SB_IDX 0x0002 3170 3171 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp) 3172 { 3173 struct host_sp_status_block *def_sb = bp->def_status_blk; 3174 u16 rc = 0; 3175 3176 barrier(); /* status block is written to by the chip */ 3177 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 3178 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; 3179 rc |= BNX2X_DEF_SB_ATT_IDX; 3180 } 3181 3182 if (bp->def_idx != def_sb->sp_sb.running_index) { 3183 bp->def_idx = def_sb->sp_sb.running_index; 3184 rc |= BNX2X_DEF_SB_IDX; 3185 } 3186 3187 /* Do not reorder: indecies reading should complete before handling */ 3188 barrier(); 3189 return rc; 3190 } 3191 3192 /* 3193 * slow path service functions 3194 */ 3195 3196 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) 3197 { 3198 int port = BP_PORT(bp); 3199 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 3200 MISC_REG_AEU_MASK_ATTN_FUNC_0; 3201 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 3202 NIG_REG_MASK_INTERRUPT_PORT0; 3203 u32 aeu_mask; 3204 u32 nig_mask = 0; 3205 u32 reg_addr; 3206 3207 if (bp->attn_state & asserted) 3208 BNX2X_ERR("IGU ERROR\n"); 3209 3210 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3211 aeu_mask = REG_RD(bp, aeu_addr); 3212 3213 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", 3214 aeu_mask, asserted); 3215 aeu_mask &= ~(asserted & 0x3ff); 3216 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 3217 3218 REG_WR(bp, aeu_addr, aeu_mask); 3219 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3220 3221 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 3222 bp->attn_state |= asserted; 3223 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 3224 3225 if (asserted & ATTN_HARD_WIRED_MASK) { 3226 if (asserted & ATTN_NIG_FOR_FUNC) { 3227 3228 bnx2x_acquire_phy_lock(bp); 3229 3230 /* save nig interrupt mask */ 3231 nig_mask = REG_RD(bp, nig_int_mask_addr); 3232 3233 /* If nig_mask is not set, no need to call the update 3234 * function. 3235 */ 3236 if (nig_mask) { 3237 REG_WR(bp, nig_int_mask_addr, 0); 3238 3239 bnx2x_link_attn(bp); 3240 } 3241 3242 /* handle unicore attn? */ 3243 } 3244 if (asserted & ATTN_SW_TIMER_4_FUNC) 3245 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); 3246 3247 if (asserted & GPIO_2_FUNC) 3248 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); 3249 3250 if (asserted & GPIO_3_FUNC) 3251 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); 3252 3253 if (asserted & GPIO_4_FUNC) 3254 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); 3255 3256 if (port == 0) { 3257 if (asserted & ATTN_GENERAL_ATTN_1) { 3258 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); 3259 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); 3260 } 3261 if (asserted & ATTN_GENERAL_ATTN_2) { 3262 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); 3263 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); 3264 } 3265 if (asserted & ATTN_GENERAL_ATTN_3) { 3266 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); 3267 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); 3268 } 3269 } else { 3270 if (asserted & ATTN_GENERAL_ATTN_4) { 3271 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); 3272 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); 3273 } 3274 if (asserted & ATTN_GENERAL_ATTN_5) { 3275 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); 3276 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); 3277 } 3278 if (asserted & ATTN_GENERAL_ATTN_6) { 3279 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); 3280 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); 3281 } 3282 } 3283 3284 } /* if hardwired */ 3285 3286 if (bp->common.int_block == INT_BLOCK_HC) 3287 reg_addr = (HC_REG_COMMAND_REG + port*32 + 3288 COMMAND_REG_ATTN_BITS_SET); 3289 else 3290 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); 3291 3292 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, 3293 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 3294 REG_WR(bp, reg_addr, asserted); 3295 3296 /* now set back the mask */ 3297 if (asserted & ATTN_NIG_FOR_FUNC) { 3298 REG_WR(bp, nig_int_mask_addr, nig_mask); 3299 bnx2x_release_phy_lock(bp); 3300 } 3301 } 3302 3303 static inline void bnx2x_fan_failure(struct bnx2x *bp) 3304 { 3305 int port = BP_PORT(bp); 3306 u32 ext_phy_config; 3307 /* mark the failure */ 3308 ext_phy_config = 3309 SHMEM_RD(bp, 3310 dev_info.port_hw_config[port].external_phy_config); 3311 3312 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 3313 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 3314 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, 3315 ext_phy_config); 3316 3317 /* log the failure */ 3318 netdev_err(bp->dev, "Fan Failure on Network Controller has caused" 3319 " the driver to shutdown the card to prevent permanent" 3320 " damage. Please contact OEM Support for assistance\n"); 3321 } 3322 3323 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) 3324 { 3325 int port = BP_PORT(bp); 3326 int reg_offset; 3327 u32 val; 3328 3329 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 3330 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 3331 3332 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { 3333 3334 val = REG_RD(bp, reg_offset); 3335 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; 3336 REG_WR(bp, reg_offset, val); 3337 3338 BNX2X_ERR("SPIO5 hw attention\n"); 3339 3340 /* Fan failure attention */ 3341 bnx2x_hw_reset_phy(&bp->link_params); 3342 bnx2x_fan_failure(bp); 3343 } 3344 3345 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { 3346 bnx2x_acquire_phy_lock(bp); 3347 bnx2x_handle_module_detect_int(&bp->link_params); 3348 bnx2x_release_phy_lock(bp); 3349 } 3350 3351 if (attn & HW_INTERRUT_ASSERT_SET_0) { 3352 3353 val = REG_RD(bp, reg_offset); 3354 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); 3355 REG_WR(bp, reg_offset, val); 3356 3357 BNX2X_ERR("FATAL HW block attention set0 0x%x\n", 3358 (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); 3359 bnx2x_panic(); 3360 } 3361 } 3362 3363 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) 3364 { 3365 u32 val; 3366 3367 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { 3368 3369 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); 3370 BNX2X_ERR("DB hw attention 0x%x\n", val); 3371 /* DORQ discard attention */ 3372 if (val & 0x2) 3373 BNX2X_ERR("FATAL error from DORQ\n"); 3374 } 3375 3376 if (attn & HW_INTERRUT_ASSERT_SET_1) { 3377 3378 int port = BP_PORT(bp); 3379 int reg_offset; 3380 3381 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : 3382 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); 3383 3384 val = REG_RD(bp, reg_offset); 3385 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); 3386 REG_WR(bp, reg_offset, val); 3387 3388 BNX2X_ERR("FATAL HW block attention set1 0x%x\n", 3389 (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); 3390 bnx2x_panic(); 3391 } 3392 } 3393 3394 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) 3395 { 3396 u32 val; 3397 3398 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { 3399 3400 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); 3401 BNX2X_ERR("CFC hw attention 0x%x\n", val); 3402 /* CFC error attention */ 3403 if (val & 0x2) 3404 BNX2X_ERR("FATAL error from CFC\n"); 3405 } 3406 3407 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { 3408 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); 3409 BNX2X_ERR("PXP hw attention-0 0x%x\n", val); 3410 /* RQ_USDMDP_FIFO_OVERFLOW */ 3411 if (val & 0x18000) 3412 BNX2X_ERR("FATAL error from PXP\n"); 3413 3414 if (!CHIP_IS_E1x(bp)) { 3415 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); 3416 BNX2X_ERR("PXP hw attention-1 0x%x\n", val); 3417 } 3418 } 3419 3420 if (attn & HW_INTERRUT_ASSERT_SET_2) { 3421 3422 int port = BP_PORT(bp); 3423 int reg_offset; 3424 3425 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : 3426 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); 3427 3428 val = REG_RD(bp, reg_offset); 3429 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); 3430 REG_WR(bp, reg_offset, val); 3431 3432 BNX2X_ERR("FATAL HW block attention set2 0x%x\n", 3433 (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); 3434 bnx2x_panic(); 3435 } 3436 } 3437 3438 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) 3439 { 3440 u32 val; 3441 3442 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { 3443 3444 if (attn & BNX2X_PMF_LINK_ASSERT) { 3445 int func = BP_FUNC(bp); 3446 3447 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 3448 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, 3449 func_mf_config[BP_ABS_FUNC(bp)].config); 3450 val = SHMEM_RD(bp, 3451 func_mb[BP_FW_MB_IDX(bp)].drv_status); 3452 if (val & DRV_STATUS_DCC_EVENT_MASK) 3453 bnx2x_dcc_event(bp, 3454 (val & DRV_STATUS_DCC_EVENT_MASK)); 3455 3456 if (val & DRV_STATUS_SET_MF_BW) 3457 bnx2x_set_mf_bw(bp); 3458 3459 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) 3460 bnx2x_pmf_update(bp); 3461 3462 if (bp->port.pmf && 3463 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && 3464 bp->dcbx_enabled > 0) 3465 /* start dcbx state machine */ 3466 bnx2x_dcbx_set_params(bp, 3467 BNX2X_DCBX_STATE_NEG_RECEIVED); 3468 if (bp->link_vars.periodic_flags & 3469 PERIODIC_FLAGS_LINK_EVENT) { 3470 /* sync with link */ 3471 bnx2x_acquire_phy_lock(bp); 3472 bp->link_vars.periodic_flags &= 3473 ~PERIODIC_FLAGS_LINK_EVENT; 3474 bnx2x_release_phy_lock(bp); 3475 if (IS_MF(bp)) 3476 bnx2x_link_sync_notify(bp); 3477 bnx2x_link_report(bp); 3478 } 3479 /* Always call it here: bnx2x_link_report() will 3480 * prevent the link indication duplication. 3481 */ 3482 bnx2x__link_status_update(bp); 3483 } else if (attn & BNX2X_MC_ASSERT_BITS) { 3484 3485 BNX2X_ERR("MC assert!\n"); 3486 bnx2x_mc_assert(bp); 3487 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); 3488 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); 3489 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); 3490 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); 3491 bnx2x_panic(); 3492 3493 } else if (attn & BNX2X_MCP_ASSERT) { 3494 3495 BNX2X_ERR("MCP assert!\n"); 3496 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); 3497 bnx2x_fw_dump(bp); 3498 3499 } else 3500 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); 3501 } 3502 3503 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { 3504 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); 3505 if (attn & BNX2X_GRC_TIMEOUT) { 3506 val = CHIP_IS_E1(bp) ? 0 : 3507 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); 3508 BNX2X_ERR("GRC time-out 0x%08x\n", val); 3509 } 3510 if (attn & BNX2X_GRC_RSV) { 3511 val = CHIP_IS_E1(bp) ? 0 : 3512 REG_RD(bp, MISC_REG_GRC_RSV_ATTN); 3513 BNX2X_ERR("GRC reserved 0x%08x\n", val); 3514 } 3515 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); 3516 } 3517 } 3518 3519 /* 3520 * Bits map: 3521 * 0-7 - Engine0 load counter. 3522 * 8-15 - Engine1 load counter. 3523 * 16 - Engine0 RESET_IN_PROGRESS bit. 3524 * 17 - Engine1 RESET_IN_PROGRESS bit. 3525 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function 3526 * on the engine 3527 * 19 - Engine1 ONE_IS_LOADED. 3528 * 20 - Chip reset flow bit. When set none-leader must wait for both engines 3529 * leader to complete (check for both RESET_IN_PROGRESS bits and not for 3530 * just the one belonging to its engine). 3531 * 3532 */ 3533 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 3534 3535 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff 3536 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0 3537 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 3538 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8 3539 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 3540 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 3541 #define BNX2X_GLOBAL_RESET_BIT 0x00040000 3542 3543 /* 3544 * Set the GLOBAL_RESET bit. 3545 * 3546 * Should be run under rtnl lock 3547 */ 3548 void bnx2x_set_reset_global(struct bnx2x *bp) 3549 { 3550 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3551 3552 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); 3553 barrier(); 3554 mmiowb(); 3555 } 3556 3557 /* 3558 * Clear the GLOBAL_RESET bit. 3559 * 3560 * Should be run under rtnl lock 3561 */ 3562 static inline void bnx2x_clear_reset_global(struct bnx2x *bp) 3563 { 3564 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3565 3566 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); 3567 barrier(); 3568 mmiowb(); 3569 } 3570 3571 /* 3572 * Checks the GLOBAL_RESET bit. 3573 * 3574 * should be run under rtnl lock 3575 */ 3576 static inline bool bnx2x_reset_is_global(struct bnx2x *bp) 3577 { 3578 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3579 3580 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); 3581 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; 3582 } 3583 3584 /* 3585 * Clear RESET_IN_PROGRESS bit for the current engine. 3586 * 3587 * Should be run under rtnl lock 3588 */ 3589 static inline void bnx2x_set_reset_done(struct bnx2x *bp) 3590 { 3591 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3592 u32 bit = BP_PATH(bp) ? 3593 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3594 3595 /* Clear the bit */ 3596 val &= ~bit; 3597 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3598 barrier(); 3599 mmiowb(); 3600 } 3601 3602 /* 3603 * Set RESET_IN_PROGRESS for the current engine. 3604 * 3605 * should be run under rtnl lock 3606 */ 3607 void bnx2x_set_reset_in_progress(struct bnx2x *bp) 3608 { 3609 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3610 u32 bit = BP_PATH(bp) ? 3611 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3612 3613 /* Set the bit */ 3614 val |= bit; 3615 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3616 barrier(); 3617 mmiowb(); 3618 } 3619 3620 /* 3621 * Checks the RESET_IN_PROGRESS bit for the given engine. 3622 * should be run under rtnl lock 3623 */ 3624 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) 3625 { 3626 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3627 u32 bit = engine ? 3628 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3629 3630 /* return false if bit is set */ 3631 return (val & bit) ? false : true; 3632 } 3633 3634 /* 3635 * Increment the load counter for the current engine. 3636 * 3637 * should be run under rtnl lock 3638 */ 3639 void bnx2x_inc_load_cnt(struct bnx2x *bp) 3640 { 3641 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3642 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3643 BNX2X_PATH0_LOAD_CNT_MASK; 3644 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3645 BNX2X_PATH0_LOAD_CNT_SHIFT; 3646 3647 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); 3648 3649 /* get the current counter value */ 3650 val1 = (val & mask) >> shift; 3651 3652 /* increment... */ 3653 val1++; 3654 3655 /* clear the old value */ 3656 val &= ~mask; 3657 3658 /* set the new one */ 3659 val |= ((val1 << shift) & mask); 3660 3661 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3662 barrier(); 3663 mmiowb(); 3664 } 3665 3666 /** 3667 * bnx2x_dec_load_cnt - decrement the load counter 3668 * 3669 * @bp: driver handle 3670 * 3671 * Should be run under rtnl lock. 3672 * Decrements the load counter for the current engine. Returns 3673 * the new counter value. 3674 */ 3675 u32 bnx2x_dec_load_cnt(struct bnx2x *bp) 3676 { 3677 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3678 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3679 BNX2X_PATH0_LOAD_CNT_MASK; 3680 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3681 BNX2X_PATH0_LOAD_CNT_SHIFT; 3682 3683 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); 3684 3685 /* get the current counter value */ 3686 val1 = (val & mask) >> shift; 3687 3688 /* decrement... */ 3689 val1--; 3690 3691 /* clear the old value */ 3692 val &= ~mask; 3693 3694 /* set the new one */ 3695 val |= ((val1 << shift) & mask); 3696 3697 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3698 barrier(); 3699 mmiowb(); 3700 3701 return val1; 3702 } 3703 3704 /* 3705 * Read the load counter for the current engine. 3706 * 3707 * should be run under rtnl lock 3708 */ 3709 static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine) 3710 { 3711 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : 3712 BNX2X_PATH0_LOAD_CNT_MASK); 3713 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3714 BNX2X_PATH0_LOAD_CNT_SHIFT); 3715 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3716 3717 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val); 3718 3719 val = (val & mask) >> shift; 3720 3721 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val); 3722 3723 return val; 3724 } 3725 3726 /* 3727 * Reset the load counter for the current engine. 3728 * 3729 * should be run under rtnl lock 3730 */ 3731 static inline void bnx2x_clear_load_cnt(struct bnx2x *bp) 3732 { 3733 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3734 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3735 BNX2X_PATH0_LOAD_CNT_MASK); 3736 3737 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask)); 3738 } 3739 3740 static inline void _print_next_block(int idx, const char *blk) 3741 { 3742 pr_cont("%s%s", idx ? ", " : "", blk); 3743 } 3744 3745 static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num, 3746 bool print) 3747 { 3748 int i = 0; 3749 u32 cur_bit = 0; 3750 for (i = 0; sig; i++) { 3751 cur_bit = ((u32)0x1 << i); 3752 if (sig & cur_bit) { 3753 switch (cur_bit) { 3754 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: 3755 if (print) 3756 _print_next_block(par_num++, "BRB"); 3757 break; 3758 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: 3759 if (print) 3760 _print_next_block(par_num++, "PARSER"); 3761 break; 3762 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: 3763 if (print) 3764 _print_next_block(par_num++, "TSDM"); 3765 break; 3766 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: 3767 if (print) 3768 _print_next_block(par_num++, 3769 "SEARCHER"); 3770 break; 3771 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: 3772 if (print) 3773 _print_next_block(par_num++, "TCM"); 3774 break; 3775 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: 3776 if (print) 3777 _print_next_block(par_num++, "TSEMI"); 3778 break; 3779 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: 3780 if (print) 3781 _print_next_block(par_num++, "XPB"); 3782 break; 3783 } 3784 3785 /* Clear the bit */ 3786 sig &= ~cur_bit; 3787 } 3788 } 3789 3790 return par_num; 3791 } 3792 3793 static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num, 3794 bool *global, bool print) 3795 { 3796 int i = 0; 3797 u32 cur_bit = 0; 3798 for (i = 0; sig; i++) { 3799 cur_bit = ((u32)0x1 << i); 3800 if (sig & cur_bit) { 3801 switch (cur_bit) { 3802 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: 3803 if (print) 3804 _print_next_block(par_num++, "PBF"); 3805 break; 3806 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: 3807 if (print) 3808 _print_next_block(par_num++, "QM"); 3809 break; 3810 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: 3811 if (print) 3812 _print_next_block(par_num++, "TM"); 3813 break; 3814 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: 3815 if (print) 3816 _print_next_block(par_num++, "XSDM"); 3817 break; 3818 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: 3819 if (print) 3820 _print_next_block(par_num++, "XCM"); 3821 break; 3822 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: 3823 if (print) 3824 _print_next_block(par_num++, "XSEMI"); 3825 break; 3826 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: 3827 if (print) 3828 _print_next_block(par_num++, 3829 "DOORBELLQ"); 3830 break; 3831 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: 3832 if (print) 3833 _print_next_block(par_num++, "NIG"); 3834 break; 3835 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: 3836 if (print) 3837 _print_next_block(par_num++, 3838 "VAUX PCI CORE"); 3839 *global = true; 3840 break; 3841 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: 3842 if (print) 3843 _print_next_block(par_num++, "DEBUG"); 3844 break; 3845 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: 3846 if (print) 3847 _print_next_block(par_num++, "USDM"); 3848 break; 3849 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: 3850 if (print) 3851 _print_next_block(par_num++, "UCM"); 3852 break; 3853 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: 3854 if (print) 3855 _print_next_block(par_num++, "USEMI"); 3856 break; 3857 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: 3858 if (print) 3859 _print_next_block(par_num++, "UPB"); 3860 break; 3861 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: 3862 if (print) 3863 _print_next_block(par_num++, "CSDM"); 3864 break; 3865 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: 3866 if (print) 3867 _print_next_block(par_num++, "CCM"); 3868 break; 3869 } 3870 3871 /* Clear the bit */ 3872 sig &= ~cur_bit; 3873 } 3874 } 3875 3876 return par_num; 3877 } 3878 3879 static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num, 3880 bool print) 3881 { 3882 int i = 0; 3883 u32 cur_bit = 0; 3884 for (i = 0; sig; i++) { 3885 cur_bit = ((u32)0x1 << i); 3886 if (sig & cur_bit) { 3887 switch (cur_bit) { 3888 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: 3889 if (print) 3890 _print_next_block(par_num++, "CSEMI"); 3891 break; 3892 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: 3893 if (print) 3894 _print_next_block(par_num++, "PXP"); 3895 break; 3896 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: 3897 if (print) 3898 _print_next_block(par_num++, 3899 "PXPPCICLOCKCLIENT"); 3900 break; 3901 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: 3902 if (print) 3903 _print_next_block(par_num++, "CFC"); 3904 break; 3905 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: 3906 if (print) 3907 _print_next_block(par_num++, "CDU"); 3908 break; 3909 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: 3910 if (print) 3911 _print_next_block(par_num++, "DMAE"); 3912 break; 3913 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: 3914 if (print) 3915 _print_next_block(par_num++, "IGU"); 3916 break; 3917 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: 3918 if (print) 3919 _print_next_block(par_num++, "MISC"); 3920 break; 3921 } 3922 3923 /* Clear the bit */ 3924 sig &= ~cur_bit; 3925 } 3926 } 3927 3928 return par_num; 3929 } 3930 3931 static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, 3932 bool *global, bool print) 3933 { 3934 int i = 0; 3935 u32 cur_bit = 0; 3936 for (i = 0; sig; i++) { 3937 cur_bit = ((u32)0x1 << i); 3938 if (sig & cur_bit) { 3939 switch (cur_bit) { 3940 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: 3941 if (print) 3942 _print_next_block(par_num++, "MCP ROM"); 3943 *global = true; 3944 break; 3945 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: 3946 if (print) 3947 _print_next_block(par_num++, 3948 "MCP UMP RX"); 3949 *global = true; 3950 break; 3951 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: 3952 if (print) 3953 _print_next_block(par_num++, 3954 "MCP UMP TX"); 3955 *global = true; 3956 break; 3957 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: 3958 if (print) 3959 _print_next_block(par_num++, 3960 "MCP SCPAD"); 3961 *global = true; 3962 break; 3963 } 3964 3965 /* Clear the bit */ 3966 sig &= ~cur_bit; 3967 } 3968 } 3969 3970 return par_num; 3971 } 3972 3973 static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num, 3974 bool print) 3975 { 3976 int i = 0; 3977 u32 cur_bit = 0; 3978 for (i = 0; sig; i++) { 3979 cur_bit = ((u32)0x1 << i); 3980 if (sig & cur_bit) { 3981 switch (cur_bit) { 3982 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: 3983 if (print) 3984 _print_next_block(par_num++, "PGLUE_B"); 3985 break; 3986 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: 3987 if (print) 3988 _print_next_block(par_num++, "ATC"); 3989 break; 3990 } 3991 3992 /* Clear the bit */ 3993 sig &= ~cur_bit; 3994 } 3995 } 3996 3997 return par_num; 3998 } 3999 4000 static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, 4001 u32 *sig) 4002 { 4003 if ((sig[0] & HW_PRTY_ASSERT_SET_0) || 4004 (sig[1] & HW_PRTY_ASSERT_SET_1) || 4005 (sig[2] & HW_PRTY_ASSERT_SET_2) || 4006 (sig[3] & HW_PRTY_ASSERT_SET_3) || 4007 (sig[4] & HW_PRTY_ASSERT_SET_4)) { 4008 int par_num = 0; 4009 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: " 4010 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x " 4011 "[4]:0x%08x\n", 4012 sig[0] & HW_PRTY_ASSERT_SET_0, 4013 sig[1] & HW_PRTY_ASSERT_SET_1, 4014 sig[2] & HW_PRTY_ASSERT_SET_2, 4015 sig[3] & HW_PRTY_ASSERT_SET_3, 4016 sig[4] & HW_PRTY_ASSERT_SET_4); 4017 if (print) 4018 netdev_err(bp->dev, 4019 "Parity errors detected in blocks: "); 4020 par_num = bnx2x_check_blocks_with_parity0( 4021 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); 4022 par_num = bnx2x_check_blocks_with_parity1( 4023 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); 4024 par_num = bnx2x_check_blocks_with_parity2( 4025 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); 4026 par_num = bnx2x_check_blocks_with_parity3( 4027 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); 4028 par_num = bnx2x_check_blocks_with_parity4( 4029 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); 4030 4031 if (print) 4032 pr_cont("\n"); 4033 4034 return true; 4035 } else 4036 return false; 4037 } 4038 4039 /** 4040 * bnx2x_chk_parity_attn - checks for parity attentions. 4041 * 4042 * @bp: driver handle 4043 * @global: true if there was a global attention 4044 * @print: show parity attention in syslog 4045 */ 4046 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) 4047 { 4048 struct attn_route attn = { {0} }; 4049 int port = BP_PORT(bp); 4050 4051 attn.sig[0] = REG_RD(bp, 4052 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + 4053 port*4); 4054 attn.sig[1] = REG_RD(bp, 4055 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + 4056 port*4); 4057 attn.sig[2] = REG_RD(bp, 4058 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + 4059 port*4); 4060 attn.sig[3] = REG_RD(bp, 4061 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + 4062 port*4); 4063 4064 if (!CHIP_IS_E1x(bp)) 4065 attn.sig[4] = REG_RD(bp, 4066 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + 4067 port*4); 4068 4069 return bnx2x_parity_attn(bp, global, print, attn.sig); 4070 } 4071 4072 4073 static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) 4074 { 4075 u32 val; 4076 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { 4077 4078 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); 4079 BNX2X_ERR("PGLUE hw attention 0x%x\n", val); 4080 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) 4081 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4082 "ADDRESS_ERROR\n"); 4083 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) 4084 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4085 "INCORRECT_RCV_BEHAVIOR\n"); 4086 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) 4087 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4088 "WAS_ERROR_ATTN\n"); 4089 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) 4090 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4091 "VF_LENGTH_VIOLATION_ATTN\n"); 4092 if (val & 4093 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) 4094 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4095 "VF_GRC_SPACE_VIOLATION_ATTN\n"); 4096 if (val & 4097 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) 4098 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4099 "VF_MSIX_BAR_VIOLATION_ATTN\n"); 4100 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) 4101 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4102 "TCPL_ERROR_ATTN\n"); 4103 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) 4104 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4105 "TCPL_IN_TWO_RCBS_ATTN\n"); 4106 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) 4107 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4108 "CSSNOOP_FIFO_OVERFLOW\n"); 4109 } 4110 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { 4111 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); 4112 BNX2X_ERR("ATC hw attention 0x%x\n", val); 4113 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) 4114 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); 4115 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) 4116 BNX2X_ERR("ATC_ATC_INT_STS_REG" 4117 "_ATC_TCPL_TO_NOT_PEND\n"); 4118 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) 4119 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4120 "ATC_GPA_MULTIPLE_HITS\n"); 4121 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) 4122 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4123 "ATC_RCPL_TO_EMPTY_CNT\n"); 4124 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) 4125 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); 4126 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) 4127 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4128 "ATC_IREQ_LESS_THAN_STU\n"); 4129 } 4130 4131 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4132 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { 4133 BNX2X_ERR("FATAL parity attention set4 0x%x\n", 4134 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4135 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); 4136 } 4137 4138 } 4139 4140 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) 4141 { 4142 struct attn_route attn, *group_mask; 4143 int port = BP_PORT(bp); 4144 int index; 4145 u32 reg_addr; 4146 u32 val; 4147 u32 aeu_mask; 4148 bool global = false; 4149 4150 /* need to take HW lock because MCP or other port might also 4151 try to handle this event */ 4152 bnx2x_acquire_alr(bp); 4153 4154 if (bnx2x_chk_parity_attn(bp, &global, true)) { 4155 #ifndef BNX2X_STOP_ON_ERROR 4156 bp->recovery_state = BNX2X_RECOVERY_INIT; 4157 schedule_delayed_work(&bp->sp_rtnl_task, 0); 4158 /* Disable HW interrupts */ 4159 bnx2x_int_disable(bp); 4160 /* In case of parity errors don't handle attentions so that 4161 * other function would "see" parity errors. 4162 */ 4163 #else 4164 bnx2x_panic(); 4165 #endif 4166 bnx2x_release_alr(bp); 4167 return; 4168 } 4169 4170 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 4171 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 4172 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 4173 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 4174 if (!CHIP_IS_E1x(bp)) 4175 attn.sig[4] = 4176 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); 4177 else 4178 attn.sig[4] = 0; 4179 4180 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", 4181 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); 4182 4183 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 4184 if (deasserted & (1 << index)) { 4185 group_mask = &bp->attn_group[index]; 4186 4187 DP(NETIF_MSG_HW, "group[%d]: %08x %08x " 4188 "%08x %08x %08x\n", 4189 index, 4190 group_mask->sig[0], group_mask->sig[1], 4191 group_mask->sig[2], group_mask->sig[3], 4192 group_mask->sig[4]); 4193 4194 bnx2x_attn_int_deasserted4(bp, 4195 attn.sig[4] & group_mask->sig[4]); 4196 bnx2x_attn_int_deasserted3(bp, 4197 attn.sig[3] & group_mask->sig[3]); 4198 bnx2x_attn_int_deasserted1(bp, 4199 attn.sig[1] & group_mask->sig[1]); 4200 bnx2x_attn_int_deasserted2(bp, 4201 attn.sig[2] & group_mask->sig[2]); 4202 bnx2x_attn_int_deasserted0(bp, 4203 attn.sig[0] & group_mask->sig[0]); 4204 } 4205 } 4206 4207 bnx2x_release_alr(bp); 4208 4209 if (bp->common.int_block == INT_BLOCK_HC) 4210 reg_addr = (HC_REG_COMMAND_REG + port*32 + 4211 COMMAND_REG_ATTN_BITS_CLR); 4212 else 4213 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); 4214 4215 val = ~deasserted; 4216 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, 4217 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 4218 REG_WR(bp, reg_addr, val); 4219 4220 if (~bp->attn_state & deasserted) 4221 BNX2X_ERR("IGU ERROR\n"); 4222 4223 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 4224 MISC_REG_AEU_MASK_ATTN_FUNC_0; 4225 4226 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4227 aeu_mask = REG_RD(bp, reg_addr); 4228 4229 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", 4230 aeu_mask, deasserted); 4231 aeu_mask |= (deasserted & 0x3ff); 4232 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 4233 4234 REG_WR(bp, reg_addr, aeu_mask); 4235 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4236 4237 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 4238 bp->attn_state &= ~deasserted; 4239 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 4240 } 4241 4242 static void bnx2x_attn_int(struct bnx2x *bp) 4243 { 4244 /* read local copy of bits */ 4245 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. 4246 attn_bits); 4247 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. 4248 attn_bits_ack); 4249 u32 attn_state = bp->attn_state; 4250 4251 /* look for changed bits */ 4252 u32 asserted = attn_bits & ~attn_ack & ~attn_state; 4253 u32 deasserted = ~attn_bits & attn_ack & attn_state; 4254 4255 DP(NETIF_MSG_HW, 4256 "attn_bits %x attn_ack %x asserted %x deasserted %x\n", 4257 attn_bits, attn_ack, asserted, deasserted); 4258 4259 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) 4260 BNX2X_ERR("BAD attention state\n"); 4261 4262 /* handle bits that were raised */ 4263 if (asserted) 4264 bnx2x_attn_int_asserted(bp, asserted); 4265 4266 if (deasserted) 4267 bnx2x_attn_int_deasserted(bp, deasserted); 4268 } 4269 4270 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 4271 u16 index, u8 op, u8 update) 4272 { 4273 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; 4274 4275 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, 4276 igu_addr); 4277 } 4278 4279 static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) 4280 { 4281 /* No memory barriers */ 4282 storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); 4283 mmiowb(); /* keep prod updates ordered */ 4284 } 4285 4286 #ifdef BCM_CNIC 4287 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, 4288 union event_ring_elem *elem) 4289 { 4290 u8 err = elem->message.error; 4291 4292 if (!bp->cnic_eth_dev.starting_cid || 4293 (cid < bp->cnic_eth_dev.starting_cid && 4294 cid != bp->cnic_eth_dev.iscsi_l2_cid)) 4295 return 1; 4296 4297 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); 4298 4299 if (unlikely(err)) { 4300 4301 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", 4302 cid); 4303 bnx2x_panic_dump(bp); 4304 } 4305 bnx2x_cnic_cfc_comp(bp, cid, err); 4306 return 0; 4307 } 4308 #endif 4309 4310 static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp) 4311 { 4312 struct bnx2x_mcast_ramrod_params rparam; 4313 int rc; 4314 4315 memset(&rparam, 0, sizeof(rparam)); 4316 4317 rparam.mcast_obj = &bp->mcast_obj; 4318 4319 netif_addr_lock_bh(bp->dev); 4320 4321 /* Clear pending state for the last command */ 4322 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); 4323 4324 /* If there are pending mcast commands - send them */ 4325 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { 4326 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 4327 if (rc < 0) 4328 BNX2X_ERR("Failed to send pending mcast commands: %d\n", 4329 rc); 4330 } 4331 4332 netif_addr_unlock_bh(bp->dev); 4333 } 4334 4335 static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp, 4336 union event_ring_elem *elem) 4337 { 4338 unsigned long ramrod_flags = 0; 4339 int rc = 0; 4340 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; 4341 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 4342 4343 /* Always push next commands out, don't wait here */ 4344 __set_bit(RAMROD_CONT, &ramrod_flags); 4345 4346 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { 4347 case BNX2X_FILTER_MAC_PENDING: 4348 #ifdef BCM_CNIC 4349 if (cid == BNX2X_ISCSI_ETH_CID) 4350 vlan_mac_obj = &bp->iscsi_l2_mac_obj; 4351 else 4352 #endif 4353 vlan_mac_obj = &bp->fp[cid].mac_obj; 4354 4355 break; 4356 case BNX2X_FILTER_MCAST_PENDING: 4357 /* This is only relevant for 57710 where multicast MACs are 4358 * configured as unicast MACs using the same ramrod. 4359 */ 4360 bnx2x_handle_mcast_eqe(bp); 4361 return; 4362 default: 4363 BNX2X_ERR("Unsupported classification command: %d\n", 4364 elem->message.data.eth_event.echo); 4365 return; 4366 } 4367 4368 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); 4369 4370 if (rc < 0) 4371 BNX2X_ERR("Failed to schedule new commands: %d\n", rc); 4372 else if (rc > 0) 4373 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); 4374 4375 } 4376 4377 #ifdef BCM_CNIC 4378 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); 4379 #endif 4380 4381 static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) 4382 { 4383 netif_addr_lock_bh(bp->dev); 4384 4385 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 4386 4387 /* Send rx_mode command again if was requested */ 4388 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) 4389 bnx2x_set_storm_rx_mode(bp); 4390 #ifdef BCM_CNIC 4391 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, 4392 &bp->sp_state)) 4393 bnx2x_set_iscsi_eth_rx_mode(bp, true); 4394 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 4395 &bp->sp_state)) 4396 bnx2x_set_iscsi_eth_rx_mode(bp, false); 4397 #endif 4398 4399 netif_addr_unlock_bh(bp->dev); 4400 } 4401 4402 static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( 4403 struct bnx2x *bp, u32 cid) 4404 { 4405 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); 4406 #ifdef BCM_CNIC 4407 if (cid == BNX2X_FCOE_ETH_CID) 4408 return &bnx2x_fcoe(bp, q_obj); 4409 else 4410 #endif 4411 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj); 4412 } 4413 4414 static void bnx2x_eq_int(struct bnx2x *bp) 4415 { 4416 u16 hw_cons, sw_cons, sw_prod; 4417 union event_ring_elem *elem; 4418 u32 cid; 4419 u8 opcode; 4420 int spqe_cnt = 0; 4421 struct bnx2x_queue_sp_obj *q_obj; 4422 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; 4423 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; 4424 4425 hw_cons = le16_to_cpu(*bp->eq_cons_sb); 4426 4427 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. 4428 * when we get the the next-page we nned to adjust so the loop 4429 * condition below will be met. The next element is the size of a 4430 * regular element and hence incrementing by 1 4431 */ 4432 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) 4433 hw_cons++; 4434 4435 /* This function may never run in parallel with itself for a 4436 * specific bp, thus there is no need in "paired" read memory 4437 * barrier here. 4438 */ 4439 sw_cons = bp->eq_cons; 4440 sw_prod = bp->eq_prod; 4441 4442 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", 4443 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); 4444 4445 for (; sw_cons != hw_cons; 4446 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { 4447 4448 4449 elem = &bp->eq_ring[EQ_DESC(sw_cons)]; 4450 4451 cid = SW_CID(elem->message.data.cfc_del_event.cid); 4452 opcode = elem->message.opcode; 4453 4454 4455 /* handle eq element */ 4456 switch (opcode) { 4457 case EVENT_RING_OPCODE_STAT_QUERY: 4458 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n", 4459 bp->stats_comp++); 4460 /* nothing to do with stats comp */ 4461 goto next_spqe; 4462 4463 case EVENT_RING_OPCODE_CFC_DEL: 4464 /* handle according to cid range */ 4465 /* 4466 * we may want to verify here that the bp state is 4467 * HALTING 4468 */ 4469 DP(BNX2X_MSG_SP, 4470 "got delete ramrod for MULTI[%d]\n", cid); 4471 #ifdef BCM_CNIC 4472 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem)) 4473 goto next_spqe; 4474 #endif 4475 q_obj = bnx2x_cid_to_q_obj(bp, cid); 4476 4477 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) 4478 break; 4479 4480 4481 4482 goto next_spqe; 4483 4484 case EVENT_RING_OPCODE_STOP_TRAFFIC: 4485 DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n"); 4486 if (f_obj->complete_cmd(bp, f_obj, 4487 BNX2X_F_CMD_TX_STOP)) 4488 break; 4489 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); 4490 goto next_spqe; 4491 4492 case EVENT_RING_OPCODE_START_TRAFFIC: 4493 DP(BNX2X_MSG_SP, "got START TRAFFIC\n"); 4494 if (f_obj->complete_cmd(bp, f_obj, 4495 BNX2X_F_CMD_TX_START)) 4496 break; 4497 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); 4498 goto next_spqe; 4499 case EVENT_RING_OPCODE_FUNCTION_START: 4500 DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n"); 4501 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) 4502 break; 4503 4504 goto next_spqe; 4505 4506 case EVENT_RING_OPCODE_FUNCTION_STOP: 4507 DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n"); 4508 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) 4509 break; 4510 4511 goto next_spqe; 4512 } 4513 4514 switch (opcode | bp->state) { 4515 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 4516 BNX2X_STATE_OPEN): 4517 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 4518 BNX2X_STATE_OPENING_WAIT4_PORT): 4519 cid = elem->message.data.eth_event.echo & 4520 BNX2X_SWCID_MASK; 4521 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", 4522 cid); 4523 rss_raw->clear_pending(rss_raw); 4524 break; 4525 4526 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): 4527 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): 4528 case (EVENT_RING_OPCODE_SET_MAC | 4529 BNX2X_STATE_CLOSING_WAIT4_HALT): 4530 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4531 BNX2X_STATE_OPEN): 4532 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4533 BNX2X_STATE_DIAG): 4534 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4535 BNX2X_STATE_CLOSING_WAIT4_HALT): 4536 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); 4537 bnx2x_handle_classification_eqe(bp, elem); 4538 break; 4539 4540 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4541 BNX2X_STATE_OPEN): 4542 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4543 BNX2X_STATE_DIAG): 4544 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4545 BNX2X_STATE_CLOSING_WAIT4_HALT): 4546 DP(BNX2X_MSG_SP, "got mcast ramrod\n"); 4547 bnx2x_handle_mcast_eqe(bp); 4548 break; 4549 4550 case (EVENT_RING_OPCODE_FILTERS_RULES | 4551 BNX2X_STATE_OPEN): 4552 case (EVENT_RING_OPCODE_FILTERS_RULES | 4553 BNX2X_STATE_DIAG): 4554 case (EVENT_RING_OPCODE_FILTERS_RULES | 4555 BNX2X_STATE_CLOSING_WAIT4_HALT): 4556 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); 4557 bnx2x_handle_rx_mode_eqe(bp); 4558 break; 4559 default: 4560 /* unknown event log error and continue */ 4561 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", 4562 elem->message.opcode, bp->state); 4563 } 4564 next_spqe: 4565 spqe_cnt++; 4566 } /* for */ 4567 4568 smp_mb__before_atomic_inc(); 4569 atomic_add(spqe_cnt, &bp->eq_spq_left); 4570 4571 bp->eq_cons = sw_cons; 4572 bp->eq_prod = sw_prod; 4573 /* Make sure that above mem writes were issued towards the memory */ 4574 smp_wmb(); 4575 4576 /* update producer */ 4577 bnx2x_update_eq_prod(bp, bp->eq_prod); 4578 } 4579 4580 static void bnx2x_sp_task(struct work_struct *work) 4581 { 4582 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); 4583 u16 status; 4584 4585 status = bnx2x_update_dsb_idx(bp); 4586 /* if (status == 0) */ 4587 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */ 4588 4589 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status); 4590 4591 /* HW attentions */ 4592 if (status & BNX2X_DEF_SB_ATT_IDX) { 4593 bnx2x_attn_int(bp); 4594 status &= ~BNX2X_DEF_SB_ATT_IDX; 4595 } 4596 4597 /* SP events: STAT_QUERY and others */ 4598 if (status & BNX2X_DEF_SB_IDX) { 4599 #ifdef BCM_CNIC 4600 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 4601 4602 if ((!NO_FCOE(bp)) && 4603 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { 4604 /* 4605 * Prevent local bottom-halves from running as 4606 * we are going to change the local NAPI list. 4607 */ 4608 local_bh_disable(); 4609 napi_schedule(&bnx2x_fcoe(bp, napi)); 4610 local_bh_enable(); 4611 } 4612 #endif 4613 /* Handle EQ completions */ 4614 bnx2x_eq_int(bp); 4615 4616 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 4617 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); 4618 4619 status &= ~BNX2X_DEF_SB_IDX; 4620 } 4621 4622 if (unlikely(status)) 4623 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 4624 status); 4625 4626 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, 4627 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); 4628 } 4629 4630 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) 4631 { 4632 struct net_device *dev = dev_instance; 4633 struct bnx2x *bp = netdev_priv(dev); 4634 4635 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, 4636 IGU_INT_DISABLE, 0); 4637 4638 #ifdef BNX2X_STOP_ON_ERROR 4639 if (unlikely(bp->panic)) 4640 return IRQ_HANDLED; 4641 #endif 4642 4643 #ifdef BCM_CNIC 4644 { 4645 struct cnic_ops *c_ops; 4646 4647 rcu_read_lock(); 4648 c_ops = rcu_dereference(bp->cnic_ops); 4649 if (c_ops) 4650 c_ops->cnic_handler(bp->cnic_data, NULL); 4651 rcu_read_unlock(); 4652 } 4653 #endif 4654 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 4655 4656 return IRQ_HANDLED; 4657 } 4658 4659 /* end of slow path */ 4660 4661 4662 void bnx2x_drv_pulse(struct bnx2x *bp) 4663 { 4664 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, 4665 bp->fw_drv_pulse_wr_seq); 4666 } 4667 4668 4669 static void bnx2x_timer(unsigned long data) 4670 { 4671 u8 cos; 4672 struct bnx2x *bp = (struct bnx2x *) data; 4673 4674 if (!netif_running(bp->dev)) 4675 return; 4676 4677 if (poll) { 4678 struct bnx2x_fastpath *fp = &bp->fp[0]; 4679 4680 for_each_cos_in_tx_queue(fp, cos) 4681 bnx2x_tx_int(bp, &fp->txdata[cos]); 4682 bnx2x_rx_int(fp, 1000); 4683 } 4684 4685 if (!BP_NOMCP(bp)) { 4686 int mb_idx = BP_FW_MB_IDX(bp); 4687 u32 drv_pulse; 4688 u32 mcp_pulse; 4689 4690 ++bp->fw_drv_pulse_wr_seq; 4691 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; 4692 /* TBD - add SYSTEM_TIME */ 4693 drv_pulse = bp->fw_drv_pulse_wr_seq; 4694 bnx2x_drv_pulse(bp); 4695 4696 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & 4697 MCP_PULSE_SEQ_MASK); 4698 /* The delta between driver pulse and mcp response 4699 * should be 1 (before mcp response) or 0 (after mcp response) 4700 */ 4701 if ((drv_pulse != mcp_pulse) && 4702 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { 4703 /* someone lost a heartbeat... */ 4704 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", 4705 drv_pulse, mcp_pulse); 4706 } 4707 } 4708 4709 if (bp->state == BNX2X_STATE_OPEN) 4710 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); 4711 4712 mod_timer(&bp->timer, jiffies + bp->current_interval); 4713 } 4714 4715 /* end of Statistics */ 4716 4717 /* nic init */ 4718 4719 /* 4720 * nic init service functions 4721 */ 4722 4723 static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) 4724 { 4725 u32 i; 4726 if (!(len%4) && !(addr%4)) 4727 for (i = 0; i < len; i += 4) 4728 REG_WR(bp, addr + i, fill); 4729 else 4730 for (i = 0; i < len; i++) 4731 REG_WR8(bp, addr + i, fill); 4732 4733 } 4734 4735 /* helper: writes FP SP data to FW - data_size in dwords */ 4736 static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp, 4737 int fw_sb_id, 4738 u32 *sb_data_p, 4739 u32 data_size) 4740 { 4741 int index; 4742 for (index = 0; index < data_size; index++) 4743 REG_WR(bp, BAR_CSTRORM_INTMEM + 4744 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + 4745 sizeof(u32)*index, 4746 *(sb_data_p + index)); 4747 } 4748 4749 static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) 4750 { 4751 u32 *sb_data_p; 4752 u32 data_size = 0; 4753 struct hc_status_block_data_e2 sb_data_e2; 4754 struct hc_status_block_data_e1x sb_data_e1x; 4755 4756 /* disable the function first */ 4757 if (!CHIP_IS_E1x(bp)) { 4758 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 4759 sb_data_e2.common.state = SB_DISABLED; 4760 sb_data_e2.common.p_func.vf_valid = false; 4761 sb_data_p = (u32 *)&sb_data_e2; 4762 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 4763 } else { 4764 memset(&sb_data_e1x, 0, 4765 sizeof(struct hc_status_block_data_e1x)); 4766 sb_data_e1x.common.state = SB_DISABLED; 4767 sb_data_e1x.common.p_func.vf_valid = false; 4768 sb_data_p = (u32 *)&sb_data_e1x; 4769 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 4770 } 4771 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 4772 4773 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4774 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, 4775 CSTORM_STATUS_BLOCK_SIZE); 4776 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4777 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, 4778 CSTORM_SYNC_BLOCK_SIZE); 4779 } 4780 4781 /* helper: writes SP SB data to FW */ 4782 static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp, 4783 struct hc_sp_status_block_data *sp_sb_data) 4784 { 4785 int func = BP_FUNC(bp); 4786 int i; 4787 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 4788 REG_WR(bp, BAR_CSTRORM_INTMEM + 4789 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 4790 i*sizeof(u32), 4791 *((u32 *)sp_sb_data + i)); 4792 } 4793 4794 static inline void bnx2x_zero_sp_sb(struct bnx2x *bp) 4795 { 4796 int func = BP_FUNC(bp); 4797 struct hc_sp_status_block_data sp_sb_data; 4798 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 4799 4800 sp_sb_data.state = SB_DISABLED; 4801 sp_sb_data.p_func.vf_valid = false; 4802 4803 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 4804 4805 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4806 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, 4807 CSTORM_SP_STATUS_BLOCK_SIZE); 4808 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4809 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, 4810 CSTORM_SP_SYNC_BLOCK_SIZE); 4811 4812 } 4813 4814 4815 static inline 4816 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, 4817 int igu_sb_id, int igu_seg_id) 4818 { 4819 hc_sm->igu_sb_id = igu_sb_id; 4820 hc_sm->igu_seg_id = igu_seg_id; 4821 hc_sm->timer_value = 0xFF; 4822 hc_sm->time_to_expire = 0xFFFFFFFF; 4823 } 4824 4825 4826 /* allocates state machine ids. */ 4827 static inline 4828 void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) 4829 { 4830 /* zero out state machine indices */ 4831 /* rx indices */ 4832 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 4833 4834 /* tx indices */ 4835 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 4836 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; 4837 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; 4838 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; 4839 4840 /* map indices */ 4841 /* rx indices */ 4842 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= 4843 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 4844 4845 /* tx indices */ 4846 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= 4847 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 4848 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= 4849 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 4850 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= 4851 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 4852 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= 4853 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 4854 } 4855 4856 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 4857 u8 vf_valid, int fw_sb_id, int igu_sb_id) 4858 { 4859 int igu_seg_id; 4860 4861 struct hc_status_block_data_e2 sb_data_e2; 4862 struct hc_status_block_data_e1x sb_data_e1x; 4863 struct hc_status_block_sm *hc_sm_p; 4864 int data_size; 4865 u32 *sb_data_p; 4866 4867 if (CHIP_INT_MODE_IS_BC(bp)) 4868 igu_seg_id = HC_SEG_ACCESS_NORM; 4869 else 4870 igu_seg_id = IGU_SEG_ACCESS_NORM; 4871 4872 bnx2x_zero_fp_sb(bp, fw_sb_id); 4873 4874 if (!CHIP_IS_E1x(bp)) { 4875 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 4876 sb_data_e2.common.state = SB_ENABLED; 4877 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); 4878 sb_data_e2.common.p_func.vf_id = vfid; 4879 sb_data_e2.common.p_func.vf_valid = vf_valid; 4880 sb_data_e2.common.p_func.vnic_id = BP_VN(bp); 4881 sb_data_e2.common.same_igu_sb_1b = true; 4882 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); 4883 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); 4884 hc_sm_p = sb_data_e2.common.state_machine; 4885 sb_data_p = (u32 *)&sb_data_e2; 4886 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 4887 bnx2x_map_sb_state_machines(sb_data_e2.index_data); 4888 } else { 4889 memset(&sb_data_e1x, 0, 4890 sizeof(struct hc_status_block_data_e1x)); 4891 sb_data_e1x.common.state = SB_ENABLED; 4892 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); 4893 sb_data_e1x.common.p_func.vf_id = 0xff; 4894 sb_data_e1x.common.p_func.vf_valid = false; 4895 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); 4896 sb_data_e1x.common.same_igu_sb_1b = true; 4897 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); 4898 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); 4899 hc_sm_p = sb_data_e1x.common.state_machine; 4900 sb_data_p = (u32 *)&sb_data_e1x; 4901 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 4902 bnx2x_map_sb_state_machines(sb_data_e1x.index_data); 4903 } 4904 4905 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], 4906 igu_sb_id, igu_seg_id); 4907 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], 4908 igu_sb_id, igu_seg_id); 4909 4910 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id); 4911 4912 /* write indecies to HW */ 4913 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 4914 } 4915 4916 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, 4917 u16 tx_usec, u16 rx_usec) 4918 { 4919 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, 4920 false, rx_usec); 4921 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 4922 HC_INDEX_ETH_TX_CQ_CONS_COS0, false, 4923 tx_usec); 4924 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 4925 HC_INDEX_ETH_TX_CQ_CONS_COS1, false, 4926 tx_usec); 4927 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 4928 HC_INDEX_ETH_TX_CQ_CONS_COS2, false, 4929 tx_usec); 4930 } 4931 4932 static void bnx2x_init_def_sb(struct bnx2x *bp) 4933 { 4934 struct host_sp_status_block *def_sb = bp->def_status_blk; 4935 dma_addr_t mapping = bp->def_status_blk_mapping; 4936 int igu_sp_sb_index; 4937 int igu_seg_id; 4938 int port = BP_PORT(bp); 4939 int func = BP_FUNC(bp); 4940 int reg_offset, reg_offset_en5; 4941 u64 section; 4942 int index; 4943 struct hc_sp_status_block_data sp_sb_data; 4944 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 4945 4946 if (CHIP_INT_MODE_IS_BC(bp)) { 4947 igu_sp_sb_index = DEF_SB_IGU_ID; 4948 igu_seg_id = HC_SEG_ACCESS_DEF; 4949 } else { 4950 igu_sp_sb_index = bp->igu_dsb_id; 4951 igu_seg_id = IGU_SEG_ACCESS_DEF; 4952 } 4953 4954 /* ATTN */ 4955 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 4956 atten_status_block); 4957 def_sb->atten_status_block.status_block_id = igu_sp_sb_index; 4958 4959 bp->attn_state = 0; 4960 4961 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 4962 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 4963 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : 4964 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); 4965 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 4966 int sindex; 4967 /* take care of sig[0]..sig[4] */ 4968 for (sindex = 0; sindex < 4; sindex++) 4969 bp->attn_group[index].sig[sindex] = 4970 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); 4971 4972 if (!CHIP_IS_E1x(bp)) 4973 /* 4974 * enable5 is separate from the rest of the registers, 4975 * and therefore the address skip is 4 4976 * and not 16 between the different groups 4977 */ 4978 bp->attn_group[index].sig[4] = REG_RD(bp, 4979 reg_offset_en5 + 0x4*index); 4980 else 4981 bp->attn_group[index].sig[4] = 0; 4982 } 4983 4984 if (bp->common.int_block == INT_BLOCK_HC) { 4985 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : 4986 HC_REG_ATTN_MSG0_ADDR_L); 4987 4988 REG_WR(bp, reg_offset, U64_LO(section)); 4989 REG_WR(bp, reg_offset + 4, U64_HI(section)); 4990 } else if (!CHIP_IS_E1x(bp)) { 4991 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); 4992 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); 4993 } 4994 4995 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 4996 sp_sb); 4997 4998 bnx2x_zero_sp_sb(bp); 4999 5000 sp_sb_data.state = SB_ENABLED; 5001 sp_sb_data.host_sb_addr.lo = U64_LO(section); 5002 sp_sb_data.host_sb_addr.hi = U64_HI(section); 5003 sp_sb_data.igu_sb_id = igu_sp_sb_index; 5004 sp_sb_data.igu_seg_id = igu_seg_id; 5005 sp_sb_data.p_func.pf_id = func; 5006 sp_sb_data.p_func.vnic_id = BP_VN(bp); 5007 sp_sb_data.p_func.vf_id = 0xff; 5008 5009 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 5010 5011 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); 5012 } 5013 5014 void bnx2x_update_coalesce(struct bnx2x *bp) 5015 { 5016 int i; 5017 5018 for_each_eth_queue(bp, i) 5019 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, 5020 bp->tx_ticks, bp->rx_ticks); 5021 } 5022 5023 static void bnx2x_init_sp_ring(struct bnx2x *bp) 5024 { 5025 spin_lock_init(&bp->spq_lock); 5026 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); 5027 5028 bp->spq_prod_idx = 0; 5029 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; 5030 bp->spq_prod_bd = bp->spq; 5031 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; 5032 } 5033 5034 static void bnx2x_init_eq_ring(struct bnx2x *bp) 5035 { 5036 int i; 5037 for (i = 1; i <= NUM_EQ_PAGES; i++) { 5038 union event_ring_elem *elem = 5039 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; 5040 5041 elem->next_page.addr.hi = 5042 cpu_to_le32(U64_HI(bp->eq_mapping + 5043 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); 5044 elem->next_page.addr.lo = 5045 cpu_to_le32(U64_LO(bp->eq_mapping + 5046 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); 5047 } 5048 bp->eq_cons = 0; 5049 bp->eq_prod = NUM_EQ_DESC; 5050 bp->eq_cons_sb = BNX2X_EQ_INDEX; 5051 /* we want a warning message before it gets rought... */ 5052 atomic_set(&bp->eq_spq_left, 5053 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); 5054 } 5055 5056 5057 /* called with netif_addr_lock_bh() */ 5058 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 5059 unsigned long rx_mode_flags, 5060 unsigned long rx_accept_flags, 5061 unsigned long tx_accept_flags, 5062 unsigned long ramrod_flags) 5063 { 5064 struct bnx2x_rx_mode_ramrod_params ramrod_param; 5065 int rc; 5066 5067 memset(&ramrod_param, 0, sizeof(ramrod_param)); 5068 5069 /* Prepare ramrod parameters */ 5070 ramrod_param.cid = 0; 5071 ramrod_param.cl_id = cl_id; 5072 ramrod_param.rx_mode_obj = &bp->rx_mode_obj; 5073 ramrod_param.func_id = BP_FUNC(bp); 5074 5075 ramrod_param.pstate = &bp->sp_state; 5076 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; 5077 5078 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); 5079 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); 5080 5081 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 5082 5083 ramrod_param.ramrod_flags = ramrod_flags; 5084 ramrod_param.rx_mode_flags = rx_mode_flags; 5085 5086 ramrod_param.rx_accept_flags = rx_accept_flags; 5087 ramrod_param.tx_accept_flags = tx_accept_flags; 5088 5089 rc = bnx2x_config_rx_mode(bp, &ramrod_param); 5090 if (rc < 0) { 5091 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); 5092 return; 5093 } 5094 } 5095 5096 /* called with netif_addr_lock_bh() */ 5097 void bnx2x_set_storm_rx_mode(struct bnx2x *bp) 5098 { 5099 unsigned long rx_mode_flags = 0, ramrod_flags = 0; 5100 unsigned long rx_accept_flags = 0, tx_accept_flags = 0; 5101 5102 #ifdef BCM_CNIC 5103 if (!NO_FCOE(bp)) 5104 5105 /* Configure rx_mode of FCoE Queue */ 5106 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); 5107 #endif 5108 5109 switch (bp->rx_mode) { 5110 case BNX2X_RX_MODE_NONE: 5111 /* 5112 * 'drop all' supersedes any accept flags that may have been 5113 * passed to the function. 5114 */ 5115 break; 5116 case BNX2X_RX_MODE_NORMAL: 5117 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5118 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags); 5119 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5120 5121 /* internal switching mode */ 5122 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5123 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags); 5124 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5125 5126 break; 5127 case BNX2X_RX_MODE_ALLMULTI: 5128 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5129 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5130 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5131 5132 /* internal switching mode */ 5133 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5134 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5135 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5136 5137 break; 5138 case BNX2X_RX_MODE_PROMISC: 5139 /* According to deffinition of SI mode, iface in promisc mode 5140 * should receive matched and unmatched (in resolution of port) 5141 * unicast packets. 5142 */ 5143 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags); 5144 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5145 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5146 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5147 5148 /* internal switching mode */ 5149 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5150 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5151 5152 if (IS_MF_SI(bp)) 5153 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags); 5154 else 5155 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5156 5157 break; 5158 default: 5159 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode); 5160 return; 5161 } 5162 5163 if (bp->rx_mode != BNX2X_RX_MODE_NONE) { 5164 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags); 5165 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags); 5166 } 5167 5168 __set_bit(RAMROD_RX, &ramrod_flags); 5169 __set_bit(RAMROD_TX, &ramrod_flags); 5170 5171 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags, 5172 tx_accept_flags, ramrod_flags); 5173 } 5174 5175 static void bnx2x_init_internal_common(struct bnx2x *bp) 5176 { 5177 int i; 5178 5179 if (IS_MF_SI(bp)) 5180 /* 5181 * In switch independent mode, the TSTORM needs to accept 5182 * packets that failed classification, since approximate match 5183 * mac addresses aren't written to NIG LLH 5184 */ 5185 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5186 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); 5187 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ 5188 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5189 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); 5190 5191 /* Zero this manually as its initialization is 5192 currently missing in the initTool */ 5193 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) 5194 REG_WR(bp, BAR_USTRORM_INTMEM + 5195 USTORM_AGG_DATA_OFFSET + i * 4, 0); 5196 if (!CHIP_IS_E1x(bp)) { 5197 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, 5198 CHIP_INT_MODE_IS_BC(bp) ? 5199 HC_IGU_BC_MODE : HC_IGU_NBC_MODE); 5200 } 5201 } 5202 5203 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) 5204 { 5205 switch (load_code) { 5206 case FW_MSG_CODE_DRV_LOAD_COMMON: 5207 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 5208 bnx2x_init_internal_common(bp); 5209 /* no break */ 5210 5211 case FW_MSG_CODE_DRV_LOAD_PORT: 5212 /* nothing to do */ 5213 /* no break */ 5214 5215 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 5216 /* internal memory per function is 5217 initialized inside bnx2x_pf_init */ 5218 break; 5219 5220 default: 5221 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); 5222 break; 5223 } 5224 } 5225 5226 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) 5227 { 5228 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT; 5229 } 5230 5231 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) 5232 { 5233 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT; 5234 } 5235 5236 static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) 5237 { 5238 if (CHIP_IS_E1x(fp->bp)) 5239 return BP_L_ID(fp->bp) + fp->index; 5240 else /* We want Client ID to be the same as IGU SB ID for 57712 */ 5241 return bnx2x_fp_igu_sb_id(fp); 5242 } 5243 5244 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) 5245 { 5246 struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; 5247 u8 cos; 5248 unsigned long q_type = 0; 5249 u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; 5250 5251 fp->cid = fp_idx; 5252 fp->cl_id = bnx2x_fp_cl_id(fp); 5253 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); 5254 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); 5255 /* qZone id equals to FW (per path) client id */ 5256 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); 5257 5258 /* init shortcut */ 5259 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); 5260 /* Setup SB indicies */ 5261 fp->rx_cons_sb = BNX2X_RX_SB_INDEX; 5262 5263 /* Configure Queue State object */ 5264 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 5265 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 5266 5267 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); 5268 5269 /* init tx data */ 5270 for_each_cos_in_tx_queue(fp, cos) { 5271 bnx2x_init_txdata(bp, &fp->txdata[cos], 5272 CID_COS_TO_TX_ONLY_CID(fp->cid, cos), 5273 FP_COS_TO_TXQ(fp, cos), 5274 BNX2X_TX_SB_INDEX_BASE + cos); 5275 cids[cos] = fp->txdata[cos].cid; 5276 } 5277 5278 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos, 5279 BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 5280 bnx2x_sp_mapping(bp, q_rdata), q_type); 5281 5282 /** 5283 * Configure classification DBs: Always enable Tx switching 5284 */ 5285 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); 5286 5287 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) " 5288 "cl_id %d fw_sb %d igu_sb %d\n", 5289 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 5290 fp->igu_sb_id); 5291 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, 5292 fp->fw_sb_id, fp->igu_sb_id); 5293 5294 bnx2x_update_fpsb_idx(fp); 5295 } 5296 5297 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) 5298 { 5299 int i; 5300 5301 for_each_eth_queue(bp, i) 5302 bnx2x_init_eth_fp(bp, i); 5303 #ifdef BCM_CNIC 5304 if (!NO_FCOE(bp)) 5305 bnx2x_init_fcoe_fp(bp); 5306 5307 bnx2x_init_sb(bp, bp->cnic_sb_mapping, 5308 BNX2X_VF_ID_INVALID, false, 5309 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); 5310 5311 #endif 5312 5313 /* Initialize MOD_ABS interrupts */ 5314 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, 5315 bp->common.shmem_base, bp->common.shmem2_base, 5316 BP_PORT(bp)); 5317 /* ensure status block indices were read */ 5318 rmb(); 5319 5320 bnx2x_init_def_sb(bp); 5321 bnx2x_update_dsb_idx(bp); 5322 bnx2x_init_rx_rings(bp); 5323 bnx2x_init_tx_rings(bp); 5324 bnx2x_init_sp_ring(bp); 5325 bnx2x_init_eq_ring(bp); 5326 bnx2x_init_internal(bp, load_code); 5327 bnx2x_pf_init(bp); 5328 bnx2x_stats_init(bp); 5329 5330 /* flush all before enabling interrupts */ 5331 mb(); 5332 mmiowb(); 5333 5334 bnx2x_int_enable(bp); 5335 5336 /* Check for SPIO5 */ 5337 bnx2x_attn_int_deasserted0(bp, 5338 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & 5339 AEU_INPUTS_ATTN_BITS_SPIO5); 5340 } 5341 5342 /* end of nic init */ 5343 5344 /* 5345 * gzip service functions 5346 */ 5347 5348 static int bnx2x_gunzip_init(struct bnx2x *bp) 5349 { 5350 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, 5351 &bp->gunzip_mapping, GFP_KERNEL); 5352 if (bp->gunzip_buf == NULL) 5353 goto gunzip_nomem1; 5354 5355 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); 5356 if (bp->strm == NULL) 5357 goto gunzip_nomem2; 5358 5359 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); 5360 if (bp->strm->workspace == NULL) 5361 goto gunzip_nomem3; 5362 5363 return 0; 5364 5365 gunzip_nomem3: 5366 kfree(bp->strm); 5367 bp->strm = NULL; 5368 5369 gunzip_nomem2: 5370 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 5371 bp->gunzip_mapping); 5372 bp->gunzip_buf = NULL; 5373 5374 gunzip_nomem1: 5375 netdev_err(bp->dev, "Cannot allocate firmware buffer for" 5376 " un-compression\n"); 5377 return -ENOMEM; 5378 } 5379 5380 static void bnx2x_gunzip_end(struct bnx2x *bp) 5381 { 5382 if (bp->strm) { 5383 vfree(bp->strm->workspace); 5384 kfree(bp->strm); 5385 bp->strm = NULL; 5386 } 5387 5388 if (bp->gunzip_buf) { 5389 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 5390 bp->gunzip_mapping); 5391 bp->gunzip_buf = NULL; 5392 } 5393 } 5394 5395 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) 5396 { 5397 int n, rc; 5398 5399 /* check gzip header */ 5400 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { 5401 BNX2X_ERR("Bad gzip header\n"); 5402 return -EINVAL; 5403 } 5404 5405 n = 10; 5406 5407 #define FNAME 0x8 5408 5409 if (zbuf[3] & FNAME) 5410 while ((zbuf[n++] != 0) && (n < len)); 5411 5412 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; 5413 bp->strm->avail_in = len - n; 5414 bp->strm->next_out = bp->gunzip_buf; 5415 bp->strm->avail_out = FW_BUF_SIZE; 5416 5417 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); 5418 if (rc != Z_OK) 5419 return rc; 5420 5421 rc = zlib_inflate(bp->strm, Z_FINISH); 5422 if ((rc != Z_OK) && (rc != Z_STREAM_END)) 5423 netdev_err(bp->dev, "Firmware decompression error: %s\n", 5424 bp->strm->msg); 5425 5426 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); 5427 if (bp->gunzip_outlen & 0x3) 5428 netdev_err(bp->dev, "Firmware decompression error:" 5429 " gunzip_outlen (%d) not aligned\n", 5430 bp->gunzip_outlen); 5431 bp->gunzip_outlen >>= 2; 5432 5433 zlib_inflateEnd(bp->strm); 5434 5435 if (rc == Z_STREAM_END) 5436 return 0; 5437 5438 return rc; 5439 } 5440 5441 /* nic load/unload */ 5442 5443 /* 5444 * General service functions 5445 */ 5446 5447 /* send a NIG loopback debug packet */ 5448 static void bnx2x_lb_pckt(struct bnx2x *bp) 5449 { 5450 u32 wb_write[3]; 5451 5452 /* Ethernet source and destination addresses */ 5453 wb_write[0] = 0x55555555; 5454 wb_write[1] = 0x55555555; 5455 wb_write[2] = 0x20; /* SOP */ 5456 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 5457 5458 /* NON-IP protocol */ 5459 wb_write[0] = 0x09000000; 5460 wb_write[1] = 0x55555555; 5461 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ 5462 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 5463 } 5464 5465 /* some of the internal memories 5466 * are not directly readable from the driver 5467 * to test them we send debug packets 5468 */ 5469 static int bnx2x_int_mem_test(struct bnx2x *bp) 5470 { 5471 int factor; 5472 int count, i; 5473 u32 val = 0; 5474 5475 if (CHIP_REV_IS_FPGA(bp)) 5476 factor = 120; 5477 else if (CHIP_REV_IS_EMUL(bp)) 5478 factor = 200; 5479 else 5480 factor = 1; 5481 5482 /* Disable inputs of parser neighbor blocks */ 5483 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 5484 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 5485 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 5486 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 5487 5488 /* Write 0 to parser credits for CFC search request */ 5489 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 5490 5491 /* send Ethernet packet */ 5492 bnx2x_lb_pckt(bp); 5493 5494 /* TODO do i reset NIG statistic? */ 5495 /* Wait until NIG register shows 1 packet of size 0x10 */ 5496 count = 1000 * factor; 5497 while (count) { 5498 5499 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5500 val = *bnx2x_sp(bp, wb_data[0]); 5501 if (val == 0x10) 5502 break; 5503 5504 msleep(10); 5505 count--; 5506 } 5507 if (val != 0x10) { 5508 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 5509 return -1; 5510 } 5511 5512 /* Wait until PRS register shows 1 packet */ 5513 count = 1000 * factor; 5514 while (count) { 5515 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5516 if (val == 1) 5517 break; 5518 5519 msleep(10); 5520 count--; 5521 } 5522 if (val != 0x1) { 5523 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5524 return -2; 5525 } 5526 5527 /* Reset and init BRB, PRS */ 5528 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 5529 msleep(50); 5530 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 5531 msleep(50); 5532 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 5533 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 5534 5535 DP(NETIF_MSG_HW, "part2\n"); 5536 5537 /* Disable inputs of parser neighbor blocks */ 5538 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 5539 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 5540 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 5541 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 5542 5543 /* Write 0 to parser credits for CFC search request */ 5544 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 5545 5546 /* send 10 Ethernet packets */ 5547 for (i = 0; i < 10; i++) 5548 bnx2x_lb_pckt(bp); 5549 5550 /* Wait until NIG register shows 10 + 1 5551 packets of size 11*0x10 = 0xb0 */ 5552 count = 1000 * factor; 5553 while (count) { 5554 5555 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5556 val = *bnx2x_sp(bp, wb_data[0]); 5557 if (val == 0xb0) 5558 break; 5559 5560 msleep(10); 5561 count--; 5562 } 5563 if (val != 0xb0) { 5564 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 5565 return -3; 5566 } 5567 5568 /* Wait until PRS register shows 2 packets */ 5569 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5570 if (val != 2) 5571 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5572 5573 /* Write 1 to parser credits for CFC search request */ 5574 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); 5575 5576 /* Wait until PRS register shows 3 packets */ 5577 msleep(10 * factor); 5578 /* Wait until NIG register shows 1 packet of size 0x10 */ 5579 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5580 if (val != 3) 5581 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5582 5583 /* clear NIG EOP FIFO */ 5584 for (i = 0; i < 11; i++) 5585 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); 5586 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); 5587 if (val != 1) { 5588 BNX2X_ERR("clear of NIG failed\n"); 5589 return -4; 5590 } 5591 5592 /* Reset and init BRB, PRS, NIG */ 5593 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 5594 msleep(50); 5595 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 5596 msleep(50); 5597 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 5598 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 5599 #ifndef BCM_CNIC 5600 /* set NIC mode */ 5601 REG_WR(bp, PRS_REG_NIC_MODE, 1); 5602 #endif 5603 5604 /* Enable inputs of parser neighbor blocks */ 5605 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); 5606 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); 5607 REG_WR(bp, CFC_REG_DEBUG0, 0x0); 5608 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); 5609 5610 DP(NETIF_MSG_HW, "done\n"); 5611 5612 return 0; /* OK */ 5613 } 5614 5615 static void bnx2x_enable_blocks_attention(struct bnx2x *bp) 5616 { 5617 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 5618 if (!CHIP_IS_E1x(bp)) 5619 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); 5620 else 5621 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); 5622 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 5623 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 5624 /* 5625 * mask read length error interrupts in brb for parser 5626 * (parsing unit and 'checksum and crc' unit) 5627 * these errors are legal (PU reads fixed length and CAC can cause 5628 * read length error on truncated packets) 5629 */ 5630 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); 5631 REG_WR(bp, QM_REG_QM_INT_MASK, 0); 5632 REG_WR(bp, TM_REG_TM_INT_MASK, 0); 5633 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); 5634 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); 5635 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); 5636 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ 5637 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ 5638 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); 5639 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); 5640 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); 5641 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ 5642 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ 5643 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); 5644 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); 5645 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); 5646 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); 5647 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ 5648 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ 5649 5650 if (CHIP_REV_IS_FPGA(bp)) 5651 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000); 5652 else if (!CHIP_IS_E1x(bp)) 5653 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 5654 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF 5655 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT 5656 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN 5657 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED 5658 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED)); 5659 else 5660 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000); 5661 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); 5662 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); 5663 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); 5664 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ 5665 5666 if (!CHIP_IS_E1x(bp)) 5667 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ 5668 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); 5669 5670 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); 5671 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); 5672 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ 5673 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ 5674 } 5675 5676 static void bnx2x_reset_common(struct bnx2x *bp) 5677 { 5678 u32 val = 0x1400; 5679 5680 /* reset_common */ 5681 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 5682 0xd3ffff7f); 5683 5684 if (CHIP_IS_E3(bp)) { 5685 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 5686 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 5687 } 5688 5689 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); 5690 } 5691 5692 static void bnx2x_setup_dmae(struct bnx2x *bp) 5693 { 5694 bp->dmae_ready = 0; 5695 spin_lock_init(&bp->dmae_lock); 5696 } 5697 5698 static void bnx2x_init_pxp(struct bnx2x *bp) 5699 { 5700 u16 devctl; 5701 int r_order, w_order; 5702 5703 pci_read_config_word(bp->pdev, 5704 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl); 5705 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); 5706 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 5707 if (bp->mrrs == -1) 5708 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); 5709 else { 5710 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); 5711 r_order = bp->mrrs; 5712 } 5713 5714 bnx2x_init_pxp_arb(bp, r_order, w_order); 5715 } 5716 5717 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) 5718 { 5719 int is_required; 5720 u32 val; 5721 int port; 5722 5723 if (BP_NOMCP(bp)) 5724 return; 5725 5726 is_required = 0; 5727 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 5728 SHARED_HW_CFG_FAN_FAILURE_MASK; 5729 5730 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) 5731 is_required = 1; 5732 5733 /* 5734 * The fan failure mechanism is usually related to the PHY type since 5735 * the power consumption of the board is affected by the PHY. Currently, 5736 * fan is required for most designs with SFX7101, BCM8727 and BCM8481. 5737 */ 5738 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) 5739 for (port = PORT_0; port < PORT_MAX; port++) { 5740 is_required |= 5741 bnx2x_fan_failure_det_req( 5742 bp, 5743 bp->common.shmem_base, 5744 bp->common.shmem2_base, 5745 port); 5746 } 5747 5748 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); 5749 5750 if (is_required == 0) 5751 return; 5752 5753 /* Fan failure is indicated by SPIO 5 */ 5754 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, 5755 MISC_REGISTERS_SPIO_INPUT_HI_Z); 5756 5757 /* set to active low mode */ 5758 val = REG_RD(bp, MISC_REG_SPIO_INT); 5759 val |= ((1 << MISC_REGISTERS_SPIO_5) << 5760 MISC_REGISTERS_SPIO_INT_OLD_SET_POS); 5761 REG_WR(bp, MISC_REG_SPIO_INT, val); 5762 5763 /* enable interrupt to signal the IGU */ 5764 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 5765 val |= (1 << MISC_REGISTERS_SPIO_5); 5766 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); 5767 } 5768 5769 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num) 5770 { 5771 u32 offset = 0; 5772 5773 if (CHIP_IS_E1(bp)) 5774 return; 5775 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX)) 5776 return; 5777 5778 switch (BP_ABS_FUNC(bp)) { 5779 case 0: 5780 offset = PXP2_REG_PGL_PRETEND_FUNC_F0; 5781 break; 5782 case 1: 5783 offset = PXP2_REG_PGL_PRETEND_FUNC_F1; 5784 break; 5785 case 2: 5786 offset = PXP2_REG_PGL_PRETEND_FUNC_F2; 5787 break; 5788 case 3: 5789 offset = PXP2_REG_PGL_PRETEND_FUNC_F3; 5790 break; 5791 case 4: 5792 offset = PXP2_REG_PGL_PRETEND_FUNC_F4; 5793 break; 5794 case 5: 5795 offset = PXP2_REG_PGL_PRETEND_FUNC_F5; 5796 break; 5797 case 6: 5798 offset = PXP2_REG_PGL_PRETEND_FUNC_F6; 5799 break; 5800 case 7: 5801 offset = PXP2_REG_PGL_PRETEND_FUNC_F7; 5802 break; 5803 default: 5804 return; 5805 } 5806 5807 REG_WR(bp, offset, pretend_func_num); 5808 REG_RD(bp, offset); 5809 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num); 5810 } 5811 5812 void bnx2x_pf_disable(struct bnx2x *bp) 5813 { 5814 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 5815 val &= ~IGU_PF_CONF_FUNC_EN; 5816 5817 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 5818 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 5819 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); 5820 } 5821 5822 static inline void bnx2x__common_init_phy(struct bnx2x *bp) 5823 { 5824 u32 shmem_base[2], shmem2_base[2]; 5825 shmem_base[0] = bp->common.shmem_base; 5826 shmem2_base[0] = bp->common.shmem2_base; 5827 if (!CHIP_IS_E1x(bp)) { 5828 shmem_base[1] = 5829 SHMEM2_RD(bp, other_shmem_base_addr); 5830 shmem2_base[1] = 5831 SHMEM2_RD(bp, other_shmem2_base_addr); 5832 } 5833 bnx2x_acquire_phy_lock(bp); 5834 bnx2x_common_init_phy(bp, shmem_base, shmem2_base, 5835 bp->common.chip_id); 5836 bnx2x_release_phy_lock(bp); 5837 } 5838 5839 /** 5840 * bnx2x_init_hw_common - initialize the HW at the COMMON phase. 5841 * 5842 * @bp: driver handle 5843 */ 5844 static int bnx2x_init_hw_common(struct bnx2x *bp) 5845 { 5846 u32 val; 5847 5848 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp)); 5849 5850 /* 5851 * take the UNDI lock to protect undi_unload flow from accessing 5852 * registers while we're resetting the chip 5853 */ 5854 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 5855 5856 bnx2x_reset_common(bp); 5857 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); 5858 5859 val = 0xfffc; 5860 if (CHIP_IS_E3(bp)) { 5861 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 5862 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 5863 } 5864 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); 5865 5866 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 5867 5868 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); 5869 5870 if (!CHIP_IS_E1x(bp)) { 5871 u8 abs_func_id; 5872 5873 /** 5874 * 4-port mode or 2-port mode we need to turn of master-enable 5875 * for everyone, after that, turn it back on for self. 5876 * so, we disregard multi-function or not, and always disable 5877 * for all functions on the given path, this means 0,2,4,6 for 5878 * path 0 and 1,3,5,7 for path 1 5879 */ 5880 for (abs_func_id = BP_PATH(bp); 5881 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { 5882 if (abs_func_id == BP_ABS_FUNC(bp)) { 5883 REG_WR(bp, 5884 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 5885 1); 5886 continue; 5887 } 5888 5889 bnx2x_pretend_func(bp, abs_func_id); 5890 /* clear pf enable */ 5891 bnx2x_pf_disable(bp); 5892 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 5893 } 5894 } 5895 5896 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); 5897 if (CHIP_IS_E1(bp)) { 5898 /* enable HW interrupt from PXP on USDM overflow 5899 bit 16 on INT_MASK_0 */ 5900 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 5901 } 5902 5903 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); 5904 bnx2x_init_pxp(bp); 5905 5906 #ifdef __BIG_ENDIAN 5907 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); 5908 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); 5909 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); 5910 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); 5911 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); 5912 /* make sure this value is 0 */ 5913 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); 5914 5915 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ 5916 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); 5917 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); 5918 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); 5919 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); 5920 #endif 5921 5922 bnx2x_ilt_init_page_size(bp, INITOP_SET); 5923 5924 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) 5925 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); 5926 5927 /* let the HW do it's magic ... */ 5928 msleep(100); 5929 /* finish PXP init */ 5930 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); 5931 if (val != 1) { 5932 BNX2X_ERR("PXP2 CFG failed\n"); 5933 return -EBUSY; 5934 } 5935 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); 5936 if (val != 1) { 5937 BNX2X_ERR("PXP2 RD_INIT failed\n"); 5938 return -EBUSY; 5939 } 5940 5941 /* Timers bug workaround E2 only. We need to set the entire ILT to 5942 * have entries with value "0" and valid bit on. 5943 * This needs to be done by the first PF that is loaded in a path 5944 * (i.e. common phase) 5945 */ 5946 if (!CHIP_IS_E1x(bp)) { 5947 /* In E2 there is a bug in the timers block that can cause function 6 / 7 5948 * (i.e. vnic3) to start even if it is marked as "scan-off". 5949 * This occurs when a different function (func2,3) is being marked 5950 * as "scan-off". Real-life scenario for example: if a driver is being 5951 * load-unloaded while func6,7 are down. This will cause the timer to access 5952 * the ilt, translate to a logical address and send a request to read/write. 5953 * Since the ilt for the function that is down is not valid, this will cause 5954 * a translation error which is unrecoverable. 5955 * The Workaround is intended to make sure that when this happens nothing fatal 5956 * will occur. The workaround: 5957 * 1. First PF driver which loads on a path will: 5958 * a. After taking the chip out of reset, by using pretend, 5959 * it will write "0" to the following registers of 5960 * the other vnics. 5961 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 5962 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); 5963 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); 5964 * And for itself it will write '1' to 5965 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable 5966 * dmae-operations (writing to pram for example.) 5967 * note: can be done for only function 6,7 but cleaner this 5968 * way. 5969 * b. Write zero+valid to the entire ILT. 5970 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of 5971 * VNIC3 (of that port). The range allocated will be the 5972 * entire ILT. This is needed to prevent ILT range error. 5973 * 2. Any PF driver load flow: 5974 * a. ILT update with the physical addresses of the allocated 5975 * logical pages. 5976 * b. Wait 20msec. - note that this timeout is needed to make 5977 * sure there are no requests in one of the PXP internal 5978 * queues with "old" ILT addresses. 5979 * c. PF enable in the PGLC. 5980 * d. Clear the was_error of the PF in the PGLC. (could have 5981 * occured while driver was down) 5982 * e. PF enable in the CFC (WEAK + STRONG) 5983 * f. Timers scan enable 5984 * 3. PF driver unload flow: 5985 * a. Clear the Timers scan_en. 5986 * b. Polling for scan_on=0 for that PF. 5987 * c. Clear the PF enable bit in the PXP. 5988 * d. Clear the PF enable in the CFC (WEAK + STRONG) 5989 * e. Write zero+valid to all ILT entries (The valid bit must 5990 * stay set) 5991 * f. If this is VNIC 3 of a port then also init 5992 * first_timers_ilt_entry to zero and last_timers_ilt_entry 5993 * to the last enrty in the ILT. 5994 * 5995 * Notes: 5996 * Currently the PF error in the PGLC is non recoverable. 5997 * In the future the there will be a recovery routine for this error. 5998 * Currently attention is masked. 5999 * Having an MCP lock on the load/unload process does not guarantee that 6000 * there is no Timer disable during Func6/7 enable. This is because the 6001 * Timers scan is currently being cleared by the MCP on FLR. 6002 * Step 2.d can be done only for PF6/7 and the driver can also check if 6003 * there is error before clearing it. But the flow above is simpler and 6004 * more general. 6005 * All ILT entries are written by zero+valid and not just PF6/7 6006 * ILT entries since in the future the ILT entries allocation for 6007 * PF-s might be dynamic. 6008 */ 6009 struct ilt_client_info ilt_cli; 6010 struct bnx2x_ilt ilt; 6011 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 6012 memset(&ilt, 0, sizeof(struct bnx2x_ilt)); 6013 6014 /* initialize dummy TM client */ 6015 ilt_cli.start = 0; 6016 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 6017 ilt_cli.client_num = ILT_CLIENT_TM; 6018 6019 /* Step 1: set zeroes to all ilt page entries with valid bit on 6020 * Step 2: set the timers first/last ilt entry to point 6021 * to the entire range to prevent ILT range error for 3rd/4th 6022 * vnic (this code assumes existance of the vnic) 6023 * 6024 * both steps performed by call to bnx2x_ilt_client_init_op() 6025 * with dummy TM client 6026 * 6027 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT 6028 * and his brother are split registers 6029 */ 6030 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); 6031 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); 6032 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 6033 6034 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); 6035 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); 6036 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); 6037 } 6038 6039 6040 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); 6041 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); 6042 6043 if (!CHIP_IS_E1x(bp)) { 6044 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : 6045 (CHIP_REV_IS_FPGA(bp) ? 400 : 0); 6046 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); 6047 6048 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); 6049 6050 /* let the HW do it's magic ... */ 6051 do { 6052 msleep(200); 6053 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); 6054 } while (factor-- && (val != 1)); 6055 6056 if (val != 1) { 6057 BNX2X_ERR("ATC_INIT failed\n"); 6058 return -EBUSY; 6059 } 6060 } 6061 6062 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); 6063 6064 /* clean the DMAE memory */ 6065 bp->dmae_ready = 1; 6066 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); 6067 6068 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); 6069 6070 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); 6071 6072 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); 6073 6074 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); 6075 6076 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); 6077 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); 6078 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); 6079 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); 6080 6081 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); 6082 6083 6084 /* QM queues pointers table */ 6085 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); 6086 6087 /* soft reset pulse */ 6088 REG_WR(bp, QM_REG_SOFT_RESET, 1); 6089 REG_WR(bp, QM_REG_SOFT_RESET, 0); 6090 6091 #ifdef BCM_CNIC 6092 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); 6093 #endif 6094 6095 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); 6096 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); 6097 if (!CHIP_REV_IS_SLOW(bp)) 6098 /* enable hw interrupt from doorbell Q */ 6099 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 6100 6101 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6102 6103 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6104 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); 6105 6106 if (!CHIP_IS_E1(bp)) 6107 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); 6108 6109 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) 6110 /* Bit-map indicating which L2 hdrs may appear 6111 * after the basic Ethernet header 6112 */ 6113 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 6114 bp->path_has_ovlan ? 7 : 6); 6115 6116 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); 6117 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); 6118 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); 6119 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); 6120 6121 if (!CHIP_IS_E1x(bp)) { 6122 /* reset VFC memories */ 6123 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6124 VFC_MEMORIES_RST_REG_CAM_RST | 6125 VFC_MEMORIES_RST_REG_RAM_RST); 6126 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6127 VFC_MEMORIES_RST_REG_CAM_RST | 6128 VFC_MEMORIES_RST_REG_RAM_RST); 6129 6130 msleep(20); 6131 } 6132 6133 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); 6134 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); 6135 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); 6136 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); 6137 6138 /* sync semi rtc */ 6139 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 6140 0x80000000); 6141 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 6142 0x80000000); 6143 6144 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); 6145 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); 6146 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); 6147 6148 if (!CHIP_IS_E1x(bp)) 6149 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 6150 bp->path_has_ovlan ? 7 : 6); 6151 6152 REG_WR(bp, SRC_REG_SOFT_RST, 1); 6153 6154 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); 6155 6156 #ifdef BCM_CNIC 6157 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); 6158 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); 6159 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); 6160 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); 6161 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); 6162 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); 6163 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); 6164 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); 6165 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); 6166 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); 6167 #endif 6168 REG_WR(bp, SRC_REG_SOFT_RST, 0); 6169 6170 if (sizeof(union cdu_context) != 1024) 6171 /* we currently assume that a context is 1024 bytes */ 6172 dev_alert(&bp->pdev->dev, "please adjust the size " 6173 "of cdu_context(%ld)\n", 6174 (long)sizeof(union cdu_context)); 6175 6176 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); 6177 val = (4 << 24) + (0 << 12) + 1024; 6178 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); 6179 6180 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); 6181 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); 6182 /* enable context validation interrupt from CFC */ 6183 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 6184 6185 /* set the thresholds to prevent CFC/CDU race */ 6186 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); 6187 6188 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); 6189 6190 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) 6191 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); 6192 6193 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); 6194 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); 6195 6196 /* Reset PCIE errors for debug */ 6197 REG_WR(bp, 0x2814, 0xffffffff); 6198 REG_WR(bp, 0x3820, 0xffffffff); 6199 6200 if (!CHIP_IS_E1x(bp)) { 6201 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, 6202 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | 6203 PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); 6204 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, 6205 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | 6206 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | 6207 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); 6208 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, 6209 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | 6210 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | 6211 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); 6212 } 6213 6214 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); 6215 if (!CHIP_IS_E1(bp)) { 6216 /* in E3 this done in per-port section */ 6217 if (!CHIP_IS_E3(bp)) 6218 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6219 } 6220 if (CHIP_IS_E1H(bp)) 6221 /* not applicable for E2 (and above ...) */ 6222 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); 6223 6224 if (CHIP_REV_IS_SLOW(bp)) 6225 msleep(200); 6226 6227 /* finish CFC init */ 6228 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); 6229 if (val != 1) { 6230 BNX2X_ERR("CFC LL_INIT failed\n"); 6231 return -EBUSY; 6232 } 6233 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); 6234 if (val != 1) { 6235 BNX2X_ERR("CFC AC_INIT failed\n"); 6236 return -EBUSY; 6237 } 6238 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); 6239 if (val != 1) { 6240 BNX2X_ERR("CFC CAM_INIT failed\n"); 6241 return -EBUSY; 6242 } 6243 REG_WR(bp, CFC_REG_DEBUG0, 0); 6244 6245 if (CHIP_IS_E1(bp)) { 6246 /* read NIG statistic 6247 to see if this is our first up since powerup */ 6248 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6249 val = *bnx2x_sp(bp, wb_data[0]); 6250 6251 /* do internal memory self test */ 6252 if ((val == 0) && bnx2x_int_mem_test(bp)) { 6253 BNX2X_ERR("internal mem self test failed\n"); 6254 return -EBUSY; 6255 } 6256 } 6257 6258 bnx2x_setup_fan_failure_detection(bp); 6259 6260 /* clear PXP2 attentions */ 6261 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); 6262 6263 bnx2x_enable_blocks_attention(bp); 6264 bnx2x_enable_blocks_parity(bp); 6265 6266 if (!BP_NOMCP(bp)) { 6267 if (CHIP_IS_E1x(bp)) 6268 bnx2x__common_init_phy(bp); 6269 } else 6270 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 6271 6272 return 0; 6273 } 6274 6275 /** 6276 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. 6277 * 6278 * @bp: driver handle 6279 */ 6280 static int bnx2x_init_hw_common_chip(struct bnx2x *bp) 6281 { 6282 int rc = bnx2x_init_hw_common(bp); 6283 6284 if (rc) 6285 return rc; 6286 6287 /* In E2 2-PORT mode, same ext phy is used for the two paths */ 6288 if (!BP_NOMCP(bp)) 6289 bnx2x__common_init_phy(bp); 6290 6291 return 0; 6292 } 6293 6294 static int bnx2x_init_hw_port(struct bnx2x *bp) 6295 { 6296 int port = BP_PORT(bp); 6297 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; 6298 u32 low, high; 6299 u32 val; 6300 6301 bnx2x__link_reset(bp); 6302 6303 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port); 6304 6305 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 6306 6307 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6308 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6309 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6310 6311 /* Timers bug workaround: disables the pf_master bit in pglue at 6312 * common phase, we need to enable it here before any dmae access are 6313 * attempted. Therefore we manually added the enable-master to the 6314 * port phase (it also happens in the function phase) 6315 */ 6316 if (!CHIP_IS_E1x(bp)) 6317 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6318 6319 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6320 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6321 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6322 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6323 6324 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6325 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6326 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6327 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6328 6329 /* QM cid (connection) count */ 6330 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); 6331 6332 #ifdef BCM_CNIC 6333 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6334 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); 6335 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); 6336 #endif 6337 6338 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6339 6340 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { 6341 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6342 6343 if (IS_MF(bp)) 6344 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); 6345 else if (bp->dev->mtu > 4096) { 6346 if (bp->flags & ONE_PORT_FLAG) 6347 low = 160; 6348 else { 6349 val = bp->dev->mtu; 6350 /* (24*1024 + val*4)/256 */ 6351 low = 96 + (val/64) + 6352 ((val % 64) ? 1 : 0); 6353 } 6354 } else 6355 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); 6356 high = low + 56; /* 14*1024/256 */ 6357 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); 6358 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); 6359 } 6360 6361 if (CHIP_MODE_IS_4_PORT(bp)) 6362 REG_WR(bp, (BP_PORT(bp) ? 6363 BRB1_REG_MAC_GUARANTIED_1 : 6364 BRB1_REG_MAC_GUARANTIED_0), 40); 6365 6366 6367 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 6368 if (CHIP_IS_E3B0(bp)) 6369 /* Ovlan exists only if we are in multi-function + 6370 * switch-dependent mode, in switch-independent there 6371 * is no ovlan headers 6372 */ 6373 REG_WR(bp, BP_PORT(bp) ? 6374 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 6375 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 6376 (bp->path_has_ovlan ? 7 : 6)); 6377 6378 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 6379 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 6380 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 6381 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 6382 6383 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 6384 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 6385 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 6386 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 6387 6388 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 6389 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 6390 6391 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 6392 6393 if (CHIP_IS_E1x(bp)) { 6394 /* configure PBF to work without PAUSE mtu 9000 */ 6395 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 6396 6397 /* update threshold */ 6398 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); 6399 /* update init credit */ 6400 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); 6401 6402 /* probe changes */ 6403 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); 6404 udelay(50); 6405 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); 6406 } 6407 6408 #ifdef BCM_CNIC 6409 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 6410 #endif 6411 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 6412 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 6413 6414 if (CHIP_IS_E1(bp)) { 6415 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6416 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6417 } 6418 bnx2x_init_block(bp, BLOCK_HC, init_phase); 6419 6420 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 6421 6422 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 6423 /* init aeu_mask_attn_func_0/1: 6424 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use 6425 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF 6426 * bits 4-7 are used for "per vn group attention" */ 6427 val = IS_MF(bp) ? 0xF7 : 0x7; 6428 /* Enable DCBX attention for all but E1 */ 6429 val |= CHIP_IS_E1(bp) ? 0 : 0x10; 6430 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); 6431 6432 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 6433 6434 if (!CHIP_IS_E1x(bp)) { 6435 /* Bit-map indicating which L2 hdrs may appear after the 6436 * basic Ethernet header 6437 */ 6438 REG_WR(bp, BP_PORT(bp) ? 6439 NIG_REG_P1_HDRS_AFTER_BASIC : 6440 NIG_REG_P0_HDRS_AFTER_BASIC, 6441 IS_MF_SD(bp) ? 7 : 6); 6442 6443 if (CHIP_IS_E3(bp)) 6444 REG_WR(bp, BP_PORT(bp) ? 6445 NIG_REG_LLH1_MF_MODE : 6446 NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6447 } 6448 if (!CHIP_IS_E3(bp)) 6449 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 6450 6451 if (!CHIP_IS_E1(bp)) { 6452 /* 0x2 disable mf_ov, 0x1 enable */ 6453 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, 6454 (IS_MF_SD(bp) ? 0x1 : 0x2)); 6455 6456 if (!CHIP_IS_E1x(bp)) { 6457 val = 0; 6458 switch (bp->mf_mode) { 6459 case MULTI_FUNCTION_SD: 6460 val = 1; 6461 break; 6462 case MULTI_FUNCTION_SI: 6463 val = 2; 6464 break; 6465 } 6466 6467 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : 6468 NIG_REG_LLH0_CLS_TYPE), val); 6469 } 6470 { 6471 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); 6472 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); 6473 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); 6474 } 6475 } 6476 6477 6478 /* If SPIO5 is set to generate interrupts, enable it for this port */ 6479 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 6480 if (val & (1 << MISC_REGISTERS_SPIO_5)) { 6481 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 6482 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 6483 val = REG_RD(bp, reg_addr); 6484 val |= AEU_INPUTS_ATTN_BITS_SPIO5; 6485 REG_WR(bp, reg_addr, val); 6486 } 6487 6488 return 0; 6489 } 6490 6491 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) 6492 { 6493 int reg; 6494 6495 if (CHIP_IS_E1(bp)) 6496 reg = PXP2_REG_RQ_ONCHIP_AT + index*8; 6497 else 6498 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; 6499 6500 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr)); 6501 } 6502 6503 static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) 6504 { 6505 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); 6506 } 6507 6508 static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) 6509 { 6510 u32 i, base = FUNC_ILT_BASE(func); 6511 for (i = base; i < base + ILT_PER_FUNC; i++) 6512 bnx2x_ilt_wr(bp, i, 0); 6513 } 6514 6515 static int bnx2x_init_hw_func(struct bnx2x *bp) 6516 { 6517 int port = BP_PORT(bp); 6518 int func = BP_FUNC(bp); 6519 int init_phase = PHASE_PF0 + func; 6520 struct bnx2x_ilt *ilt = BP_ILT(bp); 6521 u16 cdu_ilt_start; 6522 u32 addr, val; 6523 u32 main_mem_base, main_mem_size, main_mem_prty_clr; 6524 int i, main_mem_width; 6525 6526 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func); 6527 6528 /* FLR cleanup - hmmm */ 6529 if (!CHIP_IS_E1x(bp)) 6530 bnx2x_pf_flr_clnup(bp); 6531 6532 /* set MSI reconfigure capability */ 6533 if (bp->common.int_block == INT_BLOCK_HC) { 6534 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); 6535 val = REG_RD(bp, addr); 6536 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; 6537 REG_WR(bp, addr, val); 6538 } 6539 6540 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6541 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6542 6543 ilt = BP_ILT(bp); 6544 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 6545 6546 for (i = 0; i < L2_ILT_LINES(bp); i++) { 6547 ilt->lines[cdu_ilt_start + i].page = 6548 bp->context.vcxt + (ILT_PAGE_CIDS * i); 6549 ilt->lines[cdu_ilt_start + i].page_mapping = 6550 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i); 6551 /* cdu ilt pages are allocated manually so there's no need to 6552 set the size */ 6553 } 6554 bnx2x_ilt_init_op(bp, INITOP_SET); 6555 6556 #ifdef BCM_CNIC 6557 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); 6558 6559 /* T1 hash bits value determines the T1 number of entries */ 6560 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); 6561 #endif 6562 6563 #ifndef BCM_CNIC 6564 /* set NIC mode */ 6565 REG_WR(bp, PRS_REG_NIC_MODE, 1); 6566 #endif /* BCM_CNIC */ 6567 6568 if (!CHIP_IS_E1x(bp)) { 6569 u32 pf_conf = IGU_PF_CONF_FUNC_EN; 6570 6571 /* Turn on a single ISR mode in IGU if driver is going to use 6572 * INT#x or MSI 6573 */ 6574 if (!(bp->flags & USING_MSIX_FLAG)) 6575 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 6576 /* 6577 * Timers workaround bug: function init part. 6578 * Need to wait 20msec after initializing ILT, 6579 * needed to make sure there are no requests in 6580 * one of the PXP internal queues with "old" ILT addresses 6581 */ 6582 msleep(20); 6583 /* 6584 * Master enable - Due to WB DMAE writes performed before this 6585 * register is re-initialized as part of the regular function 6586 * init 6587 */ 6588 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6589 /* Enable the function in IGU */ 6590 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); 6591 } 6592 6593 bp->dmae_ready = 1; 6594 6595 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6596 6597 if (!CHIP_IS_E1x(bp)) 6598 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); 6599 6600 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6601 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6602 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 6603 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 6604 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6605 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6606 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6607 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6608 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6609 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 6610 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 6611 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 6612 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 6613 6614 if (!CHIP_IS_E1x(bp)) 6615 REG_WR(bp, QM_REG_PF_EN, 1); 6616 6617 if (!CHIP_IS_E1x(bp)) { 6618 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6619 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6620 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6621 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6622 } 6623 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6624 6625 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6626 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6627 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6628 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 6629 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 6630 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 6631 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 6632 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 6633 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 6634 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 6635 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 6636 if (!CHIP_IS_E1x(bp)) 6637 REG_WR(bp, PBF_REG_DISABLE_PF, 0); 6638 6639 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 6640 6641 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 6642 6643 if (!CHIP_IS_E1x(bp)) 6644 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); 6645 6646 if (IS_MF(bp)) { 6647 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 6648 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); 6649 } 6650 6651 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 6652 6653 /* HC init per function */ 6654 if (bp->common.int_block == INT_BLOCK_HC) { 6655 if (CHIP_IS_E1H(bp)) { 6656 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 6657 6658 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6659 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6660 } 6661 bnx2x_init_block(bp, BLOCK_HC, init_phase); 6662 6663 } else { 6664 int num_segs, sb_idx, prod_offset; 6665 6666 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 6667 6668 if (!CHIP_IS_E1x(bp)) { 6669 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 6670 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 6671 } 6672 6673 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 6674 6675 if (!CHIP_IS_E1x(bp)) { 6676 int dsb_idx = 0; 6677 /** 6678 * Producer memory: 6679 * E2 mode: address 0-135 match to the mapping memory; 6680 * 136 - PF0 default prod; 137 - PF1 default prod; 6681 * 138 - PF2 default prod; 139 - PF3 default prod; 6682 * 140 - PF0 attn prod; 141 - PF1 attn prod; 6683 * 142 - PF2 attn prod; 143 - PF3 attn prod; 6684 * 144-147 reserved. 6685 * 6686 * E1.5 mode - In backward compatible mode; 6687 * for non default SB; each even line in the memory 6688 * holds the U producer and each odd line hold 6689 * the C producer. The first 128 producers are for 6690 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 6691 * producers are for the DSB for each PF. 6692 * Each PF has five segments: (the order inside each 6693 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 6694 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 6695 * 144-147 attn prods; 6696 */ 6697 /* non-default-status-blocks */ 6698 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 6699 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; 6700 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { 6701 prod_offset = (bp->igu_base_sb + sb_idx) * 6702 num_segs; 6703 6704 for (i = 0; i < num_segs; i++) { 6705 addr = IGU_REG_PROD_CONS_MEMORY + 6706 (prod_offset + i) * 4; 6707 REG_WR(bp, addr, 0); 6708 } 6709 /* send consumer update with value 0 */ 6710 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, 6711 USTORM_ID, 0, IGU_INT_NOP, 1); 6712 bnx2x_igu_clear_sb(bp, 6713 bp->igu_base_sb + sb_idx); 6714 } 6715 6716 /* default-status-blocks */ 6717 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 6718 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; 6719 6720 if (CHIP_MODE_IS_4_PORT(bp)) 6721 dsb_idx = BP_FUNC(bp); 6722 else 6723 dsb_idx = BP_VN(bp); 6724 6725 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? 6726 IGU_BC_BASE_DSB_PROD + dsb_idx : 6727 IGU_NORM_BASE_DSB_PROD + dsb_idx); 6728 6729 /* 6730 * igu prods come in chunks of E1HVN_MAX (4) - 6731 * does not matters what is the current chip mode 6732 */ 6733 for (i = 0; i < (num_segs * E1HVN_MAX); 6734 i += E1HVN_MAX) { 6735 addr = IGU_REG_PROD_CONS_MEMORY + 6736 (prod_offset + i)*4; 6737 REG_WR(bp, addr, 0); 6738 } 6739 /* send consumer update with 0 */ 6740 if (CHIP_INT_MODE_IS_BC(bp)) { 6741 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6742 USTORM_ID, 0, IGU_INT_NOP, 1); 6743 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6744 CSTORM_ID, 0, IGU_INT_NOP, 1); 6745 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6746 XSTORM_ID, 0, IGU_INT_NOP, 1); 6747 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6748 TSTORM_ID, 0, IGU_INT_NOP, 1); 6749 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6750 ATTENTION_ID, 0, IGU_INT_NOP, 1); 6751 } else { 6752 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6753 USTORM_ID, 0, IGU_INT_NOP, 1); 6754 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6755 ATTENTION_ID, 0, IGU_INT_NOP, 1); 6756 } 6757 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); 6758 6759 /* !!! these should become driver const once 6760 rf-tool supports split-68 const */ 6761 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 6762 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 6763 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); 6764 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); 6765 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); 6766 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); 6767 } 6768 } 6769 6770 /* Reset PCIE errors for debug */ 6771 REG_WR(bp, 0x2114, 0xffffffff); 6772 REG_WR(bp, 0x2120, 0xffffffff); 6773 6774 if (CHIP_IS_E1x(bp)) { 6775 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ 6776 main_mem_base = HC_REG_MAIN_MEMORY + 6777 BP_PORT(bp) * (main_mem_size * 4); 6778 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; 6779 main_mem_width = 8; 6780 6781 val = REG_RD(bp, main_mem_prty_clr); 6782 if (val) 6783 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC " 6784 "block during " 6785 "function init (0x%x)!\n", val); 6786 6787 /* Clear "false" parity errors in MSI-X table */ 6788 for (i = main_mem_base; 6789 i < main_mem_base + main_mem_size * 4; 6790 i += main_mem_width) { 6791 bnx2x_read_dmae(bp, i, main_mem_width / 4); 6792 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), 6793 i, main_mem_width / 4); 6794 } 6795 /* Clear HC parity attention */ 6796 REG_RD(bp, main_mem_prty_clr); 6797 } 6798 6799 #ifdef BNX2X_STOP_ON_ERROR 6800 /* Enable STORMs SP logging */ 6801 REG_WR8(bp, BAR_USTRORM_INTMEM + 6802 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6803 REG_WR8(bp, BAR_TSTRORM_INTMEM + 6804 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6805 REG_WR8(bp, BAR_CSTRORM_INTMEM + 6806 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6807 REG_WR8(bp, BAR_XSTRORM_INTMEM + 6808 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6809 #endif 6810 6811 bnx2x_phy_probe(&bp->link_params); 6812 6813 return 0; 6814 } 6815 6816 6817 void bnx2x_free_mem(struct bnx2x *bp) 6818 { 6819 /* fastpath */ 6820 bnx2x_free_fp_mem(bp); 6821 /* end of fastpath */ 6822 6823 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, 6824 sizeof(struct host_sp_status_block)); 6825 6826 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 6827 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 6828 6829 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, 6830 sizeof(struct bnx2x_slowpath)); 6831 6832 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping, 6833 bp->context.size); 6834 6835 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); 6836 6837 BNX2X_FREE(bp->ilt->lines); 6838 6839 #ifdef BCM_CNIC 6840 if (!CHIP_IS_E1x(bp)) 6841 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, 6842 sizeof(struct host_hc_status_block_e2)); 6843 else 6844 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, 6845 sizeof(struct host_hc_status_block_e1x)); 6846 6847 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); 6848 #endif 6849 6850 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); 6851 6852 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, 6853 BCM_PAGE_SIZE * NUM_EQ_PAGES); 6854 } 6855 6856 static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp) 6857 { 6858 int num_groups; 6859 6860 /* number of eth_queues */ 6861 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp); 6862 6863 /* Total number of FW statistics requests = 6864 * 1 for port stats + 1 for PF stats + num_eth_queues */ 6865 bp->fw_stats_num = 2 + num_queue_stats; 6866 6867 6868 /* Request is built from stats_query_header and an array of 6869 * stats_query_cmd_group each of which contains 6870 * STATS_QUERY_CMD_COUNT rules. The real number or requests is 6871 * configured in the stats_query_header. 6872 */ 6873 num_groups = (2 + num_queue_stats) / STATS_QUERY_CMD_COUNT + 6874 (((2 + num_queue_stats) % STATS_QUERY_CMD_COUNT) ? 1 : 0); 6875 6876 bp->fw_stats_req_sz = sizeof(struct stats_query_header) + 6877 num_groups * sizeof(struct stats_query_cmd_group); 6878 6879 /* Data for statistics requests + stats_conter 6880 * 6881 * stats_counter holds per-STORM counters that are incremented 6882 * when STORM has finished with the current request. 6883 */ 6884 bp->fw_stats_data_sz = sizeof(struct per_port_stats) + 6885 sizeof(struct per_pf_stats) + 6886 sizeof(struct per_queue_stats) * num_queue_stats + 6887 sizeof(struct stats_counter); 6888 6889 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping, 6890 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 6891 6892 /* Set shortcuts */ 6893 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats; 6894 bp->fw_stats_req_mapping = bp->fw_stats_mapping; 6895 6896 bp->fw_stats_data = (struct bnx2x_fw_stats_data *) 6897 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz); 6898 6899 bp->fw_stats_data_mapping = bp->fw_stats_mapping + 6900 bp->fw_stats_req_sz; 6901 return 0; 6902 6903 alloc_mem_err: 6904 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 6905 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 6906 return -ENOMEM; 6907 } 6908 6909 6910 int bnx2x_alloc_mem(struct bnx2x *bp) 6911 { 6912 #ifdef BCM_CNIC 6913 if (!CHIP_IS_E1x(bp)) 6914 /* size = the status block + ramrod buffers */ 6915 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, 6916 sizeof(struct host_hc_status_block_e2)); 6917 else 6918 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping, 6919 sizeof(struct host_hc_status_block_e1x)); 6920 6921 /* allocate searcher T2 table */ 6922 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); 6923 #endif 6924 6925 6926 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, 6927 sizeof(struct host_sp_status_block)); 6928 6929 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, 6930 sizeof(struct bnx2x_slowpath)); 6931 6932 /* Allocated memory for FW statistics */ 6933 if (bnx2x_alloc_fw_stats_mem(bp)) 6934 goto alloc_mem_err; 6935 6936 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); 6937 6938 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping, 6939 bp->context.size); 6940 6941 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); 6942 6943 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) 6944 goto alloc_mem_err; 6945 6946 /* Slow path ring */ 6947 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); 6948 6949 /* EQ */ 6950 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, 6951 BCM_PAGE_SIZE * NUM_EQ_PAGES); 6952 6953 6954 /* fastpath */ 6955 /* need to be done at the end, since it's self adjusting to amount 6956 * of memory available for RSS queues 6957 */ 6958 if (bnx2x_alloc_fp_mem(bp)) 6959 goto alloc_mem_err; 6960 return 0; 6961 6962 alloc_mem_err: 6963 bnx2x_free_mem(bp); 6964 return -ENOMEM; 6965 } 6966 6967 /* 6968 * Init service functions 6969 */ 6970 6971 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 6972 struct bnx2x_vlan_mac_obj *obj, bool set, 6973 int mac_type, unsigned long *ramrod_flags) 6974 { 6975 int rc; 6976 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 6977 6978 memset(&ramrod_param, 0, sizeof(ramrod_param)); 6979 6980 /* Fill general parameters */ 6981 ramrod_param.vlan_mac_obj = obj; 6982 ramrod_param.ramrod_flags = *ramrod_flags; 6983 6984 /* Fill a user request section if needed */ 6985 if (!test_bit(RAMROD_CONT, ramrod_flags)) { 6986 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); 6987 6988 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); 6989 6990 /* Set the command: ADD or DEL */ 6991 if (set) 6992 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; 6993 else 6994 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; 6995 } 6996 6997 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 6998 if (rc < 0) 6999 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); 7000 return rc; 7001 } 7002 7003 int bnx2x_del_all_macs(struct bnx2x *bp, 7004 struct bnx2x_vlan_mac_obj *mac_obj, 7005 int mac_type, bool wait_for_comp) 7006 { 7007 int rc; 7008 unsigned long ramrod_flags = 0, vlan_mac_flags = 0; 7009 7010 /* Wait for completion of requested */ 7011 if (wait_for_comp) 7012 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 7013 7014 /* Set the mac type of addresses we want to clear */ 7015 __set_bit(mac_type, &vlan_mac_flags); 7016 7017 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); 7018 if (rc < 0) 7019 BNX2X_ERR("Failed to delete MACs: %d\n", rc); 7020 7021 return rc; 7022 } 7023 7024 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) 7025 { 7026 unsigned long ramrod_flags = 0; 7027 7028 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); 7029 7030 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 7031 /* Eth MAC is set on RSS leading client (fp[0]) */ 7032 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set, 7033 BNX2X_ETH_MAC, &ramrod_flags); 7034 } 7035 7036 int bnx2x_setup_leading(struct bnx2x *bp) 7037 { 7038 return bnx2x_setup_queue(bp, &bp->fp[0], 1); 7039 } 7040 7041 /** 7042 * bnx2x_set_int_mode - configure interrupt mode 7043 * 7044 * @bp: driver handle 7045 * 7046 * In case of MSI-X it will also try to enable MSI-X. 7047 */ 7048 static void __devinit bnx2x_set_int_mode(struct bnx2x *bp) 7049 { 7050 switch (int_mode) { 7051 case INT_MODE_MSI: 7052 bnx2x_enable_msi(bp); 7053 /* falling through... */ 7054 case INT_MODE_INTx: 7055 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7056 DP(NETIF_MSG_IFUP, "set number of queues to 1\n"); 7057 break; 7058 default: 7059 /* Set number of queues according to bp->multi_mode value */ 7060 bnx2x_set_num_queues(bp); 7061 7062 DP(NETIF_MSG_IFUP, "set number of queues to %d\n", 7063 bp->num_queues); 7064 7065 /* if we can't use MSI-X we only need one fp, 7066 * so try to enable MSI-X with the requested number of fp's 7067 * and fallback to MSI or legacy INTx with one fp 7068 */ 7069 if (bnx2x_enable_msix(bp)) { 7070 /* failed to enable MSI-X */ 7071 if (bp->multi_mode) 7072 DP(NETIF_MSG_IFUP, 7073 "Multi requested but failed to " 7074 "enable MSI-X (%d), " 7075 "set number of queues to %d\n", 7076 bp->num_queues, 7077 1 + NON_ETH_CONTEXT_USE); 7078 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7079 7080 /* Try to enable MSI */ 7081 if (!(bp->flags & DISABLE_MSI_FLAG)) 7082 bnx2x_enable_msi(bp); 7083 } 7084 break; 7085 } 7086 } 7087 7088 /* must be called prioir to any HW initializations */ 7089 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) 7090 { 7091 return L2_ILT_LINES(bp); 7092 } 7093 7094 void bnx2x_ilt_set_info(struct bnx2x *bp) 7095 { 7096 struct ilt_client_info *ilt_client; 7097 struct bnx2x_ilt *ilt = BP_ILT(bp); 7098 u16 line = 0; 7099 7100 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); 7101 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); 7102 7103 /* CDU */ 7104 ilt_client = &ilt->clients[ILT_CLIENT_CDU]; 7105 ilt_client->client_num = ILT_CLIENT_CDU; 7106 ilt_client->page_size = CDU_ILT_PAGE_SZ; 7107 ilt_client->flags = ILT_CLIENT_SKIP_MEM; 7108 ilt_client->start = line; 7109 line += bnx2x_cid_ilt_lines(bp); 7110 #ifdef BCM_CNIC 7111 line += CNIC_ILT_LINES; 7112 #endif 7113 ilt_client->end = line - 1; 7114 7115 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, " 7116 "flags 0x%x, hw psz %d\n", 7117 ilt_client->start, 7118 ilt_client->end, 7119 ilt_client->page_size, 7120 ilt_client->flags, 7121 ilog2(ilt_client->page_size >> 12)); 7122 7123 /* QM */ 7124 if (QM_INIT(bp->qm_cid_count)) { 7125 ilt_client = &ilt->clients[ILT_CLIENT_QM]; 7126 ilt_client->client_num = ILT_CLIENT_QM; 7127 ilt_client->page_size = QM_ILT_PAGE_SZ; 7128 ilt_client->flags = 0; 7129 ilt_client->start = line; 7130 7131 /* 4 bytes for each cid */ 7132 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, 7133 QM_ILT_PAGE_SZ); 7134 7135 ilt_client->end = line - 1; 7136 7137 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, " 7138 "flags 0x%x, hw psz %d\n", 7139 ilt_client->start, 7140 ilt_client->end, 7141 ilt_client->page_size, 7142 ilt_client->flags, 7143 ilog2(ilt_client->page_size >> 12)); 7144 7145 } 7146 /* SRC */ 7147 ilt_client = &ilt->clients[ILT_CLIENT_SRC]; 7148 #ifdef BCM_CNIC 7149 ilt_client->client_num = ILT_CLIENT_SRC; 7150 ilt_client->page_size = SRC_ILT_PAGE_SZ; 7151 ilt_client->flags = 0; 7152 ilt_client->start = line; 7153 line += SRC_ILT_LINES; 7154 ilt_client->end = line - 1; 7155 7156 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, " 7157 "flags 0x%x, hw psz %d\n", 7158 ilt_client->start, 7159 ilt_client->end, 7160 ilt_client->page_size, 7161 ilt_client->flags, 7162 ilog2(ilt_client->page_size >> 12)); 7163 7164 #else 7165 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); 7166 #endif 7167 7168 /* TM */ 7169 ilt_client = &ilt->clients[ILT_CLIENT_TM]; 7170 #ifdef BCM_CNIC 7171 ilt_client->client_num = ILT_CLIENT_TM; 7172 ilt_client->page_size = TM_ILT_PAGE_SZ; 7173 ilt_client->flags = 0; 7174 ilt_client->start = line; 7175 line += TM_ILT_LINES; 7176 ilt_client->end = line - 1; 7177 7178 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, " 7179 "flags 0x%x, hw psz %d\n", 7180 ilt_client->start, 7181 ilt_client->end, 7182 ilt_client->page_size, 7183 ilt_client->flags, 7184 ilog2(ilt_client->page_size >> 12)); 7185 7186 #else 7187 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); 7188 #endif 7189 BUG_ON(line > ILT_MAX_LINES); 7190 } 7191 7192 /** 7193 * bnx2x_pf_q_prep_init - prepare INIT transition parameters 7194 * 7195 * @bp: driver handle 7196 * @fp: pointer to fastpath 7197 * @init_params: pointer to parameters structure 7198 * 7199 * parameters configured: 7200 * - HC configuration 7201 * - Queue's CDU context 7202 */ 7203 static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp, 7204 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) 7205 { 7206 7207 u8 cos; 7208 /* FCoE Queue uses Default SB, thus has no HC capabilities */ 7209 if (!IS_FCOE_FP(fp)) { 7210 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); 7211 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); 7212 7213 /* If HC is supporterd, enable host coalescing in the transition 7214 * to INIT state. 7215 */ 7216 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); 7217 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); 7218 7219 /* HC rate */ 7220 init_params->rx.hc_rate = bp->rx_ticks ? 7221 (1000000 / bp->rx_ticks) : 0; 7222 init_params->tx.hc_rate = bp->tx_ticks ? 7223 (1000000 / bp->tx_ticks) : 0; 7224 7225 /* FW SB ID */ 7226 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = 7227 fp->fw_sb_id; 7228 7229 /* 7230 * CQ index among the SB indices: FCoE clients uses the default 7231 * SB, therefore it's different. 7232 */ 7233 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 7234 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; 7235 } 7236 7237 /* set maximum number of COSs supported by this queue */ 7238 init_params->max_cos = fp->max_cos; 7239 7240 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d\n", 7241 fp->index, init_params->max_cos); 7242 7243 /* set the context pointers queue object */ 7244 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) 7245 init_params->cxts[cos] = 7246 &bp->context.vcxt[fp->txdata[cos].cid].eth; 7247 } 7248 7249 int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, 7250 struct bnx2x_queue_state_params *q_params, 7251 struct bnx2x_queue_setup_tx_only_params *tx_only_params, 7252 int tx_index, bool leading) 7253 { 7254 memset(tx_only_params, 0, sizeof(*tx_only_params)); 7255 7256 /* Set the command */ 7257 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 7258 7259 /* Set tx-only QUEUE flags: don't zero statistics */ 7260 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); 7261 7262 /* choose the index of the cid to send the slow path on */ 7263 tx_only_params->cid_index = tx_index; 7264 7265 /* Set general TX_ONLY_SETUP parameters */ 7266 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); 7267 7268 /* Set Tx TX_ONLY_SETUP parameters */ 7269 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); 7270 7271 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:" 7272 "cos %d, primary cid %d, cid %d, " 7273 "client id %d, sp-client id %d, flags %lx\n", 7274 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], 7275 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, 7276 tx_only_params->gen_params.spcl_id, tx_only_params->flags); 7277 7278 /* send the ramrod */ 7279 return bnx2x_queue_state_change(bp, q_params); 7280 } 7281 7282 7283 /** 7284 * bnx2x_setup_queue - setup queue 7285 * 7286 * @bp: driver handle 7287 * @fp: pointer to fastpath 7288 * @leading: is leading 7289 * 7290 * This function performs 2 steps in a Queue state machine 7291 * actually: 1) RESET->INIT 2) INIT->SETUP 7292 */ 7293 7294 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 7295 bool leading) 7296 { 7297 struct bnx2x_queue_state_params q_params = {0}; 7298 struct bnx2x_queue_setup_params *setup_params = 7299 &q_params.params.setup; 7300 struct bnx2x_queue_setup_tx_only_params *tx_only_params = 7301 &q_params.params.tx_only; 7302 int rc; 7303 u8 tx_index; 7304 7305 DP(BNX2X_MSG_SP, "setting up queue %d\n", fp->index); 7306 7307 /* reset IGU state skip FCoE L2 queue */ 7308 if (!IS_FCOE_FP(fp)) 7309 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, 7310 IGU_INT_ENABLE, 0); 7311 7312 q_params.q_obj = &fp->q_obj; 7313 /* We want to wait for completion in this context */ 7314 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 7315 7316 /* Prepare the INIT parameters */ 7317 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); 7318 7319 /* Set the command */ 7320 q_params.cmd = BNX2X_Q_CMD_INIT; 7321 7322 /* Change the state to INIT */ 7323 rc = bnx2x_queue_state_change(bp, &q_params); 7324 if (rc) { 7325 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); 7326 return rc; 7327 } 7328 7329 DP(BNX2X_MSG_SP, "init complete\n"); 7330 7331 7332 /* Now move the Queue to the SETUP state... */ 7333 memset(setup_params, 0, sizeof(*setup_params)); 7334 7335 /* Set QUEUE flags */ 7336 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); 7337 7338 /* Set general SETUP parameters */ 7339 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, 7340 FIRST_TX_COS_INDEX); 7341 7342 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, 7343 &setup_params->rxq_params); 7344 7345 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, 7346 FIRST_TX_COS_INDEX); 7347 7348 /* Set the command */ 7349 q_params.cmd = BNX2X_Q_CMD_SETUP; 7350 7351 /* Change the state to SETUP */ 7352 rc = bnx2x_queue_state_change(bp, &q_params); 7353 if (rc) { 7354 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); 7355 return rc; 7356 } 7357 7358 /* loop through the relevant tx-only indices */ 7359 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 7360 tx_index < fp->max_cos; 7361 tx_index++) { 7362 7363 /* prepare and send tx-only ramrod*/ 7364 rc = bnx2x_setup_tx_only(bp, fp, &q_params, 7365 tx_only_params, tx_index, leading); 7366 if (rc) { 7367 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", 7368 fp->index, tx_index); 7369 return rc; 7370 } 7371 } 7372 7373 return rc; 7374 } 7375 7376 static int bnx2x_stop_queue(struct bnx2x *bp, int index) 7377 { 7378 struct bnx2x_fastpath *fp = &bp->fp[index]; 7379 struct bnx2x_fp_txdata *txdata; 7380 struct bnx2x_queue_state_params q_params = {0}; 7381 int rc, tx_index; 7382 7383 DP(BNX2X_MSG_SP, "stopping queue %d cid %d\n", index, fp->cid); 7384 7385 q_params.q_obj = &fp->q_obj; 7386 /* We want to wait for completion in this context */ 7387 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 7388 7389 7390 /* close tx-only connections */ 7391 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 7392 tx_index < fp->max_cos; 7393 tx_index++){ 7394 7395 /* ascertain this is a normal queue*/ 7396 txdata = &fp->txdata[tx_index]; 7397 7398 DP(BNX2X_MSG_SP, "stopping tx-only queue %d\n", 7399 txdata->txq_index); 7400 7401 /* send halt terminate on tx-only connection */ 7402 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 7403 memset(&q_params.params.terminate, 0, 7404 sizeof(q_params.params.terminate)); 7405 q_params.params.terminate.cid_index = tx_index; 7406 7407 rc = bnx2x_queue_state_change(bp, &q_params); 7408 if (rc) 7409 return rc; 7410 7411 /* send halt terminate on tx-only connection */ 7412 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 7413 memset(&q_params.params.cfc_del, 0, 7414 sizeof(q_params.params.cfc_del)); 7415 q_params.params.cfc_del.cid_index = tx_index; 7416 rc = bnx2x_queue_state_change(bp, &q_params); 7417 if (rc) 7418 return rc; 7419 } 7420 /* Stop the primary connection: */ 7421 /* ...halt the connection */ 7422 q_params.cmd = BNX2X_Q_CMD_HALT; 7423 rc = bnx2x_queue_state_change(bp, &q_params); 7424 if (rc) 7425 return rc; 7426 7427 /* ...terminate the connection */ 7428 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 7429 memset(&q_params.params.terminate, 0, 7430 sizeof(q_params.params.terminate)); 7431 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; 7432 rc = bnx2x_queue_state_change(bp, &q_params); 7433 if (rc) 7434 return rc; 7435 /* ...delete cfc entry */ 7436 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 7437 memset(&q_params.params.cfc_del, 0, 7438 sizeof(q_params.params.cfc_del)); 7439 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; 7440 return bnx2x_queue_state_change(bp, &q_params); 7441 } 7442 7443 7444 static void bnx2x_reset_func(struct bnx2x *bp) 7445 { 7446 int port = BP_PORT(bp); 7447 int func = BP_FUNC(bp); 7448 int i; 7449 7450 /* Disable the function in the FW */ 7451 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); 7452 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); 7453 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); 7454 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); 7455 7456 /* FP SBs */ 7457 for_each_eth_queue(bp, i) { 7458 struct bnx2x_fastpath *fp = &bp->fp[i]; 7459 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7460 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), 7461 SB_DISABLED); 7462 } 7463 7464 #ifdef BCM_CNIC 7465 /* CNIC SB */ 7466 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7467 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)), 7468 SB_DISABLED); 7469 #endif 7470 /* SP SB */ 7471 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7472 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), 7473 SB_DISABLED); 7474 7475 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) 7476 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 7477 0); 7478 7479 /* Configure IGU */ 7480 if (bp->common.int_block == INT_BLOCK_HC) { 7481 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 7482 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 7483 } else { 7484 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 7485 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 7486 } 7487 7488 #ifdef BCM_CNIC 7489 /* Disable Timer scan */ 7490 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); 7491 /* 7492 * Wait for at least 10ms and up to 2 second for the timers scan to 7493 * complete 7494 */ 7495 for (i = 0; i < 200; i++) { 7496 msleep(10); 7497 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) 7498 break; 7499 } 7500 #endif 7501 /* Clear ILT */ 7502 bnx2x_clear_func_ilt(bp, func); 7503 7504 /* Timers workaround bug for E2: if this is vnic-3, 7505 * we need to set the entire ilt range for this timers. 7506 */ 7507 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { 7508 struct ilt_client_info ilt_cli; 7509 /* use dummy TM client */ 7510 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 7511 ilt_cli.start = 0; 7512 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 7513 ilt_cli.client_num = ILT_CLIENT_TM; 7514 7515 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); 7516 } 7517 7518 /* this assumes that reset_port() called before reset_func()*/ 7519 if (!CHIP_IS_E1x(bp)) 7520 bnx2x_pf_disable(bp); 7521 7522 bp->dmae_ready = 0; 7523 } 7524 7525 static void bnx2x_reset_port(struct bnx2x *bp) 7526 { 7527 int port = BP_PORT(bp); 7528 u32 val; 7529 7530 /* Reset physical Link */ 7531 bnx2x__link_reset(bp); 7532 7533 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 7534 7535 /* Do not rcv packets to BRB */ 7536 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); 7537 /* Do not direct rcv packets that are not for MCP to the BRB */ 7538 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 7539 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 7540 7541 /* Configure AEU */ 7542 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); 7543 7544 msleep(100); 7545 /* Check for BRB port occupancy */ 7546 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); 7547 if (val) 7548 DP(NETIF_MSG_IFDOWN, 7549 "BRB1 is not empty %d blocks are occupied\n", val); 7550 7551 /* TODO: Close Doorbell port? */ 7552 } 7553 7554 static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) 7555 { 7556 struct bnx2x_func_state_params func_params = {0}; 7557 7558 /* Prepare parameters for function state transitions */ 7559 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7560 7561 func_params.f_obj = &bp->func_obj; 7562 func_params.cmd = BNX2X_F_CMD_HW_RESET; 7563 7564 func_params.params.hw_init.load_phase = load_code; 7565 7566 return bnx2x_func_state_change(bp, &func_params); 7567 } 7568 7569 static inline int bnx2x_func_stop(struct bnx2x *bp) 7570 { 7571 struct bnx2x_func_state_params func_params = {0}; 7572 int rc; 7573 7574 /* Prepare parameters for function state transitions */ 7575 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7576 func_params.f_obj = &bp->func_obj; 7577 func_params.cmd = BNX2X_F_CMD_STOP; 7578 7579 /* 7580 * Try to stop the function the 'good way'. If fails (in case 7581 * of a parity error during bnx2x_chip_cleanup()) and we are 7582 * not in a debug mode, perform a state transaction in order to 7583 * enable further HW_RESET transaction. 7584 */ 7585 rc = bnx2x_func_state_change(bp, &func_params); 7586 if (rc) { 7587 #ifdef BNX2X_STOP_ON_ERROR 7588 return rc; 7589 #else 7590 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry " 7591 "transaction\n"); 7592 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); 7593 return bnx2x_func_state_change(bp, &func_params); 7594 #endif 7595 } 7596 7597 return 0; 7598 } 7599 7600 /** 7601 * bnx2x_send_unload_req - request unload mode from the MCP. 7602 * 7603 * @bp: driver handle 7604 * @unload_mode: requested function's unload mode 7605 * 7606 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 7607 */ 7608 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) 7609 { 7610 u32 reset_code = 0; 7611 int port = BP_PORT(bp); 7612 7613 /* Select the UNLOAD request mode */ 7614 if (unload_mode == UNLOAD_NORMAL) 7615 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7616 7617 else if (bp->flags & NO_WOL_FLAG) 7618 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; 7619 7620 else if (bp->wol) { 7621 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 7622 u8 *mac_addr = bp->dev->dev_addr; 7623 u32 val; 7624 u16 pmc; 7625 7626 /* The mac address is written to entries 1-4 to 7627 * preserve entry 0 which is used by the PMF 7628 */ 7629 u8 entry = (BP_VN(bp) + 1)*8; 7630 7631 val = (mac_addr[0] << 8) | mac_addr[1]; 7632 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); 7633 7634 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 7635 (mac_addr[4] << 8) | mac_addr[5]; 7636 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); 7637 7638 /* Enable the PME and clear the status */ 7639 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc); 7640 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; 7641 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc); 7642 7643 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; 7644 7645 } else 7646 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7647 7648 /* Send the request to the MCP */ 7649 if (!BP_NOMCP(bp)) 7650 reset_code = bnx2x_fw_command(bp, reset_code, 0); 7651 else { 7652 int path = BP_PATH(bp); 7653 7654 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] " 7655 "%d, %d, %d\n", 7656 path, load_count[path][0], load_count[path][1], 7657 load_count[path][2]); 7658 load_count[path][0]--; 7659 load_count[path][1 + port]--; 7660 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] " 7661 "%d, %d, %d\n", 7662 path, load_count[path][0], load_count[path][1], 7663 load_count[path][2]); 7664 if (load_count[path][0] == 0) 7665 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; 7666 else if (load_count[path][1 + port] == 0) 7667 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; 7668 else 7669 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; 7670 } 7671 7672 return reset_code; 7673 } 7674 7675 /** 7676 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 7677 * 7678 * @bp: driver handle 7679 */ 7680 void bnx2x_send_unload_done(struct bnx2x *bp) 7681 { 7682 /* Report UNLOAD_DONE to MCP */ 7683 if (!BP_NOMCP(bp)) 7684 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 7685 } 7686 7687 static inline int bnx2x_func_wait_started(struct bnx2x *bp) 7688 { 7689 int tout = 50; 7690 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 7691 7692 if (!bp->port.pmf) 7693 return 0; 7694 7695 /* 7696 * (assumption: No Attention from MCP at this stage) 7697 * PMF probably in the middle of TXdisable/enable transaction 7698 * 1. Sync IRS for default SB 7699 * 2. Sync SP queue - this guarantes us that attention handling started 7700 * 3. Wait, that TXdisable/enable transaction completes 7701 * 7702 * 1+2 guranty that if DCBx attention was scheduled it already changed 7703 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy 7704 * received complettion for the transaction the state is TX_STOPPED. 7705 * State will return to STARTED after completion of TX_STOPPED-->STARTED 7706 * transaction. 7707 */ 7708 7709 /* make sure default SB ISR is done */ 7710 if (msix) 7711 synchronize_irq(bp->msix_table[0].vector); 7712 else 7713 synchronize_irq(bp->pdev->irq); 7714 7715 flush_workqueue(bnx2x_wq); 7716 7717 while (bnx2x_func_get_state(bp, &bp->func_obj) != 7718 BNX2X_F_STATE_STARTED && tout--) 7719 msleep(20); 7720 7721 if (bnx2x_func_get_state(bp, &bp->func_obj) != 7722 BNX2X_F_STATE_STARTED) { 7723 #ifdef BNX2X_STOP_ON_ERROR 7724 return -EBUSY; 7725 #else 7726 /* 7727 * Failed to complete the transaction in a "good way" 7728 * Force both transactions with CLR bit 7729 */ 7730 struct bnx2x_func_state_params func_params = {0}; 7731 7732 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! " 7733 "Forcing STARTED-->TX_ST0PPED-->STARTED\n"); 7734 7735 func_params.f_obj = &bp->func_obj; 7736 __set_bit(RAMROD_DRV_CLR_ONLY, 7737 &func_params.ramrod_flags); 7738 7739 /* STARTED-->TX_ST0PPED */ 7740 func_params.cmd = BNX2X_F_CMD_TX_STOP; 7741 bnx2x_func_state_change(bp, &func_params); 7742 7743 /* TX_ST0PPED-->STARTED */ 7744 func_params.cmd = BNX2X_F_CMD_TX_START; 7745 return bnx2x_func_state_change(bp, &func_params); 7746 #endif 7747 } 7748 7749 return 0; 7750 } 7751 7752 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode) 7753 { 7754 int port = BP_PORT(bp); 7755 int i, rc = 0; 7756 u8 cos; 7757 struct bnx2x_mcast_ramrod_params rparam = {0}; 7758 u32 reset_code; 7759 7760 /* Wait until tx fastpath tasks complete */ 7761 for_each_tx_queue(bp, i) { 7762 struct bnx2x_fastpath *fp = &bp->fp[i]; 7763 7764 for_each_cos_in_tx_queue(fp, cos) 7765 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]); 7766 #ifdef BNX2X_STOP_ON_ERROR 7767 if (rc) 7768 return; 7769 #endif 7770 } 7771 7772 /* Give HW time to discard old tx messages */ 7773 usleep_range(1000, 1000); 7774 7775 /* Clean all ETH MACs */ 7776 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false); 7777 if (rc < 0) 7778 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); 7779 7780 /* Clean up UC list */ 7781 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC, 7782 true); 7783 if (rc < 0) 7784 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: " 7785 "%d\n", rc); 7786 7787 /* Disable LLH */ 7788 if (!CHIP_IS_E1(bp)) 7789 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 7790 7791 /* Set "drop all" (stop Rx). 7792 * We need to take a netif_addr_lock() here in order to prevent 7793 * a race between the completion code and this code. 7794 */ 7795 netif_addr_lock_bh(bp->dev); 7796 /* Schedule the rx_mode command */ 7797 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 7798 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 7799 else 7800 bnx2x_set_storm_rx_mode(bp); 7801 7802 /* Cleanup multicast configuration */ 7803 rparam.mcast_obj = &bp->mcast_obj; 7804 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 7805 if (rc < 0) 7806 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); 7807 7808 netif_addr_unlock_bh(bp->dev); 7809 7810 7811 7812 /* 7813 * Send the UNLOAD_REQUEST to the MCP. This will return if 7814 * this function should perform FUNC, PORT or COMMON HW 7815 * reset. 7816 */ 7817 reset_code = bnx2x_send_unload_req(bp, unload_mode); 7818 7819 /* 7820 * (assumption: No Attention from MCP at this stage) 7821 * PMF probably in the middle of TXdisable/enable transaction 7822 */ 7823 rc = bnx2x_func_wait_started(bp); 7824 if (rc) { 7825 BNX2X_ERR("bnx2x_func_wait_started failed\n"); 7826 #ifdef BNX2X_STOP_ON_ERROR 7827 return; 7828 #endif 7829 } 7830 7831 /* Close multi and leading connections 7832 * Completions for ramrods are collected in a synchronous way 7833 */ 7834 for_each_queue(bp, i) 7835 if (bnx2x_stop_queue(bp, i)) 7836 #ifdef BNX2X_STOP_ON_ERROR 7837 return; 7838 #else 7839 goto unload_error; 7840 #endif 7841 /* If SP settings didn't get completed so far - something 7842 * very wrong has happen. 7843 */ 7844 if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) 7845 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); 7846 7847 #ifndef BNX2X_STOP_ON_ERROR 7848 unload_error: 7849 #endif 7850 rc = bnx2x_func_stop(bp); 7851 if (rc) { 7852 BNX2X_ERR("Function stop failed!\n"); 7853 #ifdef BNX2X_STOP_ON_ERROR 7854 return; 7855 #endif 7856 } 7857 7858 /* Disable HW interrupts, NAPI */ 7859 bnx2x_netif_stop(bp, 1); 7860 7861 /* Release IRQs */ 7862 bnx2x_free_irq(bp); 7863 7864 /* Reset the chip */ 7865 rc = bnx2x_reset_hw(bp, reset_code); 7866 if (rc) 7867 BNX2X_ERR("HW_RESET failed\n"); 7868 7869 7870 /* Report UNLOAD_DONE to MCP */ 7871 bnx2x_send_unload_done(bp); 7872 } 7873 7874 void bnx2x_disable_close_the_gate(struct bnx2x *bp) 7875 { 7876 u32 val; 7877 7878 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n"); 7879 7880 if (CHIP_IS_E1(bp)) { 7881 int port = BP_PORT(bp); 7882 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 7883 MISC_REG_AEU_MASK_ATTN_FUNC_0; 7884 7885 val = REG_RD(bp, addr); 7886 val &= ~(0x300); 7887 REG_WR(bp, addr, val); 7888 } else { 7889 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); 7890 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | 7891 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); 7892 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); 7893 } 7894 } 7895 7896 /* Close gates #2, #3 and #4: */ 7897 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) 7898 { 7899 u32 val; 7900 7901 /* Gates #2 and #4a are closed/opened for "not E1" only */ 7902 if (!CHIP_IS_E1(bp)) { 7903 /* #4 */ 7904 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); 7905 /* #2 */ 7906 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); 7907 } 7908 7909 /* #3 */ 7910 if (CHIP_IS_E1x(bp)) { 7911 /* Prevent interrupts from HC on both ports */ 7912 val = REG_RD(bp, HC_REG_CONFIG_1); 7913 REG_WR(bp, HC_REG_CONFIG_1, 7914 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : 7915 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); 7916 7917 val = REG_RD(bp, HC_REG_CONFIG_0); 7918 REG_WR(bp, HC_REG_CONFIG_0, 7919 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : 7920 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); 7921 } else { 7922 /* Prevent incomming interrupts in IGU */ 7923 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 7924 7925 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, 7926 (!close) ? 7927 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : 7928 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); 7929 } 7930 7931 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n", 7932 close ? "closing" : "opening"); 7933 mmiowb(); 7934 } 7935 7936 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ 7937 7938 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) 7939 { 7940 /* Do some magic... */ 7941 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 7942 *magic_val = val & SHARED_MF_CLP_MAGIC; 7943 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); 7944 } 7945 7946 /** 7947 * bnx2x_clp_reset_done - restore the value of the `magic' bit. 7948 * 7949 * @bp: driver handle 7950 * @magic_val: old value of the `magic' bit. 7951 */ 7952 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) 7953 { 7954 /* Restore the `magic' bit value... */ 7955 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 7956 MF_CFG_WR(bp, shared_mf_config.clp_mb, 7957 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); 7958 } 7959 7960 /** 7961 * bnx2x_reset_mcp_prep - prepare for MCP reset. 7962 * 7963 * @bp: driver handle 7964 * @magic_val: old value of 'magic' bit. 7965 * 7966 * Takes care of CLP configurations. 7967 */ 7968 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) 7969 { 7970 u32 shmem; 7971 u32 validity_offset; 7972 7973 DP(NETIF_MSG_HW, "Starting\n"); 7974 7975 /* Set `magic' bit in order to save MF config */ 7976 if (!CHIP_IS_E1(bp)) 7977 bnx2x_clp_reset_prep(bp, magic_val); 7978 7979 /* Get shmem offset */ 7980 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 7981 validity_offset = offsetof(struct shmem_region, validity_map[0]); 7982 7983 /* Clear validity map flags */ 7984 if (shmem > 0) 7985 REG_WR(bp, shmem + validity_offset, 0); 7986 } 7987 7988 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ 7989 #define MCP_ONE_TIMEOUT 100 /* 100 ms */ 7990 7991 /** 7992 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT 7993 * 7994 * @bp: driver handle 7995 */ 7996 static inline void bnx2x_mcp_wait_one(struct bnx2x *bp) 7997 { 7998 /* special handling for emulation and FPGA, 7999 wait 10 times longer */ 8000 if (CHIP_REV_IS_SLOW(bp)) 8001 msleep(MCP_ONE_TIMEOUT*10); 8002 else 8003 msleep(MCP_ONE_TIMEOUT); 8004 } 8005 8006 /* 8007 * initializes bp->common.shmem_base and waits for validity signature to appear 8008 */ 8009 static int bnx2x_init_shmem(struct bnx2x *bp) 8010 { 8011 int cnt = 0; 8012 u32 val = 0; 8013 8014 do { 8015 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 8016 if (bp->common.shmem_base) { 8017 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 8018 if (val & SHR_MEM_VALIDITY_MB) 8019 return 0; 8020 } 8021 8022 bnx2x_mcp_wait_one(bp); 8023 8024 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); 8025 8026 BNX2X_ERR("BAD MCP validity signature\n"); 8027 8028 return -ENODEV; 8029 } 8030 8031 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) 8032 { 8033 int rc = bnx2x_init_shmem(bp); 8034 8035 /* Restore the `magic' bit value */ 8036 if (!CHIP_IS_E1(bp)) 8037 bnx2x_clp_reset_done(bp, magic_val); 8038 8039 return rc; 8040 } 8041 8042 static void bnx2x_pxp_prep(struct bnx2x *bp) 8043 { 8044 if (!CHIP_IS_E1(bp)) { 8045 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); 8046 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); 8047 mmiowb(); 8048 } 8049 } 8050 8051 /* 8052 * Reset the whole chip except for: 8053 * - PCIE core 8054 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by 8055 * one reset bit) 8056 * - IGU 8057 * - MISC (including AEU) 8058 * - GRC 8059 * - RBCN, RBCP 8060 */ 8061 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) 8062 { 8063 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; 8064 u32 global_bits2, stay_reset2; 8065 8066 /* 8067 * Bits that have to be set in reset_mask2 if we want to reset 'global' 8068 * (per chip) blocks. 8069 */ 8070 global_bits2 = 8071 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | 8072 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; 8073 8074 /* Don't reset the following blocks */ 8075 not_reset_mask1 = 8076 MISC_REGISTERS_RESET_REG_1_RST_HC | 8077 MISC_REGISTERS_RESET_REG_1_RST_PXPV | 8078 MISC_REGISTERS_RESET_REG_1_RST_PXP; 8079 8080 not_reset_mask2 = 8081 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | 8082 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | 8083 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | 8084 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | 8085 MISC_REGISTERS_RESET_REG_2_RST_RBCN | 8086 MISC_REGISTERS_RESET_REG_2_RST_GRC | 8087 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | 8088 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | 8089 MISC_REGISTERS_RESET_REG_2_RST_ATC | 8090 MISC_REGISTERS_RESET_REG_2_PGLC; 8091 8092 /* 8093 * Keep the following blocks in reset: 8094 * - all xxMACs are handled by the bnx2x_link code. 8095 */ 8096 stay_reset2 = 8097 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | 8098 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | 8099 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | 8100 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | 8101 MISC_REGISTERS_RESET_REG_2_UMAC0 | 8102 MISC_REGISTERS_RESET_REG_2_UMAC1 | 8103 MISC_REGISTERS_RESET_REG_2_XMAC | 8104 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; 8105 8106 /* Full reset masks according to the chip */ 8107 reset_mask1 = 0xffffffff; 8108 8109 if (CHIP_IS_E1(bp)) 8110 reset_mask2 = 0xffff; 8111 else if (CHIP_IS_E1H(bp)) 8112 reset_mask2 = 0x1ffff; 8113 else if (CHIP_IS_E2(bp)) 8114 reset_mask2 = 0xfffff; 8115 else /* CHIP_IS_E3 */ 8116 reset_mask2 = 0x3ffffff; 8117 8118 /* Don't reset global blocks unless we need to */ 8119 if (!global) 8120 reset_mask2 &= ~global_bits2; 8121 8122 /* 8123 * In case of attention in the QM, we need to reset PXP 8124 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM 8125 * because otherwise QM reset would release 'close the gates' shortly 8126 * before resetting the PXP, then the PSWRQ would send a write 8127 * request to PGLUE. Then when PXP is reset, PGLUE would try to 8128 * read the payload data from PSWWR, but PSWWR would not 8129 * respond. The write queue in PGLUE would stuck, dmae commands 8130 * would not return. Therefore it's important to reset the second 8131 * reset register (containing the 8132 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the 8133 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM 8134 * bit). 8135 */ 8136 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 8137 reset_mask2 & (~not_reset_mask2)); 8138 8139 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 8140 reset_mask1 & (~not_reset_mask1)); 8141 8142 barrier(); 8143 mmiowb(); 8144 8145 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 8146 reset_mask2 & (~stay_reset2)); 8147 8148 barrier(); 8149 mmiowb(); 8150 8151 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); 8152 mmiowb(); 8153 } 8154 8155 /** 8156 * bnx2x_er_poll_igu_vq - poll for pending writes bit. 8157 * It should get cleared in no more than 1s. 8158 * 8159 * @bp: driver handle 8160 * 8161 * It should get cleared in no more than 1s. Returns 0 if 8162 * pending writes bit gets cleared. 8163 */ 8164 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) 8165 { 8166 u32 cnt = 1000; 8167 u32 pend_bits = 0; 8168 8169 do { 8170 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); 8171 8172 if (pend_bits == 0) 8173 break; 8174 8175 usleep_range(1000, 1000); 8176 } while (cnt-- > 0); 8177 8178 if (cnt <= 0) { 8179 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", 8180 pend_bits); 8181 return -EBUSY; 8182 } 8183 8184 return 0; 8185 } 8186 8187 static int bnx2x_process_kill(struct bnx2x *bp, bool global) 8188 { 8189 int cnt = 1000; 8190 u32 val = 0; 8191 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; 8192 8193 8194 /* Empty the Tetris buffer, wait for 1s */ 8195 do { 8196 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); 8197 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); 8198 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); 8199 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); 8200 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); 8201 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && 8202 ((port_is_idle_0 & 0x1) == 0x1) && 8203 ((port_is_idle_1 & 0x1) == 0x1) && 8204 (pgl_exp_rom2 == 0xffffffff)) 8205 break; 8206 usleep_range(1000, 1000); 8207 } while (cnt-- > 0); 8208 8209 if (cnt <= 0) { 8210 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there" 8211 " are still" 8212 " outstanding read requests after 1s!\n"); 8213 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x," 8214 " port_is_idle_0=0x%08x," 8215 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", 8216 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, 8217 pgl_exp_rom2); 8218 return -EAGAIN; 8219 } 8220 8221 barrier(); 8222 8223 /* Close gates #2, #3 and #4 */ 8224 bnx2x_set_234_gates(bp, true); 8225 8226 /* Poll for IGU VQs for 57712 and newer chips */ 8227 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) 8228 return -EAGAIN; 8229 8230 8231 /* TBD: Indicate that "process kill" is in progress to MCP */ 8232 8233 /* Clear "unprepared" bit */ 8234 REG_WR(bp, MISC_REG_UNPREPARED, 0); 8235 barrier(); 8236 8237 /* Make sure all is written to the chip before the reset */ 8238 mmiowb(); 8239 8240 /* Wait for 1ms to empty GLUE and PCI-E core queues, 8241 * PSWHST, GRC and PSWRD Tetris buffer. 8242 */ 8243 usleep_range(1000, 1000); 8244 8245 /* Prepare to chip reset: */ 8246 /* MCP */ 8247 if (global) 8248 bnx2x_reset_mcp_prep(bp, &val); 8249 8250 /* PXP */ 8251 bnx2x_pxp_prep(bp); 8252 barrier(); 8253 8254 /* reset the chip */ 8255 bnx2x_process_kill_chip_reset(bp, global); 8256 barrier(); 8257 8258 /* Recover after reset: */ 8259 /* MCP */ 8260 if (global && bnx2x_reset_mcp_comp(bp, val)) 8261 return -EAGAIN; 8262 8263 /* TBD: Add resetting the NO_MCP mode DB here */ 8264 8265 /* PXP */ 8266 bnx2x_pxp_prep(bp); 8267 8268 /* Open the gates #2, #3 and #4 */ 8269 bnx2x_set_234_gates(bp, false); 8270 8271 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a 8272 * reset state, re-enable attentions. */ 8273 8274 return 0; 8275 } 8276 8277 int bnx2x_leader_reset(struct bnx2x *bp) 8278 { 8279 int rc = 0; 8280 bool global = bnx2x_reset_is_global(bp); 8281 8282 /* Try to recover after the failure */ 8283 if (bnx2x_process_kill(bp, global)) { 8284 netdev_err(bp->dev, "Something bad had happen on engine %d! " 8285 "Aii!\n", BP_PATH(bp)); 8286 rc = -EAGAIN; 8287 goto exit_leader_reset; 8288 } 8289 8290 /* 8291 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver 8292 * state. 8293 */ 8294 bnx2x_set_reset_done(bp); 8295 if (global) 8296 bnx2x_clear_reset_global(bp); 8297 8298 exit_leader_reset: 8299 bp->is_leader = 0; 8300 bnx2x_release_leader_lock(bp); 8301 smp_mb(); 8302 return rc; 8303 } 8304 8305 static inline void bnx2x_recovery_failed(struct bnx2x *bp) 8306 { 8307 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); 8308 8309 /* Disconnect this device */ 8310 netif_device_detach(bp->dev); 8311 8312 /* 8313 * Block ifup for all function on this engine until "process kill" 8314 * or power cycle. 8315 */ 8316 bnx2x_set_reset_in_progress(bp); 8317 8318 /* Shut down the power */ 8319 bnx2x_set_power_state(bp, PCI_D3hot); 8320 8321 bp->recovery_state = BNX2X_RECOVERY_FAILED; 8322 8323 smp_mb(); 8324 } 8325 8326 /* 8327 * Assumption: runs under rtnl lock. This together with the fact 8328 * that it's called only from bnx2x_sp_rtnl() ensure that it 8329 * will never be called when netif_running(bp->dev) is false. 8330 */ 8331 static void bnx2x_parity_recover(struct bnx2x *bp) 8332 { 8333 bool global = false; 8334 8335 DP(NETIF_MSG_HW, "Handling parity\n"); 8336 while (1) { 8337 switch (bp->recovery_state) { 8338 case BNX2X_RECOVERY_INIT: 8339 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); 8340 bnx2x_chk_parity_attn(bp, &global, false); 8341 8342 /* Try to get a LEADER_LOCK HW lock */ 8343 if (bnx2x_trylock_leader_lock(bp)) { 8344 bnx2x_set_reset_in_progress(bp); 8345 /* 8346 * Check if there is a global attention and if 8347 * there was a global attention, set the global 8348 * reset bit. 8349 */ 8350 8351 if (global) 8352 bnx2x_set_reset_global(bp); 8353 8354 bp->is_leader = 1; 8355 } 8356 8357 /* Stop the driver */ 8358 /* If interface has been removed - break */ 8359 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY)) 8360 return; 8361 8362 bp->recovery_state = BNX2X_RECOVERY_WAIT; 8363 8364 /* 8365 * Reset MCP command sequence number and MCP mail box 8366 * sequence as we are going to reset the MCP. 8367 */ 8368 if (global) { 8369 bp->fw_seq = 0; 8370 bp->fw_drv_pulse_wr_seq = 0; 8371 } 8372 8373 /* Ensure "is_leader", MCP command sequence and 8374 * "recovery_state" update values are seen on other 8375 * CPUs. 8376 */ 8377 smp_mb(); 8378 break; 8379 8380 case BNX2X_RECOVERY_WAIT: 8381 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); 8382 if (bp->is_leader) { 8383 int other_engine = BP_PATH(bp) ? 0 : 1; 8384 u32 other_load_counter = 8385 bnx2x_get_load_cnt(bp, other_engine); 8386 u32 load_counter = 8387 bnx2x_get_load_cnt(bp, BP_PATH(bp)); 8388 global = bnx2x_reset_is_global(bp); 8389 8390 /* 8391 * In case of a parity in a global block, let 8392 * the first leader that performs a 8393 * leader_reset() reset the global blocks in 8394 * order to clear global attentions. Otherwise 8395 * the the gates will remain closed for that 8396 * engine. 8397 */ 8398 if (load_counter || 8399 (global && other_load_counter)) { 8400 /* Wait until all other functions get 8401 * down. 8402 */ 8403 schedule_delayed_work(&bp->sp_rtnl_task, 8404 HZ/10); 8405 return; 8406 } else { 8407 /* If all other functions got down - 8408 * try to bring the chip back to 8409 * normal. In any case it's an exit 8410 * point for a leader. 8411 */ 8412 if (bnx2x_leader_reset(bp)) { 8413 bnx2x_recovery_failed(bp); 8414 return; 8415 } 8416 8417 /* If we are here, means that the 8418 * leader has succeeded and doesn't 8419 * want to be a leader any more. Try 8420 * to continue as a none-leader. 8421 */ 8422 break; 8423 } 8424 } else { /* non-leader */ 8425 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { 8426 /* Try to get a LEADER_LOCK HW lock as 8427 * long as a former leader may have 8428 * been unloaded by the user or 8429 * released a leadership by another 8430 * reason. 8431 */ 8432 if (bnx2x_trylock_leader_lock(bp)) { 8433 /* I'm a leader now! Restart a 8434 * switch case. 8435 */ 8436 bp->is_leader = 1; 8437 break; 8438 } 8439 8440 schedule_delayed_work(&bp->sp_rtnl_task, 8441 HZ/10); 8442 return; 8443 8444 } else { 8445 /* 8446 * If there was a global attention, wait 8447 * for it to be cleared. 8448 */ 8449 if (bnx2x_reset_is_global(bp)) { 8450 schedule_delayed_work( 8451 &bp->sp_rtnl_task, 8452 HZ/10); 8453 return; 8454 } 8455 8456 if (bnx2x_nic_load(bp, LOAD_NORMAL)) 8457 bnx2x_recovery_failed(bp); 8458 else { 8459 bp->recovery_state = 8460 BNX2X_RECOVERY_DONE; 8461 smp_mb(); 8462 } 8463 8464 return; 8465 } 8466 } 8467 default: 8468 return; 8469 } 8470 } 8471 } 8472 8473 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is 8474 * scheduled on a general queue in order to prevent a dead lock. 8475 */ 8476 static void bnx2x_sp_rtnl_task(struct work_struct *work) 8477 { 8478 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); 8479 8480 rtnl_lock(); 8481 8482 if (!netif_running(bp->dev)) 8483 goto sp_rtnl_exit; 8484 8485 /* if stop on error is defined no recovery flows should be executed */ 8486 #ifdef BNX2X_STOP_ON_ERROR 8487 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined " 8488 "so reset not done to allow debug dump,\n" 8489 "you will need to reboot when done\n"); 8490 goto sp_rtnl_not_reset; 8491 #endif 8492 8493 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { 8494 /* 8495 * Clear all pending SP commands as we are going to reset the 8496 * function anyway. 8497 */ 8498 bp->sp_rtnl_state = 0; 8499 smp_mb(); 8500 8501 bnx2x_parity_recover(bp); 8502 8503 goto sp_rtnl_exit; 8504 } 8505 8506 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { 8507 /* 8508 * Clear all pending SP commands as we are going to reset the 8509 * function anyway. 8510 */ 8511 bp->sp_rtnl_state = 0; 8512 smp_mb(); 8513 8514 bnx2x_nic_unload(bp, UNLOAD_NORMAL); 8515 bnx2x_nic_load(bp, LOAD_NORMAL); 8516 8517 goto sp_rtnl_exit; 8518 } 8519 #ifdef BNX2X_STOP_ON_ERROR 8520 sp_rtnl_not_reset: 8521 #endif 8522 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) 8523 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); 8524 8525 sp_rtnl_exit: 8526 rtnl_unlock(); 8527 } 8528 8529 /* end of nic load/unload */ 8530 8531 static void bnx2x_period_task(struct work_struct *work) 8532 { 8533 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); 8534 8535 if (!netif_running(bp->dev)) 8536 goto period_task_exit; 8537 8538 if (CHIP_REV_IS_SLOW(bp)) { 8539 BNX2X_ERR("period task called on emulation, ignoring\n"); 8540 goto period_task_exit; 8541 } 8542 8543 bnx2x_acquire_phy_lock(bp); 8544 /* 8545 * The barrier is needed to ensure the ordering between the writing to 8546 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and 8547 * the reading here. 8548 */ 8549 smp_mb(); 8550 if (bp->port.pmf) { 8551 bnx2x_period_func(&bp->link_params, &bp->link_vars); 8552 8553 /* Re-queue task in 1 sec */ 8554 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); 8555 } 8556 8557 bnx2x_release_phy_lock(bp); 8558 period_task_exit: 8559 return; 8560 } 8561 8562 /* 8563 * Init service functions 8564 */ 8565 8566 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) 8567 { 8568 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; 8569 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; 8570 return base + (BP_ABS_FUNC(bp)) * stride; 8571 } 8572 8573 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp) 8574 { 8575 u32 reg = bnx2x_get_pretend_reg(bp); 8576 8577 /* Flush all outstanding writes */ 8578 mmiowb(); 8579 8580 /* Pretend to be function 0 */ 8581 REG_WR(bp, reg, 0); 8582 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */ 8583 8584 /* From now we are in the "like-E1" mode */ 8585 bnx2x_int_disable(bp); 8586 8587 /* Flush all outstanding writes */ 8588 mmiowb(); 8589 8590 /* Restore the original function */ 8591 REG_WR(bp, reg, BP_ABS_FUNC(bp)); 8592 REG_RD(bp, reg); 8593 } 8594 8595 static inline void bnx2x_undi_int_disable(struct bnx2x *bp) 8596 { 8597 if (CHIP_IS_E1(bp)) 8598 bnx2x_int_disable(bp); 8599 else 8600 bnx2x_undi_int_disable_e1h(bp); 8601 } 8602 8603 static void __devinit bnx2x_undi_unload(struct bnx2x *bp) 8604 { 8605 u32 val; 8606 8607 /* Check if there is any driver already loaded */ 8608 val = REG_RD(bp, MISC_REG_UNPREPARED); 8609 if (val == 0x1) { 8610 8611 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 8612 /* 8613 * Check if it is the UNDI driver 8614 * UNDI driver initializes CID offset for normal bell to 0x7 8615 */ 8616 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST); 8617 if (val == 0x7) { 8618 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8619 /* save our pf_num */ 8620 int orig_pf_num = bp->pf_num; 8621 int port; 8622 u32 swap_en, swap_val, value; 8623 8624 /* clear the UNDI indication */ 8625 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); 8626 8627 BNX2X_DEV_INFO("UNDI is active! reset device\n"); 8628 8629 /* try unload UNDI on port 0 */ 8630 bp->pf_num = 0; 8631 bp->fw_seq = 8632 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8633 DRV_MSG_SEQ_NUMBER_MASK); 8634 reset_code = bnx2x_fw_command(bp, reset_code, 0); 8635 8636 /* if UNDI is loaded on the other port */ 8637 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) { 8638 8639 /* send "DONE" for previous unload */ 8640 bnx2x_fw_command(bp, 8641 DRV_MSG_CODE_UNLOAD_DONE, 0); 8642 8643 /* unload UNDI on port 1 */ 8644 bp->pf_num = 1; 8645 bp->fw_seq = 8646 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8647 DRV_MSG_SEQ_NUMBER_MASK); 8648 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8649 8650 bnx2x_fw_command(bp, reset_code, 0); 8651 } 8652 8653 bnx2x_undi_int_disable(bp); 8654 port = BP_PORT(bp); 8655 8656 /* close input traffic and wait for it */ 8657 /* Do not rcv packets to BRB */ 8658 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK : 8659 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0); 8660 /* Do not direct rcv packets that are not for MCP to 8661 * the BRB */ 8662 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 8663 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 8664 /* clear AEU */ 8665 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8666 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0); 8667 msleep(10); 8668 8669 /* save NIG port swap info */ 8670 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 8671 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 8672 /* reset device */ 8673 REG_WR(bp, 8674 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 8675 0xd3ffffff); 8676 8677 value = 0x1400; 8678 if (CHIP_IS_E3(bp)) { 8679 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 8680 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 8681 } 8682 8683 REG_WR(bp, 8684 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 8685 value); 8686 8687 /* take the NIG out of reset and restore swap values */ 8688 REG_WR(bp, 8689 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 8690 MISC_REGISTERS_RESET_REG_1_RST_NIG); 8691 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val); 8692 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en); 8693 8694 /* send unload done to the MCP */ 8695 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 8696 8697 /* restore our func and fw_seq */ 8698 bp->pf_num = orig_pf_num; 8699 bp->fw_seq = 8700 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8701 DRV_MSG_SEQ_NUMBER_MASK); 8702 } 8703 8704 /* now it's safe to release the lock */ 8705 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 8706 } 8707 } 8708 8709 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) 8710 { 8711 u32 val, val2, val3, val4, id; 8712 u16 pmc; 8713 8714 /* Get the chip revision id and number. */ 8715 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 8716 val = REG_RD(bp, MISC_REG_CHIP_NUM); 8717 id = ((val & 0xffff) << 16); 8718 val = REG_RD(bp, MISC_REG_CHIP_REV); 8719 id |= ((val & 0xf) << 12); 8720 val = REG_RD(bp, MISC_REG_CHIP_METAL); 8721 id |= ((val & 0xff) << 4); 8722 val = REG_RD(bp, MISC_REG_BOND_ID); 8723 id |= (val & 0xf); 8724 bp->common.chip_id = id; 8725 8726 /* Set doorbell size */ 8727 bp->db_size = (1 << BNX2X_DB_SHIFT); 8728 8729 if (!CHIP_IS_E1x(bp)) { 8730 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 8731 if ((val & 1) == 0) 8732 val = REG_RD(bp, MISC_REG_PORT4MODE_EN); 8733 else 8734 val = (val >> 1) & 1; 8735 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : 8736 "2_PORT_MODE"); 8737 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : 8738 CHIP_2_PORT_MODE; 8739 8740 if (CHIP_MODE_IS_4_PORT(bp)) 8741 bp->pfid = (bp->pf_num >> 1); /* 0..3 */ 8742 else 8743 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ 8744 } else { 8745 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ 8746 bp->pfid = bp->pf_num; /* 0..7 */ 8747 } 8748 8749 bp->link_params.chip_id = bp->common.chip_id; 8750 BNX2X_DEV_INFO("chip ID is 0x%x\n", id); 8751 8752 val = (REG_RD(bp, 0x2874) & 0x55); 8753 if ((bp->common.chip_id & 0x1) || 8754 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { 8755 bp->flags |= ONE_PORT_FLAG; 8756 BNX2X_DEV_INFO("single port device\n"); 8757 } 8758 8759 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); 8760 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << 8761 (val & MCPR_NVM_CFG4_FLASH_SIZE)); 8762 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", 8763 bp->common.flash_size, bp->common.flash_size); 8764 8765 bnx2x_init_shmem(bp); 8766 8767 8768 8769 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? 8770 MISC_REG_GENERIC_CR_1 : 8771 MISC_REG_GENERIC_CR_0)); 8772 8773 bp->link_params.shmem_base = bp->common.shmem_base; 8774 bp->link_params.shmem2_base = bp->common.shmem2_base; 8775 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", 8776 bp->common.shmem_base, bp->common.shmem2_base); 8777 8778 if (!bp->common.shmem_base) { 8779 BNX2X_DEV_INFO("MCP not active\n"); 8780 bp->flags |= NO_MCP_FLAG; 8781 return; 8782 } 8783 8784 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); 8785 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); 8786 8787 bp->link_params.hw_led_mode = ((bp->common.hw_config & 8788 SHARED_HW_CFG_LED_MODE_MASK) >> 8789 SHARED_HW_CFG_LED_MODE_SHIFT); 8790 8791 bp->link_params.feature_config_flags = 0; 8792 val = SHMEM_RD(bp, dev_info.shared_feature_config.config); 8793 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) 8794 bp->link_params.feature_config_flags |= 8795 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 8796 else 8797 bp->link_params.feature_config_flags &= 8798 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 8799 8800 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; 8801 bp->common.bc_ver = val; 8802 BNX2X_DEV_INFO("bc_ver %X\n", val); 8803 if (val < BNX2X_BC_VER) { 8804 /* for now only warn 8805 * later we might need to enforce this */ 8806 BNX2X_ERR("This driver needs bc_ver %X but found %X, " 8807 "please upgrade BC\n", BNX2X_BC_VER, val); 8808 } 8809 bp->link_params.feature_config_flags |= 8810 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? 8811 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; 8812 8813 bp->link_params.feature_config_flags |= 8814 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? 8815 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; 8816 8817 bp->link_params.feature_config_flags |= 8818 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? 8819 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; 8820 8821 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); 8822 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; 8823 8824 BNX2X_DEV_INFO("%sWoL capable\n", 8825 (bp->flags & NO_WOL_FLAG) ? "not " : ""); 8826 8827 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); 8828 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); 8829 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); 8830 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); 8831 8832 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", 8833 val, val2, val3, val4); 8834 } 8835 8836 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) 8837 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) 8838 8839 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp) 8840 { 8841 int pfid = BP_FUNC(bp); 8842 int igu_sb_id; 8843 u32 val; 8844 u8 fid, igu_sb_cnt = 0; 8845 8846 bp->igu_base_sb = 0xff; 8847 if (CHIP_INT_MODE_IS_BC(bp)) { 8848 int vn = BP_VN(bp); 8849 igu_sb_cnt = bp->igu_sb_cnt; 8850 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * 8851 FP_SB_MAX_E1x; 8852 8853 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + 8854 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); 8855 8856 return; 8857 } 8858 8859 /* IGU in normal mode - read CAM */ 8860 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; 8861 igu_sb_id++) { 8862 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); 8863 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) 8864 continue; 8865 fid = IGU_FID(val); 8866 if ((fid & IGU_FID_ENCODE_IS_PF)) { 8867 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) 8868 continue; 8869 if (IGU_VEC(val) == 0) 8870 /* default status block */ 8871 bp->igu_dsb_id = igu_sb_id; 8872 else { 8873 if (bp->igu_base_sb == 0xff) 8874 bp->igu_base_sb = igu_sb_id; 8875 igu_sb_cnt++; 8876 } 8877 } 8878 } 8879 8880 #ifdef CONFIG_PCI_MSI 8881 /* 8882 * It's expected that number of CAM entries for this functions is equal 8883 * to the number evaluated based on the MSI-X table size. We want a 8884 * harsh warning if these values are different! 8885 */ 8886 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt); 8887 #endif 8888 8889 if (igu_sb_cnt == 0) 8890 BNX2X_ERR("CAM configuration error\n"); 8891 } 8892 8893 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp, 8894 u32 switch_cfg) 8895 { 8896 int cfg_size = 0, idx, port = BP_PORT(bp); 8897 8898 /* Aggregation of supported attributes of all external phys */ 8899 bp->port.supported[0] = 0; 8900 bp->port.supported[1] = 0; 8901 switch (bp->link_params.num_phys) { 8902 case 1: 8903 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; 8904 cfg_size = 1; 8905 break; 8906 case 2: 8907 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; 8908 cfg_size = 1; 8909 break; 8910 case 3: 8911 if (bp->link_params.multi_phy_config & 8912 PORT_HW_CFG_PHY_SWAPPED_ENABLED) { 8913 bp->port.supported[1] = 8914 bp->link_params.phy[EXT_PHY1].supported; 8915 bp->port.supported[0] = 8916 bp->link_params.phy[EXT_PHY2].supported; 8917 } else { 8918 bp->port.supported[0] = 8919 bp->link_params.phy[EXT_PHY1].supported; 8920 bp->port.supported[1] = 8921 bp->link_params.phy[EXT_PHY2].supported; 8922 } 8923 cfg_size = 2; 8924 break; 8925 } 8926 8927 if (!(bp->port.supported[0] || bp->port.supported[1])) { 8928 BNX2X_ERR("NVRAM config error. BAD phy config." 8929 "PHY1 config 0x%x, PHY2 config 0x%x\n", 8930 SHMEM_RD(bp, 8931 dev_info.port_hw_config[port].external_phy_config), 8932 SHMEM_RD(bp, 8933 dev_info.port_hw_config[port].external_phy_config2)); 8934 return; 8935 } 8936 8937 if (CHIP_IS_E3(bp)) 8938 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); 8939 else { 8940 switch (switch_cfg) { 8941 case SWITCH_CFG_1G: 8942 bp->port.phy_addr = REG_RD( 8943 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); 8944 break; 8945 case SWITCH_CFG_10G: 8946 bp->port.phy_addr = REG_RD( 8947 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); 8948 break; 8949 default: 8950 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", 8951 bp->port.link_config[0]); 8952 return; 8953 } 8954 } 8955 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); 8956 /* mask what we support according to speed_cap_mask per configuration */ 8957 for (idx = 0; idx < cfg_size; idx++) { 8958 if (!(bp->link_params.speed_cap_mask[idx] & 8959 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) 8960 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; 8961 8962 if (!(bp->link_params.speed_cap_mask[idx] & 8963 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) 8964 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; 8965 8966 if (!(bp->link_params.speed_cap_mask[idx] & 8967 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) 8968 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; 8969 8970 if (!(bp->link_params.speed_cap_mask[idx] & 8971 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) 8972 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; 8973 8974 if (!(bp->link_params.speed_cap_mask[idx] & 8975 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) 8976 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | 8977 SUPPORTED_1000baseT_Full); 8978 8979 if (!(bp->link_params.speed_cap_mask[idx] & 8980 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 8981 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; 8982 8983 if (!(bp->link_params.speed_cap_mask[idx] & 8984 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) 8985 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; 8986 8987 } 8988 8989 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], 8990 bp->port.supported[1]); 8991 } 8992 8993 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp) 8994 { 8995 u32 link_config, idx, cfg_size = 0; 8996 bp->port.advertising[0] = 0; 8997 bp->port.advertising[1] = 0; 8998 switch (bp->link_params.num_phys) { 8999 case 1: 9000 case 2: 9001 cfg_size = 1; 9002 break; 9003 case 3: 9004 cfg_size = 2; 9005 break; 9006 } 9007 for (idx = 0; idx < cfg_size; idx++) { 9008 bp->link_params.req_duplex[idx] = DUPLEX_FULL; 9009 link_config = bp->port.link_config[idx]; 9010 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 9011 case PORT_FEATURE_LINK_SPEED_AUTO: 9012 if (bp->port.supported[idx] & SUPPORTED_Autoneg) { 9013 bp->link_params.req_line_speed[idx] = 9014 SPEED_AUTO_NEG; 9015 bp->port.advertising[idx] |= 9016 bp->port.supported[idx]; 9017 } else { 9018 /* force 10G, no AN */ 9019 bp->link_params.req_line_speed[idx] = 9020 SPEED_10000; 9021 bp->port.advertising[idx] |= 9022 (ADVERTISED_10000baseT_Full | 9023 ADVERTISED_FIBRE); 9024 continue; 9025 } 9026 break; 9027 9028 case PORT_FEATURE_LINK_SPEED_10M_FULL: 9029 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { 9030 bp->link_params.req_line_speed[idx] = 9031 SPEED_10; 9032 bp->port.advertising[idx] |= 9033 (ADVERTISED_10baseT_Full | 9034 ADVERTISED_TP); 9035 } else { 9036 BNX2X_ERR("NVRAM config error. " 9037 "Invalid link_config 0x%x" 9038 " speed_cap_mask 0x%x\n", 9039 link_config, 9040 bp->link_params.speed_cap_mask[idx]); 9041 return; 9042 } 9043 break; 9044 9045 case PORT_FEATURE_LINK_SPEED_10M_HALF: 9046 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { 9047 bp->link_params.req_line_speed[idx] = 9048 SPEED_10; 9049 bp->link_params.req_duplex[idx] = 9050 DUPLEX_HALF; 9051 bp->port.advertising[idx] |= 9052 (ADVERTISED_10baseT_Half | 9053 ADVERTISED_TP); 9054 } else { 9055 BNX2X_ERR("NVRAM config error. " 9056 "Invalid link_config 0x%x" 9057 " speed_cap_mask 0x%x\n", 9058 link_config, 9059 bp->link_params.speed_cap_mask[idx]); 9060 return; 9061 } 9062 break; 9063 9064 case PORT_FEATURE_LINK_SPEED_100M_FULL: 9065 if (bp->port.supported[idx] & 9066 SUPPORTED_100baseT_Full) { 9067 bp->link_params.req_line_speed[idx] = 9068 SPEED_100; 9069 bp->port.advertising[idx] |= 9070 (ADVERTISED_100baseT_Full | 9071 ADVERTISED_TP); 9072 } else { 9073 BNX2X_ERR("NVRAM config error. " 9074 "Invalid link_config 0x%x" 9075 " speed_cap_mask 0x%x\n", 9076 link_config, 9077 bp->link_params.speed_cap_mask[idx]); 9078 return; 9079 } 9080 break; 9081 9082 case PORT_FEATURE_LINK_SPEED_100M_HALF: 9083 if (bp->port.supported[idx] & 9084 SUPPORTED_100baseT_Half) { 9085 bp->link_params.req_line_speed[idx] = 9086 SPEED_100; 9087 bp->link_params.req_duplex[idx] = 9088 DUPLEX_HALF; 9089 bp->port.advertising[idx] |= 9090 (ADVERTISED_100baseT_Half | 9091 ADVERTISED_TP); 9092 } else { 9093 BNX2X_ERR("NVRAM config error. " 9094 "Invalid link_config 0x%x" 9095 " speed_cap_mask 0x%x\n", 9096 link_config, 9097 bp->link_params.speed_cap_mask[idx]); 9098 return; 9099 } 9100 break; 9101 9102 case PORT_FEATURE_LINK_SPEED_1G: 9103 if (bp->port.supported[idx] & 9104 SUPPORTED_1000baseT_Full) { 9105 bp->link_params.req_line_speed[idx] = 9106 SPEED_1000; 9107 bp->port.advertising[idx] |= 9108 (ADVERTISED_1000baseT_Full | 9109 ADVERTISED_TP); 9110 } else { 9111 BNX2X_ERR("NVRAM config error. " 9112 "Invalid link_config 0x%x" 9113 " speed_cap_mask 0x%x\n", 9114 link_config, 9115 bp->link_params.speed_cap_mask[idx]); 9116 return; 9117 } 9118 break; 9119 9120 case PORT_FEATURE_LINK_SPEED_2_5G: 9121 if (bp->port.supported[idx] & 9122 SUPPORTED_2500baseX_Full) { 9123 bp->link_params.req_line_speed[idx] = 9124 SPEED_2500; 9125 bp->port.advertising[idx] |= 9126 (ADVERTISED_2500baseX_Full | 9127 ADVERTISED_TP); 9128 } else { 9129 BNX2X_ERR("NVRAM config error. " 9130 "Invalid link_config 0x%x" 9131 " speed_cap_mask 0x%x\n", 9132 link_config, 9133 bp->link_params.speed_cap_mask[idx]); 9134 return; 9135 } 9136 break; 9137 9138 case PORT_FEATURE_LINK_SPEED_10G_CX4: 9139 if (bp->port.supported[idx] & 9140 SUPPORTED_10000baseT_Full) { 9141 bp->link_params.req_line_speed[idx] = 9142 SPEED_10000; 9143 bp->port.advertising[idx] |= 9144 (ADVERTISED_10000baseT_Full | 9145 ADVERTISED_FIBRE); 9146 } else { 9147 BNX2X_ERR("NVRAM config error. " 9148 "Invalid link_config 0x%x" 9149 " speed_cap_mask 0x%x\n", 9150 link_config, 9151 bp->link_params.speed_cap_mask[idx]); 9152 return; 9153 } 9154 break; 9155 case PORT_FEATURE_LINK_SPEED_20G: 9156 bp->link_params.req_line_speed[idx] = SPEED_20000; 9157 9158 break; 9159 default: 9160 BNX2X_ERR("NVRAM config error. " 9161 "BAD link speed link_config 0x%x\n", 9162 link_config); 9163 bp->link_params.req_line_speed[idx] = 9164 SPEED_AUTO_NEG; 9165 bp->port.advertising[idx] = 9166 bp->port.supported[idx]; 9167 break; 9168 } 9169 9170 bp->link_params.req_flow_ctrl[idx] = (link_config & 9171 PORT_FEATURE_FLOW_CONTROL_MASK); 9172 if ((bp->link_params.req_flow_ctrl[idx] == 9173 BNX2X_FLOW_CTRL_AUTO) && 9174 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) { 9175 bp->link_params.req_flow_ctrl[idx] = 9176 BNX2X_FLOW_CTRL_NONE; 9177 } 9178 9179 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl" 9180 " 0x%x advertising 0x%x\n", 9181 bp->link_params.req_line_speed[idx], 9182 bp->link_params.req_duplex[idx], 9183 bp->link_params.req_flow_ctrl[idx], 9184 bp->port.advertising[idx]); 9185 } 9186 } 9187 9188 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) 9189 { 9190 mac_hi = cpu_to_be16(mac_hi); 9191 mac_lo = cpu_to_be32(mac_lo); 9192 memcpy(mac_buf, &mac_hi, sizeof(mac_hi)); 9193 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo)); 9194 } 9195 9196 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp) 9197 { 9198 int port = BP_PORT(bp); 9199 u32 config; 9200 u32 ext_phy_type, ext_phy_config; 9201 9202 bp->link_params.bp = bp; 9203 bp->link_params.port = port; 9204 9205 bp->link_params.lane_config = 9206 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); 9207 9208 bp->link_params.speed_cap_mask[0] = 9209 SHMEM_RD(bp, 9210 dev_info.port_hw_config[port].speed_capability_mask); 9211 bp->link_params.speed_cap_mask[1] = 9212 SHMEM_RD(bp, 9213 dev_info.port_hw_config[port].speed_capability_mask2); 9214 bp->port.link_config[0] = 9215 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); 9216 9217 bp->port.link_config[1] = 9218 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); 9219 9220 bp->link_params.multi_phy_config = 9221 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); 9222 /* If the device is capable of WoL, set the default state according 9223 * to the HW 9224 */ 9225 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); 9226 bp->wol = (!(bp->flags & NO_WOL_FLAG) && 9227 (config & PORT_FEATURE_WOL_ENABLED)); 9228 9229 BNX2X_DEV_INFO("lane_config 0x%08x " 9230 "speed_cap_mask0 0x%08x link_config0 0x%08x\n", 9231 bp->link_params.lane_config, 9232 bp->link_params.speed_cap_mask[0], 9233 bp->port.link_config[0]); 9234 9235 bp->link_params.switch_cfg = (bp->port.link_config[0] & 9236 PORT_FEATURE_CONNECTED_SWITCH_MASK); 9237 bnx2x_phy_probe(&bp->link_params); 9238 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); 9239 9240 bnx2x_link_settings_requested(bp); 9241 9242 /* 9243 * If connected directly, work with the internal PHY, otherwise, work 9244 * with the external PHY 9245 */ 9246 ext_phy_config = 9247 SHMEM_RD(bp, 9248 dev_info.port_hw_config[port].external_phy_config); 9249 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 9250 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 9251 bp->mdio.prtad = bp->port.phy_addr; 9252 9253 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && 9254 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 9255 bp->mdio.prtad = 9256 XGXS_EXT_PHY_ADDR(ext_phy_config); 9257 9258 /* 9259 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s) 9260 * In MF mode, it is set to cover self test cases 9261 */ 9262 if (IS_MF(bp)) 9263 bp->port.need_hw_lock = 1; 9264 else 9265 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp, 9266 bp->common.shmem_base, 9267 bp->common.shmem2_base); 9268 } 9269 9270 #ifdef BCM_CNIC 9271 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp) 9272 { 9273 int port = BP_PORT(bp); 9274 int func = BP_ABS_FUNC(bp); 9275 9276 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 9277 drv_lic_key[port].max_iscsi_conn); 9278 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 9279 drv_lic_key[port].max_fcoe_conn); 9280 9281 /* Get the number of maximum allowed iSCSI and FCoE connections */ 9282 bp->cnic_eth_dev.max_iscsi_conn = 9283 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> 9284 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; 9285 9286 bp->cnic_eth_dev.max_fcoe_conn = 9287 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> 9288 BNX2X_MAX_FCOE_INIT_CONN_SHIFT; 9289 9290 /* Read the WWN: */ 9291 if (!IS_MF(bp)) { 9292 /* Port info */ 9293 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 9294 SHMEM_RD(bp, 9295 dev_info.port_hw_config[port]. 9296 fcoe_wwn_port_name_upper); 9297 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 9298 SHMEM_RD(bp, 9299 dev_info.port_hw_config[port]. 9300 fcoe_wwn_port_name_lower); 9301 9302 /* Node info */ 9303 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 9304 SHMEM_RD(bp, 9305 dev_info.port_hw_config[port]. 9306 fcoe_wwn_node_name_upper); 9307 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 9308 SHMEM_RD(bp, 9309 dev_info.port_hw_config[port]. 9310 fcoe_wwn_node_name_lower); 9311 } else if (!IS_MF_SD(bp)) { 9312 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 9313 9314 /* 9315 * Read the WWN info only if the FCoE feature is enabled for 9316 * this function. 9317 */ 9318 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 9319 /* Port info */ 9320 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 9321 MF_CFG_RD(bp, func_ext_config[func]. 9322 fcoe_wwn_port_name_upper); 9323 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 9324 MF_CFG_RD(bp, func_ext_config[func]. 9325 fcoe_wwn_port_name_lower); 9326 9327 /* Node info */ 9328 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 9329 MF_CFG_RD(bp, func_ext_config[func]. 9330 fcoe_wwn_node_name_upper); 9331 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 9332 MF_CFG_RD(bp, func_ext_config[func]. 9333 fcoe_wwn_node_name_lower); 9334 } 9335 } 9336 9337 BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n", 9338 bp->cnic_eth_dev.max_iscsi_conn, 9339 bp->cnic_eth_dev.max_fcoe_conn); 9340 9341 /* 9342 * If maximum allowed number of connections is zero - 9343 * disable the feature. 9344 */ 9345 if (!bp->cnic_eth_dev.max_iscsi_conn) 9346 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; 9347 9348 if (!bp->cnic_eth_dev.max_fcoe_conn) 9349 bp->flags |= NO_FCOE_FLAG; 9350 } 9351 #endif 9352 9353 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp) 9354 { 9355 u32 val, val2; 9356 int func = BP_ABS_FUNC(bp); 9357 int port = BP_PORT(bp); 9358 #ifdef BCM_CNIC 9359 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; 9360 u8 *fip_mac = bp->fip_mac; 9361 #endif 9362 9363 /* Zero primary MAC configuration */ 9364 memset(bp->dev->dev_addr, 0, ETH_ALEN); 9365 9366 if (BP_NOMCP(bp)) { 9367 BNX2X_ERROR("warning: random MAC workaround active\n"); 9368 random_ether_addr(bp->dev->dev_addr); 9369 } else if (IS_MF(bp)) { 9370 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); 9371 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); 9372 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && 9373 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) 9374 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 9375 9376 #ifdef BCM_CNIC 9377 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or 9378 * FCoE MAC then the appropriate feature should be disabled. 9379 */ 9380 if (IS_MF_SI(bp)) { 9381 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 9382 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { 9383 val2 = MF_CFG_RD(bp, func_ext_config[func]. 9384 iscsi_mac_addr_upper); 9385 val = MF_CFG_RD(bp, func_ext_config[func]. 9386 iscsi_mac_addr_lower); 9387 bnx2x_set_mac_buf(iscsi_mac, val, val2); 9388 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", 9389 iscsi_mac); 9390 } else 9391 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; 9392 9393 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 9394 val2 = MF_CFG_RD(bp, func_ext_config[func]. 9395 fcoe_mac_addr_upper); 9396 val = MF_CFG_RD(bp, func_ext_config[func]. 9397 fcoe_mac_addr_lower); 9398 bnx2x_set_mac_buf(fip_mac, val, val2); 9399 BNX2X_DEV_INFO("Read FCoE L2 MAC to %pM\n", 9400 fip_mac); 9401 9402 } else 9403 bp->flags |= NO_FCOE_FLAG; 9404 } 9405 #endif 9406 } else { 9407 /* in SF read MACs from port configuration */ 9408 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); 9409 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); 9410 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 9411 9412 #ifdef BCM_CNIC 9413 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9414 iscsi_mac_upper); 9415 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9416 iscsi_mac_lower); 9417 bnx2x_set_mac_buf(iscsi_mac, val, val2); 9418 9419 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9420 fcoe_fip_mac_upper); 9421 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9422 fcoe_fip_mac_lower); 9423 bnx2x_set_mac_buf(fip_mac, val, val2); 9424 #endif 9425 } 9426 9427 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); 9428 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); 9429 9430 #ifdef BCM_CNIC 9431 /* Set the FCoE MAC in MF_SD mode */ 9432 if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp)) 9433 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); 9434 9435 /* Disable iSCSI if MAC configuration is 9436 * invalid. 9437 */ 9438 if (!is_valid_ether_addr(iscsi_mac)) { 9439 bp->flags |= NO_ISCSI_FLAG; 9440 memset(iscsi_mac, 0, ETH_ALEN); 9441 } 9442 9443 /* Disable FCoE if MAC configuration is 9444 * invalid. 9445 */ 9446 if (!is_valid_ether_addr(fip_mac)) { 9447 bp->flags |= NO_FCOE_FLAG; 9448 memset(bp->fip_mac, 0, ETH_ALEN); 9449 } 9450 #endif 9451 9452 if (!is_valid_ether_addr(bp->dev->dev_addr)) 9453 dev_err(&bp->pdev->dev, 9454 "bad Ethernet MAC address configuration: " 9455 "%pM, change it manually before bringing up " 9456 "the appropriate network interface\n", 9457 bp->dev->dev_addr); 9458 } 9459 9460 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) 9461 { 9462 int /*abs*/func = BP_ABS_FUNC(bp); 9463 int vn; 9464 u32 val = 0; 9465 int rc = 0; 9466 9467 bnx2x_get_common_hwinfo(bp); 9468 9469 /* 9470 * initialize IGU parameters 9471 */ 9472 if (CHIP_IS_E1x(bp)) { 9473 bp->common.int_block = INT_BLOCK_HC; 9474 9475 bp->igu_dsb_id = DEF_SB_IGU_ID; 9476 bp->igu_base_sb = 0; 9477 } else { 9478 bp->common.int_block = INT_BLOCK_IGU; 9479 9480 /* do not allow device reset during IGU info preocessing */ 9481 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 9482 9483 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 9484 9485 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 9486 int tout = 5000; 9487 9488 BNX2X_DEV_INFO("FORCING Normal Mode\n"); 9489 9490 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); 9491 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); 9492 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); 9493 9494 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 9495 tout--; 9496 usleep_range(1000, 1000); 9497 } 9498 9499 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 9500 dev_err(&bp->pdev->dev, 9501 "FORCING Normal Mode failed!!!\n"); 9502 return -EPERM; 9503 } 9504 } 9505 9506 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 9507 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); 9508 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; 9509 } else 9510 BNX2X_DEV_INFO("IGU Normal Mode\n"); 9511 9512 bnx2x_get_igu_cam_info(bp); 9513 9514 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 9515 } 9516 9517 /* 9518 * set base FW non-default (fast path) status block id, this value is 9519 * used to initialize the fw_sb_id saved on the fp/queue structure to 9520 * determine the id used by the FW. 9521 */ 9522 if (CHIP_IS_E1x(bp)) 9523 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); 9524 else /* 9525 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of 9526 * the same queue are indicated on the same IGU SB). So we prefer 9527 * FW and IGU SBs to be the same value. 9528 */ 9529 bp->base_fw_ndsb = bp->igu_base_sb; 9530 9531 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" 9532 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, 9533 bp->igu_sb_cnt, bp->base_fw_ndsb); 9534 9535 /* 9536 * Initialize MF configuration 9537 */ 9538 9539 bp->mf_ov = 0; 9540 bp->mf_mode = 0; 9541 vn = BP_VN(bp); 9542 9543 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { 9544 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", 9545 bp->common.shmem2_base, SHMEM2_RD(bp, size), 9546 (u32)offsetof(struct shmem2_region, mf_cfg_addr)); 9547 9548 if (SHMEM2_HAS(bp, mf_cfg_addr)) 9549 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); 9550 else 9551 bp->common.mf_cfg_base = bp->common.shmem_base + 9552 offsetof(struct shmem_region, func_mb) + 9553 E1H_FUNC_MAX * sizeof(struct drv_func_mb); 9554 /* 9555 * get mf configuration: 9556 * 1. existence of MF configuration 9557 * 2. MAC address must be legal (check only upper bytes) 9558 * for Switch-Independent mode; 9559 * OVLAN must be legal for Switch-Dependent mode 9560 * 3. SF_MODE configures specific MF mode 9561 */ 9562 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 9563 /* get mf configuration */ 9564 val = SHMEM_RD(bp, 9565 dev_info.shared_feature_config.config); 9566 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; 9567 9568 switch (val) { 9569 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: 9570 val = MF_CFG_RD(bp, func_mf_config[func]. 9571 mac_upper); 9572 /* check for legal mac (upper bytes)*/ 9573 if (val != 0xffff) { 9574 bp->mf_mode = MULTI_FUNCTION_SI; 9575 bp->mf_config[vn] = MF_CFG_RD(bp, 9576 func_mf_config[func].config); 9577 } else 9578 BNX2X_DEV_INFO("illegal MAC address " 9579 "for SI\n"); 9580 break; 9581 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: 9582 /* get OV configuration */ 9583 val = MF_CFG_RD(bp, 9584 func_mf_config[FUNC_0].e1hov_tag); 9585 val &= FUNC_MF_CFG_E1HOV_TAG_MASK; 9586 9587 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 9588 bp->mf_mode = MULTI_FUNCTION_SD; 9589 bp->mf_config[vn] = MF_CFG_RD(bp, 9590 func_mf_config[func].config); 9591 } else 9592 BNX2X_DEV_INFO("illegal OV for SD\n"); 9593 break; 9594 default: 9595 /* Unknown configuration: reset mf_config */ 9596 bp->mf_config[vn] = 0; 9597 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val); 9598 } 9599 } 9600 9601 BNX2X_DEV_INFO("%s function mode\n", 9602 IS_MF(bp) ? "multi" : "single"); 9603 9604 switch (bp->mf_mode) { 9605 case MULTI_FUNCTION_SD: 9606 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 9607 FUNC_MF_CFG_E1HOV_TAG_MASK; 9608 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 9609 bp->mf_ov = val; 9610 bp->path_has_ovlan = true; 9611 9612 BNX2X_DEV_INFO("MF OV for func %d is %d " 9613 "(0x%04x)\n", func, bp->mf_ov, 9614 bp->mf_ov); 9615 } else { 9616 dev_err(&bp->pdev->dev, 9617 "No valid MF OV for func %d, " 9618 "aborting\n", func); 9619 return -EPERM; 9620 } 9621 break; 9622 case MULTI_FUNCTION_SI: 9623 BNX2X_DEV_INFO("func %d is in MF " 9624 "switch-independent mode\n", func); 9625 break; 9626 default: 9627 if (vn) { 9628 dev_err(&bp->pdev->dev, 9629 "VN %d is in a single function mode, " 9630 "aborting\n", vn); 9631 return -EPERM; 9632 } 9633 break; 9634 } 9635 9636 /* check if other port on the path needs ovlan: 9637 * Since MF configuration is shared between ports 9638 * Possible mixed modes are only 9639 * {SF, SI} {SF, SD} {SD, SF} {SI, SF} 9640 */ 9641 if (CHIP_MODE_IS_4_PORT(bp) && 9642 !bp->path_has_ovlan && 9643 !IS_MF(bp) && 9644 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 9645 u8 other_port = !BP_PORT(bp); 9646 u8 other_func = BP_PATH(bp) + 2*other_port; 9647 val = MF_CFG_RD(bp, 9648 func_mf_config[other_func].e1hov_tag); 9649 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) 9650 bp->path_has_ovlan = true; 9651 } 9652 } 9653 9654 /* adjust igu_sb_cnt to MF for E1x */ 9655 if (CHIP_IS_E1x(bp) && IS_MF(bp)) 9656 bp->igu_sb_cnt /= E1HVN_MAX; 9657 9658 /* port info */ 9659 bnx2x_get_port_hwinfo(bp); 9660 9661 /* Get MAC addresses */ 9662 bnx2x_get_mac_hwinfo(bp); 9663 9664 #ifdef BCM_CNIC 9665 bnx2x_get_cnic_info(bp); 9666 #endif 9667 9668 /* Get current FW pulse sequence */ 9669 if (!BP_NOMCP(bp)) { 9670 int mb_idx = BP_FW_MB_IDX(bp); 9671 9672 bp->fw_drv_pulse_wr_seq = 9673 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) & 9674 DRV_PULSE_SEQ_MASK); 9675 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq); 9676 } 9677 9678 return rc; 9679 } 9680 9681 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp) 9682 { 9683 int cnt, i, block_end, rodi; 9684 char vpd_data[BNX2X_VPD_LEN+1]; 9685 char str_id_reg[VENDOR_ID_LEN+1]; 9686 char str_id_cap[VENDOR_ID_LEN+1]; 9687 u8 len; 9688 9689 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data); 9690 memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); 9691 9692 if (cnt < BNX2X_VPD_LEN) 9693 goto out_not_found; 9694 9695 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN, 9696 PCI_VPD_LRDT_RO_DATA); 9697 if (i < 0) 9698 goto out_not_found; 9699 9700 9701 block_end = i + PCI_VPD_LRDT_TAG_SIZE + 9702 pci_vpd_lrdt_size(&vpd_data[i]); 9703 9704 i += PCI_VPD_LRDT_TAG_SIZE; 9705 9706 if (block_end > BNX2X_VPD_LEN) 9707 goto out_not_found; 9708 9709 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 9710 PCI_VPD_RO_KEYWORD_MFR_ID); 9711 if (rodi < 0) 9712 goto out_not_found; 9713 9714 len = pci_vpd_info_field_size(&vpd_data[rodi]); 9715 9716 if (len != VENDOR_ID_LEN) 9717 goto out_not_found; 9718 9719 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 9720 9721 /* vendor specific info */ 9722 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); 9723 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); 9724 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || 9725 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { 9726 9727 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 9728 PCI_VPD_RO_KEYWORD_VENDOR0); 9729 if (rodi >= 0) { 9730 len = pci_vpd_info_field_size(&vpd_data[rodi]); 9731 9732 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 9733 9734 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { 9735 memcpy(bp->fw_ver, &vpd_data[rodi], len); 9736 bp->fw_ver[len] = ' '; 9737 } 9738 } 9739 return; 9740 } 9741 out_not_found: 9742 return; 9743 } 9744 9745 static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp) 9746 { 9747 u32 flags = 0; 9748 9749 if (CHIP_REV_IS_FPGA(bp)) 9750 SET_FLAGS(flags, MODE_FPGA); 9751 else if (CHIP_REV_IS_EMUL(bp)) 9752 SET_FLAGS(flags, MODE_EMUL); 9753 else 9754 SET_FLAGS(flags, MODE_ASIC); 9755 9756 if (CHIP_MODE_IS_4_PORT(bp)) 9757 SET_FLAGS(flags, MODE_PORT4); 9758 else 9759 SET_FLAGS(flags, MODE_PORT2); 9760 9761 if (CHIP_IS_E2(bp)) 9762 SET_FLAGS(flags, MODE_E2); 9763 else if (CHIP_IS_E3(bp)) { 9764 SET_FLAGS(flags, MODE_E3); 9765 if (CHIP_REV(bp) == CHIP_REV_Ax) 9766 SET_FLAGS(flags, MODE_E3_A0); 9767 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ 9768 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); 9769 } 9770 9771 if (IS_MF(bp)) { 9772 SET_FLAGS(flags, MODE_MF); 9773 switch (bp->mf_mode) { 9774 case MULTI_FUNCTION_SD: 9775 SET_FLAGS(flags, MODE_MF_SD); 9776 break; 9777 case MULTI_FUNCTION_SI: 9778 SET_FLAGS(flags, MODE_MF_SI); 9779 break; 9780 } 9781 } else 9782 SET_FLAGS(flags, MODE_SF); 9783 9784 #if defined(__LITTLE_ENDIAN) 9785 SET_FLAGS(flags, MODE_LITTLE_ENDIAN); 9786 #else /*(__BIG_ENDIAN)*/ 9787 SET_FLAGS(flags, MODE_BIG_ENDIAN); 9788 #endif 9789 INIT_MODE_FLAGS(bp) = flags; 9790 } 9791 9792 static int __devinit bnx2x_init_bp(struct bnx2x *bp) 9793 { 9794 int func; 9795 int timer_interval; 9796 int rc; 9797 9798 mutex_init(&bp->port.phy_mutex); 9799 mutex_init(&bp->fw_mb_mutex); 9800 spin_lock_init(&bp->stats_lock); 9801 #ifdef BCM_CNIC 9802 mutex_init(&bp->cnic_mutex); 9803 #endif 9804 9805 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); 9806 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); 9807 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); 9808 rc = bnx2x_get_hwinfo(bp); 9809 if (rc) 9810 return rc; 9811 9812 bnx2x_set_modes_bitmap(bp); 9813 9814 rc = bnx2x_alloc_mem_bp(bp); 9815 if (rc) 9816 return rc; 9817 9818 bnx2x_read_fwinfo(bp); 9819 9820 func = BP_FUNC(bp); 9821 9822 /* need to reset chip if undi was active */ 9823 if (!BP_NOMCP(bp)) 9824 bnx2x_undi_unload(bp); 9825 9826 /* init fw_seq after undi_unload! */ 9827 if (!BP_NOMCP(bp)) { 9828 bp->fw_seq = 9829 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & 9830 DRV_MSG_SEQ_NUMBER_MASK); 9831 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); 9832 } 9833 9834 if (CHIP_REV_IS_FPGA(bp)) 9835 dev_err(&bp->pdev->dev, "FPGA detected\n"); 9836 9837 if (BP_NOMCP(bp) && (func == 0)) 9838 dev_err(&bp->pdev->dev, "MCP disabled, " 9839 "must load devices in order!\n"); 9840 9841 bp->multi_mode = multi_mode; 9842 9843 /* Set TPA flags */ 9844 if (disable_tpa) { 9845 bp->flags &= ~TPA_ENABLE_FLAG; 9846 bp->dev->features &= ~NETIF_F_LRO; 9847 } else { 9848 bp->flags |= TPA_ENABLE_FLAG; 9849 bp->dev->features |= NETIF_F_LRO; 9850 } 9851 bp->disable_tpa = disable_tpa; 9852 9853 if (CHIP_IS_E1(bp)) 9854 bp->dropless_fc = 0; 9855 else 9856 bp->dropless_fc = dropless_fc; 9857 9858 bp->mrrs = mrrs; 9859 9860 bp->tx_ring_size = MAX_TX_AVAIL; 9861 9862 /* make sure that the numbers are in the right granularity */ 9863 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; 9864 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; 9865 9866 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ); 9867 bp->current_interval = (poll ? poll : timer_interval); 9868 9869 init_timer(&bp->timer); 9870 bp->timer.expires = jiffies + bp->current_interval; 9871 bp->timer.data = (unsigned long) bp; 9872 bp->timer.function = bnx2x_timer; 9873 9874 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); 9875 bnx2x_dcbx_init_params(bp); 9876 9877 #ifdef BCM_CNIC 9878 if (CHIP_IS_E1x(bp)) 9879 bp->cnic_base_cl_id = FP_SB_MAX_E1x; 9880 else 9881 bp->cnic_base_cl_id = FP_SB_MAX_E2; 9882 #endif 9883 9884 /* multiple tx priority */ 9885 if (CHIP_IS_E1x(bp)) 9886 bp->max_cos = BNX2X_MULTI_TX_COS_E1X; 9887 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) 9888 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; 9889 if (CHIP_IS_E3B0(bp)) 9890 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; 9891 9892 return rc; 9893 } 9894 9895 9896 /**************************************************************************** 9897 * General service functions 9898 ****************************************************************************/ 9899 9900 /* 9901 * net_device service functions 9902 */ 9903 9904 /* called with rtnl_lock */ 9905 static int bnx2x_open(struct net_device *dev) 9906 { 9907 struct bnx2x *bp = netdev_priv(dev); 9908 bool global = false; 9909 int other_engine = BP_PATH(bp) ? 0 : 1; 9910 u32 other_load_counter, load_counter; 9911 9912 netif_carrier_off(dev); 9913 9914 bnx2x_set_power_state(bp, PCI_D0); 9915 9916 other_load_counter = bnx2x_get_load_cnt(bp, other_engine); 9917 load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp)); 9918 9919 /* 9920 * If parity had happen during the unload, then attentions 9921 * and/or RECOVERY_IN_PROGRES may still be set. In this case we 9922 * want the first function loaded on the current engine to 9923 * complete the recovery. 9924 */ 9925 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || 9926 bnx2x_chk_parity_attn(bp, &global, true)) 9927 do { 9928 /* 9929 * If there are attentions and they are in a global 9930 * blocks, set the GLOBAL_RESET bit regardless whether 9931 * it will be this function that will complete the 9932 * recovery or not. 9933 */ 9934 if (global) 9935 bnx2x_set_reset_global(bp); 9936 9937 /* 9938 * Only the first function on the current engine should 9939 * try to recover in open. In case of attentions in 9940 * global blocks only the first in the chip should try 9941 * to recover. 9942 */ 9943 if ((!load_counter && 9944 (!global || !other_load_counter)) && 9945 bnx2x_trylock_leader_lock(bp) && 9946 !bnx2x_leader_reset(bp)) { 9947 netdev_info(bp->dev, "Recovered in open\n"); 9948 break; 9949 } 9950 9951 /* recovery has failed... */ 9952 bnx2x_set_power_state(bp, PCI_D3hot); 9953 bp->recovery_state = BNX2X_RECOVERY_FAILED; 9954 9955 netdev_err(bp->dev, "Recovery flow hasn't been properly" 9956 " completed yet. Try again later. If u still see this" 9957 " message after a few retries then power cycle is" 9958 " required.\n"); 9959 9960 return -EAGAIN; 9961 } while (0); 9962 9963 bp->recovery_state = BNX2X_RECOVERY_DONE; 9964 return bnx2x_nic_load(bp, LOAD_OPEN); 9965 } 9966 9967 /* called with rtnl_lock */ 9968 static int bnx2x_close(struct net_device *dev) 9969 { 9970 struct bnx2x *bp = netdev_priv(dev); 9971 9972 /* Unload the driver, release IRQs */ 9973 bnx2x_nic_unload(bp, UNLOAD_CLOSE); 9974 9975 /* Power off */ 9976 bnx2x_set_power_state(bp, PCI_D3hot); 9977 9978 return 0; 9979 } 9980 9981 static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp, 9982 struct bnx2x_mcast_ramrod_params *p) 9983 { 9984 int mc_count = netdev_mc_count(bp->dev); 9985 struct bnx2x_mcast_list_elem *mc_mac = 9986 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); 9987 struct netdev_hw_addr *ha; 9988 9989 if (!mc_mac) 9990 return -ENOMEM; 9991 9992 INIT_LIST_HEAD(&p->mcast_list); 9993 9994 netdev_for_each_mc_addr(ha, bp->dev) { 9995 mc_mac->mac = bnx2x_mc_addr(ha); 9996 list_add_tail(&mc_mac->link, &p->mcast_list); 9997 mc_mac++; 9998 } 9999 10000 p->mcast_list_len = mc_count; 10001 10002 return 0; 10003 } 10004 10005 static inline void bnx2x_free_mcast_macs_list( 10006 struct bnx2x_mcast_ramrod_params *p) 10007 { 10008 struct bnx2x_mcast_list_elem *mc_mac = 10009 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, 10010 link); 10011 10012 WARN_ON(!mc_mac); 10013 kfree(mc_mac); 10014 } 10015 10016 /** 10017 * bnx2x_set_uc_list - configure a new unicast MACs list. 10018 * 10019 * @bp: driver handle 10020 * 10021 * We will use zero (0) as a MAC type for these MACs. 10022 */ 10023 static inline int bnx2x_set_uc_list(struct bnx2x *bp) 10024 { 10025 int rc; 10026 struct net_device *dev = bp->dev; 10027 struct netdev_hw_addr *ha; 10028 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj; 10029 unsigned long ramrod_flags = 0; 10030 10031 /* First schedule a cleanup up of old configuration */ 10032 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); 10033 if (rc < 0) { 10034 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); 10035 return rc; 10036 } 10037 10038 netdev_for_each_uc_addr(ha, dev) { 10039 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, 10040 BNX2X_UC_LIST_MAC, &ramrod_flags); 10041 if (rc < 0) { 10042 BNX2X_ERR("Failed to schedule ADD operations: %d\n", 10043 rc); 10044 return rc; 10045 } 10046 } 10047 10048 /* Execute the pending commands */ 10049 __set_bit(RAMROD_CONT, &ramrod_flags); 10050 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, 10051 BNX2X_UC_LIST_MAC, &ramrod_flags); 10052 } 10053 10054 static inline int bnx2x_set_mc_list(struct bnx2x *bp) 10055 { 10056 struct net_device *dev = bp->dev; 10057 struct bnx2x_mcast_ramrod_params rparam = {0}; 10058 int rc = 0; 10059 10060 rparam.mcast_obj = &bp->mcast_obj; 10061 10062 /* first, clear all configured multicast MACs */ 10063 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 10064 if (rc < 0) { 10065 BNX2X_ERR("Failed to clear multicast " 10066 "configuration: %d\n", rc); 10067 return rc; 10068 } 10069 10070 /* then, configure a new MACs list */ 10071 if (netdev_mc_count(dev)) { 10072 rc = bnx2x_init_mcast_macs_list(bp, &rparam); 10073 if (rc) { 10074 BNX2X_ERR("Failed to create multicast MACs " 10075 "list: %d\n", rc); 10076 return rc; 10077 } 10078 10079 /* Now add the new MACs */ 10080 rc = bnx2x_config_mcast(bp, &rparam, 10081 BNX2X_MCAST_CMD_ADD); 10082 if (rc < 0) 10083 BNX2X_ERR("Failed to set a new multicast " 10084 "configuration: %d\n", rc); 10085 10086 bnx2x_free_mcast_macs_list(&rparam); 10087 } 10088 10089 return rc; 10090 } 10091 10092 10093 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ 10094 void bnx2x_set_rx_mode(struct net_device *dev) 10095 { 10096 struct bnx2x *bp = netdev_priv(dev); 10097 u32 rx_mode = BNX2X_RX_MODE_NORMAL; 10098 10099 if (bp->state != BNX2X_STATE_OPEN) { 10100 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); 10101 return; 10102 } 10103 10104 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); 10105 10106 if (dev->flags & IFF_PROMISC) 10107 rx_mode = BNX2X_RX_MODE_PROMISC; 10108 else if ((dev->flags & IFF_ALLMULTI) || 10109 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) && 10110 CHIP_IS_E1(bp))) 10111 rx_mode = BNX2X_RX_MODE_ALLMULTI; 10112 else { 10113 /* some multicasts */ 10114 if (bnx2x_set_mc_list(bp) < 0) 10115 rx_mode = BNX2X_RX_MODE_ALLMULTI; 10116 10117 if (bnx2x_set_uc_list(bp) < 0) 10118 rx_mode = BNX2X_RX_MODE_PROMISC; 10119 } 10120 10121 bp->rx_mode = rx_mode; 10122 10123 /* Schedule the rx_mode command */ 10124 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { 10125 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 10126 return; 10127 } 10128 10129 bnx2x_set_storm_rx_mode(bp); 10130 } 10131 10132 /* called with rtnl_lock */ 10133 static int bnx2x_mdio_read(struct net_device *netdev, int prtad, 10134 int devad, u16 addr) 10135 { 10136 struct bnx2x *bp = netdev_priv(netdev); 10137 u16 value; 10138 int rc; 10139 10140 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", 10141 prtad, devad, addr); 10142 10143 /* The HW expects different devad if CL22 is used */ 10144 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10145 10146 bnx2x_acquire_phy_lock(bp); 10147 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); 10148 bnx2x_release_phy_lock(bp); 10149 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); 10150 10151 if (!rc) 10152 rc = value; 10153 return rc; 10154 } 10155 10156 /* called with rtnl_lock */ 10157 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, 10158 u16 addr, u16 value) 10159 { 10160 struct bnx2x *bp = netdev_priv(netdev); 10161 int rc; 10162 10163 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x," 10164 " value 0x%x\n", prtad, devad, addr, value); 10165 10166 /* The HW expects different devad if CL22 is used */ 10167 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10168 10169 bnx2x_acquire_phy_lock(bp); 10170 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); 10171 bnx2x_release_phy_lock(bp); 10172 return rc; 10173 } 10174 10175 /* called with rtnl_lock */ 10176 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 10177 { 10178 struct bnx2x *bp = netdev_priv(dev); 10179 struct mii_ioctl_data *mdio = if_mii(ifr); 10180 10181 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", 10182 mdio->phy_id, mdio->reg_num, mdio->val_in); 10183 10184 if (!netif_running(dev)) 10185 return -EAGAIN; 10186 10187 return mdio_mii_ioctl(&bp->mdio, mdio, cmd); 10188 } 10189 10190 #ifdef CONFIG_NET_POLL_CONTROLLER 10191 static void poll_bnx2x(struct net_device *dev) 10192 { 10193 struct bnx2x *bp = netdev_priv(dev); 10194 10195 disable_irq(bp->pdev->irq); 10196 bnx2x_interrupt(bp->pdev->irq, dev); 10197 enable_irq(bp->pdev->irq); 10198 } 10199 #endif 10200 10201 static const struct net_device_ops bnx2x_netdev_ops = { 10202 .ndo_open = bnx2x_open, 10203 .ndo_stop = bnx2x_close, 10204 .ndo_start_xmit = bnx2x_start_xmit, 10205 .ndo_select_queue = bnx2x_select_queue, 10206 .ndo_set_rx_mode = bnx2x_set_rx_mode, 10207 .ndo_set_mac_address = bnx2x_change_mac_addr, 10208 .ndo_validate_addr = eth_validate_addr, 10209 .ndo_do_ioctl = bnx2x_ioctl, 10210 .ndo_change_mtu = bnx2x_change_mtu, 10211 .ndo_fix_features = bnx2x_fix_features, 10212 .ndo_set_features = bnx2x_set_features, 10213 .ndo_tx_timeout = bnx2x_tx_timeout, 10214 #ifdef CONFIG_NET_POLL_CONTROLLER 10215 .ndo_poll_controller = poll_bnx2x, 10216 #endif 10217 .ndo_setup_tc = bnx2x_setup_tc, 10218 10219 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) 10220 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, 10221 #endif 10222 }; 10223 10224 static inline int bnx2x_set_coherency_mask(struct bnx2x *bp) 10225 { 10226 struct device *dev = &bp->pdev->dev; 10227 10228 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 10229 bp->flags |= USING_DAC_FLAG; 10230 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 10231 dev_err(dev, "dma_set_coherent_mask failed, " 10232 "aborting\n"); 10233 return -EIO; 10234 } 10235 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 10236 dev_err(dev, "System does not support DMA, aborting\n"); 10237 return -EIO; 10238 } 10239 10240 return 0; 10241 } 10242 10243 static int __devinit bnx2x_init_dev(struct pci_dev *pdev, 10244 struct net_device *dev, 10245 unsigned long board_type) 10246 { 10247 struct bnx2x *bp; 10248 int rc; 10249 10250 SET_NETDEV_DEV(dev, &pdev->dev); 10251 bp = netdev_priv(dev); 10252 10253 bp->dev = dev; 10254 bp->pdev = pdev; 10255 bp->flags = 0; 10256 bp->pf_num = PCI_FUNC(pdev->devfn); 10257 10258 rc = pci_enable_device(pdev); 10259 if (rc) { 10260 dev_err(&bp->pdev->dev, 10261 "Cannot enable PCI device, aborting\n"); 10262 goto err_out; 10263 } 10264 10265 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 10266 dev_err(&bp->pdev->dev, 10267 "Cannot find PCI device base address, aborting\n"); 10268 rc = -ENODEV; 10269 goto err_out_disable; 10270 } 10271 10272 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 10273 dev_err(&bp->pdev->dev, "Cannot find second PCI device" 10274 " base address, aborting\n"); 10275 rc = -ENODEV; 10276 goto err_out_disable; 10277 } 10278 10279 if (atomic_read(&pdev->enable_cnt) == 1) { 10280 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 10281 if (rc) { 10282 dev_err(&bp->pdev->dev, 10283 "Cannot obtain PCI resources, aborting\n"); 10284 goto err_out_disable; 10285 } 10286 10287 pci_set_master(pdev); 10288 pci_save_state(pdev); 10289 } 10290 10291 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 10292 if (bp->pm_cap == 0) { 10293 dev_err(&bp->pdev->dev, 10294 "Cannot find power management capability, aborting\n"); 10295 rc = -EIO; 10296 goto err_out_release; 10297 } 10298 10299 if (!pci_is_pcie(pdev)) { 10300 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); 10301 rc = -EIO; 10302 goto err_out_release; 10303 } 10304 10305 rc = bnx2x_set_coherency_mask(bp); 10306 if (rc) 10307 goto err_out_release; 10308 10309 dev->mem_start = pci_resource_start(pdev, 0); 10310 dev->base_addr = dev->mem_start; 10311 dev->mem_end = pci_resource_end(pdev, 0); 10312 10313 dev->irq = pdev->irq; 10314 10315 bp->regview = pci_ioremap_bar(pdev, 0); 10316 if (!bp->regview) { 10317 dev_err(&bp->pdev->dev, 10318 "Cannot map register space, aborting\n"); 10319 rc = -ENOMEM; 10320 goto err_out_release; 10321 } 10322 10323 bnx2x_set_power_state(bp, PCI_D0); 10324 10325 /* clean indirect addresses */ 10326 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 10327 PCICFG_VENDOR_ID_OFFSET); 10328 /* 10329 * Clean the following indirect addresses for all functions since it 10330 * is not used by the driver. 10331 */ 10332 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); 10333 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); 10334 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); 10335 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); 10336 10337 if (CHIP_IS_E1x(bp)) { 10338 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); 10339 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); 10340 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); 10341 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); 10342 } 10343 10344 /* 10345 * Enable internal target-read (in case we are probed after PF FLR). 10346 * Must be done prior to any BAR read access. Only for 57712 and up 10347 */ 10348 if (board_type != BCM57710 && 10349 board_type != BCM57711 && 10350 board_type != BCM57711E) 10351 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 10352 10353 /* Reset the load counter */ 10354 bnx2x_clear_load_cnt(bp); 10355 10356 dev->watchdog_timeo = TX_TIMEOUT; 10357 10358 dev->netdev_ops = &bnx2x_netdev_ops; 10359 bnx2x_set_ethtool_ops(dev); 10360 10361 dev->priv_flags |= IFF_UNICAST_FLT; 10362 10363 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 10364 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_LRO | 10365 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX; 10366 10367 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 10368 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; 10369 10370 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX; 10371 if (bp->flags & USING_DAC_FLAG) 10372 dev->features |= NETIF_F_HIGHDMA; 10373 10374 /* Add Loopback capability to the device */ 10375 dev->hw_features |= NETIF_F_LOOPBACK; 10376 10377 #ifdef BCM_DCBNL 10378 dev->dcbnl_ops = &bnx2x_dcbnl_ops; 10379 #endif 10380 10381 /* get_port_hwinfo() will set prtad and mmds properly */ 10382 bp->mdio.prtad = MDIO_PRTAD_NONE; 10383 bp->mdio.mmds = 0; 10384 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10385 bp->mdio.dev = dev; 10386 bp->mdio.mdio_read = bnx2x_mdio_read; 10387 bp->mdio.mdio_write = bnx2x_mdio_write; 10388 10389 return 0; 10390 10391 err_out_release: 10392 if (atomic_read(&pdev->enable_cnt) == 1) 10393 pci_release_regions(pdev); 10394 10395 err_out_disable: 10396 pci_disable_device(pdev); 10397 pci_set_drvdata(pdev, NULL); 10398 10399 err_out: 10400 return rc; 10401 } 10402 10403 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp, 10404 int *width, int *speed) 10405 { 10406 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL); 10407 10408 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; 10409 10410 /* return value of 1=2.5GHz 2=5GHz */ 10411 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; 10412 } 10413 10414 static int bnx2x_check_firmware(struct bnx2x *bp) 10415 { 10416 const struct firmware *firmware = bp->firmware; 10417 struct bnx2x_fw_file_hdr *fw_hdr; 10418 struct bnx2x_fw_file_section *sections; 10419 u32 offset, len, num_ops; 10420 u16 *ops_offsets; 10421 int i; 10422 const u8 *fw_ver; 10423 10424 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) 10425 return -EINVAL; 10426 10427 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; 10428 sections = (struct bnx2x_fw_file_section *)fw_hdr; 10429 10430 /* Make sure none of the offsets and sizes make us read beyond 10431 * the end of the firmware data */ 10432 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { 10433 offset = be32_to_cpu(sections[i].offset); 10434 len = be32_to_cpu(sections[i].len); 10435 if (offset + len > firmware->size) { 10436 dev_err(&bp->pdev->dev, 10437 "Section %d length is out of bounds\n", i); 10438 return -EINVAL; 10439 } 10440 } 10441 10442 /* Likewise for the init_ops offsets */ 10443 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); 10444 ops_offsets = (u16 *)(firmware->data + offset); 10445 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); 10446 10447 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { 10448 if (be16_to_cpu(ops_offsets[i]) > num_ops) { 10449 dev_err(&bp->pdev->dev, 10450 "Section offset %d is out of bounds\n", i); 10451 return -EINVAL; 10452 } 10453 } 10454 10455 /* Check FW version */ 10456 offset = be32_to_cpu(fw_hdr->fw_version.offset); 10457 fw_ver = firmware->data + offset; 10458 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || 10459 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || 10460 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || 10461 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { 10462 dev_err(&bp->pdev->dev, 10463 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", 10464 fw_ver[0], fw_ver[1], fw_ver[2], 10465 fw_ver[3], BCM_5710_FW_MAJOR_VERSION, 10466 BCM_5710_FW_MINOR_VERSION, 10467 BCM_5710_FW_REVISION_VERSION, 10468 BCM_5710_FW_ENGINEERING_VERSION); 10469 return -EINVAL; 10470 } 10471 10472 return 0; 10473 } 10474 10475 static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 10476 { 10477 const __be32 *source = (const __be32 *)_source; 10478 u32 *target = (u32 *)_target; 10479 u32 i; 10480 10481 for (i = 0; i < n/4; i++) 10482 target[i] = be32_to_cpu(source[i]); 10483 } 10484 10485 /* 10486 Ops array is stored in the following format: 10487 {op(8bit), offset(24bit, big endian), data(32bit, big endian)} 10488 */ 10489 static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) 10490 { 10491 const __be32 *source = (const __be32 *)_source; 10492 struct raw_op *target = (struct raw_op *)_target; 10493 u32 i, j, tmp; 10494 10495 for (i = 0, j = 0; i < n/8; i++, j += 2) { 10496 tmp = be32_to_cpu(source[j]); 10497 target[i].op = (tmp >> 24) & 0xff; 10498 target[i].offset = tmp & 0xffffff; 10499 target[i].raw_data = be32_to_cpu(source[j + 1]); 10500 } 10501 } 10502 10503 /** 10504 * IRO array is stored in the following format: 10505 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } 10506 */ 10507 static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) 10508 { 10509 const __be32 *source = (const __be32 *)_source; 10510 struct iro *target = (struct iro *)_target; 10511 u32 i, j, tmp; 10512 10513 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { 10514 target[i].base = be32_to_cpu(source[j]); 10515 j++; 10516 tmp = be32_to_cpu(source[j]); 10517 target[i].m1 = (tmp >> 16) & 0xffff; 10518 target[i].m2 = tmp & 0xffff; 10519 j++; 10520 tmp = be32_to_cpu(source[j]); 10521 target[i].m3 = (tmp >> 16) & 0xffff; 10522 target[i].size = tmp & 0xffff; 10523 j++; 10524 } 10525 } 10526 10527 static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 10528 { 10529 const __be16 *source = (const __be16 *)_source; 10530 u16 *target = (u16 *)_target; 10531 u32 i; 10532 10533 for (i = 0; i < n/2; i++) 10534 target[i] = be16_to_cpu(source[i]); 10535 } 10536 10537 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ 10538 do { \ 10539 u32 len = be32_to_cpu(fw_hdr->arr.len); \ 10540 bp->arr = kmalloc(len, GFP_KERNEL); \ 10541 if (!bp->arr) { \ 10542 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \ 10543 goto lbl; \ 10544 } \ 10545 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ 10546 (u8 *)bp->arr, len); \ 10547 } while (0) 10548 10549 int bnx2x_init_firmware(struct bnx2x *bp) 10550 { 10551 const char *fw_file_name; 10552 struct bnx2x_fw_file_hdr *fw_hdr; 10553 int rc; 10554 10555 if (CHIP_IS_E1(bp)) 10556 fw_file_name = FW_FILE_NAME_E1; 10557 else if (CHIP_IS_E1H(bp)) 10558 fw_file_name = FW_FILE_NAME_E1H; 10559 else if (!CHIP_IS_E1x(bp)) 10560 fw_file_name = FW_FILE_NAME_E2; 10561 else { 10562 BNX2X_ERR("Unsupported chip revision\n"); 10563 return -EINVAL; 10564 } 10565 10566 BNX2X_DEV_INFO("Loading %s\n", fw_file_name); 10567 10568 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); 10569 if (rc) { 10570 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name); 10571 goto request_firmware_exit; 10572 } 10573 10574 rc = bnx2x_check_firmware(bp); 10575 if (rc) { 10576 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); 10577 goto request_firmware_exit; 10578 } 10579 10580 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; 10581 10582 /* Initialize the pointers to the init arrays */ 10583 /* Blob */ 10584 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); 10585 10586 /* Opcodes */ 10587 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); 10588 10589 /* Offsets */ 10590 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, 10591 be16_to_cpu_n); 10592 10593 /* STORMs firmware */ 10594 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10595 be32_to_cpu(fw_hdr->tsem_int_table_data.offset); 10596 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + 10597 be32_to_cpu(fw_hdr->tsem_pram_data.offset); 10598 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10599 be32_to_cpu(fw_hdr->usem_int_table_data.offset); 10600 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + 10601 be32_to_cpu(fw_hdr->usem_pram_data.offset); 10602 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10603 be32_to_cpu(fw_hdr->xsem_int_table_data.offset); 10604 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + 10605 be32_to_cpu(fw_hdr->xsem_pram_data.offset); 10606 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10607 be32_to_cpu(fw_hdr->csem_int_table_data.offset); 10608 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + 10609 be32_to_cpu(fw_hdr->csem_pram_data.offset); 10610 /* IRO */ 10611 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); 10612 10613 return 0; 10614 10615 iro_alloc_err: 10616 kfree(bp->init_ops_offsets); 10617 init_offsets_alloc_err: 10618 kfree(bp->init_ops); 10619 init_ops_alloc_err: 10620 kfree(bp->init_data); 10621 request_firmware_exit: 10622 release_firmware(bp->firmware); 10623 10624 return rc; 10625 } 10626 10627 static void bnx2x_release_firmware(struct bnx2x *bp) 10628 { 10629 kfree(bp->init_ops_offsets); 10630 kfree(bp->init_ops); 10631 kfree(bp->init_data); 10632 release_firmware(bp->firmware); 10633 } 10634 10635 10636 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { 10637 .init_hw_cmn_chip = bnx2x_init_hw_common_chip, 10638 .init_hw_cmn = bnx2x_init_hw_common, 10639 .init_hw_port = bnx2x_init_hw_port, 10640 .init_hw_func = bnx2x_init_hw_func, 10641 10642 .reset_hw_cmn = bnx2x_reset_common, 10643 .reset_hw_port = bnx2x_reset_port, 10644 .reset_hw_func = bnx2x_reset_func, 10645 10646 .gunzip_init = bnx2x_gunzip_init, 10647 .gunzip_end = bnx2x_gunzip_end, 10648 10649 .init_fw = bnx2x_init_firmware, 10650 .release_fw = bnx2x_release_firmware, 10651 }; 10652 10653 void bnx2x__init_func_obj(struct bnx2x *bp) 10654 { 10655 /* Prepare DMAE related driver resources */ 10656 bnx2x_setup_dmae(bp); 10657 10658 bnx2x_init_func_obj(bp, &bp->func_obj, 10659 bnx2x_sp(bp, func_rdata), 10660 bnx2x_sp_mapping(bp, func_rdata), 10661 &bnx2x_func_sp_drv); 10662 } 10663 10664 /* must be called after sriov-enable */ 10665 static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp) 10666 { 10667 int cid_count = BNX2X_L2_CID_COUNT(bp); 10668 10669 #ifdef BCM_CNIC 10670 cid_count += CNIC_CID_MAX; 10671 #endif 10672 return roundup(cid_count, QM_CID_ROUND); 10673 } 10674 10675 /** 10676 * bnx2x_get_num_none_def_sbs - return the number of none default SBs 10677 * 10678 * @dev: pci device 10679 * 10680 */ 10681 static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev) 10682 { 10683 int pos; 10684 u16 control; 10685 10686 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 10687 10688 /* 10689 * If MSI-X is not supported - return number of SBs needed to support 10690 * one fast path queue: one FP queue + SB for CNIC 10691 */ 10692 if (!pos) 10693 return 1 + CNIC_PRESENT; 10694 10695 /* 10696 * The value in the PCI configuration space is the index of the last 10697 * entry, namely one less than the actual size of the table, which is 10698 * exactly what we want to return from this function: number of all SBs 10699 * without the default SB. 10700 */ 10701 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); 10702 return control & PCI_MSIX_FLAGS_QSIZE; 10703 } 10704 10705 static int __devinit bnx2x_init_one(struct pci_dev *pdev, 10706 const struct pci_device_id *ent) 10707 { 10708 struct net_device *dev = NULL; 10709 struct bnx2x *bp; 10710 int pcie_width, pcie_speed; 10711 int rc, max_non_def_sbs; 10712 int rx_count, tx_count, rss_count; 10713 /* 10714 * An estimated maximum supported CoS number according to the chip 10715 * version. 10716 * We will try to roughly estimate the maximum number of CoSes this chip 10717 * may support in order to minimize the memory allocated for Tx 10718 * netdev_queue's. This number will be accurately calculated during the 10719 * initialization of bp->max_cos based on the chip versions AND chip 10720 * revision in the bnx2x_init_bp(). 10721 */ 10722 u8 max_cos_est = 0; 10723 10724 switch (ent->driver_data) { 10725 case BCM57710: 10726 case BCM57711: 10727 case BCM57711E: 10728 max_cos_est = BNX2X_MULTI_TX_COS_E1X; 10729 break; 10730 10731 case BCM57712: 10732 case BCM57712_MF: 10733 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0; 10734 break; 10735 10736 case BCM57800: 10737 case BCM57800_MF: 10738 case BCM57810: 10739 case BCM57810_MF: 10740 case BCM57840: 10741 case BCM57840_MF: 10742 max_cos_est = BNX2X_MULTI_TX_COS_E3B0; 10743 break; 10744 10745 default: 10746 pr_err("Unknown board_type (%ld), aborting\n", 10747 ent->driver_data); 10748 return -ENODEV; 10749 } 10750 10751 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev); 10752 10753 /* !!! FIXME !!! 10754 * Do not allow the maximum SB count to grow above 16 10755 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48. 10756 * We will use the FP_SB_MAX_E1x macro for this matter. 10757 */ 10758 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs); 10759 10760 WARN_ON(!max_non_def_sbs); 10761 10762 /* Maximum number of RSS queues: one IGU SB goes to CNIC */ 10763 rss_count = max_non_def_sbs - CNIC_PRESENT; 10764 10765 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ 10766 rx_count = rss_count + FCOE_PRESENT; 10767 10768 /* 10769 * Maximum number of netdev Tx queues: 10770 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 10771 */ 10772 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT; 10773 10774 /* dev zeroed in init_etherdev */ 10775 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); 10776 if (!dev) { 10777 dev_err(&pdev->dev, "Cannot allocate net device\n"); 10778 return -ENOMEM; 10779 } 10780 10781 bp = netdev_priv(dev); 10782 10783 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n", 10784 tx_count, rx_count); 10785 10786 bp->igu_sb_cnt = max_non_def_sbs; 10787 bp->msg_enable = debug; 10788 pci_set_drvdata(pdev, dev); 10789 10790 rc = bnx2x_init_dev(pdev, dev, ent->driver_data); 10791 if (rc < 0) { 10792 free_netdev(dev); 10793 return rc; 10794 } 10795 10796 DP(NETIF_MSG_DRV, "max_non_def_sbs %d\n", max_non_def_sbs); 10797 10798 rc = bnx2x_init_bp(bp); 10799 if (rc) 10800 goto init_one_exit; 10801 10802 /* 10803 * Map doorbels here as we need the real value of bp->max_cos which 10804 * is initialized in bnx2x_init_bp(). 10805 */ 10806 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), 10807 min_t(u64, BNX2X_DB_SIZE(bp), 10808 pci_resource_len(pdev, 2))); 10809 if (!bp->doorbells) { 10810 dev_err(&bp->pdev->dev, 10811 "Cannot map doorbell space, aborting\n"); 10812 rc = -ENOMEM; 10813 goto init_one_exit; 10814 } 10815 10816 /* calc qm_cid_count */ 10817 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); 10818 10819 #ifdef BCM_CNIC 10820 /* disable FCOE L2 queue for E1x and E3*/ 10821 if (CHIP_IS_E1x(bp) || CHIP_IS_E3(bp)) 10822 bp->flags |= NO_FCOE_FLAG; 10823 10824 #endif 10825 10826 /* Configure interrupt mode: try to enable MSI-X/MSI if 10827 * needed, set bp->num_queues appropriately. 10828 */ 10829 bnx2x_set_int_mode(bp); 10830 10831 /* Add all NAPI objects */ 10832 bnx2x_add_all_napi(bp); 10833 10834 rc = register_netdev(dev); 10835 if (rc) { 10836 dev_err(&pdev->dev, "Cannot register net device\n"); 10837 goto init_one_exit; 10838 } 10839 10840 #ifdef BCM_CNIC 10841 if (!NO_FCOE(bp)) { 10842 /* Add storage MAC address */ 10843 rtnl_lock(); 10844 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 10845 rtnl_unlock(); 10846 } 10847 #endif 10848 10849 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); 10850 10851 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", 10852 board_info[ent->driver_data].name, 10853 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), 10854 pcie_width, 10855 ((!CHIP_IS_E2(bp) && pcie_speed == 2) || 10856 (CHIP_IS_E2(bp) && pcie_speed == 1)) ? 10857 "5GHz (Gen2)" : "2.5GHz", 10858 dev->base_addr, bp->pdev->irq, dev->dev_addr); 10859 10860 return 0; 10861 10862 init_one_exit: 10863 if (bp->regview) 10864 iounmap(bp->regview); 10865 10866 if (bp->doorbells) 10867 iounmap(bp->doorbells); 10868 10869 free_netdev(dev); 10870 10871 if (atomic_read(&pdev->enable_cnt) == 1) 10872 pci_release_regions(pdev); 10873 10874 pci_disable_device(pdev); 10875 pci_set_drvdata(pdev, NULL); 10876 10877 return rc; 10878 } 10879 10880 static void __devexit bnx2x_remove_one(struct pci_dev *pdev) 10881 { 10882 struct net_device *dev = pci_get_drvdata(pdev); 10883 struct bnx2x *bp; 10884 10885 if (!dev) { 10886 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); 10887 return; 10888 } 10889 bp = netdev_priv(dev); 10890 10891 #ifdef BCM_CNIC 10892 /* Delete storage MAC address */ 10893 if (!NO_FCOE(bp)) { 10894 rtnl_lock(); 10895 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 10896 rtnl_unlock(); 10897 } 10898 #endif 10899 10900 #ifdef BCM_DCBNL 10901 /* Delete app tlvs from dcbnl */ 10902 bnx2x_dcbnl_update_applist(bp, true); 10903 #endif 10904 10905 unregister_netdev(dev); 10906 10907 /* Delete all NAPI objects */ 10908 bnx2x_del_all_napi(bp); 10909 10910 /* Power on: we can't let PCI layer write to us while we are in D3 */ 10911 bnx2x_set_power_state(bp, PCI_D0); 10912 10913 /* Disable MSI/MSI-X */ 10914 bnx2x_disable_msi(bp); 10915 10916 /* Power off */ 10917 bnx2x_set_power_state(bp, PCI_D3hot); 10918 10919 /* Make sure RESET task is not scheduled before continuing */ 10920 cancel_delayed_work_sync(&bp->sp_rtnl_task); 10921 10922 if (bp->regview) 10923 iounmap(bp->regview); 10924 10925 if (bp->doorbells) 10926 iounmap(bp->doorbells); 10927 10928 bnx2x_free_mem_bp(bp); 10929 10930 free_netdev(dev); 10931 10932 if (atomic_read(&pdev->enable_cnt) == 1) 10933 pci_release_regions(pdev); 10934 10935 pci_disable_device(pdev); 10936 pci_set_drvdata(pdev, NULL); 10937 } 10938 10939 static int bnx2x_eeh_nic_unload(struct bnx2x *bp) 10940 { 10941 int i; 10942 10943 bp->state = BNX2X_STATE_ERROR; 10944 10945 bp->rx_mode = BNX2X_RX_MODE_NONE; 10946 10947 #ifdef BCM_CNIC 10948 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); 10949 #endif 10950 /* Stop Tx */ 10951 bnx2x_tx_disable(bp); 10952 10953 bnx2x_netif_stop(bp, 0); 10954 10955 del_timer_sync(&bp->timer); 10956 10957 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 10958 10959 /* Release IRQs */ 10960 bnx2x_free_irq(bp); 10961 10962 /* Free SKBs, SGEs, TPA pool and driver internals */ 10963 bnx2x_free_skbs(bp); 10964 10965 for_each_rx_queue(bp, i) 10966 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); 10967 10968 bnx2x_free_mem(bp); 10969 10970 bp->state = BNX2X_STATE_CLOSED; 10971 10972 netif_carrier_off(bp->dev); 10973 10974 return 0; 10975 } 10976 10977 static void bnx2x_eeh_recover(struct bnx2x *bp) 10978 { 10979 u32 val; 10980 10981 mutex_init(&bp->port.phy_mutex); 10982 10983 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 10984 bp->link_params.shmem_base = bp->common.shmem_base; 10985 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base); 10986 10987 if (!bp->common.shmem_base || 10988 (bp->common.shmem_base < 0xA0000) || 10989 (bp->common.shmem_base >= 0xC0000)) { 10990 BNX2X_DEV_INFO("MCP not active\n"); 10991 bp->flags |= NO_MCP_FLAG; 10992 return; 10993 } 10994 10995 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 10996 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 10997 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 10998 BNX2X_ERR("BAD MCP validity signature\n"); 10999 11000 if (!BP_NOMCP(bp)) { 11001 bp->fw_seq = 11002 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & 11003 DRV_MSG_SEQ_NUMBER_MASK); 11004 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); 11005 } 11006 } 11007 11008 /** 11009 * bnx2x_io_error_detected - called when PCI error is detected 11010 * @pdev: Pointer to PCI device 11011 * @state: The current pci connection state 11012 * 11013 * This function is called after a PCI bus error affecting 11014 * this device has been detected. 11015 */ 11016 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, 11017 pci_channel_state_t state) 11018 { 11019 struct net_device *dev = pci_get_drvdata(pdev); 11020 struct bnx2x *bp = netdev_priv(dev); 11021 11022 rtnl_lock(); 11023 11024 netif_device_detach(dev); 11025 11026 if (state == pci_channel_io_perm_failure) { 11027 rtnl_unlock(); 11028 return PCI_ERS_RESULT_DISCONNECT; 11029 } 11030 11031 if (netif_running(dev)) 11032 bnx2x_eeh_nic_unload(bp); 11033 11034 pci_disable_device(pdev); 11035 11036 rtnl_unlock(); 11037 11038 /* Request a slot reset */ 11039 return PCI_ERS_RESULT_NEED_RESET; 11040 } 11041 11042 /** 11043 * bnx2x_io_slot_reset - called after the PCI bus has been reset 11044 * @pdev: Pointer to PCI device 11045 * 11046 * Restart the card from scratch, as if from a cold-boot. 11047 */ 11048 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) 11049 { 11050 struct net_device *dev = pci_get_drvdata(pdev); 11051 struct bnx2x *bp = netdev_priv(dev); 11052 11053 rtnl_lock(); 11054 11055 if (pci_enable_device(pdev)) { 11056 dev_err(&pdev->dev, 11057 "Cannot re-enable PCI device after reset\n"); 11058 rtnl_unlock(); 11059 return PCI_ERS_RESULT_DISCONNECT; 11060 } 11061 11062 pci_set_master(pdev); 11063 pci_restore_state(pdev); 11064 11065 if (netif_running(dev)) 11066 bnx2x_set_power_state(bp, PCI_D0); 11067 11068 rtnl_unlock(); 11069 11070 return PCI_ERS_RESULT_RECOVERED; 11071 } 11072 11073 /** 11074 * bnx2x_io_resume - called when traffic can start flowing again 11075 * @pdev: Pointer to PCI device 11076 * 11077 * This callback is called when the error recovery driver tells us that 11078 * its OK to resume normal operation. 11079 */ 11080 static void bnx2x_io_resume(struct pci_dev *pdev) 11081 { 11082 struct net_device *dev = pci_get_drvdata(pdev); 11083 struct bnx2x *bp = netdev_priv(dev); 11084 11085 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 11086 netdev_err(bp->dev, "Handling parity error recovery. " 11087 "Try again later\n"); 11088 return; 11089 } 11090 11091 rtnl_lock(); 11092 11093 bnx2x_eeh_recover(bp); 11094 11095 if (netif_running(dev)) 11096 bnx2x_nic_load(bp, LOAD_NORMAL); 11097 11098 netif_device_attach(dev); 11099 11100 rtnl_unlock(); 11101 } 11102 11103 static struct pci_error_handlers bnx2x_err_handler = { 11104 .error_detected = bnx2x_io_error_detected, 11105 .slot_reset = bnx2x_io_slot_reset, 11106 .resume = bnx2x_io_resume, 11107 }; 11108 11109 static struct pci_driver bnx2x_pci_driver = { 11110 .name = DRV_MODULE_NAME, 11111 .id_table = bnx2x_pci_tbl, 11112 .probe = bnx2x_init_one, 11113 .remove = __devexit_p(bnx2x_remove_one), 11114 .suspend = bnx2x_suspend, 11115 .resume = bnx2x_resume, 11116 .err_handler = &bnx2x_err_handler, 11117 }; 11118 11119 static int __init bnx2x_init(void) 11120 { 11121 int ret; 11122 11123 pr_info("%s", version); 11124 11125 bnx2x_wq = create_singlethread_workqueue("bnx2x"); 11126 if (bnx2x_wq == NULL) { 11127 pr_err("Cannot create workqueue\n"); 11128 return -ENOMEM; 11129 } 11130 11131 ret = pci_register_driver(&bnx2x_pci_driver); 11132 if (ret) { 11133 pr_err("Cannot register driver\n"); 11134 destroy_workqueue(bnx2x_wq); 11135 } 11136 return ret; 11137 } 11138 11139 static void __exit bnx2x_cleanup(void) 11140 { 11141 pci_unregister_driver(&bnx2x_pci_driver); 11142 11143 destroy_workqueue(bnx2x_wq); 11144 } 11145 11146 void bnx2x_notify_link_changed(struct bnx2x *bp) 11147 { 11148 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); 11149 } 11150 11151 module_init(bnx2x_init); 11152 module_exit(bnx2x_cleanup); 11153 11154 #ifdef BCM_CNIC 11155 /** 11156 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). 11157 * 11158 * @bp: driver handle 11159 * @set: set or clear the CAM entry 11160 * 11161 * This function will wait until the ramdord completion returns. 11162 * Return 0 if success, -ENODEV if ramrod doesn't return. 11163 */ 11164 static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) 11165 { 11166 unsigned long ramrod_flags = 0; 11167 11168 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 11169 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, 11170 &bp->iscsi_l2_mac_obj, true, 11171 BNX2X_ISCSI_ETH_MAC, &ramrod_flags); 11172 } 11173 11174 /* count denotes the number of new completions we have seen */ 11175 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) 11176 { 11177 struct eth_spe *spe; 11178 11179 #ifdef BNX2X_STOP_ON_ERROR 11180 if (unlikely(bp->panic)) 11181 return; 11182 #endif 11183 11184 spin_lock_bh(&bp->spq_lock); 11185 BUG_ON(bp->cnic_spq_pending < count); 11186 bp->cnic_spq_pending -= count; 11187 11188 11189 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { 11190 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) 11191 & SPE_HDR_CONN_TYPE) >> 11192 SPE_HDR_CONN_TYPE_SHIFT; 11193 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) 11194 >> SPE_HDR_CMD_ID_SHIFT) & 0xff; 11195 11196 /* Set validation for iSCSI L2 client before sending SETUP 11197 * ramrod 11198 */ 11199 if (type == ETH_CONNECTION_TYPE) { 11200 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) 11201 bnx2x_set_ctx_validation(bp, &bp->context. 11202 vcxt[BNX2X_ISCSI_ETH_CID].eth, 11203 BNX2X_ISCSI_ETH_CID); 11204 } 11205 11206 /* 11207 * There may be not more than 8 L2, not more than 8 L5 SPEs 11208 * and in the air. We also check that number of outstanding 11209 * COMMON ramrods is not more than the EQ and SPQ can 11210 * accommodate. 11211 */ 11212 if (type == ETH_CONNECTION_TYPE) { 11213 if (!atomic_read(&bp->cq_spq_left)) 11214 break; 11215 else 11216 atomic_dec(&bp->cq_spq_left); 11217 } else if (type == NONE_CONNECTION_TYPE) { 11218 if (!atomic_read(&bp->eq_spq_left)) 11219 break; 11220 else 11221 atomic_dec(&bp->eq_spq_left); 11222 } else if ((type == ISCSI_CONNECTION_TYPE) || 11223 (type == FCOE_CONNECTION_TYPE)) { 11224 if (bp->cnic_spq_pending >= 11225 bp->cnic_eth_dev.max_kwqe_pending) 11226 break; 11227 else 11228 bp->cnic_spq_pending++; 11229 } else { 11230 BNX2X_ERR("Unknown SPE type: %d\n", type); 11231 bnx2x_panic(); 11232 break; 11233 } 11234 11235 spe = bnx2x_sp_get_next(bp); 11236 *spe = *bp->cnic_kwq_cons; 11237 11238 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n", 11239 bp->cnic_spq_pending, bp->cnic_kwq_pending, count); 11240 11241 if (bp->cnic_kwq_cons == bp->cnic_kwq_last) 11242 bp->cnic_kwq_cons = bp->cnic_kwq; 11243 else 11244 bp->cnic_kwq_cons++; 11245 } 11246 bnx2x_sp_prod_update(bp); 11247 spin_unlock_bh(&bp->spq_lock); 11248 } 11249 11250 static int bnx2x_cnic_sp_queue(struct net_device *dev, 11251 struct kwqe_16 *kwqes[], u32 count) 11252 { 11253 struct bnx2x *bp = netdev_priv(dev); 11254 int i; 11255 11256 #ifdef BNX2X_STOP_ON_ERROR 11257 if (unlikely(bp->panic)) 11258 return -EIO; 11259 #endif 11260 11261 spin_lock_bh(&bp->spq_lock); 11262 11263 for (i = 0; i < count; i++) { 11264 struct eth_spe *spe = (struct eth_spe *)kwqes[i]; 11265 11266 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) 11267 break; 11268 11269 *bp->cnic_kwq_prod = *spe; 11270 11271 bp->cnic_kwq_pending++; 11272 11273 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n", 11274 spe->hdr.conn_and_cmd_data, spe->hdr.type, 11275 spe->data.update_data_addr.hi, 11276 spe->data.update_data_addr.lo, 11277 bp->cnic_kwq_pending); 11278 11279 if (bp->cnic_kwq_prod == bp->cnic_kwq_last) 11280 bp->cnic_kwq_prod = bp->cnic_kwq; 11281 else 11282 bp->cnic_kwq_prod++; 11283 } 11284 11285 spin_unlock_bh(&bp->spq_lock); 11286 11287 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) 11288 bnx2x_cnic_sp_post(bp, 0); 11289 11290 return i; 11291 } 11292 11293 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) 11294 { 11295 struct cnic_ops *c_ops; 11296 int rc = 0; 11297 11298 mutex_lock(&bp->cnic_mutex); 11299 c_ops = rcu_dereference_protected(bp->cnic_ops, 11300 lockdep_is_held(&bp->cnic_mutex)); 11301 if (c_ops) 11302 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 11303 mutex_unlock(&bp->cnic_mutex); 11304 11305 return rc; 11306 } 11307 11308 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) 11309 { 11310 struct cnic_ops *c_ops; 11311 int rc = 0; 11312 11313 rcu_read_lock(); 11314 c_ops = rcu_dereference(bp->cnic_ops); 11315 if (c_ops) 11316 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 11317 rcu_read_unlock(); 11318 11319 return rc; 11320 } 11321 11322 /* 11323 * for commands that have no data 11324 */ 11325 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) 11326 { 11327 struct cnic_ctl_info ctl = {0}; 11328 11329 ctl.cmd = cmd; 11330 11331 return bnx2x_cnic_ctl_send(bp, &ctl); 11332 } 11333 11334 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) 11335 { 11336 struct cnic_ctl_info ctl = {0}; 11337 11338 /* first we tell CNIC and only then we count this as a completion */ 11339 ctl.cmd = CNIC_CTL_COMPLETION_CMD; 11340 ctl.data.comp.cid = cid; 11341 ctl.data.comp.error = err; 11342 11343 bnx2x_cnic_ctl_send_bh(bp, &ctl); 11344 bnx2x_cnic_sp_post(bp, 0); 11345 } 11346 11347 11348 /* Called with netif_addr_lock_bh() taken. 11349 * Sets an rx_mode config for an iSCSI ETH client. 11350 * Doesn't block. 11351 * Completion should be checked outside. 11352 */ 11353 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) 11354 { 11355 unsigned long accept_flags = 0, ramrod_flags = 0; 11356 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 11357 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; 11358 11359 if (start) { 11360 /* Start accepting on iSCSI L2 ring. Accept all multicasts 11361 * because it's the only way for UIO Queue to accept 11362 * multicasts (in non-promiscuous mode only one Queue per 11363 * function will receive multicast packets (leading in our 11364 * case). 11365 */ 11366 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); 11367 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); 11368 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); 11369 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 11370 11371 /* Clear STOP_PENDING bit if START is requested */ 11372 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); 11373 11374 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; 11375 } else 11376 /* Clear START_PENDING bit if STOP is requested */ 11377 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); 11378 11379 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 11380 set_bit(sched_state, &bp->sp_state); 11381 else { 11382 __set_bit(RAMROD_RX, &ramrod_flags); 11383 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, 11384 ramrod_flags); 11385 } 11386 } 11387 11388 11389 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) 11390 { 11391 struct bnx2x *bp = netdev_priv(dev); 11392 int rc = 0; 11393 11394 switch (ctl->cmd) { 11395 case DRV_CTL_CTXTBL_WR_CMD: { 11396 u32 index = ctl->data.io.offset; 11397 dma_addr_t addr = ctl->data.io.dma_addr; 11398 11399 bnx2x_ilt_wr(bp, index, addr); 11400 break; 11401 } 11402 11403 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { 11404 int count = ctl->data.credit.credit_count; 11405 11406 bnx2x_cnic_sp_post(bp, count); 11407 break; 11408 } 11409 11410 /* rtnl_lock is held. */ 11411 case DRV_CTL_START_L2_CMD: { 11412 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11413 unsigned long sp_bits = 0; 11414 11415 /* Configure the iSCSI classification object */ 11416 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, 11417 cp->iscsi_l2_client_id, 11418 cp->iscsi_l2_cid, BP_FUNC(bp), 11419 bnx2x_sp(bp, mac_rdata), 11420 bnx2x_sp_mapping(bp, mac_rdata), 11421 BNX2X_FILTER_MAC_PENDING, 11422 &bp->sp_state, BNX2X_OBJ_TYPE_RX, 11423 &bp->macs_pool); 11424 11425 /* Set iSCSI MAC address */ 11426 rc = bnx2x_set_iscsi_eth_mac_addr(bp); 11427 if (rc) 11428 break; 11429 11430 mmiowb(); 11431 barrier(); 11432 11433 /* Start accepting on iSCSI L2 ring */ 11434 11435 netif_addr_lock_bh(dev); 11436 bnx2x_set_iscsi_eth_rx_mode(bp, true); 11437 netif_addr_unlock_bh(dev); 11438 11439 /* bits to wait on */ 11440 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 11441 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); 11442 11443 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 11444 BNX2X_ERR("rx_mode completion timed out!\n"); 11445 11446 break; 11447 } 11448 11449 /* rtnl_lock is held. */ 11450 case DRV_CTL_STOP_L2_CMD: { 11451 unsigned long sp_bits = 0; 11452 11453 /* Stop accepting on iSCSI L2 ring */ 11454 netif_addr_lock_bh(dev); 11455 bnx2x_set_iscsi_eth_rx_mode(bp, false); 11456 netif_addr_unlock_bh(dev); 11457 11458 /* bits to wait on */ 11459 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 11460 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); 11461 11462 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 11463 BNX2X_ERR("rx_mode completion timed out!\n"); 11464 11465 mmiowb(); 11466 barrier(); 11467 11468 /* Unset iSCSI L2 MAC */ 11469 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, 11470 BNX2X_ISCSI_ETH_MAC, true); 11471 break; 11472 } 11473 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { 11474 int count = ctl->data.credit.credit_count; 11475 11476 smp_mb__before_atomic_inc(); 11477 atomic_add(count, &bp->cq_spq_left); 11478 smp_mb__after_atomic_inc(); 11479 break; 11480 } 11481 11482 default: 11483 BNX2X_ERR("unknown command %x\n", ctl->cmd); 11484 rc = -EINVAL; 11485 } 11486 11487 return rc; 11488 } 11489 11490 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) 11491 { 11492 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11493 11494 if (bp->flags & USING_MSIX_FLAG) { 11495 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; 11496 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; 11497 cp->irq_arr[0].vector = bp->msix_table[1].vector; 11498 } else { 11499 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; 11500 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; 11501 } 11502 if (!CHIP_IS_E1x(bp)) 11503 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; 11504 else 11505 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; 11506 11507 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); 11508 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); 11509 cp->irq_arr[1].status_blk = bp->def_status_blk; 11510 cp->irq_arr[1].status_blk_num = DEF_SB_ID; 11511 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; 11512 11513 cp->num_irq = 2; 11514 } 11515 11516 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, 11517 void *data) 11518 { 11519 struct bnx2x *bp = netdev_priv(dev); 11520 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11521 11522 if (ops == NULL) 11523 return -EINVAL; 11524 11525 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); 11526 if (!bp->cnic_kwq) 11527 return -ENOMEM; 11528 11529 bp->cnic_kwq_cons = bp->cnic_kwq; 11530 bp->cnic_kwq_prod = bp->cnic_kwq; 11531 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; 11532 11533 bp->cnic_spq_pending = 0; 11534 bp->cnic_kwq_pending = 0; 11535 11536 bp->cnic_data = data; 11537 11538 cp->num_irq = 0; 11539 cp->drv_state |= CNIC_DRV_STATE_REGD; 11540 cp->iro_arr = bp->iro_arr; 11541 11542 bnx2x_setup_cnic_irq_info(bp); 11543 11544 rcu_assign_pointer(bp->cnic_ops, ops); 11545 11546 return 0; 11547 } 11548 11549 static int bnx2x_unregister_cnic(struct net_device *dev) 11550 { 11551 struct bnx2x *bp = netdev_priv(dev); 11552 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11553 11554 mutex_lock(&bp->cnic_mutex); 11555 cp->drv_state = 0; 11556 rcu_assign_pointer(bp->cnic_ops, NULL); 11557 mutex_unlock(&bp->cnic_mutex); 11558 synchronize_rcu(); 11559 kfree(bp->cnic_kwq); 11560 bp->cnic_kwq = NULL; 11561 11562 return 0; 11563 } 11564 11565 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) 11566 { 11567 struct bnx2x *bp = netdev_priv(dev); 11568 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11569 11570 /* If both iSCSI and FCoE are disabled - return NULL in 11571 * order to indicate CNIC that it should not try to work 11572 * with this device. 11573 */ 11574 if (NO_ISCSI(bp) && NO_FCOE(bp)) 11575 return NULL; 11576 11577 cp->drv_owner = THIS_MODULE; 11578 cp->chip_id = CHIP_ID(bp); 11579 cp->pdev = bp->pdev; 11580 cp->io_base = bp->regview; 11581 cp->io_base2 = bp->doorbells; 11582 cp->max_kwqe_pending = 8; 11583 cp->ctx_blk_size = CDU_ILT_PAGE_SZ; 11584 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + 11585 bnx2x_cid_ilt_lines(bp); 11586 cp->ctx_tbl_len = CNIC_ILT_LINES; 11587 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; 11588 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; 11589 cp->drv_ctl = bnx2x_drv_ctl; 11590 cp->drv_register_cnic = bnx2x_register_cnic; 11591 cp->drv_unregister_cnic = bnx2x_unregister_cnic; 11592 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID; 11593 cp->iscsi_l2_client_id = 11594 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 11595 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID; 11596 11597 if (NO_ISCSI_OOO(bp)) 11598 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; 11599 11600 if (NO_ISCSI(bp)) 11601 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; 11602 11603 if (NO_FCOE(bp)) 11604 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; 11605 11606 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, " 11607 "starting cid %d\n", 11608 cp->ctx_blk_size, 11609 cp->ctx_tbl_offset, 11610 cp->ctx_tbl_len, 11611 cp->starting_cid); 11612 return cp; 11613 } 11614 EXPORT_SYMBOL(bnx2x_cnic_probe); 11615 11616 #endif /* BCM_CNIC */ 11617 11618